Initial commit
mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_fsmc.c@0:bb348c97df44, 2020-09-16 (annotated)
- Committer:
- lypinator
- Date:
- Wed Sep 16 01:11:49 2020 +0000
- Revision:
- 0:bb348c97df44
Added PWM
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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lypinator | 0:bb348c97df44 | 1 | /** |
lypinator | 0:bb348c97df44 | 2 | ****************************************************************************** |
lypinator | 0:bb348c97df44 | 3 | * @file stm32f4xx_ll_fsmc.c |
lypinator | 0:bb348c97df44 | 4 | * @author MCD Application Team |
lypinator | 0:bb348c97df44 | 5 | * @brief FSMC Low Layer HAL module driver. |
lypinator | 0:bb348c97df44 | 6 | * |
lypinator | 0:bb348c97df44 | 7 | * This file provides firmware functions to manage the following |
lypinator | 0:bb348c97df44 | 8 | * functionalities of the Flexible Static Memory Controller (FSMC) peripheral memories: |
lypinator | 0:bb348c97df44 | 9 | * + Initialization/de-initialization functions |
lypinator | 0:bb348c97df44 | 10 | * + Peripheral Control functions |
lypinator | 0:bb348c97df44 | 11 | * + Peripheral State functions |
lypinator | 0:bb348c97df44 | 12 | * |
lypinator | 0:bb348c97df44 | 13 | @verbatim |
lypinator | 0:bb348c97df44 | 14 | ============================================================================== |
lypinator | 0:bb348c97df44 | 15 | ##### FSMC peripheral features ##### |
lypinator | 0:bb348c97df44 | 16 | ============================================================================== |
lypinator | 0:bb348c97df44 | 17 | [..] The Flexible static memory controller (FSMC) includes two memory controllers: |
lypinator | 0:bb348c97df44 | 18 | (+) The NOR/PSRAM memory controller |
lypinator | 0:bb348c97df44 | 19 | (+) The NAND/PC Card memory controller |
lypinator | 0:bb348c97df44 | 20 | |
lypinator | 0:bb348c97df44 | 21 | [..] The FSMC functional block makes the interface with synchronous and asynchronous static |
lypinator | 0:bb348c97df44 | 22 | memories, SDRAM memories, and 16-bit PC memory cards. Its main purposes are: |
lypinator | 0:bb348c97df44 | 23 | (+) to translate AHB transactions into the appropriate external device protocol. |
lypinator | 0:bb348c97df44 | 24 | (+) to meet the access time requirements of the external memory devices. |
lypinator | 0:bb348c97df44 | 25 | |
lypinator | 0:bb348c97df44 | 26 | [..] All external memories share the addresses, data and control signals with the controller. |
lypinator | 0:bb348c97df44 | 27 | Each external device is accessed by means of a unique Chip Select. The FSMC performs |
lypinator | 0:bb348c97df44 | 28 | only one access at a time to an external device. |
lypinator | 0:bb348c97df44 | 29 | The main features of the FSMC controller are the following: |
lypinator | 0:bb348c97df44 | 30 | (+) Interface with static-memory mapped devices including: |
lypinator | 0:bb348c97df44 | 31 | (++) Static random access memory (SRAM). |
lypinator | 0:bb348c97df44 | 32 | (++) Read-only memory (ROM). |
lypinator | 0:bb348c97df44 | 33 | (++) NOR Flash memory/OneNAND Flash memory. |
lypinator | 0:bb348c97df44 | 34 | (++) PSRAM (4 memory banks). |
lypinator | 0:bb348c97df44 | 35 | (++) 16-bit PC Card compatible devices. |
lypinator | 0:bb348c97df44 | 36 | (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of |
lypinator | 0:bb348c97df44 | 37 | data. |
lypinator | 0:bb348c97df44 | 38 | (+) Independent Chip Select control for each memory bank. |
lypinator | 0:bb348c97df44 | 39 | (+) Independent configuration for each memory bank. |
lypinator | 0:bb348c97df44 | 40 | |
lypinator | 0:bb348c97df44 | 41 | @endverbatim |
lypinator | 0:bb348c97df44 | 42 | ****************************************************************************** |
lypinator | 0:bb348c97df44 | 43 | * @attention |
lypinator | 0:bb348c97df44 | 44 | * |
lypinator | 0:bb348c97df44 | 45 | * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> |
lypinator | 0:bb348c97df44 | 46 | * |
lypinator | 0:bb348c97df44 | 47 | * Redistribution and use in source and binary forms, with or without modification, |
lypinator | 0:bb348c97df44 | 48 | * are permitted provided that the following conditions are met: |
lypinator | 0:bb348c97df44 | 49 | * 1. Redistributions of source code must retain the above copyright notice, |
lypinator | 0:bb348c97df44 | 50 | * this list of conditions and the following disclaimer. |
lypinator | 0:bb348c97df44 | 51 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
lypinator | 0:bb348c97df44 | 52 | * this list of conditions and the following disclaimer in the documentation |
lypinator | 0:bb348c97df44 | 53 | * and/or other materials provided with the distribution. |
lypinator | 0:bb348c97df44 | 54 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
lypinator | 0:bb348c97df44 | 55 | * may be used to endorse or promote products derived from this software |
lypinator | 0:bb348c97df44 | 56 | * without specific prior written permission. |
lypinator | 0:bb348c97df44 | 57 | * |
lypinator | 0:bb348c97df44 | 58 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
lypinator | 0:bb348c97df44 | 59 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
lypinator | 0:bb348c97df44 | 60 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
lypinator | 0:bb348c97df44 | 61 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
lypinator | 0:bb348c97df44 | 62 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
lypinator | 0:bb348c97df44 | 63 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
lypinator | 0:bb348c97df44 | 64 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
lypinator | 0:bb348c97df44 | 65 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
lypinator | 0:bb348c97df44 | 66 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
lypinator | 0:bb348c97df44 | 67 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
lypinator | 0:bb348c97df44 | 68 | * |
lypinator | 0:bb348c97df44 | 69 | ****************************************************************************** |
lypinator | 0:bb348c97df44 | 70 | */ |
lypinator | 0:bb348c97df44 | 71 | |
lypinator | 0:bb348c97df44 | 72 | /* Includes ------------------------------------------------------------------*/ |
lypinator | 0:bb348c97df44 | 73 | #include "stm32f4xx_hal.h" |
lypinator | 0:bb348c97df44 | 74 | |
lypinator | 0:bb348c97df44 | 75 | /** @addtogroup STM32F4xx_HAL_Driver |
lypinator | 0:bb348c97df44 | 76 | * @{ |
lypinator | 0:bb348c97df44 | 77 | */ |
lypinator | 0:bb348c97df44 | 78 | |
lypinator | 0:bb348c97df44 | 79 | /** @defgroup FSMC_LL FSMC Low Layer |
lypinator | 0:bb348c97df44 | 80 | * @brief FSMC driver modules |
lypinator | 0:bb348c97df44 | 81 | * @{ |
lypinator | 0:bb348c97df44 | 82 | */ |
lypinator | 0:bb348c97df44 | 83 | |
lypinator | 0:bb348c97df44 | 84 | #if defined (HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_PCCARD_MODULE_ENABLED) |
lypinator | 0:bb348c97df44 | 85 | #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F412Zx) ||\ |
lypinator | 0:bb348c97df44 | 86 | defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx) |
lypinator | 0:bb348c97df44 | 87 | /* Private typedef -----------------------------------------------------------*/ |
lypinator | 0:bb348c97df44 | 88 | /* Private define ------------------------------------------------------------*/ |
lypinator | 0:bb348c97df44 | 89 | /* Private macro -------------------------------------------------------------*/ |
lypinator | 0:bb348c97df44 | 90 | /* Private variables ---------------------------------------------------------*/ |
lypinator | 0:bb348c97df44 | 91 | /* Private function prototypes -----------------------------------------------*/ |
lypinator | 0:bb348c97df44 | 92 | /* Private functions ---------------------------------------------------------*/ |
lypinator | 0:bb348c97df44 | 93 | /** @addtogroup FSMC_LL_Private_Functions |
lypinator | 0:bb348c97df44 | 94 | * @{ |
lypinator | 0:bb348c97df44 | 95 | */ |
lypinator | 0:bb348c97df44 | 96 | |
lypinator | 0:bb348c97df44 | 97 | /** @addtogroup FSMC_LL_NORSRAM |
lypinator | 0:bb348c97df44 | 98 | * @brief NORSRAM Controller functions |
lypinator | 0:bb348c97df44 | 99 | * |
lypinator | 0:bb348c97df44 | 100 | @verbatim |
lypinator | 0:bb348c97df44 | 101 | ============================================================================== |
lypinator | 0:bb348c97df44 | 102 | ##### How to use NORSRAM device driver ##### |
lypinator | 0:bb348c97df44 | 103 | ============================================================================== |
lypinator | 0:bb348c97df44 | 104 | |
lypinator | 0:bb348c97df44 | 105 | [..] |
lypinator | 0:bb348c97df44 | 106 | This driver contains a set of APIs to interface with the FSMC NORSRAM banks in order |
lypinator | 0:bb348c97df44 | 107 | to run the NORSRAM external devices. |
lypinator | 0:bb348c97df44 | 108 | |
lypinator | 0:bb348c97df44 | 109 | (+) FSMC NORSRAM bank reset using the function FSMC_NORSRAM_DeInit() |
lypinator | 0:bb348c97df44 | 110 | (+) FSMC NORSRAM bank control configuration using the function FSMC_NORSRAM_Init() |
lypinator | 0:bb348c97df44 | 111 | (+) FSMC NORSRAM bank timing configuration using the function FSMC_NORSRAM_Timing_Init() |
lypinator | 0:bb348c97df44 | 112 | (+) FSMC NORSRAM bank extended timing configuration using the function |
lypinator | 0:bb348c97df44 | 113 | FSMC_NORSRAM_Extended_Timing_Init() |
lypinator | 0:bb348c97df44 | 114 | (+) FSMC NORSRAM bank enable/disable write operation using the functions |
lypinator | 0:bb348c97df44 | 115 | FSMC_NORSRAM_WriteOperation_Enable()/FSMC_NORSRAM_WriteOperation_Disable() |
lypinator | 0:bb348c97df44 | 116 | |
lypinator | 0:bb348c97df44 | 117 | @endverbatim |
lypinator | 0:bb348c97df44 | 118 | * @{ |
lypinator | 0:bb348c97df44 | 119 | */ |
lypinator | 0:bb348c97df44 | 120 | |
lypinator | 0:bb348c97df44 | 121 | /** @addtogroup FSMC_LL_NORSRAM_Private_Functions_Group1 |
lypinator | 0:bb348c97df44 | 122 | * @brief Initialization and Configuration functions |
lypinator | 0:bb348c97df44 | 123 | * |
lypinator | 0:bb348c97df44 | 124 | @verbatim |
lypinator | 0:bb348c97df44 | 125 | ============================================================================== |
lypinator | 0:bb348c97df44 | 126 | ##### Initialization and de_initialization functions ##### |
lypinator | 0:bb348c97df44 | 127 | ============================================================================== |
lypinator | 0:bb348c97df44 | 128 | [..] |
lypinator | 0:bb348c97df44 | 129 | This section provides functions allowing to: |
lypinator | 0:bb348c97df44 | 130 | (+) Initialize and configure the FSMC NORSRAM interface |
lypinator | 0:bb348c97df44 | 131 | (+) De-initialize the FSMC NORSRAM interface |
lypinator | 0:bb348c97df44 | 132 | (+) Configure the FSMC clock and associated GPIOs |
lypinator | 0:bb348c97df44 | 133 | |
lypinator | 0:bb348c97df44 | 134 | @endverbatim |
lypinator | 0:bb348c97df44 | 135 | * @{ |
lypinator | 0:bb348c97df44 | 136 | */ |
lypinator | 0:bb348c97df44 | 137 | |
lypinator | 0:bb348c97df44 | 138 | /** |
lypinator | 0:bb348c97df44 | 139 | * @brief Initialize the FSMC_NORSRAM device according to the specified |
lypinator | 0:bb348c97df44 | 140 | * control parameters in the FSMC_NORSRAM_InitTypeDef |
lypinator | 0:bb348c97df44 | 141 | * @param Device Pointer to NORSRAM device instance |
lypinator | 0:bb348c97df44 | 142 | * @param Init Pointer to NORSRAM Initialization structure |
lypinator | 0:bb348c97df44 | 143 | * @retval HAL status |
lypinator | 0:bb348c97df44 | 144 | */ |
lypinator | 0:bb348c97df44 | 145 | HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_InitTypeDef* Init) |
lypinator | 0:bb348c97df44 | 146 | { |
lypinator | 0:bb348c97df44 | 147 | uint32_t tmpr = 0U; |
lypinator | 0:bb348c97df44 | 148 | |
lypinator | 0:bb348c97df44 | 149 | /* Check the parameters */ |
lypinator | 0:bb348c97df44 | 150 | assert_param(IS_FSMC_NORSRAM_DEVICE(Device)); |
lypinator | 0:bb348c97df44 | 151 | assert_param(IS_FSMC_NORSRAM_BANK(Init->NSBank)); |
lypinator | 0:bb348c97df44 | 152 | assert_param(IS_FSMC_MUX(Init->DataAddressMux)); |
lypinator | 0:bb348c97df44 | 153 | assert_param(IS_FSMC_MEMORY(Init->MemoryType)); |
lypinator | 0:bb348c97df44 | 154 | assert_param(IS_FSMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth)); |
lypinator | 0:bb348c97df44 | 155 | assert_param(IS_FSMC_BURSTMODE(Init->BurstAccessMode)); |
lypinator | 0:bb348c97df44 | 156 | assert_param(IS_FSMC_WAIT_POLARITY(Init->WaitSignalPolarity)); |
lypinator | 0:bb348c97df44 | 157 | #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) |
lypinator | 0:bb348c97df44 | 158 | assert_param(IS_FSMC_WRAP_MODE(Init->WrapMode)); |
lypinator | 0:bb348c97df44 | 159 | #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ |
lypinator | 0:bb348c97df44 | 160 | assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive)); |
lypinator | 0:bb348c97df44 | 161 | assert_param(IS_FSMC_WRITE_OPERATION(Init->WriteOperation)); |
lypinator | 0:bb348c97df44 | 162 | assert_param(IS_FSMC_WAITE_SIGNAL(Init->WaitSignal)); |
lypinator | 0:bb348c97df44 | 163 | assert_param(IS_FSMC_EXTENDED_MODE(Init->ExtendedMode)); |
lypinator | 0:bb348c97df44 | 164 | assert_param(IS_FSMC_ASYNWAIT(Init->AsynchronousWait)); |
lypinator | 0:bb348c97df44 | 165 | assert_param(IS_FSMC_WRITE_BURST(Init->WriteBurst)); |
lypinator | 0:bb348c97df44 | 166 | assert_param(IS_FSMC_PAGESIZE(Init->PageSize)); |
lypinator | 0:bb348c97df44 | 167 | #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx) |
lypinator | 0:bb348c97df44 | 168 | assert_param(IS_FSMC_WRITE_FIFO(Init->WriteFifo)); |
lypinator | 0:bb348c97df44 | 169 | assert_param(IS_FSMC_CONTINOUS_CLOCK(Init->ContinuousClock)); |
lypinator | 0:bb348c97df44 | 170 | #endif /* STM32F412Zx || STM32F412Vx || STM32F413xx || STM32F423xx */ |
lypinator | 0:bb348c97df44 | 171 | |
lypinator | 0:bb348c97df44 | 172 | /* Get the BTCR register value */ |
lypinator | 0:bb348c97df44 | 173 | tmpr = Device->BTCR[Init->NSBank]; |
lypinator | 0:bb348c97df44 | 174 | |
lypinator | 0:bb348c97df44 | 175 | #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) |
lypinator | 0:bb348c97df44 | 176 | /* Clear MBKEN, MUXEN, MTYP, MWID, FACCEN, BURSTEN, WAITPOL, WRAPMOD, WAITCFG, WREN, |
lypinator | 0:bb348c97df44 | 177 | WAITEN, EXTMOD, ASYNCWAIT, CPSIZE and CBURSTRW bits */ |
lypinator | 0:bb348c97df44 | 178 | tmpr &= ((uint32_t)~(FSMC_BCR1_MBKEN | FSMC_BCR1_MUXEN | FSMC_BCR1_MTYP | \ |
lypinator | 0:bb348c97df44 | 179 | FSMC_BCR1_MWID | FSMC_BCR1_FACCEN | FSMC_BCR1_BURSTEN | \ |
lypinator | 0:bb348c97df44 | 180 | FSMC_BCR1_WAITPOL | FSMC_BCR1_WRAPMOD | FSMC_BCR1_WAITCFG | \ |
lypinator | 0:bb348c97df44 | 181 | FSMC_BCR1_WREN | FSMC_BCR1_WAITEN | FSMC_BCR1_EXTMOD | \ |
lypinator | 0:bb348c97df44 | 182 | FSMC_BCR1_ASYNCWAIT | FSMC_BCR1_CPSIZE | FSMC_BCR1_CBURSTRW)); |
lypinator | 0:bb348c97df44 | 183 | /* Set NORSRAM device control parameters */ |
lypinator | 0:bb348c97df44 | 184 | tmpr |= (uint32_t)(Init->DataAddressMux |\ |
lypinator | 0:bb348c97df44 | 185 | Init->MemoryType |\ |
lypinator | 0:bb348c97df44 | 186 | Init->MemoryDataWidth |\ |
lypinator | 0:bb348c97df44 | 187 | Init->BurstAccessMode |\ |
lypinator | 0:bb348c97df44 | 188 | Init->WaitSignalPolarity |\ |
lypinator | 0:bb348c97df44 | 189 | Init->WrapMode |\ |
lypinator | 0:bb348c97df44 | 190 | Init->WaitSignalActive |\ |
lypinator | 0:bb348c97df44 | 191 | Init->WriteOperation |\ |
lypinator | 0:bb348c97df44 | 192 | Init->WaitSignal |\ |
lypinator | 0:bb348c97df44 | 193 | Init->ExtendedMode |\ |
lypinator | 0:bb348c97df44 | 194 | Init->AsynchronousWait |\ |
lypinator | 0:bb348c97df44 | 195 | Init->PageSize |\ |
lypinator | 0:bb348c97df44 | 196 | Init->WriteBurst |
lypinator | 0:bb348c97df44 | 197 | ); |
lypinator | 0:bb348c97df44 | 198 | #else /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */ |
lypinator | 0:bb348c97df44 | 199 | /* Clear MBKEN, MUXEN, MTYP, MWID, FACCEN, BURSTEN, WAITPOL, WAITCFG, WREN, |
lypinator | 0:bb348c97df44 | 200 | WAITEN, EXTMOD, ASYNCWAIT,CPSIZE, CBURSTRW, CCLKEN and WFDIS bits */ |
lypinator | 0:bb348c97df44 | 201 | tmpr &= ((uint32_t)~(FSMC_BCR1_MBKEN | FSMC_BCR1_MUXEN | FSMC_BCR1_MTYP | \ |
lypinator | 0:bb348c97df44 | 202 | FSMC_BCR1_MWID | FSMC_BCR1_FACCEN | FSMC_BCR1_BURSTEN | \ |
lypinator | 0:bb348c97df44 | 203 | FSMC_BCR1_WAITPOL | FSMC_BCR1_WAITCFG | FSMC_BCR1_WREN | \ |
lypinator | 0:bb348c97df44 | 204 | FSMC_BCR1_WAITEN | FSMC_BCR1_EXTMOD | FSMC_BCR1_ASYNCWAIT | \ |
lypinator | 0:bb348c97df44 | 205 | FSMC_BCR1_CPSIZE | FSMC_BCR1_CBURSTRW | FSMC_BCR1_CCLKEN | \ |
lypinator | 0:bb348c97df44 | 206 | FSMC_BCR1_WFDIS)); |
lypinator | 0:bb348c97df44 | 207 | /* Set NORSRAM device control parameters */ |
lypinator | 0:bb348c97df44 | 208 | tmpr |= (uint32_t)(Init->DataAddressMux |\ |
lypinator | 0:bb348c97df44 | 209 | Init->MemoryType |\ |
lypinator | 0:bb348c97df44 | 210 | Init->MemoryDataWidth |\ |
lypinator | 0:bb348c97df44 | 211 | Init->BurstAccessMode |\ |
lypinator | 0:bb348c97df44 | 212 | Init->WaitSignalPolarity |\ |
lypinator | 0:bb348c97df44 | 213 | Init->WaitSignalActive |\ |
lypinator | 0:bb348c97df44 | 214 | Init->WriteOperation |\ |
lypinator | 0:bb348c97df44 | 215 | Init->WaitSignal |\ |
lypinator | 0:bb348c97df44 | 216 | Init->ExtendedMode |\ |
lypinator | 0:bb348c97df44 | 217 | Init->AsynchronousWait |\ |
lypinator | 0:bb348c97df44 | 218 | Init->WriteBurst |\ |
lypinator | 0:bb348c97df44 | 219 | Init->ContinuousClock |\ |
lypinator | 0:bb348c97df44 | 220 | Init->PageSize |\ |
lypinator | 0:bb348c97df44 | 221 | Init->WriteFifo); |
lypinator | 0:bb348c97df44 | 222 | #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ |
lypinator | 0:bb348c97df44 | 223 | |
lypinator | 0:bb348c97df44 | 224 | if(Init->MemoryType == FSMC_MEMORY_TYPE_NOR) |
lypinator | 0:bb348c97df44 | 225 | { |
lypinator | 0:bb348c97df44 | 226 | tmpr |= (uint32_t)FSMC_NORSRAM_FLASH_ACCESS_ENABLE; |
lypinator | 0:bb348c97df44 | 227 | } |
lypinator | 0:bb348c97df44 | 228 | |
lypinator | 0:bb348c97df44 | 229 | Device->BTCR[Init->NSBank] = tmpr; |
lypinator | 0:bb348c97df44 | 230 | |
lypinator | 0:bb348c97df44 | 231 | #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx) |
lypinator | 0:bb348c97df44 | 232 | /* Configure synchronous mode when Continuous clock is enabled for bank2..4 */ |
lypinator | 0:bb348c97df44 | 233 | if((Init->ContinuousClock == FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FSMC_NORSRAM_BANK1)) |
lypinator | 0:bb348c97df44 | 234 | { |
lypinator | 0:bb348c97df44 | 235 | Device->BTCR[FSMC_NORSRAM_BANK1] |= (uint32_t)(Init->ContinuousClock); |
lypinator | 0:bb348c97df44 | 236 | } |
lypinator | 0:bb348c97df44 | 237 | |
lypinator | 0:bb348c97df44 | 238 | if(Init->NSBank != FSMC_NORSRAM_BANK1) |
lypinator | 0:bb348c97df44 | 239 | { |
lypinator | 0:bb348c97df44 | 240 | Device->BTCR[FSMC_NORSRAM_BANK1] |= (uint32_t)(Init->WriteFifo); |
lypinator | 0:bb348c97df44 | 241 | } |
lypinator | 0:bb348c97df44 | 242 | #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */ |
lypinator | 0:bb348c97df44 | 243 | |
lypinator | 0:bb348c97df44 | 244 | return HAL_OK; |
lypinator | 0:bb348c97df44 | 245 | } |
lypinator | 0:bb348c97df44 | 246 | |
lypinator | 0:bb348c97df44 | 247 | /** |
lypinator | 0:bb348c97df44 | 248 | * @brief DeInitialize the FSMC_NORSRAM peripheral |
lypinator | 0:bb348c97df44 | 249 | * @param Device Pointer to NORSRAM device instance |
lypinator | 0:bb348c97df44 | 250 | * @param ExDevice Pointer to NORSRAM extended mode device instance |
lypinator | 0:bb348c97df44 | 251 | * @param Bank NORSRAM bank number |
lypinator | 0:bb348c97df44 | 252 | * @retval HAL status |
lypinator | 0:bb348c97df44 | 253 | */ |
lypinator | 0:bb348c97df44 | 254 | HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank) |
lypinator | 0:bb348c97df44 | 255 | { |
lypinator | 0:bb348c97df44 | 256 | /* Check the parameters */ |
lypinator | 0:bb348c97df44 | 257 | assert_param(IS_FSMC_NORSRAM_DEVICE(Device)); |
lypinator | 0:bb348c97df44 | 258 | assert_param(IS_FSMC_NORSRAM_EXTENDED_DEVICE(ExDevice)); |
lypinator | 0:bb348c97df44 | 259 | assert_param(IS_FSMC_NORSRAM_BANK(Bank)); |
lypinator | 0:bb348c97df44 | 260 | |
lypinator | 0:bb348c97df44 | 261 | /* Disable the FSMC_NORSRAM device */ |
lypinator | 0:bb348c97df44 | 262 | __FSMC_NORSRAM_DISABLE(Device, Bank); |
lypinator | 0:bb348c97df44 | 263 | |
lypinator | 0:bb348c97df44 | 264 | /* De-initialize the FSMC_NORSRAM device */ |
lypinator | 0:bb348c97df44 | 265 | /* FSMC_NORSRAM_BANK1 */ |
lypinator | 0:bb348c97df44 | 266 | if(Bank == FSMC_NORSRAM_BANK1) |
lypinator | 0:bb348c97df44 | 267 | { |
lypinator | 0:bb348c97df44 | 268 | Device->BTCR[Bank] = 0x000030DBU; |
lypinator | 0:bb348c97df44 | 269 | } |
lypinator | 0:bb348c97df44 | 270 | /* FSMC_NORSRAM_BANK2, FSMC_NORSRAM_BANK3 or FSMC_NORSRAM_BANK4 */ |
lypinator | 0:bb348c97df44 | 271 | else |
lypinator | 0:bb348c97df44 | 272 | { |
lypinator | 0:bb348c97df44 | 273 | Device->BTCR[Bank] = 0x000030D2U; |
lypinator | 0:bb348c97df44 | 274 | } |
lypinator | 0:bb348c97df44 | 275 | |
lypinator | 0:bb348c97df44 | 276 | Device->BTCR[Bank + 1U] = 0x0FFFFFFFU; |
lypinator | 0:bb348c97df44 | 277 | ExDevice->BWTR[Bank] = 0x0FFFFFFFU; |
lypinator | 0:bb348c97df44 | 278 | |
lypinator | 0:bb348c97df44 | 279 | return HAL_OK; |
lypinator | 0:bb348c97df44 | 280 | } |
lypinator | 0:bb348c97df44 | 281 | |
lypinator | 0:bb348c97df44 | 282 | |
lypinator | 0:bb348c97df44 | 283 | /** |
lypinator | 0:bb348c97df44 | 284 | * @brief Initialize the FSMC_NORSRAM Timing according to the specified |
lypinator | 0:bb348c97df44 | 285 | * parameters in the FSMC_NORSRAM_TimingTypeDef |
lypinator | 0:bb348c97df44 | 286 | * @param Device Pointer to NORSRAM device instance |
lypinator | 0:bb348c97df44 | 287 | * @param Timing Pointer to NORSRAM Timing structure |
lypinator | 0:bb348c97df44 | 288 | * @param Bank NORSRAM bank number |
lypinator | 0:bb348c97df44 | 289 | * @retval HAL status |
lypinator | 0:bb348c97df44 | 290 | */ |
lypinator | 0:bb348c97df44 | 291 | HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) |
lypinator | 0:bb348c97df44 | 292 | { |
lypinator | 0:bb348c97df44 | 293 | uint32_t tmpr = 0U; |
lypinator | 0:bb348c97df44 | 294 | |
lypinator | 0:bb348c97df44 | 295 | /* Check the parameters */ |
lypinator | 0:bb348c97df44 | 296 | assert_param(IS_FSMC_NORSRAM_DEVICE(Device)); |
lypinator | 0:bb348c97df44 | 297 | assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); |
lypinator | 0:bb348c97df44 | 298 | assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime)); |
lypinator | 0:bb348c97df44 | 299 | assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime)); |
lypinator | 0:bb348c97df44 | 300 | assert_param(IS_FSMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration)); |
lypinator | 0:bb348c97df44 | 301 | assert_param(IS_FSMC_CLK_DIV(Timing->CLKDivision)); |
lypinator | 0:bb348c97df44 | 302 | assert_param(IS_FSMC_DATA_LATENCY(Timing->DataLatency)); |
lypinator | 0:bb348c97df44 | 303 | assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode)); |
lypinator | 0:bb348c97df44 | 304 | assert_param(IS_FSMC_NORSRAM_BANK(Bank)); |
lypinator | 0:bb348c97df44 | 305 | |
lypinator | 0:bb348c97df44 | 306 | /* Get the BTCR register value */ |
lypinator | 0:bb348c97df44 | 307 | tmpr = Device->BTCR[Bank + 1U]; |
lypinator | 0:bb348c97df44 | 308 | |
lypinator | 0:bb348c97df44 | 309 | /* Clear ADDSET, ADDHLD, DATAST, BUSTURN, CLKDIV, DATLAT and ACCMOD bits */ |
lypinator | 0:bb348c97df44 | 310 | tmpr &= ((uint32_t)~(FSMC_BTR1_ADDSET | FSMC_BTR1_ADDHLD | FSMC_BTR1_DATAST | \ |
lypinator | 0:bb348c97df44 | 311 | FSMC_BTR1_BUSTURN | FSMC_BTR1_CLKDIV | FSMC_BTR1_DATLAT | \ |
lypinator | 0:bb348c97df44 | 312 | FSMC_BTR1_ACCMOD)); |
lypinator | 0:bb348c97df44 | 313 | |
lypinator | 0:bb348c97df44 | 314 | /* Set FSMC_NORSRAM device timing parameters */ |
lypinator | 0:bb348c97df44 | 315 | tmpr |= (uint32_t)(Timing->AddressSetupTime |\ |
lypinator | 0:bb348c97df44 | 316 | ((Timing->AddressHoldTime) << 4U) |\ |
lypinator | 0:bb348c97df44 | 317 | ((Timing->DataSetupTime) << 8U) |\ |
lypinator | 0:bb348c97df44 | 318 | ((Timing->BusTurnAroundDuration) << 16U) |\ |
lypinator | 0:bb348c97df44 | 319 | (((Timing->CLKDivision)-1U) << 20U) |\ |
lypinator | 0:bb348c97df44 | 320 | (((Timing->DataLatency)-2U) << 24U) |\ |
lypinator | 0:bb348c97df44 | 321 | (Timing->AccessMode)); |
lypinator | 0:bb348c97df44 | 322 | |
lypinator | 0:bb348c97df44 | 323 | Device->BTCR[Bank + 1] = tmpr; |
lypinator | 0:bb348c97df44 | 324 | |
lypinator | 0:bb348c97df44 | 325 | #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx) |
lypinator | 0:bb348c97df44 | 326 | /* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */ |
lypinator | 0:bb348c97df44 | 327 | if(HAL_IS_BIT_SET(Device->BTCR[FSMC_NORSRAM_BANK1], FSMC_BCR1_CCLKEN)) |
lypinator | 0:bb348c97df44 | 328 | { |
lypinator | 0:bb348c97df44 | 329 | tmpr = (uint32_t)(Device->BTCR[FSMC_NORSRAM_BANK1 + 1U] & ~(0x0FU << 20U)); |
lypinator | 0:bb348c97df44 | 330 | tmpr |= (uint32_t)(((Timing->CLKDivision)-1U) << 20U); |
lypinator | 0:bb348c97df44 | 331 | Device->BTCR[FSMC_NORSRAM_BANK1 + 1U] = tmpr; |
lypinator | 0:bb348c97df44 | 332 | } |
lypinator | 0:bb348c97df44 | 333 | #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */ |
lypinator | 0:bb348c97df44 | 334 | |
lypinator | 0:bb348c97df44 | 335 | return HAL_OK; |
lypinator | 0:bb348c97df44 | 336 | } |
lypinator | 0:bb348c97df44 | 337 | |
lypinator | 0:bb348c97df44 | 338 | /** |
lypinator | 0:bb348c97df44 | 339 | * @brief Initialize the FSMC_NORSRAM Extended mode Timing according to the specified |
lypinator | 0:bb348c97df44 | 340 | * parameters in the FSMC_NORSRAM_TimingTypeDef |
lypinator | 0:bb348c97df44 | 341 | * @param Device Pointer to NORSRAM device instance |
lypinator | 0:bb348c97df44 | 342 | * @param Timing Pointer to NORSRAM Timing structure |
lypinator | 0:bb348c97df44 | 343 | * @param Bank NORSRAM bank number |
lypinator | 0:bb348c97df44 | 344 | * @retval HAL status |
lypinator | 0:bb348c97df44 | 345 | */ |
lypinator | 0:bb348c97df44 | 346 | HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode) |
lypinator | 0:bb348c97df44 | 347 | { |
lypinator | 0:bb348c97df44 | 348 | uint32_t tmpr = 0U; |
lypinator | 0:bb348c97df44 | 349 | |
lypinator | 0:bb348c97df44 | 350 | /* Check the parameters */ |
lypinator | 0:bb348c97df44 | 351 | assert_param(IS_FSMC_EXTENDED_MODE(ExtendedMode)); |
lypinator | 0:bb348c97df44 | 352 | |
lypinator | 0:bb348c97df44 | 353 | /* Set NORSRAM device timing register for write configuration, if extended mode is used */ |
lypinator | 0:bb348c97df44 | 354 | if(ExtendedMode == FSMC_EXTENDED_MODE_ENABLE) |
lypinator | 0:bb348c97df44 | 355 | { |
lypinator | 0:bb348c97df44 | 356 | /* Check the parameters */ |
lypinator | 0:bb348c97df44 | 357 | assert_param(IS_FSMC_NORSRAM_EXTENDED_DEVICE(Device)); |
lypinator | 0:bb348c97df44 | 358 | assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); |
lypinator | 0:bb348c97df44 | 359 | assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime)); |
lypinator | 0:bb348c97df44 | 360 | assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime)); |
lypinator | 0:bb348c97df44 | 361 | assert_param(IS_FSMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration)); |
lypinator | 0:bb348c97df44 | 362 | assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode)); |
lypinator | 0:bb348c97df44 | 363 | assert_param(IS_FSMC_NORSRAM_BANK(Bank)); |
lypinator | 0:bb348c97df44 | 364 | |
lypinator | 0:bb348c97df44 | 365 | /* Get the BWTR register value */ |
lypinator | 0:bb348c97df44 | 366 | tmpr = Device->BWTR[Bank]; |
lypinator | 0:bb348c97df44 | 367 | |
lypinator | 0:bb348c97df44 | 368 | /* Clear ADDSET, ADDHLD, DATAST, BUSTURN and ACCMOD bits */ |
lypinator | 0:bb348c97df44 | 369 | tmpr &= ((uint32_t)~(FSMC_BWTR1_ADDSET | FSMC_BWTR1_ADDHLD | FSMC_BWTR1_DATAST | \ |
lypinator | 0:bb348c97df44 | 370 | FSMC_BWTR1_BUSTURN | FSMC_BWTR1_ACCMOD)); |
lypinator | 0:bb348c97df44 | 371 | |
lypinator | 0:bb348c97df44 | 372 | tmpr |= (uint32_t)(Timing->AddressSetupTime |\ |
lypinator | 0:bb348c97df44 | 373 | ((Timing->AddressHoldTime) << 4U) |\ |
lypinator | 0:bb348c97df44 | 374 | ((Timing->DataSetupTime) << 8U) |\ |
lypinator | 0:bb348c97df44 | 375 | ((Timing->BusTurnAroundDuration) << 16U) |\ |
lypinator | 0:bb348c97df44 | 376 | (Timing->AccessMode)); |
lypinator | 0:bb348c97df44 | 377 | |
lypinator | 0:bb348c97df44 | 378 | Device->BWTR[Bank] = tmpr; |
lypinator | 0:bb348c97df44 | 379 | } |
lypinator | 0:bb348c97df44 | 380 | else |
lypinator | 0:bb348c97df44 | 381 | { |
lypinator | 0:bb348c97df44 | 382 | Device->BWTR[Bank] = 0x0FFFFFFFU; |
lypinator | 0:bb348c97df44 | 383 | } |
lypinator | 0:bb348c97df44 | 384 | |
lypinator | 0:bb348c97df44 | 385 | return HAL_OK; |
lypinator | 0:bb348c97df44 | 386 | } |
lypinator | 0:bb348c97df44 | 387 | /** |
lypinator | 0:bb348c97df44 | 388 | * @} |
lypinator | 0:bb348c97df44 | 389 | */ |
lypinator | 0:bb348c97df44 | 390 | |
lypinator | 0:bb348c97df44 | 391 | /** @addtogroup FSMC_LL_NORSRAM_Private_Functions_Group2 |
lypinator | 0:bb348c97df44 | 392 | * @brief management functions |
lypinator | 0:bb348c97df44 | 393 | * |
lypinator | 0:bb348c97df44 | 394 | @verbatim |
lypinator | 0:bb348c97df44 | 395 | ============================================================================== |
lypinator | 0:bb348c97df44 | 396 | ##### FSMC_NORSRAM Control functions ##### |
lypinator | 0:bb348c97df44 | 397 | ============================================================================== |
lypinator | 0:bb348c97df44 | 398 | [..] |
lypinator | 0:bb348c97df44 | 399 | This subsection provides a set of functions allowing to control dynamically |
lypinator | 0:bb348c97df44 | 400 | the FSMC NORSRAM interface. |
lypinator | 0:bb348c97df44 | 401 | |
lypinator | 0:bb348c97df44 | 402 | @endverbatim |
lypinator | 0:bb348c97df44 | 403 | * @{ |
lypinator | 0:bb348c97df44 | 404 | */ |
lypinator | 0:bb348c97df44 | 405 | |
lypinator | 0:bb348c97df44 | 406 | /** |
lypinator | 0:bb348c97df44 | 407 | * @brief Enables dynamically FSMC_NORSRAM write operation. |
lypinator | 0:bb348c97df44 | 408 | * @param Device Pointer to NORSRAM device instance |
lypinator | 0:bb348c97df44 | 409 | * @param Bank NORSRAM bank number |
lypinator | 0:bb348c97df44 | 410 | * @retval HAL status |
lypinator | 0:bb348c97df44 | 411 | */ |
lypinator | 0:bb348c97df44 | 412 | HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank) |
lypinator | 0:bb348c97df44 | 413 | { |
lypinator | 0:bb348c97df44 | 414 | /* Check the parameters */ |
lypinator | 0:bb348c97df44 | 415 | assert_param(IS_FSMC_NORSRAM_DEVICE(Device)); |
lypinator | 0:bb348c97df44 | 416 | assert_param(IS_FSMC_NORSRAM_BANK(Bank)); |
lypinator | 0:bb348c97df44 | 417 | |
lypinator | 0:bb348c97df44 | 418 | /* Enable write operation */ |
lypinator | 0:bb348c97df44 | 419 | Device->BTCR[Bank] |= FSMC_WRITE_OPERATION_ENABLE; |
lypinator | 0:bb348c97df44 | 420 | |
lypinator | 0:bb348c97df44 | 421 | return HAL_OK; |
lypinator | 0:bb348c97df44 | 422 | } |
lypinator | 0:bb348c97df44 | 423 | |
lypinator | 0:bb348c97df44 | 424 | /** |
lypinator | 0:bb348c97df44 | 425 | * @brief Disables dynamically FSMC_NORSRAM write operation. |
lypinator | 0:bb348c97df44 | 426 | * @param Device Pointer to NORSRAM device instance |
lypinator | 0:bb348c97df44 | 427 | * @param Bank NORSRAM bank number |
lypinator | 0:bb348c97df44 | 428 | * @retval HAL status |
lypinator | 0:bb348c97df44 | 429 | */ |
lypinator | 0:bb348c97df44 | 430 | HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank) |
lypinator | 0:bb348c97df44 | 431 | { |
lypinator | 0:bb348c97df44 | 432 | /* Check the parameters */ |
lypinator | 0:bb348c97df44 | 433 | assert_param(IS_FSMC_NORSRAM_DEVICE(Device)); |
lypinator | 0:bb348c97df44 | 434 | assert_param(IS_FSMC_NORSRAM_BANK(Bank)); |
lypinator | 0:bb348c97df44 | 435 | |
lypinator | 0:bb348c97df44 | 436 | /* Disable write operation */ |
lypinator | 0:bb348c97df44 | 437 | Device->BTCR[Bank] &= ~FSMC_WRITE_OPERATION_ENABLE; |
lypinator | 0:bb348c97df44 | 438 | |
lypinator | 0:bb348c97df44 | 439 | return HAL_OK; |
lypinator | 0:bb348c97df44 | 440 | } |
lypinator | 0:bb348c97df44 | 441 | /** |
lypinator | 0:bb348c97df44 | 442 | * @} |
lypinator | 0:bb348c97df44 | 443 | */ |
lypinator | 0:bb348c97df44 | 444 | |
lypinator | 0:bb348c97df44 | 445 | /** |
lypinator | 0:bb348c97df44 | 446 | * @} |
lypinator | 0:bb348c97df44 | 447 | */ |
lypinator | 0:bb348c97df44 | 448 | |
lypinator | 0:bb348c97df44 | 449 | #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) |
lypinator | 0:bb348c97df44 | 450 | /** @addtogroup FSMC_LL_NAND |
lypinator | 0:bb348c97df44 | 451 | * @brief NAND Controller functions |
lypinator | 0:bb348c97df44 | 452 | * |
lypinator | 0:bb348c97df44 | 453 | @verbatim |
lypinator | 0:bb348c97df44 | 454 | ============================================================================== |
lypinator | 0:bb348c97df44 | 455 | ##### How to use NAND device driver ##### |
lypinator | 0:bb348c97df44 | 456 | ============================================================================== |
lypinator | 0:bb348c97df44 | 457 | [..] |
lypinator | 0:bb348c97df44 | 458 | This driver contains a set of APIs to interface with the FSMC NAND banks in order |
lypinator | 0:bb348c97df44 | 459 | to run the NAND external devices. |
lypinator | 0:bb348c97df44 | 460 | |
lypinator | 0:bb348c97df44 | 461 | (+) FSMC NAND bank reset using the function FSMC_NAND_DeInit() |
lypinator | 0:bb348c97df44 | 462 | (+) FSMC NAND bank control configuration using the function FSMC_NAND_Init() |
lypinator | 0:bb348c97df44 | 463 | (+) FSMC NAND bank common space timing configuration using the function |
lypinator | 0:bb348c97df44 | 464 | FSMC_NAND_CommonSpace_Timing_Init() |
lypinator | 0:bb348c97df44 | 465 | (+) FSMC NAND bank attribute space timing configuration using the function |
lypinator | 0:bb348c97df44 | 466 | FSMC_NAND_AttributeSpace_Timing_Init() |
lypinator | 0:bb348c97df44 | 467 | (+) FSMC NAND bank enable/disable ECC correction feature using the functions |
lypinator | 0:bb348c97df44 | 468 | FSMC_NAND_ECC_Enable()/FSMC_NAND_ECC_Disable() |
lypinator | 0:bb348c97df44 | 469 | (+) FSMC NAND bank get ECC correction code using the function FSMC_NAND_GetECC() |
lypinator | 0:bb348c97df44 | 470 | |
lypinator | 0:bb348c97df44 | 471 | @endverbatim |
lypinator | 0:bb348c97df44 | 472 | * @{ |
lypinator | 0:bb348c97df44 | 473 | */ |
lypinator | 0:bb348c97df44 | 474 | |
lypinator | 0:bb348c97df44 | 475 | /** @addtogroup FSMC_LL_NAND_Private_Functions_Group1 |
lypinator | 0:bb348c97df44 | 476 | * @brief Initialization and Configuration functions |
lypinator | 0:bb348c97df44 | 477 | * |
lypinator | 0:bb348c97df44 | 478 | @verbatim |
lypinator | 0:bb348c97df44 | 479 | ============================================================================== |
lypinator | 0:bb348c97df44 | 480 | ##### Initialization and de_initialization functions ##### |
lypinator | 0:bb348c97df44 | 481 | ============================================================================== |
lypinator | 0:bb348c97df44 | 482 | [..] |
lypinator | 0:bb348c97df44 | 483 | This section provides functions allowing to: |
lypinator | 0:bb348c97df44 | 484 | (+) Initialize and configure the FSMC NAND interface |
lypinator | 0:bb348c97df44 | 485 | (+) De-initialize the FSMC NAND interface |
lypinator | 0:bb348c97df44 | 486 | (+) Configure the FSMC clock and associated GPIOs |
lypinator | 0:bb348c97df44 | 487 | |
lypinator | 0:bb348c97df44 | 488 | @endverbatim |
lypinator | 0:bb348c97df44 | 489 | * @{ |
lypinator | 0:bb348c97df44 | 490 | */ |
lypinator | 0:bb348c97df44 | 491 | |
lypinator | 0:bb348c97df44 | 492 | /** |
lypinator | 0:bb348c97df44 | 493 | * @brief Initializes the FSMC_NAND device according to the specified |
lypinator | 0:bb348c97df44 | 494 | * control parameters in the FSMC_NAND_HandleTypeDef |
lypinator | 0:bb348c97df44 | 495 | * @param Device Pointer to NAND device instance |
lypinator | 0:bb348c97df44 | 496 | * @param Init Pointer to NAND Initialization structure |
lypinator | 0:bb348c97df44 | 497 | * @retval HAL status |
lypinator | 0:bb348c97df44 | 498 | */ |
lypinator | 0:bb348c97df44 | 499 | HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init) |
lypinator | 0:bb348c97df44 | 500 | { |
lypinator | 0:bb348c97df44 | 501 | uint32_t tmpr = 0U; |
lypinator | 0:bb348c97df44 | 502 | |
lypinator | 0:bb348c97df44 | 503 | /* Check the parameters */ |
lypinator | 0:bb348c97df44 | 504 | assert_param(IS_FSMC_NAND_BANK(Init->NandBank)); |
lypinator | 0:bb348c97df44 | 505 | assert_param(IS_FSMC_WAIT_FEATURE(Init->Waitfeature)); |
lypinator | 0:bb348c97df44 | 506 | assert_param(IS_FSMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth)); |
lypinator | 0:bb348c97df44 | 507 | assert_param(IS_FSMC_ECC_STATE(Init->EccComputation)); |
lypinator | 0:bb348c97df44 | 508 | assert_param(IS_FSMC_ECCPAGE_SIZE(Init->ECCPageSize)); |
lypinator | 0:bb348c97df44 | 509 | assert_param(IS_FSMC_TCLR_TIME(Init->TCLRSetupTime)); |
lypinator | 0:bb348c97df44 | 510 | assert_param(IS_FSMC_TAR_TIME(Init->TARSetupTime)); |
lypinator | 0:bb348c97df44 | 511 | |
lypinator | 0:bb348c97df44 | 512 | if(Init->NandBank == FSMC_NAND_BANK2) |
lypinator | 0:bb348c97df44 | 513 | { |
lypinator | 0:bb348c97df44 | 514 | /* Get the NAND bank 2 register value */ |
lypinator | 0:bb348c97df44 | 515 | tmpr = Device->PCR2; |
lypinator | 0:bb348c97df44 | 516 | } |
lypinator | 0:bb348c97df44 | 517 | else |
lypinator | 0:bb348c97df44 | 518 | { |
lypinator | 0:bb348c97df44 | 519 | /* Get the NAND bank 3 register value */ |
lypinator | 0:bb348c97df44 | 520 | tmpr = Device->PCR3; |
lypinator | 0:bb348c97df44 | 521 | } |
lypinator | 0:bb348c97df44 | 522 | |
lypinator | 0:bb348c97df44 | 523 | /* Clear PWAITEN, PBKEN, PTYP, PWID, ECCEN, TCLR, TAR and ECCPS bits */ |
lypinator | 0:bb348c97df44 | 524 | tmpr &= ((uint32_t)~(FSMC_PCR2_PWAITEN | FSMC_PCR2_PBKEN | FSMC_PCR2_PTYP | \ |
lypinator | 0:bb348c97df44 | 525 | FSMC_PCR2_PWID | FSMC_PCR2_ECCEN | FSMC_PCR2_TCLR | \ |
lypinator | 0:bb348c97df44 | 526 | FSMC_PCR2_TAR | FSMC_PCR2_ECCPS)); |
lypinator | 0:bb348c97df44 | 527 | |
lypinator | 0:bb348c97df44 | 528 | /* Set NAND device control parameters */ |
lypinator | 0:bb348c97df44 | 529 | tmpr |= (uint32_t)(Init->Waitfeature |\ |
lypinator | 0:bb348c97df44 | 530 | FSMC_PCR_MEMORY_TYPE_NAND |\ |
lypinator | 0:bb348c97df44 | 531 | Init->MemoryDataWidth |\ |
lypinator | 0:bb348c97df44 | 532 | Init->EccComputation |\ |
lypinator | 0:bb348c97df44 | 533 | Init->ECCPageSize |\ |
lypinator | 0:bb348c97df44 | 534 | ((Init->TCLRSetupTime) << 9U) |\ |
lypinator | 0:bb348c97df44 | 535 | ((Init->TARSetupTime) << 13U)); |
lypinator | 0:bb348c97df44 | 536 | |
lypinator | 0:bb348c97df44 | 537 | if(Init->NandBank == FSMC_NAND_BANK2) |
lypinator | 0:bb348c97df44 | 538 | { |
lypinator | 0:bb348c97df44 | 539 | /* NAND bank 2 registers configuration */ |
lypinator | 0:bb348c97df44 | 540 | Device->PCR2 = tmpr; |
lypinator | 0:bb348c97df44 | 541 | } |
lypinator | 0:bb348c97df44 | 542 | else |
lypinator | 0:bb348c97df44 | 543 | { |
lypinator | 0:bb348c97df44 | 544 | /* NAND bank 3 registers configuration */ |
lypinator | 0:bb348c97df44 | 545 | Device->PCR3 = tmpr; |
lypinator | 0:bb348c97df44 | 546 | } |
lypinator | 0:bb348c97df44 | 547 | |
lypinator | 0:bb348c97df44 | 548 | return HAL_OK; |
lypinator | 0:bb348c97df44 | 549 | } |
lypinator | 0:bb348c97df44 | 550 | |
lypinator | 0:bb348c97df44 | 551 | /** |
lypinator | 0:bb348c97df44 | 552 | * @brief Initializes the FSMC_NAND Common space Timing according to the specified |
lypinator | 0:bb348c97df44 | 553 | * parameters in the FSMC_NAND_PCC_TimingTypeDef |
lypinator | 0:bb348c97df44 | 554 | * @param Device Pointer to NAND device instance |
lypinator | 0:bb348c97df44 | 555 | * @param Timing Pointer to NAND timing structure |
lypinator | 0:bb348c97df44 | 556 | * @param Bank NAND bank number |
lypinator | 0:bb348c97df44 | 557 | * @retval HAL status |
lypinator | 0:bb348c97df44 | 558 | */ |
lypinator | 0:bb348c97df44 | 559 | HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) |
lypinator | 0:bb348c97df44 | 560 | { |
lypinator | 0:bb348c97df44 | 561 | uint32_t tmpr = 0U; |
lypinator | 0:bb348c97df44 | 562 | |
lypinator | 0:bb348c97df44 | 563 | /* Check the parameters */ |
lypinator | 0:bb348c97df44 | 564 | assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime)); |
lypinator | 0:bb348c97df44 | 565 | assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime)); |
lypinator | 0:bb348c97df44 | 566 | assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime)); |
lypinator | 0:bb348c97df44 | 567 | assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime)); |
lypinator | 0:bb348c97df44 | 568 | |
lypinator | 0:bb348c97df44 | 569 | if(Bank == FSMC_NAND_BANK2) |
lypinator | 0:bb348c97df44 | 570 | { |
lypinator | 0:bb348c97df44 | 571 | /* Get the NAND bank 2 register value */ |
lypinator | 0:bb348c97df44 | 572 | tmpr = Device->PMEM2; |
lypinator | 0:bb348c97df44 | 573 | } |
lypinator | 0:bb348c97df44 | 574 | else |
lypinator | 0:bb348c97df44 | 575 | { |
lypinator | 0:bb348c97df44 | 576 | /* Get the NAND bank 3 register value */ |
lypinator | 0:bb348c97df44 | 577 | tmpr = Device->PMEM3; |
lypinator | 0:bb348c97df44 | 578 | } |
lypinator | 0:bb348c97df44 | 579 | |
lypinator | 0:bb348c97df44 | 580 | /* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */ |
lypinator | 0:bb348c97df44 | 581 | tmpr &= ((uint32_t)~(FSMC_PMEM2_MEMSET2 | FSMC_PMEM2_MEMWAIT2 | FSMC_PMEM2_MEMHOLD2 | \ |
lypinator | 0:bb348c97df44 | 582 | FSMC_PMEM2_MEMHIZ2)); |
lypinator | 0:bb348c97df44 | 583 | |
lypinator | 0:bb348c97df44 | 584 | /* Set FSMC_NAND device timing parameters */ |
lypinator | 0:bb348c97df44 | 585 | tmpr |= (uint32_t)(Timing->SetupTime |\ |
lypinator | 0:bb348c97df44 | 586 | ((Timing->WaitSetupTime) << 8U) |\ |
lypinator | 0:bb348c97df44 | 587 | ((Timing->HoldSetupTime) << 16U) |\ |
lypinator | 0:bb348c97df44 | 588 | ((Timing->HiZSetupTime) << 24U) |
lypinator | 0:bb348c97df44 | 589 | ); |
lypinator | 0:bb348c97df44 | 590 | |
lypinator | 0:bb348c97df44 | 591 | if(Bank == FSMC_NAND_BANK2) |
lypinator | 0:bb348c97df44 | 592 | { |
lypinator | 0:bb348c97df44 | 593 | /* NAND bank 2 registers configuration */ |
lypinator | 0:bb348c97df44 | 594 | Device->PMEM2 = tmpr; |
lypinator | 0:bb348c97df44 | 595 | } |
lypinator | 0:bb348c97df44 | 596 | else |
lypinator | 0:bb348c97df44 | 597 | { |
lypinator | 0:bb348c97df44 | 598 | /* NAND bank 3 registers configuration */ |
lypinator | 0:bb348c97df44 | 599 | Device->PMEM3 = tmpr; |
lypinator | 0:bb348c97df44 | 600 | } |
lypinator | 0:bb348c97df44 | 601 | |
lypinator | 0:bb348c97df44 | 602 | return HAL_OK; |
lypinator | 0:bb348c97df44 | 603 | } |
lypinator | 0:bb348c97df44 | 604 | |
lypinator | 0:bb348c97df44 | 605 | /** |
lypinator | 0:bb348c97df44 | 606 | * @brief Initializes the FSMC_NAND Attribute space Timing according to the specified |
lypinator | 0:bb348c97df44 | 607 | * parameters in the FSMC_NAND_PCC_TimingTypeDef |
lypinator | 0:bb348c97df44 | 608 | * @param Device Pointer to NAND device instance |
lypinator | 0:bb348c97df44 | 609 | * @param Timing Pointer to NAND timing structure |
lypinator | 0:bb348c97df44 | 610 | * @param Bank NAND bank number |
lypinator | 0:bb348c97df44 | 611 | * @retval HAL status |
lypinator | 0:bb348c97df44 | 612 | */ |
lypinator | 0:bb348c97df44 | 613 | HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) |
lypinator | 0:bb348c97df44 | 614 | { |
lypinator | 0:bb348c97df44 | 615 | uint32_t tmpr = 0U; |
lypinator | 0:bb348c97df44 | 616 | |
lypinator | 0:bb348c97df44 | 617 | /* Check the parameters */ |
lypinator | 0:bb348c97df44 | 618 | assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime)); |
lypinator | 0:bb348c97df44 | 619 | assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime)); |
lypinator | 0:bb348c97df44 | 620 | assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime)); |
lypinator | 0:bb348c97df44 | 621 | assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime)); |
lypinator | 0:bb348c97df44 | 622 | |
lypinator | 0:bb348c97df44 | 623 | if(Bank == FSMC_NAND_BANK2) |
lypinator | 0:bb348c97df44 | 624 | { |
lypinator | 0:bb348c97df44 | 625 | /* Get the NAND bank 2 register value */ |
lypinator | 0:bb348c97df44 | 626 | tmpr = Device->PATT2; |
lypinator | 0:bb348c97df44 | 627 | } |
lypinator | 0:bb348c97df44 | 628 | else |
lypinator | 0:bb348c97df44 | 629 | { |
lypinator | 0:bb348c97df44 | 630 | /* Get the NAND bank 3 register value */ |
lypinator | 0:bb348c97df44 | 631 | tmpr = Device->PATT3; |
lypinator | 0:bb348c97df44 | 632 | } |
lypinator | 0:bb348c97df44 | 633 | |
lypinator | 0:bb348c97df44 | 634 | /* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */ |
lypinator | 0:bb348c97df44 | 635 | tmpr &= ((uint32_t)~(FSMC_PATT2_ATTSET2 | FSMC_PATT2_ATTWAIT2 | FSMC_PATT2_ATTHOLD2 | \ |
lypinator | 0:bb348c97df44 | 636 | FSMC_PATT2_ATTHIZ2)); |
lypinator | 0:bb348c97df44 | 637 | |
lypinator | 0:bb348c97df44 | 638 | /* Set FSMC_NAND device timing parameters */ |
lypinator | 0:bb348c97df44 | 639 | tmpr |= (uint32_t)(Timing->SetupTime |\ |
lypinator | 0:bb348c97df44 | 640 | ((Timing->WaitSetupTime) << 8U) |\ |
lypinator | 0:bb348c97df44 | 641 | ((Timing->HoldSetupTime) << 16U) |\ |
lypinator | 0:bb348c97df44 | 642 | ((Timing->HiZSetupTime) << 24U) |
lypinator | 0:bb348c97df44 | 643 | ); |
lypinator | 0:bb348c97df44 | 644 | |
lypinator | 0:bb348c97df44 | 645 | if(Bank == FSMC_NAND_BANK2) |
lypinator | 0:bb348c97df44 | 646 | { |
lypinator | 0:bb348c97df44 | 647 | /* NAND bank 2 registers configuration */ |
lypinator | 0:bb348c97df44 | 648 | Device->PATT2 = tmpr; |
lypinator | 0:bb348c97df44 | 649 | } |
lypinator | 0:bb348c97df44 | 650 | else |
lypinator | 0:bb348c97df44 | 651 | { |
lypinator | 0:bb348c97df44 | 652 | /* NAND bank 3 registers configuration */ |
lypinator | 0:bb348c97df44 | 653 | Device->PATT3 = tmpr; |
lypinator | 0:bb348c97df44 | 654 | } |
lypinator | 0:bb348c97df44 | 655 | |
lypinator | 0:bb348c97df44 | 656 | return HAL_OK; |
lypinator | 0:bb348c97df44 | 657 | } |
lypinator | 0:bb348c97df44 | 658 | |
lypinator | 0:bb348c97df44 | 659 | /** |
lypinator | 0:bb348c97df44 | 660 | * @brief DeInitializes the FSMC_NAND device |
lypinator | 0:bb348c97df44 | 661 | * @param Device Pointer to NAND device instance |
lypinator | 0:bb348c97df44 | 662 | * @param Bank NAND bank number |
lypinator | 0:bb348c97df44 | 663 | * @retval HAL status |
lypinator | 0:bb348c97df44 | 664 | */ |
lypinator | 0:bb348c97df44 | 665 | HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank) |
lypinator | 0:bb348c97df44 | 666 | { |
lypinator | 0:bb348c97df44 | 667 | /* Disable the NAND Bank */ |
lypinator | 0:bb348c97df44 | 668 | __FSMC_NAND_DISABLE(Device, Bank); |
lypinator | 0:bb348c97df44 | 669 | |
lypinator | 0:bb348c97df44 | 670 | /* De-initialize the NAND Bank */ |
lypinator | 0:bb348c97df44 | 671 | if(Bank == FSMC_NAND_BANK2) |
lypinator | 0:bb348c97df44 | 672 | { |
lypinator | 0:bb348c97df44 | 673 | /* Set the FSMC_NAND_BANK2 registers to their reset values */ |
lypinator | 0:bb348c97df44 | 674 | Device->PCR2 = 0x00000018U; |
lypinator | 0:bb348c97df44 | 675 | Device->SR2 = 0x00000040U; |
lypinator | 0:bb348c97df44 | 676 | Device->PMEM2 = 0xFCFCFCFCU; |
lypinator | 0:bb348c97df44 | 677 | Device->PATT2 = 0xFCFCFCFCU; |
lypinator | 0:bb348c97df44 | 678 | } |
lypinator | 0:bb348c97df44 | 679 | /* FSMC_Bank3_NAND */ |
lypinator | 0:bb348c97df44 | 680 | else |
lypinator | 0:bb348c97df44 | 681 | { |
lypinator | 0:bb348c97df44 | 682 | /* Set the FSMC_NAND_BANK3 registers to their reset values */ |
lypinator | 0:bb348c97df44 | 683 | Device->PCR3 = 0x00000018U; |
lypinator | 0:bb348c97df44 | 684 | Device->SR3 = 0x00000040U; |
lypinator | 0:bb348c97df44 | 685 | Device->PMEM3 = 0xFCFCFCFCU; |
lypinator | 0:bb348c97df44 | 686 | Device->PATT3 = 0xFCFCFCFCU; |
lypinator | 0:bb348c97df44 | 687 | } |
lypinator | 0:bb348c97df44 | 688 | |
lypinator | 0:bb348c97df44 | 689 | return HAL_OK; |
lypinator | 0:bb348c97df44 | 690 | } |
lypinator | 0:bb348c97df44 | 691 | /** |
lypinator | 0:bb348c97df44 | 692 | * @} |
lypinator | 0:bb348c97df44 | 693 | */ |
lypinator | 0:bb348c97df44 | 694 | |
lypinator | 0:bb348c97df44 | 695 | /** @addtogroup FSMC_LL_NAND_Private_Functions_Group2 |
lypinator | 0:bb348c97df44 | 696 | * @brief management functions |
lypinator | 0:bb348c97df44 | 697 | * |
lypinator | 0:bb348c97df44 | 698 | @verbatim |
lypinator | 0:bb348c97df44 | 699 | ============================================================================== |
lypinator | 0:bb348c97df44 | 700 | ##### FSMC_NAND Control functions ##### |
lypinator | 0:bb348c97df44 | 701 | ============================================================================== |
lypinator | 0:bb348c97df44 | 702 | [..] |
lypinator | 0:bb348c97df44 | 703 | This subsection provides a set of functions allowing to control dynamically |
lypinator | 0:bb348c97df44 | 704 | the FSMC NAND interface. |
lypinator | 0:bb348c97df44 | 705 | |
lypinator | 0:bb348c97df44 | 706 | @endverbatim |
lypinator | 0:bb348c97df44 | 707 | * @{ |
lypinator | 0:bb348c97df44 | 708 | */ |
lypinator | 0:bb348c97df44 | 709 | |
lypinator | 0:bb348c97df44 | 710 | /** |
lypinator | 0:bb348c97df44 | 711 | * @brief Enables dynamically FSMC_NAND ECC feature. |
lypinator | 0:bb348c97df44 | 712 | * @param Device Pointer to NAND device instance |
lypinator | 0:bb348c97df44 | 713 | * @param Bank NAND bank number |
lypinator | 0:bb348c97df44 | 714 | * @retval HAL status |
lypinator | 0:bb348c97df44 | 715 | */ |
lypinator | 0:bb348c97df44 | 716 | HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank) |
lypinator | 0:bb348c97df44 | 717 | { |
lypinator | 0:bb348c97df44 | 718 | /* Enable ECC feature */ |
lypinator | 0:bb348c97df44 | 719 | if(Bank == FSMC_NAND_BANK2) |
lypinator | 0:bb348c97df44 | 720 | { |
lypinator | 0:bb348c97df44 | 721 | Device->PCR2 |= FSMC_PCR2_ECCEN; |
lypinator | 0:bb348c97df44 | 722 | } |
lypinator | 0:bb348c97df44 | 723 | else |
lypinator | 0:bb348c97df44 | 724 | { |
lypinator | 0:bb348c97df44 | 725 | Device->PCR3 |= FSMC_PCR3_ECCEN; |
lypinator | 0:bb348c97df44 | 726 | } |
lypinator | 0:bb348c97df44 | 727 | |
lypinator | 0:bb348c97df44 | 728 | return HAL_OK; |
lypinator | 0:bb348c97df44 | 729 | } |
lypinator | 0:bb348c97df44 | 730 | |
lypinator | 0:bb348c97df44 | 731 | /** |
lypinator | 0:bb348c97df44 | 732 | * @brief Disables dynamically FSMC_NAND ECC feature. |
lypinator | 0:bb348c97df44 | 733 | * @param Device Pointer to NAND device instance |
lypinator | 0:bb348c97df44 | 734 | * @param Bank NAND bank number |
lypinator | 0:bb348c97df44 | 735 | * @retval HAL status |
lypinator | 0:bb348c97df44 | 736 | */ |
lypinator | 0:bb348c97df44 | 737 | HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank) |
lypinator | 0:bb348c97df44 | 738 | { |
lypinator | 0:bb348c97df44 | 739 | /* Disable ECC feature */ |
lypinator | 0:bb348c97df44 | 740 | if(Bank == FSMC_NAND_BANK2) |
lypinator | 0:bb348c97df44 | 741 | { |
lypinator | 0:bb348c97df44 | 742 | Device->PCR2 &= ~FSMC_PCR2_ECCEN; |
lypinator | 0:bb348c97df44 | 743 | } |
lypinator | 0:bb348c97df44 | 744 | else |
lypinator | 0:bb348c97df44 | 745 | { |
lypinator | 0:bb348c97df44 | 746 | Device->PCR3 &= ~FSMC_PCR3_ECCEN; |
lypinator | 0:bb348c97df44 | 747 | } |
lypinator | 0:bb348c97df44 | 748 | |
lypinator | 0:bb348c97df44 | 749 | return HAL_OK; |
lypinator | 0:bb348c97df44 | 750 | } |
lypinator | 0:bb348c97df44 | 751 | |
lypinator | 0:bb348c97df44 | 752 | /** |
lypinator | 0:bb348c97df44 | 753 | * @brief Disables dynamically FSMC_NAND ECC feature. |
lypinator | 0:bb348c97df44 | 754 | * @param Device Pointer to NAND device instance |
lypinator | 0:bb348c97df44 | 755 | * @param ECCval Pointer to ECC value |
lypinator | 0:bb348c97df44 | 756 | * @param Bank NAND bank number |
lypinator | 0:bb348c97df44 | 757 | * @param Timeout Timeout wait value |
lypinator | 0:bb348c97df44 | 758 | * @retval HAL status |
lypinator | 0:bb348c97df44 | 759 | */ |
lypinator | 0:bb348c97df44 | 760 | HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout) |
lypinator | 0:bb348c97df44 | 761 | { |
lypinator | 0:bb348c97df44 | 762 | uint32_t tickstart = 0U; |
lypinator | 0:bb348c97df44 | 763 | |
lypinator | 0:bb348c97df44 | 764 | /* Check the parameters */ |
lypinator | 0:bb348c97df44 | 765 | assert_param(IS_FSMC_NAND_DEVICE(Device)); |
lypinator | 0:bb348c97df44 | 766 | assert_param(IS_FSMC_NAND_BANK(Bank)); |
lypinator | 0:bb348c97df44 | 767 | |
lypinator | 0:bb348c97df44 | 768 | /* Get tick */ |
lypinator | 0:bb348c97df44 | 769 | tickstart = HAL_GetTick(); |
lypinator | 0:bb348c97df44 | 770 | |
lypinator | 0:bb348c97df44 | 771 | /* Wait until FIFO is empty */ |
lypinator | 0:bb348c97df44 | 772 | while(__FSMC_NAND_GET_FLAG(Device, Bank, FSMC_FLAG_FEMPT) == RESET) |
lypinator | 0:bb348c97df44 | 773 | { |
lypinator | 0:bb348c97df44 | 774 | /* Check for the Timeout */ |
lypinator | 0:bb348c97df44 | 775 | if(Timeout != HAL_MAX_DELAY) |
lypinator | 0:bb348c97df44 | 776 | { |
lypinator | 0:bb348c97df44 | 777 | if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) |
lypinator | 0:bb348c97df44 | 778 | { |
lypinator | 0:bb348c97df44 | 779 | return HAL_TIMEOUT; |
lypinator | 0:bb348c97df44 | 780 | } |
lypinator | 0:bb348c97df44 | 781 | } |
lypinator | 0:bb348c97df44 | 782 | } |
lypinator | 0:bb348c97df44 | 783 | |
lypinator | 0:bb348c97df44 | 784 | if(Bank == FSMC_NAND_BANK2) |
lypinator | 0:bb348c97df44 | 785 | { |
lypinator | 0:bb348c97df44 | 786 | /* Get the ECCR2 register value */ |
lypinator | 0:bb348c97df44 | 787 | *ECCval = (uint32_t)Device->ECCR2; |
lypinator | 0:bb348c97df44 | 788 | } |
lypinator | 0:bb348c97df44 | 789 | else |
lypinator | 0:bb348c97df44 | 790 | { |
lypinator | 0:bb348c97df44 | 791 | /* Get the ECCR3 register value */ |
lypinator | 0:bb348c97df44 | 792 | *ECCval = (uint32_t)Device->ECCR3; |
lypinator | 0:bb348c97df44 | 793 | } |
lypinator | 0:bb348c97df44 | 794 | |
lypinator | 0:bb348c97df44 | 795 | return HAL_OK; |
lypinator | 0:bb348c97df44 | 796 | } |
lypinator | 0:bb348c97df44 | 797 | |
lypinator | 0:bb348c97df44 | 798 | /** |
lypinator | 0:bb348c97df44 | 799 | * @} |
lypinator | 0:bb348c97df44 | 800 | */ |
lypinator | 0:bb348c97df44 | 801 | |
lypinator | 0:bb348c97df44 | 802 | /** |
lypinator | 0:bb348c97df44 | 803 | * @} |
lypinator | 0:bb348c97df44 | 804 | */ |
lypinator | 0:bb348c97df44 | 805 | |
lypinator | 0:bb348c97df44 | 806 | /** @addtogroup FSMC_LL_PCCARD |
lypinator | 0:bb348c97df44 | 807 | * @brief PCCARD Controller functions |
lypinator | 0:bb348c97df44 | 808 | * |
lypinator | 0:bb348c97df44 | 809 | @verbatim |
lypinator | 0:bb348c97df44 | 810 | ============================================================================== |
lypinator | 0:bb348c97df44 | 811 | ##### How to use PCCARD device driver ##### |
lypinator | 0:bb348c97df44 | 812 | ============================================================================== |
lypinator | 0:bb348c97df44 | 813 | [..] |
lypinator | 0:bb348c97df44 | 814 | This driver contains a set of APIs to interface with the FSMC PCCARD bank in order |
lypinator | 0:bb348c97df44 | 815 | to run the PCCARD/compact flash external devices. |
lypinator | 0:bb348c97df44 | 816 | |
lypinator | 0:bb348c97df44 | 817 | (+) FSMC PCCARD bank reset using the function FSMC_PCCARD_DeInit() |
lypinator | 0:bb348c97df44 | 818 | (+) FSMC PCCARD bank control configuration using the function FSMC_PCCARD_Init() |
lypinator | 0:bb348c97df44 | 819 | (+) FSMC PCCARD bank common space timing configuration using the function |
lypinator | 0:bb348c97df44 | 820 | FSMC_PCCARD_CommonSpace_Timing_Init() |
lypinator | 0:bb348c97df44 | 821 | (+) FSMC PCCARD bank attribute space timing configuration using the function |
lypinator | 0:bb348c97df44 | 822 | FSMC_PCCARD_AttributeSpace_Timing_Init() |
lypinator | 0:bb348c97df44 | 823 | (+) FSMC PCCARD bank IO space timing configuration using the function |
lypinator | 0:bb348c97df44 | 824 | FSMC_PCCARD_IOSpace_Timing_Init() |
lypinator | 0:bb348c97df44 | 825 | |
lypinator | 0:bb348c97df44 | 826 | @endverbatim |
lypinator | 0:bb348c97df44 | 827 | * @{ |
lypinator | 0:bb348c97df44 | 828 | */ |
lypinator | 0:bb348c97df44 | 829 | |
lypinator | 0:bb348c97df44 | 830 | /** @addtogroup FSMC_LL_PCCARD_Private_Functions_Group1 |
lypinator | 0:bb348c97df44 | 831 | * @brief Initialization and Configuration functions |
lypinator | 0:bb348c97df44 | 832 | * |
lypinator | 0:bb348c97df44 | 833 | @verbatim |
lypinator | 0:bb348c97df44 | 834 | ============================================================================== |
lypinator | 0:bb348c97df44 | 835 | ##### Initialization and de_initialization functions ##### |
lypinator | 0:bb348c97df44 | 836 | ============================================================================== |
lypinator | 0:bb348c97df44 | 837 | [..] |
lypinator | 0:bb348c97df44 | 838 | This section provides functions allowing to: |
lypinator | 0:bb348c97df44 | 839 | (+) Initialize and configure the FSMC PCCARD interface |
lypinator | 0:bb348c97df44 | 840 | (+) De-initialize the FSMC PCCARD interface |
lypinator | 0:bb348c97df44 | 841 | (+) Configure the FSMC clock and associated GPIOs |
lypinator | 0:bb348c97df44 | 842 | |
lypinator | 0:bb348c97df44 | 843 | @endverbatim |
lypinator | 0:bb348c97df44 | 844 | * @{ |
lypinator | 0:bb348c97df44 | 845 | */ |
lypinator | 0:bb348c97df44 | 846 | |
lypinator | 0:bb348c97df44 | 847 | /** |
lypinator | 0:bb348c97df44 | 848 | * @brief Initializes the FSMC_PCCARD device according to the specified |
lypinator | 0:bb348c97df44 | 849 | * control parameters in the FSMC_PCCARD_HandleTypeDef |
lypinator | 0:bb348c97df44 | 850 | * @param Device Pointer to PCCARD device instance |
lypinator | 0:bb348c97df44 | 851 | * @param Init Pointer to PCCARD Initialization structure |
lypinator | 0:bb348c97df44 | 852 | * @retval HAL status |
lypinator | 0:bb348c97df44 | 853 | */ |
lypinator | 0:bb348c97df44 | 854 | HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_InitTypeDef *Init) |
lypinator | 0:bb348c97df44 | 855 | { |
lypinator | 0:bb348c97df44 | 856 | uint32_t tmpr = 0U; |
lypinator | 0:bb348c97df44 | 857 | |
lypinator | 0:bb348c97df44 | 858 | /* Check the parameters */ |
lypinator | 0:bb348c97df44 | 859 | assert_param(IS_FSMC_WAIT_FEATURE(Init->Waitfeature)); |
lypinator | 0:bb348c97df44 | 860 | assert_param(IS_FSMC_TCLR_TIME(Init->TCLRSetupTime)); |
lypinator | 0:bb348c97df44 | 861 | assert_param(IS_FSMC_TAR_TIME(Init->TARSetupTime)); |
lypinator | 0:bb348c97df44 | 862 | |
lypinator | 0:bb348c97df44 | 863 | /* Get PCCARD control register value */ |
lypinator | 0:bb348c97df44 | 864 | tmpr = Device->PCR4; |
lypinator | 0:bb348c97df44 | 865 | |
lypinator | 0:bb348c97df44 | 866 | /* Clear TAR, TCLR, PWAITEN and PWID bits */ |
lypinator | 0:bb348c97df44 | 867 | tmpr &= ((uint32_t)~(FSMC_PCR4_TAR | FSMC_PCR4_TCLR | FSMC_PCR4_PWAITEN | \ |
lypinator | 0:bb348c97df44 | 868 | FSMC_PCR4_PWID | FSMC_PCR4_PTYP)); |
lypinator | 0:bb348c97df44 | 869 | |
lypinator | 0:bb348c97df44 | 870 | /* Set FSMC_PCCARD device control parameters */ |
lypinator | 0:bb348c97df44 | 871 | tmpr |= (uint32_t)(Init->Waitfeature |\ |
lypinator | 0:bb348c97df44 | 872 | FSMC_NAND_PCC_MEM_BUS_WIDTH_16 |\ |
lypinator | 0:bb348c97df44 | 873 | (Init->TCLRSetupTime << 9U) |\ |
lypinator | 0:bb348c97df44 | 874 | (Init->TARSetupTime << 13U)); |
lypinator | 0:bb348c97df44 | 875 | |
lypinator | 0:bb348c97df44 | 876 | Device->PCR4 = tmpr; |
lypinator | 0:bb348c97df44 | 877 | |
lypinator | 0:bb348c97df44 | 878 | return HAL_OK; |
lypinator | 0:bb348c97df44 | 879 | } |
lypinator | 0:bb348c97df44 | 880 | |
lypinator | 0:bb348c97df44 | 881 | /** |
lypinator | 0:bb348c97df44 | 882 | * @brief Initializes the FSMC_PCCARD Common space Timing according to the specified |
lypinator | 0:bb348c97df44 | 883 | * parameters in the FSMC_NAND_PCC_TimingTypeDef |
lypinator | 0:bb348c97df44 | 884 | * @param Device Pointer to PCCARD device instance |
lypinator | 0:bb348c97df44 | 885 | * @param Timing Pointer to PCCARD timing structure |
lypinator | 0:bb348c97df44 | 886 | * @retval HAL status |
lypinator | 0:bb348c97df44 | 887 | */ |
lypinator | 0:bb348c97df44 | 888 | HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing) |
lypinator | 0:bb348c97df44 | 889 | { |
lypinator | 0:bb348c97df44 | 890 | uint32_t tmpr = 0U; |
lypinator | 0:bb348c97df44 | 891 | |
lypinator | 0:bb348c97df44 | 892 | /* Check the parameters */ |
lypinator | 0:bb348c97df44 | 893 | assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime)); |
lypinator | 0:bb348c97df44 | 894 | assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime)); |
lypinator | 0:bb348c97df44 | 895 | assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime)); |
lypinator | 0:bb348c97df44 | 896 | assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime)); |
lypinator | 0:bb348c97df44 | 897 | |
lypinator | 0:bb348c97df44 | 898 | /* Get PCCARD common space timing register value */ |
lypinator | 0:bb348c97df44 | 899 | tmpr = Device->PMEM4; |
lypinator | 0:bb348c97df44 | 900 | |
lypinator | 0:bb348c97df44 | 901 | /* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */ |
lypinator | 0:bb348c97df44 | 902 | tmpr &= ((uint32_t)~(FSMC_PMEM4_MEMSET4 | FSMC_PMEM4_MEMWAIT4 | FSMC_PMEM4_MEMHOLD4 | \ |
lypinator | 0:bb348c97df44 | 903 | FSMC_PMEM4_MEMHIZ4)); |
lypinator | 0:bb348c97df44 | 904 | /* Set PCCARD timing parameters */ |
lypinator | 0:bb348c97df44 | 905 | tmpr |= (uint32_t)((Timing->SetupTime |\ |
lypinator | 0:bb348c97df44 | 906 | ((Timing->WaitSetupTime) << 8U) |\ |
lypinator | 0:bb348c97df44 | 907 | (Timing->HoldSetupTime) << 16U) |\ |
lypinator | 0:bb348c97df44 | 908 | ((Timing->HiZSetupTime) << 24U)); |
lypinator | 0:bb348c97df44 | 909 | |
lypinator | 0:bb348c97df44 | 910 | Device->PMEM4 = tmpr; |
lypinator | 0:bb348c97df44 | 911 | |
lypinator | 0:bb348c97df44 | 912 | return HAL_OK; |
lypinator | 0:bb348c97df44 | 913 | } |
lypinator | 0:bb348c97df44 | 914 | |
lypinator | 0:bb348c97df44 | 915 | /** |
lypinator | 0:bb348c97df44 | 916 | * @brief Initializes the FSMC_PCCARD Attribute space Timing according to the specified |
lypinator | 0:bb348c97df44 | 917 | * parameters in the FSMC_NAND_PCC_TimingTypeDef |
lypinator | 0:bb348c97df44 | 918 | * @param Device Pointer to PCCARD device instance |
lypinator | 0:bb348c97df44 | 919 | * @param Timing Pointer to PCCARD timing structure |
lypinator | 0:bb348c97df44 | 920 | * @retval HAL status |
lypinator | 0:bb348c97df44 | 921 | */ |
lypinator | 0:bb348c97df44 | 922 | HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing) |
lypinator | 0:bb348c97df44 | 923 | { |
lypinator | 0:bb348c97df44 | 924 | uint32_t tmpr = 0U; |
lypinator | 0:bb348c97df44 | 925 | |
lypinator | 0:bb348c97df44 | 926 | /* Check the parameters */ |
lypinator | 0:bb348c97df44 | 927 | assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime)); |
lypinator | 0:bb348c97df44 | 928 | assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime)); |
lypinator | 0:bb348c97df44 | 929 | assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime)); |
lypinator | 0:bb348c97df44 | 930 | assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime)); |
lypinator | 0:bb348c97df44 | 931 | |
lypinator | 0:bb348c97df44 | 932 | /* Get PCCARD timing parameters */ |
lypinator | 0:bb348c97df44 | 933 | tmpr = Device->PATT4; |
lypinator | 0:bb348c97df44 | 934 | |
lypinator | 0:bb348c97df44 | 935 | /* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */ |
lypinator | 0:bb348c97df44 | 936 | tmpr &= ((uint32_t)~(FSMC_PATT4_ATTSET4 | FSMC_PATT4_ATTWAIT4 | FSMC_PATT4_ATTHOLD4 | \ |
lypinator | 0:bb348c97df44 | 937 | FSMC_PATT4_ATTHIZ4)); |
lypinator | 0:bb348c97df44 | 938 | |
lypinator | 0:bb348c97df44 | 939 | /* Set PCCARD timing parameters */ |
lypinator | 0:bb348c97df44 | 940 | tmpr |= (uint32_t)(Timing->SetupTime |\ |
lypinator | 0:bb348c97df44 | 941 | ((Timing->WaitSetupTime) << 8U) |\ |
lypinator | 0:bb348c97df44 | 942 | ((Timing->HoldSetupTime) << 16U) |\ |
lypinator | 0:bb348c97df44 | 943 | ((Timing->HiZSetupTime) << 24U)); |
lypinator | 0:bb348c97df44 | 944 | Device->PATT4 = tmpr; |
lypinator | 0:bb348c97df44 | 945 | |
lypinator | 0:bb348c97df44 | 946 | return HAL_OK; |
lypinator | 0:bb348c97df44 | 947 | } |
lypinator | 0:bb348c97df44 | 948 | |
lypinator | 0:bb348c97df44 | 949 | /** |
lypinator | 0:bb348c97df44 | 950 | * @brief Initializes the FSMC_PCCARD IO space Timing according to the specified |
lypinator | 0:bb348c97df44 | 951 | * parameters in the FSMC_NAND_PCC_TimingTypeDef |
lypinator | 0:bb348c97df44 | 952 | * @param Device Pointer to PCCARD device instance |
lypinator | 0:bb348c97df44 | 953 | * @param Timing Pointer to PCCARD timing structure |
lypinator | 0:bb348c97df44 | 954 | * @retval HAL status |
lypinator | 0:bb348c97df44 | 955 | */ |
lypinator | 0:bb348c97df44 | 956 | HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing) |
lypinator | 0:bb348c97df44 | 957 | { |
lypinator | 0:bb348c97df44 | 958 | uint32_t tmpr = 0U; |
lypinator | 0:bb348c97df44 | 959 | |
lypinator | 0:bb348c97df44 | 960 | /* Check the parameters */ |
lypinator | 0:bb348c97df44 | 961 | assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime)); |
lypinator | 0:bb348c97df44 | 962 | assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime)); |
lypinator | 0:bb348c97df44 | 963 | assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime)); |
lypinator | 0:bb348c97df44 | 964 | assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime)); |
lypinator | 0:bb348c97df44 | 965 | |
lypinator | 0:bb348c97df44 | 966 | /* Get FSMC_PCCARD device timing parameters */ |
lypinator | 0:bb348c97df44 | 967 | tmpr = Device->PIO4; |
lypinator | 0:bb348c97df44 | 968 | |
lypinator | 0:bb348c97df44 | 969 | /* Clear IOSET4, IOWAIT4, IOHOLD4 and IOHIZ4 bits */ |
lypinator | 0:bb348c97df44 | 970 | tmpr &= ((uint32_t)~(FSMC_PIO4_IOSET4 | FSMC_PIO4_IOWAIT4 | FSMC_PIO4_IOHOLD4 | \ |
lypinator | 0:bb348c97df44 | 971 | FSMC_PIO4_IOHIZ4)); |
lypinator | 0:bb348c97df44 | 972 | |
lypinator | 0:bb348c97df44 | 973 | /* Set FSMC_PCCARD device timing parameters */ |
lypinator | 0:bb348c97df44 | 974 | tmpr |= (uint32_t)(Timing->SetupTime |\ |
lypinator | 0:bb348c97df44 | 975 | ((Timing->WaitSetupTime) << 8U) |\ |
lypinator | 0:bb348c97df44 | 976 | ((Timing->HoldSetupTime) << 16U) |\ |
lypinator | 0:bb348c97df44 | 977 | ((Timing->HiZSetupTime) << 24U)); |
lypinator | 0:bb348c97df44 | 978 | |
lypinator | 0:bb348c97df44 | 979 | Device->PIO4 = tmpr; |
lypinator | 0:bb348c97df44 | 980 | |
lypinator | 0:bb348c97df44 | 981 | return HAL_OK; |
lypinator | 0:bb348c97df44 | 982 | } |
lypinator | 0:bb348c97df44 | 983 | |
lypinator | 0:bb348c97df44 | 984 | /** |
lypinator | 0:bb348c97df44 | 985 | * @brief DeInitializes the FSMC_PCCARD device |
lypinator | 0:bb348c97df44 | 986 | * @param Device Pointer to PCCARD device instance |
lypinator | 0:bb348c97df44 | 987 | * @retval HAL status |
lypinator | 0:bb348c97df44 | 988 | */ |
lypinator | 0:bb348c97df44 | 989 | HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device) |
lypinator | 0:bb348c97df44 | 990 | { |
lypinator | 0:bb348c97df44 | 991 | /* Disable the FSMC_PCCARD device */ |
lypinator | 0:bb348c97df44 | 992 | __FSMC_PCCARD_DISABLE(Device); |
lypinator | 0:bb348c97df44 | 993 | |
lypinator | 0:bb348c97df44 | 994 | /* De-initialize the FSMC_PCCARD device */ |
lypinator | 0:bb348c97df44 | 995 | Device->PCR4 = 0x00000018U; |
lypinator | 0:bb348c97df44 | 996 | Device->SR4 = 0x00000000U; |
lypinator | 0:bb348c97df44 | 997 | Device->PMEM4 = 0xFCFCFCFCU; |
lypinator | 0:bb348c97df44 | 998 | Device->PATT4 = 0xFCFCFCFCU; |
lypinator | 0:bb348c97df44 | 999 | Device->PIO4 = 0xFCFCFCFCU; |
lypinator | 0:bb348c97df44 | 1000 | |
lypinator | 0:bb348c97df44 | 1001 | return HAL_OK; |
lypinator | 0:bb348c97df44 | 1002 | } |
lypinator | 0:bb348c97df44 | 1003 | /** |
lypinator | 0:bb348c97df44 | 1004 | * @} |
lypinator | 0:bb348c97df44 | 1005 | */ |
lypinator | 0:bb348c97df44 | 1006 | |
lypinator | 0:bb348c97df44 | 1007 | /** |
lypinator | 0:bb348c97df44 | 1008 | * @} |
lypinator | 0:bb348c97df44 | 1009 | */ |
lypinator | 0:bb348c97df44 | 1010 | #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ |
lypinator | 0:bb348c97df44 | 1011 | |
lypinator | 0:bb348c97df44 | 1012 | /** |
lypinator | 0:bb348c97df44 | 1013 | * @} |
lypinator | 0:bb348c97df44 | 1014 | */ |
lypinator | 0:bb348c97df44 | 1015 | #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx || STM32F413xx || STM32F423xx */ |
lypinator | 0:bb348c97df44 | 1016 | #endif /* HAL_SRAM_MODULE_ENABLED || HAL_NOR_MODULE_ENABLED || HAL_NAND_MODULE_ENABLED || HAL_PCCARD_MODULE_ENABLED */ |
lypinator | 0:bb348c97df44 | 1017 | |
lypinator | 0:bb348c97df44 | 1018 | /** |
lypinator | 0:bb348c97df44 | 1019 | * @} |
lypinator | 0:bb348c97df44 | 1020 | */ |
lypinator | 0:bb348c97df44 | 1021 | |
lypinator | 0:bb348c97df44 | 1022 | /** |
lypinator | 0:bb348c97df44 | 1023 | * @} |
lypinator | 0:bb348c97df44 | 1024 | */ |
lypinator | 0:bb348c97df44 | 1025 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |