Initial commit
mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_adc.c@0:bb348c97df44, 2020-09-16 (annotated)
- Committer:
- lypinator
- Date:
- Wed Sep 16 01:11:49 2020 +0000
- Revision:
- 0:bb348c97df44
Added PWM
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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lypinator | 0:bb348c97df44 | 1 | /** |
lypinator | 0:bb348c97df44 | 2 | ****************************************************************************** |
lypinator | 0:bb348c97df44 | 3 | * @file stm32f4xx_ll_adc.c |
lypinator | 0:bb348c97df44 | 4 | * @author MCD Application Team |
lypinator | 0:bb348c97df44 | 5 | * @brief ADC LL module driver |
lypinator | 0:bb348c97df44 | 6 | ****************************************************************************** |
lypinator | 0:bb348c97df44 | 7 | * @attention |
lypinator | 0:bb348c97df44 | 8 | * |
lypinator | 0:bb348c97df44 | 9 | * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> |
lypinator | 0:bb348c97df44 | 10 | * |
lypinator | 0:bb348c97df44 | 11 | * Redistribution and use in source and binary forms, with or without modification, |
lypinator | 0:bb348c97df44 | 12 | * are permitted provided that the following conditions are met: |
lypinator | 0:bb348c97df44 | 13 | * 1. Redistributions of source code must retain the above copyright notice, |
lypinator | 0:bb348c97df44 | 14 | * this list of conditions and the following disclaimer. |
lypinator | 0:bb348c97df44 | 15 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
lypinator | 0:bb348c97df44 | 16 | * this list of conditions and the following disclaimer in the documentation |
lypinator | 0:bb348c97df44 | 17 | * and/or other materials provided with the distribution. |
lypinator | 0:bb348c97df44 | 18 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
lypinator | 0:bb348c97df44 | 19 | * may be used to endorse or promote products derived from this software |
lypinator | 0:bb348c97df44 | 20 | * without specific prior written permission. |
lypinator | 0:bb348c97df44 | 21 | * |
lypinator | 0:bb348c97df44 | 22 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
lypinator | 0:bb348c97df44 | 23 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
lypinator | 0:bb348c97df44 | 24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
lypinator | 0:bb348c97df44 | 25 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
lypinator | 0:bb348c97df44 | 26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
lypinator | 0:bb348c97df44 | 27 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
lypinator | 0:bb348c97df44 | 28 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
lypinator | 0:bb348c97df44 | 29 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
lypinator | 0:bb348c97df44 | 30 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
lypinator | 0:bb348c97df44 | 31 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
lypinator | 0:bb348c97df44 | 32 | * |
lypinator | 0:bb348c97df44 | 33 | ****************************************************************************** |
lypinator | 0:bb348c97df44 | 34 | */ |
lypinator | 0:bb348c97df44 | 35 | #if defined(USE_FULL_LL_DRIVER) |
lypinator | 0:bb348c97df44 | 36 | |
lypinator | 0:bb348c97df44 | 37 | /* Includes ------------------------------------------------------------------*/ |
lypinator | 0:bb348c97df44 | 38 | #include "stm32f4xx_ll_adc.h" |
lypinator | 0:bb348c97df44 | 39 | #include "stm32f4xx_ll_bus.h" |
lypinator | 0:bb348c97df44 | 40 | |
lypinator | 0:bb348c97df44 | 41 | #ifdef USE_FULL_ASSERT |
lypinator | 0:bb348c97df44 | 42 | #include "stm32_assert.h" |
lypinator | 0:bb348c97df44 | 43 | #else |
lypinator | 0:bb348c97df44 | 44 | #define assert_param(expr) ((void)0U) |
lypinator | 0:bb348c97df44 | 45 | #endif |
lypinator | 0:bb348c97df44 | 46 | |
lypinator | 0:bb348c97df44 | 47 | /** @addtogroup STM32F4xx_LL_Driver |
lypinator | 0:bb348c97df44 | 48 | * @{ |
lypinator | 0:bb348c97df44 | 49 | */ |
lypinator | 0:bb348c97df44 | 50 | |
lypinator | 0:bb348c97df44 | 51 | #if defined (ADC1) || defined (ADC2) || defined (ADC3) |
lypinator | 0:bb348c97df44 | 52 | |
lypinator | 0:bb348c97df44 | 53 | /** @addtogroup ADC_LL ADC |
lypinator | 0:bb348c97df44 | 54 | * @{ |
lypinator | 0:bb348c97df44 | 55 | */ |
lypinator | 0:bb348c97df44 | 56 | |
lypinator | 0:bb348c97df44 | 57 | /* Private types -------------------------------------------------------------*/ |
lypinator | 0:bb348c97df44 | 58 | /* Private variables ---------------------------------------------------------*/ |
lypinator | 0:bb348c97df44 | 59 | /* Private constants ---------------------------------------------------------*/ |
lypinator | 0:bb348c97df44 | 60 | /* Private macros ------------------------------------------------------------*/ |
lypinator | 0:bb348c97df44 | 61 | |
lypinator | 0:bb348c97df44 | 62 | /** @addtogroup ADC_LL_Private_Macros |
lypinator | 0:bb348c97df44 | 63 | * @{ |
lypinator | 0:bb348c97df44 | 64 | */ |
lypinator | 0:bb348c97df44 | 65 | |
lypinator | 0:bb348c97df44 | 66 | /* Check of parameters for configuration of ADC hierarchical scope: */ |
lypinator | 0:bb348c97df44 | 67 | /* common to several ADC instances. */ |
lypinator | 0:bb348c97df44 | 68 | #define IS_LL_ADC_COMMON_CLOCK(__CLOCK__) \ |
lypinator | 0:bb348c97df44 | 69 | ( ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV2) \ |
lypinator | 0:bb348c97df44 | 70 | || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV4) \ |
lypinator | 0:bb348c97df44 | 71 | || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV6) \ |
lypinator | 0:bb348c97df44 | 72 | || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV8) \ |
lypinator | 0:bb348c97df44 | 73 | ) |
lypinator | 0:bb348c97df44 | 74 | |
lypinator | 0:bb348c97df44 | 75 | /* Check of parameters for configuration of ADC hierarchical scope: */ |
lypinator | 0:bb348c97df44 | 76 | /* ADC instance. */ |
lypinator | 0:bb348c97df44 | 77 | #define IS_LL_ADC_RESOLUTION(__RESOLUTION__) \ |
lypinator | 0:bb348c97df44 | 78 | ( ((__RESOLUTION__) == LL_ADC_RESOLUTION_12B) \ |
lypinator | 0:bb348c97df44 | 79 | || ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B) \ |
lypinator | 0:bb348c97df44 | 80 | || ((__RESOLUTION__) == LL_ADC_RESOLUTION_8B) \ |
lypinator | 0:bb348c97df44 | 81 | || ((__RESOLUTION__) == LL_ADC_RESOLUTION_6B) \ |
lypinator | 0:bb348c97df44 | 82 | ) |
lypinator | 0:bb348c97df44 | 83 | |
lypinator | 0:bb348c97df44 | 84 | #define IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__) \ |
lypinator | 0:bb348c97df44 | 85 | ( ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT) \ |
lypinator | 0:bb348c97df44 | 86 | || ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT) \ |
lypinator | 0:bb348c97df44 | 87 | ) |
lypinator | 0:bb348c97df44 | 88 | |
lypinator | 0:bb348c97df44 | 89 | #define IS_LL_ADC_SCAN_SELECTION(__SCAN_SELECTION__) \ |
lypinator | 0:bb348c97df44 | 90 | ( ((__SCAN_SELECTION__) == LL_ADC_SEQ_SCAN_DISABLE) \ |
lypinator | 0:bb348c97df44 | 91 | || ((__SCAN_SELECTION__) == LL_ADC_SEQ_SCAN_ENABLE) \ |
lypinator | 0:bb348c97df44 | 92 | ) |
lypinator | 0:bb348c97df44 | 93 | |
lypinator | 0:bb348c97df44 | 94 | #define IS_LL_ADC_SEQ_SCAN_MODE(__SEQ_SCAN_MODE__) \ |
lypinator | 0:bb348c97df44 | 95 | ( ((__SCAN_MODE__) == LL_ADC_SEQ_SCAN_DISABLE) \ |
lypinator | 0:bb348c97df44 | 96 | || ((__SCAN_MODE__) == LL_ADC_SEQ_SCAN_ENABLE) \ |
lypinator | 0:bb348c97df44 | 97 | ) |
lypinator | 0:bb348c97df44 | 98 | |
lypinator | 0:bb348c97df44 | 99 | /* Check of parameters for configuration of ADC hierarchical scope: */ |
lypinator | 0:bb348c97df44 | 100 | /* ADC group regular */ |
lypinator | 0:bb348c97df44 | 101 | #define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \ |
lypinator | 0:bb348c97df44 | 102 | ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \ |
lypinator | 0:bb348c97df44 | 103 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \ |
lypinator | 0:bb348c97df44 | 104 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \ |
lypinator | 0:bb348c97df44 | 105 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \ |
lypinator | 0:bb348c97df44 | 106 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \ |
lypinator | 0:bb348c97df44 | 107 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH3) \ |
lypinator | 0:bb348c97df44 | 108 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH4) \ |
lypinator | 0:bb348c97df44 | 109 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \ |
lypinator | 0:bb348c97df44 | 110 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH1) \ |
lypinator | 0:bb348c97df44 | 111 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \ |
lypinator | 0:bb348c97df44 | 112 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \ |
lypinator | 0:bb348c97df44 | 113 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM5_CH1) \ |
lypinator | 0:bb348c97df44 | 114 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM5_CH2) \ |
lypinator | 0:bb348c97df44 | 115 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM5_CH3) \ |
lypinator | 0:bb348c97df44 | 116 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_CH1) \ |
lypinator | 0:bb348c97df44 | 117 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO) \ |
lypinator | 0:bb348c97df44 | 118 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \ |
lypinator | 0:bb348c97df44 | 119 | ) |
lypinator | 0:bb348c97df44 | 120 | #define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \ |
lypinator | 0:bb348c97df44 | 121 | ( ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \ |
lypinator | 0:bb348c97df44 | 122 | || ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS) \ |
lypinator | 0:bb348c97df44 | 123 | ) |
lypinator | 0:bb348c97df44 | 124 | |
lypinator | 0:bb348c97df44 | 125 | #define IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__) \ |
lypinator | 0:bb348c97df44 | 126 | ( ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE) \ |
lypinator | 0:bb348c97df44 | 127 | || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_LIMITED) \ |
lypinator | 0:bb348c97df44 | 128 | || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED) \ |
lypinator | 0:bb348c97df44 | 129 | ) |
lypinator | 0:bb348c97df44 | 130 | |
lypinator | 0:bb348c97df44 | 131 | #define IS_LL_ADC_REG_FLAG_EOC_SELECTION(__REG_FLAG_EOC_SELECTION__) \ |
lypinator | 0:bb348c97df44 | 132 | ( ((__REG_FLAG_EOC_SELECTION__) == LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV) \ |
lypinator | 0:bb348c97df44 | 133 | || ((__REG_FLAG_EOC_SELECTION__) == LL_ADC_REG_FLAG_EOC_UNITARY_CONV) \ |
lypinator | 0:bb348c97df44 | 134 | ) |
lypinator | 0:bb348c97df44 | 135 | |
lypinator | 0:bb348c97df44 | 136 | #define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__) \ |
lypinator | 0:bb348c97df44 | 137 | ( ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE) \ |
lypinator | 0:bb348c97df44 | 138 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS) \ |
lypinator | 0:bb348c97df44 | 139 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS) \ |
lypinator | 0:bb348c97df44 | 140 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS) \ |
lypinator | 0:bb348c97df44 | 141 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS) \ |
lypinator | 0:bb348c97df44 | 142 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS) \ |
lypinator | 0:bb348c97df44 | 143 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS) \ |
lypinator | 0:bb348c97df44 | 144 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS) \ |
lypinator | 0:bb348c97df44 | 145 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS) \ |
lypinator | 0:bb348c97df44 | 146 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS) \ |
lypinator | 0:bb348c97df44 | 147 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS) \ |
lypinator | 0:bb348c97df44 | 148 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS) \ |
lypinator | 0:bb348c97df44 | 149 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS) \ |
lypinator | 0:bb348c97df44 | 150 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS) \ |
lypinator | 0:bb348c97df44 | 151 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS) \ |
lypinator | 0:bb348c97df44 | 152 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS) \ |
lypinator | 0:bb348c97df44 | 153 | ) |
lypinator | 0:bb348c97df44 | 154 | |
lypinator | 0:bb348c97df44 | 155 | #define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \ |
lypinator | 0:bb348c97df44 | 156 | ( ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \ |
lypinator | 0:bb348c97df44 | 157 | || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \ |
lypinator | 0:bb348c97df44 | 158 | || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_2RANKS) \ |
lypinator | 0:bb348c97df44 | 159 | || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_3RANKS) \ |
lypinator | 0:bb348c97df44 | 160 | || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_4RANKS) \ |
lypinator | 0:bb348c97df44 | 161 | || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_5RANKS) \ |
lypinator | 0:bb348c97df44 | 162 | || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_6RANKS) \ |
lypinator | 0:bb348c97df44 | 163 | || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_7RANKS) \ |
lypinator | 0:bb348c97df44 | 164 | || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_8RANKS) \ |
lypinator | 0:bb348c97df44 | 165 | ) |
lypinator | 0:bb348c97df44 | 166 | |
lypinator | 0:bb348c97df44 | 167 | /* Check of parameters for configuration of ADC hierarchical scope: */ |
lypinator | 0:bb348c97df44 | 168 | /* ADC group injected */ |
lypinator | 0:bb348c97df44 | 169 | #define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__) \ |
lypinator | 0:bb348c97df44 | 170 | ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \ |
lypinator | 0:bb348c97df44 | 171 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \ |
lypinator | 0:bb348c97df44 | 172 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \ |
lypinator | 0:bb348c97df44 | 173 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \ |
lypinator | 0:bb348c97df44 | 174 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \ |
lypinator | 0:bb348c97df44 | 175 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH2) \ |
lypinator | 0:bb348c97df44 | 176 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \ |
lypinator | 0:bb348c97df44 | 177 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH1) \ |
lypinator | 0:bb348c97df44 | 178 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH2) \ |
lypinator | 0:bb348c97df44 | 179 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH3) \ |
lypinator | 0:bb348c97df44 | 180 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \ |
lypinator | 0:bb348c97df44 | 181 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM5_CH4) \ |
lypinator | 0:bb348c97df44 | 182 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM5_TRGO) \ |
lypinator | 0:bb348c97df44 | 183 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH2) \ |
lypinator | 0:bb348c97df44 | 184 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH3) \ |
lypinator | 0:bb348c97df44 | 185 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4) \ |
lypinator | 0:bb348c97df44 | 186 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \ |
lypinator | 0:bb348c97df44 | 187 | ) |
lypinator | 0:bb348c97df44 | 188 | |
lypinator | 0:bb348c97df44 | 189 | #define IS_LL_ADC_INJ_TRIG_EXT_EDGE(__INJ_TRIG_EXT_EDGE__) \ |
lypinator | 0:bb348c97df44 | 190 | ( ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISING) \ |
lypinator | 0:bb348c97df44 | 191 | || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_FALLING) \ |
lypinator | 0:bb348c97df44 | 192 | || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISINGFALLING) \ |
lypinator | 0:bb348c97df44 | 193 | ) |
lypinator | 0:bb348c97df44 | 194 | |
lypinator | 0:bb348c97df44 | 195 | #define IS_LL_ADC_INJ_TRIG_AUTO(__INJ_TRIG_AUTO__) \ |
lypinator | 0:bb348c97df44 | 196 | ( ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_INDEPENDENT) \ |
lypinator | 0:bb348c97df44 | 197 | || ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_FROM_GRP_REGULAR) \ |
lypinator | 0:bb348c97df44 | 198 | ) |
lypinator | 0:bb348c97df44 | 199 | |
lypinator | 0:bb348c97df44 | 200 | #define IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(__INJ_SEQ_SCAN_LENGTH__) \ |
lypinator | 0:bb348c97df44 | 201 | ( ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_DISABLE) \ |
lypinator | 0:bb348c97df44 | 202 | || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS) \ |
lypinator | 0:bb348c97df44 | 203 | || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS) \ |
lypinator | 0:bb348c97df44 | 204 | || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS) \ |
lypinator | 0:bb348c97df44 | 205 | ) |
lypinator | 0:bb348c97df44 | 206 | |
lypinator | 0:bb348c97df44 | 207 | #define IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(__INJ_SEQ_DISCONT_MODE__) \ |
lypinator | 0:bb348c97df44 | 208 | ( ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_DISABLE) \ |
lypinator | 0:bb348c97df44 | 209 | || ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_1RANK) \ |
lypinator | 0:bb348c97df44 | 210 | ) |
lypinator | 0:bb348c97df44 | 211 | |
lypinator | 0:bb348c97df44 | 212 | #if defined(ADC_MULTIMODE_SUPPORT) |
lypinator | 0:bb348c97df44 | 213 | /* Check of parameters for configuration of ADC hierarchical scope: */ |
lypinator | 0:bb348c97df44 | 214 | /* multimode. */ |
lypinator | 0:bb348c97df44 | 215 | #if defined(ADC3) |
lypinator | 0:bb348c97df44 | 216 | #define IS_LL_ADC_MULTI_MODE(__MULTI_MODE__) \ |
lypinator | 0:bb348c97df44 | 217 | ( ((__MULTI_MODE__) == LL_ADC_MULTI_INDEPENDENT) \ |
lypinator | 0:bb348c97df44 | 218 | || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIMULT) \ |
lypinator | 0:bb348c97df44 | 219 | || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL) \ |
lypinator | 0:bb348c97df44 | 220 | || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_SIMULT) \ |
lypinator | 0:bb348c97df44 | 221 | || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_ALTERN) \ |
lypinator | 0:bb348c97df44 | 222 | || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) \ |
lypinator | 0:bb348c97df44 | 223 | || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) \ |
lypinator | 0:bb348c97df44 | 224 | || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) \ |
lypinator | 0:bb348c97df44 | 225 | || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_SIM) \ |
lypinator | 0:bb348c97df44 | 226 | || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_ALT) \ |
lypinator | 0:bb348c97df44 | 227 | || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_INJ_SIMULT) \ |
lypinator | 0:bb348c97df44 | 228 | || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_REG_SIMULT) \ |
lypinator | 0:bb348c97df44 | 229 | || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_REG_INTERL) \ |
lypinator | 0:bb348c97df44 | 230 | || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_INJ_ALTERN) \ |
lypinator | 0:bb348c97df44 | 231 | ) |
lypinator | 0:bb348c97df44 | 232 | #else |
lypinator | 0:bb348c97df44 | 233 | #define IS_LL_ADC_MULTI_MODE(__MULTI_MODE__) \ |
lypinator | 0:bb348c97df44 | 234 | ( ((__MULTI_MODE__) == LL_ADC_MULTI_INDEPENDENT) \ |
lypinator | 0:bb348c97df44 | 235 | || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIMULT) \ |
lypinator | 0:bb348c97df44 | 236 | || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL) \ |
lypinator | 0:bb348c97df44 | 237 | || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_SIMULT) \ |
lypinator | 0:bb348c97df44 | 238 | || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_ALTERN) \ |
lypinator | 0:bb348c97df44 | 239 | || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) \ |
lypinator | 0:bb348c97df44 | 240 | || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) \ |
lypinator | 0:bb348c97df44 | 241 | || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) \ |
lypinator | 0:bb348c97df44 | 242 | ) |
lypinator | 0:bb348c97df44 | 243 | #endif |
lypinator | 0:bb348c97df44 | 244 | |
lypinator | 0:bb348c97df44 | 245 | #define IS_LL_ADC_MULTI_DMA_TRANSFER(__MULTI_DMA_TRANSFER__) \ |
lypinator | 0:bb348c97df44 | 246 | ( ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_EACH_ADC) \ |
lypinator | 0:bb348c97df44 | 247 | || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_1) \ |
lypinator | 0:bb348c97df44 | 248 | || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_2) \ |
lypinator | 0:bb348c97df44 | 249 | || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_3) \ |
lypinator | 0:bb348c97df44 | 250 | || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_1) \ |
lypinator | 0:bb348c97df44 | 251 | || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_2) \ |
lypinator | 0:bb348c97df44 | 252 | || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_3) \ |
lypinator | 0:bb348c97df44 | 253 | ) |
lypinator | 0:bb348c97df44 | 254 | |
lypinator | 0:bb348c97df44 | 255 | #define IS_LL_ADC_MULTI_TWOSMP_DELAY(__MULTI_TWOSMP_DELAY__) \ |
lypinator | 0:bb348c97df44 | 256 | ( ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES) \ |
lypinator | 0:bb348c97df44 | 257 | || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES) \ |
lypinator | 0:bb348c97df44 | 258 | || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES) \ |
lypinator | 0:bb348c97df44 | 259 | || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES) \ |
lypinator | 0:bb348c97df44 | 260 | || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES) \ |
lypinator | 0:bb348c97df44 | 261 | || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES) \ |
lypinator | 0:bb348c97df44 | 262 | || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES) \ |
lypinator | 0:bb348c97df44 | 263 | || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES) \ |
lypinator | 0:bb348c97df44 | 264 | || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES) \ |
lypinator | 0:bb348c97df44 | 265 | || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES) \ |
lypinator | 0:bb348c97df44 | 266 | || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES) \ |
lypinator | 0:bb348c97df44 | 267 | || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_16CYCLES) \ |
lypinator | 0:bb348c97df44 | 268 | || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_17CYCLES) \ |
lypinator | 0:bb348c97df44 | 269 | || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_18CYCLES) \ |
lypinator | 0:bb348c97df44 | 270 | || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_19CYCLES) \ |
lypinator | 0:bb348c97df44 | 271 | || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_20CYCLES) \ |
lypinator | 0:bb348c97df44 | 272 | ) |
lypinator | 0:bb348c97df44 | 273 | |
lypinator | 0:bb348c97df44 | 274 | #define IS_LL_ADC_MULTI_MASTER_SLAVE(__MULTI_MASTER_SLAVE__) \ |
lypinator | 0:bb348c97df44 | 275 | ( ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER) \ |
lypinator | 0:bb348c97df44 | 276 | || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_SLAVE) \ |
lypinator | 0:bb348c97df44 | 277 | || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER_SLAVE) \ |
lypinator | 0:bb348c97df44 | 278 | ) |
lypinator | 0:bb348c97df44 | 279 | |
lypinator | 0:bb348c97df44 | 280 | #endif /* ADC_MULTIMODE_SUPPORT */ |
lypinator | 0:bb348c97df44 | 281 | /** |
lypinator | 0:bb348c97df44 | 282 | * @} |
lypinator | 0:bb348c97df44 | 283 | */ |
lypinator | 0:bb348c97df44 | 284 | |
lypinator | 0:bb348c97df44 | 285 | |
lypinator | 0:bb348c97df44 | 286 | /* Private function prototypes -----------------------------------------------*/ |
lypinator | 0:bb348c97df44 | 287 | |
lypinator | 0:bb348c97df44 | 288 | /* Exported functions --------------------------------------------------------*/ |
lypinator | 0:bb348c97df44 | 289 | /** @addtogroup ADC_LL_Exported_Functions |
lypinator | 0:bb348c97df44 | 290 | * @{ |
lypinator | 0:bb348c97df44 | 291 | */ |
lypinator | 0:bb348c97df44 | 292 | |
lypinator | 0:bb348c97df44 | 293 | /** @addtogroup ADC_LL_EF_Init |
lypinator | 0:bb348c97df44 | 294 | * @{ |
lypinator | 0:bb348c97df44 | 295 | */ |
lypinator | 0:bb348c97df44 | 296 | |
lypinator | 0:bb348c97df44 | 297 | /** |
lypinator | 0:bb348c97df44 | 298 | * @brief De-initialize registers of all ADC instances belonging to |
lypinator | 0:bb348c97df44 | 299 | * the same ADC common instance to their default reset values. |
lypinator | 0:bb348c97df44 | 300 | * @param ADCxy_COMMON ADC common instance |
lypinator | 0:bb348c97df44 | 301 | * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) |
lypinator | 0:bb348c97df44 | 302 | * @retval An ErrorStatus enumeration value: |
lypinator | 0:bb348c97df44 | 303 | * - SUCCESS: ADC common registers are de-initialized |
lypinator | 0:bb348c97df44 | 304 | * - ERROR: not applicable |
lypinator | 0:bb348c97df44 | 305 | */ |
lypinator | 0:bb348c97df44 | 306 | ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON) |
lypinator | 0:bb348c97df44 | 307 | { |
lypinator | 0:bb348c97df44 | 308 | /* Check the parameters */ |
lypinator | 0:bb348c97df44 | 309 | assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON)); |
lypinator | 0:bb348c97df44 | 310 | |
lypinator | 0:bb348c97df44 | 311 | |
lypinator | 0:bb348c97df44 | 312 | /* Force reset of ADC clock (core clock) */ |
lypinator | 0:bb348c97df44 | 313 | LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_ADC); |
lypinator | 0:bb348c97df44 | 314 | |
lypinator | 0:bb348c97df44 | 315 | /* Release reset of ADC clock (core clock) */ |
lypinator | 0:bb348c97df44 | 316 | LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_ADC); |
lypinator | 0:bb348c97df44 | 317 | |
lypinator | 0:bb348c97df44 | 318 | return SUCCESS; |
lypinator | 0:bb348c97df44 | 319 | } |
lypinator | 0:bb348c97df44 | 320 | |
lypinator | 0:bb348c97df44 | 321 | /** |
lypinator | 0:bb348c97df44 | 322 | * @brief Initialize some features of ADC common parameters |
lypinator | 0:bb348c97df44 | 323 | * (all ADC instances belonging to the same ADC common instance) |
lypinator | 0:bb348c97df44 | 324 | * and multimode (for devices with several ADC instances available). |
lypinator | 0:bb348c97df44 | 325 | * @note The setting of ADC common parameters is conditioned to |
lypinator | 0:bb348c97df44 | 326 | * ADC instances state: |
lypinator | 0:bb348c97df44 | 327 | * All ADC instances belonging to the same ADC common instance |
lypinator | 0:bb348c97df44 | 328 | * must be disabled. |
lypinator | 0:bb348c97df44 | 329 | * @param ADCxy_COMMON ADC common instance |
lypinator | 0:bb348c97df44 | 330 | * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) |
lypinator | 0:bb348c97df44 | 331 | * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure |
lypinator | 0:bb348c97df44 | 332 | * @retval An ErrorStatus enumeration value: |
lypinator | 0:bb348c97df44 | 333 | * - SUCCESS: ADC common registers are initialized |
lypinator | 0:bb348c97df44 | 334 | * - ERROR: ADC common registers are not initialized |
lypinator | 0:bb348c97df44 | 335 | */ |
lypinator | 0:bb348c97df44 | 336 | ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct) |
lypinator | 0:bb348c97df44 | 337 | { |
lypinator | 0:bb348c97df44 | 338 | ErrorStatus status = SUCCESS; |
lypinator | 0:bb348c97df44 | 339 | |
lypinator | 0:bb348c97df44 | 340 | /* Check the parameters */ |
lypinator | 0:bb348c97df44 | 341 | assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON)); |
lypinator | 0:bb348c97df44 | 342 | assert_param(IS_LL_ADC_COMMON_CLOCK(ADC_CommonInitStruct->CommonClock)); |
lypinator | 0:bb348c97df44 | 343 | |
lypinator | 0:bb348c97df44 | 344 | #if defined(ADC_MULTIMODE_SUPPORT) |
lypinator | 0:bb348c97df44 | 345 | assert_param(IS_LL_ADC_MULTI_MODE(ADC_CommonInitStruct->Multimode)); |
lypinator | 0:bb348c97df44 | 346 | if(ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT) |
lypinator | 0:bb348c97df44 | 347 | { |
lypinator | 0:bb348c97df44 | 348 | assert_param(IS_LL_ADC_MULTI_DMA_TRANSFER(ADC_CommonInitStruct->MultiDMATransfer)); |
lypinator | 0:bb348c97df44 | 349 | assert_param(IS_LL_ADC_MULTI_TWOSMP_DELAY(ADC_CommonInitStruct->MultiTwoSamplingDelay)); |
lypinator | 0:bb348c97df44 | 350 | } |
lypinator | 0:bb348c97df44 | 351 | #endif /* ADC_MULTIMODE_SUPPORT */ |
lypinator | 0:bb348c97df44 | 352 | |
lypinator | 0:bb348c97df44 | 353 | /* Note: Hardware constraint (refer to description of functions */ |
lypinator | 0:bb348c97df44 | 354 | /* "LL_ADC_SetCommonXXX()" and "LL_ADC_SetMultiXXX()"): */ |
lypinator | 0:bb348c97df44 | 355 | /* On this STM32 serie, setting of these features is conditioned to */ |
lypinator | 0:bb348c97df44 | 356 | /* ADC state: */ |
lypinator | 0:bb348c97df44 | 357 | /* All ADC instances of the ADC common group must be disabled. */ |
lypinator | 0:bb348c97df44 | 358 | if(__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0U) |
lypinator | 0:bb348c97df44 | 359 | { |
lypinator | 0:bb348c97df44 | 360 | /* Configuration of ADC hierarchical scope: */ |
lypinator | 0:bb348c97df44 | 361 | /* - common to several ADC */ |
lypinator | 0:bb348c97df44 | 362 | /* (all ADC instances belonging to the same ADC common instance) */ |
lypinator | 0:bb348c97df44 | 363 | /* - Set ADC clock (conversion clock) */ |
lypinator | 0:bb348c97df44 | 364 | /* - multimode (if several ADC instances available on the */ |
lypinator | 0:bb348c97df44 | 365 | /* selected device) */ |
lypinator | 0:bb348c97df44 | 366 | /* - Set ADC multimode configuration */ |
lypinator | 0:bb348c97df44 | 367 | /* - Set ADC multimode DMA transfer */ |
lypinator | 0:bb348c97df44 | 368 | /* - Set ADC multimode: delay between 2 sampling phases */ |
lypinator | 0:bb348c97df44 | 369 | #if defined(ADC_MULTIMODE_SUPPORT) |
lypinator | 0:bb348c97df44 | 370 | if(ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT) |
lypinator | 0:bb348c97df44 | 371 | { |
lypinator | 0:bb348c97df44 | 372 | MODIFY_REG(ADCxy_COMMON->CCR, |
lypinator | 0:bb348c97df44 | 373 | ADC_CCR_ADCPRE |
lypinator | 0:bb348c97df44 | 374 | | ADC_CCR_MULTI |
lypinator | 0:bb348c97df44 | 375 | | ADC_CCR_DMA |
lypinator | 0:bb348c97df44 | 376 | | ADC_CCR_DDS |
lypinator | 0:bb348c97df44 | 377 | | ADC_CCR_DELAY |
lypinator | 0:bb348c97df44 | 378 | , |
lypinator | 0:bb348c97df44 | 379 | ADC_CommonInitStruct->CommonClock |
lypinator | 0:bb348c97df44 | 380 | | ADC_CommonInitStruct->Multimode |
lypinator | 0:bb348c97df44 | 381 | | ADC_CommonInitStruct->MultiDMATransfer |
lypinator | 0:bb348c97df44 | 382 | | ADC_CommonInitStruct->MultiTwoSamplingDelay |
lypinator | 0:bb348c97df44 | 383 | ); |
lypinator | 0:bb348c97df44 | 384 | } |
lypinator | 0:bb348c97df44 | 385 | else |
lypinator | 0:bb348c97df44 | 386 | { |
lypinator | 0:bb348c97df44 | 387 | MODIFY_REG(ADCxy_COMMON->CCR, |
lypinator | 0:bb348c97df44 | 388 | ADC_CCR_ADCPRE |
lypinator | 0:bb348c97df44 | 389 | | ADC_CCR_MULTI |
lypinator | 0:bb348c97df44 | 390 | | ADC_CCR_DMA |
lypinator | 0:bb348c97df44 | 391 | | ADC_CCR_DDS |
lypinator | 0:bb348c97df44 | 392 | | ADC_CCR_DELAY |
lypinator | 0:bb348c97df44 | 393 | , |
lypinator | 0:bb348c97df44 | 394 | ADC_CommonInitStruct->CommonClock |
lypinator | 0:bb348c97df44 | 395 | | LL_ADC_MULTI_INDEPENDENT |
lypinator | 0:bb348c97df44 | 396 | ); |
lypinator | 0:bb348c97df44 | 397 | } |
lypinator | 0:bb348c97df44 | 398 | #else |
lypinator | 0:bb348c97df44 | 399 | LL_ADC_SetCommonClock(ADCxy_COMMON, ADC_CommonInitStruct->CommonClock); |
lypinator | 0:bb348c97df44 | 400 | #endif |
lypinator | 0:bb348c97df44 | 401 | } |
lypinator | 0:bb348c97df44 | 402 | else |
lypinator | 0:bb348c97df44 | 403 | { |
lypinator | 0:bb348c97df44 | 404 | /* Initialization error: One or several ADC instances belonging to */ |
lypinator | 0:bb348c97df44 | 405 | /* the same ADC common instance are not disabled. */ |
lypinator | 0:bb348c97df44 | 406 | status = ERROR; |
lypinator | 0:bb348c97df44 | 407 | } |
lypinator | 0:bb348c97df44 | 408 | |
lypinator | 0:bb348c97df44 | 409 | return status; |
lypinator | 0:bb348c97df44 | 410 | } |
lypinator | 0:bb348c97df44 | 411 | |
lypinator | 0:bb348c97df44 | 412 | /** |
lypinator | 0:bb348c97df44 | 413 | * @brief Set each @ref LL_ADC_CommonInitTypeDef field to default value. |
lypinator | 0:bb348c97df44 | 414 | * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure |
lypinator | 0:bb348c97df44 | 415 | * whose fields will be set to default values. |
lypinator | 0:bb348c97df44 | 416 | * @retval None |
lypinator | 0:bb348c97df44 | 417 | */ |
lypinator | 0:bb348c97df44 | 418 | void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct) |
lypinator | 0:bb348c97df44 | 419 | { |
lypinator | 0:bb348c97df44 | 420 | /* Set ADC_CommonInitStruct fields to default values */ |
lypinator | 0:bb348c97df44 | 421 | /* Set fields of ADC common */ |
lypinator | 0:bb348c97df44 | 422 | /* (all ADC instances belonging to the same ADC common instance) */ |
lypinator | 0:bb348c97df44 | 423 | ADC_CommonInitStruct->CommonClock = LL_ADC_CLOCK_SYNC_PCLK_DIV2; |
lypinator | 0:bb348c97df44 | 424 | |
lypinator | 0:bb348c97df44 | 425 | #if defined(ADC_MULTIMODE_SUPPORT) |
lypinator | 0:bb348c97df44 | 426 | /* Set fields of ADC multimode */ |
lypinator | 0:bb348c97df44 | 427 | ADC_CommonInitStruct->Multimode = LL_ADC_MULTI_INDEPENDENT; |
lypinator | 0:bb348c97df44 | 428 | ADC_CommonInitStruct->MultiDMATransfer = LL_ADC_MULTI_REG_DMA_EACH_ADC; |
lypinator | 0:bb348c97df44 | 429 | ADC_CommonInitStruct->MultiTwoSamplingDelay = LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES; |
lypinator | 0:bb348c97df44 | 430 | #endif /* ADC_MULTIMODE_SUPPORT */ |
lypinator | 0:bb348c97df44 | 431 | } |
lypinator | 0:bb348c97df44 | 432 | |
lypinator | 0:bb348c97df44 | 433 | /** |
lypinator | 0:bb348c97df44 | 434 | * @brief De-initialize registers of the selected ADC instance |
lypinator | 0:bb348c97df44 | 435 | * to their default reset values. |
lypinator | 0:bb348c97df44 | 436 | * @note To reset all ADC instances quickly (perform a hard reset), |
lypinator | 0:bb348c97df44 | 437 | * use function @ref LL_ADC_CommonDeInit(). |
lypinator | 0:bb348c97df44 | 438 | * @param ADCx ADC instance |
lypinator | 0:bb348c97df44 | 439 | * @retval An ErrorStatus enumeration value: |
lypinator | 0:bb348c97df44 | 440 | * - SUCCESS: ADC registers are de-initialized |
lypinator | 0:bb348c97df44 | 441 | * - ERROR: ADC registers are not de-initialized |
lypinator | 0:bb348c97df44 | 442 | */ |
lypinator | 0:bb348c97df44 | 443 | ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx) |
lypinator | 0:bb348c97df44 | 444 | { |
lypinator | 0:bb348c97df44 | 445 | ErrorStatus status = SUCCESS; |
lypinator | 0:bb348c97df44 | 446 | |
lypinator | 0:bb348c97df44 | 447 | /* Check the parameters */ |
lypinator | 0:bb348c97df44 | 448 | assert_param(IS_ADC_ALL_INSTANCE(ADCx)); |
lypinator | 0:bb348c97df44 | 449 | |
lypinator | 0:bb348c97df44 | 450 | /* Disable ADC instance if not already disabled. */ |
lypinator | 0:bb348c97df44 | 451 | if(LL_ADC_IsEnabled(ADCx) == 1U) |
lypinator | 0:bb348c97df44 | 452 | { |
lypinator | 0:bb348c97df44 | 453 | /* Set ADC group regular trigger source to SW start to ensure to not */ |
lypinator | 0:bb348c97df44 | 454 | /* have an external trigger event occurring during the conversion stop */ |
lypinator | 0:bb348c97df44 | 455 | /* ADC disable process. */ |
lypinator | 0:bb348c97df44 | 456 | LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE); |
lypinator | 0:bb348c97df44 | 457 | |
lypinator | 0:bb348c97df44 | 458 | /* Set ADC group injected trigger source to SW start to ensure to not */ |
lypinator | 0:bb348c97df44 | 459 | /* have an external trigger event occurring during the conversion stop */ |
lypinator | 0:bb348c97df44 | 460 | /* ADC disable process. */ |
lypinator | 0:bb348c97df44 | 461 | LL_ADC_INJ_SetTriggerSource(ADCx, LL_ADC_INJ_TRIG_SOFTWARE); |
lypinator | 0:bb348c97df44 | 462 | |
lypinator | 0:bb348c97df44 | 463 | /* Disable the ADC instance */ |
lypinator | 0:bb348c97df44 | 464 | LL_ADC_Disable(ADCx); |
lypinator | 0:bb348c97df44 | 465 | } |
lypinator | 0:bb348c97df44 | 466 | |
lypinator | 0:bb348c97df44 | 467 | /* Check whether ADC state is compliant with expected state */ |
lypinator | 0:bb348c97df44 | 468 | /* (hardware requirements of bits state to reset registers below) */ |
lypinator | 0:bb348c97df44 | 469 | if(READ_BIT(ADCx->CR2, ADC_CR2_ADON) == 0U) |
lypinator | 0:bb348c97df44 | 470 | { |
lypinator | 0:bb348c97df44 | 471 | /* ========== Reset ADC registers ========== */ |
lypinator | 0:bb348c97df44 | 472 | /* Reset register SR */ |
lypinator | 0:bb348c97df44 | 473 | CLEAR_BIT(ADCx->SR, |
lypinator | 0:bb348c97df44 | 474 | ( LL_ADC_FLAG_STRT |
lypinator | 0:bb348c97df44 | 475 | | LL_ADC_FLAG_JSTRT |
lypinator | 0:bb348c97df44 | 476 | | LL_ADC_FLAG_EOCS |
lypinator | 0:bb348c97df44 | 477 | | LL_ADC_FLAG_OVR |
lypinator | 0:bb348c97df44 | 478 | | LL_ADC_FLAG_JEOS |
lypinator | 0:bb348c97df44 | 479 | | LL_ADC_FLAG_AWD1 ) |
lypinator | 0:bb348c97df44 | 480 | ); |
lypinator | 0:bb348c97df44 | 481 | |
lypinator | 0:bb348c97df44 | 482 | /* Reset register CR1 */ |
lypinator | 0:bb348c97df44 | 483 | CLEAR_BIT(ADCx->CR1, |
lypinator | 0:bb348c97df44 | 484 | ( ADC_CR1_OVRIE | ADC_CR1_RES | ADC_CR1_AWDEN |
lypinator | 0:bb348c97df44 | 485 | | ADC_CR1_JAWDEN |
lypinator | 0:bb348c97df44 | 486 | | ADC_CR1_DISCNUM | ADC_CR1_JDISCEN | ADC_CR1_DISCEN |
lypinator | 0:bb348c97df44 | 487 | | ADC_CR1_JAUTO | ADC_CR1_AWDSGL | ADC_CR1_SCAN |
lypinator | 0:bb348c97df44 | 488 | | ADC_CR1_JEOCIE | ADC_CR1_AWDIE | ADC_CR1_EOCIE |
lypinator | 0:bb348c97df44 | 489 | | ADC_CR1_AWDCH ) |
lypinator | 0:bb348c97df44 | 490 | ); |
lypinator | 0:bb348c97df44 | 491 | |
lypinator | 0:bb348c97df44 | 492 | /* Reset register CR2 */ |
lypinator | 0:bb348c97df44 | 493 | CLEAR_BIT(ADCx->CR2, |
lypinator | 0:bb348c97df44 | 494 | ( ADC_CR2_SWSTART | ADC_CR2_EXTEN | ADC_CR2_EXTSEL |
lypinator | 0:bb348c97df44 | 495 | | ADC_CR2_JSWSTART | ADC_CR2_JEXTEN | ADC_CR2_JEXTSEL |
lypinator | 0:bb348c97df44 | 496 | | ADC_CR2_ALIGN | ADC_CR2_EOCS |
lypinator | 0:bb348c97df44 | 497 | | ADC_CR2_DDS | ADC_CR2_DMA |
lypinator | 0:bb348c97df44 | 498 | | ADC_CR2_CONT | ADC_CR2_ADON ) |
lypinator | 0:bb348c97df44 | 499 | ); |
lypinator | 0:bb348c97df44 | 500 | |
lypinator | 0:bb348c97df44 | 501 | /* Reset register SMPR1 */ |
lypinator | 0:bb348c97df44 | 502 | CLEAR_BIT(ADCx->SMPR1, |
lypinator | 0:bb348c97df44 | 503 | ( ADC_SMPR1_SMP18 | ADC_SMPR1_SMP17 | ADC_SMPR1_SMP16 |
lypinator | 0:bb348c97df44 | 504 | | ADC_SMPR1_SMP15 | ADC_SMPR1_SMP14 | ADC_SMPR1_SMP13 |
lypinator | 0:bb348c97df44 | 505 | | ADC_SMPR1_SMP12 | ADC_SMPR1_SMP11 | ADC_SMPR1_SMP10) |
lypinator | 0:bb348c97df44 | 506 | ); |
lypinator | 0:bb348c97df44 | 507 | |
lypinator | 0:bb348c97df44 | 508 | /* Reset register SMPR2 */ |
lypinator | 0:bb348c97df44 | 509 | CLEAR_BIT(ADCx->SMPR2, |
lypinator | 0:bb348c97df44 | 510 | ( ADC_SMPR2_SMP9 |
lypinator | 0:bb348c97df44 | 511 | | ADC_SMPR2_SMP8 | ADC_SMPR2_SMP7 | ADC_SMPR2_SMP6 |
lypinator | 0:bb348c97df44 | 512 | | ADC_SMPR2_SMP5 | ADC_SMPR2_SMP4 | ADC_SMPR2_SMP3 |
lypinator | 0:bb348c97df44 | 513 | | ADC_SMPR2_SMP2 | ADC_SMPR2_SMP1 | ADC_SMPR2_SMP0) |
lypinator | 0:bb348c97df44 | 514 | ); |
lypinator | 0:bb348c97df44 | 515 | |
lypinator | 0:bb348c97df44 | 516 | /* Reset register JOFR1 */ |
lypinator | 0:bb348c97df44 | 517 | CLEAR_BIT(ADCx->JOFR1, ADC_JOFR1_JOFFSET1); |
lypinator | 0:bb348c97df44 | 518 | /* Reset register JOFR2 */ |
lypinator | 0:bb348c97df44 | 519 | CLEAR_BIT(ADCx->JOFR2, ADC_JOFR2_JOFFSET2); |
lypinator | 0:bb348c97df44 | 520 | /* Reset register JOFR3 */ |
lypinator | 0:bb348c97df44 | 521 | CLEAR_BIT(ADCx->JOFR3, ADC_JOFR3_JOFFSET3); |
lypinator | 0:bb348c97df44 | 522 | /* Reset register JOFR4 */ |
lypinator | 0:bb348c97df44 | 523 | CLEAR_BIT(ADCx->JOFR4, ADC_JOFR4_JOFFSET4); |
lypinator | 0:bb348c97df44 | 524 | |
lypinator | 0:bb348c97df44 | 525 | /* Reset register HTR */ |
lypinator | 0:bb348c97df44 | 526 | SET_BIT(ADCx->HTR, ADC_HTR_HT); |
lypinator | 0:bb348c97df44 | 527 | /* Reset register LTR */ |
lypinator | 0:bb348c97df44 | 528 | CLEAR_BIT(ADCx->LTR, ADC_LTR_LT); |
lypinator | 0:bb348c97df44 | 529 | |
lypinator | 0:bb348c97df44 | 530 | /* Reset register SQR1 */ |
lypinator | 0:bb348c97df44 | 531 | CLEAR_BIT(ADCx->SQR1, |
lypinator | 0:bb348c97df44 | 532 | ( ADC_SQR1_L |
lypinator | 0:bb348c97df44 | 533 | | ADC_SQR1_SQ16 |
lypinator | 0:bb348c97df44 | 534 | | ADC_SQR1_SQ15 | ADC_SQR1_SQ14 | ADC_SQR1_SQ13) |
lypinator | 0:bb348c97df44 | 535 | ); |
lypinator | 0:bb348c97df44 | 536 | |
lypinator | 0:bb348c97df44 | 537 | /* Reset register SQR2 */ |
lypinator | 0:bb348c97df44 | 538 | CLEAR_BIT(ADCx->SQR2, |
lypinator | 0:bb348c97df44 | 539 | ( ADC_SQR2_SQ12 | ADC_SQR2_SQ11 | ADC_SQR2_SQ10 |
lypinator | 0:bb348c97df44 | 540 | | ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7) |
lypinator | 0:bb348c97df44 | 541 | ); |
lypinator | 0:bb348c97df44 | 542 | |
lypinator | 0:bb348c97df44 | 543 | |
lypinator | 0:bb348c97df44 | 544 | /* Reset register JSQR */ |
lypinator | 0:bb348c97df44 | 545 | CLEAR_BIT(ADCx->JSQR, |
lypinator | 0:bb348c97df44 | 546 | ( ADC_JSQR_JL |
lypinator | 0:bb348c97df44 | 547 | | ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3 |
lypinator | 0:bb348c97df44 | 548 | | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1 ) |
lypinator | 0:bb348c97df44 | 549 | ); |
lypinator | 0:bb348c97df44 | 550 | |
lypinator | 0:bb348c97df44 | 551 | /* Reset register DR */ |
lypinator | 0:bb348c97df44 | 552 | /* bits in access mode read only, no direct reset applicable */ |
lypinator | 0:bb348c97df44 | 553 | |
lypinator | 0:bb348c97df44 | 554 | /* Reset registers JDR1, JDR2, JDR3, JDR4 */ |
lypinator | 0:bb348c97df44 | 555 | /* bits in access mode read only, no direct reset applicable */ |
lypinator | 0:bb348c97df44 | 556 | |
lypinator | 0:bb348c97df44 | 557 | /* Reset register CCR */ |
lypinator | 0:bb348c97df44 | 558 | CLEAR_BIT(ADC->CCR, ADC_CCR_TSVREFE | ADC_CCR_ADCPRE); |
lypinator | 0:bb348c97df44 | 559 | } |
lypinator | 0:bb348c97df44 | 560 | |
lypinator | 0:bb348c97df44 | 561 | return status; |
lypinator | 0:bb348c97df44 | 562 | } |
lypinator | 0:bb348c97df44 | 563 | |
lypinator | 0:bb348c97df44 | 564 | /** |
lypinator | 0:bb348c97df44 | 565 | * @brief Initialize some features of ADC instance. |
lypinator | 0:bb348c97df44 | 566 | * @note These parameters have an impact on ADC scope: ADC instance. |
lypinator | 0:bb348c97df44 | 567 | * Affects both group regular and group injected (availability |
lypinator | 0:bb348c97df44 | 568 | * of ADC group injected depends on STM32 families). |
lypinator | 0:bb348c97df44 | 569 | * Refer to corresponding unitary functions into |
lypinator | 0:bb348c97df44 | 570 | * @ref ADC_LL_EF_Configuration_ADC_Instance . |
lypinator | 0:bb348c97df44 | 571 | * @note The setting of these parameters by function @ref LL_ADC_Init() |
lypinator | 0:bb348c97df44 | 572 | * is conditioned to ADC state: |
lypinator | 0:bb348c97df44 | 573 | * ADC instance must be disabled. |
lypinator | 0:bb348c97df44 | 574 | * This condition is applied to all ADC features, for efficiency |
lypinator | 0:bb348c97df44 | 575 | * and compatibility over all STM32 families. However, the different |
lypinator | 0:bb348c97df44 | 576 | * features can be set under different ADC state conditions |
lypinator | 0:bb348c97df44 | 577 | * (setting possible with ADC enabled without conversion on going, |
lypinator | 0:bb348c97df44 | 578 | * ADC enabled with conversion on going, ...) |
lypinator | 0:bb348c97df44 | 579 | * Each feature can be updated afterwards with a unitary function |
lypinator | 0:bb348c97df44 | 580 | * and potentially with ADC in a different state than disabled, |
lypinator | 0:bb348c97df44 | 581 | * refer to description of each function for setting |
lypinator | 0:bb348c97df44 | 582 | * conditioned to ADC state. |
lypinator | 0:bb348c97df44 | 583 | * @note After using this function, some other features must be configured |
lypinator | 0:bb348c97df44 | 584 | * using LL unitary functions. |
lypinator | 0:bb348c97df44 | 585 | * The minimum configuration remaining to be done is: |
lypinator | 0:bb348c97df44 | 586 | * - Set ADC group regular or group injected sequencer: |
lypinator | 0:bb348c97df44 | 587 | * map channel on the selected sequencer rank. |
lypinator | 0:bb348c97df44 | 588 | * Refer to function @ref LL_ADC_REG_SetSequencerRanks(). |
lypinator | 0:bb348c97df44 | 589 | * - Set ADC channel sampling time |
lypinator | 0:bb348c97df44 | 590 | * Refer to function LL_ADC_SetChannelSamplingTime(); |
lypinator | 0:bb348c97df44 | 591 | * @param ADCx ADC instance |
lypinator | 0:bb348c97df44 | 592 | * @param ADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure |
lypinator | 0:bb348c97df44 | 593 | * @retval An ErrorStatus enumeration value: |
lypinator | 0:bb348c97df44 | 594 | * - SUCCESS: ADC registers are initialized |
lypinator | 0:bb348c97df44 | 595 | * - ERROR: ADC registers are not initialized |
lypinator | 0:bb348c97df44 | 596 | */ |
lypinator | 0:bb348c97df44 | 597 | ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct) |
lypinator | 0:bb348c97df44 | 598 | { |
lypinator | 0:bb348c97df44 | 599 | ErrorStatus status = SUCCESS; |
lypinator | 0:bb348c97df44 | 600 | |
lypinator | 0:bb348c97df44 | 601 | /* Check the parameters */ |
lypinator | 0:bb348c97df44 | 602 | assert_param(IS_ADC_ALL_INSTANCE(ADCx)); |
lypinator | 0:bb348c97df44 | 603 | |
lypinator | 0:bb348c97df44 | 604 | assert_param(IS_LL_ADC_RESOLUTION(ADC_InitStruct->Resolution)); |
lypinator | 0:bb348c97df44 | 605 | assert_param(IS_LL_ADC_DATA_ALIGN(ADC_InitStruct->DataAlignment)); |
lypinator | 0:bb348c97df44 | 606 | assert_param(IS_LL_ADC_SCAN_SELECTION(ADC_InitStruct->SequencersScanMode)); |
lypinator | 0:bb348c97df44 | 607 | |
lypinator | 0:bb348c97df44 | 608 | /* Note: Hardware constraint (refer to description of this function): */ |
lypinator | 0:bb348c97df44 | 609 | /* ADC instance must be disabled. */ |
lypinator | 0:bb348c97df44 | 610 | if(LL_ADC_IsEnabled(ADCx) == 0U) |
lypinator | 0:bb348c97df44 | 611 | { |
lypinator | 0:bb348c97df44 | 612 | /* Configuration of ADC hierarchical scope: */ |
lypinator | 0:bb348c97df44 | 613 | /* - ADC instance */ |
lypinator | 0:bb348c97df44 | 614 | /* - Set ADC data resolution */ |
lypinator | 0:bb348c97df44 | 615 | /* - Set ADC conversion data alignment */ |
lypinator | 0:bb348c97df44 | 616 | MODIFY_REG(ADCx->CR1, |
lypinator | 0:bb348c97df44 | 617 | ADC_CR1_RES |
lypinator | 0:bb348c97df44 | 618 | | ADC_CR1_SCAN |
lypinator | 0:bb348c97df44 | 619 | , |
lypinator | 0:bb348c97df44 | 620 | ADC_InitStruct->Resolution |
lypinator | 0:bb348c97df44 | 621 | | ADC_InitStruct->SequencersScanMode |
lypinator | 0:bb348c97df44 | 622 | ); |
lypinator | 0:bb348c97df44 | 623 | |
lypinator | 0:bb348c97df44 | 624 | MODIFY_REG(ADCx->CR2, |
lypinator | 0:bb348c97df44 | 625 | ADC_CR2_ALIGN |
lypinator | 0:bb348c97df44 | 626 | , |
lypinator | 0:bb348c97df44 | 627 | ADC_InitStruct->DataAlignment |
lypinator | 0:bb348c97df44 | 628 | ); |
lypinator | 0:bb348c97df44 | 629 | |
lypinator | 0:bb348c97df44 | 630 | } |
lypinator | 0:bb348c97df44 | 631 | else |
lypinator | 0:bb348c97df44 | 632 | { |
lypinator | 0:bb348c97df44 | 633 | /* Initialization error: ADC instance is not disabled. */ |
lypinator | 0:bb348c97df44 | 634 | status = ERROR; |
lypinator | 0:bb348c97df44 | 635 | } |
lypinator | 0:bb348c97df44 | 636 | return status; |
lypinator | 0:bb348c97df44 | 637 | } |
lypinator | 0:bb348c97df44 | 638 | |
lypinator | 0:bb348c97df44 | 639 | /** |
lypinator | 0:bb348c97df44 | 640 | * @brief Set each @ref LL_ADC_InitTypeDef field to default value. |
lypinator | 0:bb348c97df44 | 641 | * @param ADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure |
lypinator | 0:bb348c97df44 | 642 | * whose fields will be set to default values. |
lypinator | 0:bb348c97df44 | 643 | * @retval None |
lypinator | 0:bb348c97df44 | 644 | */ |
lypinator | 0:bb348c97df44 | 645 | void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct) |
lypinator | 0:bb348c97df44 | 646 | { |
lypinator | 0:bb348c97df44 | 647 | /* Set ADC_InitStruct fields to default values */ |
lypinator | 0:bb348c97df44 | 648 | /* Set fields of ADC instance */ |
lypinator | 0:bb348c97df44 | 649 | ADC_InitStruct->Resolution = LL_ADC_RESOLUTION_12B; |
lypinator | 0:bb348c97df44 | 650 | ADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT; |
lypinator | 0:bb348c97df44 | 651 | |
lypinator | 0:bb348c97df44 | 652 | /* Enable scan mode to have a generic behavior with ADC of other */ |
lypinator | 0:bb348c97df44 | 653 | /* STM32 families, without this setting available: */ |
lypinator | 0:bb348c97df44 | 654 | /* ADC group regular sequencer and ADC group injected sequencer depend */ |
lypinator | 0:bb348c97df44 | 655 | /* only of their own configuration. */ |
lypinator | 0:bb348c97df44 | 656 | ADC_InitStruct->SequencersScanMode = LL_ADC_SEQ_SCAN_ENABLE; |
lypinator | 0:bb348c97df44 | 657 | |
lypinator | 0:bb348c97df44 | 658 | } |
lypinator | 0:bb348c97df44 | 659 | |
lypinator | 0:bb348c97df44 | 660 | /** |
lypinator | 0:bb348c97df44 | 661 | * @brief Initialize some features of ADC group regular. |
lypinator | 0:bb348c97df44 | 662 | * @note These parameters have an impact on ADC scope: ADC group regular. |
lypinator | 0:bb348c97df44 | 663 | * Refer to corresponding unitary functions into |
lypinator | 0:bb348c97df44 | 664 | * @ref ADC_LL_EF_Configuration_ADC_Group_Regular |
lypinator | 0:bb348c97df44 | 665 | * (functions with prefix "REG"). |
lypinator | 0:bb348c97df44 | 666 | * @note The setting of these parameters by function @ref LL_ADC_Init() |
lypinator | 0:bb348c97df44 | 667 | * is conditioned to ADC state: |
lypinator | 0:bb348c97df44 | 668 | * ADC instance must be disabled. |
lypinator | 0:bb348c97df44 | 669 | * This condition is applied to all ADC features, for efficiency |
lypinator | 0:bb348c97df44 | 670 | * and compatibility over all STM32 families. However, the different |
lypinator | 0:bb348c97df44 | 671 | * features can be set under different ADC state conditions |
lypinator | 0:bb348c97df44 | 672 | * (setting possible with ADC enabled without conversion on going, |
lypinator | 0:bb348c97df44 | 673 | * ADC enabled with conversion on going, ...) |
lypinator | 0:bb348c97df44 | 674 | * Each feature can be updated afterwards with a unitary function |
lypinator | 0:bb348c97df44 | 675 | * and potentially with ADC in a different state than disabled, |
lypinator | 0:bb348c97df44 | 676 | * refer to description of each function for setting |
lypinator | 0:bb348c97df44 | 677 | * conditioned to ADC state. |
lypinator | 0:bb348c97df44 | 678 | * @note After using this function, other features must be configured |
lypinator | 0:bb348c97df44 | 679 | * using LL unitary functions. |
lypinator | 0:bb348c97df44 | 680 | * The minimum configuration remaining to be done is: |
lypinator | 0:bb348c97df44 | 681 | * - Set ADC group regular or group injected sequencer: |
lypinator | 0:bb348c97df44 | 682 | * map channel on the selected sequencer rank. |
lypinator | 0:bb348c97df44 | 683 | * Refer to function @ref LL_ADC_REG_SetSequencerRanks(). |
lypinator | 0:bb348c97df44 | 684 | * - Set ADC channel sampling time |
lypinator | 0:bb348c97df44 | 685 | * Refer to function LL_ADC_SetChannelSamplingTime(); |
lypinator | 0:bb348c97df44 | 686 | * @param ADCx ADC instance |
lypinator | 0:bb348c97df44 | 687 | * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure |
lypinator | 0:bb348c97df44 | 688 | * @retval An ErrorStatus enumeration value: |
lypinator | 0:bb348c97df44 | 689 | * - SUCCESS: ADC registers are initialized |
lypinator | 0:bb348c97df44 | 690 | * - ERROR: ADC registers are not initialized |
lypinator | 0:bb348c97df44 | 691 | */ |
lypinator | 0:bb348c97df44 | 692 | ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct) |
lypinator | 0:bb348c97df44 | 693 | { |
lypinator | 0:bb348c97df44 | 694 | ErrorStatus status = SUCCESS; |
lypinator | 0:bb348c97df44 | 695 | |
lypinator | 0:bb348c97df44 | 696 | /* Check the parameters */ |
lypinator | 0:bb348c97df44 | 697 | assert_param(IS_ADC_ALL_INSTANCE(ADCx)); |
lypinator | 0:bb348c97df44 | 698 | assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADC_REG_InitStruct->TriggerSource)); |
lypinator | 0:bb348c97df44 | 699 | assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(ADC_REG_InitStruct->SequencerLength)); |
lypinator | 0:bb348c97df44 | 700 | if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) |
lypinator | 0:bb348c97df44 | 701 | { |
lypinator | 0:bb348c97df44 | 702 | assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont)); |
lypinator | 0:bb348c97df44 | 703 | } |
lypinator | 0:bb348c97df44 | 704 | assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode)); |
lypinator | 0:bb348c97df44 | 705 | assert_param(IS_LL_ADC_REG_DMA_TRANSFER(ADC_REG_InitStruct->DMATransfer)); |
lypinator | 0:bb348c97df44 | 706 | |
lypinator | 0:bb348c97df44 | 707 | /* Note: Hardware constraint (refer to description of this function): */ |
lypinator | 0:bb348c97df44 | 708 | /* ADC instance must be disabled. */ |
lypinator | 0:bb348c97df44 | 709 | if(LL_ADC_IsEnabled(ADCx) == 0U) |
lypinator | 0:bb348c97df44 | 710 | { |
lypinator | 0:bb348c97df44 | 711 | /* Configuration of ADC hierarchical scope: */ |
lypinator | 0:bb348c97df44 | 712 | /* - ADC group regular */ |
lypinator | 0:bb348c97df44 | 713 | /* - Set ADC group regular trigger source */ |
lypinator | 0:bb348c97df44 | 714 | /* - Set ADC group regular sequencer length */ |
lypinator | 0:bb348c97df44 | 715 | /* - Set ADC group regular sequencer discontinuous mode */ |
lypinator | 0:bb348c97df44 | 716 | /* - Set ADC group regular continuous mode */ |
lypinator | 0:bb348c97df44 | 717 | /* - Set ADC group regular conversion data transfer: no transfer or */ |
lypinator | 0:bb348c97df44 | 718 | /* transfer by DMA, and DMA requests mode */ |
lypinator | 0:bb348c97df44 | 719 | /* Note: On this STM32 serie, ADC trigger edge is set when starting */ |
lypinator | 0:bb348c97df44 | 720 | /* ADC conversion. */ |
lypinator | 0:bb348c97df44 | 721 | /* Refer to function @ref LL_ADC_REG_StartConversionExtTrig(). */ |
lypinator | 0:bb348c97df44 | 722 | if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) |
lypinator | 0:bb348c97df44 | 723 | { |
lypinator | 0:bb348c97df44 | 724 | MODIFY_REG(ADCx->CR1, |
lypinator | 0:bb348c97df44 | 725 | ADC_CR1_DISCEN |
lypinator | 0:bb348c97df44 | 726 | | ADC_CR1_DISCNUM |
lypinator | 0:bb348c97df44 | 727 | , |
lypinator | 0:bb348c97df44 | 728 | ADC_REG_InitStruct->SequencerLength |
lypinator | 0:bb348c97df44 | 729 | | ADC_REG_InitStruct->SequencerDiscont |
lypinator | 0:bb348c97df44 | 730 | ); |
lypinator | 0:bb348c97df44 | 731 | } |
lypinator | 0:bb348c97df44 | 732 | else |
lypinator | 0:bb348c97df44 | 733 | { |
lypinator | 0:bb348c97df44 | 734 | MODIFY_REG(ADCx->CR1, |
lypinator | 0:bb348c97df44 | 735 | ADC_CR1_DISCEN |
lypinator | 0:bb348c97df44 | 736 | | ADC_CR1_DISCNUM |
lypinator | 0:bb348c97df44 | 737 | , |
lypinator | 0:bb348c97df44 | 738 | ADC_REG_InitStruct->SequencerLength |
lypinator | 0:bb348c97df44 | 739 | | LL_ADC_REG_SEQ_DISCONT_DISABLE |
lypinator | 0:bb348c97df44 | 740 | ); |
lypinator | 0:bb348c97df44 | 741 | } |
lypinator | 0:bb348c97df44 | 742 | |
lypinator | 0:bb348c97df44 | 743 | MODIFY_REG(ADCx->CR2, |
lypinator | 0:bb348c97df44 | 744 | ADC_CR2_EXTSEL |
lypinator | 0:bb348c97df44 | 745 | | ADC_CR2_EXTEN |
lypinator | 0:bb348c97df44 | 746 | | ADC_CR2_CONT |
lypinator | 0:bb348c97df44 | 747 | | ADC_CR2_DMA |
lypinator | 0:bb348c97df44 | 748 | | ADC_CR2_DDS |
lypinator | 0:bb348c97df44 | 749 | , |
lypinator | 0:bb348c97df44 | 750 | (ADC_REG_InitStruct->TriggerSource & ADC_CR2_EXTSEL) |
lypinator | 0:bb348c97df44 | 751 | | ADC_REG_InitStruct->ContinuousMode |
lypinator | 0:bb348c97df44 | 752 | | ADC_REG_InitStruct->DMATransfer |
lypinator | 0:bb348c97df44 | 753 | ); |
lypinator | 0:bb348c97df44 | 754 | |
lypinator | 0:bb348c97df44 | 755 | /* Set ADC group regular sequencer length and scan direction */ |
lypinator | 0:bb348c97df44 | 756 | /* Note: Hardware constraint (refer to description of this function): */ |
lypinator | 0:bb348c97df44 | 757 | /* Note: If ADC instance feature scan mode is disabled */ |
lypinator | 0:bb348c97df44 | 758 | /* (refer to ADC instance initialization structure */ |
lypinator | 0:bb348c97df44 | 759 | /* parameter @ref SequencersScanMode */ |
lypinator | 0:bb348c97df44 | 760 | /* or function @ref LL_ADC_SetSequencersScanMode() ), */ |
lypinator | 0:bb348c97df44 | 761 | /* this parameter is discarded. */ |
lypinator | 0:bb348c97df44 | 762 | LL_ADC_REG_SetSequencerLength(ADCx, ADC_REG_InitStruct->SequencerLength); |
lypinator | 0:bb348c97df44 | 763 | } |
lypinator | 0:bb348c97df44 | 764 | else |
lypinator | 0:bb348c97df44 | 765 | { |
lypinator | 0:bb348c97df44 | 766 | /* Initialization error: ADC instance is not disabled. */ |
lypinator | 0:bb348c97df44 | 767 | status = ERROR; |
lypinator | 0:bb348c97df44 | 768 | } |
lypinator | 0:bb348c97df44 | 769 | return status; |
lypinator | 0:bb348c97df44 | 770 | } |
lypinator | 0:bb348c97df44 | 771 | |
lypinator | 0:bb348c97df44 | 772 | /** |
lypinator | 0:bb348c97df44 | 773 | * @brief Set each @ref LL_ADC_REG_InitTypeDef field to default value. |
lypinator | 0:bb348c97df44 | 774 | * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure |
lypinator | 0:bb348c97df44 | 775 | * whose fields will be set to default values. |
lypinator | 0:bb348c97df44 | 776 | * @retval None |
lypinator | 0:bb348c97df44 | 777 | */ |
lypinator | 0:bb348c97df44 | 778 | void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct) |
lypinator | 0:bb348c97df44 | 779 | { |
lypinator | 0:bb348c97df44 | 780 | /* Set ADC_REG_InitStruct fields to default values */ |
lypinator | 0:bb348c97df44 | 781 | /* Set fields of ADC group regular */ |
lypinator | 0:bb348c97df44 | 782 | /* Note: On this STM32 serie, ADC trigger edge is set when starting */ |
lypinator | 0:bb348c97df44 | 783 | /* ADC conversion. */ |
lypinator | 0:bb348c97df44 | 784 | /* Refer to function @ref LL_ADC_REG_StartConversionExtTrig(). */ |
lypinator | 0:bb348c97df44 | 785 | ADC_REG_InitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE; |
lypinator | 0:bb348c97df44 | 786 | ADC_REG_InitStruct->SequencerLength = LL_ADC_REG_SEQ_SCAN_DISABLE; |
lypinator | 0:bb348c97df44 | 787 | ADC_REG_InitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE; |
lypinator | 0:bb348c97df44 | 788 | ADC_REG_InitStruct->ContinuousMode = LL_ADC_REG_CONV_SINGLE; |
lypinator | 0:bb348c97df44 | 789 | ADC_REG_InitStruct->DMATransfer = LL_ADC_REG_DMA_TRANSFER_NONE; |
lypinator | 0:bb348c97df44 | 790 | } |
lypinator | 0:bb348c97df44 | 791 | |
lypinator | 0:bb348c97df44 | 792 | /** |
lypinator | 0:bb348c97df44 | 793 | * @brief Initialize some features of ADC group injected. |
lypinator | 0:bb348c97df44 | 794 | * @note These parameters have an impact on ADC scope: ADC group injected. |
lypinator | 0:bb348c97df44 | 795 | * Refer to corresponding unitary functions into |
lypinator | 0:bb348c97df44 | 796 | * @ref ADC_LL_EF_Configuration_ADC_Group_Regular |
lypinator | 0:bb348c97df44 | 797 | * (functions with prefix "INJ"). |
lypinator | 0:bb348c97df44 | 798 | * @note The setting of these parameters by function @ref LL_ADC_Init() |
lypinator | 0:bb348c97df44 | 799 | * is conditioned to ADC state: |
lypinator | 0:bb348c97df44 | 800 | * ADC instance must be disabled. |
lypinator | 0:bb348c97df44 | 801 | * This condition is applied to all ADC features, for efficiency |
lypinator | 0:bb348c97df44 | 802 | * and compatibility over all STM32 families. However, the different |
lypinator | 0:bb348c97df44 | 803 | * features can be set under different ADC state conditions |
lypinator | 0:bb348c97df44 | 804 | * (setting possible with ADC enabled without conversion on going, |
lypinator | 0:bb348c97df44 | 805 | * ADC enabled with conversion on going, ...) |
lypinator | 0:bb348c97df44 | 806 | * Each feature can be updated afterwards with a unitary function |
lypinator | 0:bb348c97df44 | 807 | * and potentially with ADC in a different state than disabled, |
lypinator | 0:bb348c97df44 | 808 | * refer to description of each function for setting |
lypinator | 0:bb348c97df44 | 809 | * conditioned to ADC state. |
lypinator | 0:bb348c97df44 | 810 | * @note After using this function, other features must be configured |
lypinator | 0:bb348c97df44 | 811 | * using LL unitary functions. |
lypinator | 0:bb348c97df44 | 812 | * The minimum configuration remaining to be done is: |
lypinator | 0:bb348c97df44 | 813 | * - Set ADC group injected sequencer: |
lypinator | 0:bb348c97df44 | 814 | * map channel on the selected sequencer rank. |
lypinator | 0:bb348c97df44 | 815 | * Refer to function @ref LL_ADC_INJ_SetSequencerRanks(). |
lypinator | 0:bb348c97df44 | 816 | * - Set ADC channel sampling time |
lypinator | 0:bb348c97df44 | 817 | * Refer to function LL_ADC_SetChannelSamplingTime(); |
lypinator | 0:bb348c97df44 | 818 | * @param ADCx ADC instance |
lypinator | 0:bb348c97df44 | 819 | * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure |
lypinator | 0:bb348c97df44 | 820 | * @retval An ErrorStatus enumeration value: |
lypinator | 0:bb348c97df44 | 821 | * - SUCCESS: ADC registers are initialized |
lypinator | 0:bb348c97df44 | 822 | * - ERROR: ADC registers are not initialized |
lypinator | 0:bb348c97df44 | 823 | */ |
lypinator | 0:bb348c97df44 | 824 | ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct) |
lypinator | 0:bb348c97df44 | 825 | { |
lypinator | 0:bb348c97df44 | 826 | ErrorStatus status = SUCCESS; |
lypinator | 0:bb348c97df44 | 827 | |
lypinator | 0:bb348c97df44 | 828 | /* Check the parameters */ |
lypinator | 0:bb348c97df44 | 829 | assert_param(IS_ADC_ALL_INSTANCE(ADCx)); |
lypinator | 0:bb348c97df44 | 830 | assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(ADC_INJ_InitStruct->TriggerSource)); |
lypinator | 0:bb348c97df44 | 831 | assert_param(IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(ADC_INJ_InitStruct->SequencerLength)); |
lypinator | 0:bb348c97df44 | 832 | if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_INJ_SEQ_SCAN_DISABLE) |
lypinator | 0:bb348c97df44 | 833 | { |
lypinator | 0:bb348c97df44 | 834 | assert_param(IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(ADC_INJ_InitStruct->SequencerDiscont)); |
lypinator | 0:bb348c97df44 | 835 | } |
lypinator | 0:bb348c97df44 | 836 | assert_param(IS_LL_ADC_INJ_TRIG_AUTO(ADC_INJ_InitStruct->TrigAuto)); |
lypinator | 0:bb348c97df44 | 837 | |
lypinator | 0:bb348c97df44 | 838 | /* Note: Hardware constraint (refer to description of this function): */ |
lypinator | 0:bb348c97df44 | 839 | /* ADC instance must be disabled. */ |
lypinator | 0:bb348c97df44 | 840 | if(LL_ADC_IsEnabled(ADCx) == 0U) |
lypinator | 0:bb348c97df44 | 841 | { |
lypinator | 0:bb348c97df44 | 842 | /* Configuration of ADC hierarchical scope: */ |
lypinator | 0:bb348c97df44 | 843 | /* - ADC group injected */ |
lypinator | 0:bb348c97df44 | 844 | /* - Set ADC group injected trigger source */ |
lypinator | 0:bb348c97df44 | 845 | /* - Set ADC group injected sequencer length */ |
lypinator | 0:bb348c97df44 | 846 | /* - Set ADC group injected sequencer discontinuous mode */ |
lypinator | 0:bb348c97df44 | 847 | /* - Set ADC group injected conversion trigger: independent or */ |
lypinator | 0:bb348c97df44 | 848 | /* from ADC group regular */ |
lypinator | 0:bb348c97df44 | 849 | /* Note: On this STM32 serie, ADC trigger edge is set when starting */ |
lypinator | 0:bb348c97df44 | 850 | /* ADC conversion. */ |
lypinator | 0:bb348c97df44 | 851 | /* Refer to function @ref LL_ADC_INJ_StartConversionExtTrig(). */ |
lypinator | 0:bb348c97df44 | 852 | if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) |
lypinator | 0:bb348c97df44 | 853 | { |
lypinator | 0:bb348c97df44 | 854 | MODIFY_REG(ADCx->CR1, |
lypinator | 0:bb348c97df44 | 855 | ADC_CR1_JDISCEN |
lypinator | 0:bb348c97df44 | 856 | | ADC_CR1_JAUTO |
lypinator | 0:bb348c97df44 | 857 | , |
lypinator | 0:bb348c97df44 | 858 | ADC_INJ_InitStruct->SequencerDiscont |
lypinator | 0:bb348c97df44 | 859 | | ADC_INJ_InitStruct->TrigAuto |
lypinator | 0:bb348c97df44 | 860 | ); |
lypinator | 0:bb348c97df44 | 861 | } |
lypinator | 0:bb348c97df44 | 862 | else |
lypinator | 0:bb348c97df44 | 863 | { |
lypinator | 0:bb348c97df44 | 864 | MODIFY_REG(ADCx->CR1, |
lypinator | 0:bb348c97df44 | 865 | ADC_CR1_JDISCEN |
lypinator | 0:bb348c97df44 | 866 | | ADC_CR1_JAUTO |
lypinator | 0:bb348c97df44 | 867 | , |
lypinator | 0:bb348c97df44 | 868 | LL_ADC_REG_SEQ_DISCONT_DISABLE |
lypinator | 0:bb348c97df44 | 869 | | ADC_INJ_InitStruct->TrigAuto |
lypinator | 0:bb348c97df44 | 870 | ); |
lypinator | 0:bb348c97df44 | 871 | } |
lypinator | 0:bb348c97df44 | 872 | |
lypinator | 0:bb348c97df44 | 873 | MODIFY_REG(ADCx->CR2, |
lypinator | 0:bb348c97df44 | 874 | ADC_CR2_JEXTSEL |
lypinator | 0:bb348c97df44 | 875 | | ADC_CR2_JEXTEN |
lypinator | 0:bb348c97df44 | 876 | , |
lypinator | 0:bb348c97df44 | 877 | (ADC_INJ_InitStruct->TriggerSource & ADC_CR2_JEXTSEL) |
lypinator | 0:bb348c97df44 | 878 | ); |
lypinator | 0:bb348c97df44 | 879 | |
lypinator | 0:bb348c97df44 | 880 | /* Note: Hardware constraint (refer to description of this function): */ |
lypinator | 0:bb348c97df44 | 881 | /* Note: If ADC instance feature scan mode is disabled */ |
lypinator | 0:bb348c97df44 | 882 | /* (refer to ADC instance initialization structure */ |
lypinator | 0:bb348c97df44 | 883 | /* parameter @ref SequencersScanMode */ |
lypinator | 0:bb348c97df44 | 884 | /* or function @ref LL_ADC_SetSequencersScanMode() ), */ |
lypinator | 0:bb348c97df44 | 885 | /* this parameter is discarded. */ |
lypinator | 0:bb348c97df44 | 886 | LL_ADC_INJ_SetSequencerLength(ADCx, ADC_INJ_InitStruct->SequencerLength); |
lypinator | 0:bb348c97df44 | 887 | } |
lypinator | 0:bb348c97df44 | 888 | else |
lypinator | 0:bb348c97df44 | 889 | { |
lypinator | 0:bb348c97df44 | 890 | /* Initialization error: ADC instance is not disabled. */ |
lypinator | 0:bb348c97df44 | 891 | status = ERROR; |
lypinator | 0:bb348c97df44 | 892 | } |
lypinator | 0:bb348c97df44 | 893 | return status; |
lypinator | 0:bb348c97df44 | 894 | } |
lypinator | 0:bb348c97df44 | 895 | |
lypinator | 0:bb348c97df44 | 896 | /** |
lypinator | 0:bb348c97df44 | 897 | * @brief Set each @ref LL_ADC_INJ_InitTypeDef field to default value. |
lypinator | 0:bb348c97df44 | 898 | * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure |
lypinator | 0:bb348c97df44 | 899 | * whose fields will be set to default values. |
lypinator | 0:bb348c97df44 | 900 | * @retval None |
lypinator | 0:bb348c97df44 | 901 | */ |
lypinator | 0:bb348c97df44 | 902 | void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct) |
lypinator | 0:bb348c97df44 | 903 | { |
lypinator | 0:bb348c97df44 | 904 | /* Set ADC_INJ_InitStruct fields to default values */ |
lypinator | 0:bb348c97df44 | 905 | /* Set fields of ADC group injected */ |
lypinator | 0:bb348c97df44 | 906 | ADC_INJ_InitStruct->TriggerSource = LL_ADC_INJ_TRIG_SOFTWARE; |
lypinator | 0:bb348c97df44 | 907 | ADC_INJ_InitStruct->SequencerLength = LL_ADC_INJ_SEQ_SCAN_DISABLE; |
lypinator | 0:bb348c97df44 | 908 | ADC_INJ_InitStruct->SequencerDiscont = LL_ADC_INJ_SEQ_DISCONT_DISABLE; |
lypinator | 0:bb348c97df44 | 909 | ADC_INJ_InitStruct->TrigAuto = LL_ADC_INJ_TRIG_INDEPENDENT; |
lypinator | 0:bb348c97df44 | 910 | } |
lypinator | 0:bb348c97df44 | 911 | |
lypinator | 0:bb348c97df44 | 912 | /** |
lypinator | 0:bb348c97df44 | 913 | * @} |
lypinator | 0:bb348c97df44 | 914 | */ |
lypinator | 0:bb348c97df44 | 915 | |
lypinator | 0:bb348c97df44 | 916 | /** |
lypinator | 0:bb348c97df44 | 917 | * @} |
lypinator | 0:bb348c97df44 | 918 | */ |
lypinator | 0:bb348c97df44 | 919 | |
lypinator | 0:bb348c97df44 | 920 | /** |
lypinator | 0:bb348c97df44 | 921 | * @} |
lypinator | 0:bb348c97df44 | 922 | */ |
lypinator | 0:bb348c97df44 | 923 | |
lypinator | 0:bb348c97df44 | 924 | #endif /* ADC1 || ADC2 || ADC3 */ |
lypinator | 0:bb348c97df44 | 925 | |
lypinator | 0:bb348c97df44 | 926 | /** |
lypinator | 0:bb348c97df44 | 927 | * @} |
lypinator | 0:bb348c97df44 | 928 | */ |
lypinator | 0:bb348c97df44 | 929 | |
lypinator | 0:bb348c97df44 | 930 | #endif /* USE_FULL_LL_DRIVER */ |
lypinator | 0:bb348c97df44 | 931 | |
lypinator | 0:bb348c97df44 | 932 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |