Initial commit
mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_spi.c@0:bb348c97df44, 2020-09-16 (annotated)
- Committer:
- lypinator
- Date:
- Wed Sep 16 01:11:49 2020 +0000
- Revision:
- 0:bb348c97df44
Added PWM
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
lypinator | 0:bb348c97df44 | 1 | /** |
lypinator | 0:bb348c97df44 | 2 | ****************************************************************************** |
lypinator | 0:bb348c97df44 | 3 | * @file stm32f4xx_hal_spi.c |
lypinator | 0:bb348c97df44 | 4 | * @author MCD Application Team |
lypinator | 0:bb348c97df44 | 5 | * @brief SPI HAL module driver. |
lypinator | 0:bb348c97df44 | 6 | * This file provides firmware functions to manage the following |
lypinator | 0:bb348c97df44 | 7 | * functionalities of the Serial Peripheral Interface (SPI) peripheral: |
lypinator | 0:bb348c97df44 | 8 | * + Initialization and de-initialization functions |
lypinator | 0:bb348c97df44 | 9 | * + IO operation functions |
lypinator | 0:bb348c97df44 | 10 | * + Peripheral Control functions |
lypinator | 0:bb348c97df44 | 11 | * + Peripheral State functions |
lypinator | 0:bb348c97df44 | 12 | * |
lypinator | 0:bb348c97df44 | 13 | @verbatim |
lypinator | 0:bb348c97df44 | 14 | ============================================================================== |
lypinator | 0:bb348c97df44 | 15 | ##### How to use this driver ##### |
lypinator | 0:bb348c97df44 | 16 | ============================================================================== |
lypinator | 0:bb348c97df44 | 17 | [..] |
lypinator | 0:bb348c97df44 | 18 | The SPI HAL driver can be used as follows: |
lypinator | 0:bb348c97df44 | 19 | |
lypinator | 0:bb348c97df44 | 20 | (#) Declare a SPI_HandleTypeDef handle structure, for example: |
lypinator | 0:bb348c97df44 | 21 | SPI_HandleTypeDef hspi; |
lypinator | 0:bb348c97df44 | 22 | |
lypinator | 0:bb348c97df44 | 23 | (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit() API: |
lypinator | 0:bb348c97df44 | 24 | (##) Enable the SPIx interface clock |
lypinator | 0:bb348c97df44 | 25 | (##) SPI pins configuration |
lypinator | 0:bb348c97df44 | 26 | (+++) Enable the clock for the SPI GPIOs |
lypinator | 0:bb348c97df44 | 27 | (+++) Configure these SPI pins as alternate function push-pull |
lypinator | 0:bb348c97df44 | 28 | (##) NVIC configuration if you need to use interrupt process |
lypinator | 0:bb348c97df44 | 29 | (+++) Configure the SPIx interrupt priority |
lypinator | 0:bb348c97df44 | 30 | (+++) Enable the NVIC SPI IRQ handle |
lypinator | 0:bb348c97df44 | 31 | (##) DMA Configuration if you need to use DMA process |
lypinator | 0:bb348c97df44 | 32 | (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive stream |
lypinator | 0:bb348c97df44 | 33 | (+++) Enable the DMAx clock |
lypinator | 0:bb348c97df44 | 34 | (+++) Configure the DMA handle parameters |
lypinator | 0:bb348c97df44 | 35 | (+++) Configure the DMA Tx or Rx stream |
lypinator | 0:bb348c97df44 | 36 | (+++) Associate the initialized hdma_tx handle to the hspi DMA Tx or Rx handle |
lypinator | 0:bb348c97df44 | 37 | (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx stream |
lypinator | 0:bb348c97df44 | 38 | |
lypinator | 0:bb348c97df44 | 39 | (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS |
lypinator | 0:bb348c97df44 | 40 | management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure. |
lypinator | 0:bb348c97df44 | 41 | |
lypinator | 0:bb348c97df44 | 42 | (#) Initialize the SPI registers by calling the HAL_SPI_Init() API: |
lypinator | 0:bb348c97df44 | 43 | (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc) |
lypinator | 0:bb348c97df44 | 44 | by calling the customized HAL_SPI_MspInit() API. |
lypinator | 0:bb348c97df44 | 45 | [..] |
lypinator | 0:bb348c97df44 | 46 | Circular mode restriction: |
lypinator | 0:bb348c97df44 | 47 | (#) The DMA circular mode cannot be used when the SPI is configured in these modes: |
lypinator | 0:bb348c97df44 | 48 | (##) Master 2Lines RxOnly |
lypinator | 0:bb348c97df44 | 49 | (##) Master 1Line Rx |
lypinator | 0:bb348c97df44 | 50 | (#) The CRC feature is not managed when the DMA circular mode is enabled |
lypinator | 0:bb348c97df44 | 51 | (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs |
lypinator | 0:bb348c97df44 | 52 | the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks |
lypinator | 0:bb348c97df44 | 53 | [..] |
lypinator | 0:bb348c97df44 | 54 | Master Receive mode restriction: |
lypinator | 0:bb348c97df44 | 55 | (#) In Master unidirectional receive-only mode (MSTR =1, BIDIMODE=0, RXONLY=0) or |
lypinator | 0:bb348c97df44 | 56 | bidirectional receive mode (MSTR=1, BIDIMODE=1, BIDIOE=0), to ensure that the SPI |
lypinator | 0:bb348c97df44 | 57 | does not initiate a new transfer the following procedure has to be respected: |
lypinator | 0:bb348c97df44 | 58 | (##) HAL_SPI_DeInit() |
lypinator | 0:bb348c97df44 | 59 | (##) HAL_SPI_Init() |
lypinator | 0:bb348c97df44 | 60 | |
lypinator | 0:bb348c97df44 | 61 | @endverbatim |
lypinator | 0:bb348c97df44 | 62 | |
lypinator | 0:bb348c97df44 | 63 | Using the HAL it is not possible to reach all supported SPI frequency with the differents SPI Modes, |
lypinator | 0:bb348c97df44 | 64 | the following tables resume the max SPI frequency reached with data size 8bits/16bits, |
lypinator | 0:bb348c97df44 | 65 | according to frequency used on APBx Peripheral Clock (fPCLK) used by the SPI instance : |
lypinator | 0:bb348c97df44 | 66 | |
lypinator | 0:bb348c97df44 | 67 | DataSize = SPI_DATASIZE_8BIT: |
lypinator | 0:bb348c97df44 | 68 | +----------------------------------------------------------------------------------------------+ |
lypinator | 0:bb348c97df44 | 69 | | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line | |
lypinator | 0:bb348c97df44 | 70 | | Process | Tranfert mode |---------------------|----------------------|----------------------| |
lypinator | 0:bb348c97df44 | 71 | | | | Master | Slave | Master | Slave | Master | Slave | |
lypinator | 0:bb348c97df44 | 72 | |==============================================================================================| |
lypinator | 0:bb348c97df44 | 73 | | T | Polling | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA | |
lypinator | 0:bb348c97df44 | 74 | | X |----------------|----------|----------|-----------|----------|-----------|----------| |
lypinator | 0:bb348c97df44 | 75 | | / | Interrupt | Fpclk/4 | Fpclk/8 | NA | NA | NA | NA | |
lypinator | 0:bb348c97df44 | 76 | | R |----------------|----------|----------|-----------|----------|-----------|----------| |
lypinator | 0:bb348c97df44 | 77 | | X | DMA | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA | |
lypinator | 0:bb348c97df44 | 78 | |=========|================|==========|==========|===========|==========|===========|==========| |
lypinator | 0:bb348c97df44 | 79 | | | Polling | Fpclk/2 | Fpclk/2 | Fpclk/64 | Fpclk/2 | Fpclk/64 | Fpclk/2 | |
lypinator | 0:bb348c97df44 | 80 | | |----------------|----------|----------|-----------|----------|-----------|----------| |
lypinator | 0:bb348c97df44 | 81 | | R | Interrupt | Fpclk/8 | Fpclk/8 | Fpclk/64 | Fpclk/2 | Fpclk/64 | Fpclk/2 | |
lypinator | 0:bb348c97df44 | 82 | | X |----------------|----------|----------|-----------|----------|-----------|----------| |
lypinator | 0:bb348c97df44 | 83 | | | DMA | Fpclk/2 | Fpclk/2 | Fpclk/64 | Fpclk/2 | Fpclk/128 | Fpclk/2 | |
lypinator | 0:bb348c97df44 | 84 | |=========|================|==========|==========|===========|==========|===========|==========| |
lypinator | 0:bb348c97df44 | 85 | | | Polling | Fpclk/2 | Fpclk/4 | NA | NA | Fpclk/2 | Fpclk/64 | |
lypinator | 0:bb348c97df44 | 86 | | |----------------|----------|----------|-----------|----------|-----------|----------| |
lypinator | 0:bb348c97df44 | 87 | | T | Interrupt | Fpclk/2 | Fpclk/4 | NA | NA | Fpclk/2 | Fpclk/64 | |
lypinator | 0:bb348c97df44 | 88 | | X |----------------|----------|----------|-----------|----------|-----------|----------| |
lypinator | 0:bb348c97df44 | 89 | | | DMA | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/2 | Fpclk/128| |
lypinator | 0:bb348c97df44 | 90 | +----------------------------------------------------------------------------------------------+ |
lypinator | 0:bb348c97df44 | 91 | |
lypinator | 0:bb348c97df44 | 92 | DataSize = SPI_DATASIZE_16BIT: |
lypinator | 0:bb348c97df44 | 93 | +----------------------------------------------------------------------------------------------+ |
lypinator | 0:bb348c97df44 | 94 | | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line | |
lypinator | 0:bb348c97df44 | 95 | | Process | Tranfert mode |---------------------|----------------------|----------------------| |
lypinator | 0:bb348c97df44 | 96 | | | | Master | Slave | Master | Slave | Master | Slave | |
lypinator | 0:bb348c97df44 | 97 | |==============================================================================================| |
lypinator | 0:bb348c97df44 | 98 | | T | Polling | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA | |
lypinator | 0:bb348c97df44 | 99 | | X |----------------|----------|----------|-----------|----------|-----------|----------| |
lypinator | 0:bb348c97df44 | 100 | | / | Interrupt | Fpclk/4 | Fpclk/4 | NA | NA | NA | NA | |
lypinator | 0:bb348c97df44 | 101 | | R |----------------|----------|----------|-----------|----------|-----------|----------| |
lypinator | 0:bb348c97df44 | 102 | | X | DMA | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA | |
lypinator | 0:bb348c97df44 | 103 | |=========|================|==========|==========|===========|==========|===========|==========| |
lypinator | 0:bb348c97df44 | 104 | | | Polling | Fpclk/2 | Fpclk/2 | Fpclk/64 | Fpclk/2 | Fpclk/32 | Fpclk/2 | |
lypinator | 0:bb348c97df44 | 105 | | |----------------|----------|----------|-----------|----------|-----------|----------| |
lypinator | 0:bb348c97df44 | 106 | | R | Interrupt | Fpclk/4 | Fpclk/4 | Fpclk/64 | Fpclk/2 | Fpclk/64 | Fpclk/2 | |
lypinator | 0:bb348c97df44 | 107 | | X |----------------|----------|----------|-----------|----------|-----------|----------| |
lypinator | 0:bb348c97df44 | 108 | | | DMA | Fpclk/2 | Fpclk/2 | Fpclk/64 | Fpclk/2 | Fpclk/128 | Fpclk/2 | |
lypinator | 0:bb348c97df44 | 109 | |=========|================|==========|==========|===========|==========|===========|==========| |
lypinator | 0:bb348c97df44 | 110 | | | Polling | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/2 | Fpclk/32 | |
lypinator | 0:bb348c97df44 | 111 | | |----------------|----------|----------|-----------|----------|-----------|----------| |
lypinator | 0:bb348c97df44 | 112 | | T | Interrupt | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/2 | Fpclk/64 | |
lypinator | 0:bb348c97df44 | 113 | | X |----------------|----------|----------|-----------|----------|-----------|----------| |
lypinator | 0:bb348c97df44 | 114 | | | DMA | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/2 | Fpclk/128| |
lypinator | 0:bb348c97df44 | 115 | +----------------------------------------------------------------------------------------------+ |
lypinator | 0:bb348c97df44 | 116 | [..] |
lypinator | 0:bb348c97df44 | 117 | (@) The max SPI frequency depend on SPI data size (8bits, 16bits), |
lypinator | 0:bb348c97df44 | 118 | SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA). |
lypinator | 0:bb348c97df44 | 119 | (@) |
lypinator | 0:bb348c97df44 | 120 | (+@) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA() |
lypinator | 0:bb348c97df44 | 121 | (+@) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA() |
lypinator | 0:bb348c97df44 | 122 | (+@) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA() |
lypinator | 0:bb348c97df44 | 123 | ****************************************************************************** |
lypinator | 0:bb348c97df44 | 124 | * @attention |
lypinator | 0:bb348c97df44 | 125 | * |
lypinator | 0:bb348c97df44 | 126 | * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> |
lypinator | 0:bb348c97df44 | 127 | * |
lypinator | 0:bb348c97df44 | 128 | * Redistribution and use in source and binary forms, with or without modification, |
lypinator | 0:bb348c97df44 | 129 | * are permitted provided that the following conditions are met: |
lypinator | 0:bb348c97df44 | 130 | * 1. Redistributions of source code must retain the above copyright notice, |
lypinator | 0:bb348c97df44 | 131 | * this list of conditions and the following disclaimer. |
lypinator | 0:bb348c97df44 | 132 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
lypinator | 0:bb348c97df44 | 133 | * this list of conditions and the following disclaimer in the documentation |
lypinator | 0:bb348c97df44 | 134 | * and/or other materials provided with the distribution. |
lypinator | 0:bb348c97df44 | 135 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
lypinator | 0:bb348c97df44 | 136 | * may be used to endorse or promote products derived from this software |
lypinator | 0:bb348c97df44 | 137 | * without specific prior written permission. |
lypinator | 0:bb348c97df44 | 138 | * |
lypinator | 0:bb348c97df44 | 139 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
lypinator | 0:bb348c97df44 | 140 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
lypinator | 0:bb348c97df44 | 141 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
lypinator | 0:bb348c97df44 | 142 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
lypinator | 0:bb348c97df44 | 143 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
lypinator | 0:bb348c97df44 | 144 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
lypinator | 0:bb348c97df44 | 145 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
lypinator | 0:bb348c97df44 | 146 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
lypinator | 0:bb348c97df44 | 147 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
lypinator | 0:bb348c97df44 | 148 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
lypinator | 0:bb348c97df44 | 149 | * |
lypinator | 0:bb348c97df44 | 150 | ****************************************************************************** |
lypinator | 0:bb348c97df44 | 151 | */ |
lypinator | 0:bb348c97df44 | 152 | |
lypinator | 0:bb348c97df44 | 153 | /* Includes ------------------------------------------------------------------*/ |
lypinator | 0:bb348c97df44 | 154 | #include "stm32f4xx_hal.h" |
lypinator | 0:bb348c97df44 | 155 | |
lypinator | 0:bb348c97df44 | 156 | /** @addtogroup STM32F4xx_HAL_Driver |
lypinator | 0:bb348c97df44 | 157 | * @{ |
lypinator | 0:bb348c97df44 | 158 | */ |
lypinator | 0:bb348c97df44 | 159 | /** @defgroup SPI SPI |
lypinator | 0:bb348c97df44 | 160 | * @brief SPI HAL module driver |
lypinator | 0:bb348c97df44 | 161 | * @{ |
lypinator | 0:bb348c97df44 | 162 | */ |
lypinator | 0:bb348c97df44 | 163 | #ifdef HAL_SPI_MODULE_ENABLED |
lypinator | 0:bb348c97df44 | 164 | |
lypinator | 0:bb348c97df44 | 165 | /* Private typedef -----------------------------------------------------------*/ |
lypinator | 0:bb348c97df44 | 166 | /* Private defines -----------------------------------------------------------*/ |
lypinator | 0:bb348c97df44 | 167 | /** @defgroup SPI_Private_Constants SPI Private Constants |
lypinator | 0:bb348c97df44 | 168 | * @{ |
lypinator | 0:bb348c97df44 | 169 | */ |
lypinator | 0:bb348c97df44 | 170 | #define SPI_DEFAULT_TIMEOUT 100U |
lypinator | 0:bb348c97df44 | 171 | /** |
lypinator | 0:bb348c97df44 | 172 | * @} |
lypinator | 0:bb348c97df44 | 173 | */ |
lypinator | 0:bb348c97df44 | 174 | |
lypinator | 0:bb348c97df44 | 175 | /* Private macros ------------------------------------------------------------*/ |
lypinator | 0:bb348c97df44 | 176 | /* Private variables ---------------------------------------------------------*/ |
lypinator | 0:bb348c97df44 | 177 | /* Private function prototypes -----------------------------------------------*/ |
lypinator | 0:bb348c97df44 | 178 | /** @addtogroup SPI_Private_Functions |
lypinator | 0:bb348c97df44 | 179 | * @{ |
lypinator | 0:bb348c97df44 | 180 | */ |
lypinator | 0:bb348c97df44 | 181 | static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma); |
lypinator | 0:bb348c97df44 | 182 | static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma); |
lypinator | 0:bb348c97df44 | 183 | static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma); |
lypinator | 0:bb348c97df44 | 184 | static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma); |
lypinator | 0:bb348c97df44 | 185 | static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma); |
lypinator | 0:bb348c97df44 | 186 | static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma); |
lypinator | 0:bb348c97df44 | 187 | static void SPI_DMAError(DMA_HandleTypeDef *hdma); |
lypinator | 0:bb348c97df44 | 188 | static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma); |
lypinator | 0:bb348c97df44 | 189 | static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma); |
lypinator | 0:bb348c97df44 | 190 | static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma); |
lypinator | 0:bb348c97df44 | 191 | static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout, uint32_t Tickstart); |
lypinator | 0:bb348c97df44 | 192 | /* MBED */ |
lypinator | 0:bb348c97df44 | 193 | static HAL_StatusTypeDef SPI_WaitTXEFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart); |
lypinator | 0:bb348c97df44 | 194 | /* MBED */ |
lypinator | 0:bb348c97df44 | 195 | static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi); |
lypinator | 0:bb348c97df44 | 196 | static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi); |
lypinator | 0:bb348c97df44 | 197 | static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi); |
lypinator | 0:bb348c97df44 | 198 | static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi); |
lypinator | 0:bb348c97df44 | 199 | static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi); |
lypinator | 0:bb348c97df44 | 200 | static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi); |
lypinator | 0:bb348c97df44 | 201 | static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi); |
lypinator | 0:bb348c97df44 | 202 | static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi); |
lypinator | 0:bb348c97df44 | 203 | #if (USE_SPI_CRC != 0U) |
lypinator | 0:bb348c97df44 | 204 | static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi); |
lypinator | 0:bb348c97df44 | 205 | static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi); |
lypinator | 0:bb348c97df44 | 206 | static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi); |
lypinator | 0:bb348c97df44 | 207 | static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi); |
lypinator | 0:bb348c97df44 | 208 | #endif /* USE_SPI_CRC */ |
lypinator | 0:bb348c97df44 | 209 | static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi); |
lypinator | 0:bb348c97df44 | 210 | static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi); |
lypinator | 0:bb348c97df44 | 211 | static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi); |
lypinator | 0:bb348c97df44 | 212 | static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi); |
lypinator | 0:bb348c97df44 | 213 | static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi); |
lypinator | 0:bb348c97df44 | 214 | static HAL_StatusTypeDef SPI_CheckFlag_BSY(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart); |
lypinator | 0:bb348c97df44 | 215 | /** |
lypinator | 0:bb348c97df44 | 216 | * @} |
lypinator | 0:bb348c97df44 | 217 | */ |
lypinator | 0:bb348c97df44 | 218 | |
lypinator | 0:bb348c97df44 | 219 | /* Exported functions --------------------------------------------------------*/ |
lypinator | 0:bb348c97df44 | 220 | /** @defgroup SPI_Exported_Functions SPI Exported Functions |
lypinator | 0:bb348c97df44 | 221 | * @{ |
lypinator | 0:bb348c97df44 | 222 | */ |
lypinator | 0:bb348c97df44 | 223 | |
lypinator | 0:bb348c97df44 | 224 | /** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions |
lypinator | 0:bb348c97df44 | 225 | * @brief Initialization and Configuration functions |
lypinator | 0:bb348c97df44 | 226 | * |
lypinator | 0:bb348c97df44 | 227 | @verbatim |
lypinator | 0:bb348c97df44 | 228 | =============================================================================== |
lypinator | 0:bb348c97df44 | 229 | ##### Initialization and de-initialization functions ##### |
lypinator | 0:bb348c97df44 | 230 | =============================================================================== |
lypinator | 0:bb348c97df44 | 231 | [..] This subsection provides a set of functions allowing to initialize and |
lypinator | 0:bb348c97df44 | 232 | de-initialize the SPIx peripheral: |
lypinator | 0:bb348c97df44 | 233 | |
lypinator | 0:bb348c97df44 | 234 | (+) User must implement HAL_SPI_MspInit() function in which he configures |
lypinator | 0:bb348c97df44 | 235 | all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ). |
lypinator | 0:bb348c97df44 | 236 | |
lypinator | 0:bb348c97df44 | 237 | (+) Call the function HAL_SPI_Init() to configure the selected device with |
lypinator | 0:bb348c97df44 | 238 | the selected configuration: |
lypinator | 0:bb348c97df44 | 239 | (++) Mode |
lypinator | 0:bb348c97df44 | 240 | (++) Direction |
lypinator | 0:bb348c97df44 | 241 | (++) Data Size |
lypinator | 0:bb348c97df44 | 242 | (++) Clock Polarity and Phase |
lypinator | 0:bb348c97df44 | 243 | (++) NSS Management |
lypinator | 0:bb348c97df44 | 244 | (++) BaudRate Prescaler |
lypinator | 0:bb348c97df44 | 245 | (++) FirstBit |
lypinator | 0:bb348c97df44 | 246 | (++) TIMode |
lypinator | 0:bb348c97df44 | 247 | (++) CRC Calculation |
lypinator | 0:bb348c97df44 | 248 | (++) CRC Polynomial if CRC enabled |
lypinator | 0:bb348c97df44 | 249 | |
lypinator | 0:bb348c97df44 | 250 | (+) Call the function HAL_SPI_DeInit() to restore the default configuration |
lypinator | 0:bb348c97df44 | 251 | of the selected SPIx peripheral. |
lypinator | 0:bb348c97df44 | 252 | |
lypinator | 0:bb348c97df44 | 253 | @endverbatim |
lypinator | 0:bb348c97df44 | 254 | * @{ |
lypinator | 0:bb348c97df44 | 255 | */ |
lypinator | 0:bb348c97df44 | 256 | |
lypinator | 0:bb348c97df44 | 257 | /** |
lypinator | 0:bb348c97df44 | 258 | * @brief Initialize the SPI according to the specified parameters |
lypinator | 0:bb348c97df44 | 259 | * in the SPI_InitTypeDef and initialize the associated handle. |
lypinator | 0:bb348c97df44 | 260 | * @param hspi pointer to a SPI_HandleTypeDef structure that contains |
lypinator | 0:bb348c97df44 | 261 | * the configuration information for SPI module. |
lypinator | 0:bb348c97df44 | 262 | * @retval HAL status |
lypinator | 0:bb348c97df44 | 263 | */ |
lypinator | 0:bb348c97df44 | 264 | HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) |
lypinator | 0:bb348c97df44 | 265 | { |
lypinator | 0:bb348c97df44 | 266 | /* Check the SPI handle allocation */ |
lypinator | 0:bb348c97df44 | 267 | if(hspi == NULL) |
lypinator | 0:bb348c97df44 | 268 | { |
lypinator | 0:bb348c97df44 | 269 | return HAL_ERROR; |
lypinator | 0:bb348c97df44 | 270 | } |
lypinator | 0:bb348c97df44 | 271 | |
lypinator | 0:bb348c97df44 | 272 | /* Check the parameters */ |
lypinator | 0:bb348c97df44 | 273 | assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance)); |
lypinator | 0:bb348c97df44 | 274 | assert_param(IS_SPI_MODE(hspi->Init.Mode)); |
lypinator | 0:bb348c97df44 | 275 | assert_param(IS_SPI_DIRECTION(hspi->Init.Direction)); |
lypinator | 0:bb348c97df44 | 276 | assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize)); |
lypinator | 0:bb348c97df44 | 277 | assert_param(IS_SPI_NSS(hspi->Init.NSS)); |
lypinator | 0:bb348c97df44 | 278 | assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); |
lypinator | 0:bb348c97df44 | 279 | assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit)); |
lypinator | 0:bb348c97df44 | 280 | assert_param(IS_SPI_TIMODE(hspi->Init.TIMode)); |
lypinator | 0:bb348c97df44 | 281 | if(hspi->Init.TIMode == SPI_TIMODE_DISABLE) |
lypinator | 0:bb348c97df44 | 282 | { |
lypinator | 0:bb348c97df44 | 283 | assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity)); |
lypinator | 0:bb348c97df44 | 284 | assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase)); |
lypinator | 0:bb348c97df44 | 285 | } |
lypinator | 0:bb348c97df44 | 286 | #if (USE_SPI_CRC != 0U) |
lypinator | 0:bb348c97df44 | 287 | assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation)); |
lypinator | 0:bb348c97df44 | 288 | if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) |
lypinator | 0:bb348c97df44 | 289 | { |
lypinator | 0:bb348c97df44 | 290 | assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial)); |
lypinator | 0:bb348c97df44 | 291 | } |
lypinator | 0:bb348c97df44 | 292 | #else |
lypinator | 0:bb348c97df44 | 293 | hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; |
lypinator | 0:bb348c97df44 | 294 | #endif /* USE_SPI_CRC */ |
lypinator | 0:bb348c97df44 | 295 | |
lypinator | 0:bb348c97df44 | 296 | if(hspi->State == HAL_SPI_STATE_RESET) |
lypinator | 0:bb348c97df44 | 297 | { |
lypinator | 0:bb348c97df44 | 298 | /* Allocate lock resource and initialize it */ |
lypinator | 0:bb348c97df44 | 299 | hspi->Lock = HAL_UNLOCKED; |
lypinator | 0:bb348c97df44 | 300 | |
lypinator | 0:bb348c97df44 | 301 | /* Init the low level hardware : GPIO, CLOCK, NVIC... */ |
lypinator | 0:bb348c97df44 | 302 | HAL_SPI_MspInit(hspi); |
lypinator | 0:bb348c97df44 | 303 | } |
lypinator | 0:bb348c97df44 | 304 | |
lypinator | 0:bb348c97df44 | 305 | hspi->State = HAL_SPI_STATE_BUSY; |
lypinator | 0:bb348c97df44 | 306 | |
lypinator | 0:bb348c97df44 | 307 | /* Disable the selected SPI peripheral */ |
lypinator | 0:bb348c97df44 | 308 | __HAL_SPI_DISABLE(hspi); |
lypinator | 0:bb348c97df44 | 309 | |
lypinator | 0:bb348c97df44 | 310 | /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/ |
lypinator | 0:bb348c97df44 | 311 | /* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management, |
lypinator | 0:bb348c97df44 | 312 | Communication speed, First bit and CRC calculation state */ |
lypinator | 0:bb348c97df44 | 313 | WRITE_REG(hspi->Instance->CR1, (hspi->Init.Mode | hspi->Init.Direction | hspi->Init.DataSize | |
lypinator | 0:bb348c97df44 | 314 | hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) | |
lypinator | 0:bb348c97df44 | 315 | hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit | hspi->Init.CRCCalculation) ); |
lypinator | 0:bb348c97df44 | 316 | |
lypinator | 0:bb348c97df44 | 317 | /* Configure : NSS management */ |
lypinator | 0:bb348c97df44 | 318 | WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | hspi->Init.TIMode)); |
lypinator | 0:bb348c97df44 | 319 | |
lypinator | 0:bb348c97df44 | 320 | #if (USE_SPI_CRC != 0U) |
lypinator | 0:bb348c97df44 | 321 | /*---------------------------- SPIx CRCPOLY Configuration ------------------*/ |
lypinator | 0:bb348c97df44 | 322 | /* Configure : CRC Polynomial */ |
lypinator | 0:bb348c97df44 | 323 | if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) |
lypinator | 0:bb348c97df44 | 324 | { |
lypinator | 0:bb348c97df44 | 325 | WRITE_REG(hspi->Instance->CRCPR, hspi->Init.CRCPolynomial); |
lypinator | 0:bb348c97df44 | 326 | } |
lypinator | 0:bb348c97df44 | 327 | #endif /* USE_SPI_CRC */ |
lypinator | 0:bb348c97df44 | 328 | |
lypinator | 0:bb348c97df44 | 329 | #if defined(SPI_I2SCFGR_I2SMOD) |
lypinator | 0:bb348c97df44 | 330 | /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */ |
lypinator | 0:bb348c97df44 | 331 | CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD); |
lypinator | 0:bb348c97df44 | 332 | #endif /* USE_SPI_CRC */ |
lypinator | 0:bb348c97df44 | 333 | |
lypinator | 0:bb348c97df44 | 334 | hspi->ErrorCode = HAL_SPI_ERROR_NONE; |
lypinator | 0:bb348c97df44 | 335 | hspi->State = HAL_SPI_STATE_READY; |
lypinator | 0:bb348c97df44 | 336 | |
lypinator | 0:bb348c97df44 | 337 | return HAL_OK; |
lypinator | 0:bb348c97df44 | 338 | } |
lypinator | 0:bb348c97df44 | 339 | |
lypinator | 0:bb348c97df44 | 340 | /** |
lypinator | 0:bb348c97df44 | 341 | * @brief De Initialize the SPI peripheral. |
lypinator | 0:bb348c97df44 | 342 | * @param hspi pointer to a SPI_HandleTypeDef structure that contains |
lypinator | 0:bb348c97df44 | 343 | * the configuration information for SPI module. |
lypinator | 0:bb348c97df44 | 344 | * @retval HAL status |
lypinator | 0:bb348c97df44 | 345 | */ |
lypinator | 0:bb348c97df44 | 346 | HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi) |
lypinator | 0:bb348c97df44 | 347 | { |
lypinator | 0:bb348c97df44 | 348 | /* Check the SPI handle allocation */ |
lypinator | 0:bb348c97df44 | 349 | if(hspi == NULL) |
lypinator | 0:bb348c97df44 | 350 | { |
lypinator | 0:bb348c97df44 | 351 | return HAL_ERROR; |
lypinator | 0:bb348c97df44 | 352 | } |
lypinator | 0:bb348c97df44 | 353 | |
lypinator | 0:bb348c97df44 | 354 | /* Check SPI Instance parameter */ |
lypinator | 0:bb348c97df44 | 355 | assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance)); |
lypinator | 0:bb348c97df44 | 356 | |
lypinator | 0:bb348c97df44 | 357 | hspi->State = HAL_SPI_STATE_BUSY; |
lypinator | 0:bb348c97df44 | 358 | |
lypinator | 0:bb348c97df44 | 359 | /* Disable the SPI Peripheral Clock */ |
lypinator | 0:bb348c97df44 | 360 | __HAL_SPI_DISABLE(hspi); |
lypinator | 0:bb348c97df44 | 361 | |
lypinator | 0:bb348c97df44 | 362 | /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */ |
lypinator | 0:bb348c97df44 | 363 | HAL_SPI_MspDeInit(hspi); |
lypinator | 0:bb348c97df44 | 364 | |
lypinator | 0:bb348c97df44 | 365 | hspi->ErrorCode = HAL_SPI_ERROR_NONE; |
lypinator | 0:bb348c97df44 | 366 | hspi->State = HAL_SPI_STATE_RESET; |
lypinator | 0:bb348c97df44 | 367 | |
lypinator | 0:bb348c97df44 | 368 | /* Release Lock */ |
lypinator | 0:bb348c97df44 | 369 | __HAL_UNLOCK(hspi); |
lypinator | 0:bb348c97df44 | 370 | |
lypinator | 0:bb348c97df44 | 371 | return HAL_OK; |
lypinator | 0:bb348c97df44 | 372 | } |
lypinator | 0:bb348c97df44 | 373 | |
lypinator | 0:bb348c97df44 | 374 | /** |
lypinator | 0:bb348c97df44 | 375 | * @brief Initialize the SPI MSP. |
lypinator | 0:bb348c97df44 | 376 | * @param hspi pointer to a SPI_HandleTypeDef structure that contains |
lypinator | 0:bb348c97df44 | 377 | * the configuration information for SPI module. |
lypinator | 0:bb348c97df44 | 378 | * @retval None |
lypinator | 0:bb348c97df44 | 379 | */ |
lypinator | 0:bb348c97df44 | 380 | __weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi) |
lypinator | 0:bb348c97df44 | 381 | { |
lypinator | 0:bb348c97df44 | 382 | /* Prevent unused argument(s) compilation warning */ |
lypinator | 0:bb348c97df44 | 383 | UNUSED(hspi); |
lypinator | 0:bb348c97df44 | 384 | /* NOTE : This function should not be modified, when the callback is needed, |
lypinator | 0:bb348c97df44 | 385 | the HAL_SPI_MspInit should be implemented in the user file |
lypinator | 0:bb348c97df44 | 386 | */ |
lypinator | 0:bb348c97df44 | 387 | } |
lypinator | 0:bb348c97df44 | 388 | |
lypinator | 0:bb348c97df44 | 389 | /** |
lypinator | 0:bb348c97df44 | 390 | * @brief De-Initialize the SPI MSP. |
lypinator | 0:bb348c97df44 | 391 | * @param hspi pointer to a SPI_HandleTypeDef structure that contains |
lypinator | 0:bb348c97df44 | 392 | * the configuration information for SPI module. |
lypinator | 0:bb348c97df44 | 393 | * @retval None |
lypinator | 0:bb348c97df44 | 394 | */ |
lypinator | 0:bb348c97df44 | 395 | __weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi) |
lypinator | 0:bb348c97df44 | 396 | { |
lypinator | 0:bb348c97df44 | 397 | /* Prevent unused argument(s) compilation warning */ |
lypinator | 0:bb348c97df44 | 398 | UNUSED(hspi); |
lypinator | 0:bb348c97df44 | 399 | /* NOTE : This function should not be modified, when the callback is needed, |
lypinator | 0:bb348c97df44 | 400 | the HAL_SPI_MspDeInit should be implemented in the user file |
lypinator | 0:bb348c97df44 | 401 | */ |
lypinator | 0:bb348c97df44 | 402 | } |
lypinator | 0:bb348c97df44 | 403 | |
lypinator | 0:bb348c97df44 | 404 | /** |
lypinator | 0:bb348c97df44 | 405 | * @} |
lypinator | 0:bb348c97df44 | 406 | */ |
lypinator | 0:bb348c97df44 | 407 | |
lypinator | 0:bb348c97df44 | 408 | /** @defgroup SPI_Exported_Functions_Group2 IO operation functions |
lypinator | 0:bb348c97df44 | 409 | * @brief Data transfers functions |
lypinator | 0:bb348c97df44 | 410 | * |
lypinator | 0:bb348c97df44 | 411 | @verbatim |
lypinator | 0:bb348c97df44 | 412 | ============================================================================== |
lypinator | 0:bb348c97df44 | 413 | ##### IO operation functions ##### |
lypinator | 0:bb348c97df44 | 414 | =============================================================================== |
lypinator | 0:bb348c97df44 | 415 | [..] |
lypinator | 0:bb348c97df44 | 416 | This subsection provides a set of functions allowing to manage the SPI |
lypinator | 0:bb348c97df44 | 417 | data transfers. |
lypinator | 0:bb348c97df44 | 418 | |
lypinator | 0:bb348c97df44 | 419 | [..] The SPI supports master and slave mode : |
lypinator | 0:bb348c97df44 | 420 | |
lypinator | 0:bb348c97df44 | 421 | (#) There are two modes of transfer: |
lypinator | 0:bb348c97df44 | 422 | (++) Blocking mode: The communication is performed in polling mode. |
lypinator | 0:bb348c97df44 | 423 | The HAL status of all data processing is returned by the same function |
lypinator | 0:bb348c97df44 | 424 | after finishing transfer. |
lypinator | 0:bb348c97df44 | 425 | (++) No-Blocking mode: The communication is performed using Interrupts |
lypinator | 0:bb348c97df44 | 426 | or DMA, These APIs return the HAL status. |
lypinator | 0:bb348c97df44 | 427 | The end of the data processing will be indicated through the |
lypinator | 0:bb348c97df44 | 428 | dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when |
lypinator | 0:bb348c97df44 | 429 | using DMA mode. |
lypinator | 0:bb348c97df44 | 430 | The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks |
lypinator | 0:bb348c97df44 | 431 | will be executed respectively at the end of the transmit or Receive process |
lypinator | 0:bb348c97df44 | 432 | The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected |
lypinator | 0:bb348c97df44 | 433 | |
lypinator | 0:bb348c97df44 | 434 | (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA) |
lypinator | 0:bb348c97df44 | 435 | exist for 1Line (simplex) and 2Lines (full duplex) modes. |
lypinator | 0:bb348c97df44 | 436 | |
lypinator | 0:bb348c97df44 | 437 | @endverbatim |
lypinator | 0:bb348c97df44 | 438 | * @{ |
lypinator | 0:bb348c97df44 | 439 | */ |
lypinator | 0:bb348c97df44 | 440 | |
lypinator | 0:bb348c97df44 | 441 | /** |
lypinator | 0:bb348c97df44 | 442 | * @brief Transmit an amount of data in blocking mode. |
lypinator | 0:bb348c97df44 | 443 | * @param hspi pointer to a SPI_HandleTypeDef structure that contains |
lypinator | 0:bb348c97df44 | 444 | * the configuration information for SPI module. |
lypinator | 0:bb348c97df44 | 445 | * @param pData pointer to data buffer |
lypinator | 0:bb348c97df44 | 446 | * @param Size amount of data to be sent |
lypinator | 0:bb348c97df44 | 447 | * @param Timeout Timeout duration |
lypinator | 0:bb348c97df44 | 448 | * @retval HAL status |
lypinator | 0:bb348c97df44 | 449 | */ |
lypinator | 0:bb348c97df44 | 450 | HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) |
lypinator | 0:bb348c97df44 | 451 | { |
lypinator | 0:bb348c97df44 | 452 | uint32_t tickstart = 0U; |
lypinator | 0:bb348c97df44 | 453 | HAL_StatusTypeDef errorcode = HAL_OK; |
lypinator | 0:bb348c97df44 | 454 | |
lypinator | 0:bb348c97df44 | 455 | /* Check Direction parameter */ |
lypinator | 0:bb348c97df44 | 456 | assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); |
lypinator | 0:bb348c97df44 | 457 | |
lypinator | 0:bb348c97df44 | 458 | /* Process Locked */ |
lypinator | 0:bb348c97df44 | 459 | __HAL_LOCK(hspi); |
lypinator | 0:bb348c97df44 | 460 | |
lypinator | 0:bb348c97df44 | 461 | /* Init tickstart for timeout management*/ |
lypinator | 0:bb348c97df44 | 462 | tickstart = HAL_GetTick(); |
lypinator | 0:bb348c97df44 | 463 | |
lypinator | 0:bb348c97df44 | 464 | if(hspi->State != HAL_SPI_STATE_READY) |
lypinator | 0:bb348c97df44 | 465 | { |
lypinator | 0:bb348c97df44 | 466 | errorcode = HAL_BUSY; |
lypinator | 0:bb348c97df44 | 467 | goto error; |
lypinator | 0:bb348c97df44 | 468 | } |
lypinator | 0:bb348c97df44 | 469 | |
lypinator | 0:bb348c97df44 | 470 | if((pData == NULL ) || (Size == 0)) |
lypinator | 0:bb348c97df44 | 471 | { |
lypinator | 0:bb348c97df44 | 472 | errorcode = HAL_ERROR; |
lypinator | 0:bb348c97df44 | 473 | goto error; |
lypinator | 0:bb348c97df44 | 474 | } |
lypinator | 0:bb348c97df44 | 475 | |
lypinator | 0:bb348c97df44 | 476 | /* Set the transaction information */ |
lypinator | 0:bb348c97df44 | 477 | hspi->State = HAL_SPI_STATE_BUSY_TX; |
lypinator | 0:bb348c97df44 | 478 | hspi->ErrorCode = HAL_SPI_ERROR_NONE; |
lypinator | 0:bb348c97df44 | 479 | hspi->pTxBuffPtr = (uint8_t *)pData; |
lypinator | 0:bb348c97df44 | 480 | hspi->TxXferSize = Size; |
lypinator | 0:bb348c97df44 | 481 | hspi->TxXferCount = Size; |
lypinator | 0:bb348c97df44 | 482 | |
lypinator | 0:bb348c97df44 | 483 | /*Init field not used in handle to zero */ |
lypinator | 0:bb348c97df44 | 484 | hspi->pRxBuffPtr = (uint8_t *)NULL; |
lypinator | 0:bb348c97df44 | 485 | hspi->RxXferSize = 0U; |
lypinator | 0:bb348c97df44 | 486 | hspi->RxXferCount = 0U; |
lypinator | 0:bb348c97df44 | 487 | hspi->TxISR = NULL; |
lypinator | 0:bb348c97df44 | 488 | hspi->RxISR = NULL; |
lypinator | 0:bb348c97df44 | 489 | |
lypinator | 0:bb348c97df44 | 490 | /* Configure communication direction : 1Line */ |
lypinator | 0:bb348c97df44 | 491 | if(hspi->Init.Direction == SPI_DIRECTION_1LINE) |
lypinator | 0:bb348c97df44 | 492 | { |
lypinator | 0:bb348c97df44 | 493 | SPI_1LINE_TX(hspi); |
lypinator | 0:bb348c97df44 | 494 | } |
lypinator | 0:bb348c97df44 | 495 | |
lypinator | 0:bb348c97df44 | 496 | #if (USE_SPI_CRC != 0U) |
lypinator | 0:bb348c97df44 | 497 | /* Reset CRC Calculation */ |
lypinator | 0:bb348c97df44 | 498 | if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) |
lypinator | 0:bb348c97df44 | 499 | { |
lypinator | 0:bb348c97df44 | 500 | SPI_RESET_CRC(hspi); |
lypinator | 0:bb348c97df44 | 501 | } |
lypinator | 0:bb348c97df44 | 502 | #endif /* USE_SPI_CRC */ |
lypinator | 0:bb348c97df44 | 503 | |
lypinator | 0:bb348c97df44 | 504 | /* Check if the SPI is already enabled */ |
lypinator | 0:bb348c97df44 | 505 | if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) |
lypinator | 0:bb348c97df44 | 506 | { |
lypinator | 0:bb348c97df44 | 507 | /* Enable SPI peripheral */ |
lypinator | 0:bb348c97df44 | 508 | __HAL_SPI_ENABLE(hspi); |
lypinator | 0:bb348c97df44 | 509 | } |
lypinator | 0:bb348c97df44 | 510 | |
lypinator | 0:bb348c97df44 | 511 | /* Transmit data in 16 Bit mode */ |
lypinator | 0:bb348c97df44 | 512 | if(hspi->Init.DataSize == SPI_DATASIZE_16BIT) |
lypinator | 0:bb348c97df44 | 513 | { |
lypinator | 0:bb348c97df44 | 514 | if((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01)) |
lypinator | 0:bb348c97df44 | 515 | { |
lypinator | 0:bb348c97df44 | 516 | hspi->Instance->DR = *((uint16_t *)pData); |
lypinator | 0:bb348c97df44 | 517 | pData += sizeof(uint16_t); |
lypinator | 0:bb348c97df44 | 518 | hspi->TxXferCount--; |
lypinator | 0:bb348c97df44 | 519 | } |
lypinator | 0:bb348c97df44 | 520 | /* Transmit data in 16 Bit mode */ |
lypinator | 0:bb348c97df44 | 521 | while (hspi->TxXferCount > 0U) |
lypinator | 0:bb348c97df44 | 522 | { |
lypinator | 0:bb348c97df44 | 523 | /* Wait until TXE flag is set to send data */ |
lypinator | 0:bb348c97df44 | 524 | if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) |
lypinator | 0:bb348c97df44 | 525 | { |
lypinator | 0:bb348c97df44 | 526 | hspi->Instance->DR = *((uint16_t *)pData); |
lypinator | 0:bb348c97df44 | 527 | pData += sizeof(uint16_t); |
lypinator | 0:bb348c97df44 | 528 | hspi->TxXferCount--; |
lypinator | 0:bb348c97df44 | 529 | } |
lypinator | 0:bb348c97df44 | 530 | else |
lypinator | 0:bb348c97df44 | 531 | { |
lypinator | 0:bb348c97df44 | 532 | /* Timeout management */ |
lypinator | 0:bb348c97df44 | 533 | if((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout))) |
lypinator | 0:bb348c97df44 | 534 | { |
lypinator | 0:bb348c97df44 | 535 | errorcode = HAL_TIMEOUT; |
lypinator | 0:bb348c97df44 | 536 | goto error; |
lypinator | 0:bb348c97df44 | 537 | } |
lypinator | 0:bb348c97df44 | 538 | } |
lypinator | 0:bb348c97df44 | 539 | } |
lypinator | 0:bb348c97df44 | 540 | } |
lypinator | 0:bb348c97df44 | 541 | /* Transmit data in 8 Bit mode */ |
lypinator | 0:bb348c97df44 | 542 | else |
lypinator | 0:bb348c97df44 | 543 | { |
lypinator | 0:bb348c97df44 | 544 | if((hspi->Init.Mode == SPI_MODE_SLAVE)|| (hspi->TxXferCount == 0x01)) |
lypinator | 0:bb348c97df44 | 545 | { |
lypinator | 0:bb348c97df44 | 546 | *((__IO uint8_t*)&hspi->Instance->DR) = (*pData); |
lypinator | 0:bb348c97df44 | 547 | pData += sizeof(uint8_t); |
lypinator | 0:bb348c97df44 | 548 | hspi->TxXferCount--; |
lypinator | 0:bb348c97df44 | 549 | } |
lypinator | 0:bb348c97df44 | 550 | while (hspi->TxXferCount > 0U) |
lypinator | 0:bb348c97df44 | 551 | { |
lypinator | 0:bb348c97df44 | 552 | /* Wait until TXE flag is set to send data */ |
lypinator | 0:bb348c97df44 | 553 | if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) |
lypinator | 0:bb348c97df44 | 554 | { |
lypinator | 0:bb348c97df44 | 555 | *((__IO uint8_t*)&hspi->Instance->DR) = (*pData); |
lypinator | 0:bb348c97df44 | 556 | pData += sizeof(uint8_t); |
lypinator | 0:bb348c97df44 | 557 | hspi->TxXferCount--; |
lypinator | 0:bb348c97df44 | 558 | } |
lypinator | 0:bb348c97df44 | 559 | else |
lypinator | 0:bb348c97df44 | 560 | { |
lypinator | 0:bb348c97df44 | 561 | /* Timeout management */ |
lypinator | 0:bb348c97df44 | 562 | if((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout))) |
lypinator | 0:bb348c97df44 | 563 | { |
lypinator | 0:bb348c97df44 | 564 | errorcode = HAL_TIMEOUT; |
lypinator | 0:bb348c97df44 | 565 | goto error; |
lypinator | 0:bb348c97df44 | 566 | } |
lypinator | 0:bb348c97df44 | 567 | } |
lypinator | 0:bb348c97df44 | 568 | } |
lypinator | 0:bb348c97df44 | 569 | } |
lypinator | 0:bb348c97df44 | 570 | |
lypinator | 0:bb348c97df44 | 571 | /* Wait until TXE flag */ |
lypinator | 0:bb348c97df44 | 572 | /* MBED */ |
lypinator | 0:bb348c97df44 | 573 | if(SPI_WaitTXEFlagStateUntilTimeout(hspi, Timeout, tickstart) != HAL_OK) |
lypinator | 0:bb348c97df44 | 574 | /* MBED */ |
lypinator | 0:bb348c97df44 | 575 | { |
lypinator | 0:bb348c97df44 | 576 | errorcode = HAL_TIMEOUT; |
lypinator | 0:bb348c97df44 | 577 | goto error; |
lypinator | 0:bb348c97df44 | 578 | } |
lypinator | 0:bb348c97df44 | 579 | |
lypinator | 0:bb348c97df44 | 580 | /* Check Busy flag */ |
lypinator | 0:bb348c97df44 | 581 | if(SPI_CheckFlag_BSY(hspi, Timeout, tickstart) != HAL_OK) |
lypinator | 0:bb348c97df44 | 582 | { |
lypinator | 0:bb348c97df44 | 583 | errorcode = HAL_ERROR; |
lypinator | 0:bb348c97df44 | 584 | hspi->ErrorCode = HAL_SPI_ERROR_FLAG; |
lypinator | 0:bb348c97df44 | 585 | goto error; |
lypinator | 0:bb348c97df44 | 586 | } |
lypinator | 0:bb348c97df44 | 587 | |
lypinator | 0:bb348c97df44 | 588 | /* Clear overrun flag in 2 Lines communication mode because received is not read */ |
lypinator | 0:bb348c97df44 | 589 | if(hspi->Init.Direction == SPI_DIRECTION_2LINES) |
lypinator | 0:bb348c97df44 | 590 | { |
lypinator | 0:bb348c97df44 | 591 | __HAL_SPI_CLEAR_OVRFLAG(hspi); |
lypinator | 0:bb348c97df44 | 592 | } |
lypinator | 0:bb348c97df44 | 593 | #if (USE_SPI_CRC != 0U) |
lypinator | 0:bb348c97df44 | 594 | /* Enable CRC Transmission */ |
lypinator | 0:bb348c97df44 | 595 | if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) |
lypinator | 0:bb348c97df44 | 596 | { |
lypinator | 0:bb348c97df44 | 597 | SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); |
lypinator | 0:bb348c97df44 | 598 | } |
lypinator | 0:bb348c97df44 | 599 | #endif /* USE_SPI_CRC */ |
lypinator | 0:bb348c97df44 | 600 | |
lypinator | 0:bb348c97df44 | 601 | if(hspi->ErrorCode != HAL_SPI_ERROR_NONE) |
lypinator | 0:bb348c97df44 | 602 | { |
lypinator | 0:bb348c97df44 | 603 | errorcode = HAL_ERROR; |
lypinator | 0:bb348c97df44 | 604 | } |
lypinator | 0:bb348c97df44 | 605 | |
lypinator | 0:bb348c97df44 | 606 | error: |
lypinator | 0:bb348c97df44 | 607 | hspi->State = HAL_SPI_STATE_READY; |
lypinator | 0:bb348c97df44 | 608 | /* Process Unlocked */ |
lypinator | 0:bb348c97df44 | 609 | __HAL_UNLOCK(hspi); |
lypinator | 0:bb348c97df44 | 610 | return errorcode; |
lypinator | 0:bb348c97df44 | 611 | } |
lypinator | 0:bb348c97df44 | 612 | |
lypinator | 0:bb348c97df44 | 613 | /** |
lypinator | 0:bb348c97df44 | 614 | * @brief Receive an amount of data in blocking mode. |
lypinator | 0:bb348c97df44 | 615 | * @param hspi pointer to a SPI_HandleTypeDef structure that contains |
lypinator | 0:bb348c97df44 | 616 | * the configuration information for SPI module. |
lypinator | 0:bb348c97df44 | 617 | * @param pData pointer to data buffer |
lypinator | 0:bb348c97df44 | 618 | * @param Size amount of data to be received |
lypinator | 0:bb348c97df44 | 619 | * @param Timeout Timeout duration |
lypinator | 0:bb348c97df44 | 620 | * @retval HAL status |
lypinator | 0:bb348c97df44 | 621 | */ |
lypinator | 0:bb348c97df44 | 622 | HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) |
lypinator | 0:bb348c97df44 | 623 | { |
lypinator | 0:bb348c97df44 | 624 | #if (USE_SPI_CRC != 0U) |
lypinator | 0:bb348c97df44 | 625 | __IO uint16_t tmpreg = 0U; |
lypinator | 0:bb348c97df44 | 626 | #endif /* USE_SPI_CRC */ |
lypinator | 0:bb348c97df44 | 627 | uint32_t tickstart = 0U; |
lypinator | 0:bb348c97df44 | 628 | HAL_StatusTypeDef errorcode = HAL_OK; |
lypinator | 0:bb348c97df44 | 629 | |
lypinator | 0:bb348c97df44 | 630 | if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES)) |
lypinator | 0:bb348c97df44 | 631 | { |
lypinator | 0:bb348c97df44 | 632 | hspi->State = HAL_SPI_STATE_BUSY_RX; |
lypinator | 0:bb348c97df44 | 633 | /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */ |
lypinator | 0:bb348c97df44 | 634 | return HAL_SPI_TransmitReceive(hspi,pData,pData,Size,Timeout); |
lypinator | 0:bb348c97df44 | 635 | } |
lypinator | 0:bb348c97df44 | 636 | |
lypinator | 0:bb348c97df44 | 637 | /* Process Locked */ |
lypinator | 0:bb348c97df44 | 638 | __HAL_LOCK(hspi); |
lypinator | 0:bb348c97df44 | 639 | |
lypinator | 0:bb348c97df44 | 640 | /* Init tickstart for timeout management*/ |
lypinator | 0:bb348c97df44 | 641 | tickstart = HAL_GetTick(); |
lypinator | 0:bb348c97df44 | 642 | |
lypinator | 0:bb348c97df44 | 643 | if(hspi->State != HAL_SPI_STATE_READY) |
lypinator | 0:bb348c97df44 | 644 | { |
lypinator | 0:bb348c97df44 | 645 | errorcode = HAL_BUSY; |
lypinator | 0:bb348c97df44 | 646 | goto error; |
lypinator | 0:bb348c97df44 | 647 | } |
lypinator | 0:bb348c97df44 | 648 | |
lypinator | 0:bb348c97df44 | 649 | if((pData == NULL ) || (Size == 0)) |
lypinator | 0:bb348c97df44 | 650 | { |
lypinator | 0:bb348c97df44 | 651 | errorcode = HAL_ERROR; |
lypinator | 0:bb348c97df44 | 652 | goto error; |
lypinator | 0:bb348c97df44 | 653 | } |
lypinator | 0:bb348c97df44 | 654 | |
lypinator | 0:bb348c97df44 | 655 | /* Set the transaction information */ |
lypinator | 0:bb348c97df44 | 656 | hspi->State = HAL_SPI_STATE_BUSY_RX; |
lypinator | 0:bb348c97df44 | 657 | hspi->ErrorCode = HAL_SPI_ERROR_NONE; |
lypinator | 0:bb348c97df44 | 658 | hspi->pRxBuffPtr = (uint8_t *)pData; |
lypinator | 0:bb348c97df44 | 659 | hspi->RxXferSize = Size; |
lypinator | 0:bb348c97df44 | 660 | hspi->RxXferCount = Size; |
lypinator | 0:bb348c97df44 | 661 | |
lypinator | 0:bb348c97df44 | 662 | /*Init field not used in handle to zero */ |
lypinator | 0:bb348c97df44 | 663 | hspi->pTxBuffPtr = (uint8_t *)NULL; |
lypinator | 0:bb348c97df44 | 664 | hspi->TxXferSize = 0U; |
lypinator | 0:bb348c97df44 | 665 | hspi->TxXferCount = 0U; |
lypinator | 0:bb348c97df44 | 666 | hspi->RxISR = NULL; |
lypinator | 0:bb348c97df44 | 667 | hspi->TxISR = NULL; |
lypinator | 0:bb348c97df44 | 668 | |
lypinator | 0:bb348c97df44 | 669 | #if (USE_SPI_CRC != 0U) |
lypinator | 0:bb348c97df44 | 670 | /* Reset CRC Calculation */ |
lypinator | 0:bb348c97df44 | 671 | if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) |
lypinator | 0:bb348c97df44 | 672 | { |
lypinator | 0:bb348c97df44 | 673 | SPI_RESET_CRC(hspi); |
lypinator | 0:bb348c97df44 | 674 | /* this is done to handle the CRCNEXT before the latest data */ |
lypinator | 0:bb348c97df44 | 675 | hspi->RxXferCount--; |
lypinator | 0:bb348c97df44 | 676 | } |
lypinator | 0:bb348c97df44 | 677 | #endif /* USE_SPI_CRC */ |
lypinator | 0:bb348c97df44 | 678 | |
lypinator | 0:bb348c97df44 | 679 | /* Configure communication direction: 1Line */ |
lypinator | 0:bb348c97df44 | 680 | if(hspi->Init.Direction == SPI_DIRECTION_1LINE) |
lypinator | 0:bb348c97df44 | 681 | { |
lypinator | 0:bb348c97df44 | 682 | SPI_1LINE_RX(hspi); |
lypinator | 0:bb348c97df44 | 683 | } |
lypinator | 0:bb348c97df44 | 684 | |
lypinator | 0:bb348c97df44 | 685 | /* Check if the SPI is already enabled */ |
lypinator | 0:bb348c97df44 | 686 | if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) |
lypinator | 0:bb348c97df44 | 687 | { |
lypinator | 0:bb348c97df44 | 688 | /* Enable SPI peripheral */ |
lypinator | 0:bb348c97df44 | 689 | __HAL_SPI_ENABLE(hspi); |
lypinator | 0:bb348c97df44 | 690 | } |
lypinator | 0:bb348c97df44 | 691 | |
lypinator | 0:bb348c97df44 | 692 | /* Receive data in 8 Bit mode */ |
lypinator | 0:bb348c97df44 | 693 | if(hspi->Init.DataSize == SPI_DATASIZE_8BIT) |
lypinator | 0:bb348c97df44 | 694 | { |
lypinator | 0:bb348c97df44 | 695 | /* Transfer loop */ |
lypinator | 0:bb348c97df44 | 696 | while(hspi->RxXferCount > 0U) |
lypinator | 0:bb348c97df44 | 697 | { |
lypinator | 0:bb348c97df44 | 698 | /* Check the RXNE flag */ |
lypinator | 0:bb348c97df44 | 699 | if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) |
lypinator | 0:bb348c97df44 | 700 | { |
lypinator | 0:bb348c97df44 | 701 | /* read the received data */ |
lypinator | 0:bb348c97df44 | 702 | (* (uint8_t *)pData)= *(__IO uint8_t *)&hspi->Instance->DR; |
lypinator | 0:bb348c97df44 | 703 | pData += sizeof(uint8_t); |
lypinator | 0:bb348c97df44 | 704 | hspi->RxXferCount--; |
lypinator | 0:bb348c97df44 | 705 | } |
lypinator | 0:bb348c97df44 | 706 | else |
lypinator | 0:bb348c97df44 | 707 | { |
lypinator | 0:bb348c97df44 | 708 | /* Timeout management */ |
lypinator | 0:bb348c97df44 | 709 | if((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout))) |
lypinator | 0:bb348c97df44 | 710 | { |
lypinator | 0:bb348c97df44 | 711 | errorcode = HAL_TIMEOUT; |
lypinator | 0:bb348c97df44 | 712 | goto error; |
lypinator | 0:bb348c97df44 | 713 | } |
lypinator | 0:bb348c97df44 | 714 | } |
lypinator | 0:bb348c97df44 | 715 | } |
lypinator | 0:bb348c97df44 | 716 | } |
lypinator | 0:bb348c97df44 | 717 | else |
lypinator | 0:bb348c97df44 | 718 | { |
lypinator | 0:bb348c97df44 | 719 | /* Transfer loop */ |
lypinator | 0:bb348c97df44 | 720 | while(hspi->RxXferCount > 0U) |
lypinator | 0:bb348c97df44 | 721 | { |
lypinator | 0:bb348c97df44 | 722 | /* Check the RXNE flag */ |
lypinator | 0:bb348c97df44 | 723 | if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) |
lypinator | 0:bb348c97df44 | 724 | { |
lypinator | 0:bb348c97df44 | 725 | *((uint16_t*)pData) = hspi->Instance->DR; |
lypinator | 0:bb348c97df44 | 726 | pData += sizeof(uint16_t); |
lypinator | 0:bb348c97df44 | 727 | hspi->RxXferCount--; |
lypinator | 0:bb348c97df44 | 728 | } |
lypinator | 0:bb348c97df44 | 729 | else |
lypinator | 0:bb348c97df44 | 730 | { |
lypinator | 0:bb348c97df44 | 731 | /* Timeout management */ |
lypinator | 0:bb348c97df44 | 732 | if((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout))) |
lypinator | 0:bb348c97df44 | 733 | { |
lypinator | 0:bb348c97df44 | 734 | errorcode = HAL_TIMEOUT; |
lypinator | 0:bb348c97df44 | 735 | goto error; |
lypinator | 0:bb348c97df44 | 736 | } |
lypinator | 0:bb348c97df44 | 737 | } |
lypinator | 0:bb348c97df44 | 738 | } |
lypinator | 0:bb348c97df44 | 739 | } |
lypinator | 0:bb348c97df44 | 740 | |
lypinator | 0:bb348c97df44 | 741 | #if (USE_SPI_CRC != 0U) |
lypinator | 0:bb348c97df44 | 742 | /* Handle the CRC Transmission */ |
lypinator | 0:bb348c97df44 | 743 | if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) |
lypinator | 0:bb348c97df44 | 744 | { |
lypinator | 0:bb348c97df44 | 745 | /* freeze the CRC before the latest data */ |
lypinator | 0:bb348c97df44 | 746 | SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); |
lypinator | 0:bb348c97df44 | 747 | |
lypinator | 0:bb348c97df44 | 748 | /* Read the latest data */ |
lypinator | 0:bb348c97df44 | 749 | if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK) |
lypinator | 0:bb348c97df44 | 750 | { |
lypinator | 0:bb348c97df44 | 751 | /* the latest data has not been received */ |
lypinator | 0:bb348c97df44 | 752 | errorcode = HAL_TIMEOUT; |
lypinator | 0:bb348c97df44 | 753 | goto error; |
lypinator | 0:bb348c97df44 | 754 | } |
lypinator | 0:bb348c97df44 | 755 | |
lypinator | 0:bb348c97df44 | 756 | /* Receive last data in 16 Bit mode */ |
lypinator | 0:bb348c97df44 | 757 | if(hspi->Init.DataSize == SPI_DATASIZE_16BIT) |
lypinator | 0:bb348c97df44 | 758 | { |
lypinator | 0:bb348c97df44 | 759 | *((uint16_t*)pData) = hspi->Instance->DR; |
lypinator | 0:bb348c97df44 | 760 | } |
lypinator | 0:bb348c97df44 | 761 | /* Receive last data in 8 Bit mode */ |
lypinator | 0:bb348c97df44 | 762 | else |
lypinator | 0:bb348c97df44 | 763 | { |
lypinator | 0:bb348c97df44 | 764 | (*(uint8_t *)pData) = *(__IO uint8_t *)&hspi->Instance->DR; |
lypinator | 0:bb348c97df44 | 765 | } |
lypinator | 0:bb348c97df44 | 766 | |
lypinator | 0:bb348c97df44 | 767 | /* Wait the CRC data */ |
lypinator | 0:bb348c97df44 | 768 | if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK) |
lypinator | 0:bb348c97df44 | 769 | { |
lypinator | 0:bb348c97df44 | 770 | SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); |
lypinator | 0:bb348c97df44 | 771 | errorcode = HAL_TIMEOUT; |
lypinator | 0:bb348c97df44 | 772 | goto error; |
lypinator | 0:bb348c97df44 | 773 | } |
lypinator | 0:bb348c97df44 | 774 | |
lypinator | 0:bb348c97df44 | 775 | /* Read CRC to Flush DR and RXNE flag */ |
lypinator | 0:bb348c97df44 | 776 | tmpreg = hspi->Instance->DR; |
lypinator | 0:bb348c97df44 | 777 | /* To avoid GCC warning */ |
lypinator | 0:bb348c97df44 | 778 | UNUSED(tmpreg); |
lypinator | 0:bb348c97df44 | 779 | } |
lypinator | 0:bb348c97df44 | 780 | #endif /* USE_SPI_CRC */ |
lypinator | 0:bb348c97df44 | 781 | |
lypinator | 0:bb348c97df44 | 782 | /* Check the end of the transaction */ |
lypinator | 0:bb348c97df44 | 783 | if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) |
lypinator | 0:bb348c97df44 | 784 | { |
lypinator | 0:bb348c97df44 | 785 | /* Disable SPI peripheral */ |
lypinator | 0:bb348c97df44 | 786 | __HAL_SPI_DISABLE(hspi); |
lypinator | 0:bb348c97df44 | 787 | } |
lypinator | 0:bb348c97df44 | 788 | |
lypinator | 0:bb348c97df44 | 789 | #if (USE_SPI_CRC != 0U) |
lypinator | 0:bb348c97df44 | 790 | /* Check if CRC error occurred */ |
lypinator | 0:bb348c97df44 | 791 | if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR)) |
lypinator | 0:bb348c97df44 | 792 | { |
lypinator | 0:bb348c97df44 | 793 | SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); |
lypinator | 0:bb348c97df44 | 794 | __HAL_SPI_CLEAR_CRCERRFLAG(hspi); |
lypinator | 0:bb348c97df44 | 795 | } |
lypinator | 0:bb348c97df44 | 796 | #endif /* USE_SPI_CRC */ |
lypinator | 0:bb348c97df44 | 797 | |
lypinator | 0:bb348c97df44 | 798 | if(hspi->ErrorCode != HAL_SPI_ERROR_NONE) |
lypinator | 0:bb348c97df44 | 799 | { |
lypinator | 0:bb348c97df44 | 800 | errorcode = HAL_ERROR; |
lypinator | 0:bb348c97df44 | 801 | } |
lypinator | 0:bb348c97df44 | 802 | |
lypinator | 0:bb348c97df44 | 803 | error : |
lypinator | 0:bb348c97df44 | 804 | hspi->State = HAL_SPI_STATE_READY; |
lypinator | 0:bb348c97df44 | 805 | __HAL_UNLOCK(hspi); |
lypinator | 0:bb348c97df44 | 806 | return errorcode; |
lypinator | 0:bb348c97df44 | 807 | } |
lypinator | 0:bb348c97df44 | 808 | |
lypinator | 0:bb348c97df44 | 809 | /** |
lypinator | 0:bb348c97df44 | 810 | * @brief Transmit and Receive an amount of data in blocking mode. |
lypinator | 0:bb348c97df44 | 811 | * @param hspi pointer to a SPI_HandleTypeDef structure that contains |
lypinator | 0:bb348c97df44 | 812 | * the configuration information for SPI module. |
lypinator | 0:bb348c97df44 | 813 | * @param pTxData pointer to transmission data buffer |
lypinator | 0:bb348c97df44 | 814 | * @param pRxData pointer to reception data buffer |
lypinator | 0:bb348c97df44 | 815 | * @param Size amount of data to be sent and received |
lypinator | 0:bb348c97df44 | 816 | * @param Timeout Timeout duration |
lypinator | 0:bb348c97df44 | 817 | * @retval HAL status |
lypinator | 0:bb348c97df44 | 818 | */ |
lypinator | 0:bb348c97df44 | 819 | HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout) |
lypinator | 0:bb348c97df44 | 820 | { |
lypinator | 0:bb348c97df44 | 821 | uint32_t tmp = 0U, tmp1 = 0U; |
lypinator | 0:bb348c97df44 | 822 | #if (USE_SPI_CRC != 0U) |
lypinator | 0:bb348c97df44 | 823 | __IO uint16_t tmpreg1 = 0U; |
lypinator | 0:bb348c97df44 | 824 | #endif /* USE_SPI_CRC */ |
lypinator | 0:bb348c97df44 | 825 | uint32_t tickstart = 0U; |
lypinator | 0:bb348c97df44 | 826 | /* Variable used to alternate Rx and Tx during transfer */ |
lypinator | 0:bb348c97df44 | 827 | uint32_t txallowed = 1U; |
lypinator | 0:bb348c97df44 | 828 | HAL_StatusTypeDef errorcode = HAL_OK; |
lypinator | 0:bb348c97df44 | 829 | |
lypinator | 0:bb348c97df44 | 830 | /* Check Direction parameter */ |
lypinator | 0:bb348c97df44 | 831 | assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); |
lypinator | 0:bb348c97df44 | 832 | |
lypinator | 0:bb348c97df44 | 833 | /* Process Locked */ |
lypinator | 0:bb348c97df44 | 834 | __HAL_LOCK(hspi); |
lypinator | 0:bb348c97df44 | 835 | |
lypinator | 0:bb348c97df44 | 836 | /* Init tickstart for timeout management*/ |
lypinator | 0:bb348c97df44 | 837 | tickstart = HAL_GetTick(); |
lypinator | 0:bb348c97df44 | 838 | |
lypinator | 0:bb348c97df44 | 839 | tmp = hspi->State; |
lypinator | 0:bb348c97df44 | 840 | tmp1 = hspi->Init.Mode; |
lypinator | 0:bb348c97df44 | 841 | |
lypinator | 0:bb348c97df44 | 842 | if(!((tmp == HAL_SPI_STATE_READY) || \ |
lypinator | 0:bb348c97df44 | 843 | ((tmp1 == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp == HAL_SPI_STATE_BUSY_RX)))) |
lypinator | 0:bb348c97df44 | 844 | { |
lypinator | 0:bb348c97df44 | 845 | errorcode = HAL_BUSY; |
lypinator | 0:bb348c97df44 | 846 | goto error; |
lypinator | 0:bb348c97df44 | 847 | } |
lypinator | 0:bb348c97df44 | 848 | |
lypinator | 0:bb348c97df44 | 849 | if((pTxData == NULL) || (pRxData == NULL) || (Size == 0)) |
lypinator | 0:bb348c97df44 | 850 | { |
lypinator | 0:bb348c97df44 | 851 | errorcode = HAL_ERROR; |
lypinator | 0:bb348c97df44 | 852 | goto error; |
lypinator | 0:bb348c97df44 | 853 | } |
lypinator | 0:bb348c97df44 | 854 | |
lypinator | 0:bb348c97df44 | 855 | /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ |
lypinator | 0:bb348c97df44 | 856 | if(hspi->State == HAL_SPI_STATE_READY) |
lypinator | 0:bb348c97df44 | 857 | { |
lypinator | 0:bb348c97df44 | 858 | hspi->State = HAL_SPI_STATE_BUSY_TX_RX; |
lypinator | 0:bb348c97df44 | 859 | } |
lypinator | 0:bb348c97df44 | 860 | |
lypinator | 0:bb348c97df44 | 861 | /* Set the transaction information */ |
lypinator | 0:bb348c97df44 | 862 | hspi->ErrorCode = HAL_SPI_ERROR_NONE; |
lypinator | 0:bb348c97df44 | 863 | hspi->pRxBuffPtr = (uint8_t *)pRxData; |
lypinator | 0:bb348c97df44 | 864 | hspi->RxXferCount = Size; |
lypinator | 0:bb348c97df44 | 865 | hspi->RxXferSize = Size; |
lypinator | 0:bb348c97df44 | 866 | hspi->pTxBuffPtr = (uint8_t *)pTxData; |
lypinator | 0:bb348c97df44 | 867 | hspi->TxXferCount = Size; |
lypinator | 0:bb348c97df44 | 868 | hspi->TxXferSize = Size; |
lypinator | 0:bb348c97df44 | 869 | |
lypinator | 0:bb348c97df44 | 870 | /*Init field not used in handle to zero */ |
lypinator | 0:bb348c97df44 | 871 | hspi->RxISR = NULL; |
lypinator | 0:bb348c97df44 | 872 | hspi->TxISR = NULL; |
lypinator | 0:bb348c97df44 | 873 | |
lypinator | 0:bb348c97df44 | 874 | #if (USE_SPI_CRC != 0U) |
lypinator | 0:bb348c97df44 | 875 | /* Reset CRC Calculation */ |
lypinator | 0:bb348c97df44 | 876 | if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) |
lypinator | 0:bb348c97df44 | 877 | { |
lypinator | 0:bb348c97df44 | 878 | SPI_RESET_CRC(hspi); |
lypinator | 0:bb348c97df44 | 879 | } |
lypinator | 0:bb348c97df44 | 880 | #endif /* USE_SPI_CRC */ |
lypinator | 0:bb348c97df44 | 881 | |
lypinator | 0:bb348c97df44 | 882 | /* Check if the SPI is already enabled */ |
lypinator | 0:bb348c97df44 | 883 | if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) |
lypinator | 0:bb348c97df44 | 884 | { |
lypinator | 0:bb348c97df44 | 885 | /* Enable SPI peripheral */ |
lypinator | 0:bb348c97df44 | 886 | __HAL_SPI_ENABLE(hspi); |
lypinator | 0:bb348c97df44 | 887 | } |
lypinator | 0:bb348c97df44 | 888 | |
lypinator | 0:bb348c97df44 | 889 | /* Transmit and Receive data in 16 Bit mode */ |
lypinator | 0:bb348c97df44 | 890 | if(hspi->Init.DataSize == SPI_DATASIZE_16BIT) |
lypinator | 0:bb348c97df44 | 891 | { |
lypinator | 0:bb348c97df44 | 892 | if((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01U)) |
lypinator | 0:bb348c97df44 | 893 | { |
lypinator | 0:bb348c97df44 | 894 | hspi->Instance->DR = *((uint16_t *)pTxData); |
lypinator | 0:bb348c97df44 | 895 | pTxData += sizeof(uint16_t); |
lypinator | 0:bb348c97df44 | 896 | hspi->TxXferCount--; |
lypinator | 0:bb348c97df44 | 897 | } |
lypinator | 0:bb348c97df44 | 898 | while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U)) |
lypinator | 0:bb348c97df44 | 899 | { |
lypinator | 0:bb348c97df44 | 900 | /* Check TXE flag */ |
lypinator | 0:bb348c97df44 | 901 | if(txallowed && (hspi->TxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))) |
lypinator | 0:bb348c97df44 | 902 | { |
lypinator | 0:bb348c97df44 | 903 | hspi->Instance->DR = *((uint16_t *)pTxData); |
lypinator | 0:bb348c97df44 | 904 | pTxData += sizeof(uint16_t); |
lypinator | 0:bb348c97df44 | 905 | hspi->TxXferCount--; |
lypinator | 0:bb348c97df44 | 906 | /* Next Data is a reception (Rx). Tx not allowed */ |
lypinator | 0:bb348c97df44 | 907 | txallowed = 0U; |
lypinator | 0:bb348c97df44 | 908 | |
lypinator | 0:bb348c97df44 | 909 | #if (USE_SPI_CRC != 0U) |
lypinator | 0:bb348c97df44 | 910 | /* Enable CRC Transmission */ |
lypinator | 0:bb348c97df44 | 911 | if((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) |
lypinator | 0:bb348c97df44 | 912 | { |
lypinator | 0:bb348c97df44 | 913 | SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); |
lypinator | 0:bb348c97df44 | 914 | } |
lypinator | 0:bb348c97df44 | 915 | #endif /* USE_SPI_CRC */ |
lypinator | 0:bb348c97df44 | 916 | } |
lypinator | 0:bb348c97df44 | 917 | |
lypinator | 0:bb348c97df44 | 918 | /* Check RXNE flag */ |
lypinator | 0:bb348c97df44 | 919 | if((hspi->RxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))) |
lypinator | 0:bb348c97df44 | 920 | { |
lypinator | 0:bb348c97df44 | 921 | *((uint16_t *)pRxData) = hspi->Instance->DR; |
lypinator | 0:bb348c97df44 | 922 | pRxData += sizeof(uint16_t); |
lypinator | 0:bb348c97df44 | 923 | hspi->RxXferCount--; |
lypinator | 0:bb348c97df44 | 924 | /* Next Data is a Transmission (Tx). Tx is allowed */ |
lypinator | 0:bb348c97df44 | 925 | txallowed = 1U; |
lypinator | 0:bb348c97df44 | 926 | } |
lypinator | 0:bb348c97df44 | 927 | if((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout)) |
lypinator | 0:bb348c97df44 | 928 | { |
lypinator | 0:bb348c97df44 | 929 | errorcode = HAL_TIMEOUT; |
lypinator | 0:bb348c97df44 | 930 | goto error; |
lypinator | 0:bb348c97df44 | 931 | } |
lypinator | 0:bb348c97df44 | 932 | } |
lypinator | 0:bb348c97df44 | 933 | } |
lypinator | 0:bb348c97df44 | 934 | /* Transmit and Receive data in 8 Bit mode */ |
lypinator | 0:bb348c97df44 | 935 | else |
lypinator | 0:bb348c97df44 | 936 | { |
lypinator | 0:bb348c97df44 | 937 | if((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01U)) |
lypinator | 0:bb348c97df44 | 938 | { |
lypinator | 0:bb348c97df44 | 939 | *((__IO uint8_t*)&hspi->Instance->DR) = (*pTxData); |
lypinator | 0:bb348c97df44 | 940 | pTxData += sizeof(uint8_t); |
lypinator | 0:bb348c97df44 | 941 | hspi->TxXferCount--; |
lypinator | 0:bb348c97df44 | 942 | } |
lypinator | 0:bb348c97df44 | 943 | while((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U)) |
lypinator | 0:bb348c97df44 | 944 | { |
lypinator | 0:bb348c97df44 | 945 | /* check TXE flag */ |
lypinator | 0:bb348c97df44 | 946 | if(txallowed && (hspi->TxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))) |
lypinator | 0:bb348c97df44 | 947 | { |
lypinator | 0:bb348c97df44 | 948 | *(__IO uint8_t *)&hspi->Instance->DR = (*pTxData++); |
lypinator | 0:bb348c97df44 | 949 | hspi->TxXferCount--; |
lypinator | 0:bb348c97df44 | 950 | /* Next Data is a reception (Rx). Tx not allowed */ |
lypinator | 0:bb348c97df44 | 951 | txallowed = 0U; |
lypinator | 0:bb348c97df44 | 952 | |
lypinator | 0:bb348c97df44 | 953 | #if (USE_SPI_CRC != 0U) |
lypinator | 0:bb348c97df44 | 954 | /* Enable CRC Transmission */ |
lypinator | 0:bb348c97df44 | 955 | if((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) |
lypinator | 0:bb348c97df44 | 956 | { |
lypinator | 0:bb348c97df44 | 957 | SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); |
lypinator | 0:bb348c97df44 | 958 | } |
lypinator | 0:bb348c97df44 | 959 | #endif /* USE_SPI_CRC */ |
lypinator | 0:bb348c97df44 | 960 | } |
lypinator | 0:bb348c97df44 | 961 | |
lypinator | 0:bb348c97df44 | 962 | /* Wait until RXNE flag is reset */ |
lypinator | 0:bb348c97df44 | 963 | if((hspi->RxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))) |
lypinator | 0:bb348c97df44 | 964 | { |
lypinator | 0:bb348c97df44 | 965 | (*(uint8_t *)pRxData++) = hspi->Instance->DR; |
lypinator | 0:bb348c97df44 | 966 | hspi->RxXferCount--; |
lypinator | 0:bb348c97df44 | 967 | /* Next Data is a Transmission (Tx). Tx is allowed */ |
lypinator | 0:bb348c97df44 | 968 | txallowed = 1U; |
lypinator | 0:bb348c97df44 | 969 | } |
lypinator | 0:bb348c97df44 | 970 | if((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout)) |
lypinator | 0:bb348c97df44 | 971 | { |
lypinator | 0:bb348c97df44 | 972 | errorcode = HAL_TIMEOUT; |
lypinator | 0:bb348c97df44 | 973 | goto error; |
lypinator | 0:bb348c97df44 | 974 | } |
lypinator | 0:bb348c97df44 | 975 | } |
lypinator | 0:bb348c97df44 | 976 | } |
lypinator | 0:bb348c97df44 | 977 | |
lypinator | 0:bb348c97df44 | 978 | #if (USE_SPI_CRC != 0U) |
lypinator | 0:bb348c97df44 | 979 | /* Read CRC from DR to close CRC calculation process */ |
lypinator | 0:bb348c97df44 | 980 | if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) |
lypinator | 0:bb348c97df44 | 981 | { |
lypinator | 0:bb348c97df44 | 982 | /* Wait until TXE flag */ |
lypinator | 0:bb348c97df44 | 983 | if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK) |
lypinator | 0:bb348c97df44 | 984 | { |
lypinator | 0:bb348c97df44 | 985 | /* Error on the CRC reception */ |
lypinator | 0:bb348c97df44 | 986 | SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); |
lypinator | 0:bb348c97df44 | 987 | errorcode = HAL_TIMEOUT; |
lypinator | 0:bb348c97df44 | 988 | goto error; |
lypinator | 0:bb348c97df44 | 989 | } |
lypinator | 0:bb348c97df44 | 990 | /* Read CRC */ |
lypinator | 0:bb348c97df44 | 991 | tmpreg1 = hspi->Instance->DR; |
lypinator | 0:bb348c97df44 | 992 | /* To avoid GCC warning */ |
lypinator | 0:bb348c97df44 | 993 | UNUSED(tmpreg1); |
lypinator | 0:bb348c97df44 | 994 | } |
lypinator | 0:bb348c97df44 | 995 | |
lypinator | 0:bb348c97df44 | 996 | /* Check if CRC error occurred */ |
lypinator | 0:bb348c97df44 | 997 | if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR)) |
lypinator | 0:bb348c97df44 | 998 | { |
lypinator | 0:bb348c97df44 | 999 | SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); |
lypinator | 0:bb348c97df44 | 1000 | /* Clear CRC Flag */ |
lypinator | 0:bb348c97df44 | 1001 | __HAL_SPI_CLEAR_CRCERRFLAG(hspi); |
lypinator | 0:bb348c97df44 | 1002 | |
lypinator | 0:bb348c97df44 | 1003 | errorcode = HAL_ERROR; |
lypinator | 0:bb348c97df44 | 1004 | } |
lypinator | 0:bb348c97df44 | 1005 | #endif /* USE_SPI_CRC */ |
lypinator | 0:bb348c97df44 | 1006 | |
lypinator | 0:bb348c97df44 | 1007 | /* Wait until TXE flag */ |
lypinator | 0:bb348c97df44 | 1008 | /* MBED */ |
lypinator | 0:bb348c97df44 | 1009 | if(SPI_WaitTXEFlagStateUntilTimeout(hspi, Timeout, tickstart) != HAL_OK) |
lypinator | 0:bb348c97df44 | 1010 | /* MBED */ |
lypinator | 0:bb348c97df44 | 1011 | { |
lypinator | 0:bb348c97df44 | 1012 | errorcode = HAL_TIMEOUT; |
lypinator | 0:bb348c97df44 | 1013 | goto error; |
lypinator | 0:bb348c97df44 | 1014 | } |
lypinator | 0:bb348c97df44 | 1015 | |
lypinator | 0:bb348c97df44 | 1016 | /* Check Busy flag */ |
lypinator | 0:bb348c97df44 | 1017 | if(SPI_CheckFlag_BSY(hspi, Timeout, tickstart) != HAL_OK) |
lypinator | 0:bb348c97df44 | 1018 | { |
lypinator | 0:bb348c97df44 | 1019 | errorcode = HAL_ERROR; |
lypinator | 0:bb348c97df44 | 1020 | hspi->ErrorCode = HAL_SPI_ERROR_FLAG; |
lypinator | 0:bb348c97df44 | 1021 | goto error; |
lypinator | 0:bb348c97df44 | 1022 | } |
lypinator | 0:bb348c97df44 | 1023 | |
lypinator | 0:bb348c97df44 | 1024 | /* Clear overrun flag in 2 Lines communication mode because received is not read */ |
lypinator | 0:bb348c97df44 | 1025 | if(hspi->Init.Direction == SPI_DIRECTION_2LINES) |
lypinator | 0:bb348c97df44 | 1026 | { |
lypinator | 0:bb348c97df44 | 1027 | __HAL_SPI_CLEAR_OVRFLAG(hspi); |
lypinator | 0:bb348c97df44 | 1028 | } |
lypinator | 0:bb348c97df44 | 1029 | |
lypinator | 0:bb348c97df44 | 1030 | error : |
lypinator | 0:bb348c97df44 | 1031 | hspi->State = HAL_SPI_STATE_READY; |
lypinator | 0:bb348c97df44 | 1032 | __HAL_UNLOCK(hspi); |
lypinator | 0:bb348c97df44 | 1033 | return errorcode; |
lypinator | 0:bb348c97df44 | 1034 | } |
lypinator | 0:bb348c97df44 | 1035 | |
lypinator | 0:bb348c97df44 | 1036 | /** |
lypinator | 0:bb348c97df44 | 1037 | * @brief Transmit an amount of data in non-blocking mode with Interrupt. |
lypinator | 0:bb348c97df44 | 1038 | * @param hspi pointer to a SPI_HandleTypeDef structure that contains |
lypinator | 0:bb348c97df44 | 1039 | * the configuration information for SPI module. |
lypinator | 0:bb348c97df44 | 1040 | * @param pData pointer to data buffer |
lypinator | 0:bb348c97df44 | 1041 | * @param Size amount of data to be sent |
lypinator | 0:bb348c97df44 | 1042 | * @retval HAL status |
lypinator | 0:bb348c97df44 | 1043 | */ |
lypinator | 0:bb348c97df44 | 1044 | HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) |
lypinator | 0:bb348c97df44 | 1045 | { |
lypinator | 0:bb348c97df44 | 1046 | HAL_StatusTypeDef errorcode = HAL_OK; |
lypinator | 0:bb348c97df44 | 1047 | |
lypinator | 0:bb348c97df44 | 1048 | /* Check Direction parameter */ |
lypinator | 0:bb348c97df44 | 1049 | assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); |
lypinator | 0:bb348c97df44 | 1050 | |
lypinator | 0:bb348c97df44 | 1051 | /* Process Locked */ |
lypinator | 0:bb348c97df44 | 1052 | __HAL_LOCK(hspi); |
lypinator | 0:bb348c97df44 | 1053 | |
lypinator | 0:bb348c97df44 | 1054 | if((pData == NULL) || (Size == 0)) |
lypinator | 0:bb348c97df44 | 1055 | { |
lypinator | 0:bb348c97df44 | 1056 | errorcode = HAL_ERROR; |
lypinator | 0:bb348c97df44 | 1057 | goto error; |
lypinator | 0:bb348c97df44 | 1058 | } |
lypinator | 0:bb348c97df44 | 1059 | |
lypinator | 0:bb348c97df44 | 1060 | if(hspi->State != HAL_SPI_STATE_READY) |
lypinator | 0:bb348c97df44 | 1061 | { |
lypinator | 0:bb348c97df44 | 1062 | errorcode = HAL_BUSY; |
lypinator | 0:bb348c97df44 | 1063 | goto error; |
lypinator | 0:bb348c97df44 | 1064 | } |
lypinator | 0:bb348c97df44 | 1065 | |
lypinator | 0:bb348c97df44 | 1066 | /* Set the transaction information */ |
lypinator | 0:bb348c97df44 | 1067 | hspi->State = HAL_SPI_STATE_BUSY_TX; |
lypinator | 0:bb348c97df44 | 1068 | hspi->ErrorCode = HAL_SPI_ERROR_NONE; |
lypinator | 0:bb348c97df44 | 1069 | hspi->pTxBuffPtr = (uint8_t *)pData; |
lypinator | 0:bb348c97df44 | 1070 | hspi->TxXferSize = Size; |
lypinator | 0:bb348c97df44 | 1071 | hspi->TxXferCount = Size; |
lypinator | 0:bb348c97df44 | 1072 | |
lypinator | 0:bb348c97df44 | 1073 | /* Init field not used in handle to zero */ |
lypinator | 0:bb348c97df44 | 1074 | hspi->pRxBuffPtr = (uint8_t *)NULL; |
lypinator | 0:bb348c97df44 | 1075 | hspi->RxXferSize = 0U; |
lypinator | 0:bb348c97df44 | 1076 | hspi->RxXferCount = 0U; |
lypinator | 0:bb348c97df44 | 1077 | hspi->RxISR = NULL; |
lypinator | 0:bb348c97df44 | 1078 | |
lypinator | 0:bb348c97df44 | 1079 | /* Set the function for IT treatment */ |
lypinator | 0:bb348c97df44 | 1080 | if(hspi->Init.DataSize > SPI_DATASIZE_8BIT ) |
lypinator | 0:bb348c97df44 | 1081 | { |
lypinator | 0:bb348c97df44 | 1082 | hspi->TxISR = SPI_TxISR_16BIT; |
lypinator | 0:bb348c97df44 | 1083 | } |
lypinator | 0:bb348c97df44 | 1084 | else |
lypinator | 0:bb348c97df44 | 1085 | { |
lypinator | 0:bb348c97df44 | 1086 | hspi->TxISR = SPI_TxISR_8BIT; |
lypinator | 0:bb348c97df44 | 1087 | } |
lypinator | 0:bb348c97df44 | 1088 | |
lypinator | 0:bb348c97df44 | 1089 | /* Configure communication direction : 1Line */ |
lypinator | 0:bb348c97df44 | 1090 | if(hspi->Init.Direction == SPI_DIRECTION_1LINE) |
lypinator | 0:bb348c97df44 | 1091 | { |
lypinator | 0:bb348c97df44 | 1092 | SPI_1LINE_TX(hspi); |
lypinator | 0:bb348c97df44 | 1093 | } |
lypinator | 0:bb348c97df44 | 1094 | |
lypinator | 0:bb348c97df44 | 1095 | #if (USE_SPI_CRC != 0U) |
lypinator | 0:bb348c97df44 | 1096 | /* Reset CRC Calculation */ |
lypinator | 0:bb348c97df44 | 1097 | if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) |
lypinator | 0:bb348c97df44 | 1098 | { |
lypinator | 0:bb348c97df44 | 1099 | SPI_RESET_CRC(hspi); |
lypinator | 0:bb348c97df44 | 1100 | } |
lypinator | 0:bb348c97df44 | 1101 | #endif /* USE_SPI_CRC */ |
lypinator | 0:bb348c97df44 | 1102 | |
lypinator | 0:bb348c97df44 | 1103 | if (hspi->Init.Direction == SPI_DIRECTION_2LINES) |
lypinator | 0:bb348c97df44 | 1104 | { |
lypinator | 0:bb348c97df44 | 1105 | /* Enable TXE interrupt */ |
lypinator | 0:bb348c97df44 | 1106 | __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE)); |
lypinator | 0:bb348c97df44 | 1107 | } |
lypinator | 0:bb348c97df44 | 1108 | else |
lypinator | 0:bb348c97df44 | 1109 | { |
lypinator | 0:bb348c97df44 | 1110 | /* Enable TXE and ERR interrupt */ |
lypinator | 0:bb348c97df44 | 1111 | __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR)); |
lypinator | 0:bb348c97df44 | 1112 | } |
lypinator | 0:bb348c97df44 | 1113 | |
lypinator | 0:bb348c97df44 | 1114 | /* Check if the SPI is already enabled */ |
lypinator | 0:bb348c97df44 | 1115 | if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) |
lypinator | 0:bb348c97df44 | 1116 | { |
lypinator | 0:bb348c97df44 | 1117 | /* Enable SPI peripheral */ |
lypinator | 0:bb348c97df44 | 1118 | __HAL_SPI_ENABLE(hspi); |
lypinator | 0:bb348c97df44 | 1119 | } |
lypinator | 0:bb348c97df44 | 1120 | |
lypinator | 0:bb348c97df44 | 1121 | error : |
lypinator | 0:bb348c97df44 | 1122 | __HAL_UNLOCK(hspi); |
lypinator | 0:bb348c97df44 | 1123 | return errorcode; |
lypinator | 0:bb348c97df44 | 1124 | } |
lypinator | 0:bb348c97df44 | 1125 | |
lypinator | 0:bb348c97df44 | 1126 | /** |
lypinator | 0:bb348c97df44 | 1127 | * @brief Receive an amount of data in non-blocking mode with Interrupt. |
lypinator | 0:bb348c97df44 | 1128 | * @param hspi pointer to a SPI_HandleTypeDef structure that contains |
lypinator | 0:bb348c97df44 | 1129 | * the configuration information for SPI module. |
lypinator | 0:bb348c97df44 | 1130 | * @param pData pointer to data buffer |
lypinator | 0:bb348c97df44 | 1131 | * @param Size amount of data to be sent |
lypinator | 0:bb348c97df44 | 1132 | * @retval HAL status |
lypinator | 0:bb348c97df44 | 1133 | */ |
lypinator | 0:bb348c97df44 | 1134 | HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) |
lypinator | 0:bb348c97df44 | 1135 | { |
lypinator | 0:bb348c97df44 | 1136 | HAL_StatusTypeDef errorcode = HAL_OK; |
lypinator | 0:bb348c97df44 | 1137 | |
lypinator | 0:bb348c97df44 | 1138 | if((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER)) |
lypinator | 0:bb348c97df44 | 1139 | { |
lypinator | 0:bb348c97df44 | 1140 | hspi->State = HAL_SPI_STATE_BUSY_RX; |
lypinator | 0:bb348c97df44 | 1141 | /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */ |
lypinator | 0:bb348c97df44 | 1142 | return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size); |
lypinator | 0:bb348c97df44 | 1143 | } |
lypinator | 0:bb348c97df44 | 1144 | |
lypinator | 0:bb348c97df44 | 1145 | /* Process Locked */ |
lypinator | 0:bb348c97df44 | 1146 | __HAL_LOCK(hspi); |
lypinator | 0:bb348c97df44 | 1147 | |
lypinator | 0:bb348c97df44 | 1148 | if(hspi->State != HAL_SPI_STATE_READY) |
lypinator | 0:bb348c97df44 | 1149 | { |
lypinator | 0:bb348c97df44 | 1150 | errorcode = HAL_BUSY; |
lypinator | 0:bb348c97df44 | 1151 | goto error; |
lypinator | 0:bb348c97df44 | 1152 | } |
lypinator | 0:bb348c97df44 | 1153 | |
lypinator | 0:bb348c97df44 | 1154 | if((pData == NULL) || (Size == 0)) |
lypinator | 0:bb348c97df44 | 1155 | { |
lypinator | 0:bb348c97df44 | 1156 | errorcode = HAL_ERROR; |
lypinator | 0:bb348c97df44 | 1157 | goto error; |
lypinator | 0:bb348c97df44 | 1158 | } |
lypinator | 0:bb348c97df44 | 1159 | |
lypinator | 0:bb348c97df44 | 1160 | /* Set the transaction information */ |
lypinator | 0:bb348c97df44 | 1161 | hspi->State = HAL_SPI_STATE_BUSY_RX; |
lypinator | 0:bb348c97df44 | 1162 | hspi->ErrorCode = HAL_SPI_ERROR_NONE; |
lypinator | 0:bb348c97df44 | 1163 | hspi->pRxBuffPtr = (uint8_t *)pData; |
lypinator | 0:bb348c97df44 | 1164 | hspi->RxXferSize = Size; |
lypinator | 0:bb348c97df44 | 1165 | hspi->RxXferCount = Size; |
lypinator | 0:bb348c97df44 | 1166 | |
lypinator | 0:bb348c97df44 | 1167 | /* Init field not used in handle to zero */ |
lypinator | 0:bb348c97df44 | 1168 | hspi->pTxBuffPtr = (uint8_t *)NULL; |
lypinator | 0:bb348c97df44 | 1169 | hspi->TxXferSize = 0U; |
lypinator | 0:bb348c97df44 | 1170 | hspi->TxXferCount = 0U; |
lypinator | 0:bb348c97df44 | 1171 | hspi->TxISR = NULL; |
lypinator | 0:bb348c97df44 | 1172 | |
lypinator | 0:bb348c97df44 | 1173 | /* Set the function for IT treatment */ |
lypinator | 0:bb348c97df44 | 1174 | if(hspi->Init.DataSize > SPI_DATASIZE_8BIT ) |
lypinator | 0:bb348c97df44 | 1175 | { |
lypinator | 0:bb348c97df44 | 1176 | hspi->RxISR = SPI_RxISR_16BIT; |
lypinator | 0:bb348c97df44 | 1177 | } |
lypinator | 0:bb348c97df44 | 1178 | else |
lypinator | 0:bb348c97df44 | 1179 | { |
lypinator | 0:bb348c97df44 | 1180 | hspi->RxISR = SPI_RxISR_8BIT; |
lypinator | 0:bb348c97df44 | 1181 | } |
lypinator | 0:bb348c97df44 | 1182 | |
lypinator | 0:bb348c97df44 | 1183 | /* Configure communication direction : 1Line */ |
lypinator | 0:bb348c97df44 | 1184 | if(hspi->Init.Direction == SPI_DIRECTION_1LINE) |
lypinator | 0:bb348c97df44 | 1185 | { |
lypinator | 0:bb348c97df44 | 1186 | SPI_1LINE_RX(hspi); |
lypinator | 0:bb348c97df44 | 1187 | } |
lypinator | 0:bb348c97df44 | 1188 | |
lypinator | 0:bb348c97df44 | 1189 | #if (USE_SPI_CRC != 0U) |
lypinator | 0:bb348c97df44 | 1190 | /* Reset CRC Calculation */ |
lypinator | 0:bb348c97df44 | 1191 | if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) |
lypinator | 0:bb348c97df44 | 1192 | { |
lypinator | 0:bb348c97df44 | 1193 | SPI_RESET_CRC(hspi); |
lypinator | 0:bb348c97df44 | 1194 | } |
lypinator | 0:bb348c97df44 | 1195 | #endif /* USE_SPI_CRC */ |
lypinator | 0:bb348c97df44 | 1196 | |
lypinator | 0:bb348c97df44 | 1197 | /* Enable TXE and ERR interrupt */ |
lypinator | 0:bb348c97df44 | 1198 | __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); |
lypinator | 0:bb348c97df44 | 1199 | |
lypinator | 0:bb348c97df44 | 1200 | /* Note : The SPI must be enabled after unlocking current process |
lypinator | 0:bb348c97df44 | 1201 | to avoid the risk of SPI interrupt handle execution before current |
lypinator | 0:bb348c97df44 | 1202 | process unlock */ |
lypinator | 0:bb348c97df44 | 1203 | |
lypinator | 0:bb348c97df44 | 1204 | /* Check if the SPI is already enabled */ |
lypinator | 0:bb348c97df44 | 1205 | if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) |
lypinator | 0:bb348c97df44 | 1206 | { |
lypinator | 0:bb348c97df44 | 1207 | /* Enable SPI peripheral */ |
lypinator | 0:bb348c97df44 | 1208 | __HAL_SPI_ENABLE(hspi); |
lypinator | 0:bb348c97df44 | 1209 | } |
lypinator | 0:bb348c97df44 | 1210 | |
lypinator | 0:bb348c97df44 | 1211 | error : |
lypinator | 0:bb348c97df44 | 1212 | /* Process Unlocked */ |
lypinator | 0:bb348c97df44 | 1213 | __HAL_UNLOCK(hspi); |
lypinator | 0:bb348c97df44 | 1214 | return errorcode; |
lypinator | 0:bb348c97df44 | 1215 | } |
lypinator | 0:bb348c97df44 | 1216 | |
lypinator | 0:bb348c97df44 | 1217 | /** |
lypinator | 0:bb348c97df44 | 1218 | * @brief Transmit and Receive an amount of data in non-blocking mode with Interrupt. |
lypinator | 0:bb348c97df44 | 1219 | * @param hspi pointer to a SPI_HandleTypeDef structure that contains |
lypinator | 0:bb348c97df44 | 1220 | * the configuration information for SPI module. |
lypinator | 0:bb348c97df44 | 1221 | * @param pTxData pointer to transmission data buffer |
lypinator | 0:bb348c97df44 | 1222 | * @param pRxData pointer to reception data buffer |
lypinator | 0:bb348c97df44 | 1223 | * @param Size amount of data to be sent and received |
lypinator | 0:bb348c97df44 | 1224 | * @retval HAL status |
lypinator | 0:bb348c97df44 | 1225 | */ |
lypinator | 0:bb348c97df44 | 1226 | HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) |
lypinator | 0:bb348c97df44 | 1227 | { |
lypinator | 0:bb348c97df44 | 1228 | uint32_t tmp = 0U, tmp1 = 0U; |
lypinator | 0:bb348c97df44 | 1229 | HAL_StatusTypeDef errorcode = HAL_OK; |
lypinator | 0:bb348c97df44 | 1230 | |
lypinator | 0:bb348c97df44 | 1231 | /* Check Direction parameter */ |
lypinator | 0:bb348c97df44 | 1232 | assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); |
lypinator | 0:bb348c97df44 | 1233 | |
lypinator | 0:bb348c97df44 | 1234 | /* Process locked */ |
lypinator | 0:bb348c97df44 | 1235 | __HAL_LOCK(hspi); |
lypinator | 0:bb348c97df44 | 1236 | |
lypinator | 0:bb348c97df44 | 1237 | tmp = hspi->State; |
lypinator | 0:bb348c97df44 | 1238 | tmp1 = hspi->Init.Mode; |
lypinator | 0:bb348c97df44 | 1239 | |
lypinator | 0:bb348c97df44 | 1240 | if(!((tmp == HAL_SPI_STATE_READY) || \ |
lypinator | 0:bb348c97df44 | 1241 | ((tmp1 == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp == HAL_SPI_STATE_BUSY_RX)))) |
lypinator | 0:bb348c97df44 | 1242 | { |
lypinator | 0:bb348c97df44 | 1243 | errorcode = HAL_BUSY; |
lypinator | 0:bb348c97df44 | 1244 | goto error; |
lypinator | 0:bb348c97df44 | 1245 | } |
lypinator | 0:bb348c97df44 | 1246 | |
lypinator | 0:bb348c97df44 | 1247 | if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0)) |
lypinator | 0:bb348c97df44 | 1248 | { |
lypinator | 0:bb348c97df44 | 1249 | errorcode = HAL_ERROR; |
lypinator | 0:bb348c97df44 | 1250 | goto error; |
lypinator | 0:bb348c97df44 | 1251 | } |
lypinator | 0:bb348c97df44 | 1252 | |
lypinator | 0:bb348c97df44 | 1253 | /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ |
lypinator | 0:bb348c97df44 | 1254 | if(hspi->State == HAL_SPI_STATE_READY) |
lypinator | 0:bb348c97df44 | 1255 | { |
lypinator | 0:bb348c97df44 | 1256 | hspi->State = HAL_SPI_STATE_BUSY_TX_RX; |
lypinator | 0:bb348c97df44 | 1257 | } |
lypinator | 0:bb348c97df44 | 1258 | |
lypinator | 0:bb348c97df44 | 1259 | /* Set the transaction information */ |
lypinator | 0:bb348c97df44 | 1260 | hspi->ErrorCode = HAL_SPI_ERROR_NONE; |
lypinator | 0:bb348c97df44 | 1261 | hspi->pTxBuffPtr = (uint8_t *)pTxData; |
lypinator | 0:bb348c97df44 | 1262 | hspi->TxXferSize = Size; |
lypinator | 0:bb348c97df44 | 1263 | hspi->TxXferCount = Size; |
lypinator | 0:bb348c97df44 | 1264 | hspi->pRxBuffPtr = (uint8_t *)pRxData; |
lypinator | 0:bb348c97df44 | 1265 | hspi->RxXferSize = Size; |
lypinator | 0:bb348c97df44 | 1266 | hspi->RxXferCount = Size; |
lypinator | 0:bb348c97df44 | 1267 | |
lypinator | 0:bb348c97df44 | 1268 | /* Set the function for IT treatment */ |
lypinator | 0:bb348c97df44 | 1269 | if(hspi->Init.DataSize > SPI_DATASIZE_8BIT ) |
lypinator | 0:bb348c97df44 | 1270 | { |
lypinator | 0:bb348c97df44 | 1271 | hspi->RxISR = SPI_2linesRxISR_16BIT; |
lypinator | 0:bb348c97df44 | 1272 | hspi->TxISR = SPI_2linesTxISR_16BIT; |
lypinator | 0:bb348c97df44 | 1273 | } |
lypinator | 0:bb348c97df44 | 1274 | else |
lypinator | 0:bb348c97df44 | 1275 | { |
lypinator | 0:bb348c97df44 | 1276 | hspi->RxISR = SPI_2linesRxISR_8BIT; |
lypinator | 0:bb348c97df44 | 1277 | hspi->TxISR = SPI_2linesTxISR_8BIT; |
lypinator | 0:bb348c97df44 | 1278 | } |
lypinator | 0:bb348c97df44 | 1279 | |
lypinator | 0:bb348c97df44 | 1280 | #if (USE_SPI_CRC != 0U) |
lypinator | 0:bb348c97df44 | 1281 | /* Reset CRC Calculation */ |
lypinator | 0:bb348c97df44 | 1282 | if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) |
lypinator | 0:bb348c97df44 | 1283 | { |
lypinator | 0:bb348c97df44 | 1284 | SPI_RESET_CRC(hspi); |
lypinator | 0:bb348c97df44 | 1285 | } |
lypinator | 0:bb348c97df44 | 1286 | #endif /* USE_SPI_CRC */ |
lypinator | 0:bb348c97df44 | 1287 | |
lypinator | 0:bb348c97df44 | 1288 | /* Enable TXE, RXNE and ERR interrupt */ |
lypinator | 0:bb348c97df44 | 1289 | __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); |
lypinator | 0:bb348c97df44 | 1290 | |
lypinator | 0:bb348c97df44 | 1291 | /* Check if the SPI is already enabled */ |
lypinator | 0:bb348c97df44 | 1292 | if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) |
lypinator | 0:bb348c97df44 | 1293 | { |
lypinator | 0:bb348c97df44 | 1294 | /* Enable SPI peripheral */ |
lypinator | 0:bb348c97df44 | 1295 | __HAL_SPI_ENABLE(hspi); |
lypinator | 0:bb348c97df44 | 1296 | } |
lypinator | 0:bb348c97df44 | 1297 | |
lypinator | 0:bb348c97df44 | 1298 | error : |
lypinator | 0:bb348c97df44 | 1299 | /* Process Unlocked */ |
lypinator | 0:bb348c97df44 | 1300 | __HAL_UNLOCK(hspi); |
lypinator | 0:bb348c97df44 | 1301 | return errorcode; |
lypinator | 0:bb348c97df44 | 1302 | } |
lypinator | 0:bb348c97df44 | 1303 | |
lypinator | 0:bb348c97df44 | 1304 | /** |
lypinator | 0:bb348c97df44 | 1305 | * @brief Transmit an amount of data in non-blocking mode with DMA. |
lypinator | 0:bb348c97df44 | 1306 | * @param hspi pointer to a SPI_HandleTypeDef structure that contains |
lypinator | 0:bb348c97df44 | 1307 | * the configuration information for SPI module. |
lypinator | 0:bb348c97df44 | 1308 | * @param pData pointer to data buffer |
lypinator | 0:bb348c97df44 | 1309 | * @param Size amount of data to be sent |
lypinator | 0:bb348c97df44 | 1310 | * @retval HAL status |
lypinator | 0:bb348c97df44 | 1311 | */ |
lypinator | 0:bb348c97df44 | 1312 | HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) |
lypinator | 0:bb348c97df44 | 1313 | { |
lypinator | 0:bb348c97df44 | 1314 | HAL_StatusTypeDef errorcode = HAL_OK; |
lypinator | 0:bb348c97df44 | 1315 | |
lypinator | 0:bb348c97df44 | 1316 | /* Check Direction parameter */ |
lypinator | 0:bb348c97df44 | 1317 | assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); |
lypinator | 0:bb348c97df44 | 1318 | |
lypinator | 0:bb348c97df44 | 1319 | /* Process Locked */ |
lypinator | 0:bb348c97df44 | 1320 | __HAL_LOCK(hspi); |
lypinator | 0:bb348c97df44 | 1321 | |
lypinator | 0:bb348c97df44 | 1322 | if(hspi->State != HAL_SPI_STATE_READY) |
lypinator | 0:bb348c97df44 | 1323 | { |
lypinator | 0:bb348c97df44 | 1324 | errorcode = HAL_BUSY; |
lypinator | 0:bb348c97df44 | 1325 | goto error; |
lypinator | 0:bb348c97df44 | 1326 | } |
lypinator | 0:bb348c97df44 | 1327 | |
lypinator | 0:bb348c97df44 | 1328 | if((pData == NULL) || (Size == 0)) |
lypinator | 0:bb348c97df44 | 1329 | { |
lypinator | 0:bb348c97df44 | 1330 | errorcode = HAL_ERROR; |
lypinator | 0:bb348c97df44 | 1331 | goto error; |
lypinator | 0:bb348c97df44 | 1332 | } |
lypinator | 0:bb348c97df44 | 1333 | |
lypinator | 0:bb348c97df44 | 1334 | /* Set the transaction information */ |
lypinator | 0:bb348c97df44 | 1335 | hspi->State = HAL_SPI_STATE_BUSY_TX; |
lypinator | 0:bb348c97df44 | 1336 | hspi->ErrorCode = HAL_SPI_ERROR_NONE; |
lypinator | 0:bb348c97df44 | 1337 | hspi->pTxBuffPtr = (uint8_t *)pData; |
lypinator | 0:bb348c97df44 | 1338 | hspi->TxXferSize = Size; |
lypinator | 0:bb348c97df44 | 1339 | hspi->TxXferCount = Size; |
lypinator | 0:bb348c97df44 | 1340 | |
lypinator | 0:bb348c97df44 | 1341 | /* Init field not used in handle to zero */ |
lypinator | 0:bb348c97df44 | 1342 | hspi->pRxBuffPtr = (uint8_t *)NULL; |
lypinator | 0:bb348c97df44 | 1343 | hspi->TxISR = NULL; |
lypinator | 0:bb348c97df44 | 1344 | hspi->RxISR = NULL; |
lypinator | 0:bb348c97df44 | 1345 | hspi->RxXferSize = 0U; |
lypinator | 0:bb348c97df44 | 1346 | hspi->RxXferCount = 0U; |
lypinator | 0:bb348c97df44 | 1347 | |
lypinator | 0:bb348c97df44 | 1348 | /* Configure communication direction : 1Line */ |
lypinator | 0:bb348c97df44 | 1349 | if(hspi->Init.Direction == SPI_DIRECTION_1LINE) |
lypinator | 0:bb348c97df44 | 1350 | { |
lypinator | 0:bb348c97df44 | 1351 | SPI_1LINE_TX(hspi); |
lypinator | 0:bb348c97df44 | 1352 | } |
lypinator | 0:bb348c97df44 | 1353 | |
lypinator | 0:bb348c97df44 | 1354 | #if (USE_SPI_CRC != 0U) |
lypinator | 0:bb348c97df44 | 1355 | /* Reset CRC Calculation */ |
lypinator | 0:bb348c97df44 | 1356 | if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) |
lypinator | 0:bb348c97df44 | 1357 | { |
lypinator | 0:bb348c97df44 | 1358 | SPI_RESET_CRC(hspi); |
lypinator | 0:bb348c97df44 | 1359 | } |
lypinator | 0:bb348c97df44 | 1360 | #endif /* USE_SPI_CRC */ |
lypinator | 0:bb348c97df44 | 1361 | |
lypinator | 0:bb348c97df44 | 1362 | /* Set the SPI TxDMA Half transfer complete callback */ |
lypinator | 0:bb348c97df44 | 1363 | hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt; |
lypinator | 0:bb348c97df44 | 1364 | |
lypinator | 0:bb348c97df44 | 1365 | /* Set the SPI TxDMA transfer complete callback */ |
lypinator | 0:bb348c97df44 | 1366 | hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt; |
lypinator | 0:bb348c97df44 | 1367 | |
lypinator | 0:bb348c97df44 | 1368 | /* Set the DMA error callback */ |
lypinator | 0:bb348c97df44 | 1369 | hspi->hdmatx->XferErrorCallback = SPI_DMAError; |
lypinator | 0:bb348c97df44 | 1370 | |
lypinator | 0:bb348c97df44 | 1371 | /* Set the DMA AbortCpltCallback */ |
lypinator | 0:bb348c97df44 | 1372 | hspi->hdmatx->XferAbortCallback = NULL; |
lypinator | 0:bb348c97df44 | 1373 | |
lypinator | 0:bb348c97df44 | 1374 | /* Enable the Tx DMA Stream */ |
lypinator | 0:bb348c97df44 | 1375 | HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount); |
lypinator | 0:bb348c97df44 | 1376 | |
lypinator | 0:bb348c97df44 | 1377 | /* Check if the SPI is already enabled */ |
lypinator | 0:bb348c97df44 | 1378 | if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) |
lypinator | 0:bb348c97df44 | 1379 | { |
lypinator | 0:bb348c97df44 | 1380 | /* Enable SPI peripheral */ |
lypinator | 0:bb348c97df44 | 1381 | __HAL_SPI_ENABLE(hspi); |
lypinator | 0:bb348c97df44 | 1382 | } |
lypinator | 0:bb348c97df44 | 1383 | |
lypinator | 0:bb348c97df44 | 1384 | /* Enable the SPI Error Interrupt Bit */ |
lypinator | 0:bb348c97df44 | 1385 | SET_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE); |
lypinator | 0:bb348c97df44 | 1386 | |
lypinator | 0:bb348c97df44 | 1387 | /* Enable Tx DMA Request */ |
lypinator | 0:bb348c97df44 | 1388 | SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); |
lypinator | 0:bb348c97df44 | 1389 | |
lypinator | 0:bb348c97df44 | 1390 | error : |
lypinator | 0:bb348c97df44 | 1391 | /* Process Unlocked */ |
lypinator | 0:bb348c97df44 | 1392 | __HAL_UNLOCK(hspi); |
lypinator | 0:bb348c97df44 | 1393 | return errorcode; |
lypinator | 0:bb348c97df44 | 1394 | } |
lypinator | 0:bb348c97df44 | 1395 | |
lypinator | 0:bb348c97df44 | 1396 | /** |
lypinator | 0:bb348c97df44 | 1397 | * @brief Receive an amount of data in non-blocking mode with DMA. |
lypinator | 0:bb348c97df44 | 1398 | * @param hspi pointer to a SPI_HandleTypeDef structure that contains |
lypinator | 0:bb348c97df44 | 1399 | * the configuration information for SPI module. |
lypinator | 0:bb348c97df44 | 1400 | * @param pData pointer to data buffer |
lypinator | 0:bb348c97df44 | 1401 | * @note When the CRC feature is enabled the pData Length must be Size + 1. |
lypinator | 0:bb348c97df44 | 1402 | * @param Size amount of data to be sent |
lypinator | 0:bb348c97df44 | 1403 | * @retval HAL status |
lypinator | 0:bb348c97df44 | 1404 | */ |
lypinator | 0:bb348c97df44 | 1405 | HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) |
lypinator | 0:bb348c97df44 | 1406 | { |
lypinator | 0:bb348c97df44 | 1407 | HAL_StatusTypeDef errorcode = HAL_OK; |
lypinator | 0:bb348c97df44 | 1408 | |
lypinator | 0:bb348c97df44 | 1409 | if((hspi->Init.Direction == SPI_DIRECTION_2LINES)&&(hspi->Init.Mode == SPI_MODE_MASTER)) |
lypinator | 0:bb348c97df44 | 1410 | { |
lypinator | 0:bb348c97df44 | 1411 | hspi->State = HAL_SPI_STATE_BUSY_RX; |
lypinator | 0:bb348c97df44 | 1412 | /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */ |
lypinator | 0:bb348c97df44 | 1413 | return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size); |
lypinator | 0:bb348c97df44 | 1414 | } |
lypinator | 0:bb348c97df44 | 1415 | |
lypinator | 0:bb348c97df44 | 1416 | /* Process Locked */ |
lypinator | 0:bb348c97df44 | 1417 | __HAL_LOCK(hspi); |
lypinator | 0:bb348c97df44 | 1418 | |
lypinator | 0:bb348c97df44 | 1419 | if(hspi->State != HAL_SPI_STATE_READY) |
lypinator | 0:bb348c97df44 | 1420 | { |
lypinator | 0:bb348c97df44 | 1421 | errorcode = HAL_BUSY; |
lypinator | 0:bb348c97df44 | 1422 | goto error; |
lypinator | 0:bb348c97df44 | 1423 | } |
lypinator | 0:bb348c97df44 | 1424 | |
lypinator | 0:bb348c97df44 | 1425 | if((pData == NULL) || (Size == 0)) |
lypinator | 0:bb348c97df44 | 1426 | { |
lypinator | 0:bb348c97df44 | 1427 | errorcode = HAL_ERROR; |
lypinator | 0:bb348c97df44 | 1428 | goto error; |
lypinator | 0:bb348c97df44 | 1429 | } |
lypinator | 0:bb348c97df44 | 1430 | |
lypinator | 0:bb348c97df44 | 1431 | /* Set the transaction information */ |
lypinator | 0:bb348c97df44 | 1432 | hspi->State = HAL_SPI_STATE_BUSY_RX; |
lypinator | 0:bb348c97df44 | 1433 | hspi->ErrorCode = HAL_SPI_ERROR_NONE; |
lypinator | 0:bb348c97df44 | 1434 | hspi->pRxBuffPtr = (uint8_t *)pData; |
lypinator | 0:bb348c97df44 | 1435 | hspi->RxXferSize = Size; |
lypinator | 0:bb348c97df44 | 1436 | hspi->RxXferCount = Size; |
lypinator | 0:bb348c97df44 | 1437 | |
lypinator | 0:bb348c97df44 | 1438 | /*Init field not used in handle to zero */ |
lypinator | 0:bb348c97df44 | 1439 | hspi->RxISR = NULL; |
lypinator | 0:bb348c97df44 | 1440 | hspi->TxISR = NULL; |
lypinator | 0:bb348c97df44 | 1441 | hspi->TxXferSize = 0U; |
lypinator | 0:bb348c97df44 | 1442 | hspi->TxXferCount = 0U; |
lypinator | 0:bb348c97df44 | 1443 | |
lypinator | 0:bb348c97df44 | 1444 | /* Configure communication direction : 1Line */ |
lypinator | 0:bb348c97df44 | 1445 | if(hspi->Init.Direction == SPI_DIRECTION_1LINE) |
lypinator | 0:bb348c97df44 | 1446 | { |
lypinator | 0:bb348c97df44 | 1447 | SPI_1LINE_RX(hspi); |
lypinator | 0:bb348c97df44 | 1448 | } |
lypinator | 0:bb348c97df44 | 1449 | |
lypinator | 0:bb348c97df44 | 1450 | #if (USE_SPI_CRC != 0U) |
lypinator | 0:bb348c97df44 | 1451 | /* Reset CRC Calculation */ |
lypinator | 0:bb348c97df44 | 1452 | if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) |
lypinator | 0:bb348c97df44 | 1453 | { |
lypinator | 0:bb348c97df44 | 1454 | SPI_RESET_CRC(hspi); |
lypinator | 0:bb348c97df44 | 1455 | } |
lypinator | 0:bb348c97df44 | 1456 | #endif /* USE_SPI_CRC */ |
lypinator | 0:bb348c97df44 | 1457 | |
lypinator | 0:bb348c97df44 | 1458 | /* Set the SPI RxDMA Half transfer complete callback */ |
lypinator | 0:bb348c97df44 | 1459 | hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt; |
lypinator | 0:bb348c97df44 | 1460 | |
lypinator | 0:bb348c97df44 | 1461 | /* Set the SPI Rx DMA transfer complete callback */ |
lypinator | 0:bb348c97df44 | 1462 | hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt; |
lypinator | 0:bb348c97df44 | 1463 | |
lypinator | 0:bb348c97df44 | 1464 | /* Set the DMA error callback */ |
lypinator | 0:bb348c97df44 | 1465 | hspi->hdmarx->XferErrorCallback = SPI_DMAError; |
lypinator | 0:bb348c97df44 | 1466 | |
lypinator | 0:bb348c97df44 | 1467 | /* Set the DMA AbortCpltCallback */ |
lypinator | 0:bb348c97df44 | 1468 | hspi->hdmarx->XferAbortCallback = NULL; |
lypinator | 0:bb348c97df44 | 1469 | |
lypinator | 0:bb348c97df44 | 1470 | /* Enable the Rx DMA Stream */ |
lypinator | 0:bb348c97df44 | 1471 | HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount); |
lypinator | 0:bb348c97df44 | 1472 | |
lypinator | 0:bb348c97df44 | 1473 | /* Check if the SPI is already enabled */ |
lypinator | 0:bb348c97df44 | 1474 | if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) |
lypinator | 0:bb348c97df44 | 1475 | { |
lypinator | 0:bb348c97df44 | 1476 | /* Enable SPI peripheral */ |
lypinator | 0:bb348c97df44 | 1477 | __HAL_SPI_ENABLE(hspi); |
lypinator | 0:bb348c97df44 | 1478 | } |
lypinator | 0:bb348c97df44 | 1479 | |
lypinator | 0:bb348c97df44 | 1480 | /* Enable the SPI Error Interrupt Bit */ |
lypinator | 0:bb348c97df44 | 1481 | SET_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE); |
lypinator | 0:bb348c97df44 | 1482 | |
lypinator | 0:bb348c97df44 | 1483 | /* Enable Rx DMA Request */ |
lypinator | 0:bb348c97df44 | 1484 | SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); |
lypinator | 0:bb348c97df44 | 1485 | |
lypinator | 0:bb348c97df44 | 1486 | error: |
lypinator | 0:bb348c97df44 | 1487 | /* Process Unlocked */ |
lypinator | 0:bb348c97df44 | 1488 | __HAL_UNLOCK(hspi); |
lypinator | 0:bb348c97df44 | 1489 | return errorcode; |
lypinator | 0:bb348c97df44 | 1490 | } |
lypinator | 0:bb348c97df44 | 1491 | |
lypinator | 0:bb348c97df44 | 1492 | /** |
lypinator | 0:bb348c97df44 | 1493 | * @brief Transmit and Receive an amount of data in non-blocking mode with DMA. |
lypinator | 0:bb348c97df44 | 1494 | * @param hspi pointer to a SPI_HandleTypeDef structure that contains |
lypinator | 0:bb348c97df44 | 1495 | * the configuration information for SPI module. |
lypinator | 0:bb348c97df44 | 1496 | * @param pTxData pointer to transmission data buffer |
lypinator | 0:bb348c97df44 | 1497 | * @param pRxData pointer to reception data buffer |
lypinator | 0:bb348c97df44 | 1498 | * @note When the CRC feature is enabled the pRxData Length must be Size + 1 |
lypinator | 0:bb348c97df44 | 1499 | * @param Size amount of data to be sent |
lypinator | 0:bb348c97df44 | 1500 | * @retval HAL status |
lypinator | 0:bb348c97df44 | 1501 | */ |
lypinator | 0:bb348c97df44 | 1502 | HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) |
lypinator | 0:bb348c97df44 | 1503 | { |
lypinator | 0:bb348c97df44 | 1504 | uint32_t tmp = 0U, tmp1 = 0U; |
lypinator | 0:bb348c97df44 | 1505 | HAL_StatusTypeDef errorcode = HAL_OK; |
lypinator | 0:bb348c97df44 | 1506 | |
lypinator | 0:bb348c97df44 | 1507 | /* Check Direction parameter */ |
lypinator | 0:bb348c97df44 | 1508 | assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); |
lypinator | 0:bb348c97df44 | 1509 | |
lypinator | 0:bb348c97df44 | 1510 | /* Process locked */ |
lypinator | 0:bb348c97df44 | 1511 | __HAL_LOCK(hspi); |
lypinator | 0:bb348c97df44 | 1512 | |
lypinator | 0:bb348c97df44 | 1513 | tmp = hspi->State; |
lypinator | 0:bb348c97df44 | 1514 | tmp1 = hspi->Init.Mode; |
lypinator | 0:bb348c97df44 | 1515 | if(!((tmp == HAL_SPI_STATE_READY) || |
lypinator | 0:bb348c97df44 | 1516 | ((tmp1 == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp == HAL_SPI_STATE_BUSY_RX)))) |
lypinator | 0:bb348c97df44 | 1517 | { |
lypinator | 0:bb348c97df44 | 1518 | errorcode = HAL_BUSY; |
lypinator | 0:bb348c97df44 | 1519 | goto error; |
lypinator | 0:bb348c97df44 | 1520 | } |
lypinator | 0:bb348c97df44 | 1521 | |
lypinator | 0:bb348c97df44 | 1522 | if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0)) |
lypinator | 0:bb348c97df44 | 1523 | { |
lypinator | 0:bb348c97df44 | 1524 | errorcode = HAL_ERROR; |
lypinator | 0:bb348c97df44 | 1525 | goto error; |
lypinator | 0:bb348c97df44 | 1526 | } |
lypinator | 0:bb348c97df44 | 1527 | |
lypinator | 0:bb348c97df44 | 1528 | /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ |
lypinator | 0:bb348c97df44 | 1529 | if(hspi->State == HAL_SPI_STATE_READY) |
lypinator | 0:bb348c97df44 | 1530 | { |
lypinator | 0:bb348c97df44 | 1531 | hspi->State = HAL_SPI_STATE_BUSY_TX_RX; |
lypinator | 0:bb348c97df44 | 1532 | } |
lypinator | 0:bb348c97df44 | 1533 | |
lypinator | 0:bb348c97df44 | 1534 | /* Set the transaction information */ |
lypinator | 0:bb348c97df44 | 1535 | hspi->ErrorCode = HAL_SPI_ERROR_NONE; |
lypinator | 0:bb348c97df44 | 1536 | hspi->pTxBuffPtr = (uint8_t*)pTxData; |
lypinator | 0:bb348c97df44 | 1537 | hspi->TxXferSize = Size; |
lypinator | 0:bb348c97df44 | 1538 | hspi->TxXferCount = Size; |
lypinator | 0:bb348c97df44 | 1539 | hspi->pRxBuffPtr = (uint8_t*)pRxData; |
lypinator | 0:bb348c97df44 | 1540 | hspi->RxXferSize = Size; |
lypinator | 0:bb348c97df44 | 1541 | hspi->RxXferCount = Size; |
lypinator | 0:bb348c97df44 | 1542 | |
lypinator | 0:bb348c97df44 | 1543 | /* Init field not used in handle to zero */ |
lypinator | 0:bb348c97df44 | 1544 | hspi->RxISR = NULL; |
lypinator | 0:bb348c97df44 | 1545 | hspi->TxISR = NULL; |
lypinator | 0:bb348c97df44 | 1546 | |
lypinator | 0:bb348c97df44 | 1547 | #if (USE_SPI_CRC != 0U) |
lypinator | 0:bb348c97df44 | 1548 | /* Reset CRC Calculation */ |
lypinator | 0:bb348c97df44 | 1549 | if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) |
lypinator | 0:bb348c97df44 | 1550 | { |
lypinator | 0:bb348c97df44 | 1551 | SPI_RESET_CRC(hspi); |
lypinator | 0:bb348c97df44 | 1552 | } |
lypinator | 0:bb348c97df44 | 1553 | #endif /* USE_SPI_CRC */ |
lypinator | 0:bb348c97df44 | 1554 | |
lypinator | 0:bb348c97df44 | 1555 | /* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */ |
lypinator | 0:bb348c97df44 | 1556 | if(hspi->State == HAL_SPI_STATE_BUSY_RX) |
lypinator | 0:bb348c97df44 | 1557 | { |
lypinator | 0:bb348c97df44 | 1558 | /* Set the SPI Rx DMA Half transfer complete callback */ |
lypinator | 0:bb348c97df44 | 1559 | hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt; |
lypinator | 0:bb348c97df44 | 1560 | hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt; |
lypinator | 0:bb348c97df44 | 1561 | } |
lypinator | 0:bb348c97df44 | 1562 | else |
lypinator | 0:bb348c97df44 | 1563 | { |
lypinator | 0:bb348c97df44 | 1564 | /* Set the SPI Tx/Rx DMA Half transfer complete callback */ |
lypinator | 0:bb348c97df44 | 1565 | hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt; |
lypinator | 0:bb348c97df44 | 1566 | hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt; |
lypinator | 0:bb348c97df44 | 1567 | } |
lypinator | 0:bb348c97df44 | 1568 | |
lypinator | 0:bb348c97df44 | 1569 | /* Set the DMA error callback */ |
lypinator | 0:bb348c97df44 | 1570 | hspi->hdmarx->XferErrorCallback = SPI_DMAError; |
lypinator | 0:bb348c97df44 | 1571 | |
lypinator | 0:bb348c97df44 | 1572 | /* Set the DMA AbortCpltCallback */ |
lypinator | 0:bb348c97df44 | 1573 | hspi->hdmarx->XferAbortCallback = NULL; |
lypinator | 0:bb348c97df44 | 1574 | |
lypinator | 0:bb348c97df44 | 1575 | /* Enable the Rx DMA Stream */ |
lypinator | 0:bb348c97df44 | 1576 | HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount); |
lypinator | 0:bb348c97df44 | 1577 | |
lypinator | 0:bb348c97df44 | 1578 | /* Enable Rx DMA Request */ |
lypinator | 0:bb348c97df44 | 1579 | SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); |
lypinator | 0:bb348c97df44 | 1580 | |
lypinator | 0:bb348c97df44 | 1581 | /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing |
lypinator | 0:bb348c97df44 | 1582 | is performed in DMA reception complete callback */ |
lypinator | 0:bb348c97df44 | 1583 | hspi->hdmatx->XferHalfCpltCallback = NULL; |
lypinator | 0:bb348c97df44 | 1584 | hspi->hdmatx->XferCpltCallback = NULL; |
lypinator | 0:bb348c97df44 | 1585 | hspi->hdmatx->XferErrorCallback = NULL; |
lypinator | 0:bb348c97df44 | 1586 | hspi->hdmatx->XferAbortCallback = NULL; |
lypinator | 0:bb348c97df44 | 1587 | |
lypinator | 0:bb348c97df44 | 1588 | /* Enable the Tx DMA Stream */ |
lypinator | 0:bb348c97df44 | 1589 | HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount); |
lypinator | 0:bb348c97df44 | 1590 | |
lypinator | 0:bb348c97df44 | 1591 | /* Check if the SPI is already enabled */ |
lypinator | 0:bb348c97df44 | 1592 | if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) |
lypinator | 0:bb348c97df44 | 1593 | { |
lypinator | 0:bb348c97df44 | 1594 | /* Enable SPI peripheral */ |
lypinator | 0:bb348c97df44 | 1595 | __HAL_SPI_ENABLE(hspi); |
lypinator | 0:bb348c97df44 | 1596 | } |
lypinator | 0:bb348c97df44 | 1597 | /* Enable the SPI Error Interrupt Bit */ |
lypinator | 0:bb348c97df44 | 1598 | SET_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE); |
lypinator | 0:bb348c97df44 | 1599 | |
lypinator | 0:bb348c97df44 | 1600 | /* Enable Tx DMA Request */ |
lypinator | 0:bb348c97df44 | 1601 | SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); |
lypinator | 0:bb348c97df44 | 1602 | |
lypinator | 0:bb348c97df44 | 1603 | error : |
lypinator | 0:bb348c97df44 | 1604 | /* Process Unlocked */ |
lypinator | 0:bb348c97df44 | 1605 | __HAL_UNLOCK(hspi); |
lypinator | 0:bb348c97df44 | 1606 | return errorcode; |
lypinator | 0:bb348c97df44 | 1607 | } |
lypinator | 0:bb348c97df44 | 1608 | |
lypinator | 0:bb348c97df44 | 1609 | /** |
lypinator | 0:bb348c97df44 | 1610 | * @brief Abort ongoing transfer (blocking mode). |
lypinator | 0:bb348c97df44 | 1611 | * @param hspi SPI handle. |
lypinator | 0:bb348c97df44 | 1612 | * @note This procedure could be used for aborting any ongoing transfer (Tx and Rx), |
lypinator | 0:bb348c97df44 | 1613 | * started in Interrupt or DMA mode. |
lypinator | 0:bb348c97df44 | 1614 | * This procedure performs following operations : |
lypinator | 0:bb348c97df44 | 1615 | * - Disable SPI Interrupts (depending of transfer direction) |
lypinator | 0:bb348c97df44 | 1616 | * - Disable the DMA transfer in the peripheral register (if enabled) |
lypinator | 0:bb348c97df44 | 1617 | * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) |
lypinator | 0:bb348c97df44 | 1618 | * - Set handle State to READY |
lypinator | 0:bb348c97df44 | 1619 | * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. |
lypinator | 0:bb348c97df44 | 1620 | * @note Once transfer is aborted, the __HAL_SPI_CLEAR_OVRFLAG() macro must be called in user application |
lypinator | 0:bb348c97df44 | 1621 | * before starting new SPI receive process. |
lypinator | 0:bb348c97df44 | 1622 | * @retval HAL status |
lypinator | 0:bb348c97df44 | 1623 | */ |
lypinator | 0:bb348c97df44 | 1624 | HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi) |
lypinator | 0:bb348c97df44 | 1625 | { |
lypinator | 0:bb348c97df44 | 1626 | __IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U); |
lypinator | 0:bb348c97df44 | 1627 | |
lypinator | 0:bb348c97df44 | 1628 | /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */ |
lypinator | 0:bb348c97df44 | 1629 | if(HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE)) |
lypinator | 0:bb348c97df44 | 1630 | { |
lypinator | 0:bb348c97df44 | 1631 | hspi->TxISR = SPI_AbortTx_ISR; |
lypinator | 0:bb348c97df44 | 1632 | } |
lypinator | 0:bb348c97df44 | 1633 | |
lypinator | 0:bb348c97df44 | 1634 | if(HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE)) |
lypinator | 0:bb348c97df44 | 1635 | { |
lypinator | 0:bb348c97df44 | 1636 | hspi->RxISR = SPI_AbortRx_ISR; |
lypinator | 0:bb348c97df44 | 1637 | } |
lypinator | 0:bb348c97df44 | 1638 | |
lypinator | 0:bb348c97df44 | 1639 | /* Clear ERRIE interrupts in case of DMA Mode */ |
lypinator | 0:bb348c97df44 | 1640 | CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE); |
lypinator | 0:bb348c97df44 | 1641 | |
lypinator | 0:bb348c97df44 | 1642 | /* Disable the SPI DMA Tx or SPI DMA Rx request if enabled */ |
lypinator | 0:bb348c97df44 | 1643 | if ((HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) || (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))) |
lypinator | 0:bb348c97df44 | 1644 | { |
lypinator | 0:bb348c97df44 | 1645 | /* Abort the SPI DMA Tx channel : use blocking DMA Abort API (no callback) */ |
lypinator | 0:bb348c97df44 | 1646 | if(hspi->hdmatx != NULL) |
lypinator | 0:bb348c97df44 | 1647 | { |
lypinator | 0:bb348c97df44 | 1648 | /* Set the SPI DMA Abort callback : |
lypinator | 0:bb348c97df44 | 1649 | will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */ |
lypinator | 0:bb348c97df44 | 1650 | hspi->hdmatx->XferAbortCallback = NULL; |
lypinator | 0:bb348c97df44 | 1651 | |
lypinator | 0:bb348c97df44 | 1652 | /* Abort DMA Tx Handle linked to SPI Peripheral */ |
lypinator | 0:bb348c97df44 | 1653 | HAL_DMA_Abort(hspi->hdmatx); |
lypinator | 0:bb348c97df44 | 1654 | |
lypinator | 0:bb348c97df44 | 1655 | /* Disable Tx DMA Request */ |
lypinator | 0:bb348c97df44 | 1656 | CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN)); |
lypinator | 0:bb348c97df44 | 1657 | |
lypinator | 0:bb348c97df44 | 1658 | /* Wait until TXE flag is set */ |
lypinator | 0:bb348c97df44 | 1659 | do |
lypinator | 0:bb348c97df44 | 1660 | { |
lypinator | 0:bb348c97df44 | 1661 | if(count-- == 0U) |
lypinator | 0:bb348c97df44 | 1662 | { |
lypinator | 0:bb348c97df44 | 1663 | SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); |
lypinator | 0:bb348c97df44 | 1664 | break; |
lypinator | 0:bb348c97df44 | 1665 | } |
lypinator | 0:bb348c97df44 | 1666 | } |
lypinator | 0:bb348c97df44 | 1667 | while((hspi->Instance->SR & SPI_FLAG_TXE) == RESET); |
lypinator | 0:bb348c97df44 | 1668 | } |
lypinator | 0:bb348c97df44 | 1669 | /* Abort the SPI DMA Rx channel : use blocking DMA Abort API (no callback) */ |
lypinator | 0:bb348c97df44 | 1670 | if(hspi->hdmarx != NULL) |
lypinator | 0:bb348c97df44 | 1671 | { |
lypinator | 0:bb348c97df44 | 1672 | /* Set the SPI DMA Abort callback : |
lypinator | 0:bb348c97df44 | 1673 | will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */ |
lypinator | 0:bb348c97df44 | 1674 | hspi->hdmarx->XferAbortCallback = NULL; |
lypinator | 0:bb348c97df44 | 1675 | |
lypinator | 0:bb348c97df44 | 1676 | /* Abort DMA Rx Handle linked to SPI Peripheral */ |
lypinator | 0:bb348c97df44 | 1677 | HAL_DMA_Abort(hspi->hdmarx); |
lypinator | 0:bb348c97df44 | 1678 | |
lypinator | 0:bb348c97df44 | 1679 | /* Disable peripheral */ |
lypinator | 0:bb348c97df44 | 1680 | __HAL_SPI_DISABLE(hspi); |
lypinator | 0:bb348c97df44 | 1681 | |
lypinator | 0:bb348c97df44 | 1682 | /* Disable Rx DMA Request */ |
lypinator | 0:bb348c97df44 | 1683 | CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXDMAEN)); |
lypinator | 0:bb348c97df44 | 1684 | |
lypinator | 0:bb348c97df44 | 1685 | } |
lypinator | 0:bb348c97df44 | 1686 | } |
lypinator | 0:bb348c97df44 | 1687 | /* Reset Tx and Rx transfer counters */ |
lypinator | 0:bb348c97df44 | 1688 | hspi->RxXferCount = 0U; |
lypinator | 0:bb348c97df44 | 1689 | hspi->TxXferCount = 0U; |
lypinator | 0:bb348c97df44 | 1690 | |
lypinator | 0:bb348c97df44 | 1691 | /* Reset errorCode */ |
lypinator | 0:bb348c97df44 | 1692 | hspi->ErrorCode = HAL_SPI_ERROR_NONE; |
lypinator | 0:bb348c97df44 | 1693 | |
lypinator | 0:bb348c97df44 | 1694 | /* Clear the Error flags in the SR register */ |
lypinator | 0:bb348c97df44 | 1695 | __HAL_SPI_CLEAR_OVRFLAG(hspi); |
lypinator | 0:bb348c97df44 | 1696 | __HAL_SPI_CLEAR_FREFLAG(hspi); |
lypinator | 0:bb348c97df44 | 1697 | |
lypinator | 0:bb348c97df44 | 1698 | /* Restore hspi->state to ready */ |
lypinator | 0:bb348c97df44 | 1699 | hspi->State = HAL_SPI_STATE_READY; |
lypinator | 0:bb348c97df44 | 1700 | |
lypinator | 0:bb348c97df44 | 1701 | return HAL_OK; |
lypinator | 0:bb348c97df44 | 1702 | } |
lypinator | 0:bb348c97df44 | 1703 | |
lypinator | 0:bb348c97df44 | 1704 | /** |
lypinator | 0:bb348c97df44 | 1705 | * @brief Abort ongoing transfer (Interrupt mode). |
lypinator | 0:bb348c97df44 | 1706 | * @param hspi SPI handle. |
lypinator | 0:bb348c97df44 | 1707 | * @note This procedure could be used for aborting any ongoing transfer (Tx and Rx), |
lypinator | 0:bb348c97df44 | 1708 | * started in Interrupt or DMA mode. |
lypinator | 0:bb348c97df44 | 1709 | * This procedure performs following operations : |
lypinator | 0:bb348c97df44 | 1710 | * - Disable SPI Interrupts (depending of transfer direction) |
lypinator | 0:bb348c97df44 | 1711 | * - Disable the DMA transfer in the peripheral register (if enabled) |
lypinator | 0:bb348c97df44 | 1712 | * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) |
lypinator | 0:bb348c97df44 | 1713 | * - Set handle State to READY |
lypinator | 0:bb348c97df44 | 1714 | * - At abort completion, call user abort complete callback |
lypinator | 0:bb348c97df44 | 1715 | * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be |
lypinator | 0:bb348c97df44 | 1716 | * considered as completed only when user abort complete callback is executed (not when exiting function). |
lypinator | 0:bb348c97df44 | 1717 | * @note Once transfer is aborted, the __HAL_SPI_CLEAR_OVRFLAG() macro must be called in user application |
lypinator | 0:bb348c97df44 | 1718 | * before starting new SPI receive process. |
lypinator | 0:bb348c97df44 | 1719 | * @retval HAL status |
lypinator | 0:bb348c97df44 | 1720 | */ |
lypinator | 0:bb348c97df44 | 1721 | HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi) |
lypinator | 0:bb348c97df44 | 1722 | { |
lypinator | 0:bb348c97df44 | 1723 | uint32_t abortcplt; |
lypinator | 0:bb348c97df44 | 1724 | |
lypinator | 0:bb348c97df44 | 1725 | /* Change Rx and Tx Irq Handler to Disable TXEIE, RXNEIE and ERRIE interrupts */ |
lypinator | 0:bb348c97df44 | 1726 | if(HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE)) |
lypinator | 0:bb348c97df44 | 1727 | { |
lypinator | 0:bb348c97df44 | 1728 | hspi->TxISR = SPI_AbortTx_ISR; |
lypinator | 0:bb348c97df44 | 1729 | } |
lypinator | 0:bb348c97df44 | 1730 | |
lypinator | 0:bb348c97df44 | 1731 | if(HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE)) |
lypinator | 0:bb348c97df44 | 1732 | { |
lypinator | 0:bb348c97df44 | 1733 | hspi->RxISR = SPI_AbortRx_ISR; |
lypinator | 0:bb348c97df44 | 1734 | } |
lypinator | 0:bb348c97df44 | 1735 | |
lypinator | 0:bb348c97df44 | 1736 | /* Clear ERRIE interrupts in case of DMA Mode */ |
lypinator | 0:bb348c97df44 | 1737 | CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE); |
lypinator | 0:bb348c97df44 | 1738 | |
lypinator | 0:bb348c97df44 | 1739 | abortcplt = 1U; |
lypinator | 0:bb348c97df44 | 1740 | |
lypinator | 0:bb348c97df44 | 1741 | /* If DMA Tx and/or DMA Rx Handles are associated to SPI Handle, DMA Abort complete callbacks should be initialised |
lypinator | 0:bb348c97df44 | 1742 | before any call to DMA Abort functions */ |
lypinator | 0:bb348c97df44 | 1743 | /* DMA Tx Handle is valid */ |
lypinator | 0:bb348c97df44 | 1744 | if(hspi->hdmatx != NULL) |
lypinator | 0:bb348c97df44 | 1745 | { |
lypinator | 0:bb348c97df44 | 1746 | /* Set DMA Abort Complete callback if UART DMA Tx request if enabled. |
lypinator | 0:bb348c97df44 | 1747 | Otherwise, set it to NULL */ |
lypinator | 0:bb348c97df44 | 1748 | if(HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) |
lypinator | 0:bb348c97df44 | 1749 | { |
lypinator | 0:bb348c97df44 | 1750 | hspi->hdmatx->XferAbortCallback = SPI_DMATxAbortCallback; |
lypinator | 0:bb348c97df44 | 1751 | } |
lypinator | 0:bb348c97df44 | 1752 | else |
lypinator | 0:bb348c97df44 | 1753 | { |
lypinator | 0:bb348c97df44 | 1754 | hspi->hdmatx->XferAbortCallback = NULL; |
lypinator | 0:bb348c97df44 | 1755 | } |
lypinator | 0:bb348c97df44 | 1756 | } |
lypinator | 0:bb348c97df44 | 1757 | /* DMA Rx Handle is valid */ |
lypinator | 0:bb348c97df44 | 1758 | if(hspi->hdmarx != NULL) |
lypinator | 0:bb348c97df44 | 1759 | { |
lypinator | 0:bb348c97df44 | 1760 | /* Set DMA Abort Complete callback if UART DMA Rx request if enabled. |
lypinator | 0:bb348c97df44 | 1761 | Otherwise, set it to NULL */ |
lypinator | 0:bb348c97df44 | 1762 | if(HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN)) |
lypinator | 0:bb348c97df44 | 1763 | { |
lypinator | 0:bb348c97df44 | 1764 | hspi->hdmarx->XferAbortCallback = SPI_DMARxAbortCallback; |
lypinator | 0:bb348c97df44 | 1765 | } |
lypinator | 0:bb348c97df44 | 1766 | else |
lypinator | 0:bb348c97df44 | 1767 | { |
lypinator | 0:bb348c97df44 | 1768 | hspi->hdmarx->XferAbortCallback = NULL; |
lypinator | 0:bb348c97df44 | 1769 | } |
lypinator | 0:bb348c97df44 | 1770 | } |
lypinator | 0:bb348c97df44 | 1771 | |
lypinator | 0:bb348c97df44 | 1772 | /* Disable the SPI DMA Tx or the SPI Rx request if enabled */ |
lypinator | 0:bb348c97df44 | 1773 | if((HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) && (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))) |
lypinator | 0:bb348c97df44 | 1774 | { |
lypinator | 0:bb348c97df44 | 1775 | /* Abort the SPI DMA Tx channel */ |
lypinator | 0:bb348c97df44 | 1776 | if(hspi->hdmatx != NULL) |
lypinator | 0:bb348c97df44 | 1777 | { |
lypinator | 0:bb348c97df44 | 1778 | /* Abort DMA Tx Handle linked to SPI Peripheral */ |
lypinator | 0:bb348c97df44 | 1779 | if(HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK) |
lypinator | 0:bb348c97df44 | 1780 | { |
lypinator | 0:bb348c97df44 | 1781 | hspi->hdmatx->XferAbortCallback = NULL; |
lypinator | 0:bb348c97df44 | 1782 | } |
lypinator | 0:bb348c97df44 | 1783 | else |
lypinator | 0:bb348c97df44 | 1784 | { |
lypinator | 0:bb348c97df44 | 1785 | abortcplt = 0U; |
lypinator | 0:bb348c97df44 | 1786 | } |
lypinator | 0:bb348c97df44 | 1787 | } |
lypinator | 0:bb348c97df44 | 1788 | /* Abort the SPI DMA Rx channel */ |
lypinator | 0:bb348c97df44 | 1789 | if(hspi->hdmarx != NULL) |
lypinator | 0:bb348c97df44 | 1790 | { |
lypinator | 0:bb348c97df44 | 1791 | /* Abort DMA Rx Handle linked to SPI Peripheral */ |
lypinator | 0:bb348c97df44 | 1792 | if(HAL_DMA_Abort_IT(hspi->hdmarx)!= HAL_OK) |
lypinator | 0:bb348c97df44 | 1793 | { |
lypinator | 0:bb348c97df44 | 1794 | hspi->hdmarx->XferAbortCallback = NULL; |
lypinator | 0:bb348c97df44 | 1795 | abortcplt = 1U; |
lypinator | 0:bb348c97df44 | 1796 | } |
lypinator | 0:bb348c97df44 | 1797 | else |
lypinator | 0:bb348c97df44 | 1798 | { |
lypinator | 0:bb348c97df44 | 1799 | abortcplt = 0U; |
lypinator | 0:bb348c97df44 | 1800 | } |
lypinator | 0:bb348c97df44 | 1801 | } |
lypinator | 0:bb348c97df44 | 1802 | } |
lypinator | 0:bb348c97df44 | 1803 | |
lypinator | 0:bb348c97df44 | 1804 | /* Disable the SPI DMA Tx or the SPI Rx request if enabled */ |
lypinator | 0:bb348c97df44 | 1805 | if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) |
lypinator | 0:bb348c97df44 | 1806 | { |
lypinator | 0:bb348c97df44 | 1807 | /* Abort the SPI DMA Tx channel */ |
lypinator | 0:bb348c97df44 | 1808 | if(hspi->hdmatx != NULL) |
lypinator | 0:bb348c97df44 | 1809 | { |
lypinator | 0:bb348c97df44 | 1810 | /* Abort DMA Tx Handle linked to SPI Peripheral */ |
lypinator | 0:bb348c97df44 | 1811 | if(HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK) |
lypinator | 0:bb348c97df44 | 1812 | { |
lypinator | 0:bb348c97df44 | 1813 | hspi->hdmatx->XferAbortCallback = NULL; |
lypinator | 0:bb348c97df44 | 1814 | } |
lypinator | 0:bb348c97df44 | 1815 | else |
lypinator | 0:bb348c97df44 | 1816 | { |
lypinator | 0:bb348c97df44 | 1817 | abortcplt = 0U; |
lypinator | 0:bb348c97df44 | 1818 | } |
lypinator | 0:bb348c97df44 | 1819 | } |
lypinator | 0:bb348c97df44 | 1820 | } |
lypinator | 0:bb348c97df44 | 1821 | /* Disable the SPI DMA Tx or the SPI Rx request if enabled */ |
lypinator | 0:bb348c97df44 | 1822 | if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN)) |
lypinator | 0:bb348c97df44 | 1823 | { |
lypinator | 0:bb348c97df44 | 1824 | /* Abort the SPI DMA Rx channel */ |
lypinator | 0:bb348c97df44 | 1825 | if(hspi->hdmarx != NULL) |
lypinator | 0:bb348c97df44 | 1826 | { |
lypinator | 0:bb348c97df44 | 1827 | /* Abort DMA Rx Handle linked to SPI Peripheral */ |
lypinator | 0:bb348c97df44 | 1828 | if(HAL_DMA_Abort_IT(hspi->hdmarx)!= HAL_OK) |
lypinator | 0:bb348c97df44 | 1829 | { |
lypinator | 0:bb348c97df44 | 1830 | hspi->hdmarx->XferAbortCallback = NULL; |
lypinator | 0:bb348c97df44 | 1831 | } |
lypinator | 0:bb348c97df44 | 1832 | else |
lypinator | 0:bb348c97df44 | 1833 | { |
lypinator | 0:bb348c97df44 | 1834 | abortcplt = 0U; |
lypinator | 0:bb348c97df44 | 1835 | } |
lypinator | 0:bb348c97df44 | 1836 | } |
lypinator | 0:bb348c97df44 | 1837 | } |
lypinator | 0:bb348c97df44 | 1838 | |
lypinator | 0:bb348c97df44 | 1839 | if(abortcplt == 1U) |
lypinator | 0:bb348c97df44 | 1840 | { |
lypinator | 0:bb348c97df44 | 1841 | /* Reset Tx and Rx transfer counters */ |
lypinator | 0:bb348c97df44 | 1842 | hspi->RxXferCount = 0U; |
lypinator | 0:bb348c97df44 | 1843 | hspi->TxXferCount = 0U; |
lypinator | 0:bb348c97df44 | 1844 | |
lypinator | 0:bb348c97df44 | 1845 | /* Reset errorCode */ |
lypinator | 0:bb348c97df44 | 1846 | hspi->ErrorCode = HAL_SPI_ERROR_NONE; |
lypinator | 0:bb348c97df44 | 1847 | |
lypinator | 0:bb348c97df44 | 1848 | /* Clear the Error flags in the SR register */ |
lypinator | 0:bb348c97df44 | 1849 | __HAL_SPI_CLEAR_OVRFLAG(hspi); |
lypinator | 0:bb348c97df44 | 1850 | __HAL_SPI_CLEAR_FREFLAG(hspi); |
lypinator | 0:bb348c97df44 | 1851 | |
lypinator | 0:bb348c97df44 | 1852 | /* Restore hspi->State to Ready */ |
lypinator | 0:bb348c97df44 | 1853 | hspi->State = HAL_SPI_STATE_READY; |
lypinator | 0:bb348c97df44 | 1854 | |
lypinator | 0:bb348c97df44 | 1855 | /* As no DMA to be aborted, call directly user Abort complete callback */ |
lypinator | 0:bb348c97df44 | 1856 | HAL_SPI_AbortCpltCallback(hspi); |
lypinator | 0:bb348c97df44 | 1857 | } |
lypinator | 0:bb348c97df44 | 1858 | return HAL_OK; |
lypinator | 0:bb348c97df44 | 1859 | } |
lypinator | 0:bb348c97df44 | 1860 | |
lypinator | 0:bb348c97df44 | 1861 | /** |
lypinator | 0:bb348c97df44 | 1862 | * @brief Pause the DMA Transfer. |
lypinator | 0:bb348c97df44 | 1863 | * @param hspi pointer to a SPI_HandleTypeDef structure that contains |
lypinator | 0:bb348c97df44 | 1864 | * the configuration information for the specified SPI module. |
lypinator | 0:bb348c97df44 | 1865 | * @retval HAL status |
lypinator | 0:bb348c97df44 | 1866 | */ |
lypinator | 0:bb348c97df44 | 1867 | HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi) |
lypinator | 0:bb348c97df44 | 1868 | { |
lypinator | 0:bb348c97df44 | 1869 | /* Process Locked */ |
lypinator | 0:bb348c97df44 | 1870 | __HAL_LOCK(hspi); |
lypinator | 0:bb348c97df44 | 1871 | |
lypinator | 0:bb348c97df44 | 1872 | /* Disable the SPI DMA Tx & Rx requests */ |
lypinator | 0:bb348c97df44 | 1873 | CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); |
lypinator | 0:bb348c97df44 | 1874 | |
lypinator | 0:bb348c97df44 | 1875 | /* Process Unlocked */ |
lypinator | 0:bb348c97df44 | 1876 | __HAL_UNLOCK(hspi); |
lypinator | 0:bb348c97df44 | 1877 | |
lypinator | 0:bb348c97df44 | 1878 | return HAL_OK; |
lypinator | 0:bb348c97df44 | 1879 | } |
lypinator | 0:bb348c97df44 | 1880 | |
lypinator | 0:bb348c97df44 | 1881 | /** |
lypinator | 0:bb348c97df44 | 1882 | * @brief Resume the DMA Transfer. |
lypinator | 0:bb348c97df44 | 1883 | * @param hspi pointer to a SPI_HandleTypeDef structure that contains |
lypinator | 0:bb348c97df44 | 1884 | * the configuration information for the specified SPI module. |
lypinator | 0:bb348c97df44 | 1885 | * @retval HAL status |
lypinator | 0:bb348c97df44 | 1886 | */ |
lypinator | 0:bb348c97df44 | 1887 | HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi) |
lypinator | 0:bb348c97df44 | 1888 | { |
lypinator | 0:bb348c97df44 | 1889 | /* Process Locked */ |
lypinator | 0:bb348c97df44 | 1890 | __HAL_LOCK(hspi); |
lypinator | 0:bb348c97df44 | 1891 | |
lypinator | 0:bb348c97df44 | 1892 | /* Enable the SPI DMA Tx & Rx requests */ |
lypinator | 0:bb348c97df44 | 1893 | SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); |
lypinator | 0:bb348c97df44 | 1894 | |
lypinator | 0:bb348c97df44 | 1895 | /* Process Unlocked */ |
lypinator | 0:bb348c97df44 | 1896 | __HAL_UNLOCK(hspi); |
lypinator | 0:bb348c97df44 | 1897 | |
lypinator | 0:bb348c97df44 | 1898 | return HAL_OK; |
lypinator | 0:bb348c97df44 | 1899 | } |
lypinator | 0:bb348c97df44 | 1900 | |
lypinator | 0:bb348c97df44 | 1901 | /** |
lypinator | 0:bb348c97df44 | 1902 | * @brief Stop the DMA Transfer. |
lypinator | 0:bb348c97df44 | 1903 | * @param hspi pointer to a SPI_HandleTypeDef structure that contains |
lypinator | 0:bb348c97df44 | 1904 | * the configuration information for the specified SPI module. |
lypinator | 0:bb348c97df44 | 1905 | * @retval HAL status |
lypinator | 0:bb348c97df44 | 1906 | */ |
lypinator | 0:bb348c97df44 | 1907 | HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi) |
lypinator | 0:bb348c97df44 | 1908 | { |
lypinator | 0:bb348c97df44 | 1909 | /* The Lock is not implemented on this API to allow the user application |
lypinator | 0:bb348c97df44 | 1910 | to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback(): |
lypinator | 0:bb348c97df44 | 1911 | when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated |
lypinator | 0:bb348c97df44 | 1912 | and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback() |
lypinator | 0:bb348c97df44 | 1913 | */ |
lypinator | 0:bb348c97df44 | 1914 | |
lypinator | 0:bb348c97df44 | 1915 | /* Abort the SPI DMA tx Stream */ |
lypinator | 0:bb348c97df44 | 1916 | if(hspi->hdmatx != NULL) |
lypinator | 0:bb348c97df44 | 1917 | { |
lypinator | 0:bb348c97df44 | 1918 | HAL_DMA_Abort(hspi->hdmatx); |
lypinator | 0:bb348c97df44 | 1919 | } |
lypinator | 0:bb348c97df44 | 1920 | /* Abort the SPI DMA rx Stream */ |
lypinator | 0:bb348c97df44 | 1921 | if(hspi->hdmarx != NULL) |
lypinator | 0:bb348c97df44 | 1922 | { |
lypinator | 0:bb348c97df44 | 1923 | HAL_DMA_Abort(hspi->hdmarx); |
lypinator | 0:bb348c97df44 | 1924 | } |
lypinator | 0:bb348c97df44 | 1925 | |
lypinator | 0:bb348c97df44 | 1926 | /* Disable the SPI DMA Tx & Rx requests */ |
lypinator | 0:bb348c97df44 | 1927 | CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); |
lypinator | 0:bb348c97df44 | 1928 | hspi->State = HAL_SPI_STATE_READY; |
lypinator | 0:bb348c97df44 | 1929 | return HAL_OK; |
lypinator | 0:bb348c97df44 | 1930 | } |
lypinator | 0:bb348c97df44 | 1931 | |
lypinator | 0:bb348c97df44 | 1932 | /** |
lypinator | 0:bb348c97df44 | 1933 | * @brief Handle SPI interrupt request. |
lypinator | 0:bb348c97df44 | 1934 | * @param hspi pointer to a SPI_HandleTypeDef structure that contains |
lypinator | 0:bb348c97df44 | 1935 | * the configuration information for the specified SPI module. |
lypinator | 0:bb348c97df44 | 1936 | * @retval None |
lypinator | 0:bb348c97df44 | 1937 | */ |
lypinator | 0:bb348c97df44 | 1938 | void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi) |
lypinator | 0:bb348c97df44 | 1939 | { |
lypinator | 0:bb348c97df44 | 1940 | uint32_t itsource = hspi->Instance->CR2; |
lypinator | 0:bb348c97df44 | 1941 | uint32_t itflag = hspi->Instance->SR; |
lypinator | 0:bb348c97df44 | 1942 | |
lypinator | 0:bb348c97df44 | 1943 | /* SPI in mode Receiver ----------------------------------------------------*/ |
lypinator | 0:bb348c97df44 | 1944 | if(((itflag & SPI_FLAG_OVR) == RESET) && |
lypinator | 0:bb348c97df44 | 1945 | ((itflag & SPI_FLAG_RXNE) != RESET) && ((itsource & SPI_IT_RXNE) != RESET)) |
lypinator | 0:bb348c97df44 | 1946 | { |
lypinator | 0:bb348c97df44 | 1947 | hspi->RxISR(hspi); |
lypinator | 0:bb348c97df44 | 1948 | return; |
lypinator | 0:bb348c97df44 | 1949 | } |
lypinator | 0:bb348c97df44 | 1950 | |
lypinator | 0:bb348c97df44 | 1951 | /* SPI in mode Transmitter -------------------------------------------------*/ |
lypinator | 0:bb348c97df44 | 1952 | if(((itflag & SPI_FLAG_TXE) != RESET) && ((itsource & SPI_IT_TXE) != RESET)) |
lypinator | 0:bb348c97df44 | 1953 | { |
lypinator | 0:bb348c97df44 | 1954 | hspi->TxISR(hspi); |
lypinator | 0:bb348c97df44 | 1955 | return; |
lypinator | 0:bb348c97df44 | 1956 | } |
lypinator | 0:bb348c97df44 | 1957 | |
lypinator | 0:bb348c97df44 | 1958 | /* SPI in Error Treatment --------------------------------------------------*/ |
lypinator | 0:bb348c97df44 | 1959 | if(((itflag & (SPI_FLAG_MODF | SPI_FLAG_OVR | SPI_FLAG_FRE)) != RESET) && ((itsource & SPI_IT_ERR) != RESET)) |
lypinator | 0:bb348c97df44 | 1960 | { |
lypinator | 0:bb348c97df44 | 1961 | /* SPI Overrun error interrupt occurred ----------------------------------*/ |
lypinator | 0:bb348c97df44 | 1962 | if((itflag & SPI_FLAG_OVR) != RESET) |
lypinator | 0:bb348c97df44 | 1963 | { |
lypinator | 0:bb348c97df44 | 1964 | if(hspi->State != HAL_SPI_STATE_BUSY_TX) |
lypinator | 0:bb348c97df44 | 1965 | { |
lypinator | 0:bb348c97df44 | 1966 | SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR); |
lypinator | 0:bb348c97df44 | 1967 | __HAL_SPI_CLEAR_OVRFLAG(hspi); |
lypinator | 0:bb348c97df44 | 1968 | } |
lypinator | 0:bb348c97df44 | 1969 | else |
lypinator | 0:bb348c97df44 | 1970 | { |
lypinator | 0:bb348c97df44 | 1971 | __HAL_SPI_CLEAR_OVRFLAG(hspi); |
lypinator | 0:bb348c97df44 | 1972 | return; |
lypinator | 0:bb348c97df44 | 1973 | } |
lypinator | 0:bb348c97df44 | 1974 | } |
lypinator | 0:bb348c97df44 | 1975 | |
lypinator | 0:bb348c97df44 | 1976 | /* SPI Mode Fault error interrupt occurred -------------------------------*/ |
lypinator | 0:bb348c97df44 | 1977 | if((itflag & SPI_FLAG_MODF) != RESET) |
lypinator | 0:bb348c97df44 | 1978 | { |
lypinator | 0:bb348c97df44 | 1979 | SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF); |
lypinator | 0:bb348c97df44 | 1980 | __HAL_SPI_CLEAR_MODFFLAG(hspi); |
lypinator | 0:bb348c97df44 | 1981 | } |
lypinator | 0:bb348c97df44 | 1982 | |
lypinator | 0:bb348c97df44 | 1983 | /* SPI Frame error interrupt occurred ------------------------------------*/ |
lypinator | 0:bb348c97df44 | 1984 | if((itflag & SPI_FLAG_FRE) != RESET) |
lypinator | 0:bb348c97df44 | 1985 | { |
lypinator | 0:bb348c97df44 | 1986 | SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE); |
lypinator | 0:bb348c97df44 | 1987 | __HAL_SPI_CLEAR_FREFLAG(hspi); |
lypinator | 0:bb348c97df44 | 1988 | } |
lypinator | 0:bb348c97df44 | 1989 | |
lypinator | 0:bb348c97df44 | 1990 | if(hspi->ErrorCode != HAL_SPI_ERROR_NONE) |
lypinator | 0:bb348c97df44 | 1991 | { |
lypinator | 0:bb348c97df44 | 1992 | /* Disable all interrupts */ |
lypinator | 0:bb348c97df44 | 1993 | __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR); |
lypinator | 0:bb348c97df44 | 1994 | |
lypinator | 0:bb348c97df44 | 1995 | hspi->State = HAL_SPI_STATE_READY; |
lypinator | 0:bb348c97df44 | 1996 | /* Disable the SPI DMA requests if enabled */ |
lypinator | 0:bb348c97df44 | 1997 | if ((HAL_IS_BIT_SET(itsource, SPI_CR2_TXDMAEN))||(HAL_IS_BIT_SET(itsource, SPI_CR2_RXDMAEN))) |
lypinator | 0:bb348c97df44 | 1998 | { |
lypinator | 0:bb348c97df44 | 1999 | CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN)); |
lypinator | 0:bb348c97df44 | 2000 | |
lypinator | 0:bb348c97df44 | 2001 | /* Abort the SPI DMA Rx channel */ |
lypinator | 0:bb348c97df44 | 2002 | if(hspi->hdmarx != NULL) |
lypinator | 0:bb348c97df44 | 2003 | { |
lypinator | 0:bb348c97df44 | 2004 | /* Set the SPI DMA Abort callback : |
lypinator | 0:bb348c97df44 | 2005 | will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */ |
lypinator | 0:bb348c97df44 | 2006 | hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError; |
lypinator | 0:bb348c97df44 | 2007 | HAL_DMA_Abort_IT(hspi->hdmarx); |
lypinator | 0:bb348c97df44 | 2008 | } |
lypinator | 0:bb348c97df44 | 2009 | /* Abort the SPI DMA Tx channel */ |
lypinator | 0:bb348c97df44 | 2010 | if(hspi->hdmatx != NULL) |
lypinator | 0:bb348c97df44 | 2011 | { |
lypinator | 0:bb348c97df44 | 2012 | /* Set the SPI DMA Abort callback : |
lypinator | 0:bb348c97df44 | 2013 | will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */ |
lypinator | 0:bb348c97df44 | 2014 | hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError; |
lypinator | 0:bb348c97df44 | 2015 | HAL_DMA_Abort_IT(hspi->hdmatx); |
lypinator | 0:bb348c97df44 | 2016 | } |
lypinator | 0:bb348c97df44 | 2017 | } |
lypinator | 0:bb348c97df44 | 2018 | else |
lypinator | 0:bb348c97df44 | 2019 | { |
lypinator | 0:bb348c97df44 | 2020 | /* Call user error callback */ |
lypinator | 0:bb348c97df44 | 2021 | HAL_SPI_ErrorCallback(hspi); |
lypinator | 0:bb348c97df44 | 2022 | } |
lypinator | 0:bb348c97df44 | 2023 | } |
lypinator | 0:bb348c97df44 | 2024 | return; |
lypinator | 0:bb348c97df44 | 2025 | } |
lypinator | 0:bb348c97df44 | 2026 | } |
lypinator | 0:bb348c97df44 | 2027 | |
lypinator | 0:bb348c97df44 | 2028 | /** |
lypinator | 0:bb348c97df44 | 2029 | * @brief Tx Transfer completed callback. |
lypinator | 0:bb348c97df44 | 2030 | * @param hspi pointer to a SPI_HandleTypeDef structure that contains |
lypinator | 0:bb348c97df44 | 2031 | * the configuration information for SPI module. |
lypinator | 0:bb348c97df44 | 2032 | * @retval None |
lypinator | 0:bb348c97df44 | 2033 | */ |
lypinator | 0:bb348c97df44 | 2034 | __weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi) |
lypinator | 0:bb348c97df44 | 2035 | { |
lypinator | 0:bb348c97df44 | 2036 | /* Prevent unused argument(s) compilation warning */ |
lypinator | 0:bb348c97df44 | 2037 | UNUSED(hspi); |
lypinator | 0:bb348c97df44 | 2038 | /* NOTE : This function should not be modified, when the callback is needed, |
lypinator | 0:bb348c97df44 | 2039 | the HAL_SPI_TxCpltCallback should be implemented in the user file |
lypinator | 0:bb348c97df44 | 2040 | */ |
lypinator | 0:bb348c97df44 | 2041 | } |
lypinator | 0:bb348c97df44 | 2042 | |
lypinator | 0:bb348c97df44 | 2043 | /** |
lypinator | 0:bb348c97df44 | 2044 | * @brief Rx Transfer completed callback. |
lypinator | 0:bb348c97df44 | 2045 | * @param hspi pointer to a SPI_HandleTypeDef structure that contains |
lypinator | 0:bb348c97df44 | 2046 | * the configuration information for SPI module. |
lypinator | 0:bb348c97df44 | 2047 | * @retval None |
lypinator | 0:bb348c97df44 | 2048 | */ |
lypinator | 0:bb348c97df44 | 2049 | __weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi) |
lypinator | 0:bb348c97df44 | 2050 | { |
lypinator | 0:bb348c97df44 | 2051 | /* Prevent unused argument(s) compilation warning */ |
lypinator | 0:bb348c97df44 | 2052 | UNUSED(hspi); |
lypinator | 0:bb348c97df44 | 2053 | /* NOTE : This function should not be modified, when the callback is needed, |
lypinator | 0:bb348c97df44 | 2054 | the HAL_SPI_RxCpltCallback should be implemented in the user file |
lypinator | 0:bb348c97df44 | 2055 | */ |
lypinator | 0:bb348c97df44 | 2056 | } |
lypinator | 0:bb348c97df44 | 2057 | |
lypinator | 0:bb348c97df44 | 2058 | /** |
lypinator | 0:bb348c97df44 | 2059 | * @brief Tx and Rx Transfer completed callback. |
lypinator | 0:bb348c97df44 | 2060 | * @param hspi pointer to a SPI_HandleTypeDef structure that contains |
lypinator | 0:bb348c97df44 | 2061 | * the configuration information for SPI module. |
lypinator | 0:bb348c97df44 | 2062 | * @retval None |
lypinator | 0:bb348c97df44 | 2063 | */ |
lypinator | 0:bb348c97df44 | 2064 | __weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi) |
lypinator | 0:bb348c97df44 | 2065 | { |
lypinator | 0:bb348c97df44 | 2066 | /* Prevent unused argument(s) compilation warning */ |
lypinator | 0:bb348c97df44 | 2067 | UNUSED(hspi); |
lypinator | 0:bb348c97df44 | 2068 | /* NOTE : This function should not be modified, when the callback is needed, |
lypinator | 0:bb348c97df44 | 2069 | the HAL_SPI_TxRxCpltCallback should be implemented in the user file |
lypinator | 0:bb348c97df44 | 2070 | */ |
lypinator | 0:bb348c97df44 | 2071 | } |
lypinator | 0:bb348c97df44 | 2072 | |
lypinator | 0:bb348c97df44 | 2073 | /** |
lypinator | 0:bb348c97df44 | 2074 | * @brief Tx Half Transfer completed callback. |
lypinator | 0:bb348c97df44 | 2075 | * @param hspi pointer to a SPI_HandleTypeDef structure that contains |
lypinator | 0:bb348c97df44 | 2076 | * the configuration information for SPI module. |
lypinator | 0:bb348c97df44 | 2077 | * @retval None |
lypinator | 0:bb348c97df44 | 2078 | */ |
lypinator | 0:bb348c97df44 | 2079 | __weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi) |
lypinator | 0:bb348c97df44 | 2080 | { |
lypinator | 0:bb348c97df44 | 2081 | /* Prevent unused argument(s) compilation warning */ |
lypinator | 0:bb348c97df44 | 2082 | UNUSED(hspi); |
lypinator | 0:bb348c97df44 | 2083 | /* NOTE : This function should not be modified, when the callback is needed, |
lypinator | 0:bb348c97df44 | 2084 | the HAL_SPI_TxHalfCpltCallback should be implemented in the user file |
lypinator | 0:bb348c97df44 | 2085 | */ |
lypinator | 0:bb348c97df44 | 2086 | } |
lypinator | 0:bb348c97df44 | 2087 | |
lypinator | 0:bb348c97df44 | 2088 | /** |
lypinator | 0:bb348c97df44 | 2089 | * @brief Rx Half Transfer completed callback. |
lypinator | 0:bb348c97df44 | 2090 | * @param hspi pointer to a SPI_HandleTypeDef structure that contains |
lypinator | 0:bb348c97df44 | 2091 | * the configuration information for SPI module. |
lypinator | 0:bb348c97df44 | 2092 | * @retval None |
lypinator | 0:bb348c97df44 | 2093 | */ |
lypinator | 0:bb348c97df44 | 2094 | __weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi) |
lypinator | 0:bb348c97df44 | 2095 | { |
lypinator | 0:bb348c97df44 | 2096 | /* Prevent unused argument(s) compilation warning */ |
lypinator | 0:bb348c97df44 | 2097 | UNUSED(hspi); |
lypinator | 0:bb348c97df44 | 2098 | /* NOTE : This function should not be modified, when the callback is needed, |
lypinator | 0:bb348c97df44 | 2099 | the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file |
lypinator | 0:bb348c97df44 | 2100 | */ |
lypinator | 0:bb348c97df44 | 2101 | } |
lypinator | 0:bb348c97df44 | 2102 | |
lypinator | 0:bb348c97df44 | 2103 | /** |
lypinator | 0:bb348c97df44 | 2104 | * @brief Tx and Rx Half Transfer callback. |
lypinator | 0:bb348c97df44 | 2105 | * @param hspi pointer to a SPI_HandleTypeDef structure that contains |
lypinator | 0:bb348c97df44 | 2106 | * the configuration information for SPI module. |
lypinator | 0:bb348c97df44 | 2107 | * @retval None |
lypinator | 0:bb348c97df44 | 2108 | */ |
lypinator | 0:bb348c97df44 | 2109 | __weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi) |
lypinator | 0:bb348c97df44 | 2110 | { |
lypinator | 0:bb348c97df44 | 2111 | /* Prevent unused argument(s) compilation warning */ |
lypinator | 0:bb348c97df44 | 2112 | UNUSED(hspi); |
lypinator | 0:bb348c97df44 | 2113 | /* NOTE : This function should not be modified, when the callback is needed, |
lypinator | 0:bb348c97df44 | 2114 | the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file |
lypinator | 0:bb348c97df44 | 2115 | */ |
lypinator | 0:bb348c97df44 | 2116 | } |
lypinator | 0:bb348c97df44 | 2117 | |
lypinator | 0:bb348c97df44 | 2118 | /** |
lypinator | 0:bb348c97df44 | 2119 | * @brief SPI error callback. |
lypinator | 0:bb348c97df44 | 2120 | * @param hspi pointer to a SPI_HandleTypeDef structure that contains |
lypinator | 0:bb348c97df44 | 2121 | * the configuration information for SPI module. |
lypinator | 0:bb348c97df44 | 2122 | * @retval None |
lypinator | 0:bb348c97df44 | 2123 | */ |
lypinator | 0:bb348c97df44 | 2124 | __weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi) |
lypinator | 0:bb348c97df44 | 2125 | { |
lypinator | 0:bb348c97df44 | 2126 | /* Prevent unused argument(s) compilation warning */ |
lypinator | 0:bb348c97df44 | 2127 | UNUSED(hspi); |
lypinator | 0:bb348c97df44 | 2128 | /* NOTE : This function should not be modified, when the callback is needed, |
lypinator | 0:bb348c97df44 | 2129 | the HAL_SPI_ErrorCallback should be implemented in the user file |
lypinator | 0:bb348c97df44 | 2130 | */ |
lypinator | 0:bb348c97df44 | 2131 | /* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes |
lypinator | 0:bb348c97df44 | 2132 | and user can use HAL_SPI_GetError() API to check the latest error occurred |
lypinator | 0:bb348c97df44 | 2133 | */ |
lypinator | 0:bb348c97df44 | 2134 | } |
lypinator | 0:bb348c97df44 | 2135 | |
lypinator | 0:bb348c97df44 | 2136 | /** |
lypinator | 0:bb348c97df44 | 2137 | * @brief SPI Abort Complete callback. |
lypinator | 0:bb348c97df44 | 2138 | * @param hspi SPI handle. |
lypinator | 0:bb348c97df44 | 2139 | * @retval None |
lypinator | 0:bb348c97df44 | 2140 | */ |
lypinator | 0:bb348c97df44 | 2141 | __weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi) |
lypinator | 0:bb348c97df44 | 2142 | { |
lypinator | 0:bb348c97df44 | 2143 | /* Prevent unused argument(s) compilation warning */ |
lypinator | 0:bb348c97df44 | 2144 | UNUSED(hspi); |
lypinator | 0:bb348c97df44 | 2145 | |
lypinator | 0:bb348c97df44 | 2146 | /* NOTE : This function should not be modified, when the callback is needed, |
lypinator | 0:bb348c97df44 | 2147 | the HAL_SPI_AbortCpltCallback can be implemented in the user file. |
lypinator | 0:bb348c97df44 | 2148 | */ |
lypinator | 0:bb348c97df44 | 2149 | } |
lypinator | 0:bb348c97df44 | 2150 | |
lypinator | 0:bb348c97df44 | 2151 | /** |
lypinator | 0:bb348c97df44 | 2152 | * @} |
lypinator | 0:bb348c97df44 | 2153 | */ |
lypinator | 0:bb348c97df44 | 2154 | |
lypinator | 0:bb348c97df44 | 2155 | /** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions |
lypinator | 0:bb348c97df44 | 2156 | * @brief SPI control functions |
lypinator | 0:bb348c97df44 | 2157 | * |
lypinator | 0:bb348c97df44 | 2158 | @verbatim |
lypinator | 0:bb348c97df44 | 2159 | =============================================================================== |
lypinator | 0:bb348c97df44 | 2160 | ##### Peripheral State and Errors functions ##### |
lypinator | 0:bb348c97df44 | 2161 | =============================================================================== |
lypinator | 0:bb348c97df44 | 2162 | [..] |
lypinator | 0:bb348c97df44 | 2163 | This subsection provides a set of functions allowing to control the SPI. |
lypinator | 0:bb348c97df44 | 2164 | (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral |
lypinator | 0:bb348c97df44 | 2165 | (+) HAL_SPI_GetError() check in run-time Errors occurring during communication |
lypinator | 0:bb348c97df44 | 2166 | @endverbatim |
lypinator | 0:bb348c97df44 | 2167 | * @{ |
lypinator | 0:bb348c97df44 | 2168 | */ |
lypinator | 0:bb348c97df44 | 2169 | |
lypinator | 0:bb348c97df44 | 2170 | /** |
lypinator | 0:bb348c97df44 | 2171 | * @brief Return the SPI handle state. |
lypinator | 0:bb348c97df44 | 2172 | * @param hspi pointer to a SPI_HandleTypeDef structure that contains |
lypinator | 0:bb348c97df44 | 2173 | * the configuration information for SPI module. |
lypinator | 0:bb348c97df44 | 2174 | * @retval SPI state |
lypinator | 0:bb348c97df44 | 2175 | */ |
lypinator | 0:bb348c97df44 | 2176 | HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi) |
lypinator | 0:bb348c97df44 | 2177 | { |
lypinator | 0:bb348c97df44 | 2178 | /* Return SPI handle state */ |
lypinator | 0:bb348c97df44 | 2179 | return hspi->State; |
lypinator | 0:bb348c97df44 | 2180 | } |
lypinator | 0:bb348c97df44 | 2181 | |
lypinator | 0:bb348c97df44 | 2182 | /** |
lypinator | 0:bb348c97df44 | 2183 | * @brief Return the SPI error code. |
lypinator | 0:bb348c97df44 | 2184 | * @param hspi pointer to a SPI_HandleTypeDef structure that contains |
lypinator | 0:bb348c97df44 | 2185 | * the configuration information for SPI module. |
lypinator | 0:bb348c97df44 | 2186 | * @retval SPI error code in bitmap format |
lypinator | 0:bb348c97df44 | 2187 | */ |
lypinator | 0:bb348c97df44 | 2188 | uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi) |
lypinator | 0:bb348c97df44 | 2189 | { |
lypinator | 0:bb348c97df44 | 2190 | /* Return SPI ErrorCode */ |
lypinator | 0:bb348c97df44 | 2191 | return hspi->ErrorCode; |
lypinator | 0:bb348c97df44 | 2192 | } |
lypinator | 0:bb348c97df44 | 2193 | |
lypinator | 0:bb348c97df44 | 2194 | /** |
lypinator | 0:bb348c97df44 | 2195 | * @} |
lypinator | 0:bb348c97df44 | 2196 | */ |
lypinator | 0:bb348c97df44 | 2197 | |
lypinator | 0:bb348c97df44 | 2198 | /** |
lypinator | 0:bb348c97df44 | 2199 | * @} |
lypinator | 0:bb348c97df44 | 2200 | */ |
lypinator | 0:bb348c97df44 | 2201 | |
lypinator | 0:bb348c97df44 | 2202 | /** @addtogroup SPI_Private_Functions |
lypinator | 0:bb348c97df44 | 2203 | * @brief Private functions |
lypinator | 0:bb348c97df44 | 2204 | * @{ |
lypinator | 0:bb348c97df44 | 2205 | */ |
lypinator | 0:bb348c97df44 | 2206 | |
lypinator | 0:bb348c97df44 | 2207 | /** |
lypinator | 0:bb348c97df44 | 2208 | * @brief DMA SPI transmit process complete callback. |
lypinator | 0:bb348c97df44 | 2209 | * @param hdma pointer to a DMA_HandleTypeDef structure that contains |
lypinator | 0:bb348c97df44 | 2210 | * the configuration information for the specified DMA module. |
lypinator | 0:bb348c97df44 | 2211 | * @retval None |
lypinator | 0:bb348c97df44 | 2212 | */ |
lypinator | 0:bb348c97df44 | 2213 | static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma) |
lypinator | 0:bb348c97df44 | 2214 | { |
lypinator | 0:bb348c97df44 | 2215 | SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; |
lypinator | 0:bb348c97df44 | 2216 | uint32_t tickstart = 0U; |
lypinator | 0:bb348c97df44 | 2217 | |
lypinator | 0:bb348c97df44 | 2218 | /* Init tickstart for timeout managment*/ |
lypinator | 0:bb348c97df44 | 2219 | tickstart = HAL_GetTick(); |
lypinator | 0:bb348c97df44 | 2220 | |
lypinator | 0:bb348c97df44 | 2221 | /* DMA Normal Mode */ |
lypinator | 0:bb348c97df44 | 2222 | if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U) |
lypinator | 0:bb348c97df44 | 2223 | { |
lypinator | 0:bb348c97df44 | 2224 | /* Disable Tx DMA Request */ |
lypinator | 0:bb348c97df44 | 2225 | CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); |
lypinator | 0:bb348c97df44 | 2226 | |
lypinator | 0:bb348c97df44 | 2227 | /* Check the end of the transaction */ |
lypinator | 0:bb348c97df44 | 2228 | if(SPI_CheckFlag_BSY(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) |
lypinator | 0:bb348c97df44 | 2229 | { |
lypinator | 0:bb348c97df44 | 2230 | SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); |
lypinator | 0:bb348c97df44 | 2231 | } |
lypinator | 0:bb348c97df44 | 2232 | |
lypinator | 0:bb348c97df44 | 2233 | /* Clear overrun flag in 2 Lines communication mode because received data is not read */ |
lypinator | 0:bb348c97df44 | 2234 | if(hspi->Init.Direction == SPI_DIRECTION_2LINES) |
lypinator | 0:bb348c97df44 | 2235 | { |
lypinator | 0:bb348c97df44 | 2236 | __HAL_SPI_CLEAR_OVRFLAG(hspi); |
lypinator | 0:bb348c97df44 | 2237 | } |
lypinator | 0:bb348c97df44 | 2238 | |
lypinator | 0:bb348c97df44 | 2239 | hspi->TxXferCount = 0U; |
lypinator | 0:bb348c97df44 | 2240 | hspi->State = HAL_SPI_STATE_READY; |
lypinator | 0:bb348c97df44 | 2241 | |
lypinator | 0:bb348c97df44 | 2242 | if(hspi->ErrorCode != HAL_SPI_ERROR_NONE) |
lypinator | 0:bb348c97df44 | 2243 | { |
lypinator | 0:bb348c97df44 | 2244 | HAL_SPI_ErrorCallback(hspi); |
lypinator | 0:bb348c97df44 | 2245 | return; |
lypinator | 0:bb348c97df44 | 2246 | } |
lypinator | 0:bb348c97df44 | 2247 | } |
lypinator | 0:bb348c97df44 | 2248 | HAL_SPI_TxCpltCallback(hspi); |
lypinator | 0:bb348c97df44 | 2249 | } |
lypinator | 0:bb348c97df44 | 2250 | |
lypinator | 0:bb348c97df44 | 2251 | /** |
lypinator | 0:bb348c97df44 | 2252 | * @brief DMA SPI receive process complete callback. |
lypinator | 0:bb348c97df44 | 2253 | * @param hdma pointer to a DMA_HandleTypeDef structure that contains |
lypinator | 0:bb348c97df44 | 2254 | * the configuration information for the specified DMA module. |
lypinator | 0:bb348c97df44 | 2255 | * @retval None |
lypinator | 0:bb348c97df44 | 2256 | */ |
lypinator | 0:bb348c97df44 | 2257 | static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) |
lypinator | 0:bb348c97df44 | 2258 | { |
lypinator | 0:bb348c97df44 | 2259 | SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; |
lypinator | 0:bb348c97df44 | 2260 | #if (USE_SPI_CRC != 0U) |
lypinator | 0:bb348c97df44 | 2261 | uint32_t tickstart = 0U; |
lypinator | 0:bb348c97df44 | 2262 | __IO uint16_t tmpreg = 0U; |
lypinator | 0:bb348c97df44 | 2263 | |
lypinator | 0:bb348c97df44 | 2264 | /* Init tickstart for timeout management*/ |
lypinator | 0:bb348c97df44 | 2265 | tickstart = HAL_GetTick(); |
lypinator | 0:bb348c97df44 | 2266 | #endif /* USE_SPI_CRC */ |
lypinator | 0:bb348c97df44 | 2267 | |
lypinator | 0:bb348c97df44 | 2268 | if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U) |
lypinator | 0:bb348c97df44 | 2269 | { |
lypinator | 0:bb348c97df44 | 2270 | #if (USE_SPI_CRC != 0U) |
lypinator | 0:bb348c97df44 | 2271 | /* CRC handling */ |
lypinator | 0:bb348c97df44 | 2272 | if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) |
lypinator | 0:bb348c97df44 | 2273 | { |
lypinator | 0:bb348c97df44 | 2274 | /* Wait until RXNE flag */ |
lypinator | 0:bb348c97df44 | 2275 | if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) |
lypinator | 0:bb348c97df44 | 2276 | { |
lypinator | 0:bb348c97df44 | 2277 | /* Error on the CRC reception */ |
lypinator | 0:bb348c97df44 | 2278 | SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); |
lypinator | 0:bb348c97df44 | 2279 | } |
lypinator | 0:bb348c97df44 | 2280 | /* Read CRC */ |
lypinator | 0:bb348c97df44 | 2281 | tmpreg = hspi->Instance->DR; |
lypinator | 0:bb348c97df44 | 2282 | /* To avoid GCC warning */ |
lypinator | 0:bb348c97df44 | 2283 | UNUSED(tmpreg); |
lypinator | 0:bb348c97df44 | 2284 | } |
lypinator | 0:bb348c97df44 | 2285 | #endif /* USE_SPI_CRC */ |
lypinator | 0:bb348c97df44 | 2286 | |
lypinator | 0:bb348c97df44 | 2287 | /* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */ |
lypinator | 0:bb348c97df44 | 2288 | CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); |
lypinator | 0:bb348c97df44 | 2289 | |
lypinator | 0:bb348c97df44 | 2290 | /* Check the end of the transaction */ |
lypinator | 0:bb348c97df44 | 2291 | if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) |
lypinator | 0:bb348c97df44 | 2292 | { |
lypinator | 0:bb348c97df44 | 2293 | /* Disable SPI peripheral */ |
lypinator | 0:bb348c97df44 | 2294 | __HAL_SPI_DISABLE(hspi); |
lypinator | 0:bb348c97df44 | 2295 | } |
lypinator | 0:bb348c97df44 | 2296 | |
lypinator | 0:bb348c97df44 | 2297 | hspi->RxXferCount = 0U; |
lypinator | 0:bb348c97df44 | 2298 | hspi->State = HAL_SPI_STATE_READY; |
lypinator | 0:bb348c97df44 | 2299 | |
lypinator | 0:bb348c97df44 | 2300 | #if (USE_SPI_CRC != 0U) |
lypinator | 0:bb348c97df44 | 2301 | /* Check if CRC error occurred */ |
lypinator | 0:bb348c97df44 | 2302 | if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR)) |
lypinator | 0:bb348c97df44 | 2303 | { |
lypinator | 0:bb348c97df44 | 2304 | SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); |
lypinator | 0:bb348c97df44 | 2305 | __HAL_SPI_CLEAR_CRCERRFLAG(hspi); |
lypinator | 0:bb348c97df44 | 2306 | } |
lypinator | 0:bb348c97df44 | 2307 | #endif /* USE_SPI_CRC */ |
lypinator | 0:bb348c97df44 | 2308 | |
lypinator | 0:bb348c97df44 | 2309 | if(hspi->ErrorCode != HAL_SPI_ERROR_NONE) |
lypinator | 0:bb348c97df44 | 2310 | { |
lypinator | 0:bb348c97df44 | 2311 | HAL_SPI_ErrorCallback(hspi); |
lypinator | 0:bb348c97df44 | 2312 | return; |
lypinator | 0:bb348c97df44 | 2313 | } |
lypinator | 0:bb348c97df44 | 2314 | } |
lypinator | 0:bb348c97df44 | 2315 | HAL_SPI_RxCpltCallback(hspi); |
lypinator | 0:bb348c97df44 | 2316 | } |
lypinator | 0:bb348c97df44 | 2317 | |
lypinator | 0:bb348c97df44 | 2318 | /** |
lypinator | 0:bb348c97df44 | 2319 | * @brief DMA SPI transmit receive process complete callback. |
lypinator | 0:bb348c97df44 | 2320 | * @param hdma pointer to a DMA_HandleTypeDef structure that contains |
lypinator | 0:bb348c97df44 | 2321 | * the configuration information for the specified DMA module. |
lypinator | 0:bb348c97df44 | 2322 | * @retval None |
lypinator | 0:bb348c97df44 | 2323 | */ |
lypinator | 0:bb348c97df44 | 2324 | static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) |
lypinator | 0:bb348c97df44 | 2325 | { |
lypinator | 0:bb348c97df44 | 2326 | SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; |
lypinator | 0:bb348c97df44 | 2327 | uint32_t tickstart = 0U; |
lypinator | 0:bb348c97df44 | 2328 | #if (USE_SPI_CRC != 0U) |
lypinator | 0:bb348c97df44 | 2329 | __IO int16_t tmpreg = 0U; |
lypinator | 0:bb348c97df44 | 2330 | #endif /* USE_SPI_CRC */ |
lypinator | 0:bb348c97df44 | 2331 | /* Init tickstart for timeout management*/ |
lypinator | 0:bb348c97df44 | 2332 | tickstart = HAL_GetTick(); |
lypinator | 0:bb348c97df44 | 2333 | |
lypinator | 0:bb348c97df44 | 2334 | if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U) |
lypinator | 0:bb348c97df44 | 2335 | { |
lypinator | 0:bb348c97df44 | 2336 | #if (USE_SPI_CRC != 0U) |
lypinator | 0:bb348c97df44 | 2337 | /* CRC handling */ |
lypinator | 0:bb348c97df44 | 2338 | if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) |
lypinator | 0:bb348c97df44 | 2339 | { |
lypinator | 0:bb348c97df44 | 2340 | /* Wait the CRC data */ |
lypinator | 0:bb348c97df44 | 2341 | if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) |
lypinator | 0:bb348c97df44 | 2342 | { |
lypinator | 0:bb348c97df44 | 2343 | SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); |
lypinator | 0:bb348c97df44 | 2344 | } |
lypinator | 0:bb348c97df44 | 2345 | /* Read CRC to Flush DR and RXNE flag */ |
lypinator | 0:bb348c97df44 | 2346 | tmpreg = hspi->Instance->DR; |
lypinator | 0:bb348c97df44 | 2347 | /* To avoid GCC warning */ |
lypinator | 0:bb348c97df44 | 2348 | UNUSED(tmpreg); |
lypinator | 0:bb348c97df44 | 2349 | } |
lypinator | 0:bb348c97df44 | 2350 | #endif /* USE_SPI_CRC */ |
lypinator | 0:bb348c97df44 | 2351 | /* Check the end of the transaction */ |
lypinator | 0:bb348c97df44 | 2352 | if(SPI_CheckFlag_BSY(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) |
lypinator | 0:bb348c97df44 | 2353 | { |
lypinator | 0:bb348c97df44 | 2354 | SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); |
lypinator | 0:bb348c97df44 | 2355 | } |
lypinator | 0:bb348c97df44 | 2356 | |
lypinator | 0:bb348c97df44 | 2357 | /* Disable Rx/Tx DMA Request */ |
lypinator | 0:bb348c97df44 | 2358 | CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); |
lypinator | 0:bb348c97df44 | 2359 | |
lypinator | 0:bb348c97df44 | 2360 | hspi->TxXferCount = 0U; |
lypinator | 0:bb348c97df44 | 2361 | hspi->RxXferCount = 0U; |
lypinator | 0:bb348c97df44 | 2362 | hspi->State = HAL_SPI_STATE_READY; |
lypinator | 0:bb348c97df44 | 2363 | |
lypinator | 0:bb348c97df44 | 2364 | #if (USE_SPI_CRC != 0U) |
lypinator | 0:bb348c97df44 | 2365 | /* Check if CRC error occurred */ |
lypinator | 0:bb348c97df44 | 2366 | if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR)) |
lypinator | 0:bb348c97df44 | 2367 | { |
lypinator | 0:bb348c97df44 | 2368 | SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); |
lypinator | 0:bb348c97df44 | 2369 | __HAL_SPI_CLEAR_CRCERRFLAG(hspi); |
lypinator | 0:bb348c97df44 | 2370 | } |
lypinator | 0:bb348c97df44 | 2371 | #endif /* USE_SPI_CRC */ |
lypinator | 0:bb348c97df44 | 2372 | |
lypinator | 0:bb348c97df44 | 2373 | if(hspi->ErrorCode != HAL_SPI_ERROR_NONE) |
lypinator | 0:bb348c97df44 | 2374 | { |
lypinator | 0:bb348c97df44 | 2375 | HAL_SPI_ErrorCallback(hspi); |
lypinator | 0:bb348c97df44 | 2376 | return; |
lypinator | 0:bb348c97df44 | 2377 | } |
lypinator | 0:bb348c97df44 | 2378 | } |
lypinator | 0:bb348c97df44 | 2379 | HAL_SPI_TxRxCpltCallback(hspi); |
lypinator | 0:bb348c97df44 | 2380 | } |
lypinator | 0:bb348c97df44 | 2381 | |
lypinator | 0:bb348c97df44 | 2382 | /** |
lypinator | 0:bb348c97df44 | 2383 | * @brief DMA SPI half transmit process complete callback. |
lypinator | 0:bb348c97df44 | 2384 | * @param hdma pointer to a DMA_HandleTypeDef structure that contains |
lypinator | 0:bb348c97df44 | 2385 | * the configuration information for the specified DMA module. |
lypinator | 0:bb348c97df44 | 2386 | * @retval None |
lypinator | 0:bb348c97df44 | 2387 | */ |
lypinator | 0:bb348c97df44 | 2388 | static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma) |
lypinator | 0:bb348c97df44 | 2389 | { |
lypinator | 0:bb348c97df44 | 2390 | SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; |
lypinator | 0:bb348c97df44 | 2391 | |
lypinator | 0:bb348c97df44 | 2392 | HAL_SPI_TxHalfCpltCallback(hspi); |
lypinator | 0:bb348c97df44 | 2393 | } |
lypinator | 0:bb348c97df44 | 2394 | |
lypinator | 0:bb348c97df44 | 2395 | /** |
lypinator | 0:bb348c97df44 | 2396 | * @brief DMA SPI half receive process complete callback |
lypinator | 0:bb348c97df44 | 2397 | * @param hdma pointer to a DMA_HandleTypeDef structure that contains |
lypinator | 0:bb348c97df44 | 2398 | * the configuration information for the specified DMA module. |
lypinator | 0:bb348c97df44 | 2399 | * @retval None |
lypinator | 0:bb348c97df44 | 2400 | */ |
lypinator | 0:bb348c97df44 | 2401 | static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma) |
lypinator | 0:bb348c97df44 | 2402 | { |
lypinator | 0:bb348c97df44 | 2403 | SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; |
lypinator | 0:bb348c97df44 | 2404 | |
lypinator | 0:bb348c97df44 | 2405 | HAL_SPI_RxHalfCpltCallback(hspi); |
lypinator | 0:bb348c97df44 | 2406 | } |
lypinator | 0:bb348c97df44 | 2407 | |
lypinator | 0:bb348c97df44 | 2408 | /** |
lypinator | 0:bb348c97df44 | 2409 | * @brief DMA SPI half transmit receive process complete callback. |
lypinator | 0:bb348c97df44 | 2410 | * @param hdma pointer to a DMA_HandleTypeDef structure that contains |
lypinator | 0:bb348c97df44 | 2411 | * the configuration information for the specified DMA module. |
lypinator | 0:bb348c97df44 | 2412 | * @retval None |
lypinator | 0:bb348c97df44 | 2413 | */ |
lypinator | 0:bb348c97df44 | 2414 | static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma) |
lypinator | 0:bb348c97df44 | 2415 | { |
lypinator | 0:bb348c97df44 | 2416 | SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; |
lypinator | 0:bb348c97df44 | 2417 | |
lypinator | 0:bb348c97df44 | 2418 | HAL_SPI_TxRxHalfCpltCallback(hspi); |
lypinator | 0:bb348c97df44 | 2419 | } |
lypinator | 0:bb348c97df44 | 2420 | |
lypinator | 0:bb348c97df44 | 2421 | /** |
lypinator | 0:bb348c97df44 | 2422 | * @brief DMA SPI communication error callback. |
lypinator | 0:bb348c97df44 | 2423 | * @param hdma pointer to a DMA_HandleTypeDef structure that contains |
lypinator | 0:bb348c97df44 | 2424 | * the configuration information for the specified DMA module. |
lypinator | 0:bb348c97df44 | 2425 | * @retval None |
lypinator | 0:bb348c97df44 | 2426 | */ |
lypinator | 0:bb348c97df44 | 2427 | static void SPI_DMAError(DMA_HandleTypeDef *hdma) |
lypinator | 0:bb348c97df44 | 2428 | { |
lypinator | 0:bb348c97df44 | 2429 | SPI_HandleTypeDef* hspi = (SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; |
lypinator | 0:bb348c97df44 | 2430 | |
lypinator | 0:bb348c97df44 | 2431 | /* Stop the disable DMA transfer on SPI side */ |
lypinator | 0:bb348c97df44 | 2432 | CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); |
lypinator | 0:bb348c97df44 | 2433 | |
lypinator | 0:bb348c97df44 | 2434 | SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); |
lypinator | 0:bb348c97df44 | 2435 | hspi->State = HAL_SPI_STATE_READY; |
lypinator | 0:bb348c97df44 | 2436 | HAL_SPI_ErrorCallback(hspi); |
lypinator | 0:bb348c97df44 | 2437 | } |
lypinator | 0:bb348c97df44 | 2438 | |
lypinator | 0:bb348c97df44 | 2439 | /** |
lypinator | 0:bb348c97df44 | 2440 | * @brief DMA SPI communication abort callback, when initiated by HAL services on Error |
lypinator | 0:bb348c97df44 | 2441 | * (To be called at end of DMA Abort procedure following error occurrence). |
lypinator | 0:bb348c97df44 | 2442 | * @param hdma DMA handle. |
lypinator | 0:bb348c97df44 | 2443 | * @retval None |
lypinator | 0:bb348c97df44 | 2444 | */ |
lypinator | 0:bb348c97df44 | 2445 | static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma) |
lypinator | 0:bb348c97df44 | 2446 | { |
lypinator | 0:bb348c97df44 | 2447 | SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; |
lypinator | 0:bb348c97df44 | 2448 | hspi->RxXferCount = 0U; |
lypinator | 0:bb348c97df44 | 2449 | hspi->TxXferCount = 0U; |
lypinator | 0:bb348c97df44 | 2450 | |
lypinator | 0:bb348c97df44 | 2451 | HAL_SPI_ErrorCallback(hspi); |
lypinator | 0:bb348c97df44 | 2452 | } |
lypinator | 0:bb348c97df44 | 2453 | |
lypinator | 0:bb348c97df44 | 2454 | /** |
lypinator | 0:bb348c97df44 | 2455 | * @brief DMA SPI Tx communication abort callback, when initiated by user |
lypinator | 0:bb348c97df44 | 2456 | * (To be called at end of DMA Tx Abort procedure following user abort request). |
lypinator | 0:bb348c97df44 | 2457 | * @note When this callback is executed, User Abort complete call back is called only if no |
lypinator | 0:bb348c97df44 | 2458 | * Abort still ongoing for Rx DMA Handle. |
lypinator | 0:bb348c97df44 | 2459 | * @param hdma DMA handle. |
lypinator | 0:bb348c97df44 | 2460 | * @retval None |
lypinator | 0:bb348c97df44 | 2461 | */ |
lypinator | 0:bb348c97df44 | 2462 | static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma) |
lypinator | 0:bb348c97df44 | 2463 | { |
lypinator | 0:bb348c97df44 | 2464 | __IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U); |
lypinator | 0:bb348c97df44 | 2465 | SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; |
lypinator | 0:bb348c97df44 | 2466 | |
lypinator | 0:bb348c97df44 | 2467 | hspi->hdmatx->XferAbortCallback = NULL; |
lypinator | 0:bb348c97df44 | 2468 | |
lypinator | 0:bb348c97df44 | 2469 | /* Disable Tx DMA Request */ |
lypinator | 0:bb348c97df44 | 2470 | CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN ); |
lypinator | 0:bb348c97df44 | 2471 | |
lypinator | 0:bb348c97df44 | 2472 | /* Wait until TXE flag is set */ |
lypinator | 0:bb348c97df44 | 2473 | do |
lypinator | 0:bb348c97df44 | 2474 | { |
lypinator | 0:bb348c97df44 | 2475 | if(count-- == 0U) |
lypinator | 0:bb348c97df44 | 2476 | { |
lypinator | 0:bb348c97df44 | 2477 | SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); |
lypinator | 0:bb348c97df44 | 2478 | break; |
lypinator | 0:bb348c97df44 | 2479 | } |
lypinator | 0:bb348c97df44 | 2480 | } |
lypinator | 0:bb348c97df44 | 2481 | while((hspi->Instance->SR & SPI_FLAG_TXE) == RESET); |
lypinator | 0:bb348c97df44 | 2482 | |
lypinator | 0:bb348c97df44 | 2483 | /* Check if an Abort process is still ongoing */ |
lypinator | 0:bb348c97df44 | 2484 | if(hspi->hdmarx != NULL) |
lypinator | 0:bb348c97df44 | 2485 | { |
lypinator | 0:bb348c97df44 | 2486 | if(hspi->hdmarx->XferAbortCallback != NULL) |
lypinator | 0:bb348c97df44 | 2487 | { |
lypinator | 0:bb348c97df44 | 2488 | return; |
lypinator | 0:bb348c97df44 | 2489 | } |
lypinator | 0:bb348c97df44 | 2490 | } |
lypinator | 0:bb348c97df44 | 2491 | |
lypinator | 0:bb348c97df44 | 2492 | /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ |
lypinator | 0:bb348c97df44 | 2493 | hspi->RxXferCount = 0U; |
lypinator | 0:bb348c97df44 | 2494 | hspi->TxXferCount = 0U; |
lypinator | 0:bb348c97df44 | 2495 | |
lypinator | 0:bb348c97df44 | 2496 | /* Reset errorCode */ |
lypinator | 0:bb348c97df44 | 2497 | hspi->ErrorCode = HAL_SPI_ERROR_NONE; |
lypinator | 0:bb348c97df44 | 2498 | |
lypinator | 0:bb348c97df44 | 2499 | /* Clear the Error flags in the SR register */ |
lypinator | 0:bb348c97df44 | 2500 | __HAL_SPI_CLEAR_FREFLAG(hspi); |
lypinator | 0:bb348c97df44 | 2501 | |
lypinator | 0:bb348c97df44 | 2502 | /* Restore hspi->State to Ready */ |
lypinator | 0:bb348c97df44 | 2503 | hspi->State = HAL_SPI_STATE_READY; |
lypinator | 0:bb348c97df44 | 2504 | |
lypinator | 0:bb348c97df44 | 2505 | /* Call user Abort complete callback */ |
lypinator | 0:bb348c97df44 | 2506 | HAL_SPI_AbortCpltCallback(hspi); |
lypinator | 0:bb348c97df44 | 2507 | } |
lypinator | 0:bb348c97df44 | 2508 | |
lypinator | 0:bb348c97df44 | 2509 | /** |
lypinator | 0:bb348c97df44 | 2510 | * @brief DMA SPI Rx communication abort callback, when initiated by user |
lypinator | 0:bb348c97df44 | 2511 | * (To be called at end of DMA Rx Abort procedure following user abort request). |
lypinator | 0:bb348c97df44 | 2512 | * @note When this callback is executed, User Abort complete call back is called only if no |
lypinator | 0:bb348c97df44 | 2513 | * Abort still ongoing for Tx DMA Handle. |
lypinator | 0:bb348c97df44 | 2514 | * @param hdma DMA handle. |
lypinator | 0:bb348c97df44 | 2515 | * @retval None |
lypinator | 0:bb348c97df44 | 2516 | */ |
lypinator | 0:bb348c97df44 | 2517 | static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma) |
lypinator | 0:bb348c97df44 | 2518 | { |
lypinator | 0:bb348c97df44 | 2519 | SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; |
lypinator | 0:bb348c97df44 | 2520 | |
lypinator | 0:bb348c97df44 | 2521 | /* Disable SPI Peripheral */ |
lypinator | 0:bb348c97df44 | 2522 | __HAL_SPI_DISABLE(hspi); |
lypinator | 0:bb348c97df44 | 2523 | |
lypinator | 0:bb348c97df44 | 2524 | hspi->hdmarx->XferAbortCallback = NULL; |
lypinator | 0:bb348c97df44 | 2525 | |
lypinator | 0:bb348c97df44 | 2526 | /* Disable Rx DMA Request */ |
lypinator | 0:bb348c97df44 | 2527 | CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); |
lypinator | 0:bb348c97df44 | 2528 | |
lypinator | 0:bb348c97df44 | 2529 | /* Check if an Abort process is still ongoing */ |
lypinator | 0:bb348c97df44 | 2530 | if(hspi->hdmatx != NULL) |
lypinator | 0:bb348c97df44 | 2531 | { |
lypinator | 0:bb348c97df44 | 2532 | if(hspi->hdmatx->XferAbortCallback != NULL) |
lypinator | 0:bb348c97df44 | 2533 | { |
lypinator | 0:bb348c97df44 | 2534 | return; |
lypinator | 0:bb348c97df44 | 2535 | } |
lypinator | 0:bb348c97df44 | 2536 | } |
lypinator | 0:bb348c97df44 | 2537 | |
lypinator | 0:bb348c97df44 | 2538 | /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ |
lypinator | 0:bb348c97df44 | 2539 | hspi->RxXferCount = 0U; |
lypinator | 0:bb348c97df44 | 2540 | hspi->TxXferCount = 0U; |
lypinator | 0:bb348c97df44 | 2541 | |
lypinator | 0:bb348c97df44 | 2542 | /* Reset errorCode */ |
lypinator | 0:bb348c97df44 | 2543 | hspi->ErrorCode = HAL_SPI_ERROR_NONE; |
lypinator | 0:bb348c97df44 | 2544 | |
lypinator | 0:bb348c97df44 | 2545 | /* Clear the Error flags in the SR register */ |
lypinator | 0:bb348c97df44 | 2546 | __HAL_SPI_CLEAR_OVRFLAG(hspi); |
lypinator | 0:bb348c97df44 | 2547 | __HAL_SPI_CLEAR_FREFLAG(hspi); |
lypinator | 0:bb348c97df44 | 2548 | |
lypinator | 0:bb348c97df44 | 2549 | /* Restore hspi->State to Ready */ |
lypinator | 0:bb348c97df44 | 2550 | hspi->State = HAL_SPI_STATE_READY; |
lypinator | 0:bb348c97df44 | 2551 | |
lypinator | 0:bb348c97df44 | 2552 | /* Call user Abort complete callback */ |
lypinator | 0:bb348c97df44 | 2553 | HAL_SPI_AbortCpltCallback(hspi); |
lypinator | 0:bb348c97df44 | 2554 | } |
lypinator | 0:bb348c97df44 | 2555 | |
lypinator | 0:bb348c97df44 | 2556 | /** |
lypinator | 0:bb348c97df44 | 2557 | * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode. |
lypinator | 0:bb348c97df44 | 2558 | * @param hspi pointer to a SPI_HandleTypeDef structure that contains |
lypinator | 0:bb348c97df44 | 2559 | * the configuration information for SPI module. |
lypinator | 0:bb348c97df44 | 2560 | * @retval None |
lypinator | 0:bb348c97df44 | 2561 | */ |
lypinator | 0:bb348c97df44 | 2562 | static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi) |
lypinator | 0:bb348c97df44 | 2563 | { |
lypinator | 0:bb348c97df44 | 2564 | /* Receive data in 8bit mode */ |
lypinator | 0:bb348c97df44 | 2565 | *hspi->pRxBuffPtr++ = *((__IO uint8_t *)&hspi->Instance->DR); |
lypinator | 0:bb348c97df44 | 2566 | hspi->RxXferCount--; |
lypinator | 0:bb348c97df44 | 2567 | |
lypinator | 0:bb348c97df44 | 2568 | /* check end of the reception */ |
lypinator | 0:bb348c97df44 | 2569 | if(hspi->RxXferCount == 0U) |
lypinator | 0:bb348c97df44 | 2570 | { |
lypinator | 0:bb348c97df44 | 2571 | #if (USE_SPI_CRC != 0U) |
lypinator | 0:bb348c97df44 | 2572 | if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) |
lypinator | 0:bb348c97df44 | 2573 | { |
lypinator | 0:bb348c97df44 | 2574 | hspi->RxISR = SPI_2linesRxISR_8BITCRC; |
lypinator | 0:bb348c97df44 | 2575 | return; |
lypinator | 0:bb348c97df44 | 2576 | } |
lypinator | 0:bb348c97df44 | 2577 | #endif /* USE_SPI_CRC */ |
lypinator | 0:bb348c97df44 | 2578 | |
lypinator | 0:bb348c97df44 | 2579 | /* Disable RXNE interrupt */ |
lypinator | 0:bb348c97df44 | 2580 | __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); |
lypinator | 0:bb348c97df44 | 2581 | |
lypinator | 0:bb348c97df44 | 2582 | if(hspi->TxXferCount == 0U) |
lypinator | 0:bb348c97df44 | 2583 | { |
lypinator | 0:bb348c97df44 | 2584 | SPI_CloseRxTx_ISR(hspi); |
lypinator | 0:bb348c97df44 | 2585 | } |
lypinator | 0:bb348c97df44 | 2586 | } |
lypinator | 0:bb348c97df44 | 2587 | } |
lypinator | 0:bb348c97df44 | 2588 | |
lypinator | 0:bb348c97df44 | 2589 | #if (USE_SPI_CRC != 0U) |
lypinator | 0:bb348c97df44 | 2590 | /** |
lypinator | 0:bb348c97df44 | 2591 | * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode. |
lypinator | 0:bb348c97df44 | 2592 | * @param hspi pointer to a SPI_HandleTypeDef structure that contains |
lypinator | 0:bb348c97df44 | 2593 | * the configuration information for SPI module. |
lypinator | 0:bb348c97df44 | 2594 | * @retval None |
lypinator | 0:bb348c97df44 | 2595 | */ |
lypinator | 0:bb348c97df44 | 2596 | static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi) |
lypinator | 0:bb348c97df44 | 2597 | { |
lypinator | 0:bb348c97df44 | 2598 | __IO uint8_t tmpreg = 0U; |
lypinator | 0:bb348c97df44 | 2599 | |
lypinator | 0:bb348c97df44 | 2600 | /* Read data register to flush CRC */ |
lypinator | 0:bb348c97df44 | 2601 | tmpreg = *((__IO uint8_t *)&hspi->Instance->DR); |
lypinator | 0:bb348c97df44 | 2602 | |
lypinator | 0:bb348c97df44 | 2603 | /* To avoid GCC warning */ |
lypinator | 0:bb348c97df44 | 2604 | |
lypinator | 0:bb348c97df44 | 2605 | UNUSED(tmpreg); |
lypinator | 0:bb348c97df44 | 2606 | |
lypinator | 0:bb348c97df44 | 2607 | /* Disable RXNE interrupt */ |
lypinator | 0:bb348c97df44 | 2608 | __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); |
lypinator | 0:bb348c97df44 | 2609 | |
lypinator | 0:bb348c97df44 | 2610 | if(hspi->TxXferCount == 0U) |
lypinator | 0:bb348c97df44 | 2611 | { |
lypinator | 0:bb348c97df44 | 2612 | SPI_CloseRxTx_ISR(hspi); |
lypinator | 0:bb348c97df44 | 2613 | } |
lypinator | 0:bb348c97df44 | 2614 | } |
lypinator | 0:bb348c97df44 | 2615 | #endif /* USE_SPI_CRC */ |
lypinator | 0:bb348c97df44 | 2616 | |
lypinator | 0:bb348c97df44 | 2617 | /** |
lypinator | 0:bb348c97df44 | 2618 | * @brief Tx 8-bit handler for Transmit and Receive in Interrupt mode. |
lypinator | 0:bb348c97df44 | 2619 | * @param hspi pointer to a SPI_HandleTypeDef structure that contains |
lypinator | 0:bb348c97df44 | 2620 | * the configuration information for SPI module. |
lypinator | 0:bb348c97df44 | 2621 | * @retval None |
lypinator | 0:bb348c97df44 | 2622 | */ |
lypinator | 0:bb348c97df44 | 2623 | static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi) |
lypinator | 0:bb348c97df44 | 2624 | { |
lypinator | 0:bb348c97df44 | 2625 | *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++); |
lypinator | 0:bb348c97df44 | 2626 | hspi->TxXferCount--; |
lypinator | 0:bb348c97df44 | 2627 | |
lypinator | 0:bb348c97df44 | 2628 | /* check the end of the transmission */ |
lypinator | 0:bb348c97df44 | 2629 | if(hspi->TxXferCount == 0U) |
lypinator | 0:bb348c97df44 | 2630 | { |
lypinator | 0:bb348c97df44 | 2631 | #if (USE_SPI_CRC != 0U) |
lypinator | 0:bb348c97df44 | 2632 | if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) |
lypinator | 0:bb348c97df44 | 2633 | { |
lypinator | 0:bb348c97df44 | 2634 | SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); |
lypinator | 0:bb348c97df44 | 2635 | __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE); |
lypinator | 0:bb348c97df44 | 2636 | return; |
lypinator | 0:bb348c97df44 | 2637 | } |
lypinator | 0:bb348c97df44 | 2638 | #endif /* USE_SPI_CRC */ |
lypinator | 0:bb348c97df44 | 2639 | |
lypinator | 0:bb348c97df44 | 2640 | /* Disable TXE interrupt */ |
lypinator | 0:bb348c97df44 | 2641 | __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE); |
lypinator | 0:bb348c97df44 | 2642 | |
lypinator | 0:bb348c97df44 | 2643 | if(hspi->RxXferCount == 0U) |
lypinator | 0:bb348c97df44 | 2644 | { |
lypinator | 0:bb348c97df44 | 2645 | SPI_CloseRxTx_ISR(hspi); |
lypinator | 0:bb348c97df44 | 2646 | } |
lypinator | 0:bb348c97df44 | 2647 | } |
lypinator | 0:bb348c97df44 | 2648 | } |
lypinator | 0:bb348c97df44 | 2649 | |
lypinator | 0:bb348c97df44 | 2650 | /** |
lypinator | 0:bb348c97df44 | 2651 | * @brief Rx 16-bit handler for Transmit and Receive in Interrupt mode. |
lypinator | 0:bb348c97df44 | 2652 | * @param hspi pointer to a SPI_HandleTypeDef structure that contains |
lypinator | 0:bb348c97df44 | 2653 | * the configuration information for SPI module. |
lypinator | 0:bb348c97df44 | 2654 | * @retval None |
lypinator | 0:bb348c97df44 | 2655 | */ |
lypinator | 0:bb348c97df44 | 2656 | static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi) |
lypinator | 0:bb348c97df44 | 2657 | { |
lypinator | 0:bb348c97df44 | 2658 | /* Receive data in 16 Bit mode */ |
lypinator | 0:bb348c97df44 | 2659 | *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; |
lypinator | 0:bb348c97df44 | 2660 | hspi->pRxBuffPtr += sizeof(uint16_t); |
lypinator | 0:bb348c97df44 | 2661 | hspi->RxXferCount--; |
lypinator | 0:bb348c97df44 | 2662 | |
lypinator | 0:bb348c97df44 | 2663 | if(hspi->RxXferCount == 0U) |
lypinator | 0:bb348c97df44 | 2664 | { |
lypinator | 0:bb348c97df44 | 2665 | #if (USE_SPI_CRC != 0U) |
lypinator | 0:bb348c97df44 | 2666 | if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) |
lypinator | 0:bb348c97df44 | 2667 | { |
lypinator | 0:bb348c97df44 | 2668 | hspi->RxISR = SPI_2linesRxISR_16BITCRC; |
lypinator | 0:bb348c97df44 | 2669 | return; |
lypinator | 0:bb348c97df44 | 2670 | } |
lypinator | 0:bb348c97df44 | 2671 | #endif /* USE_SPI_CRC */ |
lypinator | 0:bb348c97df44 | 2672 | |
lypinator | 0:bb348c97df44 | 2673 | /* Disable RXNE interrupt */ |
lypinator | 0:bb348c97df44 | 2674 | __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE); |
lypinator | 0:bb348c97df44 | 2675 | |
lypinator | 0:bb348c97df44 | 2676 | if(hspi->TxXferCount == 0U) |
lypinator | 0:bb348c97df44 | 2677 | { |
lypinator | 0:bb348c97df44 | 2678 | SPI_CloseRxTx_ISR(hspi); |
lypinator | 0:bb348c97df44 | 2679 | } |
lypinator | 0:bb348c97df44 | 2680 | } |
lypinator | 0:bb348c97df44 | 2681 | } |
lypinator | 0:bb348c97df44 | 2682 | |
lypinator | 0:bb348c97df44 | 2683 | #if (USE_SPI_CRC != 0U) |
lypinator | 0:bb348c97df44 | 2684 | /** |
lypinator | 0:bb348c97df44 | 2685 | * @brief Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode. |
lypinator | 0:bb348c97df44 | 2686 | * @param hspi pointer to a SPI_HandleTypeDef structure that contains |
lypinator | 0:bb348c97df44 | 2687 | * the configuration information for SPI module. |
lypinator | 0:bb348c97df44 | 2688 | * @retval None |
lypinator | 0:bb348c97df44 | 2689 | */ |
lypinator | 0:bb348c97df44 | 2690 | static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi) |
lypinator | 0:bb348c97df44 | 2691 | { |
lypinator | 0:bb348c97df44 | 2692 | /* Receive data in 16 Bit mode */ |
lypinator | 0:bb348c97df44 | 2693 | __IO uint16_t tmpreg = 0U; |
lypinator | 0:bb348c97df44 | 2694 | |
lypinator | 0:bb348c97df44 | 2695 | /* Read data register to flush CRC */ |
lypinator | 0:bb348c97df44 | 2696 | tmpreg = hspi->Instance->DR; |
lypinator | 0:bb348c97df44 | 2697 | |
lypinator | 0:bb348c97df44 | 2698 | /* To avoid GCC warning */ |
lypinator | 0:bb348c97df44 | 2699 | UNUSED(tmpreg); |
lypinator | 0:bb348c97df44 | 2700 | |
lypinator | 0:bb348c97df44 | 2701 | /* Disable RXNE interrupt */ |
lypinator | 0:bb348c97df44 | 2702 | __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE); |
lypinator | 0:bb348c97df44 | 2703 | |
lypinator | 0:bb348c97df44 | 2704 | SPI_CloseRxTx_ISR(hspi); |
lypinator | 0:bb348c97df44 | 2705 | } |
lypinator | 0:bb348c97df44 | 2706 | #endif /* USE_SPI_CRC */ |
lypinator | 0:bb348c97df44 | 2707 | |
lypinator | 0:bb348c97df44 | 2708 | /** |
lypinator | 0:bb348c97df44 | 2709 | * @brief Tx 16-bit handler for Transmit and Receive in Interrupt mode. |
lypinator | 0:bb348c97df44 | 2710 | * @param hspi pointer to a SPI_HandleTypeDef structure that contains |
lypinator | 0:bb348c97df44 | 2711 | * the configuration information for SPI module. |
lypinator | 0:bb348c97df44 | 2712 | * @retval None |
lypinator | 0:bb348c97df44 | 2713 | */ |
lypinator | 0:bb348c97df44 | 2714 | static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi) |
lypinator | 0:bb348c97df44 | 2715 | { |
lypinator | 0:bb348c97df44 | 2716 | /* Transmit data in 16 Bit mode */ |
lypinator | 0:bb348c97df44 | 2717 | hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); |
lypinator | 0:bb348c97df44 | 2718 | hspi->pTxBuffPtr += sizeof(uint16_t); |
lypinator | 0:bb348c97df44 | 2719 | hspi->TxXferCount--; |
lypinator | 0:bb348c97df44 | 2720 | |
lypinator | 0:bb348c97df44 | 2721 | /* Enable CRC Transmission */ |
lypinator | 0:bb348c97df44 | 2722 | if(hspi->TxXferCount == 0U) |
lypinator | 0:bb348c97df44 | 2723 | { |
lypinator | 0:bb348c97df44 | 2724 | #if (USE_SPI_CRC != 0U) |
lypinator | 0:bb348c97df44 | 2725 | if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) |
lypinator | 0:bb348c97df44 | 2726 | { |
lypinator | 0:bb348c97df44 | 2727 | SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); |
lypinator | 0:bb348c97df44 | 2728 | __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE); |
lypinator | 0:bb348c97df44 | 2729 | return; |
lypinator | 0:bb348c97df44 | 2730 | } |
lypinator | 0:bb348c97df44 | 2731 | #endif /* USE_SPI_CRC */ |
lypinator | 0:bb348c97df44 | 2732 | |
lypinator | 0:bb348c97df44 | 2733 | /* Disable TXE interrupt */ |
lypinator | 0:bb348c97df44 | 2734 | __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE); |
lypinator | 0:bb348c97df44 | 2735 | |
lypinator | 0:bb348c97df44 | 2736 | if(hspi->RxXferCount == 0U) |
lypinator | 0:bb348c97df44 | 2737 | { |
lypinator | 0:bb348c97df44 | 2738 | SPI_CloseRxTx_ISR(hspi); |
lypinator | 0:bb348c97df44 | 2739 | } |
lypinator | 0:bb348c97df44 | 2740 | } |
lypinator | 0:bb348c97df44 | 2741 | } |
lypinator | 0:bb348c97df44 | 2742 | |
lypinator | 0:bb348c97df44 | 2743 | #if (USE_SPI_CRC != 0U) |
lypinator | 0:bb348c97df44 | 2744 | /** |
lypinator | 0:bb348c97df44 | 2745 | * @brief Manage the CRC 8-bit receive in Interrupt context. |
lypinator | 0:bb348c97df44 | 2746 | * @param hspi pointer to a SPI_HandleTypeDef structure that contains |
lypinator | 0:bb348c97df44 | 2747 | * the configuration information for SPI module. |
lypinator | 0:bb348c97df44 | 2748 | * @retval None |
lypinator | 0:bb348c97df44 | 2749 | */ |
lypinator | 0:bb348c97df44 | 2750 | static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi) |
lypinator | 0:bb348c97df44 | 2751 | { |
lypinator | 0:bb348c97df44 | 2752 | __IO uint8_t tmpreg = 0U; |
lypinator | 0:bb348c97df44 | 2753 | |
lypinator | 0:bb348c97df44 | 2754 | /* Read data register to flush CRC */ |
lypinator | 0:bb348c97df44 | 2755 | tmpreg = *((__IO uint8_t*)&hspi->Instance->DR); |
lypinator | 0:bb348c97df44 | 2756 | |
lypinator | 0:bb348c97df44 | 2757 | /* To avoid GCC warning */ |
lypinator | 0:bb348c97df44 | 2758 | UNUSED(tmpreg); |
lypinator | 0:bb348c97df44 | 2759 | |
lypinator | 0:bb348c97df44 | 2760 | SPI_CloseRx_ISR(hspi); |
lypinator | 0:bb348c97df44 | 2761 | } |
lypinator | 0:bb348c97df44 | 2762 | #endif /* USE_SPI_CRC */ |
lypinator | 0:bb348c97df44 | 2763 | |
lypinator | 0:bb348c97df44 | 2764 | /** |
lypinator | 0:bb348c97df44 | 2765 | * @brief Manage the receive 8-bit in Interrupt context. |
lypinator | 0:bb348c97df44 | 2766 | * @param hspi pointer to a SPI_HandleTypeDef structure that contains |
lypinator | 0:bb348c97df44 | 2767 | * the configuration information for SPI module. |
lypinator | 0:bb348c97df44 | 2768 | * @retval None |
lypinator | 0:bb348c97df44 | 2769 | */ |
lypinator | 0:bb348c97df44 | 2770 | static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi) |
lypinator | 0:bb348c97df44 | 2771 | { |
lypinator | 0:bb348c97df44 | 2772 | *hspi->pRxBuffPtr++ = (*(__IO uint8_t *)&hspi->Instance->DR); |
lypinator | 0:bb348c97df44 | 2773 | hspi->RxXferCount--; |
lypinator | 0:bb348c97df44 | 2774 | |
lypinator | 0:bb348c97df44 | 2775 | #if (USE_SPI_CRC != 0U) |
lypinator | 0:bb348c97df44 | 2776 | /* Enable CRC Transmission */ |
lypinator | 0:bb348c97df44 | 2777 | if((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) |
lypinator | 0:bb348c97df44 | 2778 | { |
lypinator | 0:bb348c97df44 | 2779 | SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); |
lypinator | 0:bb348c97df44 | 2780 | } |
lypinator | 0:bb348c97df44 | 2781 | #endif /* USE_SPI_CRC */ |
lypinator | 0:bb348c97df44 | 2782 | |
lypinator | 0:bb348c97df44 | 2783 | if(hspi->RxXferCount == 0U) |
lypinator | 0:bb348c97df44 | 2784 | { |
lypinator | 0:bb348c97df44 | 2785 | #if (USE_SPI_CRC != 0U) |
lypinator | 0:bb348c97df44 | 2786 | if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) |
lypinator | 0:bb348c97df44 | 2787 | { |
lypinator | 0:bb348c97df44 | 2788 | hspi->RxISR = SPI_RxISR_8BITCRC; |
lypinator | 0:bb348c97df44 | 2789 | return; |
lypinator | 0:bb348c97df44 | 2790 | } |
lypinator | 0:bb348c97df44 | 2791 | #endif /* USE_SPI_CRC */ |
lypinator | 0:bb348c97df44 | 2792 | SPI_CloseRx_ISR(hspi); |
lypinator | 0:bb348c97df44 | 2793 | } |
lypinator | 0:bb348c97df44 | 2794 | } |
lypinator | 0:bb348c97df44 | 2795 | |
lypinator | 0:bb348c97df44 | 2796 | #if (USE_SPI_CRC != 0U) |
lypinator | 0:bb348c97df44 | 2797 | /** |
lypinator | 0:bb348c97df44 | 2798 | * @brief Manage the CRC 16-bit receive in Interrupt context. |
lypinator | 0:bb348c97df44 | 2799 | * @param hspi pointer to a SPI_HandleTypeDef structure that contains |
lypinator | 0:bb348c97df44 | 2800 | * the configuration information for SPI module. |
lypinator | 0:bb348c97df44 | 2801 | * @retval None |
lypinator | 0:bb348c97df44 | 2802 | */ |
lypinator | 0:bb348c97df44 | 2803 | static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi) |
lypinator | 0:bb348c97df44 | 2804 | { |
lypinator | 0:bb348c97df44 | 2805 | __IO uint16_t tmpreg = 0U; |
lypinator | 0:bb348c97df44 | 2806 | |
lypinator | 0:bb348c97df44 | 2807 | /* Read data register to flush CRC */ |
lypinator | 0:bb348c97df44 | 2808 | tmpreg = hspi->Instance->DR; |
lypinator | 0:bb348c97df44 | 2809 | |
lypinator | 0:bb348c97df44 | 2810 | /* To avoid GCC warning */ |
lypinator | 0:bb348c97df44 | 2811 | UNUSED(tmpreg); |
lypinator | 0:bb348c97df44 | 2812 | |
lypinator | 0:bb348c97df44 | 2813 | /* Disable RXNE and ERR interrupt */ |
lypinator | 0:bb348c97df44 | 2814 | __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); |
lypinator | 0:bb348c97df44 | 2815 | |
lypinator | 0:bb348c97df44 | 2816 | SPI_CloseRx_ISR(hspi); |
lypinator | 0:bb348c97df44 | 2817 | } |
lypinator | 0:bb348c97df44 | 2818 | #endif /* USE_SPI_CRC */ |
lypinator | 0:bb348c97df44 | 2819 | |
lypinator | 0:bb348c97df44 | 2820 | /** |
lypinator | 0:bb348c97df44 | 2821 | * @brief Manage the 16-bit receive in Interrupt context. |
lypinator | 0:bb348c97df44 | 2822 | * @param hspi pointer to a SPI_HandleTypeDef structure that contains |
lypinator | 0:bb348c97df44 | 2823 | * the configuration information for SPI module. |
lypinator | 0:bb348c97df44 | 2824 | * @retval None |
lypinator | 0:bb348c97df44 | 2825 | */ |
lypinator | 0:bb348c97df44 | 2826 | static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi) |
lypinator | 0:bb348c97df44 | 2827 | { |
lypinator | 0:bb348c97df44 | 2828 | *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR; |
lypinator | 0:bb348c97df44 | 2829 | hspi->pRxBuffPtr += sizeof(uint16_t); |
lypinator | 0:bb348c97df44 | 2830 | hspi->RxXferCount--; |
lypinator | 0:bb348c97df44 | 2831 | |
lypinator | 0:bb348c97df44 | 2832 | #if (USE_SPI_CRC != 0U) |
lypinator | 0:bb348c97df44 | 2833 | /* Enable CRC Transmission */ |
lypinator | 0:bb348c97df44 | 2834 | if((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) |
lypinator | 0:bb348c97df44 | 2835 | { |
lypinator | 0:bb348c97df44 | 2836 | SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); |
lypinator | 0:bb348c97df44 | 2837 | } |
lypinator | 0:bb348c97df44 | 2838 | #endif /* USE_SPI_CRC */ |
lypinator | 0:bb348c97df44 | 2839 | |
lypinator | 0:bb348c97df44 | 2840 | if(hspi->RxXferCount == 0U) |
lypinator | 0:bb348c97df44 | 2841 | { |
lypinator | 0:bb348c97df44 | 2842 | #if (USE_SPI_CRC != 0U) |
lypinator | 0:bb348c97df44 | 2843 | if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) |
lypinator | 0:bb348c97df44 | 2844 | { |
lypinator | 0:bb348c97df44 | 2845 | hspi->RxISR = SPI_RxISR_16BITCRC; |
lypinator | 0:bb348c97df44 | 2846 | return; |
lypinator | 0:bb348c97df44 | 2847 | } |
lypinator | 0:bb348c97df44 | 2848 | #endif /* USE_SPI_CRC */ |
lypinator | 0:bb348c97df44 | 2849 | SPI_CloseRx_ISR(hspi); |
lypinator | 0:bb348c97df44 | 2850 | } |
lypinator | 0:bb348c97df44 | 2851 | } |
lypinator | 0:bb348c97df44 | 2852 | |
lypinator | 0:bb348c97df44 | 2853 | /** |
lypinator | 0:bb348c97df44 | 2854 | * @brief Handle the data 8-bit transmit in Interrupt mode. |
lypinator | 0:bb348c97df44 | 2855 | * @param hspi pointer to a SPI_HandleTypeDef structure that contains |
lypinator | 0:bb348c97df44 | 2856 | * the configuration information for SPI module. |
lypinator | 0:bb348c97df44 | 2857 | * @retval None |
lypinator | 0:bb348c97df44 | 2858 | */ |
lypinator | 0:bb348c97df44 | 2859 | static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi) |
lypinator | 0:bb348c97df44 | 2860 | { |
lypinator | 0:bb348c97df44 | 2861 | *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++); |
lypinator | 0:bb348c97df44 | 2862 | hspi->TxXferCount--; |
lypinator | 0:bb348c97df44 | 2863 | |
lypinator | 0:bb348c97df44 | 2864 | if(hspi->TxXferCount == 0U) |
lypinator | 0:bb348c97df44 | 2865 | { |
lypinator | 0:bb348c97df44 | 2866 | #if (USE_SPI_CRC != 0U) |
lypinator | 0:bb348c97df44 | 2867 | if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) |
lypinator | 0:bb348c97df44 | 2868 | { |
lypinator | 0:bb348c97df44 | 2869 | /* Enable CRC Transmission */ |
lypinator | 0:bb348c97df44 | 2870 | SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); |
lypinator | 0:bb348c97df44 | 2871 | } |
lypinator | 0:bb348c97df44 | 2872 | #endif /* USE_SPI_CRC */ |
lypinator | 0:bb348c97df44 | 2873 | /* MBED */ |
lypinator | 0:bb348c97df44 | 2874 | __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE)); |
lypinator | 0:bb348c97df44 | 2875 | /* MBED */ |
lypinator | 0:bb348c97df44 | 2876 | SPI_CloseTx_ISR(hspi); |
lypinator | 0:bb348c97df44 | 2877 | } |
lypinator | 0:bb348c97df44 | 2878 | } |
lypinator | 0:bb348c97df44 | 2879 | |
lypinator | 0:bb348c97df44 | 2880 | /** |
lypinator | 0:bb348c97df44 | 2881 | * @brief Handle the data 16-bit transmit in Interrupt mode. |
lypinator | 0:bb348c97df44 | 2882 | * @param hspi pointer to a SPI_HandleTypeDef structure that contains |
lypinator | 0:bb348c97df44 | 2883 | * the configuration information for SPI module. |
lypinator | 0:bb348c97df44 | 2884 | * @retval None |
lypinator | 0:bb348c97df44 | 2885 | */ |
lypinator | 0:bb348c97df44 | 2886 | static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi) |
lypinator | 0:bb348c97df44 | 2887 | { |
lypinator | 0:bb348c97df44 | 2888 | /* Transmit data in 16 Bit mode */ |
lypinator | 0:bb348c97df44 | 2889 | hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); |
lypinator | 0:bb348c97df44 | 2890 | hspi->pTxBuffPtr += sizeof(uint16_t); |
lypinator | 0:bb348c97df44 | 2891 | hspi->TxXferCount--; |
lypinator | 0:bb348c97df44 | 2892 | |
lypinator | 0:bb348c97df44 | 2893 | if(hspi->TxXferCount == 0U) |
lypinator | 0:bb348c97df44 | 2894 | { |
lypinator | 0:bb348c97df44 | 2895 | #if (USE_SPI_CRC != 0U) |
lypinator | 0:bb348c97df44 | 2896 | if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) |
lypinator | 0:bb348c97df44 | 2897 | { |
lypinator | 0:bb348c97df44 | 2898 | /* Enable CRC Transmission */ |
lypinator | 0:bb348c97df44 | 2899 | SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); |
lypinator | 0:bb348c97df44 | 2900 | } |
lypinator | 0:bb348c97df44 | 2901 | #endif /* USE_SPI_CRC */ |
lypinator | 0:bb348c97df44 | 2902 | /* MBED */ |
lypinator | 0:bb348c97df44 | 2903 | __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE)); |
lypinator | 0:bb348c97df44 | 2904 | /* MBED */ |
lypinator | 0:bb348c97df44 | 2905 | SPI_CloseTx_ISR(hspi); |
lypinator | 0:bb348c97df44 | 2906 | } |
lypinator | 0:bb348c97df44 | 2907 | } |
lypinator | 0:bb348c97df44 | 2908 | |
lypinator | 0:bb348c97df44 | 2909 | /** |
lypinator | 0:bb348c97df44 | 2910 | * @brief Handle SPI Communication Timeout. |
lypinator | 0:bb348c97df44 | 2911 | * @param hspi pointer to a SPI_HandleTypeDef structure that contains |
lypinator | 0:bb348c97df44 | 2912 | * the configuration information for SPI module. |
lypinator | 0:bb348c97df44 | 2913 | * @param Flag SPI flag to check |
lypinator | 0:bb348c97df44 | 2914 | * @param State flag state to check |
lypinator | 0:bb348c97df44 | 2915 | * @param Timeout Timeout duration |
lypinator | 0:bb348c97df44 | 2916 | * @param Tickstart tick start value |
lypinator | 0:bb348c97df44 | 2917 | * @retval HAL status |
lypinator | 0:bb348c97df44 | 2918 | */ |
lypinator | 0:bb348c97df44 | 2919 | static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout, uint32_t Tickstart) |
lypinator | 0:bb348c97df44 | 2920 | { |
lypinator | 0:bb348c97df44 | 2921 | /* MBED */ |
lypinator | 0:bb348c97df44 | 2922 | while((hspi->Instance->SR & Flag) != State) |
lypinator | 0:bb348c97df44 | 2923 | /* MBED */ |
lypinator | 0:bb348c97df44 | 2924 | { |
lypinator | 0:bb348c97df44 | 2925 | if(Timeout != HAL_MAX_DELAY) |
lypinator | 0:bb348c97df44 | 2926 | { |
lypinator | 0:bb348c97df44 | 2927 | if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) >= Timeout)) |
lypinator | 0:bb348c97df44 | 2928 | { |
lypinator | 0:bb348c97df44 | 2929 | /* Disable the SPI and reset the CRC: the CRC value should be cleared |
lypinator | 0:bb348c97df44 | 2930 | on both master and slave sides in order to resynchronize the master |
lypinator | 0:bb348c97df44 | 2931 | and slave for their respective CRC calculation */ |
lypinator | 0:bb348c97df44 | 2932 | |
lypinator | 0:bb348c97df44 | 2933 | /* Disable TXE, RXNE and ERR interrupts for the interrupt process */ |
lypinator | 0:bb348c97df44 | 2934 | __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); |
lypinator | 0:bb348c97df44 | 2935 | |
lypinator | 0:bb348c97df44 | 2936 | if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) |
lypinator | 0:bb348c97df44 | 2937 | { |
lypinator | 0:bb348c97df44 | 2938 | /* Disable SPI peripheral */ |
lypinator | 0:bb348c97df44 | 2939 | __HAL_SPI_DISABLE(hspi); |
lypinator | 0:bb348c97df44 | 2940 | } |
lypinator | 0:bb348c97df44 | 2941 | |
lypinator | 0:bb348c97df44 | 2942 | /* Reset CRC Calculation */ |
lypinator | 0:bb348c97df44 | 2943 | if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) |
lypinator | 0:bb348c97df44 | 2944 | { |
lypinator | 0:bb348c97df44 | 2945 | SPI_RESET_CRC(hspi); |
lypinator | 0:bb348c97df44 | 2946 | } |
lypinator | 0:bb348c97df44 | 2947 | |
lypinator | 0:bb348c97df44 | 2948 | hspi->State= HAL_SPI_STATE_READY; |
lypinator | 0:bb348c97df44 | 2949 | |
lypinator | 0:bb348c97df44 | 2950 | /* Process Unlocked */ |
lypinator | 0:bb348c97df44 | 2951 | __HAL_UNLOCK(hspi); |
lypinator | 0:bb348c97df44 | 2952 | |
lypinator | 0:bb348c97df44 | 2953 | return HAL_TIMEOUT; |
lypinator | 0:bb348c97df44 | 2954 | } |
lypinator | 0:bb348c97df44 | 2955 | } |
lypinator | 0:bb348c97df44 | 2956 | } |
lypinator | 0:bb348c97df44 | 2957 | |
lypinator | 0:bb348c97df44 | 2958 | return HAL_OK; |
lypinator | 0:bb348c97df44 | 2959 | } |
lypinator | 0:bb348c97df44 | 2960 | |
lypinator | 0:bb348c97df44 | 2961 | /* MBED */ |
lypinator | 0:bb348c97df44 | 2962 | /** |
lypinator | 0:bb348c97df44 | 2963 | * @brief Handle SPI Communication Timeout. |
lypinator | 0:bb348c97df44 | 2964 | * @param hspi: pointer to a SPI_HandleTypeDef structure that contains |
lypinator | 0:bb348c97df44 | 2965 | * the configuration information for SPI module. |
lypinator | 0:bb348c97df44 | 2966 | * @param Flag: SPI TXE flag to check |
lypinator | 0:bb348c97df44 | 2967 | * @param State: flag state to check |
lypinator | 0:bb348c97df44 | 2968 | * @param Timeout: Timeout duration |
lypinator | 0:bb348c97df44 | 2969 | * @param Tickstart: tick start value |
lypinator | 0:bb348c97df44 | 2970 | * @retval HAL status |
lypinator | 0:bb348c97df44 | 2971 | */ |
lypinator | 0:bb348c97df44 | 2972 | static HAL_StatusTypeDef SPI_WaitTXEFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart) |
lypinator | 0:bb348c97df44 | 2973 | { |
lypinator | 0:bb348c97df44 | 2974 | while((hspi->Instance->SR & SPI_FLAG_TXE) == RESET) |
lypinator | 0:bb348c97df44 | 2975 | { |
lypinator | 0:bb348c97df44 | 2976 | if(Timeout != HAL_MAX_DELAY) |
lypinator | 0:bb348c97df44 | 2977 | { |
lypinator | 0:bb348c97df44 | 2978 | if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) >= Timeout)) |
lypinator | 0:bb348c97df44 | 2979 | { |
lypinator | 0:bb348c97df44 | 2980 | /* Disable the SPI and reset the CRC: the CRC value should be cleared |
lypinator | 0:bb348c97df44 | 2981 | on both master and slave sides in order to resynchronize the master |
lypinator | 0:bb348c97df44 | 2982 | and slave for their respective CRC calculation */ |
lypinator | 0:bb348c97df44 | 2983 | |
lypinator | 0:bb348c97df44 | 2984 | /* Disable TXE, RXNE and ERR interrupts for the interrupt process */ |
lypinator | 0:bb348c97df44 | 2985 | __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); |
lypinator | 0:bb348c97df44 | 2986 | |
lypinator | 0:bb348c97df44 | 2987 | if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) |
lypinator | 0:bb348c97df44 | 2988 | { |
lypinator | 0:bb348c97df44 | 2989 | /* Disable SPI peripheral */ |
lypinator | 0:bb348c97df44 | 2990 | __HAL_SPI_DISABLE(hspi); |
lypinator | 0:bb348c97df44 | 2991 | } |
lypinator | 0:bb348c97df44 | 2992 | |
lypinator | 0:bb348c97df44 | 2993 | /* Reset CRC Calculation */ |
lypinator | 0:bb348c97df44 | 2994 | if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) |
lypinator | 0:bb348c97df44 | 2995 | { |
lypinator | 0:bb348c97df44 | 2996 | SPI_RESET_CRC(hspi); |
lypinator | 0:bb348c97df44 | 2997 | } |
lypinator | 0:bb348c97df44 | 2998 | |
lypinator | 0:bb348c97df44 | 2999 | hspi->State= HAL_SPI_STATE_READY; |
lypinator | 0:bb348c97df44 | 3000 | |
lypinator | 0:bb348c97df44 | 3001 | /* Process Unlocked */ |
lypinator | 0:bb348c97df44 | 3002 | __HAL_UNLOCK(hspi); |
lypinator | 0:bb348c97df44 | 3003 | |
lypinator | 0:bb348c97df44 | 3004 | return HAL_TIMEOUT; |
lypinator | 0:bb348c97df44 | 3005 | } |
lypinator | 0:bb348c97df44 | 3006 | } |
lypinator | 0:bb348c97df44 | 3007 | } |
lypinator | 0:bb348c97df44 | 3008 | |
lypinator | 0:bb348c97df44 | 3009 | return HAL_OK; |
lypinator | 0:bb348c97df44 | 3010 | } |
lypinator | 0:bb348c97df44 | 3011 | /* MBED */ |
lypinator | 0:bb348c97df44 | 3012 | |
lypinator | 0:bb348c97df44 | 3013 | /** |
lypinator | 0:bb348c97df44 | 3014 | * @brief Handle to check BSY flag before start a new transaction. |
lypinator | 0:bb348c97df44 | 3015 | * @param hspi pointer to a SPI_HandleTypeDef structure that contains |
lypinator | 0:bb348c97df44 | 3016 | * the configuration information for SPI module. |
lypinator | 0:bb348c97df44 | 3017 | * @param Timeout Timeout duration |
lypinator | 0:bb348c97df44 | 3018 | * @param Tickstart tick start value |
lypinator | 0:bb348c97df44 | 3019 | * @retval HAL status |
lypinator | 0:bb348c97df44 | 3020 | */ |
lypinator | 0:bb348c97df44 | 3021 | static HAL_StatusTypeDef SPI_CheckFlag_BSY(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart) |
lypinator | 0:bb348c97df44 | 3022 | { |
lypinator | 0:bb348c97df44 | 3023 | /* Control the BSY flag */ |
lypinator | 0:bb348c97df44 | 3024 | if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK) |
lypinator | 0:bb348c97df44 | 3025 | { |
lypinator | 0:bb348c97df44 | 3026 | SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); |
lypinator | 0:bb348c97df44 | 3027 | return HAL_TIMEOUT; |
lypinator | 0:bb348c97df44 | 3028 | } |
lypinator | 0:bb348c97df44 | 3029 | return HAL_OK; |
lypinator | 0:bb348c97df44 | 3030 | } |
lypinator | 0:bb348c97df44 | 3031 | |
lypinator | 0:bb348c97df44 | 3032 | /** |
lypinator | 0:bb348c97df44 | 3033 | * @brief Handle the end of the RXTX transaction. |
lypinator | 0:bb348c97df44 | 3034 | * @param hspi pointer to a SPI_HandleTypeDef structure that contains |
lypinator | 0:bb348c97df44 | 3035 | * the configuration information for SPI module. |
lypinator | 0:bb348c97df44 | 3036 | * @retval None |
lypinator | 0:bb348c97df44 | 3037 | */ |
lypinator | 0:bb348c97df44 | 3038 | static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi) |
lypinator | 0:bb348c97df44 | 3039 | { |
lypinator | 0:bb348c97df44 | 3040 | uint32_t tickstart = 0U; |
lypinator | 0:bb348c97df44 | 3041 | __IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U); |
lypinator | 0:bb348c97df44 | 3042 | /* Init tickstart for timeout managment*/ |
lypinator | 0:bb348c97df44 | 3043 | tickstart = HAL_GetTick(); |
lypinator | 0:bb348c97df44 | 3044 | |
lypinator | 0:bb348c97df44 | 3045 | /* Disable ERR interrupt */ |
lypinator | 0:bb348c97df44 | 3046 | __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR); |
lypinator | 0:bb348c97df44 | 3047 | |
lypinator | 0:bb348c97df44 | 3048 | /* Wait until TXE flag is set */ |
lypinator | 0:bb348c97df44 | 3049 | do |
lypinator | 0:bb348c97df44 | 3050 | { |
lypinator | 0:bb348c97df44 | 3051 | if(count-- == 0U) |
lypinator | 0:bb348c97df44 | 3052 | { |
lypinator | 0:bb348c97df44 | 3053 | SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); |
lypinator | 0:bb348c97df44 | 3054 | break; |
lypinator | 0:bb348c97df44 | 3055 | } |
lypinator | 0:bb348c97df44 | 3056 | } |
lypinator | 0:bb348c97df44 | 3057 | while((hspi->Instance->SR & SPI_FLAG_TXE) == RESET); |
lypinator | 0:bb348c97df44 | 3058 | |
lypinator | 0:bb348c97df44 | 3059 | /* Check the end of the transaction */ |
lypinator | 0:bb348c97df44 | 3060 | if(SPI_CheckFlag_BSY(hspi, SPI_DEFAULT_TIMEOUT, tickstart)!=HAL_OK) |
lypinator | 0:bb348c97df44 | 3061 | { |
lypinator | 0:bb348c97df44 | 3062 | SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); |
lypinator | 0:bb348c97df44 | 3063 | } |
lypinator | 0:bb348c97df44 | 3064 | |
lypinator | 0:bb348c97df44 | 3065 | /* Clear overrun flag in 2 Lines communication mode because received is not read */ |
lypinator | 0:bb348c97df44 | 3066 | if(hspi->Init.Direction == SPI_DIRECTION_2LINES) |
lypinator | 0:bb348c97df44 | 3067 | { |
lypinator | 0:bb348c97df44 | 3068 | __HAL_SPI_CLEAR_OVRFLAG(hspi); |
lypinator | 0:bb348c97df44 | 3069 | } |
lypinator | 0:bb348c97df44 | 3070 | |
lypinator | 0:bb348c97df44 | 3071 | #if (USE_SPI_CRC != 0U) |
lypinator | 0:bb348c97df44 | 3072 | /* Check if CRC error occurred */ |
lypinator | 0:bb348c97df44 | 3073 | if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) |
lypinator | 0:bb348c97df44 | 3074 | { |
lypinator | 0:bb348c97df44 | 3075 | hspi->State = HAL_SPI_STATE_READY; |
lypinator | 0:bb348c97df44 | 3076 | SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); |
lypinator | 0:bb348c97df44 | 3077 | __HAL_SPI_CLEAR_CRCERRFLAG(hspi); |
lypinator | 0:bb348c97df44 | 3078 | HAL_SPI_ErrorCallback(hspi); |
lypinator | 0:bb348c97df44 | 3079 | } |
lypinator | 0:bb348c97df44 | 3080 | else |
lypinator | 0:bb348c97df44 | 3081 | { |
lypinator | 0:bb348c97df44 | 3082 | #endif /* USE_SPI_CRC */ |
lypinator | 0:bb348c97df44 | 3083 | if(hspi->ErrorCode == HAL_SPI_ERROR_NONE) |
lypinator | 0:bb348c97df44 | 3084 | { |
lypinator | 0:bb348c97df44 | 3085 | if(hspi->State == HAL_SPI_STATE_BUSY_RX) |
lypinator | 0:bb348c97df44 | 3086 | { |
lypinator | 0:bb348c97df44 | 3087 | hspi->State = HAL_SPI_STATE_READY; |
lypinator | 0:bb348c97df44 | 3088 | HAL_SPI_RxCpltCallback(hspi); |
lypinator | 0:bb348c97df44 | 3089 | } |
lypinator | 0:bb348c97df44 | 3090 | else |
lypinator | 0:bb348c97df44 | 3091 | { |
lypinator | 0:bb348c97df44 | 3092 | hspi->State = HAL_SPI_STATE_READY; |
lypinator | 0:bb348c97df44 | 3093 | HAL_SPI_TxRxCpltCallback(hspi); |
lypinator | 0:bb348c97df44 | 3094 | } |
lypinator | 0:bb348c97df44 | 3095 | } |
lypinator | 0:bb348c97df44 | 3096 | else |
lypinator | 0:bb348c97df44 | 3097 | { |
lypinator | 0:bb348c97df44 | 3098 | hspi->State = HAL_SPI_STATE_READY; |
lypinator | 0:bb348c97df44 | 3099 | HAL_SPI_ErrorCallback(hspi); |
lypinator | 0:bb348c97df44 | 3100 | } |
lypinator | 0:bb348c97df44 | 3101 | #if (USE_SPI_CRC != 0U) |
lypinator | 0:bb348c97df44 | 3102 | } |
lypinator | 0:bb348c97df44 | 3103 | #endif /* USE_SPI_CRC */ |
lypinator | 0:bb348c97df44 | 3104 | } |
lypinator | 0:bb348c97df44 | 3105 | |
lypinator | 0:bb348c97df44 | 3106 | /** |
lypinator | 0:bb348c97df44 | 3107 | * @brief Handle the end of the RX transaction. |
lypinator | 0:bb348c97df44 | 3108 | * @param hspi pointer to a SPI_HandleTypeDef structure that contains |
lypinator | 0:bb348c97df44 | 3109 | * the configuration information for SPI module. |
lypinator | 0:bb348c97df44 | 3110 | * @retval None |
lypinator | 0:bb348c97df44 | 3111 | */ |
lypinator | 0:bb348c97df44 | 3112 | static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi) |
lypinator | 0:bb348c97df44 | 3113 | { |
lypinator | 0:bb348c97df44 | 3114 | /* Disable RXNE and ERR interrupt */ |
lypinator | 0:bb348c97df44 | 3115 | __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); |
lypinator | 0:bb348c97df44 | 3116 | |
lypinator | 0:bb348c97df44 | 3117 | /* Check the end of the transaction */ |
lypinator | 0:bb348c97df44 | 3118 | if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) |
lypinator | 0:bb348c97df44 | 3119 | { |
lypinator | 0:bb348c97df44 | 3120 | /* Disable SPI peripheral */ |
lypinator | 0:bb348c97df44 | 3121 | __HAL_SPI_DISABLE(hspi); |
lypinator | 0:bb348c97df44 | 3122 | } |
lypinator | 0:bb348c97df44 | 3123 | |
lypinator | 0:bb348c97df44 | 3124 | /* Clear overrun flag in 2 Lines communication mode because received is not read */ |
lypinator | 0:bb348c97df44 | 3125 | if(hspi->Init.Direction == SPI_DIRECTION_2LINES) |
lypinator | 0:bb348c97df44 | 3126 | { |
lypinator | 0:bb348c97df44 | 3127 | __HAL_SPI_CLEAR_OVRFLAG(hspi); |
lypinator | 0:bb348c97df44 | 3128 | } |
lypinator | 0:bb348c97df44 | 3129 | hspi->State = HAL_SPI_STATE_READY; |
lypinator | 0:bb348c97df44 | 3130 | |
lypinator | 0:bb348c97df44 | 3131 | #if (USE_SPI_CRC != 0U) |
lypinator | 0:bb348c97df44 | 3132 | /* Check if CRC error occurred */ |
lypinator | 0:bb348c97df44 | 3133 | if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) |
lypinator | 0:bb348c97df44 | 3134 | { |
lypinator | 0:bb348c97df44 | 3135 | SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); |
lypinator | 0:bb348c97df44 | 3136 | __HAL_SPI_CLEAR_CRCERRFLAG(hspi); |
lypinator | 0:bb348c97df44 | 3137 | HAL_SPI_ErrorCallback(hspi); |
lypinator | 0:bb348c97df44 | 3138 | } |
lypinator | 0:bb348c97df44 | 3139 | else |
lypinator | 0:bb348c97df44 | 3140 | { |
lypinator | 0:bb348c97df44 | 3141 | #endif /* USE_SPI_CRC */ |
lypinator | 0:bb348c97df44 | 3142 | if(hspi->ErrorCode == HAL_SPI_ERROR_NONE) |
lypinator | 0:bb348c97df44 | 3143 | { |
lypinator | 0:bb348c97df44 | 3144 | HAL_SPI_RxCpltCallback(hspi); |
lypinator | 0:bb348c97df44 | 3145 | } |
lypinator | 0:bb348c97df44 | 3146 | else |
lypinator | 0:bb348c97df44 | 3147 | { |
lypinator | 0:bb348c97df44 | 3148 | HAL_SPI_ErrorCallback(hspi); |
lypinator | 0:bb348c97df44 | 3149 | } |
lypinator | 0:bb348c97df44 | 3150 | #if (USE_SPI_CRC != 0U) |
lypinator | 0:bb348c97df44 | 3151 | } |
lypinator | 0:bb348c97df44 | 3152 | #endif /* USE_SPI_CRC */ |
lypinator | 0:bb348c97df44 | 3153 | } |
lypinator | 0:bb348c97df44 | 3154 | |
lypinator | 0:bb348c97df44 | 3155 | /** |
lypinator | 0:bb348c97df44 | 3156 | * @brief Handle the end of the TX transaction. |
lypinator | 0:bb348c97df44 | 3157 | * @param hspi pointer to a SPI_HandleTypeDef structure that contains |
lypinator | 0:bb348c97df44 | 3158 | * the configuration information for SPI module. |
lypinator | 0:bb348c97df44 | 3159 | * @retval None |
lypinator | 0:bb348c97df44 | 3160 | */ |
lypinator | 0:bb348c97df44 | 3161 | static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi) |
lypinator | 0:bb348c97df44 | 3162 | { |
lypinator | 0:bb348c97df44 | 3163 | uint32_t tickstart = 0U; |
lypinator | 0:bb348c97df44 | 3164 | __IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U); |
lypinator | 0:bb348c97df44 | 3165 | |
lypinator | 0:bb348c97df44 | 3166 | /* Init tickstart for timeout management*/ |
lypinator | 0:bb348c97df44 | 3167 | tickstart = HAL_GetTick(); |
lypinator | 0:bb348c97df44 | 3168 | |
lypinator | 0:bb348c97df44 | 3169 | /* Wait until TXE flag is set */ |
lypinator | 0:bb348c97df44 | 3170 | do |
lypinator | 0:bb348c97df44 | 3171 | { |
lypinator | 0:bb348c97df44 | 3172 | if(count-- == 0U) |
lypinator | 0:bb348c97df44 | 3173 | { |
lypinator | 0:bb348c97df44 | 3174 | SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); |
lypinator | 0:bb348c97df44 | 3175 | break; |
lypinator | 0:bb348c97df44 | 3176 | } |
lypinator | 0:bb348c97df44 | 3177 | } |
lypinator | 0:bb348c97df44 | 3178 | while((hspi->Instance->SR & SPI_FLAG_TXE) == RESET); |
lypinator | 0:bb348c97df44 | 3179 | |
lypinator | 0:bb348c97df44 | 3180 | /* Disable TXE and ERR interrupt */ |
lypinator | 0:bb348c97df44 | 3181 | __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR)); |
lypinator | 0:bb348c97df44 | 3182 | |
lypinator | 0:bb348c97df44 | 3183 | /* Check Busy flag */ |
lypinator | 0:bb348c97df44 | 3184 | if(SPI_CheckFlag_BSY(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) |
lypinator | 0:bb348c97df44 | 3185 | { |
lypinator | 0:bb348c97df44 | 3186 | SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); |
lypinator | 0:bb348c97df44 | 3187 | } |
lypinator | 0:bb348c97df44 | 3188 | |
lypinator | 0:bb348c97df44 | 3189 | /* Clear overrun flag in 2 Lines communication mode because received is not read */ |
lypinator | 0:bb348c97df44 | 3190 | if(hspi->Init.Direction == SPI_DIRECTION_2LINES) |
lypinator | 0:bb348c97df44 | 3191 | { |
lypinator | 0:bb348c97df44 | 3192 | __HAL_SPI_CLEAR_OVRFLAG(hspi); |
lypinator | 0:bb348c97df44 | 3193 | } |
lypinator | 0:bb348c97df44 | 3194 | |
lypinator | 0:bb348c97df44 | 3195 | hspi->State = HAL_SPI_STATE_READY; |
lypinator | 0:bb348c97df44 | 3196 | if(hspi->ErrorCode != HAL_SPI_ERROR_NONE) |
lypinator | 0:bb348c97df44 | 3197 | { |
lypinator | 0:bb348c97df44 | 3198 | HAL_SPI_ErrorCallback(hspi); |
lypinator | 0:bb348c97df44 | 3199 | } |
lypinator | 0:bb348c97df44 | 3200 | else |
lypinator | 0:bb348c97df44 | 3201 | { |
lypinator | 0:bb348c97df44 | 3202 | HAL_SPI_TxCpltCallback(hspi); |
lypinator | 0:bb348c97df44 | 3203 | } |
lypinator | 0:bb348c97df44 | 3204 | } |
lypinator | 0:bb348c97df44 | 3205 | |
lypinator | 0:bb348c97df44 | 3206 | /** |
lypinator | 0:bb348c97df44 | 3207 | * @} |
lypinator | 0:bb348c97df44 | 3208 | */ |
lypinator | 0:bb348c97df44 | 3209 | |
lypinator | 0:bb348c97df44 | 3210 | /** |
lypinator | 0:bb348c97df44 | 3211 | * @brief Handle abort a Tx or Rx transaction. |
lypinator | 0:bb348c97df44 | 3212 | * @param hspi pointer to a SPI_HandleTypeDef structure that contains |
lypinator | 0:bb348c97df44 | 3213 | * the configuration information for SPI module. |
lypinator | 0:bb348c97df44 | 3214 | * @retval None |
lypinator | 0:bb348c97df44 | 3215 | */ |
lypinator | 0:bb348c97df44 | 3216 | static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi) |
lypinator | 0:bb348c97df44 | 3217 | { |
lypinator | 0:bb348c97df44 | 3218 | __IO uint32_t tmpreg = 0U; |
lypinator | 0:bb348c97df44 | 3219 | __IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U); |
lypinator | 0:bb348c97df44 | 3220 | |
lypinator | 0:bb348c97df44 | 3221 | /* Wait until TXE flag is set */ |
lypinator | 0:bb348c97df44 | 3222 | do |
lypinator | 0:bb348c97df44 | 3223 | { |
lypinator | 0:bb348c97df44 | 3224 | if(count-- == 0U) |
lypinator | 0:bb348c97df44 | 3225 | { |
lypinator | 0:bb348c97df44 | 3226 | SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); |
lypinator | 0:bb348c97df44 | 3227 | break; |
lypinator | 0:bb348c97df44 | 3228 | } |
lypinator | 0:bb348c97df44 | 3229 | } |
lypinator | 0:bb348c97df44 | 3230 | while((hspi->Instance->SR & SPI_FLAG_TXE) == RESET); |
lypinator | 0:bb348c97df44 | 3231 | |
lypinator | 0:bb348c97df44 | 3232 | /* Disable SPI Peripheral */ |
lypinator | 0:bb348c97df44 | 3233 | __HAL_SPI_DISABLE(hspi); |
lypinator | 0:bb348c97df44 | 3234 | |
lypinator | 0:bb348c97df44 | 3235 | /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */ |
lypinator | 0:bb348c97df44 | 3236 | CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE | SPI_CR2_RXNEIE | SPI_CR2_ERRIE)); |
lypinator | 0:bb348c97df44 | 3237 | |
lypinator | 0:bb348c97df44 | 3238 | /* Flush DR Register */ |
lypinator | 0:bb348c97df44 | 3239 | tmpreg = (*(__IO uint32_t *)&hspi->Instance->DR); |
lypinator | 0:bb348c97df44 | 3240 | |
lypinator | 0:bb348c97df44 | 3241 | /* To avoid GCC warning */ |
lypinator | 0:bb348c97df44 | 3242 | UNUSED(tmpreg); |
lypinator | 0:bb348c97df44 | 3243 | } |
lypinator | 0:bb348c97df44 | 3244 | |
lypinator | 0:bb348c97df44 | 3245 | /** |
lypinator | 0:bb348c97df44 | 3246 | * @brief Handle abort a Tx or Rx transaction. |
lypinator | 0:bb348c97df44 | 3247 | * @param hspi pointer to a SPI_HandleTypeDef structure that contains |
lypinator | 0:bb348c97df44 | 3248 | * the configuration information for SPI module. |
lypinator | 0:bb348c97df44 | 3249 | * @retval None |
lypinator | 0:bb348c97df44 | 3250 | */ |
lypinator | 0:bb348c97df44 | 3251 | static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi) |
lypinator | 0:bb348c97df44 | 3252 | { |
lypinator | 0:bb348c97df44 | 3253 | /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */ |
lypinator | 0:bb348c97df44 | 3254 | CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE | SPI_CR2_RXNEIE | SPI_CR2_ERRIE)); |
lypinator | 0:bb348c97df44 | 3255 | |
lypinator | 0:bb348c97df44 | 3256 | /* Disable SPI Peripheral */ |
lypinator | 0:bb348c97df44 | 3257 | __HAL_SPI_DISABLE(hspi); |
lypinator | 0:bb348c97df44 | 3258 | } |
lypinator | 0:bb348c97df44 | 3259 | /** |
lypinator | 0:bb348c97df44 | 3260 | * @} |
lypinator | 0:bb348c97df44 | 3261 | */ |
lypinator | 0:bb348c97df44 | 3262 | #endif /* HAL_SPI_MODULE_ENABLED */ |
lypinator | 0:bb348c97df44 | 3263 | |
lypinator | 0:bb348c97df44 | 3264 | /** |
lypinator | 0:bb348c97df44 | 3265 | * @} |
lypinator | 0:bb348c97df44 | 3266 | */ |
lypinator | 0:bb348c97df44 | 3267 | |
lypinator | 0:bb348c97df44 | 3268 | /** |
lypinator | 0:bb348c97df44 | 3269 | * @} |
lypinator | 0:bb348c97df44 | 3270 | */ |
lypinator | 0:bb348c97df44 | 3271 | |
lypinator | 0:bb348c97df44 | 3272 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |