Initial commit
mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_i2s_ex.c@0:bb348c97df44, 2020-09-16 (annotated)
- Committer:
- lypinator
- Date:
- Wed Sep 16 01:11:49 2020 +0000
- Revision:
- 0:bb348c97df44
Added PWM
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
lypinator | 0:bb348c97df44 | 1 | /** |
lypinator | 0:bb348c97df44 | 2 | ****************************************************************************** |
lypinator | 0:bb348c97df44 | 3 | * @file stm32f4xx_hal_i2s_ex.c |
lypinator | 0:bb348c97df44 | 4 | * @author MCD Application Team |
lypinator | 0:bb348c97df44 | 5 | * @brief I2S HAL module driver. |
lypinator | 0:bb348c97df44 | 6 | * This file provides firmware functions to manage the following |
lypinator | 0:bb348c97df44 | 7 | * functionalities of I2S extension peripheral: |
lypinator | 0:bb348c97df44 | 8 | * + Extension features Functions |
lypinator | 0:bb348c97df44 | 9 | * |
lypinator | 0:bb348c97df44 | 10 | @verbatim |
lypinator | 0:bb348c97df44 | 11 | ============================================================================== |
lypinator | 0:bb348c97df44 | 12 | ##### I2S Extension features ##### |
lypinator | 0:bb348c97df44 | 13 | ============================================================================== |
lypinator | 0:bb348c97df44 | 14 | [..] |
lypinator | 0:bb348c97df44 | 15 | (#) In I2S full duplex mode, each SPI peripheral is able to manage sending and receiving |
lypinator | 0:bb348c97df44 | 16 | data simultaneously using two data lines. Each SPI peripheral has an extended block |
lypinator | 0:bb348c97df44 | 17 | called I2Sxext (i.e I2S2ext for SPI2 and I2S3ext for SPI3). |
lypinator | 0:bb348c97df44 | 18 | (#) The extension block is not a full SPI IP, it is used only as I2S slave to |
lypinator | 0:bb348c97df44 | 19 | implement full duplex mode. The extension block uses the same clock sources |
lypinator | 0:bb348c97df44 | 20 | as its master. |
lypinator | 0:bb348c97df44 | 21 | |
lypinator | 0:bb348c97df44 | 22 | (#) Both I2Sx and I2Sx_ext can be configured as transmitters or receivers. |
lypinator | 0:bb348c97df44 | 23 | |
lypinator | 0:bb348c97df44 | 24 | [..] |
lypinator | 0:bb348c97df44 | 25 | (@) Only I2Sx can deliver SCK and WS to I2Sx_ext in full duplex mode, where |
lypinator | 0:bb348c97df44 | 26 | I2Sx can be I2S2 or I2S3. |
lypinator | 0:bb348c97df44 | 27 | |
lypinator | 0:bb348c97df44 | 28 | ##### How to use this driver ##### |
lypinator | 0:bb348c97df44 | 29 | =============================================================================== |
lypinator | 0:bb348c97df44 | 30 | [..] |
lypinator | 0:bb348c97df44 | 31 | Three operation modes are available within this driver : |
lypinator | 0:bb348c97df44 | 32 | |
lypinator | 0:bb348c97df44 | 33 | *** Polling mode IO operation *** |
lypinator | 0:bb348c97df44 | 34 | ================================= |
lypinator | 0:bb348c97df44 | 35 | [..] |
lypinator | 0:bb348c97df44 | 36 | (+) Send and receive in the same time an amount of data in blocking mode using HAL_I2SEx_TransmitReceive() |
lypinator | 0:bb348c97df44 | 37 | |
lypinator | 0:bb348c97df44 | 38 | *** Interrupt mode IO operation *** |
lypinator | 0:bb348c97df44 | 39 | =================================== |
lypinator | 0:bb348c97df44 | 40 | [..] |
lypinator | 0:bb348c97df44 | 41 | (+) Send and receive in the same time an amount of data in non blocking mode using HAL_I2SEx_TransmitReceive_IT() |
lypinator | 0:bb348c97df44 | 42 | (+) At transmission/reception end of transfer HAL_I2SEx_TxRxCpltCallback is executed and user can |
lypinator | 0:bb348c97df44 | 43 | add his own code by customization of function pointer HAL_I2SEx_TxRxCpltCallback |
lypinator | 0:bb348c97df44 | 44 | (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can |
lypinator | 0:bb348c97df44 | 45 | add his own code by customization of function pointer HAL_I2S_ErrorCallback |
lypinator | 0:bb348c97df44 | 46 | |
lypinator | 0:bb348c97df44 | 47 | *** DMA mode IO operation *** |
lypinator | 0:bb348c97df44 | 48 | ============================== |
lypinator | 0:bb348c97df44 | 49 | [..] |
lypinator | 0:bb348c97df44 | 50 | (+) Send and receive an amount of data in non blocking mode (DMA) using HAL_I2SEx_TransmitReceive_DMA() |
lypinator | 0:bb348c97df44 | 51 | (+) At transmission/reception end of transfer HAL_I2SEx_TxRxCpltCallback is executed and user can |
lypinator | 0:bb348c97df44 | 52 | add his own code by customization of function pointer HAL_I2S_TxRxCpltCallback |
lypinator | 0:bb348c97df44 | 53 | (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can |
lypinator | 0:bb348c97df44 | 54 | add his own code by customization of function pointer HAL_I2S_ErrorCallback |
lypinator | 0:bb348c97df44 | 55 | @endverbatim |
lypinator | 0:bb348c97df44 | 56 | |
lypinator | 0:bb348c97df44 | 57 | Additional Figure: The Extended block uses the same clock sources as its master. |
lypinator | 0:bb348c97df44 | 58 | |
lypinator | 0:bb348c97df44 | 59 | +-----------------------+ |
lypinator | 0:bb348c97df44 | 60 | I2Sx_SCK | | |
lypinator | 0:bb348c97df44 | 61 | ----------+-->| I2Sx |------------------->I2Sx_SD(in/out) |
lypinator | 0:bb348c97df44 | 62 | +--|-->| | |
lypinator | 0:bb348c97df44 | 63 | | | +-----------------------+ |
lypinator | 0:bb348c97df44 | 64 | | | |
lypinator | 0:bb348c97df44 | 65 | I2S_WS | | |
lypinator | 0:bb348c97df44 | 66 | ------>| | |
lypinator | 0:bb348c97df44 | 67 | | | +-----------------------+ |
lypinator | 0:bb348c97df44 | 68 | | +-->| | |
lypinator | 0:bb348c97df44 | 69 | | | I2Sx_ext |------------------->I2Sx_extSD(in/out) |
lypinator | 0:bb348c97df44 | 70 | +----->| | |
lypinator | 0:bb348c97df44 | 71 | +-----------------------+ |
lypinator | 0:bb348c97df44 | 72 | ****************************************************************************** |
lypinator | 0:bb348c97df44 | 73 | * @attention |
lypinator | 0:bb348c97df44 | 74 | * |
lypinator | 0:bb348c97df44 | 75 | * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> |
lypinator | 0:bb348c97df44 | 76 | * |
lypinator | 0:bb348c97df44 | 77 | * Redistribution and use in source and binary forms, with or without modification, |
lypinator | 0:bb348c97df44 | 78 | * are permitted provided that the following conditions are met: |
lypinator | 0:bb348c97df44 | 79 | * 1. Redistributions of source code must retain the above copyright notice, |
lypinator | 0:bb348c97df44 | 80 | * this list of conditions and the following disclaimer. |
lypinator | 0:bb348c97df44 | 81 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
lypinator | 0:bb348c97df44 | 82 | * this list of conditions and the following disclaimer in the documentation |
lypinator | 0:bb348c97df44 | 83 | * and/or other materials provided with the distribution. |
lypinator | 0:bb348c97df44 | 84 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
lypinator | 0:bb348c97df44 | 85 | * may be used to endorse or promote products derived from this software |
lypinator | 0:bb348c97df44 | 86 | * without specific prior written permission. |
lypinator | 0:bb348c97df44 | 87 | * |
lypinator | 0:bb348c97df44 | 88 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
lypinator | 0:bb348c97df44 | 89 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
lypinator | 0:bb348c97df44 | 90 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
lypinator | 0:bb348c97df44 | 91 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
lypinator | 0:bb348c97df44 | 92 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
lypinator | 0:bb348c97df44 | 93 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
lypinator | 0:bb348c97df44 | 94 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
lypinator | 0:bb348c97df44 | 95 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
lypinator | 0:bb348c97df44 | 96 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
lypinator | 0:bb348c97df44 | 97 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
lypinator | 0:bb348c97df44 | 98 | * |
lypinator | 0:bb348c97df44 | 99 | ****************************************************************************** |
lypinator | 0:bb348c97df44 | 100 | */ |
lypinator | 0:bb348c97df44 | 101 | |
lypinator | 0:bb348c97df44 | 102 | /* Includes ------------------------------------------------------------------*/ |
lypinator | 0:bb348c97df44 | 103 | #include "stm32f4xx_hal.h" |
lypinator | 0:bb348c97df44 | 104 | |
lypinator | 0:bb348c97df44 | 105 | /** @addtogroup STM32F4xx_HAL_Driver |
lypinator | 0:bb348c97df44 | 106 | * @{ |
lypinator | 0:bb348c97df44 | 107 | */ |
lypinator | 0:bb348c97df44 | 108 | |
lypinator | 0:bb348c97df44 | 109 | #ifdef HAL_I2S_MODULE_ENABLED |
lypinator | 0:bb348c97df44 | 110 | |
lypinator | 0:bb348c97df44 | 111 | /** @defgroup I2SEx I2SEx |
lypinator | 0:bb348c97df44 | 112 | * @brief I2S Extended HAL module driver |
lypinator | 0:bb348c97df44 | 113 | * @{ |
lypinator | 0:bb348c97df44 | 114 | */ |
lypinator | 0:bb348c97df44 | 115 | |
lypinator | 0:bb348c97df44 | 116 | #if defined (SPI_I2S_FULLDUPLEX_SUPPORT) |
lypinator | 0:bb348c97df44 | 117 | |
lypinator | 0:bb348c97df44 | 118 | /* Private typedef -----------------------------------------------------------*/ |
lypinator | 0:bb348c97df44 | 119 | /** @defgroup I2SEx_Private_Typedef I2S Extended Private Typedef |
lypinator | 0:bb348c97df44 | 120 | * @{ |
lypinator | 0:bb348c97df44 | 121 | */ |
lypinator | 0:bb348c97df44 | 122 | typedef enum |
lypinator | 0:bb348c97df44 | 123 | { |
lypinator | 0:bb348c97df44 | 124 | I2S_USE_I2S = 0x00U, /*!< I2Sx should be used */ |
lypinator | 0:bb348c97df44 | 125 | I2S_USE_I2SEXT = 0x01U, /*!< I2Sx_ext should be used */ |
lypinator | 0:bb348c97df44 | 126 | }I2S_UseTypeDef; |
lypinator | 0:bb348c97df44 | 127 | /** |
lypinator | 0:bb348c97df44 | 128 | * @} |
lypinator | 0:bb348c97df44 | 129 | */ |
lypinator | 0:bb348c97df44 | 130 | /* Private define ------------------------------------------------------------*/ |
lypinator | 0:bb348c97df44 | 131 | /* Private macro -------------------------------------------------------------*/ |
lypinator | 0:bb348c97df44 | 132 | /* Private variables ---------------------------------------------------------*/ |
lypinator | 0:bb348c97df44 | 133 | /* Private function prototypes -----------------------------------------------*/ |
lypinator | 0:bb348c97df44 | 134 | /** @defgroup I2SEx_Private_Functions I2S Extended Private Functions |
lypinator | 0:bb348c97df44 | 135 | * @{ |
lypinator | 0:bb348c97df44 | 136 | */ |
lypinator | 0:bb348c97df44 | 137 | static void I2SEx_TxRxDMAHalfCplt(DMA_HandleTypeDef *hdma); |
lypinator | 0:bb348c97df44 | 138 | static void I2SEx_TxRxDMACplt(DMA_HandleTypeDef *hdma); |
lypinator | 0:bb348c97df44 | 139 | static void I2SEx_TxRxDMAError(DMA_HandleTypeDef *hdma); |
lypinator | 0:bb348c97df44 | 140 | static void I2SEx_FullDuplexTx_IT(I2S_HandleTypeDef *hi2s, I2S_UseTypeDef i2sUsed); |
lypinator | 0:bb348c97df44 | 141 | static void I2SEx_FullDuplexRx_IT(I2S_HandleTypeDef *hi2s, I2S_UseTypeDef i2sUsed); |
lypinator | 0:bb348c97df44 | 142 | static HAL_StatusTypeDef I2SEx_FullDuplexWaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, |
lypinator | 0:bb348c97df44 | 143 | uint32_t State, uint32_t Timeout, I2S_UseTypeDef i2sUsed); |
lypinator | 0:bb348c97df44 | 144 | /** |
lypinator | 0:bb348c97df44 | 145 | * @} |
lypinator | 0:bb348c97df44 | 146 | */ |
lypinator | 0:bb348c97df44 | 147 | |
lypinator | 0:bb348c97df44 | 148 | /** |
lypinator | 0:bb348c97df44 | 149 | * @} |
lypinator | 0:bb348c97df44 | 150 | */ |
lypinator | 0:bb348c97df44 | 151 | |
lypinator | 0:bb348c97df44 | 152 | /* Private functions ---------------------------------------------------------*/ |
lypinator | 0:bb348c97df44 | 153 | /* Exported functions --------------------------------------------------------*/ |
lypinator | 0:bb348c97df44 | 154 | |
lypinator | 0:bb348c97df44 | 155 | /** @addtogroup I2SEx I2SEx |
lypinator | 0:bb348c97df44 | 156 | * @{ |
lypinator | 0:bb348c97df44 | 157 | */ |
lypinator | 0:bb348c97df44 | 158 | |
lypinator | 0:bb348c97df44 | 159 | /** @addtogroup I2SEx_Exported_Functions I2S Extended Exported Functions |
lypinator | 0:bb348c97df44 | 160 | * @{ |
lypinator | 0:bb348c97df44 | 161 | */ |
lypinator | 0:bb348c97df44 | 162 | |
lypinator | 0:bb348c97df44 | 163 | /** @defgroup I2SEx_Exported_Functions_Group1 I2S Extended IO operation functions |
lypinator | 0:bb348c97df44 | 164 | * @brief I2SEx IO operation functions |
lypinator | 0:bb348c97df44 | 165 | * |
lypinator | 0:bb348c97df44 | 166 | @verbatim |
lypinator | 0:bb348c97df44 | 167 | =============================================================================== |
lypinator | 0:bb348c97df44 | 168 | ##### IO operation functions##### |
lypinator | 0:bb348c97df44 | 169 | =============================================================================== |
lypinator | 0:bb348c97df44 | 170 | [..] |
lypinator | 0:bb348c97df44 | 171 | This subsection provides a set of functions allowing to manage the I2S data |
lypinator | 0:bb348c97df44 | 172 | transfers. |
lypinator | 0:bb348c97df44 | 173 | |
lypinator | 0:bb348c97df44 | 174 | (#) There are two modes of transfer: |
lypinator | 0:bb348c97df44 | 175 | (++) Blocking mode : The communication is performed in the polling mode. |
lypinator | 0:bb348c97df44 | 176 | The status of all data processing is returned by the same function |
lypinator | 0:bb348c97df44 | 177 | after finishing transfer. |
lypinator | 0:bb348c97df44 | 178 | (++) No-Blocking mode : The communication is performed using Interrupts |
lypinator | 0:bb348c97df44 | 179 | or DMA. These functions return the status of the transfer startup. |
lypinator | 0:bb348c97df44 | 180 | The end of the data processing will be indicated through the |
lypinator | 0:bb348c97df44 | 181 | dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when |
lypinator | 0:bb348c97df44 | 182 | using DMA mode. |
lypinator | 0:bb348c97df44 | 183 | |
lypinator | 0:bb348c97df44 | 184 | (#) Blocking mode functions are : |
lypinator | 0:bb348c97df44 | 185 | (++) HAL_I2SEx_TransmitReceive() |
lypinator | 0:bb348c97df44 | 186 | |
lypinator | 0:bb348c97df44 | 187 | (#) No-Blocking mode functions with Interrupt are : |
lypinator | 0:bb348c97df44 | 188 | (++) HAL_I2SEx_TransmitReceive_IT() |
lypinator | 0:bb348c97df44 | 189 | (++) HAL_I2SEx_FullDuplex_IRQHandler() |
lypinator | 0:bb348c97df44 | 190 | |
lypinator | 0:bb348c97df44 | 191 | (#) No-Blocking mode functions with DMA are : |
lypinator | 0:bb348c97df44 | 192 | (++) HAL_I2SEx_TransmitReceive_DMA() |
lypinator | 0:bb348c97df44 | 193 | |
lypinator | 0:bb348c97df44 | 194 | (#) A set of Transfer Complete Callback are provided in non Blocking mode: |
lypinator | 0:bb348c97df44 | 195 | (++) HAL_I2SEx_TxRxCpltCallback() |
lypinator | 0:bb348c97df44 | 196 | @endverbatim |
lypinator | 0:bb348c97df44 | 197 | * @{ |
lypinator | 0:bb348c97df44 | 198 | */ |
lypinator | 0:bb348c97df44 | 199 | /** |
lypinator | 0:bb348c97df44 | 200 | * @brief Full-Duplex Transmit/Receive data in blocking mode. |
lypinator | 0:bb348c97df44 | 201 | * @param hi2s pointer to a I2S_HandleTypeDef structure that contains |
lypinator | 0:bb348c97df44 | 202 | * the configuration information for I2S module |
lypinator | 0:bb348c97df44 | 203 | * @param pTxData a 16-bit pointer to the Transmit data buffer. |
lypinator | 0:bb348c97df44 | 204 | * @param pRxData a 16-bit pointer to the Receive data buffer. |
lypinator | 0:bb348c97df44 | 205 | * @param Size number of data sample to be sent: |
lypinator | 0:bb348c97df44 | 206 | * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S |
lypinator | 0:bb348c97df44 | 207 | * configuration phase, the Size parameter means the number of 16-bit data length |
lypinator | 0:bb348c97df44 | 208 | * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected |
lypinator | 0:bb348c97df44 | 209 | * the Size parameter means the number of 16-bit data length. |
lypinator | 0:bb348c97df44 | 210 | * @param Timeout Timeout duration |
lypinator | 0:bb348c97df44 | 211 | * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization |
lypinator | 0:bb348c97df44 | 212 | * between Master and Slave(example: audio streaming). |
lypinator | 0:bb348c97df44 | 213 | * @retval HAL status |
lypinator | 0:bb348c97df44 | 214 | */ |
lypinator | 0:bb348c97df44 | 215 | HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, |
lypinator | 0:bb348c97df44 | 216 | uint16_t Size, uint32_t Timeout) |
lypinator | 0:bb348c97df44 | 217 | { |
lypinator | 0:bb348c97df44 | 218 | uint32_t tmp1 = 0U; |
lypinator | 0:bb348c97df44 | 219 | |
lypinator | 0:bb348c97df44 | 220 | if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0U)) |
lypinator | 0:bb348c97df44 | 221 | { |
lypinator | 0:bb348c97df44 | 222 | return HAL_ERROR; |
lypinator | 0:bb348c97df44 | 223 | } |
lypinator | 0:bb348c97df44 | 224 | |
lypinator | 0:bb348c97df44 | 225 | /* Check the I2S State */ |
lypinator | 0:bb348c97df44 | 226 | if(hi2s->State == HAL_I2S_STATE_READY) |
lypinator | 0:bb348c97df44 | 227 | { |
lypinator | 0:bb348c97df44 | 228 | tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN); |
lypinator | 0:bb348c97df44 | 229 | /* Check the Data format: When a 16-bit data frame or a 16-bit data frame extended |
lypinator | 0:bb348c97df44 | 230 | is selected during the I2S configuration phase, the Size parameter means the number |
lypinator | 0:bb348c97df44 | 231 | of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data |
lypinator | 0:bb348c97df44 | 232 | frame is selected the Size parameter means the number of 16-bit data length. */ |
lypinator | 0:bb348c97df44 | 233 | if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B)) |
lypinator | 0:bb348c97df44 | 234 | { |
lypinator | 0:bb348c97df44 | 235 | hi2s->TxXferSize = (Size << 1U); |
lypinator | 0:bb348c97df44 | 236 | hi2s->TxXferCount = (Size << 1U); |
lypinator | 0:bb348c97df44 | 237 | hi2s->RxXferSize = (Size << 1U); |
lypinator | 0:bb348c97df44 | 238 | hi2s->RxXferCount = (Size << 1U); |
lypinator | 0:bb348c97df44 | 239 | } |
lypinator | 0:bb348c97df44 | 240 | else |
lypinator | 0:bb348c97df44 | 241 | { |
lypinator | 0:bb348c97df44 | 242 | hi2s->TxXferSize = Size; |
lypinator | 0:bb348c97df44 | 243 | hi2s->TxXferCount = Size; |
lypinator | 0:bb348c97df44 | 244 | hi2s->RxXferSize = Size; |
lypinator | 0:bb348c97df44 | 245 | hi2s->RxXferCount = Size; |
lypinator | 0:bb348c97df44 | 246 | } |
lypinator | 0:bb348c97df44 | 247 | |
lypinator | 0:bb348c97df44 | 248 | /* Process Locked */ |
lypinator | 0:bb348c97df44 | 249 | __HAL_LOCK(hi2s); |
lypinator | 0:bb348c97df44 | 250 | |
lypinator | 0:bb348c97df44 | 251 | hi2s->ErrorCode = HAL_I2S_ERROR_NONE; |
lypinator | 0:bb348c97df44 | 252 | |
lypinator | 0:bb348c97df44 | 253 | /* Set the I2S State busy TX/RX */ |
lypinator | 0:bb348c97df44 | 254 | hi2s->State = HAL_I2S_STATE_BUSY_TX_RX; |
lypinator | 0:bb348c97df44 | 255 | |
lypinator | 0:bb348c97df44 | 256 | tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG; |
lypinator | 0:bb348c97df44 | 257 | /* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */ |
lypinator | 0:bb348c97df44 | 258 | if((tmp1 == I2S_MODE_MASTER_TX) || (tmp1 == I2S_MODE_SLAVE_TX)) |
lypinator | 0:bb348c97df44 | 259 | { |
lypinator | 0:bb348c97df44 | 260 | /* Prepare the First Data before enabling the I2S */ |
lypinator | 0:bb348c97df44 | 261 | hi2s->Instance->DR = (*pTxData++); |
lypinator | 0:bb348c97df44 | 262 | hi2s->TxXferCount--; |
lypinator | 0:bb348c97df44 | 263 | |
lypinator | 0:bb348c97df44 | 264 | /* Enable I2Sext(receiver) before enabling I2Sx peripheral */ |
lypinator | 0:bb348c97df44 | 265 | __HAL_I2SEXT_ENABLE(hi2s); |
lypinator | 0:bb348c97df44 | 266 | |
lypinator | 0:bb348c97df44 | 267 | /* Enable I2Sx peripheral */ |
lypinator | 0:bb348c97df44 | 268 | __HAL_I2S_ENABLE(hi2s); |
lypinator | 0:bb348c97df44 | 269 | |
lypinator | 0:bb348c97df44 | 270 | /* Check if Master Receiver mode is selected */ |
lypinator | 0:bb348c97df44 | 271 | if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_TX) |
lypinator | 0:bb348c97df44 | 272 | { |
lypinator | 0:bb348c97df44 | 273 | /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read |
lypinator | 0:bb348c97df44 | 274 | access to the SPI_SR register. */ |
lypinator | 0:bb348c97df44 | 275 | __HAL_I2SEXT_CLEAR_OVRFLAG(hi2s); |
lypinator | 0:bb348c97df44 | 276 | } |
lypinator | 0:bb348c97df44 | 277 | |
lypinator | 0:bb348c97df44 | 278 | while((hi2s->RxXferCount > 0U) || (hi2s->TxXferCount > 0U)) |
lypinator | 0:bb348c97df44 | 279 | { |
lypinator | 0:bb348c97df44 | 280 | if(hi2s->TxXferCount > 0U) |
lypinator | 0:bb348c97df44 | 281 | { |
lypinator | 0:bb348c97df44 | 282 | /* Wait until TXE flag is set */ |
lypinator | 0:bb348c97df44 | 283 | if (I2SEx_FullDuplexWaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, Timeout, I2S_USE_I2S) != HAL_OK) |
lypinator | 0:bb348c97df44 | 284 | { |
lypinator | 0:bb348c97df44 | 285 | /* Set the error code and execute error callback*/ |
lypinator | 0:bb348c97df44 | 286 | SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT); |
lypinator | 0:bb348c97df44 | 287 | HAL_I2S_ErrorCallback(hi2s); |
lypinator | 0:bb348c97df44 | 288 | return HAL_TIMEOUT; |
lypinator | 0:bb348c97df44 | 289 | } |
lypinator | 0:bb348c97df44 | 290 | /* Write Data on DR register */ |
lypinator | 0:bb348c97df44 | 291 | hi2s->Instance->DR = (*pTxData++); |
lypinator | 0:bb348c97df44 | 292 | hi2s->TxXferCount--; |
lypinator | 0:bb348c97df44 | 293 | |
lypinator | 0:bb348c97df44 | 294 | /* Check if an underrun occurs */ |
lypinator | 0:bb348c97df44 | 295 | if((__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR) == SET) && (tmp1 == I2S_MODE_SLAVE_TX)) |
lypinator | 0:bb348c97df44 | 296 | { |
lypinator | 0:bb348c97df44 | 297 | /* Clear Underrun flag */ |
lypinator | 0:bb348c97df44 | 298 | __HAL_I2S_CLEAR_UDRFLAG(hi2s); |
lypinator | 0:bb348c97df44 | 299 | |
lypinator | 0:bb348c97df44 | 300 | /* Set the I2S State ready */ |
lypinator | 0:bb348c97df44 | 301 | hi2s->State = HAL_I2S_STATE_READY; |
lypinator | 0:bb348c97df44 | 302 | |
lypinator | 0:bb348c97df44 | 303 | /* Process Unlocked */ |
lypinator | 0:bb348c97df44 | 304 | __HAL_UNLOCK(hi2s); |
lypinator | 0:bb348c97df44 | 305 | |
lypinator | 0:bb348c97df44 | 306 | /* Set the error code and execute error callback*/ |
lypinator | 0:bb348c97df44 | 307 | SET_BIT(hi2s->ErrorCode,HAL_I2S_ERROR_UDR); |
lypinator | 0:bb348c97df44 | 308 | HAL_I2S_ErrorCallback(hi2s); |
lypinator | 0:bb348c97df44 | 309 | |
lypinator | 0:bb348c97df44 | 310 | return HAL_ERROR; |
lypinator | 0:bb348c97df44 | 311 | } |
lypinator | 0:bb348c97df44 | 312 | } |
lypinator | 0:bb348c97df44 | 313 | if(hi2s->RxXferCount > 0U) |
lypinator | 0:bb348c97df44 | 314 | { |
lypinator | 0:bb348c97df44 | 315 | /* Wait until RXNE flag is set */ |
lypinator | 0:bb348c97df44 | 316 | if (I2SEx_FullDuplexWaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, SET, Timeout, I2S_USE_I2SEXT) != HAL_OK) |
lypinator | 0:bb348c97df44 | 317 | { |
lypinator | 0:bb348c97df44 | 318 | /* Set the error code and execute error callback*/ |
lypinator | 0:bb348c97df44 | 319 | SET_BIT(hi2s->ErrorCode,HAL_I2S_ERROR_TIMEOUT); |
lypinator | 0:bb348c97df44 | 320 | HAL_I2S_ErrorCallback(hi2s); |
lypinator | 0:bb348c97df44 | 321 | return HAL_TIMEOUT; |
lypinator | 0:bb348c97df44 | 322 | } |
lypinator | 0:bb348c97df44 | 323 | /* Read Data from DR register */ |
lypinator | 0:bb348c97df44 | 324 | (*pRxData++) = I2SxEXT(hi2s->Instance)->DR; |
lypinator | 0:bb348c97df44 | 325 | hi2s->RxXferCount--; |
lypinator | 0:bb348c97df44 | 326 | |
lypinator | 0:bb348c97df44 | 327 | /* Check if an overrun occurs */ |
lypinator | 0:bb348c97df44 | 328 | if(__HAL_I2SEXT_GET_FLAG(hi2s, I2S_FLAG_OVR) == SET) |
lypinator | 0:bb348c97df44 | 329 | { |
lypinator | 0:bb348c97df44 | 330 | /* Clear Overrun flag */ |
lypinator | 0:bb348c97df44 | 331 | __HAL_I2S_CLEAR_OVRFLAG(hi2s); |
lypinator | 0:bb348c97df44 | 332 | |
lypinator | 0:bb348c97df44 | 333 | /* Set the I2S State ready */ |
lypinator | 0:bb348c97df44 | 334 | hi2s->State = HAL_I2S_STATE_READY; |
lypinator | 0:bb348c97df44 | 335 | |
lypinator | 0:bb348c97df44 | 336 | /* Process Unlocked */ |
lypinator | 0:bb348c97df44 | 337 | __HAL_UNLOCK(hi2s); |
lypinator | 0:bb348c97df44 | 338 | |
lypinator | 0:bb348c97df44 | 339 | /* Set the error code and execute error callback*/ |
lypinator | 0:bb348c97df44 | 340 | SET_BIT(hi2s->ErrorCode,HAL_I2S_ERROR_OVR); |
lypinator | 0:bb348c97df44 | 341 | HAL_I2S_ErrorCallback(hi2s); |
lypinator | 0:bb348c97df44 | 342 | |
lypinator | 0:bb348c97df44 | 343 | return HAL_ERROR; |
lypinator | 0:bb348c97df44 | 344 | } |
lypinator | 0:bb348c97df44 | 345 | } |
lypinator | 0:bb348c97df44 | 346 | } |
lypinator | 0:bb348c97df44 | 347 | } |
lypinator | 0:bb348c97df44 | 348 | /* The I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX Mode is selected */ |
lypinator | 0:bb348c97df44 | 349 | else |
lypinator | 0:bb348c97df44 | 350 | { |
lypinator | 0:bb348c97df44 | 351 | /* Prepare the First Data before enabling the I2S */ |
lypinator | 0:bb348c97df44 | 352 | I2SxEXT(hi2s->Instance)->DR = (*pTxData++); |
lypinator | 0:bb348c97df44 | 353 | hi2s->TxXferCount--; |
lypinator | 0:bb348c97df44 | 354 | |
lypinator | 0:bb348c97df44 | 355 | /* Enable I2Sext(transmitter) after enabling I2Sx peripheral */ |
lypinator | 0:bb348c97df44 | 356 | __HAL_I2SEXT_ENABLE(hi2s); |
lypinator | 0:bb348c97df44 | 357 | |
lypinator | 0:bb348c97df44 | 358 | /* Enable I2S peripheral before the I2Sext*/ |
lypinator | 0:bb348c97df44 | 359 | __HAL_I2S_ENABLE(hi2s); |
lypinator | 0:bb348c97df44 | 360 | |
lypinator | 0:bb348c97df44 | 361 | /* Check if Master Receiver mode is selected */ |
lypinator | 0:bb348c97df44 | 362 | if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX) |
lypinator | 0:bb348c97df44 | 363 | { |
lypinator | 0:bb348c97df44 | 364 | /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read |
lypinator | 0:bb348c97df44 | 365 | access to the SPI_SR register. */ |
lypinator | 0:bb348c97df44 | 366 | __HAL_I2S_CLEAR_OVRFLAG(hi2s); |
lypinator | 0:bb348c97df44 | 367 | } |
lypinator | 0:bb348c97df44 | 368 | |
lypinator | 0:bb348c97df44 | 369 | while((hi2s->RxXferCount > 0U) || (hi2s->TxXferCount > 0U)) |
lypinator | 0:bb348c97df44 | 370 | { |
lypinator | 0:bb348c97df44 | 371 | if(hi2s->TxXferCount > 0U) |
lypinator | 0:bb348c97df44 | 372 | { |
lypinator | 0:bb348c97df44 | 373 | /* Wait until TXE flag is set */ |
lypinator | 0:bb348c97df44 | 374 | if (I2SEx_FullDuplexWaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, Timeout, I2S_USE_I2SEXT) != HAL_OK) |
lypinator | 0:bb348c97df44 | 375 | { |
lypinator | 0:bb348c97df44 | 376 | /* Set the error code and execute error callback*/ |
lypinator | 0:bb348c97df44 | 377 | SET_BIT(hi2s->ErrorCode,HAL_I2S_ERROR_TIMEOUT); |
lypinator | 0:bb348c97df44 | 378 | HAL_I2S_ErrorCallback(hi2s); |
lypinator | 0:bb348c97df44 | 379 | return HAL_TIMEOUT; |
lypinator | 0:bb348c97df44 | 380 | } |
lypinator | 0:bb348c97df44 | 381 | /* Write Data on DR register */ |
lypinator | 0:bb348c97df44 | 382 | I2SxEXT(hi2s->Instance)->DR = (*pTxData++); |
lypinator | 0:bb348c97df44 | 383 | hi2s->TxXferCount--; |
lypinator | 0:bb348c97df44 | 384 | |
lypinator | 0:bb348c97df44 | 385 | /* Check if an underrun occurs */ |
lypinator | 0:bb348c97df44 | 386 | if((__HAL_I2SEXT_GET_FLAG(hi2s, I2S_FLAG_UDR) == SET) && (tmp1 == I2S_MODE_SLAVE_RX)) |
lypinator | 0:bb348c97df44 | 387 | { |
lypinator | 0:bb348c97df44 | 388 | /* Clear Underrun flag */ |
lypinator | 0:bb348c97df44 | 389 | __HAL_I2S_CLEAR_UDRFLAG(hi2s); |
lypinator | 0:bb348c97df44 | 390 | |
lypinator | 0:bb348c97df44 | 391 | /* Set the I2S State ready */ |
lypinator | 0:bb348c97df44 | 392 | hi2s->State = HAL_I2S_STATE_READY; |
lypinator | 0:bb348c97df44 | 393 | |
lypinator | 0:bb348c97df44 | 394 | /* Process Unlocked */ |
lypinator | 0:bb348c97df44 | 395 | __HAL_UNLOCK(hi2s); |
lypinator | 0:bb348c97df44 | 396 | |
lypinator | 0:bb348c97df44 | 397 | /* Set the error code and execute error callback*/ |
lypinator | 0:bb348c97df44 | 398 | SET_BIT(hi2s->ErrorCode,HAL_I2S_ERROR_UDR); |
lypinator | 0:bb348c97df44 | 399 | HAL_I2S_ErrorCallback(hi2s); |
lypinator | 0:bb348c97df44 | 400 | |
lypinator | 0:bb348c97df44 | 401 | return HAL_ERROR; |
lypinator | 0:bb348c97df44 | 402 | } |
lypinator | 0:bb348c97df44 | 403 | } |
lypinator | 0:bb348c97df44 | 404 | if(hi2s->RxXferCount > 0U) |
lypinator | 0:bb348c97df44 | 405 | { |
lypinator | 0:bb348c97df44 | 406 | /* Wait until RXNE flag is set */ |
lypinator | 0:bb348c97df44 | 407 | if (I2SEx_FullDuplexWaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, SET, Timeout, I2S_USE_I2S) != HAL_OK) |
lypinator | 0:bb348c97df44 | 408 | { |
lypinator | 0:bb348c97df44 | 409 | /* Set the error code and execute error callback*/ |
lypinator | 0:bb348c97df44 | 410 | SET_BIT(hi2s->ErrorCode,HAL_I2S_ERROR_TIMEOUT); |
lypinator | 0:bb348c97df44 | 411 | HAL_I2S_ErrorCallback(hi2s); |
lypinator | 0:bb348c97df44 | 412 | return HAL_TIMEOUT; |
lypinator | 0:bb348c97df44 | 413 | } |
lypinator | 0:bb348c97df44 | 414 | /* Read Data from DR register */ |
lypinator | 0:bb348c97df44 | 415 | (*pRxData++) = hi2s->Instance->DR; |
lypinator | 0:bb348c97df44 | 416 | hi2s->RxXferCount--; |
lypinator | 0:bb348c97df44 | 417 | |
lypinator | 0:bb348c97df44 | 418 | /* Check if an overrun occurs */ |
lypinator | 0:bb348c97df44 | 419 | if(__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR) == SET) |
lypinator | 0:bb348c97df44 | 420 | { |
lypinator | 0:bb348c97df44 | 421 | /* Clear Overrun flag */ |
lypinator | 0:bb348c97df44 | 422 | __HAL_I2S_CLEAR_OVRFLAG(hi2s); |
lypinator | 0:bb348c97df44 | 423 | |
lypinator | 0:bb348c97df44 | 424 | /* Set the I2S State ready */ |
lypinator | 0:bb348c97df44 | 425 | hi2s->State = HAL_I2S_STATE_READY; |
lypinator | 0:bb348c97df44 | 426 | |
lypinator | 0:bb348c97df44 | 427 | /* Process Unlocked */ |
lypinator | 0:bb348c97df44 | 428 | __HAL_UNLOCK(hi2s); |
lypinator | 0:bb348c97df44 | 429 | |
lypinator | 0:bb348c97df44 | 430 | /* Set the error code and execute error callback*/ |
lypinator | 0:bb348c97df44 | 431 | SET_BIT(hi2s->ErrorCode,HAL_I2S_ERROR_OVR); |
lypinator | 0:bb348c97df44 | 432 | HAL_I2S_ErrorCallback(hi2s); |
lypinator | 0:bb348c97df44 | 433 | |
lypinator | 0:bb348c97df44 | 434 | return HAL_ERROR; |
lypinator | 0:bb348c97df44 | 435 | } |
lypinator | 0:bb348c97df44 | 436 | } |
lypinator | 0:bb348c97df44 | 437 | } |
lypinator | 0:bb348c97df44 | 438 | } |
lypinator | 0:bb348c97df44 | 439 | |
lypinator | 0:bb348c97df44 | 440 | /* Set the I2S State ready */ |
lypinator | 0:bb348c97df44 | 441 | hi2s->State = HAL_I2S_STATE_READY; |
lypinator | 0:bb348c97df44 | 442 | |
lypinator | 0:bb348c97df44 | 443 | /* Process Unlocked */ |
lypinator | 0:bb348c97df44 | 444 | __HAL_UNLOCK(hi2s); |
lypinator | 0:bb348c97df44 | 445 | |
lypinator | 0:bb348c97df44 | 446 | return HAL_OK; |
lypinator | 0:bb348c97df44 | 447 | } |
lypinator | 0:bb348c97df44 | 448 | else |
lypinator | 0:bb348c97df44 | 449 | { |
lypinator | 0:bb348c97df44 | 450 | return HAL_BUSY; |
lypinator | 0:bb348c97df44 | 451 | } |
lypinator | 0:bb348c97df44 | 452 | } |
lypinator | 0:bb348c97df44 | 453 | |
lypinator | 0:bb348c97df44 | 454 | /** |
lypinator | 0:bb348c97df44 | 455 | * @brief Full-Duplex Transmit/Receive data in non-blocking mode using Interrupt |
lypinator | 0:bb348c97df44 | 456 | * @param hi2s pointer to a I2S_HandleTypeDef structure that contains |
lypinator | 0:bb348c97df44 | 457 | * the configuration information for I2S module |
lypinator | 0:bb348c97df44 | 458 | * @param pTxData a 16-bit pointer to the Transmit data buffer. |
lypinator | 0:bb348c97df44 | 459 | * @param pRxData a 16-bit pointer to the Receive data buffer. |
lypinator | 0:bb348c97df44 | 460 | * @param Size number of data sample to be sent: |
lypinator | 0:bb348c97df44 | 461 | * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S |
lypinator | 0:bb348c97df44 | 462 | * configuration phase, the Size parameter means the number of 16-bit data length |
lypinator | 0:bb348c97df44 | 463 | * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected |
lypinator | 0:bb348c97df44 | 464 | * the Size parameter means the number of 16-bit data length. |
lypinator | 0:bb348c97df44 | 465 | * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization |
lypinator | 0:bb348c97df44 | 466 | * between Master and Slave(example: audio streaming). |
lypinator | 0:bb348c97df44 | 467 | * @retval HAL status |
lypinator | 0:bb348c97df44 | 468 | */ |
lypinator | 0:bb348c97df44 | 469 | HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, |
lypinator | 0:bb348c97df44 | 470 | uint16_t Size) |
lypinator | 0:bb348c97df44 | 471 | { |
lypinator | 0:bb348c97df44 | 472 | uint32_t tmp1 = 0U; |
lypinator | 0:bb348c97df44 | 473 | |
lypinator | 0:bb348c97df44 | 474 | if(hi2s->State == HAL_I2S_STATE_READY) |
lypinator | 0:bb348c97df44 | 475 | { |
lypinator | 0:bb348c97df44 | 476 | if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0U)) |
lypinator | 0:bb348c97df44 | 477 | { |
lypinator | 0:bb348c97df44 | 478 | return HAL_ERROR; |
lypinator | 0:bb348c97df44 | 479 | } |
lypinator | 0:bb348c97df44 | 480 | |
lypinator | 0:bb348c97df44 | 481 | hi2s->pTxBuffPtr = pTxData; |
lypinator | 0:bb348c97df44 | 482 | hi2s->pRxBuffPtr = pRxData; |
lypinator | 0:bb348c97df44 | 483 | |
lypinator | 0:bb348c97df44 | 484 | tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN); |
lypinator | 0:bb348c97df44 | 485 | /* Check the Data format: When a 16-bit data frame or a 16-bit data frame extended |
lypinator | 0:bb348c97df44 | 486 | is selected during the I2S configuration phase, the Size parameter means the number |
lypinator | 0:bb348c97df44 | 487 | of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data |
lypinator | 0:bb348c97df44 | 488 | frame is selected the Size parameter means the number of 16-bit data length. */ |
lypinator | 0:bb348c97df44 | 489 | if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B)) |
lypinator | 0:bb348c97df44 | 490 | { |
lypinator | 0:bb348c97df44 | 491 | hi2s->TxXferSize = (Size << 1U); |
lypinator | 0:bb348c97df44 | 492 | hi2s->TxXferCount = (Size << 1U); |
lypinator | 0:bb348c97df44 | 493 | hi2s->RxXferSize = (Size << 1U); |
lypinator | 0:bb348c97df44 | 494 | hi2s->RxXferCount = (Size << 1U); |
lypinator | 0:bb348c97df44 | 495 | } |
lypinator | 0:bb348c97df44 | 496 | else |
lypinator | 0:bb348c97df44 | 497 | { |
lypinator | 0:bb348c97df44 | 498 | hi2s->TxXferSize = Size; |
lypinator | 0:bb348c97df44 | 499 | hi2s->TxXferCount = Size; |
lypinator | 0:bb348c97df44 | 500 | hi2s->RxXferSize = Size; |
lypinator | 0:bb348c97df44 | 501 | hi2s->RxXferCount = Size; |
lypinator | 0:bb348c97df44 | 502 | } |
lypinator | 0:bb348c97df44 | 503 | |
lypinator | 0:bb348c97df44 | 504 | /* Process Locked */ |
lypinator | 0:bb348c97df44 | 505 | __HAL_LOCK(hi2s); |
lypinator | 0:bb348c97df44 | 506 | |
lypinator | 0:bb348c97df44 | 507 | hi2s->ErrorCode = HAL_I2S_ERROR_NONE; |
lypinator | 0:bb348c97df44 | 508 | hi2s->State = HAL_I2S_STATE_BUSY_TX_RX; |
lypinator | 0:bb348c97df44 | 509 | |
lypinator | 0:bb348c97df44 | 510 | tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG; |
lypinator | 0:bb348c97df44 | 511 | /* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */ |
lypinator | 0:bb348c97df44 | 512 | if((tmp1 == I2S_MODE_MASTER_TX) || (tmp1 == I2S_MODE_SLAVE_TX)) |
lypinator | 0:bb348c97df44 | 513 | { |
lypinator | 0:bb348c97df44 | 514 | /* Enable I2Sext RXNE and ERR interrupts */ |
lypinator | 0:bb348c97df44 | 515 | __HAL_I2SEXT_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR)); |
lypinator | 0:bb348c97df44 | 516 | |
lypinator | 0:bb348c97df44 | 517 | /* Enable I2Sx TXE and ERR interrupts */ |
lypinator | 0:bb348c97df44 | 518 | __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR)); |
lypinator | 0:bb348c97df44 | 519 | |
lypinator | 0:bb348c97df44 | 520 | /* Check if the I2S is already enabled */ |
lypinator | 0:bb348c97df44 | 521 | if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE) |
lypinator | 0:bb348c97df44 | 522 | { |
lypinator | 0:bb348c97df44 | 523 | if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX) |
lypinator | 0:bb348c97df44 | 524 | { |
lypinator | 0:bb348c97df44 | 525 | /* Prepare the First Data before enabling the I2S */ |
lypinator | 0:bb348c97df44 | 526 | if(hi2s->TxXferCount != 0U) |
lypinator | 0:bb348c97df44 | 527 | { |
lypinator | 0:bb348c97df44 | 528 | /* Transmit First data */ |
lypinator | 0:bb348c97df44 | 529 | hi2s->Instance->DR = (*hi2s->pTxBuffPtr++); |
lypinator | 0:bb348c97df44 | 530 | hi2s->TxXferCount--; |
lypinator | 0:bb348c97df44 | 531 | |
lypinator | 0:bb348c97df44 | 532 | if(hi2s->TxXferCount == 0U) |
lypinator | 0:bb348c97df44 | 533 | { |
lypinator | 0:bb348c97df44 | 534 | /* Disable TXE and ERR interrupt */ |
lypinator | 0:bb348c97df44 | 535 | __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR)); |
lypinator | 0:bb348c97df44 | 536 | |
lypinator | 0:bb348c97df44 | 537 | if(hi2s->RxXferCount == 0U) |
lypinator | 0:bb348c97df44 | 538 | { |
lypinator | 0:bb348c97df44 | 539 | /* Disable I2Sext RXNE and ERR interrupt */ |
lypinator | 0:bb348c97df44 | 540 | __HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_RXNE| I2S_IT_ERR)); |
lypinator | 0:bb348c97df44 | 541 | |
lypinator | 0:bb348c97df44 | 542 | hi2s->State = HAL_I2S_STATE_READY; |
lypinator | 0:bb348c97df44 | 543 | HAL_I2SEx_TxRxCpltCallback(hi2s); |
lypinator | 0:bb348c97df44 | 544 | } |
lypinator | 0:bb348c97df44 | 545 | } |
lypinator | 0:bb348c97df44 | 546 | } |
lypinator | 0:bb348c97df44 | 547 | } |
lypinator | 0:bb348c97df44 | 548 | /* Enable I2Sext(receiver) before enabling I2Sx peripheral */ |
lypinator | 0:bb348c97df44 | 549 | __HAL_I2SEXT_ENABLE(hi2s); |
lypinator | 0:bb348c97df44 | 550 | |
lypinator | 0:bb348c97df44 | 551 | /* Enable I2Sx peripheral */ |
lypinator | 0:bb348c97df44 | 552 | __HAL_I2S_ENABLE(hi2s); |
lypinator | 0:bb348c97df44 | 553 | } |
lypinator | 0:bb348c97df44 | 554 | } |
lypinator | 0:bb348c97df44 | 555 | /* The I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX Mode is selected */ |
lypinator | 0:bb348c97df44 | 556 | else |
lypinator | 0:bb348c97df44 | 557 | { |
lypinator | 0:bb348c97df44 | 558 | /* Enable I2Sext TXE and ERR interrupts */ |
lypinator | 0:bb348c97df44 | 559 | __HAL_I2SEXT_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR)); |
lypinator | 0:bb348c97df44 | 560 | |
lypinator | 0:bb348c97df44 | 561 | /* Enable I2Sext RXNE and ERR interrupts */ |
lypinator | 0:bb348c97df44 | 562 | __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR)); |
lypinator | 0:bb348c97df44 | 563 | |
lypinator | 0:bb348c97df44 | 564 | /* Check if the I2S is already enabled */ |
lypinator | 0:bb348c97df44 | 565 | if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE) |
lypinator | 0:bb348c97df44 | 566 | { |
lypinator | 0:bb348c97df44 | 567 | /* Check if the I2S_MODE_MASTER_RX is selected */ |
lypinator | 0:bb348c97df44 | 568 | if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX) |
lypinator | 0:bb348c97df44 | 569 | { |
lypinator | 0:bb348c97df44 | 570 | /* Prepare the First Data before enabling the I2S */ |
lypinator | 0:bb348c97df44 | 571 | if(hi2s->TxXferCount != 0U) |
lypinator | 0:bb348c97df44 | 572 | { |
lypinator | 0:bb348c97df44 | 573 | /* Transmit First data */ |
lypinator | 0:bb348c97df44 | 574 | I2SxEXT(hi2s->Instance)->DR = (*hi2s->pTxBuffPtr++); |
lypinator | 0:bb348c97df44 | 575 | hi2s->TxXferCount--; |
lypinator | 0:bb348c97df44 | 576 | |
lypinator | 0:bb348c97df44 | 577 | if(hi2s->TxXferCount == 0U) |
lypinator | 0:bb348c97df44 | 578 | { |
lypinator | 0:bb348c97df44 | 579 | /* Disable I2Sext TXE and ERR interrupt */ |
lypinator | 0:bb348c97df44 | 580 | __HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR)); |
lypinator | 0:bb348c97df44 | 581 | if(hi2s->RxXferCount == 0U) |
lypinator | 0:bb348c97df44 | 582 | { |
lypinator | 0:bb348c97df44 | 583 | /* Disable RXNE and ERR interrupt */ |
lypinator | 0:bb348c97df44 | 584 | __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE| I2S_IT_ERR)); |
lypinator | 0:bb348c97df44 | 585 | |
lypinator | 0:bb348c97df44 | 586 | hi2s->State = HAL_I2S_STATE_READY; |
lypinator | 0:bb348c97df44 | 587 | HAL_I2SEx_TxRxCpltCallback(hi2s); |
lypinator | 0:bb348c97df44 | 588 | } |
lypinator | 0:bb348c97df44 | 589 | } |
lypinator | 0:bb348c97df44 | 590 | } |
lypinator | 0:bb348c97df44 | 591 | } |
lypinator | 0:bb348c97df44 | 592 | /* Enable I2Sext(transmitter) after enabling I2Sx peripheral */ |
lypinator | 0:bb348c97df44 | 593 | __HAL_I2SEXT_ENABLE(hi2s); |
lypinator | 0:bb348c97df44 | 594 | |
lypinator | 0:bb348c97df44 | 595 | /* Enable I2S peripheral */ |
lypinator | 0:bb348c97df44 | 596 | __HAL_I2S_ENABLE(hi2s); |
lypinator | 0:bb348c97df44 | 597 | } |
lypinator | 0:bb348c97df44 | 598 | } |
lypinator | 0:bb348c97df44 | 599 | /* Process Unlocked */ |
lypinator | 0:bb348c97df44 | 600 | __HAL_UNLOCK(hi2s); |
lypinator | 0:bb348c97df44 | 601 | |
lypinator | 0:bb348c97df44 | 602 | return HAL_OK; |
lypinator | 0:bb348c97df44 | 603 | } |
lypinator | 0:bb348c97df44 | 604 | else |
lypinator | 0:bb348c97df44 | 605 | { |
lypinator | 0:bb348c97df44 | 606 | return HAL_BUSY; |
lypinator | 0:bb348c97df44 | 607 | } |
lypinator | 0:bb348c97df44 | 608 | } |
lypinator | 0:bb348c97df44 | 609 | |
lypinator | 0:bb348c97df44 | 610 | /** |
lypinator | 0:bb348c97df44 | 611 | * @brief Full-Duplex Transmit/Receive data in non-blocking mode using DMA |
lypinator | 0:bb348c97df44 | 612 | * @param hi2s pointer to a I2S_HandleTypeDef structure that contains |
lypinator | 0:bb348c97df44 | 613 | * the configuration information for I2S module |
lypinator | 0:bb348c97df44 | 614 | * @param pTxData a 16-bit pointer to the Transmit data buffer. |
lypinator | 0:bb348c97df44 | 615 | * @param pRxData a 16-bit pointer to the Receive data buffer. |
lypinator | 0:bb348c97df44 | 616 | * @param Size number of data sample to be sent: |
lypinator | 0:bb348c97df44 | 617 | * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S |
lypinator | 0:bb348c97df44 | 618 | * configuration phase, the Size parameter means the number of 16-bit data length |
lypinator | 0:bb348c97df44 | 619 | * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected |
lypinator | 0:bb348c97df44 | 620 | * the Size parameter means the number of 16-bit data length. |
lypinator | 0:bb348c97df44 | 621 | * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization |
lypinator | 0:bb348c97df44 | 622 | * between Master and Slave(example: audio streaming). |
lypinator | 0:bb348c97df44 | 623 | * @retval HAL status |
lypinator | 0:bb348c97df44 | 624 | */ |
lypinator | 0:bb348c97df44 | 625 | HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, |
lypinator | 0:bb348c97df44 | 626 | uint16_t Size) |
lypinator | 0:bb348c97df44 | 627 | { |
lypinator | 0:bb348c97df44 | 628 | uint32_t *tmp = NULL; |
lypinator | 0:bb348c97df44 | 629 | uint32_t tmp1 = 0U; |
lypinator | 0:bb348c97df44 | 630 | |
lypinator | 0:bb348c97df44 | 631 | if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0U)) |
lypinator | 0:bb348c97df44 | 632 | { |
lypinator | 0:bb348c97df44 | 633 | return HAL_ERROR; |
lypinator | 0:bb348c97df44 | 634 | } |
lypinator | 0:bb348c97df44 | 635 | |
lypinator | 0:bb348c97df44 | 636 | if(hi2s->State == HAL_I2S_STATE_READY) |
lypinator | 0:bb348c97df44 | 637 | { |
lypinator | 0:bb348c97df44 | 638 | hi2s->pTxBuffPtr = pTxData; |
lypinator | 0:bb348c97df44 | 639 | hi2s->pRxBuffPtr = pRxData; |
lypinator | 0:bb348c97df44 | 640 | |
lypinator | 0:bb348c97df44 | 641 | tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN); |
lypinator | 0:bb348c97df44 | 642 | /* Check the Data format: When a 16-bit data frame or a 16-bit data frame extended |
lypinator | 0:bb348c97df44 | 643 | is selected during the I2S configuration phase, the Size parameter means the number |
lypinator | 0:bb348c97df44 | 644 | of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data |
lypinator | 0:bb348c97df44 | 645 | frame is selected the Size parameter means the number of 16-bit data length. */ |
lypinator | 0:bb348c97df44 | 646 | if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B)) |
lypinator | 0:bb348c97df44 | 647 | { |
lypinator | 0:bb348c97df44 | 648 | hi2s->TxXferSize = (Size << 1U); |
lypinator | 0:bb348c97df44 | 649 | hi2s->TxXferCount = (Size << 1U); |
lypinator | 0:bb348c97df44 | 650 | hi2s->RxXferSize = (Size << 1U); |
lypinator | 0:bb348c97df44 | 651 | hi2s->RxXferCount = (Size << 1U); |
lypinator | 0:bb348c97df44 | 652 | } |
lypinator | 0:bb348c97df44 | 653 | else |
lypinator | 0:bb348c97df44 | 654 | { |
lypinator | 0:bb348c97df44 | 655 | hi2s->TxXferSize = Size; |
lypinator | 0:bb348c97df44 | 656 | hi2s->TxXferCount = Size; |
lypinator | 0:bb348c97df44 | 657 | hi2s->RxXferSize = Size; |
lypinator | 0:bb348c97df44 | 658 | hi2s->RxXferCount = Size; |
lypinator | 0:bb348c97df44 | 659 | } |
lypinator | 0:bb348c97df44 | 660 | |
lypinator | 0:bb348c97df44 | 661 | /* Process Locked */ |
lypinator | 0:bb348c97df44 | 662 | __HAL_LOCK(hi2s); |
lypinator | 0:bb348c97df44 | 663 | |
lypinator | 0:bb348c97df44 | 664 | hi2s->ErrorCode = HAL_I2S_ERROR_NONE; |
lypinator | 0:bb348c97df44 | 665 | hi2s->State = HAL_I2S_STATE_BUSY_TX_RX; |
lypinator | 0:bb348c97df44 | 666 | |
lypinator | 0:bb348c97df44 | 667 | /* Set the I2S Rx DMA Half transfer complete callback */ |
lypinator | 0:bb348c97df44 | 668 | hi2s->hdmarx->XferHalfCpltCallback = I2SEx_TxRxDMAHalfCplt; |
lypinator | 0:bb348c97df44 | 669 | |
lypinator | 0:bb348c97df44 | 670 | /* Set the I2S Rx DMA transfer complete callback */ |
lypinator | 0:bb348c97df44 | 671 | hi2s->hdmarx->XferCpltCallback = I2SEx_TxRxDMACplt; |
lypinator | 0:bb348c97df44 | 672 | |
lypinator | 0:bb348c97df44 | 673 | /* Set the I2S Rx DMA error callback */ |
lypinator | 0:bb348c97df44 | 674 | hi2s->hdmarx->XferErrorCallback = I2SEx_TxRxDMAError; |
lypinator | 0:bb348c97df44 | 675 | |
lypinator | 0:bb348c97df44 | 676 | /* Set the I2S Tx DMA Half transfer complete callback */ |
lypinator | 0:bb348c97df44 | 677 | hi2s->hdmatx->XferHalfCpltCallback = I2SEx_TxRxDMAHalfCplt; |
lypinator | 0:bb348c97df44 | 678 | |
lypinator | 0:bb348c97df44 | 679 | /* Set the I2S Tx DMA transfer complete callback */ |
lypinator | 0:bb348c97df44 | 680 | hi2s->hdmatx->XferCpltCallback = I2SEx_TxRxDMACplt; |
lypinator | 0:bb348c97df44 | 681 | |
lypinator | 0:bb348c97df44 | 682 | /* Set the I2S Tx DMA error callback */ |
lypinator | 0:bb348c97df44 | 683 | hi2s->hdmatx->XferErrorCallback = I2SEx_TxRxDMAError; |
lypinator | 0:bb348c97df44 | 684 | |
lypinator | 0:bb348c97df44 | 685 | tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG; |
lypinator | 0:bb348c97df44 | 686 | /* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */ |
lypinator | 0:bb348c97df44 | 687 | if((tmp1 == I2S_MODE_MASTER_TX) || (tmp1 == I2S_MODE_SLAVE_TX)) |
lypinator | 0:bb348c97df44 | 688 | { |
lypinator | 0:bb348c97df44 | 689 | /* Enable the Rx DMA Stream */ |
lypinator | 0:bb348c97df44 | 690 | tmp = (uint32_t*)&pRxData; |
lypinator | 0:bb348c97df44 | 691 | HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&I2SxEXT(hi2s->Instance)->DR, *(uint32_t*)tmp, hi2s->RxXferSize); |
lypinator | 0:bb348c97df44 | 692 | |
lypinator | 0:bb348c97df44 | 693 | /* Enable Rx DMA Request */ |
lypinator | 0:bb348c97df44 | 694 | SET_BIT(I2SxEXT(hi2s->Instance)->CR2,SPI_CR2_RXDMAEN); |
lypinator | 0:bb348c97df44 | 695 | |
lypinator | 0:bb348c97df44 | 696 | /* Enable the Tx DMA Stream */ |
lypinator | 0:bb348c97df44 | 697 | tmp = (uint32_t*)&pTxData; |
lypinator | 0:bb348c97df44 | 698 | HAL_DMA_Start_IT(hi2s->hdmatx, *(uint32_t*)tmp, (uint32_t)&hi2s->Instance->DR, hi2s->TxXferSize); |
lypinator | 0:bb348c97df44 | 699 | |
lypinator | 0:bb348c97df44 | 700 | /* Enable Tx DMA Request */ |
lypinator | 0:bb348c97df44 | 701 | SET_BIT(hi2s->Instance->CR2,SPI_CR2_TXDMAEN); |
lypinator | 0:bb348c97df44 | 702 | |
lypinator | 0:bb348c97df44 | 703 | /* Check if the I2S is already enabled */ |
lypinator | 0:bb348c97df44 | 704 | if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE) |
lypinator | 0:bb348c97df44 | 705 | { |
lypinator | 0:bb348c97df44 | 706 | /* Enable I2Sext(receiver) before enabling I2Sx peripheral */ |
lypinator | 0:bb348c97df44 | 707 | __HAL_I2SEXT_ENABLE(hi2s); |
lypinator | 0:bb348c97df44 | 708 | |
lypinator | 0:bb348c97df44 | 709 | /* Enable I2S peripheral after the I2Sext */ |
lypinator | 0:bb348c97df44 | 710 | __HAL_I2S_ENABLE(hi2s); |
lypinator | 0:bb348c97df44 | 711 | } |
lypinator | 0:bb348c97df44 | 712 | } |
lypinator | 0:bb348c97df44 | 713 | else |
lypinator | 0:bb348c97df44 | 714 | { |
lypinator | 0:bb348c97df44 | 715 | /* Check if Master Receiver mode is selected */ |
lypinator | 0:bb348c97df44 | 716 | if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX) |
lypinator | 0:bb348c97df44 | 717 | { |
lypinator | 0:bb348c97df44 | 718 | /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read |
lypinator | 0:bb348c97df44 | 719 | access to the SPI_SR register. */ |
lypinator | 0:bb348c97df44 | 720 | __HAL_I2S_CLEAR_OVRFLAG(hi2s); |
lypinator | 0:bb348c97df44 | 721 | } |
lypinator | 0:bb348c97df44 | 722 | /* Enable the Tx DMA Stream */ |
lypinator | 0:bb348c97df44 | 723 | tmp = (uint32_t*)&pTxData; |
lypinator | 0:bb348c97df44 | 724 | HAL_DMA_Start_IT(hi2s->hdmatx, *(uint32_t*)tmp, (uint32_t)&I2SxEXT(hi2s->Instance)->DR, hi2s->TxXferSize); |
lypinator | 0:bb348c97df44 | 725 | |
lypinator | 0:bb348c97df44 | 726 | /* Enable Tx DMA Request */ |
lypinator | 0:bb348c97df44 | 727 | SET_BIT(I2SxEXT(hi2s->Instance)->CR2,SPI_CR2_TXDMAEN); |
lypinator | 0:bb348c97df44 | 728 | |
lypinator | 0:bb348c97df44 | 729 | /* Enable the Rx DMA Stream */ |
lypinator | 0:bb348c97df44 | 730 | tmp = (uint32_t*)&pRxData; |
lypinator | 0:bb348c97df44 | 731 | HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, *(uint32_t*)tmp, hi2s->RxXferSize); |
lypinator | 0:bb348c97df44 | 732 | |
lypinator | 0:bb348c97df44 | 733 | /* Enable Rx DMA Request */ |
lypinator | 0:bb348c97df44 | 734 | SET_BIT(hi2s->Instance->CR2,SPI_CR2_RXDMAEN); |
lypinator | 0:bb348c97df44 | 735 | |
lypinator | 0:bb348c97df44 | 736 | /* Check if the I2S is already enabled */ |
lypinator | 0:bb348c97df44 | 737 | if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE) |
lypinator | 0:bb348c97df44 | 738 | { |
lypinator | 0:bb348c97df44 | 739 | /* Enable I2Sext(transmitter) before enabling I2Sx peripheral */ |
lypinator | 0:bb348c97df44 | 740 | __HAL_I2SEXT_ENABLE(hi2s); |
lypinator | 0:bb348c97df44 | 741 | /* Enable I2S peripheral before the I2Sext */ |
lypinator | 0:bb348c97df44 | 742 | __HAL_I2S_ENABLE(hi2s); |
lypinator | 0:bb348c97df44 | 743 | } |
lypinator | 0:bb348c97df44 | 744 | } |
lypinator | 0:bb348c97df44 | 745 | |
lypinator | 0:bb348c97df44 | 746 | /* Process Unlocked */ |
lypinator | 0:bb348c97df44 | 747 | __HAL_UNLOCK(hi2s); |
lypinator | 0:bb348c97df44 | 748 | |
lypinator | 0:bb348c97df44 | 749 | return HAL_OK; |
lypinator | 0:bb348c97df44 | 750 | } |
lypinator | 0:bb348c97df44 | 751 | else |
lypinator | 0:bb348c97df44 | 752 | { |
lypinator | 0:bb348c97df44 | 753 | return HAL_BUSY; |
lypinator | 0:bb348c97df44 | 754 | } |
lypinator | 0:bb348c97df44 | 755 | } |
lypinator | 0:bb348c97df44 | 756 | |
lypinator | 0:bb348c97df44 | 757 | /** |
lypinator | 0:bb348c97df44 | 758 | * @brief This function handles I2S/I2Sext interrupt requests in full-duplex mode. |
lypinator | 0:bb348c97df44 | 759 | * @param hi2s I2S handle |
lypinator | 0:bb348c97df44 | 760 | * @retval HAL status |
lypinator | 0:bb348c97df44 | 761 | */ |
lypinator | 0:bb348c97df44 | 762 | void HAL_I2SEx_FullDuplex_IRQHandler(I2S_HandleTypeDef *hi2s) |
lypinator | 0:bb348c97df44 | 763 | { |
lypinator | 0:bb348c97df44 | 764 | __IO uint32_t i2ssr = hi2s->Instance->SR ; |
lypinator | 0:bb348c97df44 | 765 | __IO uint32_t i2sextsr = I2SxEXT(hi2s->Instance)->SR; |
lypinator | 0:bb348c97df44 | 766 | |
lypinator | 0:bb348c97df44 | 767 | /* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */ |
lypinator | 0:bb348c97df44 | 768 | if (((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_TX) |
lypinator | 0:bb348c97df44 | 769 | || ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX)) |
lypinator | 0:bb348c97df44 | 770 | { |
lypinator | 0:bb348c97df44 | 771 | /* I2S in mode Transmitter -------------------------------------------------*/ |
lypinator | 0:bb348c97df44 | 772 | if(((i2ssr & I2S_FLAG_TXE) == I2S_FLAG_TXE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_TXE) != RESET)) |
lypinator | 0:bb348c97df44 | 773 | { |
lypinator | 0:bb348c97df44 | 774 | /* When the I2S mode is configured as I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX, |
lypinator | 0:bb348c97df44 | 775 | the I2S TXE interrupt will be generated to manage the full-duplex transmit phase. */ |
lypinator | 0:bb348c97df44 | 776 | I2SEx_FullDuplexTx_IT(hi2s, I2S_USE_I2S); |
lypinator | 0:bb348c97df44 | 777 | } |
lypinator | 0:bb348c97df44 | 778 | |
lypinator | 0:bb348c97df44 | 779 | /* I2Sext in mode Receiver -----------------------------------------------*/ |
lypinator | 0:bb348c97df44 | 780 | if(((i2sextsr & I2S_FLAG_RXNE) == I2S_FLAG_RXNE) && (__HAL_I2SEXT_GET_IT_SOURCE(hi2s, I2S_IT_RXNE) != RESET)) |
lypinator | 0:bb348c97df44 | 781 | { |
lypinator | 0:bb348c97df44 | 782 | /* When the I2S mode is configured as I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX, |
lypinator | 0:bb348c97df44 | 783 | the I2Sext RXNE interrupt will be generated to manage the full-duplex receive phase. */ |
lypinator | 0:bb348c97df44 | 784 | I2SEx_FullDuplexRx_IT(hi2s, I2S_USE_I2SEXT); |
lypinator | 0:bb348c97df44 | 785 | } |
lypinator | 0:bb348c97df44 | 786 | |
lypinator | 0:bb348c97df44 | 787 | /* I2Sext Overrun error interrupt occured --------------------------------*/ |
lypinator | 0:bb348c97df44 | 788 | if(((i2sextsr & I2S_FLAG_OVR) == I2S_FLAG_OVR) && (__HAL_I2SEXT_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET)) |
lypinator | 0:bb348c97df44 | 789 | { |
lypinator | 0:bb348c97df44 | 790 | /* Disable RXNE and ERR interrupt */ |
lypinator | 0:bb348c97df44 | 791 | __HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR)); |
lypinator | 0:bb348c97df44 | 792 | |
lypinator | 0:bb348c97df44 | 793 | /* Disable TXE and ERR interrupt */ |
lypinator | 0:bb348c97df44 | 794 | __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR)); |
lypinator | 0:bb348c97df44 | 795 | |
lypinator | 0:bb348c97df44 | 796 | /* Clear Overrun flag */ |
lypinator | 0:bb348c97df44 | 797 | __HAL_I2S_CLEAR_OVRFLAG(hi2s); |
lypinator | 0:bb348c97df44 | 798 | |
lypinator | 0:bb348c97df44 | 799 | /* Set the I2S State ready */ |
lypinator | 0:bb348c97df44 | 800 | hi2s->State = HAL_I2S_STATE_READY; |
lypinator | 0:bb348c97df44 | 801 | |
lypinator | 0:bb348c97df44 | 802 | /* Set the error code and execute error callback*/ |
lypinator | 0:bb348c97df44 | 803 | SET_BIT(hi2s->ErrorCode,HAL_I2S_ERROR_OVR); |
lypinator | 0:bb348c97df44 | 804 | HAL_I2S_ErrorCallback(hi2s); |
lypinator | 0:bb348c97df44 | 805 | } |
lypinator | 0:bb348c97df44 | 806 | |
lypinator | 0:bb348c97df44 | 807 | /* I2S Underrun error interrupt occured ----------------------------------*/ |
lypinator | 0:bb348c97df44 | 808 | if(((i2ssr & I2S_FLAG_UDR) == I2S_FLAG_UDR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET)) |
lypinator | 0:bb348c97df44 | 809 | { |
lypinator | 0:bb348c97df44 | 810 | /* Disable TXE and ERR interrupt */ |
lypinator | 0:bb348c97df44 | 811 | __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR)); |
lypinator | 0:bb348c97df44 | 812 | |
lypinator | 0:bb348c97df44 | 813 | /* Disable RXNE and ERR interrupt */ |
lypinator | 0:bb348c97df44 | 814 | __HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR)); |
lypinator | 0:bb348c97df44 | 815 | |
lypinator | 0:bb348c97df44 | 816 | /* Clear underrun flag */ |
lypinator | 0:bb348c97df44 | 817 | __HAL_I2S_CLEAR_UDRFLAG(hi2s); |
lypinator | 0:bb348c97df44 | 818 | |
lypinator | 0:bb348c97df44 | 819 | /* Set the I2S State ready */ |
lypinator | 0:bb348c97df44 | 820 | hi2s->State = HAL_I2S_STATE_READY; |
lypinator | 0:bb348c97df44 | 821 | |
lypinator | 0:bb348c97df44 | 822 | /* Set the error code and execute error callback*/ |
lypinator | 0:bb348c97df44 | 823 | SET_BIT(hi2s->ErrorCode,HAL_I2S_ERROR_UDR); |
lypinator | 0:bb348c97df44 | 824 | HAL_I2S_ErrorCallback(hi2s); |
lypinator | 0:bb348c97df44 | 825 | } |
lypinator | 0:bb348c97df44 | 826 | } |
lypinator | 0:bb348c97df44 | 827 | /* The I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX Mode is selected */ |
lypinator | 0:bb348c97df44 | 828 | else |
lypinator | 0:bb348c97df44 | 829 | { |
lypinator | 0:bb348c97df44 | 830 | /* I2Sext in mode Transmitter ----------------------------------------------*/ |
lypinator | 0:bb348c97df44 | 831 | if(((i2sextsr & I2S_FLAG_TXE) == I2S_FLAG_TXE) && (__HAL_I2SEXT_GET_IT_SOURCE(hi2s, I2S_IT_TXE) != RESET)) |
lypinator | 0:bb348c97df44 | 832 | { |
lypinator | 0:bb348c97df44 | 833 | /* When the I2S mode is configured as I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX, |
lypinator | 0:bb348c97df44 | 834 | the I2Sext TXE interrupt will be generated to manage the full-duplex transmit phase. */ |
lypinator | 0:bb348c97df44 | 835 | I2SEx_FullDuplexTx_IT(hi2s, I2S_USE_I2SEXT); |
lypinator | 0:bb348c97df44 | 836 | } |
lypinator | 0:bb348c97df44 | 837 | |
lypinator | 0:bb348c97df44 | 838 | /* I2S in mode Receiver --------------------------------------------------*/ |
lypinator | 0:bb348c97df44 | 839 | if(((i2ssr & I2S_FLAG_RXNE) == I2S_FLAG_RXNE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_RXNE) != RESET)) |
lypinator | 0:bb348c97df44 | 840 | { |
lypinator | 0:bb348c97df44 | 841 | /* When the I2S mode is configured as I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX, |
lypinator | 0:bb348c97df44 | 842 | the I2S RXNE interrupt will be generated to manage the full-duplex receive phase. */ |
lypinator | 0:bb348c97df44 | 843 | I2SEx_FullDuplexRx_IT(hi2s, I2S_USE_I2S); |
lypinator | 0:bb348c97df44 | 844 | } |
lypinator | 0:bb348c97df44 | 845 | |
lypinator | 0:bb348c97df44 | 846 | /* I2S Overrun error interrupt occured -------------------------------------*/ |
lypinator | 0:bb348c97df44 | 847 | if(((i2ssr & I2S_FLAG_OVR) == I2S_FLAG_OVR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET)) |
lypinator | 0:bb348c97df44 | 848 | { |
lypinator | 0:bb348c97df44 | 849 | /* Disable RXNE and ERR interrupt */ |
lypinator | 0:bb348c97df44 | 850 | __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR)); |
lypinator | 0:bb348c97df44 | 851 | |
lypinator | 0:bb348c97df44 | 852 | /* Disable TXE and ERR interrupt */ |
lypinator | 0:bb348c97df44 | 853 | __HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR)); |
lypinator | 0:bb348c97df44 | 854 | |
lypinator | 0:bb348c97df44 | 855 | /* Set the I2S State ready */ |
lypinator | 0:bb348c97df44 | 856 | hi2s->State = HAL_I2S_STATE_READY; |
lypinator | 0:bb348c97df44 | 857 | |
lypinator | 0:bb348c97df44 | 858 | /* Set the error code and execute error callback*/ |
lypinator | 0:bb348c97df44 | 859 | SET_BIT(hi2s->ErrorCode,HAL_I2S_ERROR_OVR); |
lypinator | 0:bb348c97df44 | 860 | HAL_I2S_ErrorCallback(hi2s); |
lypinator | 0:bb348c97df44 | 861 | } |
lypinator | 0:bb348c97df44 | 862 | |
lypinator | 0:bb348c97df44 | 863 | /* I2Sext Underrun error interrupt occured -------------------------------*/ |
lypinator | 0:bb348c97df44 | 864 | if(((i2sextsr & I2S_FLAG_UDR) == I2S_FLAG_UDR) && (__HAL_I2SEXT_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET)) |
lypinator | 0:bb348c97df44 | 865 | { |
lypinator | 0:bb348c97df44 | 866 | /* Disable TXE and ERR interrupt */ |
lypinator | 0:bb348c97df44 | 867 | __HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR)); |
lypinator | 0:bb348c97df44 | 868 | |
lypinator | 0:bb348c97df44 | 869 | /* Disable RXNE and ERR interrupt */ |
lypinator | 0:bb348c97df44 | 870 | __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR)); |
lypinator | 0:bb348c97df44 | 871 | |
lypinator | 0:bb348c97df44 | 872 | /* Set the I2S State ready */ |
lypinator | 0:bb348c97df44 | 873 | hi2s->State = HAL_I2S_STATE_READY; |
lypinator | 0:bb348c97df44 | 874 | |
lypinator | 0:bb348c97df44 | 875 | /* Set the error code and execute error callback*/ |
lypinator | 0:bb348c97df44 | 876 | SET_BIT(hi2s->ErrorCode,HAL_I2S_ERROR_UDR); |
lypinator | 0:bb348c97df44 | 877 | HAL_I2S_ErrorCallback(hi2s); |
lypinator | 0:bb348c97df44 | 878 | } |
lypinator | 0:bb348c97df44 | 879 | } |
lypinator | 0:bb348c97df44 | 880 | } |
lypinator | 0:bb348c97df44 | 881 | |
lypinator | 0:bb348c97df44 | 882 | /** |
lypinator | 0:bb348c97df44 | 883 | * @brief Tx and Rx Transfer half completed callback |
lypinator | 0:bb348c97df44 | 884 | * @param hi2s I2S handle |
lypinator | 0:bb348c97df44 | 885 | * @retval None |
lypinator | 0:bb348c97df44 | 886 | */ |
lypinator | 0:bb348c97df44 | 887 | __weak void HAL_I2SEx_TxRxHalfCpltCallback(I2S_HandleTypeDef *hi2s) |
lypinator | 0:bb348c97df44 | 888 | { |
lypinator | 0:bb348c97df44 | 889 | /* Prevent unused argument(s) compilation warning */ |
lypinator | 0:bb348c97df44 | 890 | UNUSED(hi2s); |
lypinator | 0:bb348c97df44 | 891 | |
lypinator | 0:bb348c97df44 | 892 | /* NOTE : This function Should not be modified, when the callback is needed, |
lypinator | 0:bb348c97df44 | 893 | the HAL_I2SEx_TxRxHalfCpltCallback could be implemented in the user file |
lypinator | 0:bb348c97df44 | 894 | */ |
lypinator | 0:bb348c97df44 | 895 | } |
lypinator | 0:bb348c97df44 | 896 | |
lypinator | 0:bb348c97df44 | 897 | /** |
lypinator | 0:bb348c97df44 | 898 | * @brief Tx and Rx Transfer completed callback |
lypinator | 0:bb348c97df44 | 899 | * @param hi2s I2S handle |
lypinator | 0:bb348c97df44 | 900 | * @retval None |
lypinator | 0:bb348c97df44 | 901 | */ |
lypinator | 0:bb348c97df44 | 902 | __weak void HAL_I2SEx_TxRxCpltCallback(I2S_HandleTypeDef *hi2s) |
lypinator | 0:bb348c97df44 | 903 | { |
lypinator | 0:bb348c97df44 | 904 | /* Prevent unused argument(s) compilation warning */ |
lypinator | 0:bb348c97df44 | 905 | UNUSED(hi2s); |
lypinator | 0:bb348c97df44 | 906 | |
lypinator | 0:bb348c97df44 | 907 | /* NOTE : This function Should not be modified, when the callback is needed, |
lypinator | 0:bb348c97df44 | 908 | the HAL_I2SEx_TxRxCpltCallback could be implemented in the user file |
lypinator | 0:bb348c97df44 | 909 | */ |
lypinator | 0:bb348c97df44 | 910 | } |
lypinator | 0:bb348c97df44 | 911 | |
lypinator | 0:bb348c97df44 | 912 | /** |
lypinator | 0:bb348c97df44 | 913 | * @} |
lypinator | 0:bb348c97df44 | 914 | */ |
lypinator | 0:bb348c97df44 | 915 | |
lypinator | 0:bb348c97df44 | 916 | /** |
lypinator | 0:bb348c97df44 | 917 | * @} |
lypinator | 0:bb348c97df44 | 918 | */ |
lypinator | 0:bb348c97df44 | 919 | |
lypinator | 0:bb348c97df44 | 920 | /** @addtogroup I2SEx_Private_Functions I2S Extended Private Functions |
lypinator | 0:bb348c97df44 | 921 | * @{ |
lypinator | 0:bb348c97df44 | 922 | */ |
lypinator | 0:bb348c97df44 | 923 | |
lypinator | 0:bb348c97df44 | 924 | /** |
lypinator | 0:bb348c97df44 | 925 | * @brief DMA I2S transmit receive process half complete callback |
lypinator | 0:bb348c97df44 | 926 | * @param hdma pointer to a DMA_HandleTypeDef structure that contains |
lypinator | 0:bb348c97df44 | 927 | * the configuration information for the specified DMA module. |
lypinator | 0:bb348c97df44 | 928 | * @retval None |
lypinator | 0:bb348c97df44 | 929 | */ |
lypinator | 0:bb348c97df44 | 930 | static void I2SEx_TxRxDMAHalfCplt(DMA_HandleTypeDef *hdma) |
lypinator | 0:bb348c97df44 | 931 | { |
lypinator | 0:bb348c97df44 | 932 | I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; |
lypinator | 0:bb348c97df44 | 933 | |
lypinator | 0:bb348c97df44 | 934 | HAL_I2SEx_TxRxHalfCpltCallback(hi2s); |
lypinator | 0:bb348c97df44 | 935 | } |
lypinator | 0:bb348c97df44 | 936 | |
lypinator | 0:bb348c97df44 | 937 | /** |
lypinator | 0:bb348c97df44 | 938 | * @brief DMA I2S transmit receive process complete callback |
lypinator | 0:bb348c97df44 | 939 | * @param hdma pointer to a DMA_HandleTypeDef structure that contains |
lypinator | 0:bb348c97df44 | 940 | * the configuration information for the specified DMA module. |
lypinator | 0:bb348c97df44 | 941 | * @retval None |
lypinator | 0:bb348c97df44 | 942 | */ |
lypinator | 0:bb348c97df44 | 943 | static void I2SEx_TxRxDMACplt(DMA_HandleTypeDef *hdma) |
lypinator | 0:bb348c97df44 | 944 | { |
lypinator | 0:bb348c97df44 | 945 | I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; |
lypinator | 0:bb348c97df44 | 946 | |
lypinator | 0:bb348c97df44 | 947 | /* if DMA is not configured in DMA_CIRCULAR mode */ |
lypinator | 0:bb348c97df44 | 948 | if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U) |
lypinator | 0:bb348c97df44 | 949 | { |
lypinator | 0:bb348c97df44 | 950 | if (hi2s->hdmarx == hdma) |
lypinator | 0:bb348c97df44 | 951 | { |
lypinator | 0:bb348c97df44 | 952 | /* Disable Rx DMA Request */ |
lypinator | 0:bb348c97df44 | 953 | if (((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_TX) ||\ |
lypinator | 0:bb348c97df44 | 954 | ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX)) |
lypinator | 0:bb348c97df44 | 955 | { |
lypinator | 0:bb348c97df44 | 956 | CLEAR_BIT(I2SxEXT(hi2s->Instance)->CR2,SPI_CR2_RXDMAEN); |
lypinator | 0:bb348c97df44 | 957 | } |
lypinator | 0:bb348c97df44 | 958 | else |
lypinator | 0:bb348c97df44 | 959 | { |
lypinator | 0:bb348c97df44 | 960 | CLEAR_BIT(hi2s->Instance->CR2,SPI_CR2_RXDMAEN); |
lypinator | 0:bb348c97df44 | 961 | } |
lypinator | 0:bb348c97df44 | 962 | |
lypinator | 0:bb348c97df44 | 963 | hi2s->RxXferCount = 0U; |
lypinator | 0:bb348c97df44 | 964 | |
lypinator | 0:bb348c97df44 | 965 | if (hi2s->TxXferCount == 0U) |
lypinator | 0:bb348c97df44 | 966 | { |
lypinator | 0:bb348c97df44 | 967 | hi2s->State = HAL_I2S_STATE_READY; |
lypinator | 0:bb348c97df44 | 968 | |
lypinator | 0:bb348c97df44 | 969 | HAL_I2SEx_TxRxCpltCallback(hi2s); |
lypinator | 0:bb348c97df44 | 970 | } |
lypinator | 0:bb348c97df44 | 971 | } |
lypinator | 0:bb348c97df44 | 972 | |
lypinator | 0:bb348c97df44 | 973 | if (hi2s->hdmatx == hdma) |
lypinator | 0:bb348c97df44 | 974 | { |
lypinator | 0:bb348c97df44 | 975 | /* Disable Tx DMA Request */ |
lypinator | 0:bb348c97df44 | 976 | if (((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_TX) ||\ |
lypinator | 0:bb348c97df44 | 977 | ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX)) |
lypinator | 0:bb348c97df44 | 978 | { |
lypinator | 0:bb348c97df44 | 979 | CLEAR_BIT(hi2s->Instance->CR2,SPI_CR2_TXDMAEN); |
lypinator | 0:bb348c97df44 | 980 | } |
lypinator | 0:bb348c97df44 | 981 | else |
lypinator | 0:bb348c97df44 | 982 | { |
lypinator | 0:bb348c97df44 | 983 | CLEAR_BIT(I2SxEXT(hi2s->Instance)->CR2,SPI_CR2_TXDMAEN); |
lypinator | 0:bb348c97df44 | 984 | } |
lypinator | 0:bb348c97df44 | 985 | |
lypinator | 0:bb348c97df44 | 986 | hi2s->TxXferCount = 0U; |
lypinator | 0:bb348c97df44 | 987 | |
lypinator | 0:bb348c97df44 | 988 | if (hi2s->RxXferCount == 0U) |
lypinator | 0:bb348c97df44 | 989 | { |
lypinator | 0:bb348c97df44 | 990 | hi2s->State = HAL_I2S_STATE_READY; |
lypinator | 0:bb348c97df44 | 991 | |
lypinator | 0:bb348c97df44 | 992 | HAL_I2SEx_TxRxCpltCallback(hi2s); |
lypinator | 0:bb348c97df44 | 993 | } |
lypinator | 0:bb348c97df44 | 994 | } |
lypinator | 0:bb348c97df44 | 995 | } |
lypinator | 0:bb348c97df44 | 996 | } |
lypinator | 0:bb348c97df44 | 997 | |
lypinator | 0:bb348c97df44 | 998 | /** |
lypinator | 0:bb348c97df44 | 999 | * @brief DMA I2S communication error callback |
lypinator | 0:bb348c97df44 | 1000 | * @param hdma DMA handle |
lypinator | 0:bb348c97df44 | 1001 | * @retval None |
lypinator | 0:bb348c97df44 | 1002 | */ |
lypinator | 0:bb348c97df44 | 1003 | static void I2SEx_TxRxDMAError(DMA_HandleTypeDef *hdma) |
lypinator | 0:bb348c97df44 | 1004 | { |
lypinator | 0:bb348c97df44 | 1005 | I2S_HandleTypeDef* hi2s = ( I2S_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; |
lypinator | 0:bb348c97df44 | 1006 | |
lypinator | 0:bb348c97df44 | 1007 | /* Disable Rx and Tx DMA Request */ |
lypinator | 0:bb348c97df44 | 1008 | CLEAR_BIT(hi2s->Instance->CR2,(SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN)); |
lypinator | 0:bb348c97df44 | 1009 | CLEAR_BIT(I2SxEXT(hi2s->Instance)->CR2,(SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN)); |
lypinator | 0:bb348c97df44 | 1010 | |
lypinator | 0:bb348c97df44 | 1011 | hi2s->TxXferCount = 0U; |
lypinator | 0:bb348c97df44 | 1012 | hi2s->RxXferCount = 0U; |
lypinator | 0:bb348c97df44 | 1013 | |
lypinator | 0:bb348c97df44 | 1014 | hi2s->State= HAL_I2S_STATE_READY; |
lypinator | 0:bb348c97df44 | 1015 | |
lypinator | 0:bb348c97df44 | 1016 | /* Set the error code and execute error callback*/ |
lypinator | 0:bb348c97df44 | 1017 | SET_BIT(hi2s->ErrorCode,HAL_I2S_ERROR_DMA); |
lypinator | 0:bb348c97df44 | 1018 | HAL_I2S_ErrorCallback(hi2s); |
lypinator | 0:bb348c97df44 | 1019 | } |
lypinator | 0:bb348c97df44 | 1020 | |
lypinator | 0:bb348c97df44 | 1021 | /** |
lypinator | 0:bb348c97df44 | 1022 | * @brief Full-Duplex IT handler transmit function |
lypinator | 0:bb348c97df44 | 1023 | * @param hi2s I2S handle |
lypinator | 0:bb348c97df44 | 1024 | * @param i2sUsed indicate if I2Sx or I2Sx_ext is concerned |
lypinator | 0:bb348c97df44 | 1025 | * @retval None |
lypinator | 0:bb348c97df44 | 1026 | */ |
lypinator | 0:bb348c97df44 | 1027 | static void I2SEx_FullDuplexTx_IT(I2S_HandleTypeDef *hi2s, I2S_UseTypeDef i2sUsed) |
lypinator | 0:bb348c97df44 | 1028 | { |
lypinator | 0:bb348c97df44 | 1029 | if(i2sUsed == I2S_USE_I2S) |
lypinator | 0:bb348c97df44 | 1030 | { |
lypinator | 0:bb348c97df44 | 1031 | /* Write Data on DR register */ |
lypinator | 0:bb348c97df44 | 1032 | hi2s->Instance->DR = (*hi2s->pTxBuffPtr++); |
lypinator | 0:bb348c97df44 | 1033 | hi2s->TxXferCount--; |
lypinator | 0:bb348c97df44 | 1034 | |
lypinator | 0:bb348c97df44 | 1035 | if(hi2s->TxXferCount == 0U) |
lypinator | 0:bb348c97df44 | 1036 | { |
lypinator | 0:bb348c97df44 | 1037 | /* Disable TXE and ERR interrupt */ |
lypinator | 0:bb348c97df44 | 1038 | __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR)); |
lypinator | 0:bb348c97df44 | 1039 | |
lypinator | 0:bb348c97df44 | 1040 | if(hi2s->RxXferCount == 0U) |
lypinator | 0:bb348c97df44 | 1041 | { |
lypinator | 0:bb348c97df44 | 1042 | hi2s->State = HAL_I2S_STATE_READY; |
lypinator | 0:bb348c97df44 | 1043 | HAL_I2SEx_TxRxCpltCallback(hi2s); |
lypinator | 0:bb348c97df44 | 1044 | } |
lypinator | 0:bb348c97df44 | 1045 | } |
lypinator | 0:bb348c97df44 | 1046 | } |
lypinator | 0:bb348c97df44 | 1047 | else |
lypinator | 0:bb348c97df44 | 1048 | { |
lypinator | 0:bb348c97df44 | 1049 | /* Write Data on DR register */ |
lypinator | 0:bb348c97df44 | 1050 | I2SxEXT(hi2s->Instance)->DR = (*hi2s->pTxBuffPtr++); |
lypinator | 0:bb348c97df44 | 1051 | hi2s->TxXferCount--; |
lypinator | 0:bb348c97df44 | 1052 | |
lypinator | 0:bb348c97df44 | 1053 | if(hi2s->TxXferCount == 0U) |
lypinator | 0:bb348c97df44 | 1054 | { |
lypinator | 0:bb348c97df44 | 1055 | /* Disable I2Sext TXE and ERR interrupt */ |
lypinator | 0:bb348c97df44 | 1056 | __HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR)); |
lypinator | 0:bb348c97df44 | 1057 | |
lypinator | 0:bb348c97df44 | 1058 | if(hi2s->RxXferCount == 0U) |
lypinator | 0:bb348c97df44 | 1059 | { |
lypinator | 0:bb348c97df44 | 1060 | hi2s->State = HAL_I2S_STATE_READY; |
lypinator | 0:bb348c97df44 | 1061 | HAL_I2SEx_TxRxCpltCallback(hi2s); |
lypinator | 0:bb348c97df44 | 1062 | } |
lypinator | 0:bb348c97df44 | 1063 | } |
lypinator | 0:bb348c97df44 | 1064 | } |
lypinator | 0:bb348c97df44 | 1065 | } |
lypinator | 0:bb348c97df44 | 1066 | |
lypinator | 0:bb348c97df44 | 1067 | /** |
lypinator | 0:bb348c97df44 | 1068 | * @brief Full-Duplex IT handler receive function |
lypinator | 0:bb348c97df44 | 1069 | * @param hi2s I2S handle |
lypinator | 0:bb348c97df44 | 1070 | * @param i2sUsed indicate if I2Sx or I2Sx_ext is concerned |
lypinator | 0:bb348c97df44 | 1071 | * @retval None |
lypinator | 0:bb348c97df44 | 1072 | */ |
lypinator | 0:bb348c97df44 | 1073 | static void I2SEx_FullDuplexRx_IT(I2S_HandleTypeDef *hi2s, I2S_UseTypeDef i2sUsed) |
lypinator | 0:bb348c97df44 | 1074 | { |
lypinator | 0:bb348c97df44 | 1075 | if(i2sUsed == I2S_USE_I2S) |
lypinator | 0:bb348c97df44 | 1076 | { |
lypinator | 0:bb348c97df44 | 1077 | /* Read Data from DR register */ |
lypinator | 0:bb348c97df44 | 1078 | (*hi2s->pRxBuffPtr++) = hi2s->Instance->DR; |
lypinator | 0:bb348c97df44 | 1079 | hi2s->RxXferCount--; |
lypinator | 0:bb348c97df44 | 1080 | |
lypinator | 0:bb348c97df44 | 1081 | if(hi2s->RxXferCount == 0U) |
lypinator | 0:bb348c97df44 | 1082 | { |
lypinator | 0:bb348c97df44 | 1083 | /* Disable RXNE and ERR interrupt */ |
lypinator | 0:bb348c97df44 | 1084 | __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR)); |
lypinator | 0:bb348c97df44 | 1085 | |
lypinator | 0:bb348c97df44 | 1086 | if(hi2s->TxXferCount == 0U) |
lypinator | 0:bb348c97df44 | 1087 | { |
lypinator | 0:bb348c97df44 | 1088 | hi2s->State = HAL_I2S_STATE_READY; |
lypinator | 0:bb348c97df44 | 1089 | HAL_I2SEx_TxRxCpltCallback(hi2s); |
lypinator | 0:bb348c97df44 | 1090 | } |
lypinator | 0:bb348c97df44 | 1091 | } |
lypinator | 0:bb348c97df44 | 1092 | } |
lypinator | 0:bb348c97df44 | 1093 | else |
lypinator | 0:bb348c97df44 | 1094 | { |
lypinator | 0:bb348c97df44 | 1095 | /* Read Data from DR register */ |
lypinator | 0:bb348c97df44 | 1096 | (*hi2s->pRxBuffPtr++) = I2SxEXT(hi2s->Instance)->DR; |
lypinator | 0:bb348c97df44 | 1097 | hi2s->RxXferCount--; |
lypinator | 0:bb348c97df44 | 1098 | |
lypinator | 0:bb348c97df44 | 1099 | if(hi2s->RxXferCount == 0U) |
lypinator | 0:bb348c97df44 | 1100 | { |
lypinator | 0:bb348c97df44 | 1101 | /* Disable I2Sext RXNE and ERR interrupt */ |
lypinator | 0:bb348c97df44 | 1102 | __HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR)); |
lypinator | 0:bb348c97df44 | 1103 | |
lypinator | 0:bb348c97df44 | 1104 | if(hi2s->TxXferCount == 0U) |
lypinator | 0:bb348c97df44 | 1105 | { |
lypinator | 0:bb348c97df44 | 1106 | hi2s->State = HAL_I2S_STATE_READY; |
lypinator | 0:bb348c97df44 | 1107 | HAL_I2SEx_TxRxCpltCallback(hi2s); |
lypinator | 0:bb348c97df44 | 1108 | } |
lypinator | 0:bb348c97df44 | 1109 | } |
lypinator | 0:bb348c97df44 | 1110 | } |
lypinator | 0:bb348c97df44 | 1111 | } |
lypinator | 0:bb348c97df44 | 1112 | |
lypinator | 0:bb348c97df44 | 1113 | /** |
lypinator | 0:bb348c97df44 | 1114 | * @brief This function handles I2S Communication Timeout. |
lypinator | 0:bb348c97df44 | 1115 | * @param hi2s I2S handle |
lypinator | 0:bb348c97df44 | 1116 | * @param Flag Flag checked |
lypinator | 0:bb348c97df44 | 1117 | * @param State Value of the flag expected |
lypinator | 0:bb348c97df44 | 1118 | * @param Timeout Duration of the timeout |
lypinator | 0:bb348c97df44 | 1119 | * @param i2sUsed I2S instance reference |
lypinator | 0:bb348c97df44 | 1120 | * @retval HAL status |
lypinator | 0:bb348c97df44 | 1121 | */ |
lypinator | 0:bb348c97df44 | 1122 | static HAL_StatusTypeDef I2SEx_FullDuplexWaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, |
lypinator | 0:bb348c97df44 | 1123 | uint32_t State, uint32_t Timeout, I2S_UseTypeDef i2sUsed) |
lypinator | 0:bb348c97df44 | 1124 | { |
lypinator | 0:bb348c97df44 | 1125 | uint32_t tickstart = HAL_GetTick(); |
lypinator | 0:bb348c97df44 | 1126 | |
lypinator | 0:bb348c97df44 | 1127 | if(i2sUsed == I2S_USE_I2S) |
lypinator | 0:bb348c97df44 | 1128 | { |
lypinator | 0:bb348c97df44 | 1129 | /* Wait until flag is reset */ |
lypinator | 0:bb348c97df44 | 1130 | while(((__HAL_I2S_GET_FLAG(hi2s, Flag)) ? SET : RESET) != State) |
lypinator | 0:bb348c97df44 | 1131 | { |
lypinator | 0:bb348c97df44 | 1132 | if(Timeout != HAL_MAX_DELAY) |
lypinator | 0:bb348c97df44 | 1133 | { |
lypinator | 0:bb348c97df44 | 1134 | if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout)) |
lypinator | 0:bb348c97df44 | 1135 | { |
lypinator | 0:bb348c97df44 | 1136 | /* Set the I2S State ready */ |
lypinator | 0:bb348c97df44 | 1137 | hi2s->State= HAL_I2S_STATE_READY; |
lypinator | 0:bb348c97df44 | 1138 | |
lypinator | 0:bb348c97df44 | 1139 | /* Process Unlocked */ |
lypinator | 0:bb348c97df44 | 1140 | __HAL_UNLOCK(hi2s); |
lypinator | 0:bb348c97df44 | 1141 | |
lypinator | 0:bb348c97df44 | 1142 | return HAL_TIMEOUT; |
lypinator | 0:bb348c97df44 | 1143 | } |
lypinator | 0:bb348c97df44 | 1144 | } |
lypinator | 0:bb348c97df44 | 1145 | } |
lypinator | 0:bb348c97df44 | 1146 | } |
lypinator | 0:bb348c97df44 | 1147 | else /* i2sUsed == I2S_USE_I2SEXT */ |
lypinator | 0:bb348c97df44 | 1148 | { |
lypinator | 0:bb348c97df44 | 1149 | /* Wait until flag is reset */ |
lypinator | 0:bb348c97df44 | 1150 | while(((__HAL_I2SEXT_GET_FLAG(hi2s, Flag)) ? SET : RESET) != State) |
lypinator | 0:bb348c97df44 | 1151 | { |
lypinator | 0:bb348c97df44 | 1152 | if(Timeout != HAL_MAX_DELAY) |
lypinator | 0:bb348c97df44 | 1153 | { |
lypinator | 0:bb348c97df44 | 1154 | if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout)) |
lypinator | 0:bb348c97df44 | 1155 | { |
lypinator | 0:bb348c97df44 | 1156 | /* Set the I2S State ready */ |
lypinator | 0:bb348c97df44 | 1157 | hi2s->State= HAL_I2S_STATE_READY; |
lypinator | 0:bb348c97df44 | 1158 | |
lypinator | 0:bb348c97df44 | 1159 | /* Process Unlocked */ |
lypinator | 0:bb348c97df44 | 1160 | __HAL_UNLOCK(hi2s); |
lypinator | 0:bb348c97df44 | 1161 | |
lypinator | 0:bb348c97df44 | 1162 | return HAL_TIMEOUT; |
lypinator | 0:bb348c97df44 | 1163 | } |
lypinator | 0:bb348c97df44 | 1164 | } |
lypinator | 0:bb348c97df44 | 1165 | } |
lypinator | 0:bb348c97df44 | 1166 | } |
lypinator | 0:bb348c97df44 | 1167 | return HAL_OK; |
lypinator | 0:bb348c97df44 | 1168 | } |
lypinator | 0:bb348c97df44 | 1169 | |
lypinator | 0:bb348c97df44 | 1170 | /** |
lypinator | 0:bb348c97df44 | 1171 | * @} |
lypinator | 0:bb348c97df44 | 1172 | */ |
lypinator | 0:bb348c97df44 | 1173 | #endif /* SPI_I2S_FULLDUPLEX_SUPPORT */ |
lypinator | 0:bb348c97df44 | 1174 | |
lypinator | 0:bb348c97df44 | 1175 | /** |
lypinator | 0:bb348c97df44 | 1176 | * @} |
lypinator | 0:bb348c97df44 | 1177 | */ |
lypinator | 0:bb348c97df44 | 1178 | #endif /* HAL_I2S_MODULE_ENABLED */ |
lypinator | 0:bb348c97df44 | 1179 | |
lypinator | 0:bb348c97df44 | 1180 | /** |
lypinator | 0:bb348c97df44 | 1181 | * @} |
lypinator | 0:bb348c97df44 | 1182 | */ |
lypinator | 0:bb348c97df44 | 1183 | |
lypinator | 0:bb348c97df44 | 1184 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |