Initial commit
mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_NUCLEO_F429ZI/system_clock.c@0:bb348c97df44, 2020-09-16 (annotated)
- Committer:
- lypinator
- Date:
- Wed Sep 16 01:11:49 2020 +0000
- Revision:
- 0:bb348c97df44
Added PWM
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
lypinator | 0:bb348c97df44 | 1 | /* mbed Microcontroller Library |
lypinator | 0:bb348c97df44 | 2 | * Copyright (c) 2006-2017 ARM Limited |
lypinator | 0:bb348c97df44 | 3 | * |
lypinator | 0:bb348c97df44 | 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
lypinator | 0:bb348c97df44 | 5 | * you may not use this file except in compliance with the License. |
lypinator | 0:bb348c97df44 | 6 | * You may obtain a copy of the License at |
lypinator | 0:bb348c97df44 | 7 | * |
lypinator | 0:bb348c97df44 | 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
lypinator | 0:bb348c97df44 | 9 | * |
lypinator | 0:bb348c97df44 | 10 | * Unless required by applicable law or agreed to in writing, software |
lypinator | 0:bb348c97df44 | 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
lypinator | 0:bb348c97df44 | 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
lypinator | 0:bb348c97df44 | 13 | * See the License for the specific language governing permissions and |
lypinator | 0:bb348c97df44 | 14 | * limitations under the License. |
lypinator | 0:bb348c97df44 | 15 | */ |
lypinator | 0:bb348c97df44 | 16 | |
lypinator | 0:bb348c97df44 | 17 | /** |
lypinator | 0:bb348c97df44 | 18 | * This file configures the system clock as follows: |
lypinator | 0:bb348c97df44 | 19 | *----------------------------------------------------------------------------------- |
lypinator | 0:bb348c97df44 | 20 | * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock) | |
lypinator | 0:bb348c97df44 | 21 | * | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal) | CLOCK_SOURCE_USB=1 |
lypinator | 0:bb348c97df44 | 22 | * | 3- USE_PLL_HSI (internal 16 MHz clock) | |
lypinator | 0:bb348c97df44 | 23 | *----------------------------------------------------------------------------------- |
lypinator | 0:bb348c97df44 | 24 | * SYSCLK(MHz) | 180 | 168 |
lypinator | 0:bb348c97df44 | 25 | * AHBCLK (MHz) | 180 | 168 |
lypinator | 0:bb348c97df44 | 26 | * APB1CLK (MHz) | 45 | 42 |
lypinator | 0:bb348c97df44 | 27 | * APB2CLK (MHz) | 90 | 84 |
lypinator | 0:bb348c97df44 | 28 | * USB capable (48 MHz) | NO | YES (HSI calibration needed) |
lypinator | 0:bb348c97df44 | 29 | *----------------------------------------------------------------------------------- |
lypinator | 0:bb348c97df44 | 30 | **/ |
lypinator | 0:bb348c97df44 | 31 | |
lypinator | 0:bb348c97df44 | 32 | #include "stm32f4xx.h" |
lypinator | 0:bb348c97df44 | 33 | |
lypinator | 0:bb348c97df44 | 34 | #include "mbed_error.h" |
lypinator | 0:bb348c97df44 | 35 | |
lypinator | 0:bb348c97df44 | 36 | // clock source is selected with CLOCK_SOURCE in json config |
lypinator | 0:bb348c97df44 | 37 | #define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO) |
lypinator | 0:bb348c97df44 | 38 | #define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default) |
lypinator | 0:bb348c97df44 | 39 | #define USE_PLL_HSI 0x2 // Use HSI internal clock |
lypinator | 0:bb348c97df44 | 40 | |
lypinator | 0:bb348c97df44 | 41 | #if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) ) |
lypinator | 0:bb348c97df44 | 42 | uint8_t SetSysClock_PLL_HSE(uint8_t bypass); |
lypinator | 0:bb348c97df44 | 43 | #endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */ |
lypinator | 0:bb348c97df44 | 44 | |
lypinator | 0:bb348c97df44 | 45 | #if ((CLOCK_SOURCE) & USE_PLL_HSI) |
lypinator | 0:bb348c97df44 | 46 | uint8_t SetSysClock_PLL_HSI(void); |
lypinator | 0:bb348c97df44 | 47 | #endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */ |
lypinator | 0:bb348c97df44 | 48 | |
lypinator | 0:bb348c97df44 | 49 | |
lypinator | 0:bb348c97df44 | 50 | /** |
lypinator | 0:bb348c97df44 | 51 | * @brief Setup the microcontroller system |
lypinator | 0:bb348c97df44 | 52 | * Initialize the FPU setting, vector table location and External memory |
lypinator | 0:bb348c97df44 | 53 | * configuration. |
lypinator | 0:bb348c97df44 | 54 | * @param None |
lypinator | 0:bb348c97df44 | 55 | * @retval None |
lypinator | 0:bb348c97df44 | 56 | */ |
lypinator | 0:bb348c97df44 | 57 | void SystemInit(void) |
lypinator | 0:bb348c97df44 | 58 | { |
lypinator | 0:bb348c97df44 | 59 | /* Reset the RCC clock configuration to the default reset state ------------*/ |
lypinator | 0:bb348c97df44 | 60 | /* Set HSION bit */ |
lypinator | 0:bb348c97df44 | 61 | RCC->CR |= (uint32_t)0x00000001; |
lypinator | 0:bb348c97df44 | 62 | |
lypinator | 0:bb348c97df44 | 63 | /* Reset CFGR register */ |
lypinator | 0:bb348c97df44 | 64 | RCC->CFGR = 0x00000000; |
lypinator | 0:bb348c97df44 | 65 | |
lypinator | 0:bb348c97df44 | 66 | /* Reset HSEON, CSSON and PLLON bits */ |
lypinator | 0:bb348c97df44 | 67 | RCC->CR &= (uint32_t)0xFEF6FFFF; |
lypinator | 0:bb348c97df44 | 68 | |
lypinator | 0:bb348c97df44 | 69 | /* Reset PLLCFGR register */ |
lypinator | 0:bb348c97df44 | 70 | RCC->PLLCFGR = 0x24003010; |
lypinator | 0:bb348c97df44 | 71 | |
lypinator | 0:bb348c97df44 | 72 | /* Reset HSEBYP bit */ |
lypinator | 0:bb348c97df44 | 73 | RCC->CR &= (uint32_t)0xFFFBFFFF; |
lypinator | 0:bb348c97df44 | 74 | |
lypinator | 0:bb348c97df44 | 75 | /* Disable all interrupts */ |
lypinator | 0:bb348c97df44 | 76 | RCC->CIR = 0x00000000; |
lypinator | 0:bb348c97df44 | 77 | |
lypinator | 0:bb348c97df44 | 78 | #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) |
lypinator | 0:bb348c97df44 | 79 | SystemInit_ExtMemCtl(); |
lypinator | 0:bb348c97df44 | 80 | #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ |
lypinator | 0:bb348c97df44 | 81 | |
lypinator | 0:bb348c97df44 | 82 | } |
lypinator | 0:bb348c97df44 | 83 | |
lypinator | 0:bb348c97df44 | 84 | /** |
lypinator | 0:bb348c97df44 | 85 | * @brief Configures the System clock source, PLL Multiplier and Divider factors, |
lypinator | 0:bb348c97df44 | 86 | * AHB/APBx prescalers and Flash settings |
lypinator | 0:bb348c97df44 | 87 | * @note This function should be called only once the RCC clock configuration |
lypinator | 0:bb348c97df44 | 88 | * is reset to the default reset state (done in SystemInit() function). |
lypinator | 0:bb348c97df44 | 89 | * @param None |
lypinator | 0:bb348c97df44 | 90 | * @retval None |
lypinator | 0:bb348c97df44 | 91 | */ |
lypinator | 0:bb348c97df44 | 92 | |
lypinator | 0:bb348c97df44 | 93 | void SetSysClock(void) |
lypinator | 0:bb348c97df44 | 94 | { |
lypinator | 0:bb348c97df44 | 95 | #if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) |
lypinator | 0:bb348c97df44 | 96 | /* 1- Try to start with HSE and external clock */ |
lypinator | 0:bb348c97df44 | 97 | if (SetSysClock_PLL_HSE(1) == 0) |
lypinator | 0:bb348c97df44 | 98 | #endif |
lypinator | 0:bb348c97df44 | 99 | { |
lypinator | 0:bb348c97df44 | 100 | #if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) |
lypinator | 0:bb348c97df44 | 101 | /* 2- If fail try to start with HSE and external xtal */ |
lypinator | 0:bb348c97df44 | 102 | if (SetSysClock_PLL_HSE(0) == 0) |
lypinator | 0:bb348c97df44 | 103 | #endif |
lypinator | 0:bb348c97df44 | 104 | { |
lypinator | 0:bb348c97df44 | 105 | #if ((CLOCK_SOURCE) & USE_PLL_HSI) |
lypinator | 0:bb348c97df44 | 106 | /* 3- If fail start with HSI clock */ |
lypinator | 0:bb348c97df44 | 107 | if (SetSysClock_PLL_HSI() == 0) |
lypinator | 0:bb348c97df44 | 108 | #endif |
lypinator | 0:bb348c97df44 | 109 | { |
lypinator | 0:bb348c97df44 | 110 | { |
lypinator | 0:bb348c97df44 | 111 | error("SetSysClock failed\n"); |
lypinator | 0:bb348c97df44 | 112 | } |
lypinator | 0:bb348c97df44 | 113 | } |
lypinator | 0:bb348c97df44 | 114 | } |
lypinator | 0:bb348c97df44 | 115 | } |
lypinator | 0:bb348c97df44 | 116 | } |
lypinator | 0:bb348c97df44 | 117 | |
lypinator | 0:bb348c97df44 | 118 | #if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) ) |
lypinator | 0:bb348c97df44 | 119 | /******************************************************************************/ |
lypinator | 0:bb348c97df44 | 120 | /* PLL (clocked by HSE) used as System clock source */ |
lypinator | 0:bb348c97df44 | 121 | /******************************************************************************/ |
lypinator | 0:bb348c97df44 | 122 | uint8_t SetSysClock_PLL_HSE(uint8_t bypass) |
lypinator | 0:bb348c97df44 | 123 | { |
lypinator | 0:bb348c97df44 | 124 | RCC_OscInitTypeDef RCC_OscInitStruct; |
lypinator | 0:bb348c97df44 | 125 | RCC_ClkInitTypeDef RCC_ClkInitStruct; |
lypinator | 0:bb348c97df44 | 126 | |
lypinator | 0:bb348c97df44 | 127 | /* The voltage scaling allows optimizing the power consumption when the device is |
lypinator | 0:bb348c97df44 | 128 | clocked below the maximum system frequency, to update the voltage scaling value |
lypinator | 0:bb348c97df44 | 129 | regarding system frequency refer to product datasheet. */ |
lypinator | 0:bb348c97df44 | 130 | __HAL_RCC_PWR_CLK_ENABLE(); |
lypinator | 0:bb348c97df44 | 131 | __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); |
lypinator | 0:bb348c97df44 | 132 | |
lypinator | 0:bb348c97df44 | 133 | // Enable HSE oscillator and activate PLL with HSE as source |
lypinator | 0:bb348c97df44 | 134 | RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; |
lypinator | 0:bb348c97df44 | 135 | if (bypass == 0) { |
lypinator | 0:bb348c97df44 | 136 | RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT |
lypinator | 0:bb348c97df44 | 137 | } else { |
lypinator | 0:bb348c97df44 | 138 | RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN |
lypinator | 0:bb348c97df44 | 139 | } |
lypinator | 0:bb348c97df44 | 140 | |
lypinator | 0:bb348c97df44 | 141 | RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; |
lypinator | 0:bb348c97df44 | 142 | RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; |
lypinator | 0:bb348c97df44 | 143 | RCC_OscInitStruct.PLL.PLLM = 8; |
lypinator | 0:bb348c97df44 | 144 | #if (CLOCK_SOURCE_USB) |
lypinator | 0:bb348c97df44 | 145 | RCC_OscInitStruct.PLL.PLLN = 336; |
lypinator | 0:bb348c97df44 | 146 | #else |
lypinator | 0:bb348c97df44 | 147 | RCC_OscInitStruct.PLL.PLLN = 360; |
lypinator | 0:bb348c97df44 | 148 | #endif |
lypinator | 0:bb348c97df44 | 149 | RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // 180 MHz or 168 MHz if CLOCK_SOURCE_USB defined |
lypinator | 0:bb348c97df44 | 150 | RCC_OscInitStruct.PLL.PLLQ = 7; // 48 MHz if CLOCK_SOURCE_USB defined |
lypinator | 0:bb348c97df44 | 151 | if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { |
lypinator | 0:bb348c97df44 | 152 | return 0; // FAIL |
lypinator | 0:bb348c97df44 | 153 | } |
lypinator | 0:bb348c97df44 | 154 | |
lypinator | 0:bb348c97df44 | 155 | // Activate the OverDrive to reach the 180 MHz Frequency |
lypinator | 0:bb348c97df44 | 156 | if (HAL_PWREx_EnableOverDrive() != HAL_OK) { |
lypinator | 0:bb348c97df44 | 157 | return 0; // FAIL |
lypinator | 0:bb348c97df44 | 158 | } |
lypinator | 0:bb348c97df44 | 159 | |
lypinator | 0:bb348c97df44 | 160 | // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers |
lypinator | 0:bb348c97df44 | 161 | RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; |
lypinator | 0:bb348c97df44 | 162 | RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; |
lypinator | 0:bb348c97df44 | 163 | RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 180 or 168 MHz |
lypinator | 0:bb348c97df44 | 164 | RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; // 45 or 42 MHz |
lypinator | 0:bb348c97df44 | 165 | RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; // 90 or 84 MHz |
lypinator | 0:bb348c97df44 | 166 | if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) { |
lypinator | 0:bb348c97df44 | 167 | return 0; // FAIL |
lypinator | 0:bb348c97df44 | 168 | } |
lypinator | 0:bb348c97df44 | 169 | |
lypinator | 0:bb348c97df44 | 170 | // HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_3); |
lypinator | 0:bb348c97df44 | 171 | |
lypinator | 0:bb348c97df44 | 172 | return 1; |
lypinator | 0:bb348c97df44 | 173 | } |
lypinator | 0:bb348c97df44 | 174 | #endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */ |
lypinator | 0:bb348c97df44 | 175 | |
lypinator | 0:bb348c97df44 | 176 | #if ((CLOCK_SOURCE) & USE_PLL_HSI) |
lypinator | 0:bb348c97df44 | 177 | /******************************************************************************/ |
lypinator | 0:bb348c97df44 | 178 | /* PLL (clocked by HSI) used as System clock source */ |
lypinator | 0:bb348c97df44 | 179 | /******************************************************************************/ |
lypinator | 0:bb348c97df44 | 180 | uint8_t SetSysClock_PLL_HSI(void) |
lypinator | 0:bb348c97df44 | 181 | { |
lypinator | 0:bb348c97df44 | 182 | RCC_OscInitTypeDef RCC_OscInitStruct; |
lypinator | 0:bb348c97df44 | 183 | RCC_ClkInitTypeDef RCC_ClkInitStruct; |
lypinator | 0:bb348c97df44 | 184 | |
lypinator | 0:bb348c97df44 | 185 | /* The voltage scaling allows optimizing the power consumption when the device is |
lypinator | 0:bb348c97df44 | 186 | clocked below the maximum system frequency, to update the voltage scaling value |
lypinator | 0:bb348c97df44 | 187 | regarding system frequency refer to product datasheet. */ |
lypinator | 0:bb348c97df44 | 188 | __HAL_RCC_PWR_CLK_ENABLE(); |
lypinator | 0:bb348c97df44 | 189 | __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); |
lypinator | 0:bb348c97df44 | 190 | |
lypinator | 0:bb348c97df44 | 191 | // Enable HSI oscillator and activate PLL with HSI as source |
lypinator | 0:bb348c97df44 | 192 | RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE; |
lypinator | 0:bb348c97df44 | 193 | RCC_OscInitStruct.HSIState = RCC_HSI_ON; |
lypinator | 0:bb348c97df44 | 194 | RCC_OscInitStruct.HSEState = RCC_HSE_OFF; |
lypinator | 0:bb348c97df44 | 195 | RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; |
lypinator | 0:bb348c97df44 | 196 | RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; |
lypinator | 0:bb348c97df44 | 197 | RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; |
lypinator | 0:bb348c97df44 | 198 | RCC_OscInitStruct.PLL.PLLM = 8; |
lypinator | 0:bb348c97df44 | 199 | #if (CLOCK_SOURCE_USB) |
lypinator | 0:bb348c97df44 | 200 | RCC_OscInitStruct.PLL.PLLN = 168; |
lypinator | 0:bb348c97df44 | 201 | #else |
lypinator | 0:bb348c97df44 | 202 | RCC_OscInitStruct.PLL.PLLN = 180; |
lypinator | 0:bb348c97df44 | 203 | #endif |
lypinator | 0:bb348c97df44 | 204 | RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // 180 MHz or 168 MHz if CLOCK_SOURCE_USB defined |
lypinator | 0:bb348c97df44 | 205 | RCC_OscInitStruct.PLL.PLLQ = 7; // 48 MHz if CLOCK_SOURCE_USB defined |
lypinator | 0:bb348c97df44 | 206 | if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { |
lypinator | 0:bb348c97df44 | 207 | return 0; // FAIL |
lypinator | 0:bb348c97df44 | 208 | } |
lypinator | 0:bb348c97df44 | 209 | |
lypinator | 0:bb348c97df44 | 210 | // Activate the OverDrive to reach the 180 MHz Frequency |
lypinator | 0:bb348c97df44 | 211 | if (HAL_PWREx_EnableOverDrive() != HAL_OK) { |
lypinator | 0:bb348c97df44 | 212 | return 0; // FAIL |
lypinator | 0:bb348c97df44 | 213 | } |
lypinator | 0:bb348c97df44 | 214 | |
lypinator | 0:bb348c97df44 | 215 | /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ |
lypinator | 0:bb348c97df44 | 216 | RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); |
lypinator | 0:bb348c97df44 | 217 | RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; |
lypinator | 0:bb348c97df44 | 218 | RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 180 or 168 MHz |
lypinator | 0:bb348c97df44 | 219 | RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; // 45 or 42 MHz |
lypinator | 0:bb348c97df44 | 220 | RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; // 90 or 84 MHz |
lypinator | 0:bb348c97df44 | 221 | if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) { |
lypinator | 0:bb348c97df44 | 222 | return 0; // FAIL |
lypinator | 0:bb348c97df44 | 223 | } |
lypinator | 0:bb348c97df44 | 224 | |
lypinator | 0:bb348c97df44 | 225 | // HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_3); |
lypinator | 0:bb348c97df44 | 226 | |
lypinator | 0:bb348c97df44 | 227 | return 1; |
lypinator | 0:bb348c97df44 | 228 | } |
lypinator | 0:bb348c97df44 | 229 | #endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */ |