Initial commit
mbed-dev-master/hal/mbed_itm_api.c@0:bb348c97df44, 2020-09-16 (annotated)
- Committer:
- lypinator
- Date:
- Wed Sep 16 01:11:49 2020 +0000
- Revision:
- 0:bb348c97df44
Added PWM
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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lypinator | 0:bb348c97df44 | 1 | /* mbed Microcontroller Library |
lypinator | 0:bb348c97df44 | 2 | * Copyright (c) 2017 ARM Limited |
lypinator | 0:bb348c97df44 | 3 | * |
lypinator | 0:bb348c97df44 | 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
lypinator | 0:bb348c97df44 | 5 | * you may not use this file except in compliance with the License. |
lypinator | 0:bb348c97df44 | 6 | * You may obtain a copy of the License at |
lypinator | 0:bb348c97df44 | 7 | * |
lypinator | 0:bb348c97df44 | 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
lypinator | 0:bb348c97df44 | 9 | * |
lypinator | 0:bb348c97df44 | 10 | * Unless required by applicable law or agreed to in writing, software |
lypinator | 0:bb348c97df44 | 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
lypinator | 0:bb348c97df44 | 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
lypinator | 0:bb348c97df44 | 13 | * See the License for the specific language governing permissions and |
lypinator | 0:bb348c97df44 | 14 | * limitations under the License. |
lypinator | 0:bb348c97df44 | 15 | */ |
lypinator | 0:bb348c97df44 | 16 | |
lypinator | 0:bb348c97df44 | 17 | #if defined(DEVICE_ITM) |
lypinator | 0:bb348c97df44 | 18 | |
lypinator | 0:bb348c97df44 | 19 | #include "hal/itm_api.h" |
lypinator | 0:bb348c97df44 | 20 | #include "cmsis.h" |
lypinator | 0:bb348c97df44 | 21 | |
lypinator | 0:bb348c97df44 | 22 | #include <stdbool.h> |
lypinator | 0:bb348c97df44 | 23 | |
lypinator | 0:bb348c97df44 | 24 | #ifndef ITM_STIM_FIFOREADY_Msk |
lypinator | 0:bb348c97df44 | 25 | #define ITM_STIM_FIFOREADY_Msk 1 |
lypinator | 0:bb348c97df44 | 26 | #endif |
lypinator | 0:bb348c97df44 | 27 | |
lypinator | 0:bb348c97df44 | 28 | #define ITM_ENABLE_WRITE 0xC5ACCE55 |
lypinator | 0:bb348c97df44 | 29 | |
lypinator | 0:bb348c97df44 | 30 | #define SWO_NRZ 0x02 |
lypinator | 0:bb348c97df44 | 31 | #define SWO_STIMULUS_PORT 0x01 |
lypinator | 0:bb348c97df44 | 32 | |
lypinator | 0:bb348c97df44 | 33 | void mbed_itm_init(void) |
lypinator | 0:bb348c97df44 | 34 | { |
lypinator | 0:bb348c97df44 | 35 | static bool do_init = true; |
lypinator | 0:bb348c97df44 | 36 | |
lypinator | 0:bb348c97df44 | 37 | if (do_init) { |
lypinator | 0:bb348c97df44 | 38 | do_init = false; |
lypinator | 0:bb348c97df44 | 39 | |
lypinator | 0:bb348c97df44 | 40 | itm_init(); |
lypinator | 0:bb348c97df44 | 41 | |
lypinator | 0:bb348c97df44 | 42 | /* Enable write access to ITM registers. */ |
lypinator | 0:bb348c97df44 | 43 | ITM->LAR = ITM_ENABLE_WRITE; |
lypinator | 0:bb348c97df44 | 44 | |
lypinator | 0:bb348c97df44 | 45 | /* Trace Port Interface Selected Pin Protocol Register. */ |
lypinator | 0:bb348c97df44 | 46 | TPI->SPPR = (SWO_NRZ << TPI_SPPR_TXMODE_Pos); |
lypinator | 0:bb348c97df44 | 47 | |
lypinator | 0:bb348c97df44 | 48 | /* Trace Port Interface Formatter and Flush Control Register */ |
lypinator | 0:bb348c97df44 | 49 | TPI->FFCR = (1 << TPI_FFCR_TrigIn_Pos); |
lypinator | 0:bb348c97df44 | 50 | |
lypinator | 0:bb348c97df44 | 51 | /* Data Watchpoint and Trace Control Register */ |
lypinator | 0:bb348c97df44 | 52 | DWT->CTRL = (1 << DWT_CTRL_CYCTAP_Pos) | |
lypinator | 0:bb348c97df44 | 53 | (0xF << DWT_CTRL_POSTINIT_Pos) | |
lypinator | 0:bb348c97df44 | 54 | (0xF << DWT_CTRL_POSTPRESET_Pos) | |
lypinator | 0:bb348c97df44 | 55 | (1 << DWT_CTRL_CYCCNTENA_Pos); |
lypinator | 0:bb348c97df44 | 56 | |
lypinator | 0:bb348c97df44 | 57 | /* Trace Privilege Register. |
lypinator | 0:bb348c97df44 | 58 | * Disable access to trace channel configuration from non-privileged mode. |
lypinator | 0:bb348c97df44 | 59 | */ |
lypinator | 0:bb348c97df44 | 60 | ITM->TPR = 0x0; |
lypinator | 0:bb348c97df44 | 61 | |
lypinator | 0:bb348c97df44 | 62 | /* Trace Control Register */ |
lypinator | 0:bb348c97df44 | 63 | ITM->TCR = (1 << ITM_TCR_TraceBusID_Pos) | |
lypinator | 0:bb348c97df44 | 64 | (1 << ITM_TCR_DWTENA_Pos) | |
lypinator | 0:bb348c97df44 | 65 | (1 << ITM_TCR_SYNCENA_Pos) | |
lypinator | 0:bb348c97df44 | 66 | (1 << ITM_TCR_ITMENA_Pos); |
lypinator | 0:bb348c97df44 | 67 | |
lypinator | 0:bb348c97df44 | 68 | /* Trace Enable Register */ |
lypinator | 0:bb348c97df44 | 69 | ITM->TER = SWO_STIMULUS_PORT; |
lypinator | 0:bb348c97df44 | 70 | } |
lypinator | 0:bb348c97df44 | 71 | } |
lypinator | 0:bb348c97df44 | 72 | |
lypinator | 0:bb348c97df44 | 73 | static void itm_out8(uint32_t port, uint8_t data) |
lypinator | 0:bb348c97df44 | 74 | { |
lypinator | 0:bb348c97df44 | 75 | /* Wait until port is available */ |
lypinator | 0:bb348c97df44 | 76 | while ((ITM->PORT[port].u32 & ITM_STIM_FIFOREADY_Msk) == 0) { |
lypinator | 0:bb348c97df44 | 77 | __NOP(); |
lypinator | 0:bb348c97df44 | 78 | } |
lypinator | 0:bb348c97df44 | 79 | |
lypinator | 0:bb348c97df44 | 80 | /* write data to port */ |
lypinator | 0:bb348c97df44 | 81 | ITM->PORT[port].u8 = data; |
lypinator | 0:bb348c97df44 | 82 | } |
lypinator | 0:bb348c97df44 | 83 | |
lypinator | 0:bb348c97df44 | 84 | static void itm_out32(uint32_t port, uint32_t data) |
lypinator | 0:bb348c97df44 | 85 | { |
lypinator | 0:bb348c97df44 | 86 | /* Wait until port is available */ |
lypinator | 0:bb348c97df44 | 87 | while ((ITM->PORT[port].u32 & ITM_STIM_FIFOREADY_Msk) == 0) { |
lypinator | 0:bb348c97df44 | 88 | __NOP(); |
lypinator | 0:bb348c97df44 | 89 | } |
lypinator | 0:bb348c97df44 | 90 | |
lypinator | 0:bb348c97df44 | 91 | /* write data to port */ |
lypinator | 0:bb348c97df44 | 92 | ITM->PORT[port].u32 = data; |
lypinator | 0:bb348c97df44 | 93 | } |
lypinator | 0:bb348c97df44 | 94 | |
lypinator | 0:bb348c97df44 | 95 | uint32_t mbed_itm_send(uint32_t port, uint32_t data) |
lypinator | 0:bb348c97df44 | 96 | { |
lypinator | 0:bb348c97df44 | 97 | /* Check if ITM and port is enabled */ |
lypinator | 0:bb348c97df44 | 98 | if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ |
lypinator | 0:bb348c97df44 | 99 | ((ITM->TER & (1UL << port)) != 0UL)) { /* ITM Port enabled */ |
lypinator | 0:bb348c97df44 | 100 | itm_out32(port, data); |
lypinator | 0:bb348c97df44 | 101 | } |
lypinator | 0:bb348c97df44 | 102 | |
lypinator | 0:bb348c97df44 | 103 | return data; |
lypinator | 0:bb348c97df44 | 104 | } |
lypinator | 0:bb348c97df44 | 105 | |
lypinator | 0:bb348c97df44 | 106 | void mbed_itm_send_block(uint32_t port, const void *data, size_t len) |
lypinator | 0:bb348c97df44 | 107 | { |
lypinator | 0:bb348c97df44 | 108 | const char *ptr = data; |
lypinator | 0:bb348c97df44 | 109 | |
lypinator | 0:bb348c97df44 | 110 | /* Check if ITM and port is enabled */ |
lypinator | 0:bb348c97df44 | 111 | if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ |
lypinator | 0:bb348c97df44 | 112 | ((ITM->TER & (1UL << port)) != 0UL)) { /* ITM Port enabled */ |
lypinator | 0:bb348c97df44 | 113 | /* Output single byte at a time until data is aligned */ |
lypinator | 0:bb348c97df44 | 114 | while ((((uintptr_t) ptr) & 3) && len != 0) { |
lypinator | 0:bb348c97df44 | 115 | itm_out8(port, *ptr++); |
lypinator | 0:bb348c97df44 | 116 | len--; |
lypinator | 0:bb348c97df44 | 117 | } |
lypinator | 0:bb348c97df44 | 118 | |
lypinator | 0:bb348c97df44 | 119 | /* Output bulk of data one word at a time */ |
lypinator | 0:bb348c97df44 | 120 | while (len >= 4) { |
lypinator | 0:bb348c97df44 | 121 | itm_out32(port, *(const uint32_t *) ptr); |
lypinator | 0:bb348c97df44 | 122 | ptr += 4; |
lypinator | 0:bb348c97df44 | 123 | len -= 4; |
lypinator | 0:bb348c97df44 | 124 | } |
lypinator | 0:bb348c97df44 | 125 | |
lypinator | 0:bb348c97df44 | 126 | /* Output any trailing bytes */ |
lypinator | 0:bb348c97df44 | 127 | while (len != 0) { |
lypinator | 0:bb348c97df44 | 128 | itm_out8(port, *ptr++); |
lypinator | 0:bb348c97df44 | 129 | len--; |
lypinator | 0:bb348c97df44 | 130 | } |
lypinator | 0:bb348c97df44 | 131 | } |
lypinator | 0:bb348c97df44 | 132 | } |
lypinator | 0:bb348c97df44 | 133 | #endif // defined(DEVICE_ITM) |