Diff: mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/device/TOOLCHAIN_IAR/stm32f411xe.icf

Revision:

0:bb348c97df44

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/device/TOOLCHAIN_IAR/stm32f411xe.icf	Wed Sep 16 01:11:49 2020 +0000
@@ -0,0 +1,32 @@
+/* [ROM = 512kb = 0x80000] */
+define symbol __intvec_start__     = 0x08010000;
+define symbol __region_ROM_start__ = 0x08010000;
+define symbol __region_ROM_end__   = 0x0807FFFF;
+
+/* [RAM = 128kb = 0x20000] Vector table dynamic copy: 102 vectors = 408 bytes (0x198) to be reserved in RAM */
+define symbol __NVIC_start__          = 0x20000000;
+define symbol __NVIC_end__            = 0x20000197; /* Aligned on 8 bytes */
+define symbol __region_RAM_start__    = 0x20000198;
+define symbol __region_RAM_end__      = 0x2001FFFF;
+
+/* Memory regions */
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__];
+define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__];
+
+/* Stack and Heap */
+/* Stack: 4kB - 408B for vector table */
+/* Heap: 64kB */
+define symbol __size_cstack__ = 0xe68;
+define symbol __size_heap__   = 0x10000;
+define block CSTACK    with alignment = 8, size = __size_cstack__   { };
+define block HEAP      with alignment = 8, size = __size_heap__     { };
+define block STACKHEAP with fixed order { block HEAP, block CSTACK };
+
+initialize by copy with packing = zeros { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite, block STACKHEAP };