Thomas Lyp / DevLibMemoryController

Initial commit

Dependencies:   FastPWM

mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/system_stm32f4xx.c@0:bb348c97df44, 2020-09-16 (annotated)

Committer:
lypinator
Date:
Wed Sep 16 01:11:49 2020 +0000
Revision:
0:bb348c97df44
Added PWM

Who changed what in which revision?

UserRevisionLine numberNew contents of line
lypinator 0:bb348c97df44 1 /**
lypinator 0:bb348c97df44 2 ******************************************************************************
lypinator 0:bb348c97df44 3 * @file system_stm32f4xx.c
lypinator 0:bb348c97df44 4 * @author MCD Application Team
lypinator 0:bb348c97df44 5 * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
lypinator 0:bb348c97df44 6 *
lypinator 0:bb348c97df44 7 * This file provides two functions and one global variable to be called from
lypinator 0:bb348c97df44 8 * user application:
lypinator 0:bb348c97df44 9 * - SystemInit(): This function is called at startup just after reset and
lypinator 0:bb348c97df44 10 * before branch to main program. This call is made inside
lypinator 0:bb348c97df44 11 * the "startup_stm32f4xx.s" file.
lypinator 0:bb348c97df44 12 *
lypinator 0:bb348c97df44 13 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
lypinator 0:bb348c97df44 14 * by the user application to setup the SysTick
lypinator 0:bb348c97df44 15 * timer or configure other parameters.
lypinator 0:bb348c97df44 16 *
lypinator 0:bb348c97df44 17 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
lypinator 0:bb348c97df44 18 * be called whenever the core clock is changed
lypinator 0:bb348c97df44 19 * during program execution.
lypinator 0:bb348c97df44 20 *
lypinator 0:bb348c97df44 21 *
lypinator 0:bb348c97df44 22 ******************************************************************************
lypinator 0:bb348c97df44 23 * @attention
lypinator 0:bb348c97df44 24 *
lypinator 0:bb348c97df44 25 * <h2><center>&copy; COPYRIGHT 2017 STMicroelectronics</center></h2>
lypinator 0:bb348c97df44 26 *
lypinator 0:bb348c97df44 27 * Redistribution and use in source and binary forms, with or without modification,
lypinator 0:bb348c97df44 28 * are permitted provided that the following conditions are met:
lypinator 0:bb348c97df44 29 * 1. Redistributions of source code must retain the above copyright notice,
lypinator 0:bb348c97df44 30 * this list of conditions and the following disclaimer.
lypinator 0:bb348c97df44 31 * 2. Redistributions in binary form must reproduce the above copyright notice,
lypinator 0:bb348c97df44 32 * this list of conditions and the following disclaimer in the documentation
lypinator 0:bb348c97df44 33 * and/or other materials provided with the distribution.
lypinator 0:bb348c97df44 34 * 3. Neither the name of STMicroelectronics nor the names of its contributors
lypinator 0:bb348c97df44 35 * may be used to endorse or promote products derived from this software
lypinator 0:bb348c97df44 36 * without specific prior written permission.
lypinator 0:bb348c97df44 37 *
lypinator 0:bb348c97df44 38 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
lypinator 0:bb348c97df44 39 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
lypinator 0:bb348c97df44 40 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
lypinator 0:bb348c97df44 41 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
lypinator 0:bb348c97df44 42 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
lypinator 0:bb348c97df44 43 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
lypinator 0:bb348c97df44 44 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
lypinator 0:bb348c97df44 45 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
lypinator 0:bb348c97df44 46 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
lypinator 0:bb348c97df44 47 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
lypinator 0:bb348c97df44 48 *
lypinator 0:bb348c97df44 49 ******************************************************************************
lypinator 0:bb348c97df44 50 */
lypinator 0:bb348c97df44 51
lypinator 0:bb348c97df44 52 /** @addtogroup CMSIS
lypinator 0:bb348c97df44 53 * @{
lypinator 0:bb348c97df44 54 */
lypinator 0:bb348c97df44 55
lypinator 0:bb348c97df44 56 /** @addtogroup stm32f4xx_system
lypinator 0:bb348c97df44 57 * @{
lypinator 0:bb348c97df44 58 */
lypinator 0:bb348c97df44 59
lypinator 0:bb348c97df44 60 /** @addtogroup STM32F4xx_System_Private_Includes
lypinator 0:bb348c97df44 61 * @{
lypinator 0:bb348c97df44 62 */
lypinator 0:bb348c97df44 63
lypinator 0:bb348c97df44 64
lypinator 0:bb348c97df44 65 #include "stm32f4xx.h"
lypinator 0:bb348c97df44 66
lypinator 0:bb348c97df44 67 #if !defined (HSE_VALUE)
lypinator 0:bb348c97df44 68 #define HSE_VALUE ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */
lypinator 0:bb348c97df44 69 #endif /* HSE_VALUE */
lypinator 0:bb348c97df44 70
lypinator 0:bb348c97df44 71 #if !defined (HSI_VALUE)
lypinator 0:bb348c97df44 72 #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
lypinator 0:bb348c97df44 73 #endif /* HSI_VALUE */
lypinator 0:bb348c97df44 74
lypinator 0:bb348c97df44 75 /**
lypinator 0:bb348c97df44 76 * @}
lypinator 0:bb348c97df44 77 */
lypinator 0:bb348c97df44 78
lypinator 0:bb348c97df44 79 /** @addtogroup STM32F4xx_System_Private_TypesDefinitions
lypinator 0:bb348c97df44 80 * @{
lypinator 0:bb348c97df44 81 */
lypinator 0:bb348c97df44 82
lypinator 0:bb348c97df44 83 /**
lypinator 0:bb348c97df44 84 * @}
lypinator 0:bb348c97df44 85 */
lypinator 0:bb348c97df44 86
lypinator 0:bb348c97df44 87 /** @addtogroup STM32F4xx_System_Private_Defines
lypinator 0:bb348c97df44 88 * @{
lypinator 0:bb348c97df44 89 */
lypinator 0:bb348c97df44 90
lypinator 0:bb348c97df44 91 /************************* Miscellaneous Configuration ************************/
lypinator 0:bb348c97df44 92 /*!< Uncomment the following line if you need to use external SRAM or SDRAM as data memory */
lypinator 0:bb348c97df44 93 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\
lypinator 0:bb348c97df44 94 || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
lypinator 0:bb348c97df44 95 || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx)
lypinator 0:bb348c97df44 96 /* #define DATA_IN_ExtSRAM */
lypinator 0:bb348c97df44 97 #endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx ||\
lypinator 0:bb348c97df44 98 STM32F412Zx || STM32F412Vx */
lypinator 0:bb348c97df44 99
lypinator 0:bb348c97df44 100 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
lypinator 0:bb348c97df44 101 || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
lypinator 0:bb348c97df44 102 /* #define DATA_IN_ExtSDRAM */
lypinator 0:bb348c97df44 103 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||\
lypinator 0:bb348c97df44 104 STM32F479xx */
lypinator 0:bb348c97df44 105
lypinator 0:bb348c97df44 106 /*!< Uncomment the following line if you need to relocate your vector Table in
lypinator 0:bb348c97df44 107 Internal SRAM. */
lypinator 0:bb348c97df44 108 /* #define VECT_TAB_SRAM */
lypinator 0:bb348c97df44 109 #define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
lypinator 0:bb348c97df44 110 This value must be a multiple of 0x200. */
lypinator 0:bb348c97df44 111 /******************************************************************************/
lypinator 0:bb348c97df44 112
lypinator 0:bb348c97df44 113 /**
lypinator 0:bb348c97df44 114 * @}
lypinator 0:bb348c97df44 115 */
lypinator 0:bb348c97df44 116
lypinator 0:bb348c97df44 117 /** @addtogroup STM32F4xx_System_Private_Macros
lypinator 0:bb348c97df44 118 * @{
lypinator 0:bb348c97df44 119 */
lypinator 0:bb348c97df44 120
lypinator 0:bb348c97df44 121 /**
lypinator 0:bb348c97df44 122 * @}
lypinator 0:bb348c97df44 123 */
lypinator 0:bb348c97df44 124
lypinator 0:bb348c97df44 125 /** @addtogroup STM32F4xx_System_Private_Variables
lypinator 0:bb348c97df44 126 * @{
lypinator 0:bb348c97df44 127 */
lypinator 0:bb348c97df44 128 /* This variable is updated in three ways:
lypinator 0:bb348c97df44 129 1) by calling CMSIS function SystemCoreClockUpdate()
lypinator 0:bb348c97df44 130 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
lypinator 0:bb348c97df44 131 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
lypinator 0:bb348c97df44 132 Note: If you use this function to configure the system clock; then there
lypinator 0:bb348c97df44 133 is no need to call the 2 first functions listed above, since SystemCoreClock
lypinator 0:bb348c97df44 134 variable is updated automatically.
lypinator 0:bb348c97df44 135 */
lypinator 0:bb348c97df44 136 uint32_t SystemCoreClock = 16000000;
lypinator 0:bb348c97df44 137 const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
lypinator 0:bb348c97df44 138 const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
lypinator 0:bb348c97df44 139 /**
lypinator 0:bb348c97df44 140 * @}
lypinator 0:bb348c97df44 141 */
lypinator 0:bb348c97df44 142
lypinator 0:bb348c97df44 143 /** @addtogroup STM32F4xx_System_Private_FunctionPrototypes
lypinator 0:bb348c97df44 144 * @{
lypinator 0:bb348c97df44 145 */
lypinator 0:bb348c97df44 146
lypinator 0:bb348c97df44 147 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
lypinator 0:bb348c97df44 148 static void SystemInit_ExtMemCtl(void);
lypinator 0:bb348c97df44 149 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
lypinator 0:bb348c97df44 150
lypinator 0:bb348c97df44 151 /**
lypinator 0:bb348c97df44 152 * @}
lypinator 0:bb348c97df44 153 */
lypinator 0:bb348c97df44 154
lypinator 0:bb348c97df44 155 /** @addtogroup STM32F4xx_System_Private_Functions
lypinator 0:bb348c97df44 156 * @{
lypinator 0:bb348c97df44 157 */
lypinator 0:bb348c97df44 158
lypinator 0:bb348c97df44 159 /*+ MBED */
lypinator 0:bb348c97df44 160 #if 0
lypinator 0:bb348c97df44 161 /*- MBED */
lypinator 0:bb348c97df44 162
lypinator 0:bb348c97df44 163 /**
lypinator 0:bb348c97df44 164 * @brief Setup the microcontroller system
lypinator 0:bb348c97df44 165 * Initialize the FPU setting, vector table location and External memory
lypinator 0:bb348c97df44 166 * configuration.
lypinator 0:bb348c97df44 167 * @param None
lypinator 0:bb348c97df44 168 * @retval None
lypinator 0:bb348c97df44 169 */
lypinator 0:bb348c97df44 170 void SystemInit(void)
lypinator 0:bb348c97df44 171 {
lypinator 0:bb348c97df44 172 /* FPU settings ------------------------------------------------------------*/
lypinator 0:bb348c97df44 173 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
lypinator 0:bb348c97df44 174 SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
lypinator 0:bb348c97df44 175 #endif
lypinator 0:bb348c97df44 176 /* Reset the RCC clock configuration to the default reset state ------------*/
lypinator 0:bb348c97df44 177 /* Set HSION bit */
lypinator 0:bb348c97df44 178 RCC->CR |= (uint32_t)0x00000001;
lypinator 0:bb348c97df44 179
lypinator 0:bb348c97df44 180 /* Reset CFGR register */
lypinator 0:bb348c97df44 181 RCC->CFGR = 0x00000000;
lypinator 0:bb348c97df44 182
lypinator 0:bb348c97df44 183 /* Reset HSEON, CSSON and PLLON bits */
lypinator 0:bb348c97df44 184 RCC->CR &= (uint32_t)0xFEF6FFFF;
lypinator 0:bb348c97df44 185
lypinator 0:bb348c97df44 186 /* Reset PLLCFGR register */
lypinator 0:bb348c97df44 187 RCC->PLLCFGR = 0x24003010;
lypinator 0:bb348c97df44 188
lypinator 0:bb348c97df44 189 /* Reset HSEBYP bit */
lypinator 0:bb348c97df44 190 RCC->CR &= (uint32_t)0xFFFBFFFF;
lypinator 0:bb348c97df44 191
lypinator 0:bb348c97df44 192 /* Disable all interrupts */
lypinator 0:bb348c97df44 193 RCC->CIR = 0x00000000;
lypinator 0:bb348c97df44 194
lypinator 0:bb348c97df44 195 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
lypinator 0:bb348c97df44 196 SystemInit_ExtMemCtl();
lypinator 0:bb348c97df44 197 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
lypinator 0:bb348c97df44 198
lypinator 0:bb348c97df44 199 /* Configure the Vector Table location add offset address ------------------*/
lypinator 0:bb348c97df44 200 #ifdef VECT_TAB_SRAM
lypinator 0:bb348c97df44 201 SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
lypinator 0:bb348c97df44 202 #else
lypinator 0:bb348c97df44 203 SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
lypinator 0:bb348c97df44 204 #endif
lypinator 0:bb348c97df44 205 }
lypinator 0:bb348c97df44 206
lypinator 0:bb348c97df44 207 /*+ MBED */
lypinator 0:bb348c97df44 208 #endif
lypinator 0:bb348c97df44 209 /*- MBED */
lypinator 0:bb348c97df44 210
lypinator 0:bb348c97df44 211 /**
lypinator 0:bb348c97df44 212 * @brief Update SystemCoreClock variable according to Clock Register Values.
lypinator 0:bb348c97df44 213 * The SystemCoreClock variable contains the core clock (HCLK), it can
lypinator 0:bb348c97df44 214 * be used by the user application to setup the SysTick timer or configure
lypinator 0:bb348c97df44 215 * other parameters.
lypinator 0:bb348c97df44 216 *
lypinator 0:bb348c97df44 217 * @note Each time the core clock (HCLK) changes, this function must be called
lypinator 0:bb348c97df44 218 * to update SystemCoreClock variable value. Otherwise, any configuration
lypinator 0:bb348c97df44 219 * based on this variable will be incorrect.
lypinator 0:bb348c97df44 220 *
lypinator 0:bb348c97df44 221 * @note - The system frequency computed by this function is not the real
lypinator 0:bb348c97df44 222 * frequency in the chip. It is calculated based on the predefined
lypinator 0:bb348c97df44 223 * constant and the selected clock source:
lypinator 0:bb348c97df44 224 *
lypinator 0:bb348c97df44 225 * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
lypinator 0:bb348c97df44 226 *
lypinator 0:bb348c97df44 227 * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
lypinator 0:bb348c97df44 228 *
lypinator 0:bb348c97df44 229 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
lypinator 0:bb348c97df44 230 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
lypinator 0:bb348c97df44 231 *
lypinator 0:bb348c97df44 232 * (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
lypinator 0:bb348c97df44 233 * 16 MHz) but the real value may vary depending on the variations
lypinator 0:bb348c97df44 234 * in voltage and temperature.
lypinator 0:bb348c97df44 235 *
lypinator 0:bb348c97df44 236 * (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value
lypinator 0:bb348c97df44 237 * depends on the application requirements), user has to ensure that HSE_VALUE
lypinator 0:bb348c97df44 238 * is same as the real frequency of the crystal used. Otherwise, this function
lypinator 0:bb348c97df44 239 * may have wrong result.
lypinator 0:bb348c97df44 240 *
lypinator 0:bb348c97df44 241 * - The result of this function could be not correct when using fractional
lypinator 0:bb348c97df44 242 * value for HSE crystal.
lypinator 0:bb348c97df44 243 *
lypinator 0:bb348c97df44 244 * @param None
lypinator 0:bb348c97df44 245 * @retval None
lypinator 0:bb348c97df44 246 */
lypinator 0:bb348c97df44 247 void SystemCoreClockUpdate(void)
lypinator 0:bb348c97df44 248 {
lypinator 0:bb348c97df44 249 uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
lypinator 0:bb348c97df44 250
lypinator 0:bb348c97df44 251 /* Get SYSCLK source -------------------------------------------------------*/
lypinator 0:bb348c97df44 252 tmp = RCC->CFGR & RCC_CFGR_SWS;
lypinator 0:bb348c97df44 253
lypinator 0:bb348c97df44 254 switch (tmp)
lypinator 0:bb348c97df44 255 {
lypinator 0:bb348c97df44 256 case 0x00: /* HSI used as system clock source */
lypinator 0:bb348c97df44 257 SystemCoreClock = HSI_VALUE;
lypinator 0:bb348c97df44 258 break;
lypinator 0:bb348c97df44 259 case 0x04: /* HSE used as system clock source */
lypinator 0:bb348c97df44 260 SystemCoreClock = HSE_VALUE;
lypinator 0:bb348c97df44 261 break;
lypinator 0:bb348c97df44 262 case 0x08: /* PLL used as system clock source */
lypinator 0:bb348c97df44 263
lypinator 0:bb348c97df44 264 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
lypinator 0:bb348c97df44 265 SYSCLK = PLL_VCO / PLL_P
lypinator 0:bb348c97df44 266 */
lypinator 0:bb348c97df44 267 pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
lypinator 0:bb348c97df44 268 pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
lypinator 0:bb348c97df44 269
lypinator 0:bb348c97df44 270 if (pllsource != 0)
lypinator 0:bb348c97df44 271 {
lypinator 0:bb348c97df44 272 /* HSE used as PLL clock source */
lypinator 0:bb348c97df44 273 pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
lypinator 0:bb348c97df44 274 }
lypinator 0:bb348c97df44 275 else
lypinator 0:bb348c97df44 276 {
lypinator 0:bb348c97df44 277 /* HSI used as PLL clock source */
lypinator 0:bb348c97df44 278 pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
lypinator 0:bb348c97df44 279 }
lypinator 0:bb348c97df44 280
lypinator 0:bb348c97df44 281 pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
lypinator 0:bb348c97df44 282 SystemCoreClock = pllvco/pllp;
lypinator 0:bb348c97df44 283 break;
lypinator 0:bb348c97df44 284 default:
lypinator 0:bb348c97df44 285 SystemCoreClock = HSI_VALUE;
lypinator 0:bb348c97df44 286 break;
lypinator 0:bb348c97df44 287 }
lypinator 0:bb348c97df44 288 /* Compute HCLK frequency --------------------------------------------------*/
lypinator 0:bb348c97df44 289 /* Get HCLK prescaler */
lypinator 0:bb348c97df44 290 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
lypinator 0:bb348c97df44 291 /* HCLK frequency */
lypinator 0:bb348c97df44 292 SystemCoreClock >>= tmp;
lypinator 0:bb348c97df44 293 }
lypinator 0:bb348c97df44 294
lypinator 0:bb348c97df44 295 #if defined (DATA_IN_ExtSRAM) && defined (DATA_IN_ExtSDRAM)
lypinator 0:bb348c97df44 296 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
lypinator 0:bb348c97df44 297 || defined(STM32F469xx) || defined(STM32F479xx)
lypinator 0:bb348c97df44 298 /**
lypinator 0:bb348c97df44 299 * @brief Setup the external memory controller.
lypinator 0:bb348c97df44 300 * Called in startup_stm32f4xx.s before jump to main.
lypinator 0:bb348c97df44 301 * This function configures the external memories (SRAM/SDRAM)
lypinator 0:bb348c97df44 302 * This SRAM/SDRAM will be used as program data memory (including heap and stack).
lypinator 0:bb348c97df44 303 * @param None
lypinator 0:bb348c97df44 304 * @retval None
lypinator 0:bb348c97df44 305 */
lypinator 0:bb348c97df44 306 void SystemInit_ExtMemCtl(void)
lypinator 0:bb348c97df44 307 {
lypinator 0:bb348c97df44 308 __IO uint32_t tmp = 0x00;
lypinator 0:bb348c97df44 309
lypinator 0:bb348c97df44 310 register uint32_t tmpreg = 0, timeout = 0xFFFF;
lypinator 0:bb348c97df44 311 register __IO uint32_t index;
lypinator 0:bb348c97df44 312
lypinator 0:bb348c97df44 313 /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface clock */
lypinator 0:bb348c97df44 314 RCC->AHB1ENR |= 0x000001F8;
lypinator 0:bb348c97df44 315
lypinator 0:bb348c97df44 316 /* Delay after an RCC peripheral clock enabling */
lypinator 0:bb348c97df44 317 tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);
lypinator 0:bb348c97df44 318
lypinator 0:bb348c97df44 319 /* Connect PDx pins to FMC Alternate function */
lypinator 0:bb348c97df44 320 GPIOD->AFR[0] = 0x00CCC0CC;
lypinator 0:bb348c97df44 321 GPIOD->AFR[1] = 0xCCCCCCCC;
lypinator 0:bb348c97df44 322 /* Configure PDx pins in Alternate function mode */
lypinator 0:bb348c97df44 323 GPIOD->MODER = 0xAAAA0A8A;
lypinator 0:bb348c97df44 324 /* Configure PDx pins speed to 100 MHz */
lypinator 0:bb348c97df44 325 GPIOD->OSPEEDR = 0xFFFF0FCF;
lypinator 0:bb348c97df44 326 /* Configure PDx pins Output type to push-pull */
lypinator 0:bb348c97df44 327 GPIOD->OTYPER = 0x00000000;
lypinator 0:bb348c97df44 328 /* No pull-up, pull-down for PDx pins */
lypinator 0:bb348c97df44 329 GPIOD->PUPDR = 0x00000000;
lypinator 0:bb348c97df44 330
lypinator 0:bb348c97df44 331 /* Connect PEx pins to FMC Alternate function */
lypinator 0:bb348c97df44 332 GPIOE->AFR[0] = 0xC00CC0CC;
lypinator 0:bb348c97df44 333 GPIOE->AFR[1] = 0xCCCCCCCC;
lypinator 0:bb348c97df44 334 /* Configure PEx pins in Alternate function mode */
lypinator 0:bb348c97df44 335 GPIOE->MODER = 0xAAAA828A;
lypinator 0:bb348c97df44 336 /* Configure PEx pins speed to 100 MHz */
lypinator 0:bb348c97df44 337 GPIOE->OSPEEDR = 0xFFFFC3CF;
lypinator 0:bb348c97df44 338 /* Configure PEx pins Output type to push-pull */
lypinator 0:bb348c97df44 339 GPIOE->OTYPER = 0x00000000;
lypinator 0:bb348c97df44 340 /* No pull-up, pull-down for PEx pins */
lypinator 0:bb348c97df44 341 GPIOE->PUPDR = 0x00000000;
lypinator 0:bb348c97df44 342
lypinator 0:bb348c97df44 343 /* Connect PFx pins to FMC Alternate function */
lypinator 0:bb348c97df44 344 GPIOF->AFR[0] = 0xCCCCCCCC;
lypinator 0:bb348c97df44 345 GPIOF->AFR[1] = 0xCCCCCCCC;
lypinator 0:bb348c97df44 346 /* Configure PFx pins in Alternate function mode */
lypinator 0:bb348c97df44 347 GPIOF->MODER = 0xAA800AAA;
lypinator 0:bb348c97df44 348 /* Configure PFx pins speed to 50 MHz */
lypinator 0:bb348c97df44 349 GPIOF->OSPEEDR = 0xAA800AAA;
lypinator 0:bb348c97df44 350 /* Configure PFx pins Output type to push-pull */
lypinator 0:bb348c97df44 351 GPIOF->OTYPER = 0x00000000;
lypinator 0:bb348c97df44 352 /* No pull-up, pull-down for PFx pins */
lypinator 0:bb348c97df44 353 GPIOF->PUPDR = 0x00000000;
lypinator 0:bb348c97df44 354
lypinator 0:bb348c97df44 355 /* Connect PGx pins to FMC Alternate function */
lypinator 0:bb348c97df44 356 GPIOG->AFR[0] = 0xCCCCCCCC;
lypinator 0:bb348c97df44 357 GPIOG->AFR[1] = 0xCCCCCCCC;
lypinator 0:bb348c97df44 358 /* Configure PGx pins in Alternate function mode */
lypinator 0:bb348c97df44 359 GPIOG->MODER = 0xAAAAAAAA;
lypinator 0:bb348c97df44 360 /* Configure PGx pins speed to 50 MHz */
lypinator 0:bb348c97df44 361 GPIOG->OSPEEDR = 0xAAAAAAAA;
lypinator 0:bb348c97df44 362 /* Configure PGx pins Output type to push-pull */
lypinator 0:bb348c97df44 363 GPIOG->OTYPER = 0x00000000;
lypinator 0:bb348c97df44 364 /* No pull-up, pull-down for PGx pins */
lypinator 0:bb348c97df44 365 GPIOG->PUPDR = 0x00000000;
lypinator 0:bb348c97df44 366
lypinator 0:bb348c97df44 367 /* Connect PHx pins to FMC Alternate function */
lypinator 0:bb348c97df44 368 GPIOH->AFR[0] = 0x00C0CC00;
lypinator 0:bb348c97df44 369 GPIOH->AFR[1] = 0xCCCCCCCC;
lypinator 0:bb348c97df44 370 /* Configure PHx pins in Alternate function mode */
lypinator 0:bb348c97df44 371 GPIOH->MODER = 0xAAAA08A0;
lypinator 0:bb348c97df44 372 /* Configure PHx pins speed to 50 MHz */
lypinator 0:bb348c97df44 373 GPIOH->OSPEEDR = 0xAAAA08A0;
lypinator 0:bb348c97df44 374 /* Configure PHx pins Output type to push-pull */
lypinator 0:bb348c97df44 375 GPIOH->OTYPER = 0x00000000;
lypinator 0:bb348c97df44 376 /* No pull-up, pull-down for PHx pins */
lypinator 0:bb348c97df44 377 GPIOH->PUPDR = 0x00000000;
lypinator 0:bb348c97df44 378
lypinator 0:bb348c97df44 379 /* Connect PIx pins to FMC Alternate function */
lypinator 0:bb348c97df44 380 GPIOI->AFR[0] = 0xCCCCCCCC;
lypinator 0:bb348c97df44 381 GPIOI->AFR[1] = 0x00000CC0;
lypinator 0:bb348c97df44 382 /* Configure PIx pins in Alternate function mode */
lypinator 0:bb348c97df44 383 GPIOI->MODER = 0x0028AAAA;
lypinator 0:bb348c97df44 384 /* Configure PIx pins speed to 50 MHz */
lypinator 0:bb348c97df44 385 GPIOI->OSPEEDR = 0x0028AAAA;
lypinator 0:bb348c97df44 386 /* Configure PIx pins Output type to push-pull */
lypinator 0:bb348c97df44 387 GPIOI->OTYPER = 0x00000000;
lypinator 0:bb348c97df44 388 /* No pull-up, pull-down for PIx pins */
lypinator 0:bb348c97df44 389 GPIOI->PUPDR = 0x00000000;
lypinator 0:bb348c97df44 390
lypinator 0:bb348c97df44 391 /*-- FMC Configuration -------------------------------------------------------*/
lypinator 0:bb348c97df44 392 /* Enable the FMC interface clock */
lypinator 0:bb348c97df44 393 RCC->AHB3ENR |= 0x00000001;
lypinator 0:bb348c97df44 394 /* Delay after an RCC peripheral clock enabling */
lypinator 0:bb348c97df44 395 tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
lypinator 0:bb348c97df44 396
lypinator 0:bb348c97df44 397 FMC_Bank5_6->SDCR[0] = 0x000019E4;
lypinator 0:bb348c97df44 398 FMC_Bank5_6->SDTR[0] = 0x01115351;
lypinator 0:bb348c97df44 399
lypinator 0:bb348c97df44 400 /* SDRAM initialization sequence */
lypinator 0:bb348c97df44 401 /* Clock enable command */
lypinator 0:bb348c97df44 402 FMC_Bank5_6->SDCMR = 0x00000011;
lypinator 0:bb348c97df44 403 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
lypinator 0:bb348c97df44 404 while((tmpreg != 0) && (timeout-- > 0))
lypinator 0:bb348c97df44 405 {
lypinator 0:bb348c97df44 406 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
lypinator 0:bb348c97df44 407 }
lypinator 0:bb348c97df44 408
lypinator 0:bb348c97df44 409 /* Delay */
lypinator 0:bb348c97df44 410 for (index = 0; index<1000; index++);
lypinator 0:bb348c97df44 411
lypinator 0:bb348c97df44 412 /* PALL command */
lypinator 0:bb348c97df44 413 FMC_Bank5_6->SDCMR = 0x00000012;
lypinator 0:bb348c97df44 414 timeout = 0xFFFF;
lypinator 0:bb348c97df44 415 while((tmpreg != 0) && (timeout-- > 0))
lypinator 0:bb348c97df44 416 {
lypinator 0:bb348c97df44 417 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
lypinator 0:bb348c97df44 418 }
lypinator 0:bb348c97df44 419
lypinator 0:bb348c97df44 420 /* Auto refresh command */
lypinator 0:bb348c97df44 421 FMC_Bank5_6->SDCMR = 0x00000073;
lypinator 0:bb348c97df44 422 timeout = 0xFFFF;
lypinator 0:bb348c97df44 423 while((tmpreg != 0) && (timeout-- > 0))
lypinator 0:bb348c97df44 424 {
lypinator 0:bb348c97df44 425 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
lypinator 0:bb348c97df44 426 }
lypinator 0:bb348c97df44 427
lypinator 0:bb348c97df44 428 /* MRD register program */
lypinator 0:bb348c97df44 429 FMC_Bank5_6->SDCMR = 0x00046014;
lypinator 0:bb348c97df44 430 timeout = 0xFFFF;
lypinator 0:bb348c97df44 431 while((tmpreg != 0) && (timeout-- > 0))
lypinator 0:bb348c97df44 432 {
lypinator 0:bb348c97df44 433 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
lypinator 0:bb348c97df44 434 }
lypinator 0:bb348c97df44 435
lypinator 0:bb348c97df44 436 /* Set refresh count */
lypinator 0:bb348c97df44 437 tmpreg = FMC_Bank5_6->SDRTR;
lypinator 0:bb348c97df44 438 FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1));
lypinator 0:bb348c97df44 439
lypinator 0:bb348c97df44 440 /* Disable write protection */
lypinator 0:bb348c97df44 441 tmpreg = FMC_Bank5_6->SDCR[0];
lypinator 0:bb348c97df44 442 FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
lypinator 0:bb348c97df44 443
lypinator 0:bb348c97df44 444 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
lypinator 0:bb348c97df44 445 /* Configure and enable Bank1_SRAM2 */
lypinator 0:bb348c97df44 446 FMC_Bank1->BTCR[2] = 0x00001011;
lypinator 0:bb348c97df44 447 FMC_Bank1->BTCR[3] = 0x00000201;
lypinator 0:bb348c97df44 448 FMC_Bank1E->BWTR[2] = 0x0fffffff;
lypinator 0:bb348c97df44 449 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
lypinator 0:bb348c97df44 450 #if defined(STM32F469xx) || defined(STM32F479xx)
lypinator 0:bb348c97df44 451 /* Configure and enable Bank1_SRAM2 */
lypinator 0:bb348c97df44 452 FMC_Bank1->BTCR[2] = 0x00001091;
lypinator 0:bb348c97df44 453 FMC_Bank1->BTCR[3] = 0x00110212;
lypinator 0:bb348c97df44 454 FMC_Bank1E->BWTR[2] = 0x0fffffff;
lypinator 0:bb348c97df44 455 #endif /* STM32F469xx || STM32F479xx */
lypinator 0:bb348c97df44 456
lypinator 0:bb348c97df44 457 (void)(tmp);
lypinator 0:bb348c97df44 458 }
lypinator 0:bb348c97df44 459 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
lypinator 0:bb348c97df44 460 #elif defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
lypinator 0:bb348c97df44 461 /**
lypinator 0:bb348c97df44 462 * @brief Setup the external memory controller.
lypinator 0:bb348c97df44 463 * Called in startup_stm32f4xx.s before jump to main.
lypinator 0:bb348c97df44 464 * This function configures the external memories (SRAM/SDRAM)
lypinator 0:bb348c97df44 465 * This SRAM/SDRAM will be used as program data memory (including heap and stack).
lypinator 0:bb348c97df44 466 * @param None
lypinator 0:bb348c97df44 467 * @retval None
lypinator 0:bb348c97df44 468 */
lypinator 0:bb348c97df44 469 void SystemInit_ExtMemCtl(void)
lypinator 0:bb348c97df44 470 {
lypinator 0:bb348c97df44 471 __IO uint32_t tmp = 0x00;
lypinator 0:bb348c97df44 472 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
lypinator 0:bb348c97df44 473 || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
lypinator 0:bb348c97df44 474 #if defined (DATA_IN_ExtSDRAM)
lypinator 0:bb348c97df44 475 register uint32_t tmpreg = 0, timeout = 0xFFFF;
lypinator 0:bb348c97df44 476 register __IO uint32_t index;
lypinator 0:bb348c97df44 477
lypinator 0:bb348c97df44 478 #if defined(STM32F446xx)
lypinator 0:bb348c97df44 479 /* Enable GPIOA, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG interface
lypinator 0:bb348c97df44 480 clock */
lypinator 0:bb348c97df44 481 RCC->AHB1ENR |= 0x0000007D;
lypinator 0:bb348c97df44 482 #else
lypinator 0:bb348c97df44 483 /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface
lypinator 0:bb348c97df44 484 clock */
lypinator 0:bb348c97df44 485 RCC->AHB1ENR |= 0x000001F8;
lypinator 0:bb348c97df44 486 #endif /* STM32F446xx */
lypinator 0:bb348c97df44 487 /* Delay after an RCC peripheral clock enabling */
lypinator 0:bb348c97df44 488 tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);
lypinator 0:bb348c97df44 489
lypinator 0:bb348c97df44 490 #if defined(STM32F446xx)
lypinator 0:bb348c97df44 491 /* Connect PAx pins to FMC Alternate function */
lypinator 0:bb348c97df44 492 GPIOA->AFR[0] |= 0xC0000000;
lypinator 0:bb348c97df44 493 GPIOA->AFR[1] |= 0x00000000;
lypinator 0:bb348c97df44 494 /* Configure PDx pins in Alternate function mode */
lypinator 0:bb348c97df44 495 GPIOA->MODER |= 0x00008000;
lypinator 0:bb348c97df44 496 /* Configure PDx pins speed to 50 MHz */
lypinator 0:bb348c97df44 497 GPIOA->OSPEEDR |= 0x00008000;
lypinator 0:bb348c97df44 498 /* Configure PDx pins Output type to push-pull */
lypinator 0:bb348c97df44 499 GPIOA->OTYPER |= 0x00000000;
lypinator 0:bb348c97df44 500 /* No pull-up, pull-down for PDx pins */
lypinator 0:bb348c97df44 501 GPIOA->PUPDR |= 0x00000000;
lypinator 0:bb348c97df44 502
lypinator 0:bb348c97df44 503 /* Connect PCx pins to FMC Alternate function */
lypinator 0:bb348c97df44 504 GPIOC->AFR[0] |= 0x00CC0000;
lypinator 0:bb348c97df44 505 GPIOC->AFR[1] |= 0x00000000;
lypinator 0:bb348c97df44 506 /* Configure PDx pins in Alternate function mode */
lypinator 0:bb348c97df44 507 GPIOC->MODER |= 0x00000A00;
lypinator 0:bb348c97df44 508 /* Configure PDx pins speed to 50 MHz */
lypinator 0:bb348c97df44 509 GPIOC->OSPEEDR |= 0x00000A00;
lypinator 0:bb348c97df44 510 /* Configure PDx pins Output type to push-pull */
lypinator 0:bb348c97df44 511 GPIOC->OTYPER |= 0x00000000;
lypinator 0:bb348c97df44 512 /* No pull-up, pull-down for PDx pins */
lypinator 0:bb348c97df44 513 GPIOC->PUPDR |= 0x00000000;
lypinator 0:bb348c97df44 514 #endif /* STM32F446xx */
lypinator 0:bb348c97df44 515
lypinator 0:bb348c97df44 516 /* Connect PDx pins to FMC Alternate function */
lypinator 0:bb348c97df44 517 GPIOD->AFR[0] = 0x000000CC;
lypinator 0:bb348c97df44 518 GPIOD->AFR[1] = 0xCC000CCC;
lypinator 0:bb348c97df44 519 /* Configure PDx pins in Alternate function mode */
lypinator 0:bb348c97df44 520 GPIOD->MODER = 0xA02A000A;
lypinator 0:bb348c97df44 521 /* Configure PDx pins speed to 50 MHz */
lypinator 0:bb348c97df44 522 GPIOD->OSPEEDR = 0xA02A000A;
lypinator 0:bb348c97df44 523 /* Configure PDx pins Output type to push-pull */
lypinator 0:bb348c97df44 524 GPIOD->OTYPER = 0x00000000;
lypinator 0:bb348c97df44 525 /* No pull-up, pull-down for PDx pins */
lypinator 0:bb348c97df44 526 GPIOD->PUPDR = 0x00000000;
lypinator 0:bb348c97df44 527
lypinator 0:bb348c97df44 528 /* Connect PEx pins to FMC Alternate function */
lypinator 0:bb348c97df44 529 GPIOE->AFR[0] = 0xC00000CC;
lypinator 0:bb348c97df44 530 GPIOE->AFR[1] = 0xCCCCCCCC;
lypinator 0:bb348c97df44 531 /* Configure PEx pins in Alternate function mode */
lypinator 0:bb348c97df44 532 GPIOE->MODER = 0xAAAA800A;
lypinator 0:bb348c97df44 533 /* Configure PEx pins speed to 50 MHz */
lypinator 0:bb348c97df44 534 GPIOE->OSPEEDR = 0xAAAA800A;
lypinator 0:bb348c97df44 535 /* Configure PEx pins Output type to push-pull */
lypinator 0:bb348c97df44 536 GPIOE->OTYPER = 0x00000000;
lypinator 0:bb348c97df44 537 /* No pull-up, pull-down for PEx pins */
lypinator 0:bb348c97df44 538 GPIOE->PUPDR = 0x00000000;
lypinator 0:bb348c97df44 539
lypinator 0:bb348c97df44 540 /* Connect PFx pins to FMC Alternate function */
lypinator 0:bb348c97df44 541 GPIOF->AFR[0] = 0xCCCCCCCC;
lypinator 0:bb348c97df44 542 GPIOF->AFR[1] = 0xCCCCCCCC;
lypinator 0:bb348c97df44 543 /* Configure PFx pins in Alternate function mode */
lypinator 0:bb348c97df44 544 GPIOF->MODER = 0xAA800AAA;
lypinator 0:bb348c97df44 545 /* Configure PFx pins speed to 50 MHz */
lypinator 0:bb348c97df44 546 GPIOF->OSPEEDR = 0xAA800AAA;
lypinator 0:bb348c97df44 547 /* Configure PFx pins Output type to push-pull */
lypinator 0:bb348c97df44 548 GPIOF->OTYPER = 0x00000000;
lypinator 0:bb348c97df44 549 /* No pull-up, pull-down for PFx pins */
lypinator 0:bb348c97df44 550 GPIOF->PUPDR = 0x00000000;
lypinator 0:bb348c97df44 551
lypinator 0:bb348c97df44 552 /* Connect PGx pins to FMC Alternate function */
lypinator 0:bb348c97df44 553 GPIOG->AFR[0] = 0xCCCCCCCC;
lypinator 0:bb348c97df44 554 GPIOG->AFR[1] = 0xCCCCCCCC;
lypinator 0:bb348c97df44 555 /* Configure PGx pins in Alternate function mode */
lypinator 0:bb348c97df44 556 GPIOG->MODER = 0xAAAAAAAA;
lypinator 0:bb348c97df44 557 /* Configure PGx pins speed to 50 MHz */
lypinator 0:bb348c97df44 558 GPIOG->OSPEEDR = 0xAAAAAAAA;
lypinator 0:bb348c97df44 559 /* Configure PGx pins Output type to push-pull */
lypinator 0:bb348c97df44 560 GPIOG->OTYPER = 0x00000000;
lypinator 0:bb348c97df44 561 /* No pull-up, pull-down for PGx pins */
lypinator 0:bb348c97df44 562 GPIOG->PUPDR = 0x00000000;
lypinator 0:bb348c97df44 563
lypinator 0:bb348c97df44 564 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
lypinator 0:bb348c97df44 565 || defined(STM32F469xx) || defined(STM32F479xx)
lypinator 0:bb348c97df44 566 /* Connect PHx pins to FMC Alternate function */
lypinator 0:bb348c97df44 567 GPIOH->AFR[0] = 0x00C0CC00;
lypinator 0:bb348c97df44 568 GPIOH->AFR[1] = 0xCCCCCCCC;
lypinator 0:bb348c97df44 569 /* Configure PHx pins in Alternate function mode */
lypinator 0:bb348c97df44 570 GPIOH->MODER = 0xAAAA08A0;
lypinator 0:bb348c97df44 571 /* Configure PHx pins speed to 50 MHz */
lypinator 0:bb348c97df44 572 GPIOH->OSPEEDR = 0xAAAA08A0;
lypinator 0:bb348c97df44 573 /* Configure PHx pins Output type to push-pull */
lypinator 0:bb348c97df44 574 GPIOH->OTYPER = 0x00000000;
lypinator 0:bb348c97df44 575 /* No pull-up, pull-down for PHx pins */
lypinator 0:bb348c97df44 576 GPIOH->PUPDR = 0x00000000;
lypinator 0:bb348c97df44 577
lypinator 0:bb348c97df44 578 /* Connect PIx pins to FMC Alternate function */
lypinator 0:bb348c97df44 579 GPIOI->AFR[0] = 0xCCCCCCCC;
lypinator 0:bb348c97df44 580 GPIOI->AFR[1] = 0x00000CC0;
lypinator 0:bb348c97df44 581 /* Configure PIx pins in Alternate function mode */
lypinator 0:bb348c97df44 582 GPIOI->MODER = 0x0028AAAA;
lypinator 0:bb348c97df44 583 /* Configure PIx pins speed to 50 MHz */
lypinator 0:bb348c97df44 584 GPIOI->OSPEEDR = 0x0028AAAA;
lypinator 0:bb348c97df44 585 /* Configure PIx pins Output type to push-pull */
lypinator 0:bb348c97df44 586 GPIOI->OTYPER = 0x00000000;
lypinator 0:bb348c97df44 587 /* No pull-up, pull-down for PIx pins */
lypinator 0:bb348c97df44 588 GPIOI->PUPDR = 0x00000000;
lypinator 0:bb348c97df44 589 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
lypinator 0:bb348c97df44 590
lypinator 0:bb348c97df44 591 /*-- FMC Configuration -------------------------------------------------------*/
lypinator 0:bb348c97df44 592 /* Enable the FMC interface clock */
lypinator 0:bb348c97df44 593 RCC->AHB3ENR |= 0x00000001;
lypinator 0:bb348c97df44 594 /* Delay after an RCC peripheral clock enabling */
lypinator 0:bb348c97df44 595 tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
lypinator 0:bb348c97df44 596
lypinator 0:bb348c97df44 597 /* Configure and enable SDRAM bank1 */
lypinator 0:bb348c97df44 598 #if defined(STM32F446xx)
lypinator 0:bb348c97df44 599 FMC_Bank5_6->SDCR[0] = 0x00001954;
lypinator 0:bb348c97df44 600 #else
lypinator 0:bb348c97df44 601 FMC_Bank5_6->SDCR[0] = 0x000019E4;
lypinator 0:bb348c97df44 602 #endif /* STM32F446xx */
lypinator 0:bb348c97df44 603 FMC_Bank5_6->SDTR[0] = 0x01115351;
lypinator 0:bb348c97df44 604
lypinator 0:bb348c97df44 605 /* SDRAM initialization sequence */
lypinator 0:bb348c97df44 606 /* Clock enable command */
lypinator 0:bb348c97df44 607 FMC_Bank5_6->SDCMR = 0x00000011;
lypinator 0:bb348c97df44 608 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
lypinator 0:bb348c97df44 609 while((tmpreg != 0) && (timeout-- > 0))
lypinator 0:bb348c97df44 610 {
lypinator 0:bb348c97df44 611 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
lypinator 0:bb348c97df44 612 }
lypinator 0:bb348c97df44 613
lypinator 0:bb348c97df44 614 /* Delay */
lypinator 0:bb348c97df44 615 for (index = 0; index<1000; index++);
lypinator 0:bb348c97df44 616
lypinator 0:bb348c97df44 617 /* PALL command */
lypinator 0:bb348c97df44 618 FMC_Bank5_6->SDCMR = 0x00000012;
lypinator 0:bb348c97df44 619 timeout = 0xFFFF;
lypinator 0:bb348c97df44 620 while((tmpreg != 0) && (timeout-- > 0))
lypinator 0:bb348c97df44 621 {
lypinator 0:bb348c97df44 622 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
lypinator 0:bb348c97df44 623 }
lypinator 0:bb348c97df44 624
lypinator 0:bb348c97df44 625 /* Auto refresh command */
lypinator 0:bb348c97df44 626 #if defined(STM32F446xx)
lypinator 0:bb348c97df44 627 FMC_Bank5_6->SDCMR = 0x000000F3;
lypinator 0:bb348c97df44 628 #else
lypinator 0:bb348c97df44 629 FMC_Bank5_6->SDCMR = 0x00000073;
lypinator 0:bb348c97df44 630 #endif /* STM32F446xx */
lypinator 0:bb348c97df44 631 timeout = 0xFFFF;
lypinator 0:bb348c97df44 632 while((tmpreg != 0) && (timeout-- > 0))
lypinator 0:bb348c97df44 633 {
lypinator 0:bb348c97df44 634 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
lypinator 0:bb348c97df44 635 }
lypinator 0:bb348c97df44 636
lypinator 0:bb348c97df44 637 /* MRD register program */
lypinator 0:bb348c97df44 638 #if defined(STM32F446xx)
lypinator 0:bb348c97df44 639 FMC_Bank5_6->SDCMR = 0x00044014;
lypinator 0:bb348c97df44 640 #else
lypinator 0:bb348c97df44 641 FMC_Bank5_6->SDCMR = 0x00046014;
lypinator 0:bb348c97df44 642 #endif /* STM32F446xx */
lypinator 0:bb348c97df44 643 timeout = 0xFFFF;
lypinator 0:bb348c97df44 644 while((tmpreg != 0) && (timeout-- > 0))
lypinator 0:bb348c97df44 645 {
lypinator 0:bb348c97df44 646 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
lypinator 0:bb348c97df44 647 }
lypinator 0:bb348c97df44 648
lypinator 0:bb348c97df44 649 /* Set refresh count */
lypinator 0:bb348c97df44 650 tmpreg = FMC_Bank5_6->SDRTR;
lypinator 0:bb348c97df44 651 #if defined(STM32F446xx)
lypinator 0:bb348c97df44 652 FMC_Bank5_6->SDRTR = (tmpreg | (0x0000050C<<1));
lypinator 0:bb348c97df44 653 #else
lypinator 0:bb348c97df44 654 FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1));
lypinator 0:bb348c97df44 655 #endif /* STM32F446xx */
lypinator 0:bb348c97df44 656
lypinator 0:bb348c97df44 657 /* Disable write protection */
lypinator 0:bb348c97df44 658 tmpreg = FMC_Bank5_6->SDCR[0];
lypinator 0:bb348c97df44 659 FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
lypinator 0:bb348c97df44 660 #endif /* DATA_IN_ExtSDRAM */
lypinator 0:bb348c97df44 661 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
lypinator 0:bb348c97df44 662
lypinator 0:bb348c97df44 663 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\
lypinator 0:bb348c97df44 664 || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
lypinator 0:bb348c97df44 665 || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx)
lypinator 0:bb348c97df44 666
lypinator 0:bb348c97df44 667 #if defined(DATA_IN_ExtSRAM)
lypinator 0:bb348c97df44 668 /*-- GPIOs Configuration -----------------------------------------------------*/
lypinator 0:bb348c97df44 669 /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
lypinator 0:bb348c97df44 670 RCC->AHB1ENR |= 0x00000078;
lypinator 0:bb348c97df44 671 /* Delay after an RCC peripheral clock enabling */
lypinator 0:bb348c97df44 672 tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);
lypinator 0:bb348c97df44 673
lypinator 0:bb348c97df44 674 /* Connect PDx pins to FMC Alternate function */
lypinator 0:bb348c97df44 675 GPIOD->AFR[0] = 0x00CCC0CC;
lypinator 0:bb348c97df44 676 GPIOD->AFR[1] = 0xCCCCCCCC;
lypinator 0:bb348c97df44 677 /* Configure PDx pins in Alternate function mode */
lypinator 0:bb348c97df44 678 GPIOD->MODER = 0xAAAA0A8A;
lypinator 0:bb348c97df44 679 /* Configure PDx pins speed to 100 MHz */
lypinator 0:bb348c97df44 680 GPIOD->OSPEEDR = 0xFFFF0FCF;
lypinator 0:bb348c97df44 681 /* Configure PDx pins Output type to push-pull */
lypinator 0:bb348c97df44 682 GPIOD->OTYPER = 0x00000000;
lypinator 0:bb348c97df44 683 /* No pull-up, pull-down for PDx pins */
lypinator 0:bb348c97df44 684 GPIOD->PUPDR = 0x00000000;
lypinator 0:bb348c97df44 685
lypinator 0:bb348c97df44 686 /* Connect PEx pins to FMC Alternate function */
lypinator 0:bb348c97df44 687 GPIOE->AFR[0] = 0xC00CC0CC;
lypinator 0:bb348c97df44 688 GPIOE->AFR[1] = 0xCCCCCCCC;
lypinator 0:bb348c97df44 689 /* Configure PEx pins in Alternate function mode */
lypinator 0:bb348c97df44 690 GPIOE->MODER = 0xAAAA828A;
lypinator 0:bb348c97df44 691 /* Configure PEx pins speed to 100 MHz */
lypinator 0:bb348c97df44 692 GPIOE->OSPEEDR = 0xFFFFC3CF;
lypinator 0:bb348c97df44 693 /* Configure PEx pins Output type to push-pull */
lypinator 0:bb348c97df44 694 GPIOE->OTYPER = 0x00000000;
lypinator 0:bb348c97df44 695 /* No pull-up, pull-down for PEx pins */
lypinator 0:bb348c97df44 696 GPIOE->PUPDR = 0x00000000;
lypinator 0:bb348c97df44 697
lypinator 0:bb348c97df44 698 /* Connect PFx pins to FMC Alternate function */
lypinator 0:bb348c97df44 699 GPIOF->AFR[0] = 0x00CCCCCC;
lypinator 0:bb348c97df44 700 GPIOF->AFR[1] = 0xCCCC0000;
lypinator 0:bb348c97df44 701 /* Configure PFx pins in Alternate function mode */
lypinator 0:bb348c97df44 702 GPIOF->MODER = 0xAA000AAA;
lypinator 0:bb348c97df44 703 /* Configure PFx pins speed to 100 MHz */
lypinator 0:bb348c97df44 704 GPIOF->OSPEEDR = 0xFF000FFF;
lypinator 0:bb348c97df44 705 /* Configure PFx pins Output type to push-pull */
lypinator 0:bb348c97df44 706 GPIOF->OTYPER = 0x00000000;
lypinator 0:bb348c97df44 707 /* No pull-up, pull-down for PFx pins */
lypinator 0:bb348c97df44 708 GPIOF->PUPDR = 0x00000000;
lypinator 0:bb348c97df44 709
lypinator 0:bb348c97df44 710 /* Connect PGx pins to FMC Alternate function */
lypinator 0:bb348c97df44 711 GPIOG->AFR[0] = 0x00CCCCCC;
lypinator 0:bb348c97df44 712 GPIOG->AFR[1] = 0x000000C0;
lypinator 0:bb348c97df44 713 /* Configure PGx pins in Alternate function mode */
lypinator 0:bb348c97df44 714 GPIOG->MODER = 0x00085AAA;
lypinator 0:bb348c97df44 715 /* Configure PGx pins speed to 100 MHz */
lypinator 0:bb348c97df44 716 GPIOG->OSPEEDR = 0x000CAFFF;
lypinator 0:bb348c97df44 717 /* Configure PGx pins Output type to push-pull */
lypinator 0:bb348c97df44 718 GPIOG->OTYPER = 0x00000000;
lypinator 0:bb348c97df44 719 /* No pull-up, pull-down for PGx pins */
lypinator 0:bb348c97df44 720 GPIOG->PUPDR = 0x00000000;
lypinator 0:bb348c97df44 721
lypinator 0:bb348c97df44 722 /*-- FMC/FSMC Configuration --------------------------------------------------*/
lypinator 0:bb348c97df44 723 /* Enable the FMC/FSMC interface clock */
lypinator 0:bb348c97df44 724 RCC->AHB3ENR |= 0x00000001;
lypinator 0:bb348c97df44 725
lypinator 0:bb348c97df44 726 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
lypinator 0:bb348c97df44 727 /* Delay after an RCC peripheral clock enabling */
lypinator 0:bb348c97df44 728 tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
lypinator 0:bb348c97df44 729 /* Configure and enable Bank1_SRAM2 */
lypinator 0:bb348c97df44 730 FMC_Bank1->BTCR[2] = 0x00001011;
lypinator 0:bb348c97df44 731 FMC_Bank1->BTCR[3] = 0x00000201;
lypinator 0:bb348c97df44 732 FMC_Bank1E->BWTR[2] = 0x0fffffff;
lypinator 0:bb348c97df44 733 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
lypinator 0:bb348c97df44 734 #if defined(STM32F469xx) || defined(STM32F479xx)
lypinator 0:bb348c97df44 735 /* Delay after an RCC peripheral clock enabling */
lypinator 0:bb348c97df44 736 tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
lypinator 0:bb348c97df44 737 /* Configure and enable Bank1_SRAM2 */
lypinator 0:bb348c97df44 738 FMC_Bank1->BTCR[2] = 0x00001091;
lypinator 0:bb348c97df44 739 FMC_Bank1->BTCR[3] = 0x00110212;
lypinator 0:bb348c97df44 740 FMC_Bank1E->BWTR[2] = 0x0fffffff;
lypinator 0:bb348c97df44 741 #endif /* STM32F469xx || STM32F479xx */
lypinator 0:bb348c97df44 742 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)\
lypinator 0:bb348c97df44 743 || defined(STM32F412Zx) || defined(STM32F412Vx)
lypinator 0:bb348c97df44 744 /* Delay after an RCC peripheral clock enabling */
lypinator 0:bb348c97df44 745 tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);
lypinator 0:bb348c97df44 746 /* Configure and enable Bank1_SRAM2 */
lypinator 0:bb348c97df44 747 FSMC_Bank1->BTCR[2] = 0x00001011;
lypinator 0:bb348c97df44 748 FSMC_Bank1->BTCR[3] = 0x00000201;
lypinator 0:bb348c97df44 749 FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF;
lypinator 0:bb348c97df44 750 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx */
lypinator 0:bb348c97df44 751
lypinator 0:bb348c97df44 752 #endif /* DATA_IN_ExtSRAM */
lypinator 0:bb348c97df44 753 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\
lypinator 0:bb348c97df44 754 STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx */
lypinator 0:bb348c97df44 755 (void)(tmp);
lypinator 0:bb348c97df44 756 }
lypinator 0:bb348c97df44 757 #endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */
lypinator 0:bb348c97df44 758 /**
lypinator 0:bb348c97df44 759 * @}
lypinator 0:bb348c97df44 760 */
lypinator 0:bb348c97df44 761
lypinator 0:bb348c97df44 762 /**
lypinator 0:bb348c97df44 763 * @}
lypinator 0:bb348c97df44 764 */
lypinator 0:bb348c97df44 765
lypinator 0:bb348c97df44 766 /**
lypinator 0:bb348c97df44 767 * @}
lypinator 0:bb348c97df44 768 */
lypinator 0:bb348c97df44 769 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/