Thomas Lyp / DevLibMemoryController

Initial commit

Dependencies:   FastPWM

mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_utils.c@0:bb348c97df44, 2020-09-16 (annotated)

Committer:
lypinator
Date:
Wed Sep 16 01:11:49 2020 +0000
Revision:
0:bb348c97df44
Added PWM

Who changed what in which revision?

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lypinator 0:bb348c97df44 1 /**
lypinator 0:bb348c97df44 2 ******************************************************************************
lypinator 0:bb348c97df44 3 * @file stm32f4xx_ll_utils.c
lypinator 0:bb348c97df44 4 * @author MCD Application Team
lypinator 0:bb348c97df44 5 * @brief UTILS LL module driver.
lypinator 0:bb348c97df44 6 ******************************************************************************
lypinator 0:bb348c97df44 7 * @attention
lypinator 0:bb348c97df44 8 *
lypinator 0:bb348c97df44 9 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
lypinator 0:bb348c97df44 10 *
lypinator 0:bb348c97df44 11 * Redistribution and use in source and binary forms, with or without modification,
lypinator 0:bb348c97df44 12 * are permitted provided that the following conditions are met:
lypinator 0:bb348c97df44 13 * 1. Redistributions of source code must retain the above copyright notice,
lypinator 0:bb348c97df44 14 * this list of conditions and the following disclaimer.
lypinator 0:bb348c97df44 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
lypinator 0:bb348c97df44 16 * this list of conditions and the following disclaimer in the documentation
lypinator 0:bb348c97df44 17 * and/or other materials provided with the distribution.
lypinator 0:bb348c97df44 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
lypinator 0:bb348c97df44 19 * may be used to endorse or promote products derived from this software
lypinator 0:bb348c97df44 20 * without specific prior written permission.
lypinator 0:bb348c97df44 21 *
lypinator 0:bb348c97df44 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
lypinator 0:bb348c97df44 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
lypinator 0:bb348c97df44 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
lypinator 0:bb348c97df44 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
lypinator 0:bb348c97df44 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
lypinator 0:bb348c97df44 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
lypinator 0:bb348c97df44 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
lypinator 0:bb348c97df44 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
lypinator 0:bb348c97df44 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
lypinator 0:bb348c97df44 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
lypinator 0:bb348c97df44 32 *
lypinator 0:bb348c97df44 33 ******************************************************************************
lypinator 0:bb348c97df44 34 */
lypinator 0:bb348c97df44 35 /* Includes ------------------------------------------------------------------*/
lypinator 0:bb348c97df44 36 #include "stm32f4xx_ll_utils.h"
lypinator 0:bb348c97df44 37 #include "stm32f4xx_ll_rcc.h"
lypinator 0:bb348c97df44 38 #include "stm32f4xx_ll_system.h"
lypinator 0:bb348c97df44 39 #include "stm32f4xx_ll_pwr.h"
lypinator 0:bb348c97df44 40
lypinator 0:bb348c97df44 41 /** @addtogroup STM32F4xx_LL_Driver
lypinator 0:bb348c97df44 42 * @{
lypinator 0:bb348c97df44 43 */
lypinator 0:bb348c97df44 44
lypinator 0:bb348c97df44 45 /** @addtogroup UTILS_LL
lypinator 0:bb348c97df44 46 * @{
lypinator 0:bb348c97df44 47 */
lypinator 0:bb348c97df44 48
lypinator 0:bb348c97df44 49 /* Private types -------------------------------------------------------------*/
lypinator 0:bb348c97df44 50 /* Private variables ---------------------------------------------------------*/
lypinator 0:bb348c97df44 51 /* Private constants ---------------------------------------------------------*/
lypinator 0:bb348c97df44 52 /** @addtogroup UTILS_LL_Private_Constants
lypinator 0:bb348c97df44 53 * @{
lypinator 0:bb348c97df44 54 */
lypinator 0:bb348c97df44 55 #if defined(RCC_MAX_FREQUENCY_SCALE1)
lypinator 0:bb348c97df44 56 #define UTILS_MAX_FREQUENCY_SCALE1 RCC_MAX_FREQUENCY /*!< Maximum frequency for system clock at power scale1, in Hz */
lypinator 0:bb348c97df44 57 #endif /*RCC_MAX_FREQUENCY_SCALE1 */
lypinator 0:bb348c97df44 58 #define UTILS_MAX_FREQUENCY_SCALE2 RCC_MAX_FREQUENCY_SCALE2 /*!< Maximum frequency for system clock at power scale2, in Hz */
lypinator 0:bb348c97df44 59 #if defined(RCC_MAX_FREQUENCY_SCALE3)
lypinator 0:bb348c97df44 60 #define UTILS_MAX_FREQUENCY_SCALE3 RCC_MAX_FREQUENCY_SCALE3 /*!< Maximum frequency for system clock at power scale3, in Hz */
lypinator 0:bb348c97df44 61 #endif /* MAX_FREQUENCY_SCALE3 */
lypinator 0:bb348c97df44 62
lypinator 0:bb348c97df44 63 /* Defines used for PLL range */
lypinator 0:bb348c97df44 64 #define UTILS_PLLVCO_INPUT_MIN RCC_PLLVCO_INPUT_MIN /*!< Frequency min for PLLVCO input, in Hz */
lypinator 0:bb348c97df44 65 #define UTILS_PLLVCO_INPUT_MAX RCC_PLLVCO_INPUT_MAX /*!< Frequency max for PLLVCO input, in Hz */
lypinator 0:bb348c97df44 66 #define UTILS_PLLVCO_OUTPUT_MIN RCC_PLLVCO_OUTPUT_MIN /*!< Frequency min for PLLVCO output, in Hz */
lypinator 0:bb348c97df44 67 #define UTILS_PLLVCO_OUTPUT_MAX RCC_PLLVCO_OUTPUT_MAX /*!< Frequency max for PLLVCO output, in Hz */
lypinator 0:bb348c97df44 68
lypinator 0:bb348c97df44 69 /* Defines used for HSE range */
lypinator 0:bb348c97df44 70 #define UTILS_HSE_FREQUENCY_MIN 4000000U /*!< Frequency min for HSE frequency, in Hz */
lypinator 0:bb348c97df44 71 #define UTILS_HSE_FREQUENCY_MAX 26000000U /*!< Frequency max for HSE frequency, in Hz */
lypinator 0:bb348c97df44 72
lypinator 0:bb348c97df44 73 /* Defines used for FLASH latency according to HCLK Frequency */
lypinator 0:bb348c97df44 74 #if defined(FLASH_SCALE1_LATENCY1_FREQ)
lypinator 0:bb348c97df44 75 #define UTILS_SCALE1_LATENCY1_FREQ FLASH_SCALE1_LATENCY1_FREQ /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */
lypinator 0:bb348c97df44 76 #endif
lypinator 0:bb348c97df44 77 #if defined(FLASH_SCALE1_LATENCY2_FREQ)
lypinator 0:bb348c97df44 78 #define UTILS_SCALE1_LATENCY2_FREQ FLASH_SCALE1_LATENCY2_FREQ /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */
lypinator 0:bb348c97df44 79 #endif
lypinator 0:bb348c97df44 80 #if defined(FLASH_SCALE1_LATENCY3_FREQ)
lypinator 0:bb348c97df44 81 #define UTILS_SCALE1_LATENCY3_FREQ FLASH_SCALE1_LATENCY3_FREQ /*!< HCLK frequency to set FLASH latency 3 in power scale 1 */
lypinator 0:bb348c97df44 82 #endif
lypinator 0:bb348c97df44 83 #if defined(FLASH_SCALE1_LATENCY4_FREQ)
lypinator 0:bb348c97df44 84 #define UTILS_SCALE1_LATENCY4_FREQ FLASH_SCALE1_LATENCY4_FREQ /*!< HCLK frequency to set FLASH latency 4 in power scale 1 */
lypinator 0:bb348c97df44 85 #endif
lypinator 0:bb348c97df44 86 #if defined(FLASH_SCALE1_LATENCY5_FREQ)
lypinator 0:bb348c97df44 87 #define UTILS_SCALE1_LATENCY5_FREQ FLASH_SCALE1_LATENCY5_FREQ /*!< HCLK frequency to set FLASH latency 5 in power scale 1 */
lypinator 0:bb348c97df44 88 #endif
lypinator 0:bb348c97df44 89 #define UTILS_SCALE2_LATENCY1_FREQ FLASH_SCALE2_LATENCY1_FREQ /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */
lypinator 0:bb348c97df44 90 #define UTILS_SCALE2_LATENCY2_FREQ FLASH_SCALE2_LATENCY2_FREQ /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */
lypinator 0:bb348c97df44 91 #if defined(FLASH_SCALE2_LATENCY3_FREQ)
lypinator 0:bb348c97df44 92 #define UTILS_SCALE2_LATENCY3_FREQ FLASH_SCALE2_LATENCY3_FREQ /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */
lypinator 0:bb348c97df44 93 #endif
lypinator 0:bb348c97df44 94 #if defined(FLASH_SCALE2_LATENCY4_FREQ)
lypinator 0:bb348c97df44 95 #define UTILS_SCALE2_LATENCY4_FREQ FLASH_SCALE2_LATENCY4_FREQ /*!< HCLK frequency to set FLASH latency 4 in power scale 2 */
lypinator 0:bb348c97df44 96 #endif
lypinator 0:bb348c97df44 97 #if defined(FLASH_SCALE2_LATENCY5_FREQ)
lypinator 0:bb348c97df44 98 #define UTILS_SCALE2_LATENCY5_FREQ FLASH_SCALE2_LATENCY5_FREQ /*!< HCLK frequency to set FLASH latency 5 in power scale 2 */
lypinator 0:bb348c97df44 99 #endif
lypinator 0:bb348c97df44 100 #if defined(FLASH_SCALE3_LATENCY1_FREQ)
lypinator 0:bb348c97df44 101 #define UTILS_SCALE3_LATENCY1_FREQ FLASH_SCALE3_LATENCY1_FREQ /*!< HCLK frequency to set FLASH latency 1 in power scale 3 */
lypinator 0:bb348c97df44 102 #endif
lypinator 0:bb348c97df44 103 #if defined(FLASH_SCALE3_LATENCY2_FREQ)
lypinator 0:bb348c97df44 104 #define UTILS_SCALE3_LATENCY2_FREQ FLASH_SCALE3_LATENCY2_FREQ /*!< HCLK frequency to set FLASH latency 2 in power scale 3 */
lypinator 0:bb348c97df44 105 #endif
lypinator 0:bb348c97df44 106 #if defined(FLASH_SCALE3_LATENCY3_FREQ)
lypinator 0:bb348c97df44 107 #define UTILS_SCALE3_LATENCY3_FREQ FLASH_SCALE3_LATENCY3_FREQ /*!< HCLK frequency to set FLASH latency 3 in power scale 3 */
lypinator 0:bb348c97df44 108 #endif
lypinator 0:bb348c97df44 109 #if defined(FLASH_SCALE3_LATENCY4_FREQ)
lypinator 0:bb348c97df44 110 #define UTILS_SCALE3_LATENCY4_FREQ FLASH_SCALE3_LATENCY4_FREQ /*!< HCLK frequency to set FLASH latency 4 in power scale 3 */
lypinator 0:bb348c97df44 111 #endif
lypinator 0:bb348c97df44 112 #if defined(FLASH_SCALE3_LATENCY5_FREQ)
lypinator 0:bb348c97df44 113 #define UTILS_SCALE3_LATENCY5_FREQ FLASH_SCALE3_LATENCY5_FREQ /*!< HCLK frequency to set FLASH latency 5 in power scale 3 */
lypinator 0:bb348c97df44 114 #endif
lypinator 0:bb348c97df44 115 /**
lypinator 0:bb348c97df44 116 * @}
lypinator 0:bb348c97df44 117 */
lypinator 0:bb348c97df44 118
lypinator 0:bb348c97df44 119 /* Private macros ------------------------------------------------------------*/
lypinator 0:bb348c97df44 120 /** @addtogroup UTILS_LL_Private_Macros
lypinator 0:bb348c97df44 121 * @{
lypinator 0:bb348c97df44 122 */
lypinator 0:bb348c97df44 123 #define IS_LL_UTILS_SYSCLK_DIV(__VALUE__) (((__VALUE__) == LL_RCC_SYSCLK_DIV_1) \
lypinator 0:bb348c97df44 124 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_2) \
lypinator 0:bb348c97df44 125 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_4) \
lypinator 0:bb348c97df44 126 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_8) \
lypinator 0:bb348c97df44 127 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_16) \
lypinator 0:bb348c97df44 128 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_64) \
lypinator 0:bb348c97df44 129 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_128) \
lypinator 0:bb348c97df44 130 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_256) \
lypinator 0:bb348c97df44 131 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_512))
lypinator 0:bb348c97df44 132
lypinator 0:bb348c97df44 133 #define IS_LL_UTILS_APB1_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB1_DIV_1) \
lypinator 0:bb348c97df44 134 || ((__VALUE__) == LL_RCC_APB1_DIV_2) \
lypinator 0:bb348c97df44 135 || ((__VALUE__) == LL_RCC_APB1_DIV_4) \
lypinator 0:bb348c97df44 136 || ((__VALUE__) == LL_RCC_APB1_DIV_8) \
lypinator 0:bb348c97df44 137 || ((__VALUE__) == LL_RCC_APB1_DIV_16))
lypinator 0:bb348c97df44 138
lypinator 0:bb348c97df44 139 #define IS_LL_UTILS_APB2_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB2_DIV_1) \
lypinator 0:bb348c97df44 140 || ((__VALUE__) == LL_RCC_APB2_DIV_2) \
lypinator 0:bb348c97df44 141 || ((__VALUE__) == LL_RCC_APB2_DIV_4) \
lypinator 0:bb348c97df44 142 || ((__VALUE__) == LL_RCC_APB2_DIV_8) \
lypinator 0:bb348c97df44 143 || ((__VALUE__) == LL_RCC_APB2_DIV_16))
lypinator 0:bb348c97df44 144
lypinator 0:bb348c97df44 145 #define IS_LL_UTILS_PLLM_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLLM_DIV_2) \
lypinator 0:bb348c97df44 146 || ((__VALUE__) == LL_RCC_PLLM_DIV_3) \
lypinator 0:bb348c97df44 147 || ((__VALUE__) == LL_RCC_PLLM_DIV_4) \
lypinator 0:bb348c97df44 148 || ((__VALUE__) == LL_RCC_PLLM_DIV_5) \
lypinator 0:bb348c97df44 149 || ((__VALUE__) == LL_RCC_PLLM_DIV_6) \
lypinator 0:bb348c97df44 150 || ((__VALUE__) == LL_RCC_PLLM_DIV_7) \
lypinator 0:bb348c97df44 151 || ((__VALUE__) == LL_RCC_PLLM_DIV_8) \
lypinator 0:bb348c97df44 152 || ((__VALUE__) == LL_RCC_PLLM_DIV_9) \
lypinator 0:bb348c97df44 153 || ((__VALUE__) == LL_RCC_PLLM_DIV_10) \
lypinator 0:bb348c97df44 154 || ((__VALUE__) == LL_RCC_PLLM_DIV_11) \
lypinator 0:bb348c97df44 155 || ((__VALUE__) == LL_RCC_PLLM_DIV_12) \
lypinator 0:bb348c97df44 156 || ((__VALUE__) == LL_RCC_PLLM_DIV_13) \
lypinator 0:bb348c97df44 157 || ((__VALUE__) == LL_RCC_PLLM_DIV_14) \
lypinator 0:bb348c97df44 158 || ((__VALUE__) == LL_RCC_PLLM_DIV_15) \
lypinator 0:bb348c97df44 159 || ((__VALUE__) == LL_RCC_PLLM_DIV_16) \
lypinator 0:bb348c97df44 160 || ((__VALUE__) == LL_RCC_PLLM_DIV_17) \
lypinator 0:bb348c97df44 161 || ((__VALUE__) == LL_RCC_PLLM_DIV_18) \
lypinator 0:bb348c97df44 162 || ((__VALUE__) == LL_RCC_PLLM_DIV_19) \
lypinator 0:bb348c97df44 163 || ((__VALUE__) == LL_RCC_PLLM_DIV_20) \
lypinator 0:bb348c97df44 164 || ((__VALUE__) == LL_RCC_PLLM_DIV_21) \
lypinator 0:bb348c97df44 165 || ((__VALUE__) == LL_RCC_PLLM_DIV_22) \
lypinator 0:bb348c97df44 166 || ((__VALUE__) == LL_RCC_PLLM_DIV_23) \
lypinator 0:bb348c97df44 167 || ((__VALUE__) == LL_RCC_PLLM_DIV_24) \
lypinator 0:bb348c97df44 168 || ((__VALUE__) == LL_RCC_PLLM_DIV_25) \
lypinator 0:bb348c97df44 169 || ((__VALUE__) == LL_RCC_PLLM_DIV_26) \
lypinator 0:bb348c97df44 170 || ((__VALUE__) == LL_RCC_PLLM_DIV_27) \
lypinator 0:bb348c97df44 171 || ((__VALUE__) == LL_RCC_PLLM_DIV_28) \
lypinator 0:bb348c97df44 172 || ((__VALUE__) == LL_RCC_PLLM_DIV_29) \
lypinator 0:bb348c97df44 173 || ((__VALUE__) == LL_RCC_PLLM_DIV_30) \
lypinator 0:bb348c97df44 174 || ((__VALUE__) == LL_RCC_PLLM_DIV_31) \
lypinator 0:bb348c97df44 175 || ((__VALUE__) == LL_RCC_PLLM_DIV_32) \
lypinator 0:bb348c97df44 176 || ((__VALUE__) == LL_RCC_PLLM_DIV_33) \
lypinator 0:bb348c97df44 177 || ((__VALUE__) == LL_RCC_PLLM_DIV_34) \
lypinator 0:bb348c97df44 178 || ((__VALUE__) == LL_RCC_PLLM_DIV_35) \
lypinator 0:bb348c97df44 179 || ((__VALUE__) == LL_RCC_PLLM_DIV_36) \
lypinator 0:bb348c97df44 180 || ((__VALUE__) == LL_RCC_PLLM_DIV_37) \
lypinator 0:bb348c97df44 181 || ((__VALUE__) == LL_RCC_PLLM_DIV_38) \
lypinator 0:bb348c97df44 182 || ((__VALUE__) == LL_RCC_PLLM_DIV_39) \
lypinator 0:bb348c97df44 183 || ((__VALUE__) == LL_RCC_PLLM_DIV_40) \
lypinator 0:bb348c97df44 184 || ((__VALUE__) == LL_RCC_PLLM_DIV_41) \
lypinator 0:bb348c97df44 185 || ((__VALUE__) == LL_RCC_PLLM_DIV_42) \
lypinator 0:bb348c97df44 186 || ((__VALUE__) == LL_RCC_PLLM_DIV_43) \
lypinator 0:bb348c97df44 187 || ((__VALUE__) == LL_RCC_PLLM_DIV_44) \
lypinator 0:bb348c97df44 188 || ((__VALUE__) == LL_RCC_PLLM_DIV_45) \
lypinator 0:bb348c97df44 189 || ((__VALUE__) == LL_RCC_PLLM_DIV_46) \
lypinator 0:bb348c97df44 190 || ((__VALUE__) == LL_RCC_PLLM_DIV_47) \
lypinator 0:bb348c97df44 191 || ((__VALUE__) == LL_RCC_PLLM_DIV_48) \
lypinator 0:bb348c97df44 192 || ((__VALUE__) == LL_RCC_PLLM_DIV_49) \
lypinator 0:bb348c97df44 193 || ((__VALUE__) == LL_RCC_PLLM_DIV_50) \
lypinator 0:bb348c97df44 194 || ((__VALUE__) == LL_RCC_PLLM_DIV_51) \
lypinator 0:bb348c97df44 195 || ((__VALUE__) == LL_RCC_PLLM_DIV_52) \
lypinator 0:bb348c97df44 196 || ((__VALUE__) == LL_RCC_PLLM_DIV_53) \
lypinator 0:bb348c97df44 197 || ((__VALUE__) == LL_RCC_PLLM_DIV_54) \
lypinator 0:bb348c97df44 198 || ((__VALUE__) == LL_RCC_PLLM_DIV_55) \
lypinator 0:bb348c97df44 199 || ((__VALUE__) == LL_RCC_PLLM_DIV_56) \
lypinator 0:bb348c97df44 200 || ((__VALUE__) == LL_RCC_PLLM_DIV_57) \
lypinator 0:bb348c97df44 201 || ((__VALUE__) == LL_RCC_PLLM_DIV_58) \
lypinator 0:bb348c97df44 202 || ((__VALUE__) == LL_RCC_PLLM_DIV_59) \
lypinator 0:bb348c97df44 203 || ((__VALUE__) == LL_RCC_PLLM_DIV_60) \
lypinator 0:bb348c97df44 204 || ((__VALUE__) == LL_RCC_PLLM_DIV_61) \
lypinator 0:bb348c97df44 205 || ((__VALUE__) == LL_RCC_PLLM_DIV_62) \
lypinator 0:bb348c97df44 206 || ((__VALUE__) == LL_RCC_PLLM_DIV_63))
lypinator 0:bb348c97df44 207
lypinator 0:bb348c97df44 208 #define IS_LL_UTILS_PLLN_VALUE(__VALUE__) ((RCC_PLLN_MIN_VALUE <= (__VALUE__)) && ((__VALUE__) <= RCC_PLLN_MAX_VALUE))
lypinator 0:bb348c97df44 209
lypinator 0:bb348c97df44 210 #define IS_LL_UTILS_PLLP_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLLP_DIV_2) \
lypinator 0:bb348c97df44 211 || ((__VALUE__) == LL_RCC_PLLP_DIV_4) \
lypinator 0:bb348c97df44 212 || ((__VALUE__) == LL_RCC_PLLP_DIV_6) \
lypinator 0:bb348c97df44 213 || ((__VALUE__) == LL_RCC_PLLP_DIV_8))
lypinator 0:bb348c97df44 214
lypinator 0:bb348c97df44 215 #define IS_LL_UTILS_PLLVCO_INPUT(__VALUE__) ((UTILS_PLLVCO_INPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_INPUT_MAX))
lypinator 0:bb348c97df44 216
lypinator 0:bb348c97df44 217 #define IS_LL_UTILS_PLLVCO_OUTPUT(__VALUE__) ((UTILS_PLLVCO_OUTPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_OUTPUT_MAX))
lypinator 0:bb348c97df44 218
lypinator 0:bb348c97df44 219 #if !defined(RCC_MAX_FREQUENCY_SCALE1)
lypinator 0:bb348c97df44 220 #define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE2) : \
lypinator 0:bb348c97df44 221 ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE3))
lypinator 0:bb348c97df44 222
lypinator 0:bb348c97df44 223 #elif defined(RCC_MAX_FREQUENCY_SCALE3)
lypinator 0:bb348c97df44 224 #define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE1) : \
lypinator 0:bb348c97df44 225 (LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE2) : \
lypinator 0:bb348c97df44 226 ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE3))
lypinator 0:bb348c97df44 227
lypinator 0:bb348c97df44 228 #else
lypinator 0:bb348c97df44 229 #define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE1) : \
lypinator 0:bb348c97df44 230 ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE2))
lypinator 0:bb348c97df44 231
lypinator 0:bb348c97df44 232 #endif /* RCC_MAX_FREQUENCY_SCALE1*/
lypinator 0:bb348c97df44 233 #define IS_LL_UTILS_HSE_BYPASS(__STATE__) (((__STATE__) == LL_UTILS_HSEBYPASS_ON) \
lypinator 0:bb348c97df44 234 || ((__STATE__) == LL_UTILS_HSEBYPASS_OFF))
lypinator 0:bb348c97df44 235
lypinator 0:bb348c97df44 236 #define IS_LL_UTILS_HSE_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN) && ((__FREQUENCY__) <= UTILS_HSE_FREQUENCY_MAX))
lypinator 0:bb348c97df44 237 /**
lypinator 0:bb348c97df44 238 * @}
lypinator 0:bb348c97df44 239 */
lypinator 0:bb348c97df44 240 /* Private function prototypes -----------------------------------------------*/
lypinator 0:bb348c97df44 241 /** @defgroup UTILS_LL_Private_Functions UTILS Private functions
lypinator 0:bb348c97df44 242 * @{
lypinator 0:bb348c97df44 243 */
lypinator 0:bb348c97df44 244 static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency,
lypinator 0:bb348c97df44 245 LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct);
lypinator 0:bb348c97df44 246 static ErrorStatus UTILS_SetFlashLatency(uint32_t HCLK_Frequency);
lypinator 0:bb348c97df44 247 static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
lypinator 0:bb348c97df44 248 static ErrorStatus UTILS_PLL_IsBusy(void);
lypinator 0:bb348c97df44 249 /**
lypinator 0:bb348c97df44 250 * @}
lypinator 0:bb348c97df44 251 */
lypinator 0:bb348c97df44 252
lypinator 0:bb348c97df44 253 /* Exported functions --------------------------------------------------------*/
lypinator 0:bb348c97df44 254 /** @addtogroup UTILS_LL_Exported_Functions
lypinator 0:bb348c97df44 255 * @{
lypinator 0:bb348c97df44 256 */
lypinator 0:bb348c97df44 257
lypinator 0:bb348c97df44 258 /** @addtogroup UTILS_LL_EF_DELAY
lypinator 0:bb348c97df44 259 * @{
lypinator 0:bb348c97df44 260 */
lypinator 0:bb348c97df44 261
lypinator 0:bb348c97df44 262 /**
lypinator 0:bb348c97df44 263 * @brief This function configures the Cortex-M SysTick source to have 1ms time base.
lypinator 0:bb348c97df44 264 * @note When a RTOS is used, it is recommended to avoid changing the Systick
lypinator 0:bb348c97df44 265 * configuration by calling this function, for a delay use rather osDelay RTOS service.
lypinator 0:bb348c97df44 266 * @param HCLKFrequency HCLK frequency in Hz
lypinator 0:bb348c97df44 267 * @note HCLK frequency can be calculated thanks to RCC helper macro or function @ref LL_RCC_GetSystemClocksFreq
lypinator 0:bb348c97df44 268 * @retval None
lypinator 0:bb348c97df44 269 */
lypinator 0:bb348c97df44 270 void LL_Init1msTick(uint32_t HCLKFrequency)
lypinator 0:bb348c97df44 271 {
lypinator 0:bb348c97df44 272 /* Use frequency provided in argument */
lypinator 0:bb348c97df44 273 LL_InitTick(HCLKFrequency, 1000U);
lypinator 0:bb348c97df44 274 }
lypinator 0:bb348c97df44 275
lypinator 0:bb348c97df44 276 /**
lypinator 0:bb348c97df44 277 * @brief This function provides accurate delay (in milliseconds) based
lypinator 0:bb348c97df44 278 * on SysTick counter flag
lypinator 0:bb348c97df44 279 * @note When a RTOS is used, it is recommended to avoid using blocking delay
lypinator 0:bb348c97df44 280 * and use rather osDelay service.
lypinator 0:bb348c97df44 281 * @note To respect 1ms timebase, user should call @ref LL_Init1msTick function which
lypinator 0:bb348c97df44 282 * will configure Systick to 1ms
lypinator 0:bb348c97df44 283 * @param Delay specifies the delay time length, in milliseconds.
lypinator 0:bb348c97df44 284 * @retval None
lypinator 0:bb348c97df44 285 */
lypinator 0:bb348c97df44 286 void LL_mDelay(uint32_t Delay)
lypinator 0:bb348c97df44 287 {
lypinator 0:bb348c97df44 288 __IO uint32_t tmp = SysTick->CTRL; /* Clear the COUNTFLAG first */
lypinator 0:bb348c97df44 289 /* Add this code to indicate that local variable is not used */
lypinator 0:bb348c97df44 290 ((void)tmp);
lypinator 0:bb348c97df44 291
lypinator 0:bb348c97df44 292 /* Add a period to guaranty minimum wait */
lypinator 0:bb348c97df44 293 if(Delay < LL_MAX_DELAY)
lypinator 0:bb348c97df44 294 {
lypinator 0:bb348c97df44 295 Delay++;
lypinator 0:bb348c97df44 296 }
lypinator 0:bb348c97df44 297
lypinator 0:bb348c97df44 298 while (Delay)
lypinator 0:bb348c97df44 299 {
lypinator 0:bb348c97df44 300 if((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != 0U)
lypinator 0:bb348c97df44 301 {
lypinator 0:bb348c97df44 302 Delay--;
lypinator 0:bb348c97df44 303 }
lypinator 0:bb348c97df44 304 }
lypinator 0:bb348c97df44 305 }
lypinator 0:bb348c97df44 306
lypinator 0:bb348c97df44 307 /**
lypinator 0:bb348c97df44 308 * @}
lypinator 0:bb348c97df44 309 */
lypinator 0:bb348c97df44 310
lypinator 0:bb348c97df44 311 /** @addtogroup UTILS_EF_SYSTEM
lypinator 0:bb348c97df44 312 * @brief System Configuration functions
lypinator 0:bb348c97df44 313 *
lypinator 0:bb348c97df44 314 @verbatim
lypinator 0:bb348c97df44 315 ===============================================================================
lypinator 0:bb348c97df44 316 ##### System Configuration functions #####
lypinator 0:bb348c97df44 317 ===============================================================================
lypinator 0:bb348c97df44 318 [..]
lypinator 0:bb348c97df44 319 System, AHB and APB buses clocks configuration
lypinator 0:bb348c97df44 320
lypinator 0:bb348c97df44 321 (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 180000000 Hz.
lypinator 0:bb348c97df44 322 @endverbatim
lypinator 0:bb348c97df44 323 @internal
lypinator 0:bb348c97df44 324 Depending on the device voltage range, the maximum frequency should be
lypinator 0:bb348c97df44 325 adapted accordingly to the Refenece manual.
lypinator 0:bb348c97df44 326 @endinternal
lypinator 0:bb348c97df44 327 * @{
lypinator 0:bb348c97df44 328 */
lypinator 0:bb348c97df44 329
lypinator 0:bb348c97df44 330 /**
lypinator 0:bb348c97df44 331 * @brief This function sets directly SystemCoreClock CMSIS variable.
lypinator 0:bb348c97df44 332 * @note Variable can be calculated also through SystemCoreClockUpdate function.
lypinator 0:bb348c97df44 333 * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
lypinator 0:bb348c97df44 334 * @retval None
lypinator 0:bb348c97df44 335 */
lypinator 0:bb348c97df44 336 void LL_SetSystemCoreClock(uint32_t HCLKFrequency)
lypinator 0:bb348c97df44 337 {
lypinator 0:bb348c97df44 338 /* HCLK clock frequency */
lypinator 0:bb348c97df44 339 SystemCoreClock = HCLKFrequency;
lypinator 0:bb348c97df44 340 }
lypinator 0:bb348c97df44 341
lypinator 0:bb348c97df44 342 /**
lypinator 0:bb348c97df44 343 * @brief This function configures system clock at maximum frequency with HSI as clock source of the PLL
lypinator 0:bb348c97df44 344 * @note The application need to ensure that PLL is disabled.
lypinator 0:bb348c97df44 345 * @note Function is based on the following formula:
lypinator 0:bb348c97df44 346 * - PLL output frequency = (((HSI frequency / PLLM) * PLLN) / PLLP)
lypinator 0:bb348c97df44 347 * - PLLM: ensure that the VCO input frequency ranges from @ref RCC_PLLVCO_INPUT_MIN to @ref RCC_PLLVCO_INPUT_MAX (PLLVCO_input = HSI frequency / PLLM)
lypinator 0:bb348c97df44 348 * - PLLN: ensure that the VCO output frequency is between @ref RCC_PLLVCO_OUTPUT_MIN and @ref RCC_PLLVCO_OUTPUT_MAX (PLLVCO_output = PLLVCO_input * PLLN)
lypinator 0:bb348c97df44 349 * - PLLP: ensure that max frequency at 180000000 Hz is reach (PLLVCO_output / PLLP)
lypinator 0:bb348c97df44 350 * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
lypinator 0:bb348c97df44 351 * the configuration information for the PLL.
lypinator 0:bb348c97df44 352 * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
lypinator 0:bb348c97df44 353 * the configuration information for the BUS prescalers.
lypinator 0:bb348c97df44 354 * @retval An ErrorStatus enumeration value:
lypinator 0:bb348c97df44 355 * - SUCCESS: Max frequency configuration done
lypinator 0:bb348c97df44 356 * - ERROR: Max frequency configuration not done
lypinator 0:bb348c97df44 357 */
lypinator 0:bb348c97df44 358 ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
lypinator 0:bb348c97df44 359 LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
lypinator 0:bb348c97df44 360 {
lypinator 0:bb348c97df44 361 ErrorStatus status = SUCCESS;
lypinator 0:bb348c97df44 362 uint32_t pllfreq = 0U;
lypinator 0:bb348c97df44 363
lypinator 0:bb348c97df44 364 /* Check if one of the PLL is enabled */
lypinator 0:bb348c97df44 365 if(UTILS_PLL_IsBusy() == SUCCESS)
lypinator 0:bb348c97df44 366 {
lypinator 0:bb348c97df44 367 /* Calculate the new PLL output frequency */
lypinator 0:bb348c97df44 368 pllfreq = UTILS_GetPLLOutputFrequency(HSI_VALUE, UTILS_PLLInitStruct);
lypinator 0:bb348c97df44 369
lypinator 0:bb348c97df44 370 /* Enable HSI if not enabled */
lypinator 0:bb348c97df44 371 if(LL_RCC_HSI_IsReady() != 1U)
lypinator 0:bb348c97df44 372 {
lypinator 0:bb348c97df44 373 LL_RCC_HSI_Enable();
lypinator 0:bb348c97df44 374 while (LL_RCC_HSI_IsReady() != 1U)
lypinator 0:bb348c97df44 375 {
lypinator 0:bb348c97df44 376 /* Wait for HSI ready */
lypinator 0:bb348c97df44 377 }
lypinator 0:bb348c97df44 378 }
lypinator 0:bb348c97df44 379
lypinator 0:bb348c97df44 380 /* Configure PLL */
lypinator 0:bb348c97df44 381 LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN,
lypinator 0:bb348c97df44 382 UTILS_PLLInitStruct->PLLP);
lypinator 0:bb348c97df44 383
lypinator 0:bb348c97df44 384 /* Enable PLL and switch system clock to PLL */
lypinator 0:bb348c97df44 385 status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
lypinator 0:bb348c97df44 386 }
lypinator 0:bb348c97df44 387 else
lypinator 0:bb348c97df44 388 {
lypinator 0:bb348c97df44 389 /* Current PLL configuration cannot be modified */
lypinator 0:bb348c97df44 390 status = ERROR;
lypinator 0:bb348c97df44 391 }
lypinator 0:bb348c97df44 392
lypinator 0:bb348c97df44 393 return status;
lypinator 0:bb348c97df44 394 }
lypinator 0:bb348c97df44 395
lypinator 0:bb348c97df44 396 /**
lypinator 0:bb348c97df44 397 * @brief This function configures system clock with HSE as clock source of the PLL
lypinator 0:bb348c97df44 398 * @note The application need to ensure that PLL is disabled.
lypinator 0:bb348c97df44 399 * - PLL output frequency = (((HSI frequency / PLLM) * PLLN) / PLLP)
lypinator 0:bb348c97df44 400 * - PLLM: ensure that the VCO input frequency ranges from @ref RCC_PLLVCO_INPUT_MIN to @ref RCC_PLLVCO_INPUT_MAX (PLLVCO_input = HSI frequency / PLLM)
lypinator 0:bb348c97df44 401 * - PLLN: ensure that the VCO output frequency is between @ref RCC_PLLVCO_OUTPUT_MIN and @ref RCC_PLLVCO_OUTPUT_MAX (PLLVCO_output = PLLVCO_input * PLLN)
lypinator 0:bb348c97df44 402 * - PLLP: ensure that max frequency at 180000000 Hz is reach (PLLVCO_output / PLLP)
lypinator 0:bb348c97df44 403 * @param HSEFrequency Value between Min_Data = 4000000 and Max_Data = 26000000
lypinator 0:bb348c97df44 404 * @param HSEBypass This parameter can be one of the following values:
lypinator 0:bb348c97df44 405 * @arg @ref LL_UTILS_HSEBYPASS_ON
lypinator 0:bb348c97df44 406 * @arg @ref LL_UTILS_HSEBYPASS_OFF
lypinator 0:bb348c97df44 407 * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
lypinator 0:bb348c97df44 408 * the configuration information for the PLL.
lypinator 0:bb348c97df44 409 * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
lypinator 0:bb348c97df44 410 * the configuration information for the BUS prescalers.
lypinator 0:bb348c97df44 411 * @retval An ErrorStatus enumeration value:
lypinator 0:bb348c97df44 412 * - SUCCESS: Max frequency configuration done
lypinator 0:bb348c97df44 413 * - ERROR: Max frequency configuration not done
lypinator 0:bb348c97df44 414 */
lypinator 0:bb348c97df44 415 ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
lypinator 0:bb348c97df44 416 LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
lypinator 0:bb348c97df44 417 {
lypinator 0:bb348c97df44 418 ErrorStatus status = SUCCESS;
lypinator 0:bb348c97df44 419 uint32_t pllfreq = 0U;
lypinator 0:bb348c97df44 420
lypinator 0:bb348c97df44 421 /* Check the parameters */
lypinator 0:bb348c97df44 422 assert_param(IS_LL_UTILS_HSE_FREQUENCY(HSEFrequency));
lypinator 0:bb348c97df44 423 assert_param(IS_LL_UTILS_HSE_BYPASS(HSEBypass));
lypinator 0:bb348c97df44 424
lypinator 0:bb348c97df44 425 /* Check if one of the PLL is enabled */
lypinator 0:bb348c97df44 426 if(UTILS_PLL_IsBusy() == SUCCESS)
lypinator 0:bb348c97df44 427 {
lypinator 0:bb348c97df44 428 /* Calculate the new PLL output frequency */
lypinator 0:bb348c97df44 429 pllfreq = UTILS_GetPLLOutputFrequency(HSEFrequency, UTILS_PLLInitStruct);
lypinator 0:bb348c97df44 430
lypinator 0:bb348c97df44 431 /* Enable HSE if not enabled */
lypinator 0:bb348c97df44 432 if(LL_RCC_HSE_IsReady() != 1U)
lypinator 0:bb348c97df44 433 {
lypinator 0:bb348c97df44 434 /* Check if need to enable HSE bypass feature or not */
lypinator 0:bb348c97df44 435 if(HSEBypass == LL_UTILS_HSEBYPASS_ON)
lypinator 0:bb348c97df44 436 {
lypinator 0:bb348c97df44 437 LL_RCC_HSE_EnableBypass();
lypinator 0:bb348c97df44 438 }
lypinator 0:bb348c97df44 439 else
lypinator 0:bb348c97df44 440 {
lypinator 0:bb348c97df44 441 LL_RCC_HSE_DisableBypass();
lypinator 0:bb348c97df44 442 }
lypinator 0:bb348c97df44 443
lypinator 0:bb348c97df44 444 /* Enable HSE */
lypinator 0:bb348c97df44 445 LL_RCC_HSE_Enable();
lypinator 0:bb348c97df44 446 while (LL_RCC_HSE_IsReady() != 1U)
lypinator 0:bb348c97df44 447 {
lypinator 0:bb348c97df44 448 /* Wait for HSE ready */
lypinator 0:bb348c97df44 449 }
lypinator 0:bb348c97df44 450 }
lypinator 0:bb348c97df44 451
lypinator 0:bb348c97df44 452 /* Configure PLL */
lypinator 0:bb348c97df44 453 LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN,
lypinator 0:bb348c97df44 454 UTILS_PLLInitStruct->PLLP);
lypinator 0:bb348c97df44 455
lypinator 0:bb348c97df44 456 /* Enable PLL and switch system clock to PLL */
lypinator 0:bb348c97df44 457 status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
lypinator 0:bb348c97df44 458 }
lypinator 0:bb348c97df44 459 else
lypinator 0:bb348c97df44 460 {
lypinator 0:bb348c97df44 461 /* Current PLL configuration cannot be modified */
lypinator 0:bb348c97df44 462 status = ERROR;
lypinator 0:bb348c97df44 463 }
lypinator 0:bb348c97df44 464
lypinator 0:bb348c97df44 465 return status;
lypinator 0:bb348c97df44 466 }
lypinator 0:bb348c97df44 467
lypinator 0:bb348c97df44 468 /**
lypinator 0:bb348c97df44 469 * @}
lypinator 0:bb348c97df44 470 */
lypinator 0:bb348c97df44 471
lypinator 0:bb348c97df44 472 /**
lypinator 0:bb348c97df44 473 * @}
lypinator 0:bb348c97df44 474 */
lypinator 0:bb348c97df44 475
lypinator 0:bb348c97df44 476 /** @addtogroup UTILS_LL_Private_Functions
lypinator 0:bb348c97df44 477 * @{
lypinator 0:bb348c97df44 478 */
lypinator 0:bb348c97df44 479 /**
lypinator 0:bb348c97df44 480 * @brief Update number of Flash wait states in line with new frequency and current
lypinator 0:bb348c97df44 481 voltage range.
lypinator 0:bb348c97df44 482 * @note This Function support ONLY devices with supply voltage (voltage range) between 2.7V and 3.6V
lypinator 0:bb348c97df44 483 * @param HCLK_Frequency HCLK frequency
lypinator 0:bb348c97df44 484 * @retval An ErrorStatus enumeration value:
lypinator 0:bb348c97df44 485 * - SUCCESS: Latency has been modified
lypinator 0:bb348c97df44 486 * - ERROR: Latency cannot be modified
lypinator 0:bb348c97df44 487 */
lypinator 0:bb348c97df44 488 static ErrorStatus UTILS_SetFlashLatency(uint32_t HCLK_Frequency)
lypinator 0:bb348c97df44 489 {
lypinator 0:bb348c97df44 490 ErrorStatus status = SUCCESS;
lypinator 0:bb348c97df44 491
lypinator 0:bb348c97df44 492 uint32_t latency = LL_FLASH_LATENCY_0; /* default value 0WS */
lypinator 0:bb348c97df44 493
lypinator 0:bb348c97df44 494 /* Frequency cannot be equal to 0 */
lypinator 0:bb348c97df44 495 if(HCLK_Frequency == 0U)
lypinator 0:bb348c97df44 496 {
lypinator 0:bb348c97df44 497 status = ERROR;
lypinator 0:bb348c97df44 498 }
lypinator 0:bb348c97df44 499 else
lypinator 0:bb348c97df44 500 {
lypinator 0:bb348c97df44 501 if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1)
lypinator 0:bb348c97df44 502 {
lypinator 0:bb348c97df44 503 #if defined (UTILS_SCALE1_LATENCY5_FREQ)
lypinator 0:bb348c97df44 504 if((HCLK_Frequency > UTILS_SCALE1_LATENCY5_FREQ)&&(latency == LL_FLASH_LATENCY_0))
lypinator 0:bb348c97df44 505 {
lypinator 0:bb348c97df44 506 latency = LL_FLASH_LATENCY_5;
lypinator 0:bb348c97df44 507 }
lypinator 0:bb348c97df44 508 #endif /*UTILS_SCALE1_LATENCY5_FREQ */
lypinator 0:bb348c97df44 509 #if defined (UTILS_SCALE1_LATENCY4_FREQ)
lypinator 0:bb348c97df44 510 if((HCLK_Frequency > UTILS_SCALE1_LATENCY4_FREQ)&&(latency == LL_FLASH_LATENCY_0))
lypinator 0:bb348c97df44 511 {
lypinator 0:bb348c97df44 512 latency = LL_FLASH_LATENCY_4;
lypinator 0:bb348c97df44 513 }
lypinator 0:bb348c97df44 514 #endif /* UTILS_SCALE1_LATENCY4_FREQ */
lypinator 0:bb348c97df44 515 #if defined (UTILS_SCALE1_LATENCY3_FREQ)
lypinator 0:bb348c97df44 516 if((HCLK_Frequency > UTILS_SCALE1_LATENCY3_FREQ)&&(latency == LL_FLASH_LATENCY_0))
lypinator 0:bb348c97df44 517 {
lypinator 0:bb348c97df44 518 latency = LL_FLASH_LATENCY_3;
lypinator 0:bb348c97df44 519 }
lypinator 0:bb348c97df44 520 #endif /* UTILS_SCALE1_LATENCY3_FREQ */
lypinator 0:bb348c97df44 521 #if defined (UTILS_SCALE1_LATENCY2_FREQ)
lypinator 0:bb348c97df44 522 if((HCLK_Frequency > UTILS_SCALE1_LATENCY2_FREQ)&&(latency == LL_FLASH_LATENCY_0))
lypinator 0:bb348c97df44 523 {
lypinator 0:bb348c97df44 524 latency = LL_FLASH_LATENCY_2;
lypinator 0:bb348c97df44 525 }
lypinator 0:bb348c97df44 526 else
lypinator 0:bb348c97df44 527 {
lypinator 0:bb348c97df44 528 if((HCLK_Frequency > UTILS_SCALE1_LATENCY1_FREQ)&&(latency == LL_FLASH_LATENCY_0))
lypinator 0:bb348c97df44 529 {
lypinator 0:bb348c97df44 530 latency = LL_FLASH_LATENCY_1;
lypinator 0:bb348c97df44 531 }
lypinator 0:bb348c97df44 532 }
lypinator 0:bb348c97df44 533 #endif /* UTILS_SCALE1_LATENCY2_FREQ */
lypinator 0:bb348c97df44 534 }
lypinator 0:bb348c97df44 535 if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2)
lypinator 0:bb348c97df44 536 {
lypinator 0:bb348c97df44 537 #if defined (UTILS_SCALE2_LATENCY5_FREQ)
lypinator 0:bb348c97df44 538 if((HCLK_Frequency > UTILS_SCALE2_LATENCY5_FREQ)&&(latency == LL_FLASH_LATENCY_0))
lypinator 0:bb348c97df44 539 {
lypinator 0:bb348c97df44 540 latency = LL_FLASH_LATENCY_5;
lypinator 0:bb348c97df44 541 }
lypinator 0:bb348c97df44 542 #endif /*UTILS_SCALE1_LATENCY5_FREQ */
lypinator 0:bb348c97df44 543 #if defined (UTILS_SCALE2_LATENCY4_FREQ)
lypinator 0:bb348c97df44 544 if((HCLK_Frequency > UTILS_SCALE2_LATENCY4_FREQ)&&(latency == LL_FLASH_LATENCY_0))
lypinator 0:bb348c97df44 545 {
lypinator 0:bb348c97df44 546 latency = LL_FLASH_LATENCY_4;
lypinator 0:bb348c97df44 547 }
lypinator 0:bb348c97df44 548 #endif /*UTILS_SCALE1_LATENCY4_FREQ */
lypinator 0:bb348c97df44 549 #if defined (UTILS_SCALE2_LATENCY3_FREQ)
lypinator 0:bb348c97df44 550 if((HCLK_Frequency > UTILS_SCALE2_LATENCY3_FREQ)&&(latency == LL_FLASH_LATENCY_0))
lypinator 0:bb348c97df44 551 {
lypinator 0:bb348c97df44 552 latency = LL_FLASH_LATENCY_3;
lypinator 0:bb348c97df44 553 }
lypinator 0:bb348c97df44 554 #endif /*UTILS_SCALE1_LATENCY3_FREQ */
lypinator 0:bb348c97df44 555 if((HCLK_Frequency > UTILS_SCALE2_LATENCY2_FREQ)&&(latency == LL_FLASH_LATENCY_0))
lypinator 0:bb348c97df44 556 {
lypinator 0:bb348c97df44 557 latency = LL_FLASH_LATENCY_2;
lypinator 0:bb348c97df44 558 }
lypinator 0:bb348c97df44 559 else
lypinator 0:bb348c97df44 560 {
lypinator 0:bb348c97df44 561 if((HCLK_Frequency > UTILS_SCALE2_LATENCY1_FREQ)&&(latency == LL_FLASH_LATENCY_0))
lypinator 0:bb348c97df44 562 {
lypinator 0:bb348c97df44 563 latency = LL_FLASH_LATENCY_1;
lypinator 0:bb348c97df44 564 }
lypinator 0:bb348c97df44 565 }
lypinator 0:bb348c97df44 566 }
lypinator 0:bb348c97df44 567 #if defined (LL_PWR_REGU_VOLTAGE_SCALE3)
lypinator 0:bb348c97df44 568 if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE3)
lypinator 0:bb348c97df44 569 {
lypinator 0:bb348c97df44 570 #if defined (UTILS_SCALE3_LATENCY3_FREQ)
lypinator 0:bb348c97df44 571 if((HCLK_Frequency > UTILS_SCALE3_LATENCY3_FREQ)&&(latency == LL_FLASH_LATENCY_0))
lypinator 0:bb348c97df44 572 {
lypinator 0:bb348c97df44 573 latency = LL_FLASH_LATENCY_3;
lypinator 0:bb348c97df44 574 }
lypinator 0:bb348c97df44 575 #endif /*UTILS_SCALE1_LATENCY3_FREQ */
lypinator 0:bb348c97df44 576 #if defined (UTILS_SCALE3_LATENCY2_FREQ)
lypinator 0:bb348c97df44 577 if((HCLK_Frequency > UTILS_SCALE3_LATENCY2_FREQ)&&(latency == LL_FLASH_LATENCY_0))
lypinator 0:bb348c97df44 578 {
lypinator 0:bb348c97df44 579 latency = LL_FLASH_LATENCY_2;
lypinator 0:bb348c97df44 580 }
lypinator 0:bb348c97df44 581 else
lypinator 0:bb348c97df44 582 {
lypinator 0:bb348c97df44 583 if((HCLK_Frequency > UTILS_SCALE3_LATENCY1_FREQ)&&(latency == LL_FLASH_LATENCY_0))
lypinator 0:bb348c97df44 584 {
lypinator 0:bb348c97df44 585 latency = LL_FLASH_LATENCY_1;
lypinator 0:bb348c97df44 586 }
lypinator 0:bb348c97df44 587 }
lypinator 0:bb348c97df44 588 }
lypinator 0:bb348c97df44 589 #endif /*UTILS_SCALE1_LATENCY2_FREQ */
lypinator 0:bb348c97df44 590 #endif /* LL_PWR_REGU_VOLTAGE_SCALE3 */
lypinator 0:bb348c97df44 591
lypinator 0:bb348c97df44 592 LL_FLASH_SetLatency(latency);
lypinator 0:bb348c97df44 593
lypinator 0:bb348c97df44 594 /* Check that the new number of wait states is taken into account to access the Flash
lypinator 0:bb348c97df44 595 memory by reading the FLASH_ACR register */
lypinator 0:bb348c97df44 596 if(LL_FLASH_GetLatency() != latency)
lypinator 0:bb348c97df44 597 {
lypinator 0:bb348c97df44 598 status = ERROR;
lypinator 0:bb348c97df44 599 }
lypinator 0:bb348c97df44 600 }
lypinator 0:bb348c97df44 601 return status;
lypinator 0:bb348c97df44 602 }
lypinator 0:bb348c97df44 603
lypinator 0:bb348c97df44 604 /**
lypinator 0:bb348c97df44 605 * @brief Function to check that PLL can be modified
lypinator 0:bb348c97df44 606 * @param PLL_InputFrequency PLL input frequency (in Hz)
lypinator 0:bb348c97df44 607 * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
lypinator 0:bb348c97df44 608 * the configuration information for the PLL.
lypinator 0:bb348c97df44 609 * @retval PLL output frequency (in Hz)
lypinator 0:bb348c97df44 610 */
lypinator 0:bb348c97df44 611 static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct)
lypinator 0:bb348c97df44 612 {
lypinator 0:bb348c97df44 613 uint32_t pllfreq = 0U;
lypinator 0:bb348c97df44 614
lypinator 0:bb348c97df44 615 /* Check the parameters */
lypinator 0:bb348c97df44 616 assert_param(IS_LL_UTILS_PLLM_VALUE(UTILS_PLLInitStruct->PLLM));
lypinator 0:bb348c97df44 617 assert_param(IS_LL_UTILS_PLLN_VALUE(UTILS_PLLInitStruct->PLLN));
lypinator 0:bb348c97df44 618 assert_param(IS_LL_UTILS_PLLP_VALUE(UTILS_PLLInitStruct->PLLP));
lypinator 0:bb348c97df44 619
lypinator 0:bb348c97df44 620 /* Check different PLL parameters according to RM */
lypinator 0:bb348c97df44 621 /* - PLLM: ensure that the VCO input frequency ranges from @ref UTILS_PLLVCO_INPUT_MIN to @ref UTILS_PLLVCO_INPUT_MAX MHz. */
lypinator 0:bb348c97df44 622 pllfreq = PLL_InputFrequency / (UTILS_PLLInitStruct->PLLM & (RCC_PLLCFGR_PLLM >> RCC_PLLCFGR_PLLM_Pos));
lypinator 0:bb348c97df44 623 assert_param(IS_LL_UTILS_PLLVCO_INPUT(pllfreq));
lypinator 0:bb348c97df44 624
lypinator 0:bb348c97df44 625 /* - PLLN: ensure that the VCO output frequency is between @ref UTILS_PLLVCO_OUTPUT_MIN and @ref UTILS_PLLVCO_OUTPUT_MAX .*/
lypinator 0:bb348c97df44 626 pllfreq = pllfreq * (UTILS_PLLInitStruct->PLLN & (RCC_PLLCFGR_PLLN >> RCC_PLLCFGR_PLLN_Pos));
lypinator 0:bb348c97df44 627 assert_param(IS_LL_UTILS_PLLVCO_OUTPUT(pllfreq));
lypinator 0:bb348c97df44 628
lypinator 0:bb348c97df44 629 /* - PLLP: ensure that max frequency at @ref RCC_MAX_FREQUENCY Hz is reached */
lypinator 0:bb348c97df44 630 pllfreq = pllfreq / (((UTILS_PLLInitStruct->PLLP >> RCC_PLLCFGR_PLLP_Pos) + 1) * 2);
lypinator 0:bb348c97df44 631 assert_param(IS_LL_UTILS_PLL_FREQUENCY(pllfreq));
lypinator 0:bb348c97df44 632
lypinator 0:bb348c97df44 633 return pllfreq;
lypinator 0:bb348c97df44 634 }
lypinator 0:bb348c97df44 635
lypinator 0:bb348c97df44 636 /**
lypinator 0:bb348c97df44 637 * @brief Function to check that PLL can be modified
lypinator 0:bb348c97df44 638 * @retval An ErrorStatus enumeration value:
lypinator 0:bb348c97df44 639 * - SUCCESS: PLL modification can be done
lypinator 0:bb348c97df44 640 * - ERROR: PLL is busy
lypinator 0:bb348c97df44 641 */
lypinator 0:bb348c97df44 642 static ErrorStatus UTILS_PLL_IsBusy(void)
lypinator 0:bb348c97df44 643 {
lypinator 0:bb348c97df44 644 ErrorStatus status = SUCCESS;
lypinator 0:bb348c97df44 645
lypinator 0:bb348c97df44 646 /* Check if PLL is busy*/
lypinator 0:bb348c97df44 647 if(LL_RCC_PLL_IsReady() != 0U)
lypinator 0:bb348c97df44 648 {
lypinator 0:bb348c97df44 649 /* PLL configuration cannot be modified */
lypinator 0:bb348c97df44 650 status = ERROR;
lypinator 0:bb348c97df44 651 }
lypinator 0:bb348c97df44 652
lypinator 0:bb348c97df44 653 #if defined(RCC_PLLSAI_SUPPORT)
lypinator 0:bb348c97df44 654 /* Check if PLLSAI is busy*/
lypinator 0:bb348c97df44 655 if(LL_RCC_PLLSAI_IsReady() != 0U)
lypinator 0:bb348c97df44 656 {
lypinator 0:bb348c97df44 657 /* PLLSAI1 configuration cannot be modified */
lypinator 0:bb348c97df44 658 status = ERROR;
lypinator 0:bb348c97df44 659 }
lypinator 0:bb348c97df44 660 #endif /*RCC_PLLSAI_SUPPORT*/
lypinator 0:bb348c97df44 661 #if defined(RCC_PLLI2S_SUPPORT)
lypinator 0:bb348c97df44 662 /* Check if PLLI2S is busy*/
lypinator 0:bb348c97df44 663 if(LL_RCC_PLLI2S_IsReady() != 0U)
lypinator 0:bb348c97df44 664 {
lypinator 0:bb348c97df44 665 /* PLLI2S configuration cannot be modified */
lypinator 0:bb348c97df44 666 status = ERROR;
lypinator 0:bb348c97df44 667 }
lypinator 0:bb348c97df44 668 #endif /*RCC_PLLI2S_SUPPORT*/
lypinator 0:bb348c97df44 669 return status;
lypinator 0:bb348c97df44 670 }
lypinator 0:bb348c97df44 671
lypinator 0:bb348c97df44 672 /**
lypinator 0:bb348c97df44 673 * @brief Function to enable PLL and switch system clock to PLL
lypinator 0:bb348c97df44 674 * @param SYSCLK_Frequency SYSCLK frequency
lypinator 0:bb348c97df44 675 * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
lypinator 0:bb348c97df44 676 * the configuration information for the BUS prescalers.
lypinator 0:bb348c97df44 677 * @retval An ErrorStatus enumeration value:
lypinator 0:bb348c97df44 678 * - SUCCESS: No problem to switch system to PLL
lypinator 0:bb348c97df44 679 * - ERROR: Problem to switch system to PLL
lypinator 0:bb348c97df44 680 */
lypinator 0:bb348c97df44 681 static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
lypinator 0:bb348c97df44 682 {
lypinator 0:bb348c97df44 683 ErrorStatus status = SUCCESS;
lypinator 0:bb348c97df44 684 uint32_t hclk_frequency = 0U;
lypinator 0:bb348c97df44 685
lypinator 0:bb348c97df44 686 assert_param(IS_LL_UTILS_SYSCLK_DIV(UTILS_ClkInitStruct->AHBCLKDivider));
lypinator 0:bb348c97df44 687 assert_param(IS_LL_UTILS_APB1_DIV(UTILS_ClkInitStruct->APB1CLKDivider));
lypinator 0:bb348c97df44 688 assert_param(IS_LL_UTILS_APB2_DIV(UTILS_ClkInitStruct->APB2CLKDivider));
lypinator 0:bb348c97df44 689
lypinator 0:bb348c97df44 690 /* Calculate HCLK frequency */
lypinator 0:bb348c97df44 691 hclk_frequency = __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, UTILS_ClkInitStruct->AHBCLKDivider);
lypinator 0:bb348c97df44 692
lypinator 0:bb348c97df44 693 /* Increasing the number of wait states because of higher CPU frequency */
lypinator 0:bb348c97df44 694 if(SystemCoreClock < hclk_frequency)
lypinator 0:bb348c97df44 695 {
lypinator 0:bb348c97df44 696 /* Set FLASH latency to highest latency */
lypinator 0:bb348c97df44 697 status = UTILS_SetFlashLatency(hclk_frequency);
lypinator 0:bb348c97df44 698 }
lypinator 0:bb348c97df44 699
lypinator 0:bb348c97df44 700 /* Update system clock configuration */
lypinator 0:bb348c97df44 701 if(status == SUCCESS)
lypinator 0:bb348c97df44 702 {
lypinator 0:bb348c97df44 703 /* Enable PLL */
lypinator 0:bb348c97df44 704 LL_RCC_PLL_Enable();
lypinator 0:bb348c97df44 705 while (LL_RCC_PLL_IsReady() != 1U)
lypinator 0:bb348c97df44 706 {
lypinator 0:bb348c97df44 707 /* Wait for PLL ready */
lypinator 0:bb348c97df44 708 }
lypinator 0:bb348c97df44 709
lypinator 0:bb348c97df44 710 /* Sysclk activation on the main PLL */
lypinator 0:bb348c97df44 711 LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider);
lypinator 0:bb348c97df44 712 LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
lypinator 0:bb348c97df44 713 while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
lypinator 0:bb348c97df44 714 {
lypinator 0:bb348c97df44 715 /* Wait for system clock switch to PLL */
lypinator 0:bb348c97df44 716 }
lypinator 0:bb348c97df44 717
lypinator 0:bb348c97df44 718 /* Set APB1 & APB2 prescaler*/
lypinator 0:bb348c97df44 719 LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider);
lypinator 0:bb348c97df44 720 LL_RCC_SetAPB2Prescaler(UTILS_ClkInitStruct->APB2CLKDivider);
lypinator 0:bb348c97df44 721 }
lypinator 0:bb348c97df44 722
lypinator 0:bb348c97df44 723 /* Decreasing the number of wait states because of lower CPU frequency */
lypinator 0:bb348c97df44 724 if(SystemCoreClock > hclk_frequency)
lypinator 0:bb348c97df44 725 {
lypinator 0:bb348c97df44 726 /* Set FLASH latency to lowest latency */
lypinator 0:bb348c97df44 727 status = UTILS_SetFlashLatency(hclk_frequency);
lypinator 0:bb348c97df44 728 }
lypinator 0:bb348c97df44 729
lypinator 0:bb348c97df44 730 /* Update SystemCoreClock variable */
lypinator 0:bb348c97df44 731 if(status == SUCCESS)
lypinator 0:bb348c97df44 732 {
lypinator 0:bb348c97df44 733 LL_SetSystemCoreClock(hclk_frequency);
lypinator 0:bb348c97df44 734 }
lypinator 0:bb348c97df44 735
lypinator 0:bb348c97df44 736 return status;
lypinator 0:bb348c97df44 737 }
lypinator 0:bb348c97df44 738
lypinator 0:bb348c97df44 739 /**
lypinator 0:bb348c97df44 740 * @}
lypinator 0:bb348c97df44 741 */
lypinator 0:bb348c97df44 742
lypinator 0:bb348c97df44 743 /**
lypinator 0:bb348c97df44 744 * @}
lypinator 0:bb348c97df44 745 */
lypinator 0:bb348c97df44 746
lypinator 0:bb348c97df44 747 /**
lypinator 0:bb348c97df44 748 * @}
lypinator 0:bb348c97df44 749 */
lypinator 0:bb348c97df44 750
lypinator 0:bb348c97df44 751 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/