DevLibMemoryController - Initial commit

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Initial commit

mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_tim.h@0:bb348c97df44, 2020-09-16 (annotated)

Committer:: lypinator
Date:: Wed Sep 16 01:11:49 2020 +0000
Revision:: 0:bb348c97df44

Added PWM

Who changed what in which revision?

User	Revision	Line number	New contents of line
lypinator	0:bb348c97df44	1	/**
lypinator	0:bb348c97df44	2	******************************************************************************
lypinator	0:bb348c97df44	3	* @file stm32f4xx_ll_tim.h
lypinator	0:bb348c97df44	4	* @author MCD Application Team
lypinator	0:bb348c97df44	5	* @brief Header file of TIM LL module.
lypinator	0:bb348c97df44	6	******************************************************************************
lypinator	0:bb348c97df44	7	* @attention
lypinator	0:bb348c97df44	8	*
lypinator	0:bb348c97df44	9	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
lypinator	0:bb348c97df44	10	*
lypinator	0:bb348c97df44	11	* Redistribution and use in source and binary forms, with or without modification,
lypinator	0:bb348c97df44	12	* are permitted provided that the following conditions are met:
lypinator	0:bb348c97df44	13	* 1. Redistributions of source code must retain the above copyright notice,
lypinator	0:bb348c97df44	14	* this list of conditions and the following disclaimer.
lypinator	0:bb348c97df44	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
lypinator	0:bb348c97df44	16	* this list of conditions and the following disclaimer in the documentation
lypinator	0:bb348c97df44	17	* and/or other materials provided with the distribution.
lypinator	0:bb348c97df44	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
lypinator	0:bb348c97df44	19	* may be used to endorse or promote products derived from this software
lypinator	0:bb348c97df44	20	* without specific prior written permission.
lypinator	0:bb348c97df44	21	*
lypinator	0:bb348c97df44	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
lypinator	0:bb348c97df44	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
lypinator	0:bb348c97df44	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
lypinator	0:bb348c97df44	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
lypinator	0:bb348c97df44	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
lypinator	0:bb348c97df44	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
lypinator	0:bb348c97df44	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
lypinator	0:bb348c97df44	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
lypinator	0:bb348c97df44	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
lypinator	0:bb348c97df44	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
lypinator	0:bb348c97df44	32	*
lypinator	0:bb348c97df44	33	******************************************************************************
lypinator	0:bb348c97df44	34	*/
lypinator	0:bb348c97df44	35
lypinator	0:bb348c97df44	36	/* Define to prevent recursive inclusion -------------------------------------*/
lypinator	0:bb348c97df44	37	#ifndef __STM32F4xx_LL_TIM_H
lypinator	0:bb348c97df44	38	#define __STM32F4xx_LL_TIM_H
lypinator	0:bb348c97df44	39
lypinator	0:bb348c97df44	40	#ifdef __cplusplus
lypinator	0:bb348c97df44	41	extern "C" {
lypinator	0:bb348c97df44	42	#endif
lypinator	0:bb348c97df44	43
lypinator	0:bb348c97df44	44	/* Includes ------------------------------------------------------------------*/
lypinator	0:bb348c97df44	45	#include "stm32f4xx.h"
lypinator	0:bb348c97df44	46
lypinator	0:bb348c97df44	47	/** @addtogroup STM32F4xx_LL_Driver
lypinator	0:bb348c97df44	48	* @{
lypinator	0:bb348c97df44	49	*/
lypinator	0:bb348c97df44	50
lypinator	0:bb348c97df44	51	#if defined (TIM1) \|\| defined (TIM2) \|\| defined (TIM3) \|\| defined (TIM4) \|\| defined (TIM5) \|\| defined (TIM6) \|\| defined (TIM7) \|\| defined (TIM8) \|\| defined (TIM9) \|\| defined (TIM10) \|\| defined (TIM11) \|\| defined (TIM12) \|\| defined (TIM13) \|\| defined (TIM14)
lypinator	0:bb348c97df44	52
lypinator	0:bb348c97df44	53	/** @defgroup TIM_LL TIM
lypinator	0:bb348c97df44	54	* @{
lypinator	0:bb348c97df44	55	*/
lypinator	0:bb348c97df44	56
lypinator	0:bb348c97df44	57	/* Private types -------------------------------------------------------------*/
lypinator	0:bb348c97df44	58	/* Private variables ---------------------------------------------------------*/
lypinator	0:bb348c97df44	59	/** @defgroup TIM_LL_Private_Variables TIM Private Variables
lypinator	0:bb348c97df44	60	* @{
lypinator	0:bb348c97df44	61	*/
lypinator	0:bb348c97df44	62	static const uint8_t OFFSET_TAB_CCMRx[] =
lypinator	0:bb348c97df44	63	{
lypinator	0:bb348c97df44	64	0x00U, /* 0: TIMx_CH1 */
lypinator	0:bb348c97df44	65	0x00U, /* 1: TIMx_CH1N */
lypinator	0:bb348c97df44	66	0x00U, /* 2: TIMx_CH2 */
lypinator	0:bb348c97df44	67	0x00U, /* 3: TIMx_CH2N */
lypinator	0:bb348c97df44	68	0x04U, /* 4: TIMx_CH3 */
lypinator	0:bb348c97df44	69	0x04U, /* 5: TIMx_CH3N */
lypinator	0:bb348c97df44	70	0x04U /* 6: TIMx_CH4 */
lypinator	0:bb348c97df44	71	};
lypinator	0:bb348c97df44	72
lypinator	0:bb348c97df44	73	static const uint8_t SHIFT_TAB_OCxx[] =
lypinator	0:bb348c97df44	74	{
lypinator	0:bb348c97df44	75	0U, /* 0: OC1M, OC1FE, OC1PE */
lypinator	0:bb348c97df44	76	0U, /* 1: - NA */
lypinator	0:bb348c97df44	77	8U, /* 2: OC2M, OC2FE, OC2PE */
lypinator	0:bb348c97df44	78	0U, /* 3: - NA */
lypinator	0:bb348c97df44	79	0U, /* 4: OC3M, OC3FE, OC3PE */
lypinator	0:bb348c97df44	80	0U, /* 5: - NA */
lypinator	0:bb348c97df44	81	8U /* 6: OC4M, OC4FE, OC4PE */
lypinator	0:bb348c97df44	82	};
lypinator	0:bb348c97df44	83
lypinator	0:bb348c97df44	84	static const uint8_t SHIFT_TAB_ICxx[] =
lypinator	0:bb348c97df44	85	{
lypinator	0:bb348c97df44	86	0U, /* 0: CC1S, IC1PSC, IC1F */
lypinator	0:bb348c97df44	87	0U, /* 1: - NA */
lypinator	0:bb348c97df44	88	8U, /* 2: CC2S, IC2PSC, IC2F */
lypinator	0:bb348c97df44	89	0U, /* 3: - NA */
lypinator	0:bb348c97df44	90	0U, /* 4: CC3S, IC3PSC, IC3F */
lypinator	0:bb348c97df44	91	0U, /* 5: - NA */
lypinator	0:bb348c97df44	92	8U /* 6: CC4S, IC4PSC, IC4F */
lypinator	0:bb348c97df44	93	};
lypinator	0:bb348c97df44	94
lypinator	0:bb348c97df44	95	static const uint8_t SHIFT_TAB_CCxP[] =
lypinator	0:bb348c97df44	96	{
lypinator	0:bb348c97df44	97	0U, /* 0: CC1P */
lypinator	0:bb348c97df44	98	2U, /* 1: CC1NP */
lypinator	0:bb348c97df44	99	4U, /* 2: CC2P */
lypinator	0:bb348c97df44	100	6U, /* 3: CC2NP */
lypinator	0:bb348c97df44	101	8U, /* 4: CC3P */
lypinator	0:bb348c97df44	102	10U, /* 5: CC3NP */
lypinator	0:bb348c97df44	103	12U /* 6: CC4P */
lypinator	0:bb348c97df44	104	};
lypinator	0:bb348c97df44	105
lypinator	0:bb348c97df44	106	static const uint8_t SHIFT_TAB_OISx[] =
lypinator	0:bb348c97df44	107	{
lypinator	0:bb348c97df44	108	0U, /* 0: OIS1 */
lypinator	0:bb348c97df44	109	1U, /* 1: OIS1N */
lypinator	0:bb348c97df44	110	2U, /* 2: OIS2 */
lypinator	0:bb348c97df44	111	3U, /* 3: OIS2N */
lypinator	0:bb348c97df44	112	4U, /* 4: OIS3 */
lypinator	0:bb348c97df44	113	5U, /* 5: OIS3N */
lypinator	0:bb348c97df44	114	6U /* 6: OIS4 */
lypinator	0:bb348c97df44	115	};
lypinator	0:bb348c97df44	116	/**
lypinator	0:bb348c97df44	117	* @}
lypinator	0:bb348c97df44	118	*/
lypinator	0:bb348c97df44	119
lypinator	0:bb348c97df44	120
lypinator	0:bb348c97df44	121	/* Private constants ---------------------------------------------------------*/
lypinator	0:bb348c97df44	122	/** @defgroup TIM_LL_Private_Constants TIM Private Constants
lypinator	0:bb348c97df44	123	* @{
lypinator	0:bb348c97df44	124	*/
lypinator	0:bb348c97df44	125
lypinator	0:bb348c97df44	126
lypinator	0:bb348c97df44	127	/* Remap mask definitions */
lypinator	0:bb348c97df44	128	#define TIMx_OR_RMP_SHIFT 16U
lypinator	0:bb348c97df44	129	#define TIMx_OR_RMP_MASK 0x0000FFFFU
lypinator	0:bb348c97df44	130	#define TIM2_OR_RMP_MASK (TIM_OR_ITR1_RMP << TIMx_OR_RMP_SHIFT)
lypinator	0:bb348c97df44	131	#define TIM5_OR_RMP_MASK (TIM_OR_TI4_RMP << TIMx_OR_RMP_SHIFT)
lypinator	0:bb348c97df44	132	#define TIM11_OR_RMP_MASK (TIM_OR_TI1_RMP << TIMx_OR_RMP_SHIFT)
lypinator	0:bb348c97df44	133
lypinator	0:bb348c97df44	134	/* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */
lypinator	0:bb348c97df44	135	#define DT_DELAY_1 ((uint8_t)0x7FU)
lypinator	0:bb348c97df44	136	#define DT_DELAY_2 ((uint8_t)0x3FU)
lypinator	0:bb348c97df44	137	#define DT_DELAY_3 ((uint8_t)0x1FU)
lypinator	0:bb348c97df44	138	#define DT_DELAY_4 ((uint8_t)0x1FU)
lypinator	0:bb348c97df44	139
lypinator	0:bb348c97df44	140	/* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */
lypinator	0:bb348c97df44	141	#define DT_RANGE_1 ((uint8_t)0x00U)
lypinator	0:bb348c97df44	142	#define DT_RANGE_2 ((uint8_t)0x80U)
lypinator	0:bb348c97df44	143	#define DT_RANGE_3 ((uint8_t)0xC0U)
lypinator	0:bb348c97df44	144	#define DT_RANGE_4 ((uint8_t)0xE0U)
lypinator	0:bb348c97df44	145
lypinator	0:bb348c97df44	146
lypinator	0:bb348c97df44	147	/**
lypinator	0:bb348c97df44	148	* @}
lypinator	0:bb348c97df44	149	*/
lypinator	0:bb348c97df44	150
lypinator	0:bb348c97df44	151	/* Private macros ------------------------------------------------------------*/
lypinator	0:bb348c97df44	152	/** @defgroup TIM_LL_Private_Macros TIM Private Macros
lypinator	0:bb348c97df44	153	* @{
lypinator	0:bb348c97df44	154	*/
lypinator	0:bb348c97df44	155	/** @brief Convert channel id into channel index.
lypinator	0:bb348c97df44	156	* @param __CHANNEL__ This parameter can be one of the following values:
lypinator	0:bb348c97df44	157	* @arg @ref LL_TIM_CHANNEL_CH1
lypinator	0:bb348c97df44	158	* @arg @ref LL_TIM_CHANNEL_CH1N
lypinator	0:bb348c97df44	159	* @arg @ref LL_TIM_CHANNEL_CH2
lypinator	0:bb348c97df44	160	* @arg @ref LL_TIM_CHANNEL_CH2N
lypinator	0:bb348c97df44	161	* @arg @ref LL_TIM_CHANNEL_CH3
lypinator	0:bb348c97df44	162	* @arg @ref LL_TIM_CHANNEL_CH3N
lypinator	0:bb348c97df44	163	* @arg @ref LL_TIM_CHANNEL_CH4
lypinator	0:bb348c97df44	164	* @retval none
lypinator	0:bb348c97df44	165	*/
lypinator	0:bb348c97df44	166	#define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
lypinator	0:bb348c97df44	167	(((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
lypinator	0:bb348c97df44	168	((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
lypinator	0:bb348c97df44	169	((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
lypinator	0:bb348c97df44	170	((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
lypinator	0:bb348c97df44	171	((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
lypinator	0:bb348c97df44	172	((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U : 6U)
lypinator	0:bb348c97df44	173
lypinator	0:bb348c97df44	174	/** @brief Calculate the deadtime sampling period(in ps).
lypinator	0:bb348c97df44	175	* @param __TIMCLK__ timer input clock frequency (in Hz).
lypinator	0:bb348c97df44	176	* @param __CKD__ This parameter can be one of the following values:
lypinator	0:bb348c97df44	177	* @arg @ref LL_TIM_CLOCKDIVISION_DIV1
lypinator	0:bb348c97df44	178	* @arg @ref LL_TIM_CLOCKDIVISION_DIV2
lypinator	0:bb348c97df44	179	* @arg @ref LL_TIM_CLOCKDIVISION_DIV4
lypinator	0:bb348c97df44	180	* @retval none
lypinator	0:bb348c97df44	181	*/
lypinator	0:bb348c97df44	182	#define TIM_CALC_DTS(__TIMCLK__, __CKD__) \
lypinator	0:bb348c97df44	183	(((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \
lypinator	0:bb348c97df44	184	((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
lypinator	0:bb348c97df44	185	((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))
lypinator	0:bb348c97df44	186	/**
lypinator	0:bb348c97df44	187	* @}
lypinator	0:bb348c97df44	188	*/
lypinator	0:bb348c97df44	189
lypinator	0:bb348c97df44	190
lypinator	0:bb348c97df44	191	/* Exported types ------------------------------------------------------------*/
lypinator	0:bb348c97df44	192	#if defined(USE_FULL_LL_DRIVER)
lypinator	0:bb348c97df44	193	/** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
lypinator	0:bb348c97df44	194	* @{
lypinator	0:bb348c97df44	195	*/
lypinator	0:bb348c97df44	196
lypinator	0:bb348c97df44	197	/**
lypinator	0:bb348c97df44	198	* @brief TIM Time Base configuration structure definition.
lypinator	0:bb348c97df44	199	*/
lypinator	0:bb348c97df44	200	typedef struct
lypinator	0:bb348c97df44	201	{
lypinator	0:bb348c97df44	202	uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
lypinator	0:bb348c97df44	203	This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
lypinator	0:bb348c97df44	204
lypinator	0:bb348c97df44	205	This feature can be modified afterwards using unitary function @ref LL_TIM_SetPrescaler().*/
lypinator	0:bb348c97df44	206
lypinator	0:bb348c97df44	207	uint32_t CounterMode; /*!< Specifies the counter mode.
lypinator	0:bb348c97df44	208	This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
lypinator	0:bb348c97df44	209
lypinator	0:bb348c97df44	210	This feature can be modified afterwards using unitary function @ref LL_TIM_SetCounterMode().*/
lypinator	0:bb348c97df44	211
lypinator	0:bb348c97df44	212	uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active
lypinator	0:bb348c97df44	213	Auto-Reload Register at the next update event.
lypinator	0:bb348c97df44	214	This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
lypinator	0:bb348c97df44	215	Some timer instances may support 32 bits counters. In that case this parameter must be a number between 0x0000 and 0xFFFFFFFF.
lypinator	0:bb348c97df44	216
lypinator	0:bb348c97df44	217	This feature can be modified afterwards using unitary function @ref LL_TIM_SetAutoReload().*/
lypinator	0:bb348c97df44	218
lypinator	0:bb348c97df44	219	uint32_t ClockDivision; /*!< Specifies the clock division.
lypinator	0:bb348c97df44	220	This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
lypinator	0:bb348c97df44	221
lypinator	0:bb348c97df44	222	This feature can be modified afterwards using unitary function @ref LL_TIM_SetClockDivision().*/
lypinator	0:bb348c97df44	223
lypinator	0:bb348c97df44	224	uint8_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
lypinator	0:bb348c97df44	225	reaches zero, an update event is generated and counting restarts
lypinator	0:bb348c97df44	226	from the RCR value (N).
lypinator	0:bb348c97df44	227	This means in PWM mode that (N+1) corresponds to:
lypinator	0:bb348c97df44	228	- the number of PWM periods in edge-aligned mode
lypinator	0:bb348c97df44	229	- the number of half PWM period in center-aligned mode
lypinator	0:bb348c97df44	230	This parameter must be a number between 0x00 and 0xFF.
lypinator	0:bb348c97df44	231
lypinator	0:bb348c97df44	232	This feature can be modified afterwards using unitary function @ref LL_TIM_SetRepetitionCounter().*/
lypinator	0:bb348c97df44	233	} LL_TIM_InitTypeDef;
lypinator	0:bb348c97df44	234
lypinator	0:bb348c97df44	235	/**
lypinator	0:bb348c97df44	236	* @brief TIM Output Compare configuration structure definition.
lypinator	0:bb348c97df44	237	*/
lypinator	0:bb348c97df44	238	typedef struct
lypinator	0:bb348c97df44	239	{
lypinator	0:bb348c97df44	240	uint32_t OCMode; /*!< Specifies the output mode.
lypinator	0:bb348c97df44	241	This parameter can be a value of @ref TIM_LL_EC_OCMODE.
lypinator	0:bb348c97df44	242
lypinator	0:bb348c97df44	243	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetMode().*/
lypinator	0:bb348c97df44	244
lypinator	0:bb348c97df44	245	uint32_t OCState; /*!< Specifies the TIM Output Compare state.
lypinator	0:bb348c97df44	246	This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
lypinator	0:bb348c97df44	247
lypinator	0:bb348c97df44	248	This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
lypinator	0:bb348c97df44	249
lypinator	0:bb348c97df44	250	uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state.
lypinator	0:bb348c97df44	251	This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
lypinator	0:bb348c97df44	252
lypinator	0:bb348c97df44	253	This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
lypinator	0:bb348c97df44	254
lypinator	0:bb348c97df44	255	uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
lypinator	0:bb348c97df44	256	This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
lypinator	0:bb348c97df44	257
lypinator	0:bb348c97df44	258	This feature can be modified afterwards using unitary function LL_TIM_OC_SetCompareCHx (x=1..6).*/
lypinator	0:bb348c97df44	259
lypinator	0:bb348c97df44	260	uint32_t OCPolarity; /*!< Specifies the output polarity.
lypinator	0:bb348c97df44	261	This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
lypinator	0:bb348c97df44	262
lypinator	0:bb348c97df44	263	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/
lypinator	0:bb348c97df44	264
lypinator	0:bb348c97df44	265	uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
lypinator	0:bb348c97df44	266	This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
lypinator	0:bb348c97df44	267
lypinator	0:bb348c97df44	268	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/
lypinator	0:bb348c97df44	269
lypinator	0:bb348c97df44	270
lypinator	0:bb348c97df44	271	uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
lypinator	0:bb348c97df44	272	This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
lypinator	0:bb348c97df44	273
lypinator	0:bb348c97df44	274	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/
lypinator	0:bb348c97df44	275
lypinator	0:bb348c97df44	276	uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
lypinator	0:bb348c97df44	277	This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
lypinator	0:bb348c97df44	278
lypinator	0:bb348c97df44	279	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/
lypinator	0:bb348c97df44	280	} LL_TIM_OC_InitTypeDef;
lypinator	0:bb348c97df44	281
lypinator	0:bb348c97df44	282	/**
lypinator	0:bb348c97df44	283	* @brief TIM Input Capture configuration structure definition.
lypinator	0:bb348c97df44	284	*/
lypinator	0:bb348c97df44	285
lypinator	0:bb348c97df44	286	typedef struct
lypinator	0:bb348c97df44	287	{
lypinator	0:bb348c97df44	288
lypinator	0:bb348c97df44	289	uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
lypinator	0:bb348c97df44	290	This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
lypinator	0:bb348c97df44	291
lypinator	0:bb348c97df44	292	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
lypinator	0:bb348c97df44	293
lypinator	0:bb348c97df44	294	uint32_t ICActiveInput; /*!< Specifies the input.
lypinator	0:bb348c97df44	295	This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
lypinator	0:bb348c97df44	296
lypinator	0:bb348c97df44	297	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
lypinator	0:bb348c97df44	298
lypinator	0:bb348c97df44	299	uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
lypinator	0:bb348c97df44	300	This parameter can be a value of @ref TIM_LL_EC_ICPSC.
lypinator	0:bb348c97df44	301
lypinator	0:bb348c97df44	302	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
lypinator	0:bb348c97df44	303
lypinator	0:bb348c97df44	304	uint32_t ICFilter; /*!< Specifies the input capture filter.
lypinator	0:bb348c97df44	305	This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
lypinator	0:bb348c97df44	306
lypinator	0:bb348c97df44	307	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
lypinator	0:bb348c97df44	308	} LL_TIM_IC_InitTypeDef;
lypinator	0:bb348c97df44	309
lypinator	0:bb348c97df44	310
lypinator	0:bb348c97df44	311	/**
lypinator	0:bb348c97df44	312	* @brief TIM Encoder interface configuration structure definition.
lypinator	0:bb348c97df44	313	*/
lypinator	0:bb348c97df44	314	typedef struct
lypinator	0:bb348c97df44	315	{
lypinator	0:bb348c97df44	316	uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4).
lypinator	0:bb348c97df44	317	This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
lypinator	0:bb348c97df44	318
lypinator	0:bb348c97df44	319	This feature can be modified afterwards using unitary function @ref LL_TIM_SetEncoderMode().*/
lypinator	0:bb348c97df44	320
lypinator	0:bb348c97df44	321	uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
lypinator	0:bb348c97df44	322	This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
lypinator	0:bb348c97df44	323
lypinator	0:bb348c97df44	324	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
lypinator	0:bb348c97df44	325
lypinator	0:bb348c97df44	326	uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source
lypinator	0:bb348c97df44	327	This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
lypinator	0:bb348c97df44	328
lypinator	0:bb348c97df44	329	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
lypinator	0:bb348c97df44	330
lypinator	0:bb348c97df44	331	uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
lypinator	0:bb348c97df44	332	This parameter can be a value of @ref TIM_LL_EC_ICPSC.
lypinator	0:bb348c97df44	333
lypinator	0:bb348c97df44	334	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
lypinator	0:bb348c97df44	335
lypinator	0:bb348c97df44	336	uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
lypinator	0:bb348c97df44	337	This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
lypinator	0:bb348c97df44	338
lypinator	0:bb348c97df44	339	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
lypinator	0:bb348c97df44	340
lypinator	0:bb348c97df44	341	uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input.
lypinator	0:bb348c97df44	342	This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
lypinator	0:bb348c97df44	343
lypinator	0:bb348c97df44	344	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
lypinator	0:bb348c97df44	345
lypinator	0:bb348c97df44	346	uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source
lypinator	0:bb348c97df44	347	This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
lypinator	0:bb348c97df44	348
lypinator	0:bb348c97df44	349	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
lypinator	0:bb348c97df44	350
lypinator	0:bb348c97df44	351	uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value.
lypinator	0:bb348c97df44	352	This parameter can be a value of @ref TIM_LL_EC_ICPSC.
lypinator	0:bb348c97df44	353
lypinator	0:bb348c97df44	354	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
lypinator	0:bb348c97df44	355
lypinator	0:bb348c97df44	356	uint32_t IC2Filter; /*!< Specifies the TI2 input filter.
lypinator	0:bb348c97df44	357	This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
lypinator	0:bb348c97df44	358
lypinator	0:bb348c97df44	359	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
lypinator	0:bb348c97df44	360
lypinator	0:bb348c97df44	361	} LL_TIM_ENCODER_InitTypeDef;
lypinator	0:bb348c97df44	362
lypinator	0:bb348c97df44	363	/**
lypinator	0:bb348c97df44	364	* @brief TIM Hall sensor interface configuration structure definition.
lypinator	0:bb348c97df44	365	*/
lypinator	0:bb348c97df44	366	typedef struct
lypinator	0:bb348c97df44	367	{
lypinator	0:bb348c97df44	368
lypinator	0:bb348c97df44	369	uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
lypinator	0:bb348c97df44	370	This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
lypinator	0:bb348c97df44	371
lypinator	0:bb348c97df44	372	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
lypinator	0:bb348c97df44	373
lypinator	0:bb348c97df44	374	uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
lypinator	0:bb348c97df44	375	Prescaler must be set to get a maximum counter period longer than the
lypinator	0:bb348c97df44	376	time interval between 2 consecutive changes on the Hall inputs.
lypinator	0:bb348c97df44	377	This parameter can be a value of @ref TIM_LL_EC_ICPSC.
lypinator	0:bb348c97df44	378
lypinator	0:bb348c97df44	379	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
lypinator	0:bb348c97df44	380
lypinator	0:bb348c97df44	381	uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
lypinator	0:bb348c97df44	382	This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
lypinator	0:bb348c97df44	383
lypinator	0:bb348c97df44	384	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
lypinator	0:bb348c97df44	385
lypinator	0:bb348c97df44	386	uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register.
lypinator	0:bb348c97df44	387	A positive pulse (TRGO event) is generated with a programmable delay every time
lypinator	0:bb348c97df44	388	a change occurs on the Hall inputs.
lypinator	0:bb348c97df44	389	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
lypinator	0:bb348c97df44	390
lypinator	0:bb348c97df44	391	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetCompareCH2().*/
lypinator	0:bb348c97df44	392	} LL_TIM_HALLSENSOR_InitTypeDef;
lypinator	0:bb348c97df44	393
lypinator	0:bb348c97df44	394	/**
lypinator	0:bb348c97df44	395	* @brief BDTR (Break and Dead Time) structure definition
lypinator	0:bb348c97df44	396	*/
lypinator	0:bb348c97df44	397	typedef struct
lypinator	0:bb348c97df44	398	{
lypinator	0:bb348c97df44	399	uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode.
lypinator	0:bb348c97df44	400	This parameter can be a value of @ref TIM_LL_EC_OSSR
lypinator	0:bb348c97df44	401
lypinator	0:bb348c97df44	402	This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates()
lypinator	0:bb348c97df44	403
lypinator	0:bb348c97df44	404	@note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */
lypinator	0:bb348c97df44	405
lypinator	0:bb348c97df44	406	uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state.
lypinator	0:bb348c97df44	407	This parameter can be a value of @ref TIM_LL_EC_OSSI
lypinator	0:bb348c97df44	408
lypinator	0:bb348c97df44	409	This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates()
lypinator	0:bb348c97df44	410
lypinator	0:bb348c97df44	411	@note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */
lypinator	0:bb348c97df44	412
lypinator	0:bb348c97df44	413	uint32_t LockLevel; /*!< Specifies the LOCK level parameters.
lypinator	0:bb348c97df44	414	This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL
lypinator	0:bb348c97df44	415
lypinator	0:bb348c97df44	416	@note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register
lypinator	0:bb348c97df44	417	has been written, their content is frozen until the next reset.*/
lypinator	0:bb348c97df44	418
lypinator	0:bb348c97df44	419	uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the
lypinator	0:bb348c97df44	420	switching-on of the outputs.
lypinator	0:bb348c97df44	421	This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF.
lypinator	0:bb348c97df44	422
lypinator	0:bb348c97df44	423	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetDeadTime()
lypinator	0:bb348c97df44	424
lypinator	0:bb348c97df44	425	@note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed. */
lypinator	0:bb348c97df44	426
lypinator	0:bb348c97df44	427	uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not.
lypinator	0:bb348c97df44	428	This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE
lypinator	0:bb348c97df44	429
lypinator	0:bb348c97df44	430	This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK()
lypinator	0:bb348c97df44	431
lypinator	0:bb348c97df44	432	@note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
lypinator	0:bb348c97df44	433
lypinator	0:bb348c97df44	434	uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
lypinator	0:bb348c97df44	435	This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY
lypinator	0:bb348c97df44	436
lypinator	0:bb348c97df44	437	This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK()
lypinator	0:bb348c97df44	438
lypinator	0:bb348c97df44	439	@note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
lypinator	0:bb348c97df44	440
lypinator	0:bb348c97df44	441	uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
lypinator	0:bb348c97df44	442	This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE
lypinator	0:bb348c97df44	443
lypinator	0:bb348c97df44	444	This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput()
lypinator	0:bb348c97df44	445
lypinator	0:bb348c97df44	446	@note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
lypinator	0:bb348c97df44	447	} LL_TIM_BDTR_InitTypeDef;
lypinator	0:bb348c97df44	448
lypinator	0:bb348c97df44	449	/**
lypinator	0:bb348c97df44	450	* @}
lypinator	0:bb348c97df44	451	*/
lypinator	0:bb348c97df44	452	#endif /* USE_FULL_LL_DRIVER */
lypinator	0:bb348c97df44	453
lypinator	0:bb348c97df44	454	/* Exported constants --------------------------------------------------------*/
lypinator	0:bb348c97df44	455	/** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
lypinator	0:bb348c97df44	456	* @{
lypinator	0:bb348c97df44	457	*/
lypinator	0:bb348c97df44	458
lypinator	0:bb348c97df44	459	/** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
lypinator	0:bb348c97df44	460	* @brief Flags defines which can be used with LL_TIM_ReadReg function.
lypinator	0:bb348c97df44	461	* @{
lypinator	0:bb348c97df44	462	*/
lypinator	0:bb348c97df44	463	#define LL_TIM_SR_UIF TIM_SR_UIF /!< Update interrupt flag /
lypinator	0:bb348c97df44	464	#define LL_TIM_SR_CC1IF TIM_SR_CC1IF /!< Capture/compare 1 interrupt flag /
lypinator	0:bb348c97df44	465	#define LL_TIM_SR_CC2IF TIM_SR_CC2IF /!< Capture/compare 2 interrupt flag /
lypinator	0:bb348c97df44	466	#define LL_TIM_SR_CC3IF TIM_SR_CC3IF /!< Capture/compare 3 interrupt flag /
lypinator	0:bb348c97df44	467	#define LL_TIM_SR_CC4IF TIM_SR_CC4IF /!< Capture/compare 4 interrupt flag /
lypinator	0:bb348c97df44	468	#define LL_TIM_SR_COMIF TIM_SR_COMIF /!< COM interrupt flag /
lypinator	0:bb348c97df44	469	#define LL_TIM_SR_TIF TIM_SR_TIF /!< Trigger interrupt flag /
lypinator	0:bb348c97df44	470	#define LL_TIM_SR_BIF TIM_SR_BIF /!< Break interrupt flag /
lypinator	0:bb348c97df44	471	#define LL_TIM_SR_CC1OF TIM_SR_CC1OF /!< Capture/Compare 1 overcapture flag /
lypinator	0:bb348c97df44	472	#define LL_TIM_SR_CC2OF TIM_SR_CC2OF /!< Capture/Compare 2 overcapture flag /
lypinator	0:bb348c97df44	473	#define LL_TIM_SR_CC3OF TIM_SR_CC3OF /!< Capture/Compare 3 overcapture flag /
lypinator	0:bb348c97df44	474	#define LL_TIM_SR_CC4OF TIM_SR_CC4OF /!< Capture/Compare 4 overcapture flag /
lypinator	0:bb348c97df44	475	/**
lypinator	0:bb348c97df44	476	* @}
lypinator	0:bb348c97df44	477	*/
lypinator	0:bb348c97df44	478
lypinator	0:bb348c97df44	479	#if defined(USE_FULL_LL_DRIVER)
lypinator	0:bb348c97df44	480	/** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable
lypinator	0:bb348c97df44	481	* @{
lypinator	0:bb348c97df44	482	*/
lypinator	0:bb348c97df44	483	#define LL_TIM_BREAK_DISABLE 0x00000000U /!< Break function disabled /
lypinator	0:bb348c97df44	484	#define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /!< Break function enabled /
lypinator	0:bb348c97df44	485	/**
lypinator	0:bb348c97df44	486	* @}
lypinator	0:bb348c97df44	487	*/
lypinator	0:bb348c97df44	488
lypinator	0:bb348c97df44	489	/** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable
lypinator	0:bb348c97df44	490	* @{
lypinator	0:bb348c97df44	491	*/
lypinator	0:bb348c97df44	492	#define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /!< MOE can be set only by software /
lypinator	0:bb348c97df44	493	#define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /!< MOE can be set by software or automatically at the next update event /
lypinator	0:bb348c97df44	494	/**
lypinator	0:bb348c97df44	495	* @}
lypinator	0:bb348c97df44	496	*/
lypinator	0:bb348c97df44	497	#endif /* USE_FULL_LL_DRIVER */
lypinator	0:bb348c97df44	498
lypinator	0:bb348c97df44	499	/** @defgroup TIM_LL_EC_IT IT Defines
lypinator	0:bb348c97df44	500	* @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions.
lypinator	0:bb348c97df44	501	* @{
lypinator	0:bb348c97df44	502	*/
lypinator	0:bb348c97df44	503	#define LL_TIM_DIER_UIE TIM_DIER_UIE /!< Update interrupt enable /
lypinator	0:bb348c97df44	504	#define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /!< Capture/compare 1 interrupt enable /
lypinator	0:bb348c97df44	505	#define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /!< Capture/compare 2 interrupt enable /
lypinator	0:bb348c97df44	506	#define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /!< Capture/compare 3 interrupt enable /
lypinator	0:bb348c97df44	507	#define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /!< Capture/compare 4 interrupt enable /
lypinator	0:bb348c97df44	508	#define LL_TIM_DIER_COMIE TIM_DIER_COMIE /!< COM interrupt enable /
lypinator	0:bb348c97df44	509	#define LL_TIM_DIER_TIE TIM_DIER_TIE /!< Trigger interrupt enable /
lypinator	0:bb348c97df44	510	#define LL_TIM_DIER_BIE TIM_DIER_BIE /!< Break interrupt enable /
lypinator	0:bb348c97df44	511	/**
lypinator	0:bb348c97df44	512	* @}
lypinator	0:bb348c97df44	513	*/
lypinator	0:bb348c97df44	514
lypinator	0:bb348c97df44	515	/** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
lypinator	0:bb348c97df44	516	* @{
lypinator	0:bb348c97df44	517	*/
lypinator	0:bb348c97df44	518	#define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request /
lypinator	0:bb348c97df44	519	#define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /!< Only counter overflow/underflow generates an update request /
lypinator	0:bb348c97df44	520	/**
lypinator	0:bb348c97df44	521	* @}
lypinator	0:bb348c97df44	522	*/
lypinator	0:bb348c97df44	523
lypinator	0:bb348c97df44	524	/** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
lypinator	0:bb348c97df44	525	* @{
lypinator	0:bb348c97df44	526	*/
lypinator	0:bb348c97df44	527	#define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /!< Counter is not stopped at update event /
lypinator	0:bb348c97df44	528	#define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /!< Counter stops counting at the next update event /
lypinator	0:bb348c97df44	529	/**
lypinator	0:bb348c97df44	530	* @}
lypinator	0:bb348c97df44	531	*/
lypinator	0:bb348c97df44	532
lypinator	0:bb348c97df44	533	/** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
lypinator	0:bb348c97df44	534	* @{
lypinator	0:bb348c97df44	535	*/
lypinator	0:bb348c97df44	536	#define LL_TIM_COUNTERMODE_UP 0x00000000U /!<Counter used as upcounter /
lypinator	0:bb348c97df44	537	#define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /!< Counter used as downcounter /
lypinator	0:bb348c97df44	538	#define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_0 /!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. /
lypinator	0:bb348c97df44	539	#define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_1 /!<The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up /
lypinator	0:bb348c97df44	540	#define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. /
lypinator	0:bb348c97df44	541	/**
lypinator	0:bb348c97df44	542	* @}
lypinator	0:bb348c97df44	543	*/
lypinator	0:bb348c97df44	544
lypinator	0:bb348c97df44	545	/** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
lypinator	0:bb348c97df44	546	* @{
lypinator	0:bb348c97df44	547	*/
lypinator	0:bb348c97df44	548	#define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U /!< tDTS=tCK_INT /
lypinator	0:bb348c97df44	549	#define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /!< tDTS=2tCK_INT */
lypinator	0:bb348c97df44	550	#define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /!< tDTS=4tCK_INT */
lypinator	0:bb348c97df44	551	/**
lypinator	0:bb348c97df44	552	* @}
lypinator	0:bb348c97df44	553	*/
lypinator	0:bb348c97df44	554
lypinator	0:bb348c97df44	555	/** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
lypinator	0:bb348c97df44	556	* @{
lypinator	0:bb348c97df44	557	*/
lypinator	0:bb348c97df44	558	#define LL_TIM_COUNTERDIRECTION_UP 0x00000000U /!< Timer counter counts up /
lypinator	0:bb348c97df44	559	#define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /!< Timer counter counts down /
lypinator	0:bb348c97df44	560	/**
lypinator	0:bb348c97df44	561	* @}
lypinator	0:bb348c97df44	562	*/
lypinator	0:bb348c97df44	563
lypinator	0:bb348c97df44	564	/** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare Update Source
lypinator	0:bb348c97df44	565	* @{
lypinator	0:bb348c97df44	566	*/
lypinator	0:bb348c97df44	567	#define LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U /!< Capture/compare control bits are updated by setting the COMG bit only /
lypinator	0:bb348c97df44	568	#define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS /!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) /
lypinator	0:bb348c97df44	569	/**
lypinator	0:bb348c97df44	570	* @}
lypinator	0:bb348c97df44	571	*/
lypinator	0:bb348c97df44	572
lypinator	0:bb348c97df44	573	/** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
lypinator	0:bb348c97df44	574	* @{
lypinator	0:bb348c97df44	575	*/
lypinator	0:bb348c97df44	576	#define LL_TIM_CCDMAREQUEST_CC 0x00000000U /!< CCx DMA request sent when CCx event occurs /
lypinator	0:bb348c97df44	577	#define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /!< CCx DMA requests sent when update event occurs /
lypinator	0:bb348c97df44	578	/**
lypinator	0:bb348c97df44	579	* @}
lypinator	0:bb348c97df44	580	*/
lypinator	0:bb348c97df44	581
lypinator	0:bb348c97df44	582	/** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level
lypinator	0:bb348c97df44	583	* @{
lypinator	0:bb348c97df44	584	*/
lypinator	0:bb348c97df44	585	#define LL_TIM_LOCKLEVEL_OFF 0x00000000U /!< LOCK OFF - No bit is write protected /
lypinator	0:bb348c97df44	586	#define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /!< LOCK Level 1 /
lypinator	0:bb348c97df44	587	#define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /!< LOCK Level 2 /
lypinator	0:bb348c97df44	588	#define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /!< LOCK Level 3 /
lypinator	0:bb348c97df44	589	/**
lypinator	0:bb348c97df44	590	* @}
lypinator	0:bb348c97df44	591	*/
lypinator	0:bb348c97df44	592
lypinator	0:bb348c97df44	593	/** @defgroup TIM_LL_EC_CHANNEL Channel
lypinator	0:bb348c97df44	594	* @{
lypinator	0:bb348c97df44	595	*/
lypinator	0:bb348c97df44	596	#define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /!< Timer input/output channel 1 /
lypinator	0:bb348c97df44	597	#define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /!< Timer complementary output channel 1 /
lypinator	0:bb348c97df44	598	#define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /!< Timer input/output channel 2 /
lypinator	0:bb348c97df44	599	#define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /!< Timer complementary output channel 2 /
lypinator	0:bb348c97df44	600	#define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /!< Timer input/output channel 3 /
lypinator	0:bb348c97df44	601	#define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /!< Timer complementary output channel 3 /
lypinator	0:bb348c97df44	602	#define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /!< Timer input/output channel 4 /
lypinator	0:bb348c97df44	603	/**
lypinator	0:bb348c97df44	604	* @}
lypinator	0:bb348c97df44	605	*/
lypinator	0:bb348c97df44	606
lypinator	0:bb348c97df44	607	#if defined(USE_FULL_LL_DRIVER)
lypinator	0:bb348c97df44	608	/** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
lypinator	0:bb348c97df44	609	* @{
lypinator	0:bb348c97df44	610	*/
lypinator	0:bb348c97df44	611	#define LL_TIM_OCSTATE_DISABLE 0x00000000U /!< OCx is not active /
lypinator	0:bb348c97df44	612	#define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /!< OCx signal is output on the corresponding output pin /
lypinator	0:bb348c97df44	613	/**
lypinator	0:bb348c97df44	614	* @}
lypinator	0:bb348c97df44	615	*/
lypinator	0:bb348c97df44	616	#endif /* USE_FULL_LL_DRIVER */
lypinator	0:bb348c97df44	617
lypinator	0:bb348c97df44	618	/** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
lypinator	0:bb348c97df44	619	* @{
lypinator	0:bb348c97df44	620	*/
lypinator	0:bb348c97df44	621	#define LL_TIM_OCMODE_FROZEN 0x00000000U /!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level /
lypinator	0:bb348c97df44	622	#define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /!<OCyREF is forced high on compare match/
lypinator	0:bb348c97df44	623	#define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /!<OCyREF is forced low on compare match/
lypinator	0:bb348c97df44	624	#define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_0) /!<OCyREF toggles on compare match/
lypinator	0:bb348c97df44	625	#define LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /!<OCyREF is forced low/
lypinator	0:bb348c97df44	626	#define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_0) /!<OCyREF is forced high/
lypinator	0:bb348c97df44	627	#define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_1) /!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active./
lypinator	0:bb348c97df44	628	#define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_0) /!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active. In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive/
lypinator	0:bb348c97df44	629	/**
lypinator	0:bb348c97df44	630	* @}
lypinator	0:bb348c97df44	631	*/
lypinator	0:bb348c97df44	632
lypinator	0:bb348c97df44	633	/** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
lypinator	0:bb348c97df44	634	* @{
lypinator	0:bb348c97df44	635	*/
lypinator	0:bb348c97df44	636	#define LL_TIM_OCPOLARITY_HIGH 0x00000000U /!< OCxactive high/
lypinator	0:bb348c97df44	637	#define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /!< OCxactive low/
lypinator	0:bb348c97df44	638	/**
lypinator	0:bb348c97df44	639	* @}
lypinator	0:bb348c97df44	640	*/
lypinator	0:bb348c97df44	641
lypinator	0:bb348c97df44	642	/** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State
lypinator	0:bb348c97df44	643	* @{
lypinator	0:bb348c97df44	644	*/
lypinator	0:bb348c97df44	645	#define LL_TIM_OCIDLESTATE_LOW 0x00000000U /!<OCx=0 (after a dead-time if OC is implemented) when MOE=0/
lypinator	0:bb348c97df44	646	#define LL_TIM_OCIDLESTATE_HIGH TIM_CR2_OIS1 /!<OCx=1 (after a dead-time if OC is implemented) when MOE=0/
lypinator	0:bb348c97df44	647	/**
lypinator	0:bb348c97df44	648	* @}
lypinator	0:bb348c97df44	649	*/
lypinator	0:bb348c97df44	650
lypinator	0:bb348c97df44	651
lypinator	0:bb348c97df44	652	/** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection
lypinator	0:bb348c97df44	653	* @{
lypinator	0:bb348c97df44	654	*/
lypinator	0:bb348c97df44	655	#define LL_TIM_ACTIVEINPUT_DIRECTTI (TIM_CCMR1_CC1S_0 << 16U) /!< ICx is mapped on TIx /
lypinator	0:bb348c97df44	656	#define LL_TIM_ACTIVEINPUT_INDIRECTTI (TIM_CCMR1_CC1S_1 << 16U) /!< ICx is mapped on TIy /
lypinator	0:bb348c97df44	657	#define LL_TIM_ACTIVEINPUT_TRC (TIM_CCMR1_CC1S << 16U) /!< ICx is mapped on TRC /
lypinator	0:bb348c97df44	658	/**
lypinator	0:bb348c97df44	659	* @}
lypinator	0:bb348c97df44	660	*/
lypinator	0:bb348c97df44	661
lypinator	0:bb348c97df44	662	/** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
lypinator	0:bb348c97df44	663	* @{
lypinator	0:bb348c97df44	664	*/
lypinator	0:bb348c97df44	665	#define LL_TIM_ICPSC_DIV1 0x00000000U /!< No prescaler, capture is done each time an edge is detected on the capture input /
lypinator	0:bb348c97df44	666	#define LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U) /!< Capture is done once every 2 events /
lypinator	0:bb348c97df44	667	#define LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U) /!< Capture is done once every 4 events /
lypinator	0:bb348c97df44	668	#define LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U) /!< Capture is done once every 8 events /
lypinator	0:bb348c97df44	669	/**
lypinator	0:bb348c97df44	670	* @}
lypinator	0:bb348c97df44	671	*/
lypinator	0:bb348c97df44	672
lypinator	0:bb348c97df44	673	/** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter
lypinator	0:bb348c97df44	674	* @{
lypinator	0:bb348c97df44	675	*/
lypinator	0:bb348c97df44	676	#define LL_TIM_IC_FILTER_FDIV1 0x00000000U /!< No filter, sampling is done at fDTS /
lypinator	0:bb348c97df44	677	#define LL_TIM_IC_FILTER_FDIV1_N2 (TIM_CCMR1_IC1F_0 << 16U) /!< fSAMPLING=fCK_INT, N=2 /
lypinator	0:bb348c97df44	678	#define LL_TIM_IC_FILTER_FDIV1_N4 (TIM_CCMR1_IC1F_1 << 16U) /!< fSAMPLING=fCK_INT, N=4 /
lypinator	0:bb348c97df44	679	#define LL_TIM_IC_FILTER_FDIV1_N8 ((TIM_CCMR1_IC1F_1 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fCK_INT, N=8 /
lypinator	0:bb348c97df44	680	#define LL_TIM_IC_FILTER_FDIV2_N6 (TIM_CCMR1_IC1F_2 << 16U) /!< fSAMPLING=fDTS/2, N=6 /
lypinator	0:bb348c97df44	681	#define LL_TIM_IC_FILTER_FDIV2_N8 ((TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/2, N=8 /
lypinator	0:bb348c97df44	682	#define LL_TIM_IC_FILTER_FDIV4_N6 ((TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_1) << 16U) /!< fSAMPLING=fDTS/4, N=6 /
lypinator	0:bb348c97df44	683	#define LL_TIM_IC_FILTER_FDIV4_N8 ((TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_1 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/4, N=8 /
lypinator	0:bb348c97df44	684	#define LL_TIM_IC_FILTER_FDIV8_N6 (TIM_CCMR1_IC1F_3 << 16U) /!< fSAMPLING=fDTS/8, N=6 /
lypinator	0:bb348c97df44	685	#define LL_TIM_IC_FILTER_FDIV8_N8 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/8, N=8 /
lypinator	0:bb348c97df44	686	#define LL_TIM_IC_FILTER_FDIV16_N5 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_1) << 16U) /!< fSAMPLING=fDTS/16, N=5 /
lypinator	0:bb348c97df44	687	#define LL_TIM_IC_FILTER_FDIV16_N6 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_1 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/16, N=6 /
lypinator	0:bb348c97df44	688	#define LL_TIM_IC_FILTER_FDIV16_N8 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_2) << 16U) /!< fSAMPLING=fDTS/16, N=8 /
lypinator	0:bb348c97df44	689	#define LL_TIM_IC_FILTER_FDIV32_N5 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/32, N=5 /
lypinator	0:bb348c97df44	690	#define LL_TIM_IC_FILTER_FDIV32_N6 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_1) << 16U) /!< fSAMPLING=fDTS/32, N=6 /
lypinator	0:bb348c97df44	691	#define LL_TIM_IC_FILTER_FDIV32_N8 (TIM_CCMR1_IC1F << 16U) /!< fSAMPLING=fDTS/32, N=8 /
lypinator	0:bb348c97df44	692	/**
lypinator	0:bb348c97df44	693	* @}
lypinator	0:bb348c97df44	694	*/
lypinator	0:bb348c97df44	695
lypinator	0:bb348c97df44	696	/** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity
lypinator	0:bb348c97df44	697	* @{
lypinator	0:bb348c97df44	698	*/
lypinator	0:bb348c97df44	699	#define LL_TIM_IC_POLARITY_RISING 0x00000000U /!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted /
lypinator	0:bb348c97df44	700	#define LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P /!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted /
lypinator	0:bb348c97df44	701	#define LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P \| TIM_CCER_CC1NP) /!< The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted /
lypinator	0:bb348c97df44	702	/**
lypinator	0:bb348c97df44	703	* @}
lypinator	0:bb348c97df44	704	*/
lypinator	0:bb348c97df44	705
lypinator	0:bb348c97df44	706	/** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source
lypinator	0:bb348c97df44	707	* @{
lypinator	0:bb348c97df44	708	*/
lypinator	0:bb348c97df44	709	#define LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U /!< The timer is clocked by the internal clock provided from the RCC /
lypinator	0:bb348c97df44	710	#define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_1 \| TIM_SMCR_SMS_0) /!< Counter counts at each rising or falling edge on a selected inpu t/
lypinator	0:bb348c97df44	711	#define LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE /!< Counter counts at each rising or falling edge on the external trigger input ETR /
lypinator	0:bb348c97df44	712	/**
lypinator	0:bb348c97df44	713	* @}
lypinator	0:bb348c97df44	714	*/
lypinator	0:bb348c97df44	715
lypinator	0:bb348c97df44	716	/** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode
lypinator	0:bb348c97df44	717	* @{
lypinator	0:bb348c97df44	718	*/
lypinator	0:bb348c97df44	719	#define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0 /!< Encoder mode 1 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level /
lypinator	0:bb348c97df44	720	#define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1 /!< Encoder mode 2 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level /
lypinator	0:bb348c97df44	721	#define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 \| TIM_SMCR_SMS_0) /!< Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input l /
lypinator	0:bb348c97df44	722	/**
lypinator	0:bb348c97df44	723	* @}
lypinator	0:bb348c97df44	724	*/
lypinator	0:bb348c97df44	725
lypinator	0:bb348c97df44	726	/** @defgroup TIM_LL_EC_TRGO Trigger Output
lypinator	0:bb348c97df44	727	* @{
lypinator	0:bb348c97df44	728	*/
lypinator	0:bb348c97df44	729	#define LL_TIM_TRGO_RESET 0x00000000U /!< UG bit from the TIMx_EGR register is used as trigger output /
lypinator	0:bb348c97df44	730	#define LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0 /!< Counter Enable signal (CNT_EN) is used as trigger output /
lypinator	0:bb348c97df44	731	#define LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1 /!< Update event is used as trigger output /
lypinator	0:bb348c97df44	732	#define LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 \| TIM_CR2_MMS_0) /!< CC1 capture or a compare match is used as trigger output /
lypinator	0:bb348c97df44	733	#define LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2 /!< OC1REF signal is used as trigger output /
lypinator	0:bb348c97df44	734	#define LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 \| TIM_CR2_MMS_0) /!< OC2REF signal is used as trigger output /
lypinator	0:bb348c97df44	735	#define LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 \| TIM_CR2_MMS_1) /!< OC3REF signal is used as trigger output /
lypinator	0:bb348c97df44	736	#define LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 \| TIM_CR2_MMS_1 \| TIM_CR2_MMS_0) /!< OC4REF signal is used as trigger output /
lypinator	0:bb348c97df44	737	/**
lypinator	0:bb348c97df44	738	* @}
lypinator	0:bb348c97df44	739	*/
lypinator	0:bb348c97df44	740
lypinator	0:bb348c97df44	741
lypinator	0:bb348c97df44	742	/** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode
lypinator	0:bb348c97df44	743	* @{
lypinator	0:bb348c97df44	744	*/
lypinator	0:bb348c97df44	745	#define LL_TIM_SLAVEMODE_DISABLED 0x00000000U /!< Slave mode disabled /
lypinator	0:bb348c97df44	746	#define LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter /
lypinator	0:bb348c97df44	747	#define LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_0) /!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high /
lypinator	0:bb348c97df44	748	#define LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_1) /!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI /
lypinator	0:bb348c97df44	749	/**
lypinator	0:bb348c97df44	750	* @}
lypinator	0:bb348c97df44	751	*/
lypinator	0:bb348c97df44	752
lypinator	0:bb348c97df44	753	/** @defgroup TIM_LL_EC_TS Trigger Selection
lypinator	0:bb348c97df44	754	* @{
lypinator	0:bb348c97df44	755	*/
lypinator	0:bb348c97df44	756	#define LL_TIM_TS_ITR0 0x00000000U /!< Internal Trigger 0 (ITR0) is used as trigger input /
lypinator	0:bb348c97df44	757	#define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /!< Internal Trigger 1 (ITR1) is used as trigger input /
lypinator	0:bb348c97df44	758	#define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /!< Internal Trigger 2 (ITR2) is used as trigger input /
lypinator	0:bb348c97df44	759	#define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_1) /!< Internal Trigger 3 (ITR3) is used as trigger input /
lypinator	0:bb348c97df44	760	#define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /!< TI1 Edge Detector (TI1F_ED) is used as trigger input /
lypinator	0:bb348c97df44	761	#define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 \| TIM_SMCR_TS_0) /!< Filtered Timer Input 1 (TI1FP1) is used as trigger input /
lypinator	0:bb348c97df44	762	#define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 \| TIM_SMCR_TS_1) /!< Filtered Timer Input 2 (TI12P2) is used as trigger input /
lypinator	0:bb348c97df44	763	#define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 \| TIM_SMCR_TS_1 \| TIM_SMCR_TS_0) /!< Filtered external Trigger (ETRF) is used as trigger input /
lypinator	0:bb348c97df44	764	/**
lypinator	0:bb348c97df44	765	* @}
lypinator	0:bb348c97df44	766	*/
lypinator	0:bb348c97df44	767
lypinator	0:bb348c97df44	768	/** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity
lypinator	0:bb348c97df44	769	* @{
lypinator	0:bb348c97df44	770	*/
lypinator	0:bb348c97df44	771	#define LL_TIM_ETR_POLARITY_NONINVERTED 0x00000000U /!< ETR is non-inverted, active at high level or rising edge /
lypinator	0:bb348c97df44	772	#define LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP /!< ETR is inverted, active at low level or falling edge /
lypinator	0:bb348c97df44	773	/**
lypinator	0:bb348c97df44	774	* @}
lypinator	0:bb348c97df44	775	*/
lypinator	0:bb348c97df44	776
lypinator	0:bb348c97df44	777	/** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler
lypinator	0:bb348c97df44	778	* @{
lypinator	0:bb348c97df44	779	*/
lypinator	0:bb348c97df44	780	#define LL_TIM_ETR_PRESCALER_DIV1 0x00000000U /!< ETR prescaler OFF /
lypinator	0:bb348c97df44	781	#define LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0 /!< ETR frequency is divided by 2 /
lypinator	0:bb348c97df44	782	#define LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1 /!< ETR frequency is divided by 4 /
lypinator	0:bb348c97df44	783	#define LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS /!< ETR frequency is divided by 8 /
lypinator	0:bb348c97df44	784	/**
lypinator	0:bb348c97df44	785	* @}
lypinator	0:bb348c97df44	786	*/
lypinator	0:bb348c97df44	787
lypinator	0:bb348c97df44	788	/** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter
lypinator	0:bb348c97df44	789	* @{
lypinator	0:bb348c97df44	790	*/
lypinator	0:bb348c97df44	791	#define LL_TIM_ETR_FILTER_FDIV1 0x00000000U /!< No filter, sampling is done at fDTS /
lypinator	0:bb348c97df44	792	#define LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0 /!< fSAMPLING=fCK_INT, N=2 /
lypinator	0:bb348c97df44	793	#define LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1 /!< fSAMPLING=fCK_INT, N=4 /
lypinator	0:bb348c97df44	794	#define LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fCK_INT, N=8 /
lypinator	0:bb348c97df44	795	#define LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2 /!< fSAMPLING=fDTS/2, N=6 /
lypinator	0:bb348c97df44	796	#define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/2, N=8 /
lypinator	0:bb348c97df44	797	#define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_1) /!< fSAMPLING=fDTS/4, N=6 /
lypinator	0:bb348c97df44	798	#define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_1 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/4, N=8 /
lypinator	0:bb348c97df44	799	#define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /!< fSAMPLING=fDTS/8, N=8 /
lypinator	0:bb348c97df44	800	#define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/16, N=5 /
lypinator	0:bb348c97df44	801	#define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_1) /!< fSAMPLING=fDTS/16, N=6 /
lypinator	0:bb348c97df44	802	#define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_1 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/16, N=8 /
lypinator	0:bb348c97df44	803	#define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_2) /!< fSAMPLING=fDTS/16, N=5 /
lypinator	0:bb348c97df44	804	#define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/32, N=5 /
lypinator	0:bb348c97df44	805	#define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_1) /!< fSAMPLING=fDTS/32, N=6 /
lypinator	0:bb348c97df44	806	#define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF /!< fSAMPLING=fDTS/32, N=8 /
lypinator	0:bb348c97df44	807	/**
lypinator	0:bb348c97df44	808	* @}
lypinator	0:bb348c97df44	809	*/
lypinator	0:bb348c97df44	810
lypinator	0:bb348c97df44	811
lypinator	0:bb348c97df44	812	/** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity
lypinator	0:bb348c97df44	813	* @{
lypinator	0:bb348c97df44	814	*/
lypinator	0:bb348c97df44	815	#define LL_TIM_BREAK_POLARITY_LOW 0x00000000U /!< Break input BRK is active low /
lypinator	0:bb348c97df44	816	#define LL_TIM_BREAK_POLARITY_HIGH TIM_BDTR_BKP /!< Break input BRK is active high /
lypinator	0:bb348c97df44	817	/**
lypinator	0:bb348c97df44	818	* @}
lypinator	0:bb348c97df44	819	*/
lypinator	0:bb348c97df44	820
lypinator	0:bb348c97df44	821
lypinator	0:bb348c97df44	822
lypinator	0:bb348c97df44	823
lypinator	0:bb348c97df44	824	/** @defgroup TIM_LL_EC_OSSI OSSI
lypinator	0:bb348c97df44	825	* @{
lypinator	0:bb348c97df44	826	*/
lypinator	0:bb348c97df44	827	#define LL_TIM_OSSI_DISABLE 0x00000000U /!< When inactive, OCx/OCxN outputs are disabled /
lypinator	0:bb348c97df44	828	#define LL_TIM_OSSI_ENABLE TIM_BDTR_OSSI /!< When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime /
lypinator	0:bb348c97df44	829	/**
lypinator	0:bb348c97df44	830	* @}
lypinator	0:bb348c97df44	831	*/
lypinator	0:bb348c97df44	832
lypinator	0:bb348c97df44	833	/** @defgroup TIM_LL_EC_OSSR OSSR
lypinator	0:bb348c97df44	834	* @{
lypinator	0:bb348c97df44	835	*/
lypinator	0:bb348c97df44	836	#define LL_TIM_OSSR_DISABLE 0x00000000U /!< When inactive, OCx/OCxN outputs are disabled /
lypinator	0:bb348c97df44	837	#define LL_TIM_OSSR_ENABLE TIM_BDTR_OSSR /!< When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 /
lypinator	0:bb348c97df44	838	/**
lypinator	0:bb348c97df44	839	* @}
lypinator	0:bb348c97df44	840	*/
lypinator	0:bb348c97df44	841
lypinator	0:bb348c97df44	842
lypinator	0:bb348c97df44	843	/** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
lypinator	0:bb348c97df44	844	* @{
lypinator	0:bb348c97df44	845	*/
lypinator	0:bb348c97df44	846	#define LL_TIM_DMABURST_BASEADDR_CR1 0x00000000U /!< TIMx_CR1 register is the DMA base address for DMA burst /
lypinator	0:bb348c97df44	847	#define LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0 /!< TIMx_CR2 register is the DMA base address for DMA burst /
lypinator	0:bb348c97df44	848	#define LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1 /!< TIMx_SMCR register is the DMA base address for DMA burst /
lypinator	0:bb348c97df44	849	#define LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_DIER register is the DMA base address for DMA burst /
lypinator	0:bb348c97df44	850	#define LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2 /!< TIMx_SR register is the DMA base address for DMA burst /
lypinator	0:bb348c97df44	851	#define LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 \| TIM_DCR_DBA_0) /!< TIMx_EGR register is the DMA base address for DMA burst /
lypinator	0:bb348c97df44	852	#define LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 \| TIM_DCR_DBA_1) /!< TIMx_CCMR1 register is the DMA base address for DMA burst /
lypinator	0:bb348c97df44	853	#define LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 \| TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_CCMR2 register is the DMA base address for DMA burst /
lypinator	0:bb348c97df44	854	#define LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3 /!< TIMx_CCER register is the DMA base address for DMA burst /
lypinator	0:bb348c97df44	855	#define LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 \| TIM_DCR_DBA_0) /!< TIMx_CNT register is the DMA base address for DMA burst /
lypinator	0:bb348c97df44	856	#define LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 \| TIM_DCR_DBA_1) /!< TIMx_PSC register is the DMA base address for DMA burst /
lypinator	0:bb348c97df44	857	#define LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 \| TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_ARR register is the DMA base address for DMA burst /
lypinator	0:bb348c97df44	858	#define LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 \| TIM_DCR_DBA_2) /!< TIMx_RCR register is the DMA base address for DMA burst /
lypinator	0:bb348c97df44	859	#define LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_0) /!< TIMx_CCR1 register is the DMA base address for DMA burst /
lypinator	0:bb348c97df44	860	#define LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_1) /!< TIMx_CCR2 register is the DMA base address for DMA burst /
lypinator	0:bb348c97df44	861	#define LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_CCR3 register is the DMA base address for DMA burst /
lypinator	0:bb348c97df44	862	#define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 /!< TIMx_CCR4 register is the DMA base address for DMA burst /
lypinator	0:bb348c97df44	863	#define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 \| TIM_DCR_DBA_0) /!< TIMx_BDTR register is the DMA base address for DMA burst /
lypinator	0:bb348c97df44	864	#define LL_TIM_DMABURST_BASEADDR_OR (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_0)
lypinator	0:bb348c97df44	865	/**
lypinator	0:bb348c97df44	866	* @}
lypinator	0:bb348c97df44	867	*/
lypinator	0:bb348c97df44	868
lypinator	0:bb348c97df44	869	/** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length
lypinator	0:bb348c97df44	870	* @{
lypinator	0:bb348c97df44	871	*/
lypinator	0:bb348c97df44	872	#define LL_TIM_DMABURST_LENGTH_1TRANSFER 0x00000000U /!< Transfer is done to 1 register starting from the DMA burst base address /
lypinator	0:bb348c97df44	873	#define LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0 /!< Transfer is done to 2 registers starting from the DMA burst base address /
lypinator	0:bb348c97df44	874	#define LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1 /!< Transfer is done to 3 registers starting from the DMA burst base address /
lypinator	0:bb348c97df44	875	#define LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 \| TIM_DCR_DBL_0) /!< Transfer is done to 4 registers starting from the DMA burst base address /
lypinator	0:bb348c97df44	876	#define LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2 /!< Transfer is done to 5 registers starting from the DMA burst base address /
lypinator	0:bb348c97df44	877	#define LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 \| TIM_DCR_DBL_0) /!< Transfer is done to 6 registers starting from the DMA burst base address /
lypinator	0:bb348c97df44	878	#define LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 \| TIM_DCR_DBL_1) /!< Transfer is done to 7 registers starting from the DMA burst base address /
lypinator	0:bb348c97df44	879	#define LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 \| TIM_DCR_DBL_1 \| TIM_DCR_DBL_0) /!< Transfer is done to 1 registers starting from the DMA burst base address /
lypinator	0:bb348c97df44	880	#define LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3 /!< Transfer is done to 9 registers starting from the DMA burst base address /
lypinator	0:bb348c97df44	881	#define LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_0) /!< Transfer is done to 10 registers starting from the DMA burst base address /
lypinator	0:bb348c97df44	882	#define LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_1) /!< Transfer is done to 11 registers starting from the DMA burst base address /
lypinator	0:bb348c97df44	883	#define LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_1 \| TIM_DCR_DBL_0) /!< Transfer is done to 12 registers starting from the DMA burst base address /
lypinator	0:bb348c97df44	884	#define LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_2) /!< Transfer is done to 13 registers starting from the DMA burst base address /
lypinator	0:bb348c97df44	885	#define LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_2 \| TIM_DCR_DBL_0) /!< Transfer is done to 14 registers starting from the DMA burst base address /
lypinator	0:bb348c97df44	886	#define LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_2 \| TIM_DCR_DBL_1) /!< Transfer is done to 15 registers starting from the DMA burst base address /
lypinator	0:bb348c97df44	887	#define LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_2 \| TIM_DCR_DBL_1 \| TIM_DCR_DBL_0) /!< Transfer is done to 16 registers starting from the DMA burst base address /
lypinator	0:bb348c97df44	888	#define LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4 /!< Transfer is done to 17 registers starting from the DMA burst base address /
lypinator	0:bb348c97df44	889	#define LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 \| TIM_DCR_DBL_0) /!< Transfer is done to 18 registers starting from the DMA burst base address /
lypinator	0:bb348c97df44	890	/**
lypinator	0:bb348c97df44	891	* @}
lypinator	0:bb348c97df44	892	*/
lypinator	0:bb348c97df44	893
lypinator	0:bb348c97df44	894
lypinator	0:bb348c97df44	895	/** @defgroup TIM_LL_EC_TIM2_ITR1_RMP_TIM8 TIM2 Internal Trigger1 Remap TIM8
lypinator	0:bb348c97df44	896	* @{
lypinator	0:bb348c97df44	897	*/
lypinator	0:bb348c97df44	898	#define LL_TIM_TIM2_ITR1_RMP_TIM8_TRGO TIM2_OR_RMP_MASK /!< TIM2_ITR1 is connected to TIM8_TRGO /
lypinator	0:bb348c97df44	899	#define LL_TIM_TIM2_ITR1_RMP_OTG_FS_SOF (TIM_OR_ITR1_RMP_1 \| TIM2_OR_RMP_MASK) /!< TIM2_ITR1 is connected to OTG_FS SOF /
lypinator	0:bb348c97df44	900	#define LL_TIM_TIM2_ITR1_RMP_OTG_HS_SOF (TIM_OR_ITR1_RMP \| TIM2_OR_RMP_MASK) /!< TIM2_ITR1 is connected to OTG_HS SOF /
lypinator	0:bb348c97df44	901	/**
lypinator	0:bb348c97df44	902	* @}
lypinator	0:bb348c97df44	903	*/
lypinator	0:bb348c97df44	904
lypinator	0:bb348c97df44	905	/** @defgroup TIM_LL_EC_TIM5_TI4_RMP TIM5 External Input Ch4 Remap
lypinator	0:bb348c97df44	906	* @{
lypinator	0:bb348c97df44	907	*/
lypinator	0:bb348c97df44	908	#define LL_TIM_TIM5_TI4_RMP_GPIO TIM5_OR_RMP_MASK /!< TIM5 channel 4 is connected to GPIO /
lypinator	0:bb348c97df44	909	#define LL_TIM_TIM5_TI4_RMP_LSI (TIM_OR_TI4_RMP_0 \| TIM5_OR_RMP_MASK) /!< TIM5 channel 4 is connected to LSI internal clock /
lypinator	0:bb348c97df44	910	#define LL_TIM_TIM5_TI4_RMP_LSE (TIM_OR_TI4_RMP_1 \| TIM5_OR_RMP_MASK) /!< TIM5 channel 4 is connected to LSE /
lypinator	0:bb348c97df44	911	#define LL_TIM_TIM5_TI4_RMP_RTC (TIM_OR_TI4_RMP \| TIM5_OR_RMP_MASK) /!< TIM5 channel 4 is connected to RTC wakeup interrupt /
lypinator	0:bb348c97df44	912	/**
lypinator	0:bb348c97df44	913	* @}
lypinator	0:bb348c97df44	914	*/
lypinator	0:bb348c97df44	915
lypinator	0:bb348c97df44	916	/** @defgroup TIM_LL_EC_TIM11_TI1_RMP TIM11 External Input Capture 1 Remap
lypinator	0:bb348c97df44	917	* @{
lypinator	0:bb348c97df44	918	*/
lypinator	0:bb348c97df44	919	#define LL_TIM_TIM11_TI1_RMP_GPIO TIM11_OR_RMP_MASK /!< TIM11 channel 1 is connected to GPIO /
lypinator	0:bb348c97df44	920	#define LL_TIM_TIM11_TI1_RMP_GPIO1 (TIM_OR_TI1_RMP_0 \| TIM11_OR_RMP_MASK) /!< TIM11 channel 1 is connected to GPIO /
lypinator	0:bb348c97df44	921	#define LL_TIM_TIM11_TI1_RMP_GPIO2 (TIM_OR_TI1_RMP \| TIM11_OR_RMP_MASK) /!< TIM11 channel 1 is connected to GPIO /
lypinator	0:bb348c97df44	922	#define LL_TIM_TIM11_TI1_RMP_HSE_RTC (TIM_OR_TI1_RMP_1 \| TIM11_OR_RMP_MASK) /!< TIM11 channel 1 is connected to HSE_RTC /
lypinator	0:bb348c97df44	923	/**
lypinator	0:bb348c97df44	924	* @}
lypinator	0:bb348c97df44	925	*/
lypinator	0:bb348c97df44	926
lypinator	0:bb348c97df44	927
lypinator	0:bb348c97df44	928	/**
lypinator	0:bb348c97df44	929	* @}
lypinator	0:bb348c97df44	930	*/
lypinator	0:bb348c97df44	931
lypinator	0:bb348c97df44	932	/* Exported macro ------------------------------------------------------------*/
lypinator	0:bb348c97df44	933	/** @defgroup TIM_LL_Exported_Macros TIM Exported Macros
lypinator	0:bb348c97df44	934	* @{
lypinator	0:bb348c97df44	935	*/
lypinator	0:bb348c97df44	936
lypinator	0:bb348c97df44	937	/** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros
lypinator	0:bb348c97df44	938	* @{
lypinator	0:bb348c97df44	939	*/
lypinator	0:bb348c97df44	940	/**
lypinator	0:bb348c97df44	941	* @brief Write a value in TIM register.
lypinator	0:bb348c97df44	942	* @param __INSTANCE__ TIM Instance
lypinator	0:bb348c97df44	943	* @param __REG__ Register to be written
lypinator	0:bb348c97df44	944	* @param __VALUE__ Value to be written in the register
lypinator	0:bb348c97df44	945	* @retval None
lypinator	0:bb348c97df44	946	*/
lypinator	0:bb348c97df44	947	#define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
lypinator	0:bb348c97df44	948
lypinator	0:bb348c97df44	949	/**
lypinator	0:bb348c97df44	950	* @brief Read a value in TIM register.
lypinator	0:bb348c97df44	951	* @param __INSTANCE__ TIM Instance
lypinator	0:bb348c97df44	952	* @param __REG__ Register to be read
lypinator	0:bb348c97df44	953	* @retval Register value
lypinator	0:bb348c97df44	954	*/
lypinator	0:bb348c97df44	955	#define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
lypinator	0:bb348c97df44	956	/**
lypinator	0:bb348c97df44	957	* @}
lypinator	0:bb348c97df44	958	*/
lypinator	0:bb348c97df44	959
lypinator	0:bb348c97df44	960	/** @defgroup TIM_LL_EM_Exported_Macros Exported_Macros
lypinator	0:bb348c97df44	961	* @{
lypinator	0:bb348c97df44	962	*/
lypinator	0:bb348c97df44	963
lypinator	0:bb348c97df44	964	/**
lypinator	0:bb348c97df44	965	* @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
lypinator	0:bb348c97df44	966	* @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120);
lypinator	0:bb348c97df44	967	* @param __TIMCLK__ timer input clock frequency (in Hz)
lypinator	0:bb348c97df44	968	* @param __CKD__ This parameter can be one of the following values:
lypinator	0:bb348c97df44	969	* @arg @ref LL_TIM_CLOCKDIVISION_DIV1
lypinator	0:bb348c97df44	970	* @arg @ref LL_TIM_CLOCKDIVISION_DIV2
lypinator	0:bb348c97df44	971	* @arg @ref LL_TIM_CLOCKDIVISION_DIV4
lypinator	0:bb348c97df44	972	* @param __DT__ deadtime duration (in ns)
lypinator	0:bb348c97df44	973	* @retval DTG[0:7]
lypinator	0:bb348c97df44	974	*/
lypinator	0:bb348c97df44	975	#define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \
lypinator	0:bb348c97df44	976	( (((uint64_t)((__DT__)1000U)) < ((DT_DELAY_1+1U) TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \
lypinator	0:bb348c97df44	977	(((uint64_t)((__DT__)1000U)) < (64U + (DT_DELAY_2+1U)) 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_2 \| ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 1U) - (uint8_t) 64U) & DT_DELAY_2)) :\
lypinator	0:bb348c97df44	978	(((uint64_t)((__DT__)1000U)) < (32U + (DT_DELAY_3+1U)) 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_3 \| ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 3U) - (uint8_t) 32U) & DT_DELAY_3)) :\
lypinator	0:bb348c97df44	979	(((uint64_t)((__DT__)1000U)) < (32U + (DT_DELAY_4+1U)) 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_4 \| ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 4U) - (uint8_t) 32U) & DT_DELAY_4)) :\
lypinator	0:bb348c97df44	980	0U)
lypinator	0:bb348c97df44	981
lypinator	0:bb348c97df44	982	/**
lypinator	0:bb348c97df44	983	* @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
lypinator	0:bb348c97df44	984	* @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
lypinator	0:bb348c97df44	985	* @param __TIMCLK__ timer input clock frequency (in Hz)
lypinator	0:bb348c97df44	986	* @param __CNTCLK__ counter clock frequency (in Hz)
lypinator	0:bb348c97df44	987	* @retval Prescaler value (between Min_Data=0 and Max_Data=65535)
lypinator	0:bb348c97df44	988	*/
lypinator	0:bb348c97df44	989	#define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \
lypinator	0:bb348c97df44	990	((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((__TIMCLK__)/(__CNTCLK__) - 1U) : 0U
lypinator	0:bb348c97df44	991
lypinator	0:bb348c97df44	992	/**
lypinator	0:bb348c97df44	993	* @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
lypinator	0:bb348c97df44	994	* @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);
lypinator	0:bb348c97df44	995	* @param __TIMCLK__ timer input clock frequency (in Hz)
lypinator	0:bb348c97df44	996	* @param __PSC__ prescaler
lypinator	0:bb348c97df44	997	* @param __FREQ__ output signal frequency (in Hz)
lypinator	0:bb348c97df44	998	* @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
lypinator	0:bb348c97df44	999	*/
lypinator	0:bb348c97df44	1000	#define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
lypinator	0:bb348c97df44	1001	(((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? ((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U)) - 1U) : 0U
lypinator	0:bb348c97df44	1002
lypinator	0:bb348c97df44	1003	/**
lypinator	0:bb348c97df44	1004	* @brief HELPER macro calculating the compare value required to achieve the required timer output compare active/inactive delay.
lypinator	0:bb348c97df44	1005	* @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
lypinator	0:bb348c97df44	1006	* @param __TIMCLK__ timer input clock frequency (in Hz)
lypinator	0:bb348c97df44	1007	* @param __PSC__ prescaler
lypinator	0:bb348c97df44	1008	* @param __DELAY__ timer output compare active/inactive delay (in us)
lypinator	0:bb348c97df44	1009	* @retval Compare value (between Min_Data=0 and Max_Data=65535)
lypinator	0:bb348c97df44	1010	*/
lypinator	0:bb348c97df44	1011	#define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \
lypinator	0:bb348c97df44	1012	((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
lypinator	0:bb348c97df44	1013	/ ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
lypinator	0:bb348c97df44	1014
lypinator	0:bb348c97df44	1015	/**
lypinator	0:bb348c97df44	1016	* @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration (when the timer operates in one pulse mode).
lypinator	0:bb348c97df44	1017	* @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
lypinator	0:bb348c97df44	1018	* @param __TIMCLK__ timer input clock frequency (in Hz)
lypinator	0:bb348c97df44	1019	* @param __PSC__ prescaler
lypinator	0:bb348c97df44	1020	* @param __DELAY__ timer output compare active/inactive delay (in us)
lypinator	0:bb348c97df44	1021	* @param __PULSE__ pulse duration (in us)
lypinator	0:bb348c97df44	1022	* @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
lypinator	0:bb348c97df44	1023	*/
lypinator	0:bb348c97df44	1024	#define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \
lypinator	0:bb348c97df44	1025	((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
lypinator	0:bb348c97df44	1026	+ __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
lypinator	0:bb348c97df44	1027
lypinator	0:bb348c97df44	1028	/**
lypinator	0:bb348c97df44	1029	* @brief HELPER macro retrieving the ratio of the input capture prescaler
lypinator	0:bb348c97df44	1030	* @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
lypinator	0:bb348c97df44	1031	* @param __ICPSC__ This parameter can be one of the following values:
lypinator	0:bb348c97df44	1032	* @arg @ref LL_TIM_ICPSC_DIV1
lypinator	0:bb348c97df44	1033	* @arg @ref LL_TIM_ICPSC_DIV2
lypinator	0:bb348c97df44	1034	* @arg @ref LL_TIM_ICPSC_DIV4
lypinator	0:bb348c97df44	1035	* @arg @ref LL_TIM_ICPSC_DIV8
lypinator	0:bb348c97df44	1036	* @retval Input capture prescaler ratio (1, 2, 4 or 8)
lypinator	0:bb348c97df44	1037	*/
lypinator	0:bb348c97df44	1038	#define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \
lypinator	0:bb348c97df44	1039	((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
lypinator	0:bb348c97df44	1040
lypinator	0:bb348c97df44	1041
lypinator	0:bb348c97df44	1042	/**
lypinator	0:bb348c97df44	1043	* @}
lypinator	0:bb348c97df44	1044	*/
lypinator	0:bb348c97df44	1045
lypinator	0:bb348c97df44	1046
lypinator	0:bb348c97df44	1047	/**
lypinator	0:bb348c97df44	1048	* @}
lypinator	0:bb348c97df44	1049	*/
lypinator	0:bb348c97df44	1050
lypinator	0:bb348c97df44	1051	/* Exported functions --------------------------------------------------------*/
lypinator	0:bb348c97df44	1052	/** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
lypinator	0:bb348c97df44	1053	* @{
lypinator	0:bb348c97df44	1054	*/
lypinator	0:bb348c97df44	1055
lypinator	0:bb348c97df44	1056	/** @defgroup TIM_LL_EF_Time_Base Time Base configuration
lypinator	0:bb348c97df44	1057	* @{
lypinator	0:bb348c97df44	1058	*/
lypinator	0:bb348c97df44	1059	/**
lypinator	0:bb348c97df44	1060	* @brief Enable timer counter.
lypinator	0:bb348c97df44	1061	* @rmtoll CR1 CEN LL_TIM_EnableCounter
lypinator	0:bb348c97df44	1062	* @param TIMx Timer instance
lypinator	0:bb348c97df44	1063	* @retval None
lypinator	0:bb348c97df44	1064	*/
lypinator	0:bb348c97df44	1065	__STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	1066	{
lypinator	0:bb348c97df44	1067	SET_BIT(TIMx->CR1, TIM_CR1_CEN);
lypinator	0:bb348c97df44	1068	}
lypinator	0:bb348c97df44	1069
lypinator	0:bb348c97df44	1070	/**
lypinator	0:bb348c97df44	1071	* @brief Disable timer counter.
lypinator	0:bb348c97df44	1072	* @rmtoll CR1 CEN LL_TIM_DisableCounter
lypinator	0:bb348c97df44	1073	* @param TIMx Timer instance
lypinator	0:bb348c97df44	1074	* @retval None
lypinator	0:bb348c97df44	1075	*/
lypinator	0:bb348c97df44	1076	__STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	1077	{
lypinator	0:bb348c97df44	1078	CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
lypinator	0:bb348c97df44	1079	}
lypinator	0:bb348c97df44	1080
lypinator	0:bb348c97df44	1081	/**
lypinator	0:bb348c97df44	1082	* @brief Indicates whether the timer counter is enabled.
lypinator	0:bb348c97df44	1083	* @rmtoll CR1 CEN LL_TIM_IsEnabledCounter
lypinator	0:bb348c97df44	1084	* @param TIMx Timer instance
lypinator	0:bb348c97df44	1085	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	1086	*/
lypinator	0:bb348c97df44	1087	__STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	1088	{
lypinator	0:bb348c97df44	1089	return (READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN));
lypinator	0:bb348c97df44	1090	}
lypinator	0:bb348c97df44	1091
lypinator	0:bb348c97df44	1092	/**
lypinator	0:bb348c97df44	1093	* @brief Enable update event generation.
lypinator	0:bb348c97df44	1094	* @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent
lypinator	0:bb348c97df44	1095	* @param TIMx Timer instance
lypinator	0:bb348c97df44	1096	* @retval None
lypinator	0:bb348c97df44	1097	*/
lypinator	0:bb348c97df44	1098	__STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	1099	{
lypinator	0:bb348c97df44	1100	CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
lypinator	0:bb348c97df44	1101	}
lypinator	0:bb348c97df44	1102
lypinator	0:bb348c97df44	1103	/**
lypinator	0:bb348c97df44	1104	* @brief Disable update event generation.
lypinator	0:bb348c97df44	1105	* @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent
lypinator	0:bb348c97df44	1106	* @param TIMx Timer instance
lypinator	0:bb348c97df44	1107	* @retval None
lypinator	0:bb348c97df44	1108	*/
lypinator	0:bb348c97df44	1109	__STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	1110	{
lypinator	0:bb348c97df44	1111	SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
lypinator	0:bb348c97df44	1112	}
lypinator	0:bb348c97df44	1113
lypinator	0:bb348c97df44	1114	/**
lypinator	0:bb348c97df44	1115	* @brief Indicates whether update event generation is enabled.
lypinator	0:bb348c97df44	1116	* @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent
lypinator	0:bb348c97df44	1117	* @param TIMx Timer instance
lypinator	0:bb348c97df44	1118	* @retval Inverted state of bit (0 or 1).
lypinator	0:bb348c97df44	1119	*/
lypinator	0:bb348c97df44	1120	__STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	1121	{
lypinator	0:bb348c97df44	1122	return (READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == RESET);
lypinator	0:bb348c97df44	1123	}
lypinator	0:bb348c97df44	1124
lypinator	0:bb348c97df44	1125	/**
lypinator	0:bb348c97df44	1126	* @brief Set update event source
lypinator	0:bb348c97df44	1127	* @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
lypinator	0:bb348c97df44	1128	* generate an update interrupt or DMA request if enabled:
lypinator	0:bb348c97df44	1129	* - Counter overflow/underflow
lypinator	0:bb348c97df44	1130	* - Setting the UG bit
lypinator	0:bb348c97df44	1131	* - Update generation through the slave mode controller
lypinator	0:bb348c97df44	1132	* @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
lypinator	0:bb348c97df44	1133	* overflow/underflow generates an update interrupt or DMA request if enabled.
lypinator	0:bb348c97df44	1134	* @rmtoll CR1 URS LL_TIM_SetUpdateSource
lypinator	0:bb348c97df44	1135	* @param TIMx Timer instance
lypinator	0:bb348c97df44	1136	* @param UpdateSource This parameter can be one of the following values:
lypinator	0:bb348c97df44	1137	* @arg @ref LL_TIM_UPDATESOURCE_REGULAR
lypinator	0:bb348c97df44	1138	* @arg @ref LL_TIM_UPDATESOURCE_COUNTER
lypinator	0:bb348c97df44	1139	* @retval None
lypinator	0:bb348c97df44	1140	*/
lypinator	0:bb348c97df44	1141	__STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource)
lypinator	0:bb348c97df44	1142	{
lypinator	0:bb348c97df44	1143	MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
lypinator	0:bb348c97df44	1144	}
lypinator	0:bb348c97df44	1145
lypinator	0:bb348c97df44	1146	/**
lypinator	0:bb348c97df44	1147	* @brief Get actual event update source
lypinator	0:bb348c97df44	1148	* @rmtoll CR1 URS LL_TIM_GetUpdateSource
lypinator	0:bb348c97df44	1149	* @param TIMx Timer instance
lypinator	0:bb348c97df44	1150	* @retval Returned value can be one of the following values:
lypinator	0:bb348c97df44	1151	* @arg @ref LL_TIM_UPDATESOURCE_REGULAR
lypinator	0:bb348c97df44	1152	* @arg @ref LL_TIM_UPDATESOURCE_COUNTER
lypinator	0:bb348c97df44	1153	*/
lypinator	0:bb348c97df44	1154	__STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	1155	{
lypinator	0:bb348c97df44	1156	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
lypinator	0:bb348c97df44	1157	}
lypinator	0:bb348c97df44	1158
lypinator	0:bb348c97df44	1159	/**
lypinator	0:bb348c97df44	1160	* @brief Set one pulse mode (one shot v.s. repetitive).
lypinator	0:bb348c97df44	1161	* @rmtoll CR1 OPM LL_TIM_SetOnePulseMode
lypinator	0:bb348c97df44	1162	* @param TIMx Timer instance
lypinator	0:bb348c97df44	1163	* @param OnePulseMode This parameter can be one of the following values:
lypinator	0:bb348c97df44	1164	* @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
lypinator	0:bb348c97df44	1165	* @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
lypinator	0:bb348c97df44	1166	* @retval None
lypinator	0:bb348c97df44	1167	*/
lypinator	0:bb348c97df44	1168	__STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode)
lypinator	0:bb348c97df44	1169	{
lypinator	0:bb348c97df44	1170	MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
lypinator	0:bb348c97df44	1171	}
lypinator	0:bb348c97df44	1172
lypinator	0:bb348c97df44	1173	/**
lypinator	0:bb348c97df44	1174	* @brief Get actual one pulse mode.
lypinator	0:bb348c97df44	1175	* @rmtoll CR1 OPM LL_TIM_GetOnePulseMode
lypinator	0:bb348c97df44	1176	* @param TIMx Timer instance
lypinator	0:bb348c97df44	1177	* @retval Returned value can be one of the following values:
lypinator	0:bb348c97df44	1178	* @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
lypinator	0:bb348c97df44	1179	* @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
lypinator	0:bb348c97df44	1180	*/
lypinator	0:bb348c97df44	1181	__STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	1182	{
lypinator	0:bb348c97df44	1183	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
lypinator	0:bb348c97df44	1184	}
lypinator	0:bb348c97df44	1185
lypinator	0:bb348c97df44	1186	/**
lypinator	0:bb348c97df44	1187	* @brief Set the timer counter counting mode.
lypinator	0:bb348c97df44	1188	* @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
lypinator	0:bb348c97df44	1189	* check whether or not the counter mode selection feature is supported
lypinator	0:bb348c97df44	1190	* by a timer instance.
lypinator	0:bb348c97df44	1191	* @rmtoll CR1 DIR LL_TIM_SetCounterMode\n
lypinator	0:bb348c97df44	1192	* CR1 CMS LL_TIM_SetCounterMode
lypinator	0:bb348c97df44	1193	* @param TIMx Timer instance
lypinator	0:bb348c97df44	1194	* @param CounterMode This parameter can be one of the following values:
lypinator	0:bb348c97df44	1195	* @arg @ref LL_TIM_COUNTERMODE_UP
lypinator	0:bb348c97df44	1196	* @arg @ref LL_TIM_COUNTERMODE_DOWN
lypinator	0:bb348c97df44	1197	* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
lypinator	0:bb348c97df44	1198	* @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
lypinator	0:bb348c97df44	1199	* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
lypinator	0:bb348c97df44	1200	* @retval None
lypinator	0:bb348c97df44	1201	*/
lypinator	0:bb348c97df44	1202	__STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
lypinator	0:bb348c97df44	1203	{
lypinator	0:bb348c97df44	1204	MODIFY_REG(TIMx->CR1, TIM_CR1_DIR \| TIM_CR1_CMS, CounterMode);
lypinator	0:bb348c97df44	1205	}
lypinator	0:bb348c97df44	1206
lypinator	0:bb348c97df44	1207	/**
lypinator	0:bb348c97df44	1208	* @brief Get actual counter mode.
lypinator	0:bb348c97df44	1209	* @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
lypinator	0:bb348c97df44	1210	* check whether or not the counter mode selection feature is supported
lypinator	0:bb348c97df44	1211	* by a timer instance.
lypinator	0:bb348c97df44	1212	* @rmtoll CR1 DIR LL_TIM_GetCounterMode\n
lypinator	0:bb348c97df44	1213	* CR1 CMS LL_TIM_GetCounterMode
lypinator	0:bb348c97df44	1214	* @param TIMx Timer instance
lypinator	0:bb348c97df44	1215	* @retval Returned value can be one of the following values:
lypinator	0:bb348c97df44	1216	* @arg @ref LL_TIM_COUNTERMODE_UP
lypinator	0:bb348c97df44	1217	* @arg @ref LL_TIM_COUNTERMODE_DOWN
lypinator	0:bb348c97df44	1218	* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
lypinator	0:bb348c97df44	1219	* @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
lypinator	0:bb348c97df44	1220	* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
lypinator	0:bb348c97df44	1221	*/
lypinator	0:bb348c97df44	1222	__STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	1223	{
lypinator	0:bb348c97df44	1224	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR \| TIM_CR1_CMS));
lypinator	0:bb348c97df44	1225	}
lypinator	0:bb348c97df44	1226
lypinator	0:bb348c97df44	1227	/**
lypinator	0:bb348c97df44	1228	* @brief Enable auto-reload (ARR) preload.
lypinator	0:bb348c97df44	1229	* @rmtoll CR1 ARPE LL_TIM_EnableARRPreload
lypinator	0:bb348c97df44	1230	* @param TIMx Timer instance
lypinator	0:bb348c97df44	1231	* @retval None
lypinator	0:bb348c97df44	1232	*/
lypinator	0:bb348c97df44	1233	__STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	1234	{
lypinator	0:bb348c97df44	1235	SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
lypinator	0:bb348c97df44	1236	}
lypinator	0:bb348c97df44	1237
lypinator	0:bb348c97df44	1238	/**
lypinator	0:bb348c97df44	1239	* @brief Disable auto-reload (ARR) preload.
lypinator	0:bb348c97df44	1240	* @rmtoll CR1 ARPE LL_TIM_DisableARRPreload
lypinator	0:bb348c97df44	1241	* @param TIMx Timer instance
lypinator	0:bb348c97df44	1242	* @retval None
lypinator	0:bb348c97df44	1243	*/
lypinator	0:bb348c97df44	1244	__STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	1245	{
lypinator	0:bb348c97df44	1246	CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
lypinator	0:bb348c97df44	1247	}
lypinator	0:bb348c97df44	1248
lypinator	0:bb348c97df44	1249	/**
lypinator	0:bb348c97df44	1250	* @brief Indicates whether auto-reload (ARR) preload is enabled.
lypinator	0:bb348c97df44	1251	* @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload
lypinator	0:bb348c97df44	1252	* @param TIMx Timer instance
lypinator	0:bb348c97df44	1253	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	1254	*/
lypinator	0:bb348c97df44	1255	__STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	1256	{
lypinator	0:bb348c97df44	1257	return (READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE));
lypinator	0:bb348c97df44	1258	}
lypinator	0:bb348c97df44	1259
lypinator	0:bb348c97df44	1260	/**
lypinator	0:bb348c97df44	1261	* @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
lypinator	0:bb348c97df44	1262	* @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
lypinator	0:bb348c97df44	1263	* whether or not the clock division feature is supported by the timer
lypinator	0:bb348c97df44	1264	* instance.
lypinator	0:bb348c97df44	1265	* @rmtoll CR1 CKD LL_TIM_SetClockDivision
lypinator	0:bb348c97df44	1266	* @param TIMx Timer instance
lypinator	0:bb348c97df44	1267	* @param ClockDivision This parameter can be one of the following values:
lypinator	0:bb348c97df44	1268	* @arg @ref LL_TIM_CLOCKDIVISION_DIV1
lypinator	0:bb348c97df44	1269	* @arg @ref LL_TIM_CLOCKDIVISION_DIV2
lypinator	0:bb348c97df44	1270	* @arg @ref LL_TIM_CLOCKDIVISION_DIV4
lypinator	0:bb348c97df44	1271	* @retval None
lypinator	0:bb348c97df44	1272	*/
lypinator	0:bb348c97df44	1273	__STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision)
lypinator	0:bb348c97df44	1274	{
lypinator	0:bb348c97df44	1275	MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
lypinator	0:bb348c97df44	1276	}
lypinator	0:bb348c97df44	1277
lypinator	0:bb348c97df44	1278	/**
lypinator	0:bb348c97df44	1279	* @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
lypinator	0:bb348c97df44	1280	* @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
lypinator	0:bb348c97df44	1281	* whether or not the clock division feature is supported by the timer
lypinator	0:bb348c97df44	1282	* instance.
lypinator	0:bb348c97df44	1283	* @rmtoll CR1 CKD LL_TIM_GetClockDivision
lypinator	0:bb348c97df44	1284	* @param TIMx Timer instance
lypinator	0:bb348c97df44	1285	* @retval Returned value can be one of the following values:
lypinator	0:bb348c97df44	1286	* @arg @ref LL_TIM_CLOCKDIVISION_DIV1
lypinator	0:bb348c97df44	1287	* @arg @ref LL_TIM_CLOCKDIVISION_DIV2
lypinator	0:bb348c97df44	1288	* @arg @ref LL_TIM_CLOCKDIVISION_DIV4
lypinator	0:bb348c97df44	1289	*/
lypinator	0:bb348c97df44	1290	__STATIC_INLINE uint32_t LL_TIM_GetClockDivision(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	1291	{
lypinator	0:bb348c97df44	1292	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
lypinator	0:bb348c97df44	1293	}
lypinator	0:bb348c97df44	1294
lypinator	0:bb348c97df44	1295	/**
lypinator	0:bb348c97df44	1296	* @brief Set the counter value.
lypinator	0:bb348c97df44	1297	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
lypinator	0:bb348c97df44	1298	* whether or not a timer instance supports a 32 bits counter.
lypinator	0:bb348c97df44	1299	* @rmtoll CNT CNT LL_TIM_SetCounter
lypinator	0:bb348c97df44	1300	* @param TIMx Timer instance
lypinator	0:bb348c97df44	1301	* @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
lypinator	0:bb348c97df44	1302	* @retval None
lypinator	0:bb348c97df44	1303	*/
lypinator	0:bb348c97df44	1304	__STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
lypinator	0:bb348c97df44	1305	{
lypinator	0:bb348c97df44	1306	WRITE_REG(TIMx->CNT, Counter);
lypinator	0:bb348c97df44	1307	}
lypinator	0:bb348c97df44	1308
lypinator	0:bb348c97df44	1309	/**
lypinator	0:bb348c97df44	1310	* @brief Get the counter value.
lypinator	0:bb348c97df44	1311	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
lypinator	0:bb348c97df44	1312	* whether or not a timer instance supports a 32 bits counter.
lypinator	0:bb348c97df44	1313	* @rmtoll CNT CNT LL_TIM_GetCounter
lypinator	0:bb348c97df44	1314	* @param TIMx Timer instance
lypinator	0:bb348c97df44	1315	* @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
lypinator	0:bb348c97df44	1316	*/
lypinator	0:bb348c97df44	1317	__STATIC_INLINE uint32_t LL_TIM_GetCounter(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	1318	{
lypinator	0:bb348c97df44	1319	return (uint32_t)(READ_REG(TIMx->CNT));
lypinator	0:bb348c97df44	1320	}
lypinator	0:bb348c97df44	1321
lypinator	0:bb348c97df44	1322	/**
lypinator	0:bb348c97df44	1323	* @brief Get the current direction of the counter
lypinator	0:bb348c97df44	1324	* @rmtoll CR1 DIR LL_TIM_GetDirection
lypinator	0:bb348c97df44	1325	* @param TIMx Timer instance
lypinator	0:bb348c97df44	1326	* @retval Returned value can be one of the following values:
lypinator	0:bb348c97df44	1327	* @arg @ref LL_TIM_COUNTERDIRECTION_UP
lypinator	0:bb348c97df44	1328	* @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
lypinator	0:bb348c97df44	1329	*/
lypinator	0:bb348c97df44	1330	__STATIC_INLINE uint32_t LL_TIM_GetDirection(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	1331	{
lypinator	0:bb348c97df44	1332	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
lypinator	0:bb348c97df44	1333	}
lypinator	0:bb348c97df44	1334
lypinator	0:bb348c97df44	1335	/**
lypinator	0:bb348c97df44	1336	* @brief Set the prescaler value.
lypinator	0:bb348c97df44	1337	* @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
lypinator	0:bb348c97df44	1338	* @note The prescaler can be changed on the fly as this control register is buffered. The new
lypinator	0:bb348c97df44	1339	* prescaler ratio is taken into account at the next update event.
lypinator	0:bb348c97df44	1340	* @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
lypinator	0:bb348c97df44	1341	* @rmtoll PSC PSC LL_TIM_SetPrescaler
lypinator	0:bb348c97df44	1342	* @param TIMx Timer instance
lypinator	0:bb348c97df44	1343	* @param Prescaler between Min_Data=0 and Max_Data=65535
lypinator	0:bb348c97df44	1344	* @retval None
lypinator	0:bb348c97df44	1345	*/
lypinator	0:bb348c97df44	1346	__STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
lypinator	0:bb348c97df44	1347	{
lypinator	0:bb348c97df44	1348	WRITE_REG(TIMx->PSC, Prescaler);
lypinator	0:bb348c97df44	1349	}
lypinator	0:bb348c97df44	1350
lypinator	0:bb348c97df44	1351	/**
lypinator	0:bb348c97df44	1352	* @brief Get the prescaler value.
lypinator	0:bb348c97df44	1353	* @rmtoll PSC PSC LL_TIM_GetPrescaler
lypinator	0:bb348c97df44	1354	* @param TIMx Timer instance
lypinator	0:bb348c97df44	1355	* @retval Prescaler value between Min_Data=0 and Max_Data=65535
lypinator	0:bb348c97df44	1356	*/
lypinator	0:bb348c97df44	1357	__STATIC_INLINE uint32_t LL_TIM_GetPrescaler(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	1358	{
lypinator	0:bb348c97df44	1359	return (uint32_t)(READ_REG(TIMx->PSC));
lypinator	0:bb348c97df44	1360	}
lypinator	0:bb348c97df44	1361
lypinator	0:bb348c97df44	1362	/**
lypinator	0:bb348c97df44	1363	* @brief Set the auto-reload value.
lypinator	0:bb348c97df44	1364	* @note The counter is blocked while the auto-reload value is null.
lypinator	0:bb348c97df44	1365	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
lypinator	0:bb348c97df44	1366	* whether or not a timer instance supports a 32 bits counter.
lypinator	0:bb348c97df44	1367	* @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
lypinator	0:bb348c97df44	1368	* @rmtoll ARR ARR LL_TIM_SetAutoReload
lypinator	0:bb348c97df44	1369	* @param TIMx Timer instance
lypinator	0:bb348c97df44	1370	* @param AutoReload between Min_Data=0 and Max_Data=65535
lypinator	0:bb348c97df44	1371	* @retval None
lypinator	0:bb348c97df44	1372	*/
lypinator	0:bb348c97df44	1373	__STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload)
lypinator	0:bb348c97df44	1374	{
lypinator	0:bb348c97df44	1375	WRITE_REG(TIMx->ARR, AutoReload);
lypinator	0:bb348c97df44	1376	}
lypinator	0:bb348c97df44	1377
lypinator	0:bb348c97df44	1378	/**
lypinator	0:bb348c97df44	1379	* @brief Get the auto-reload value.
lypinator	0:bb348c97df44	1380	* @rmtoll ARR ARR LL_TIM_GetAutoReload
lypinator	0:bb348c97df44	1381	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
lypinator	0:bb348c97df44	1382	* whether or not a timer instance supports a 32 bits counter.
lypinator	0:bb348c97df44	1383	* @param TIMx Timer instance
lypinator	0:bb348c97df44	1384	* @retval Auto-reload value
lypinator	0:bb348c97df44	1385	*/
lypinator	0:bb348c97df44	1386	__STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	1387	{
lypinator	0:bb348c97df44	1388	return (uint32_t)(READ_REG(TIMx->ARR));
lypinator	0:bb348c97df44	1389	}
lypinator	0:bb348c97df44	1390
lypinator	0:bb348c97df44	1391	/**
lypinator	0:bb348c97df44	1392	* @brief Set the repetition counter value.
lypinator	0:bb348c97df44	1393	* @note Macro @ref IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
lypinator	0:bb348c97df44	1394	* whether or not a timer instance supports a repetition counter.
lypinator	0:bb348c97df44	1395	* @rmtoll RCR REP LL_TIM_SetRepetitionCounter
lypinator	0:bb348c97df44	1396	* @param TIMx Timer instance
lypinator	0:bb348c97df44	1397	* @param RepetitionCounter between Min_Data=0 and Max_Data=255
lypinator	0:bb348c97df44	1398	* @retval None
lypinator	0:bb348c97df44	1399	*/
lypinator	0:bb348c97df44	1400	__STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
lypinator	0:bb348c97df44	1401	{
lypinator	0:bb348c97df44	1402	WRITE_REG(TIMx->RCR, RepetitionCounter);
lypinator	0:bb348c97df44	1403	}
lypinator	0:bb348c97df44	1404
lypinator	0:bb348c97df44	1405	/**
lypinator	0:bb348c97df44	1406	* @brief Get the repetition counter value.
lypinator	0:bb348c97df44	1407	* @note Macro @ref IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
lypinator	0:bb348c97df44	1408	* whether or not a timer instance supports a repetition counter.
lypinator	0:bb348c97df44	1409	* @rmtoll RCR REP LL_TIM_GetRepetitionCounter
lypinator	0:bb348c97df44	1410	* @param TIMx Timer instance
lypinator	0:bb348c97df44	1411	* @retval Repetition counter value
lypinator	0:bb348c97df44	1412	*/
lypinator	0:bb348c97df44	1413	__STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	1414	{
lypinator	0:bb348c97df44	1415	return (uint32_t)(READ_REG(TIMx->RCR));
lypinator	0:bb348c97df44	1416	}
lypinator	0:bb348c97df44	1417
lypinator	0:bb348c97df44	1418	/**
lypinator	0:bb348c97df44	1419	* @}
lypinator	0:bb348c97df44	1420	*/
lypinator	0:bb348c97df44	1421
lypinator	0:bb348c97df44	1422	/** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
lypinator	0:bb348c97df44	1423	* @{
lypinator	0:bb348c97df44	1424	*/
lypinator	0:bb348c97df44	1425	/**
lypinator	0:bb348c97df44	1426	* @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
lypinator	0:bb348c97df44	1427	* @note CCxE, CCxNE and OCxM bits are preloaded, after having been written,
lypinator	0:bb348c97df44	1428	* they are updated only when a commutation event (COM) occurs.
lypinator	0:bb348c97df44	1429	* @note Only on channels that have a complementary output.
lypinator	0:bb348c97df44	1430	* @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
lypinator	0:bb348c97df44	1431	* whether or not a timer instance is able to generate a commutation event.
lypinator	0:bb348c97df44	1432	* @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload
lypinator	0:bb348c97df44	1433	* @param TIMx Timer instance
lypinator	0:bb348c97df44	1434	* @retval None
lypinator	0:bb348c97df44	1435	*/
lypinator	0:bb348c97df44	1436	__STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	1437	{
lypinator	0:bb348c97df44	1438	SET_BIT(TIMx->CR2, TIM_CR2_CCPC);
lypinator	0:bb348c97df44	1439	}
lypinator	0:bb348c97df44	1440
lypinator	0:bb348c97df44	1441	/**
lypinator	0:bb348c97df44	1442	* @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
lypinator	0:bb348c97df44	1443	* @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
lypinator	0:bb348c97df44	1444	* whether or not a timer instance is able to generate a commutation event.
lypinator	0:bb348c97df44	1445	* @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload
lypinator	0:bb348c97df44	1446	* @param TIMx Timer instance
lypinator	0:bb348c97df44	1447	* @retval None
lypinator	0:bb348c97df44	1448	*/
lypinator	0:bb348c97df44	1449	__STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	1450	{
lypinator	0:bb348c97df44	1451	CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);
lypinator	0:bb348c97df44	1452	}
lypinator	0:bb348c97df44	1453
lypinator	0:bb348c97df44	1454	/**
lypinator	0:bb348c97df44	1455	* @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
lypinator	0:bb348c97df44	1456	* @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
lypinator	0:bb348c97df44	1457	* whether or not a timer instance is able to generate a commutation event.
lypinator	0:bb348c97df44	1458	* @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate
lypinator	0:bb348c97df44	1459	* @param TIMx Timer instance
lypinator	0:bb348c97df44	1460	* @param CCUpdateSource This parameter can be one of the following values:
lypinator	0:bb348c97df44	1461	* @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY
lypinator	0:bb348c97df44	1462	* @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
lypinator	0:bb348c97df44	1463	* @retval None
lypinator	0:bb348c97df44	1464	*/
lypinator	0:bb348c97df44	1465	__STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
lypinator	0:bb348c97df44	1466	{
lypinator	0:bb348c97df44	1467	MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource);
lypinator	0:bb348c97df44	1468	}
lypinator	0:bb348c97df44	1469
lypinator	0:bb348c97df44	1470	/**
lypinator	0:bb348c97df44	1471	* @brief Set the trigger of the capture/compare DMA request.
lypinator	0:bb348c97df44	1472	* @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger
lypinator	0:bb348c97df44	1473	* @param TIMx Timer instance
lypinator	0:bb348c97df44	1474	* @param DMAReqTrigger This parameter can be one of the following values:
lypinator	0:bb348c97df44	1475	* @arg @ref LL_TIM_CCDMAREQUEST_CC
lypinator	0:bb348c97df44	1476	* @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
lypinator	0:bb348c97df44	1477	* @retval None
lypinator	0:bb348c97df44	1478	*/
lypinator	0:bb348c97df44	1479	__STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
lypinator	0:bb348c97df44	1480	{
lypinator	0:bb348c97df44	1481	MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
lypinator	0:bb348c97df44	1482	}
lypinator	0:bb348c97df44	1483
lypinator	0:bb348c97df44	1484	/**
lypinator	0:bb348c97df44	1485	* @brief Get actual trigger of the capture/compare DMA request.
lypinator	0:bb348c97df44	1486	* @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger
lypinator	0:bb348c97df44	1487	* @param TIMx Timer instance
lypinator	0:bb348c97df44	1488	* @retval Returned value can be one of the following values:
lypinator	0:bb348c97df44	1489	* @arg @ref LL_TIM_CCDMAREQUEST_CC
lypinator	0:bb348c97df44	1490	* @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
lypinator	0:bb348c97df44	1491	*/
lypinator	0:bb348c97df44	1492	__STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	1493	{
lypinator	0:bb348c97df44	1494	return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
lypinator	0:bb348c97df44	1495	}
lypinator	0:bb348c97df44	1496
lypinator	0:bb348c97df44	1497	/**
lypinator	0:bb348c97df44	1498	* @brief Set the lock level to freeze the
lypinator	0:bb348c97df44	1499	* configuration of several capture/compare parameters.
lypinator	0:bb348c97df44	1500	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
lypinator	0:bb348c97df44	1501	* the lock mechanism is supported by a timer instance.
lypinator	0:bb348c97df44	1502	* @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel
lypinator	0:bb348c97df44	1503	* @param TIMx Timer instance
lypinator	0:bb348c97df44	1504	* @param LockLevel This parameter can be one of the following values:
lypinator	0:bb348c97df44	1505	* @arg @ref LL_TIM_LOCKLEVEL_OFF
lypinator	0:bb348c97df44	1506	* @arg @ref LL_TIM_LOCKLEVEL_1
lypinator	0:bb348c97df44	1507	* @arg @ref LL_TIM_LOCKLEVEL_2
lypinator	0:bb348c97df44	1508	* @arg @ref LL_TIM_LOCKLEVEL_3
lypinator	0:bb348c97df44	1509	* @retval None
lypinator	0:bb348c97df44	1510	*/
lypinator	0:bb348c97df44	1511	__STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel)
lypinator	0:bb348c97df44	1512	{
lypinator	0:bb348c97df44	1513	MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel);
lypinator	0:bb348c97df44	1514	}
lypinator	0:bb348c97df44	1515
lypinator	0:bb348c97df44	1516	/**
lypinator	0:bb348c97df44	1517	* @brief Enable capture/compare channels.
lypinator	0:bb348c97df44	1518	* @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n
lypinator	0:bb348c97df44	1519	* CCER CC1NE LL_TIM_CC_EnableChannel\n
lypinator	0:bb348c97df44	1520	* CCER CC2E LL_TIM_CC_EnableChannel\n
lypinator	0:bb348c97df44	1521	* CCER CC2NE LL_TIM_CC_EnableChannel\n
lypinator	0:bb348c97df44	1522	* CCER CC3E LL_TIM_CC_EnableChannel\n
lypinator	0:bb348c97df44	1523	* CCER CC3NE LL_TIM_CC_EnableChannel\n
lypinator	0:bb348c97df44	1524	* CCER CC4E LL_TIM_CC_EnableChannel
lypinator	0:bb348c97df44	1525	* @param TIMx Timer instance
lypinator	0:bb348c97df44	1526	* @param Channels This parameter can be a combination of the following values:
lypinator	0:bb348c97df44	1527	* @arg @ref LL_TIM_CHANNEL_CH1
lypinator	0:bb348c97df44	1528	* @arg @ref LL_TIM_CHANNEL_CH1N
lypinator	0:bb348c97df44	1529	* @arg @ref LL_TIM_CHANNEL_CH2
lypinator	0:bb348c97df44	1530	* @arg @ref LL_TIM_CHANNEL_CH2N
lypinator	0:bb348c97df44	1531	* @arg @ref LL_TIM_CHANNEL_CH3
lypinator	0:bb348c97df44	1532	* @arg @ref LL_TIM_CHANNEL_CH3N
lypinator	0:bb348c97df44	1533	* @arg @ref LL_TIM_CHANNEL_CH4
lypinator	0:bb348c97df44	1534	* @retval None
lypinator	0:bb348c97df44	1535	*/
lypinator	0:bb348c97df44	1536	__STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
lypinator	0:bb348c97df44	1537	{
lypinator	0:bb348c97df44	1538	SET_BIT(TIMx->CCER, Channels);
lypinator	0:bb348c97df44	1539	}
lypinator	0:bb348c97df44	1540
lypinator	0:bb348c97df44	1541	/**
lypinator	0:bb348c97df44	1542	* @brief Disable capture/compare channels.
lypinator	0:bb348c97df44	1543	* @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n
lypinator	0:bb348c97df44	1544	* CCER CC1NE LL_TIM_CC_DisableChannel\n
lypinator	0:bb348c97df44	1545	* CCER CC2E LL_TIM_CC_DisableChannel\n
lypinator	0:bb348c97df44	1546	* CCER CC2NE LL_TIM_CC_DisableChannel\n
lypinator	0:bb348c97df44	1547	* CCER CC3E LL_TIM_CC_DisableChannel\n
lypinator	0:bb348c97df44	1548	* CCER CC3NE LL_TIM_CC_DisableChannel\n
lypinator	0:bb348c97df44	1549	* CCER CC4E LL_TIM_CC_DisableChannel
lypinator	0:bb348c97df44	1550	* @param TIMx Timer instance
lypinator	0:bb348c97df44	1551	* @param Channels This parameter can be a combination of the following values:
lypinator	0:bb348c97df44	1552	* @arg @ref LL_TIM_CHANNEL_CH1
lypinator	0:bb348c97df44	1553	* @arg @ref LL_TIM_CHANNEL_CH1N
lypinator	0:bb348c97df44	1554	* @arg @ref LL_TIM_CHANNEL_CH2
lypinator	0:bb348c97df44	1555	* @arg @ref LL_TIM_CHANNEL_CH2N
lypinator	0:bb348c97df44	1556	* @arg @ref LL_TIM_CHANNEL_CH3
lypinator	0:bb348c97df44	1557	* @arg @ref LL_TIM_CHANNEL_CH3N
lypinator	0:bb348c97df44	1558	* @arg @ref LL_TIM_CHANNEL_CH4
lypinator	0:bb348c97df44	1559	* @retval None
lypinator	0:bb348c97df44	1560	*/
lypinator	0:bb348c97df44	1561	__STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
lypinator	0:bb348c97df44	1562	{
lypinator	0:bb348c97df44	1563	CLEAR_BIT(TIMx->CCER, Channels);
lypinator	0:bb348c97df44	1564	}
lypinator	0:bb348c97df44	1565
lypinator	0:bb348c97df44	1566	/**
lypinator	0:bb348c97df44	1567	* @brief Indicate whether channel(s) is(are) enabled.
lypinator	0:bb348c97df44	1568	* @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n
lypinator	0:bb348c97df44	1569	* CCER CC1NE LL_TIM_CC_IsEnabledChannel\n
lypinator	0:bb348c97df44	1570	* CCER CC2E LL_TIM_CC_IsEnabledChannel\n
lypinator	0:bb348c97df44	1571	* CCER CC2NE LL_TIM_CC_IsEnabledChannel\n
lypinator	0:bb348c97df44	1572	* CCER CC3E LL_TIM_CC_IsEnabledChannel\n
lypinator	0:bb348c97df44	1573	* CCER CC3NE LL_TIM_CC_IsEnabledChannel\n
lypinator	0:bb348c97df44	1574	* CCER CC4E LL_TIM_CC_IsEnabledChannel
lypinator	0:bb348c97df44	1575	* @param TIMx Timer instance
lypinator	0:bb348c97df44	1576	* @param Channels This parameter can be a combination of the following values:
lypinator	0:bb348c97df44	1577	* @arg @ref LL_TIM_CHANNEL_CH1
lypinator	0:bb348c97df44	1578	* @arg @ref LL_TIM_CHANNEL_CH1N
lypinator	0:bb348c97df44	1579	* @arg @ref LL_TIM_CHANNEL_CH2
lypinator	0:bb348c97df44	1580	* @arg @ref LL_TIM_CHANNEL_CH2N
lypinator	0:bb348c97df44	1581	* @arg @ref LL_TIM_CHANNEL_CH3
lypinator	0:bb348c97df44	1582	* @arg @ref LL_TIM_CHANNEL_CH3N
lypinator	0:bb348c97df44	1583	* @arg @ref LL_TIM_CHANNEL_CH4
lypinator	0:bb348c97df44	1584	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	1585	*/
lypinator	0:bb348c97df44	1586	__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels)
lypinator	0:bb348c97df44	1587	{
lypinator	0:bb348c97df44	1588	return (READ_BIT(TIMx->CCER, Channels) == (Channels));
lypinator	0:bb348c97df44	1589	}
lypinator	0:bb348c97df44	1590
lypinator	0:bb348c97df44	1591	/**
lypinator	0:bb348c97df44	1592	* @}
lypinator	0:bb348c97df44	1593	*/
lypinator	0:bb348c97df44	1594
lypinator	0:bb348c97df44	1595	/** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
lypinator	0:bb348c97df44	1596	* @{
lypinator	0:bb348c97df44	1597	*/
lypinator	0:bb348c97df44	1598	/**
lypinator	0:bb348c97df44	1599	* @brief Configure an output channel.
lypinator	0:bb348c97df44	1600	* @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n
lypinator	0:bb348c97df44	1601	* CCMR1 CC2S LL_TIM_OC_ConfigOutput\n
lypinator	0:bb348c97df44	1602	* CCMR2 CC3S LL_TIM_OC_ConfigOutput\n
lypinator	0:bb348c97df44	1603	* CCMR2 CC4S LL_TIM_OC_ConfigOutput\n
lypinator	0:bb348c97df44	1604	* CCER CC1P LL_TIM_OC_ConfigOutput\n
lypinator	0:bb348c97df44	1605	* CCER CC2P LL_TIM_OC_ConfigOutput\n
lypinator	0:bb348c97df44	1606	* CCER CC3P LL_TIM_OC_ConfigOutput\n
lypinator	0:bb348c97df44	1607	* CCER CC4P LL_TIM_OC_ConfigOutput\n
lypinator	0:bb348c97df44	1608	* CR2 OIS1 LL_TIM_OC_ConfigOutput\n
lypinator	0:bb348c97df44	1609	* CR2 OIS2 LL_TIM_OC_ConfigOutput\n
lypinator	0:bb348c97df44	1610	* CR2 OIS3 LL_TIM_OC_ConfigOutput\n
lypinator	0:bb348c97df44	1611	* CR2 OIS4 LL_TIM_OC_ConfigOutput
lypinator	0:bb348c97df44	1612	* @param TIMx Timer instance
lypinator	0:bb348c97df44	1613	* @param Channel This parameter can be one of the following values:
lypinator	0:bb348c97df44	1614	* @arg @ref LL_TIM_CHANNEL_CH1
lypinator	0:bb348c97df44	1615	* @arg @ref LL_TIM_CHANNEL_CH2
lypinator	0:bb348c97df44	1616	* @arg @ref LL_TIM_CHANNEL_CH3
lypinator	0:bb348c97df44	1617	* @arg @ref LL_TIM_CHANNEL_CH4
lypinator	0:bb348c97df44	1618	* @param Configuration This parameter must be a combination of all the following values:
lypinator	0:bb348c97df44	1619	* @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
lypinator	0:bb348c97df44	1620	* @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH
lypinator	0:bb348c97df44	1621	* @retval None
lypinator	0:bb348c97df44	1622	*/
lypinator	0:bb348c97df44	1623	__STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
lypinator	0:bb348c97df44	1624	{
lypinator	0:bb348c97df44	1625	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
lypinator	0:bb348c97df44	1626	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
lypinator	0:bb348c97df44	1627	CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
lypinator	0:bb348c97df44	1628	MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
lypinator	0:bb348c97df44	1629	(Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
lypinator	0:bb348c97df44	1630	MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),
lypinator	0:bb348c97df44	1631	(Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]);
lypinator	0:bb348c97df44	1632	}
lypinator	0:bb348c97df44	1633
lypinator	0:bb348c97df44	1634	/**
lypinator	0:bb348c97df44	1635	* @brief Define the behavior of the output reference signal OCxREF from which
lypinator	0:bb348c97df44	1636	* OCx and OCxN (when relevant) are derived.
lypinator	0:bb348c97df44	1637	* @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n
lypinator	0:bb348c97df44	1638	* CCMR1 OC2M LL_TIM_OC_SetMode\n
lypinator	0:bb348c97df44	1639	* CCMR2 OC3M LL_TIM_OC_SetMode\n
lypinator	0:bb348c97df44	1640	* CCMR2 OC4M LL_TIM_OC_SetMode
lypinator	0:bb348c97df44	1641	* @param TIMx Timer instance
lypinator	0:bb348c97df44	1642	* @param Channel This parameter can be one of the following values:
lypinator	0:bb348c97df44	1643	* @arg @ref LL_TIM_CHANNEL_CH1
lypinator	0:bb348c97df44	1644	* @arg @ref LL_TIM_CHANNEL_CH2
lypinator	0:bb348c97df44	1645	* @arg @ref LL_TIM_CHANNEL_CH3
lypinator	0:bb348c97df44	1646	* @arg @ref LL_TIM_CHANNEL_CH4
lypinator	0:bb348c97df44	1647	* @param Mode This parameter can be one of the following values:
lypinator	0:bb348c97df44	1648	* @arg @ref LL_TIM_OCMODE_FROZEN
lypinator	0:bb348c97df44	1649	* @arg @ref LL_TIM_OCMODE_ACTIVE
lypinator	0:bb348c97df44	1650	* @arg @ref LL_TIM_OCMODE_INACTIVE
lypinator	0:bb348c97df44	1651	* @arg @ref LL_TIM_OCMODE_TOGGLE
lypinator	0:bb348c97df44	1652	* @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
lypinator	0:bb348c97df44	1653	* @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
lypinator	0:bb348c97df44	1654	* @arg @ref LL_TIM_OCMODE_PWM1
lypinator	0:bb348c97df44	1655	* @arg @ref LL_TIM_OCMODE_PWM2
lypinator	0:bb348c97df44	1656	* @retval None
lypinator	0:bb348c97df44	1657	*/
lypinator	0:bb348c97df44	1658	__STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
lypinator	0:bb348c97df44	1659	{
lypinator	0:bb348c97df44	1660	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
lypinator	0:bb348c97df44	1661	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
lypinator	0:bb348c97df44	1662	MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M \| TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
lypinator	0:bb348c97df44	1663	}
lypinator	0:bb348c97df44	1664
lypinator	0:bb348c97df44	1665	/**
lypinator	0:bb348c97df44	1666	* @brief Get the output compare mode of an output channel.
lypinator	0:bb348c97df44	1667	* @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n
lypinator	0:bb348c97df44	1668	* CCMR1 OC2M LL_TIM_OC_GetMode\n
lypinator	0:bb348c97df44	1669	* CCMR2 OC3M LL_TIM_OC_GetMode\n
lypinator	0:bb348c97df44	1670	* CCMR2 OC4M LL_TIM_OC_GetMode
lypinator	0:bb348c97df44	1671	* @param TIMx Timer instance
lypinator	0:bb348c97df44	1672	* @param Channel This parameter can be one of the following values:
lypinator	0:bb348c97df44	1673	* @arg @ref LL_TIM_CHANNEL_CH1
lypinator	0:bb348c97df44	1674	* @arg @ref LL_TIM_CHANNEL_CH2
lypinator	0:bb348c97df44	1675	* @arg @ref LL_TIM_CHANNEL_CH3
lypinator	0:bb348c97df44	1676	* @arg @ref LL_TIM_CHANNEL_CH4
lypinator	0:bb348c97df44	1677	* @retval Returned value can be one of the following values:
lypinator	0:bb348c97df44	1678	* @arg @ref LL_TIM_OCMODE_FROZEN
lypinator	0:bb348c97df44	1679	* @arg @ref LL_TIM_OCMODE_ACTIVE
lypinator	0:bb348c97df44	1680	* @arg @ref LL_TIM_OCMODE_INACTIVE
lypinator	0:bb348c97df44	1681	* @arg @ref LL_TIM_OCMODE_TOGGLE
lypinator	0:bb348c97df44	1682	* @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
lypinator	0:bb348c97df44	1683	* @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
lypinator	0:bb348c97df44	1684	* @arg @ref LL_TIM_OCMODE_PWM1
lypinator	0:bb348c97df44	1685	* @arg @ref LL_TIM_OCMODE_PWM2
lypinator	0:bb348c97df44	1686	*/
lypinator	0:bb348c97df44	1687	__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel)
lypinator	0:bb348c97df44	1688	{
lypinator	0:bb348c97df44	1689	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
lypinator	0:bb348c97df44	1690	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
lypinator	0:bb348c97df44	1691	return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M \| TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
lypinator	0:bb348c97df44	1692	}
lypinator	0:bb348c97df44	1693
lypinator	0:bb348c97df44	1694	/**
lypinator	0:bb348c97df44	1695	* @brief Set the polarity of an output channel.
lypinator	0:bb348c97df44	1696	* @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n
lypinator	0:bb348c97df44	1697	* CCER CC1NP LL_TIM_OC_SetPolarity\n
lypinator	0:bb348c97df44	1698	* CCER CC2P LL_TIM_OC_SetPolarity\n
lypinator	0:bb348c97df44	1699	* CCER CC2NP LL_TIM_OC_SetPolarity\n
lypinator	0:bb348c97df44	1700	* CCER CC3P LL_TIM_OC_SetPolarity\n
lypinator	0:bb348c97df44	1701	* CCER CC3NP LL_TIM_OC_SetPolarity\n
lypinator	0:bb348c97df44	1702	* CCER CC4P LL_TIM_OC_SetPolarity
lypinator	0:bb348c97df44	1703	* @param TIMx Timer instance
lypinator	0:bb348c97df44	1704	* @param Channel This parameter can be one of the following values:
lypinator	0:bb348c97df44	1705	* @arg @ref LL_TIM_CHANNEL_CH1
lypinator	0:bb348c97df44	1706	* @arg @ref LL_TIM_CHANNEL_CH1N
lypinator	0:bb348c97df44	1707	* @arg @ref LL_TIM_CHANNEL_CH2
lypinator	0:bb348c97df44	1708	* @arg @ref LL_TIM_CHANNEL_CH2N
lypinator	0:bb348c97df44	1709	* @arg @ref LL_TIM_CHANNEL_CH3
lypinator	0:bb348c97df44	1710	* @arg @ref LL_TIM_CHANNEL_CH3N
lypinator	0:bb348c97df44	1711	* @arg @ref LL_TIM_CHANNEL_CH4
lypinator	0:bb348c97df44	1712	* @param Polarity This parameter can be one of the following values:
lypinator	0:bb348c97df44	1713	* @arg @ref LL_TIM_OCPOLARITY_HIGH
lypinator	0:bb348c97df44	1714	* @arg @ref LL_TIM_OCPOLARITY_LOW
lypinator	0:bb348c97df44	1715	* @retval None
lypinator	0:bb348c97df44	1716	*/
lypinator	0:bb348c97df44	1717	__STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
lypinator	0:bb348c97df44	1718	{
lypinator	0:bb348c97df44	1719	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
lypinator	0:bb348c97df44	1720	MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]);
lypinator	0:bb348c97df44	1721	}
lypinator	0:bb348c97df44	1722
lypinator	0:bb348c97df44	1723	/**
lypinator	0:bb348c97df44	1724	* @brief Get the polarity of an output channel.
lypinator	0:bb348c97df44	1725	* @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n
lypinator	0:bb348c97df44	1726	* CCER CC1NP LL_TIM_OC_GetPolarity\n
lypinator	0:bb348c97df44	1727	* CCER CC2P LL_TIM_OC_GetPolarity\n
lypinator	0:bb348c97df44	1728	* CCER CC2NP LL_TIM_OC_GetPolarity\n
lypinator	0:bb348c97df44	1729	* CCER CC3P LL_TIM_OC_GetPolarity\n
lypinator	0:bb348c97df44	1730	* CCER CC3NP LL_TIM_OC_GetPolarity\n
lypinator	0:bb348c97df44	1731	* CCER CC4P LL_TIM_OC_GetPolarity
lypinator	0:bb348c97df44	1732	* @param TIMx Timer instance
lypinator	0:bb348c97df44	1733	* @param Channel This parameter can be one of the following values:
lypinator	0:bb348c97df44	1734	* @arg @ref LL_TIM_CHANNEL_CH1
lypinator	0:bb348c97df44	1735	* @arg @ref LL_TIM_CHANNEL_CH1N
lypinator	0:bb348c97df44	1736	* @arg @ref LL_TIM_CHANNEL_CH2
lypinator	0:bb348c97df44	1737	* @arg @ref LL_TIM_CHANNEL_CH2N
lypinator	0:bb348c97df44	1738	* @arg @ref LL_TIM_CHANNEL_CH3
lypinator	0:bb348c97df44	1739	* @arg @ref LL_TIM_CHANNEL_CH3N
lypinator	0:bb348c97df44	1740	* @arg @ref LL_TIM_CHANNEL_CH4
lypinator	0:bb348c97df44	1741	* @retval Returned value can be one of the following values:
lypinator	0:bb348c97df44	1742	* @arg @ref LL_TIM_OCPOLARITY_HIGH
lypinator	0:bb348c97df44	1743	* @arg @ref LL_TIM_OCPOLARITY_LOW
lypinator	0:bb348c97df44	1744	*/
lypinator	0:bb348c97df44	1745	__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
lypinator	0:bb348c97df44	1746	{
lypinator	0:bb348c97df44	1747	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
lypinator	0:bb348c97df44	1748	return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
lypinator	0:bb348c97df44	1749	}
lypinator	0:bb348c97df44	1750
lypinator	0:bb348c97df44	1751	/**
lypinator	0:bb348c97df44	1752	* @brief Set the IDLE state of an output channel
lypinator	0:bb348c97df44	1753	* @note This function is significant only for the timer instances
lypinator	0:bb348c97df44	1754	* supporting the break feature. Macro @ref IS_TIM_BREAK_INSTANCE(TIMx)
lypinator	0:bb348c97df44	1755	* can be used to check whether or not a timer instance provides
lypinator	0:bb348c97df44	1756	* a break input.
lypinator	0:bb348c97df44	1757	* @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n
lypinator	0:bb348c97df44	1758	* CR2 OIS1N LL_TIM_OC_SetIdleState\n
lypinator	0:bb348c97df44	1759	* CR2 OIS2 LL_TIM_OC_SetIdleState\n
lypinator	0:bb348c97df44	1760	* CR2 OIS2N LL_TIM_OC_SetIdleState\n
lypinator	0:bb348c97df44	1761	* CR2 OIS3 LL_TIM_OC_SetIdleState\n
lypinator	0:bb348c97df44	1762	* CR2 OIS3N LL_TIM_OC_SetIdleState\n
lypinator	0:bb348c97df44	1763	* CR2 OIS4 LL_TIM_OC_SetIdleState
lypinator	0:bb348c97df44	1764	* @param TIMx Timer instance
lypinator	0:bb348c97df44	1765	* @param Channel This parameter can be one of the following values:
lypinator	0:bb348c97df44	1766	* @arg @ref LL_TIM_CHANNEL_CH1
lypinator	0:bb348c97df44	1767	* @arg @ref LL_TIM_CHANNEL_CH1N
lypinator	0:bb348c97df44	1768	* @arg @ref LL_TIM_CHANNEL_CH2
lypinator	0:bb348c97df44	1769	* @arg @ref LL_TIM_CHANNEL_CH2N
lypinator	0:bb348c97df44	1770	* @arg @ref LL_TIM_CHANNEL_CH3
lypinator	0:bb348c97df44	1771	* @arg @ref LL_TIM_CHANNEL_CH3N
lypinator	0:bb348c97df44	1772	* @arg @ref LL_TIM_CHANNEL_CH4
lypinator	0:bb348c97df44	1773	* @param IdleState This parameter can be one of the following values:
lypinator	0:bb348c97df44	1774	* @arg @ref LL_TIM_OCIDLESTATE_LOW
lypinator	0:bb348c97df44	1775	* @arg @ref LL_TIM_OCIDLESTATE_HIGH
lypinator	0:bb348c97df44	1776	* @retval None
lypinator	0:bb348c97df44	1777	*/
lypinator	0:bb348c97df44	1778	__STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
lypinator	0:bb348c97df44	1779	{
lypinator	0:bb348c97df44	1780	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
lypinator	0:bb348c97df44	1781	MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]);
lypinator	0:bb348c97df44	1782	}
lypinator	0:bb348c97df44	1783
lypinator	0:bb348c97df44	1784	/**
lypinator	0:bb348c97df44	1785	* @brief Get the IDLE state of an output channel
lypinator	0:bb348c97df44	1786	* @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n
lypinator	0:bb348c97df44	1787	* CR2 OIS1N LL_TIM_OC_GetIdleState\n
lypinator	0:bb348c97df44	1788	* CR2 OIS2 LL_TIM_OC_GetIdleState\n
lypinator	0:bb348c97df44	1789	* CR2 OIS2N LL_TIM_OC_GetIdleState\n
lypinator	0:bb348c97df44	1790	* CR2 OIS3 LL_TIM_OC_GetIdleState\n
lypinator	0:bb348c97df44	1791	* CR2 OIS3N LL_TIM_OC_GetIdleState\n
lypinator	0:bb348c97df44	1792	* CR2 OIS4 LL_TIM_OC_GetIdleState
lypinator	0:bb348c97df44	1793	* @param TIMx Timer instance
lypinator	0:bb348c97df44	1794	* @param Channel This parameter can be one of the following values:
lypinator	0:bb348c97df44	1795	* @arg @ref LL_TIM_CHANNEL_CH1
lypinator	0:bb348c97df44	1796	* @arg @ref LL_TIM_CHANNEL_CH1N
lypinator	0:bb348c97df44	1797	* @arg @ref LL_TIM_CHANNEL_CH2
lypinator	0:bb348c97df44	1798	* @arg @ref LL_TIM_CHANNEL_CH2N
lypinator	0:bb348c97df44	1799	* @arg @ref LL_TIM_CHANNEL_CH3
lypinator	0:bb348c97df44	1800	* @arg @ref LL_TIM_CHANNEL_CH3N
lypinator	0:bb348c97df44	1801	* @arg @ref LL_TIM_CHANNEL_CH4
lypinator	0:bb348c97df44	1802	* @retval Returned value can be one of the following values:
lypinator	0:bb348c97df44	1803	* @arg @ref LL_TIM_OCIDLESTATE_LOW
lypinator	0:bb348c97df44	1804	* @arg @ref LL_TIM_OCIDLESTATE_HIGH
lypinator	0:bb348c97df44	1805	*/
lypinator	0:bb348c97df44	1806	__STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Channel)
lypinator	0:bb348c97df44	1807	{
lypinator	0:bb348c97df44	1808	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
lypinator	0:bb348c97df44	1809	return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
lypinator	0:bb348c97df44	1810	}
lypinator	0:bb348c97df44	1811
lypinator	0:bb348c97df44	1812	/**
lypinator	0:bb348c97df44	1813	* @brief Enable fast mode for the output channel.
lypinator	0:bb348c97df44	1814	* @note Acts only if the channel is configured in PWM1 or PWM2 mode.
lypinator	0:bb348c97df44	1815	* @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n
lypinator	0:bb348c97df44	1816	* CCMR1 OC2FE LL_TIM_OC_EnableFast\n
lypinator	0:bb348c97df44	1817	* CCMR2 OC3FE LL_TIM_OC_EnableFast\n
lypinator	0:bb348c97df44	1818	* CCMR2 OC4FE LL_TIM_OC_EnableFast
lypinator	0:bb348c97df44	1819	* @param TIMx Timer instance
lypinator	0:bb348c97df44	1820	* @param Channel This parameter can be one of the following values:
lypinator	0:bb348c97df44	1821	* @arg @ref LL_TIM_CHANNEL_CH1
lypinator	0:bb348c97df44	1822	* @arg @ref LL_TIM_CHANNEL_CH2
lypinator	0:bb348c97df44	1823	* @arg @ref LL_TIM_CHANNEL_CH3
lypinator	0:bb348c97df44	1824	* @arg @ref LL_TIM_CHANNEL_CH4
lypinator	0:bb348c97df44	1825	* @retval None
lypinator	0:bb348c97df44	1826	*/
lypinator	0:bb348c97df44	1827	__STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
lypinator	0:bb348c97df44	1828	{
lypinator	0:bb348c97df44	1829	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
lypinator	0:bb348c97df44	1830	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
lypinator	0:bb348c97df44	1831	SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
lypinator	0:bb348c97df44	1832
lypinator	0:bb348c97df44	1833	}
lypinator	0:bb348c97df44	1834
lypinator	0:bb348c97df44	1835	/**
lypinator	0:bb348c97df44	1836	* @brief Disable fast mode for the output channel.
lypinator	0:bb348c97df44	1837	* @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n
lypinator	0:bb348c97df44	1838	* CCMR1 OC2FE LL_TIM_OC_DisableFast\n
lypinator	0:bb348c97df44	1839	* CCMR2 OC3FE LL_TIM_OC_DisableFast\n
lypinator	0:bb348c97df44	1840	* CCMR2 OC4FE LL_TIM_OC_DisableFast
lypinator	0:bb348c97df44	1841	* @param TIMx Timer instance
lypinator	0:bb348c97df44	1842	* @param Channel This parameter can be one of the following values:
lypinator	0:bb348c97df44	1843	* @arg @ref LL_TIM_CHANNEL_CH1
lypinator	0:bb348c97df44	1844	* @arg @ref LL_TIM_CHANNEL_CH2
lypinator	0:bb348c97df44	1845	* @arg @ref LL_TIM_CHANNEL_CH3
lypinator	0:bb348c97df44	1846	* @arg @ref LL_TIM_CHANNEL_CH4
lypinator	0:bb348c97df44	1847	* @retval None
lypinator	0:bb348c97df44	1848	*/
lypinator	0:bb348c97df44	1849	__STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
lypinator	0:bb348c97df44	1850	{
lypinator	0:bb348c97df44	1851	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
lypinator	0:bb348c97df44	1852	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
lypinator	0:bb348c97df44	1853	CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
lypinator	0:bb348c97df44	1854
lypinator	0:bb348c97df44	1855	}
lypinator	0:bb348c97df44	1856
lypinator	0:bb348c97df44	1857	/**
lypinator	0:bb348c97df44	1858	* @brief Indicates whether fast mode is enabled for the output channel.
lypinator	0:bb348c97df44	1859	* @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n
lypinator	0:bb348c97df44	1860	* CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n
lypinator	0:bb348c97df44	1861	* CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n
lypinator	0:bb348c97df44	1862	* CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n
lypinator	0:bb348c97df44	1863	* @param TIMx Timer instance
lypinator	0:bb348c97df44	1864	* @param Channel This parameter can be one of the following values:
lypinator	0:bb348c97df44	1865	* @arg @ref LL_TIM_CHANNEL_CH1
lypinator	0:bb348c97df44	1866	* @arg @ref LL_TIM_CHANNEL_CH2
lypinator	0:bb348c97df44	1867	* @arg @ref LL_TIM_CHANNEL_CH3
lypinator	0:bb348c97df44	1868	* @arg @ref LL_TIM_CHANNEL_CH4
lypinator	0:bb348c97df44	1869	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	1870	*/
lypinator	0:bb348c97df44	1871	__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel)
lypinator	0:bb348c97df44	1872	{
lypinator	0:bb348c97df44	1873	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
lypinator	0:bb348c97df44	1874	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
lypinator	0:bb348c97df44	1875	register uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
lypinator	0:bb348c97df44	1876	return (READ_BIT(*pReg, bitfield) == bitfield);
lypinator	0:bb348c97df44	1877	}
lypinator	0:bb348c97df44	1878
lypinator	0:bb348c97df44	1879	/**
lypinator	0:bb348c97df44	1880	* @brief Enable compare register (TIMx_CCRx) preload for the output channel.
lypinator	0:bb348c97df44	1881	* @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n
lypinator	0:bb348c97df44	1882	* CCMR1 OC2PE LL_TIM_OC_EnablePreload\n
lypinator	0:bb348c97df44	1883	* CCMR2 OC3PE LL_TIM_OC_EnablePreload\n
lypinator	0:bb348c97df44	1884	* CCMR2 OC4PE LL_TIM_OC_EnablePreload
lypinator	0:bb348c97df44	1885	* @param TIMx Timer instance
lypinator	0:bb348c97df44	1886	* @param Channel This parameter can be one of the following values:
lypinator	0:bb348c97df44	1887	* @arg @ref LL_TIM_CHANNEL_CH1
lypinator	0:bb348c97df44	1888	* @arg @ref LL_TIM_CHANNEL_CH2
lypinator	0:bb348c97df44	1889	* @arg @ref LL_TIM_CHANNEL_CH3
lypinator	0:bb348c97df44	1890	* @arg @ref LL_TIM_CHANNEL_CH4
lypinator	0:bb348c97df44	1891	* @retval None
lypinator	0:bb348c97df44	1892	*/
lypinator	0:bb348c97df44	1893	__STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
lypinator	0:bb348c97df44	1894	{
lypinator	0:bb348c97df44	1895	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
lypinator	0:bb348c97df44	1896	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
lypinator	0:bb348c97df44	1897	SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
lypinator	0:bb348c97df44	1898	}
lypinator	0:bb348c97df44	1899
lypinator	0:bb348c97df44	1900	/**
lypinator	0:bb348c97df44	1901	* @brief Disable compare register (TIMx_CCRx) preload for the output channel.
lypinator	0:bb348c97df44	1902	* @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n
lypinator	0:bb348c97df44	1903	* CCMR1 OC2PE LL_TIM_OC_DisablePreload\n
lypinator	0:bb348c97df44	1904	* CCMR2 OC3PE LL_TIM_OC_DisablePreload\n
lypinator	0:bb348c97df44	1905	* CCMR2 OC4PE LL_TIM_OC_DisablePreload
lypinator	0:bb348c97df44	1906	* @param TIMx Timer instance
lypinator	0:bb348c97df44	1907	* @param Channel This parameter can be one of the following values:
lypinator	0:bb348c97df44	1908	* @arg @ref LL_TIM_CHANNEL_CH1
lypinator	0:bb348c97df44	1909	* @arg @ref LL_TIM_CHANNEL_CH2
lypinator	0:bb348c97df44	1910	* @arg @ref LL_TIM_CHANNEL_CH3
lypinator	0:bb348c97df44	1911	* @arg @ref LL_TIM_CHANNEL_CH4
lypinator	0:bb348c97df44	1912	* @retval None
lypinator	0:bb348c97df44	1913	*/
lypinator	0:bb348c97df44	1914	__STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
lypinator	0:bb348c97df44	1915	{
lypinator	0:bb348c97df44	1916	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
lypinator	0:bb348c97df44	1917	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
lypinator	0:bb348c97df44	1918	CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
lypinator	0:bb348c97df44	1919	}
lypinator	0:bb348c97df44	1920
lypinator	0:bb348c97df44	1921	/**
lypinator	0:bb348c97df44	1922	* @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
lypinator	0:bb348c97df44	1923	* @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n
lypinator	0:bb348c97df44	1924	* CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n
lypinator	0:bb348c97df44	1925	* CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n
lypinator	0:bb348c97df44	1926	* CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n
lypinator	0:bb348c97df44	1927	* @param TIMx Timer instance
lypinator	0:bb348c97df44	1928	* @param Channel This parameter can be one of the following values:
lypinator	0:bb348c97df44	1929	* @arg @ref LL_TIM_CHANNEL_CH1
lypinator	0:bb348c97df44	1930	* @arg @ref LL_TIM_CHANNEL_CH2
lypinator	0:bb348c97df44	1931	* @arg @ref LL_TIM_CHANNEL_CH3
lypinator	0:bb348c97df44	1932	* @arg @ref LL_TIM_CHANNEL_CH4
lypinator	0:bb348c97df44	1933	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	1934	*/
lypinator	0:bb348c97df44	1935	__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel)
lypinator	0:bb348c97df44	1936	{
lypinator	0:bb348c97df44	1937	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
lypinator	0:bb348c97df44	1938	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
lypinator	0:bb348c97df44	1939	register uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
lypinator	0:bb348c97df44	1940	return (READ_BIT(*pReg, bitfield) == bitfield);
lypinator	0:bb348c97df44	1941	}
lypinator	0:bb348c97df44	1942
lypinator	0:bb348c97df44	1943	/**
lypinator	0:bb348c97df44	1944	* @brief Enable clearing the output channel on an external event.
lypinator	0:bb348c97df44	1945	* @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
lypinator	0:bb348c97df44	1946	* @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
lypinator	0:bb348c97df44	1947	* or not a timer instance can clear the OCxREF signal on an external event.
lypinator	0:bb348c97df44	1948	* @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n
lypinator	0:bb348c97df44	1949	* CCMR1 OC2CE LL_TIM_OC_EnableClear\n
lypinator	0:bb348c97df44	1950	* CCMR2 OC3CE LL_TIM_OC_EnableClear\n
lypinator	0:bb348c97df44	1951	* CCMR2 OC4CE LL_TIM_OC_EnableClear
lypinator	0:bb348c97df44	1952	* @param TIMx Timer instance
lypinator	0:bb348c97df44	1953	* @param Channel This parameter can be one of the following values:
lypinator	0:bb348c97df44	1954	* @arg @ref LL_TIM_CHANNEL_CH1
lypinator	0:bb348c97df44	1955	* @arg @ref LL_TIM_CHANNEL_CH2
lypinator	0:bb348c97df44	1956	* @arg @ref LL_TIM_CHANNEL_CH3
lypinator	0:bb348c97df44	1957	* @arg @ref LL_TIM_CHANNEL_CH4
lypinator	0:bb348c97df44	1958	* @retval None
lypinator	0:bb348c97df44	1959	*/
lypinator	0:bb348c97df44	1960	__STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
lypinator	0:bb348c97df44	1961	{
lypinator	0:bb348c97df44	1962	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
lypinator	0:bb348c97df44	1963	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
lypinator	0:bb348c97df44	1964	SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
lypinator	0:bb348c97df44	1965	}
lypinator	0:bb348c97df44	1966
lypinator	0:bb348c97df44	1967	/**
lypinator	0:bb348c97df44	1968	* @brief Disable clearing the output channel on an external event.
lypinator	0:bb348c97df44	1969	* @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
lypinator	0:bb348c97df44	1970	* or not a timer instance can clear the OCxREF signal on an external event.
lypinator	0:bb348c97df44	1971	* @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n
lypinator	0:bb348c97df44	1972	* CCMR1 OC2CE LL_TIM_OC_DisableClear\n
lypinator	0:bb348c97df44	1973	* CCMR2 OC3CE LL_TIM_OC_DisableClear\n
lypinator	0:bb348c97df44	1974	* CCMR2 OC4CE LL_TIM_OC_DisableClear
lypinator	0:bb348c97df44	1975	* @param TIMx Timer instance
lypinator	0:bb348c97df44	1976	* @param Channel This parameter can be one of the following values:
lypinator	0:bb348c97df44	1977	* @arg @ref LL_TIM_CHANNEL_CH1
lypinator	0:bb348c97df44	1978	* @arg @ref LL_TIM_CHANNEL_CH2
lypinator	0:bb348c97df44	1979	* @arg @ref LL_TIM_CHANNEL_CH3
lypinator	0:bb348c97df44	1980	* @arg @ref LL_TIM_CHANNEL_CH4
lypinator	0:bb348c97df44	1981	* @retval None
lypinator	0:bb348c97df44	1982	*/
lypinator	0:bb348c97df44	1983	__STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
lypinator	0:bb348c97df44	1984	{
lypinator	0:bb348c97df44	1985	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
lypinator	0:bb348c97df44	1986	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
lypinator	0:bb348c97df44	1987	CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
lypinator	0:bb348c97df44	1988	}
lypinator	0:bb348c97df44	1989
lypinator	0:bb348c97df44	1990	/**
lypinator	0:bb348c97df44	1991	* @brief Indicates clearing the output channel on an external event is enabled for the output channel.
lypinator	0:bb348c97df44	1992	* @note This function enables clearing the output channel on an external event.
lypinator	0:bb348c97df44	1993	* @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
lypinator	0:bb348c97df44	1994	* @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
lypinator	0:bb348c97df44	1995	* or not a timer instance can clear the OCxREF signal on an external event.
lypinator	0:bb348c97df44	1996	* @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n
lypinator	0:bb348c97df44	1997	* CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n
lypinator	0:bb348c97df44	1998	* CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n
lypinator	0:bb348c97df44	1999	* CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n
lypinator	0:bb348c97df44	2000	* @param TIMx Timer instance
lypinator	0:bb348c97df44	2001	* @param Channel This parameter can be one of the following values:
lypinator	0:bb348c97df44	2002	* @arg @ref LL_TIM_CHANNEL_CH1
lypinator	0:bb348c97df44	2003	* @arg @ref LL_TIM_CHANNEL_CH2
lypinator	0:bb348c97df44	2004	* @arg @ref LL_TIM_CHANNEL_CH3
lypinator	0:bb348c97df44	2005	* @arg @ref LL_TIM_CHANNEL_CH4
lypinator	0:bb348c97df44	2006	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	2007	*/
lypinator	0:bb348c97df44	2008	__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel)
lypinator	0:bb348c97df44	2009	{
lypinator	0:bb348c97df44	2010	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
lypinator	0:bb348c97df44	2011	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
lypinator	0:bb348c97df44	2012	register uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
lypinator	0:bb348c97df44	2013	return (READ_BIT(*pReg, bitfield) == bitfield);
lypinator	0:bb348c97df44	2014	}
lypinator	0:bb348c97df44	2015
lypinator	0:bb348c97df44	2016	/**
lypinator	0:bb348c97df44	2017	* @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge if the Ocx and OCxN signals).
lypinator	0:bb348c97df44	2018	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
lypinator	0:bb348c97df44	2019	* dead-time insertion feature is supported by a timer instance.
lypinator	0:bb348c97df44	2020	* @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
lypinator	0:bb348c97df44	2021	* @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime
lypinator	0:bb348c97df44	2022	* @param TIMx Timer instance
lypinator	0:bb348c97df44	2023	* @param DeadTime between Min_Data=0 and Max_Data=255
lypinator	0:bb348c97df44	2024	* @retval None
lypinator	0:bb348c97df44	2025	*/
lypinator	0:bb348c97df44	2026	__STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
lypinator	0:bb348c97df44	2027	{
lypinator	0:bb348c97df44	2028	MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime);
lypinator	0:bb348c97df44	2029	}
lypinator	0:bb348c97df44	2030
lypinator	0:bb348c97df44	2031	/**
lypinator	0:bb348c97df44	2032	* @brief Set compare value for output channel 1 (TIMx_CCR1).
lypinator	0:bb348c97df44	2033	* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
lypinator	0:bb348c97df44	2034	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
lypinator	0:bb348c97df44	2035	* whether or not a timer instance supports a 32 bits counter.
lypinator	0:bb348c97df44	2036	* @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
lypinator	0:bb348c97df44	2037	* output channel 1 is supported by a timer instance.
lypinator	0:bb348c97df44	2038	* @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1
lypinator	0:bb348c97df44	2039	* @param TIMx Timer instance
lypinator	0:bb348c97df44	2040	* @param CompareValue between Min_Data=0 and Max_Data=65535
lypinator	0:bb348c97df44	2041	* @retval None
lypinator	0:bb348c97df44	2042	*/
lypinator	0:bb348c97df44	2043	__STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue)
lypinator	0:bb348c97df44	2044	{
lypinator	0:bb348c97df44	2045	WRITE_REG(TIMx->CCR1, CompareValue);
lypinator	0:bb348c97df44	2046	}
lypinator	0:bb348c97df44	2047
lypinator	0:bb348c97df44	2048	/**
lypinator	0:bb348c97df44	2049	* @brief Set compare value for output channel 2 (TIMx_CCR2).
lypinator	0:bb348c97df44	2050	* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
lypinator	0:bb348c97df44	2051	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
lypinator	0:bb348c97df44	2052	* whether or not a timer instance supports a 32 bits counter.
lypinator	0:bb348c97df44	2053	* @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
lypinator	0:bb348c97df44	2054	* output channel 2 is supported by a timer instance.
lypinator	0:bb348c97df44	2055	* @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2
lypinator	0:bb348c97df44	2056	* @param TIMx Timer instance
lypinator	0:bb348c97df44	2057	* @param CompareValue between Min_Data=0 and Max_Data=65535
lypinator	0:bb348c97df44	2058	* @retval None
lypinator	0:bb348c97df44	2059	*/
lypinator	0:bb348c97df44	2060	__STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue)
lypinator	0:bb348c97df44	2061	{
lypinator	0:bb348c97df44	2062	WRITE_REG(TIMx->CCR2, CompareValue);
lypinator	0:bb348c97df44	2063	}
lypinator	0:bb348c97df44	2064
lypinator	0:bb348c97df44	2065	/**
lypinator	0:bb348c97df44	2066	* @brief Set compare value for output channel 3 (TIMx_CCR3).
lypinator	0:bb348c97df44	2067	* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
lypinator	0:bb348c97df44	2068	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
lypinator	0:bb348c97df44	2069	* whether or not a timer instance supports a 32 bits counter.
lypinator	0:bb348c97df44	2070	* @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
lypinator	0:bb348c97df44	2071	* output channel is supported by a timer instance.
lypinator	0:bb348c97df44	2072	* @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3
lypinator	0:bb348c97df44	2073	* @param TIMx Timer instance
lypinator	0:bb348c97df44	2074	* @param CompareValue between Min_Data=0 and Max_Data=65535
lypinator	0:bb348c97df44	2075	* @retval None
lypinator	0:bb348c97df44	2076	*/
lypinator	0:bb348c97df44	2077	__STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue)
lypinator	0:bb348c97df44	2078	{
lypinator	0:bb348c97df44	2079	WRITE_REG(TIMx->CCR3, CompareValue);
lypinator	0:bb348c97df44	2080	}
lypinator	0:bb348c97df44	2081
lypinator	0:bb348c97df44	2082	/**
lypinator	0:bb348c97df44	2083	* @brief Set compare value for output channel 4 (TIMx_CCR4).
lypinator	0:bb348c97df44	2084	* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
lypinator	0:bb348c97df44	2085	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
lypinator	0:bb348c97df44	2086	* whether or not a timer instance supports a 32 bits counter.
lypinator	0:bb348c97df44	2087	* @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
lypinator	0:bb348c97df44	2088	* output channel 4 is supported by a timer instance.
lypinator	0:bb348c97df44	2089	* @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4
lypinator	0:bb348c97df44	2090	* @param TIMx Timer instance
lypinator	0:bb348c97df44	2091	* @param CompareValue between Min_Data=0 and Max_Data=65535
lypinator	0:bb348c97df44	2092	* @retval None
lypinator	0:bb348c97df44	2093	*/
lypinator	0:bb348c97df44	2094	__STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue)
lypinator	0:bb348c97df44	2095	{
lypinator	0:bb348c97df44	2096	WRITE_REG(TIMx->CCR4, CompareValue);
lypinator	0:bb348c97df44	2097	}
lypinator	0:bb348c97df44	2098
lypinator	0:bb348c97df44	2099	/**
lypinator	0:bb348c97df44	2100	* @brief Get compare value (TIMx_CCR1) set for output channel 1.
lypinator	0:bb348c97df44	2101	* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
lypinator	0:bb348c97df44	2102	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
lypinator	0:bb348c97df44	2103	* whether or not a timer instance supports a 32 bits counter.
lypinator	0:bb348c97df44	2104	* @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
lypinator	0:bb348c97df44	2105	* output channel 1 is supported by a timer instance.
lypinator	0:bb348c97df44	2106	* @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1
lypinator	0:bb348c97df44	2107	* @param TIMx Timer instance
lypinator	0:bb348c97df44	2108	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
lypinator	0:bb348c97df44	2109	*/
lypinator	0:bb348c97df44	2110	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	2111	{
lypinator	0:bb348c97df44	2112	return (uint32_t)(READ_REG(TIMx->CCR1));
lypinator	0:bb348c97df44	2113	}
lypinator	0:bb348c97df44	2114
lypinator	0:bb348c97df44	2115	/**
lypinator	0:bb348c97df44	2116	* @brief Get compare value (TIMx_CCR2) set for output channel 2.
lypinator	0:bb348c97df44	2117	* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
lypinator	0:bb348c97df44	2118	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
lypinator	0:bb348c97df44	2119	* whether or not a timer instance supports a 32 bits counter.
lypinator	0:bb348c97df44	2120	* @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
lypinator	0:bb348c97df44	2121	* output channel 2 is supported by a timer instance.
lypinator	0:bb348c97df44	2122	* @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2
lypinator	0:bb348c97df44	2123	* @param TIMx Timer instance
lypinator	0:bb348c97df44	2124	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
lypinator	0:bb348c97df44	2125	*/
lypinator	0:bb348c97df44	2126	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	2127	{
lypinator	0:bb348c97df44	2128	return (uint32_t)(READ_REG(TIMx->CCR2));
lypinator	0:bb348c97df44	2129	}
lypinator	0:bb348c97df44	2130
lypinator	0:bb348c97df44	2131	/**
lypinator	0:bb348c97df44	2132	* @brief Get compare value (TIMx_CCR3) set for output channel 3.
lypinator	0:bb348c97df44	2133	* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
lypinator	0:bb348c97df44	2134	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
lypinator	0:bb348c97df44	2135	* whether or not a timer instance supports a 32 bits counter.
lypinator	0:bb348c97df44	2136	* @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
lypinator	0:bb348c97df44	2137	* output channel 3 is supported by a timer instance.
lypinator	0:bb348c97df44	2138	* @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3
lypinator	0:bb348c97df44	2139	* @param TIMx Timer instance
lypinator	0:bb348c97df44	2140	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
lypinator	0:bb348c97df44	2141	*/
lypinator	0:bb348c97df44	2142	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	2143	{
lypinator	0:bb348c97df44	2144	return (uint32_t)(READ_REG(TIMx->CCR3));
lypinator	0:bb348c97df44	2145	}
lypinator	0:bb348c97df44	2146
lypinator	0:bb348c97df44	2147	/**
lypinator	0:bb348c97df44	2148	* @brief Get compare value (TIMx_CCR4) set for output channel 4.
lypinator	0:bb348c97df44	2149	* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
lypinator	0:bb348c97df44	2150	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
lypinator	0:bb348c97df44	2151	* whether or not a timer instance supports a 32 bits counter.
lypinator	0:bb348c97df44	2152	* @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
lypinator	0:bb348c97df44	2153	* output channel 4 is supported by a timer instance.
lypinator	0:bb348c97df44	2154	* @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4
lypinator	0:bb348c97df44	2155	* @param TIMx Timer instance
lypinator	0:bb348c97df44	2156	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
lypinator	0:bb348c97df44	2157	*/
lypinator	0:bb348c97df44	2158	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	2159	{
lypinator	0:bb348c97df44	2160	return (uint32_t)(READ_REG(TIMx->CCR4));
lypinator	0:bb348c97df44	2161	}
lypinator	0:bb348c97df44	2162
lypinator	0:bb348c97df44	2163	/**
lypinator	0:bb348c97df44	2164	* @}
lypinator	0:bb348c97df44	2165	*/
lypinator	0:bb348c97df44	2166
lypinator	0:bb348c97df44	2167	/** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
lypinator	0:bb348c97df44	2168	* @{
lypinator	0:bb348c97df44	2169	*/
lypinator	0:bb348c97df44	2170	/**
lypinator	0:bb348c97df44	2171	* @brief Configure input channel.
lypinator	0:bb348c97df44	2172	* @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n
lypinator	0:bb348c97df44	2173	* CCMR1 IC1PSC LL_TIM_IC_Config\n
lypinator	0:bb348c97df44	2174	* CCMR1 IC1F LL_TIM_IC_Config\n
lypinator	0:bb348c97df44	2175	* CCMR1 CC2S LL_TIM_IC_Config\n
lypinator	0:bb348c97df44	2176	* CCMR1 IC2PSC LL_TIM_IC_Config\n
lypinator	0:bb348c97df44	2177	* CCMR1 IC2F LL_TIM_IC_Config\n
lypinator	0:bb348c97df44	2178	* CCMR2 CC3S LL_TIM_IC_Config\n
lypinator	0:bb348c97df44	2179	* CCMR2 IC3PSC LL_TIM_IC_Config\n
lypinator	0:bb348c97df44	2180	* CCMR2 IC3F LL_TIM_IC_Config\n
lypinator	0:bb348c97df44	2181	* CCMR2 CC4S LL_TIM_IC_Config\n
lypinator	0:bb348c97df44	2182	* CCMR2 IC4PSC LL_TIM_IC_Config\n
lypinator	0:bb348c97df44	2183	* CCMR2 IC4F LL_TIM_IC_Config\n
lypinator	0:bb348c97df44	2184	* CCER CC1P LL_TIM_IC_Config\n
lypinator	0:bb348c97df44	2185	* CCER CC1NP LL_TIM_IC_Config\n
lypinator	0:bb348c97df44	2186	* CCER CC2P LL_TIM_IC_Config\n
lypinator	0:bb348c97df44	2187	* CCER CC2NP LL_TIM_IC_Config\n
lypinator	0:bb348c97df44	2188	* CCER CC3P LL_TIM_IC_Config\n
lypinator	0:bb348c97df44	2189	* CCER CC3NP LL_TIM_IC_Config\n
lypinator	0:bb348c97df44	2190	* CCER CC4P LL_TIM_IC_Config\n
lypinator	0:bb348c97df44	2191	* CCER CC4NP LL_TIM_IC_Config
lypinator	0:bb348c97df44	2192	* @param TIMx Timer instance
lypinator	0:bb348c97df44	2193	* @param Channel This parameter can be one of the following values:
lypinator	0:bb348c97df44	2194	* @arg @ref LL_TIM_CHANNEL_CH1
lypinator	0:bb348c97df44	2195	* @arg @ref LL_TIM_CHANNEL_CH2
lypinator	0:bb348c97df44	2196	* @arg @ref LL_TIM_CHANNEL_CH3
lypinator	0:bb348c97df44	2197	* @arg @ref LL_TIM_CHANNEL_CH4
lypinator	0:bb348c97df44	2198	* @param Configuration This parameter must be a combination of all the following values:
lypinator	0:bb348c97df44	2199	* @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC
lypinator	0:bb348c97df44	2200	* @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
lypinator	0:bb348c97df44	2201	* @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
lypinator	0:bb348c97df44	2202	* @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE
lypinator	0:bb348c97df44	2203	* @retval None
lypinator	0:bb348c97df44	2204	*/
lypinator	0:bb348c97df44	2205	__STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
lypinator	0:bb348c97df44	2206	{
lypinator	0:bb348c97df44	2207	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
lypinator	0:bb348c97df44	2208	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
lypinator	0:bb348c97df44	2209	MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F \| TIM_CCMR1_IC1PSC \| TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
lypinator	0:bb348c97df44	2210	((Configuration >> 16U) & (TIM_CCMR1_IC1F \| TIM_CCMR1_IC1PSC \| TIM_CCMR1_CC1S)) << SHIFT_TAB_ICxx[iChannel]);
lypinator	0:bb348c97df44	2211	MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP \| TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
lypinator	0:bb348c97df44	2212	(Configuration & (TIM_CCER_CC1NP \| TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
lypinator	0:bb348c97df44	2213	}
lypinator	0:bb348c97df44	2214
lypinator	0:bb348c97df44	2215	/**
lypinator	0:bb348c97df44	2216	* @brief Set the active input.
lypinator	0:bb348c97df44	2217	* @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n
lypinator	0:bb348c97df44	2218	* CCMR1 CC2S LL_TIM_IC_SetActiveInput\n
lypinator	0:bb348c97df44	2219	* CCMR2 CC3S LL_TIM_IC_SetActiveInput\n
lypinator	0:bb348c97df44	2220	* CCMR2 CC4S LL_TIM_IC_SetActiveInput
lypinator	0:bb348c97df44	2221	* @param TIMx Timer instance
lypinator	0:bb348c97df44	2222	* @param Channel This parameter can be one of the following values:
lypinator	0:bb348c97df44	2223	* @arg @ref LL_TIM_CHANNEL_CH1
lypinator	0:bb348c97df44	2224	* @arg @ref LL_TIM_CHANNEL_CH2
lypinator	0:bb348c97df44	2225	* @arg @ref LL_TIM_CHANNEL_CH3
lypinator	0:bb348c97df44	2226	* @arg @ref LL_TIM_CHANNEL_CH4
lypinator	0:bb348c97df44	2227	* @param ICActiveInput This parameter can be one of the following values:
lypinator	0:bb348c97df44	2228	* @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
lypinator	0:bb348c97df44	2229	* @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
lypinator	0:bb348c97df44	2230	* @arg @ref LL_TIM_ACTIVEINPUT_TRC
lypinator	0:bb348c97df44	2231	* @retval None
lypinator	0:bb348c97df44	2232	*/
lypinator	0:bb348c97df44	2233	__STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
lypinator	0:bb348c97df44	2234	{
lypinator	0:bb348c97df44	2235	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
lypinator	0:bb348c97df44	2236	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
lypinator	0:bb348c97df44	2237	MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
lypinator	0:bb348c97df44	2238	}
lypinator	0:bb348c97df44	2239
lypinator	0:bb348c97df44	2240	/**
lypinator	0:bb348c97df44	2241	* @brief Get the current active input.
lypinator	0:bb348c97df44	2242	* @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n
lypinator	0:bb348c97df44	2243	* CCMR1 CC2S LL_TIM_IC_GetActiveInput\n
lypinator	0:bb348c97df44	2244	* CCMR2 CC3S LL_TIM_IC_GetActiveInput\n
lypinator	0:bb348c97df44	2245	* CCMR2 CC4S LL_TIM_IC_GetActiveInput
lypinator	0:bb348c97df44	2246	* @param TIMx Timer instance
lypinator	0:bb348c97df44	2247	* @param Channel This parameter can be one of the following values:
lypinator	0:bb348c97df44	2248	* @arg @ref LL_TIM_CHANNEL_CH1
lypinator	0:bb348c97df44	2249	* @arg @ref LL_TIM_CHANNEL_CH2
lypinator	0:bb348c97df44	2250	* @arg @ref LL_TIM_CHANNEL_CH3
lypinator	0:bb348c97df44	2251	* @arg @ref LL_TIM_CHANNEL_CH4
lypinator	0:bb348c97df44	2252	* @retval Returned value can be one of the following values:
lypinator	0:bb348c97df44	2253	* @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
lypinator	0:bb348c97df44	2254	* @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
lypinator	0:bb348c97df44	2255	* @arg @ref LL_TIM_ACTIVEINPUT_TRC
lypinator	0:bb348c97df44	2256	*/
lypinator	0:bb348c97df44	2257	__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel)
lypinator	0:bb348c97df44	2258	{
lypinator	0:bb348c97df44	2259	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
lypinator	0:bb348c97df44	2260	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
lypinator	0:bb348c97df44	2261	return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
lypinator	0:bb348c97df44	2262	}
lypinator	0:bb348c97df44	2263
lypinator	0:bb348c97df44	2264	/**
lypinator	0:bb348c97df44	2265	* @brief Set the prescaler of input channel.
lypinator	0:bb348c97df44	2266	* @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n
lypinator	0:bb348c97df44	2267	* CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n
lypinator	0:bb348c97df44	2268	* CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n
lypinator	0:bb348c97df44	2269	* CCMR2 IC4PSC LL_TIM_IC_SetPrescaler
lypinator	0:bb348c97df44	2270	* @param TIMx Timer instance
lypinator	0:bb348c97df44	2271	* @param Channel This parameter can be one of the following values:
lypinator	0:bb348c97df44	2272	* @arg @ref LL_TIM_CHANNEL_CH1
lypinator	0:bb348c97df44	2273	* @arg @ref LL_TIM_CHANNEL_CH2
lypinator	0:bb348c97df44	2274	* @arg @ref LL_TIM_CHANNEL_CH3
lypinator	0:bb348c97df44	2275	* @arg @ref LL_TIM_CHANNEL_CH4
lypinator	0:bb348c97df44	2276	* @param ICPrescaler This parameter can be one of the following values:
lypinator	0:bb348c97df44	2277	* @arg @ref LL_TIM_ICPSC_DIV1
lypinator	0:bb348c97df44	2278	* @arg @ref LL_TIM_ICPSC_DIV2
lypinator	0:bb348c97df44	2279	* @arg @ref LL_TIM_ICPSC_DIV4
lypinator	0:bb348c97df44	2280	* @arg @ref LL_TIM_ICPSC_DIV8
lypinator	0:bb348c97df44	2281	* @retval None
lypinator	0:bb348c97df44	2282	*/
lypinator	0:bb348c97df44	2283	__STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
lypinator	0:bb348c97df44	2284	{
lypinator	0:bb348c97df44	2285	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
lypinator	0:bb348c97df44	2286	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
lypinator	0:bb348c97df44	2287	MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
lypinator	0:bb348c97df44	2288	}
lypinator	0:bb348c97df44	2289
lypinator	0:bb348c97df44	2290	/**
lypinator	0:bb348c97df44	2291	* @brief Get the current prescaler value acting on an input channel.
lypinator	0:bb348c97df44	2292	* @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n
lypinator	0:bb348c97df44	2293	* CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n
lypinator	0:bb348c97df44	2294	* CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n
lypinator	0:bb348c97df44	2295	* CCMR2 IC4PSC LL_TIM_IC_GetPrescaler
lypinator	0:bb348c97df44	2296	* @param TIMx Timer instance
lypinator	0:bb348c97df44	2297	* @param Channel This parameter can be one of the following values:
lypinator	0:bb348c97df44	2298	* @arg @ref LL_TIM_CHANNEL_CH1
lypinator	0:bb348c97df44	2299	* @arg @ref LL_TIM_CHANNEL_CH2
lypinator	0:bb348c97df44	2300	* @arg @ref LL_TIM_CHANNEL_CH3
lypinator	0:bb348c97df44	2301	* @arg @ref LL_TIM_CHANNEL_CH4
lypinator	0:bb348c97df44	2302	* @retval Returned value can be one of the following values:
lypinator	0:bb348c97df44	2303	* @arg @ref LL_TIM_ICPSC_DIV1
lypinator	0:bb348c97df44	2304	* @arg @ref LL_TIM_ICPSC_DIV2
lypinator	0:bb348c97df44	2305	* @arg @ref LL_TIM_ICPSC_DIV4
lypinator	0:bb348c97df44	2306	* @arg @ref LL_TIM_ICPSC_DIV8
lypinator	0:bb348c97df44	2307	*/
lypinator	0:bb348c97df44	2308	__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel)
lypinator	0:bb348c97df44	2309	{
lypinator	0:bb348c97df44	2310	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
lypinator	0:bb348c97df44	2311	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
lypinator	0:bb348c97df44	2312	return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
lypinator	0:bb348c97df44	2313	}
lypinator	0:bb348c97df44	2314
lypinator	0:bb348c97df44	2315	/**
lypinator	0:bb348c97df44	2316	* @brief Set the input filter duration.
lypinator	0:bb348c97df44	2317	* @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n
lypinator	0:bb348c97df44	2318	* CCMR1 IC2F LL_TIM_IC_SetFilter\n
lypinator	0:bb348c97df44	2319	* CCMR2 IC3F LL_TIM_IC_SetFilter\n
lypinator	0:bb348c97df44	2320	* CCMR2 IC4F LL_TIM_IC_SetFilter
lypinator	0:bb348c97df44	2321	* @param TIMx Timer instance
lypinator	0:bb348c97df44	2322	* @param Channel This parameter can be one of the following values:
lypinator	0:bb348c97df44	2323	* @arg @ref LL_TIM_CHANNEL_CH1
lypinator	0:bb348c97df44	2324	* @arg @ref LL_TIM_CHANNEL_CH2
lypinator	0:bb348c97df44	2325	* @arg @ref LL_TIM_CHANNEL_CH3
lypinator	0:bb348c97df44	2326	* @arg @ref LL_TIM_CHANNEL_CH4
lypinator	0:bb348c97df44	2327	* @param ICFilter This parameter can be one of the following values:
lypinator	0:bb348c97df44	2328	* @arg @ref LL_TIM_IC_FILTER_FDIV1
lypinator	0:bb348c97df44	2329	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
lypinator	0:bb348c97df44	2330	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
lypinator	0:bb348c97df44	2331	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
lypinator	0:bb348c97df44	2332	* @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
lypinator	0:bb348c97df44	2333	* @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
lypinator	0:bb348c97df44	2334	* @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
lypinator	0:bb348c97df44	2335	* @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
lypinator	0:bb348c97df44	2336	* @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
lypinator	0:bb348c97df44	2337	* @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
lypinator	0:bb348c97df44	2338	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
lypinator	0:bb348c97df44	2339	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
lypinator	0:bb348c97df44	2340	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
lypinator	0:bb348c97df44	2341	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
lypinator	0:bb348c97df44	2342	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
lypinator	0:bb348c97df44	2343	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
lypinator	0:bb348c97df44	2344	* @retval None
lypinator	0:bb348c97df44	2345	*/
lypinator	0:bb348c97df44	2346	__STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
lypinator	0:bb348c97df44	2347	{
lypinator	0:bb348c97df44	2348	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
lypinator	0:bb348c97df44	2349	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
lypinator	0:bb348c97df44	2350	MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
lypinator	0:bb348c97df44	2351	}
lypinator	0:bb348c97df44	2352
lypinator	0:bb348c97df44	2353	/**
lypinator	0:bb348c97df44	2354	* @brief Get the input filter duration.
lypinator	0:bb348c97df44	2355	* @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n
lypinator	0:bb348c97df44	2356	* CCMR1 IC2F LL_TIM_IC_GetFilter\n
lypinator	0:bb348c97df44	2357	* CCMR2 IC3F LL_TIM_IC_GetFilter\n
lypinator	0:bb348c97df44	2358	* CCMR2 IC4F LL_TIM_IC_GetFilter
lypinator	0:bb348c97df44	2359	* @param TIMx Timer instance
lypinator	0:bb348c97df44	2360	* @param Channel This parameter can be one of the following values:
lypinator	0:bb348c97df44	2361	* @arg @ref LL_TIM_CHANNEL_CH1
lypinator	0:bb348c97df44	2362	* @arg @ref LL_TIM_CHANNEL_CH2
lypinator	0:bb348c97df44	2363	* @arg @ref LL_TIM_CHANNEL_CH3
lypinator	0:bb348c97df44	2364	* @arg @ref LL_TIM_CHANNEL_CH4
lypinator	0:bb348c97df44	2365	* @retval Returned value can be one of the following values:
lypinator	0:bb348c97df44	2366	* @arg @ref LL_TIM_IC_FILTER_FDIV1
lypinator	0:bb348c97df44	2367	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
lypinator	0:bb348c97df44	2368	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
lypinator	0:bb348c97df44	2369	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
lypinator	0:bb348c97df44	2370	* @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
lypinator	0:bb348c97df44	2371	* @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
lypinator	0:bb348c97df44	2372	* @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
lypinator	0:bb348c97df44	2373	* @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
lypinator	0:bb348c97df44	2374	* @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
lypinator	0:bb348c97df44	2375	* @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
lypinator	0:bb348c97df44	2376	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
lypinator	0:bb348c97df44	2377	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
lypinator	0:bb348c97df44	2378	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
lypinator	0:bb348c97df44	2379	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
lypinator	0:bb348c97df44	2380	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
lypinator	0:bb348c97df44	2381	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
lypinator	0:bb348c97df44	2382	*/
lypinator	0:bb348c97df44	2383	__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel)
lypinator	0:bb348c97df44	2384	{
lypinator	0:bb348c97df44	2385	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
lypinator	0:bb348c97df44	2386	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
lypinator	0:bb348c97df44	2387	return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
lypinator	0:bb348c97df44	2388	}
lypinator	0:bb348c97df44	2389
lypinator	0:bb348c97df44	2390	/**
lypinator	0:bb348c97df44	2391	* @brief Set the input channel polarity.
lypinator	0:bb348c97df44	2392	* @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n
lypinator	0:bb348c97df44	2393	* CCER CC1NP LL_TIM_IC_SetPolarity\n
lypinator	0:bb348c97df44	2394	* CCER CC2P LL_TIM_IC_SetPolarity\n
lypinator	0:bb348c97df44	2395	* CCER CC2NP LL_TIM_IC_SetPolarity\n
lypinator	0:bb348c97df44	2396	* CCER CC3P LL_TIM_IC_SetPolarity\n
lypinator	0:bb348c97df44	2397	* CCER CC3NP LL_TIM_IC_SetPolarity\n
lypinator	0:bb348c97df44	2398	* CCER CC4P LL_TIM_IC_SetPolarity\n
lypinator	0:bb348c97df44	2399	* CCER CC4NP LL_TIM_IC_SetPolarity
lypinator	0:bb348c97df44	2400	* @param TIMx Timer instance
lypinator	0:bb348c97df44	2401	* @param Channel This parameter can be one of the following values:
lypinator	0:bb348c97df44	2402	* @arg @ref LL_TIM_CHANNEL_CH1
lypinator	0:bb348c97df44	2403	* @arg @ref LL_TIM_CHANNEL_CH2
lypinator	0:bb348c97df44	2404	* @arg @ref LL_TIM_CHANNEL_CH3
lypinator	0:bb348c97df44	2405	* @arg @ref LL_TIM_CHANNEL_CH4
lypinator	0:bb348c97df44	2406	* @param ICPolarity This parameter can be one of the following values:
lypinator	0:bb348c97df44	2407	* @arg @ref LL_TIM_IC_POLARITY_RISING
lypinator	0:bb348c97df44	2408	* @arg @ref LL_TIM_IC_POLARITY_FALLING
lypinator	0:bb348c97df44	2409	* @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
lypinator	0:bb348c97df44	2410	* @retval None
lypinator	0:bb348c97df44	2411	*/
lypinator	0:bb348c97df44	2412	__STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
lypinator	0:bb348c97df44	2413	{
lypinator	0:bb348c97df44	2414	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
lypinator	0:bb348c97df44	2415	MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP \| TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
lypinator	0:bb348c97df44	2416	ICPolarity << SHIFT_TAB_CCxP[iChannel]);
lypinator	0:bb348c97df44	2417	}
lypinator	0:bb348c97df44	2418
lypinator	0:bb348c97df44	2419	/**
lypinator	0:bb348c97df44	2420	* @brief Get the current input channel polarity.
lypinator	0:bb348c97df44	2421	* @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n
lypinator	0:bb348c97df44	2422	* CCER CC1NP LL_TIM_IC_GetPolarity\n
lypinator	0:bb348c97df44	2423	* CCER CC2P LL_TIM_IC_GetPolarity\n
lypinator	0:bb348c97df44	2424	* CCER CC2NP LL_TIM_IC_GetPolarity\n
lypinator	0:bb348c97df44	2425	* CCER CC3P LL_TIM_IC_GetPolarity\n
lypinator	0:bb348c97df44	2426	* CCER CC3NP LL_TIM_IC_GetPolarity\n
lypinator	0:bb348c97df44	2427	* CCER CC4P LL_TIM_IC_GetPolarity\n
lypinator	0:bb348c97df44	2428	* CCER CC4NP LL_TIM_IC_GetPolarity
lypinator	0:bb348c97df44	2429	* @param TIMx Timer instance
lypinator	0:bb348c97df44	2430	* @param Channel This parameter can be one of the following values:
lypinator	0:bb348c97df44	2431	* @arg @ref LL_TIM_CHANNEL_CH1
lypinator	0:bb348c97df44	2432	* @arg @ref LL_TIM_CHANNEL_CH2
lypinator	0:bb348c97df44	2433	* @arg @ref LL_TIM_CHANNEL_CH3
lypinator	0:bb348c97df44	2434	* @arg @ref LL_TIM_CHANNEL_CH4
lypinator	0:bb348c97df44	2435	* @retval Returned value can be one of the following values:
lypinator	0:bb348c97df44	2436	* @arg @ref LL_TIM_IC_POLARITY_RISING
lypinator	0:bb348c97df44	2437	* @arg @ref LL_TIM_IC_POLARITY_FALLING
lypinator	0:bb348c97df44	2438	* @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
lypinator	0:bb348c97df44	2439	*/
lypinator	0:bb348c97df44	2440	__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
lypinator	0:bb348c97df44	2441	{
lypinator	0:bb348c97df44	2442	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
lypinator	0:bb348c97df44	2443	return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP \| TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
lypinator	0:bb348c97df44	2444	SHIFT_TAB_CCxP[iChannel]);
lypinator	0:bb348c97df44	2445	}
lypinator	0:bb348c97df44	2446
lypinator	0:bb348c97df44	2447	/**
lypinator	0:bb348c97df44	2448	* @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).
lypinator	0:bb348c97df44	2449	* @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
lypinator	0:bb348c97df44	2450	* a timer instance provides an XOR input.
lypinator	0:bb348c97df44	2451	* @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination
lypinator	0:bb348c97df44	2452	* @param TIMx Timer instance
lypinator	0:bb348c97df44	2453	* @retval None
lypinator	0:bb348c97df44	2454	*/
lypinator	0:bb348c97df44	2455	__STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	2456	{
lypinator	0:bb348c97df44	2457	SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
lypinator	0:bb348c97df44	2458	}
lypinator	0:bb348c97df44	2459
lypinator	0:bb348c97df44	2460	/**
lypinator	0:bb348c97df44	2461	* @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.
lypinator	0:bb348c97df44	2462	* @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
lypinator	0:bb348c97df44	2463	* a timer instance provides an XOR input.
lypinator	0:bb348c97df44	2464	* @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination
lypinator	0:bb348c97df44	2465	* @param TIMx Timer instance
lypinator	0:bb348c97df44	2466	* @retval None
lypinator	0:bb348c97df44	2467	*/
lypinator	0:bb348c97df44	2468	__STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	2469	{
lypinator	0:bb348c97df44	2470	CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
lypinator	0:bb348c97df44	2471	}
lypinator	0:bb348c97df44	2472
lypinator	0:bb348c97df44	2473	/**
lypinator	0:bb348c97df44	2474	* @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
lypinator	0:bb348c97df44	2475	* @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
lypinator	0:bb348c97df44	2476	* a timer instance provides an XOR input.
lypinator	0:bb348c97df44	2477	* @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination
lypinator	0:bb348c97df44	2478	* @param TIMx Timer instance
lypinator	0:bb348c97df44	2479	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	2480	*/
lypinator	0:bb348c97df44	2481	__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	2482	{
lypinator	0:bb348c97df44	2483	return (READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S));
lypinator	0:bb348c97df44	2484	}
lypinator	0:bb348c97df44	2485
lypinator	0:bb348c97df44	2486	/**
lypinator	0:bb348c97df44	2487	* @brief Get captured value for input channel 1.
lypinator	0:bb348c97df44	2488	* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
lypinator	0:bb348c97df44	2489	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
lypinator	0:bb348c97df44	2490	* whether or not a timer instance supports a 32 bits counter.
lypinator	0:bb348c97df44	2491	* @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
lypinator	0:bb348c97df44	2492	* input channel 1 is supported by a timer instance.
lypinator	0:bb348c97df44	2493	* @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1
lypinator	0:bb348c97df44	2494	* @param TIMx Timer instance
lypinator	0:bb348c97df44	2495	* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
lypinator	0:bb348c97df44	2496	*/
lypinator	0:bb348c97df44	2497	__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	2498	{
lypinator	0:bb348c97df44	2499	return (uint32_t)(READ_REG(TIMx->CCR1));
lypinator	0:bb348c97df44	2500	}
lypinator	0:bb348c97df44	2501
lypinator	0:bb348c97df44	2502	/**
lypinator	0:bb348c97df44	2503	* @brief Get captured value for input channel 2.
lypinator	0:bb348c97df44	2504	* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
lypinator	0:bb348c97df44	2505	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
lypinator	0:bb348c97df44	2506	* whether or not a timer instance supports a 32 bits counter.
lypinator	0:bb348c97df44	2507	* @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
lypinator	0:bb348c97df44	2508	* input channel 2 is supported by a timer instance.
lypinator	0:bb348c97df44	2509	* @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2
lypinator	0:bb348c97df44	2510	* @param TIMx Timer instance
lypinator	0:bb348c97df44	2511	* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
lypinator	0:bb348c97df44	2512	*/
lypinator	0:bb348c97df44	2513	__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	2514	{
lypinator	0:bb348c97df44	2515	return (uint32_t)(READ_REG(TIMx->CCR2));
lypinator	0:bb348c97df44	2516	}
lypinator	0:bb348c97df44	2517
lypinator	0:bb348c97df44	2518	/**
lypinator	0:bb348c97df44	2519	* @brief Get captured value for input channel 3.
lypinator	0:bb348c97df44	2520	* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
lypinator	0:bb348c97df44	2521	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
lypinator	0:bb348c97df44	2522	* whether or not a timer instance supports a 32 bits counter.
lypinator	0:bb348c97df44	2523	* @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
lypinator	0:bb348c97df44	2524	* input channel 3 is supported by a timer instance.
lypinator	0:bb348c97df44	2525	* @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3
lypinator	0:bb348c97df44	2526	* @param TIMx Timer instance
lypinator	0:bb348c97df44	2527	* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
lypinator	0:bb348c97df44	2528	*/
lypinator	0:bb348c97df44	2529	__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	2530	{
lypinator	0:bb348c97df44	2531	return (uint32_t)(READ_REG(TIMx->CCR3));
lypinator	0:bb348c97df44	2532	}
lypinator	0:bb348c97df44	2533
lypinator	0:bb348c97df44	2534	/**
lypinator	0:bb348c97df44	2535	* @brief Get captured value for input channel 4.
lypinator	0:bb348c97df44	2536	* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
lypinator	0:bb348c97df44	2537	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
lypinator	0:bb348c97df44	2538	* whether or not a timer instance supports a 32 bits counter.
lypinator	0:bb348c97df44	2539	* @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
lypinator	0:bb348c97df44	2540	* input channel 4 is supported by a timer instance.
lypinator	0:bb348c97df44	2541	* @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4
lypinator	0:bb348c97df44	2542	* @param TIMx Timer instance
lypinator	0:bb348c97df44	2543	* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
lypinator	0:bb348c97df44	2544	*/
lypinator	0:bb348c97df44	2545	__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	2546	{
lypinator	0:bb348c97df44	2547	return (uint32_t)(READ_REG(TIMx->CCR4));
lypinator	0:bb348c97df44	2548	}
lypinator	0:bb348c97df44	2549
lypinator	0:bb348c97df44	2550	/**
lypinator	0:bb348c97df44	2551	* @}
lypinator	0:bb348c97df44	2552	*/
lypinator	0:bb348c97df44	2553
lypinator	0:bb348c97df44	2554	/** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
lypinator	0:bb348c97df44	2555	* @{
lypinator	0:bb348c97df44	2556	*/
lypinator	0:bb348c97df44	2557	/**
lypinator	0:bb348c97df44	2558	* @brief Enable external clock mode 2.
lypinator	0:bb348c97df44	2559	* @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
lypinator	0:bb348c97df44	2560	* @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
lypinator	0:bb348c97df44	2561	* whether or not a timer instance supports external clock mode2.
lypinator	0:bb348c97df44	2562	* @rmtoll SMCR ECE LL_TIM_EnableExternalClock
lypinator	0:bb348c97df44	2563	* @param TIMx Timer instance
lypinator	0:bb348c97df44	2564	* @retval None
lypinator	0:bb348c97df44	2565	*/
lypinator	0:bb348c97df44	2566	__STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	2567	{
lypinator	0:bb348c97df44	2568	SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
lypinator	0:bb348c97df44	2569	}
lypinator	0:bb348c97df44	2570
lypinator	0:bb348c97df44	2571	/**
lypinator	0:bb348c97df44	2572	* @brief Disable external clock mode 2.
lypinator	0:bb348c97df44	2573	* @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
lypinator	0:bb348c97df44	2574	* whether or not a timer instance supports external clock mode2.
lypinator	0:bb348c97df44	2575	* @rmtoll SMCR ECE LL_TIM_DisableExternalClock
lypinator	0:bb348c97df44	2576	* @param TIMx Timer instance
lypinator	0:bb348c97df44	2577	* @retval None
lypinator	0:bb348c97df44	2578	*/
lypinator	0:bb348c97df44	2579	__STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	2580	{
lypinator	0:bb348c97df44	2581	CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
lypinator	0:bb348c97df44	2582	}
lypinator	0:bb348c97df44	2583
lypinator	0:bb348c97df44	2584	/**
lypinator	0:bb348c97df44	2585	* @brief Indicate whether external clock mode 2 is enabled.
lypinator	0:bb348c97df44	2586	* @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
lypinator	0:bb348c97df44	2587	* whether or not a timer instance supports external clock mode2.
lypinator	0:bb348c97df44	2588	* @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock
lypinator	0:bb348c97df44	2589	* @param TIMx Timer instance
lypinator	0:bb348c97df44	2590	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	2591	*/
lypinator	0:bb348c97df44	2592	__STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	2593	{
lypinator	0:bb348c97df44	2594	return (READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE));
lypinator	0:bb348c97df44	2595	}
lypinator	0:bb348c97df44	2596
lypinator	0:bb348c97df44	2597	/**
lypinator	0:bb348c97df44	2598	* @brief Set the clock source of the counter clock.
lypinator	0:bb348c97df44	2599	* @note when selected clock source is external clock mode 1, the timer input
lypinator	0:bb348c97df44	2600	* the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
lypinator	0:bb348c97df44	2601	* function. This timer input must be configured by calling
lypinator	0:bb348c97df44	2602	* the @ref LL_TIM_IC_Config() function.
lypinator	0:bb348c97df44	2603	* @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
lypinator	0:bb348c97df44	2604	* whether or not a timer instance supports external clock mode1.
lypinator	0:bb348c97df44	2605	* @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
lypinator	0:bb348c97df44	2606	* whether or not a timer instance supports external clock mode2.
lypinator	0:bb348c97df44	2607	* @rmtoll SMCR SMS LL_TIM_SetClockSource\n
lypinator	0:bb348c97df44	2608	* SMCR ECE LL_TIM_SetClockSource
lypinator	0:bb348c97df44	2609	* @param TIMx Timer instance
lypinator	0:bb348c97df44	2610	* @param ClockSource This parameter can be one of the following values:
lypinator	0:bb348c97df44	2611	* @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
lypinator	0:bb348c97df44	2612	* @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
lypinator	0:bb348c97df44	2613	* @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
lypinator	0:bb348c97df44	2614	* @retval None
lypinator	0:bb348c97df44	2615	*/
lypinator	0:bb348c97df44	2616	__STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource)
lypinator	0:bb348c97df44	2617	{
lypinator	0:bb348c97df44	2618	MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS \| TIM_SMCR_ECE, ClockSource);
lypinator	0:bb348c97df44	2619	}
lypinator	0:bb348c97df44	2620
lypinator	0:bb348c97df44	2621	/**
lypinator	0:bb348c97df44	2622	* @brief Set the encoder interface mode.
lypinator	0:bb348c97df44	2623	* @note Macro @ref IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
lypinator	0:bb348c97df44	2624	* whether or not a timer instance supports the encoder mode.
lypinator	0:bb348c97df44	2625	* @rmtoll SMCR SMS LL_TIM_SetEncoderMode
lypinator	0:bb348c97df44	2626	* @param TIMx Timer instance
lypinator	0:bb348c97df44	2627	* @param EncoderMode This parameter can be one of the following values:
lypinator	0:bb348c97df44	2628	* @arg @ref LL_TIM_ENCODERMODE_X2_TI1
lypinator	0:bb348c97df44	2629	* @arg @ref LL_TIM_ENCODERMODE_X2_TI2
lypinator	0:bb348c97df44	2630	* @arg @ref LL_TIM_ENCODERMODE_X4_TI12
lypinator	0:bb348c97df44	2631	* @retval None
lypinator	0:bb348c97df44	2632	*/
lypinator	0:bb348c97df44	2633	__STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode)
lypinator	0:bb348c97df44	2634	{
lypinator	0:bb348c97df44	2635	MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
lypinator	0:bb348c97df44	2636	}
lypinator	0:bb348c97df44	2637
lypinator	0:bb348c97df44	2638	/**
lypinator	0:bb348c97df44	2639	* @}
lypinator	0:bb348c97df44	2640	*/
lypinator	0:bb348c97df44	2641
lypinator	0:bb348c97df44	2642	/** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration
lypinator	0:bb348c97df44	2643	* @{
lypinator	0:bb348c97df44	2644	*/
lypinator	0:bb348c97df44	2645	/**
lypinator	0:bb348c97df44	2646	* @brief Set the trigger output (TRGO) used for timer synchronization .
lypinator	0:bb348c97df44	2647	* @note Macro @ref IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
lypinator	0:bb348c97df44	2648	* whether or not a timer instance can operate as a master timer.
lypinator	0:bb348c97df44	2649	* @rmtoll CR2 MMS LL_TIM_SetTriggerOutput
lypinator	0:bb348c97df44	2650	* @param TIMx Timer instance
lypinator	0:bb348c97df44	2651	* @param TimerSynchronization This parameter can be one of the following values:
lypinator	0:bb348c97df44	2652	* @arg @ref LL_TIM_TRGO_RESET
lypinator	0:bb348c97df44	2653	* @arg @ref LL_TIM_TRGO_ENABLE
lypinator	0:bb348c97df44	2654	* @arg @ref LL_TIM_TRGO_UPDATE
lypinator	0:bb348c97df44	2655	* @arg @ref LL_TIM_TRGO_CC1IF
lypinator	0:bb348c97df44	2656	* @arg @ref LL_TIM_TRGO_OC1REF
lypinator	0:bb348c97df44	2657	* @arg @ref LL_TIM_TRGO_OC2REF
lypinator	0:bb348c97df44	2658	* @arg @ref LL_TIM_TRGO_OC3REF
lypinator	0:bb348c97df44	2659	* @arg @ref LL_TIM_TRGO_OC4REF
lypinator	0:bb348c97df44	2660	* @retval None
lypinator	0:bb348c97df44	2661	*/
lypinator	0:bb348c97df44	2662	__STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
lypinator	0:bb348c97df44	2663	{
lypinator	0:bb348c97df44	2664	MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
lypinator	0:bb348c97df44	2665	}
lypinator	0:bb348c97df44	2666
lypinator	0:bb348c97df44	2667	/**
lypinator	0:bb348c97df44	2668	* @brief Set the synchronization mode of a slave timer.
lypinator	0:bb348c97df44	2669	* @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
lypinator	0:bb348c97df44	2670	* a timer instance can operate as a slave timer.
lypinator	0:bb348c97df44	2671	* @rmtoll SMCR SMS LL_TIM_SetSlaveMode
lypinator	0:bb348c97df44	2672	* @param TIMx Timer instance
lypinator	0:bb348c97df44	2673	* @param SlaveMode This parameter can be one of the following values:
lypinator	0:bb348c97df44	2674	* @arg @ref LL_TIM_SLAVEMODE_DISABLED
lypinator	0:bb348c97df44	2675	* @arg @ref LL_TIM_SLAVEMODE_RESET
lypinator	0:bb348c97df44	2676	* @arg @ref LL_TIM_SLAVEMODE_GATED
lypinator	0:bb348c97df44	2677	* @arg @ref LL_TIM_SLAVEMODE_TRIGGER
lypinator	0:bb348c97df44	2678	* @retval None
lypinator	0:bb348c97df44	2679	*/
lypinator	0:bb348c97df44	2680	__STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
lypinator	0:bb348c97df44	2681	{
lypinator	0:bb348c97df44	2682	MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
lypinator	0:bb348c97df44	2683	}
lypinator	0:bb348c97df44	2684
lypinator	0:bb348c97df44	2685	/**
lypinator	0:bb348c97df44	2686	* @brief Set the selects the trigger input to be used to synchronize the counter.
lypinator	0:bb348c97df44	2687	* @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
lypinator	0:bb348c97df44	2688	* a timer instance can operate as a slave timer.
lypinator	0:bb348c97df44	2689	* @rmtoll SMCR TS LL_TIM_SetTriggerInput
lypinator	0:bb348c97df44	2690	* @param TIMx Timer instance
lypinator	0:bb348c97df44	2691	* @param TriggerInput This parameter can be one of the following values:
lypinator	0:bb348c97df44	2692	* @arg @ref LL_TIM_TS_ITR0
lypinator	0:bb348c97df44	2693	* @arg @ref LL_TIM_TS_ITR1
lypinator	0:bb348c97df44	2694	* @arg @ref LL_TIM_TS_ITR2
lypinator	0:bb348c97df44	2695	* @arg @ref LL_TIM_TS_ITR3
lypinator	0:bb348c97df44	2696	* @arg @ref LL_TIM_TS_TI1F_ED
lypinator	0:bb348c97df44	2697	* @arg @ref LL_TIM_TS_TI1FP1
lypinator	0:bb348c97df44	2698	* @arg @ref LL_TIM_TS_TI2FP2
lypinator	0:bb348c97df44	2699	* @arg @ref LL_TIM_TS_ETRF
lypinator	0:bb348c97df44	2700	* @retval None
lypinator	0:bb348c97df44	2701	*/
lypinator	0:bb348c97df44	2702	__STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput)
lypinator	0:bb348c97df44	2703	{
lypinator	0:bb348c97df44	2704	MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
lypinator	0:bb348c97df44	2705	}
lypinator	0:bb348c97df44	2706
lypinator	0:bb348c97df44	2707	/**
lypinator	0:bb348c97df44	2708	* @brief Enable the Master/Slave mode.
lypinator	0:bb348c97df44	2709	* @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
lypinator	0:bb348c97df44	2710	* a timer instance can operate as a slave timer.
lypinator	0:bb348c97df44	2711	* @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode
lypinator	0:bb348c97df44	2712	* @param TIMx Timer instance
lypinator	0:bb348c97df44	2713	* @retval None
lypinator	0:bb348c97df44	2714	*/
lypinator	0:bb348c97df44	2715	__STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	2716	{
lypinator	0:bb348c97df44	2717	SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
lypinator	0:bb348c97df44	2718	}
lypinator	0:bb348c97df44	2719
lypinator	0:bb348c97df44	2720	/**
lypinator	0:bb348c97df44	2721	* @brief Disable the Master/Slave mode.
lypinator	0:bb348c97df44	2722	* @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
lypinator	0:bb348c97df44	2723	* a timer instance can operate as a slave timer.
lypinator	0:bb348c97df44	2724	* @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode
lypinator	0:bb348c97df44	2725	* @param TIMx Timer instance
lypinator	0:bb348c97df44	2726	* @retval None
lypinator	0:bb348c97df44	2727	*/
lypinator	0:bb348c97df44	2728	__STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	2729	{
lypinator	0:bb348c97df44	2730	CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
lypinator	0:bb348c97df44	2731	}
lypinator	0:bb348c97df44	2732
lypinator	0:bb348c97df44	2733	/**
lypinator	0:bb348c97df44	2734	* @brief Indicates whether the Master/Slave mode is enabled.
lypinator	0:bb348c97df44	2735	* @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
lypinator	0:bb348c97df44	2736	* a timer instance can operate as a slave timer.
lypinator	0:bb348c97df44	2737	* @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode
lypinator	0:bb348c97df44	2738	* @param TIMx Timer instance
lypinator	0:bb348c97df44	2739	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	2740	*/
lypinator	0:bb348c97df44	2741	__STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	2742	{
lypinator	0:bb348c97df44	2743	return (READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM));
lypinator	0:bb348c97df44	2744	}
lypinator	0:bb348c97df44	2745
lypinator	0:bb348c97df44	2746	/**
lypinator	0:bb348c97df44	2747	* @brief Configure the external trigger (ETR) input.
lypinator	0:bb348c97df44	2748	* @note Macro @ref IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
lypinator	0:bb348c97df44	2749	* a timer instance provides an external trigger input.
lypinator	0:bb348c97df44	2750	* @rmtoll SMCR ETP LL_TIM_ConfigETR\n
lypinator	0:bb348c97df44	2751	* SMCR ETPS LL_TIM_ConfigETR\n
lypinator	0:bb348c97df44	2752	* SMCR ETF LL_TIM_ConfigETR
lypinator	0:bb348c97df44	2753	* @param TIMx Timer instance
lypinator	0:bb348c97df44	2754	* @param ETRPolarity This parameter can be one of the following values:
lypinator	0:bb348c97df44	2755	* @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
lypinator	0:bb348c97df44	2756	* @arg @ref LL_TIM_ETR_POLARITY_INVERTED
lypinator	0:bb348c97df44	2757	* @param ETRPrescaler This parameter can be one of the following values:
lypinator	0:bb348c97df44	2758	* @arg @ref LL_TIM_ETR_PRESCALER_DIV1
lypinator	0:bb348c97df44	2759	* @arg @ref LL_TIM_ETR_PRESCALER_DIV2
lypinator	0:bb348c97df44	2760	* @arg @ref LL_TIM_ETR_PRESCALER_DIV4
lypinator	0:bb348c97df44	2761	* @arg @ref LL_TIM_ETR_PRESCALER_DIV8
lypinator	0:bb348c97df44	2762	* @param ETRFilter This parameter can be one of the following values:
lypinator	0:bb348c97df44	2763	* @arg @ref LL_TIM_ETR_FILTER_FDIV1
lypinator	0:bb348c97df44	2764	* @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
lypinator	0:bb348c97df44	2765	* @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
lypinator	0:bb348c97df44	2766	* @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
lypinator	0:bb348c97df44	2767	* @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
lypinator	0:bb348c97df44	2768	* @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
lypinator	0:bb348c97df44	2769	* @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
lypinator	0:bb348c97df44	2770	* @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
lypinator	0:bb348c97df44	2771	* @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
lypinator	0:bb348c97df44	2772	* @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
lypinator	0:bb348c97df44	2773	* @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
lypinator	0:bb348c97df44	2774	* @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
lypinator	0:bb348c97df44	2775	* @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
lypinator	0:bb348c97df44	2776	* @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
lypinator	0:bb348c97df44	2777	* @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
lypinator	0:bb348c97df44	2778	* @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
lypinator	0:bb348c97df44	2779	* @retval None
lypinator	0:bb348c97df44	2780	*/
lypinator	0:bb348c97df44	2781	__STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler,
lypinator	0:bb348c97df44	2782	uint32_t ETRFilter)
lypinator	0:bb348c97df44	2783	{
lypinator	0:bb348c97df44	2784	MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP \| TIM_SMCR_ETPS \| TIM_SMCR_ETF, ETRPolarity \| ETRPrescaler \| ETRFilter);
lypinator	0:bb348c97df44	2785	}
lypinator	0:bb348c97df44	2786
lypinator	0:bb348c97df44	2787	/**
lypinator	0:bb348c97df44	2788	* @}
lypinator	0:bb348c97df44	2789	*/
lypinator	0:bb348c97df44	2790
lypinator	0:bb348c97df44	2791	/** @defgroup TIM_LL_EF_Break_Function Break function configuration
lypinator	0:bb348c97df44	2792	* @{
lypinator	0:bb348c97df44	2793	*/
lypinator	0:bb348c97df44	2794	/**
lypinator	0:bb348c97df44	2795	* @brief Enable the break function.
lypinator	0:bb348c97df44	2796	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
lypinator	0:bb348c97df44	2797	* a timer instance provides a break input.
lypinator	0:bb348c97df44	2798	* @rmtoll BDTR BKE LL_TIM_EnableBRK
lypinator	0:bb348c97df44	2799	* @param TIMx Timer instance
lypinator	0:bb348c97df44	2800	* @retval None
lypinator	0:bb348c97df44	2801	*/
lypinator	0:bb348c97df44	2802	__STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	2803	{
lypinator	0:bb348c97df44	2804	SET_BIT(TIMx->BDTR, TIM_BDTR_BKE);
lypinator	0:bb348c97df44	2805	}
lypinator	0:bb348c97df44	2806
lypinator	0:bb348c97df44	2807	/**
lypinator	0:bb348c97df44	2808	* @brief Disable the break function.
lypinator	0:bb348c97df44	2809	* @rmtoll BDTR BKE LL_TIM_DisableBRK
lypinator	0:bb348c97df44	2810	* @param TIMx Timer instance
lypinator	0:bb348c97df44	2811	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
lypinator	0:bb348c97df44	2812	* a timer instance provides a break input.
lypinator	0:bb348c97df44	2813	* @retval None
lypinator	0:bb348c97df44	2814	*/
lypinator	0:bb348c97df44	2815	__STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	2816	{
lypinator	0:bb348c97df44	2817	CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
lypinator	0:bb348c97df44	2818	}
lypinator	0:bb348c97df44	2819
lypinator	0:bb348c97df44	2820	/**
lypinator	0:bb348c97df44	2821	* @brief Configure the break input.
lypinator	0:bb348c97df44	2822	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
lypinator	0:bb348c97df44	2823	* a timer instance provides a break input.
lypinator	0:bb348c97df44	2824	* @rmtoll BDTR BKP LL_TIM_ConfigBRK
lypinator	0:bb348c97df44	2825	* @param TIMx Timer instance
lypinator	0:bb348c97df44	2826	* @param BreakPolarity This parameter can be one of the following values:
lypinator	0:bb348c97df44	2827	* @arg @ref LL_TIM_BREAK_POLARITY_LOW
lypinator	0:bb348c97df44	2828	* @arg @ref LL_TIM_BREAK_POLARITY_HIGH
lypinator	0:bb348c97df44	2829	* @retval None
lypinator	0:bb348c97df44	2830	*/
lypinator	0:bb348c97df44	2831	__STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity)
lypinator	0:bb348c97df44	2832	{
lypinator	0:bb348c97df44	2833	MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP, BreakPolarity);
lypinator	0:bb348c97df44	2834	}
lypinator	0:bb348c97df44	2835
lypinator	0:bb348c97df44	2836	/**
lypinator	0:bb348c97df44	2837	* @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
lypinator	0:bb348c97df44	2838	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
lypinator	0:bb348c97df44	2839	* a timer instance provides a break input.
lypinator	0:bb348c97df44	2840	* @rmtoll BDTR OSSI LL_TIM_SetOffStates\n
lypinator	0:bb348c97df44	2841	* BDTR OSSR LL_TIM_SetOffStates
lypinator	0:bb348c97df44	2842	* @param TIMx Timer instance
lypinator	0:bb348c97df44	2843	* @param OffStateIdle This parameter can be one of the following values:
lypinator	0:bb348c97df44	2844	* @arg @ref LL_TIM_OSSI_DISABLE
lypinator	0:bb348c97df44	2845	* @arg @ref LL_TIM_OSSI_ENABLE
lypinator	0:bb348c97df44	2846	* @param OffStateRun This parameter can be one of the following values:
lypinator	0:bb348c97df44	2847	* @arg @ref LL_TIM_OSSR_DISABLE
lypinator	0:bb348c97df44	2848	* @arg @ref LL_TIM_OSSR_ENABLE
lypinator	0:bb348c97df44	2849	* @retval None
lypinator	0:bb348c97df44	2850	*/
lypinator	0:bb348c97df44	2851	__STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
lypinator	0:bb348c97df44	2852	{
lypinator	0:bb348c97df44	2853	MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI \| TIM_BDTR_OSSR, OffStateIdle \| OffStateRun);
lypinator	0:bb348c97df44	2854	}
lypinator	0:bb348c97df44	2855
lypinator	0:bb348c97df44	2856	/**
lypinator	0:bb348c97df44	2857	* @brief Enable automatic output (MOE can be set by software or automatically when a break input is active).
lypinator	0:bb348c97df44	2858	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
lypinator	0:bb348c97df44	2859	* a timer instance provides a break input.
lypinator	0:bb348c97df44	2860	* @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput
lypinator	0:bb348c97df44	2861	* @param TIMx Timer instance
lypinator	0:bb348c97df44	2862	* @retval None
lypinator	0:bb348c97df44	2863	*/
lypinator	0:bb348c97df44	2864	__STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	2865	{
lypinator	0:bb348c97df44	2866	SET_BIT(TIMx->BDTR, TIM_BDTR_AOE);
lypinator	0:bb348c97df44	2867	}
lypinator	0:bb348c97df44	2868
lypinator	0:bb348c97df44	2869	/**
lypinator	0:bb348c97df44	2870	* @brief Disable automatic output (MOE can be set only by software).
lypinator	0:bb348c97df44	2871	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
lypinator	0:bb348c97df44	2872	* a timer instance provides a break input.
lypinator	0:bb348c97df44	2873	* @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput
lypinator	0:bb348c97df44	2874	* @param TIMx Timer instance
lypinator	0:bb348c97df44	2875	* @retval None
lypinator	0:bb348c97df44	2876	*/
lypinator	0:bb348c97df44	2877	__STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	2878	{
lypinator	0:bb348c97df44	2879	CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE);
lypinator	0:bb348c97df44	2880	}
lypinator	0:bb348c97df44	2881
lypinator	0:bb348c97df44	2882	/**
lypinator	0:bb348c97df44	2883	* @brief Indicate whether automatic output is enabled.
lypinator	0:bb348c97df44	2884	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
lypinator	0:bb348c97df44	2885	* a timer instance provides a break input.
lypinator	0:bb348c97df44	2886	* @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput
lypinator	0:bb348c97df44	2887	* @param TIMx Timer instance
lypinator	0:bb348c97df44	2888	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	2889	*/
lypinator	0:bb348c97df44	2890	__STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	2891	{
lypinator	0:bb348c97df44	2892	return (READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE));
lypinator	0:bb348c97df44	2893	}
lypinator	0:bb348c97df44	2894
lypinator	0:bb348c97df44	2895	/**
lypinator	0:bb348c97df44	2896	* @brief Enable the outputs (set the MOE bit in TIMx_BDTR register).
lypinator	0:bb348c97df44	2897	* @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
lypinator	0:bb348c97df44	2898	* software and is reset in case of break or break2 event
lypinator	0:bb348c97df44	2899	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
lypinator	0:bb348c97df44	2900	* a timer instance provides a break input.
lypinator	0:bb348c97df44	2901	* @rmtoll BDTR MOE LL_TIM_EnableAllOutputs
lypinator	0:bb348c97df44	2902	* @param TIMx Timer instance
lypinator	0:bb348c97df44	2903	* @retval None
lypinator	0:bb348c97df44	2904	*/
lypinator	0:bb348c97df44	2905	__STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	2906	{
lypinator	0:bb348c97df44	2907	SET_BIT(TIMx->BDTR, TIM_BDTR_MOE);
lypinator	0:bb348c97df44	2908	}
lypinator	0:bb348c97df44	2909
lypinator	0:bb348c97df44	2910	/**
lypinator	0:bb348c97df44	2911	* @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register).
lypinator	0:bb348c97df44	2912	* @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
lypinator	0:bb348c97df44	2913	* software and is reset in case of break or break2 event.
lypinator	0:bb348c97df44	2914	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
lypinator	0:bb348c97df44	2915	* a timer instance provides a break input.
lypinator	0:bb348c97df44	2916	* @rmtoll BDTR MOE LL_TIM_DisableAllOutputs
lypinator	0:bb348c97df44	2917	* @param TIMx Timer instance
lypinator	0:bb348c97df44	2918	* @retval None
lypinator	0:bb348c97df44	2919	*/
lypinator	0:bb348c97df44	2920	__STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	2921	{
lypinator	0:bb348c97df44	2922	CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE);
lypinator	0:bb348c97df44	2923	}
lypinator	0:bb348c97df44	2924
lypinator	0:bb348c97df44	2925	/**
lypinator	0:bb348c97df44	2926	* @brief Indicates whether outputs are enabled.
lypinator	0:bb348c97df44	2927	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
lypinator	0:bb348c97df44	2928	* a timer instance provides a break input.
lypinator	0:bb348c97df44	2929	* @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs
lypinator	0:bb348c97df44	2930	* @param TIMx Timer instance
lypinator	0:bb348c97df44	2931	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	2932	*/
lypinator	0:bb348c97df44	2933	__STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	2934	{
lypinator	0:bb348c97df44	2935	return (READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE));
lypinator	0:bb348c97df44	2936	}
lypinator	0:bb348c97df44	2937
lypinator	0:bb348c97df44	2938	/**
lypinator	0:bb348c97df44	2939	* @}
lypinator	0:bb348c97df44	2940	*/
lypinator	0:bb348c97df44	2941
lypinator	0:bb348c97df44	2942	/** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
lypinator	0:bb348c97df44	2943	* @{
lypinator	0:bb348c97df44	2944	*/
lypinator	0:bb348c97df44	2945	/**
lypinator	0:bb348c97df44	2946	* @brief Configures the timer DMA burst feature.
lypinator	0:bb348c97df44	2947	* @note Macro @ref IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
lypinator	0:bb348c97df44	2948	* not a timer instance supports the DMA burst mode.
lypinator	0:bb348c97df44	2949	* @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n
lypinator	0:bb348c97df44	2950	* DCR DBA LL_TIM_ConfigDMABurst
lypinator	0:bb348c97df44	2951	* @param TIMx Timer instance
lypinator	0:bb348c97df44	2952	* @param DMABurstBaseAddress This parameter can be one of the following values:
lypinator	0:bb348c97df44	2953	* @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
lypinator	0:bb348c97df44	2954	* @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
lypinator	0:bb348c97df44	2955	* @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
lypinator	0:bb348c97df44	2956	* @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
lypinator	0:bb348c97df44	2957	* @arg @ref LL_TIM_DMABURST_BASEADDR_SR
lypinator	0:bb348c97df44	2958	* @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
lypinator	0:bb348c97df44	2959	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
lypinator	0:bb348c97df44	2960	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
lypinator	0:bb348c97df44	2961	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
lypinator	0:bb348c97df44	2962	* @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
lypinator	0:bb348c97df44	2963	* @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
lypinator	0:bb348c97df44	2964	* @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
lypinator	0:bb348c97df44	2965	* @arg @ref LL_TIM_DMABURST_BASEADDR_RCR
lypinator	0:bb348c97df44	2966	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
lypinator	0:bb348c97df44	2967	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
lypinator	0:bb348c97df44	2968	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
lypinator	0:bb348c97df44	2969	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
lypinator	0:bb348c97df44	2970	* @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR
lypinator	0:bb348c97df44	2971	* @arg @ref LL_TIM_DMABURST_BASEADDR_OR
lypinator	0:bb348c97df44	2972	* @param DMABurstLength This parameter can be one of the following values:
lypinator	0:bb348c97df44	2973	* @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
lypinator	0:bb348c97df44	2974	* @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
lypinator	0:bb348c97df44	2975	* @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
lypinator	0:bb348c97df44	2976	* @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
lypinator	0:bb348c97df44	2977	* @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
lypinator	0:bb348c97df44	2978	* @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
lypinator	0:bb348c97df44	2979	* @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
lypinator	0:bb348c97df44	2980	* @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
lypinator	0:bb348c97df44	2981	* @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
lypinator	0:bb348c97df44	2982	* @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
lypinator	0:bb348c97df44	2983	* @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
lypinator	0:bb348c97df44	2984	* @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
lypinator	0:bb348c97df44	2985	* @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
lypinator	0:bb348c97df44	2986	* @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
lypinator	0:bb348c97df44	2987	* @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
lypinator	0:bb348c97df44	2988	* @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
lypinator	0:bb348c97df44	2989	* @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
lypinator	0:bb348c97df44	2990	* @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
lypinator	0:bb348c97df44	2991	* @retval None
lypinator	0:bb348c97df44	2992	*/
lypinator	0:bb348c97df44	2993	__STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
lypinator	0:bb348c97df44	2994	{
lypinator	0:bb348c97df44	2995	MODIFY_REG(TIMx->DCR, TIM_DCR_DBL \| TIM_DCR_DBA, DMABurstBaseAddress \| DMABurstLength);
lypinator	0:bb348c97df44	2996	}
lypinator	0:bb348c97df44	2997
lypinator	0:bb348c97df44	2998	/**
lypinator	0:bb348c97df44	2999	* @}
lypinator	0:bb348c97df44	3000	*/
lypinator	0:bb348c97df44	3001
lypinator	0:bb348c97df44	3002	/** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping
lypinator	0:bb348c97df44	3003	* @{
lypinator	0:bb348c97df44	3004	*/
lypinator	0:bb348c97df44	3005	/**
lypinator	0:bb348c97df44	3006	* @brief Remap TIM inputs (input channel, internal/external triggers).
lypinator	0:bb348c97df44	3007	* @note Macro @ref IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
lypinator	0:bb348c97df44	3008	* a some timer inputs can be remapped.
lypinator	0:bb348c97df44	3009	* @rmtoll TIM2_OR ITR1_RMP LL_TIM_SetRemap\n
lypinator	0:bb348c97df44	3010	* TIM5_OR TI4_RMP LL_TIM_SetRemap\n
lypinator	0:bb348c97df44	3011	* TIM11_OR TI1_RMP LL_TIM_SetRemap
lypinator	0:bb348c97df44	3012	* @param TIMx Timer instance
lypinator	0:bb348c97df44	3013	* @param Remap Remap param depends on the TIMx. Description available only
lypinator	0:bb348c97df44	3014	* in CHM version of the User Manual (not in .pdf).
lypinator	0:bb348c97df44	3015	* Otherwise see Reference Manual description of OR registers.
lypinator	0:bb348c97df44	3016	*
lypinator	0:bb348c97df44	3017	* Below description summarizes "Timer Instance" and "Remap" param combinations:
lypinator	0:bb348c97df44	3018	*
lypinator	0:bb348c97df44	3019	* TIM2: one of the following values
lypinator	0:bb348c97df44	3020	*
lypinator	0:bb348c97df44	3021	* ITR1_RMP can be one of the following values
lypinator	0:bb348c97df44	3022	* @arg @ref LL_TIM_TIM2_ITR1_RMP_TIM8_TRGO
lypinator	0:bb348c97df44	3023	* @arg @ref LL_TIM_TIM2_ITR1_RMP_OTG_FS_SOF
lypinator	0:bb348c97df44	3024	* @arg @ref LL_TIM_TIM2_ITR1_RMP_OTG_HS_SOF
lypinator	0:bb348c97df44	3025	*
lypinator	0:bb348c97df44	3026	* TIM5: one of the following values
lypinator	0:bb348c97df44	3027	*
lypinator	0:bb348c97df44	3028	* @arg @ref LL_TIM_TIM5_TI4_RMP_GPIO
lypinator	0:bb348c97df44	3029	* @arg @ref LL_TIM_TIM5_TI4_RMP_LSI
lypinator	0:bb348c97df44	3030	* @arg @ref LL_TIM_TIM5_TI4_RMP_LSE
lypinator	0:bb348c97df44	3031	* @arg @ref LL_TIM_TIM5_TI4_RMP_RTC
lypinator	0:bb348c97df44	3032	*
lypinator	0:bb348c97df44	3033	* TIM11: one of the following values
lypinator	0:bb348c97df44	3034	*
lypinator	0:bb348c97df44	3035	* @arg @ref LL_TIM_TIM11_TI1_RMP_GPIO
lypinator	0:bb348c97df44	3036	* @arg @ref LL_TIM_TIM11_TI1_RMP_GPIO1
lypinator	0:bb348c97df44	3037	* @arg @ref LL_TIM_TIM11_TI1_RMP_HSE_RTC
lypinator	0:bb348c97df44	3038	* @arg @ref LL_TIM_TIM11_TI1_RMP_GPIO2
lypinator	0:bb348c97df44	3039	*
lypinator	0:bb348c97df44	3040	* @retval None
lypinator	0:bb348c97df44	3041	*/
lypinator	0:bb348c97df44	3042	__STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap)
lypinator	0:bb348c97df44	3043	{
lypinator	0:bb348c97df44	3044	MODIFY_REG(TIMx->OR, (Remap >> TIMx_OR_RMP_SHIFT), (Remap & TIMx_OR_RMP_MASK));
lypinator	0:bb348c97df44	3045	}
lypinator	0:bb348c97df44	3046
lypinator	0:bb348c97df44	3047	/**
lypinator	0:bb348c97df44	3048	* @}
lypinator	0:bb348c97df44	3049	*/
lypinator	0:bb348c97df44	3050
lypinator	0:bb348c97df44	3051
lypinator	0:bb348c97df44	3052	/** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
lypinator	0:bb348c97df44	3053	* @{
lypinator	0:bb348c97df44	3054	*/
lypinator	0:bb348c97df44	3055	/**
lypinator	0:bb348c97df44	3056	* @brief Clear the update interrupt flag (UIF).
lypinator	0:bb348c97df44	3057	* @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE
lypinator	0:bb348c97df44	3058	* @param TIMx Timer instance
lypinator	0:bb348c97df44	3059	* @retval None
lypinator	0:bb348c97df44	3060	*/
lypinator	0:bb348c97df44	3061	__STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	3062	{
lypinator	0:bb348c97df44	3063	WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
lypinator	0:bb348c97df44	3064	}
lypinator	0:bb348c97df44	3065
lypinator	0:bb348c97df44	3066	/**
lypinator	0:bb348c97df44	3067	* @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
lypinator	0:bb348c97df44	3068	* @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE
lypinator	0:bb348c97df44	3069	* @param TIMx Timer instance
lypinator	0:bb348c97df44	3070	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	3071	*/
lypinator	0:bb348c97df44	3072	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	3073	{
lypinator	0:bb348c97df44	3074	return (READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF));
lypinator	0:bb348c97df44	3075	}
lypinator	0:bb348c97df44	3076
lypinator	0:bb348c97df44	3077	/**
lypinator	0:bb348c97df44	3078	* @brief Clear the Capture/Compare 1 interrupt flag (CC1F).
lypinator	0:bb348c97df44	3079	* @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1
lypinator	0:bb348c97df44	3080	* @param TIMx Timer instance
lypinator	0:bb348c97df44	3081	* @retval None
lypinator	0:bb348c97df44	3082	*/
lypinator	0:bb348c97df44	3083	__STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	3084	{
lypinator	0:bb348c97df44	3085	WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
lypinator	0:bb348c97df44	3086	}
lypinator	0:bb348c97df44	3087
lypinator	0:bb348c97df44	3088	/**
lypinator	0:bb348c97df44	3089	* @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
lypinator	0:bb348c97df44	3090	* @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1
lypinator	0:bb348c97df44	3091	* @param TIMx Timer instance
lypinator	0:bb348c97df44	3092	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	3093	*/
lypinator	0:bb348c97df44	3094	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	3095	{
lypinator	0:bb348c97df44	3096	return (READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF));
lypinator	0:bb348c97df44	3097	}
lypinator	0:bb348c97df44	3098
lypinator	0:bb348c97df44	3099	/**
lypinator	0:bb348c97df44	3100	* @brief Clear the Capture/Compare 2 interrupt flag (CC2F).
lypinator	0:bb348c97df44	3101	* @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2
lypinator	0:bb348c97df44	3102	* @param TIMx Timer instance
lypinator	0:bb348c97df44	3103	* @retval None
lypinator	0:bb348c97df44	3104	*/
lypinator	0:bb348c97df44	3105	__STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	3106	{
lypinator	0:bb348c97df44	3107	WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
lypinator	0:bb348c97df44	3108	}
lypinator	0:bb348c97df44	3109
lypinator	0:bb348c97df44	3110	/**
lypinator	0:bb348c97df44	3111	* @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
lypinator	0:bb348c97df44	3112	* @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2
lypinator	0:bb348c97df44	3113	* @param TIMx Timer instance
lypinator	0:bb348c97df44	3114	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	3115	*/
lypinator	0:bb348c97df44	3116	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	3117	{
lypinator	0:bb348c97df44	3118	return (READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF));
lypinator	0:bb348c97df44	3119	}
lypinator	0:bb348c97df44	3120
lypinator	0:bb348c97df44	3121	/**
lypinator	0:bb348c97df44	3122	* @brief Clear the Capture/Compare 3 interrupt flag (CC3F).
lypinator	0:bb348c97df44	3123	* @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3
lypinator	0:bb348c97df44	3124	* @param TIMx Timer instance
lypinator	0:bb348c97df44	3125	* @retval None
lypinator	0:bb348c97df44	3126	*/
lypinator	0:bb348c97df44	3127	__STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	3128	{
lypinator	0:bb348c97df44	3129	WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
lypinator	0:bb348c97df44	3130	}
lypinator	0:bb348c97df44	3131
lypinator	0:bb348c97df44	3132	/**
lypinator	0:bb348c97df44	3133	* @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
lypinator	0:bb348c97df44	3134	* @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3
lypinator	0:bb348c97df44	3135	* @param TIMx Timer instance
lypinator	0:bb348c97df44	3136	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	3137	*/
lypinator	0:bb348c97df44	3138	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	3139	{
lypinator	0:bb348c97df44	3140	return (READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF));
lypinator	0:bb348c97df44	3141	}
lypinator	0:bb348c97df44	3142
lypinator	0:bb348c97df44	3143	/**
lypinator	0:bb348c97df44	3144	* @brief Clear the Capture/Compare 4 interrupt flag (CC4F).
lypinator	0:bb348c97df44	3145	* @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4
lypinator	0:bb348c97df44	3146	* @param TIMx Timer instance
lypinator	0:bb348c97df44	3147	* @retval None
lypinator	0:bb348c97df44	3148	*/
lypinator	0:bb348c97df44	3149	__STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	3150	{
lypinator	0:bb348c97df44	3151	WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
lypinator	0:bb348c97df44	3152	}
lypinator	0:bb348c97df44	3153
lypinator	0:bb348c97df44	3154	/**
lypinator	0:bb348c97df44	3155	* @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
lypinator	0:bb348c97df44	3156	* @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4
lypinator	0:bb348c97df44	3157	* @param TIMx Timer instance
lypinator	0:bb348c97df44	3158	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	3159	*/
lypinator	0:bb348c97df44	3160	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	3161	{
lypinator	0:bb348c97df44	3162	return (READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF));
lypinator	0:bb348c97df44	3163	}
lypinator	0:bb348c97df44	3164
lypinator	0:bb348c97df44	3165	/**
lypinator	0:bb348c97df44	3166	* @brief Clear the commutation interrupt flag (COMIF).
lypinator	0:bb348c97df44	3167	* @rmtoll SR COMIF LL_TIM_ClearFlag_COM
lypinator	0:bb348c97df44	3168	* @param TIMx Timer instance
lypinator	0:bb348c97df44	3169	* @retval None
lypinator	0:bb348c97df44	3170	*/
lypinator	0:bb348c97df44	3171	__STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	3172	{
lypinator	0:bb348c97df44	3173	WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF));
lypinator	0:bb348c97df44	3174	}
lypinator	0:bb348c97df44	3175
lypinator	0:bb348c97df44	3176	/**
lypinator	0:bb348c97df44	3177	* @brief Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
lypinator	0:bb348c97df44	3178	* @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM
lypinator	0:bb348c97df44	3179	* @param TIMx Timer instance
lypinator	0:bb348c97df44	3180	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	3181	*/
lypinator	0:bb348c97df44	3182	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	3183	{
lypinator	0:bb348c97df44	3184	return (READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF));
lypinator	0:bb348c97df44	3185	}
lypinator	0:bb348c97df44	3186
lypinator	0:bb348c97df44	3187	/**
lypinator	0:bb348c97df44	3188	* @brief Clear the trigger interrupt flag (TIF).
lypinator	0:bb348c97df44	3189	* @rmtoll SR TIF LL_TIM_ClearFlag_TRIG
lypinator	0:bb348c97df44	3190	* @param TIMx Timer instance
lypinator	0:bb348c97df44	3191	* @retval None
lypinator	0:bb348c97df44	3192	*/
lypinator	0:bb348c97df44	3193	__STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	3194	{
lypinator	0:bb348c97df44	3195	WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
lypinator	0:bb348c97df44	3196	}
lypinator	0:bb348c97df44	3197
lypinator	0:bb348c97df44	3198	/**
lypinator	0:bb348c97df44	3199	* @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
lypinator	0:bb348c97df44	3200	* @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG
lypinator	0:bb348c97df44	3201	* @param TIMx Timer instance
lypinator	0:bb348c97df44	3202	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	3203	*/
lypinator	0:bb348c97df44	3204	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	3205	{
lypinator	0:bb348c97df44	3206	return (READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF));
lypinator	0:bb348c97df44	3207	}
lypinator	0:bb348c97df44	3208
lypinator	0:bb348c97df44	3209	/**
lypinator	0:bb348c97df44	3210	* @brief Clear the break interrupt flag (BIF).
lypinator	0:bb348c97df44	3211	* @rmtoll SR BIF LL_TIM_ClearFlag_BRK
lypinator	0:bb348c97df44	3212	* @param TIMx Timer instance
lypinator	0:bb348c97df44	3213	* @retval None
lypinator	0:bb348c97df44	3214	*/
lypinator	0:bb348c97df44	3215	__STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	3216	{
lypinator	0:bb348c97df44	3217	WRITE_REG(TIMx->SR, ~(TIM_SR_BIF));
lypinator	0:bb348c97df44	3218	}
lypinator	0:bb348c97df44	3219
lypinator	0:bb348c97df44	3220	/**
lypinator	0:bb348c97df44	3221	* @brief Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
lypinator	0:bb348c97df44	3222	* @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK
lypinator	0:bb348c97df44	3223	* @param TIMx Timer instance
lypinator	0:bb348c97df44	3224	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	3225	*/
lypinator	0:bb348c97df44	3226	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	3227	{
lypinator	0:bb348c97df44	3228	return (READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF));
lypinator	0:bb348c97df44	3229	}
lypinator	0:bb348c97df44	3230
lypinator	0:bb348c97df44	3231	/**
lypinator	0:bb348c97df44	3232	* @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
lypinator	0:bb348c97df44	3233	* @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR
lypinator	0:bb348c97df44	3234	* @param TIMx Timer instance
lypinator	0:bb348c97df44	3235	* @retval None
lypinator	0:bb348c97df44	3236	*/
lypinator	0:bb348c97df44	3237	__STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	3238	{
lypinator	0:bb348c97df44	3239	WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
lypinator	0:bb348c97df44	3240	}
lypinator	0:bb348c97df44	3241
lypinator	0:bb348c97df44	3242	/**
lypinator	0:bb348c97df44	3243	* @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set (Capture/Compare 1 interrupt is pending).
lypinator	0:bb348c97df44	3244	* @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR
lypinator	0:bb348c97df44	3245	* @param TIMx Timer instance
lypinator	0:bb348c97df44	3246	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	3247	*/
lypinator	0:bb348c97df44	3248	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	3249	{
lypinator	0:bb348c97df44	3250	return (READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF));
lypinator	0:bb348c97df44	3251	}
lypinator	0:bb348c97df44	3252
lypinator	0:bb348c97df44	3253	/**
lypinator	0:bb348c97df44	3254	* @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
lypinator	0:bb348c97df44	3255	* @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR
lypinator	0:bb348c97df44	3256	* @param TIMx Timer instance
lypinator	0:bb348c97df44	3257	* @retval None
lypinator	0:bb348c97df44	3258	*/
lypinator	0:bb348c97df44	3259	__STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	3260	{
lypinator	0:bb348c97df44	3261	WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
lypinator	0:bb348c97df44	3262	}
lypinator	0:bb348c97df44	3263
lypinator	0:bb348c97df44	3264	/**
lypinator	0:bb348c97df44	3265	* @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set (Capture/Compare 2 over-capture interrupt is pending).
lypinator	0:bb348c97df44	3266	* @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR
lypinator	0:bb348c97df44	3267	* @param TIMx Timer instance
lypinator	0:bb348c97df44	3268	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	3269	*/
lypinator	0:bb348c97df44	3270	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	3271	{
lypinator	0:bb348c97df44	3272	return (READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF));
lypinator	0:bb348c97df44	3273	}
lypinator	0:bb348c97df44	3274
lypinator	0:bb348c97df44	3275	/**
lypinator	0:bb348c97df44	3276	* @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
lypinator	0:bb348c97df44	3277	* @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR
lypinator	0:bb348c97df44	3278	* @param TIMx Timer instance
lypinator	0:bb348c97df44	3279	* @retval None
lypinator	0:bb348c97df44	3280	*/
lypinator	0:bb348c97df44	3281	__STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	3282	{
lypinator	0:bb348c97df44	3283	WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
lypinator	0:bb348c97df44	3284	}
lypinator	0:bb348c97df44	3285
lypinator	0:bb348c97df44	3286	/**
lypinator	0:bb348c97df44	3287	* @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set (Capture/Compare 3 over-capture interrupt is pending).
lypinator	0:bb348c97df44	3288	* @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR
lypinator	0:bb348c97df44	3289	* @param TIMx Timer instance
lypinator	0:bb348c97df44	3290	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	3291	*/
lypinator	0:bb348c97df44	3292	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	3293	{
lypinator	0:bb348c97df44	3294	return (READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF));
lypinator	0:bb348c97df44	3295	}
lypinator	0:bb348c97df44	3296
lypinator	0:bb348c97df44	3297	/**
lypinator	0:bb348c97df44	3298	* @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
lypinator	0:bb348c97df44	3299	* @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR
lypinator	0:bb348c97df44	3300	* @param TIMx Timer instance
lypinator	0:bb348c97df44	3301	* @retval None
lypinator	0:bb348c97df44	3302	*/
lypinator	0:bb348c97df44	3303	__STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	3304	{
lypinator	0:bb348c97df44	3305	WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
lypinator	0:bb348c97df44	3306	}
lypinator	0:bb348c97df44	3307
lypinator	0:bb348c97df44	3308	/**
lypinator	0:bb348c97df44	3309	* @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set (Capture/Compare 4 over-capture interrupt is pending).
lypinator	0:bb348c97df44	3310	* @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR
lypinator	0:bb348c97df44	3311	* @param TIMx Timer instance
lypinator	0:bb348c97df44	3312	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	3313	*/
lypinator	0:bb348c97df44	3314	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	3315	{
lypinator	0:bb348c97df44	3316	return (READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF));
lypinator	0:bb348c97df44	3317	}
lypinator	0:bb348c97df44	3318
lypinator	0:bb348c97df44	3319	/**
lypinator	0:bb348c97df44	3320	* @}
lypinator	0:bb348c97df44	3321	*/
lypinator	0:bb348c97df44	3322
lypinator	0:bb348c97df44	3323	/** @defgroup TIM_LL_EF_IT_Management IT-Management
lypinator	0:bb348c97df44	3324	* @{
lypinator	0:bb348c97df44	3325	*/
lypinator	0:bb348c97df44	3326	/**
lypinator	0:bb348c97df44	3327	* @brief Enable update interrupt (UIE).
lypinator	0:bb348c97df44	3328	* @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE
lypinator	0:bb348c97df44	3329	* @param TIMx Timer instance
lypinator	0:bb348c97df44	3330	* @retval None
lypinator	0:bb348c97df44	3331	*/
lypinator	0:bb348c97df44	3332	__STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	3333	{
lypinator	0:bb348c97df44	3334	SET_BIT(TIMx->DIER, TIM_DIER_UIE);
lypinator	0:bb348c97df44	3335	}
lypinator	0:bb348c97df44	3336
lypinator	0:bb348c97df44	3337	/**
lypinator	0:bb348c97df44	3338	* @brief Disable update interrupt (UIE).
lypinator	0:bb348c97df44	3339	* @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE
lypinator	0:bb348c97df44	3340	* @param TIMx Timer instance
lypinator	0:bb348c97df44	3341	* @retval None
lypinator	0:bb348c97df44	3342	*/
lypinator	0:bb348c97df44	3343	__STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	3344	{
lypinator	0:bb348c97df44	3345	CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
lypinator	0:bb348c97df44	3346	}
lypinator	0:bb348c97df44	3347
lypinator	0:bb348c97df44	3348	/**
lypinator	0:bb348c97df44	3349	* @brief Indicates whether the update interrupt (UIE) is enabled.
lypinator	0:bb348c97df44	3350	* @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE
lypinator	0:bb348c97df44	3351	* @param TIMx Timer instance
lypinator	0:bb348c97df44	3352	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	3353	*/
lypinator	0:bb348c97df44	3354	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	3355	{
lypinator	0:bb348c97df44	3356	return (READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE));
lypinator	0:bb348c97df44	3357	}
lypinator	0:bb348c97df44	3358
lypinator	0:bb348c97df44	3359	/**
lypinator	0:bb348c97df44	3360	* @brief Enable capture/compare 1 interrupt (CC1IE).
lypinator	0:bb348c97df44	3361	* @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1
lypinator	0:bb348c97df44	3362	* @param TIMx Timer instance
lypinator	0:bb348c97df44	3363	* @retval None
lypinator	0:bb348c97df44	3364	*/
lypinator	0:bb348c97df44	3365	__STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	3366	{
lypinator	0:bb348c97df44	3367	SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
lypinator	0:bb348c97df44	3368	}
lypinator	0:bb348c97df44	3369
lypinator	0:bb348c97df44	3370	/**
lypinator	0:bb348c97df44	3371	* @brief Disable capture/compare 1 interrupt (CC1IE).
lypinator	0:bb348c97df44	3372	* @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1
lypinator	0:bb348c97df44	3373	* @param TIMx Timer instance
lypinator	0:bb348c97df44	3374	* @retval None
lypinator	0:bb348c97df44	3375	*/
lypinator	0:bb348c97df44	3376	__STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	3377	{
lypinator	0:bb348c97df44	3378	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
lypinator	0:bb348c97df44	3379	}
lypinator	0:bb348c97df44	3380
lypinator	0:bb348c97df44	3381	/**
lypinator	0:bb348c97df44	3382	* @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
lypinator	0:bb348c97df44	3383	* @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1
lypinator	0:bb348c97df44	3384	* @param TIMx Timer instance
lypinator	0:bb348c97df44	3385	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	3386	*/
lypinator	0:bb348c97df44	3387	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	3388	{
lypinator	0:bb348c97df44	3389	return (READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE));
lypinator	0:bb348c97df44	3390	}
lypinator	0:bb348c97df44	3391
lypinator	0:bb348c97df44	3392	/**
lypinator	0:bb348c97df44	3393	* @brief Enable capture/compare 2 interrupt (CC2IE).
lypinator	0:bb348c97df44	3394	* @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2
lypinator	0:bb348c97df44	3395	* @param TIMx Timer instance
lypinator	0:bb348c97df44	3396	* @retval None
lypinator	0:bb348c97df44	3397	*/
lypinator	0:bb348c97df44	3398	__STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	3399	{
lypinator	0:bb348c97df44	3400	SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
lypinator	0:bb348c97df44	3401	}
lypinator	0:bb348c97df44	3402
lypinator	0:bb348c97df44	3403	/**
lypinator	0:bb348c97df44	3404	* @brief Disable capture/compare 2 interrupt (CC2IE).
lypinator	0:bb348c97df44	3405	* @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2
lypinator	0:bb348c97df44	3406	* @param TIMx Timer instance
lypinator	0:bb348c97df44	3407	* @retval None
lypinator	0:bb348c97df44	3408	*/
lypinator	0:bb348c97df44	3409	__STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	3410	{
lypinator	0:bb348c97df44	3411	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
lypinator	0:bb348c97df44	3412	}
lypinator	0:bb348c97df44	3413
lypinator	0:bb348c97df44	3414	/**
lypinator	0:bb348c97df44	3415	* @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
lypinator	0:bb348c97df44	3416	* @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2
lypinator	0:bb348c97df44	3417	* @param TIMx Timer instance
lypinator	0:bb348c97df44	3418	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	3419	*/
lypinator	0:bb348c97df44	3420	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	3421	{
lypinator	0:bb348c97df44	3422	return (READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE));
lypinator	0:bb348c97df44	3423	}
lypinator	0:bb348c97df44	3424
lypinator	0:bb348c97df44	3425	/**
lypinator	0:bb348c97df44	3426	* @brief Enable capture/compare 3 interrupt (CC3IE).
lypinator	0:bb348c97df44	3427	* @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3
lypinator	0:bb348c97df44	3428	* @param TIMx Timer instance
lypinator	0:bb348c97df44	3429	* @retval None
lypinator	0:bb348c97df44	3430	*/
lypinator	0:bb348c97df44	3431	__STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	3432	{
lypinator	0:bb348c97df44	3433	SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
lypinator	0:bb348c97df44	3434	}
lypinator	0:bb348c97df44	3435
lypinator	0:bb348c97df44	3436	/**
lypinator	0:bb348c97df44	3437	* @brief Disable capture/compare 3 interrupt (CC3IE).
lypinator	0:bb348c97df44	3438	* @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3
lypinator	0:bb348c97df44	3439	* @param TIMx Timer instance
lypinator	0:bb348c97df44	3440	* @retval None
lypinator	0:bb348c97df44	3441	*/
lypinator	0:bb348c97df44	3442	__STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	3443	{
lypinator	0:bb348c97df44	3444	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
lypinator	0:bb348c97df44	3445	}
lypinator	0:bb348c97df44	3446
lypinator	0:bb348c97df44	3447	/**
lypinator	0:bb348c97df44	3448	* @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
lypinator	0:bb348c97df44	3449	* @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3
lypinator	0:bb348c97df44	3450	* @param TIMx Timer instance
lypinator	0:bb348c97df44	3451	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	3452	*/
lypinator	0:bb348c97df44	3453	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	3454	{
lypinator	0:bb348c97df44	3455	return (READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE));
lypinator	0:bb348c97df44	3456	}
lypinator	0:bb348c97df44	3457
lypinator	0:bb348c97df44	3458	/**
lypinator	0:bb348c97df44	3459	* @brief Enable capture/compare 4 interrupt (CC4IE).
lypinator	0:bb348c97df44	3460	* @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4
lypinator	0:bb348c97df44	3461	* @param TIMx Timer instance
lypinator	0:bb348c97df44	3462	* @retval None
lypinator	0:bb348c97df44	3463	*/
lypinator	0:bb348c97df44	3464	__STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	3465	{
lypinator	0:bb348c97df44	3466	SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
lypinator	0:bb348c97df44	3467	}
lypinator	0:bb348c97df44	3468
lypinator	0:bb348c97df44	3469	/**
lypinator	0:bb348c97df44	3470	* @brief Disable capture/compare 4 interrupt (CC4IE).
lypinator	0:bb348c97df44	3471	* @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4
lypinator	0:bb348c97df44	3472	* @param TIMx Timer instance
lypinator	0:bb348c97df44	3473	* @retval None
lypinator	0:bb348c97df44	3474	*/
lypinator	0:bb348c97df44	3475	__STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	3476	{
lypinator	0:bb348c97df44	3477	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
lypinator	0:bb348c97df44	3478	}
lypinator	0:bb348c97df44	3479
lypinator	0:bb348c97df44	3480	/**
lypinator	0:bb348c97df44	3481	* @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
lypinator	0:bb348c97df44	3482	* @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4
lypinator	0:bb348c97df44	3483	* @param TIMx Timer instance
lypinator	0:bb348c97df44	3484	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	3485	*/
lypinator	0:bb348c97df44	3486	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	3487	{
lypinator	0:bb348c97df44	3488	return (READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE));
lypinator	0:bb348c97df44	3489	}
lypinator	0:bb348c97df44	3490
lypinator	0:bb348c97df44	3491	/**
lypinator	0:bb348c97df44	3492	* @brief Enable commutation interrupt (COMIE).
lypinator	0:bb348c97df44	3493	* @rmtoll DIER COMIE LL_TIM_EnableIT_COM
lypinator	0:bb348c97df44	3494	* @param TIMx Timer instance
lypinator	0:bb348c97df44	3495	* @retval None
lypinator	0:bb348c97df44	3496	*/
lypinator	0:bb348c97df44	3497	__STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	3498	{
lypinator	0:bb348c97df44	3499	SET_BIT(TIMx->DIER, TIM_DIER_COMIE);
lypinator	0:bb348c97df44	3500	}
lypinator	0:bb348c97df44	3501
lypinator	0:bb348c97df44	3502	/**
lypinator	0:bb348c97df44	3503	* @brief Disable commutation interrupt (COMIE).
lypinator	0:bb348c97df44	3504	* @rmtoll DIER COMIE LL_TIM_DisableIT_COM
lypinator	0:bb348c97df44	3505	* @param TIMx Timer instance
lypinator	0:bb348c97df44	3506	* @retval None
lypinator	0:bb348c97df44	3507	*/
lypinator	0:bb348c97df44	3508	__STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	3509	{
lypinator	0:bb348c97df44	3510	CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE);
lypinator	0:bb348c97df44	3511	}
lypinator	0:bb348c97df44	3512
lypinator	0:bb348c97df44	3513	/**
lypinator	0:bb348c97df44	3514	* @brief Indicates whether the commutation interrupt (COMIE) is enabled.
lypinator	0:bb348c97df44	3515	* @rmtoll DIER COMIE LL_TIM_IsEnabledIT_COM
lypinator	0:bb348c97df44	3516	* @param TIMx Timer instance
lypinator	0:bb348c97df44	3517	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	3518	*/
lypinator	0:bb348c97df44	3519	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	3520	{
lypinator	0:bb348c97df44	3521	return (READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE));
lypinator	0:bb348c97df44	3522	}
lypinator	0:bb348c97df44	3523
lypinator	0:bb348c97df44	3524	/**
lypinator	0:bb348c97df44	3525	* @brief Enable trigger interrupt (TIE).
lypinator	0:bb348c97df44	3526	* @rmtoll DIER TIE LL_TIM_EnableIT_TRIG
lypinator	0:bb348c97df44	3527	* @param TIMx Timer instance
lypinator	0:bb348c97df44	3528	* @retval None
lypinator	0:bb348c97df44	3529	*/
lypinator	0:bb348c97df44	3530	__STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	3531	{
lypinator	0:bb348c97df44	3532	SET_BIT(TIMx->DIER, TIM_DIER_TIE);
lypinator	0:bb348c97df44	3533	}
lypinator	0:bb348c97df44	3534
lypinator	0:bb348c97df44	3535	/**
lypinator	0:bb348c97df44	3536	* @brief Disable trigger interrupt (TIE).
lypinator	0:bb348c97df44	3537	* @rmtoll DIER TIE LL_TIM_DisableIT_TRIG
lypinator	0:bb348c97df44	3538	* @param TIMx Timer instance
lypinator	0:bb348c97df44	3539	* @retval None
lypinator	0:bb348c97df44	3540	*/
lypinator	0:bb348c97df44	3541	__STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	3542	{
lypinator	0:bb348c97df44	3543	CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
lypinator	0:bb348c97df44	3544	}
lypinator	0:bb348c97df44	3545
lypinator	0:bb348c97df44	3546	/**
lypinator	0:bb348c97df44	3547	* @brief Indicates whether the trigger interrupt (TIE) is enabled.
lypinator	0:bb348c97df44	3548	* @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG
lypinator	0:bb348c97df44	3549	* @param TIMx Timer instance
lypinator	0:bb348c97df44	3550	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	3551	*/
lypinator	0:bb348c97df44	3552	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	3553	{
lypinator	0:bb348c97df44	3554	return (READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE));
lypinator	0:bb348c97df44	3555	}
lypinator	0:bb348c97df44	3556
lypinator	0:bb348c97df44	3557	/**
lypinator	0:bb348c97df44	3558	* @brief Enable break interrupt (BIE).
lypinator	0:bb348c97df44	3559	* @rmtoll DIER BIE LL_TIM_EnableIT_BRK
lypinator	0:bb348c97df44	3560	* @param TIMx Timer instance
lypinator	0:bb348c97df44	3561	* @retval None
lypinator	0:bb348c97df44	3562	*/
lypinator	0:bb348c97df44	3563	__STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	3564	{
lypinator	0:bb348c97df44	3565	SET_BIT(TIMx->DIER, TIM_DIER_BIE);
lypinator	0:bb348c97df44	3566	}
lypinator	0:bb348c97df44	3567
lypinator	0:bb348c97df44	3568	/**
lypinator	0:bb348c97df44	3569	* @brief Disable break interrupt (BIE).
lypinator	0:bb348c97df44	3570	* @rmtoll DIER BIE LL_TIM_DisableIT_BRK
lypinator	0:bb348c97df44	3571	* @param TIMx Timer instance
lypinator	0:bb348c97df44	3572	* @retval None
lypinator	0:bb348c97df44	3573	*/
lypinator	0:bb348c97df44	3574	__STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	3575	{
lypinator	0:bb348c97df44	3576	CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE);
lypinator	0:bb348c97df44	3577	}
lypinator	0:bb348c97df44	3578
lypinator	0:bb348c97df44	3579	/**
lypinator	0:bb348c97df44	3580	* @brief Indicates whether the break interrupt (BIE) is enabled.
lypinator	0:bb348c97df44	3581	* @rmtoll DIER BIE LL_TIM_IsEnabledIT_BRK
lypinator	0:bb348c97df44	3582	* @param TIMx Timer instance
lypinator	0:bb348c97df44	3583	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	3584	*/
lypinator	0:bb348c97df44	3585	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	3586	{
lypinator	0:bb348c97df44	3587	return (READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE));
lypinator	0:bb348c97df44	3588	}
lypinator	0:bb348c97df44	3589
lypinator	0:bb348c97df44	3590	/**
lypinator	0:bb348c97df44	3591	* @}
lypinator	0:bb348c97df44	3592	*/
lypinator	0:bb348c97df44	3593
lypinator	0:bb348c97df44	3594	/** @defgroup TIM_LL_EF_DMA_Management DMA-Management
lypinator	0:bb348c97df44	3595	* @{
lypinator	0:bb348c97df44	3596	*/
lypinator	0:bb348c97df44	3597	/**
lypinator	0:bb348c97df44	3598	* @brief Enable update DMA request (UDE).
lypinator	0:bb348c97df44	3599	* @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE
lypinator	0:bb348c97df44	3600	* @param TIMx Timer instance
lypinator	0:bb348c97df44	3601	* @retval None
lypinator	0:bb348c97df44	3602	*/
lypinator	0:bb348c97df44	3603	__STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	3604	{
lypinator	0:bb348c97df44	3605	SET_BIT(TIMx->DIER, TIM_DIER_UDE);
lypinator	0:bb348c97df44	3606	}
lypinator	0:bb348c97df44	3607
lypinator	0:bb348c97df44	3608	/**
lypinator	0:bb348c97df44	3609	* @brief Disable update DMA request (UDE).
lypinator	0:bb348c97df44	3610	* @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE
lypinator	0:bb348c97df44	3611	* @param TIMx Timer instance
lypinator	0:bb348c97df44	3612	* @retval None
lypinator	0:bb348c97df44	3613	*/
lypinator	0:bb348c97df44	3614	__STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	3615	{
lypinator	0:bb348c97df44	3616	CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
lypinator	0:bb348c97df44	3617	}
lypinator	0:bb348c97df44	3618
lypinator	0:bb348c97df44	3619	/**
lypinator	0:bb348c97df44	3620	* @brief Indicates whether the update DMA request (UDE) is enabled.
lypinator	0:bb348c97df44	3621	* @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE
lypinator	0:bb348c97df44	3622	* @param TIMx Timer instance
lypinator	0:bb348c97df44	3623	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	3624	*/
lypinator	0:bb348c97df44	3625	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	3626	{
lypinator	0:bb348c97df44	3627	return (READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE));
lypinator	0:bb348c97df44	3628	}
lypinator	0:bb348c97df44	3629
lypinator	0:bb348c97df44	3630	/**
lypinator	0:bb348c97df44	3631	* @brief Enable capture/compare 1 DMA request (CC1DE).
lypinator	0:bb348c97df44	3632	* @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1
lypinator	0:bb348c97df44	3633	* @param TIMx Timer instance
lypinator	0:bb348c97df44	3634	* @retval None
lypinator	0:bb348c97df44	3635	*/
lypinator	0:bb348c97df44	3636	__STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	3637	{
lypinator	0:bb348c97df44	3638	SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
lypinator	0:bb348c97df44	3639	}
lypinator	0:bb348c97df44	3640
lypinator	0:bb348c97df44	3641	/**
lypinator	0:bb348c97df44	3642	* @brief Disable capture/compare 1 DMA request (CC1DE).
lypinator	0:bb348c97df44	3643	* @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1
lypinator	0:bb348c97df44	3644	* @param TIMx Timer instance
lypinator	0:bb348c97df44	3645	* @retval None
lypinator	0:bb348c97df44	3646	*/
lypinator	0:bb348c97df44	3647	__STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	3648	{
lypinator	0:bb348c97df44	3649	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
lypinator	0:bb348c97df44	3650	}
lypinator	0:bb348c97df44	3651
lypinator	0:bb348c97df44	3652	/**
lypinator	0:bb348c97df44	3653	* @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
lypinator	0:bb348c97df44	3654	* @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1
lypinator	0:bb348c97df44	3655	* @param TIMx Timer instance
lypinator	0:bb348c97df44	3656	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	3657	*/
lypinator	0:bb348c97df44	3658	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	3659	{
lypinator	0:bb348c97df44	3660	return (READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE));
lypinator	0:bb348c97df44	3661	}
lypinator	0:bb348c97df44	3662
lypinator	0:bb348c97df44	3663	/**
lypinator	0:bb348c97df44	3664	* @brief Enable capture/compare 2 DMA request (CC2DE).
lypinator	0:bb348c97df44	3665	* @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2
lypinator	0:bb348c97df44	3666	* @param TIMx Timer instance
lypinator	0:bb348c97df44	3667	* @retval None
lypinator	0:bb348c97df44	3668	*/
lypinator	0:bb348c97df44	3669	__STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	3670	{
lypinator	0:bb348c97df44	3671	SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
lypinator	0:bb348c97df44	3672	}
lypinator	0:bb348c97df44	3673
lypinator	0:bb348c97df44	3674	/**
lypinator	0:bb348c97df44	3675	* @brief Disable capture/compare 2 DMA request (CC2DE).
lypinator	0:bb348c97df44	3676	* @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2
lypinator	0:bb348c97df44	3677	* @param TIMx Timer instance
lypinator	0:bb348c97df44	3678	* @retval None
lypinator	0:bb348c97df44	3679	*/
lypinator	0:bb348c97df44	3680	__STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	3681	{
lypinator	0:bb348c97df44	3682	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
lypinator	0:bb348c97df44	3683	}
lypinator	0:bb348c97df44	3684
lypinator	0:bb348c97df44	3685	/**
lypinator	0:bb348c97df44	3686	* @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
lypinator	0:bb348c97df44	3687	* @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2
lypinator	0:bb348c97df44	3688	* @param TIMx Timer instance
lypinator	0:bb348c97df44	3689	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	3690	*/
lypinator	0:bb348c97df44	3691	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	3692	{
lypinator	0:bb348c97df44	3693	return (READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE));
lypinator	0:bb348c97df44	3694	}
lypinator	0:bb348c97df44	3695
lypinator	0:bb348c97df44	3696	/**
lypinator	0:bb348c97df44	3697	* @brief Enable capture/compare 3 DMA request (CC3DE).
lypinator	0:bb348c97df44	3698	* @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3
lypinator	0:bb348c97df44	3699	* @param TIMx Timer instance
lypinator	0:bb348c97df44	3700	* @retval None
lypinator	0:bb348c97df44	3701	*/
lypinator	0:bb348c97df44	3702	__STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	3703	{
lypinator	0:bb348c97df44	3704	SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
lypinator	0:bb348c97df44	3705	}
lypinator	0:bb348c97df44	3706
lypinator	0:bb348c97df44	3707	/**
lypinator	0:bb348c97df44	3708	* @brief Disable capture/compare 3 DMA request (CC3DE).
lypinator	0:bb348c97df44	3709	* @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3
lypinator	0:bb348c97df44	3710	* @param TIMx Timer instance
lypinator	0:bb348c97df44	3711	* @retval None
lypinator	0:bb348c97df44	3712	*/
lypinator	0:bb348c97df44	3713	__STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	3714	{
lypinator	0:bb348c97df44	3715	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
lypinator	0:bb348c97df44	3716	}
lypinator	0:bb348c97df44	3717
lypinator	0:bb348c97df44	3718	/**
lypinator	0:bb348c97df44	3719	* @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
lypinator	0:bb348c97df44	3720	* @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3
lypinator	0:bb348c97df44	3721	* @param TIMx Timer instance
lypinator	0:bb348c97df44	3722	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	3723	*/
lypinator	0:bb348c97df44	3724	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	3725	{
lypinator	0:bb348c97df44	3726	return (READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE));
lypinator	0:bb348c97df44	3727	}
lypinator	0:bb348c97df44	3728
lypinator	0:bb348c97df44	3729	/**
lypinator	0:bb348c97df44	3730	* @brief Enable capture/compare 4 DMA request (CC4DE).
lypinator	0:bb348c97df44	3731	* @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4
lypinator	0:bb348c97df44	3732	* @param TIMx Timer instance
lypinator	0:bb348c97df44	3733	* @retval None
lypinator	0:bb348c97df44	3734	*/
lypinator	0:bb348c97df44	3735	__STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	3736	{
lypinator	0:bb348c97df44	3737	SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
lypinator	0:bb348c97df44	3738	}
lypinator	0:bb348c97df44	3739
lypinator	0:bb348c97df44	3740	/**
lypinator	0:bb348c97df44	3741	* @brief Disable capture/compare 4 DMA request (CC4DE).
lypinator	0:bb348c97df44	3742	* @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4
lypinator	0:bb348c97df44	3743	* @param TIMx Timer instance
lypinator	0:bb348c97df44	3744	* @retval None
lypinator	0:bb348c97df44	3745	*/
lypinator	0:bb348c97df44	3746	__STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	3747	{
lypinator	0:bb348c97df44	3748	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
lypinator	0:bb348c97df44	3749	}
lypinator	0:bb348c97df44	3750
lypinator	0:bb348c97df44	3751	/**
lypinator	0:bb348c97df44	3752	* @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
lypinator	0:bb348c97df44	3753	* @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4
lypinator	0:bb348c97df44	3754	* @param TIMx Timer instance
lypinator	0:bb348c97df44	3755	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	3756	*/
lypinator	0:bb348c97df44	3757	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	3758	{
lypinator	0:bb348c97df44	3759	return (READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE));
lypinator	0:bb348c97df44	3760	}
lypinator	0:bb348c97df44	3761
lypinator	0:bb348c97df44	3762	/**
lypinator	0:bb348c97df44	3763	* @brief Enable commutation DMA request (COMDE).
lypinator	0:bb348c97df44	3764	* @rmtoll DIER COMDE LL_TIM_EnableDMAReq_COM
lypinator	0:bb348c97df44	3765	* @param TIMx Timer instance
lypinator	0:bb348c97df44	3766	* @retval None
lypinator	0:bb348c97df44	3767	*/
lypinator	0:bb348c97df44	3768	__STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	3769	{
lypinator	0:bb348c97df44	3770	SET_BIT(TIMx->DIER, TIM_DIER_COMDE);
lypinator	0:bb348c97df44	3771	}
lypinator	0:bb348c97df44	3772
lypinator	0:bb348c97df44	3773	/**
lypinator	0:bb348c97df44	3774	* @brief Disable commutation DMA request (COMDE).
lypinator	0:bb348c97df44	3775	* @rmtoll DIER COMDE LL_TIM_DisableDMAReq_COM
lypinator	0:bb348c97df44	3776	* @param TIMx Timer instance
lypinator	0:bb348c97df44	3777	* @retval None
lypinator	0:bb348c97df44	3778	*/
lypinator	0:bb348c97df44	3779	__STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	3780	{
lypinator	0:bb348c97df44	3781	CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE);
lypinator	0:bb348c97df44	3782	}
lypinator	0:bb348c97df44	3783
lypinator	0:bb348c97df44	3784	/**
lypinator	0:bb348c97df44	3785	* @brief Indicates whether the commutation DMA request (COMDE) is enabled.
lypinator	0:bb348c97df44	3786	* @rmtoll DIER COMDE LL_TIM_IsEnabledDMAReq_COM
lypinator	0:bb348c97df44	3787	* @param TIMx Timer instance
lypinator	0:bb348c97df44	3788	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	3789	*/
lypinator	0:bb348c97df44	3790	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	3791	{
lypinator	0:bb348c97df44	3792	return (READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE));
lypinator	0:bb348c97df44	3793	}
lypinator	0:bb348c97df44	3794
lypinator	0:bb348c97df44	3795	/**
lypinator	0:bb348c97df44	3796	* @brief Enable trigger interrupt (TDE).
lypinator	0:bb348c97df44	3797	* @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG
lypinator	0:bb348c97df44	3798	* @param TIMx Timer instance
lypinator	0:bb348c97df44	3799	* @retval None
lypinator	0:bb348c97df44	3800	*/
lypinator	0:bb348c97df44	3801	__STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	3802	{
lypinator	0:bb348c97df44	3803	SET_BIT(TIMx->DIER, TIM_DIER_TDE);
lypinator	0:bb348c97df44	3804	}
lypinator	0:bb348c97df44	3805
lypinator	0:bb348c97df44	3806	/**
lypinator	0:bb348c97df44	3807	* @brief Disable trigger interrupt (TDE).
lypinator	0:bb348c97df44	3808	* @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG
lypinator	0:bb348c97df44	3809	* @param TIMx Timer instance
lypinator	0:bb348c97df44	3810	* @retval None
lypinator	0:bb348c97df44	3811	*/
lypinator	0:bb348c97df44	3812	__STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	3813	{
lypinator	0:bb348c97df44	3814	CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);
lypinator	0:bb348c97df44	3815	}
lypinator	0:bb348c97df44	3816
lypinator	0:bb348c97df44	3817	/**
lypinator	0:bb348c97df44	3818	* @brief Indicates whether the trigger interrupt (TDE) is enabled.
lypinator	0:bb348c97df44	3819	* @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG
lypinator	0:bb348c97df44	3820	* @param TIMx Timer instance
lypinator	0:bb348c97df44	3821	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	3822	*/
lypinator	0:bb348c97df44	3823	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	3824	{
lypinator	0:bb348c97df44	3825	return (READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE));
lypinator	0:bb348c97df44	3826	}
lypinator	0:bb348c97df44	3827
lypinator	0:bb348c97df44	3828	/**
lypinator	0:bb348c97df44	3829	* @}
lypinator	0:bb348c97df44	3830	*/
lypinator	0:bb348c97df44	3831
lypinator	0:bb348c97df44	3832	/** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management
lypinator	0:bb348c97df44	3833	* @{
lypinator	0:bb348c97df44	3834	*/
lypinator	0:bb348c97df44	3835	/**
lypinator	0:bb348c97df44	3836	* @brief Generate an update event.
lypinator	0:bb348c97df44	3837	* @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE
lypinator	0:bb348c97df44	3838	* @param TIMx Timer instance
lypinator	0:bb348c97df44	3839	* @retval None
lypinator	0:bb348c97df44	3840	*/
lypinator	0:bb348c97df44	3841	__STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	3842	{
lypinator	0:bb348c97df44	3843	SET_BIT(TIMx->EGR, TIM_EGR_UG);
lypinator	0:bb348c97df44	3844	}
lypinator	0:bb348c97df44	3845
lypinator	0:bb348c97df44	3846	/**
lypinator	0:bb348c97df44	3847	* @brief Generate Capture/Compare 1 event.
lypinator	0:bb348c97df44	3848	* @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1
lypinator	0:bb348c97df44	3849	* @param TIMx Timer instance
lypinator	0:bb348c97df44	3850	* @retval None
lypinator	0:bb348c97df44	3851	*/
lypinator	0:bb348c97df44	3852	__STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	3853	{
lypinator	0:bb348c97df44	3854	SET_BIT(TIMx->EGR, TIM_EGR_CC1G);
lypinator	0:bb348c97df44	3855	}
lypinator	0:bb348c97df44	3856
lypinator	0:bb348c97df44	3857	/**
lypinator	0:bb348c97df44	3858	* @brief Generate Capture/Compare 2 event.
lypinator	0:bb348c97df44	3859	* @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2
lypinator	0:bb348c97df44	3860	* @param TIMx Timer instance
lypinator	0:bb348c97df44	3861	* @retval None
lypinator	0:bb348c97df44	3862	*/
lypinator	0:bb348c97df44	3863	__STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	3864	{
lypinator	0:bb348c97df44	3865	SET_BIT(TIMx->EGR, TIM_EGR_CC2G);
lypinator	0:bb348c97df44	3866	}
lypinator	0:bb348c97df44	3867
lypinator	0:bb348c97df44	3868	/**
lypinator	0:bb348c97df44	3869	* @brief Generate Capture/Compare 3 event.
lypinator	0:bb348c97df44	3870	* @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3
lypinator	0:bb348c97df44	3871	* @param TIMx Timer instance
lypinator	0:bb348c97df44	3872	* @retval None
lypinator	0:bb348c97df44	3873	*/
lypinator	0:bb348c97df44	3874	__STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	3875	{
lypinator	0:bb348c97df44	3876	SET_BIT(TIMx->EGR, TIM_EGR_CC3G);
lypinator	0:bb348c97df44	3877	}
lypinator	0:bb348c97df44	3878
lypinator	0:bb348c97df44	3879	/**
lypinator	0:bb348c97df44	3880	* @brief Generate Capture/Compare 4 event.
lypinator	0:bb348c97df44	3881	* @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4
lypinator	0:bb348c97df44	3882	* @param TIMx Timer instance
lypinator	0:bb348c97df44	3883	* @retval None
lypinator	0:bb348c97df44	3884	*/
lypinator	0:bb348c97df44	3885	__STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	3886	{
lypinator	0:bb348c97df44	3887	SET_BIT(TIMx->EGR, TIM_EGR_CC4G);
lypinator	0:bb348c97df44	3888	}
lypinator	0:bb348c97df44	3889
lypinator	0:bb348c97df44	3890	/**
lypinator	0:bb348c97df44	3891	* @brief Generate commutation event.
lypinator	0:bb348c97df44	3892	* @rmtoll EGR COMG LL_TIM_GenerateEvent_COM
lypinator	0:bb348c97df44	3893	* @param TIMx Timer instance
lypinator	0:bb348c97df44	3894	* @retval None
lypinator	0:bb348c97df44	3895	*/
lypinator	0:bb348c97df44	3896	__STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	3897	{
lypinator	0:bb348c97df44	3898	SET_BIT(TIMx->EGR, TIM_EGR_COMG);
lypinator	0:bb348c97df44	3899	}
lypinator	0:bb348c97df44	3900
lypinator	0:bb348c97df44	3901	/**
lypinator	0:bb348c97df44	3902	* @brief Generate trigger event.
lypinator	0:bb348c97df44	3903	* @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG
lypinator	0:bb348c97df44	3904	* @param TIMx Timer instance
lypinator	0:bb348c97df44	3905	* @retval None
lypinator	0:bb348c97df44	3906	*/
lypinator	0:bb348c97df44	3907	__STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	3908	{
lypinator	0:bb348c97df44	3909	SET_BIT(TIMx->EGR, TIM_EGR_TG);
lypinator	0:bb348c97df44	3910	}
lypinator	0:bb348c97df44	3911
lypinator	0:bb348c97df44	3912	/**
lypinator	0:bb348c97df44	3913	* @brief Generate break event.
lypinator	0:bb348c97df44	3914	* @rmtoll EGR BG LL_TIM_GenerateEvent_BRK
lypinator	0:bb348c97df44	3915	* @param TIMx Timer instance
lypinator	0:bb348c97df44	3916	* @retval None
lypinator	0:bb348c97df44	3917	*/
lypinator	0:bb348c97df44	3918	__STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx)
lypinator	0:bb348c97df44	3919	{
lypinator	0:bb348c97df44	3920	SET_BIT(TIMx->EGR, TIM_EGR_BG);
lypinator	0:bb348c97df44	3921	}
lypinator	0:bb348c97df44	3922
lypinator	0:bb348c97df44	3923	/**
lypinator	0:bb348c97df44	3924	* @}
lypinator	0:bb348c97df44	3925	*/
lypinator	0:bb348c97df44	3926
lypinator	0:bb348c97df44	3927	#if defined(USE_FULL_LL_DRIVER)
lypinator	0:bb348c97df44	3928	/** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions
lypinator	0:bb348c97df44	3929	* @{
lypinator	0:bb348c97df44	3930	*/
lypinator	0:bb348c97df44	3931
lypinator	0:bb348c97df44	3932	ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx);
lypinator	0:bb348c97df44	3933	void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
lypinator	0:bb348c97df44	3934	ErrorStatus LL_TIM_Init(TIM_TypeDef TIMx, LL_TIM_InitTypeDef TIM_InitStruct);
lypinator	0:bb348c97df44	3935	void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
lypinator	0:bb348c97df44	3936	ErrorStatus LL_TIM_OC_Init(TIM_TypeDef TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef TIM_OC_InitStruct);
lypinator	0:bb348c97df44	3937	void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
lypinator	0:bb348c97df44	3938	ErrorStatus LL_TIM_IC_Init(TIM_TypeDef TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef TIM_IC_InitStruct);
lypinator	0:bb348c97df44	3939	void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
lypinator	0:bb348c97df44	3940	ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef TIMx, LL_TIM_ENCODER_InitTypeDef TIM_EncoderInitStruct);
lypinator	0:bb348c97df44	3941	void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
lypinator	0:bb348c97df44	3942	ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef TIMx, LL_TIM_HALLSENSOR_InitTypeDef TIM_HallSensorInitStruct);
lypinator	0:bb348c97df44	3943	void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
lypinator	0:bb348c97df44	3944	ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef TIMx, LL_TIM_BDTR_InitTypeDef TIM_BDTRInitStruct);
lypinator	0:bb348c97df44	3945	/**
lypinator	0:bb348c97df44	3946	* @}
lypinator	0:bb348c97df44	3947	*/
lypinator	0:bb348c97df44	3948	#endif /* USE_FULL_LL_DRIVER */
lypinator	0:bb348c97df44	3949
lypinator	0:bb348c97df44	3950	/**
lypinator	0:bb348c97df44	3951	* @}
lypinator	0:bb348c97df44	3952	*/
lypinator	0:bb348c97df44	3953
lypinator	0:bb348c97df44	3954	/**
lypinator	0:bb348c97df44	3955	* @}
lypinator	0:bb348c97df44	3956	*/
lypinator	0:bb348c97df44	3957
lypinator	0:bb348c97df44	3958	#endif /* TIM1 \|\| TIM2 \|\| TIM3 \|\| TIM4 \|\| TIM5 \|\| TIM6 \|\| TIM7 \|\| TIM8 \|\| TIM9 \|\| TIM10 \|\| TIM11 \|\| TIM12 \|\| TIM13 \|\| TIM14 */
lypinator	0:bb348c97df44	3959
lypinator	0:bb348c97df44	3960	/**
lypinator	0:bb348c97df44	3961	* @}
lypinator	0:bb348c97df44	3962	*/
lypinator	0:bb348c97df44	3963
lypinator	0:bb348c97df44	3964	#ifdef __cplusplus
lypinator	0:bb348c97df44	3965	}
lypinator	0:bb348c97df44	3966	#endif
lypinator	0:bb348c97df44	3967
lypinator	0:bb348c97df44	3968	#endif /* __STM32F4xx_LL_TIM_H */
lypinator	0:bb348c97df44	3969	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Program
Created:	16 Sep 2020
Imports:	1
Forks:	0
Commits:	1
Dependents:	0
Dependencies:	1
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mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_tim.h@0:bb348c97df44, 2020-09-16 (annotated)

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