Thomas Lyp / DevLibMemoryController

Initial commit

Dependencies:   FastPWM

mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_tim.c@0:bb348c97df44, 2020-09-16 (annotated)

Committer:
lypinator
Date:
Wed Sep 16 01:11:49 2020 +0000
Revision:
0:bb348c97df44
Added PWM

Who changed what in which revision?

UserRevisionLine numberNew contents of line
lypinator 0:bb348c97df44 1 /**
lypinator 0:bb348c97df44 2 ******************************************************************************
lypinator 0:bb348c97df44 3 * @file stm32f4xx_ll_tim.c
lypinator 0:bb348c97df44 4 * @author MCD Application Team
lypinator 0:bb348c97df44 5 * @brief TIM LL module driver.
lypinator 0:bb348c97df44 6 ******************************************************************************
lypinator 0:bb348c97df44 7 * @attention
lypinator 0:bb348c97df44 8 *
lypinator 0:bb348c97df44 9 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
lypinator 0:bb348c97df44 10 *
lypinator 0:bb348c97df44 11 * Redistribution and use in source and binary forms, with or without modification,
lypinator 0:bb348c97df44 12 * are permitted provided that the following conditions are met:
lypinator 0:bb348c97df44 13 * 1. Redistributions of source code must retain the above copyright notice,
lypinator 0:bb348c97df44 14 * this list of conditions and the following disclaimer.
lypinator 0:bb348c97df44 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
lypinator 0:bb348c97df44 16 * this list of conditions and the following disclaimer in the documentation
lypinator 0:bb348c97df44 17 * and/or other materials provided with the distribution.
lypinator 0:bb348c97df44 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
lypinator 0:bb348c97df44 19 * may be used to endorse or promote products derived from this software
lypinator 0:bb348c97df44 20 * without specific prior written permission.
lypinator 0:bb348c97df44 21 *
lypinator 0:bb348c97df44 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
lypinator 0:bb348c97df44 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
lypinator 0:bb348c97df44 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
lypinator 0:bb348c97df44 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
lypinator 0:bb348c97df44 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
lypinator 0:bb348c97df44 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
lypinator 0:bb348c97df44 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
lypinator 0:bb348c97df44 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
lypinator 0:bb348c97df44 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
lypinator 0:bb348c97df44 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
lypinator 0:bb348c97df44 32 *
lypinator 0:bb348c97df44 33 ******************************************************************************
lypinator 0:bb348c97df44 34 */
lypinator 0:bb348c97df44 35 #if defined(USE_FULL_LL_DRIVER)
lypinator 0:bb348c97df44 36
lypinator 0:bb348c97df44 37 /* Includes ------------------------------------------------------------------*/
lypinator 0:bb348c97df44 38 #include "stm32f4xx_ll_tim.h"
lypinator 0:bb348c97df44 39 #include "stm32f4xx_ll_bus.h"
lypinator 0:bb348c97df44 40
lypinator 0:bb348c97df44 41 #ifdef USE_FULL_ASSERT
lypinator 0:bb348c97df44 42 #include "stm32_assert.h"
lypinator 0:bb348c97df44 43 #else
lypinator 0:bb348c97df44 44 #define assert_param(expr) ((void)0U)
lypinator 0:bb348c97df44 45 #endif
lypinator 0:bb348c97df44 46
lypinator 0:bb348c97df44 47 /** @addtogroup STM32F4xx_LL_Driver
lypinator 0:bb348c97df44 48 * @{
lypinator 0:bb348c97df44 49 */
lypinator 0:bb348c97df44 50
lypinator 0:bb348c97df44 51 #if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM6) || defined (TIM7) || defined (TIM8) || defined (TIM9) || defined (TIM10) || defined (TIM11) || defined (TIM12) || defined (TIM13) || defined (TIM14)
lypinator 0:bb348c97df44 52
lypinator 0:bb348c97df44 53 /** @addtogroup TIM_LL
lypinator 0:bb348c97df44 54 * @{
lypinator 0:bb348c97df44 55 */
lypinator 0:bb348c97df44 56
lypinator 0:bb348c97df44 57 /* Private types -------------------------------------------------------------*/
lypinator 0:bb348c97df44 58 /* Private variables ---------------------------------------------------------*/
lypinator 0:bb348c97df44 59 /* Private constants ---------------------------------------------------------*/
lypinator 0:bb348c97df44 60 /* Private macros ------------------------------------------------------------*/
lypinator 0:bb348c97df44 61 /** @addtogroup TIM_LL_Private_Macros
lypinator 0:bb348c97df44 62 * @{
lypinator 0:bb348c97df44 63 */
lypinator 0:bb348c97df44 64 #define IS_LL_TIM_COUNTERMODE(__VALUE__) (((__VALUE__) == LL_TIM_COUNTERMODE_UP) \
lypinator 0:bb348c97df44 65 || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \
lypinator 0:bb348c97df44 66 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \
lypinator 0:bb348c97df44 67 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \
lypinator 0:bb348c97df44 68 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN))
lypinator 0:bb348c97df44 69
lypinator 0:bb348c97df44 70 #define IS_LL_TIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \
lypinator 0:bb348c97df44 71 || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \
lypinator 0:bb348c97df44 72 || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4))
lypinator 0:bb348c97df44 73
lypinator 0:bb348c97df44 74 #define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \
lypinator 0:bb348c97df44 75 || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \
lypinator 0:bb348c97df44 76 || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \
lypinator 0:bb348c97df44 77 || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \
lypinator 0:bb348c97df44 78 || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \
lypinator 0:bb348c97df44 79 || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \
lypinator 0:bb348c97df44 80 || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \
lypinator 0:bb348c97df44 81 || ((__VALUE__) == LL_TIM_OCMODE_PWM2))
lypinator 0:bb348c97df44 82
lypinator 0:bb348c97df44 83 #define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \
lypinator 0:bb348c97df44 84 || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE))
lypinator 0:bb348c97df44 85
lypinator 0:bb348c97df44 86 #define IS_LL_TIM_OCPOLARITY(__VALUE__) (((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \
lypinator 0:bb348c97df44 87 || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW))
lypinator 0:bb348c97df44 88
lypinator 0:bb348c97df44 89 #define IS_LL_TIM_OCIDLESTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCIDLESTATE_LOW) \
lypinator 0:bb348c97df44 90 || ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH))
lypinator 0:bb348c97df44 91
lypinator 0:bb348c97df44 92 #define IS_LL_TIM_ACTIVEINPUT(__VALUE__) (((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \
lypinator 0:bb348c97df44 93 || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \
lypinator 0:bb348c97df44 94 || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC))
lypinator 0:bb348c97df44 95
lypinator 0:bb348c97df44 96 #define IS_LL_TIM_ICPSC(__VALUE__) (((__VALUE__) == LL_TIM_ICPSC_DIV1) \
lypinator 0:bb348c97df44 97 || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \
lypinator 0:bb348c97df44 98 || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \
lypinator 0:bb348c97df44 99 || ((__VALUE__) == LL_TIM_ICPSC_DIV8))
lypinator 0:bb348c97df44 100
lypinator 0:bb348c97df44 101 #define IS_LL_TIM_IC_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \
lypinator 0:bb348c97df44 102 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \
lypinator 0:bb348c97df44 103 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \
lypinator 0:bb348c97df44 104 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \
lypinator 0:bb348c97df44 105 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \
lypinator 0:bb348c97df44 106 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \
lypinator 0:bb348c97df44 107 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \
lypinator 0:bb348c97df44 108 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \
lypinator 0:bb348c97df44 109 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \
lypinator 0:bb348c97df44 110 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \
lypinator 0:bb348c97df44 111 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \
lypinator 0:bb348c97df44 112 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \
lypinator 0:bb348c97df44 113 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \
lypinator 0:bb348c97df44 114 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \
lypinator 0:bb348c97df44 115 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \
lypinator 0:bb348c97df44 116 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8))
lypinator 0:bb348c97df44 117
lypinator 0:bb348c97df44 118 #define IS_LL_TIM_IC_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
lypinator 0:bb348c97df44 119 || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) \
lypinator 0:bb348c97df44 120 || ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE))
lypinator 0:bb348c97df44 121
lypinator 0:bb348c97df44 122 #define IS_LL_TIM_ENCODERMODE(__VALUE__) (((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \
lypinator 0:bb348c97df44 123 || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \
lypinator 0:bb348c97df44 124 || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12))
lypinator 0:bb348c97df44 125
lypinator 0:bb348c97df44 126 #define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
lypinator 0:bb348c97df44 127 || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING))
lypinator 0:bb348c97df44 128
lypinator 0:bb348c97df44 129 #define IS_LL_TIM_OSSR_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSR_DISABLE) \
lypinator 0:bb348c97df44 130 || ((__VALUE__) == LL_TIM_OSSR_ENABLE))
lypinator 0:bb348c97df44 131
lypinator 0:bb348c97df44 132 #define IS_LL_TIM_OSSI_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSI_DISABLE) \
lypinator 0:bb348c97df44 133 || ((__VALUE__) == LL_TIM_OSSI_ENABLE))
lypinator 0:bb348c97df44 134
lypinator 0:bb348c97df44 135 #define IS_LL_TIM_LOCK_LEVEL(__VALUE__) (((__VALUE__) == LL_TIM_LOCKLEVEL_OFF) \
lypinator 0:bb348c97df44 136 || ((__VALUE__) == LL_TIM_LOCKLEVEL_1) \
lypinator 0:bb348c97df44 137 || ((__VALUE__) == LL_TIM_LOCKLEVEL_2) \
lypinator 0:bb348c97df44 138 || ((__VALUE__) == LL_TIM_LOCKLEVEL_3))
lypinator 0:bb348c97df44 139
lypinator 0:bb348c97df44 140 #define IS_LL_TIM_BREAK_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_DISABLE) \
lypinator 0:bb348c97df44 141 || ((__VALUE__) == LL_TIM_BREAK_ENABLE))
lypinator 0:bb348c97df44 142
lypinator 0:bb348c97df44 143 #define IS_LL_TIM_BREAK_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_POLARITY_LOW) \
lypinator 0:bb348c97df44 144 || ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH))
lypinator 0:bb348c97df44 145
lypinator 0:bb348c97df44 146 #define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \
lypinator 0:bb348c97df44 147 || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE))
lypinator 0:bb348c97df44 148 /**
lypinator 0:bb348c97df44 149 * @}
lypinator 0:bb348c97df44 150 */
lypinator 0:bb348c97df44 151
lypinator 0:bb348c97df44 152
lypinator 0:bb348c97df44 153 /* Private function prototypes -----------------------------------------------*/
lypinator 0:bb348c97df44 154 /** @defgroup TIM_LL_Private_Functions TIM Private Functions
lypinator 0:bb348c97df44 155 * @{
lypinator 0:bb348c97df44 156 */
lypinator 0:bb348c97df44 157 static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
lypinator 0:bb348c97df44 158 static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
lypinator 0:bb348c97df44 159 static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
lypinator 0:bb348c97df44 160 static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
lypinator 0:bb348c97df44 161 static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
lypinator 0:bb348c97df44 162 static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
lypinator 0:bb348c97df44 163 static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
lypinator 0:bb348c97df44 164 static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
lypinator 0:bb348c97df44 165 /**
lypinator 0:bb348c97df44 166 * @}
lypinator 0:bb348c97df44 167 */
lypinator 0:bb348c97df44 168
lypinator 0:bb348c97df44 169 /* Exported functions --------------------------------------------------------*/
lypinator 0:bb348c97df44 170 /** @addtogroup TIM_LL_Exported_Functions
lypinator 0:bb348c97df44 171 * @{
lypinator 0:bb348c97df44 172 */
lypinator 0:bb348c97df44 173
lypinator 0:bb348c97df44 174 /** @addtogroup TIM_LL_EF_Init
lypinator 0:bb348c97df44 175 * @{
lypinator 0:bb348c97df44 176 */
lypinator 0:bb348c97df44 177
lypinator 0:bb348c97df44 178 /**
lypinator 0:bb348c97df44 179 * @brief Set TIMx registers to their reset values.
lypinator 0:bb348c97df44 180 * @param TIMx Timer instance
lypinator 0:bb348c97df44 181 * @retval An ErrorStatus enumeration value:
lypinator 0:bb348c97df44 182 * - SUCCESS: TIMx registers are de-initialized
lypinator 0:bb348c97df44 183 * - ERROR: invalid TIMx instance
lypinator 0:bb348c97df44 184 */
lypinator 0:bb348c97df44 185 ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx)
lypinator 0:bb348c97df44 186 {
lypinator 0:bb348c97df44 187 ErrorStatus result = SUCCESS;
lypinator 0:bb348c97df44 188
lypinator 0:bb348c97df44 189 /* Check the parameters */
lypinator 0:bb348c97df44 190 assert_param(IS_TIM_INSTANCE(TIMx));
lypinator 0:bb348c97df44 191
lypinator 0:bb348c97df44 192 if (TIMx == TIM1)
lypinator 0:bb348c97df44 193 {
lypinator 0:bb348c97df44 194 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM1);
lypinator 0:bb348c97df44 195 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM1);
lypinator 0:bb348c97df44 196 }
lypinator 0:bb348c97df44 197 #if defined(TIM2)
lypinator 0:bb348c97df44 198 else if (TIMx == TIM2)
lypinator 0:bb348c97df44 199 {
lypinator 0:bb348c97df44 200 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2);
lypinator 0:bb348c97df44 201 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2);
lypinator 0:bb348c97df44 202 }
lypinator 0:bb348c97df44 203 #endif
lypinator 0:bb348c97df44 204 #if defined(TIM3)
lypinator 0:bb348c97df44 205 else if (TIMx == TIM3)
lypinator 0:bb348c97df44 206 {
lypinator 0:bb348c97df44 207 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM3);
lypinator 0:bb348c97df44 208 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3);
lypinator 0:bb348c97df44 209 }
lypinator 0:bb348c97df44 210 #endif
lypinator 0:bb348c97df44 211 #if defined(TIM4)
lypinator 0:bb348c97df44 212 else if (TIMx == TIM4)
lypinator 0:bb348c97df44 213 {
lypinator 0:bb348c97df44 214 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM4);
lypinator 0:bb348c97df44 215 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM4);
lypinator 0:bb348c97df44 216 }
lypinator 0:bb348c97df44 217 #endif
lypinator 0:bb348c97df44 218 #if defined(TIM5)
lypinator 0:bb348c97df44 219 else if (TIMx == TIM5)
lypinator 0:bb348c97df44 220 {
lypinator 0:bb348c97df44 221 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM5);
lypinator 0:bb348c97df44 222 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM5);
lypinator 0:bb348c97df44 223 }
lypinator 0:bb348c97df44 224 #endif
lypinator 0:bb348c97df44 225 #if defined(TIM6)
lypinator 0:bb348c97df44 226 else if (TIMx == TIM6)
lypinator 0:bb348c97df44 227 {
lypinator 0:bb348c97df44 228 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM6);
lypinator 0:bb348c97df44 229 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM6);
lypinator 0:bb348c97df44 230 }
lypinator 0:bb348c97df44 231 #endif
lypinator 0:bb348c97df44 232 #if defined (TIM7)
lypinator 0:bb348c97df44 233 else if (TIMx == TIM7)
lypinator 0:bb348c97df44 234 {
lypinator 0:bb348c97df44 235 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM7);
lypinator 0:bb348c97df44 236 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM7);
lypinator 0:bb348c97df44 237 }
lypinator 0:bb348c97df44 238 #endif
lypinator 0:bb348c97df44 239 #if defined(TIM8)
lypinator 0:bb348c97df44 240 else if (TIMx == TIM8)
lypinator 0:bb348c97df44 241 {
lypinator 0:bb348c97df44 242 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM8);
lypinator 0:bb348c97df44 243 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM8);
lypinator 0:bb348c97df44 244 }
lypinator 0:bb348c97df44 245 #endif
lypinator 0:bb348c97df44 246 #if defined(TIM9)
lypinator 0:bb348c97df44 247 else if (TIMx == TIM9)
lypinator 0:bb348c97df44 248 {
lypinator 0:bb348c97df44 249 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM9);
lypinator 0:bb348c97df44 250 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM9);
lypinator 0:bb348c97df44 251 }
lypinator 0:bb348c97df44 252 #endif
lypinator 0:bb348c97df44 253 #if defined(TIM10)
lypinator 0:bb348c97df44 254 else if (TIMx == TIM10)
lypinator 0:bb348c97df44 255 {
lypinator 0:bb348c97df44 256 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM10);
lypinator 0:bb348c97df44 257 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM10);
lypinator 0:bb348c97df44 258 }
lypinator 0:bb348c97df44 259 #endif
lypinator 0:bb348c97df44 260 #if defined(TIM11)
lypinator 0:bb348c97df44 261 else if (TIMx == TIM11)
lypinator 0:bb348c97df44 262 {
lypinator 0:bb348c97df44 263 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM11);
lypinator 0:bb348c97df44 264 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM11);
lypinator 0:bb348c97df44 265 }
lypinator 0:bb348c97df44 266 #endif
lypinator 0:bb348c97df44 267 #if defined(TIM12)
lypinator 0:bb348c97df44 268 else if (TIMx == TIM12)
lypinator 0:bb348c97df44 269 {
lypinator 0:bb348c97df44 270 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM12);
lypinator 0:bb348c97df44 271 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM12);
lypinator 0:bb348c97df44 272 }
lypinator 0:bb348c97df44 273 #endif
lypinator 0:bb348c97df44 274 #if defined(TIM13)
lypinator 0:bb348c97df44 275 else if (TIMx == TIM13)
lypinator 0:bb348c97df44 276 {
lypinator 0:bb348c97df44 277 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM13);
lypinator 0:bb348c97df44 278 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM13);
lypinator 0:bb348c97df44 279 }
lypinator 0:bb348c97df44 280 #endif
lypinator 0:bb348c97df44 281 #if defined(TIM14)
lypinator 0:bb348c97df44 282 else if (TIMx == TIM14)
lypinator 0:bb348c97df44 283 {
lypinator 0:bb348c97df44 284 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM14);
lypinator 0:bb348c97df44 285 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM14);
lypinator 0:bb348c97df44 286 }
lypinator 0:bb348c97df44 287 #endif
lypinator 0:bb348c97df44 288 else
lypinator 0:bb348c97df44 289 {
lypinator 0:bb348c97df44 290 result = ERROR;
lypinator 0:bb348c97df44 291 }
lypinator 0:bb348c97df44 292
lypinator 0:bb348c97df44 293 return result;
lypinator 0:bb348c97df44 294 }
lypinator 0:bb348c97df44 295
lypinator 0:bb348c97df44 296 /**
lypinator 0:bb348c97df44 297 * @brief Set the fields of the time base unit configuration data structure
lypinator 0:bb348c97df44 298 * to their default values.
lypinator 0:bb348c97df44 299 * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (time base unit configuration data structure)
lypinator 0:bb348c97df44 300 * @retval None
lypinator 0:bb348c97df44 301 */
lypinator 0:bb348c97df44 302 void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct)
lypinator 0:bb348c97df44 303 {
lypinator 0:bb348c97df44 304 /* Set the default configuration */
lypinator 0:bb348c97df44 305 TIM_InitStruct->Prescaler = (uint16_t)0x0000U;
lypinator 0:bb348c97df44 306 TIM_InitStruct->CounterMode = LL_TIM_COUNTERMODE_UP;
lypinator 0:bb348c97df44 307 TIM_InitStruct->Autoreload = 0xFFFFFFFFU;
lypinator 0:bb348c97df44 308 TIM_InitStruct->ClockDivision = LL_TIM_CLOCKDIVISION_DIV1;
lypinator 0:bb348c97df44 309 TIM_InitStruct->RepetitionCounter = (uint8_t)0x00U;
lypinator 0:bb348c97df44 310 }
lypinator 0:bb348c97df44 311
lypinator 0:bb348c97df44 312 /**
lypinator 0:bb348c97df44 313 * @brief Configure the TIMx time base unit.
lypinator 0:bb348c97df44 314 * @param TIMx Timer Instance
lypinator 0:bb348c97df44 315 * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (TIMx time base unit configuration data structure)
lypinator 0:bb348c97df44 316 * @retval An ErrorStatus enumeration value:
lypinator 0:bb348c97df44 317 * - SUCCESS: TIMx registers are de-initialized
lypinator 0:bb348c97df44 318 * - ERROR: not applicable
lypinator 0:bb348c97df44 319 */
lypinator 0:bb348c97df44 320 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct)
lypinator 0:bb348c97df44 321 {
lypinator 0:bb348c97df44 322 uint32_t tmpcr1 = 0U;
lypinator 0:bb348c97df44 323
lypinator 0:bb348c97df44 324 /* Check the parameters */
lypinator 0:bb348c97df44 325 assert_param(IS_TIM_INSTANCE(TIMx));
lypinator 0:bb348c97df44 326 assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode));
lypinator 0:bb348c97df44 327 assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision));
lypinator 0:bb348c97df44 328
lypinator 0:bb348c97df44 329 tmpcr1 = LL_TIM_ReadReg(TIMx, CR1);
lypinator 0:bb348c97df44 330
lypinator 0:bb348c97df44 331 if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
lypinator 0:bb348c97df44 332 {
lypinator 0:bb348c97df44 333 /* Select the Counter Mode */
lypinator 0:bb348c97df44 334 MODIFY_REG(tmpcr1, (TIM_CR1_DIR | TIM_CR1_CMS), TIM_InitStruct->CounterMode);
lypinator 0:bb348c97df44 335 }
lypinator 0:bb348c97df44 336
lypinator 0:bb348c97df44 337 if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
lypinator 0:bb348c97df44 338 {
lypinator 0:bb348c97df44 339 /* Set the clock division */
lypinator 0:bb348c97df44 340 MODIFY_REG(tmpcr1, TIM_CR1_CKD, TIM_InitStruct->ClockDivision);
lypinator 0:bb348c97df44 341 }
lypinator 0:bb348c97df44 342
lypinator 0:bb348c97df44 343 /* Write to TIMx CR1 */
lypinator 0:bb348c97df44 344 LL_TIM_WriteReg(TIMx, CR1, tmpcr1);
lypinator 0:bb348c97df44 345
lypinator 0:bb348c97df44 346 /* Set the Autoreload value */
lypinator 0:bb348c97df44 347 LL_TIM_SetAutoReload(TIMx, TIM_InitStruct->Autoreload);
lypinator 0:bb348c97df44 348
lypinator 0:bb348c97df44 349 /* Set the Prescaler value */
lypinator 0:bb348c97df44 350 LL_TIM_SetPrescaler(TIMx, TIM_InitStruct->Prescaler);
lypinator 0:bb348c97df44 351
lypinator 0:bb348c97df44 352 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
lypinator 0:bb348c97df44 353 {
lypinator 0:bb348c97df44 354 /* Set the Repetition Counter value */
lypinator 0:bb348c97df44 355 LL_TIM_SetRepetitionCounter(TIMx, TIM_InitStruct->RepetitionCounter);
lypinator 0:bb348c97df44 356 }
lypinator 0:bb348c97df44 357
lypinator 0:bb348c97df44 358 /* Generate an update event to reload the Prescaler
lypinator 0:bb348c97df44 359 and the repetition counter value (if applicable) immediately */
lypinator 0:bb348c97df44 360 LL_TIM_GenerateEvent_UPDATE(TIMx);
lypinator 0:bb348c97df44 361
lypinator 0:bb348c97df44 362 return SUCCESS;
lypinator 0:bb348c97df44 363 }
lypinator 0:bb348c97df44 364
lypinator 0:bb348c97df44 365 /**
lypinator 0:bb348c97df44 366 * @brief Set the fields of the TIMx output channel configuration data
lypinator 0:bb348c97df44 367 * structure to their default values.
lypinator 0:bb348c97df44 368 * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (the output channel configuration data structure)
lypinator 0:bb348c97df44 369 * @retval None
lypinator 0:bb348c97df44 370 */
lypinator 0:bb348c97df44 371 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
lypinator 0:bb348c97df44 372 {
lypinator 0:bb348c97df44 373 /* Set the default configuration */
lypinator 0:bb348c97df44 374 TIM_OC_InitStruct->OCMode = LL_TIM_OCMODE_FROZEN;
lypinator 0:bb348c97df44 375 TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE;
lypinator 0:bb348c97df44 376 TIM_OC_InitStruct->OCNState = LL_TIM_OCSTATE_DISABLE;
lypinator 0:bb348c97df44 377 TIM_OC_InitStruct->CompareValue = 0x00000000U;
lypinator 0:bb348c97df44 378 TIM_OC_InitStruct->OCPolarity = LL_TIM_OCPOLARITY_HIGH;
lypinator 0:bb348c97df44 379 TIM_OC_InitStruct->OCNPolarity = LL_TIM_OCPOLARITY_HIGH;
lypinator 0:bb348c97df44 380 TIM_OC_InitStruct->OCIdleState = LL_TIM_OCIDLESTATE_LOW;
lypinator 0:bb348c97df44 381 TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW;
lypinator 0:bb348c97df44 382 }
lypinator 0:bb348c97df44 383
lypinator 0:bb348c97df44 384 /**
lypinator 0:bb348c97df44 385 * @brief Configure the TIMx output channel.
lypinator 0:bb348c97df44 386 * @param TIMx Timer Instance
lypinator 0:bb348c97df44 387 * @param Channel This parameter can be one of the following values:
lypinator 0:bb348c97df44 388 * @arg @ref LL_TIM_CHANNEL_CH1
lypinator 0:bb348c97df44 389 * @arg @ref LL_TIM_CHANNEL_CH2
lypinator 0:bb348c97df44 390 * @arg @ref LL_TIM_CHANNEL_CH3
lypinator 0:bb348c97df44 391 * @arg @ref LL_TIM_CHANNEL_CH4
lypinator 0:bb348c97df44 392 * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration data structure)
lypinator 0:bb348c97df44 393 * @retval An ErrorStatus enumeration value:
lypinator 0:bb348c97df44 394 * - SUCCESS: TIMx output channel is initialized
lypinator 0:bb348c97df44 395 * - ERROR: TIMx output channel is not initialized
lypinator 0:bb348c97df44 396 */
lypinator 0:bb348c97df44 397 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
lypinator 0:bb348c97df44 398 {
lypinator 0:bb348c97df44 399 ErrorStatus result = ERROR;
lypinator 0:bb348c97df44 400
lypinator 0:bb348c97df44 401 switch (Channel)
lypinator 0:bb348c97df44 402 {
lypinator 0:bb348c97df44 403 case LL_TIM_CHANNEL_CH1:
lypinator 0:bb348c97df44 404 result = OC1Config(TIMx, TIM_OC_InitStruct);
lypinator 0:bb348c97df44 405 break;
lypinator 0:bb348c97df44 406 case LL_TIM_CHANNEL_CH2:
lypinator 0:bb348c97df44 407 result = OC2Config(TIMx, TIM_OC_InitStruct);
lypinator 0:bb348c97df44 408 break;
lypinator 0:bb348c97df44 409 case LL_TIM_CHANNEL_CH3:
lypinator 0:bb348c97df44 410 result = OC3Config(TIMx, TIM_OC_InitStruct);
lypinator 0:bb348c97df44 411 break;
lypinator 0:bb348c97df44 412 case LL_TIM_CHANNEL_CH4:
lypinator 0:bb348c97df44 413 result = OC4Config(TIMx, TIM_OC_InitStruct);
lypinator 0:bb348c97df44 414 break;
lypinator 0:bb348c97df44 415 default:
lypinator 0:bb348c97df44 416 break;
lypinator 0:bb348c97df44 417 }
lypinator 0:bb348c97df44 418
lypinator 0:bb348c97df44 419 return result;
lypinator 0:bb348c97df44 420 }
lypinator 0:bb348c97df44 421
lypinator 0:bb348c97df44 422 /**
lypinator 0:bb348c97df44 423 * @brief Set the fields of the TIMx input channel configuration data
lypinator 0:bb348c97df44 424 * structure to their default values.
lypinator 0:bb348c97df44 425 * @param TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration data structure)
lypinator 0:bb348c97df44 426 * @retval None
lypinator 0:bb348c97df44 427 */
lypinator 0:bb348c97df44 428 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
lypinator 0:bb348c97df44 429 {
lypinator 0:bb348c97df44 430 /* Set the default configuration */
lypinator 0:bb348c97df44 431 TIM_ICInitStruct->ICPolarity = LL_TIM_IC_POLARITY_RISING;
lypinator 0:bb348c97df44 432 TIM_ICInitStruct->ICActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
lypinator 0:bb348c97df44 433 TIM_ICInitStruct->ICPrescaler = LL_TIM_ICPSC_DIV1;
lypinator 0:bb348c97df44 434 TIM_ICInitStruct->ICFilter = LL_TIM_IC_FILTER_FDIV1;
lypinator 0:bb348c97df44 435 }
lypinator 0:bb348c97df44 436
lypinator 0:bb348c97df44 437 /**
lypinator 0:bb348c97df44 438 * @brief Configure the TIMx input channel.
lypinator 0:bb348c97df44 439 * @param TIMx Timer Instance
lypinator 0:bb348c97df44 440 * @param Channel This parameter can be one of the following values:
lypinator 0:bb348c97df44 441 * @arg @ref LL_TIM_CHANNEL_CH1
lypinator 0:bb348c97df44 442 * @arg @ref LL_TIM_CHANNEL_CH2
lypinator 0:bb348c97df44 443 * @arg @ref LL_TIM_CHANNEL_CH3
lypinator 0:bb348c97df44 444 * @arg @ref LL_TIM_CHANNEL_CH4
lypinator 0:bb348c97df44 445 * @param TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data structure)
lypinator 0:bb348c97df44 446 * @retval An ErrorStatus enumeration value:
lypinator 0:bb348c97df44 447 * - SUCCESS: TIMx output channel is initialized
lypinator 0:bb348c97df44 448 * - ERROR: TIMx output channel is not initialized
lypinator 0:bb348c97df44 449 */
lypinator 0:bb348c97df44 450 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct)
lypinator 0:bb348c97df44 451 {
lypinator 0:bb348c97df44 452 ErrorStatus result = ERROR;
lypinator 0:bb348c97df44 453
lypinator 0:bb348c97df44 454 switch (Channel)
lypinator 0:bb348c97df44 455 {
lypinator 0:bb348c97df44 456 case LL_TIM_CHANNEL_CH1:
lypinator 0:bb348c97df44 457 result = IC1Config(TIMx, TIM_IC_InitStruct);
lypinator 0:bb348c97df44 458 break;
lypinator 0:bb348c97df44 459 case LL_TIM_CHANNEL_CH2:
lypinator 0:bb348c97df44 460 result = IC2Config(TIMx, TIM_IC_InitStruct);
lypinator 0:bb348c97df44 461 break;
lypinator 0:bb348c97df44 462 case LL_TIM_CHANNEL_CH3:
lypinator 0:bb348c97df44 463 result = IC3Config(TIMx, TIM_IC_InitStruct);
lypinator 0:bb348c97df44 464 break;
lypinator 0:bb348c97df44 465 case LL_TIM_CHANNEL_CH4:
lypinator 0:bb348c97df44 466 result = IC4Config(TIMx, TIM_IC_InitStruct);
lypinator 0:bb348c97df44 467 break;
lypinator 0:bb348c97df44 468 default:
lypinator 0:bb348c97df44 469 break;
lypinator 0:bb348c97df44 470 }
lypinator 0:bb348c97df44 471
lypinator 0:bb348c97df44 472 return result;
lypinator 0:bb348c97df44 473 }
lypinator 0:bb348c97df44 474
lypinator 0:bb348c97df44 475 /**
lypinator 0:bb348c97df44 476 * @brief Fills each TIM_EncoderInitStruct field with its default value
lypinator 0:bb348c97df44 477 * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface configuration data structure)
lypinator 0:bb348c97df44 478 * @retval None
lypinator 0:bb348c97df44 479 */
lypinator 0:bb348c97df44 480 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
lypinator 0:bb348c97df44 481 {
lypinator 0:bb348c97df44 482 /* Set the default configuration */
lypinator 0:bb348c97df44 483 TIM_EncoderInitStruct->EncoderMode = LL_TIM_ENCODERMODE_X2_TI1;
lypinator 0:bb348c97df44 484 TIM_EncoderInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING;
lypinator 0:bb348c97df44 485 TIM_EncoderInitStruct->IC1ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
lypinator 0:bb348c97df44 486 TIM_EncoderInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1;
lypinator 0:bb348c97df44 487 TIM_EncoderInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1;
lypinator 0:bb348c97df44 488 TIM_EncoderInitStruct->IC2Polarity = LL_TIM_IC_POLARITY_RISING;
lypinator 0:bb348c97df44 489 TIM_EncoderInitStruct->IC2ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
lypinator 0:bb348c97df44 490 TIM_EncoderInitStruct->IC2Prescaler = LL_TIM_ICPSC_DIV1;
lypinator 0:bb348c97df44 491 TIM_EncoderInitStruct->IC2Filter = LL_TIM_IC_FILTER_FDIV1;
lypinator 0:bb348c97df44 492 }
lypinator 0:bb348c97df44 493
lypinator 0:bb348c97df44 494 /**
lypinator 0:bb348c97df44 495 * @brief Configure the encoder interface of the timer instance.
lypinator 0:bb348c97df44 496 * @param TIMx Timer Instance
lypinator 0:bb348c97df44 497 * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface configuration data structure)
lypinator 0:bb348c97df44 498 * @retval An ErrorStatus enumeration value:
lypinator 0:bb348c97df44 499 * - SUCCESS: TIMx registers are de-initialized
lypinator 0:bb348c97df44 500 * - ERROR: not applicable
lypinator 0:bb348c97df44 501 */
lypinator 0:bb348c97df44 502 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
lypinator 0:bb348c97df44 503 {
lypinator 0:bb348c97df44 504 uint32_t tmpccmr1 = 0U;
lypinator 0:bb348c97df44 505 uint32_t tmpccer = 0U;
lypinator 0:bb348c97df44 506
lypinator 0:bb348c97df44 507 /* Check the parameters */
lypinator 0:bb348c97df44 508 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx));
lypinator 0:bb348c97df44 509 assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode));
lypinator 0:bb348c97df44 510 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity));
lypinator 0:bb348c97df44 511 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput));
lypinator 0:bb348c97df44 512 assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler));
lypinator 0:bb348c97df44 513 assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC1Filter));
lypinator 0:bb348c97df44 514 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC2Polarity));
lypinator 0:bb348c97df44 515 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC2ActiveInput));
lypinator 0:bb348c97df44 516 assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC2Prescaler));
lypinator 0:bb348c97df44 517 assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC2Filter));
lypinator 0:bb348c97df44 518
lypinator 0:bb348c97df44 519 /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
lypinator 0:bb348c97df44 520 TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
lypinator 0:bb348c97df44 521
lypinator 0:bb348c97df44 522 /* Get the TIMx CCMR1 register value */
lypinator 0:bb348c97df44 523 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
lypinator 0:bb348c97df44 524
lypinator 0:bb348c97df44 525 /* Get the TIMx CCER register value */
lypinator 0:bb348c97df44 526 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
lypinator 0:bb348c97df44 527
lypinator 0:bb348c97df44 528 /* Configure TI1 */
lypinator 0:bb348c97df44 529 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC);
lypinator 0:bb348c97df44 530 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1ActiveInput >> 16U);
lypinator 0:bb348c97df44 531 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U);
lypinator 0:bb348c97df44 532 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U);
lypinator 0:bb348c97df44 533
lypinator 0:bb348c97df44 534 /* Configure TI2 */
lypinator 0:bb348c97df44 535 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC);
lypinator 0:bb348c97df44 536 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2ActiveInput >> 8U);
lypinator 0:bb348c97df44 537 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U);
lypinator 0:bb348c97df44 538 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U);
lypinator 0:bb348c97df44 539
lypinator 0:bb348c97df44 540 /* Set TI1 and TI2 polarity and enable TI1 and TI2 */
lypinator 0:bb348c97df44 541 tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
lypinator 0:bb348c97df44 542 tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity);
lypinator 0:bb348c97df44 543 tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U);
lypinator 0:bb348c97df44 544 tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
lypinator 0:bb348c97df44 545
lypinator 0:bb348c97df44 546 /* Set encoder mode */
lypinator 0:bb348c97df44 547 LL_TIM_SetEncoderMode(TIMx, TIM_EncoderInitStruct->EncoderMode);
lypinator 0:bb348c97df44 548
lypinator 0:bb348c97df44 549 /* Write to TIMx CCMR1 */
lypinator 0:bb348c97df44 550 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
lypinator 0:bb348c97df44 551
lypinator 0:bb348c97df44 552 /* Write to TIMx CCER */
lypinator 0:bb348c97df44 553 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
lypinator 0:bb348c97df44 554
lypinator 0:bb348c97df44 555 return SUCCESS;
lypinator 0:bb348c97df44 556 }
lypinator 0:bb348c97df44 557
lypinator 0:bb348c97df44 558 /**
lypinator 0:bb348c97df44 559 * @brief Set the fields of the TIMx Hall sensor interface configuration data
lypinator 0:bb348c97df44 560 * structure to their default values.
lypinator 0:bb348c97df44 561 * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (HALL sensor interface configuration data structure)
lypinator 0:bb348c97df44 562 * @retval None
lypinator 0:bb348c97df44 563 */
lypinator 0:bb348c97df44 564 void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
lypinator 0:bb348c97df44 565 {
lypinator 0:bb348c97df44 566 /* Set the default configuration */
lypinator 0:bb348c97df44 567 TIM_HallSensorInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING;
lypinator 0:bb348c97df44 568 TIM_HallSensorInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1;
lypinator 0:bb348c97df44 569 TIM_HallSensorInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1;
lypinator 0:bb348c97df44 570 TIM_HallSensorInitStruct->CommutationDelay = 0U;
lypinator 0:bb348c97df44 571 }
lypinator 0:bb348c97df44 572
lypinator 0:bb348c97df44 573 /**
lypinator 0:bb348c97df44 574 * @brief Configure the Hall sensor interface of the timer instance.
lypinator 0:bb348c97df44 575 * @note TIMx CH1, CH2 and CH3 inputs connected through a XOR
lypinator 0:bb348c97df44 576 * to the TI1 input channel
lypinator 0:bb348c97df44 577 * @note TIMx slave mode controller is configured in reset mode.
lypinator 0:bb348c97df44 578 Selected internal trigger is TI1F_ED.
lypinator 0:bb348c97df44 579 * @note Channel 1 is configured as input, IC1 is mapped on TRC.
lypinator 0:bb348c97df44 580 * @note Captured value stored in TIMx_CCR1 correspond to the time elapsed
lypinator 0:bb348c97df44 581 * between 2 changes on the inputs. It gives information about motor speed.
lypinator 0:bb348c97df44 582 * @note Channel 2 is configured in output PWM 2 mode.
lypinator 0:bb348c97df44 583 * @note Compare value stored in TIMx_CCR2 corresponds to the commutation delay.
lypinator 0:bb348c97df44 584 * @note OC2REF is selected as trigger output on TRGO.
lypinator 0:bb348c97df44 585 * @note LL_TIM_IC_POLARITY_BOTHEDGE must not be used for TI1 when it is used
lypinator 0:bb348c97df44 586 * when TIMx operates in Hall sensor interface mode.
lypinator 0:bb348c97df44 587 * @param TIMx Timer Instance
lypinator 0:bb348c97df44 588 * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor interface configuration data structure)
lypinator 0:bb348c97df44 589 * @retval An ErrorStatus enumeration value:
lypinator 0:bb348c97df44 590 * - SUCCESS: TIMx registers are de-initialized
lypinator 0:bb348c97df44 591 * - ERROR: not applicable
lypinator 0:bb348c97df44 592 */
lypinator 0:bb348c97df44 593 ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
lypinator 0:bb348c97df44 594 {
lypinator 0:bb348c97df44 595 uint32_t tmpcr2 = 0U;
lypinator 0:bb348c97df44 596 uint32_t tmpccmr1 = 0U;
lypinator 0:bb348c97df44 597 uint32_t tmpccer = 0U;
lypinator 0:bb348c97df44 598 uint32_t tmpsmcr = 0U;
lypinator 0:bb348c97df44 599
lypinator 0:bb348c97df44 600 /* Check the parameters */
lypinator 0:bb348c97df44 601 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(TIMx));
lypinator 0:bb348c97df44 602 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_HallSensorInitStruct->IC1Polarity));
lypinator 0:bb348c97df44 603 assert_param(IS_LL_TIM_ICPSC(TIM_HallSensorInitStruct->IC1Prescaler));
lypinator 0:bb348c97df44 604 assert_param(IS_LL_TIM_IC_FILTER(TIM_HallSensorInitStruct->IC1Filter));
lypinator 0:bb348c97df44 605
lypinator 0:bb348c97df44 606 /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
lypinator 0:bb348c97df44 607 TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
lypinator 0:bb348c97df44 608
lypinator 0:bb348c97df44 609 /* Get the TIMx CR2 register value */
lypinator 0:bb348c97df44 610 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
lypinator 0:bb348c97df44 611
lypinator 0:bb348c97df44 612 /* Get the TIMx CCMR1 register value */
lypinator 0:bb348c97df44 613 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
lypinator 0:bb348c97df44 614
lypinator 0:bb348c97df44 615 /* Get the TIMx CCER register value */
lypinator 0:bb348c97df44 616 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
lypinator 0:bb348c97df44 617
lypinator 0:bb348c97df44 618 /* Get the TIMx SMCR register value */
lypinator 0:bb348c97df44 619 tmpsmcr = LL_TIM_ReadReg(TIMx, SMCR);
lypinator 0:bb348c97df44 620
lypinator 0:bb348c97df44 621 /* Connect TIMx_CH1, CH2 and CH3 pins to the TI1 input */
lypinator 0:bb348c97df44 622 tmpcr2 |= TIM_CR2_TI1S;
lypinator 0:bb348c97df44 623
lypinator 0:bb348c97df44 624 /* OC2REF signal is used as trigger output (TRGO) */
lypinator 0:bb348c97df44 625 tmpcr2 |= LL_TIM_TRGO_OC2REF;
lypinator 0:bb348c97df44 626
lypinator 0:bb348c97df44 627 /* Configure the slave mode controller */
lypinator 0:bb348c97df44 628 tmpsmcr &= (uint32_t)~(TIM_SMCR_TS | TIM_SMCR_SMS);
lypinator 0:bb348c97df44 629 tmpsmcr |= LL_TIM_TS_TI1F_ED;
lypinator 0:bb348c97df44 630 tmpsmcr |= LL_TIM_SLAVEMODE_RESET;
lypinator 0:bb348c97df44 631
lypinator 0:bb348c97df44 632 /* Configure input channel 1 */
lypinator 0:bb348c97df44 633 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC);
lypinator 0:bb348c97df44 634 tmpccmr1 |= (uint32_t)(LL_TIM_ACTIVEINPUT_TRC >> 16U);
lypinator 0:bb348c97df44 635 tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Filter >> 16U);
lypinator 0:bb348c97df44 636 tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Prescaler >> 16U);
lypinator 0:bb348c97df44 637
lypinator 0:bb348c97df44 638 /* Configure input channel 2 */
lypinator 0:bb348c97df44 639 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_OC2M | TIM_CCMR1_OC2FE | TIM_CCMR1_OC2PE | TIM_CCMR1_OC2CE);
lypinator 0:bb348c97df44 640 tmpccmr1 |= (uint32_t)(LL_TIM_OCMODE_PWM2 << 8U);
lypinator 0:bb348c97df44 641
lypinator 0:bb348c97df44 642 /* Set Channel 1 polarity and enable Channel 1 and Channel2 */
lypinator 0:bb348c97df44 643 tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
lypinator 0:bb348c97df44 644 tmpccer |= (uint32_t)(TIM_HallSensorInitStruct->IC1Polarity);
lypinator 0:bb348c97df44 645 tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
lypinator 0:bb348c97df44 646
lypinator 0:bb348c97df44 647 /* Write to TIMx CR2 */
lypinator 0:bb348c97df44 648 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
lypinator 0:bb348c97df44 649
lypinator 0:bb348c97df44 650 /* Write to TIMx SMCR */
lypinator 0:bb348c97df44 651 LL_TIM_WriteReg(TIMx, SMCR, tmpsmcr);
lypinator 0:bb348c97df44 652
lypinator 0:bb348c97df44 653 /* Write to TIMx CCMR1 */
lypinator 0:bb348c97df44 654 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
lypinator 0:bb348c97df44 655
lypinator 0:bb348c97df44 656 /* Write to TIMx CCER */
lypinator 0:bb348c97df44 657 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
lypinator 0:bb348c97df44 658
lypinator 0:bb348c97df44 659 /* Write to TIMx CCR2 */
lypinator 0:bb348c97df44 660 LL_TIM_OC_SetCompareCH2(TIMx, TIM_HallSensorInitStruct->CommutationDelay);
lypinator 0:bb348c97df44 661
lypinator 0:bb348c97df44 662 return SUCCESS;
lypinator 0:bb348c97df44 663 }
lypinator 0:bb348c97df44 664
lypinator 0:bb348c97df44 665 /**
lypinator 0:bb348c97df44 666 * @brief Set the fields of the Break and Dead Time configuration data structure
lypinator 0:bb348c97df44 667 * to their default values.
lypinator 0:bb348c97df44 668 * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure)
lypinator 0:bb348c97df44 669 * @retval None
lypinator 0:bb348c97df44 670 */
lypinator 0:bb348c97df44 671 void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
lypinator 0:bb348c97df44 672 {
lypinator 0:bb348c97df44 673 /* Set the default configuration */
lypinator 0:bb348c97df44 674 TIM_BDTRInitStruct->OSSRState = LL_TIM_OSSR_DISABLE;
lypinator 0:bb348c97df44 675 TIM_BDTRInitStruct->OSSIState = LL_TIM_OSSI_DISABLE;
lypinator 0:bb348c97df44 676 TIM_BDTRInitStruct->LockLevel = LL_TIM_LOCKLEVEL_OFF;
lypinator 0:bb348c97df44 677 TIM_BDTRInitStruct->DeadTime = (uint8_t)0x00U;
lypinator 0:bb348c97df44 678 TIM_BDTRInitStruct->BreakState = LL_TIM_BREAK_DISABLE;
lypinator 0:bb348c97df44 679 TIM_BDTRInitStruct->BreakPolarity = LL_TIM_BREAK_POLARITY_LOW;
lypinator 0:bb348c97df44 680 TIM_BDTRInitStruct->AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE;
lypinator 0:bb348c97df44 681 }
lypinator 0:bb348c97df44 682
lypinator 0:bb348c97df44 683 /**
lypinator 0:bb348c97df44 684 * @brief Configure the Break and Dead Time feature of the timer instance.
lypinator 0:bb348c97df44 685 * @note As the bits AOE, BKP, BKE, OSSR, OSSI and DTG[7:0] can be write-locked
lypinator 0:bb348c97df44 686 * depending on the LOCK configuration, it can be necessary to configure all of
lypinator 0:bb348c97df44 687 * them during the first write access to the TIMx_BDTR register.
lypinator 0:bb348c97df44 688 * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
lypinator 0:bb348c97df44 689 * a timer instance provides a break input.
lypinator 0:bb348c97df44 690 * @param TIMx Timer Instance
lypinator 0:bb348c97df44 691 * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure(Break and Dead Time configuration data structure)
lypinator 0:bb348c97df44 692 * @retval An ErrorStatus enumeration value:
lypinator 0:bb348c97df44 693 * - SUCCESS: Break and Dead Time is initialized
lypinator 0:bb348c97df44 694 * - ERROR: not applicable
lypinator 0:bb348c97df44 695 */
lypinator 0:bb348c97df44 696 ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
lypinator 0:bb348c97df44 697 {
lypinator 0:bb348c97df44 698 uint32_t tmpbdtr = 0;
lypinator 0:bb348c97df44 699
lypinator 0:bb348c97df44 700 /* Check the parameters */
lypinator 0:bb348c97df44 701 assert_param(IS_TIM_BREAK_INSTANCE(TIMx));
lypinator 0:bb348c97df44 702 assert_param(IS_LL_TIM_OSSR_STATE(TIM_BDTRInitStruct->OSSRState));
lypinator 0:bb348c97df44 703 assert_param(IS_LL_TIM_OSSI_STATE(TIM_BDTRInitStruct->OSSIState));
lypinator 0:bb348c97df44 704 assert_param(IS_LL_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->LockLevel));
lypinator 0:bb348c97df44 705 assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState));
lypinator 0:bb348c97df44 706 assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity));
lypinator 0:bb348c97df44 707 assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput));
lypinator 0:bb348c97df44 708
lypinator 0:bb348c97df44 709 /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
lypinator 0:bb348c97df44 710 the OSSI State, the dead time value and the Automatic Output Enable Bit */
lypinator 0:bb348c97df44 711
lypinator 0:bb348c97df44 712 /* Set the BDTR bits */
lypinator 0:bb348c97df44 713 MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime);
lypinator 0:bb348c97df44 714 MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel);
lypinator 0:bb348c97df44 715 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState);
lypinator 0:bb348c97df44 716 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState);
lypinator 0:bb348c97df44 717 MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState);
lypinator 0:bb348c97df44 718 MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity);
lypinator 0:bb348c97df44 719 MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput);
lypinator 0:bb348c97df44 720 MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, TIM_BDTRInitStruct->AutomaticOutput);
lypinator 0:bb348c97df44 721
lypinator 0:bb348c97df44 722 /* Set TIMx_BDTR */
lypinator 0:bb348c97df44 723 LL_TIM_WriteReg(TIMx, BDTR, tmpbdtr);
lypinator 0:bb348c97df44 724
lypinator 0:bb348c97df44 725 return SUCCESS;
lypinator 0:bb348c97df44 726 }
lypinator 0:bb348c97df44 727 /**
lypinator 0:bb348c97df44 728 * @}
lypinator 0:bb348c97df44 729 */
lypinator 0:bb348c97df44 730
lypinator 0:bb348c97df44 731 /**
lypinator 0:bb348c97df44 732 * @}
lypinator 0:bb348c97df44 733 */
lypinator 0:bb348c97df44 734
lypinator 0:bb348c97df44 735 /** @addtogroup TIM_LL_Private_Functions TIM Private Functions
lypinator 0:bb348c97df44 736 * @brief Private functions
lypinator 0:bb348c97df44 737 * @{
lypinator 0:bb348c97df44 738 */
lypinator 0:bb348c97df44 739 /**
lypinator 0:bb348c97df44 740 * @brief Configure the TIMx output channel 1.
lypinator 0:bb348c97df44 741 * @param TIMx Timer Instance
lypinator 0:bb348c97df44 742 * @param TIM_OCInitStruct pointer to the the TIMx output channel 1 configuration data structure
lypinator 0:bb348c97df44 743 * @retval An ErrorStatus enumeration value:
lypinator 0:bb348c97df44 744 * - SUCCESS: TIMx registers are de-initialized
lypinator 0:bb348c97df44 745 * - ERROR: not applicable
lypinator 0:bb348c97df44 746 */
lypinator 0:bb348c97df44 747 static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
lypinator 0:bb348c97df44 748 {
lypinator 0:bb348c97df44 749 uint32_t tmpccmr1 = 0U;
lypinator 0:bb348c97df44 750 uint32_t tmpccer = 0U;
lypinator 0:bb348c97df44 751 uint32_t tmpcr2 = 0U;
lypinator 0:bb348c97df44 752
lypinator 0:bb348c97df44 753 /* Check the parameters */
lypinator 0:bb348c97df44 754 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
lypinator 0:bb348c97df44 755 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
lypinator 0:bb348c97df44 756 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
lypinator 0:bb348c97df44 757 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
lypinator 0:bb348c97df44 758 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
lypinator 0:bb348c97df44 759 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
lypinator 0:bb348c97df44 760
lypinator 0:bb348c97df44 761 /* Disable the Channel 1: Reset the CC1E Bit */
lypinator 0:bb348c97df44 762 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E);
lypinator 0:bb348c97df44 763
lypinator 0:bb348c97df44 764 /* Get the TIMx CCER register value */
lypinator 0:bb348c97df44 765 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
lypinator 0:bb348c97df44 766
lypinator 0:bb348c97df44 767 /* Get the TIMx CR2 register value */
lypinator 0:bb348c97df44 768 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
lypinator 0:bb348c97df44 769
lypinator 0:bb348c97df44 770 /* Get the TIMx CCMR1 register value */
lypinator 0:bb348c97df44 771 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
lypinator 0:bb348c97df44 772
lypinator 0:bb348c97df44 773 /* Reset Capture/Compare selection Bits */
lypinator 0:bb348c97df44 774 CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC1S);
lypinator 0:bb348c97df44 775
lypinator 0:bb348c97df44 776 /* Set the Output Compare Mode */
lypinator 0:bb348c97df44 777 MODIFY_REG(tmpccmr1, TIM_CCMR1_OC1M, TIM_OCInitStruct->OCMode);
lypinator 0:bb348c97df44 778
lypinator 0:bb348c97df44 779 /* Set the Output Compare Polarity */
lypinator 0:bb348c97df44 780 MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity);
lypinator 0:bb348c97df44 781
lypinator 0:bb348c97df44 782 /* Set the Output State */
lypinator 0:bb348c97df44 783 MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState);
lypinator 0:bb348c97df44 784
lypinator 0:bb348c97df44 785 if (IS_TIM_BREAK_INSTANCE(TIMx))
lypinator 0:bb348c97df44 786 {
lypinator 0:bb348c97df44 787 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
lypinator 0:bb348c97df44 788 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
lypinator 0:bb348c97df44 789
lypinator 0:bb348c97df44 790 /* Set the complementary output Polarity */
lypinator 0:bb348c97df44 791 MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U);
lypinator 0:bb348c97df44 792
lypinator 0:bb348c97df44 793 /* Set the complementary output State */
lypinator 0:bb348c97df44 794 MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U);
lypinator 0:bb348c97df44 795
lypinator 0:bb348c97df44 796 /* Set the Output Idle state */
lypinator 0:bb348c97df44 797 MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState);
lypinator 0:bb348c97df44 798
lypinator 0:bb348c97df44 799 /* Set the complementary output Idle state */
lypinator 0:bb348c97df44 800 MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U);
lypinator 0:bb348c97df44 801 }
lypinator 0:bb348c97df44 802
lypinator 0:bb348c97df44 803 /* Write to TIMx CR2 */
lypinator 0:bb348c97df44 804 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
lypinator 0:bb348c97df44 805
lypinator 0:bb348c97df44 806 /* Write to TIMx CCMR1 */
lypinator 0:bb348c97df44 807 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
lypinator 0:bb348c97df44 808
lypinator 0:bb348c97df44 809 /* Set the Capture Compare Register value */
lypinator 0:bb348c97df44 810 LL_TIM_OC_SetCompareCH1(TIMx, TIM_OCInitStruct->CompareValue);
lypinator 0:bb348c97df44 811
lypinator 0:bb348c97df44 812 /* Write to TIMx CCER */
lypinator 0:bb348c97df44 813 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
lypinator 0:bb348c97df44 814
lypinator 0:bb348c97df44 815 return SUCCESS;
lypinator 0:bb348c97df44 816 }
lypinator 0:bb348c97df44 817
lypinator 0:bb348c97df44 818 /**
lypinator 0:bb348c97df44 819 * @brief Configure the TIMx output channel 2.
lypinator 0:bb348c97df44 820 * @param TIMx Timer Instance
lypinator 0:bb348c97df44 821 * @param TIM_OCInitStruct pointer to the the TIMx output channel 2 configuration data structure
lypinator 0:bb348c97df44 822 * @retval An ErrorStatus enumeration value:
lypinator 0:bb348c97df44 823 * - SUCCESS: TIMx registers are de-initialized
lypinator 0:bb348c97df44 824 * - ERROR: not applicable
lypinator 0:bb348c97df44 825 */
lypinator 0:bb348c97df44 826 static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
lypinator 0:bb348c97df44 827 {
lypinator 0:bb348c97df44 828 uint32_t tmpccmr1 = 0U;
lypinator 0:bb348c97df44 829 uint32_t tmpccer = 0U;
lypinator 0:bb348c97df44 830 uint32_t tmpcr2 = 0U;
lypinator 0:bb348c97df44 831
lypinator 0:bb348c97df44 832 /* Check the parameters */
lypinator 0:bb348c97df44 833 assert_param(IS_TIM_CC2_INSTANCE(TIMx));
lypinator 0:bb348c97df44 834 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
lypinator 0:bb348c97df44 835 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
lypinator 0:bb348c97df44 836 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
lypinator 0:bb348c97df44 837 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
lypinator 0:bb348c97df44 838 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
lypinator 0:bb348c97df44 839
lypinator 0:bb348c97df44 840 /* Disable the Channel 2: Reset the CC2E Bit */
lypinator 0:bb348c97df44 841 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E);
lypinator 0:bb348c97df44 842
lypinator 0:bb348c97df44 843 /* Get the TIMx CCER register value */
lypinator 0:bb348c97df44 844 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
lypinator 0:bb348c97df44 845
lypinator 0:bb348c97df44 846 /* Get the TIMx CR2 register value */
lypinator 0:bb348c97df44 847 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
lypinator 0:bb348c97df44 848
lypinator 0:bb348c97df44 849 /* Get the TIMx CCMR1 register value */
lypinator 0:bb348c97df44 850 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
lypinator 0:bb348c97df44 851
lypinator 0:bb348c97df44 852 /* Reset Capture/Compare selection Bits */
lypinator 0:bb348c97df44 853 CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC2S);
lypinator 0:bb348c97df44 854
lypinator 0:bb348c97df44 855 /* Select the Output Compare Mode */
lypinator 0:bb348c97df44 856 MODIFY_REG(tmpccmr1, TIM_CCMR1_OC2M, TIM_OCInitStruct->OCMode << 8U);
lypinator 0:bb348c97df44 857
lypinator 0:bb348c97df44 858 /* Set the Output Compare Polarity */
lypinator 0:bb348c97df44 859 MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U);
lypinator 0:bb348c97df44 860
lypinator 0:bb348c97df44 861 /* Set the Output State */
lypinator 0:bb348c97df44 862 MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U);
lypinator 0:bb348c97df44 863
lypinator 0:bb348c97df44 864 if (IS_TIM_BREAK_INSTANCE(TIMx))
lypinator 0:bb348c97df44 865 {
lypinator 0:bb348c97df44 866 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
lypinator 0:bb348c97df44 867 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
lypinator 0:bb348c97df44 868
lypinator 0:bb348c97df44 869 /* Set the complementary output Polarity */
lypinator 0:bb348c97df44 870 MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U);
lypinator 0:bb348c97df44 871
lypinator 0:bb348c97df44 872 /* Set the complementary output State */
lypinator 0:bb348c97df44 873 MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U);
lypinator 0:bb348c97df44 874
lypinator 0:bb348c97df44 875 /* Set the Output Idle state */
lypinator 0:bb348c97df44 876 MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U);
lypinator 0:bb348c97df44 877
lypinator 0:bb348c97df44 878 /* Set the complementary output Idle state */
lypinator 0:bb348c97df44 879 MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U);
lypinator 0:bb348c97df44 880 }
lypinator 0:bb348c97df44 881
lypinator 0:bb348c97df44 882 /* Write to TIMx CR2 */
lypinator 0:bb348c97df44 883 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
lypinator 0:bb348c97df44 884
lypinator 0:bb348c97df44 885 /* Write to TIMx CCMR1 */
lypinator 0:bb348c97df44 886 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
lypinator 0:bb348c97df44 887
lypinator 0:bb348c97df44 888 /* Set the Capture Compare Register value */
lypinator 0:bb348c97df44 889 LL_TIM_OC_SetCompareCH2(TIMx, TIM_OCInitStruct->CompareValue);
lypinator 0:bb348c97df44 890
lypinator 0:bb348c97df44 891 /* Write to TIMx CCER */
lypinator 0:bb348c97df44 892 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
lypinator 0:bb348c97df44 893
lypinator 0:bb348c97df44 894 return SUCCESS;
lypinator 0:bb348c97df44 895 }
lypinator 0:bb348c97df44 896
lypinator 0:bb348c97df44 897 /**
lypinator 0:bb348c97df44 898 * @brief Configure the TIMx output channel 3.
lypinator 0:bb348c97df44 899 * @param TIMx Timer Instance
lypinator 0:bb348c97df44 900 * @param TIM_OCInitStruct pointer to the the TIMx output channel 3 configuration data structure
lypinator 0:bb348c97df44 901 * @retval An ErrorStatus enumeration value:
lypinator 0:bb348c97df44 902 * - SUCCESS: TIMx registers are de-initialized
lypinator 0:bb348c97df44 903 * - ERROR: not applicable
lypinator 0:bb348c97df44 904 */
lypinator 0:bb348c97df44 905 static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
lypinator 0:bb348c97df44 906 {
lypinator 0:bb348c97df44 907 uint32_t tmpccmr2 = 0U;
lypinator 0:bb348c97df44 908 uint32_t tmpccer = 0U;
lypinator 0:bb348c97df44 909 uint32_t tmpcr2 = 0U;
lypinator 0:bb348c97df44 910
lypinator 0:bb348c97df44 911 /* Check the parameters */
lypinator 0:bb348c97df44 912 assert_param(IS_TIM_CC3_INSTANCE(TIMx));
lypinator 0:bb348c97df44 913 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
lypinator 0:bb348c97df44 914 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
lypinator 0:bb348c97df44 915 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
lypinator 0:bb348c97df44 916 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
lypinator 0:bb348c97df44 917 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
lypinator 0:bb348c97df44 918
lypinator 0:bb348c97df44 919 /* Disable the Channel 3: Reset the CC3E Bit */
lypinator 0:bb348c97df44 920 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E);
lypinator 0:bb348c97df44 921
lypinator 0:bb348c97df44 922 /* Get the TIMx CCER register value */
lypinator 0:bb348c97df44 923 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
lypinator 0:bb348c97df44 924
lypinator 0:bb348c97df44 925 /* Get the TIMx CR2 register value */
lypinator 0:bb348c97df44 926 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
lypinator 0:bb348c97df44 927
lypinator 0:bb348c97df44 928 /* Get the TIMx CCMR2 register value */
lypinator 0:bb348c97df44 929 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
lypinator 0:bb348c97df44 930
lypinator 0:bb348c97df44 931 /* Reset Capture/Compare selection Bits */
lypinator 0:bb348c97df44 932 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S);
lypinator 0:bb348c97df44 933
lypinator 0:bb348c97df44 934 /* Select the Output Compare Mode */
lypinator 0:bb348c97df44 935 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode);
lypinator 0:bb348c97df44 936
lypinator 0:bb348c97df44 937 /* Set the Output Compare Polarity */
lypinator 0:bb348c97df44 938 MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U);
lypinator 0:bb348c97df44 939
lypinator 0:bb348c97df44 940 /* Set the Output State */
lypinator 0:bb348c97df44 941 MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U);
lypinator 0:bb348c97df44 942
lypinator 0:bb348c97df44 943 if (IS_TIM_BREAK_INSTANCE(TIMx))
lypinator 0:bb348c97df44 944 {
lypinator 0:bb348c97df44 945 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
lypinator 0:bb348c97df44 946 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
lypinator 0:bb348c97df44 947
lypinator 0:bb348c97df44 948 /* Set the complementary output Polarity */
lypinator 0:bb348c97df44 949 MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U);
lypinator 0:bb348c97df44 950
lypinator 0:bb348c97df44 951 /* Set the complementary output State */
lypinator 0:bb348c97df44 952 MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U);
lypinator 0:bb348c97df44 953
lypinator 0:bb348c97df44 954 /* Set the Output Idle state */
lypinator 0:bb348c97df44 955 MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U);
lypinator 0:bb348c97df44 956
lypinator 0:bb348c97df44 957 /* Set the complementary output Idle state */
lypinator 0:bb348c97df44 958 MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U);
lypinator 0:bb348c97df44 959 }
lypinator 0:bb348c97df44 960
lypinator 0:bb348c97df44 961 /* Write to TIMx CR2 */
lypinator 0:bb348c97df44 962 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
lypinator 0:bb348c97df44 963
lypinator 0:bb348c97df44 964 /* Write to TIMx CCMR2 */
lypinator 0:bb348c97df44 965 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
lypinator 0:bb348c97df44 966
lypinator 0:bb348c97df44 967 /* Set the Capture Compare Register value */
lypinator 0:bb348c97df44 968 LL_TIM_OC_SetCompareCH3(TIMx, TIM_OCInitStruct->CompareValue);
lypinator 0:bb348c97df44 969
lypinator 0:bb348c97df44 970 /* Write to TIMx CCER */
lypinator 0:bb348c97df44 971 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
lypinator 0:bb348c97df44 972
lypinator 0:bb348c97df44 973 return SUCCESS;
lypinator 0:bb348c97df44 974 }
lypinator 0:bb348c97df44 975
lypinator 0:bb348c97df44 976 /**
lypinator 0:bb348c97df44 977 * @brief Configure the TIMx output channel 4.
lypinator 0:bb348c97df44 978 * @param TIMx Timer Instance
lypinator 0:bb348c97df44 979 * @param TIM_OCInitStruct pointer to the the TIMx output channel 4 configuration data structure
lypinator 0:bb348c97df44 980 * @retval An ErrorStatus enumeration value:
lypinator 0:bb348c97df44 981 * - SUCCESS: TIMx registers are de-initialized
lypinator 0:bb348c97df44 982 * - ERROR: not applicable
lypinator 0:bb348c97df44 983 */
lypinator 0:bb348c97df44 984 static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
lypinator 0:bb348c97df44 985 {
lypinator 0:bb348c97df44 986 uint32_t tmpccmr2 = 0U;
lypinator 0:bb348c97df44 987 uint32_t tmpccer = 0U;
lypinator 0:bb348c97df44 988 uint32_t tmpcr2 = 0U;
lypinator 0:bb348c97df44 989
lypinator 0:bb348c97df44 990 /* Check the parameters */
lypinator 0:bb348c97df44 991 assert_param(IS_TIM_CC4_INSTANCE(TIMx));
lypinator 0:bb348c97df44 992 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
lypinator 0:bb348c97df44 993 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
lypinator 0:bb348c97df44 994 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
lypinator 0:bb348c97df44 995 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
lypinator 0:bb348c97df44 996 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
lypinator 0:bb348c97df44 997
lypinator 0:bb348c97df44 998 /* Disable the Channel 4: Reset the CC4E Bit */
lypinator 0:bb348c97df44 999 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E);
lypinator 0:bb348c97df44 1000
lypinator 0:bb348c97df44 1001 /* Get the TIMx CCER register value */
lypinator 0:bb348c97df44 1002 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
lypinator 0:bb348c97df44 1003
lypinator 0:bb348c97df44 1004 /* Get the TIMx CR2 register value */
lypinator 0:bb348c97df44 1005 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
lypinator 0:bb348c97df44 1006
lypinator 0:bb348c97df44 1007 /* Get the TIMx CCMR2 register value */
lypinator 0:bb348c97df44 1008 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
lypinator 0:bb348c97df44 1009
lypinator 0:bb348c97df44 1010 /* Reset Capture/Compare selection Bits */
lypinator 0:bb348c97df44 1011 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S);
lypinator 0:bb348c97df44 1012
lypinator 0:bb348c97df44 1013 /* Select the Output Compare Mode */
lypinator 0:bb348c97df44 1014 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U);
lypinator 0:bb348c97df44 1015
lypinator 0:bb348c97df44 1016 /* Set the Output Compare Polarity */
lypinator 0:bb348c97df44 1017 MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U);
lypinator 0:bb348c97df44 1018
lypinator 0:bb348c97df44 1019 /* Set the Output State */
lypinator 0:bb348c97df44 1020 MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U);
lypinator 0:bb348c97df44 1021
lypinator 0:bb348c97df44 1022 if (IS_TIM_BREAK_INSTANCE(TIMx))
lypinator 0:bb348c97df44 1023 {
lypinator 0:bb348c97df44 1024 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
lypinator 0:bb348c97df44 1025 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
lypinator 0:bb348c97df44 1026
lypinator 0:bb348c97df44 1027 /* Set the Output Idle state */
lypinator 0:bb348c97df44 1028 MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U);
lypinator 0:bb348c97df44 1029 }
lypinator 0:bb348c97df44 1030
lypinator 0:bb348c97df44 1031 /* Write to TIMx CR2 */
lypinator 0:bb348c97df44 1032 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
lypinator 0:bb348c97df44 1033
lypinator 0:bb348c97df44 1034 /* Write to TIMx CCMR2 */
lypinator 0:bb348c97df44 1035 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
lypinator 0:bb348c97df44 1036
lypinator 0:bb348c97df44 1037 /* Set the Capture Compare Register value */
lypinator 0:bb348c97df44 1038 LL_TIM_OC_SetCompareCH4(TIMx, TIM_OCInitStruct->CompareValue);
lypinator 0:bb348c97df44 1039
lypinator 0:bb348c97df44 1040 /* Write to TIMx CCER */
lypinator 0:bb348c97df44 1041 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
lypinator 0:bb348c97df44 1042
lypinator 0:bb348c97df44 1043 return SUCCESS;
lypinator 0:bb348c97df44 1044 }
lypinator 0:bb348c97df44 1045
lypinator 0:bb348c97df44 1046
lypinator 0:bb348c97df44 1047 /**
lypinator 0:bb348c97df44 1048 * @brief Configure the TIMx input channel 1.
lypinator 0:bb348c97df44 1049 * @param TIMx Timer Instance
lypinator 0:bb348c97df44 1050 * @param TIM_ICInitStruct pointer to the the TIMx input channel 1 configuration data structure
lypinator 0:bb348c97df44 1051 * @retval An ErrorStatus enumeration value:
lypinator 0:bb348c97df44 1052 * - SUCCESS: TIMx registers are de-initialized
lypinator 0:bb348c97df44 1053 * - ERROR: not applicable
lypinator 0:bb348c97df44 1054 */
lypinator 0:bb348c97df44 1055 static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
lypinator 0:bb348c97df44 1056 {
lypinator 0:bb348c97df44 1057 /* Check the parameters */
lypinator 0:bb348c97df44 1058 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
lypinator 0:bb348c97df44 1059 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
lypinator 0:bb348c97df44 1060 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
lypinator 0:bb348c97df44 1061 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
lypinator 0:bb348c97df44 1062 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
lypinator 0:bb348c97df44 1063
lypinator 0:bb348c97df44 1064 /* Disable the Channel 1: Reset the CC1E Bit */
lypinator 0:bb348c97df44 1065 TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E;
lypinator 0:bb348c97df44 1066
lypinator 0:bb348c97df44 1067 /* Select the Input and set the filter and the prescaler value */
lypinator 0:bb348c97df44 1068 MODIFY_REG(TIMx->CCMR1,
lypinator 0:bb348c97df44 1069 (TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC),
lypinator 0:bb348c97df44 1070 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
lypinator 0:bb348c97df44 1071
lypinator 0:bb348c97df44 1072 /* Select the Polarity and set the CC1E Bit */
lypinator 0:bb348c97df44 1073 MODIFY_REG(TIMx->CCER,
lypinator 0:bb348c97df44 1074 (TIM_CCER_CC1P | TIM_CCER_CC1NP),
lypinator 0:bb348c97df44 1075 (TIM_ICInitStruct->ICPolarity | TIM_CCER_CC1E));
lypinator 0:bb348c97df44 1076
lypinator 0:bb348c97df44 1077 return SUCCESS;
lypinator 0:bb348c97df44 1078 }
lypinator 0:bb348c97df44 1079
lypinator 0:bb348c97df44 1080 /**
lypinator 0:bb348c97df44 1081 * @brief Configure the TIMx input channel 2.
lypinator 0:bb348c97df44 1082 * @param TIMx Timer Instance
lypinator 0:bb348c97df44 1083 * @param TIM_ICInitStruct pointer to the the TIMx input channel 2 configuration data structure
lypinator 0:bb348c97df44 1084 * @retval An ErrorStatus enumeration value:
lypinator 0:bb348c97df44 1085 * - SUCCESS: TIMx registers are de-initialized
lypinator 0:bb348c97df44 1086 * - ERROR: not applicable
lypinator 0:bb348c97df44 1087 */
lypinator 0:bb348c97df44 1088 static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
lypinator 0:bb348c97df44 1089 {
lypinator 0:bb348c97df44 1090 /* Check the parameters */
lypinator 0:bb348c97df44 1091 assert_param(IS_TIM_CC2_INSTANCE(TIMx));
lypinator 0:bb348c97df44 1092 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
lypinator 0:bb348c97df44 1093 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
lypinator 0:bb348c97df44 1094 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
lypinator 0:bb348c97df44 1095 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
lypinator 0:bb348c97df44 1096
lypinator 0:bb348c97df44 1097 /* Disable the Channel 2: Reset the CC2E Bit */
lypinator 0:bb348c97df44 1098 TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E;
lypinator 0:bb348c97df44 1099
lypinator 0:bb348c97df44 1100 /* Select the Input and set the filter and the prescaler value */
lypinator 0:bb348c97df44 1101 MODIFY_REG(TIMx->CCMR1,
lypinator 0:bb348c97df44 1102 (TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC),
lypinator 0:bb348c97df44 1103 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
lypinator 0:bb348c97df44 1104
lypinator 0:bb348c97df44 1105 /* Select the Polarity and set the CC2E Bit */
lypinator 0:bb348c97df44 1106 MODIFY_REG(TIMx->CCER,
lypinator 0:bb348c97df44 1107 (TIM_CCER_CC2P | TIM_CCER_CC2NP),
lypinator 0:bb348c97df44 1108 ((TIM_ICInitStruct->ICPolarity << 4U) | TIM_CCER_CC2E));
lypinator 0:bb348c97df44 1109
lypinator 0:bb348c97df44 1110 return SUCCESS;
lypinator 0:bb348c97df44 1111 }
lypinator 0:bb348c97df44 1112
lypinator 0:bb348c97df44 1113 /**
lypinator 0:bb348c97df44 1114 * @brief Configure the TIMx input channel 3.
lypinator 0:bb348c97df44 1115 * @param TIMx Timer Instance
lypinator 0:bb348c97df44 1116 * @param TIM_ICInitStruct pointer to the the TIMx input channel 3 configuration data structure
lypinator 0:bb348c97df44 1117 * @retval An ErrorStatus enumeration value:
lypinator 0:bb348c97df44 1118 * - SUCCESS: TIMx registers are de-initialized
lypinator 0:bb348c97df44 1119 * - ERROR: not applicable
lypinator 0:bb348c97df44 1120 */
lypinator 0:bb348c97df44 1121 static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
lypinator 0:bb348c97df44 1122 {
lypinator 0:bb348c97df44 1123 /* Check the parameters */
lypinator 0:bb348c97df44 1124 assert_param(IS_TIM_CC3_INSTANCE(TIMx));
lypinator 0:bb348c97df44 1125 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
lypinator 0:bb348c97df44 1126 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
lypinator 0:bb348c97df44 1127 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
lypinator 0:bb348c97df44 1128 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
lypinator 0:bb348c97df44 1129
lypinator 0:bb348c97df44 1130 /* Disable the Channel 3: Reset the CC3E Bit */
lypinator 0:bb348c97df44 1131 TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E;
lypinator 0:bb348c97df44 1132
lypinator 0:bb348c97df44 1133 /* Select the Input and set the filter and the prescaler value */
lypinator 0:bb348c97df44 1134 MODIFY_REG(TIMx->CCMR2,
lypinator 0:bb348c97df44 1135 (TIM_CCMR2_CC3S | TIM_CCMR2_IC3F | TIM_CCMR2_IC3PSC),
lypinator 0:bb348c97df44 1136 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
lypinator 0:bb348c97df44 1137
lypinator 0:bb348c97df44 1138 /* Select the Polarity and set the CC3E Bit */
lypinator 0:bb348c97df44 1139 MODIFY_REG(TIMx->CCER,
lypinator 0:bb348c97df44 1140 (TIM_CCER_CC3P | TIM_CCER_CC3NP),
lypinator 0:bb348c97df44 1141 ((TIM_ICInitStruct->ICPolarity << 8U) | TIM_CCER_CC3E));
lypinator 0:bb348c97df44 1142
lypinator 0:bb348c97df44 1143 return SUCCESS;
lypinator 0:bb348c97df44 1144 }
lypinator 0:bb348c97df44 1145
lypinator 0:bb348c97df44 1146 /**
lypinator 0:bb348c97df44 1147 * @brief Configure the TIMx input channel 4.
lypinator 0:bb348c97df44 1148 * @param TIMx Timer Instance
lypinator 0:bb348c97df44 1149 * @param TIM_ICInitStruct pointer to the the TIMx input channel 4 configuration data structure
lypinator 0:bb348c97df44 1150 * @retval An ErrorStatus enumeration value:
lypinator 0:bb348c97df44 1151 * - SUCCESS: TIMx registers are de-initialized
lypinator 0:bb348c97df44 1152 * - ERROR: not applicable
lypinator 0:bb348c97df44 1153 */
lypinator 0:bb348c97df44 1154 static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
lypinator 0:bb348c97df44 1155 {
lypinator 0:bb348c97df44 1156 /* Check the parameters */
lypinator 0:bb348c97df44 1157 assert_param(IS_TIM_CC4_INSTANCE(TIMx));
lypinator 0:bb348c97df44 1158 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
lypinator 0:bb348c97df44 1159 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
lypinator 0:bb348c97df44 1160 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
lypinator 0:bb348c97df44 1161 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
lypinator 0:bb348c97df44 1162
lypinator 0:bb348c97df44 1163 /* Disable the Channel 4: Reset the CC4E Bit */
lypinator 0:bb348c97df44 1164 TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E;
lypinator 0:bb348c97df44 1165
lypinator 0:bb348c97df44 1166 /* Select the Input and set the filter and the prescaler value */
lypinator 0:bb348c97df44 1167 MODIFY_REG(TIMx->CCMR2,
lypinator 0:bb348c97df44 1168 (TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC),
lypinator 0:bb348c97df44 1169 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
lypinator 0:bb348c97df44 1170
lypinator 0:bb348c97df44 1171 /* Select the Polarity and set the CC2E Bit */
lypinator 0:bb348c97df44 1172 MODIFY_REG(TIMx->CCER,
lypinator 0:bb348c97df44 1173 (TIM_CCER_CC4P | TIM_CCER_CC4NP),
lypinator 0:bb348c97df44 1174 ((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E));
lypinator 0:bb348c97df44 1175
lypinator 0:bb348c97df44 1176 return SUCCESS;
lypinator 0:bb348c97df44 1177 }
lypinator 0:bb348c97df44 1178
lypinator 0:bb348c97df44 1179
lypinator 0:bb348c97df44 1180 /**
lypinator 0:bb348c97df44 1181 * @}
lypinator 0:bb348c97df44 1182 */
lypinator 0:bb348c97df44 1183
lypinator 0:bb348c97df44 1184 /**
lypinator 0:bb348c97df44 1185 * @}
lypinator 0:bb348c97df44 1186 */
lypinator 0:bb348c97df44 1187
lypinator 0:bb348c97df44 1188 #endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM9 || TIM10 || TIM11 || TIM12 || TIM13 || TIM14 */
lypinator 0:bb348c97df44 1189
lypinator 0:bb348c97df44 1190 /**
lypinator 0:bb348c97df44 1191 * @}
lypinator 0:bb348c97df44 1192 */
lypinator 0:bb348c97df44 1193
lypinator 0:bb348c97df44 1194 #endif /* USE_FULL_LL_DRIVER */
lypinator 0:bb348c97df44 1195
lypinator 0:bb348c97df44 1196 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/