DevLibMemoryController - Initial commit

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Initial commit

mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_system.h@0:bb348c97df44, 2020-09-16 (annotated)

Committer:: lypinator
Date:: Wed Sep 16 01:11:49 2020 +0000
Revision:: 0:bb348c97df44

Added PWM

Who changed what in which revision?

User	Revision	Line number	New contents of line
lypinator	0:bb348c97df44	1	/**
lypinator	0:bb348c97df44	2	******************************************************************************
lypinator	0:bb348c97df44	3	* @file stm32f4xx_ll_system.h
lypinator	0:bb348c97df44	4	* @author MCD Application Team
lypinator	0:bb348c97df44	5	* @brief Header file of SYSTEM LL module.
lypinator	0:bb348c97df44	6	@verbatim
lypinator	0:bb348c97df44	7	==============================================================================
lypinator	0:bb348c97df44	8	##### How to use this driver #####
lypinator	0:bb348c97df44	9	==============================================================================
lypinator	0:bb348c97df44	10	[..]
lypinator	0:bb348c97df44	11	The LL SYSTEM driver contains a set of generic APIs that can be
lypinator	0:bb348c97df44	12	used by user:
lypinator	0:bb348c97df44	13	(+) Some of the FLASH features need to be handled in the SYSTEM file.
lypinator	0:bb348c97df44	14	(+) Access to DBGCMU registers
lypinator	0:bb348c97df44	15	(+) Access to SYSCFG registers
lypinator	0:bb348c97df44	16
lypinator	0:bb348c97df44	17	@endverbatim
lypinator	0:bb348c97df44	18	******************************************************************************
lypinator	0:bb348c97df44	19	* @attention
lypinator	0:bb348c97df44	20	*
lypinator	0:bb348c97df44	21	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
lypinator	0:bb348c97df44	22	*
lypinator	0:bb348c97df44	23	* Redistribution and use in source and binary forms, with or without modification,
lypinator	0:bb348c97df44	24	* are permitted provided that the following conditions are met:
lypinator	0:bb348c97df44	25	* 1. Redistributions of source code must retain the above copyright notice,
lypinator	0:bb348c97df44	26	* this list of conditions and the following disclaimer.
lypinator	0:bb348c97df44	27	* 2. Redistributions in binary form must reproduce the above copyright notice,
lypinator	0:bb348c97df44	28	* this list of conditions and the following disclaimer in the documentation
lypinator	0:bb348c97df44	29	* and/or other materials provided with the distribution.
lypinator	0:bb348c97df44	30	* 3. Neither the name of STMicroelectronics nor the names of its contributors
lypinator	0:bb348c97df44	31	* may be used to endorse or promote products derived from this software
lypinator	0:bb348c97df44	32	* without specific prior written permission.
lypinator	0:bb348c97df44	33	*
lypinator	0:bb348c97df44	34	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
lypinator	0:bb348c97df44	35	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
lypinator	0:bb348c97df44	36	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
lypinator	0:bb348c97df44	37	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
lypinator	0:bb348c97df44	38	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
lypinator	0:bb348c97df44	39	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
lypinator	0:bb348c97df44	40	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
lypinator	0:bb348c97df44	41	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
lypinator	0:bb348c97df44	42	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
lypinator	0:bb348c97df44	43	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
lypinator	0:bb348c97df44	44	*
lypinator	0:bb348c97df44	45	******************************************************************************
lypinator	0:bb348c97df44	46	*/
lypinator	0:bb348c97df44	47
lypinator	0:bb348c97df44	48	/* Define to prevent recursive inclusion -------------------------------------*/
lypinator	0:bb348c97df44	49	#ifndef __STM32F4xx_LL_SYSTEM_H
lypinator	0:bb348c97df44	50	#define __STM32F4xx_LL_SYSTEM_H
lypinator	0:bb348c97df44	51
lypinator	0:bb348c97df44	52	#ifdef __cplusplus
lypinator	0:bb348c97df44	53	extern "C" {
lypinator	0:bb348c97df44	54	#endif
lypinator	0:bb348c97df44	55
lypinator	0:bb348c97df44	56	/* Includes ------------------------------------------------------------------*/
lypinator	0:bb348c97df44	57	#include "stm32f4xx.h"
lypinator	0:bb348c97df44	58
lypinator	0:bb348c97df44	59	/** @addtogroup STM32F4xx_LL_Driver
lypinator	0:bb348c97df44	60	* @{
lypinator	0:bb348c97df44	61	*/
lypinator	0:bb348c97df44	62
lypinator	0:bb348c97df44	63	#if defined (FLASH) \|\| defined (SYSCFG) \|\| defined (DBGMCU)
lypinator	0:bb348c97df44	64
lypinator	0:bb348c97df44	65	/** @defgroup SYSTEM_LL SYSTEM
lypinator	0:bb348c97df44	66	* @{
lypinator	0:bb348c97df44	67	*/
lypinator	0:bb348c97df44	68
lypinator	0:bb348c97df44	69	/* Private types -------------------------------------------------------------*/
lypinator	0:bb348c97df44	70	/* Private variables ---------------------------------------------------------*/
lypinator	0:bb348c97df44	71
lypinator	0:bb348c97df44	72	/* Private constants ---------------------------------------------------------*/
lypinator	0:bb348c97df44	73	/** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants
lypinator	0:bb348c97df44	74	* @{
lypinator	0:bb348c97df44	75	*/
lypinator	0:bb348c97df44	76
lypinator	0:bb348c97df44	77	/**
lypinator	0:bb348c97df44	78	* @}
lypinator	0:bb348c97df44	79	*/
lypinator	0:bb348c97df44	80
lypinator	0:bb348c97df44	81	/* Private macros ------------------------------------------------------------*/
lypinator	0:bb348c97df44	82
lypinator	0:bb348c97df44	83	/* Exported types ------------------------------------------------------------*/
lypinator	0:bb348c97df44	84	/* Exported constants --------------------------------------------------------*/
lypinator	0:bb348c97df44	85	/** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants
lypinator	0:bb348c97df44	86	* @{
lypinator	0:bb348c97df44	87	*/
lypinator	0:bb348c97df44	88
lypinator	0:bb348c97df44	89	/** @defgroup SYSTEM_LL_EC_REMAP SYSCFG REMAP
lypinator	0:bb348c97df44	90	* @{
lypinator	0:bb348c97df44	91	*/
lypinator	0:bb348c97df44	92	#define LL_SYSCFG_REMAP_FLASH (uint32_t)0x00000000 /!< Main Flash memory mapped at 0x00000000 /
lypinator	0:bb348c97df44	93	#define LL_SYSCFG_REMAP_SYSTEMFLASH SYSCFG_MEMRMP_MEM_MODE_0 /!< System Flash memory mapped at 0x00000000 /
lypinator	0:bb348c97df44	94	#if defined(FSMC_Bank1)
lypinator	0:bb348c97df44	95	#define LL_SYSCFG_REMAP_FSMC SYSCFG_MEMRMP_MEM_MODE_1 /!< FSMC(NOR/PSRAM 1 and 2) mapped at 0x00000000 /
lypinator	0:bb348c97df44	96	#endif /* FSMC_Bank1 */
lypinator	0:bb348c97df44	97	#if defined(FMC_Bank1)
lypinator	0:bb348c97df44	98	#define LL_SYSCFG_REMAP_FMC SYSCFG_MEMRMP_MEM_MODE_1 /!< FMC(NOR/PSRAM 1 and 2) mapped at 0x00000000 /
lypinator	0:bb348c97df44	99	#define LL_SYSCFG_REMAP_SDRAM SYSCFG_MEMRMP_MEM_MODE_2 /!< FMC/SDRAM mapped at 0x00000000 /
lypinator	0:bb348c97df44	100	#endif /* FMC_Bank1 */
lypinator	0:bb348c97df44	101	#define LL_SYSCFG_REMAP_SRAM (SYSCFG_MEMRMP_MEM_MODE_1 \| SYSCFG_MEMRMP_MEM_MODE_0) /!< SRAM1 mapped at 0x00000000 /
lypinator	0:bb348c97df44	102
lypinator	0:bb348c97df44	103	/**
lypinator	0:bb348c97df44	104	* @}
lypinator	0:bb348c97df44	105	*/
lypinator	0:bb348c97df44	106
lypinator	0:bb348c97df44	107	#if defined(SYSCFG_PMC_MII_RMII_SEL)
lypinator	0:bb348c97df44	108	/** @defgroup SYSTEM_LL_EC_PMC SYSCFG PMC
lypinator	0:bb348c97df44	109	* @{
lypinator	0:bb348c97df44	110	*/
lypinator	0:bb348c97df44	111	#define LL_SYSCFG_PMC_ETHMII (uint32_t)0x00000000 /!< ETH Media MII interface /
lypinator	0:bb348c97df44	112	#define LL_SYSCFG_PMC_ETHRMII (uint32_t)SYSCFG_PMC_MII_RMII_SEL /!< ETH Media RMII interface /
lypinator	0:bb348c97df44	113
lypinator	0:bb348c97df44	114	/**
lypinator	0:bb348c97df44	115	* @}
lypinator	0:bb348c97df44	116	*/
lypinator	0:bb348c97df44	117	#endif /* SYSCFG_PMC_MII_RMII_SEL */
lypinator	0:bb348c97df44	118
lypinator	0:bb348c97df44	119
lypinator	0:bb348c97df44	120
lypinator	0:bb348c97df44	121	#if defined(SYSCFG_MEMRMP_UFB_MODE)
lypinator	0:bb348c97df44	122	/** @defgroup SYSTEM_LL_EC_BANKMODE SYSCFG BANK MODE
lypinator	0:bb348c97df44	123	* @{
lypinator	0:bb348c97df44	124	*/
lypinator	0:bb348c97df44	125	#define LL_SYSCFG_BANKMODE_BANK1 (uint32_t)0x00000000 /*!< Flash Bank 1 base address mapped at 0x0800 0000 (AXI) and 0x0020 0000 (TCM)
lypinator	0:bb348c97df44	126	and Flash Bank 2 base address mapped at 0x0810 0000 (AXI) and 0x0030 0000 (TCM)*/
lypinator	0:bb348c97df44	127	#define LL_SYSCFG_BANKMODE_BANK2 SYSCFG_MEMRMP_UFB_MODE /*!< Flash Bank 2 base address mapped at 0x0800 0000 (AXI) and 0x0020 0000(TCM)
lypinator	0:bb348c97df44	128	and Flash Bank 1 base address mapped at 0x0810 0000 (AXI) and 0x0030 0000(TCM) */
lypinator	0:bb348c97df44	129	/**
lypinator	0:bb348c97df44	130	* @}
lypinator	0:bb348c97df44	131	*/
lypinator	0:bb348c97df44	132	#endif /* SYSCFG_MEMRMP_UFB_MODE */
lypinator	0:bb348c97df44	133	/** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS
lypinator	0:bb348c97df44	134	* @{
lypinator	0:bb348c97df44	135	*/
lypinator	0:bb348c97df44	136	#if defined(SYSCFG_CFGR_FMPI2C1_SCL)
lypinator	0:bb348c97df44	137	#define LL_SYSCFG_I2C_FASTMODEPLUS_SCL SYSCFG_CFGR_FMPI2C1_SCL /!< Enable Fast Mode Plus on FMPI2C_SCL pin /
lypinator	0:bb348c97df44	138	#define LL_SYSCFG_I2C_FASTMODEPLUS_SDA SYSCFG_CFGR_FMPI2C1_SDA /!< Enable Fast Mode Plus on FMPI2C_SDA pin/
lypinator	0:bb348c97df44	139	#endif /* SYSCFG_CFGR_FMPI2C1_SCL */
lypinator	0:bb348c97df44	140	/**
lypinator	0:bb348c97df44	141	* @}
lypinator	0:bb348c97df44	142	*/
lypinator	0:bb348c97df44	143
lypinator	0:bb348c97df44	144	/** @defgroup SYSTEM_LL_EC_EXTI_PORT SYSCFG EXTI PORT
lypinator	0:bb348c97df44	145	* @{
lypinator	0:bb348c97df44	146	*/
lypinator	0:bb348c97df44	147	#define LL_SYSCFG_EXTI_PORTA (uint32_t)0 /!< EXTI PORT A /
lypinator	0:bb348c97df44	148	#define LL_SYSCFG_EXTI_PORTB (uint32_t)1 /!< EXTI PORT B /
lypinator	0:bb348c97df44	149	#define LL_SYSCFG_EXTI_PORTC (uint32_t)2 /!< EXTI PORT C /
lypinator	0:bb348c97df44	150	#define LL_SYSCFG_EXTI_PORTD (uint32_t)3 /!< EXTI PORT D /
lypinator	0:bb348c97df44	151	#define LL_SYSCFG_EXTI_PORTE (uint32_t)4 /!< EXTI PORT E /
lypinator	0:bb348c97df44	152	#if defined(GPIOF)
lypinator	0:bb348c97df44	153	#define LL_SYSCFG_EXTI_PORTF (uint32_t)5 /!< EXTI PORT F /
lypinator	0:bb348c97df44	154	#endif /* GPIOF */
lypinator	0:bb348c97df44	155	#if defined(GPIOG)
lypinator	0:bb348c97df44	156	#define LL_SYSCFG_EXTI_PORTG (uint32_t)6 /!< EXTI PORT G /
lypinator	0:bb348c97df44	157	#endif /* GPIOG */
lypinator	0:bb348c97df44	158	#define LL_SYSCFG_EXTI_PORTH (uint32_t)7 /!< EXTI PORT H /
lypinator	0:bb348c97df44	159	#if defined(GPIOI)
lypinator	0:bb348c97df44	160	#define LL_SYSCFG_EXTI_PORTI (uint32_t)8 /!< EXTI PORT I /
lypinator	0:bb348c97df44	161	#endif /* GPIOI */
lypinator	0:bb348c97df44	162	#if defined(GPIOJ)
lypinator	0:bb348c97df44	163	#define LL_SYSCFG_EXTI_PORTJ (uint32_t)9 /!< EXTI PORT J /
lypinator	0:bb348c97df44	164	#endif /* GPIOJ */
lypinator	0:bb348c97df44	165	#if defined(GPIOK)
lypinator	0:bb348c97df44	166	#define LL_SYSCFG_EXTI_PORTK (uint32_t)10 /!< EXTI PORT k /
lypinator	0:bb348c97df44	167	#endif /* GPIOK */
lypinator	0:bb348c97df44	168	/**
lypinator	0:bb348c97df44	169	* @}
lypinator	0:bb348c97df44	170	*/
lypinator	0:bb348c97df44	171
lypinator	0:bb348c97df44	172	/** @defgroup SYSTEM_LL_EC_EXTI_LINE SYSCFG EXTI LINE
lypinator	0:bb348c97df44	173	* @{
lypinator	0:bb348c97df44	174	*/
lypinator	0:bb348c97df44	175	#define LL_SYSCFG_EXTI_LINE0 (uint32_t)(0x000FU << 16 \| 0) /!< EXTI_POSITION_0 \| EXTICR[0] /
lypinator	0:bb348c97df44	176	#define LL_SYSCFG_EXTI_LINE1 (uint32_t)(0x00F0U << 16 \| 0) /!< EXTI_POSITION_4 \| EXTICR[0] /
lypinator	0:bb348c97df44	177	#define LL_SYSCFG_EXTI_LINE2 (uint32_t)(0x0F00U << 16 \| 0) /!< EXTI_POSITION_8 \| EXTICR[0] /
lypinator	0:bb348c97df44	178	#define LL_SYSCFG_EXTI_LINE3 (uint32_t)(0xF000U << 16 \| 0) /!< EXTI_POSITION_12 \| EXTICR[0] /
lypinator	0:bb348c97df44	179	#define LL_SYSCFG_EXTI_LINE4 (uint32_t)(0x000FU << 16 \| 1) /!< EXTI_POSITION_0 \| EXTICR[1] /
lypinator	0:bb348c97df44	180	#define LL_SYSCFG_EXTI_LINE5 (uint32_t)(0x00F0U << 16 \| 1) /!< EXTI_POSITION_4 \| EXTICR[1] /
lypinator	0:bb348c97df44	181	#define LL_SYSCFG_EXTI_LINE6 (uint32_t)(0x0F00U << 16 \| 1) /!< EXTI_POSITION_8 \| EXTICR[1] /
lypinator	0:bb348c97df44	182	#define LL_SYSCFG_EXTI_LINE7 (uint32_t)(0xF000U << 16 \| 1) /!< EXTI_POSITION_12 \| EXTICR[1] /
lypinator	0:bb348c97df44	183	#define LL_SYSCFG_EXTI_LINE8 (uint32_t)(0x000FU << 16 \| 2) /!< EXTI_POSITION_0 \| EXTICR[2] /
lypinator	0:bb348c97df44	184	#define LL_SYSCFG_EXTI_LINE9 (uint32_t)(0x00F0U << 16 \| 2) /!< EXTI_POSITION_4 \| EXTICR[2] /
lypinator	0:bb348c97df44	185	#define LL_SYSCFG_EXTI_LINE10 (uint32_t)(0x0F00U << 16 \| 2) /!< EXTI_POSITION_8 \| EXTICR[2] /
lypinator	0:bb348c97df44	186	#define LL_SYSCFG_EXTI_LINE11 (uint32_t)(0xF000U << 16 \| 2) /!< EXTI_POSITION_12 \| EXTICR[2] /
lypinator	0:bb348c97df44	187	#define LL_SYSCFG_EXTI_LINE12 (uint32_t)(0x000FU << 16 \| 3) /!< EXTI_POSITION_0 \| EXTICR[3] /
lypinator	0:bb348c97df44	188	#define LL_SYSCFG_EXTI_LINE13 (uint32_t)(0x00F0U << 16 \| 3) /!< EXTI_POSITION_4 \| EXTICR[3] /
lypinator	0:bb348c97df44	189	#define LL_SYSCFG_EXTI_LINE14 (uint32_t)(0x0F00U << 16 \| 3) /!< EXTI_POSITION_8 \| EXTICR[3] /
lypinator	0:bb348c97df44	190	#define LL_SYSCFG_EXTI_LINE15 (uint32_t)(0xF000U << 16 \| 3) /!< EXTI_POSITION_12 \| EXTICR[3] /
lypinator	0:bb348c97df44	191	/**
lypinator	0:bb348c97df44	192	* @}
lypinator	0:bb348c97df44	193	*/
lypinator	0:bb348c97df44	194
lypinator	0:bb348c97df44	195	/** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK
lypinator	0:bb348c97df44	196	* @{
lypinator	0:bb348c97df44	197	*/
lypinator	0:bb348c97df44	198	#if defined(SYSCFG_CFGR2_LOCKUP_LOCK)
lypinator	0:bb348c97df44	199	#define LL_SYSCFG_TIMBREAK_LOCKUP SYSCFG_CFGR2_LOCKUP_LOCK /*!< Enables and locks the LOCKUP output of CortexM4
lypinator	0:bb348c97df44	200	with Break Input of TIM1/8 */
lypinator	0:bb348c97df44	201	#define LL_SYSCFG_TIMBREAK_PVD SYSCFG_CFGR2_PVD_LOCK /*!< Enables and locks the PVD connection with TIM1/8 Break Input
lypinator	0:bb348c97df44	202	and also the PVDE and PLS bits of the Power Control Interface */
lypinator	0:bb348c97df44	203	#endif /* SYSCFG_CFGR2_CLL */
lypinator	0:bb348c97df44	204	/**
lypinator	0:bb348c97df44	205	* @}
lypinator	0:bb348c97df44	206	*/
lypinator	0:bb348c97df44	207
lypinator	0:bb348c97df44	208	#if defined(SYSCFG_MCHDLYCR_BSCKSEL)
lypinator	0:bb348c97df44	209	/** @defgroup SYSTEM_LL_DFSDM_BitStream_ClockSource SYSCFG MCHDLY BCKKSEL
lypinator	0:bb348c97df44	210	* @{
lypinator	0:bb348c97df44	211	*/
lypinator	0:bb348c97df44	212	#define LL_SYSCFG_BITSTREAM_CLOCK_TIM2OC1 (uint32_t)0x00000000
lypinator	0:bb348c97df44	213	#define LL_SYSCFG_BITSTREAM_CLOCK_DFSDM2 SYSCFG_MCHDLYCR_BSCKSEL
lypinator	0:bb348c97df44	214	/**
lypinator	0:bb348c97df44	215	* @}
lypinator	0:bb348c97df44	216	*/
lypinator	0:bb348c97df44	217	/** @defgroup SYSTEM_LL_DFSDM_MCHDLYEN SYSCFG MCHDLY MCHDLYEN
lypinator	0:bb348c97df44	218	* @{
lypinator	0:bb348c97df44	219	*/
lypinator	0:bb348c97df44	220	#define LL_SYSCFG_DFSDM1_MCHDLYEN SYSCFG_MCHDLYCR_MCHDLY1EN
lypinator	0:bb348c97df44	221	#define LL_SYSCFG_DFSDM2_MCHDLYEN SYSCFG_MCHDLYCR_MCHDLY2EN
lypinator	0:bb348c97df44	222	/**
lypinator	0:bb348c97df44	223	* @}
lypinator	0:bb348c97df44	224	*/
lypinator	0:bb348c97df44	225	/** @defgroup SYSTEM_LL_DFSDM_DataIn0_Source SYSCFG MCHDLY DFSDMD0SEL
lypinator	0:bb348c97df44	226	* @{
lypinator	0:bb348c97df44	227	*/
lypinator	0:bb348c97df44	228	#define LL_SYSCFG_DFSDM1_DataIn0 SYSCFG_MCHDLYCR_DFSDM1D0SEL
lypinator	0:bb348c97df44	229	#define LL_SYSCFG_DFSDM2_DataIn0 SYSCFG_MCHDLYCR_DFSDM2D0SEL
lypinator	0:bb348c97df44	230
lypinator	0:bb348c97df44	231	#define LL_SYSCFG_DFSDM1_DataIn0_PAD (uint32_t)((SYSCFG_MCHDLYCR_DFSDM1D0SEL << 16) \| 0x00000000)
lypinator	0:bb348c97df44	232	#define LL_SYSCFG_DFSDM1_DataIn0_DM (uint32_t)((SYSCFG_MCHDLYCR_DFSDM1D0SEL << 16) \| SYSCFG_MCHDLYCR_DFSDM1D0SEL)
lypinator	0:bb348c97df44	233	#define LL_SYSCFG_DFSDM2_DataIn0_PAD (uint32_t)((SYSCFG_MCHDLYCR_DFSDM2D0SEL << 16) \| 0x00000000)
lypinator	0:bb348c97df44	234	#define LL_SYSCFG_DFSDM2_DataIn0_DM (uint32_t)((SYSCFG_MCHDLYCR_DFSDM2D0SEL << 16) \| SYSCFG_MCHDLYCR_DFSDM2D0SEL)
lypinator	0:bb348c97df44	235	/**
lypinator	0:bb348c97df44	236	* @}
lypinator	0:bb348c97df44	237	*/
lypinator	0:bb348c97df44	238	/** @defgroup SYSTEM_LL_DFSDM_DataIn2_Source SYSCFG MCHDLY DFSDMD2SEL
lypinator	0:bb348c97df44	239	* @{
lypinator	0:bb348c97df44	240	*/
lypinator	0:bb348c97df44	241	#define LL_SYSCFG_DFSDM1_DataIn2 SYSCFG_MCHDLYCR_DFSDM1D2SEL
lypinator	0:bb348c97df44	242	#define LL_SYSCFG_DFSDM2_DataIn2 SYSCFG_MCHDLYCR_DFSDM2D2SEL
lypinator	0:bb348c97df44	243
lypinator	0:bb348c97df44	244	#define LL_SYSCFG_DFSDM1_DataIn2_PAD (uint32_t)((SYSCFG_MCHDLYCR_DFSDM1D2SEL << 16) \| 0x00000000)
lypinator	0:bb348c97df44	245	#define LL_SYSCFG_DFSDM1_DataIn2_DM (uint32_t)((SYSCFG_MCHDLYCR_DFSDM1D2SEL << 16) \| SYSCFG_MCHDLYCR_DFSDM1D2SEL)
lypinator	0:bb348c97df44	246	#define LL_SYSCFG_DFSDM2_DataIn2_PAD (uint32_t)((SYSCFG_MCHDLYCR_DFSDM2D2SEL << 16) \| 0x00000000)
lypinator	0:bb348c97df44	247	#define LL_SYSCFG_DFSDM2_DataIn2_DM (uint32_t)((SYSCFG_MCHDLYCR_DFSDM2D2SEL << 16) \| SYSCFG_MCHDLYCR_DFSDM2D2SEL)
lypinator	0:bb348c97df44	248	/**
lypinator	0:bb348c97df44	249	* @}
lypinator	0:bb348c97df44	250	*/
lypinator	0:bb348c97df44	251	/** @defgroup SYSTEM_LL_DFSDM1_TIM4OC2_BitstreamDistribution SYSCFG MCHDLY DFSDM1CK02SEL
lypinator	0:bb348c97df44	252	* @{
lypinator	0:bb348c97df44	253	*/
lypinator	0:bb348c97df44	254	#define LL_SYSCFG_DFSDM1_TIM4OC2_CLKIN0 (uint32_t)0x00000000
lypinator	0:bb348c97df44	255	#define LL_SYSCFG_DFSDM1_TIM4OC2_CLKIN2 SYSCFG_MCHDLYCR_DFSDM1CK02SEL
lypinator	0:bb348c97df44	256	/**
lypinator	0:bb348c97df44	257	* @}
lypinator	0:bb348c97df44	258	*/
lypinator	0:bb348c97df44	259	/** @defgroup SYSTEM_LL_DFSDM1_TIM4OC1_BitstreamDistribution SYSCFG MCHDLY DFSDM1CK13SEL
lypinator	0:bb348c97df44	260	* @{
lypinator	0:bb348c97df44	261	*/
lypinator	0:bb348c97df44	262	#define LL_SYSCFG_DFSDM1_TIM4OC1_CLKIN1 (uint32_t)0x00000000
lypinator	0:bb348c97df44	263	#define LL_SYSCFG_DFSDM1_TIM4OC1_CLKIN3 SYSCFG_MCHDLYCR_DFSDM1CK13SEL
lypinator	0:bb348c97df44	264	/**
lypinator	0:bb348c97df44	265	* @}
lypinator	0:bb348c97df44	266	*/
lypinator	0:bb348c97df44	267	/** @defgroup SYSTEM_LL_DFSDM1_CLKIN_SourceSelection SYSCFG MCHDLY DFSDMCFG
lypinator	0:bb348c97df44	268	* @{
lypinator	0:bb348c97df44	269	*/
lypinator	0:bb348c97df44	270	#define LL_SYSCFG_DFSDM1_CKIN_PAD (uint32_t)0x00000000
lypinator	0:bb348c97df44	271	#define LL_SYSCFG_DFSDM1_CKIN_DM SYSCFG_MCHDLYCR_DFSDM1CFG
lypinator	0:bb348c97df44	272	/**
lypinator	0:bb348c97df44	273	* @}
lypinator	0:bb348c97df44	274	*/
lypinator	0:bb348c97df44	275	/** @defgroup SYSTEM_LL_DFSDM1_CLKOUT_SourceSelection SYSCFG MCHDLY DFSDM1CKOSEL
lypinator	0:bb348c97df44	276	* @{
lypinator	0:bb348c97df44	277	*/
lypinator	0:bb348c97df44	278	#define LL_SYSCFG_DFSDM1_CKOUT (uint32_t)0x00000000
lypinator	0:bb348c97df44	279	#define LL_SYSCFG_DFSDM1_CKOUT_M27 SYSCFG_MCHDLYCR_DFSDM1CKOSEL
lypinator	0:bb348c97df44	280	/**
lypinator	0:bb348c97df44	281	* @}
lypinator	0:bb348c97df44	282	*/
lypinator	0:bb348c97df44	283
lypinator	0:bb348c97df44	284	/** @defgroup SYSTEM_LL_DFSDM2_DataIn4_SourceSelection SYSCFG MCHDLY DFSDM2D4SEL
lypinator	0:bb348c97df44	285	* @{
lypinator	0:bb348c97df44	286	*/
lypinator	0:bb348c97df44	287	#define LL_SYSCFG_DFSDM2_DataIn4_PAD (uint32_t)0x00000000
lypinator	0:bb348c97df44	288	#define LL_SYSCFG_DFSDM2_DataIn4_DM SYSCFG_MCHDLYCR_DFSDM2D4SEL
lypinator	0:bb348c97df44	289	/**
lypinator	0:bb348c97df44	290	* @}
lypinator	0:bb348c97df44	291	*/
lypinator	0:bb348c97df44	292	/** @defgroup SYSTEM_LL_DFSDM2_DataIn6_SourceSelection SYSCFG MCHDLY DFSDM2D6SEL
lypinator	0:bb348c97df44	293	* @{
lypinator	0:bb348c97df44	294	*/
lypinator	0:bb348c97df44	295	#define LL_SYSCFG_DFSDM2_DataIn6_PAD (uint32_t)0x00000000
lypinator	0:bb348c97df44	296	#define LL_SYSCFG_DFSDM2_DataIn6_DM SYSCFG_MCHDLYCR_DFSDM2D6SEL
lypinator	0:bb348c97df44	297	/**
lypinator	0:bb348c97df44	298	* @}
lypinator	0:bb348c97df44	299	*/
lypinator	0:bb348c97df44	300	/** @defgroup SYSTEM_LL_DFSDM2_TIM3OC4_BitstreamDistribution SYSCFG MCHDLY DFSDM2CK04SEL
lypinator	0:bb348c97df44	301	* @{
lypinator	0:bb348c97df44	302	*/
lypinator	0:bb348c97df44	303	#define LL_SYSCFG_DFSDM2_TIM3OC4_CLKIN0 (uint32_t)0x00000000
lypinator	0:bb348c97df44	304	#define LL_SYSCFG_DFSDM2_TIM3OC4_CLKIN4 SYSCFG_MCHDLYCR_DFSDM2CK04SEL
lypinator	0:bb348c97df44	305	/**
lypinator	0:bb348c97df44	306	* @}
lypinator	0:bb348c97df44	307	*/
lypinator	0:bb348c97df44	308	/** @defgroup SYSTEM_LL_DFSDM2_TIM3OC3_BitstreamDistribution SYSCFG MCHDLY DFSDM2CK15SEL
lypinator	0:bb348c97df44	309	* @{
lypinator	0:bb348c97df44	310	*/
lypinator	0:bb348c97df44	311	#define LL_SYSCFG_DFSDM2_TIM3OC3_CLKIN1 (uint32_t)0x00000000
lypinator	0:bb348c97df44	312	#define LL_SYSCFG_DFSDM2_TIM3OC3_CLKIN5 SYSCFG_MCHDLYCR_DFSDM2CK15SEL
lypinator	0:bb348c97df44	313	/**
lypinator	0:bb348c97df44	314	* @}
lypinator	0:bb348c97df44	315	*/
lypinator	0:bb348c97df44	316	/** @defgroup SYSTEM_LL_DFSDM2_TIM3OC2_BitstreamDistribution SYSCFG MCHDLY DFSDM2CK26SEL
lypinator	0:bb348c97df44	317	* @{
lypinator	0:bb348c97df44	318	*/
lypinator	0:bb348c97df44	319	#define LL_SYSCFG_DFSDM2_TIM3OC2_CLKIN2 (uint32_t)0x00000000
lypinator	0:bb348c97df44	320	#define LL_SYSCFG_DFSDM2_TIM3OC2_CLKIN6 SYSCFG_MCHDLYCR_DFSDM2CK26SEL
lypinator	0:bb348c97df44	321	/**
lypinator	0:bb348c97df44	322	* @}
lypinator	0:bb348c97df44	323	*/
lypinator	0:bb348c97df44	324	/** @defgroup SYSTEM_LL_DFSDM2_TIM3OC1_BitstreamDistribution SYSCFG MCHDLY DFSDM2CK37SEL
lypinator	0:bb348c97df44	325	* @{
lypinator	0:bb348c97df44	326	*/
lypinator	0:bb348c97df44	327	#define LL_SYSCFG_DFSDM2_TIM3OC1_CLKIN3 (uint32_t)0x00000000
lypinator	0:bb348c97df44	328	#define LL_SYSCFG_DFSDM2_TIM3OC1_CLKIN7 SYSCFG_MCHDLYCR_DFSDM2CK37SEL
lypinator	0:bb348c97df44	329	/**
lypinator	0:bb348c97df44	330	* @}
lypinator	0:bb348c97df44	331	*/
lypinator	0:bb348c97df44	332	/** @defgroup SYSTEM_LL_DFSDM2_CLKIN_SourceSelection SYSCFG MCHDLY DFSDM2CFG
lypinator	0:bb348c97df44	333	* @{
lypinator	0:bb348c97df44	334	*/
lypinator	0:bb348c97df44	335	#define LL_SYSCFG_DFSDM2_CKIN_PAD (uint32_t)0x00000000
lypinator	0:bb348c97df44	336	#define LL_SYSCFG_DFSDM2_CKIN_DM SYSCFG_MCHDLYCR_DFSDM2CFG
lypinator	0:bb348c97df44	337	/**
lypinator	0:bb348c97df44	338	* @}
lypinator	0:bb348c97df44	339	*/
lypinator	0:bb348c97df44	340	/** @defgroup SYSTEM_LL_DFSDM2_CLKOUT_SourceSelection SYSCFG MCHDLY DFSDM2CKOSEL
lypinator	0:bb348c97df44	341	* @{
lypinator	0:bb348c97df44	342	*/
lypinator	0:bb348c97df44	343	#define LL_SYSCFG_DFSDM2_CKOUT (uint32_t)0x00000000
lypinator	0:bb348c97df44	344	#define LL_SYSCFG_DFSDM2_CKOUT_M27 SYSCFG_MCHDLYCR_DFSDM2CKOSEL
lypinator	0:bb348c97df44	345	/**
lypinator	0:bb348c97df44	346	* @}
lypinator	0:bb348c97df44	347	*/
lypinator	0:bb348c97df44	348	#endif /* SYSCFG_MCHDLYCR_BSCKSEL */
lypinator	0:bb348c97df44	349
lypinator	0:bb348c97df44	350	/** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment
lypinator	0:bb348c97df44	351	* @{
lypinator	0:bb348c97df44	352	*/
lypinator	0:bb348c97df44	353	#define LL_DBGMCU_TRACE_NONE 0x00000000U /!< TRACE pins not assigned (default state) /
lypinator	0:bb348c97df44	354	#define LL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOEN /!< TRACE pin assignment for Asynchronous Mode /
lypinator	0:bb348c97df44	355	#define LL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN \| DBGMCU_CR_TRACE_MODE_0) /!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 /
lypinator	0:bb348c97df44	356	#define LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN \| DBGMCU_CR_TRACE_MODE_1) /!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 /
lypinator	0:bb348c97df44	357	#define LL_DBGMCU_TRACE_SYNCH_SIZE4 (DBGMCU_CR_TRACE_IOEN \| DBGMCU_CR_TRACE_MODE) /!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 /
lypinator	0:bb348c97df44	358	/**
lypinator	0:bb348c97df44	359	* @}
lypinator	0:bb348c97df44	360	*/
lypinator	0:bb348c97df44	361
lypinator	0:bb348c97df44	362	/** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP
lypinator	0:bb348c97df44	363	* @{
lypinator	0:bb348c97df44	364	*/
lypinator	0:bb348c97df44	365	#if defined(DBGMCU_APB1_FZ_DBG_TIM2_STOP)
lypinator	0:bb348c97df44	366	#define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP /!< TIM2 counter stopped when core is halted /
lypinator	0:bb348c97df44	367	#endif /* DBGMCU_APB1_FZ_DBG_TIM2_STOP */
lypinator	0:bb348c97df44	368	#if defined(DBGMCU_APB1_FZ_DBG_TIM3_STOP)
lypinator	0:bb348c97df44	369	#define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP /!< TIM3 counter stopped when core is halted /
lypinator	0:bb348c97df44	370	#endif /* DBGMCU_APB1_FZ_DBG_TIM3_STOP */
lypinator	0:bb348c97df44	371	#if defined(DBGMCU_APB1_FZ_DBG_TIM4_STOP)
lypinator	0:bb348c97df44	372	#define LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP /!< TIM4 counter stopped when core is halted /
lypinator	0:bb348c97df44	373	#endif /* DBGMCU_APB1_FZ_DBG_TIM4_STOP */
lypinator	0:bb348c97df44	374	#define LL_DBGMCU_APB1_GRP1_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP /!< TIM5 counter stopped when core is halted /
lypinator	0:bb348c97df44	375	#if defined(DBGMCU_APB1_FZ_DBG_TIM6_STOP)
lypinator	0:bb348c97df44	376	#define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP /!< TIM6 counter stopped when core is halted /
lypinator	0:bb348c97df44	377	#endif /* DBGMCU_APB1_FZ_DBG_TIM6_STOP */
lypinator	0:bb348c97df44	378	#if defined(DBGMCU_APB1_FZ_DBG_TIM7_STOP)
lypinator	0:bb348c97df44	379	#define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP /!< TIM7 counter stopped when core is halted /
lypinator	0:bb348c97df44	380	#endif /* DBGMCU_APB1_FZ_DBG_TIM7_STOP */
lypinator	0:bb348c97df44	381	#if defined(DBGMCU_APB1_FZ_DBG_TIM12_STOP)
lypinator	0:bb348c97df44	382	#define LL_DBGMCU_APB1_GRP1_TIM12_STOP DBGMCU_APB1_FZ_DBG_TIM12_STOP /!< TIM12 counter stopped when core is halted /
lypinator	0:bb348c97df44	383	#endif /* DBGMCU_APB1_FZ_DBG_TIM12_STOP */
lypinator	0:bb348c97df44	384	#if defined(DBGMCU_APB1_FZ_DBG_TIM13_STOP)
lypinator	0:bb348c97df44	385	#define LL_DBGMCU_APB1_GRP1_TIM13_STOP DBGMCU_APB1_FZ_DBG_TIM13_STOP /!< TIM13 counter stopped when core is halted /
lypinator	0:bb348c97df44	386	#endif /* DBGMCU_APB1_FZ_DBG_TIM13_STOP */
lypinator	0:bb348c97df44	387	#if defined(DBGMCU_APB1_FZ_DBG_TIM14_STOP)
lypinator	0:bb348c97df44	388	#define LL_DBGMCU_APB1_GRP1_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP /!< TIM14 counter stopped when core is halted /
lypinator	0:bb348c97df44	389	#endif /* DBGMCU_APB1_FZ_DBG_TIM14_STOP */
lypinator	0:bb348c97df44	390	#if defined(DBGMCU_APB1_FZ_DBG_LPTIM_STOP)
lypinator	0:bb348c97df44	391	#define LL_DBGMCU_APB1_GRP1_LPTIM_STOP DBGMCU_APB1_FZ_DBG_LPTIM_STOP /!< LPTIM counter stopped when core is halted /
lypinator	0:bb348c97df44	392	#endif /* DBGMCU_APB1_FZ_DBG_LPTIM_STOP */
lypinator	0:bb348c97df44	393	#define LL_DBGMCU_APB1_GRP1_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP /!< RTC counter stopped when core is halted /
lypinator	0:bb348c97df44	394	#define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP /!< Debug Window Watchdog stopped when Core is halted /
lypinator	0:bb348c97df44	395	#define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP /!< Debug Independent Watchdog stopped when Core is halted /
lypinator	0:bb348c97df44	396	#define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT /!< I2C1 SMBUS timeout mode stopped when Core is halted /
lypinator	0:bb348c97df44	397	#define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT /!< I2C2 SMBUS timeout mode stopped when Core is halted /
lypinator	0:bb348c97df44	398	#if defined(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT)
lypinator	0:bb348c97df44	399	#define LL_DBGMCU_APB1_GRP1_I2C3_STOP DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT /!< I2C3 SMBUS timeout mode stopped when Core is halted /
lypinator	0:bb348c97df44	400	#endif /* DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT */
lypinator	0:bb348c97df44	401	#if defined(DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT)
lypinator	0:bb348c97df44	402	#define LL_DBGMCU_APB1_GRP1_I2C4_STOP DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT /!< I2C4 SMBUS timeout mode stopped when Core is halted /
lypinator	0:bb348c97df44	403	#endif /* DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT */
lypinator	0:bb348c97df44	404	#if defined(DBGMCU_APB1_FZ_DBG_CAN1_STOP)
lypinator	0:bb348c97df44	405	#define LL_DBGMCU_APB1_GRP1_CAN1_STOP DBGMCU_APB1_FZ_DBG_CAN1_STOP /!< CAN1 debug stopped when Core is halted /
lypinator	0:bb348c97df44	406	#endif /* DBGMCU_APB1_FZ_DBG_CAN1_STOP */
lypinator	0:bb348c97df44	407	#if defined(DBGMCU_APB1_FZ_DBG_CAN2_STOP)
lypinator	0:bb348c97df44	408	#define LL_DBGMCU_APB1_GRP1_CAN2_STOP DBGMCU_APB1_FZ_DBG_CAN2_STOP /!< CAN2 debug stopped when Core is halted /
lypinator	0:bb348c97df44	409	#endif /* DBGMCU_APB1_FZ_DBG_CAN2_STOP */
lypinator	0:bb348c97df44	410	#if defined(DBGMCU_APB1_FZ_DBG_CAN3_STOP)
lypinator	0:bb348c97df44	411	#define LL_DBGMCU_APB1_GRP1_CAN3_STOP DBGMCU_APB1_FZ_DBG_CAN3_STOP /!< CAN3 debug stopped when Core is halted /
lypinator	0:bb348c97df44	412	#endif /* DBGMCU_APB1_FZ_DBG_CAN3_STOP */
lypinator	0:bb348c97df44	413	/**
lypinator	0:bb348c97df44	414	* @}
lypinator	0:bb348c97df44	415	*/
lypinator	0:bb348c97df44	416
lypinator	0:bb348c97df44	417	/** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP
lypinator	0:bb348c97df44	418	* @{
lypinator	0:bb348c97df44	419	*/
lypinator	0:bb348c97df44	420	#define LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP /!< TIM1 counter stopped when core is halted /
lypinator	0:bb348c97df44	421	#if defined(DBGMCU_APB2_FZ_DBG_TIM8_STOP)
lypinator	0:bb348c97df44	422	#define LL_DBGMCU_APB2_GRP1_TIM8_STOP DBGMCU_APB2_FZ_DBG_TIM8_STOP /!< TIM8 counter stopped when core is halted /
lypinator	0:bb348c97df44	423	#endif /* DBGMCU_APB2_FZ_DBG_TIM8_STOP */
lypinator	0:bb348c97df44	424	#define LL_DBGMCU_APB2_GRP1_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP /!< TIM9 counter stopped when core is halted /
lypinator	0:bb348c97df44	425	#if defined(DBGMCU_APB2_FZ_DBG_TIM10_STOP)
lypinator	0:bb348c97df44	426	#define LL_DBGMCU_APB2_GRP1_TIM10_STOP DBGMCU_APB2_FZ_DBG_TIM10_STOP /!< TIM10 counter stopped when core is halted /
lypinator	0:bb348c97df44	427	#endif /* DBGMCU_APB2_FZ_DBG_TIM10_STOP */
lypinator	0:bb348c97df44	428	#define LL_DBGMCU_APB2_GRP1_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP /!< TIM11 counter stopped when core is halted /
lypinator	0:bb348c97df44	429	/**
lypinator	0:bb348c97df44	430	* @}
lypinator	0:bb348c97df44	431	*/
lypinator	0:bb348c97df44	432
lypinator	0:bb348c97df44	433	/** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY
lypinator	0:bb348c97df44	434	* @{
lypinator	0:bb348c97df44	435	*/
lypinator	0:bb348c97df44	436	#define LL_FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /!< FLASH Zero wait state /
lypinator	0:bb348c97df44	437	#define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /!< FLASH One wait state /
lypinator	0:bb348c97df44	438	#define LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /!< FLASH Two wait states /
lypinator	0:bb348c97df44	439	#define LL_FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /!< FLASH Three wait states /
lypinator	0:bb348c97df44	440	#define LL_FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /!< FLASH Four wait states /
lypinator	0:bb348c97df44	441	#define LL_FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /!< FLASH five wait state /
lypinator	0:bb348c97df44	442	#define LL_FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /!< FLASH six wait state /
lypinator	0:bb348c97df44	443	#define LL_FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /!< FLASH seven wait states /
lypinator	0:bb348c97df44	444	#define LL_FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS /!< FLASH eight wait states /
lypinator	0:bb348c97df44	445	#define LL_FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS /!< FLASH nine wait states /
lypinator	0:bb348c97df44	446	#define LL_FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS /!< FLASH ten wait states /
lypinator	0:bb348c97df44	447	#define LL_FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS /!< FLASH eleven wait states /
lypinator	0:bb348c97df44	448	#define LL_FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS /!< FLASH twelve wait states /
lypinator	0:bb348c97df44	449	#define LL_FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS /!< FLASH thirteen wait states /
lypinator	0:bb348c97df44	450	#define LL_FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS /!< FLASH fourteen wait states /
lypinator	0:bb348c97df44	451	#define LL_FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS /!< FLASH fifteen wait states /
lypinator	0:bb348c97df44	452	/**
lypinator	0:bb348c97df44	453	* @}
lypinator	0:bb348c97df44	454	*/
lypinator	0:bb348c97df44	455
lypinator	0:bb348c97df44	456	/**
lypinator	0:bb348c97df44	457	* @}
lypinator	0:bb348c97df44	458	*/
lypinator	0:bb348c97df44	459
lypinator	0:bb348c97df44	460	/* Exported macro ------------------------------------------------------------*/
lypinator	0:bb348c97df44	461
lypinator	0:bb348c97df44	462	/* Exported functions --------------------------------------------------------*/
lypinator	0:bb348c97df44	463	/** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions
lypinator	0:bb348c97df44	464	* @{
lypinator	0:bb348c97df44	465	*/
lypinator	0:bb348c97df44	466
lypinator	0:bb348c97df44	467	/** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG
lypinator	0:bb348c97df44	468	* @{
lypinator	0:bb348c97df44	469	*/
lypinator	0:bb348c97df44	470	/**
lypinator	0:bb348c97df44	471	* @brief Set memory mapping at address 0x00000000
lypinator	0:bb348c97df44	472	* @rmtoll SYSCFG_MEMRMP MEM_MODE LL_SYSCFG_SetRemapMemory
lypinator	0:bb348c97df44	473	* @param Memory This parameter can be one of the following values:
lypinator	0:bb348c97df44	474	* @arg @ref LL_SYSCFG_REMAP_FLASH
lypinator	0:bb348c97df44	475	* @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
lypinator	0:bb348c97df44	476	* @arg @ref LL_SYSCFG_REMAP_SRAM
lypinator	0:bb348c97df44	477	* @arg @ref LL_SYSCFG_REMAP_FSMC (*)
lypinator	0:bb348c97df44	478	* @arg @ref LL_SYSCFG_REMAP_FMC (*)
lypinator	0:bb348c97df44	479	* @retval None
lypinator	0:bb348c97df44	480	*/
lypinator	0:bb348c97df44	481	__STATIC_INLINE void LL_SYSCFG_SetRemapMemory(uint32_t Memory)
lypinator	0:bb348c97df44	482	{
lypinator	0:bb348c97df44	483	MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, Memory);
lypinator	0:bb348c97df44	484	}
lypinator	0:bb348c97df44	485
lypinator	0:bb348c97df44	486	/**
lypinator	0:bb348c97df44	487	* @brief Get memory mapping at address 0x00000000
lypinator	0:bb348c97df44	488	* @rmtoll SYSCFG_MEMRMP MEM_MODE LL_SYSCFG_GetRemapMemory
lypinator	0:bb348c97df44	489	* @retval Returned value can be one of the following values:
lypinator	0:bb348c97df44	490	* @arg @ref LL_SYSCFG_REMAP_FLASH
lypinator	0:bb348c97df44	491	* @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
lypinator	0:bb348c97df44	492	* @arg @ref LL_SYSCFG_REMAP_SRAM
lypinator	0:bb348c97df44	493	* @arg @ref LL_SYSCFG_REMAP_FSMC (*)
lypinator	0:bb348c97df44	494	* @arg @ref LL_SYSCFG_REMAP_FMC (*)
lypinator	0:bb348c97df44	495	*/
lypinator	0:bb348c97df44	496	__STATIC_INLINE uint32_t LL_SYSCFG_GetRemapMemory(void)
lypinator	0:bb348c97df44	497	{
lypinator	0:bb348c97df44	498	return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE));
lypinator	0:bb348c97df44	499	}
lypinator	0:bb348c97df44	500
lypinator	0:bb348c97df44	501	#if defined(SYSCFG_MEMRMP_SWP_FMC)
lypinator	0:bb348c97df44	502	/**
lypinator	0:bb348c97df44	503	* @brief Enables the FMC Memory Mapping Swapping
lypinator	0:bb348c97df44	504	* @rmtoll SYSCFG_MEMRMP SWP_FMC LL_SYSCFG_EnableFMCMemorySwapping
lypinator	0:bb348c97df44	505	* @note SDRAM is accessible at 0x60000000 and NOR/RAM
lypinator	0:bb348c97df44	506	* is accessible at 0xC0000000
lypinator	0:bb348c97df44	507	* @retval None
lypinator	0:bb348c97df44	508	*/
lypinator	0:bb348c97df44	509	__STATIC_INLINE void LL_SYSCFG_EnableFMCMemorySwapping(void)
lypinator	0:bb348c97df44	510	{
lypinator	0:bb348c97df44	511	SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_SWP_FMC_0);
lypinator	0:bb348c97df44	512	}
lypinator	0:bb348c97df44	513
lypinator	0:bb348c97df44	514	/**
lypinator	0:bb348c97df44	515	* @brief Disables the FMC Memory Mapping Swapping
lypinator	0:bb348c97df44	516	* @rmtoll SYSCFG_MEMRMP SWP_FMC LL_SYSCFG_DisableFMCMemorySwapping
lypinator	0:bb348c97df44	517	* @note SDRAM is accessible at 0xC0000000 (default mapping)
lypinator	0:bb348c97df44	518	* and NOR/RAM is accessible at 0x60000000 (default mapping)
lypinator	0:bb348c97df44	519	* @retval None
lypinator	0:bb348c97df44	520	*/
lypinator	0:bb348c97df44	521	__STATIC_INLINE void LL_SYSCFG_DisableFMCMemorySwapping(void)
lypinator	0:bb348c97df44	522	{
lypinator	0:bb348c97df44	523	CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_SWP_FMC);
lypinator	0:bb348c97df44	524	}
lypinator	0:bb348c97df44	525
lypinator	0:bb348c97df44	526	#endif /* SYSCFG_MEMRMP_SWP_FMC */
lypinator	0:bb348c97df44	527	/**
lypinator	0:bb348c97df44	528	* @brief Enables the Compensation cell Power Down
lypinator	0:bb348c97df44	529	* @rmtoll SYSCFG_CMPCR CMP_PD LL_SYSCFG_EnableCompensationCell
lypinator	0:bb348c97df44	530	* @note The I/O compensation cell can be used only when the device supply
lypinator	0:bb348c97df44	531	* voltage ranges from 2.4 to 3.6 V
lypinator	0:bb348c97df44	532	* @retval None
lypinator	0:bb348c97df44	533	*/
lypinator	0:bb348c97df44	534	__STATIC_INLINE void LL_SYSCFG_EnableCompensationCell(void)
lypinator	0:bb348c97df44	535	{
lypinator	0:bb348c97df44	536	SET_BIT(SYSCFG->CMPCR, SYSCFG_CMPCR_CMP_PD);
lypinator	0:bb348c97df44	537	}
lypinator	0:bb348c97df44	538
lypinator	0:bb348c97df44	539	/**
lypinator	0:bb348c97df44	540	* @brief Disables the Compensation cell Power Down
lypinator	0:bb348c97df44	541	* @rmtoll SYSCFG_CMPCR CMP_PD LL_SYSCFG_DisableCompensationCell
lypinator	0:bb348c97df44	542	* @note The I/O compensation cell can be used only when the device supply
lypinator	0:bb348c97df44	543	* voltage ranges from 2.4 to 3.6 V
lypinator	0:bb348c97df44	544	* @retval None
lypinator	0:bb348c97df44	545	*/
lypinator	0:bb348c97df44	546	__STATIC_INLINE void LL_SYSCFG_DisableCompensationCell(void)
lypinator	0:bb348c97df44	547	{
lypinator	0:bb348c97df44	548	CLEAR_BIT(SYSCFG->CMPCR, SYSCFG_CMPCR_CMP_PD);
lypinator	0:bb348c97df44	549	}
lypinator	0:bb348c97df44	550
lypinator	0:bb348c97df44	551	/**
lypinator	0:bb348c97df44	552	* @brief Get Compensation Cell ready Flag
lypinator	0:bb348c97df44	553	* @rmtoll SYSCFG_CMPCR READY LL_SYSCFG_IsActiveFlag_CMPCR
lypinator	0:bb348c97df44	554	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	555	*/
lypinator	0:bb348c97df44	556	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CMPCR(void)
lypinator	0:bb348c97df44	557	{
lypinator	0:bb348c97df44	558	return (READ_BIT(SYSCFG->CMPCR, SYSCFG_CMPCR_READY) == (SYSCFG_CMPCR_READY));
lypinator	0:bb348c97df44	559	}
lypinator	0:bb348c97df44	560
lypinator	0:bb348c97df44	561	#if defined(SYSCFG_PMC_MII_RMII_SEL)
lypinator	0:bb348c97df44	562	/**
lypinator	0:bb348c97df44	563	* @brief Select Ethernet PHY interface
lypinator	0:bb348c97df44	564	* @rmtoll SYSCFG_PMC MII_RMII_SEL LL_SYSCFG_SetPHYInterface
lypinator	0:bb348c97df44	565	* @param Interface This parameter can be one of the following values:
lypinator	0:bb348c97df44	566	* @arg @ref LL_SYSCFG_PMC_ETHMII
lypinator	0:bb348c97df44	567	* @arg @ref LL_SYSCFG_PMC_ETHRMII
lypinator	0:bb348c97df44	568	* @retval None
lypinator	0:bb348c97df44	569	*/
lypinator	0:bb348c97df44	570	__STATIC_INLINE void LL_SYSCFG_SetPHYInterface(uint32_t Interface)
lypinator	0:bb348c97df44	571	{
lypinator	0:bb348c97df44	572	MODIFY_REG(SYSCFG->PMC, SYSCFG_PMC_MII_RMII_SEL, Interface);
lypinator	0:bb348c97df44	573	}
lypinator	0:bb348c97df44	574
lypinator	0:bb348c97df44	575	/**
lypinator	0:bb348c97df44	576	* @brief Get Ethernet PHY interface
lypinator	0:bb348c97df44	577	* @rmtoll SYSCFG_PMC MII_RMII_SEL LL_SYSCFG_GetPHYInterface
lypinator	0:bb348c97df44	578	* @retval Returned value can be one of the following values:
lypinator	0:bb348c97df44	579	* @arg @ref LL_SYSCFG_PMC_ETHMII
lypinator	0:bb348c97df44	580	* @arg @ref LL_SYSCFG_PMC_ETHRMII
lypinator	0:bb348c97df44	581	* @retval None
lypinator	0:bb348c97df44	582	*/
lypinator	0:bb348c97df44	583	__STATIC_INLINE uint32_t LL_SYSCFG_GetPHYInterface(void)
lypinator	0:bb348c97df44	584	{
lypinator	0:bb348c97df44	585	return (uint32_t)(READ_BIT(SYSCFG->PMC, SYSCFG_PMC_MII_RMII_SEL));
lypinator	0:bb348c97df44	586	}
lypinator	0:bb348c97df44	587	#endif /* SYSCFG_PMC_MII_RMII_SEL */
lypinator	0:bb348c97df44	588
lypinator	0:bb348c97df44	589
lypinator	0:bb348c97df44	590
lypinator	0:bb348c97df44	591	#if defined(SYSCFG_MEMRMP_UFB_MODE)
lypinator	0:bb348c97df44	592	/**
lypinator	0:bb348c97df44	593	* @brief Select Flash bank mode (Bank flashed at 0x08000000)
lypinator	0:bb348c97df44	594	* @rmtoll SYSCFG_MEMRMP UFB_MODE LL_SYSCFG_SetFlashBankMode
lypinator	0:bb348c97df44	595	* @param Bank This parameter can be one of the following values:
lypinator	0:bb348c97df44	596	* @arg @ref LL_SYSCFG_BANKMODE_BANK1
lypinator	0:bb348c97df44	597	* @arg @ref LL_SYSCFG_BANKMODE_BANK2
lypinator	0:bb348c97df44	598	* @retval None
lypinator	0:bb348c97df44	599	*/
lypinator	0:bb348c97df44	600	__STATIC_INLINE void LL_SYSCFG_SetFlashBankMode(uint32_t Bank)
lypinator	0:bb348c97df44	601	{
lypinator	0:bb348c97df44	602	MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_UFB_MODE, Bank);
lypinator	0:bb348c97df44	603	}
lypinator	0:bb348c97df44	604
lypinator	0:bb348c97df44	605	/**
lypinator	0:bb348c97df44	606	* @brief Get Flash bank mode (Bank flashed at 0x08000000)
lypinator	0:bb348c97df44	607	* @rmtoll SYSCFG_MEMRMP UFB_MODE LL_SYSCFG_GetFlashBankMode
lypinator	0:bb348c97df44	608	* @retval Returned value can be one of the following values:
lypinator	0:bb348c97df44	609	* @arg @ref LL_SYSCFG_BANKMODE_BANK1
lypinator	0:bb348c97df44	610	* @arg @ref LL_SYSCFG_BANKMODE_BANK2
lypinator	0:bb348c97df44	611	*/
lypinator	0:bb348c97df44	612	__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashBankMode(void)
lypinator	0:bb348c97df44	613	{
lypinator	0:bb348c97df44	614	return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_UFB_MODE));
lypinator	0:bb348c97df44	615	}
lypinator	0:bb348c97df44	616	#endif /* SYSCFG_MEMRMP_UFB_MODE */
lypinator	0:bb348c97df44	617
lypinator	0:bb348c97df44	618	#if defined(SYSCFG_CFGR_FMPI2C1_SCL)
lypinator	0:bb348c97df44	619	/**
lypinator	0:bb348c97df44	620	* @brief Enable the I2C fast mode plus driving capability.
lypinator	0:bb348c97df44	621	* @rmtoll SYSCFG_CFGR FMPI2C1_SCL LL_SYSCFG_EnableFastModePlus\n
lypinator	0:bb348c97df44	622	* SYSCFG_CFGR FMPI2C1_SDA LL_SYSCFG_EnableFastModePlus
lypinator	0:bb348c97df44	623	* @param ConfigFastModePlus This parameter can be a combination of the following values:
lypinator	0:bb348c97df44	624	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_SCL
lypinator	0:bb348c97df44	625	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_SDA
lypinator	0:bb348c97df44	626	* (*) value not defined in all devices
lypinator	0:bb348c97df44	627	* @retval None
lypinator	0:bb348c97df44	628	*/
lypinator	0:bb348c97df44	629	__STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)
lypinator	0:bb348c97df44	630	{
lypinator	0:bb348c97df44	631	SET_BIT(SYSCFG->CFGR, ConfigFastModePlus);
lypinator	0:bb348c97df44	632	}
lypinator	0:bb348c97df44	633
lypinator	0:bb348c97df44	634	/**
lypinator	0:bb348c97df44	635	* @brief Disable the I2C fast mode plus driving capability.
lypinator	0:bb348c97df44	636	* @rmtoll SYSCFG_CFGR FMPI2C1_SCL LL_SYSCFG_DisableFastModePlus\n
lypinator	0:bb348c97df44	637	* SYSCFG_CFGR FMPI2C1_SDA LL_SYSCFG_DisableFastModePlus\n
lypinator	0:bb348c97df44	638	* @param ConfigFastModePlus This parameter can be a combination of the following values:
lypinator	0:bb348c97df44	639	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_SCL
lypinator	0:bb348c97df44	640	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_SDA
lypinator	0:bb348c97df44	641	* (*) value not defined in all devices
lypinator	0:bb348c97df44	642	* @retval None
lypinator	0:bb348c97df44	643	*/
lypinator	0:bb348c97df44	644	__STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)
lypinator	0:bb348c97df44	645	{
lypinator	0:bb348c97df44	646	CLEAR_BIT(SYSCFG->CFGR, ConfigFastModePlus);
lypinator	0:bb348c97df44	647	}
lypinator	0:bb348c97df44	648	#endif /* SYSCFG_CFGR_FMPI2C1_SCL */
lypinator	0:bb348c97df44	649
lypinator	0:bb348c97df44	650	/**
lypinator	0:bb348c97df44	651	* @brief Configure source input for the EXTI external interrupt.
lypinator	0:bb348c97df44	652	* @rmtoll SYSCFG_EXTICR1 EXTIx LL_SYSCFG_SetEXTISource\n
lypinator	0:bb348c97df44	653	* SYSCFG_EXTICR2 EXTIx LL_SYSCFG_SetEXTISource\n
lypinator	0:bb348c97df44	654	* SYSCFG_EXTICR3 EXTIx LL_SYSCFG_SetEXTISource\n
lypinator	0:bb348c97df44	655	* SYSCFG_EXTICR4 EXTIx LL_SYSCFG_SetEXTISource
lypinator	0:bb348c97df44	656	* @param Port This parameter can be one of the following values:
lypinator	0:bb348c97df44	657	* @arg @ref LL_SYSCFG_EXTI_PORTA
lypinator	0:bb348c97df44	658	* @arg @ref LL_SYSCFG_EXTI_PORTB
lypinator	0:bb348c97df44	659	* @arg @ref LL_SYSCFG_EXTI_PORTC
lypinator	0:bb348c97df44	660	* @arg @ref LL_SYSCFG_EXTI_PORTD
lypinator	0:bb348c97df44	661	* @arg @ref LL_SYSCFG_EXTI_PORTE
lypinator	0:bb348c97df44	662	* @arg @ref LL_SYSCFG_EXTI_PORTF (*)
lypinator	0:bb348c97df44	663	* @arg @ref LL_SYSCFG_EXTI_PORTG (*)
lypinator	0:bb348c97df44	664	* @arg @ref LL_SYSCFG_EXTI_PORTH
lypinator	0:bb348c97df44	665	*
lypinator	0:bb348c97df44	666	* (*) value not defined in all devices
lypinator	0:bb348c97df44	667	* @param Line This parameter can be one of the following values:
lypinator	0:bb348c97df44	668	* @arg @ref LL_SYSCFG_EXTI_LINE0
lypinator	0:bb348c97df44	669	* @arg @ref LL_SYSCFG_EXTI_LINE1
lypinator	0:bb348c97df44	670	* @arg @ref LL_SYSCFG_EXTI_LINE2
lypinator	0:bb348c97df44	671	* @arg @ref LL_SYSCFG_EXTI_LINE3
lypinator	0:bb348c97df44	672	* @arg @ref LL_SYSCFG_EXTI_LINE4
lypinator	0:bb348c97df44	673	* @arg @ref LL_SYSCFG_EXTI_LINE5
lypinator	0:bb348c97df44	674	* @arg @ref LL_SYSCFG_EXTI_LINE6
lypinator	0:bb348c97df44	675	* @arg @ref LL_SYSCFG_EXTI_LINE7
lypinator	0:bb348c97df44	676	* @arg @ref LL_SYSCFG_EXTI_LINE8
lypinator	0:bb348c97df44	677	* @arg @ref LL_SYSCFG_EXTI_LINE9
lypinator	0:bb348c97df44	678	* @arg @ref LL_SYSCFG_EXTI_LINE10
lypinator	0:bb348c97df44	679	* @arg @ref LL_SYSCFG_EXTI_LINE11
lypinator	0:bb348c97df44	680	* @arg @ref LL_SYSCFG_EXTI_LINE12
lypinator	0:bb348c97df44	681	* @arg @ref LL_SYSCFG_EXTI_LINE13
lypinator	0:bb348c97df44	682	* @arg @ref LL_SYSCFG_EXTI_LINE14
lypinator	0:bb348c97df44	683	* @arg @ref LL_SYSCFG_EXTI_LINE15
lypinator	0:bb348c97df44	684	* @retval None
lypinator	0:bb348c97df44	685	*/
lypinator	0:bb348c97df44	686	__STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line)
lypinator	0:bb348c97df44	687	{
lypinator	0:bb348c97df44	688	MODIFY_REG(SYSCFG->EXTICR[Line & 0xFF], (Line >> 16), Port << POSITION_VAL((Line >> 16)));
lypinator	0:bb348c97df44	689	}
lypinator	0:bb348c97df44	690
lypinator	0:bb348c97df44	691	/**
lypinator	0:bb348c97df44	692	* @brief Get the configured defined for specific EXTI Line
lypinator	0:bb348c97df44	693	* @rmtoll SYSCFG_EXTICR1 EXTIx LL_SYSCFG_GetEXTISource\n
lypinator	0:bb348c97df44	694	* SYSCFG_EXTICR2 EXTIx LL_SYSCFG_GetEXTISource\n
lypinator	0:bb348c97df44	695	* SYSCFG_EXTICR3 EXTIx LL_SYSCFG_GetEXTISource\n
lypinator	0:bb348c97df44	696	* SYSCFG_EXTICR4 EXTIx LL_SYSCFG_GetEXTISource
lypinator	0:bb348c97df44	697	* @param Line This parameter can be one of the following values:
lypinator	0:bb348c97df44	698	* @arg @ref LL_SYSCFG_EXTI_LINE0
lypinator	0:bb348c97df44	699	* @arg @ref LL_SYSCFG_EXTI_LINE1
lypinator	0:bb348c97df44	700	* @arg @ref LL_SYSCFG_EXTI_LINE2
lypinator	0:bb348c97df44	701	* @arg @ref LL_SYSCFG_EXTI_LINE3
lypinator	0:bb348c97df44	702	* @arg @ref LL_SYSCFG_EXTI_LINE4
lypinator	0:bb348c97df44	703	* @arg @ref LL_SYSCFG_EXTI_LINE5
lypinator	0:bb348c97df44	704	* @arg @ref LL_SYSCFG_EXTI_LINE6
lypinator	0:bb348c97df44	705	* @arg @ref LL_SYSCFG_EXTI_LINE7
lypinator	0:bb348c97df44	706	* @arg @ref LL_SYSCFG_EXTI_LINE8
lypinator	0:bb348c97df44	707	* @arg @ref LL_SYSCFG_EXTI_LINE9
lypinator	0:bb348c97df44	708	* @arg @ref LL_SYSCFG_EXTI_LINE10
lypinator	0:bb348c97df44	709	* @arg @ref LL_SYSCFG_EXTI_LINE11
lypinator	0:bb348c97df44	710	* @arg @ref LL_SYSCFG_EXTI_LINE12
lypinator	0:bb348c97df44	711	* @arg @ref LL_SYSCFG_EXTI_LINE13
lypinator	0:bb348c97df44	712	* @arg @ref LL_SYSCFG_EXTI_LINE14
lypinator	0:bb348c97df44	713	* @arg @ref LL_SYSCFG_EXTI_LINE15
lypinator	0:bb348c97df44	714	* @retval Returned value can be one of the following values:
lypinator	0:bb348c97df44	715	* @arg @ref LL_SYSCFG_EXTI_PORTA
lypinator	0:bb348c97df44	716	* @arg @ref LL_SYSCFG_EXTI_PORTB
lypinator	0:bb348c97df44	717	* @arg @ref LL_SYSCFG_EXTI_PORTC
lypinator	0:bb348c97df44	718	* @arg @ref LL_SYSCFG_EXTI_PORTD
lypinator	0:bb348c97df44	719	* @arg @ref LL_SYSCFG_EXTI_PORTE
lypinator	0:bb348c97df44	720	* @arg @ref LL_SYSCFG_EXTI_PORTF (*)
lypinator	0:bb348c97df44	721	* @arg @ref LL_SYSCFG_EXTI_PORTG (*)
lypinator	0:bb348c97df44	722	* @arg @ref LL_SYSCFG_EXTI_PORTH
lypinator	0:bb348c97df44	723	* (*) value not defined in all devices
lypinator	0:bb348c97df44	724	*/
lypinator	0:bb348c97df44	725	__STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line)
lypinator	0:bb348c97df44	726	{
lypinator	0:bb348c97df44	727	return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0xFF], (Line >> 16)) >> POSITION_VAL(Line >> 16));
lypinator	0:bb348c97df44	728	}
lypinator	0:bb348c97df44	729
lypinator	0:bb348c97df44	730	#if defined(SYSCFG_CFGR2_LOCKUP_LOCK)
lypinator	0:bb348c97df44	731	/**
lypinator	0:bb348c97df44	732	* @brief Set connections to TIM1/8 break inputs
lypinator	0:bb348c97df44	733	* @rmtoll SYSCFG_CFGR2 LockUp Lock LL_SYSCFG_SetTIMBreakInputs \n
lypinator	0:bb348c97df44	734	* SYSCFG_CFGR2 PVD Lock LL_SYSCFG_SetTIMBreakInputs
lypinator	0:bb348c97df44	735	* @param Break This parameter can be a combination of the following values:
lypinator	0:bb348c97df44	736	* @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
lypinator	0:bb348c97df44	737	* @arg @ref LL_SYSCFG_TIMBREAK_PVD
lypinator	0:bb348c97df44	738	* @retval None
lypinator	0:bb348c97df44	739	*/
lypinator	0:bb348c97df44	740	__STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break)
lypinator	0:bb348c97df44	741	{
lypinator	0:bb348c97df44	742	MODIFY_REG(SYSCFG->CFGR2, SYSCFG_CFGR2_LOCKUP_LOCK \| SYSCFG_CFGR2_PVD_LOCK, Break);
lypinator	0:bb348c97df44	743	}
lypinator	0:bb348c97df44	744
lypinator	0:bb348c97df44	745	/**
lypinator	0:bb348c97df44	746	* @brief Get connections to TIM1/8 Break inputs
lypinator	0:bb348c97df44	747	* @rmtoll SYSCFG_CFGR2 LockUp Lock LL_SYSCFG_SetTIMBreakInputs \n
lypinator	0:bb348c97df44	748	* SYSCFG_CFGR2 PVD Lock LL_SYSCFG_SetTIMBreakInputs
lypinator	0:bb348c97df44	749	* @retval Returned value can be can be a combination of the following values:
lypinator	0:bb348c97df44	750	* @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
lypinator	0:bb348c97df44	751	* @arg @ref LL_SYSCFG_TIMBREAK_PVD
lypinator	0:bb348c97df44	752	*/
lypinator	0:bb348c97df44	753	__STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void)
lypinator	0:bb348c97df44	754	{
lypinator	0:bb348c97df44	755	return (uint32_t)(READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_LOCKUP_LOCK \| SYSCFG_CFGR2_PVD_LOCK));
lypinator	0:bb348c97df44	756	}
lypinator	0:bb348c97df44	757	#endif /* SYSCFG_CFGR2_LOCKUP_LOCK */
lypinator	0:bb348c97df44	758	#if defined(SYSCFG_MCHDLYCR_BSCKSEL)
lypinator	0:bb348c97df44	759	/**
lypinator	0:bb348c97df44	760	* @brief Select the DFSDM2 or TIM2_OC1 as clock source for the bitstream clock.
lypinator	0:bb348c97df44	761	* @rmtoll SYSCFG_MCHDLYCR BSCKSEL LL_SYSCFG_DFSDM_SetBitstreamClockSourceSelection
lypinator	0:bb348c97df44	762	* @param ClockSource This parameter can be one of the following values:
lypinator	0:bb348c97df44	763	* @arg @ref LL_SYSCFG_BITSTREAM_CLOCK_DFSDM2
lypinator	0:bb348c97df44	764	* @arg @ref LL_SYSCFG_BITSTREAM_CLOCK_TIM2OC1
lypinator	0:bb348c97df44	765	* @retval None
lypinator	0:bb348c97df44	766	*/
lypinator	0:bb348c97df44	767	__STATIC_INLINE void LL_SYSCFG_DFSDM_SetBitstreamClockSourceSelection(uint32_t ClockSource)
lypinator	0:bb348c97df44	768	{
lypinator	0:bb348c97df44	769	MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_BSCKSEL, ClockSource);
lypinator	0:bb348c97df44	770	}
lypinator	0:bb348c97df44	771	/**
lypinator	0:bb348c97df44	772	* @brief Get the DFSDM2 or TIM2_OC1 as clock source for the bitstream clock.
lypinator	0:bb348c97df44	773	* @rmtoll SYSCFG_MCHDLYCR BSCKSEL LL_SYSCFG_DFSDM_GetBitstreamClockSourceSelection
lypinator	0:bb348c97df44	774	* @retval Returned value can be one of the following values:
lypinator	0:bb348c97df44	775	* @arg @ref LL_SYSCFG_BITSTREAM_CLOCK_DFSDM2
lypinator	0:bb348c97df44	776	* @arg @ref LL_SYSCFG_BITSTREAM_CLOCK_TIM2OC1
lypinator	0:bb348c97df44	777	* @retval None
lypinator	0:bb348c97df44	778	*/
lypinator	0:bb348c97df44	779	__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM_GetBitstreamClockSourceSelection(void)
lypinator	0:bb348c97df44	780	{
lypinator	0:bb348c97df44	781	return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_BSCKSEL));
lypinator	0:bb348c97df44	782	}
lypinator	0:bb348c97df44	783	/**
lypinator	0:bb348c97df44	784	* @brief Enables the DFSDM1 or DFSDM2 Delay clock
lypinator	0:bb348c97df44	785	* @rmtoll SYSCFG_MCHDLYCR MCHDLYEN LL_SYSCFG_DFSDM_EnableDelayClock
lypinator	0:bb348c97df44	786	* @param MCHDLY This paramater can be one of the following values
lypinator	0:bb348c97df44	787	* @arg @ref LL_SYSCFG_DFSDM1_MCHDLYEN
lypinator	0:bb348c97df44	788	* @arg @ref LL_SYSCFG_DFSDM2_MCHDLYEN
lypinator	0:bb348c97df44	789	* @retval None
lypinator	0:bb348c97df44	790	*/
lypinator	0:bb348c97df44	791	__STATIC_INLINE void LL_SYSCFG_DFSDM_EnableDelayClock(uint32_t MCHDLY)
lypinator	0:bb348c97df44	792	{
lypinator	0:bb348c97df44	793	SET_BIT(SYSCFG->MCHDLYCR, MCHDLY);
lypinator	0:bb348c97df44	794	}
lypinator	0:bb348c97df44	795
lypinator	0:bb348c97df44	796	/**
lypinator	0:bb348c97df44	797	* @brief Disables the DFSDM1 or the DFSDM2 Delay clock
lypinator	0:bb348c97df44	798	* @rmtoll SYSCFG_MCHDLYCR MCHDLY1EN LL_SYSCFG_DFSDM1_DisableDelayClock
lypinator	0:bb348c97df44	799	* @param MCHDLY This paramater can be one of the following values
lypinator	0:bb348c97df44	800	* @arg @ref LL_SYSCFG_DFSDM1_MCHDLYEN
lypinator	0:bb348c97df44	801	* @arg @ref LL_SYSCFG_DFSDM2_MCHDLYEN
lypinator	0:bb348c97df44	802	* @retval None
lypinator	0:bb348c97df44	803	*/
lypinator	0:bb348c97df44	804	__STATIC_INLINE void LL_SYSCFG_DFSDM_DisableDelayClock(uint32_t MCHDLY)
lypinator	0:bb348c97df44	805	{
lypinator	0:bb348c97df44	806	CLEAR_BIT(SYSCFG->MCHDLYCR, MCHDLY);
lypinator	0:bb348c97df44	807	}
lypinator	0:bb348c97df44	808
lypinator	0:bb348c97df44	809	/**
lypinator	0:bb348c97df44	810	* @brief Select the source for DFSDM1 or DFSDM2 DatIn0
lypinator	0:bb348c97df44	811	* @rmtoll SYSCFG_MCHDLYCR DFSDMD0SEL LL_SYSCFG_DFSDM_SetDataIn0Source
lypinator	0:bb348c97df44	812	* @param Source This parameter can be one of the following values:
lypinator	0:bb348c97df44	813	* @arg @ref LL_SYSCFG_DFSDM1_DataIn0_PAD
lypinator	0:bb348c97df44	814	* @arg @ref LL_SYSCFG_DFSDM1_DataIn0_DM
lypinator	0:bb348c97df44	815	* @arg @ref LL_SYSCFG_DFSDM2_DataIn0_PAD
lypinator	0:bb348c97df44	816	* @arg @ref LL_SYSCFG_DFSDM2_DataIn0_DM
lypinator	0:bb348c97df44	817	* @retval None
lypinator	0:bb348c97df44	818	*/
lypinator	0:bb348c97df44	819	__STATIC_INLINE void LL_SYSCFG_DFSDM_SetDataIn0Source(uint32_t Source)
lypinator	0:bb348c97df44	820	{
lypinator	0:bb348c97df44	821	MODIFY_REG(SYSCFG->MCHDLYCR, (Source >> 16), (Source & 0x0000FFFF));
lypinator	0:bb348c97df44	822	}
lypinator	0:bb348c97df44	823	/**
lypinator	0:bb348c97df44	824	* @brief Get the source for DFSDM1 or DFSDM2 DatIn0.
lypinator	0:bb348c97df44	825	* @rmtoll SYSCFG_MCHDLYCR DFSDMD0SEL LL_SYSCFG_DFSDM_GetDataIn0Source
lypinator	0:bb348c97df44	826	* @param Source This parameter can be one of the following values:
lypinator	0:bb348c97df44	827	* @arg @ref LL_SYSCFG_DFSDM1_DataIn0
lypinator	0:bb348c97df44	828	* @arg @ref LL_SYSCFG_DFSDM2_DataIn0
lypinator	0:bb348c97df44	829	* @retval Returned value can be one of the following values:
lypinator	0:bb348c97df44	830	* @arg @ref LL_SYSCFG_DFSDM1_DataIn0_PAD
lypinator	0:bb348c97df44	831	* @arg @ref LL_SYSCFG_DFSDM1_DataIn0_DM
lypinator	0:bb348c97df44	832	* @arg @ref LL_SYSCFG_DFSDM2_DataIn0_PAD
lypinator	0:bb348c97df44	833	* @arg @ref LL_SYSCFG_DFSDM2_DataIn0_DM
lypinator	0:bb348c97df44	834	* @retval None
lypinator	0:bb348c97df44	835	*/
lypinator	0:bb348c97df44	836	__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM_GetDataIn0Source(uint32_t Source)
lypinator	0:bb348c97df44	837	{
lypinator	0:bb348c97df44	838	return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, Source));
lypinator	0:bb348c97df44	839	}
lypinator	0:bb348c97df44	840	/**
lypinator	0:bb348c97df44	841	* @brief Select the source for DFSDM1 or DFSDM2 DatIn2
lypinator	0:bb348c97df44	842	* @rmtoll SYSCFG_MCHDLYCR DFSDMD2SEL LL_SYSCFG_DFSDM_SetDataIn2Source
lypinator	0:bb348c97df44	843	* @param Source This parameter can be one of the following values:
lypinator	0:bb348c97df44	844	* @arg @ref LL_SYSCFG_DFSDM1_DataIn2_PAD
lypinator	0:bb348c97df44	845	* @arg @ref LL_SYSCFG_DFSDM1_DataIn2_DM
lypinator	0:bb348c97df44	846	* @arg @ref LL_SYSCFG_DFSDM2_DataIn2_PAD
lypinator	0:bb348c97df44	847	* @arg @ref LL_SYSCFG_DFSDM2_DataIn2_DM
lypinator	0:bb348c97df44	848	* @retval None
lypinator	0:bb348c97df44	849	*/
lypinator	0:bb348c97df44	850	__STATIC_INLINE void LL_SYSCFG_DFSDM_SetDataIn2Source(uint32_t Source)
lypinator	0:bb348c97df44	851	{
lypinator	0:bb348c97df44	852	MODIFY_REG(SYSCFG->MCHDLYCR, (Source >> 16), (Source & 0x0000FFFF));
lypinator	0:bb348c97df44	853	}
lypinator	0:bb348c97df44	854	/**
lypinator	0:bb348c97df44	855	* @brief Get the source for DFSDM1 or DFSDM2 DatIn2.
lypinator	0:bb348c97df44	856	* @rmtoll SYSCFG_MCHDLYCR DFSDMD2SEL LL_SYSCFG_DFSDM_GetDataIn2Source
lypinator	0:bb348c97df44	857	* @param Source This parameter can be one of the following values:
lypinator	0:bb348c97df44	858	* @arg @ref LL_SYSCFG_DFSDM1_DataIn2
lypinator	0:bb348c97df44	859	* @arg @ref LL_SYSCFG_DFSDM2_DataIn2
lypinator	0:bb348c97df44	860	* @retval Returned value can be one of the following values:
lypinator	0:bb348c97df44	861	* @arg @ref LL_SYSCFG_DFSDM1_DataIn2_PAD
lypinator	0:bb348c97df44	862	* @arg @ref LL_SYSCFG_DFSDM1_DataIn2_DM
lypinator	0:bb348c97df44	863	* @arg @ref LL_SYSCFG_DFSDM2_DataIn2_PAD
lypinator	0:bb348c97df44	864	* @arg @ref LL_SYSCFG_DFSDM2_DataIn2_DM
lypinator	0:bb348c97df44	865	* @retval None
lypinator	0:bb348c97df44	866	*/
lypinator	0:bb348c97df44	867	__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM_GetDataIn2Source(uint32_t Source)
lypinator	0:bb348c97df44	868	{
lypinator	0:bb348c97df44	869	return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, Source));
lypinator	0:bb348c97df44	870	}
lypinator	0:bb348c97df44	871
lypinator	0:bb348c97df44	872	/**
lypinator	0:bb348c97df44	873	* @brief Select the distribution of the bitsream lock gated by TIM4 OC2
lypinator	0:bb348c97df44	874	* @rmtoll SYSCFG_MCHDLYCR DFSDM1CK02SEL LL_SYSCFG_DFSDM1_SetTIM4OC2BitStreamDistribution
lypinator	0:bb348c97df44	875	* @param Source This parameter can be one of the following values:
lypinator	0:bb348c97df44	876	* @arg @ref LL_SYSCFG_DFSDM1_TIM4OC2_CLKIN0
lypinator	0:bb348c97df44	877	* @arg @ref LL_SYSCFG_DFSDM1_TIM4OC2_CLKIN2
lypinator	0:bb348c97df44	878	* @retval None
lypinator	0:bb348c97df44	879	*/
lypinator	0:bb348c97df44	880	__STATIC_INLINE void LL_SYSCFG_DFSDM1_SetTIM4OC2BitStreamDistribution(uint32_t Source)
lypinator	0:bb348c97df44	881	{
lypinator	0:bb348c97df44	882	MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CK02SEL, Source);
lypinator	0:bb348c97df44	883	}
lypinator	0:bb348c97df44	884	/**
lypinator	0:bb348c97df44	885	* @brief Get the distribution of the bitsream lock gated by TIM4 OC2
lypinator	0:bb348c97df44	886	* @rmtoll SYSCFG_MCHDLYCR DFSDM1D2SEL LL_SYSCFG_DFSDM1_GetTIM4OC2BitStreamDistribution
lypinator	0:bb348c97df44	887	* @retval Returned value can be one of the following values:
lypinator	0:bb348c97df44	888	* @arg @ref LL_SYSCFG_DFSDM1_TIM4OC2_CLKIN0
lypinator	0:bb348c97df44	889	* @arg @ref LL_SYSCFG_DFSDM1_TIM4OC2_CLKIN2
lypinator	0:bb348c97df44	890	* @retval None
lypinator	0:bb348c97df44	891	*/
lypinator	0:bb348c97df44	892	__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM1_GetTIM4OC2BitStreamDistribution(void)
lypinator	0:bb348c97df44	893	{
lypinator	0:bb348c97df44	894	return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CK02SEL));
lypinator	0:bb348c97df44	895	}
lypinator	0:bb348c97df44	896
lypinator	0:bb348c97df44	897	/**
lypinator	0:bb348c97df44	898	* @brief Select the distribution of the bitsream lock gated by TIM4 OC1
lypinator	0:bb348c97df44	899	* @rmtoll SYSCFG_MCHDLYCR DFSDM1CK13SEL LL_SYSCFG_DFSDM1_SetTIM4OC1BitStreamDistribution
lypinator	0:bb348c97df44	900	* @param Source This parameter can be one of the following values:
lypinator	0:bb348c97df44	901	* @arg @ref LL_SYSCFG_DFSDM1_TIM4OC1_CLKIN1
lypinator	0:bb348c97df44	902	* @arg @ref LL_SYSCFG_DFSDM1_TIM4OC1_CLKIN3
lypinator	0:bb348c97df44	903	* @retval None
lypinator	0:bb348c97df44	904	*/
lypinator	0:bb348c97df44	905	__STATIC_INLINE void LL_SYSCFG_DFSDM1_SetTIM4OC1BitStreamDistribution(uint32_t Source)
lypinator	0:bb348c97df44	906	{
lypinator	0:bb348c97df44	907	MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CK13SEL, Source);
lypinator	0:bb348c97df44	908	}
lypinator	0:bb348c97df44	909	/**
lypinator	0:bb348c97df44	910	* @brief Get the distribution of the bitsream lock gated by TIM4 OC1
lypinator	0:bb348c97df44	911	* @rmtoll SYSCFG_MCHDLYCR DFSDM1D2SEL LL_SYSCFG_DFSDM1_GetTIM4OC1BitStreamDistribution
lypinator	0:bb348c97df44	912	* @retval Returned value can be one of the following values:
lypinator	0:bb348c97df44	913	* @arg @ref LL_SYSCFG_DFSDM1_TIM4OC1_CLKIN1
lypinator	0:bb348c97df44	914	* @arg @ref LL_SYSCFG_DFSDM1_TIM4OC1_CLKIN3
lypinator	0:bb348c97df44	915	* @retval None
lypinator	0:bb348c97df44	916	*/
lypinator	0:bb348c97df44	917	__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM1_GetTIM4OC1BitStreamDistribution(void)
lypinator	0:bb348c97df44	918	{
lypinator	0:bb348c97df44	919	return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CK13SEL));
lypinator	0:bb348c97df44	920	}
lypinator	0:bb348c97df44	921
lypinator	0:bb348c97df44	922	/**
lypinator	0:bb348c97df44	923	* @brief Select the DFSDM1 Clock In
lypinator	0:bb348c97df44	924	* @rmtoll SYSCFG_MCHDLYCR DFSDM1CFG LL_SYSCFG_DFSDM1_SetClockInSourceSelection
lypinator	0:bb348c97df44	925	* @param ClockSource This parameter can be one of the following values:
lypinator	0:bb348c97df44	926	* @arg @ref LL_SYSCFG_DFSDM1_CKIN_PAD
lypinator	0:bb348c97df44	927	* @arg @ref LL_SYSCFG_DFSDM1_CKIN_DM
lypinator	0:bb348c97df44	928	* @retval None
lypinator	0:bb348c97df44	929	*/
lypinator	0:bb348c97df44	930	__STATIC_INLINE void LL_SYSCFG_DFSDM1_SetClockInSourceSelection(uint32_t ClockSource)
lypinator	0:bb348c97df44	931	{
lypinator	0:bb348c97df44	932	MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CFG, ClockSource);
lypinator	0:bb348c97df44	933	}
lypinator	0:bb348c97df44	934	/**
lypinator	0:bb348c97df44	935	* @brief GET the DFSDM1 Clock In
lypinator	0:bb348c97df44	936	* @rmtoll SYSCFG_MCHDLYCR DFSDM1CFG LL_SYSCFG_DFSDM1_GetClockInSourceSelection
lypinator	0:bb348c97df44	937	* @retval Returned value can be one of the following values:
lypinator	0:bb348c97df44	938	* @arg @ref LL_SYSCFG_DFSDM1_CKIN_PAD
lypinator	0:bb348c97df44	939	* @arg @ref LL_SYSCFG_DFSDM1_CKIN_DM
lypinator	0:bb348c97df44	940	* @retval None
lypinator	0:bb348c97df44	941	*/
lypinator	0:bb348c97df44	942	__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM1_GetClockInSourceSelection(void)
lypinator	0:bb348c97df44	943	{
lypinator	0:bb348c97df44	944	return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CFG));
lypinator	0:bb348c97df44	945	}
lypinator	0:bb348c97df44	946
lypinator	0:bb348c97df44	947	/**
lypinator	0:bb348c97df44	948	* @brief Select the DFSDM1 Clock Out
lypinator	0:bb348c97df44	949	* @rmtoll SYSCFG_MCHDLYCR DFSDM1CKOSEL LL_SYSCFG_DFSDM1_SetClockOutSourceSelection
lypinator	0:bb348c97df44	950	* @param ClockSource This parameter can be one of the following values:
lypinator	0:bb348c97df44	951	* @arg @ref LL_SYSCFG_DFSDM1_CKOUT
lypinator	0:bb348c97df44	952	* @arg @ref LL_SYSCFG_DFSDM1_CKOUT_M27
lypinator	0:bb348c97df44	953	* @retval None
lypinator	0:bb348c97df44	954	*/
lypinator	0:bb348c97df44	955	__STATIC_INLINE void LL_SYSCFG_DFSDM1_SetClockOutSourceSelection(uint32_t ClockSource)
lypinator	0:bb348c97df44	956	{
lypinator	0:bb348c97df44	957	MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CKOSEL, ClockSource);
lypinator	0:bb348c97df44	958	}
lypinator	0:bb348c97df44	959	/**
lypinator	0:bb348c97df44	960	* @brief GET the DFSDM1 Clock Out
lypinator	0:bb348c97df44	961	* @rmtoll SYSCFG_MCHDLYCR DFSDM1CKOSEL LL_SYSCFG_DFSDM1_GetClockOutSourceSelection
lypinator	0:bb348c97df44	962	* @retval Returned value can be one of the following values:
lypinator	0:bb348c97df44	963	* @arg @ref LL_SYSCFG_DFSDM1_CKOUT
lypinator	0:bb348c97df44	964	* @arg @ref LL_SYSCFG_DFSDM1_CKOUT_M27
lypinator	0:bb348c97df44	965	* @retval None
lypinator	0:bb348c97df44	966	*/
lypinator	0:bb348c97df44	967	__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM1_GetClockOutSourceSelection(void)
lypinator	0:bb348c97df44	968	{
lypinator	0:bb348c97df44	969	return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CKOSEL));
lypinator	0:bb348c97df44	970	}
lypinator	0:bb348c97df44	971
lypinator	0:bb348c97df44	972	/**
lypinator	0:bb348c97df44	973	* @brief Enables the DFSDM2 Delay clock
lypinator	0:bb348c97df44	974	* @rmtoll SYSCFG_MCHDLYCR MCHDLY2EN LL_SYSCFG_DFSDM2_EnableDelayClock
lypinator	0:bb348c97df44	975	* @retval None
lypinator	0:bb348c97df44	976	*/
lypinator	0:bb348c97df44	977	__STATIC_INLINE void LL_SYSCFG_DFSDM2_EnableDelayClock(void)
lypinator	0:bb348c97df44	978	{
lypinator	0:bb348c97df44	979	SET_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_MCHDLY2EN);
lypinator	0:bb348c97df44	980	}
lypinator	0:bb348c97df44	981
lypinator	0:bb348c97df44	982	/**
lypinator	0:bb348c97df44	983	* @brief Disables the DFSDM2 Delay clock
lypinator	0:bb348c97df44	984	* @rmtoll SYSCFG_MCHDLYCR MCHDLY2EN LL_SYSCFG_DFSDM2_DisableDelayClock
lypinator	0:bb348c97df44	985	* @retval None
lypinator	0:bb348c97df44	986	*/
lypinator	0:bb348c97df44	987	__STATIC_INLINE void LL_SYSCFG_DFSDM2_DisableDelayClock(void)
lypinator	0:bb348c97df44	988	{
lypinator	0:bb348c97df44	989	CLEAR_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_MCHDLY2EN);
lypinator	0:bb348c97df44	990	}
lypinator	0:bb348c97df44	991	/**
lypinator	0:bb348c97df44	992	* @brief Select the source for DFSDM2 DatIn0
lypinator	0:bb348c97df44	993	* @rmtoll SYSCFG_MCHDLYCR DFSDM2D0SEL LL_SYSCFG_DFSDM2_SetDataIn0Source
lypinator	0:bb348c97df44	994	* @param Source This parameter can be one of the following values:
lypinator	0:bb348c97df44	995	* @arg @ref LL_SYSCFG_DFSDM2_DataIn0_PAD
lypinator	0:bb348c97df44	996	* @arg @ref LL_SYSCFG_DFSDM2_DataIn0_DM
lypinator	0:bb348c97df44	997	* @retval None
lypinator	0:bb348c97df44	998	*/
lypinator	0:bb348c97df44	999	__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetDataIn0Source(uint32_t Source)
lypinator	0:bb348c97df44	1000	{
lypinator	0:bb348c97df44	1001	MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D0SEL, Source);
lypinator	0:bb348c97df44	1002	}
lypinator	0:bb348c97df44	1003	/**
lypinator	0:bb348c97df44	1004	* @brief Get the source for DFSDM2 DatIn0.
lypinator	0:bb348c97df44	1005	* @rmtoll SYSCFG_MCHDLYCR DFSDM2D0SEL LL_SYSCFG_DFSDM2_GetDataIn0Source
lypinator	0:bb348c97df44	1006	* @retval Returned value can be one of the following values:
lypinator	0:bb348c97df44	1007	* @arg @ref LL_SYSCFG_DFSDM2_DataIn0_PAD
lypinator	0:bb348c97df44	1008	* @arg @ref LL_SYSCFG_DFSDM2_DataIn0_DM
lypinator	0:bb348c97df44	1009	* @retval None
lypinator	0:bb348c97df44	1010	*/
lypinator	0:bb348c97df44	1011	__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetDataIn0Source(void)
lypinator	0:bb348c97df44	1012	{
lypinator	0:bb348c97df44	1013	return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D0SEL));
lypinator	0:bb348c97df44	1014	}
lypinator	0:bb348c97df44	1015
lypinator	0:bb348c97df44	1016	/**
lypinator	0:bb348c97df44	1017	* @brief Select the source for DFSDM2 DatIn2
lypinator	0:bb348c97df44	1018	* @rmtoll SYSCFG_MCHDLYCR DFSDM2D2SEL LL_SYSCFG_DFSDM2_SetDataIn2Source
lypinator	0:bb348c97df44	1019	* @param Source This parameter can be one of the following values:
lypinator	0:bb348c97df44	1020	* @arg @ref LL_SYSCFG_DFSDM2_DataIn2_PAD
lypinator	0:bb348c97df44	1021	* @arg @ref LL_SYSCFG_DFSDM2_DataIn2_DM
lypinator	0:bb348c97df44	1022	* @retval None
lypinator	0:bb348c97df44	1023	*/
lypinator	0:bb348c97df44	1024	__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetDataIn2Source(uint32_t Source)
lypinator	0:bb348c97df44	1025	{
lypinator	0:bb348c97df44	1026	MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D2SEL, Source);
lypinator	0:bb348c97df44	1027	}
lypinator	0:bb348c97df44	1028	/**
lypinator	0:bb348c97df44	1029	* @brief Get the source for DFSDM2 DatIn2.
lypinator	0:bb348c97df44	1030	* @rmtoll SYSCFG_MCHDLYCR DFSDM2D2SEL LL_SYSCFG_DFSDM2_GetDataIn2Source
lypinator	0:bb348c97df44	1031	* @retval Returned value can be one of the following values:
lypinator	0:bb348c97df44	1032	* @arg @ref LL_SYSCFG_DFSDM2_DataIn2_PAD
lypinator	0:bb348c97df44	1033	* @arg @ref LL_SYSCFG_DFSDM2_DataIn2_DM
lypinator	0:bb348c97df44	1034	* @retval None
lypinator	0:bb348c97df44	1035	*/
lypinator	0:bb348c97df44	1036	__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetDataIn2Source(void)
lypinator	0:bb348c97df44	1037	{
lypinator	0:bb348c97df44	1038	return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D2SEL));
lypinator	0:bb348c97df44	1039	}
lypinator	0:bb348c97df44	1040
lypinator	0:bb348c97df44	1041	/**
lypinator	0:bb348c97df44	1042	* @brief Select the source for DFSDM2 DatIn4
lypinator	0:bb348c97df44	1043	* @rmtoll SYSCFG_MCHDLYCR DFSDM2D4SEL LL_SYSCFG_DFSDM2_SetDataIn4Source
lypinator	0:bb348c97df44	1044	* @param Source This parameter can be one of the following values:
lypinator	0:bb348c97df44	1045	* @arg @ref LL_SYSCFG_DFSDM2_DataIn4_PAD
lypinator	0:bb348c97df44	1046	* @arg @ref LL_SYSCFG_DFSDM2_DataIn4_DM
lypinator	0:bb348c97df44	1047	* @retval None
lypinator	0:bb348c97df44	1048	*/
lypinator	0:bb348c97df44	1049	__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetDataIn4Source(uint32_t Source)
lypinator	0:bb348c97df44	1050	{
lypinator	0:bb348c97df44	1051	MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D4SEL, Source);
lypinator	0:bb348c97df44	1052	}
lypinator	0:bb348c97df44	1053	/**
lypinator	0:bb348c97df44	1054	* @brief Get the source for DFSDM2 DatIn4.
lypinator	0:bb348c97df44	1055	* @rmtoll SYSCFG_MCHDLYCR DFSDM2D4SEL LL_SYSCFG_DFSDM2_GetDataIn4Source
lypinator	0:bb348c97df44	1056	* @retval Returned value can be one of the following values:
lypinator	0:bb348c97df44	1057	* @arg @ref LL_SYSCFG_DFSDM2_DataIn4_PAD
lypinator	0:bb348c97df44	1058	* @arg @ref LL_SYSCFG_DFSDM2_DataIn4_DM
lypinator	0:bb348c97df44	1059	* @retval None
lypinator	0:bb348c97df44	1060	*/
lypinator	0:bb348c97df44	1061	__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetDataIn4Source(void)
lypinator	0:bb348c97df44	1062	{
lypinator	0:bb348c97df44	1063	return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D4SEL));
lypinator	0:bb348c97df44	1064	}
lypinator	0:bb348c97df44	1065
lypinator	0:bb348c97df44	1066	/**
lypinator	0:bb348c97df44	1067	* @brief Select the source for DFSDM2 DatIn6
lypinator	0:bb348c97df44	1068	* @rmtoll SYSCFG_MCHDLYCR DFSDM2D6SEL LL_SYSCFG_DFSDM2_SetDataIn6Source
lypinator	0:bb348c97df44	1069	* @param Source This parameter can be one of the following values:
lypinator	0:bb348c97df44	1070	* @arg @ref LL_SYSCFG_DFSDM2_DataIn6_PAD
lypinator	0:bb348c97df44	1071	* @arg @ref LL_SYSCFG_DFSDM2_DataIn6_DM
lypinator	0:bb348c97df44	1072	* @retval None
lypinator	0:bb348c97df44	1073	*/
lypinator	0:bb348c97df44	1074	__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetDataIn6Source(uint32_t Source)
lypinator	0:bb348c97df44	1075	{
lypinator	0:bb348c97df44	1076	MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D6SEL, Source);
lypinator	0:bb348c97df44	1077	}
lypinator	0:bb348c97df44	1078	/**
lypinator	0:bb348c97df44	1079	* @brief Get the source for DFSDM2 DatIn6.
lypinator	0:bb348c97df44	1080	* @rmtoll SYSCFG_MCHDLYCR DFSDM2D6SEL LL_SYSCFG_DFSDM2_GetDataIn6Source
lypinator	0:bb348c97df44	1081	* @retval Returned value can be one of the following values:
lypinator	0:bb348c97df44	1082	* @arg @ref LL_SYSCFG_DFSDM2_DataIn6_PAD
lypinator	0:bb348c97df44	1083	* @arg @ref LL_SYSCFG_DFSDM2_DataIn6_DM
lypinator	0:bb348c97df44	1084	* @retval None
lypinator	0:bb348c97df44	1085	*/
lypinator	0:bb348c97df44	1086	__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetDataIn6Source(void)
lypinator	0:bb348c97df44	1087	{
lypinator	0:bb348c97df44	1088	return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D6SEL));
lypinator	0:bb348c97df44	1089	}
lypinator	0:bb348c97df44	1090
lypinator	0:bb348c97df44	1091	/**
lypinator	0:bb348c97df44	1092	* @brief Select the distribution of the bitsream lock gated by TIM3 OC4
lypinator	0:bb348c97df44	1093	* @rmtoll SYSCFG_MCHDLYCR DFSDM2CK04SEL LL_SYSCFG_DFSDM2_SetTIM3OC4BitStreamDistribution
lypinator	0:bb348c97df44	1094	* @param Source This parameter can be one of the following values:
lypinator	0:bb348c97df44	1095	* @arg @ref LL_SYSCFG_DFSDM2_TIM3OC4_CLKIN0
lypinator	0:bb348c97df44	1096	* @arg @ref LL_SYSCFG_DFSDM2_TIM3OC4_CLKIN4
lypinator	0:bb348c97df44	1097	* @retval None
lypinator	0:bb348c97df44	1098	*/
lypinator	0:bb348c97df44	1099	__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetTIM3OC4BitStreamDistribution(uint32_t Source)
lypinator	0:bb348c97df44	1100	{
lypinator	0:bb348c97df44	1101	MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK04SEL, Source);
lypinator	0:bb348c97df44	1102	}
lypinator	0:bb348c97df44	1103	/**
lypinator	0:bb348c97df44	1104	* @brief Get the distribution of the bitsream lock gated by TIM3 OC4
lypinator	0:bb348c97df44	1105	* @rmtoll SYSCFG_MCHDLYCR DFSDM2CK04SEL LL_SYSCFG_DFSDM2_GetTIM3OC4BitStreamDistribution
lypinator	0:bb348c97df44	1106	* @retval Returned value can be one of the following values:
lypinator	0:bb348c97df44	1107	* @arg @ref LL_SYSCFG_DFSDM2_TIM3OC4_CLKIN0
lypinator	0:bb348c97df44	1108	* @arg @ref LL_SYSCFG_DFSDM2_TIM3OC4_CLKIN4
lypinator	0:bb348c97df44	1109	* @retval None
lypinator	0:bb348c97df44	1110	*/
lypinator	0:bb348c97df44	1111	__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetTIM3OC4BitStreamDistribution(void)
lypinator	0:bb348c97df44	1112	{
lypinator	0:bb348c97df44	1113	return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK04SEL));
lypinator	0:bb348c97df44	1114	}
lypinator	0:bb348c97df44	1115
lypinator	0:bb348c97df44	1116	/**
lypinator	0:bb348c97df44	1117	* @brief Select the distribution of the bitsream lock gated by TIM3 OC3
lypinator	0:bb348c97df44	1118	* @rmtoll SYSCFG_MCHDLYCR DFSDM2CK15SEL LL_SYSCFG_DFSDM2_SetTIM3OC3BitStreamDistribution
lypinator	0:bb348c97df44	1119	* @param Source This parameter can be one of the following values:
lypinator	0:bb348c97df44	1120	* @arg @ref LL_SYSCFG_DFSDM2_TIM3OC3_CLKIN1
lypinator	0:bb348c97df44	1121	* @arg @ref LL_SYSCFG_DFSDM2_TIM3OC3_CLKIN5
lypinator	0:bb348c97df44	1122	* @retval None
lypinator	0:bb348c97df44	1123	*/
lypinator	0:bb348c97df44	1124	__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetTIM3OC3BitStreamDistribution(uint32_t Source)
lypinator	0:bb348c97df44	1125	{
lypinator	0:bb348c97df44	1126	MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK15SEL, Source);
lypinator	0:bb348c97df44	1127	}
lypinator	0:bb348c97df44	1128	/**
lypinator	0:bb348c97df44	1129	* @brief Get the distribution of the bitsream lock gated by TIM3 OC4
lypinator	0:bb348c97df44	1130	* @rmtoll SYSCFG_MCHDLYCR DFSDM2CK04SEL LL_SYSCFG_DFSDM2_GetTIM3OC3BitStreamDistribution
lypinator	0:bb348c97df44	1131	* @retval Returned value can be one of the following values:
lypinator	0:bb348c97df44	1132	* @arg @ref LL_SYSCFG_DFSDM2_TIM3OC3_CLKIN1
lypinator	0:bb348c97df44	1133	* @arg @ref LL_SYSCFG_DFSDM2_TIM3OC3_CLKIN5
lypinator	0:bb348c97df44	1134	* @retval None
lypinator	0:bb348c97df44	1135	*/
lypinator	0:bb348c97df44	1136	__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetTIM3OC3BitStreamDistribution(void)
lypinator	0:bb348c97df44	1137	{
lypinator	0:bb348c97df44	1138	return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK15SEL));
lypinator	0:bb348c97df44	1139	}
lypinator	0:bb348c97df44	1140
lypinator	0:bb348c97df44	1141	/**
lypinator	0:bb348c97df44	1142	* @brief Select the distribution of the bitsream lock gated by TIM3 OC2
lypinator	0:bb348c97df44	1143	* @rmtoll SYSCFG_MCHDLYCR DFSDM2CK26SEL LL_SYSCFG_DFSDM2_SetTIM3OC2BitStreamDistribution
lypinator	0:bb348c97df44	1144	* @param Source This parameter can be one of the following values:
lypinator	0:bb348c97df44	1145	* @arg @ref LL_SYSCFG_DFSDM2_TIM3OC2_CLKIN2
lypinator	0:bb348c97df44	1146	* @arg @ref LL_SYSCFG_DFSDM2_TIM3OC2_CLKIN6
lypinator	0:bb348c97df44	1147	* @retval None
lypinator	0:bb348c97df44	1148	*/
lypinator	0:bb348c97df44	1149	__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetTIM3OC2BitStreamDistribution(uint32_t Source)
lypinator	0:bb348c97df44	1150	{
lypinator	0:bb348c97df44	1151	MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK26SEL, Source);
lypinator	0:bb348c97df44	1152	}
lypinator	0:bb348c97df44	1153	/**
lypinator	0:bb348c97df44	1154	* @brief Get the distribution of the bitsream lock gated by TIM3 OC2
lypinator	0:bb348c97df44	1155	* @rmtoll SYSCFG_MCHDLYCR DFSDM2CK04SEL LL_SYSCFG_DFSDM2_GetTIM3OC2BitStreamDistribution
lypinator	0:bb348c97df44	1156	* @retval Returned value can be one of the following values:
lypinator	0:bb348c97df44	1157	* @arg @ref LL_SYSCFG_DFSDM2_TIM3OC2_CLKIN2
lypinator	0:bb348c97df44	1158	* @arg @ref LL_SYSCFG_DFSDM2_TIM3OC2_CLKIN6
lypinator	0:bb348c97df44	1159	* @retval None
lypinator	0:bb348c97df44	1160	*/
lypinator	0:bb348c97df44	1161	__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetTIM3OC2BitStreamDistribution(void)
lypinator	0:bb348c97df44	1162	{
lypinator	0:bb348c97df44	1163	return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK26SEL));
lypinator	0:bb348c97df44	1164	}
lypinator	0:bb348c97df44	1165
lypinator	0:bb348c97df44	1166	/**
lypinator	0:bb348c97df44	1167	* @brief Select the distribution of the bitsream lock gated by TIM3 OC1
lypinator	0:bb348c97df44	1168	* @rmtoll SYSCFG_MCHDLYCR DFSDM2CK37SEL LL_SYSCFG_DFSDM2_SetTIM3OC1BitStreamDistribution
lypinator	0:bb348c97df44	1169	* @param Source This parameter can be one of the following values:
lypinator	0:bb348c97df44	1170	* @arg @ref LL_SYSCFG_DFSDM2_TIM3OC1_CLKIN3
lypinator	0:bb348c97df44	1171	* @arg @ref LL_SYSCFG_DFSDM2_TIM3OC1_CLKIN7
lypinator	0:bb348c97df44	1172	* @retval None
lypinator	0:bb348c97df44	1173	*/
lypinator	0:bb348c97df44	1174	__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetTIM3OC1BitStreamDistribution(uint32_t Source)
lypinator	0:bb348c97df44	1175	{
lypinator	0:bb348c97df44	1176	MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK37SEL, Source);
lypinator	0:bb348c97df44	1177	}
lypinator	0:bb348c97df44	1178	/**
lypinator	0:bb348c97df44	1179	* @brief Get the distribution of the bitsream lock gated by TIM3 OC1
lypinator	0:bb348c97df44	1180	* @rmtoll SYSCFG_MCHDLYCR DFSDM2CK37SEL LL_SYSCFG_DFSDM2_GetTIM3OC1BitStreamDistribution
lypinator	0:bb348c97df44	1181	* @retval Returned value can be one of the following values:
lypinator	0:bb348c97df44	1182	* @arg @ref LL_SYSCFG_DFSDM2_TIM3OC1_CLKIN3
lypinator	0:bb348c97df44	1183	* @arg @ref LL_SYSCFG_DFSDM2_TIM3OC1_CLKIN7
lypinator	0:bb348c97df44	1184	* @retval None
lypinator	0:bb348c97df44	1185	*/
lypinator	0:bb348c97df44	1186	__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetTIM3OC1BitStreamDistribution(void)
lypinator	0:bb348c97df44	1187	{
lypinator	0:bb348c97df44	1188	return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK37SEL));
lypinator	0:bb348c97df44	1189	}
lypinator	0:bb348c97df44	1190
lypinator	0:bb348c97df44	1191	/**
lypinator	0:bb348c97df44	1192	* @brief Select the DFSDM2 Clock In
lypinator	0:bb348c97df44	1193	* @rmtoll SYSCFG_MCHDLYCR DFSDM2CFG LL_SYSCFG_DFSDM2_SetClockInSourceSelection
lypinator	0:bb348c97df44	1194	* @param ClockSource This parameter can be one of the following values:
lypinator	0:bb348c97df44	1195	* @arg @ref LL_SYSCFG_DFSDM2_CKIN_PAD
lypinator	0:bb348c97df44	1196	* @arg @ref LL_SYSCFG_DFSDM2_CKIN_DM
lypinator	0:bb348c97df44	1197	* @retval None
lypinator	0:bb348c97df44	1198	*/
lypinator	0:bb348c97df44	1199	__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetClockInSourceSelection(uint32_t ClockSource)
lypinator	0:bb348c97df44	1200	{
lypinator	0:bb348c97df44	1201	MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CFG, ClockSource);
lypinator	0:bb348c97df44	1202	}
lypinator	0:bb348c97df44	1203	/**
lypinator	0:bb348c97df44	1204	* @brief GET the DFSDM2 Clock In
lypinator	0:bb348c97df44	1205	* @rmtoll SYSCFG_MCHDLYCR DFSDM2CFG LL_SYSCFG_DFSDM2_GetClockInSourceSelection
lypinator	0:bb348c97df44	1206	* @retval Returned value can be one of the following values:
lypinator	0:bb348c97df44	1207	* @arg @ref LL_SYSCFG_DFSDM2_CKIN_PAD
lypinator	0:bb348c97df44	1208	* @arg @ref LL_SYSCFG_DFSDM2_CKIN_DM
lypinator	0:bb348c97df44	1209	* @retval None
lypinator	0:bb348c97df44	1210	*/
lypinator	0:bb348c97df44	1211	__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetClockInSourceSelection(void)
lypinator	0:bb348c97df44	1212	{
lypinator	0:bb348c97df44	1213	return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CFG));
lypinator	0:bb348c97df44	1214	}
lypinator	0:bb348c97df44	1215
lypinator	0:bb348c97df44	1216	/**
lypinator	0:bb348c97df44	1217	* @brief Select the DFSDM2 Clock Out
lypinator	0:bb348c97df44	1218	* @rmtoll SYSCFG_MCHDLYCR DFSDM2CKOSEL LL_SYSCFG_DFSDM2_SetClockOutSourceSelection
lypinator	0:bb348c97df44	1219	* @param ClockSource This parameter can be one of the following values:
lypinator	0:bb348c97df44	1220	* @arg @ref LL_SYSCFG_DFSDM2_CKOUT
lypinator	0:bb348c97df44	1221	* @arg @ref LL_SYSCFG_DFSDM2_CKOUT_M27
lypinator	0:bb348c97df44	1222	* @retval None
lypinator	0:bb348c97df44	1223	*/
lypinator	0:bb348c97df44	1224	__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetClockOutSourceSelection(uint32_t ClockSource)
lypinator	0:bb348c97df44	1225	{
lypinator	0:bb348c97df44	1226	MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CKOSEL, ClockSource);
lypinator	0:bb348c97df44	1227	}
lypinator	0:bb348c97df44	1228	/**
lypinator	0:bb348c97df44	1229	* @brief GET the DFSDM2 Clock Out
lypinator	0:bb348c97df44	1230	* @rmtoll SYSCFG_MCHDLYCR DFSDM2CKOSEL LL_SYSCFG_DFSDM2_GetClockOutSourceSelection
lypinator	0:bb348c97df44	1231	* @retval Returned value can be one of the following values:
lypinator	0:bb348c97df44	1232	* @arg @ref LL_SYSCFG_DFSDM2_CKOUT
lypinator	0:bb348c97df44	1233	* @arg @ref LL_SYSCFG_DFSDM2_CKOUT_M27
lypinator	0:bb348c97df44	1234	* @retval None
lypinator	0:bb348c97df44	1235	*/
lypinator	0:bb348c97df44	1236	__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetClockOutSourceSelection(void)
lypinator	0:bb348c97df44	1237	{
lypinator	0:bb348c97df44	1238	return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CKOSEL));
lypinator	0:bb348c97df44	1239	}
lypinator	0:bb348c97df44	1240
lypinator	0:bb348c97df44	1241	#endif /* SYSCFG_MCHDLYCR_BSCKSEL */
lypinator	0:bb348c97df44	1242	/**
lypinator	0:bb348c97df44	1243	* @}
lypinator	0:bb348c97df44	1244	*/
lypinator	0:bb348c97df44	1245
lypinator	0:bb348c97df44	1246
lypinator	0:bb348c97df44	1247	/** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU
lypinator	0:bb348c97df44	1248	* @{
lypinator	0:bb348c97df44	1249	*/
lypinator	0:bb348c97df44	1250
lypinator	0:bb348c97df44	1251	/**
lypinator	0:bb348c97df44	1252	* @brief Return the device identifier
lypinator	0:bb348c97df44	1253	* @note For STM32F405/407xx and STM32F415/417xx devices, the device ID is 0x413
lypinator	0:bb348c97df44	1254	* @note For STM32F42xxx and STM32F43xxx devices, the device ID is 0x419
lypinator	0:bb348c97df44	1255	* @note For STM32F401xx devices, the device ID is 0x423
lypinator	0:bb348c97df44	1256	* @note For STM32F401xx devices, the device ID is 0x433
lypinator	0:bb348c97df44	1257	* @note For STM32F411xx devices, the device ID is 0x431
lypinator	0:bb348c97df44	1258	* @note For STM32F410xx devices, the device ID is 0x458
lypinator	0:bb348c97df44	1259	* @note For STM32F412xx devices, the device ID is 0x441
lypinator	0:bb348c97df44	1260	* @note For STM32F413xx and STM32423xx devices, the device ID is 0x463
lypinator	0:bb348c97df44	1261	* @note For STM32F446xx devices, the device ID is 0x421
lypinator	0:bb348c97df44	1262	* @note For STM32F469xx and STM32F479xx devices, the device ID is 0x434
lypinator	0:bb348c97df44	1263	* @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID
lypinator	0:bb348c97df44	1264	* @retval Values between Min_Data=0x00 and Max_Data=0xFFF
lypinator	0:bb348c97df44	1265	*/
lypinator	0:bb348c97df44	1266	__STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)
lypinator	0:bb348c97df44	1267	{
lypinator	0:bb348c97df44	1268	return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID));
lypinator	0:bb348c97df44	1269	}
lypinator	0:bb348c97df44	1270
lypinator	0:bb348c97df44	1271	/**
lypinator	0:bb348c97df44	1272	* @brief Return the device revision identifier
lypinator	0:bb348c97df44	1273	* @note This field indicates the revision of the device.
lypinator	0:bb348c97df44	1274	For example, it is read as RevA -> 0x1000, Cat 2 revZ -> 0x1001, rev1 -> 0x1003, rev2 ->0x1007, revY -> 0x100F for STM32F405/407xx and STM32F415/417xx devices
lypinator	0:bb348c97df44	1275	For example, it is read as RevA -> 0x1000, Cat 2 revY -> 0x1003, rev1 -> 0x1007, rev3 ->0x2001 for STM32F42xxx and STM32F43xxx devices
lypinator	0:bb348c97df44	1276	For example, it is read as RevZ -> 0x1000, Cat 2 revA -> 0x1001 for STM32F401xB/C devices
lypinator	0:bb348c97df44	1277	For example, it is read as RevA -> 0x1000, Cat 2 revZ -> 0x1001 for STM32F401xD/E devices
lypinator	0:bb348c97df44	1278	For example, it is read as RevA -> 0x1000 for STM32F411xx,STM32F413/423xx,STM32F469/423xx, STM32F446xx and STM32F410xx devices
lypinator	0:bb348c97df44	1279	For example, it is read as RevZ -> 0x1001, Cat 2 revB -> 0x2000, revC -> 0x3000 for STM32F412xx devices
lypinator	0:bb348c97df44	1280	* @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID
lypinator	0:bb348c97df44	1281	* @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
lypinator	0:bb348c97df44	1282	*/
lypinator	0:bb348c97df44	1283	__STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)
lypinator	0:bb348c97df44	1284	{
lypinator	0:bb348c97df44	1285	return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos);
lypinator	0:bb348c97df44	1286	}
lypinator	0:bb348c97df44	1287
lypinator	0:bb348c97df44	1288	/**
lypinator	0:bb348c97df44	1289	* @brief Enable the Debug Module during SLEEP mode
lypinator	0:bb348c97df44	1290	* @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_EnableDBGSleepMode
lypinator	0:bb348c97df44	1291	* @retval None
lypinator	0:bb348c97df44	1292	*/
lypinator	0:bb348c97df44	1293	__STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void)
lypinator	0:bb348c97df44	1294	{
lypinator	0:bb348c97df44	1295	SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
lypinator	0:bb348c97df44	1296	}
lypinator	0:bb348c97df44	1297
lypinator	0:bb348c97df44	1298	/**
lypinator	0:bb348c97df44	1299	* @brief Disable the Debug Module during SLEEP mode
lypinator	0:bb348c97df44	1300	* @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_DisableDBGSleepMode
lypinator	0:bb348c97df44	1301	* @retval None
lypinator	0:bb348c97df44	1302	*/
lypinator	0:bb348c97df44	1303	__STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void)
lypinator	0:bb348c97df44	1304	{
lypinator	0:bb348c97df44	1305	CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
lypinator	0:bb348c97df44	1306	}
lypinator	0:bb348c97df44	1307
lypinator	0:bb348c97df44	1308	/**
lypinator	0:bb348c97df44	1309	* @brief Enable the Debug Module during STOP mode
lypinator	0:bb348c97df44	1310	* @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode
lypinator	0:bb348c97df44	1311	* @retval None
lypinator	0:bb348c97df44	1312	*/
lypinator	0:bb348c97df44	1313	__STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void)
lypinator	0:bb348c97df44	1314	{
lypinator	0:bb348c97df44	1315	SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
lypinator	0:bb348c97df44	1316	}
lypinator	0:bb348c97df44	1317
lypinator	0:bb348c97df44	1318	/**
lypinator	0:bb348c97df44	1319	* @brief Disable the Debug Module during STOP mode
lypinator	0:bb348c97df44	1320	* @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode
lypinator	0:bb348c97df44	1321	* @retval None
lypinator	0:bb348c97df44	1322	*/
lypinator	0:bb348c97df44	1323	__STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void)
lypinator	0:bb348c97df44	1324	{
lypinator	0:bb348c97df44	1325	CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
lypinator	0:bb348c97df44	1326	}
lypinator	0:bb348c97df44	1327
lypinator	0:bb348c97df44	1328	/**
lypinator	0:bb348c97df44	1329	* @brief Enable the Debug Module during STANDBY mode
lypinator	0:bb348c97df44	1330	* @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode
lypinator	0:bb348c97df44	1331	* @retval None
lypinator	0:bb348c97df44	1332	*/
lypinator	0:bb348c97df44	1333	__STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void)
lypinator	0:bb348c97df44	1334	{
lypinator	0:bb348c97df44	1335	SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
lypinator	0:bb348c97df44	1336	}
lypinator	0:bb348c97df44	1337
lypinator	0:bb348c97df44	1338	/**
lypinator	0:bb348c97df44	1339	* @brief Disable the Debug Module during STANDBY mode
lypinator	0:bb348c97df44	1340	* @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode
lypinator	0:bb348c97df44	1341	* @retval None
lypinator	0:bb348c97df44	1342	*/
lypinator	0:bb348c97df44	1343	__STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void)
lypinator	0:bb348c97df44	1344	{
lypinator	0:bb348c97df44	1345	CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
lypinator	0:bb348c97df44	1346	}
lypinator	0:bb348c97df44	1347
lypinator	0:bb348c97df44	1348	/**
lypinator	0:bb348c97df44	1349	* @brief Set Trace pin assignment control
lypinator	0:bb348c97df44	1350	* @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_SetTracePinAssignment\n
lypinator	0:bb348c97df44	1351	* DBGMCU_CR TRACE_MODE LL_DBGMCU_SetTracePinAssignment
lypinator	0:bb348c97df44	1352	* @param PinAssignment This parameter can be one of the following values:
lypinator	0:bb348c97df44	1353	* @arg @ref LL_DBGMCU_TRACE_NONE
lypinator	0:bb348c97df44	1354	* @arg @ref LL_DBGMCU_TRACE_ASYNCH
lypinator	0:bb348c97df44	1355	* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
lypinator	0:bb348c97df44	1356	* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
lypinator	0:bb348c97df44	1357	* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
lypinator	0:bb348c97df44	1358	* @retval None
lypinator	0:bb348c97df44	1359	*/
lypinator	0:bb348c97df44	1360	__STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment)
lypinator	0:bb348c97df44	1361	{
lypinator	0:bb348c97df44	1362	MODIFY_REG(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN \| DBGMCU_CR_TRACE_MODE, PinAssignment);
lypinator	0:bb348c97df44	1363	}
lypinator	0:bb348c97df44	1364
lypinator	0:bb348c97df44	1365	/**
lypinator	0:bb348c97df44	1366	* @brief Get Trace pin assignment control
lypinator	0:bb348c97df44	1367	* @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_GetTracePinAssignment\n
lypinator	0:bb348c97df44	1368	* DBGMCU_CR TRACE_MODE LL_DBGMCU_GetTracePinAssignment
lypinator	0:bb348c97df44	1369	* @retval Returned value can be one of the following values:
lypinator	0:bb348c97df44	1370	* @arg @ref LL_DBGMCU_TRACE_NONE
lypinator	0:bb348c97df44	1371	* @arg @ref LL_DBGMCU_TRACE_ASYNCH
lypinator	0:bb348c97df44	1372	* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
lypinator	0:bb348c97df44	1373	* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
lypinator	0:bb348c97df44	1374	* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
lypinator	0:bb348c97df44	1375	*/
lypinator	0:bb348c97df44	1376	__STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void)
lypinator	0:bb348c97df44	1377	{
lypinator	0:bb348c97df44	1378	return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN \| DBGMCU_CR_TRACE_MODE));
lypinator	0:bb348c97df44	1379	}
lypinator	0:bb348c97df44	1380
lypinator	0:bb348c97df44	1381	/**
lypinator	0:bb348c97df44	1382	* @brief Freeze APB1 peripherals (group1 peripherals)
lypinator	0:bb348c97df44	1383	* @rmtoll DBGMCU_APB1_FZ DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
lypinator	0:bb348c97df44	1384	* DBGMCU_APB1_FZ DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
lypinator	0:bb348c97df44	1385	* DBGMCU_APB1_FZ DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
lypinator	0:bb348c97df44	1386	* DBGMCU_APB1_FZ DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
lypinator	0:bb348c97df44	1387	* DBGMCU_APB1_FZ DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
lypinator	0:bb348c97df44	1388	* DBGMCU_APB1_FZ DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
lypinator	0:bb348c97df44	1389	* DBGMCU_APB1_FZ DBG_TIM12_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
lypinator	0:bb348c97df44	1390	* DBGMCU_APB1_FZ DBG_TIM13_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
lypinator	0:bb348c97df44	1391	* DBGMCU_APB1_FZ DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
lypinator	0:bb348c97df44	1392	* DBGMCU_APB1_FZ DBG_LPTIM_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
lypinator	0:bb348c97df44	1393	* DBGMCU_APB1_FZ DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
lypinator	0:bb348c97df44	1394	* DBGMCU_APB1_FZ DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
lypinator	0:bb348c97df44	1395	* DBGMCU_APB1_FZ DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
lypinator	0:bb348c97df44	1396	* DBGMCU_APB1_FZ DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n
lypinator	0:bb348c97df44	1397	* DBGMCU_APB1_FZ DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n
lypinator	0:bb348c97df44	1398	* DBGMCU_APB1_FZ DBG_I2C3_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n
lypinator	0:bb348c97df44	1399	* DBGMCU_APB1_FZ DBG_I2C4_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n
lypinator	0:bb348c97df44	1400	* DBGMCU_APB1_FZ DBG_CAN1_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
lypinator	0:bb348c97df44	1401	* DBGMCU_APB1_FZ DBG_CAN2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
lypinator	0:bb348c97df44	1402	* DBGMCU_APB1_FZ DBG_CAN3_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph
lypinator	0:bb348c97df44	1403	* @param Periphs This parameter can be a combination of the following values:
lypinator	0:bb348c97df44	1404	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP (*)
lypinator	0:bb348c97df44	1405	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP (*)
lypinator	0:bb348c97df44	1406	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP (*)
lypinator	0:bb348c97df44	1407	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP
lypinator	0:bb348c97df44	1408	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP (*)
lypinator	0:bb348c97df44	1409	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*)
lypinator	0:bb348c97df44	1410	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP (*)
lypinator	0:bb348c97df44	1411	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP (*)
lypinator	0:bb348c97df44	1412	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP (*)
lypinator	0:bb348c97df44	1413	* @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM_STOP (*)
lypinator	0:bb348c97df44	1414	* @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
lypinator	0:bb348c97df44	1415	* @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
lypinator	0:bb348c97df44	1416	* @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
lypinator	0:bb348c97df44	1417	* @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
lypinator	0:bb348c97df44	1418	* @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP
lypinator	0:bb348c97df44	1419	* @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP (*)
lypinator	0:bb348c97df44	1420	* @arg @ref LL_DBGMCU_APB1_GRP1_I2C4_STOP (*)
lypinator	0:bb348c97df44	1421	* @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP (*)
lypinator	0:bb348c97df44	1422	* @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*)
lypinator	0:bb348c97df44	1423	* @arg @ref LL_DBGMCU_APB1_GRP1_CAN3_STOP (*)
lypinator	0:bb348c97df44	1424	*
lypinator	0:bb348c97df44	1425	* (*) value not defined in all devices.
lypinator	0:bb348c97df44	1426	* @retval None
lypinator	0:bb348c97df44	1427	*/
lypinator	0:bb348c97df44	1428	__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
lypinator	0:bb348c97df44	1429	{
lypinator	0:bb348c97df44	1430	SET_BIT(DBGMCU->APB1FZ, Periphs);
lypinator	0:bb348c97df44	1431	}
lypinator	0:bb348c97df44	1432
lypinator	0:bb348c97df44	1433	/**
lypinator	0:bb348c97df44	1434	* @brief Unfreeze APB1 peripherals (group1 peripherals)
lypinator	0:bb348c97df44	1435	* @rmtoll DBGMCU_APB1_FZ DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
lypinator	0:bb348c97df44	1436	* DBGMCU_APB1_FZ DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
lypinator	0:bb348c97df44	1437	* DBGMCU_APB1_FZ DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
lypinator	0:bb348c97df44	1438	* DBGMCU_APB1_FZ DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
lypinator	0:bb348c97df44	1439	* DBGMCU_APB1_FZ DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
lypinator	0:bb348c97df44	1440	* DBGMCU_APB1_FZ DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
lypinator	0:bb348c97df44	1441	* DBGMCU_APB1_FZ DBG_TIM12_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
lypinator	0:bb348c97df44	1442	* DBGMCU_APB1_FZ DBG_TIM13_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
lypinator	0:bb348c97df44	1443	* DBGMCU_APB1_FZ DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
lypinator	0:bb348c97df44	1444	* DBGMCU_APB1_FZ DBG_LPTIM_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
lypinator	0:bb348c97df44	1445	* DBGMCU_APB1_FZ DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
lypinator	0:bb348c97df44	1446	* DBGMCU_APB1_FZ DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
lypinator	0:bb348c97df44	1447	* DBGMCU_APB1_FZ DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
lypinator	0:bb348c97df44	1448	* DBGMCU_APB1_FZ DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
lypinator	0:bb348c97df44	1449	* DBGMCU_APB1_FZ DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
lypinator	0:bb348c97df44	1450	* DBGMCU_APB1_FZ DBG_I2C3_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
lypinator	0:bb348c97df44	1451	* DBGMCU_APB1_FZ DBG_I2C4_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
lypinator	0:bb348c97df44	1452	* DBGMCU_APB1_FZ DBG_CAN1_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
lypinator	0:bb348c97df44	1453	* DBGMCU_APB1_FZ DBG_CAN2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
lypinator	0:bb348c97df44	1454	* DBGMCU_APB1_FZ DBG_CAN3_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph
lypinator	0:bb348c97df44	1455	* @param Periphs This parameter can be a combination of the following values:
lypinator	0:bb348c97df44	1456	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP (*)
lypinator	0:bb348c97df44	1457	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP (*)
lypinator	0:bb348c97df44	1458	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP (*)
lypinator	0:bb348c97df44	1459	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP
lypinator	0:bb348c97df44	1460	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP (*)
lypinator	0:bb348c97df44	1461	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*)
lypinator	0:bb348c97df44	1462	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP (*)
lypinator	0:bb348c97df44	1463	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP (*)
lypinator	0:bb348c97df44	1464	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP (*)
lypinator	0:bb348c97df44	1465	* @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM_STOP (*)
lypinator	0:bb348c97df44	1466	* @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
lypinator	0:bb348c97df44	1467	* @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
lypinator	0:bb348c97df44	1468	* @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
lypinator	0:bb348c97df44	1469	* @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
lypinator	0:bb348c97df44	1470	* @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP
lypinator	0:bb348c97df44	1471	* @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP (*)
lypinator	0:bb348c97df44	1472	* @arg @ref LL_DBGMCU_APB1_GRP1_I2C4_STOP (*)
lypinator	0:bb348c97df44	1473	* @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP (*)
lypinator	0:bb348c97df44	1474	* @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*)
lypinator	0:bb348c97df44	1475	* @arg @ref LL_DBGMCU_APB1_GRP1_CAN3_STOP (*)
lypinator	0:bb348c97df44	1476	*
lypinator	0:bb348c97df44	1477	* (*) value not defined in all devices.
lypinator	0:bb348c97df44	1478	* @retval None
lypinator	0:bb348c97df44	1479	*/
lypinator	0:bb348c97df44	1480	__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
lypinator	0:bb348c97df44	1481	{
lypinator	0:bb348c97df44	1482	CLEAR_BIT(DBGMCU->APB1FZ, Periphs);
lypinator	0:bb348c97df44	1483	}
lypinator	0:bb348c97df44	1484
lypinator	0:bb348c97df44	1485	/**
lypinator	0:bb348c97df44	1486	* @brief Freeze APB2 peripherals
lypinator	0:bb348c97df44	1487	* @rmtoll DBGMCU_APB2_FZ DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
lypinator	0:bb348c97df44	1488	* DBGMCU_APB2_FZ DBG_TIM8_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
lypinator	0:bb348c97df44	1489	* DBGMCU_APB2_FZ DBG_TIM9_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
lypinator	0:bb348c97df44	1490	* DBGMCU_APB2_FZ DBG_TIM10_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
lypinator	0:bb348c97df44	1491	* DBGMCU_APB2_FZ DBG_TIM11_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph
lypinator	0:bb348c97df44	1492	* @param Periphs This parameter can be a combination of the following values:
lypinator	0:bb348c97df44	1493	* @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
lypinator	0:bb348c97df44	1494	* @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*)
lypinator	0:bb348c97df44	1495	* @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP (*)
lypinator	0:bb348c97df44	1496	* @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP (*)
lypinator	0:bb348c97df44	1497	* @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP (*)
lypinator	0:bb348c97df44	1498	*
lypinator	0:bb348c97df44	1499	* (*) value not defined in all devices.
lypinator	0:bb348c97df44	1500	* @retval None
lypinator	0:bb348c97df44	1501	*/
lypinator	0:bb348c97df44	1502	__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)
lypinator	0:bb348c97df44	1503	{
lypinator	0:bb348c97df44	1504	SET_BIT(DBGMCU->APB2FZ, Periphs);
lypinator	0:bb348c97df44	1505	}
lypinator	0:bb348c97df44	1506
lypinator	0:bb348c97df44	1507	/**
lypinator	0:bb348c97df44	1508	* @brief Unfreeze APB2 peripherals
lypinator	0:bb348c97df44	1509	* @rmtoll DBGMCU_APB2_FZ DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
lypinator	0:bb348c97df44	1510	* DBGMCU_APB2_FZ DBG_TIM8_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
lypinator	0:bb348c97df44	1511	* DBGMCU_APB2_FZ DBG_TIM9_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
lypinator	0:bb348c97df44	1512	* DBGMCU_APB2_FZ DBG_TIM10_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
lypinator	0:bb348c97df44	1513	* DBGMCU_APB2_FZ DBG_TIM11_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph
lypinator	0:bb348c97df44	1514	* @param Periphs This parameter can be a combination of the following values:
lypinator	0:bb348c97df44	1515	* @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
lypinator	0:bb348c97df44	1516	* @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*)
lypinator	0:bb348c97df44	1517	* @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP (*)
lypinator	0:bb348c97df44	1518	* @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP (*)
lypinator	0:bb348c97df44	1519	* @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP (*)
lypinator	0:bb348c97df44	1520	*
lypinator	0:bb348c97df44	1521	* (*) value not defined in all devices.
lypinator	0:bb348c97df44	1522	* @retval None
lypinator	0:bb348c97df44	1523	*/
lypinator	0:bb348c97df44	1524	__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)
lypinator	0:bb348c97df44	1525	{
lypinator	0:bb348c97df44	1526	CLEAR_BIT(DBGMCU->APB2FZ, Periphs);
lypinator	0:bb348c97df44	1527	}
lypinator	0:bb348c97df44	1528	/**
lypinator	0:bb348c97df44	1529	* @}
lypinator	0:bb348c97df44	1530	*/
lypinator	0:bb348c97df44	1531
lypinator	0:bb348c97df44	1532	/** @defgroup SYSTEM_LL_EF_FLASH FLASH
lypinator	0:bb348c97df44	1533	* @{
lypinator	0:bb348c97df44	1534	*/
lypinator	0:bb348c97df44	1535
lypinator	0:bb348c97df44	1536	/**
lypinator	0:bb348c97df44	1537	* @brief Set FLASH Latency
lypinator	0:bb348c97df44	1538	* @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency
lypinator	0:bb348c97df44	1539	* @param Latency This parameter can be one of the following values:
lypinator	0:bb348c97df44	1540	* @arg @ref LL_FLASH_LATENCY_0
lypinator	0:bb348c97df44	1541	* @arg @ref LL_FLASH_LATENCY_1
lypinator	0:bb348c97df44	1542	* @arg @ref LL_FLASH_LATENCY_2
lypinator	0:bb348c97df44	1543	* @arg @ref LL_FLASH_LATENCY_3
lypinator	0:bb348c97df44	1544	* @arg @ref LL_FLASH_LATENCY_4
lypinator	0:bb348c97df44	1545	* @arg @ref LL_FLASH_LATENCY_5
lypinator	0:bb348c97df44	1546	* @arg @ref LL_FLASH_LATENCY_6
lypinator	0:bb348c97df44	1547	* @arg @ref LL_FLASH_LATENCY_7
lypinator	0:bb348c97df44	1548	* @arg @ref LL_FLASH_LATENCY_8
lypinator	0:bb348c97df44	1549	* @arg @ref LL_FLASH_LATENCY_9
lypinator	0:bb348c97df44	1550	* @arg @ref LL_FLASH_LATENCY_10
lypinator	0:bb348c97df44	1551	* @arg @ref LL_FLASH_LATENCY_11
lypinator	0:bb348c97df44	1552	* @arg @ref LL_FLASH_LATENCY_12
lypinator	0:bb348c97df44	1553	* @arg @ref LL_FLASH_LATENCY_13
lypinator	0:bb348c97df44	1554	* @arg @ref LL_FLASH_LATENCY_14
lypinator	0:bb348c97df44	1555	* @arg @ref LL_FLASH_LATENCY_15
lypinator	0:bb348c97df44	1556	* @retval None
lypinator	0:bb348c97df44	1557	*/
lypinator	0:bb348c97df44	1558	__STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
lypinator	0:bb348c97df44	1559	{
lypinator	0:bb348c97df44	1560	MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
lypinator	0:bb348c97df44	1561	}
lypinator	0:bb348c97df44	1562
lypinator	0:bb348c97df44	1563	/**
lypinator	0:bb348c97df44	1564	* @brief Get FLASH Latency
lypinator	0:bb348c97df44	1565	* @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency
lypinator	0:bb348c97df44	1566	* @retval Returned value can be one of the following values:
lypinator	0:bb348c97df44	1567	* @arg @ref LL_FLASH_LATENCY_0
lypinator	0:bb348c97df44	1568	* @arg @ref LL_FLASH_LATENCY_1
lypinator	0:bb348c97df44	1569	* @arg @ref LL_FLASH_LATENCY_2
lypinator	0:bb348c97df44	1570	* @arg @ref LL_FLASH_LATENCY_3
lypinator	0:bb348c97df44	1571	* @arg @ref LL_FLASH_LATENCY_4
lypinator	0:bb348c97df44	1572	* @arg @ref LL_FLASH_LATENCY_5
lypinator	0:bb348c97df44	1573	* @arg @ref LL_FLASH_LATENCY_6
lypinator	0:bb348c97df44	1574	* @arg @ref LL_FLASH_LATENCY_7
lypinator	0:bb348c97df44	1575	* @arg @ref LL_FLASH_LATENCY_8
lypinator	0:bb348c97df44	1576	* @arg @ref LL_FLASH_LATENCY_9
lypinator	0:bb348c97df44	1577	* @arg @ref LL_FLASH_LATENCY_10
lypinator	0:bb348c97df44	1578	* @arg @ref LL_FLASH_LATENCY_11
lypinator	0:bb348c97df44	1579	* @arg @ref LL_FLASH_LATENCY_12
lypinator	0:bb348c97df44	1580	* @arg @ref LL_FLASH_LATENCY_13
lypinator	0:bb348c97df44	1581	* @arg @ref LL_FLASH_LATENCY_14
lypinator	0:bb348c97df44	1582	* @arg @ref LL_FLASH_LATENCY_15
lypinator	0:bb348c97df44	1583	*/
lypinator	0:bb348c97df44	1584	__STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
lypinator	0:bb348c97df44	1585	{
lypinator	0:bb348c97df44	1586	return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
lypinator	0:bb348c97df44	1587	}
lypinator	0:bb348c97df44	1588
lypinator	0:bb348c97df44	1589	/**
lypinator	0:bb348c97df44	1590	* @brief Enable Prefetch
lypinator	0:bb348c97df44	1591	* @rmtoll FLASH_ACR PRFTEN LL_FLASH_EnablePrefetch
lypinator	0:bb348c97df44	1592	* @retval None
lypinator	0:bb348c97df44	1593	*/
lypinator	0:bb348c97df44	1594	__STATIC_INLINE void LL_FLASH_EnablePrefetch(void)
lypinator	0:bb348c97df44	1595	{
lypinator	0:bb348c97df44	1596	SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);
lypinator	0:bb348c97df44	1597	}
lypinator	0:bb348c97df44	1598
lypinator	0:bb348c97df44	1599	/**
lypinator	0:bb348c97df44	1600	* @brief Disable Prefetch
lypinator	0:bb348c97df44	1601	* @rmtoll FLASH_ACR PRFTEN LL_FLASH_DisablePrefetch
lypinator	0:bb348c97df44	1602	* @retval None
lypinator	0:bb348c97df44	1603	*/
lypinator	0:bb348c97df44	1604	__STATIC_INLINE void LL_FLASH_DisablePrefetch(void)
lypinator	0:bb348c97df44	1605	{
lypinator	0:bb348c97df44	1606	CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);
lypinator	0:bb348c97df44	1607	}
lypinator	0:bb348c97df44	1608
lypinator	0:bb348c97df44	1609	/**
lypinator	0:bb348c97df44	1610	* @brief Check if Prefetch buffer is enabled
lypinator	0:bb348c97df44	1611	* @rmtoll FLASH_ACR PRFTEN LL_FLASH_IsPrefetchEnabled
lypinator	0:bb348c97df44	1612	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	1613	*/
lypinator	0:bb348c97df44	1614	__STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void)
lypinator	0:bb348c97df44	1615	{
lypinator	0:bb348c97df44	1616	return (READ_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) == (FLASH_ACR_PRFTEN));
lypinator	0:bb348c97df44	1617	}
lypinator	0:bb348c97df44	1618
lypinator	0:bb348c97df44	1619	/**
lypinator	0:bb348c97df44	1620	* @brief Enable Instruction cache
lypinator	0:bb348c97df44	1621	* @rmtoll FLASH_ACR ICEN LL_FLASH_EnableInstCache
lypinator	0:bb348c97df44	1622	* @retval None
lypinator	0:bb348c97df44	1623	*/
lypinator	0:bb348c97df44	1624	__STATIC_INLINE void LL_FLASH_EnableInstCache(void)
lypinator	0:bb348c97df44	1625	{
lypinator	0:bb348c97df44	1626	SET_BIT(FLASH->ACR, FLASH_ACR_ICEN);
lypinator	0:bb348c97df44	1627	}
lypinator	0:bb348c97df44	1628
lypinator	0:bb348c97df44	1629	/**
lypinator	0:bb348c97df44	1630	* @brief Disable Instruction cache
lypinator	0:bb348c97df44	1631	* @rmtoll FLASH_ACR ICEN LL_FLASH_DisableInstCache
lypinator	0:bb348c97df44	1632	* @retval None
lypinator	0:bb348c97df44	1633	*/
lypinator	0:bb348c97df44	1634	__STATIC_INLINE void LL_FLASH_DisableInstCache(void)
lypinator	0:bb348c97df44	1635	{
lypinator	0:bb348c97df44	1636	CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN);
lypinator	0:bb348c97df44	1637	}
lypinator	0:bb348c97df44	1638
lypinator	0:bb348c97df44	1639	/**
lypinator	0:bb348c97df44	1640	* @brief Enable Data cache
lypinator	0:bb348c97df44	1641	* @rmtoll FLASH_ACR DCEN LL_FLASH_EnableDataCache
lypinator	0:bb348c97df44	1642	* @retval None
lypinator	0:bb348c97df44	1643	*/
lypinator	0:bb348c97df44	1644	__STATIC_INLINE void LL_FLASH_EnableDataCache(void)
lypinator	0:bb348c97df44	1645	{
lypinator	0:bb348c97df44	1646	SET_BIT(FLASH->ACR, FLASH_ACR_DCEN);
lypinator	0:bb348c97df44	1647	}
lypinator	0:bb348c97df44	1648
lypinator	0:bb348c97df44	1649	/**
lypinator	0:bb348c97df44	1650	* @brief Disable Data cache
lypinator	0:bb348c97df44	1651	* @rmtoll FLASH_ACR DCEN LL_FLASH_DisableDataCache
lypinator	0:bb348c97df44	1652	* @retval None
lypinator	0:bb348c97df44	1653	*/
lypinator	0:bb348c97df44	1654	__STATIC_INLINE void LL_FLASH_DisableDataCache(void)
lypinator	0:bb348c97df44	1655	{
lypinator	0:bb348c97df44	1656	CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCEN);
lypinator	0:bb348c97df44	1657	}
lypinator	0:bb348c97df44	1658
lypinator	0:bb348c97df44	1659	/**
lypinator	0:bb348c97df44	1660	* @brief Enable Instruction cache reset
lypinator	0:bb348c97df44	1661	* @note bit can be written only when the instruction cache is disabled
lypinator	0:bb348c97df44	1662	* @rmtoll FLASH_ACR ICRST LL_FLASH_EnableInstCacheReset
lypinator	0:bb348c97df44	1663	* @retval None
lypinator	0:bb348c97df44	1664	*/
lypinator	0:bb348c97df44	1665	__STATIC_INLINE void LL_FLASH_EnableInstCacheReset(void)
lypinator	0:bb348c97df44	1666	{
lypinator	0:bb348c97df44	1667	SET_BIT(FLASH->ACR, FLASH_ACR_ICRST);
lypinator	0:bb348c97df44	1668	}
lypinator	0:bb348c97df44	1669
lypinator	0:bb348c97df44	1670	/**
lypinator	0:bb348c97df44	1671	* @brief Disable Instruction cache reset
lypinator	0:bb348c97df44	1672	* @rmtoll FLASH_ACR ICRST LL_FLASH_DisableInstCacheReset
lypinator	0:bb348c97df44	1673	* @retval None
lypinator	0:bb348c97df44	1674	*/
lypinator	0:bb348c97df44	1675	__STATIC_INLINE void LL_FLASH_DisableInstCacheReset(void)
lypinator	0:bb348c97df44	1676	{
lypinator	0:bb348c97df44	1677	CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICRST);
lypinator	0:bb348c97df44	1678	}
lypinator	0:bb348c97df44	1679
lypinator	0:bb348c97df44	1680	/**
lypinator	0:bb348c97df44	1681	* @brief Enable Data cache reset
lypinator	0:bb348c97df44	1682	* @note bit can be written only when the data cache is disabled
lypinator	0:bb348c97df44	1683	* @rmtoll FLASH_ACR DCRST LL_FLASH_EnableDataCacheReset
lypinator	0:bb348c97df44	1684	* @retval None
lypinator	0:bb348c97df44	1685	*/
lypinator	0:bb348c97df44	1686	__STATIC_INLINE void LL_FLASH_EnableDataCacheReset(void)
lypinator	0:bb348c97df44	1687	{
lypinator	0:bb348c97df44	1688	SET_BIT(FLASH->ACR, FLASH_ACR_DCRST);
lypinator	0:bb348c97df44	1689	}
lypinator	0:bb348c97df44	1690
lypinator	0:bb348c97df44	1691	/**
lypinator	0:bb348c97df44	1692	* @brief Disable Data cache reset
lypinator	0:bb348c97df44	1693	* @rmtoll FLASH_ACR DCRST LL_FLASH_DisableDataCacheReset
lypinator	0:bb348c97df44	1694	* @retval None
lypinator	0:bb348c97df44	1695	*/
lypinator	0:bb348c97df44	1696	__STATIC_INLINE void LL_FLASH_DisableDataCacheReset(void)
lypinator	0:bb348c97df44	1697	{
lypinator	0:bb348c97df44	1698	CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCRST);
lypinator	0:bb348c97df44	1699	}
lypinator	0:bb348c97df44	1700
lypinator	0:bb348c97df44	1701
lypinator	0:bb348c97df44	1702	/**
lypinator	0:bb348c97df44	1703	* @}
lypinator	0:bb348c97df44	1704	*/
lypinator	0:bb348c97df44	1705
lypinator	0:bb348c97df44	1706	/**
lypinator	0:bb348c97df44	1707	* @}
lypinator	0:bb348c97df44	1708	*/
lypinator	0:bb348c97df44	1709
lypinator	0:bb348c97df44	1710	/**
lypinator	0:bb348c97df44	1711	* @}
lypinator	0:bb348c97df44	1712	*/
lypinator	0:bb348c97df44	1713
lypinator	0:bb348c97df44	1714	#endif /* defined (FLASH) \|\| defined (SYSCFG) \|\| defined (DBGMCU) */
lypinator	0:bb348c97df44	1715
lypinator	0:bb348c97df44	1716	/**
lypinator	0:bb348c97df44	1717	* @}
lypinator	0:bb348c97df44	1718	*/
lypinator	0:bb348c97df44	1719
lypinator	0:bb348c97df44	1720	#ifdef __cplusplus
lypinator	0:bb348c97df44	1721	}
lypinator	0:bb348c97df44	1722	#endif
lypinator	0:bb348c97df44	1723
lypinator	0:bb348c97df44	1724	#endif /* __STM32F4xx_LL_SYSTEM_H */
lypinator	0:bb348c97df44	1725
lypinator	0:bb348c97df44	1726	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Program
Created:	16 Sep 2020
Imports:	1
Forks:	0
Commits:	1
Dependents:	0
Dependencies:	1
Followers:	1

mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_system.h@0:bb348c97df44, 2020-09-16 (annotated)

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