DevLibMemoryController - Initial commit

Users » lypinator » Code » DevLibMemoryController

Initial commit

mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_spi.h@0:bb348c97df44, 2020-09-16 (annotated)

Committer:: lypinator
Date:: Wed Sep 16 01:11:49 2020 +0000
Revision:: 0:bb348c97df44

Added PWM

Who changed what in which revision?

User	Revision	Line number	New contents of line
lypinator	0:bb348c97df44	1	/**
lypinator	0:bb348c97df44	2	******************************************************************************
lypinator	0:bb348c97df44	3	* @file stm32f4xx_ll_spi.h
lypinator	0:bb348c97df44	4	* @author MCD Application Team
lypinator	0:bb348c97df44	5	* @brief Header file of SPI LL module.
lypinator	0:bb348c97df44	6	******************************************************************************
lypinator	0:bb348c97df44	7	* @attention
lypinator	0:bb348c97df44	8	*
lypinator	0:bb348c97df44	9	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
lypinator	0:bb348c97df44	10	*
lypinator	0:bb348c97df44	11	* Redistribution and use in source and binary forms, with or without modification,
lypinator	0:bb348c97df44	12	* are permitted provided that the following conditions are met:
lypinator	0:bb348c97df44	13	* 1. Redistributions of source code must retain the above copyright notice,
lypinator	0:bb348c97df44	14	* this list of conditions and the following disclaimer.
lypinator	0:bb348c97df44	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
lypinator	0:bb348c97df44	16	* this list of conditions and the following disclaimer in the documentation
lypinator	0:bb348c97df44	17	* and/or other materials provided with the distribution.
lypinator	0:bb348c97df44	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
lypinator	0:bb348c97df44	19	* may be used to endorse or promote products derived from this software
lypinator	0:bb348c97df44	20	* without specific prior written permission.
lypinator	0:bb348c97df44	21	*
lypinator	0:bb348c97df44	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
lypinator	0:bb348c97df44	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
lypinator	0:bb348c97df44	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
lypinator	0:bb348c97df44	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
lypinator	0:bb348c97df44	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
lypinator	0:bb348c97df44	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
lypinator	0:bb348c97df44	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
lypinator	0:bb348c97df44	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
lypinator	0:bb348c97df44	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
lypinator	0:bb348c97df44	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
lypinator	0:bb348c97df44	32	*
lypinator	0:bb348c97df44	33	******************************************************************************
lypinator	0:bb348c97df44	34	*/
lypinator	0:bb348c97df44	35
lypinator	0:bb348c97df44	36	/* Define to prevent recursive inclusion -------------------------------------*/
lypinator	0:bb348c97df44	37	#ifndef __STM32F4xx_LL_SPI_H
lypinator	0:bb348c97df44	38	#define __STM32F4xx_LL_SPI_H
lypinator	0:bb348c97df44	39
lypinator	0:bb348c97df44	40	#ifdef __cplusplus
lypinator	0:bb348c97df44	41	extern "C" {
lypinator	0:bb348c97df44	42	#endif
lypinator	0:bb348c97df44	43
lypinator	0:bb348c97df44	44	/* Includes ------------------------------------------------------------------*/
lypinator	0:bb348c97df44	45	#include "stm32f4xx.h"
lypinator	0:bb348c97df44	46
lypinator	0:bb348c97df44	47	/** @addtogroup STM32F4xx_LL_Driver
lypinator	0:bb348c97df44	48	* @{
lypinator	0:bb348c97df44	49	*/
lypinator	0:bb348c97df44	50
lypinator	0:bb348c97df44	51	#if defined (SPI1) \|\| defined (SPI2) \|\| defined (SPI3) \|\| defined (SPI4) \|\| defined (SPI5) \|\| defined(SPI6)
lypinator	0:bb348c97df44	52
lypinator	0:bb348c97df44	53	/** @defgroup SPI_LL SPI
lypinator	0:bb348c97df44	54	* @{
lypinator	0:bb348c97df44	55	*/
lypinator	0:bb348c97df44	56
lypinator	0:bb348c97df44	57	/* Private types -------------------------------------------------------------*/
lypinator	0:bb348c97df44	58	/* Private variables ---------------------------------------------------------*/
lypinator	0:bb348c97df44	59	/* Private macros ------------------------------------------------------------*/
lypinator	0:bb348c97df44	60
lypinator	0:bb348c97df44	61	/* Exported types ------------------------------------------------------------*/
lypinator	0:bb348c97df44	62	#if defined(USE_FULL_LL_DRIVER)
lypinator	0:bb348c97df44	63	/** @defgroup SPI_LL_ES_INIT SPI Exported Init structure
lypinator	0:bb348c97df44	64	* @{
lypinator	0:bb348c97df44	65	*/
lypinator	0:bb348c97df44	66
lypinator	0:bb348c97df44	67	/**
lypinator	0:bb348c97df44	68	* @brief SPI Init structures definition
lypinator	0:bb348c97df44	69	*/
lypinator	0:bb348c97df44	70	typedef struct
lypinator	0:bb348c97df44	71	{
lypinator	0:bb348c97df44	72	uint32_t TransferDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode.
lypinator	0:bb348c97df44	73	This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE.
lypinator	0:bb348c97df44	74
lypinator	0:bb348c97df44	75	This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferDirection().*/
lypinator	0:bb348c97df44	76
lypinator	0:bb348c97df44	77	uint32_t Mode; /*!< Specifies the SPI mode (Master/Slave).
lypinator	0:bb348c97df44	78	This parameter can be a value of @ref SPI_LL_EC_MODE.
lypinator	0:bb348c97df44	79
lypinator	0:bb348c97df44	80	This feature can be modified afterwards using unitary function @ref LL_SPI_SetMode().*/
lypinator	0:bb348c97df44	81
lypinator	0:bb348c97df44	82	uint32_t DataWidth; /*!< Specifies the SPI data width.
lypinator	0:bb348c97df44	83	This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH.
lypinator	0:bb348c97df44	84
lypinator	0:bb348c97df44	85	This feature can be modified afterwards using unitary function @ref LL_SPI_SetDataWidth().*/
lypinator	0:bb348c97df44	86
lypinator	0:bb348c97df44	87	uint32_t ClockPolarity; /*!< Specifies the serial clock steady state.
lypinator	0:bb348c97df44	88	This parameter can be a value of @ref SPI_LL_EC_POLARITY.
lypinator	0:bb348c97df44	89
lypinator	0:bb348c97df44	90	This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPolarity().*/
lypinator	0:bb348c97df44	91
lypinator	0:bb348c97df44	92	uint32_t ClockPhase; /*!< Specifies the clock active edge for the bit capture.
lypinator	0:bb348c97df44	93	This parameter can be a value of @ref SPI_LL_EC_PHASE.
lypinator	0:bb348c97df44	94
lypinator	0:bb348c97df44	95	This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPhase().*/
lypinator	0:bb348c97df44	96
lypinator	0:bb348c97df44	97	uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit.
lypinator	0:bb348c97df44	98	This parameter can be a value of @ref SPI_LL_EC_NSS_MODE.
lypinator	0:bb348c97df44	99
lypinator	0:bb348c97df44	100	This feature can be modified afterwards using unitary function @ref LL_SPI_SetNSSMode().*/
lypinator	0:bb348c97df44	101
lypinator	0:bb348c97df44	102	uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock.
lypinator	0:bb348c97df44	103	This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER.
lypinator	0:bb348c97df44	104	@note The communication clock is derived from the master clock. The slave clock does not need to be set.
lypinator	0:bb348c97df44	105
lypinator	0:bb348c97df44	106	This feature can be modified afterwards using unitary function @ref LL_SPI_SetBaudRatePrescaler().*/
lypinator	0:bb348c97df44	107
lypinator	0:bb348c97df44	108	uint32_t BitOrder; /*!< Specifies whether data transfers start from MSB or LSB bit.
lypinator	0:bb348c97df44	109	This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER.
lypinator	0:bb348c97df44	110
lypinator	0:bb348c97df44	111	This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferBitOrder().*/
lypinator	0:bb348c97df44	112
lypinator	0:bb348c97df44	113	uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
lypinator	0:bb348c97df44	114	This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION.
lypinator	0:bb348c97df44	115
lypinator	0:bb348c97df44	116	This feature can be modified afterwards using unitary functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/
lypinator	0:bb348c97df44	117
lypinator	0:bb348c97df44	118	uint32_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation.
lypinator	0:bb348c97df44	119	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF.
lypinator	0:bb348c97df44	120
lypinator	0:bb348c97df44	121	This feature can be modified afterwards using unitary function @ref LL_SPI_SetCRCPolynomial().*/
lypinator	0:bb348c97df44	122
lypinator	0:bb348c97df44	123	} LL_SPI_InitTypeDef;
lypinator	0:bb348c97df44	124
lypinator	0:bb348c97df44	125	/**
lypinator	0:bb348c97df44	126	* @}
lypinator	0:bb348c97df44	127	*/
lypinator	0:bb348c97df44	128	#endif /* USE_FULL_LL_DRIVER */
lypinator	0:bb348c97df44	129
lypinator	0:bb348c97df44	130	/* Exported constants --------------------------------------------------------*/
lypinator	0:bb348c97df44	131	/** @defgroup SPI_LL_Exported_Constants SPI Exported Constants
lypinator	0:bb348c97df44	132	* @{
lypinator	0:bb348c97df44	133	*/
lypinator	0:bb348c97df44	134
lypinator	0:bb348c97df44	135	/** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines
lypinator	0:bb348c97df44	136	* @brief Flags defines which can be used with LL_SPI_ReadReg function
lypinator	0:bb348c97df44	137	* @{
lypinator	0:bb348c97df44	138	*/
lypinator	0:bb348c97df44	139	#define LL_SPI_SR_RXNE SPI_SR_RXNE /!< Rx buffer not empty flag /
lypinator	0:bb348c97df44	140	#define LL_SPI_SR_TXE SPI_SR_TXE /!< Tx buffer empty flag /
lypinator	0:bb348c97df44	141	#define LL_SPI_SR_BSY SPI_SR_BSY /!< Busy flag /
lypinator	0:bb348c97df44	142	#define LL_SPI_SR_CRCERR SPI_SR_CRCERR /!< CRC error flag /
lypinator	0:bb348c97df44	143	#define LL_SPI_SR_MODF SPI_SR_MODF /!< Mode fault flag /
lypinator	0:bb348c97df44	144	#define LL_SPI_SR_OVR SPI_SR_OVR /!< Overrun flag /
lypinator	0:bb348c97df44	145	#define LL_SPI_SR_FRE SPI_SR_FRE /!< TI mode frame format error flag /
lypinator	0:bb348c97df44	146	/**
lypinator	0:bb348c97df44	147	* @}
lypinator	0:bb348c97df44	148	*/
lypinator	0:bb348c97df44	149
lypinator	0:bb348c97df44	150	/** @defgroup SPI_LL_EC_IT IT Defines
lypinator	0:bb348c97df44	151	* @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
lypinator	0:bb348c97df44	152	* @{
lypinator	0:bb348c97df44	153	*/
lypinator	0:bb348c97df44	154	#define LL_SPI_CR2_RXNEIE SPI_CR2_RXNEIE /!< Rx buffer not empty interrupt enable /
lypinator	0:bb348c97df44	155	#define LL_SPI_CR2_TXEIE SPI_CR2_TXEIE /!< Tx buffer empty interrupt enable /
lypinator	0:bb348c97df44	156	#define LL_SPI_CR2_ERRIE SPI_CR2_ERRIE /!< Error interrupt enable /
lypinator	0:bb348c97df44	157	/**
lypinator	0:bb348c97df44	158	* @}
lypinator	0:bb348c97df44	159	*/
lypinator	0:bb348c97df44	160
lypinator	0:bb348c97df44	161	/** @defgroup SPI_LL_EC_MODE Operation Mode
lypinator	0:bb348c97df44	162	* @{
lypinator	0:bb348c97df44	163	*/
lypinator	0:bb348c97df44	164	#define LL_SPI_MODE_MASTER (SPI_CR1_MSTR \| SPI_CR1_SSI) /!< Master configuration /
lypinator	0:bb348c97df44	165	#define LL_SPI_MODE_SLAVE 0x00000000U /!< Slave configuration /
lypinator	0:bb348c97df44	166	/**
lypinator	0:bb348c97df44	167	* @}
lypinator	0:bb348c97df44	168	*/
lypinator	0:bb348c97df44	169
lypinator	0:bb348c97df44	170	/** @defgroup SPI_LL_EC_PROTOCOL Serial Protocol
lypinator	0:bb348c97df44	171	* @{
lypinator	0:bb348c97df44	172	*/
lypinator	0:bb348c97df44	173	#define LL_SPI_PROTOCOL_MOTOROLA 0x00000000U /!< Motorola mode. Used as default value /
lypinator	0:bb348c97df44	174	#define LL_SPI_PROTOCOL_TI (SPI_CR2_FRF) /!< TI mode /
lypinator	0:bb348c97df44	175	/**
lypinator	0:bb348c97df44	176	* @}
lypinator	0:bb348c97df44	177	*/
lypinator	0:bb348c97df44	178
lypinator	0:bb348c97df44	179	/** @defgroup SPI_LL_EC_PHASE Clock Phase
lypinator	0:bb348c97df44	180	* @{
lypinator	0:bb348c97df44	181	*/
lypinator	0:bb348c97df44	182	#define LL_SPI_PHASE_1EDGE 0x00000000U /!< First clock transition is the first data capture edge /
lypinator	0:bb348c97df44	183	#define LL_SPI_PHASE_2EDGE (SPI_CR1_CPHA) /!< Second clock transition is the first data capture edge /
lypinator	0:bb348c97df44	184	/**
lypinator	0:bb348c97df44	185	* @}
lypinator	0:bb348c97df44	186	*/
lypinator	0:bb348c97df44	187
lypinator	0:bb348c97df44	188	/** @defgroup SPI_LL_EC_POLARITY Clock Polarity
lypinator	0:bb348c97df44	189	* @{
lypinator	0:bb348c97df44	190	*/
lypinator	0:bb348c97df44	191	#define LL_SPI_POLARITY_LOW 0x00000000U /!< Clock to 0 when idle /
lypinator	0:bb348c97df44	192	#define LL_SPI_POLARITY_HIGH (SPI_CR1_CPOL) /!< Clock to 1 when idle /
lypinator	0:bb348c97df44	193	/**
lypinator	0:bb348c97df44	194	* @}
lypinator	0:bb348c97df44	195	*/
lypinator	0:bb348c97df44	196
lypinator	0:bb348c97df44	197	/** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler
lypinator	0:bb348c97df44	198	* @{
lypinator	0:bb348c97df44	199	*/
lypinator	0:bb348c97df44	200	#define LL_SPI_BAUDRATEPRESCALER_DIV2 0x00000000U /!< BaudRate control equal to fPCLK/2 /
lypinator	0:bb348c97df44	201	#define LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CR1_BR_0) /!< BaudRate control equal to fPCLK/4 /
lypinator	0:bb348c97df44	202	#define LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CR1_BR_1) /!< BaudRate control equal to fPCLK/8 /
lypinator	0:bb348c97df44	203	#define LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CR1_BR_1 \| SPI_CR1_BR_0) /!< BaudRate control equal to fPCLK/16 /
lypinator	0:bb348c97df44	204	#define LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CR1_BR_2) /!< BaudRate control equal to fPCLK/32 /
lypinator	0:bb348c97df44	205	#define LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CR1_BR_2 \| SPI_CR1_BR_0) /!< BaudRate control equal to fPCLK/64 /
lypinator	0:bb348c97df44	206	#define LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CR1_BR_2 \| SPI_CR1_BR_1) /!< BaudRate control equal to fPCLK/128 /
lypinator	0:bb348c97df44	207	#define LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CR1_BR_2 \| SPI_CR1_BR_1 \| SPI_CR1_BR_0) /!< BaudRate control equal to fPCLK/256 /
lypinator	0:bb348c97df44	208	/**
lypinator	0:bb348c97df44	209	* @}
lypinator	0:bb348c97df44	210	*/
lypinator	0:bb348c97df44	211
lypinator	0:bb348c97df44	212	/** @defgroup SPI_LL_EC_BIT_ORDER Transmission Bit Order
lypinator	0:bb348c97df44	213	* @{
lypinator	0:bb348c97df44	214	*/
lypinator	0:bb348c97df44	215	#define LL_SPI_LSB_FIRST (SPI_CR1_LSBFIRST) /!< Data is transmitted/received with the LSB first /
lypinator	0:bb348c97df44	216	#define LL_SPI_MSB_FIRST 0x00000000U /!< Data is transmitted/received with the MSB first /
lypinator	0:bb348c97df44	217	/**
lypinator	0:bb348c97df44	218	* @}
lypinator	0:bb348c97df44	219	*/
lypinator	0:bb348c97df44	220
lypinator	0:bb348c97df44	221	/** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode
lypinator	0:bb348c97df44	222	* @{
lypinator	0:bb348c97df44	223	*/
lypinator	0:bb348c97df44	224	#define LL_SPI_FULL_DUPLEX 0x00000000U /!< Full-Duplex mode. Rx and Tx transfer on 2 lines /
lypinator	0:bb348c97df44	225	#define LL_SPI_SIMPLEX_RX (SPI_CR1_RXONLY) /!< Simplex Rx mode. Rx transfer only on 1 line /
lypinator	0:bb348c97df44	226	#define LL_SPI_HALF_DUPLEX_RX (SPI_CR1_BIDIMODE) /!< Half-Duplex Rx mode. Rx transfer on 1 line /
lypinator	0:bb348c97df44	227	#define LL_SPI_HALF_DUPLEX_TX (SPI_CR1_BIDIMODE \| SPI_CR1_BIDIOE) /!< Half-Duplex Tx mode. Tx transfer on 1 line /
lypinator	0:bb348c97df44	228	/**
lypinator	0:bb348c97df44	229	* @}
lypinator	0:bb348c97df44	230	*/
lypinator	0:bb348c97df44	231
lypinator	0:bb348c97df44	232	/** @defgroup SPI_LL_EC_NSS_MODE Slave Select Pin Mode
lypinator	0:bb348c97df44	233	* @{
lypinator	0:bb348c97df44	234	*/
lypinator	0:bb348c97df44	235	#define LL_SPI_NSS_SOFT (SPI_CR1_SSM) /!< NSS managed internally. NSS pin not used and free /
lypinator	0:bb348c97df44	236	#define LL_SPI_NSS_HARD_INPUT 0x00000000U /!< NSS pin used in Input. Only used in Master mode /
lypinator	0:bb348c97df44	237	#define LL_SPI_NSS_HARD_OUTPUT (((uint32_t)SPI_CR2_SSOE << 16U)) /!< NSS pin used in Output. Only used in Slave mode as chip select /
lypinator	0:bb348c97df44	238	/**
lypinator	0:bb348c97df44	239	* @}
lypinator	0:bb348c97df44	240	*/
lypinator	0:bb348c97df44	241
lypinator	0:bb348c97df44	242	/** @defgroup SPI_LL_EC_DATAWIDTH Datawidth
lypinator	0:bb348c97df44	243	* @{
lypinator	0:bb348c97df44	244	*/
lypinator	0:bb348c97df44	245	#define LL_SPI_DATAWIDTH_8BIT 0x00000000U /!< Data length for SPI transfer: 8 bits /
lypinator	0:bb348c97df44	246	#define LL_SPI_DATAWIDTH_16BIT (SPI_CR1_DFF) /!< Data length for SPI transfer: 16 bits /
lypinator	0:bb348c97df44	247	/**
lypinator	0:bb348c97df44	248	* @}
lypinator	0:bb348c97df44	249	*/
lypinator	0:bb348c97df44	250	#if defined(USE_FULL_LL_DRIVER)
lypinator	0:bb348c97df44	251
lypinator	0:bb348c97df44	252	/** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation
lypinator	0:bb348c97df44	253	* @{
lypinator	0:bb348c97df44	254	*/
lypinator	0:bb348c97df44	255	#define LL_SPI_CRCCALCULATION_DISABLE 0x00000000U /!< CRC calculation disabled /
lypinator	0:bb348c97df44	256	#define LL_SPI_CRCCALCULATION_ENABLE (SPI_CR1_CRCEN) /!< CRC calculation enabled /
lypinator	0:bb348c97df44	257	/**
lypinator	0:bb348c97df44	258	* @}
lypinator	0:bb348c97df44	259	*/
lypinator	0:bb348c97df44	260	#endif /* USE_FULL_LL_DRIVER */
lypinator	0:bb348c97df44	261
lypinator	0:bb348c97df44	262	/**
lypinator	0:bb348c97df44	263	* @}
lypinator	0:bb348c97df44	264	*/
lypinator	0:bb348c97df44	265
lypinator	0:bb348c97df44	266	/* Exported macro ------------------------------------------------------------*/
lypinator	0:bb348c97df44	267	/** @defgroup SPI_LL_Exported_Macros SPI Exported Macros
lypinator	0:bb348c97df44	268	* @{
lypinator	0:bb348c97df44	269	*/
lypinator	0:bb348c97df44	270
lypinator	0:bb348c97df44	271	/** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros
lypinator	0:bb348c97df44	272	* @{
lypinator	0:bb348c97df44	273	*/
lypinator	0:bb348c97df44	274
lypinator	0:bb348c97df44	275	/**
lypinator	0:bb348c97df44	276	* @brief Write a value in SPI register
lypinator	0:bb348c97df44	277	* @param __INSTANCE__ SPI Instance
lypinator	0:bb348c97df44	278	* @param __REG__ Register to be written
lypinator	0:bb348c97df44	279	* @param __VALUE__ Value to be written in the register
lypinator	0:bb348c97df44	280	* @retval None
lypinator	0:bb348c97df44	281	*/
lypinator	0:bb348c97df44	282	#define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
lypinator	0:bb348c97df44	283
lypinator	0:bb348c97df44	284	/**
lypinator	0:bb348c97df44	285	* @brief Read a value in SPI register
lypinator	0:bb348c97df44	286	* @param __INSTANCE__ SPI Instance
lypinator	0:bb348c97df44	287	* @param __REG__ Register to be read
lypinator	0:bb348c97df44	288	* @retval Register value
lypinator	0:bb348c97df44	289	*/
lypinator	0:bb348c97df44	290	#define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
lypinator	0:bb348c97df44	291	/**
lypinator	0:bb348c97df44	292	* @}
lypinator	0:bb348c97df44	293	*/
lypinator	0:bb348c97df44	294
lypinator	0:bb348c97df44	295	/**
lypinator	0:bb348c97df44	296	* @}
lypinator	0:bb348c97df44	297	*/
lypinator	0:bb348c97df44	298
lypinator	0:bb348c97df44	299	/* Exported functions --------------------------------------------------------*/
lypinator	0:bb348c97df44	300	/** @defgroup SPI_LL_Exported_Functions SPI Exported Functions
lypinator	0:bb348c97df44	301	* @{
lypinator	0:bb348c97df44	302	*/
lypinator	0:bb348c97df44	303
lypinator	0:bb348c97df44	304	/** @defgroup SPI_LL_EF_Configuration Configuration
lypinator	0:bb348c97df44	305	* @{
lypinator	0:bb348c97df44	306	*/
lypinator	0:bb348c97df44	307
lypinator	0:bb348c97df44	308	/**
lypinator	0:bb348c97df44	309	* @brief Enable SPI peripheral
lypinator	0:bb348c97df44	310	* @rmtoll CR1 SPE LL_SPI_Enable
lypinator	0:bb348c97df44	311	* @param SPIx SPI Instance
lypinator	0:bb348c97df44	312	* @retval None
lypinator	0:bb348c97df44	313	*/
lypinator	0:bb348c97df44	314	__STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx)
lypinator	0:bb348c97df44	315	{
lypinator	0:bb348c97df44	316	SET_BIT(SPIx->CR1, SPI_CR1_SPE);
lypinator	0:bb348c97df44	317	}
lypinator	0:bb348c97df44	318
lypinator	0:bb348c97df44	319	/**
lypinator	0:bb348c97df44	320	* @brief Disable SPI peripheral
lypinator	0:bb348c97df44	321	* @note When disabling the SPI, follow the procedure described in the Reference Manual.
lypinator	0:bb348c97df44	322	* @rmtoll CR1 SPE LL_SPI_Disable
lypinator	0:bb348c97df44	323	* @param SPIx SPI Instance
lypinator	0:bb348c97df44	324	* @retval None
lypinator	0:bb348c97df44	325	*/
lypinator	0:bb348c97df44	326	__STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx)
lypinator	0:bb348c97df44	327	{
lypinator	0:bb348c97df44	328	CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
lypinator	0:bb348c97df44	329	}
lypinator	0:bb348c97df44	330
lypinator	0:bb348c97df44	331	/**
lypinator	0:bb348c97df44	332	* @brief Check if SPI peripheral is enabled
lypinator	0:bb348c97df44	333	* @rmtoll CR1 SPE LL_SPI_IsEnabled
lypinator	0:bb348c97df44	334	* @param SPIx SPI Instance
lypinator	0:bb348c97df44	335	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	336	*/
lypinator	0:bb348c97df44	337	__STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx)
lypinator	0:bb348c97df44	338	{
lypinator	0:bb348c97df44	339	return (READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE));
lypinator	0:bb348c97df44	340	}
lypinator	0:bb348c97df44	341
lypinator	0:bb348c97df44	342	/**
lypinator	0:bb348c97df44	343	* @brief Set SPI operation mode to Master or Slave
lypinator	0:bb348c97df44	344	* @note This bit should not be changed when communication is ongoing.
lypinator	0:bb348c97df44	345	* @rmtoll CR1 MSTR LL_SPI_SetMode\n
lypinator	0:bb348c97df44	346	* CR1 SSI LL_SPI_SetMode
lypinator	0:bb348c97df44	347	* @param SPIx SPI Instance
lypinator	0:bb348c97df44	348	* @param Mode This parameter can be one of the following values:
lypinator	0:bb348c97df44	349	* @arg @ref LL_SPI_MODE_MASTER
lypinator	0:bb348c97df44	350	* @arg @ref LL_SPI_MODE_SLAVE
lypinator	0:bb348c97df44	351	* @retval None
lypinator	0:bb348c97df44	352	*/
lypinator	0:bb348c97df44	353	__STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode)
lypinator	0:bb348c97df44	354	{
lypinator	0:bb348c97df44	355	MODIFY_REG(SPIx->CR1, SPI_CR1_MSTR \| SPI_CR1_SSI, Mode);
lypinator	0:bb348c97df44	356	}
lypinator	0:bb348c97df44	357
lypinator	0:bb348c97df44	358	/**
lypinator	0:bb348c97df44	359	* @brief Get SPI operation mode (Master or Slave)
lypinator	0:bb348c97df44	360	* @rmtoll CR1 MSTR LL_SPI_GetMode\n
lypinator	0:bb348c97df44	361	* CR1 SSI LL_SPI_GetMode
lypinator	0:bb348c97df44	362	* @param SPIx SPI Instance
lypinator	0:bb348c97df44	363	* @retval Returned value can be one of the following values:
lypinator	0:bb348c97df44	364	* @arg @ref LL_SPI_MODE_MASTER
lypinator	0:bb348c97df44	365	* @arg @ref LL_SPI_MODE_SLAVE
lypinator	0:bb348c97df44	366	*/
lypinator	0:bb348c97df44	367	__STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx)
lypinator	0:bb348c97df44	368	{
lypinator	0:bb348c97df44	369	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR \| SPI_CR1_SSI));
lypinator	0:bb348c97df44	370	}
lypinator	0:bb348c97df44	371
lypinator	0:bb348c97df44	372	/**
lypinator	0:bb348c97df44	373	* @brief Set serial protocol used
lypinator	0:bb348c97df44	374	* @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
lypinator	0:bb348c97df44	375	* @rmtoll CR2 FRF LL_SPI_SetStandard
lypinator	0:bb348c97df44	376	* @param SPIx SPI Instance
lypinator	0:bb348c97df44	377	* @param Standard This parameter can be one of the following values:
lypinator	0:bb348c97df44	378	* @arg @ref LL_SPI_PROTOCOL_MOTOROLA
lypinator	0:bb348c97df44	379	* @arg @ref LL_SPI_PROTOCOL_TI
lypinator	0:bb348c97df44	380	* @retval None
lypinator	0:bb348c97df44	381	*/
lypinator	0:bb348c97df44	382	__STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
lypinator	0:bb348c97df44	383	{
lypinator	0:bb348c97df44	384	MODIFY_REG(SPIx->CR2, SPI_CR2_FRF, Standard);
lypinator	0:bb348c97df44	385	}
lypinator	0:bb348c97df44	386
lypinator	0:bb348c97df44	387	/**
lypinator	0:bb348c97df44	388	* @brief Get serial protocol used
lypinator	0:bb348c97df44	389	* @rmtoll CR2 FRF LL_SPI_GetStandard
lypinator	0:bb348c97df44	390	* @param SPIx SPI Instance
lypinator	0:bb348c97df44	391	* @retval Returned value can be one of the following values:
lypinator	0:bb348c97df44	392	* @arg @ref LL_SPI_PROTOCOL_MOTOROLA
lypinator	0:bb348c97df44	393	* @arg @ref LL_SPI_PROTOCOL_TI
lypinator	0:bb348c97df44	394	*/
lypinator	0:bb348c97df44	395	__STATIC_INLINE uint32_t LL_SPI_GetStandard(SPI_TypeDef *SPIx)
lypinator	0:bb348c97df44	396	{
lypinator	0:bb348c97df44	397	return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRF));
lypinator	0:bb348c97df44	398	}
lypinator	0:bb348c97df44	399
lypinator	0:bb348c97df44	400	/**
lypinator	0:bb348c97df44	401	* @brief Set clock phase
lypinator	0:bb348c97df44	402	* @note This bit should not be changed when communication is ongoing.
lypinator	0:bb348c97df44	403	* This bit is not used in SPI TI mode.
lypinator	0:bb348c97df44	404	* @rmtoll CR1 CPHA LL_SPI_SetClockPhase
lypinator	0:bb348c97df44	405	* @param SPIx SPI Instance
lypinator	0:bb348c97df44	406	* @param ClockPhase This parameter can be one of the following values:
lypinator	0:bb348c97df44	407	* @arg @ref LL_SPI_PHASE_1EDGE
lypinator	0:bb348c97df44	408	* @arg @ref LL_SPI_PHASE_2EDGE
lypinator	0:bb348c97df44	409	* @retval None
lypinator	0:bb348c97df44	410	*/
lypinator	0:bb348c97df44	411	__STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase)
lypinator	0:bb348c97df44	412	{
lypinator	0:bb348c97df44	413	MODIFY_REG(SPIx->CR1, SPI_CR1_CPHA, ClockPhase);
lypinator	0:bb348c97df44	414	}
lypinator	0:bb348c97df44	415
lypinator	0:bb348c97df44	416	/**
lypinator	0:bb348c97df44	417	* @brief Get clock phase
lypinator	0:bb348c97df44	418	* @rmtoll CR1 CPHA LL_SPI_GetClockPhase
lypinator	0:bb348c97df44	419	* @param SPIx SPI Instance
lypinator	0:bb348c97df44	420	* @retval Returned value can be one of the following values:
lypinator	0:bb348c97df44	421	* @arg @ref LL_SPI_PHASE_1EDGE
lypinator	0:bb348c97df44	422	* @arg @ref LL_SPI_PHASE_2EDGE
lypinator	0:bb348c97df44	423	*/
lypinator	0:bb348c97df44	424	__STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx)
lypinator	0:bb348c97df44	425	{
lypinator	0:bb348c97df44	426	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA));
lypinator	0:bb348c97df44	427	}
lypinator	0:bb348c97df44	428
lypinator	0:bb348c97df44	429	/**
lypinator	0:bb348c97df44	430	* @brief Set clock polarity
lypinator	0:bb348c97df44	431	* @note This bit should not be changed when communication is ongoing.
lypinator	0:bb348c97df44	432	* This bit is not used in SPI TI mode.
lypinator	0:bb348c97df44	433	* @rmtoll CR1 CPOL LL_SPI_SetClockPolarity
lypinator	0:bb348c97df44	434	* @param SPIx SPI Instance
lypinator	0:bb348c97df44	435	* @param ClockPolarity This parameter can be one of the following values:
lypinator	0:bb348c97df44	436	* @arg @ref LL_SPI_POLARITY_LOW
lypinator	0:bb348c97df44	437	* @arg @ref LL_SPI_POLARITY_HIGH
lypinator	0:bb348c97df44	438	* @retval None
lypinator	0:bb348c97df44	439	*/
lypinator	0:bb348c97df44	440	__STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
lypinator	0:bb348c97df44	441	{
lypinator	0:bb348c97df44	442	MODIFY_REG(SPIx->CR1, SPI_CR1_CPOL, ClockPolarity);
lypinator	0:bb348c97df44	443	}
lypinator	0:bb348c97df44	444
lypinator	0:bb348c97df44	445	/**
lypinator	0:bb348c97df44	446	* @brief Get clock polarity
lypinator	0:bb348c97df44	447	* @rmtoll CR1 CPOL LL_SPI_GetClockPolarity
lypinator	0:bb348c97df44	448	* @param SPIx SPI Instance
lypinator	0:bb348c97df44	449	* @retval Returned value can be one of the following values:
lypinator	0:bb348c97df44	450	* @arg @ref LL_SPI_POLARITY_LOW
lypinator	0:bb348c97df44	451	* @arg @ref LL_SPI_POLARITY_HIGH
lypinator	0:bb348c97df44	452	*/
lypinator	0:bb348c97df44	453	__STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx)
lypinator	0:bb348c97df44	454	{
lypinator	0:bb348c97df44	455	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPOL));
lypinator	0:bb348c97df44	456	}
lypinator	0:bb348c97df44	457
lypinator	0:bb348c97df44	458	/**
lypinator	0:bb348c97df44	459	* @brief Set baud rate prescaler
lypinator	0:bb348c97df44	460	* @note These bits should not be changed when communication is ongoing. SPI BaudRate = fPCLK/Prescaler.
lypinator	0:bb348c97df44	461	* @rmtoll CR1 BR LL_SPI_SetBaudRatePrescaler
lypinator	0:bb348c97df44	462	* @param SPIx SPI Instance
lypinator	0:bb348c97df44	463	* @param BaudRate This parameter can be one of the following values:
lypinator	0:bb348c97df44	464	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
lypinator	0:bb348c97df44	465	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
lypinator	0:bb348c97df44	466	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
lypinator	0:bb348c97df44	467	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
lypinator	0:bb348c97df44	468	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
lypinator	0:bb348c97df44	469	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
lypinator	0:bb348c97df44	470	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
lypinator	0:bb348c97df44	471	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
lypinator	0:bb348c97df44	472	* @retval None
lypinator	0:bb348c97df44	473	*/
lypinator	0:bb348c97df44	474	__STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t BaudRate)
lypinator	0:bb348c97df44	475	{
lypinator	0:bb348c97df44	476	MODIFY_REG(SPIx->CR1, SPI_CR1_BR, BaudRate);
lypinator	0:bb348c97df44	477	}
lypinator	0:bb348c97df44	478
lypinator	0:bb348c97df44	479	/**
lypinator	0:bb348c97df44	480	* @brief Get baud rate prescaler
lypinator	0:bb348c97df44	481	* @rmtoll CR1 BR LL_SPI_GetBaudRatePrescaler
lypinator	0:bb348c97df44	482	* @param SPIx SPI Instance
lypinator	0:bb348c97df44	483	* @retval Returned value can be one of the following values:
lypinator	0:bb348c97df44	484	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
lypinator	0:bb348c97df44	485	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
lypinator	0:bb348c97df44	486	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
lypinator	0:bb348c97df44	487	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
lypinator	0:bb348c97df44	488	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
lypinator	0:bb348c97df44	489	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
lypinator	0:bb348c97df44	490	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
lypinator	0:bb348c97df44	491	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
lypinator	0:bb348c97df44	492	*/
lypinator	0:bb348c97df44	493	__STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx)
lypinator	0:bb348c97df44	494	{
lypinator	0:bb348c97df44	495	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BR));
lypinator	0:bb348c97df44	496	}
lypinator	0:bb348c97df44	497
lypinator	0:bb348c97df44	498	/**
lypinator	0:bb348c97df44	499	* @brief Set transfer bit order
lypinator	0:bb348c97df44	500	* @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
lypinator	0:bb348c97df44	501	* @rmtoll CR1 LSBFIRST LL_SPI_SetTransferBitOrder
lypinator	0:bb348c97df44	502	* @param SPIx SPI Instance
lypinator	0:bb348c97df44	503	* @param BitOrder This parameter can be one of the following values:
lypinator	0:bb348c97df44	504	* @arg @ref LL_SPI_LSB_FIRST
lypinator	0:bb348c97df44	505	* @arg @ref LL_SPI_MSB_FIRST
lypinator	0:bb348c97df44	506	* @retval None
lypinator	0:bb348c97df44	507	*/
lypinator	0:bb348c97df44	508	__STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder)
lypinator	0:bb348c97df44	509	{
lypinator	0:bb348c97df44	510	MODIFY_REG(SPIx->CR1, SPI_CR1_LSBFIRST, BitOrder);
lypinator	0:bb348c97df44	511	}
lypinator	0:bb348c97df44	512
lypinator	0:bb348c97df44	513	/**
lypinator	0:bb348c97df44	514	* @brief Get transfer bit order
lypinator	0:bb348c97df44	515	* @rmtoll CR1 LSBFIRST LL_SPI_GetTransferBitOrder
lypinator	0:bb348c97df44	516	* @param SPIx SPI Instance
lypinator	0:bb348c97df44	517	* @retval Returned value can be one of the following values:
lypinator	0:bb348c97df44	518	* @arg @ref LL_SPI_LSB_FIRST
lypinator	0:bb348c97df44	519	* @arg @ref LL_SPI_MSB_FIRST
lypinator	0:bb348c97df44	520	*/
lypinator	0:bb348c97df44	521	__STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx)
lypinator	0:bb348c97df44	522	{
lypinator	0:bb348c97df44	523	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_LSBFIRST));
lypinator	0:bb348c97df44	524	}
lypinator	0:bb348c97df44	525
lypinator	0:bb348c97df44	526	/**
lypinator	0:bb348c97df44	527	* @brief Set transfer direction mode
lypinator	0:bb348c97df44	528	* @note For Half-Duplex mode, Rx Direction is set by default.
lypinator	0:bb348c97df44	529	* In master mode, the MOSI pin is used and in slave mode, the MISO pin is used for Half-Duplex.
lypinator	0:bb348c97df44	530	* @rmtoll CR1 RXONLY LL_SPI_SetTransferDirection\n
lypinator	0:bb348c97df44	531	* CR1 BIDIMODE LL_SPI_SetTransferDirection\n
lypinator	0:bb348c97df44	532	* CR1 BIDIOE LL_SPI_SetTransferDirection
lypinator	0:bb348c97df44	533	* @param SPIx SPI Instance
lypinator	0:bb348c97df44	534	* @param TransferDirection This parameter can be one of the following values:
lypinator	0:bb348c97df44	535	* @arg @ref LL_SPI_FULL_DUPLEX
lypinator	0:bb348c97df44	536	* @arg @ref LL_SPI_SIMPLEX_RX
lypinator	0:bb348c97df44	537	* @arg @ref LL_SPI_HALF_DUPLEX_RX
lypinator	0:bb348c97df44	538	* @arg @ref LL_SPI_HALF_DUPLEX_TX
lypinator	0:bb348c97df44	539	* @retval None
lypinator	0:bb348c97df44	540	*/
lypinator	0:bb348c97df44	541	__STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection)
lypinator	0:bb348c97df44	542	{
lypinator	0:bb348c97df44	543	MODIFY_REG(SPIx->CR1, SPI_CR1_RXONLY \| SPI_CR1_BIDIMODE \| SPI_CR1_BIDIOE, TransferDirection);
lypinator	0:bb348c97df44	544	}
lypinator	0:bb348c97df44	545
lypinator	0:bb348c97df44	546	/**
lypinator	0:bb348c97df44	547	* @brief Get transfer direction mode
lypinator	0:bb348c97df44	548	* @rmtoll CR1 RXONLY LL_SPI_GetTransferDirection\n
lypinator	0:bb348c97df44	549	* CR1 BIDIMODE LL_SPI_GetTransferDirection\n
lypinator	0:bb348c97df44	550	* CR1 BIDIOE LL_SPI_GetTransferDirection
lypinator	0:bb348c97df44	551	* @param SPIx SPI Instance
lypinator	0:bb348c97df44	552	* @retval Returned value can be one of the following values:
lypinator	0:bb348c97df44	553	* @arg @ref LL_SPI_FULL_DUPLEX
lypinator	0:bb348c97df44	554	* @arg @ref LL_SPI_SIMPLEX_RX
lypinator	0:bb348c97df44	555	* @arg @ref LL_SPI_HALF_DUPLEX_RX
lypinator	0:bb348c97df44	556	* @arg @ref LL_SPI_HALF_DUPLEX_TX
lypinator	0:bb348c97df44	557	*/
lypinator	0:bb348c97df44	558	__STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx)
lypinator	0:bb348c97df44	559	{
lypinator	0:bb348c97df44	560	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RXONLY \| SPI_CR1_BIDIMODE \| SPI_CR1_BIDIOE));
lypinator	0:bb348c97df44	561	}
lypinator	0:bb348c97df44	562
lypinator	0:bb348c97df44	563	/**
lypinator	0:bb348c97df44	564	* @brief Set frame data width
lypinator	0:bb348c97df44	565	* @rmtoll CR1 DFF LL_SPI_SetDataWidth
lypinator	0:bb348c97df44	566	* @param SPIx SPI Instance
lypinator	0:bb348c97df44	567	* @param DataWidth This parameter can be one of the following values:
lypinator	0:bb348c97df44	568	* @arg @ref LL_SPI_DATAWIDTH_8BIT
lypinator	0:bb348c97df44	569	* @arg @ref LL_SPI_DATAWIDTH_16BIT
lypinator	0:bb348c97df44	570	* @retval None
lypinator	0:bb348c97df44	571	*/
lypinator	0:bb348c97df44	572	__STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth)
lypinator	0:bb348c97df44	573	{
lypinator	0:bb348c97df44	574	MODIFY_REG(SPIx->CR1, SPI_CR1_DFF, DataWidth);
lypinator	0:bb348c97df44	575	}
lypinator	0:bb348c97df44	576
lypinator	0:bb348c97df44	577	/**
lypinator	0:bb348c97df44	578	* @brief Get frame data width
lypinator	0:bb348c97df44	579	* @rmtoll CR1 DFF LL_SPI_GetDataWidth
lypinator	0:bb348c97df44	580	* @param SPIx SPI Instance
lypinator	0:bb348c97df44	581	* @retval Returned value can be one of the following values:
lypinator	0:bb348c97df44	582	* @arg @ref LL_SPI_DATAWIDTH_8BIT
lypinator	0:bb348c97df44	583	* @arg @ref LL_SPI_DATAWIDTH_16BIT
lypinator	0:bb348c97df44	584	*/
lypinator	0:bb348c97df44	585	__STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx)
lypinator	0:bb348c97df44	586	{
lypinator	0:bb348c97df44	587	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_DFF));
lypinator	0:bb348c97df44	588	}
lypinator	0:bb348c97df44	589
lypinator	0:bb348c97df44	590	/**
lypinator	0:bb348c97df44	591	* @}
lypinator	0:bb348c97df44	592	*/
lypinator	0:bb348c97df44	593
lypinator	0:bb348c97df44	594	/** @defgroup SPI_LL_EF_CRC_Management CRC Management
lypinator	0:bb348c97df44	595	* @{
lypinator	0:bb348c97df44	596	*/
lypinator	0:bb348c97df44	597
lypinator	0:bb348c97df44	598	/**
lypinator	0:bb348c97df44	599	* @brief Enable CRC
lypinator	0:bb348c97df44	600	* @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
lypinator	0:bb348c97df44	601	* @rmtoll CR1 CRCEN LL_SPI_EnableCRC
lypinator	0:bb348c97df44	602	* @param SPIx SPI Instance
lypinator	0:bb348c97df44	603	* @retval None
lypinator	0:bb348c97df44	604	*/
lypinator	0:bb348c97df44	605	__STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *SPIx)
lypinator	0:bb348c97df44	606	{
lypinator	0:bb348c97df44	607	SET_BIT(SPIx->CR1, SPI_CR1_CRCEN);
lypinator	0:bb348c97df44	608	}
lypinator	0:bb348c97df44	609
lypinator	0:bb348c97df44	610	/**
lypinator	0:bb348c97df44	611	* @brief Disable CRC
lypinator	0:bb348c97df44	612	* @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
lypinator	0:bb348c97df44	613	* @rmtoll CR1 CRCEN LL_SPI_DisableCRC
lypinator	0:bb348c97df44	614	* @param SPIx SPI Instance
lypinator	0:bb348c97df44	615	* @retval None
lypinator	0:bb348c97df44	616	*/
lypinator	0:bb348c97df44	617	__STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx)
lypinator	0:bb348c97df44	618	{
lypinator	0:bb348c97df44	619	CLEAR_BIT(SPIx->CR1, SPI_CR1_CRCEN);
lypinator	0:bb348c97df44	620	}
lypinator	0:bb348c97df44	621
lypinator	0:bb348c97df44	622	/**
lypinator	0:bb348c97df44	623	* @brief Check if CRC is enabled
lypinator	0:bb348c97df44	624	* @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
lypinator	0:bb348c97df44	625	* @rmtoll CR1 CRCEN LL_SPI_IsEnabledCRC
lypinator	0:bb348c97df44	626	* @param SPIx SPI Instance
lypinator	0:bb348c97df44	627	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	628	*/
lypinator	0:bb348c97df44	629	__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx)
lypinator	0:bb348c97df44	630	{
lypinator	0:bb348c97df44	631	return (READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN));
lypinator	0:bb348c97df44	632	}
lypinator	0:bb348c97df44	633
lypinator	0:bb348c97df44	634	/**
lypinator	0:bb348c97df44	635	* @brief Set CRCNext to transfer CRC on the line
lypinator	0:bb348c97df44	636	* @note This bit has to be written as soon as the last data is written in the SPIx_DR register.
lypinator	0:bb348c97df44	637	* @rmtoll CR1 CRCNEXT LL_SPI_SetCRCNext
lypinator	0:bb348c97df44	638	* @param SPIx SPI Instance
lypinator	0:bb348c97df44	639	* @retval None
lypinator	0:bb348c97df44	640	*/
lypinator	0:bb348c97df44	641	__STATIC_INLINE void LL_SPI_SetCRCNext(SPI_TypeDef *SPIx)
lypinator	0:bb348c97df44	642	{
lypinator	0:bb348c97df44	643	SET_BIT(SPIx->CR1, SPI_CR1_CRCNEXT);
lypinator	0:bb348c97df44	644	}
lypinator	0:bb348c97df44	645
lypinator	0:bb348c97df44	646	/**
lypinator	0:bb348c97df44	647	* @brief Set polynomial for CRC calculation
lypinator	0:bb348c97df44	648	* @rmtoll CRCPR CRCPOLY LL_SPI_SetCRCPolynomial
lypinator	0:bb348c97df44	649	* @param SPIx SPI Instance
lypinator	0:bb348c97df44	650	* @param CRCPoly This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF
lypinator	0:bb348c97df44	651	* @retval None
lypinator	0:bb348c97df44	652	*/
lypinator	0:bb348c97df44	653	__STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly)
lypinator	0:bb348c97df44	654	{
lypinator	0:bb348c97df44	655	WRITE_REG(SPIx->CRCPR, (uint16_t)CRCPoly);
lypinator	0:bb348c97df44	656	}
lypinator	0:bb348c97df44	657
lypinator	0:bb348c97df44	658	/**
lypinator	0:bb348c97df44	659	* @brief Get polynomial for CRC calculation
lypinator	0:bb348c97df44	660	* @rmtoll CRCPR CRCPOLY LL_SPI_GetCRCPolynomial
lypinator	0:bb348c97df44	661	* @param SPIx SPI Instance
lypinator	0:bb348c97df44	662	* @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
lypinator	0:bb348c97df44	663	*/
lypinator	0:bb348c97df44	664	__STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx)
lypinator	0:bb348c97df44	665	{
lypinator	0:bb348c97df44	666	return (uint32_t)(READ_REG(SPIx->CRCPR));
lypinator	0:bb348c97df44	667	}
lypinator	0:bb348c97df44	668
lypinator	0:bb348c97df44	669	/**
lypinator	0:bb348c97df44	670	* @brief Get Rx CRC
lypinator	0:bb348c97df44	671	* @rmtoll RXCRCR RXCRC LL_SPI_GetRxCRC
lypinator	0:bb348c97df44	672	* @param SPIx SPI Instance
lypinator	0:bb348c97df44	673	* @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
lypinator	0:bb348c97df44	674	*/
lypinator	0:bb348c97df44	675	__STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx)
lypinator	0:bb348c97df44	676	{
lypinator	0:bb348c97df44	677	return (uint32_t)(READ_REG(SPIx->RXCRCR));
lypinator	0:bb348c97df44	678	}
lypinator	0:bb348c97df44	679
lypinator	0:bb348c97df44	680	/**
lypinator	0:bb348c97df44	681	* @brief Get Tx CRC
lypinator	0:bb348c97df44	682	* @rmtoll TXCRCR TXCRC LL_SPI_GetTxCRC
lypinator	0:bb348c97df44	683	* @param SPIx SPI Instance
lypinator	0:bb348c97df44	684	* @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
lypinator	0:bb348c97df44	685	*/
lypinator	0:bb348c97df44	686	__STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx)
lypinator	0:bb348c97df44	687	{
lypinator	0:bb348c97df44	688	return (uint32_t)(READ_REG(SPIx->TXCRCR));
lypinator	0:bb348c97df44	689	}
lypinator	0:bb348c97df44	690
lypinator	0:bb348c97df44	691	/**
lypinator	0:bb348c97df44	692	* @}
lypinator	0:bb348c97df44	693	*/
lypinator	0:bb348c97df44	694
lypinator	0:bb348c97df44	695	/** @defgroup SPI_LL_EF_NSS_Management Slave Select Pin Management
lypinator	0:bb348c97df44	696	* @{
lypinator	0:bb348c97df44	697	*/
lypinator	0:bb348c97df44	698
lypinator	0:bb348c97df44	699	/**
lypinator	0:bb348c97df44	700	* @brief Set NSS mode
lypinator	0:bb348c97df44	701	* @note LL_SPI_NSS_SOFT Mode is not used in SPI TI mode.
lypinator	0:bb348c97df44	702	* @rmtoll CR1 SSM LL_SPI_SetNSSMode\n
lypinator	0:bb348c97df44	703	* @rmtoll CR2 SSOE LL_SPI_SetNSSMode
lypinator	0:bb348c97df44	704	* @param SPIx SPI Instance
lypinator	0:bb348c97df44	705	* @param NSS This parameter can be one of the following values:
lypinator	0:bb348c97df44	706	* @arg @ref LL_SPI_NSS_SOFT
lypinator	0:bb348c97df44	707	* @arg @ref LL_SPI_NSS_HARD_INPUT
lypinator	0:bb348c97df44	708	* @arg @ref LL_SPI_NSS_HARD_OUTPUT
lypinator	0:bb348c97df44	709	* @retval None
lypinator	0:bb348c97df44	710	*/
lypinator	0:bb348c97df44	711	__STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS)
lypinator	0:bb348c97df44	712	{
lypinator	0:bb348c97df44	713	MODIFY_REG(SPIx->CR1, SPI_CR1_SSM, NSS);
lypinator	0:bb348c97df44	714	MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, ((uint32_t)(NSS >> 16U)));
lypinator	0:bb348c97df44	715	}
lypinator	0:bb348c97df44	716
lypinator	0:bb348c97df44	717	/**
lypinator	0:bb348c97df44	718	* @brief Get NSS mode
lypinator	0:bb348c97df44	719	* @rmtoll CR1 SSM LL_SPI_GetNSSMode\n
lypinator	0:bb348c97df44	720	* @rmtoll CR2 SSOE LL_SPI_GetNSSMode
lypinator	0:bb348c97df44	721	* @param SPIx SPI Instance
lypinator	0:bb348c97df44	722	* @retval Returned value can be one of the following values:
lypinator	0:bb348c97df44	723	* @arg @ref LL_SPI_NSS_SOFT
lypinator	0:bb348c97df44	724	* @arg @ref LL_SPI_NSS_HARD_INPUT
lypinator	0:bb348c97df44	725	* @arg @ref LL_SPI_NSS_HARD_OUTPUT
lypinator	0:bb348c97df44	726	*/
lypinator	0:bb348c97df44	727	__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx)
lypinator	0:bb348c97df44	728	{
lypinator	0:bb348c97df44	729	register uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM));
lypinator	0:bb348c97df44	730	register uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U);
lypinator	0:bb348c97df44	731	return (Ssm \| Ssoe);
lypinator	0:bb348c97df44	732	}
lypinator	0:bb348c97df44	733
lypinator	0:bb348c97df44	734	/**
lypinator	0:bb348c97df44	735	* @}
lypinator	0:bb348c97df44	736	*/
lypinator	0:bb348c97df44	737
lypinator	0:bb348c97df44	738	/** @defgroup SPI_LL_EF_FLAG_Management FLAG Management
lypinator	0:bb348c97df44	739	* @{
lypinator	0:bb348c97df44	740	*/
lypinator	0:bb348c97df44	741
lypinator	0:bb348c97df44	742	/**
lypinator	0:bb348c97df44	743	* @brief Check if Rx buffer is not empty
lypinator	0:bb348c97df44	744	* @rmtoll SR RXNE LL_SPI_IsActiveFlag_RXNE
lypinator	0:bb348c97df44	745	* @param SPIx SPI Instance
lypinator	0:bb348c97df44	746	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	747	*/
lypinator	0:bb348c97df44	748	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
lypinator	0:bb348c97df44	749	{
lypinator	0:bb348c97df44	750	return (READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE));
lypinator	0:bb348c97df44	751	}
lypinator	0:bb348c97df44	752
lypinator	0:bb348c97df44	753	/**
lypinator	0:bb348c97df44	754	* @brief Check if Tx buffer is empty
lypinator	0:bb348c97df44	755	* @rmtoll SR TXE LL_SPI_IsActiveFlag_TXE
lypinator	0:bb348c97df44	756	* @param SPIx SPI Instance
lypinator	0:bb348c97df44	757	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	758	*/
lypinator	0:bb348c97df44	759	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
lypinator	0:bb348c97df44	760	{
lypinator	0:bb348c97df44	761	return (READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE));
lypinator	0:bb348c97df44	762	}
lypinator	0:bb348c97df44	763
lypinator	0:bb348c97df44	764	/**
lypinator	0:bb348c97df44	765	* @brief Get CRC error flag
lypinator	0:bb348c97df44	766	* @rmtoll SR CRCERR LL_SPI_IsActiveFlag_CRCERR
lypinator	0:bb348c97df44	767	* @param SPIx SPI Instance
lypinator	0:bb348c97df44	768	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	769	*/
lypinator	0:bb348c97df44	770	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx)
lypinator	0:bb348c97df44	771	{
lypinator	0:bb348c97df44	772	return (READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR));
lypinator	0:bb348c97df44	773	}
lypinator	0:bb348c97df44	774
lypinator	0:bb348c97df44	775	/**
lypinator	0:bb348c97df44	776	* @brief Get mode fault error flag
lypinator	0:bb348c97df44	777	* @rmtoll SR MODF LL_SPI_IsActiveFlag_MODF
lypinator	0:bb348c97df44	778	* @param SPIx SPI Instance
lypinator	0:bb348c97df44	779	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	780	*/
lypinator	0:bb348c97df44	781	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx)
lypinator	0:bb348c97df44	782	{
lypinator	0:bb348c97df44	783	return (READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF));
lypinator	0:bb348c97df44	784	}
lypinator	0:bb348c97df44	785
lypinator	0:bb348c97df44	786	/**
lypinator	0:bb348c97df44	787	* @brief Get overrun error flag
lypinator	0:bb348c97df44	788	* @rmtoll SR OVR LL_SPI_IsActiveFlag_OVR
lypinator	0:bb348c97df44	789	* @param SPIx SPI Instance
lypinator	0:bb348c97df44	790	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	791	*/
lypinator	0:bb348c97df44	792	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
lypinator	0:bb348c97df44	793	{
lypinator	0:bb348c97df44	794	return (READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR));
lypinator	0:bb348c97df44	795	}
lypinator	0:bb348c97df44	796
lypinator	0:bb348c97df44	797	/**
lypinator	0:bb348c97df44	798	* @brief Get busy flag
lypinator	0:bb348c97df44	799	* @note The BSY flag is cleared under any one of the following conditions:
lypinator	0:bb348c97df44	800	* -When the SPI is correctly disabled
lypinator	0:bb348c97df44	801	* -When a fault is detected in Master mode (MODF bit set to 1)
lypinator	0:bb348c97df44	802	* -In Master mode, when it finishes a data transmission and no new data is ready to be
lypinator	0:bb348c97df44	803	* sent
lypinator	0:bb348c97df44	804	* -In Slave mode, when the BSY flag is set to '0' for at least one SPI clock cycle between
lypinator	0:bb348c97df44	805	* each data transfer.
lypinator	0:bb348c97df44	806	* @rmtoll SR BSY LL_SPI_IsActiveFlag_BSY
lypinator	0:bb348c97df44	807	* @param SPIx SPI Instance
lypinator	0:bb348c97df44	808	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	809	*/
lypinator	0:bb348c97df44	810	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
lypinator	0:bb348c97df44	811	{
lypinator	0:bb348c97df44	812	return (READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY));
lypinator	0:bb348c97df44	813	}
lypinator	0:bb348c97df44	814
lypinator	0:bb348c97df44	815	/**
lypinator	0:bb348c97df44	816	* @brief Get frame format error flag
lypinator	0:bb348c97df44	817	* @rmtoll SR FRE LL_SPI_IsActiveFlag_FRE
lypinator	0:bb348c97df44	818	* @param SPIx SPI Instance
lypinator	0:bb348c97df44	819	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	820	*/
lypinator	0:bb348c97df44	821	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
lypinator	0:bb348c97df44	822	{
lypinator	0:bb348c97df44	823	return (READ_BIT(SPIx->SR, SPI_SR_FRE) == (SPI_SR_FRE));
lypinator	0:bb348c97df44	824	}
lypinator	0:bb348c97df44	825
lypinator	0:bb348c97df44	826	/**
lypinator	0:bb348c97df44	827	* @brief Clear CRC error flag
lypinator	0:bb348c97df44	828	* @rmtoll SR CRCERR LL_SPI_ClearFlag_CRCERR
lypinator	0:bb348c97df44	829	* @param SPIx SPI Instance
lypinator	0:bb348c97df44	830	* @retval None
lypinator	0:bb348c97df44	831	*/
lypinator	0:bb348c97df44	832	__STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx)
lypinator	0:bb348c97df44	833	{
lypinator	0:bb348c97df44	834	CLEAR_BIT(SPIx->SR, SPI_SR_CRCERR);
lypinator	0:bb348c97df44	835	}
lypinator	0:bb348c97df44	836
lypinator	0:bb348c97df44	837	/**
lypinator	0:bb348c97df44	838	* @brief Clear mode fault error flag
lypinator	0:bb348c97df44	839	* @note Clearing this flag is done by a read access to the SPIx_SR
lypinator	0:bb348c97df44	840	* register followed by a write access to the SPIx_CR1 register
lypinator	0:bb348c97df44	841	* @rmtoll SR MODF LL_SPI_ClearFlag_MODF
lypinator	0:bb348c97df44	842	* @param SPIx SPI Instance
lypinator	0:bb348c97df44	843	* @retval None
lypinator	0:bb348c97df44	844	*/
lypinator	0:bb348c97df44	845	__STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx)
lypinator	0:bb348c97df44	846	{
lypinator	0:bb348c97df44	847	__IO uint32_t tmpreg;
lypinator	0:bb348c97df44	848	tmpreg = SPIx->SR;
lypinator	0:bb348c97df44	849	(void) tmpreg;
lypinator	0:bb348c97df44	850	tmpreg = CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
lypinator	0:bb348c97df44	851	(void) tmpreg;
lypinator	0:bb348c97df44	852	}
lypinator	0:bb348c97df44	853
lypinator	0:bb348c97df44	854	/**
lypinator	0:bb348c97df44	855	* @brief Clear overrun error flag
lypinator	0:bb348c97df44	856	* @note Clearing this flag is done by a read access to the SPIx_DR
lypinator	0:bb348c97df44	857	* register followed by a read access to the SPIx_SR register
lypinator	0:bb348c97df44	858	* @rmtoll SR OVR LL_SPI_ClearFlag_OVR
lypinator	0:bb348c97df44	859	* @param SPIx SPI Instance
lypinator	0:bb348c97df44	860	* @retval None
lypinator	0:bb348c97df44	861	*/
lypinator	0:bb348c97df44	862	__STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx)
lypinator	0:bb348c97df44	863	{
lypinator	0:bb348c97df44	864	__IO uint32_t tmpreg;
lypinator	0:bb348c97df44	865	tmpreg = SPIx->DR;
lypinator	0:bb348c97df44	866	(void) tmpreg;
lypinator	0:bb348c97df44	867	tmpreg = SPIx->SR;
lypinator	0:bb348c97df44	868	(void) tmpreg;
lypinator	0:bb348c97df44	869	}
lypinator	0:bb348c97df44	870
lypinator	0:bb348c97df44	871	/**
lypinator	0:bb348c97df44	872	* @brief Clear frame format error flag
lypinator	0:bb348c97df44	873	* @note Clearing this flag is done by reading SPIx_SR register
lypinator	0:bb348c97df44	874	* @rmtoll SR FRE LL_SPI_ClearFlag_FRE
lypinator	0:bb348c97df44	875	* @param SPIx SPI Instance
lypinator	0:bb348c97df44	876	* @retval None
lypinator	0:bb348c97df44	877	*/
lypinator	0:bb348c97df44	878	__STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx)
lypinator	0:bb348c97df44	879	{
lypinator	0:bb348c97df44	880	__IO uint32_t tmpreg;
lypinator	0:bb348c97df44	881	tmpreg = SPIx->SR;
lypinator	0:bb348c97df44	882	(void) tmpreg;
lypinator	0:bb348c97df44	883	}
lypinator	0:bb348c97df44	884
lypinator	0:bb348c97df44	885	/**
lypinator	0:bb348c97df44	886	* @}
lypinator	0:bb348c97df44	887	*/
lypinator	0:bb348c97df44	888
lypinator	0:bb348c97df44	889	/** @defgroup SPI_LL_EF_IT_Management Interrupt Management
lypinator	0:bb348c97df44	890	* @{
lypinator	0:bb348c97df44	891	*/
lypinator	0:bb348c97df44	892
lypinator	0:bb348c97df44	893	/**
lypinator	0:bb348c97df44	894	* @brief Enable error interrupt
lypinator	0:bb348c97df44	895	* @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
lypinator	0:bb348c97df44	896	* @rmtoll CR2 ERRIE LL_SPI_EnableIT_ERR
lypinator	0:bb348c97df44	897	* @param SPIx SPI Instance
lypinator	0:bb348c97df44	898	* @retval None
lypinator	0:bb348c97df44	899	*/
lypinator	0:bb348c97df44	900	__STATIC_INLINE void LL_SPI_EnableIT_ERR(SPI_TypeDef *SPIx)
lypinator	0:bb348c97df44	901	{
lypinator	0:bb348c97df44	902	SET_BIT(SPIx->CR2, SPI_CR2_ERRIE);
lypinator	0:bb348c97df44	903	}
lypinator	0:bb348c97df44	904
lypinator	0:bb348c97df44	905	/**
lypinator	0:bb348c97df44	906	* @brief Enable Rx buffer not empty interrupt
lypinator	0:bb348c97df44	907	* @rmtoll CR2 RXNEIE LL_SPI_EnableIT_RXNE
lypinator	0:bb348c97df44	908	* @param SPIx SPI Instance
lypinator	0:bb348c97df44	909	* @retval None
lypinator	0:bb348c97df44	910	*/
lypinator	0:bb348c97df44	911	__STATIC_INLINE void LL_SPI_EnableIT_RXNE(SPI_TypeDef *SPIx)
lypinator	0:bb348c97df44	912	{
lypinator	0:bb348c97df44	913	SET_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
lypinator	0:bb348c97df44	914	}
lypinator	0:bb348c97df44	915
lypinator	0:bb348c97df44	916	/**
lypinator	0:bb348c97df44	917	* @brief Enable Tx buffer empty interrupt
lypinator	0:bb348c97df44	918	* @rmtoll CR2 TXEIE LL_SPI_EnableIT_TXE
lypinator	0:bb348c97df44	919	* @param SPIx SPI Instance
lypinator	0:bb348c97df44	920	* @retval None
lypinator	0:bb348c97df44	921	*/
lypinator	0:bb348c97df44	922	__STATIC_INLINE void LL_SPI_EnableIT_TXE(SPI_TypeDef *SPIx)
lypinator	0:bb348c97df44	923	{
lypinator	0:bb348c97df44	924	SET_BIT(SPIx->CR2, SPI_CR2_TXEIE);
lypinator	0:bb348c97df44	925	}
lypinator	0:bb348c97df44	926
lypinator	0:bb348c97df44	927	/**
lypinator	0:bb348c97df44	928	* @brief Disable error interrupt
lypinator	0:bb348c97df44	929	* @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
lypinator	0:bb348c97df44	930	* @rmtoll CR2 ERRIE LL_SPI_DisableIT_ERR
lypinator	0:bb348c97df44	931	* @param SPIx SPI Instance
lypinator	0:bb348c97df44	932	* @retval None
lypinator	0:bb348c97df44	933	*/
lypinator	0:bb348c97df44	934	__STATIC_INLINE void LL_SPI_DisableIT_ERR(SPI_TypeDef *SPIx)
lypinator	0:bb348c97df44	935	{
lypinator	0:bb348c97df44	936	CLEAR_BIT(SPIx->CR2, SPI_CR2_ERRIE);
lypinator	0:bb348c97df44	937	}
lypinator	0:bb348c97df44	938
lypinator	0:bb348c97df44	939	/**
lypinator	0:bb348c97df44	940	* @brief Disable Rx buffer not empty interrupt
lypinator	0:bb348c97df44	941	* @rmtoll CR2 RXNEIE LL_SPI_DisableIT_RXNE
lypinator	0:bb348c97df44	942	* @param SPIx SPI Instance
lypinator	0:bb348c97df44	943	* @retval None
lypinator	0:bb348c97df44	944	*/
lypinator	0:bb348c97df44	945	__STATIC_INLINE void LL_SPI_DisableIT_RXNE(SPI_TypeDef *SPIx)
lypinator	0:bb348c97df44	946	{
lypinator	0:bb348c97df44	947	CLEAR_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
lypinator	0:bb348c97df44	948	}
lypinator	0:bb348c97df44	949
lypinator	0:bb348c97df44	950	/**
lypinator	0:bb348c97df44	951	* @brief Disable Tx buffer empty interrupt
lypinator	0:bb348c97df44	952	* @rmtoll CR2 TXEIE LL_SPI_DisableIT_TXE
lypinator	0:bb348c97df44	953	* @param SPIx SPI Instance
lypinator	0:bb348c97df44	954	* @retval None
lypinator	0:bb348c97df44	955	*/
lypinator	0:bb348c97df44	956	__STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx)
lypinator	0:bb348c97df44	957	{
lypinator	0:bb348c97df44	958	CLEAR_BIT(SPIx->CR2, SPI_CR2_TXEIE);
lypinator	0:bb348c97df44	959	}
lypinator	0:bb348c97df44	960
lypinator	0:bb348c97df44	961	/**
lypinator	0:bb348c97df44	962	* @brief Check if error interrupt is enabled
lypinator	0:bb348c97df44	963	* @rmtoll CR2 ERRIE LL_SPI_IsEnabledIT_ERR
lypinator	0:bb348c97df44	964	* @param SPIx SPI Instance
lypinator	0:bb348c97df44	965	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	966	*/
lypinator	0:bb348c97df44	967	__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
lypinator	0:bb348c97df44	968	{
lypinator	0:bb348c97df44	969	return (READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE));
lypinator	0:bb348c97df44	970	}
lypinator	0:bb348c97df44	971
lypinator	0:bb348c97df44	972	/**
lypinator	0:bb348c97df44	973	* @brief Check if Rx buffer not empty interrupt is enabled
lypinator	0:bb348c97df44	974	* @rmtoll CR2 RXNEIE LL_SPI_IsEnabledIT_RXNE
lypinator	0:bb348c97df44	975	* @param SPIx SPI Instance
lypinator	0:bb348c97df44	976	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	977	*/
lypinator	0:bb348c97df44	978	__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
lypinator	0:bb348c97df44	979	{
lypinator	0:bb348c97df44	980	return (READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE));
lypinator	0:bb348c97df44	981	}
lypinator	0:bb348c97df44	982
lypinator	0:bb348c97df44	983	/**
lypinator	0:bb348c97df44	984	* @brief Check if Tx buffer empty interrupt
lypinator	0:bb348c97df44	985	* @rmtoll CR2 TXEIE LL_SPI_IsEnabledIT_TXE
lypinator	0:bb348c97df44	986	* @param SPIx SPI Instance
lypinator	0:bb348c97df44	987	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	988	*/
lypinator	0:bb348c97df44	989	__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
lypinator	0:bb348c97df44	990	{
lypinator	0:bb348c97df44	991	return (READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE));
lypinator	0:bb348c97df44	992	}
lypinator	0:bb348c97df44	993
lypinator	0:bb348c97df44	994	/**
lypinator	0:bb348c97df44	995	* @}
lypinator	0:bb348c97df44	996	*/
lypinator	0:bb348c97df44	997
lypinator	0:bb348c97df44	998	/** @defgroup SPI_LL_EF_DMA_Management DMA Management
lypinator	0:bb348c97df44	999	* @{
lypinator	0:bb348c97df44	1000	*/
lypinator	0:bb348c97df44	1001
lypinator	0:bb348c97df44	1002	/**
lypinator	0:bb348c97df44	1003	* @brief Enable DMA Rx
lypinator	0:bb348c97df44	1004	* @rmtoll CR2 RXDMAEN LL_SPI_EnableDMAReq_RX
lypinator	0:bb348c97df44	1005	* @param SPIx SPI Instance
lypinator	0:bb348c97df44	1006	* @retval None
lypinator	0:bb348c97df44	1007	*/
lypinator	0:bb348c97df44	1008	__STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx)
lypinator	0:bb348c97df44	1009	{
lypinator	0:bb348c97df44	1010	SET_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
lypinator	0:bb348c97df44	1011	}
lypinator	0:bb348c97df44	1012
lypinator	0:bb348c97df44	1013	/**
lypinator	0:bb348c97df44	1014	* @brief Disable DMA Rx
lypinator	0:bb348c97df44	1015	* @rmtoll CR2 RXDMAEN LL_SPI_DisableDMAReq_RX
lypinator	0:bb348c97df44	1016	* @param SPIx SPI Instance
lypinator	0:bb348c97df44	1017	* @retval None
lypinator	0:bb348c97df44	1018	*/
lypinator	0:bb348c97df44	1019	__STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx)
lypinator	0:bb348c97df44	1020	{
lypinator	0:bb348c97df44	1021	CLEAR_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
lypinator	0:bb348c97df44	1022	}
lypinator	0:bb348c97df44	1023
lypinator	0:bb348c97df44	1024	/**
lypinator	0:bb348c97df44	1025	* @brief Check if DMA Rx is enabled
lypinator	0:bb348c97df44	1026	* @rmtoll CR2 RXDMAEN LL_SPI_IsEnabledDMAReq_RX
lypinator	0:bb348c97df44	1027	* @param SPIx SPI Instance
lypinator	0:bb348c97df44	1028	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	1029	*/
lypinator	0:bb348c97df44	1030	__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
lypinator	0:bb348c97df44	1031	{
lypinator	0:bb348c97df44	1032	return (READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN));
lypinator	0:bb348c97df44	1033	}
lypinator	0:bb348c97df44	1034
lypinator	0:bb348c97df44	1035	/**
lypinator	0:bb348c97df44	1036	* @brief Enable DMA Tx
lypinator	0:bb348c97df44	1037	* @rmtoll CR2 TXDMAEN LL_SPI_EnableDMAReq_TX
lypinator	0:bb348c97df44	1038	* @param SPIx SPI Instance
lypinator	0:bb348c97df44	1039	* @retval None
lypinator	0:bb348c97df44	1040	*/
lypinator	0:bb348c97df44	1041	__STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx)
lypinator	0:bb348c97df44	1042	{
lypinator	0:bb348c97df44	1043	SET_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
lypinator	0:bb348c97df44	1044	}
lypinator	0:bb348c97df44	1045
lypinator	0:bb348c97df44	1046	/**
lypinator	0:bb348c97df44	1047	* @brief Disable DMA Tx
lypinator	0:bb348c97df44	1048	* @rmtoll CR2 TXDMAEN LL_SPI_DisableDMAReq_TX
lypinator	0:bb348c97df44	1049	* @param SPIx SPI Instance
lypinator	0:bb348c97df44	1050	* @retval None
lypinator	0:bb348c97df44	1051	*/
lypinator	0:bb348c97df44	1052	__STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx)
lypinator	0:bb348c97df44	1053	{
lypinator	0:bb348c97df44	1054	CLEAR_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
lypinator	0:bb348c97df44	1055	}
lypinator	0:bb348c97df44	1056
lypinator	0:bb348c97df44	1057	/**
lypinator	0:bb348c97df44	1058	* @brief Check if DMA Tx is enabled
lypinator	0:bb348c97df44	1059	* @rmtoll CR2 TXDMAEN LL_SPI_IsEnabledDMAReq_TX
lypinator	0:bb348c97df44	1060	* @param SPIx SPI Instance
lypinator	0:bb348c97df44	1061	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	1062	*/
lypinator	0:bb348c97df44	1063	__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
lypinator	0:bb348c97df44	1064	{
lypinator	0:bb348c97df44	1065	return (READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN));
lypinator	0:bb348c97df44	1066	}
lypinator	0:bb348c97df44	1067
lypinator	0:bb348c97df44	1068	/**
lypinator	0:bb348c97df44	1069	* @brief Get the data register address used for DMA transfer
lypinator	0:bb348c97df44	1070	* @rmtoll DR DR LL_SPI_DMA_GetRegAddr
lypinator	0:bb348c97df44	1071	* @param SPIx SPI Instance
lypinator	0:bb348c97df44	1072	* @retval Address of data register
lypinator	0:bb348c97df44	1073	*/
lypinator	0:bb348c97df44	1074	__STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx)
lypinator	0:bb348c97df44	1075	{
lypinator	0:bb348c97df44	1076	return (uint32_t) & (SPIx->DR);
lypinator	0:bb348c97df44	1077	}
lypinator	0:bb348c97df44	1078
lypinator	0:bb348c97df44	1079	/**
lypinator	0:bb348c97df44	1080	* @}
lypinator	0:bb348c97df44	1081	*/
lypinator	0:bb348c97df44	1082
lypinator	0:bb348c97df44	1083	/** @defgroup SPI_LL_EF_DATA_Management DATA Management
lypinator	0:bb348c97df44	1084	* @{
lypinator	0:bb348c97df44	1085	*/
lypinator	0:bb348c97df44	1086
lypinator	0:bb348c97df44	1087	/**
lypinator	0:bb348c97df44	1088	* @brief Read 8-Bits in the data register
lypinator	0:bb348c97df44	1089	* @rmtoll DR DR LL_SPI_ReceiveData8
lypinator	0:bb348c97df44	1090	* @param SPIx SPI Instance
lypinator	0:bb348c97df44	1091	* @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF
lypinator	0:bb348c97df44	1092	*/
lypinator	0:bb348c97df44	1093	__STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx)
lypinator	0:bb348c97df44	1094	{
lypinator	0:bb348c97df44	1095	return (uint8_t)(READ_REG(SPIx->DR));
lypinator	0:bb348c97df44	1096	}
lypinator	0:bb348c97df44	1097
lypinator	0:bb348c97df44	1098	/**
lypinator	0:bb348c97df44	1099	* @brief Read 16-Bits in the data register
lypinator	0:bb348c97df44	1100	* @rmtoll DR DR LL_SPI_ReceiveData16
lypinator	0:bb348c97df44	1101	* @param SPIx SPI Instance
lypinator	0:bb348c97df44	1102	* @retval RxData Value between Min_Data=0x00 and Max_Data=0xFFFF
lypinator	0:bb348c97df44	1103	*/
lypinator	0:bb348c97df44	1104	__STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx)
lypinator	0:bb348c97df44	1105	{
lypinator	0:bb348c97df44	1106	return (uint16_t)(READ_REG(SPIx->DR));
lypinator	0:bb348c97df44	1107	}
lypinator	0:bb348c97df44	1108
lypinator	0:bb348c97df44	1109	/**
lypinator	0:bb348c97df44	1110	* @brief Write 8-Bits in the data register
lypinator	0:bb348c97df44	1111	* @rmtoll DR DR LL_SPI_TransmitData8
lypinator	0:bb348c97df44	1112	* @param SPIx SPI Instance
lypinator	0:bb348c97df44	1113	* @param TxData Value between Min_Data=0x00 and Max_Data=0xFF
lypinator	0:bb348c97df44	1114	* @retval None
lypinator	0:bb348c97df44	1115	*/
lypinator	0:bb348c97df44	1116	__STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData)
lypinator	0:bb348c97df44	1117	{
lypinator	0:bb348c97df44	1118	SPIx->DR = TxData;
lypinator	0:bb348c97df44	1119	}
lypinator	0:bb348c97df44	1120
lypinator	0:bb348c97df44	1121	/**
lypinator	0:bb348c97df44	1122	* @brief Write 16-Bits in the data register
lypinator	0:bb348c97df44	1123	* @rmtoll DR DR LL_SPI_TransmitData16
lypinator	0:bb348c97df44	1124	* @param SPIx SPI Instance
lypinator	0:bb348c97df44	1125	* @param TxData Value between Min_Data=0x00 and Max_Data=0xFFFF
lypinator	0:bb348c97df44	1126	* @retval None
lypinator	0:bb348c97df44	1127	*/
lypinator	0:bb348c97df44	1128	__STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
lypinator	0:bb348c97df44	1129	{
lypinator	0:bb348c97df44	1130	SPIx->DR = TxData;
lypinator	0:bb348c97df44	1131	}
lypinator	0:bb348c97df44	1132
lypinator	0:bb348c97df44	1133	/**
lypinator	0:bb348c97df44	1134	* @}
lypinator	0:bb348c97df44	1135	*/
lypinator	0:bb348c97df44	1136	#if defined(USE_FULL_LL_DRIVER)
lypinator	0:bb348c97df44	1137	/** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions
lypinator	0:bb348c97df44	1138	* @{
lypinator	0:bb348c97df44	1139	*/
lypinator	0:bb348c97df44	1140
lypinator	0:bb348c97df44	1141	ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx);
lypinator	0:bb348c97df44	1142	ErrorStatus LL_SPI_Init(SPI_TypeDef SPIx, LL_SPI_InitTypeDef SPI_InitStruct);
lypinator	0:bb348c97df44	1143	void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct);
lypinator	0:bb348c97df44	1144
lypinator	0:bb348c97df44	1145	/**
lypinator	0:bb348c97df44	1146	* @}
lypinator	0:bb348c97df44	1147	*/
lypinator	0:bb348c97df44	1148	#endif /* USE_FULL_LL_DRIVER */
lypinator	0:bb348c97df44	1149	/**
lypinator	0:bb348c97df44	1150	* @}
lypinator	0:bb348c97df44	1151	*/
lypinator	0:bb348c97df44	1152
lypinator	0:bb348c97df44	1153	/**
lypinator	0:bb348c97df44	1154	* @}
lypinator	0:bb348c97df44	1155	*/
lypinator	0:bb348c97df44	1156
lypinator	0:bb348c97df44	1157	/** @defgroup I2S_LL I2S
lypinator	0:bb348c97df44	1158	* @{
lypinator	0:bb348c97df44	1159	*/
lypinator	0:bb348c97df44	1160
lypinator	0:bb348c97df44	1161	/* Private variables ---------------------------------------------------------*/
lypinator	0:bb348c97df44	1162	/* Private constants ---------------------------------------------------------*/
lypinator	0:bb348c97df44	1163	/* Private macros ------------------------------------------------------------*/
lypinator	0:bb348c97df44	1164
lypinator	0:bb348c97df44	1165	/* Exported types ------------------------------------------------------------*/
lypinator	0:bb348c97df44	1166	#if defined(USE_FULL_LL_DRIVER)
lypinator	0:bb348c97df44	1167	/** @defgroup I2S_LL_ES_INIT I2S Exported Init structure
lypinator	0:bb348c97df44	1168	* @{
lypinator	0:bb348c97df44	1169	*/
lypinator	0:bb348c97df44	1170
lypinator	0:bb348c97df44	1171	/**
lypinator	0:bb348c97df44	1172	* @brief I2S Init structure definition
lypinator	0:bb348c97df44	1173	*/
lypinator	0:bb348c97df44	1174
lypinator	0:bb348c97df44	1175	typedef struct
lypinator	0:bb348c97df44	1176	{
lypinator	0:bb348c97df44	1177	uint32_t Mode; /*!< Specifies the I2S operating mode.
lypinator	0:bb348c97df44	1178	This parameter can be a value of @ref I2S_LL_EC_MODE
lypinator	0:bb348c97df44	1179
lypinator	0:bb348c97df44	1180	This feature can be modified afterwards using unitary function @ref LL_I2S_SetTransferMode().*/
lypinator	0:bb348c97df44	1181
lypinator	0:bb348c97df44	1182	uint32_t Standard; /*!< Specifies the standard used for the I2S communication.
lypinator	0:bb348c97df44	1183	This parameter can be a value of @ref I2S_LL_EC_STANDARD
lypinator	0:bb348c97df44	1184
lypinator	0:bb348c97df44	1185	This feature can be modified afterwards using unitary function @ref LL_I2S_SetStandard().*/
lypinator	0:bb348c97df44	1186
lypinator	0:bb348c97df44	1187
lypinator	0:bb348c97df44	1188	uint32_t DataFormat; /*!< Specifies the data format for the I2S communication.
lypinator	0:bb348c97df44	1189	This parameter can be a value of @ref I2S_LL_EC_DATA_FORMAT
lypinator	0:bb348c97df44	1190
lypinator	0:bb348c97df44	1191	This feature can be modified afterwards using unitary function @ref LL_I2S_SetDataFormat().*/
lypinator	0:bb348c97df44	1192
lypinator	0:bb348c97df44	1193
lypinator	0:bb348c97df44	1194	uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
lypinator	0:bb348c97df44	1195	This parameter can be a value of @ref I2S_LL_EC_MCLK_OUTPUT
lypinator	0:bb348c97df44	1196
lypinator	0:bb348c97df44	1197	This feature can be modified afterwards using unitary functions @ref LL_I2S_EnableMasterClock() or @ref LL_I2S_DisableMasterClock.*/
lypinator	0:bb348c97df44	1198
lypinator	0:bb348c97df44	1199
lypinator	0:bb348c97df44	1200	uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
lypinator	0:bb348c97df44	1201	This parameter can be a value of @ref I2S_LL_EC_AUDIO_FREQ
lypinator	0:bb348c97df44	1202
lypinator	0:bb348c97df44	1203	Audio Frequency can be modified afterwards using Reference manual formulas to calculate Prescaler Linear, Parity
lypinator	0:bb348c97df44	1204	and unitary functions @ref LL_I2S_SetPrescalerLinear() and @ref LL_I2S_SetPrescalerParity() to set it.*/
lypinator	0:bb348c97df44	1205
lypinator	0:bb348c97df44	1206
lypinator	0:bb348c97df44	1207	uint32_t ClockPolarity; /*!< Specifies the idle state of the I2S clock.
lypinator	0:bb348c97df44	1208	This parameter can be a value of @ref I2S_LL_EC_POLARITY
lypinator	0:bb348c97df44	1209
lypinator	0:bb348c97df44	1210	This feature can be modified afterwards using unitary function @ref LL_I2S_SetClockPolarity().*/
lypinator	0:bb348c97df44	1211
lypinator	0:bb348c97df44	1212	} LL_I2S_InitTypeDef;
lypinator	0:bb348c97df44	1213
lypinator	0:bb348c97df44	1214	/**
lypinator	0:bb348c97df44	1215	* @}
lypinator	0:bb348c97df44	1216	*/
lypinator	0:bb348c97df44	1217	#endif /USE_FULL_LL_DRIVER/
lypinator	0:bb348c97df44	1218
lypinator	0:bb348c97df44	1219	/* Exported constants --------------------------------------------------------*/
lypinator	0:bb348c97df44	1220	/** @defgroup I2S_LL_Exported_Constants I2S Exported Constants
lypinator	0:bb348c97df44	1221	* @{
lypinator	0:bb348c97df44	1222	*/
lypinator	0:bb348c97df44	1223
lypinator	0:bb348c97df44	1224	/** @defgroup I2S_LL_EC_GET_FLAG Get Flags Defines
lypinator	0:bb348c97df44	1225	* @brief Flags defines which can be used with LL_I2S_ReadReg function
lypinator	0:bb348c97df44	1226	* @{
lypinator	0:bb348c97df44	1227	*/
lypinator	0:bb348c97df44	1228	#define LL_I2S_SR_RXNE LL_SPI_SR_RXNE /!< Rx buffer not empty flag /
lypinator	0:bb348c97df44	1229	#define LL_I2S_SR_TXE LL_SPI_SR_TXE /!< Tx buffer empty flag /
lypinator	0:bb348c97df44	1230	#define LL_I2S_SR_BSY LL_SPI_SR_BSY /!< Busy flag /
lypinator	0:bb348c97df44	1231	#define LL_I2S_SR_UDR SPI_SR_UDR /!< Underrun flag /
lypinator	0:bb348c97df44	1232	#define LL_I2S_SR_OVR LL_SPI_SR_OVR /!< Overrun flag /
lypinator	0:bb348c97df44	1233	#define LL_I2S_SR_FRE LL_SPI_SR_FRE /!< TI mode frame format error flag /
lypinator	0:bb348c97df44	1234	/**
lypinator	0:bb348c97df44	1235	* @}
lypinator	0:bb348c97df44	1236	*/
lypinator	0:bb348c97df44	1237
lypinator	0:bb348c97df44	1238	/** @defgroup SPI_LL_EC_IT IT Defines
lypinator	0:bb348c97df44	1239	* @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
lypinator	0:bb348c97df44	1240	* @{
lypinator	0:bb348c97df44	1241	*/
lypinator	0:bb348c97df44	1242	#define LL_I2S_CR2_RXNEIE LL_SPI_CR2_RXNEIE /!< Rx buffer not empty interrupt enable /
lypinator	0:bb348c97df44	1243	#define LL_I2S_CR2_TXEIE LL_SPI_CR2_TXEIE /!< Tx buffer empty interrupt enable /
lypinator	0:bb348c97df44	1244	#define LL_I2S_CR2_ERRIE LL_SPI_CR2_ERRIE /!< Error interrupt enable /
lypinator	0:bb348c97df44	1245	/**
lypinator	0:bb348c97df44	1246	* @}
lypinator	0:bb348c97df44	1247	*/
lypinator	0:bb348c97df44	1248
lypinator	0:bb348c97df44	1249	/** @defgroup I2S_LL_EC_DATA_FORMAT Data format
lypinator	0:bb348c97df44	1250	* @{
lypinator	0:bb348c97df44	1251	*/
lypinator	0:bb348c97df44	1252	#define LL_I2S_DATAFORMAT_16B 0x00000000U /!< Data length 16 bits, Channel lenght 16bit /
lypinator	0:bb348c97df44	1253	#define LL_I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN) /!< Data length 16 bits, Channel lenght 32bit /
lypinator	0:bb348c97df44	1254	#define LL_I2S_DATAFORMAT_24B (SPI_I2SCFGR_CHLEN \| SPI_I2SCFGR_DATLEN_0) /!< Data length 24 bits, Channel lenght 32bit /
lypinator	0:bb348c97df44	1255	#define LL_I2S_DATAFORMAT_32B (SPI_I2SCFGR_CHLEN \| SPI_I2SCFGR_DATLEN_1) /!< Data length 16 bits, Channel lenght 32bit /
lypinator	0:bb348c97df44	1256	/**
lypinator	0:bb348c97df44	1257	* @}
lypinator	0:bb348c97df44	1258	*/
lypinator	0:bb348c97df44	1259
lypinator	0:bb348c97df44	1260	/** @defgroup I2S_LL_EC_POLARITY Clock Polarity
lypinator	0:bb348c97df44	1261	* @{
lypinator	0:bb348c97df44	1262	*/
lypinator	0:bb348c97df44	1263	#define LL_I2S_POLARITY_LOW 0x00000000U /!< Clock steady state is low level /
lypinator	0:bb348c97df44	1264	#define LL_I2S_POLARITY_HIGH (SPI_I2SCFGR_CKPOL) /!< Clock steady state is high level /
lypinator	0:bb348c97df44	1265	/**
lypinator	0:bb348c97df44	1266	* @}
lypinator	0:bb348c97df44	1267	*/
lypinator	0:bb348c97df44	1268
lypinator	0:bb348c97df44	1269	/** @defgroup I2S_LL_EC_STANDARD I2s Standard
lypinator	0:bb348c97df44	1270	* @{
lypinator	0:bb348c97df44	1271	*/
lypinator	0:bb348c97df44	1272	#define LL_I2S_STANDARD_PHILIPS 0x00000000U /!< I2S standard philips /
lypinator	0:bb348c97df44	1273	#define LL_I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0) /!< MSB justified standard (left justified) /
lypinator	0:bb348c97df44	1274	#define LL_I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1) /!< LSB justified standard (right justified) /
lypinator	0:bb348c97df44	1275	#define LL_I2S_STANDARD_PCM_SHORT (SPI_I2SCFGR_I2SSTD_0 \| SPI_I2SCFGR_I2SSTD_1) /!< PCM standard, short frame synchronization /
lypinator	0:bb348c97df44	1276	#define LL_I2S_STANDARD_PCM_LONG (SPI_I2SCFGR_I2SSTD_0 \| SPI_I2SCFGR_I2SSTD_1 \| SPI_I2SCFGR_PCMSYNC) /!< PCM standard, long frame synchronization /
lypinator	0:bb348c97df44	1277	/**
lypinator	0:bb348c97df44	1278	* @}
lypinator	0:bb348c97df44	1279	*/
lypinator	0:bb348c97df44	1280
lypinator	0:bb348c97df44	1281	/** @defgroup I2S_LL_EC_MODE Operation Mode
lypinator	0:bb348c97df44	1282	* @{
lypinator	0:bb348c97df44	1283	*/
lypinator	0:bb348c97df44	1284	#define LL_I2S_MODE_SLAVE_TX 0x00000000U /!< Slave Tx configuration /
lypinator	0:bb348c97df44	1285	#define LL_I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0) /!< Slave Rx configuration /
lypinator	0:bb348c97df44	1286	#define LL_I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1) /!< Master Tx configuration /
lypinator	0:bb348c97df44	1287	#define LL_I2S_MODE_MASTER_RX (SPI_I2SCFGR_I2SCFG_0 \| SPI_I2SCFGR_I2SCFG_1) /!< Master Rx configuration /
lypinator	0:bb348c97df44	1288	/**
lypinator	0:bb348c97df44	1289	* @}
lypinator	0:bb348c97df44	1290	*/
lypinator	0:bb348c97df44	1291
lypinator	0:bb348c97df44	1292	/** @defgroup I2S_LL_EC_PRESCALER_FACTOR Prescaler Factor
lypinator	0:bb348c97df44	1293	* @{
lypinator	0:bb348c97df44	1294	*/
lypinator	0:bb348c97df44	1295	#define LL_I2S_PRESCALER_PARITY_EVEN 0x00000000U /!< Odd factor: Real divider value is = I2SDIV 2 */
lypinator	0:bb348c97df44	1296	#define LL_I2S_PRESCALER_PARITY_ODD (SPI_I2SPR_ODD >> 8U) /!< Odd factor: Real divider value is = (I2SDIV 2)+1 */
lypinator	0:bb348c97df44	1297	/**
lypinator	0:bb348c97df44	1298	* @}
lypinator	0:bb348c97df44	1299	*/
lypinator	0:bb348c97df44	1300
lypinator	0:bb348c97df44	1301	#if defined(USE_FULL_LL_DRIVER)
lypinator	0:bb348c97df44	1302
lypinator	0:bb348c97df44	1303	/** @defgroup I2S_LL_EC_MCLK_OUTPUT MCLK Output
lypinator	0:bb348c97df44	1304	* @{
lypinator	0:bb348c97df44	1305	*/
lypinator	0:bb348c97df44	1306	#define LL_I2S_MCLK_OUTPUT_DISABLE 0x00000000U /!< Master clock output is disabled /
lypinator	0:bb348c97df44	1307	#define LL_I2S_MCLK_OUTPUT_ENABLE (SPI_I2SPR_MCKOE) /!< Master clock output is enabled /
lypinator	0:bb348c97df44	1308	/**
lypinator	0:bb348c97df44	1309	* @}
lypinator	0:bb348c97df44	1310	*/
lypinator	0:bb348c97df44	1311
lypinator	0:bb348c97df44	1312	/** @defgroup I2S_LL_EC_AUDIO_FREQ Audio Frequency
lypinator	0:bb348c97df44	1313	* @{
lypinator	0:bb348c97df44	1314	*/
lypinator	0:bb348c97df44	1315
lypinator	0:bb348c97df44	1316	#define LL_I2S_AUDIOFREQ_192K 192000U /!< Audio Frequency configuration 192000 Hz /
lypinator	0:bb348c97df44	1317	#define LL_I2S_AUDIOFREQ_96K 96000U /!< Audio Frequency configuration 96000 Hz /
lypinator	0:bb348c97df44	1318	#define LL_I2S_AUDIOFREQ_48K 48000U /!< Audio Frequency configuration 48000 Hz /
lypinator	0:bb348c97df44	1319	#define LL_I2S_AUDIOFREQ_44K 44100U /!< Audio Frequency configuration 44100 Hz /
lypinator	0:bb348c97df44	1320	#define LL_I2S_AUDIOFREQ_32K 32000U /!< Audio Frequency configuration 32000 Hz /
lypinator	0:bb348c97df44	1321	#define LL_I2S_AUDIOFREQ_22K 22050U /!< Audio Frequency configuration 22050 Hz /
lypinator	0:bb348c97df44	1322	#define LL_I2S_AUDIOFREQ_16K 16000U /!< Audio Frequency configuration 16000 Hz /
lypinator	0:bb348c97df44	1323	#define LL_I2S_AUDIOFREQ_11K 11025U /!< Audio Frequency configuration 11025 Hz /
lypinator	0:bb348c97df44	1324	#define LL_I2S_AUDIOFREQ_8K 8000U /!< Audio Frequency configuration 8000 Hz /
lypinator	0:bb348c97df44	1325	#define LL_I2S_AUDIOFREQ_DEFAULT 2U /!< Audio Freq not specified. Register I2SDIV = 2 /
lypinator	0:bb348c97df44	1326	/**
lypinator	0:bb348c97df44	1327	* @}
lypinator	0:bb348c97df44	1328	*/
lypinator	0:bb348c97df44	1329	#endif /* USE_FULL_LL_DRIVER */
lypinator	0:bb348c97df44	1330
lypinator	0:bb348c97df44	1331	/**
lypinator	0:bb348c97df44	1332	* @}
lypinator	0:bb348c97df44	1333	*/
lypinator	0:bb348c97df44	1334
lypinator	0:bb348c97df44	1335	/* Exported macro ------------------------------------------------------------*/
lypinator	0:bb348c97df44	1336	/** @defgroup I2S_LL_Exported_Macros I2S Exported Macros
lypinator	0:bb348c97df44	1337	* @{
lypinator	0:bb348c97df44	1338	*/
lypinator	0:bb348c97df44	1339
lypinator	0:bb348c97df44	1340	/** @defgroup I2S_LL_EM_WRITE_READ Common Write and read registers Macros
lypinator	0:bb348c97df44	1341	* @{
lypinator	0:bb348c97df44	1342	*/
lypinator	0:bb348c97df44	1343
lypinator	0:bb348c97df44	1344	/**
lypinator	0:bb348c97df44	1345	* @brief Write a value in I2S register
lypinator	0:bb348c97df44	1346	* @param __INSTANCE__ I2S Instance
lypinator	0:bb348c97df44	1347	* @param __REG__ Register to be written
lypinator	0:bb348c97df44	1348	* @param __VALUE__ Value to be written in the register
lypinator	0:bb348c97df44	1349	* @retval None
lypinator	0:bb348c97df44	1350	*/
lypinator	0:bb348c97df44	1351	#define LL_I2S_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
lypinator	0:bb348c97df44	1352
lypinator	0:bb348c97df44	1353	/**
lypinator	0:bb348c97df44	1354	* @brief Read a value in I2S register
lypinator	0:bb348c97df44	1355	* @param __INSTANCE__ I2S Instance
lypinator	0:bb348c97df44	1356	* @param __REG__ Register to be read
lypinator	0:bb348c97df44	1357	* @retval Register value
lypinator	0:bb348c97df44	1358	*/
lypinator	0:bb348c97df44	1359	#define LL_I2S_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
lypinator	0:bb348c97df44	1360	/**
lypinator	0:bb348c97df44	1361	* @}
lypinator	0:bb348c97df44	1362	*/
lypinator	0:bb348c97df44	1363
lypinator	0:bb348c97df44	1364	/**
lypinator	0:bb348c97df44	1365	* @}
lypinator	0:bb348c97df44	1366	*/
lypinator	0:bb348c97df44	1367
lypinator	0:bb348c97df44	1368
lypinator	0:bb348c97df44	1369	/* Exported functions --------------------------------------------------------*/
lypinator	0:bb348c97df44	1370
lypinator	0:bb348c97df44	1371	/** @defgroup I2S_LL_Exported_Functions I2S Exported Functions
lypinator	0:bb348c97df44	1372	* @{
lypinator	0:bb348c97df44	1373	*/
lypinator	0:bb348c97df44	1374
lypinator	0:bb348c97df44	1375	/** @defgroup I2S_LL_EF_Configuration Configuration
lypinator	0:bb348c97df44	1376	* @{
lypinator	0:bb348c97df44	1377	*/
lypinator	0:bb348c97df44	1378
lypinator	0:bb348c97df44	1379	/**
lypinator	0:bb348c97df44	1380	* @brief Select I2S mode and Enable I2S peripheral
lypinator	0:bb348c97df44	1381	* @rmtoll I2SCFGR I2SMOD LL_I2S_Enable\n
lypinator	0:bb348c97df44	1382	* I2SCFGR I2SE LL_I2S_Enable
lypinator	0:bb348c97df44	1383	* @param SPIx SPI Instance
lypinator	0:bb348c97df44	1384	* @retval None
lypinator	0:bb348c97df44	1385	*/
lypinator	0:bb348c97df44	1386	__STATIC_INLINE void LL_I2S_Enable(SPI_TypeDef *SPIx)
lypinator	0:bb348c97df44	1387	{
lypinator	0:bb348c97df44	1388	SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD \| SPI_I2SCFGR_I2SE);
lypinator	0:bb348c97df44	1389	}
lypinator	0:bb348c97df44	1390
lypinator	0:bb348c97df44	1391	/**
lypinator	0:bb348c97df44	1392	* @brief Disable I2S peripheral
lypinator	0:bb348c97df44	1393	* @rmtoll I2SCFGR I2SE LL_I2S_Disable
lypinator	0:bb348c97df44	1394	* @param SPIx SPI Instance
lypinator	0:bb348c97df44	1395	* @retval None
lypinator	0:bb348c97df44	1396	*/
lypinator	0:bb348c97df44	1397	__STATIC_INLINE void LL_I2S_Disable(SPI_TypeDef *SPIx)
lypinator	0:bb348c97df44	1398	{
lypinator	0:bb348c97df44	1399	CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD \| SPI_I2SCFGR_I2SE);
lypinator	0:bb348c97df44	1400	}
lypinator	0:bb348c97df44	1401
lypinator	0:bb348c97df44	1402	/**
lypinator	0:bb348c97df44	1403	* @brief Check if I2S peripheral is enabled
lypinator	0:bb348c97df44	1404	* @rmtoll I2SCFGR I2SE LL_I2S_IsEnabled
lypinator	0:bb348c97df44	1405	* @param SPIx SPI Instance
lypinator	0:bb348c97df44	1406	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	1407	*/
lypinator	0:bb348c97df44	1408	__STATIC_INLINE uint32_t LL_I2S_IsEnabled(SPI_TypeDef *SPIx)
lypinator	0:bb348c97df44	1409	{
lypinator	0:bb348c97df44	1410	return (READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SE) == (SPI_I2SCFGR_I2SE));
lypinator	0:bb348c97df44	1411	}
lypinator	0:bb348c97df44	1412
lypinator	0:bb348c97df44	1413	/**
lypinator	0:bb348c97df44	1414	* @brief Set I2S data frame length
lypinator	0:bb348c97df44	1415	* @rmtoll I2SCFGR DATLEN LL_I2S_SetDataFormat\n
lypinator	0:bb348c97df44	1416	* I2SCFGR CHLEN LL_I2S_SetDataFormat
lypinator	0:bb348c97df44	1417	* @param SPIx SPI Instance
lypinator	0:bb348c97df44	1418	* @param DataFormat This parameter can be one of the following values:
lypinator	0:bb348c97df44	1419	* @arg @ref LL_I2S_DATAFORMAT_16B
lypinator	0:bb348c97df44	1420	* @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
lypinator	0:bb348c97df44	1421	* @arg @ref LL_I2S_DATAFORMAT_24B
lypinator	0:bb348c97df44	1422	* @arg @ref LL_I2S_DATAFORMAT_32B
lypinator	0:bb348c97df44	1423	* @retval None
lypinator	0:bb348c97df44	1424	*/
lypinator	0:bb348c97df44	1425	__STATIC_INLINE void LL_I2S_SetDataFormat(SPI_TypeDef *SPIx, uint32_t DataFormat)
lypinator	0:bb348c97df44	1426	{
lypinator	0:bb348c97df44	1427	MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN \| SPI_I2SCFGR_CHLEN, DataFormat);
lypinator	0:bb348c97df44	1428	}
lypinator	0:bb348c97df44	1429
lypinator	0:bb348c97df44	1430	/**
lypinator	0:bb348c97df44	1431	* @brief Get I2S data frame length
lypinator	0:bb348c97df44	1432	* @rmtoll I2SCFGR DATLEN LL_I2S_GetDataFormat\n
lypinator	0:bb348c97df44	1433	* I2SCFGR CHLEN LL_I2S_GetDataFormat
lypinator	0:bb348c97df44	1434	* @param SPIx SPI Instance
lypinator	0:bb348c97df44	1435	* @retval Returned value can be one of the following values:
lypinator	0:bb348c97df44	1436	* @arg @ref LL_I2S_DATAFORMAT_16B
lypinator	0:bb348c97df44	1437	* @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
lypinator	0:bb348c97df44	1438	* @arg @ref LL_I2S_DATAFORMAT_24B
lypinator	0:bb348c97df44	1439	* @arg @ref LL_I2S_DATAFORMAT_32B
lypinator	0:bb348c97df44	1440	*/
lypinator	0:bb348c97df44	1441	__STATIC_INLINE uint32_t LL_I2S_GetDataFormat(SPI_TypeDef *SPIx)
lypinator	0:bb348c97df44	1442	{
lypinator	0:bb348c97df44	1443	return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN \| SPI_I2SCFGR_CHLEN));
lypinator	0:bb348c97df44	1444	}
lypinator	0:bb348c97df44	1445
lypinator	0:bb348c97df44	1446	/**
lypinator	0:bb348c97df44	1447	* @brief Set I2S clock polarity
lypinator	0:bb348c97df44	1448	* @rmtoll I2SCFGR CKPOL LL_I2S_SetClockPolarity
lypinator	0:bb348c97df44	1449	* @param SPIx SPI Instance
lypinator	0:bb348c97df44	1450	* @param ClockPolarity This parameter can be one of the following values:
lypinator	0:bb348c97df44	1451	* @arg @ref LL_I2S_POLARITY_LOW
lypinator	0:bb348c97df44	1452	* @arg @ref LL_I2S_POLARITY_HIGH
lypinator	0:bb348c97df44	1453	* @retval None
lypinator	0:bb348c97df44	1454	*/
lypinator	0:bb348c97df44	1455	__STATIC_INLINE void LL_I2S_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
lypinator	0:bb348c97df44	1456	{
lypinator	0:bb348c97df44	1457	SET_BIT(SPIx->I2SCFGR, ClockPolarity);
lypinator	0:bb348c97df44	1458	}
lypinator	0:bb348c97df44	1459
lypinator	0:bb348c97df44	1460	/**
lypinator	0:bb348c97df44	1461	* @brief Get I2S clock polarity
lypinator	0:bb348c97df44	1462	* @rmtoll I2SCFGR CKPOL LL_I2S_GetClockPolarity
lypinator	0:bb348c97df44	1463	* @param SPIx SPI Instance
lypinator	0:bb348c97df44	1464	* @retval Returned value can be one of the following values:
lypinator	0:bb348c97df44	1465	* @arg @ref LL_I2S_POLARITY_LOW
lypinator	0:bb348c97df44	1466	* @arg @ref LL_I2S_POLARITY_HIGH
lypinator	0:bb348c97df44	1467	*/
lypinator	0:bb348c97df44	1468	__STATIC_INLINE uint32_t LL_I2S_GetClockPolarity(SPI_TypeDef *SPIx)
lypinator	0:bb348c97df44	1469	{
lypinator	0:bb348c97df44	1470	return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_CKPOL));
lypinator	0:bb348c97df44	1471	}
lypinator	0:bb348c97df44	1472
lypinator	0:bb348c97df44	1473	/**
lypinator	0:bb348c97df44	1474	* @brief Set I2S standard protocol
lypinator	0:bb348c97df44	1475	* @rmtoll I2SCFGR I2SSTD LL_I2S_SetStandard\n
lypinator	0:bb348c97df44	1476	* I2SCFGR PCMSYNC LL_I2S_SetStandard
lypinator	0:bb348c97df44	1477	* @param SPIx SPI Instance
lypinator	0:bb348c97df44	1478	* @param Standard This parameter can be one of the following values:
lypinator	0:bb348c97df44	1479	* @arg @ref LL_I2S_STANDARD_PHILIPS
lypinator	0:bb348c97df44	1480	* @arg @ref LL_I2S_STANDARD_MSB
lypinator	0:bb348c97df44	1481	* @arg @ref LL_I2S_STANDARD_LSB
lypinator	0:bb348c97df44	1482	* @arg @ref LL_I2S_STANDARD_PCM_SHORT
lypinator	0:bb348c97df44	1483	* @arg @ref LL_I2S_STANDARD_PCM_LONG
lypinator	0:bb348c97df44	1484	* @retval None
lypinator	0:bb348c97df44	1485	*/
lypinator	0:bb348c97df44	1486	__STATIC_INLINE void LL_I2S_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
lypinator	0:bb348c97df44	1487	{
lypinator	0:bb348c97df44	1488	MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD \| SPI_I2SCFGR_PCMSYNC, Standard);
lypinator	0:bb348c97df44	1489	}
lypinator	0:bb348c97df44	1490
lypinator	0:bb348c97df44	1491	/**
lypinator	0:bb348c97df44	1492	* @brief Get I2S standard protocol
lypinator	0:bb348c97df44	1493	* @rmtoll I2SCFGR I2SSTD LL_I2S_GetStandard\n
lypinator	0:bb348c97df44	1494	* I2SCFGR PCMSYNC LL_I2S_GetStandard
lypinator	0:bb348c97df44	1495	* @param SPIx SPI Instance
lypinator	0:bb348c97df44	1496	* @retval Returned value can be one of the following values:
lypinator	0:bb348c97df44	1497	* @arg @ref LL_I2S_STANDARD_PHILIPS
lypinator	0:bb348c97df44	1498	* @arg @ref LL_I2S_STANDARD_MSB
lypinator	0:bb348c97df44	1499	* @arg @ref LL_I2S_STANDARD_LSB
lypinator	0:bb348c97df44	1500	* @arg @ref LL_I2S_STANDARD_PCM_SHORT
lypinator	0:bb348c97df44	1501	* @arg @ref LL_I2S_STANDARD_PCM_LONG
lypinator	0:bb348c97df44	1502	*/
lypinator	0:bb348c97df44	1503	__STATIC_INLINE uint32_t LL_I2S_GetStandard(SPI_TypeDef *SPIx)
lypinator	0:bb348c97df44	1504	{
lypinator	0:bb348c97df44	1505	return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD \| SPI_I2SCFGR_PCMSYNC));
lypinator	0:bb348c97df44	1506	}
lypinator	0:bb348c97df44	1507
lypinator	0:bb348c97df44	1508	/**
lypinator	0:bb348c97df44	1509	* @brief Set I2S transfer mode
lypinator	0:bb348c97df44	1510	* @rmtoll I2SCFGR I2SCFG LL_I2S_SetTransferMode
lypinator	0:bb348c97df44	1511	* @param SPIx SPI Instance
lypinator	0:bb348c97df44	1512	* @param Mode This parameter can be one of the following values:
lypinator	0:bb348c97df44	1513	* @arg @ref LL_I2S_MODE_SLAVE_TX
lypinator	0:bb348c97df44	1514	* @arg @ref LL_I2S_MODE_SLAVE_RX
lypinator	0:bb348c97df44	1515	* @arg @ref LL_I2S_MODE_MASTER_TX
lypinator	0:bb348c97df44	1516	* @arg @ref LL_I2S_MODE_MASTER_RX
lypinator	0:bb348c97df44	1517	* @retval None
lypinator	0:bb348c97df44	1518	*/
lypinator	0:bb348c97df44	1519	__STATIC_INLINE void LL_I2S_SetTransferMode(SPI_TypeDef *SPIx, uint32_t Mode)
lypinator	0:bb348c97df44	1520	{
lypinator	0:bb348c97df44	1521	MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG, Mode);
lypinator	0:bb348c97df44	1522	}
lypinator	0:bb348c97df44	1523
lypinator	0:bb348c97df44	1524	/**
lypinator	0:bb348c97df44	1525	* @brief Get I2S transfer mode
lypinator	0:bb348c97df44	1526	* @rmtoll I2SCFGR I2SCFG LL_I2S_GetTransferMode
lypinator	0:bb348c97df44	1527	* @param SPIx SPI Instance
lypinator	0:bb348c97df44	1528	* @retval Returned value can be one of the following values:
lypinator	0:bb348c97df44	1529	* @arg @ref LL_I2S_MODE_SLAVE_TX
lypinator	0:bb348c97df44	1530	* @arg @ref LL_I2S_MODE_SLAVE_RX
lypinator	0:bb348c97df44	1531	* @arg @ref LL_I2S_MODE_MASTER_TX
lypinator	0:bb348c97df44	1532	* @arg @ref LL_I2S_MODE_MASTER_RX
lypinator	0:bb348c97df44	1533	*/
lypinator	0:bb348c97df44	1534	__STATIC_INLINE uint32_t LL_I2S_GetTransferMode(SPI_TypeDef *SPIx)
lypinator	0:bb348c97df44	1535	{
lypinator	0:bb348c97df44	1536	return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG));
lypinator	0:bb348c97df44	1537	}
lypinator	0:bb348c97df44	1538
lypinator	0:bb348c97df44	1539	/**
lypinator	0:bb348c97df44	1540	* @brief Set I2S linear prescaler
lypinator	0:bb348c97df44	1541	* @rmtoll I2SPR I2SDIV LL_I2S_SetPrescalerLinear
lypinator	0:bb348c97df44	1542	* @param SPIx SPI Instance
lypinator	0:bb348c97df44	1543	* @param PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
lypinator	0:bb348c97df44	1544	* @retval None
lypinator	0:bb348c97df44	1545	*/
lypinator	0:bb348c97df44	1546	__STATIC_INLINE void LL_I2S_SetPrescalerLinear(SPI_TypeDef *SPIx, uint8_t PrescalerLinear)
lypinator	0:bb348c97df44	1547	{
lypinator	0:bb348c97df44	1548	MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV, PrescalerLinear);
lypinator	0:bb348c97df44	1549	}
lypinator	0:bb348c97df44	1550
lypinator	0:bb348c97df44	1551	/**
lypinator	0:bb348c97df44	1552	* @brief Get I2S linear prescaler
lypinator	0:bb348c97df44	1553	* @rmtoll I2SPR I2SDIV LL_I2S_GetPrescalerLinear
lypinator	0:bb348c97df44	1554	* @param SPIx SPI Instance
lypinator	0:bb348c97df44	1555	* @retval PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
lypinator	0:bb348c97df44	1556	*/
lypinator	0:bb348c97df44	1557	__STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear(SPI_TypeDef *SPIx)
lypinator	0:bb348c97df44	1558	{
lypinator	0:bb348c97df44	1559	return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_I2SDIV));
lypinator	0:bb348c97df44	1560	}
lypinator	0:bb348c97df44	1561
lypinator	0:bb348c97df44	1562	/**
lypinator	0:bb348c97df44	1563	* @brief Set I2S parity prescaler
lypinator	0:bb348c97df44	1564	* @rmtoll I2SPR ODD LL_I2S_SetPrescalerParity
lypinator	0:bb348c97df44	1565	* @param SPIx SPI Instance
lypinator	0:bb348c97df44	1566	* @param PrescalerParity This parameter can be one of the following values:
lypinator	0:bb348c97df44	1567	* @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
lypinator	0:bb348c97df44	1568	* @arg @ref LL_I2S_PRESCALER_PARITY_ODD
lypinator	0:bb348c97df44	1569	* @retval None
lypinator	0:bb348c97df44	1570	*/
lypinator	0:bb348c97df44	1571	__STATIC_INLINE void LL_I2S_SetPrescalerParity(SPI_TypeDef *SPIx, uint32_t PrescalerParity)
lypinator	0:bb348c97df44	1572	{
lypinator	0:bb348c97df44	1573	MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_ODD, PrescalerParity << 8U);
lypinator	0:bb348c97df44	1574	}
lypinator	0:bb348c97df44	1575
lypinator	0:bb348c97df44	1576	/**
lypinator	0:bb348c97df44	1577	* @brief Get I2S parity prescaler
lypinator	0:bb348c97df44	1578	* @rmtoll I2SPR ODD LL_I2S_GetPrescalerParity
lypinator	0:bb348c97df44	1579	* @param SPIx SPI Instance
lypinator	0:bb348c97df44	1580	* @retval Returned value can be one of the following values:
lypinator	0:bb348c97df44	1581	* @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
lypinator	0:bb348c97df44	1582	* @arg @ref LL_I2S_PRESCALER_PARITY_ODD
lypinator	0:bb348c97df44	1583	*/
lypinator	0:bb348c97df44	1584	__STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(SPI_TypeDef *SPIx)
lypinator	0:bb348c97df44	1585	{
lypinator	0:bb348c97df44	1586	return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_ODD) >> 8U);
lypinator	0:bb348c97df44	1587	}
lypinator	0:bb348c97df44	1588
lypinator	0:bb348c97df44	1589	/**
lypinator	0:bb348c97df44	1590	* @brief Enable the master clock ouput (Pin MCK)
lypinator	0:bb348c97df44	1591	* @rmtoll I2SPR MCKOE LL_I2S_EnableMasterClock
lypinator	0:bb348c97df44	1592	* @param SPIx SPI Instance
lypinator	0:bb348c97df44	1593	* @retval None
lypinator	0:bb348c97df44	1594	*/
lypinator	0:bb348c97df44	1595	__STATIC_INLINE void LL_I2S_EnableMasterClock(SPI_TypeDef *SPIx)
lypinator	0:bb348c97df44	1596	{
lypinator	0:bb348c97df44	1597	SET_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
lypinator	0:bb348c97df44	1598	}
lypinator	0:bb348c97df44	1599
lypinator	0:bb348c97df44	1600	/**
lypinator	0:bb348c97df44	1601	* @brief Disable the master clock ouput (Pin MCK)
lypinator	0:bb348c97df44	1602	* @rmtoll I2SPR MCKOE LL_I2S_DisableMasterClock
lypinator	0:bb348c97df44	1603	* @param SPIx SPI Instance
lypinator	0:bb348c97df44	1604	* @retval None
lypinator	0:bb348c97df44	1605	*/
lypinator	0:bb348c97df44	1606	__STATIC_INLINE void LL_I2S_DisableMasterClock(SPI_TypeDef *SPIx)
lypinator	0:bb348c97df44	1607	{
lypinator	0:bb348c97df44	1608	CLEAR_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
lypinator	0:bb348c97df44	1609	}
lypinator	0:bb348c97df44	1610
lypinator	0:bb348c97df44	1611	/**
lypinator	0:bb348c97df44	1612	* @brief Check if the master clock ouput (Pin MCK) is enabled
lypinator	0:bb348c97df44	1613	* @rmtoll I2SPR MCKOE LL_I2S_IsEnabledMasterClock
lypinator	0:bb348c97df44	1614	* @param SPIx SPI Instance
lypinator	0:bb348c97df44	1615	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	1616	*/
lypinator	0:bb348c97df44	1617	__STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(SPI_TypeDef *SPIx)
lypinator	0:bb348c97df44	1618	{
lypinator	0:bb348c97df44	1619	return (READ_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE) == (SPI_I2SPR_MCKOE));
lypinator	0:bb348c97df44	1620	}
lypinator	0:bb348c97df44	1621
lypinator	0:bb348c97df44	1622	#if defined(SPI_I2SCFGR_ASTRTEN)
lypinator	0:bb348c97df44	1623	/**
lypinator	0:bb348c97df44	1624	* @brief Enable asynchronous start
lypinator	0:bb348c97df44	1625	* @rmtoll I2SCFGR ASTRTEN LL_I2S_EnableAsyncStart
lypinator	0:bb348c97df44	1626	* @param SPIx SPI Instance
lypinator	0:bb348c97df44	1627	* @retval None
lypinator	0:bb348c97df44	1628	*/
lypinator	0:bb348c97df44	1629	__STATIC_INLINE void LL_I2S_EnableAsyncStart(SPI_TypeDef *SPIx)
lypinator	0:bb348c97df44	1630	{
lypinator	0:bb348c97df44	1631	SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN);
lypinator	0:bb348c97df44	1632	}
lypinator	0:bb348c97df44	1633
lypinator	0:bb348c97df44	1634	/**
lypinator	0:bb348c97df44	1635	* @brief Disable asynchronous start
lypinator	0:bb348c97df44	1636	* @rmtoll I2SCFGR ASTRTEN LL_I2S_DisableAsyncStart
lypinator	0:bb348c97df44	1637	* @param SPIx SPI Instance
lypinator	0:bb348c97df44	1638	* @retval None
lypinator	0:bb348c97df44	1639	*/
lypinator	0:bb348c97df44	1640	__STATIC_INLINE void LL_I2S_DisableAsyncStart(SPI_TypeDef *SPIx)
lypinator	0:bb348c97df44	1641	{
lypinator	0:bb348c97df44	1642	CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN);
lypinator	0:bb348c97df44	1643	}
lypinator	0:bb348c97df44	1644
lypinator	0:bb348c97df44	1645	/**
lypinator	0:bb348c97df44	1646	* @brief Check if asynchronous start is enabled
lypinator	0:bb348c97df44	1647	* @rmtoll I2SCFGR ASTRTEN LL_I2S_IsEnabledAsyncStart
lypinator	0:bb348c97df44	1648	* @param SPIx SPI Instance
lypinator	0:bb348c97df44	1649	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	1650	*/
lypinator	0:bb348c97df44	1651	__STATIC_INLINE uint32_t LL_I2S_IsEnabledAsyncStart(SPI_TypeDef *SPIx)
lypinator	0:bb348c97df44	1652	{
lypinator	0:bb348c97df44	1653	return (READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN) == (SPI_I2SCFGR_ASTRTEN));
lypinator	0:bb348c97df44	1654	}
lypinator	0:bb348c97df44	1655	#endif /* SPI_I2SCFGR_ASTRTEN */
lypinator	0:bb348c97df44	1656
lypinator	0:bb348c97df44	1657	/**
lypinator	0:bb348c97df44	1658	* @}
lypinator	0:bb348c97df44	1659	*/
lypinator	0:bb348c97df44	1660
lypinator	0:bb348c97df44	1661	/** @defgroup I2S_LL_EF_FLAG FLAG Management
lypinator	0:bb348c97df44	1662	* @{
lypinator	0:bb348c97df44	1663	*/
lypinator	0:bb348c97df44	1664
lypinator	0:bb348c97df44	1665	/**
lypinator	0:bb348c97df44	1666	* @brief Check if Rx buffer is not empty
lypinator	0:bb348c97df44	1667	* @rmtoll SR RXNE LL_I2S_IsActiveFlag_RXNE
lypinator	0:bb348c97df44	1668	* @param SPIx SPI Instance
lypinator	0:bb348c97df44	1669	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	1670	*/
lypinator	0:bb348c97df44	1671	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
lypinator	0:bb348c97df44	1672	{
lypinator	0:bb348c97df44	1673	return LL_SPI_IsActiveFlag_RXNE(SPIx);
lypinator	0:bb348c97df44	1674	}
lypinator	0:bb348c97df44	1675
lypinator	0:bb348c97df44	1676	/**
lypinator	0:bb348c97df44	1677	* @brief Check if Tx buffer is empty
lypinator	0:bb348c97df44	1678	* @rmtoll SR TXE LL_I2S_IsActiveFlag_TXE
lypinator	0:bb348c97df44	1679	* @param SPIx SPI Instance
lypinator	0:bb348c97df44	1680	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	1681	*/
lypinator	0:bb348c97df44	1682	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
lypinator	0:bb348c97df44	1683	{
lypinator	0:bb348c97df44	1684	return LL_SPI_IsActiveFlag_TXE(SPIx);
lypinator	0:bb348c97df44	1685	}
lypinator	0:bb348c97df44	1686
lypinator	0:bb348c97df44	1687	/**
lypinator	0:bb348c97df44	1688	* @brief Get busy flag
lypinator	0:bb348c97df44	1689	* @rmtoll SR BSY LL_I2S_IsActiveFlag_BSY
lypinator	0:bb348c97df44	1690	* @param SPIx SPI Instance
lypinator	0:bb348c97df44	1691	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	1692	*/
lypinator	0:bb348c97df44	1693	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
lypinator	0:bb348c97df44	1694	{
lypinator	0:bb348c97df44	1695	return LL_SPI_IsActiveFlag_BSY(SPIx);
lypinator	0:bb348c97df44	1696	}
lypinator	0:bb348c97df44	1697
lypinator	0:bb348c97df44	1698	/**
lypinator	0:bb348c97df44	1699	* @brief Get overrun error flag
lypinator	0:bb348c97df44	1700	* @rmtoll SR OVR LL_I2S_IsActiveFlag_OVR
lypinator	0:bb348c97df44	1701	* @param SPIx SPI Instance
lypinator	0:bb348c97df44	1702	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	1703	*/
lypinator	0:bb348c97df44	1704	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
lypinator	0:bb348c97df44	1705	{
lypinator	0:bb348c97df44	1706	return LL_SPI_IsActiveFlag_OVR(SPIx);
lypinator	0:bb348c97df44	1707	}
lypinator	0:bb348c97df44	1708
lypinator	0:bb348c97df44	1709	/**
lypinator	0:bb348c97df44	1710	* @brief Get underrun error flag
lypinator	0:bb348c97df44	1711	* @rmtoll SR UDR LL_I2S_IsActiveFlag_UDR
lypinator	0:bb348c97df44	1712	* @param SPIx SPI Instance
lypinator	0:bb348c97df44	1713	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	1714	*/
lypinator	0:bb348c97df44	1715	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(SPI_TypeDef *SPIx)
lypinator	0:bb348c97df44	1716	{
lypinator	0:bb348c97df44	1717	return (READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR));
lypinator	0:bb348c97df44	1718	}
lypinator	0:bb348c97df44	1719
lypinator	0:bb348c97df44	1720	/**
lypinator	0:bb348c97df44	1721	* @brief Get frame format error flag
lypinator	0:bb348c97df44	1722	* @rmtoll SR FRE LL_I2S_IsActiveFlag_FRE
lypinator	0:bb348c97df44	1723	* @param SPIx SPI Instance
lypinator	0:bb348c97df44	1724	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	1725	*/
lypinator	0:bb348c97df44	1726	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
lypinator	0:bb348c97df44	1727	{
lypinator	0:bb348c97df44	1728	return LL_SPI_IsActiveFlag_FRE(SPIx);
lypinator	0:bb348c97df44	1729	}
lypinator	0:bb348c97df44	1730
lypinator	0:bb348c97df44	1731	/**
lypinator	0:bb348c97df44	1732	* @brief Get channel side flag.
lypinator	0:bb348c97df44	1733	* @note 0: Channel Left has to be transmitted or has been received\n
lypinator	0:bb348c97df44	1734	* 1: Channel Right has to be transmitted or has been received\n
lypinator	0:bb348c97df44	1735	* It has no significance in PCM mode.
lypinator	0:bb348c97df44	1736	* @rmtoll SR CHSIDE LL_I2S_IsActiveFlag_CHSIDE
lypinator	0:bb348c97df44	1737	* @param SPIx SPI Instance
lypinator	0:bb348c97df44	1738	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	1739	*/
lypinator	0:bb348c97df44	1740	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_CHSIDE(SPI_TypeDef *SPIx)
lypinator	0:bb348c97df44	1741	{
lypinator	0:bb348c97df44	1742	return (READ_BIT(SPIx->SR, SPI_SR_CHSIDE) == (SPI_SR_CHSIDE));
lypinator	0:bb348c97df44	1743	}
lypinator	0:bb348c97df44	1744
lypinator	0:bb348c97df44	1745	/**
lypinator	0:bb348c97df44	1746	* @brief Clear overrun error flag
lypinator	0:bb348c97df44	1747	* @rmtoll SR OVR LL_I2S_ClearFlag_OVR
lypinator	0:bb348c97df44	1748	* @param SPIx SPI Instance
lypinator	0:bb348c97df44	1749	* @retval None
lypinator	0:bb348c97df44	1750	*/
lypinator	0:bb348c97df44	1751	__STATIC_INLINE void LL_I2S_ClearFlag_OVR(SPI_TypeDef *SPIx)
lypinator	0:bb348c97df44	1752	{
lypinator	0:bb348c97df44	1753	LL_SPI_ClearFlag_OVR(SPIx);
lypinator	0:bb348c97df44	1754	}
lypinator	0:bb348c97df44	1755
lypinator	0:bb348c97df44	1756	/**
lypinator	0:bb348c97df44	1757	* @brief Clear underrun error flag
lypinator	0:bb348c97df44	1758	* @rmtoll SR UDR LL_I2S_ClearFlag_UDR
lypinator	0:bb348c97df44	1759	* @param SPIx SPI Instance
lypinator	0:bb348c97df44	1760	* @retval None
lypinator	0:bb348c97df44	1761	*/
lypinator	0:bb348c97df44	1762	__STATIC_INLINE void LL_I2S_ClearFlag_UDR(SPI_TypeDef *SPIx)
lypinator	0:bb348c97df44	1763	{
lypinator	0:bb348c97df44	1764	__IO uint32_t tmpreg;
lypinator	0:bb348c97df44	1765	tmpreg = SPIx->SR;
lypinator	0:bb348c97df44	1766	(void)tmpreg;
lypinator	0:bb348c97df44	1767	}
lypinator	0:bb348c97df44	1768
lypinator	0:bb348c97df44	1769	/**
lypinator	0:bb348c97df44	1770	* @brief Clear frame format error flag
lypinator	0:bb348c97df44	1771	* @rmtoll SR FRE LL_I2S_ClearFlag_FRE
lypinator	0:bb348c97df44	1772	* @param SPIx SPI Instance
lypinator	0:bb348c97df44	1773	* @retval None
lypinator	0:bb348c97df44	1774	*/
lypinator	0:bb348c97df44	1775	__STATIC_INLINE void LL_I2S_ClearFlag_FRE(SPI_TypeDef *SPIx)
lypinator	0:bb348c97df44	1776	{
lypinator	0:bb348c97df44	1777	LL_SPI_ClearFlag_FRE(SPIx);
lypinator	0:bb348c97df44	1778	}
lypinator	0:bb348c97df44	1779
lypinator	0:bb348c97df44	1780	/**
lypinator	0:bb348c97df44	1781	* @}
lypinator	0:bb348c97df44	1782	*/
lypinator	0:bb348c97df44	1783
lypinator	0:bb348c97df44	1784	/** @defgroup I2S_LL_EF_IT Interrupt Management
lypinator	0:bb348c97df44	1785	* @{
lypinator	0:bb348c97df44	1786	*/
lypinator	0:bb348c97df44	1787
lypinator	0:bb348c97df44	1788	/**
lypinator	0:bb348c97df44	1789	* @brief Enable error IT
lypinator	0:bb348c97df44	1790	* @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
lypinator	0:bb348c97df44	1791	* @rmtoll CR2 ERRIE LL_I2S_EnableIT_ERR
lypinator	0:bb348c97df44	1792	* @param SPIx SPI Instance
lypinator	0:bb348c97df44	1793	* @retval None
lypinator	0:bb348c97df44	1794	*/
lypinator	0:bb348c97df44	1795	__STATIC_INLINE void LL_I2S_EnableIT_ERR(SPI_TypeDef *SPIx)
lypinator	0:bb348c97df44	1796	{
lypinator	0:bb348c97df44	1797	LL_SPI_EnableIT_ERR(SPIx);
lypinator	0:bb348c97df44	1798	}
lypinator	0:bb348c97df44	1799
lypinator	0:bb348c97df44	1800	/**
lypinator	0:bb348c97df44	1801	* @brief Enable Rx buffer not empty IT
lypinator	0:bb348c97df44	1802	* @rmtoll CR2 RXNEIE LL_I2S_EnableIT_RXNE
lypinator	0:bb348c97df44	1803	* @param SPIx SPI Instance
lypinator	0:bb348c97df44	1804	* @retval None
lypinator	0:bb348c97df44	1805	*/
lypinator	0:bb348c97df44	1806	__STATIC_INLINE void LL_I2S_EnableIT_RXNE(SPI_TypeDef *SPIx)
lypinator	0:bb348c97df44	1807	{
lypinator	0:bb348c97df44	1808	LL_SPI_EnableIT_RXNE(SPIx);
lypinator	0:bb348c97df44	1809	}
lypinator	0:bb348c97df44	1810
lypinator	0:bb348c97df44	1811	/**
lypinator	0:bb348c97df44	1812	* @brief Enable Tx buffer empty IT
lypinator	0:bb348c97df44	1813	* @rmtoll CR2 TXEIE LL_I2S_EnableIT_TXE
lypinator	0:bb348c97df44	1814	* @param SPIx SPI Instance
lypinator	0:bb348c97df44	1815	* @retval None
lypinator	0:bb348c97df44	1816	*/
lypinator	0:bb348c97df44	1817	__STATIC_INLINE void LL_I2S_EnableIT_TXE(SPI_TypeDef *SPIx)
lypinator	0:bb348c97df44	1818	{
lypinator	0:bb348c97df44	1819	LL_SPI_EnableIT_TXE(SPIx);
lypinator	0:bb348c97df44	1820	}
lypinator	0:bb348c97df44	1821
lypinator	0:bb348c97df44	1822	/**
lypinator	0:bb348c97df44	1823	* @brief Disable error IT
lypinator	0:bb348c97df44	1824	* @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
lypinator	0:bb348c97df44	1825	* @rmtoll CR2 ERRIE LL_I2S_DisableIT_ERR
lypinator	0:bb348c97df44	1826	* @param SPIx SPI Instance
lypinator	0:bb348c97df44	1827	* @retval None
lypinator	0:bb348c97df44	1828	*/
lypinator	0:bb348c97df44	1829	__STATIC_INLINE void LL_I2S_DisableIT_ERR(SPI_TypeDef *SPIx)
lypinator	0:bb348c97df44	1830	{
lypinator	0:bb348c97df44	1831	LL_SPI_DisableIT_ERR(SPIx);
lypinator	0:bb348c97df44	1832	}
lypinator	0:bb348c97df44	1833
lypinator	0:bb348c97df44	1834	/**
lypinator	0:bb348c97df44	1835	* @brief Disable Rx buffer not empty IT
lypinator	0:bb348c97df44	1836	* @rmtoll CR2 RXNEIE LL_I2S_DisableIT_RXNE
lypinator	0:bb348c97df44	1837	* @param SPIx SPI Instance
lypinator	0:bb348c97df44	1838	* @retval None
lypinator	0:bb348c97df44	1839	*/
lypinator	0:bb348c97df44	1840	__STATIC_INLINE void LL_I2S_DisableIT_RXNE(SPI_TypeDef *SPIx)
lypinator	0:bb348c97df44	1841	{
lypinator	0:bb348c97df44	1842	LL_SPI_DisableIT_RXNE(SPIx);
lypinator	0:bb348c97df44	1843	}
lypinator	0:bb348c97df44	1844
lypinator	0:bb348c97df44	1845	/**
lypinator	0:bb348c97df44	1846	* @brief Disable Tx buffer empty IT
lypinator	0:bb348c97df44	1847	* @rmtoll CR2 TXEIE LL_I2S_DisableIT_TXE
lypinator	0:bb348c97df44	1848	* @param SPIx SPI Instance
lypinator	0:bb348c97df44	1849	* @retval None
lypinator	0:bb348c97df44	1850	*/
lypinator	0:bb348c97df44	1851	__STATIC_INLINE void LL_I2S_DisableIT_TXE(SPI_TypeDef *SPIx)
lypinator	0:bb348c97df44	1852	{
lypinator	0:bb348c97df44	1853	LL_SPI_DisableIT_TXE(SPIx);
lypinator	0:bb348c97df44	1854	}
lypinator	0:bb348c97df44	1855
lypinator	0:bb348c97df44	1856	/**
lypinator	0:bb348c97df44	1857	* @brief Check if ERR IT is enabled
lypinator	0:bb348c97df44	1858	* @rmtoll CR2 ERRIE LL_I2S_IsEnabledIT_ERR
lypinator	0:bb348c97df44	1859	* @param SPIx SPI Instance
lypinator	0:bb348c97df44	1860	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	1861	*/
lypinator	0:bb348c97df44	1862	__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
lypinator	0:bb348c97df44	1863	{
lypinator	0:bb348c97df44	1864	return LL_SPI_IsEnabledIT_ERR(SPIx);
lypinator	0:bb348c97df44	1865	}
lypinator	0:bb348c97df44	1866
lypinator	0:bb348c97df44	1867	/**
lypinator	0:bb348c97df44	1868	* @brief Check if RXNE IT is enabled
lypinator	0:bb348c97df44	1869	* @rmtoll CR2 RXNEIE LL_I2S_IsEnabledIT_RXNE
lypinator	0:bb348c97df44	1870	* @param SPIx SPI Instance
lypinator	0:bb348c97df44	1871	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	1872	*/
lypinator	0:bb348c97df44	1873	__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
lypinator	0:bb348c97df44	1874	{
lypinator	0:bb348c97df44	1875	return LL_SPI_IsEnabledIT_RXNE(SPIx);
lypinator	0:bb348c97df44	1876	}
lypinator	0:bb348c97df44	1877
lypinator	0:bb348c97df44	1878	/**
lypinator	0:bb348c97df44	1879	* @brief Check if TXE IT is enabled
lypinator	0:bb348c97df44	1880	* @rmtoll CR2 TXEIE LL_I2S_IsEnabledIT_TXE
lypinator	0:bb348c97df44	1881	* @param SPIx SPI Instance
lypinator	0:bb348c97df44	1882	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	1883	*/
lypinator	0:bb348c97df44	1884	__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
lypinator	0:bb348c97df44	1885	{
lypinator	0:bb348c97df44	1886	return LL_SPI_IsEnabledIT_TXE(SPIx);
lypinator	0:bb348c97df44	1887	}
lypinator	0:bb348c97df44	1888
lypinator	0:bb348c97df44	1889	/**
lypinator	0:bb348c97df44	1890	* @}
lypinator	0:bb348c97df44	1891	*/
lypinator	0:bb348c97df44	1892
lypinator	0:bb348c97df44	1893	/** @defgroup I2S_LL_EF_DMA DMA Management
lypinator	0:bb348c97df44	1894	* @{
lypinator	0:bb348c97df44	1895	*/
lypinator	0:bb348c97df44	1896
lypinator	0:bb348c97df44	1897	/**
lypinator	0:bb348c97df44	1898	* @brief Enable DMA Rx
lypinator	0:bb348c97df44	1899	* @rmtoll CR2 RXDMAEN LL_I2S_EnableDMAReq_RX
lypinator	0:bb348c97df44	1900	* @param SPIx SPI Instance
lypinator	0:bb348c97df44	1901	* @retval None
lypinator	0:bb348c97df44	1902	*/
lypinator	0:bb348c97df44	1903	__STATIC_INLINE void LL_I2S_EnableDMAReq_RX(SPI_TypeDef *SPIx)
lypinator	0:bb348c97df44	1904	{
lypinator	0:bb348c97df44	1905	LL_SPI_EnableDMAReq_RX(SPIx);
lypinator	0:bb348c97df44	1906	}
lypinator	0:bb348c97df44	1907
lypinator	0:bb348c97df44	1908	/**
lypinator	0:bb348c97df44	1909	* @brief Disable DMA Rx
lypinator	0:bb348c97df44	1910	* @rmtoll CR2 RXDMAEN LL_I2S_DisableDMAReq_RX
lypinator	0:bb348c97df44	1911	* @param SPIx SPI Instance
lypinator	0:bb348c97df44	1912	* @retval None
lypinator	0:bb348c97df44	1913	*/
lypinator	0:bb348c97df44	1914	__STATIC_INLINE void LL_I2S_DisableDMAReq_RX(SPI_TypeDef *SPIx)
lypinator	0:bb348c97df44	1915	{
lypinator	0:bb348c97df44	1916	LL_SPI_DisableDMAReq_RX(SPIx);
lypinator	0:bb348c97df44	1917	}
lypinator	0:bb348c97df44	1918
lypinator	0:bb348c97df44	1919	/**
lypinator	0:bb348c97df44	1920	* @brief Check if DMA Rx is enabled
lypinator	0:bb348c97df44	1921	* @rmtoll CR2 RXDMAEN LL_I2S_IsEnabledDMAReq_RX
lypinator	0:bb348c97df44	1922	* @param SPIx SPI Instance
lypinator	0:bb348c97df44	1923	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	1924	*/
lypinator	0:bb348c97df44	1925	__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
lypinator	0:bb348c97df44	1926	{
lypinator	0:bb348c97df44	1927	return LL_SPI_IsEnabledDMAReq_RX(SPIx);
lypinator	0:bb348c97df44	1928	}
lypinator	0:bb348c97df44	1929
lypinator	0:bb348c97df44	1930	/**
lypinator	0:bb348c97df44	1931	* @brief Enable DMA Tx
lypinator	0:bb348c97df44	1932	* @rmtoll CR2 TXDMAEN LL_I2S_EnableDMAReq_TX
lypinator	0:bb348c97df44	1933	* @param SPIx SPI Instance
lypinator	0:bb348c97df44	1934	* @retval None
lypinator	0:bb348c97df44	1935	*/
lypinator	0:bb348c97df44	1936	__STATIC_INLINE void LL_I2S_EnableDMAReq_TX(SPI_TypeDef *SPIx)
lypinator	0:bb348c97df44	1937	{
lypinator	0:bb348c97df44	1938	LL_SPI_EnableDMAReq_TX(SPIx);
lypinator	0:bb348c97df44	1939	}
lypinator	0:bb348c97df44	1940
lypinator	0:bb348c97df44	1941	/**
lypinator	0:bb348c97df44	1942	* @brief Disable DMA Tx
lypinator	0:bb348c97df44	1943	* @rmtoll CR2 TXDMAEN LL_I2S_DisableDMAReq_TX
lypinator	0:bb348c97df44	1944	* @param SPIx SPI Instance
lypinator	0:bb348c97df44	1945	* @retval None
lypinator	0:bb348c97df44	1946	*/
lypinator	0:bb348c97df44	1947	__STATIC_INLINE void LL_I2S_DisableDMAReq_TX(SPI_TypeDef *SPIx)
lypinator	0:bb348c97df44	1948	{
lypinator	0:bb348c97df44	1949	LL_SPI_DisableDMAReq_TX(SPIx);
lypinator	0:bb348c97df44	1950	}
lypinator	0:bb348c97df44	1951
lypinator	0:bb348c97df44	1952	/**
lypinator	0:bb348c97df44	1953	* @brief Check if DMA Tx is enabled
lypinator	0:bb348c97df44	1954	* @rmtoll CR2 TXDMAEN LL_I2S_IsEnabledDMAReq_TX
lypinator	0:bb348c97df44	1955	* @param SPIx SPI Instance
lypinator	0:bb348c97df44	1956	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	1957	*/
lypinator	0:bb348c97df44	1958	__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
lypinator	0:bb348c97df44	1959	{
lypinator	0:bb348c97df44	1960	return LL_SPI_IsEnabledDMAReq_TX(SPIx);
lypinator	0:bb348c97df44	1961	}
lypinator	0:bb348c97df44	1962
lypinator	0:bb348c97df44	1963	/**
lypinator	0:bb348c97df44	1964	* @}
lypinator	0:bb348c97df44	1965	*/
lypinator	0:bb348c97df44	1966
lypinator	0:bb348c97df44	1967	/** @defgroup I2S_LL_EF_DATA DATA Management
lypinator	0:bb348c97df44	1968	* @{
lypinator	0:bb348c97df44	1969	*/
lypinator	0:bb348c97df44	1970
lypinator	0:bb348c97df44	1971	/**
lypinator	0:bb348c97df44	1972	* @brief Read 16-Bits in data register
lypinator	0:bb348c97df44	1973	* @rmtoll DR DR LL_I2S_ReceiveData16
lypinator	0:bb348c97df44	1974	* @param SPIx SPI Instance
lypinator	0:bb348c97df44	1975	* @retval RxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
lypinator	0:bb348c97df44	1976	*/
lypinator	0:bb348c97df44	1977	__STATIC_INLINE uint16_t LL_I2S_ReceiveData16(SPI_TypeDef *SPIx)
lypinator	0:bb348c97df44	1978	{
lypinator	0:bb348c97df44	1979	return LL_SPI_ReceiveData16(SPIx);
lypinator	0:bb348c97df44	1980	}
lypinator	0:bb348c97df44	1981
lypinator	0:bb348c97df44	1982	/**
lypinator	0:bb348c97df44	1983	* @brief Write 16-Bits in data register
lypinator	0:bb348c97df44	1984	* @rmtoll DR DR LL_I2S_TransmitData16
lypinator	0:bb348c97df44	1985	* @param SPIx SPI Instance
lypinator	0:bb348c97df44	1986	* @param TxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
lypinator	0:bb348c97df44	1987	* @retval None
lypinator	0:bb348c97df44	1988	*/
lypinator	0:bb348c97df44	1989	__STATIC_INLINE void LL_I2S_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
lypinator	0:bb348c97df44	1990	{
lypinator	0:bb348c97df44	1991	LL_SPI_TransmitData16(SPIx, TxData);
lypinator	0:bb348c97df44	1992	}
lypinator	0:bb348c97df44	1993
lypinator	0:bb348c97df44	1994	/**
lypinator	0:bb348c97df44	1995	* @}
lypinator	0:bb348c97df44	1996	*/
lypinator	0:bb348c97df44	1997
lypinator	0:bb348c97df44	1998	#if defined(USE_FULL_LL_DRIVER)
lypinator	0:bb348c97df44	1999	/** @defgroup I2S_LL_EF_Init Initialization and de-initialization functions
lypinator	0:bb348c97df44	2000	* @{
lypinator	0:bb348c97df44	2001	*/
lypinator	0:bb348c97df44	2002
lypinator	0:bb348c97df44	2003	ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx);
lypinator	0:bb348c97df44	2004	ErrorStatus LL_I2S_Init(SPI_TypeDef SPIx, LL_I2S_InitTypeDef I2S_InitStruct);
lypinator	0:bb348c97df44	2005	void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct);
lypinator	0:bb348c97df44	2006	void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity);
lypinator	0:bb348c97df44	2007	#if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
lypinator	0:bb348c97df44	2008	ErrorStatus LL_I2S_InitFullDuplex(SPI_TypeDef I2Sxext, LL_I2S_InitTypeDef I2S_InitStruct);
lypinator	0:bb348c97df44	2009	#endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
lypinator	0:bb348c97df44	2010
lypinator	0:bb348c97df44	2011	/**
lypinator	0:bb348c97df44	2012	* @}
lypinator	0:bb348c97df44	2013	*/
lypinator	0:bb348c97df44	2014	#endif /* USE_FULL_LL_DRIVER */
lypinator	0:bb348c97df44	2015
lypinator	0:bb348c97df44	2016	/**
lypinator	0:bb348c97df44	2017	* @}
lypinator	0:bb348c97df44	2018	*/
lypinator	0:bb348c97df44	2019
lypinator	0:bb348c97df44	2020	/**
lypinator	0:bb348c97df44	2021	* @}
lypinator	0:bb348c97df44	2022	*/
lypinator	0:bb348c97df44	2023
lypinator	0:bb348c97df44	2024	#endif /* defined (SPI1) \|\| defined (SPI2) \|\| defined (SPI3) \|\| defined (SPI4) \|\| defined (SPI5) \|\| defined(SPI6) */
lypinator	0:bb348c97df44	2025
lypinator	0:bb348c97df44	2026	/**
lypinator	0:bb348c97df44	2027	* @}
lypinator	0:bb348c97df44	2028	*/
lypinator	0:bb348c97df44	2029
lypinator	0:bb348c97df44	2030	#ifdef __cplusplus
lypinator	0:bb348c97df44	2031	}
lypinator	0:bb348c97df44	2032	#endif
lypinator	0:bb348c97df44	2033
lypinator	0:bb348c97df44	2034	#endif /* __STM32F4xx_LL_SPI_H */
lypinator	0:bb348c97df44	2035
lypinator	0:bb348c97df44	2036	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

Repository toolbox

Export to desktop IDE

Build repository

Repository details

Type:	Program
Created:	16 Sep 2020
Imports:	1
Forks:	0
Commits:	1
Dependents:	0
Dependencies:	1
Followers:	1

mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_spi.h@0:bb348c97df44, 2020-09-16 (annotated)

Who changed what in which revision?

Repository toolbox

Repository details

Important Information for this Arm website

Access Warning