Thomas Lyp / DevLibMemoryController

Initial commit

Dependencies:   FastPWM

mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_spi.c@0:bb348c97df44, 2020-09-16 (annotated)

Committer:
lypinator
Date:
Wed Sep 16 01:11:49 2020 +0000
Revision:
0:bb348c97df44
Added PWM

Who changed what in which revision?

UserRevisionLine numberNew contents of line
lypinator 0:bb348c97df44 1 /**
lypinator 0:bb348c97df44 2 ******************************************************************************
lypinator 0:bb348c97df44 3 * @file stm32f4xx_ll_spi.c
lypinator 0:bb348c97df44 4 * @author MCD Application Team
lypinator 0:bb348c97df44 5 * @brief SPI LL module driver.
lypinator 0:bb348c97df44 6 ******************************************************************************
lypinator 0:bb348c97df44 7 * @attention
lypinator 0:bb348c97df44 8 *
lypinator 0:bb348c97df44 9 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
lypinator 0:bb348c97df44 10 *
lypinator 0:bb348c97df44 11 * Redistribution and use in source and binary forms, with or without modification,
lypinator 0:bb348c97df44 12 * are permitted provided that the following conditions are met:
lypinator 0:bb348c97df44 13 * 1. Redistributions of source code must retain the above copyright notice,
lypinator 0:bb348c97df44 14 * this list of conditions and the following disclaimer.
lypinator 0:bb348c97df44 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
lypinator 0:bb348c97df44 16 * this list of conditions and the following disclaimer in the documentation
lypinator 0:bb348c97df44 17 * and/or other materials provided with the distribution.
lypinator 0:bb348c97df44 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
lypinator 0:bb348c97df44 19 * may be used to endorse or promote products derived from this software
lypinator 0:bb348c97df44 20 * without specific prior written permission.
lypinator 0:bb348c97df44 21 *
lypinator 0:bb348c97df44 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
lypinator 0:bb348c97df44 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
lypinator 0:bb348c97df44 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
lypinator 0:bb348c97df44 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
lypinator 0:bb348c97df44 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
lypinator 0:bb348c97df44 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
lypinator 0:bb348c97df44 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
lypinator 0:bb348c97df44 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
lypinator 0:bb348c97df44 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
lypinator 0:bb348c97df44 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
lypinator 0:bb348c97df44 32 *
lypinator 0:bb348c97df44 33 ******************************************************************************
lypinator 0:bb348c97df44 34 */
lypinator 0:bb348c97df44 35 #if defined(USE_FULL_LL_DRIVER)
lypinator 0:bb348c97df44 36
lypinator 0:bb348c97df44 37 /* Includes ------------------------------------------------------------------*/
lypinator 0:bb348c97df44 38 #include "stm32f4xx_ll_spi.h"
lypinator 0:bb348c97df44 39 #include "stm32f4xx_ll_bus.h"
lypinator 0:bb348c97df44 40 #include "stm32f4xx_ll_rcc.h"
lypinator 0:bb348c97df44 41
lypinator 0:bb348c97df44 42 #ifdef USE_FULL_ASSERT
lypinator 0:bb348c97df44 43 #include "stm32_assert.h"
lypinator 0:bb348c97df44 44 #else
lypinator 0:bb348c97df44 45 #define assert_param(expr) ((void)0U)
lypinator 0:bb348c97df44 46 #endif
lypinator 0:bb348c97df44 47
lypinator 0:bb348c97df44 48 /** @addtogroup STM32F4xx_LL_Driver
lypinator 0:bb348c97df44 49 * @{
lypinator 0:bb348c97df44 50 */
lypinator 0:bb348c97df44 51
lypinator 0:bb348c97df44 52 #if defined (SPI1) || defined (SPI2) || defined (SPI3) || defined (SPI4) || defined (SPI5) || defined(SPI6)
lypinator 0:bb348c97df44 53
lypinator 0:bb348c97df44 54 /** @addtogroup SPI_LL
lypinator 0:bb348c97df44 55 * @{
lypinator 0:bb348c97df44 56 */
lypinator 0:bb348c97df44 57
lypinator 0:bb348c97df44 58 /* Private types -------------------------------------------------------------*/
lypinator 0:bb348c97df44 59 /* Private variables ---------------------------------------------------------*/
lypinator 0:bb348c97df44 60
lypinator 0:bb348c97df44 61 /* Private constants ---------------------------------------------------------*/
lypinator 0:bb348c97df44 62 /** @defgroup SPI_LL_Private_Constants SPI Private Constants
lypinator 0:bb348c97df44 63 * @{
lypinator 0:bb348c97df44 64 */
lypinator 0:bb348c97df44 65 /* SPI registers Masks */
lypinator 0:bb348c97df44 66 #define SPI_CR1_CLEAR_MASK (SPI_CR1_CPHA | SPI_CR1_CPOL | SPI_CR1_MSTR | \
lypinator 0:bb348c97df44 67 SPI_CR1_BR | SPI_CR1_LSBFIRST | SPI_CR1_SSI | \
lypinator 0:bb348c97df44 68 SPI_CR1_SSM | SPI_CR1_RXONLY | SPI_CR1_DFF | \
lypinator 0:bb348c97df44 69 SPI_CR1_CRCNEXT | SPI_CR1_CRCEN | SPI_CR1_BIDIOE | \
lypinator 0:bb348c97df44 70 SPI_CR1_BIDIMODE)
lypinator 0:bb348c97df44 71 /**
lypinator 0:bb348c97df44 72 * @}
lypinator 0:bb348c97df44 73 */
lypinator 0:bb348c97df44 74
lypinator 0:bb348c97df44 75 /* Private macros ------------------------------------------------------------*/
lypinator 0:bb348c97df44 76 /** @defgroup SPI_LL_Private_Macros SPI Private Macros
lypinator 0:bb348c97df44 77 * @{
lypinator 0:bb348c97df44 78 */
lypinator 0:bb348c97df44 79 #define IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__) (((__VALUE__) == LL_SPI_FULL_DUPLEX) \
lypinator 0:bb348c97df44 80 || ((__VALUE__) == LL_SPI_SIMPLEX_RX) \
lypinator 0:bb348c97df44 81 || ((__VALUE__) == LL_SPI_HALF_DUPLEX_RX) \
lypinator 0:bb348c97df44 82 || ((__VALUE__) == LL_SPI_HALF_DUPLEX_TX))
lypinator 0:bb348c97df44 83
lypinator 0:bb348c97df44 84 #define IS_LL_SPI_MODE(__VALUE__) (((__VALUE__) == LL_SPI_MODE_MASTER) \
lypinator 0:bb348c97df44 85 || ((__VALUE__) == LL_SPI_MODE_SLAVE))
lypinator 0:bb348c97df44 86
lypinator 0:bb348c97df44 87 #define IS_LL_SPI_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_SPI_DATAWIDTH_8BIT) \
lypinator 0:bb348c97df44 88 || ((__VALUE__) == LL_SPI_DATAWIDTH_16BIT))
lypinator 0:bb348c97df44 89
lypinator 0:bb348c97df44 90 #define IS_LL_SPI_POLARITY(__VALUE__) (((__VALUE__) == LL_SPI_POLARITY_LOW) \
lypinator 0:bb348c97df44 91 || ((__VALUE__) == LL_SPI_POLARITY_HIGH))
lypinator 0:bb348c97df44 92
lypinator 0:bb348c97df44 93 #define IS_LL_SPI_PHASE(__VALUE__) (((__VALUE__) == LL_SPI_PHASE_1EDGE) \
lypinator 0:bb348c97df44 94 || ((__VALUE__) == LL_SPI_PHASE_2EDGE))
lypinator 0:bb348c97df44 95
lypinator 0:bb348c97df44 96 #define IS_LL_SPI_NSS(__VALUE__) (((__VALUE__) == LL_SPI_NSS_SOFT) \
lypinator 0:bb348c97df44 97 || ((__VALUE__) == LL_SPI_NSS_HARD_INPUT) \
lypinator 0:bb348c97df44 98 || ((__VALUE__) == LL_SPI_NSS_HARD_OUTPUT))
lypinator 0:bb348c97df44 99
lypinator 0:bb348c97df44 100 #define IS_LL_SPI_BAUDRATE(__VALUE__) (((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV2) \
lypinator 0:bb348c97df44 101 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV4) \
lypinator 0:bb348c97df44 102 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV8) \
lypinator 0:bb348c97df44 103 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV16) \
lypinator 0:bb348c97df44 104 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV32) \
lypinator 0:bb348c97df44 105 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV64) \
lypinator 0:bb348c97df44 106 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV128) \
lypinator 0:bb348c97df44 107 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV256))
lypinator 0:bb348c97df44 108
lypinator 0:bb348c97df44 109 #define IS_LL_SPI_BITORDER(__VALUE__) (((__VALUE__) == LL_SPI_LSB_FIRST) \
lypinator 0:bb348c97df44 110 || ((__VALUE__) == LL_SPI_MSB_FIRST))
lypinator 0:bb348c97df44 111
lypinator 0:bb348c97df44 112 #define IS_LL_SPI_CRCCALCULATION(__VALUE__) (((__VALUE__) == LL_SPI_CRCCALCULATION_ENABLE) \
lypinator 0:bb348c97df44 113 || ((__VALUE__) == LL_SPI_CRCCALCULATION_DISABLE))
lypinator 0:bb348c97df44 114
lypinator 0:bb348c97df44 115 #define IS_LL_SPI_CRC_POLYNOMIAL(__VALUE__) ((__VALUE__) >= 0x1U)
lypinator 0:bb348c97df44 116
lypinator 0:bb348c97df44 117 /**
lypinator 0:bb348c97df44 118 * @}
lypinator 0:bb348c97df44 119 */
lypinator 0:bb348c97df44 120
lypinator 0:bb348c97df44 121 /* Private function prototypes -----------------------------------------------*/
lypinator 0:bb348c97df44 122
lypinator 0:bb348c97df44 123 /* Exported functions --------------------------------------------------------*/
lypinator 0:bb348c97df44 124 /** @addtogroup SPI_LL_Exported_Functions
lypinator 0:bb348c97df44 125 * @{
lypinator 0:bb348c97df44 126 */
lypinator 0:bb348c97df44 127
lypinator 0:bb348c97df44 128 /** @addtogroup SPI_LL_EF_Init
lypinator 0:bb348c97df44 129 * @{
lypinator 0:bb348c97df44 130 */
lypinator 0:bb348c97df44 131
lypinator 0:bb348c97df44 132 /**
lypinator 0:bb348c97df44 133 * @brief De-initialize the SPI registers to their default reset values.
lypinator 0:bb348c97df44 134 * @param SPIx SPI Instance
lypinator 0:bb348c97df44 135 * @retval An ErrorStatus enumeration value:
lypinator 0:bb348c97df44 136 * - SUCCESS: SPI registers are de-initialized
lypinator 0:bb348c97df44 137 * - ERROR: SPI registers are not de-initialized
lypinator 0:bb348c97df44 138 */
lypinator 0:bb348c97df44 139 ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx)
lypinator 0:bb348c97df44 140 {
lypinator 0:bb348c97df44 141 ErrorStatus status = ERROR;
lypinator 0:bb348c97df44 142
lypinator 0:bb348c97df44 143 /* Check the parameters */
lypinator 0:bb348c97df44 144 assert_param(IS_SPI_ALL_INSTANCE(SPIx));
lypinator 0:bb348c97df44 145
lypinator 0:bb348c97df44 146 #if defined(SPI1)
lypinator 0:bb348c97df44 147 if (SPIx == SPI1)
lypinator 0:bb348c97df44 148 {
lypinator 0:bb348c97df44 149 /* Force reset of SPI clock */
lypinator 0:bb348c97df44 150 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI1);
lypinator 0:bb348c97df44 151
lypinator 0:bb348c97df44 152 /* Release reset of SPI clock */
lypinator 0:bb348c97df44 153 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI1);
lypinator 0:bb348c97df44 154
lypinator 0:bb348c97df44 155 status = SUCCESS;
lypinator 0:bb348c97df44 156 }
lypinator 0:bb348c97df44 157 #endif /* SPI1 */
lypinator 0:bb348c97df44 158 #if defined(SPI2)
lypinator 0:bb348c97df44 159 if (SPIx == SPI2)
lypinator 0:bb348c97df44 160 {
lypinator 0:bb348c97df44 161 /* Force reset of SPI clock */
lypinator 0:bb348c97df44 162 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI2);
lypinator 0:bb348c97df44 163
lypinator 0:bb348c97df44 164 /* Release reset of SPI clock */
lypinator 0:bb348c97df44 165 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI2);
lypinator 0:bb348c97df44 166
lypinator 0:bb348c97df44 167 status = SUCCESS;
lypinator 0:bb348c97df44 168 }
lypinator 0:bb348c97df44 169 #endif /* SPI2 */
lypinator 0:bb348c97df44 170 #if defined(SPI3)
lypinator 0:bb348c97df44 171 if (SPIx == SPI3)
lypinator 0:bb348c97df44 172 {
lypinator 0:bb348c97df44 173 /* Force reset of SPI clock */
lypinator 0:bb348c97df44 174 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI3);
lypinator 0:bb348c97df44 175
lypinator 0:bb348c97df44 176 /* Release reset of SPI clock */
lypinator 0:bb348c97df44 177 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI3);
lypinator 0:bb348c97df44 178
lypinator 0:bb348c97df44 179 status = SUCCESS;
lypinator 0:bb348c97df44 180 }
lypinator 0:bb348c97df44 181 #endif /* SPI3 */
lypinator 0:bb348c97df44 182 #if defined(SPI4)
lypinator 0:bb348c97df44 183 if (SPIx == SPI4)
lypinator 0:bb348c97df44 184 {
lypinator 0:bb348c97df44 185 /* Force reset of SPI clock */
lypinator 0:bb348c97df44 186 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI4);
lypinator 0:bb348c97df44 187
lypinator 0:bb348c97df44 188 /* Release reset of SPI clock */
lypinator 0:bb348c97df44 189 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI4);
lypinator 0:bb348c97df44 190
lypinator 0:bb348c97df44 191 status = SUCCESS;
lypinator 0:bb348c97df44 192 }
lypinator 0:bb348c97df44 193 #endif /* SPI4 */
lypinator 0:bb348c97df44 194 #if defined(SPI5)
lypinator 0:bb348c97df44 195 if (SPIx == SPI5)
lypinator 0:bb348c97df44 196 {
lypinator 0:bb348c97df44 197 /* Force reset of SPI clock */
lypinator 0:bb348c97df44 198 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI5);
lypinator 0:bb348c97df44 199
lypinator 0:bb348c97df44 200 /* Release reset of SPI clock */
lypinator 0:bb348c97df44 201 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI5);
lypinator 0:bb348c97df44 202
lypinator 0:bb348c97df44 203 status = SUCCESS;
lypinator 0:bb348c97df44 204 }
lypinator 0:bb348c97df44 205 #endif /* SPI5 */
lypinator 0:bb348c97df44 206 #if defined(SPI6)
lypinator 0:bb348c97df44 207 if (SPIx == SPI6)
lypinator 0:bb348c97df44 208 {
lypinator 0:bb348c97df44 209 /* Force reset of SPI clock */
lypinator 0:bb348c97df44 210 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI6);
lypinator 0:bb348c97df44 211
lypinator 0:bb348c97df44 212 /* Release reset of SPI clock */
lypinator 0:bb348c97df44 213 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI6);
lypinator 0:bb348c97df44 214
lypinator 0:bb348c97df44 215 status = SUCCESS;
lypinator 0:bb348c97df44 216 }
lypinator 0:bb348c97df44 217 #endif /* SPI6 */
lypinator 0:bb348c97df44 218
lypinator 0:bb348c97df44 219 return status;
lypinator 0:bb348c97df44 220 }
lypinator 0:bb348c97df44 221
lypinator 0:bb348c97df44 222 /**
lypinator 0:bb348c97df44 223 * @brief Initialize the SPI registers according to the specified parameters in SPI_InitStruct.
lypinator 0:bb348c97df44 224 * @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
lypinator 0:bb348c97df44 225 * SPI IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
lypinator 0:bb348c97df44 226 * @param SPIx SPI Instance
lypinator 0:bb348c97df44 227 * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
lypinator 0:bb348c97df44 228 * @retval An ErrorStatus enumeration value. (Return always SUCCESS)
lypinator 0:bb348c97df44 229 */
lypinator 0:bb348c97df44 230 ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct)
lypinator 0:bb348c97df44 231 {
lypinator 0:bb348c97df44 232 ErrorStatus status = ERROR;
lypinator 0:bb348c97df44 233
lypinator 0:bb348c97df44 234 /* Check the SPI Instance SPIx*/
lypinator 0:bb348c97df44 235 assert_param(IS_SPI_ALL_INSTANCE(SPIx));
lypinator 0:bb348c97df44 236
lypinator 0:bb348c97df44 237 /* Check the SPI parameters from SPI_InitStruct*/
lypinator 0:bb348c97df44 238 assert_param(IS_LL_SPI_TRANSFER_DIRECTION(SPI_InitStruct->TransferDirection));
lypinator 0:bb348c97df44 239 assert_param(IS_LL_SPI_MODE(SPI_InitStruct->Mode));
lypinator 0:bb348c97df44 240 assert_param(IS_LL_SPI_DATAWIDTH(SPI_InitStruct->DataWidth));
lypinator 0:bb348c97df44 241 assert_param(IS_LL_SPI_POLARITY(SPI_InitStruct->ClockPolarity));
lypinator 0:bb348c97df44 242 assert_param(IS_LL_SPI_PHASE(SPI_InitStruct->ClockPhase));
lypinator 0:bb348c97df44 243 assert_param(IS_LL_SPI_NSS(SPI_InitStruct->NSS));
lypinator 0:bb348c97df44 244 assert_param(IS_LL_SPI_BAUDRATE(SPI_InitStruct->BaudRate));
lypinator 0:bb348c97df44 245 assert_param(IS_LL_SPI_BITORDER(SPI_InitStruct->BitOrder));
lypinator 0:bb348c97df44 246 assert_param(IS_LL_SPI_CRCCALCULATION(SPI_InitStruct->CRCCalculation));
lypinator 0:bb348c97df44 247
lypinator 0:bb348c97df44 248 if (LL_SPI_IsEnabled(SPIx) == 0x00000000U)
lypinator 0:bb348c97df44 249 {
lypinator 0:bb348c97df44 250 /*---------------------------- SPIx CR1 Configuration ------------------------
lypinator 0:bb348c97df44 251 * Configure SPIx CR1 with parameters:
lypinator 0:bb348c97df44 252 * - TransferDirection: SPI_CR1_BIDIMODE, SPI_CR1_BIDIOE and SPI_CR1_RXONLY bits
lypinator 0:bb348c97df44 253 * - Master/Slave Mode: SPI_CR1_MSTR bit
lypinator 0:bb348c97df44 254 * - DataWidth: SPI_CR1_DFF bit
lypinator 0:bb348c97df44 255 * - ClockPolarity: SPI_CR1_CPOL bit
lypinator 0:bb348c97df44 256 * - ClockPhase: SPI_CR1_CPHA bit
lypinator 0:bb348c97df44 257 * - NSS management: SPI_CR1_SSM bit
lypinator 0:bb348c97df44 258 * - BaudRate prescaler: SPI_CR1_BR[2:0] bits
lypinator 0:bb348c97df44 259 * - BitOrder: SPI_CR1_LSBFIRST bit
lypinator 0:bb348c97df44 260 * - CRCCalculation: SPI_CR1_CRCEN bit
lypinator 0:bb348c97df44 261 */
lypinator 0:bb348c97df44 262 MODIFY_REG(SPIx->CR1,
lypinator 0:bb348c97df44 263 SPI_CR1_CLEAR_MASK,
lypinator 0:bb348c97df44 264 SPI_InitStruct->TransferDirection | SPI_InitStruct->Mode | SPI_InitStruct->DataWidth |
lypinator 0:bb348c97df44 265 SPI_InitStruct->ClockPolarity | SPI_InitStruct->ClockPhase |
lypinator 0:bb348c97df44 266 SPI_InitStruct->NSS | SPI_InitStruct->BaudRate |
lypinator 0:bb348c97df44 267 SPI_InitStruct->BitOrder | SPI_InitStruct->CRCCalculation);
lypinator 0:bb348c97df44 268
lypinator 0:bb348c97df44 269 /*---------------------------- SPIx CR2 Configuration ------------------------
lypinator 0:bb348c97df44 270 * Configure SPIx CR2 with parameters:
lypinator 0:bb348c97df44 271 * - NSS management: SSOE bit
lypinator 0:bb348c97df44 272 */
lypinator 0:bb348c97df44 273 MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, (SPI_InitStruct->NSS >> 16U));
lypinator 0:bb348c97df44 274
lypinator 0:bb348c97df44 275 /*---------------------------- SPIx CRCPR Configuration ----------------------
lypinator 0:bb348c97df44 276 * Configure SPIx CRCPR with parameters:
lypinator 0:bb348c97df44 277 * - CRCPoly: CRCPOLY[15:0] bits
lypinator 0:bb348c97df44 278 */
lypinator 0:bb348c97df44 279 if (SPI_InitStruct->CRCCalculation == LL_SPI_CRCCALCULATION_ENABLE)
lypinator 0:bb348c97df44 280 {
lypinator 0:bb348c97df44 281 assert_param(IS_LL_SPI_CRC_POLYNOMIAL(SPI_InitStruct->CRCPoly));
lypinator 0:bb348c97df44 282 LL_SPI_SetCRCPolynomial(SPIx, SPI_InitStruct->CRCPoly);
lypinator 0:bb348c97df44 283 }
lypinator 0:bb348c97df44 284 status = SUCCESS;
lypinator 0:bb348c97df44 285 }
lypinator 0:bb348c97df44 286
lypinator 0:bb348c97df44 287 /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */
lypinator 0:bb348c97df44 288 CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD);
lypinator 0:bb348c97df44 289 return status;
lypinator 0:bb348c97df44 290 }
lypinator 0:bb348c97df44 291
lypinator 0:bb348c97df44 292 /**
lypinator 0:bb348c97df44 293 * @brief Set each @ref LL_SPI_InitTypeDef field to default value.
lypinator 0:bb348c97df44 294 * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
lypinator 0:bb348c97df44 295 * whose fields will be set to default values.
lypinator 0:bb348c97df44 296 * @retval None
lypinator 0:bb348c97df44 297 */
lypinator 0:bb348c97df44 298 void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct)
lypinator 0:bb348c97df44 299 {
lypinator 0:bb348c97df44 300 /* Set SPI_InitStruct fields to default values */
lypinator 0:bb348c97df44 301 SPI_InitStruct->TransferDirection = LL_SPI_FULL_DUPLEX;
lypinator 0:bb348c97df44 302 SPI_InitStruct->Mode = LL_SPI_MODE_SLAVE;
lypinator 0:bb348c97df44 303 SPI_InitStruct->DataWidth = LL_SPI_DATAWIDTH_8BIT;
lypinator 0:bb348c97df44 304 SPI_InitStruct->ClockPolarity = LL_SPI_POLARITY_LOW;
lypinator 0:bb348c97df44 305 SPI_InitStruct->ClockPhase = LL_SPI_PHASE_1EDGE;
lypinator 0:bb348c97df44 306 SPI_InitStruct->NSS = LL_SPI_NSS_HARD_INPUT;
lypinator 0:bb348c97df44 307 SPI_InitStruct->BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV2;
lypinator 0:bb348c97df44 308 SPI_InitStruct->BitOrder = LL_SPI_MSB_FIRST;
lypinator 0:bb348c97df44 309 SPI_InitStruct->CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE;
lypinator 0:bb348c97df44 310 SPI_InitStruct->CRCPoly = 7U;
lypinator 0:bb348c97df44 311 }
lypinator 0:bb348c97df44 312
lypinator 0:bb348c97df44 313 /**
lypinator 0:bb348c97df44 314 * @}
lypinator 0:bb348c97df44 315 */
lypinator 0:bb348c97df44 316
lypinator 0:bb348c97df44 317 /**
lypinator 0:bb348c97df44 318 * @}
lypinator 0:bb348c97df44 319 */
lypinator 0:bb348c97df44 320
lypinator 0:bb348c97df44 321 /**
lypinator 0:bb348c97df44 322 * @}
lypinator 0:bb348c97df44 323 */
lypinator 0:bb348c97df44 324
lypinator 0:bb348c97df44 325 /** @addtogroup I2S_LL
lypinator 0:bb348c97df44 326 * @{
lypinator 0:bb348c97df44 327 */
lypinator 0:bb348c97df44 328
lypinator 0:bb348c97df44 329 /* Private types -------------------------------------------------------------*/
lypinator 0:bb348c97df44 330 /* Private variables ---------------------------------------------------------*/
lypinator 0:bb348c97df44 331 /* Private constants ---------------------------------------------------------*/
lypinator 0:bb348c97df44 332 /** @defgroup I2S_LL_Private_Constants I2S Private Constants
lypinator 0:bb348c97df44 333 * @{
lypinator 0:bb348c97df44 334 */
lypinator 0:bb348c97df44 335 /* I2S registers Masks */
lypinator 0:bb348c97df44 336 #define I2S_I2SCFGR_CLEAR_MASK (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | \
lypinator 0:bb348c97df44 337 SPI_I2SCFGR_CKPOL | SPI_I2SCFGR_I2SSTD | \
lypinator 0:bb348c97df44 338 SPI_I2SCFGR_I2SCFG | SPI_I2SCFGR_I2SMOD )
lypinator 0:bb348c97df44 339
lypinator 0:bb348c97df44 340 #define I2S_I2SPR_CLEAR_MASK 0x0002U
lypinator 0:bb348c97df44 341 /**
lypinator 0:bb348c97df44 342 * @}
lypinator 0:bb348c97df44 343 */
lypinator 0:bb348c97df44 344 /* Private macros ------------------------------------------------------------*/
lypinator 0:bb348c97df44 345 /** @defgroup I2S_LL_Private_Macros I2S Private Macros
lypinator 0:bb348c97df44 346 * @{
lypinator 0:bb348c97df44 347 */
lypinator 0:bb348c97df44 348
lypinator 0:bb348c97df44 349 #define IS_LL_I2S_DATAFORMAT(__VALUE__) (((__VALUE__) == LL_I2S_DATAFORMAT_16B) \
lypinator 0:bb348c97df44 350 || ((__VALUE__) == LL_I2S_DATAFORMAT_16B_EXTENDED) \
lypinator 0:bb348c97df44 351 || ((__VALUE__) == LL_I2S_DATAFORMAT_24B) \
lypinator 0:bb348c97df44 352 || ((__VALUE__) == LL_I2S_DATAFORMAT_32B))
lypinator 0:bb348c97df44 353
lypinator 0:bb348c97df44 354 #define IS_LL_I2S_CPOL(__VALUE__) (((__VALUE__) == LL_I2S_POLARITY_LOW) \
lypinator 0:bb348c97df44 355 || ((__VALUE__) == LL_I2S_POLARITY_HIGH))
lypinator 0:bb348c97df44 356
lypinator 0:bb348c97df44 357 #define IS_LL_I2S_STANDARD(__VALUE__) (((__VALUE__) == LL_I2S_STANDARD_PHILIPS) \
lypinator 0:bb348c97df44 358 || ((__VALUE__) == LL_I2S_STANDARD_MSB) \
lypinator 0:bb348c97df44 359 || ((__VALUE__) == LL_I2S_STANDARD_LSB) \
lypinator 0:bb348c97df44 360 || ((__VALUE__) == LL_I2S_STANDARD_PCM_SHORT) \
lypinator 0:bb348c97df44 361 || ((__VALUE__) == LL_I2S_STANDARD_PCM_LONG))
lypinator 0:bb348c97df44 362
lypinator 0:bb348c97df44 363 #define IS_LL_I2S_MODE(__VALUE__) (((__VALUE__) == LL_I2S_MODE_SLAVE_TX) \
lypinator 0:bb348c97df44 364 || ((__VALUE__) == LL_I2S_MODE_SLAVE_RX) \
lypinator 0:bb348c97df44 365 || ((__VALUE__) == LL_I2S_MODE_MASTER_TX) \
lypinator 0:bb348c97df44 366 || ((__VALUE__) == LL_I2S_MODE_MASTER_RX))
lypinator 0:bb348c97df44 367
lypinator 0:bb348c97df44 368 #define IS_LL_I2S_MCLK_OUTPUT(__VALUE__) (((__VALUE__) == LL_I2S_MCLK_OUTPUT_ENABLE) \
lypinator 0:bb348c97df44 369 || ((__VALUE__) == LL_I2S_MCLK_OUTPUT_DISABLE))
lypinator 0:bb348c97df44 370
lypinator 0:bb348c97df44 371 #define IS_LL_I2S_AUDIO_FREQ(__VALUE__) ((((__VALUE__) >= LL_I2S_AUDIOFREQ_8K) \
lypinator 0:bb348c97df44 372 && ((__VALUE__) <= LL_I2S_AUDIOFREQ_192K)) \
lypinator 0:bb348c97df44 373 || ((__VALUE__) == LL_I2S_AUDIOFREQ_DEFAULT))
lypinator 0:bb348c97df44 374
lypinator 0:bb348c97df44 375 #define IS_LL_I2S_PRESCALER_LINEAR(__VALUE__) ((__VALUE__) >= 0x2U)
lypinator 0:bb348c97df44 376
lypinator 0:bb348c97df44 377 #define IS_LL_I2S_PRESCALER_PARITY(__VALUE__) (((__VALUE__) == LL_I2S_PRESCALER_PARITY_EVEN) \
lypinator 0:bb348c97df44 378 || ((__VALUE__) == LL_I2S_PRESCALER_PARITY_ODD))
lypinator 0:bb348c97df44 379 /**
lypinator 0:bb348c97df44 380 * @}
lypinator 0:bb348c97df44 381 */
lypinator 0:bb348c97df44 382
lypinator 0:bb348c97df44 383 /* Private function prototypes -----------------------------------------------*/
lypinator 0:bb348c97df44 384
lypinator 0:bb348c97df44 385 /* Exported functions --------------------------------------------------------*/
lypinator 0:bb348c97df44 386 /** @addtogroup I2S_LL_Exported_Functions
lypinator 0:bb348c97df44 387 * @{
lypinator 0:bb348c97df44 388 */
lypinator 0:bb348c97df44 389
lypinator 0:bb348c97df44 390 /** @addtogroup I2S_LL_EF_Init
lypinator 0:bb348c97df44 391 * @{
lypinator 0:bb348c97df44 392 */
lypinator 0:bb348c97df44 393
lypinator 0:bb348c97df44 394 /**
lypinator 0:bb348c97df44 395 * @brief De-initialize the SPI/I2S registers to their default reset values.
lypinator 0:bb348c97df44 396 * @param SPIx SPI Instance
lypinator 0:bb348c97df44 397 * @retval An ErrorStatus enumeration value:
lypinator 0:bb348c97df44 398 * - SUCCESS: SPI registers are de-initialized
lypinator 0:bb348c97df44 399 * - ERROR: SPI registers are not de-initialized
lypinator 0:bb348c97df44 400 */
lypinator 0:bb348c97df44 401 ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx)
lypinator 0:bb348c97df44 402 {
lypinator 0:bb348c97df44 403 return LL_SPI_DeInit(SPIx);
lypinator 0:bb348c97df44 404 }
lypinator 0:bb348c97df44 405
lypinator 0:bb348c97df44 406 /**
lypinator 0:bb348c97df44 407 * @brief Initializes the SPI/I2S registers according to the specified parameters in I2S_InitStruct.
lypinator 0:bb348c97df44 408 * @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
lypinator 0:bb348c97df44 409 * SPI IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
lypinator 0:bb348c97df44 410 * @param SPIx SPI Instance
lypinator 0:bb348c97df44 411 * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
lypinator 0:bb348c97df44 412 * @retval An ErrorStatus enumeration value:
lypinator 0:bb348c97df44 413 * - SUCCESS: SPI registers are Initialized
lypinator 0:bb348c97df44 414 * - ERROR: SPI registers are not Initialized
lypinator 0:bb348c97df44 415 */
lypinator 0:bb348c97df44 416 ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct)
lypinator 0:bb348c97df44 417 {
lypinator 0:bb348c97df44 418 uint16_t i2sdiv = 2U, i2sodd = 0U, packetlength = 1U;
lypinator 0:bb348c97df44 419 uint32_t tmp = 0U;
lypinator 0:bb348c97df44 420 uint32_t sourceclock = 0U;
lypinator 0:bb348c97df44 421 ErrorStatus status = ERROR;
lypinator 0:bb348c97df44 422
lypinator 0:bb348c97df44 423 /* Check the I2S parameters */
lypinator 0:bb348c97df44 424 assert_param(IS_I2S_ALL_INSTANCE(SPIx));
lypinator 0:bb348c97df44 425 assert_param(IS_LL_I2S_MODE(I2S_InitStruct->Mode));
lypinator 0:bb348c97df44 426 assert_param(IS_LL_I2S_STANDARD(I2S_InitStruct->Standard));
lypinator 0:bb348c97df44 427 assert_param(IS_LL_I2S_DATAFORMAT(I2S_InitStruct->DataFormat));
lypinator 0:bb348c97df44 428 assert_param(IS_LL_I2S_MCLK_OUTPUT(I2S_InitStruct->MCLKOutput));
lypinator 0:bb348c97df44 429 assert_param(IS_LL_I2S_AUDIO_FREQ(I2S_InitStruct->AudioFreq));
lypinator 0:bb348c97df44 430 assert_param(IS_LL_I2S_CPOL(I2S_InitStruct->ClockPolarity));
lypinator 0:bb348c97df44 431
lypinator 0:bb348c97df44 432 if (LL_I2S_IsEnabled(SPIx) == 0x00000000U)
lypinator 0:bb348c97df44 433 {
lypinator 0:bb348c97df44 434 /*---------------------------- SPIx I2SCFGR Configuration --------------------
lypinator 0:bb348c97df44 435 * Configure SPIx I2SCFGR with parameters:
lypinator 0:bb348c97df44 436 * - Mode: SPI_I2SCFGR_I2SCFG[1:0] bit
lypinator 0:bb348c97df44 437 * - Standard: SPI_I2SCFGR_I2SSTD[1:0] and SPI_I2SCFGR_PCMSYNC bits
lypinator 0:bb348c97df44 438 * - DataFormat: SPI_I2SCFGR_CHLEN and SPI_I2SCFGR_DATLEN bits
lypinator 0:bb348c97df44 439 * - ClockPolarity: SPI_I2SCFGR_CKPOL bit
lypinator 0:bb348c97df44 440 */
lypinator 0:bb348c97df44 441
lypinator 0:bb348c97df44 442 /* Write to SPIx I2SCFGR */
lypinator 0:bb348c97df44 443 MODIFY_REG(SPIx->I2SCFGR,
lypinator 0:bb348c97df44 444 I2S_I2SCFGR_CLEAR_MASK,
lypinator 0:bb348c97df44 445 I2S_InitStruct->Mode | I2S_InitStruct->Standard |
lypinator 0:bb348c97df44 446 I2S_InitStruct->DataFormat | I2S_InitStruct->ClockPolarity |
lypinator 0:bb348c97df44 447 SPI_I2SCFGR_I2SMOD);
lypinator 0:bb348c97df44 448
lypinator 0:bb348c97df44 449 /*---------------------------- SPIx I2SPR Configuration ----------------------
lypinator 0:bb348c97df44 450 * Configure SPIx I2SPR with parameters:
lypinator 0:bb348c97df44 451 * - MCLKOutput: SPI_I2SPR_MCKOE bit
lypinator 0:bb348c97df44 452 * - AudioFreq: SPI_I2SPR_I2SDIV[7:0] and SPI_I2SPR_ODD bits
lypinator 0:bb348c97df44 453 */
lypinator 0:bb348c97df44 454
lypinator 0:bb348c97df44 455 /* If the requested audio frequency is not the default, compute the prescaler (i2sodd, i2sdiv)
lypinator 0:bb348c97df44 456 * else, default values are used: i2sodd = 0U, i2sdiv = 2U.
lypinator 0:bb348c97df44 457 */
lypinator 0:bb348c97df44 458 if (I2S_InitStruct->AudioFreq != LL_I2S_AUDIOFREQ_DEFAULT)
lypinator 0:bb348c97df44 459 {
lypinator 0:bb348c97df44 460 /* Check the frame length (For the Prescaler computing)
lypinator 0:bb348c97df44 461 * Default value: LL_I2S_DATAFORMAT_16B (packetlength = 1U).
lypinator 0:bb348c97df44 462 */
lypinator 0:bb348c97df44 463 if (I2S_InitStruct->DataFormat != LL_I2S_DATAFORMAT_16B)
lypinator 0:bb348c97df44 464 {
lypinator 0:bb348c97df44 465 /* Packet length is 32 bits */
lypinator 0:bb348c97df44 466 packetlength = 2U;
lypinator 0:bb348c97df44 467 }
lypinator 0:bb348c97df44 468
lypinator 0:bb348c97df44 469 /* If an external I2S clock has to be used, the specific define should be set
lypinator 0:bb348c97df44 470 in the project configuration or in the stm32f4xx_ll_rcc.h file */
lypinator 0:bb348c97df44 471 /* Get the I2S source clock value */
lypinator 0:bb348c97df44 472 sourceclock = LL_RCC_GetI2SClockFreq(LL_RCC_I2S1_CLKSOURCE);
lypinator 0:bb348c97df44 473
lypinator 0:bb348c97df44 474 /* Compute the Real divider depending on the MCLK output state with a floating point */
lypinator 0:bb348c97df44 475 if (I2S_InitStruct->MCLKOutput == LL_I2S_MCLK_OUTPUT_ENABLE)
lypinator 0:bb348c97df44 476 {
lypinator 0:bb348c97df44 477 /* MCLK output is enabled */
lypinator 0:bb348c97df44 478 tmp = (uint16_t)(((((sourceclock / 256U) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
lypinator 0:bb348c97df44 479 }
lypinator 0:bb348c97df44 480 else
lypinator 0:bb348c97df44 481 {
lypinator 0:bb348c97df44 482 /* MCLK output is disabled */
lypinator 0:bb348c97df44 483 tmp = (uint16_t)(((((sourceclock / (32U * packetlength)) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
lypinator 0:bb348c97df44 484 }
lypinator 0:bb348c97df44 485
lypinator 0:bb348c97df44 486 /* Remove the floating point */
lypinator 0:bb348c97df44 487 tmp = tmp / 10U;
lypinator 0:bb348c97df44 488
lypinator 0:bb348c97df44 489 /* Check the parity of the divider */
lypinator 0:bb348c97df44 490 i2sodd = (uint16_t)(tmp & (uint16_t)0x0001U);
lypinator 0:bb348c97df44 491
lypinator 0:bb348c97df44 492 /* Compute the i2sdiv prescaler */
lypinator 0:bb348c97df44 493 i2sdiv = (uint16_t)((tmp - i2sodd) / 2U);
lypinator 0:bb348c97df44 494
lypinator 0:bb348c97df44 495 /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
lypinator 0:bb348c97df44 496 i2sodd = (uint16_t)(i2sodd << 8U);
lypinator 0:bb348c97df44 497 }
lypinator 0:bb348c97df44 498
lypinator 0:bb348c97df44 499 /* Test if the divider is 1 or 0 or greater than 0xFF */
lypinator 0:bb348c97df44 500 if ((i2sdiv < 2U) || (i2sdiv > 0xFFU))
lypinator 0:bb348c97df44 501 {
lypinator 0:bb348c97df44 502 /* Set the default values */
lypinator 0:bb348c97df44 503 i2sdiv = 2U;
lypinator 0:bb348c97df44 504 i2sodd = 0U;
lypinator 0:bb348c97df44 505 }
lypinator 0:bb348c97df44 506
lypinator 0:bb348c97df44 507 /* Write to SPIx I2SPR register the computed value */
lypinator 0:bb348c97df44 508 WRITE_REG(SPIx->I2SPR, i2sdiv | i2sodd | I2S_InitStruct->MCLKOutput);
lypinator 0:bb348c97df44 509
lypinator 0:bb348c97df44 510 status = SUCCESS;
lypinator 0:bb348c97df44 511 }
lypinator 0:bb348c97df44 512 return status;
lypinator 0:bb348c97df44 513 }
lypinator 0:bb348c97df44 514
lypinator 0:bb348c97df44 515 /**
lypinator 0:bb348c97df44 516 * @brief Set each @ref LL_I2S_InitTypeDef field to default value.
lypinator 0:bb348c97df44 517 * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
lypinator 0:bb348c97df44 518 * whose fields will be set to default values.
lypinator 0:bb348c97df44 519 * @retval None
lypinator 0:bb348c97df44 520 */
lypinator 0:bb348c97df44 521 void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct)
lypinator 0:bb348c97df44 522 {
lypinator 0:bb348c97df44 523 /*--------------- Reset I2S init structure parameters values -----------------*/
lypinator 0:bb348c97df44 524 I2S_InitStruct->Mode = LL_I2S_MODE_SLAVE_TX;
lypinator 0:bb348c97df44 525 I2S_InitStruct->Standard = LL_I2S_STANDARD_PHILIPS;
lypinator 0:bb348c97df44 526 I2S_InitStruct->DataFormat = LL_I2S_DATAFORMAT_16B;
lypinator 0:bb348c97df44 527 I2S_InitStruct->MCLKOutput = LL_I2S_MCLK_OUTPUT_DISABLE;
lypinator 0:bb348c97df44 528 I2S_InitStruct->AudioFreq = LL_I2S_AUDIOFREQ_DEFAULT;
lypinator 0:bb348c97df44 529 I2S_InitStruct->ClockPolarity = LL_I2S_POLARITY_LOW;
lypinator 0:bb348c97df44 530 }
lypinator 0:bb348c97df44 531
lypinator 0:bb348c97df44 532 /**
lypinator 0:bb348c97df44 533 * @brief Set linear and parity prescaler.
lypinator 0:bb348c97df44 534 * @note To calculate value of PrescalerLinear(I2SDIV[7:0] bits) and PrescalerParity(ODD bit)\n
lypinator 0:bb348c97df44 535 * Check Audio frequency table and formulas inside Reference Manual (SPI/I2S).
lypinator 0:bb348c97df44 536 * @param SPIx SPI Instance
lypinator 0:bb348c97df44 537 * @param PrescalerLinear value Min_Data=0x02 and Max_Data=0xFF.
lypinator 0:bb348c97df44 538 * @param PrescalerParity This parameter can be one of the following values:
lypinator 0:bb348c97df44 539 * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
lypinator 0:bb348c97df44 540 * @arg @ref LL_I2S_PRESCALER_PARITY_ODD
lypinator 0:bb348c97df44 541 * @retval None
lypinator 0:bb348c97df44 542 */
lypinator 0:bb348c97df44 543 void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity)
lypinator 0:bb348c97df44 544 {
lypinator 0:bb348c97df44 545 /* Check the I2S parameters */
lypinator 0:bb348c97df44 546 assert_param(IS_I2S_ALL_INSTANCE(SPIx));
lypinator 0:bb348c97df44 547 assert_param(IS_LL_I2S_PRESCALER_LINEAR(PrescalerLinear));
lypinator 0:bb348c97df44 548 assert_param(IS_LL_I2S_PRESCALER_PARITY(PrescalerParity));
lypinator 0:bb348c97df44 549
lypinator 0:bb348c97df44 550 /* Write to SPIx I2SPR */
lypinator 0:bb348c97df44 551 MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV | SPI_I2SPR_ODD, PrescalerLinear | (PrescalerParity << 8U));
lypinator 0:bb348c97df44 552 }
lypinator 0:bb348c97df44 553
lypinator 0:bb348c97df44 554 #if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
lypinator 0:bb348c97df44 555 /**
lypinator 0:bb348c97df44 556 * @brief Configures the full duplex mode for the I2Sx peripheral using its extension
lypinator 0:bb348c97df44 557 * I2Sxext according to the specified parameters in the I2S_InitStruct.
lypinator 0:bb348c97df44 558 * @note The structure pointed by I2S_InitStruct parameter should be the same
lypinator 0:bb348c97df44 559 * used for the master I2S peripheral. In this case, if the master is
lypinator 0:bb348c97df44 560 * configured as transmitter, the slave will be receiver and vice versa.
lypinator 0:bb348c97df44 561 * Or you can force a different mode by modifying the field I2S_Mode to the
lypinator 0:bb348c97df44 562 * value I2S_SlaveRx or I2S_SlaveTx independently of the master configuration.
lypinator 0:bb348c97df44 563 * @param I2Sxext SPI Instance
lypinator 0:bb348c97df44 564 * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
lypinator 0:bb348c97df44 565 * @retval An ErrorStatus enumeration value:
lypinator 0:bb348c97df44 566 * - SUCCESS: I2Sxext registers are Initialized
lypinator 0:bb348c97df44 567 * - ERROR: I2Sxext registers are not Initialized
lypinator 0:bb348c97df44 568 */
lypinator 0:bb348c97df44 569 ErrorStatus LL_I2S_InitFullDuplex(SPI_TypeDef *I2Sxext, LL_I2S_InitTypeDef *I2S_InitStruct)
lypinator 0:bb348c97df44 570 {
lypinator 0:bb348c97df44 571 uint16_t mode = 0U;
lypinator 0:bb348c97df44 572 ErrorStatus status = ERROR;
lypinator 0:bb348c97df44 573
lypinator 0:bb348c97df44 574 /* Check the I2S parameters */
lypinator 0:bb348c97df44 575 assert_param(IS_I2S_EXT_ALL_INSTANCE(I2Sxext));
lypinator 0:bb348c97df44 576 assert_param(IS_LL_I2S_MODE(I2S_InitStruct->Mode));
lypinator 0:bb348c97df44 577 assert_param(IS_LL_I2S_STANDARD(I2S_InitStruct->Standard));
lypinator 0:bb348c97df44 578 assert_param(IS_LL_I2S_DATAFORMAT(I2S_InitStruct->DataFormat));
lypinator 0:bb348c97df44 579 assert_param(IS_LL_I2S_CPOL(I2S_InitStruct->ClockPolarity));
lypinator 0:bb348c97df44 580
lypinator 0:bb348c97df44 581 if (LL_I2S_IsEnabled(I2Sxext) == 0x00000000U)
lypinator 0:bb348c97df44 582 {
lypinator 0:bb348c97df44 583 /*---------------------------- SPIx I2SCFGR Configuration --------------------
lypinator 0:bb348c97df44 584 * Configure SPIx I2SCFGR with parameters:
lypinator 0:bb348c97df44 585 * - Mode: SPI_I2SCFGR_I2SCFG[1:0] bit
lypinator 0:bb348c97df44 586 * - Standard: SPI_I2SCFGR_I2SSTD[1:0] and SPI_I2SCFGR_PCMSYNC bits
lypinator 0:bb348c97df44 587 * - DataFormat: SPI_I2SCFGR_CHLEN and SPI_I2SCFGR_DATLEN bits
lypinator 0:bb348c97df44 588 * - ClockPolarity: SPI_I2SCFGR_CKPOL bit
lypinator 0:bb348c97df44 589 */
lypinator 0:bb348c97df44 590
lypinator 0:bb348c97df44 591 /* Reset I2SPR registers */
lypinator 0:bb348c97df44 592 WRITE_REG(I2Sxext->I2SPR, I2S_I2SPR_CLEAR_MASK);
lypinator 0:bb348c97df44 593
lypinator 0:bb348c97df44 594 /* Get the mode to be configured for the extended I2S */
lypinator 0:bb348c97df44 595 if ((I2S_InitStruct->Mode == LL_I2S_MODE_MASTER_TX) || (I2S_InitStruct->Mode == LL_I2S_MODE_SLAVE_TX))
lypinator 0:bb348c97df44 596 {
lypinator 0:bb348c97df44 597 mode = LL_I2S_MODE_SLAVE_RX;
lypinator 0:bb348c97df44 598 }
lypinator 0:bb348c97df44 599 else
lypinator 0:bb348c97df44 600 {
lypinator 0:bb348c97df44 601 if ((I2S_InitStruct->Mode == LL_I2S_MODE_MASTER_RX) || (I2S_InitStruct->Mode == LL_I2S_MODE_SLAVE_RX))
lypinator 0:bb348c97df44 602 {
lypinator 0:bb348c97df44 603 mode = LL_I2S_MODE_SLAVE_TX;
lypinator 0:bb348c97df44 604 }
lypinator 0:bb348c97df44 605 }
lypinator 0:bb348c97df44 606
lypinator 0:bb348c97df44 607 /* Write to SPIx I2SCFGR */
lypinator 0:bb348c97df44 608 MODIFY_REG(I2Sxext->I2SCFGR,
lypinator 0:bb348c97df44 609 I2S_I2SCFGR_CLEAR_MASK,
lypinator 0:bb348c97df44 610 I2S_InitStruct->Standard |
lypinator 0:bb348c97df44 611 I2S_InitStruct->DataFormat | I2S_InitStruct->ClockPolarity |
lypinator 0:bb348c97df44 612 SPI_I2SCFGR_I2SMOD | mode);
lypinator 0:bb348c97df44 613
lypinator 0:bb348c97df44 614 status = SUCCESS;
lypinator 0:bb348c97df44 615 }
lypinator 0:bb348c97df44 616 return status;
lypinator 0:bb348c97df44 617 }
lypinator 0:bb348c97df44 618 #endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
lypinator 0:bb348c97df44 619
lypinator 0:bb348c97df44 620 /**
lypinator 0:bb348c97df44 621 * @}
lypinator 0:bb348c97df44 622 */
lypinator 0:bb348c97df44 623
lypinator 0:bb348c97df44 624 /**
lypinator 0:bb348c97df44 625 * @}
lypinator 0:bb348c97df44 626 */
lypinator 0:bb348c97df44 627
lypinator 0:bb348c97df44 628 /**
lypinator 0:bb348c97df44 629 * @}
lypinator 0:bb348c97df44 630 */
lypinator 0:bb348c97df44 631
lypinator 0:bb348c97df44 632 #endif /* defined (SPI1) || defined (SPI2) || defined (SPI3) || defined (SPI4) || defined (SPI5) || defined(SPI6) */
lypinator 0:bb348c97df44 633
lypinator 0:bb348c97df44 634 /**
lypinator 0:bb348c97df44 635 * @}
lypinator 0:bb348c97df44 636 */
lypinator 0:bb348c97df44 637
lypinator 0:bb348c97df44 638 #endif /* USE_FULL_LL_DRIVER */
lypinator 0:bb348c97df44 639
lypinator 0:bb348c97df44 640 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/