DevLibMemoryController - Initial commit

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Initial commit

mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_sdmmc.h@0:bb348c97df44, 2020-09-16 (annotated)

Committer:: lypinator
Date:: Wed Sep 16 01:11:49 2020 +0000
Revision:: 0:bb348c97df44

Added PWM

Who changed what in which revision?

User	Revision	Line number	New contents of line
lypinator	0:bb348c97df44	1	/**
lypinator	0:bb348c97df44	2	******************************************************************************
lypinator	0:bb348c97df44	3	* @file stm32f4xx_ll_sdmmc.h
lypinator	0:bb348c97df44	4	* @author MCD Application Team
lypinator	0:bb348c97df44	5	* @brief Header file of SDMMC HAL module.
lypinator	0:bb348c97df44	6	******************************************************************************
lypinator	0:bb348c97df44	7	* @attention
lypinator	0:bb348c97df44	8	*
lypinator	0:bb348c97df44	9	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
lypinator	0:bb348c97df44	10	*
lypinator	0:bb348c97df44	11	* Redistribution and use in source and binary forms, with or without modification,
lypinator	0:bb348c97df44	12	* are permitted provided that the following conditions are met:
lypinator	0:bb348c97df44	13	* 1. Redistributions of source code must retain the above copyright notice,
lypinator	0:bb348c97df44	14	* this list of conditions and the following disclaimer.
lypinator	0:bb348c97df44	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
lypinator	0:bb348c97df44	16	* this list of conditions and the following disclaimer in the documentation
lypinator	0:bb348c97df44	17	* and/or other materials provided with the distribution.
lypinator	0:bb348c97df44	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
lypinator	0:bb348c97df44	19	* may be used to endorse or promote products derived from this software
lypinator	0:bb348c97df44	20	* without specific prior written permission.
lypinator	0:bb348c97df44	21	*
lypinator	0:bb348c97df44	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
lypinator	0:bb348c97df44	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
lypinator	0:bb348c97df44	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
lypinator	0:bb348c97df44	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
lypinator	0:bb348c97df44	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
lypinator	0:bb348c97df44	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
lypinator	0:bb348c97df44	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
lypinator	0:bb348c97df44	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
lypinator	0:bb348c97df44	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
lypinator	0:bb348c97df44	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
lypinator	0:bb348c97df44	32	*
lypinator	0:bb348c97df44	33	******************************************************************************
lypinator	0:bb348c97df44	34	*/
lypinator	0:bb348c97df44	35
lypinator	0:bb348c97df44	36	/* Define to prevent recursive inclusion -------------------------------------*/
lypinator	0:bb348c97df44	37	#ifndef __STM32F4xx_LL_SDMMC_H
lypinator	0:bb348c97df44	38	#define __STM32F4xx_LL_SDMMC_H
lypinator	0:bb348c97df44	39
lypinator	0:bb348c97df44	40	#ifdef __cplusplus
lypinator	0:bb348c97df44	41	extern "C" {
lypinator	0:bb348c97df44	42	#endif
lypinator	0:bb348c97df44	43
lypinator	0:bb348c97df44	44	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\| \
lypinator	0:bb348c97df44	45	defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| \
lypinator	0:bb348c97df44	46	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| \
lypinator	0:bb348c97df44	47	defined(STM32F469xx) \|\| defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| \
lypinator	0:bb348c97df44	48	defined(STM32F412Rx) \|\| defined(STM32F412Cx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
lypinator	0:bb348c97df44	49
lypinator	0:bb348c97df44	50	/* Includes ------------------------------------------------------------------*/
lypinator	0:bb348c97df44	51	#include "stm32f4xx_hal_def.h"
lypinator	0:bb348c97df44	52
lypinator	0:bb348c97df44	53	/** @addtogroup STM32F4xx_Driver
lypinator	0:bb348c97df44	54	* @{
lypinator	0:bb348c97df44	55	*/
lypinator	0:bb348c97df44	56
lypinator	0:bb348c97df44	57	/** @addtogroup SDMMC_LL
lypinator	0:bb348c97df44	58	* @{
lypinator	0:bb348c97df44	59	*/
lypinator	0:bb348c97df44	60
lypinator	0:bb348c97df44	61	/* Exported types ------------------------------------------------------------*/
lypinator	0:bb348c97df44	62	/** @defgroup SDMMC_LL_Exported_Types SDMMC_LL Exported Types
lypinator	0:bb348c97df44	63	* @{
lypinator	0:bb348c97df44	64	*/
lypinator	0:bb348c97df44	65
lypinator	0:bb348c97df44	66	/**
lypinator	0:bb348c97df44	67	* @brief SDMMC Configuration Structure definition
lypinator	0:bb348c97df44	68	*/
lypinator	0:bb348c97df44	69	typedef struct
lypinator	0:bb348c97df44	70	{
lypinator	0:bb348c97df44	71	uint32_t ClockEdge; /*!< Specifies the clock transition on which the bit capture is made.
lypinator	0:bb348c97df44	72	This parameter can be a value of @ref SDMMC_LL_Clock_Edge */
lypinator	0:bb348c97df44	73
lypinator	0:bb348c97df44	74	uint32_t ClockBypass; /*!< Specifies whether the SDMMC Clock divider bypass is
lypinator	0:bb348c97df44	75	enabled or disabled.
lypinator	0:bb348c97df44	76	This parameter can be a value of @ref SDMMC_LL_Clock_Bypass */
lypinator	0:bb348c97df44	77
lypinator	0:bb348c97df44	78	uint32_t ClockPowerSave; /*!< Specifies whether SDMMC Clock output is enabled or
lypinator	0:bb348c97df44	79	disabled when the bus is idle.
lypinator	0:bb348c97df44	80	This parameter can be a value of @ref SDMMC_LL_Clock_Power_Save */
lypinator	0:bb348c97df44	81
lypinator	0:bb348c97df44	82	uint32_t BusWide; /*!< Specifies the SDMMC bus width.
lypinator	0:bb348c97df44	83	This parameter can be a value of @ref SDMMC_LL_Bus_Wide */
lypinator	0:bb348c97df44	84
lypinator	0:bb348c97df44	85	uint32_t HardwareFlowControl; /*!< Specifies whether the SDMMC hardware flow control is enabled or disabled.
lypinator	0:bb348c97df44	86	This parameter can be a value of @ref SDMMC_LL_Hardware_Flow_Control */
lypinator	0:bb348c97df44	87
lypinator	0:bb348c97df44	88	uint32_t ClockDiv; /*!< Specifies the clock frequency of the SDMMC controller.
lypinator	0:bb348c97df44	89	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
lypinator	0:bb348c97df44	90
lypinator	0:bb348c97df44	91	}SDIO_InitTypeDef;
lypinator	0:bb348c97df44	92
lypinator	0:bb348c97df44	93
lypinator	0:bb348c97df44	94	/**
lypinator	0:bb348c97df44	95	* @brief SDMMC Command Control structure
lypinator	0:bb348c97df44	96	*/
lypinator	0:bb348c97df44	97	typedef struct
lypinator	0:bb348c97df44	98	{
lypinator	0:bb348c97df44	99	uint32_t Argument; /*!< Specifies the SDMMC command argument which is sent
lypinator	0:bb348c97df44	100	to a card as part of a command message. If a command
lypinator	0:bb348c97df44	101	contains an argument, it must be loaded into this register
lypinator	0:bb348c97df44	102	before writing the command to the command register. */
lypinator	0:bb348c97df44	103
lypinator	0:bb348c97df44	104	uint32_t CmdIndex; /*!< Specifies the SDMMC command index. It must be Min_Data = 0 and
lypinator	0:bb348c97df44	105	Max_Data = 64 */
lypinator	0:bb348c97df44	106
lypinator	0:bb348c97df44	107	uint32_t Response; /*!< Specifies the SDMMC response type.
lypinator	0:bb348c97df44	108	This parameter can be a value of @ref SDMMC_LL_Response_Type */
lypinator	0:bb348c97df44	109
lypinator	0:bb348c97df44	110	uint32_t WaitForInterrupt; /*!< Specifies whether SDMMC wait for interrupt request is
lypinator	0:bb348c97df44	111	enabled or disabled.
lypinator	0:bb348c97df44	112	This parameter can be a value of @ref SDMMC_LL_Wait_Interrupt_State */
lypinator	0:bb348c97df44	113
lypinator	0:bb348c97df44	114	uint32_t CPSM; /*!< Specifies whether SDMMC Command path state machine (CPSM)
lypinator	0:bb348c97df44	115	is enabled or disabled.
lypinator	0:bb348c97df44	116	This parameter can be a value of @ref SDMMC_LL_CPSM_State */
lypinator	0:bb348c97df44	117	}SDIO_CmdInitTypeDef;
lypinator	0:bb348c97df44	118
lypinator	0:bb348c97df44	119
lypinator	0:bb348c97df44	120	/**
lypinator	0:bb348c97df44	121	* @brief SDMMC Data Control structure
lypinator	0:bb348c97df44	122	*/
lypinator	0:bb348c97df44	123	typedef struct
lypinator	0:bb348c97df44	124	{
lypinator	0:bb348c97df44	125	uint32_t DataTimeOut; /!< Specifies the data timeout period in card bus clock periods. /
lypinator	0:bb348c97df44	126
lypinator	0:bb348c97df44	127	uint32_t DataLength; /!< Specifies the number of data bytes to be transferred. /
lypinator	0:bb348c97df44	128
lypinator	0:bb348c97df44	129	uint32_t DataBlockSize; /*!< Specifies the data block size for block transfer.
lypinator	0:bb348c97df44	130	This parameter can be a value of @ref SDMMC_LL_Data_Block_Size */
lypinator	0:bb348c97df44	131
lypinator	0:bb348c97df44	132	uint32_t TransferDir; /*!< Specifies the data transfer direction, whether the transfer
lypinator	0:bb348c97df44	133	is a read or write.
lypinator	0:bb348c97df44	134	This parameter can be a value of @ref SDMMC_LL_Transfer_Direction */
lypinator	0:bb348c97df44	135
lypinator	0:bb348c97df44	136	uint32_t TransferMode; /*!< Specifies whether data transfer is in stream or block mode.
lypinator	0:bb348c97df44	137	This parameter can be a value of @ref SDMMC_LL_Transfer_Type */
lypinator	0:bb348c97df44	138
lypinator	0:bb348c97df44	139	uint32_t DPSM; /*!< Specifies whether SDMMC Data path state machine (DPSM)
lypinator	0:bb348c97df44	140	is enabled or disabled.
lypinator	0:bb348c97df44	141	This parameter can be a value of @ref SDMMC_LL_DPSM_State */
lypinator	0:bb348c97df44	142	}SDIO_DataInitTypeDef;
lypinator	0:bb348c97df44	143
lypinator	0:bb348c97df44	144	/**
lypinator	0:bb348c97df44	145	* @}
lypinator	0:bb348c97df44	146	*/
lypinator	0:bb348c97df44	147
lypinator	0:bb348c97df44	148	/* Exported constants --------------------------------------------------------*/
lypinator	0:bb348c97df44	149	/** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants
lypinator	0:bb348c97df44	150	* @{
lypinator	0:bb348c97df44	151	*/
lypinator	0:bb348c97df44	152	#define SDMMC_ERROR_NONE 0x00000000U /!< No error /
lypinator	0:bb348c97df44	153	#define SDMMC_ERROR_CMD_CRC_FAIL 0x00000001U /!< Command response received (but CRC check failed) /
lypinator	0:bb348c97df44	154	#define SDMMC_ERROR_DATA_CRC_FAIL 0x00000002U /!< Data block sent/received (CRC check failed) /
lypinator	0:bb348c97df44	155	#define SDMMC_ERROR_CMD_RSP_TIMEOUT 0x00000004U /!< Command response timeout /
lypinator	0:bb348c97df44	156	#define SDMMC_ERROR_DATA_TIMEOUT 0x00000008U /!< Data timeout /
lypinator	0:bb348c97df44	157	#define SDMMC_ERROR_TX_UNDERRUN 0x00000010U /!< Transmit FIFO underrun /
lypinator	0:bb348c97df44	158	#define SDMMC_ERROR_RX_OVERRUN 0x00000020U /!< Receive FIFO overrun /
lypinator	0:bb348c97df44	159	#define SDMMC_ERROR_ADDR_MISALIGNED 0x00000040U /!< Misaligned address /
lypinator	0:bb348c97df44	160	#define SDMMC_ERROR_BLOCK_LEN_ERR 0x00000080U /*!< Transferred block length is not allowed for the card or the
lypinator	0:bb348c97df44	161	number of transferred bytes does not match the block length */
lypinator	0:bb348c97df44	162	#define SDMMC_ERROR_ERASE_SEQ_ERR 0x00000100U /!< An error in the sequence of erase command occurs /
lypinator	0:bb348c97df44	163	#define SDMMC_ERROR_BAD_ERASE_PARAM 0x00000200U /!< An invalid selection for erase groups /
lypinator	0:bb348c97df44	164	#define SDMMC_ERROR_WRITE_PROT_VIOLATION 0x00000400U /!< Attempt to program a write protect block /
lypinator	0:bb348c97df44	165	#define SDMMC_ERROR_LOCK_UNLOCK_FAILED 0x00000800U /*!< Sequence or password error has been detected in unlock
lypinator	0:bb348c97df44	166	command or if there was an attempt to access a locked card */
lypinator	0:bb348c97df44	167	#define SDMMC_ERROR_COM_CRC_FAILED 0x00001000U /!< CRC check of the previous command failed /
lypinator	0:bb348c97df44	168	#define SDMMC_ERROR_ILLEGAL_CMD 0x00002000U /!< Command is not legal for the card state /
lypinator	0:bb348c97df44	169	#define SDMMC_ERROR_CARD_ECC_FAILED 0x00004000U /!< Card internal ECC was applied but failed to correct the data /
lypinator	0:bb348c97df44	170	#define SDMMC_ERROR_CC_ERR 0x00008000U /!< Internal card controller error /
lypinator	0:bb348c97df44	171	#define SDMMC_ERROR_GENERAL_UNKNOWN_ERR 0x00010000U /!< General or unknown error /
lypinator	0:bb348c97df44	172	#define SDMMC_ERROR_STREAM_READ_UNDERRUN 0x00020000U /!< The card could not sustain data reading in stream rmode /
lypinator	0:bb348c97df44	173	#define SDMMC_ERROR_STREAM_WRITE_OVERRUN 0x00040000U /!< The card could not sustain data programming in stream mode /
lypinator	0:bb348c97df44	174	#define SDMMC_ERROR_CID_CSD_OVERWRITE 0x00080000U /!< CID/CSD overwrite error /
lypinator	0:bb348c97df44	175	#define SDMMC_ERROR_WP_ERASE_SKIP 0x00100000U /!< Only partial address space was erased /
lypinator	0:bb348c97df44	176	#define SDMMC_ERROR_CARD_ECC_DISABLED 0x00200000U /!< Command has been executed without using internal ECC /
lypinator	0:bb348c97df44	177	#define SDMMC_ERROR_ERASE_RESET 0x00400000U /*!< Erase sequence was cleared before executing because an out
lypinator	0:bb348c97df44	178	of erase sequence command was received */
lypinator	0:bb348c97df44	179	#define SDMMC_ERROR_AKE_SEQ_ERR 0x00800000U /!< Error in sequence of authentication /
lypinator	0:bb348c97df44	180	#define SDMMC_ERROR_INVALID_VOLTRANGE 0x01000000U /!< Error in case of invalid voltage range /
lypinator	0:bb348c97df44	181	#define SDMMC_ERROR_ADDR_OUT_OF_RANGE 0x02000000U /!< Error when addressed block is out of range /
lypinator	0:bb348c97df44	182	#define SDMMC_ERROR_REQUEST_NOT_APPLICABLE 0x04000000U /!< Error when command request is not applicable /
lypinator	0:bb348c97df44	183	#define SDMMC_ERROR_INVALID_PARAMETER 0x08000000U /!< the used parameter is not valid /
lypinator	0:bb348c97df44	184	#define SDMMC_ERROR_UNSUPPORTED_FEATURE 0x10000000U /!< Error when feature is not insupported /
lypinator	0:bb348c97df44	185	#define SDMMC_ERROR_BUSY 0x20000000U /!< Error when transfer process is busy /
lypinator	0:bb348c97df44	186	#define SDMMC_ERROR_DMA 0x40000000U /!< Error while DMA transfer /
lypinator	0:bb348c97df44	187	#define SDMMC_ERROR_TIMEOUT 0x80000000U /!< Timeout error /
lypinator	0:bb348c97df44	188
lypinator	0:bb348c97df44	189	/**
lypinator	0:bb348c97df44	190	* @brief SDMMC Commands Index
lypinator	0:bb348c97df44	191	*/
lypinator	0:bb348c97df44	192	#define SDMMC_CMD_GO_IDLE_STATE ((uint8_t)0) /!< Resets the SD memory card. /
lypinator	0:bb348c97df44	193	#define SDMMC_CMD_SEND_OP_COND ((uint8_t)1) /!< Sends host capacity support information and activates the card's initialization process. /
lypinator	0:bb348c97df44	194	#define SDMMC_CMD_ALL_SEND_CID ((uint8_t)2) /!< Asks any card connected to the host to send the CID numbers on the CMD line. /
lypinator	0:bb348c97df44	195	#define SDMMC_CMD_SET_REL_ADDR ((uint8_t)3) /!< Asks the card to publish a new relative address (RCA). /
lypinator	0:bb348c97df44	196	#define SDMMC_CMD_SET_DSR ((uint8_t)4) /!< Programs the DSR of all cards. /
lypinator	0:bb348c97df44	197	#define SDMMC_CMD_SDMMC_SEN_OP_COND ((uint8_t)5) /*!< Sends host capacity support information (HCS) and asks the accessed card to send its
lypinator	0:bb348c97df44	198	operating condition register (OCR) content in the response on the CMD line. */
lypinator	0:bb348c97df44	199	#define SDMMC_CMD_HS_SWITCH ((uint8_t)6) /!< Checks switchable function (mode 0) and switch card function (mode 1). /
lypinator	0:bb348c97df44	200	#define SDMMC_CMD_SEL_DESEL_CARD ((uint8_t)7) /!< Selects the card by its own relative address and gets deselected by any other address /
lypinator	0:bb348c97df44	201	#define SDMMC_CMD_HS_SEND_EXT_CSD ((uint8_t)8) /*!< Sends SD Memory Card interface condition, which includes host supply voltage information
lypinator	0:bb348c97df44	202	and asks the card whether card supports voltage. */
lypinator	0:bb348c97df44	203	#define SDMMC_CMD_SEND_CSD ((uint8_t)9) /!< Addressed card sends its card specific data (CSD) on the CMD line. /
lypinator	0:bb348c97df44	204	#define SDMMC_CMD_SEND_CID ((uint8_t)10) /!< Addressed card sends its card identification (CID) on the CMD line. /
lypinator	0:bb348c97df44	205	#define SDMMC_CMD_READ_DAT_UNTIL_STOP ((uint8_t)11) /!< SD card doesn't support it. /
lypinator	0:bb348c97df44	206	#define SDMMC_CMD_STOP_TRANSMISSION ((uint8_t)12) /!< Forces the card to stop transmission. /
lypinator	0:bb348c97df44	207	#define SDMMC_CMD_SEND_STATUS ((uint8_t)13) /!< Addressed card sends its status register. /
lypinator	0:bb348c97df44	208	#define SDMMC_CMD_HS_BUSTEST_READ ((uint8_t)14) /!< Reserved /
lypinator	0:bb348c97df44	209	#define SDMMC_CMD_GO_INACTIVE_STATE ((uint8_t)15) /!< Sends an addressed card into the inactive state. /
lypinator	0:bb348c97df44	210	#define SDMMC_CMD_SET_BLOCKLEN ((uint8_t)16) /*!< Sets the block length (in bytes for SDSC) for all following block commands
lypinator	0:bb348c97df44	211	(read, write, lock). Default block length is fixed to 512 Bytes. Not effective
lypinator	0:bb348c97df44	212	for SDHS and SDXC. */
lypinator	0:bb348c97df44	213	#define SDMMC_CMD_READ_SINGLE_BLOCK ((uint8_t)17) /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
lypinator	0:bb348c97df44	214	fixed 512 bytes in case of SDHC and SDXC. */
lypinator	0:bb348c97df44	215	#define SDMMC_CMD_READ_MULT_BLOCK ((uint8_t)18) /*!< Continuously transfers data blocks from card to host until interrupted by
lypinator	0:bb348c97df44	216	STOP_TRANSMISSION command. */
lypinator	0:bb348c97df44	217	#define SDMMC_CMD_HS_BUSTEST_WRITE ((uint8_t)19) /!< 64 bytes tuning pattern is sent for SDR50 and SDR104. /
lypinator	0:bb348c97df44	218	#define SDMMC_CMD_WRITE_DAT_UNTIL_STOP ((uint8_t)20) /!< Speed class control command. /
lypinator	0:bb348c97df44	219	#define SDMMC_CMD_SET_BLOCK_COUNT ((uint8_t)23) /!< Specify block count for CMD18 and CMD25. /
lypinator	0:bb348c97df44	220	#define SDMMC_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24) /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
lypinator	0:bb348c97df44	221	fixed 512 bytes in case of SDHC and SDXC. */
lypinator	0:bb348c97df44	222	#define SDMMC_CMD_WRITE_MULT_BLOCK ((uint8_t)25) /!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. /
lypinator	0:bb348c97df44	223	#define SDMMC_CMD_PROG_CID ((uint8_t)26) /!< Reserved for manufacturers. /
lypinator	0:bb348c97df44	224	#define SDMMC_CMD_PROG_CSD ((uint8_t)27) /!< Programming of the programmable bits of the CSD. /
lypinator	0:bb348c97df44	225	#define SDMMC_CMD_SET_WRITE_PROT ((uint8_t)28) /!< Sets the write protection bit of the addressed group. /
lypinator	0:bb348c97df44	226	#define SDMMC_CMD_CLR_WRITE_PROT ((uint8_t)29) /!< Clears the write protection bit of the addressed group. /
lypinator	0:bb348c97df44	227	#define SDMMC_CMD_SEND_WRITE_PROT ((uint8_t)30) /!< Asks the card to send the status of the write protection bits. /
lypinator	0:bb348c97df44	228	#define SDMMC_CMD_SD_ERASE_GRP_START ((uint8_t)32) /!< Sets the address of the first write block to be erased. (For SD card only). /
lypinator	0:bb348c97df44	229	#define SDMMC_CMD_SD_ERASE_GRP_END ((uint8_t)33) /!< Sets the address of the last write block of the continuous range to be erased. /
lypinator	0:bb348c97df44	230	#define SDMMC_CMD_ERASE_GRP_START ((uint8_t)35) /*!< Sets the address of the first write block to be erased. Reserved for each command
lypinator	0:bb348c97df44	231	system set by switch function command (CMD6). */
lypinator	0:bb348c97df44	232	#define SDMMC_CMD_ERASE_GRP_END ((uint8_t)36) /*!< Sets the address of the last write block of the continuous range to be erased.
lypinator	0:bb348c97df44	233	Reserved for each command system set by switch function command (CMD6). */
lypinator	0:bb348c97df44	234	#define SDMMC_CMD_ERASE ((uint8_t)38) /!< Reserved for SD security applications. /
lypinator	0:bb348c97df44	235	#define SDMMC_CMD_FAST_IO ((uint8_t)39) /!< SD card doesn't support it (Reserved). /
lypinator	0:bb348c97df44	236	#define SDMMC_CMD_GO_IRQ_STATE ((uint8_t)40) /!< SD card doesn't support it (Reserved). /
lypinator	0:bb348c97df44	237	#define SDMMC_CMD_LOCK_UNLOCK ((uint8_t)42) /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by
lypinator	0:bb348c97df44	238	the SET_BLOCK_LEN command. */
lypinator	0:bb348c97df44	239	#define SDMMC_CMD_APP_CMD ((uint8_t)55) /*!< Indicates to the card that the next command is an application specific command rather
lypinator	0:bb348c97df44	240	than a standard command. */
lypinator	0:bb348c97df44	241	#define SDMMC_CMD_GEN_CMD ((uint8_t)56) /*!< Used either to transfer a data block to the card or to get a data block from the card
lypinator	0:bb348c97df44	242	for general purpose/application specific commands. */
lypinator	0:bb348c97df44	243	#define SDMMC_CMD_NO_CMD ((uint8_t)64) /!< No command /
lypinator	0:bb348c97df44	244
lypinator	0:bb348c97df44	245	/**
lypinator	0:bb348c97df44	246	* @brief Following commands are SD Card Specific commands.
lypinator	0:bb348c97df44	247	* SDMMC_APP_CMD should be sent before sending these commands.
lypinator	0:bb348c97df44	248	*/
lypinator	0:bb348c97df44	249	#define SDMMC_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6) /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus
lypinator	0:bb348c97df44	250	widths are given in SCR register. */
lypinator	0:bb348c97df44	251	#define SDMMC_CMD_SD_APP_STATUS ((uint8_t)13) /!< (ACMD13) Sends the SD status. /
lypinator	0:bb348c97df44	252	#define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22) /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with
lypinator	0:bb348c97df44	253	32bit+CRC data block. */
lypinator	0:bb348c97df44	254	#define SDMMC_CMD_SD_APP_OP_COND ((uint8_t)41) /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to
lypinator	0:bb348c97df44	255	send its operating condition register (OCR) content in the response on the CMD line. */
lypinator	0:bb348c97df44	256	#define SDMMC_CMD_SD_APP_SET_CLR_CARD_DETECT ((uint8_t)42) /!< (ACMD42) Connect/Disconnect the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card /
lypinator	0:bb348c97df44	257	#define SDMMC_CMD_SD_APP_SEND_SCR ((uint8_t)51) /!< Reads the SD Configuration Register (SCR). /
lypinator	0:bb348c97df44	258	#define SDMMC_CMD_SDMMC_RW_DIRECT ((uint8_t)52) /!< For SD I/O card only, reserved for security specification. /
lypinator	0:bb348c97df44	259	#define SDMMC_CMD_SDMMC_RW_EXTENDED ((uint8_t)53) /!< For SD I/O card only, reserved for security specification. /
lypinator	0:bb348c97df44	260
lypinator	0:bb348c97df44	261	/**
lypinator	0:bb348c97df44	262	* @brief Following commands are SD Card Specific security commands.
lypinator	0:bb348c97df44	263	* SDMMC_CMD_APP_CMD should be sent before sending these commands.
lypinator	0:bb348c97df44	264	*/
lypinator	0:bb348c97df44	265	#define SDMMC_CMD_SD_APP_GET_MKB ((uint8_t)43)
lypinator	0:bb348c97df44	266	#define SDMMC_CMD_SD_APP_GET_MID ((uint8_t)44)
lypinator	0:bb348c97df44	267	#define SDMMC_CMD_SD_APP_SET_CER_RN1 ((uint8_t)45)
lypinator	0:bb348c97df44	268	#define SDMMC_CMD_SD_APP_GET_CER_RN2 ((uint8_t)46)
lypinator	0:bb348c97df44	269	#define SDMMC_CMD_SD_APP_SET_CER_RES2 ((uint8_t)47)
lypinator	0:bb348c97df44	270	#define SDMMC_CMD_SD_APP_GET_CER_RES1 ((uint8_t)48)
lypinator	0:bb348c97df44	271	#define SDMMC_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK ((uint8_t)18)
lypinator	0:bb348c97df44	272	#define SDMMC_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK ((uint8_t)25)
lypinator	0:bb348c97df44	273	#define SDMMC_CMD_SD_APP_SECURE_ERASE ((uint8_t)38)
lypinator	0:bb348c97df44	274	#define SDMMC_CMD_SD_APP_CHANGE_SECURE_AREA ((uint8_t)49)
lypinator	0:bb348c97df44	275	#define SDMMC_CMD_SD_APP_SECURE_WRITE_MKB ((uint8_t)48)
lypinator	0:bb348c97df44	276
lypinator	0:bb348c97df44	277	/**
lypinator	0:bb348c97df44	278	* @brief Masks for errors Card Status R1 (OCR Register)
lypinator	0:bb348c97df44	279	*/
lypinator	0:bb348c97df44	280	#define SDMMC_OCR_ADDR_OUT_OF_RANGE 0x80000000U
lypinator	0:bb348c97df44	281	#define SDMMC_OCR_ADDR_MISALIGNED 0x40000000U
lypinator	0:bb348c97df44	282	#define SDMMC_OCR_BLOCK_LEN_ERR 0x20000000U
lypinator	0:bb348c97df44	283	#define SDMMC_OCR_ERASE_SEQ_ERR 0x10000000U
lypinator	0:bb348c97df44	284	#define SDMMC_OCR_BAD_ERASE_PARAM 0x08000000U
lypinator	0:bb348c97df44	285	#define SDMMC_OCR_WRITE_PROT_VIOLATION 0x04000000U
lypinator	0:bb348c97df44	286	#define SDMMC_OCR_LOCK_UNLOCK_FAILED 0x01000000U
lypinator	0:bb348c97df44	287	#define SDMMC_OCR_COM_CRC_FAILED 0x00800000U
lypinator	0:bb348c97df44	288	#define SDMMC_OCR_ILLEGAL_CMD 0x00400000U
lypinator	0:bb348c97df44	289	#define SDMMC_OCR_CARD_ECC_FAILED 0x00200000U
lypinator	0:bb348c97df44	290	#define SDMMC_OCR_CC_ERROR 0x00100000U
lypinator	0:bb348c97df44	291	#define SDMMC_OCR_GENERAL_UNKNOWN_ERROR 0x00080000U
lypinator	0:bb348c97df44	292	#define SDMMC_OCR_STREAM_READ_UNDERRUN 0x00040000U
lypinator	0:bb348c97df44	293	#define SDMMC_OCR_STREAM_WRITE_OVERRUN 0x00020000U
lypinator	0:bb348c97df44	294	#define SDMMC_OCR_CID_CSD_OVERWRITE 0x00010000U
lypinator	0:bb348c97df44	295	#define SDMMC_OCR_WP_ERASE_SKIP 0x00008000U
lypinator	0:bb348c97df44	296	#define SDMMC_OCR_CARD_ECC_DISABLED 0x00004000U
lypinator	0:bb348c97df44	297	#define SDMMC_OCR_ERASE_RESET 0x00002000U
lypinator	0:bb348c97df44	298	#define SDMMC_OCR_AKE_SEQ_ERROR 0x00000008U
lypinator	0:bb348c97df44	299	#define SDMMC_OCR_ERRORBITS 0xFDFFE008U
lypinator	0:bb348c97df44	300
lypinator	0:bb348c97df44	301	/**
lypinator	0:bb348c97df44	302	* @brief Masks for R6 Response
lypinator	0:bb348c97df44	303	*/
lypinator	0:bb348c97df44	304	#define SDMMC_R6_GENERAL_UNKNOWN_ERROR 0x00002000U
lypinator	0:bb348c97df44	305	#define SDMMC_R6_ILLEGAL_CMD 0x00004000U
lypinator	0:bb348c97df44	306	#define SDMMC_R6_COM_CRC_FAILED 0x00008000U
lypinator	0:bb348c97df44	307
lypinator	0:bb348c97df44	308	#define SDMMC_VOLTAGE_WINDOW_SD 0x80100000U
lypinator	0:bb348c97df44	309	#define SDMMC_HIGH_CAPACITY 0x40000000U
lypinator	0:bb348c97df44	310	#define SDMMC_STD_CAPACITY 0x00000000U
lypinator	0:bb348c97df44	311	#define SDMMC_CHECK_PATTERN 0x000001AAU
lypinator	0:bb348c97df44	312
lypinator	0:bb348c97df44	313	#define SDMMC_MAX_VOLT_TRIAL 0x0000FFFFU
lypinator	0:bb348c97df44	314
lypinator	0:bb348c97df44	315	#define SDMMC_MAX_TRIAL 0x0000FFFFU
lypinator	0:bb348c97df44	316
lypinator	0:bb348c97df44	317	#define SDMMC_ALLZERO 0x00000000U
lypinator	0:bb348c97df44	318
lypinator	0:bb348c97df44	319	#define SDMMC_WIDE_BUS_SUPPORT 0x00040000U
lypinator	0:bb348c97df44	320	#define SDMMC_SINGLE_BUS_SUPPORT 0x00010000U
lypinator	0:bb348c97df44	321	#define SDMMC_CARD_LOCKED 0x02000000U
lypinator	0:bb348c97df44	322
lypinator	0:bb348c97df44	323	#define SDMMC_DATATIMEOUT 0xFFFFFFFFU
lypinator	0:bb348c97df44	324
lypinator	0:bb348c97df44	325	#define SDMMC_0TO7BITS 0x000000FFU
lypinator	0:bb348c97df44	326	#define SDMMC_8TO15BITS 0x0000FF00U
lypinator	0:bb348c97df44	327	#define SDMMC_16TO23BITS 0x00FF0000U
lypinator	0:bb348c97df44	328	#define SDMMC_24TO31BITS 0xFF000000U
lypinator	0:bb348c97df44	329	#define SDMMC_MAX_DATA_LENGTH 0x01FFFFFFU
lypinator	0:bb348c97df44	330
lypinator	0:bb348c97df44	331	#define SDMMC_HALFFIFO 0x00000008U
lypinator	0:bb348c97df44	332	#define SDMMC_HALFFIFOBYTES 0x00000020U
lypinator	0:bb348c97df44	333
lypinator	0:bb348c97df44	334	/**
lypinator	0:bb348c97df44	335	* @brief Command Class supported
lypinator	0:bb348c97df44	336	*/
lypinator	0:bb348c97df44	337	#define SDIO_CCCC_ERASE 0x00000020U
lypinator	0:bb348c97df44	338
lypinator	0:bb348c97df44	339	#define SDIO_CMDTIMEOUT 5000U /* Command send and response timeout */
lypinator	0:bb348c97df44	340	#define SDIO_MAXERASETIMEOUT 63000U /* Max erase Timeout 63 s */
lypinator	0:bb348c97df44	341
lypinator	0:bb348c97df44	342
lypinator	0:bb348c97df44	343	/** @defgroup SDIO_LL_Clock_Edge Clock Edge
lypinator	0:bb348c97df44	344	* @{
lypinator	0:bb348c97df44	345	*/
lypinator	0:bb348c97df44	346	#define SDIO_CLOCK_EDGE_RISING 0x00000000U
lypinator	0:bb348c97df44	347	#define SDIO_CLOCK_EDGE_FALLING SDIO_CLKCR_NEGEDGE
lypinator	0:bb348c97df44	348
lypinator	0:bb348c97df44	349	#define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_CLOCK_EDGE_RISING) \|\| \
lypinator	0:bb348c97df44	350	((EDGE) == SDIO_CLOCK_EDGE_FALLING))
lypinator	0:bb348c97df44	351	/**
lypinator	0:bb348c97df44	352	* @}
lypinator	0:bb348c97df44	353	*/
lypinator	0:bb348c97df44	354
lypinator	0:bb348c97df44	355	/** @defgroup SDIO_LL_Clock_Bypass Clock Bypass
lypinator	0:bb348c97df44	356	* @{
lypinator	0:bb348c97df44	357	*/
lypinator	0:bb348c97df44	358	#define SDIO_CLOCK_BYPASS_DISABLE 0x00000000U
lypinator	0:bb348c97df44	359	#define SDIO_CLOCK_BYPASS_ENABLE SDIO_CLKCR_BYPASS
lypinator	0:bb348c97df44	360
lypinator	0:bb348c97df44	361	#define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_CLOCK_BYPASS_DISABLE) \|\| \
lypinator	0:bb348c97df44	362	((BYPASS) == SDIO_CLOCK_BYPASS_ENABLE))
lypinator	0:bb348c97df44	363	/**
lypinator	0:bb348c97df44	364	* @}
lypinator	0:bb348c97df44	365	*/
lypinator	0:bb348c97df44	366
lypinator	0:bb348c97df44	367	/** @defgroup SDIO_LL_Clock_Power_Save Clock Power Saving
lypinator	0:bb348c97df44	368	* @{
lypinator	0:bb348c97df44	369	*/
lypinator	0:bb348c97df44	370	#define SDIO_CLOCK_POWER_SAVE_DISABLE 0x00000000U
lypinator	0:bb348c97df44	371	#define SDIO_CLOCK_POWER_SAVE_ENABLE SDIO_CLKCR_PWRSAV
lypinator	0:bb348c97df44	372
lypinator	0:bb348c97df44	373	#define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_CLOCK_POWER_SAVE_DISABLE) \|\| \
lypinator	0:bb348c97df44	374	((SAVE) == SDIO_CLOCK_POWER_SAVE_ENABLE))
lypinator	0:bb348c97df44	375	/**
lypinator	0:bb348c97df44	376	* @}
lypinator	0:bb348c97df44	377	*/
lypinator	0:bb348c97df44	378
lypinator	0:bb348c97df44	379	/** @defgroup SDIO_LL_Bus_Wide Bus Width
lypinator	0:bb348c97df44	380	* @{
lypinator	0:bb348c97df44	381	*/
lypinator	0:bb348c97df44	382	#define SDIO_BUS_WIDE_1B 0x00000000U
lypinator	0:bb348c97df44	383	#define SDIO_BUS_WIDE_4B SDIO_CLKCR_WIDBUS_0
lypinator	0:bb348c97df44	384	#define SDIO_BUS_WIDE_8B SDIO_CLKCR_WIDBUS_1
lypinator	0:bb348c97df44	385
lypinator	0:bb348c97df44	386	#define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BUS_WIDE_1B) \|\| \
lypinator	0:bb348c97df44	387	((WIDE) == SDIO_BUS_WIDE_4B) \|\| \
lypinator	0:bb348c97df44	388	((WIDE) == SDIO_BUS_WIDE_8B))
lypinator	0:bb348c97df44	389	/**
lypinator	0:bb348c97df44	390	* @}
lypinator	0:bb348c97df44	391	*/
lypinator	0:bb348c97df44	392
lypinator	0:bb348c97df44	393	/** @defgroup SDIO_LL_Hardware_Flow_Control Hardware Flow Control
lypinator	0:bb348c97df44	394	* @{
lypinator	0:bb348c97df44	395	*/
lypinator	0:bb348c97df44	396	#define SDIO_HARDWARE_FLOW_CONTROL_DISABLE 0x00000000U
lypinator	0:bb348c97df44	397	#define SDIO_HARDWARE_FLOW_CONTROL_ENABLE SDIO_CLKCR_HWFC_EN
lypinator	0:bb348c97df44	398
lypinator	0:bb348c97df44	399	#define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_DISABLE) \|\| \
lypinator	0:bb348c97df44	400	((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_ENABLE))
lypinator	0:bb348c97df44	401	/**
lypinator	0:bb348c97df44	402	* @}
lypinator	0:bb348c97df44	403	*/
lypinator	0:bb348c97df44	404
lypinator	0:bb348c97df44	405	/** @defgroup SDIO_LL_Clock_Division Clock Division
lypinator	0:bb348c97df44	406	* @{
lypinator	0:bb348c97df44	407	*/
lypinator	0:bb348c97df44	408	#define IS_SDIO_CLKDIV(DIV) ((DIV) <= 0xFFU)
lypinator	0:bb348c97df44	409	/**
lypinator	0:bb348c97df44	410	* @}
lypinator	0:bb348c97df44	411	*/
lypinator	0:bb348c97df44	412
lypinator	0:bb348c97df44	413	/** @defgroup SDIO_LL_Command_Index Command Index
lypinator	0:bb348c97df44	414	* @{
lypinator	0:bb348c97df44	415	*/
lypinator	0:bb348c97df44	416	#define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40U)
lypinator	0:bb348c97df44	417	/**
lypinator	0:bb348c97df44	418	* @}
lypinator	0:bb348c97df44	419	*/
lypinator	0:bb348c97df44	420
lypinator	0:bb348c97df44	421	/** @defgroup SDIO_LL_Response_Type Response Type
lypinator	0:bb348c97df44	422	* @{
lypinator	0:bb348c97df44	423	*/
lypinator	0:bb348c97df44	424	#define SDIO_RESPONSE_NO 0x00000000U
lypinator	0:bb348c97df44	425	#define SDIO_RESPONSE_SHORT SDIO_CMD_WAITRESP_0
lypinator	0:bb348c97df44	426	#define SDIO_RESPONSE_LONG SDIO_CMD_WAITRESP
lypinator	0:bb348c97df44	427
lypinator	0:bb348c97df44	428	#define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_RESPONSE_NO) \|\| \
lypinator	0:bb348c97df44	429	((RESPONSE) == SDIO_RESPONSE_SHORT) \|\| \
lypinator	0:bb348c97df44	430	((RESPONSE) == SDIO_RESPONSE_LONG))
lypinator	0:bb348c97df44	431	/**
lypinator	0:bb348c97df44	432	* @}
lypinator	0:bb348c97df44	433	*/
lypinator	0:bb348c97df44	434
lypinator	0:bb348c97df44	435	/** @defgroup SDIO_LL_Wait_Interrupt_State Wait Interrupt
lypinator	0:bb348c97df44	436	* @{
lypinator	0:bb348c97df44	437	*/
lypinator	0:bb348c97df44	438	#define SDIO_WAIT_NO 0x00000000U
lypinator	0:bb348c97df44	439	#define SDIO_WAIT_IT SDIO_CMD_WAITINT
lypinator	0:bb348c97df44	440	#define SDIO_WAIT_PEND SDIO_CMD_WAITPEND
lypinator	0:bb348c97df44	441
lypinator	0:bb348c97df44	442	#define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_WAIT_NO) \|\| \
lypinator	0:bb348c97df44	443	((WAIT) == SDIO_WAIT_IT) \|\| \
lypinator	0:bb348c97df44	444	((WAIT) == SDIO_WAIT_PEND))
lypinator	0:bb348c97df44	445	/**
lypinator	0:bb348c97df44	446	* @}
lypinator	0:bb348c97df44	447	*/
lypinator	0:bb348c97df44	448
lypinator	0:bb348c97df44	449	/** @defgroup SDIO_LL_CPSM_State CPSM State
lypinator	0:bb348c97df44	450	* @{
lypinator	0:bb348c97df44	451	*/
lypinator	0:bb348c97df44	452	#define SDIO_CPSM_DISABLE 0x00000000U
lypinator	0:bb348c97df44	453	#define SDIO_CPSM_ENABLE SDIO_CMD_CPSMEN
lypinator	0:bb348c97df44	454
lypinator	0:bb348c97df44	455	#define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_DISABLE) \|\| \
lypinator	0:bb348c97df44	456	((CPSM) == SDIO_CPSM_ENABLE))
lypinator	0:bb348c97df44	457	/**
lypinator	0:bb348c97df44	458	* @}
lypinator	0:bb348c97df44	459	*/
lypinator	0:bb348c97df44	460
lypinator	0:bb348c97df44	461	/** @defgroup SDIO_LL_Response_Registers Response Register
lypinator	0:bb348c97df44	462	* @{
lypinator	0:bb348c97df44	463	*/
lypinator	0:bb348c97df44	464	#define SDIO_RESP1 0x00000000U
lypinator	0:bb348c97df44	465	#define SDIO_RESP2 0x00000004U
lypinator	0:bb348c97df44	466	#define SDIO_RESP3 0x00000008U
lypinator	0:bb348c97df44	467	#define SDIO_RESP4 0x0000000CU
lypinator	0:bb348c97df44	468
lypinator	0:bb348c97df44	469	#define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) \|\| \
lypinator	0:bb348c97df44	470	((RESP) == SDIO_RESP2) \|\| \
lypinator	0:bb348c97df44	471	((RESP) == SDIO_RESP3) \|\| \
lypinator	0:bb348c97df44	472	((RESP) == SDIO_RESP4))
lypinator	0:bb348c97df44	473	/**
lypinator	0:bb348c97df44	474	* @}
lypinator	0:bb348c97df44	475	*/
lypinator	0:bb348c97df44	476
lypinator	0:bb348c97df44	477	/** @defgroup SDIO_LL_Data_Length Data Lenght
lypinator	0:bb348c97df44	478	* @{
lypinator	0:bb348c97df44	479	*/
lypinator	0:bb348c97df44	480	#define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFFU)
lypinator	0:bb348c97df44	481	/**
lypinator	0:bb348c97df44	482	* @}
lypinator	0:bb348c97df44	483	*/
lypinator	0:bb348c97df44	484
lypinator	0:bb348c97df44	485	/** @defgroup SDIO_LL_Data_Block_Size Data Block Size
lypinator	0:bb348c97df44	486	* @{
lypinator	0:bb348c97df44	487	*/
lypinator	0:bb348c97df44	488	#define SDIO_DATABLOCK_SIZE_1B 0x00000000U
lypinator	0:bb348c97df44	489	#define SDIO_DATABLOCK_SIZE_2B SDIO_DCTRL_DBLOCKSIZE_0
lypinator	0:bb348c97df44	490	#define SDIO_DATABLOCK_SIZE_4B SDIO_DCTRL_DBLOCKSIZE_1
lypinator	0:bb348c97df44	491	#define SDIO_DATABLOCK_SIZE_8B (SDIO_DCTRL_DBLOCKSIZE_0\|SDIO_DCTRL_DBLOCKSIZE_1)
lypinator	0:bb348c97df44	492	#define SDIO_DATABLOCK_SIZE_16B SDIO_DCTRL_DBLOCKSIZE_2
lypinator	0:bb348c97df44	493	#define SDIO_DATABLOCK_SIZE_32B (SDIO_DCTRL_DBLOCKSIZE_0\|SDIO_DCTRL_DBLOCKSIZE_2)
lypinator	0:bb348c97df44	494	#define SDIO_DATABLOCK_SIZE_64B (SDIO_DCTRL_DBLOCKSIZE_1\|SDIO_DCTRL_DBLOCKSIZE_2)
lypinator	0:bb348c97df44	495	#define SDIO_DATABLOCK_SIZE_128B (SDIO_DCTRL_DBLOCKSIZE_0\|SDIO_DCTRL_DBLOCKSIZE_1\|SDIO_DCTRL_DBLOCKSIZE_2)
lypinator	0:bb348c97df44	496	#define SDIO_DATABLOCK_SIZE_256B SDIO_DCTRL_DBLOCKSIZE_3
lypinator	0:bb348c97df44	497	#define SDIO_DATABLOCK_SIZE_512B (SDIO_DCTRL_DBLOCKSIZE_0\|SDIO_DCTRL_DBLOCKSIZE_3)
lypinator	0:bb348c97df44	498	#define SDIO_DATABLOCK_SIZE_1024B (SDIO_DCTRL_DBLOCKSIZE_1\|SDIO_DCTRL_DBLOCKSIZE_3)
lypinator	0:bb348c97df44	499	#define SDIO_DATABLOCK_SIZE_2048B (SDIO_DCTRL_DBLOCKSIZE_0\|SDIO_DCTRL_DBLOCKSIZE_1\|SDIO_DCTRL_DBLOCKSIZE_3)
lypinator	0:bb348c97df44	500	#define SDIO_DATABLOCK_SIZE_4096B (SDIO_DCTRL_DBLOCKSIZE_2\|SDIO_DCTRL_DBLOCKSIZE_3)
lypinator	0:bb348c97df44	501	#define SDIO_DATABLOCK_SIZE_8192B (SDIO_DCTRL_DBLOCKSIZE_0\|SDIO_DCTRL_DBLOCKSIZE_2\|SDIO_DCTRL_DBLOCKSIZE_3)
lypinator	0:bb348c97df44	502	#define SDIO_DATABLOCK_SIZE_16384B (SDIO_DCTRL_DBLOCKSIZE_1\|SDIO_DCTRL_DBLOCKSIZE_2\|SDIO_DCTRL_DBLOCKSIZE_3)
lypinator	0:bb348c97df44	503
lypinator	0:bb348c97df44	504	#define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DATABLOCK_SIZE_1B) \|\| \
lypinator	0:bb348c97df44	505	((SIZE) == SDIO_DATABLOCK_SIZE_2B) \|\| \
lypinator	0:bb348c97df44	506	((SIZE) == SDIO_DATABLOCK_SIZE_4B) \|\| \
lypinator	0:bb348c97df44	507	((SIZE) == SDIO_DATABLOCK_SIZE_8B) \|\| \
lypinator	0:bb348c97df44	508	((SIZE) == SDIO_DATABLOCK_SIZE_16B) \|\| \
lypinator	0:bb348c97df44	509	((SIZE) == SDIO_DATABLOCK_SIZE_32B) \|\| \
lypinator	0:bb348c97df44	510	((SIZE) == SDIO_DATABLOCK_SIZE_64B) \|\| \
lypinator	0:bb348c97df44	511	((SIZE) == SDIO_DATABLOCK_SIZE_128B) \|\| \
lypinator	0:bb348c97df44	512	((SIZE) == SDIO_DATABLOCK_SIZE_256B) \|\| \
lypinator	0:bb348c97df44	513	((SIZE) == SDIO_DATABLOCK_SIZE_512B) \|\| \
lypinator	0:bb348c97df44	514	((SIZE) == SDIO_DATABLOCK_SIZE_1024B) \|\| \
lypinator	0:bb348c97df44	515	((SIZE) == SDIO_DATABLOCK_SIZE_2048B) \|\| \
lypinator	0:bb348c97df44	516	((SIZE) == SDIO_DATABLOCK_SIZE_4096B) \|\| \
lypinator	0:bb348c97df44	517	((SIZE) == SDIO_DATABLOCK_SIZE_8192B) \|\| \
lypinator	0:bb348c97df44	518	((SIZE) == SDIO_DATABLOCK_SIZE_16384B))
lypinator	0:bb348c97df44	519	/**
lypinator	0:bb348c97df44	520	* @}
lypinator	0:bb348c97df44	521	*/
lypinator	0:bb348c97df44	522
lypinator	0:bb348c97df44	523	/** @defgroup SDIO_LL_Transfer_Direction Transfer Direction
lypinator	0:bb348c97df44	524	* @{
lypinator	0:bb348c97df44	525	*/
lypinator	0:bb348c97df44	526	#define SDIO_TRANSFER_DIR_TO_CARD 0x00000000U
lypinator	0:bb348c97df44	527	#define SDIO_TRANSFER_DIR_TO_SDIO SDIO_DCTRL_DTDIR
lypinator	0:bb348c97df44	528
lypinator	0:bb348c97df44	529	#define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TRANSFER_DIR_TO_CARD) \|\| \
lypinator	0:bb348c97df44	530	((DIR) == SDIO_TRANSFER_DIR_TO_SDIO))
lypinator	0:bb348c97df44	531	/**
lypinator	0:bb348c97df44	532	* @}
lypinator	0:bb348c97df44	533	*/
lypinator	0:bb348c97df44	534
lypinator	0:bb348c97df44	535	/** @defgroup SDIO_LL_Transfer_Type Transfer Type
lypinator	0:bb348c97df44	536	* @{
lypinator	0:bb348c97df44	537	*/
lypinator	0:bb348c97df44	538	#define SDIO_TRANSFER_MODE_BLOCK 0x00000000U
lypinator	0:bb348c97df44	539	#define SDIO_TRANSFER_MODE_STREAM SDIO_DCTRL_DTMODE
lypinator	0:bb348c97df44	540
lypinator	0:bb348c97df44	541	#define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TRANSFER_MODE_BLOCK) \|\| \
lypinator	0:bb348c97df44	542	((MODE) == SDIO_TRANSFER_MODE_STREAM))
lypinator	0:bb348c97df44	543	/**
lypinator	0:bb348c97df44	544	* @}
lypinator	0:bb348c97df44	545	*/
lypinator	0:bb348c97df44	546
lypinator	0:bb348c97df44	547	/** @defgroup SDIO_LL_DPSM_State DPSM State
lypinator	0:bb348c97df44	548	* @{
lypinator	0:bb348c97df44	549	*/
lypinator	0:bb348c97df44	550	#define SDIO_DPSM_DISABLE 0x00000000U
lypinator	0:bb348c97df44	551	#define SDIO_DPSM_ENABLE SDIO_DCTRL_DTEN
lypinator	0:bb348c97df44	552
lypinator	0:bb348c97df44	553	#define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_DISABLE) \|\|\
lypinator	0:bb348c97df44	554	((DPSM) == SDIO_DPSM_ENABLE))
lypinator	0:bb348c97df44	555	/**
lypinator	0:bb348c97df44	556	* @}
lypinator	0:bb348c97df44	557	*/
lypinator	0:bb348c97df44	558
lypinator	0:bb348c97df44	559	/** @defgroup SDIO_LL_Read_Wait_Mode Read Wait Mode
lypinator	0:bb348c97df44	560	* @{
lypinator	0:bb348c97df44	561	*/
lypinator	0:bb348c97df44	562	#define SDIO_READ_WAIT_MODE_DATA2 0x00000000U
lypinator	0:bb348c97df44	563	#define SDIO_READ_WAIT_MODE_CLK (SDIO_DCTRL_RWMOD)
lypinator	0:bb348c97df44	564
lypinator	0:bb348c97df44	565	#define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_READ_WAIT_MODE_CLK) \|\| \
lypinator	0:bb348c97df44	566	((MODE) == SDIO_READ_WAIT_MODE_DATA2))
lypinator	0:bb348c97df44	567	/**
lypinator	0:bb348c97df44	568	* @}
lypinator	0:bb348c97df44	569	*/
lypinator	0:bb348c97df44	570
lypinator	0:bb348c97df44	571	/** @defgroup SDIO_LL_Interrupt_sources Interrupt Sources
lypinator	0:bb348c97df44	572	* @{
lypinator	0:bb348c97df44	573	*/
lypinator	0:bb348c97df44	574	#define SDIO_IT_CCRCFAIL SDIO_STA_CCRCFAIL
lypinator	0:bb348c97df44	575	#define SDIO_IT_DCRCFAIL SDIO_STA_DCRCFAIL
lypinator	0:bb348c97df44	576	#define SDIO_IT_CTIMEOUT SDIO_STA_CTIMEOUT
lypinator	0:bb348c97df44	577	#define SDIO_IT_DTIMEOUT SDIO_STA_DTIMEOUT
lypinator	0:bb348c97df44	578	#define SDIO_IT_TXUNDERR SDIO_STA_TXUNDERR
lypinator	0:bb348c97df44	579	#define SDIO_IT_RXOVERR SDIO_STA_RXOVERR
lypinator	0:bb348c97df44	580	#define SDIO_IT_CMDREND SDIO_STA_CMDREND
lypinator	0:bb348c97df44	581	#define SDIO_IT_CMDSENT SDIO_STA_CMDSENT
lypinator	0:bb348c97df44	582	#define SDIO_IT_DATAEND SDIO_STA_DATAEND
lypinator	0:bb348c97df44	583	#define SDIO_IT_STBITERR SDIO_STA_STBITERR
lypinator	0:bb348c97df44	584	#define SDIO_IT_DBCKEND SDIO_STA_DBCKEND
lypinator	0:bb348c97df44	585	#define SDIO_IT_CMDACT SDIO_STA_CMDACT
lypinator	0:bb348c97df44	586	#define SDIO_IT_TXACT SDIO_STA_TXACT
lypinator	0:bb348c97df44	587	#define SDIO_IT_RXACT SDIO_STA_RXACT
lypinator	0:bb348c97df44	588	#define SDIO_IT_TXFIFOHE SDIO_STA_TXFIFOHE
lypinator	0:bb348c97df44	589	#define SDIO_IT_RXFIFOHF SDIO_STA_RXFIFOHF
lypinator	0:bb348c97df44	590	#define SDIO_IT_TXFIFOF SDIO_STA_TXFIFOF
lypinator	0:bb348c97df44	591	#define SDIO_IT_RXFIFOF SDIO_STA_RXFIFOF
lypinator	0:bb348c97df44	592	#define SDIO_IT_TXFIFOE SDIO_STA_TXFIFOE
lypinator	0:bb348c97df44	593	#define SDIO_IT_RXFIFOE SDIO_STA_RXFIFOE
lypinator	0:bb348c97df44	594	#define SDIO_IT_TXDAVL SDIO_STA_TXDAVL
lypinator	0:bb348c97df44	595	#define SDIO_IT_RXDAVL SDIO_STA_RXDAVL
lypinator	0:bb348c97df44	596	#define SDIO_IT_SDIOIT SDIO_STA_SDIOIT
lypinator	0:bb348c97df44	597	#define SDIO_IT_CEATAEND SDIO_STA_CEATAEND
lypinator	0:bb348c97df44	598	/**
lypinator	0:bb348c97df44	599	* @}
lypinator	0:bb348c97df44	600	*/
lypinator	0:bb348c97df44	601
lypinator	0:bb348c97df44	602	/** @defgroup SDIO_LL_Flags Flags
lypinator	0:bb348c97df44	603	* @{
lypinator	0:bb348c97df44	604	*/
lypinator	0:bb348c97df44	605	#define SDIO_FLAG_CCRCFAIL SDIO_STA_CCRCFAIL
lypinator	0:bb348c97df44	606	#define SDIO_FLAG_DCRCFAIL SDIO_STA_DCRCFAIL
lypinator	0:bb348c97df44	607	#define SDIO_FLAG_CTIMEOUT SDIO_STA_CTIMEOUT
lypinator	0:bb348c97df44	608	#define SDIO_FLAG_DTIMEOUT SDIO_STA_DTIMEOUT
lypinator	0:bb348c97df44	609	#define SDIO_FLAG_TXUNDERR SDIO_STA_TXUNDERR
lypinator	0:bb348c97df44	610	#define SDIO_FLAG_RXOVERR SDIO_STA_RXOVERR
lypinator	0:bb348c97df44	611	#define SDIO_FLAG_CMDREND SDIO_STA_CMDREND
lypinator	0:bb348c97df44	612	#define SDIO_FLAG_CMDSENT SDIO_STA_CMDSENT
lypinator	0:bb348c97df44	613	#define SDIO_FLAG_DATAEND SDIO_STA_DATAEND
lypinator	0:bb348c97df44	614	#define SDIO_FLAG_STBITERR SDIO_STA_STBITERR
lypinator	0:bb348c97df44	615	#define SDIO_FLAG_DBCKEND SDIO_STA_DBCKEND
lypinator	0:bb348c97df44	616	#define SDIO_FLAG_CMDACT SDIO_STA_CMDACT
lypinator	0:bb348c97df44	617	#define SDIO_FLAG_TXACT SDIO_STA_TXACT
lypinator	0:bb348c97df44	618	#define SDIO_FLAG_RXACT SDIO_STA_RXACT
lypinator	0:bb348c97df44	619	#define SDIO_FLAG_TXFIFOHE SDIO_STA_TXFIFOHE
lypinator	0:bb348c97df44	620	#define SDIO_FLAG_RXFIFOHF SDIO_STA_RXFIFOHF
lypinator	0:bb348c97df44	621	#define SDIO_FLAG_TXFIFOF SDIO_STA_TXFIFOF
lypinator	0:bb348c97df44	622	#define SDIO_FLAG_RXFIFOF SDIO_STA_RXFIFOF
lypinator	0:bb348c97df44	623	#define SDIO_FLAG_TXFIFOE SDIO_STA_TXFIFOE
lypinator	0:bb348c97df44	624	#define SDIO_FLAG_RXFIFOE SDIO_STA_RXFIFOE
lypinator	0:bb348c97df44	625	#define SDIO_FLAG_TXDAVL SDIO_STA_TXDAVL
lypinator	0:bb348c97df44	626	#define SDIO_FLAG_RXDAVL SDIO_STA_RXDAVL
lypinator	0:bb348c97df44	627	#define SDIO_FLAG_SDIOIT SDIO_STA_SDIOIT
lypinator	0:bb348c97df44	628	#define SDIO_FLAG_CEATAEND SDIO_STA_CEATAEND
lypinator	0:bb348c97df44	629	#define SDIO_STATIC_FLAGS ((uint32_t)(SDIO_FLAG_CCRCFAIL \| SDIO_FLAG_DCRCFAIL \| SDIO_FLAG_CTIMEOUT \|\
lypinator	0:bb348c97df44	630	SDIO_FLAG_DTIMEOUT \| SDIO_FLAG_TXUNDERR \| SDIO_FLAG_RXOVERR \|\
lypinator	0:bb348c97df44	631	SDIO_FLAG_CMDREND \| SDIO_FLAG_CMDSENT \| SDIO_FLAG_DATAEND \|\
lypinator	0:bb348c97df44	632	SDIO_FLAG_DBCKEND))
lypinator	0:bb348c97df44	633	/**
lypinator	0:bb348c97df44	634	* @}
lypinator	0:bb348c97df44	635	*/
lypinator	0:bb348c97df44	636
lypinator	0:bb348c97df44	637	/**
lypinator	0:bb348c97df44	638	* @}
lypinator	0:bb348c97df44	639	*/
lypinator	0:bb348c97df44	640
lypinator	0:bb348c97df44	641	/* Exported macro ------------------------------------------------------------*/
lypinator	0:bb348c97df44	642	/** @defgroup SDIO_LL_Exported_macros SDIO_LL Exported Macros
lypinator	0:bb348c97df44	643	* @{
lypinator	0:bb348c97df44	644	*/
lypinator	0:bb348c97df44	645
lypinator	0:bb348c97df44	646	/** @defgroup SDMMC_LL_Alias_Region Bit Address in the alias region
lypinator	0:bb348c97df44	647	* @{
lypinator	0:bb348c97df44	648	*/
lypinator	0:bb348c97df44	649	/* ------------ SDIO registers bit address in the alias region -------------- */
lypinator	0:bb348c97df44	650	#define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE)
lypinator	0:bb348c97df44	651
lypinator	0:bb348c97df44	652	/* --- CLKCR Register ---*/
lypinator	0:bb348c97df44	653	/* Alias word address of CLKEN bit */
lypinator	0:bb348c97df44	654	#define CLKCR_OFFSET (SDIO_OFFSET + 0x04U)
lypinator	0:bb348c97df44	655	#define CLKEN_BITNUMBER 0x08U
lypinator	0:bb348c97df44	656	#define CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32U) + (CLKEN_BITNUMBER * 4U))
lypinator	0:bb348c97df44	657
lypinator	0:bb348c97df44	658	/* --- CMD Register ---*/
lypinator	0:bb348c97df44	659	/* Alias word address of SDIOSUSPEND bit */
lypinator	0:bb348c97df44	660	#define CMD_OFFSET (SDIO_OFFSET + 0x0CU)
lypinator	0:bb348c97df44	661	#define SDIOSUSPEND_BITNUMBER 0x0BU
lypinator	0:bb348c97df44	662	#define CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (SDIOSUSPEND_BITNUMBER * 4U))
lypinator	0:bb348c97df44	663
lypinator	0:bb348c97df44	664	/* Alias word address of ENCMDCOMPL bit */
lypinator	0:bb348c97df44	665	#define ENCMDCOMPL_BITNUMBER 0x0CU
lypinator	0:bb348c97df44	666	#define CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (ENCMDCOMPL_BITNUMBER * 4U))
lypinator	0:bb348c97df44	667
lypinator	0:bb348c97df44	668	/* Alias word address of NIEN bit */
lypinator	0:bb348c97df44	669	#define NIEN_BITNUMBER 0x0DU
lypinator	0:bb348c97df44	670	#define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (NIEN_BITNUMBER * 4U))
lypinator	0:bb348c97df44	671
lypinator	0:bb348c97df44	672	/* Alias word address of ATACMD bit */
lypinator	0:bb348c97df44	673	#define ATACMD_BITNUMBER 0x0EU
lypinator	0:bb348c97df44	674	#define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (ATACMD_BITNUMBER * 4U))
lypinator	0:bb348c97df44	675
lypinator	0:bb348c97df44	676	/* --- DCTRL Register ---*/
lypinator	0:bb348c97df44	677	/* Alias word address of DMAEN bit */
lypinator	0:bb348c97df44	678	#define DCTRL_OFFSET (SDIO_OFFSET + 0x2CU)
lypinator	0:bb348c97df44	679	#define DMAEN_BITNUMBER 0x03U
lypinator	0:bb348c97df44	680	#define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (DMAEN_BITNUMBER * 4U))
lypinator	0:bb348c97df44	681
lypinator	0:bb348c97df44	682	/* Alias word address of RWSTART bit */
lypinator	0:bb348c97df44	683	#define RWSTART_BITNUMBER 0x08U
lypinator	0:bb348c97df44	684	#define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (RWSTART_BITNUMBER * 4U))
lypinator	0:bb348c97df44	685
lypinator	0:bb348c97df44	686	/* Alias word address of RWSTOP bit */
lypinator	0:bb348c97df44	687	#define RWSTOP_BITNUMBER 0x09U
lypinator	0:bb348c97df44	688	#define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (RWSTOP_BITNUMBER * 4U))
lypinator	0:bb348c97df44	689
lypinator	0:bb348c97df44	690	/* Alias word address of RWMOD bit */
lypinator	0:bb348c97df44	691	#define RWMOD_BITNUMBER 0x0AU
lypinator	0:bb348c97df44	692	#define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (RWMOD_BITNUMBER * 4U))
lypinator	0:bb348c97df44	693
lypinator	0:bb348c97df44	694	/* Alias word address of SDIOEN bit */
lypinator	0:bb348c97df44	695	#define SDIOEN_BITNUMBER 0x0BU
lypinator	0:bb348c97df44	696	#define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (SDIOEN_BITNUMBER * 4U))
lypinator	0:bb348c97df44	697	/**
lypinator	0:bb348c97df44	698	* @}
lypinator	0:bb348c97df44	699	*/
lypinator	0:bb348c97df44	700
lypinator	0:bb348c97df44	701	/** @defgroup SDIO_LL_Register Bits And Addresses Definitions
lypinator	0:bb348c97df44	702	* @brief SDIO_LL registers bit address in the alias region
lypinator	0:bb348c97df44	703	* @{
lypinator	0:bb348c97df44	704	*/
lypinator	0:bb348c97df44	705	/* ---------------------- SDIO registers bit mask --------------------------- */
lypinator	0:bb348c97df44	706	/* --- CLKCR Register ---*/
lypinator	0:bb348c97df44	707	/* CLKCR register clear mask */
lypinator	0:bb348c97df44	708	#define CLKCR_CLEAR_MASK ((uint32_t)(SDIO_CLKCR_CLKDIV \| SDIO_CLKCR_PWRSAV \|\
lypinator	0:bb348c97df44	709	SDIO_CLKCR_BYPASS \| SDIO_CLKCR_WIDBUS \|\
lypinator	0:bb348c97df44	710	SDIO_CLKCR_NEGEDGE \| SDIO_CLKCR_HWFC_EN))
lypinator	0:bb348c97df44	711
lypinator	0:bb348c97df44	712	/* --- DCTRL Register ---*/
lypinator	0:bb348c97df44	713	/* SDIO DCTRL Clear Mask */
lypinator	0:bb348c97df44	714	#define DCTRL_CLEAR_MASK ((uint32_t)(SDIO_DCTRL_DTEN \| SDIO_DCTRL_DTDIR \|\
lypinator	0:bb348c97df44	715	SDIO_DCTRL_DTMODE \| SDIO_DCTRL_DBLOCKSIZE))
lypinator	0:bb348c97df44	716
lypinator	0:bb348c97df44	717	/* --- CMD Register ---*/
lypinator	0:bb348c97df44	718	/* CMD Register clear mask */
lypinator	0:bb348c97df44	719	#define CMD_CLEAR_MASK ((uint32_t)(SDIO_CMD_CMDINDEX \| SDIO_CMD_WAITRESP \|\
lypinator	0:bb348c97df44	720	SDIO_CMD_WAITINT \| SDIO_CMD_WAITPEND \|\
lypinator	0:bb348c97df44	721	SDIO_CMD_CPSMEN \| SDIO_CMD_SDIOSUSPEND))
lypinator	0:bb348c97df44	722
lypinator	0:bb348c97df44	723	/* SDIO Initialization Frequency (400KHz max) */
lypinator	0:bb348c97df44	724	#define SDIO_INIT_CLK_DIV ((uint8_t)0x76)
lypinator	0:bb348c97df44	725
lypinator	0:bb348c97df44	726	/* SDIO Data Transfer Frequency (25MHz max) */
lypinator	0:bb348c97df44	727	#define SDIO_TRANSFER_CLK_DIV ((uint8_t)0x0)
lypinator	0:bb348c97df44	728
lypinator	0:bb348c97df44	729	/**
lypinator	0:bb348c97df44	730	* @}
lypinator	0:bb348c97df44	731	*/
lypinator	0:bb348c97df44	732
lypinator	0:bb348c97df44	733	/** @defgroup SDIO_LL_Interrupt_Clock Interrupt And Clock Configuration
lypinator	0:bb348c97df44	734	* @brief macros to handle interrupts and specific clock configurations
lypinator	0:bb348c97df44	735	* @{
lypinator	0:bb348c97df44	736	*/
lypinator	0:bb348c97df44	737
lypinator	0:bb348c97df44	738	/**
lypinator	0:bb348c97df44	739	* @brief Enable the SDIO device.
lypinator	0:bb348c97df44	740	* @param __INSTANCE__ SDIO Instance
lypinator	0:bb348c97df44	741	* @retval None
lypinator	0:bb348c97df44	742	*/
lypinator	0:bb348c97df44	743	#define __SDIO_ENABLE(__INSTANCE__) ((__IO uint32_t )CLKCR_CLKEN_BB = ENABLE)
lypinator	0:bb348c97df44	744
lypinator	0:bb348c97df44	745	/**
lypinator	0:bb348c97df44	746	* @brief Disable the SDIO device.
lypinator	0:bb348c97df44	747	* @param __INSTANCE__ SDIO Instance
lypinator	0:bb348c97df44	748	* @retval None
lypinator	0:bb348c97df44	749	*/
lypinator	0:bb348c97df44	750	#define __SDIO_DISABLE(__INSTANCE__) ((__IO uint32_t )CLKCR_CLKEN_BB = DISABLE)
lypinator	0:bb348c97df44	751
lypinator	0:bb348c97df44	752	/**
lypinator	0:bb348c97df44	753	* @brief Enable the SDIO DMA transfer.
lypinator	0:bb348c97df44	754	* @param __INSTANCE__ SDIO Instance
lypinator	0:bb348c97df44	755	* @retval None
lypinator	0:bb348c97df44	756	*/
lypinator	0:bb348c97df44	757	#define __SDIO_DMA_ENABLE(__INSTANCE__) ((__IO uint32_t )DCTRL_DMAEN_BB = ENABLE)
lypinator	0:bb348c97df44	758	/**
lypinator	0:bb348c97df44	759	* @brief Disable the SDIO DMA transfer.
lypinator	0:bb348c97df44	760	* @param __INSTANCE__ SDIO Instance
lypinator	0:bb348c97df44	761	* @retval None
lypinator	0:bb348c97df44	762	*/
lypinator	0:bb348c97df44	763	#define __SDIO_DMA_DISABLE(__INSTANCE__) ((__IO uint32_t )DCTRL_DMAEN_BB = DISABLE)
lypinator	0:bb348c97df44	764
lypinator	0:bb348c97df44	765	/**
lypinator	0:bb348c97df44	766	* @brief Enable the SDIO device interrupt.
lypinator	0:bb348c97df44	767	* @param __INSTANCE__ Pointer to SDIO register base
lypinator	0:bb348c97df44	768	* @param __INTERRUPT__ specifies the SDIO interrupt sources to be enabled.
lypinator	0:bb348c97df44	769	* This parameter can be one or a combination of the following values:
lypinator	0:bb348c97df44	770	* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
lypinator	0:bb348c97df44	771	* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
lypinator	0:bb348c97df44	772	* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
lypinator	0:bb348c97df44	773	* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
lypinator	0:bb348c97df44	774	* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
lypinator	0:bb348c97df44	775	* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
lypinator	0:bb348c97df44	776	* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
lypinator	0:bb348c97df44	777	* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
lypinator	0:bb348c97df44	778	* @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
lypinator	0:bb348c97df44	779	* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
lypinator	0:bb348c97df44	780	* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
lypinator	0:bb348c97df44	781	* @arg SDIO_IT_TXACT: Data transmit in progress interrupt
lypinator	0:bb348c97df44	782	* @arg SDIO_IT_RXACT: Data receive in progress interrupt
lypinator	0:bb348c97df44	783	* @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
lypinator	0:bb348c97df44	784	* @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
lypinator	0:bb348c97df44	785	* @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
lypinator	0:bb348c97df44	786	* @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
lypinator	0:bb348c97df44	787	* @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
lypinator	0:bb348c97df44	788	* @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
lypinator	0:bb348c97df44	789	* @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
lypinator	0:bb348c97df44	790	* @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
lypinator	0:bb348c97df44	791	* @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
lypinator	0:bb348c97df44	792	* @retval None
lypinator	0:bb348c97df44	793	*/
lypinator	0:bb348c97df44	794	#define __SDIO_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK \|= (__INTERRUPT__))
lypinator	0:bb348c97df44	795
lypinator	0:bb348c97df44	796	/**
lypinator	0:bb348c97df44	797	* @brief Disable the SDIO device interrupt.
lypinator	0:bb348c97df44	798	* @param __INSTANCE__ Pointer to SDIO register base
lypinator	0:bb348c97df44	799	* @param __INTERRUPT__ specifies the SDIO interrupt sources to be disabled.
lypinator	0:bb348c97df44	800	* This parameter can be one or a combination of the following values:
lypinator	0:bb348c97df44	801	* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
lypinator	0:bb348c97df44	802	* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
lypinator	0:bb348c97df44	803	* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
lypinator	0:bb348c97df44	804	* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
lypinator	0:bb348c97df44	805	* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
lypinator	0:bb348c97df44	806	* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
lypinator	0:bb348c97df44	807	* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
lypinator	0:bb348c97df44	808	* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
lypinator	0:bb348c97df44	809	* @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
lypinator	0:bb348c97df44	810	* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
lypinator	0:bb348c97df44	811	* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
lypinator	0:bb348c97df44	812	* @arg SDIO_IT_TXACT: Data transmit in progress interrupt
lypinator	0:bb348c97df44	813	* @arg SDIO_IT_RXACT: Data receive in progress interrupt
lypinator	0:bb348c97df44	814	* @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
lypinator	0:bb348c97df44	815	* @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
lypinator	0:bb348c97df44	816	* @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
lypinator	0:bb348c97df44	817	* @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
lypinator	0:bb348c97df44	818	* @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
lypinator	0:bb348c97df44	819	* @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
lypinator	0:bb348c97df44	820	* @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
lypinator	0:bb348c97df44	821	* @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
lypinator	0:bb348c97df44	822	* @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
lypinator	0:bb348c97df44	823	* @retval None
lypinator	0:bb348c97df44	824	*/
lypinator	0:bb348c97df44	825	#define __SDIO_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK &= ~(__INTERRUPT__))
lypinator	0:bb348c97df44	826
lypinator	0:bb348c97df44	827	/**
lypinator	0:bb348c97df44	828	* @brief Checks whether the specified SDIO flag is set or not.
lypinator	0:bb348c97df44	829	* @param __INSTANCE__ Pointer to SDIO register base
lypinator	0:bb348c97df44	830	* @param __FLAG__ specifies the flag to check.
lypinator	0:bb348c97df44	831	* This parameter can be one of the following values:
lypinator	0:bb348c97df44	832	* @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
lypinator	0:bb348c97df44	833	* @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
lypinator	0:bb348c97df44	834	* @arg SDIO_FLAG_CTIMEOUT: Command response timeout
lypinator	0:bb348c97df44	835	* @arg SDIO_FLAG_DTIMEOUT: Data timeout
lypinator	0:bb348c97df44	836	* @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
lypinator	0:bb348c97df44	837	* @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
lypinator	0:bb348c97df44	838	* @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
lypinator	0:bb348c97df44	839	* @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
lypinator	0:bb348c97df44	840	* @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
lypinator	0:bb348c97df44	841	* @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
lypinator	0:bb348c97df44	842	* @arg SDIO_FLAG_CMDACT: Command transfer in progress
lypinator	0:bb348c97df44	843	* @arg SDIO_FLAG_TXACT: Data transmit in progress
lypinator	0:bb348c97df44	844	* @arg SDIO_FLAG_RXACT: Data receive in progress
lypinator	0:bb348c97df44	845	* @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty
lypinator	0:bb348c97df44	846	* @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full
lypinator	0:bb348c97df44	847	* @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full
lypinator	0:bb348c97df44	848	* @arg SDIO_FLAG_RXFIFOF: Receive FIFO full
lypinator	0:bb348c97df44	849	* @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty
lypinator	0:bb348c97df44	850	* @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty
lypinator	0:bb348c97df44	851	* @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO
lypinator	0:bb348c97df44	852	* @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO
lypinator	0:bb348c97df44	853	* @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
lypinator	0:bb348c97df44	854	* @retval The new state of SDIO_FLAG (SET or RESET).
lypinator	0:bb348c97df44	855	*/
lypinator	0:bb348c97df44	856	#define __SDIO_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != RESET)
lypinator	0:bb348c97df44	857
lypinator	0:bb348c97df44	858
lypinator	0:bb348c97df44	859	/**
lypinator	0:bb348c97df44	860	* @brief Clears the SDIO pending flags.
lypinator	0:bb348c97df44	861	* @param __INSTANCE__ Pointer to SDIO register base
lypinator	0:bb348c97df44	862	* @param __FLAG__ specifies the flag to clear.
lypinator	0:bb348c97df44	863	* This parameter can be one or a combination of the following values:
lypinator	0:bb348c97df44	864	* @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
lypinator	0:bb348c97df44	865	* @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
lypinator	0:bb348c97df44	866	* @arg SDIO_FLAG_CTIMEOUT: Command response timeout
lypinator	0:bb348c97df44	867	* @arg SDIO_FLAG_DTIMEOUT: Data timeout
lypinator	0:bb348c97df44	868	* @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
lypinator	0:bb348c97df44	869	* @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
lypinator	0:bb348c97df44	870	* @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
lypinator	0:bb348c97df44	871	* @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
lypinator	0:bb348c97df44	872	* @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
lypinator	0:bb348c97df44	873	* @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
lypinator	0:bb348c97df44	874	* @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
lypinator	0:bb348c97df44	875	* @retval None
lypinator	0:bb348c97df44	876	*/
lypinator	0:bb348c97df44	877	#define __SDIO_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->ICR = (__FLAG__))
lypinator	0:bb348c97df44	878
lypinator	0:bb348c97df44	879	/**
lypinator	0:bb348c97df44	880	* @brief Checks whether the specified SDIO interrupt has occurred or not.
lypinator	0:bb348c97df44	881	* @param __INSTANCE__ Pointer to SDIO register base
lypinator	0:bb348c97df44	882	* @param __INTERRUPT__ specifies the SDIO interrupt source to check.
lypinator	0:bb348c97df44	883	* This parameter can be one of the following values:
lypinator	0:bb348c97df44	884	* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
lypinator	0:bb348c97df44	885	* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
lypinator	0:bb348c97df44	886	* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
lypinator	0:bb348c97df44	887	* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
lypinator	0:bb348c97df44	888	* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
lypinator	0:bb348c97df44	889	* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
lypinator	0:bb348c97df44	890	* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
lypinator	0:bb348c97df44	891	* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
lypinator	0:bb348c97df44	892	* @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
lypinator	0:bb348c97df44	893	* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
lypinator	0:bb348c97df44	894	* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
lypinator	0:bb348c97df44	895	* @arg SDIO_IT_TXACT: Data transmit in progress interrupt
lypinator	0:bb348c97df44	896	* @arg SDIO_IT_RXACT: Data receive in progress interrupt
lypinator	0:bb348c97df44	897	* @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
lypinator	0:bb348c97df44	898	* @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
lypinator	0:bb348c97df44	899	* @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
lypinator	0:bb348c97df44	900	* @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
lypinator	0:bb348c97df44	901	* @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
lypinator	0:bb348c97df44	902	* @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
lypinator	0:bb348c97df44	903	* @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
lypinator	0:bb348c97df44	904	* @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
lypinator	0:bb348c97df44	905	* @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
lypinator	0:bb348c97df44	906	* @retval The new state of SDIO_IT (SET or RESET).
lypinator	0:bb348c97df44	907	*/
lypinator	0:bb348c97df44	908	#define __SDIO_GET_IT (__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__))
lypinator	0:bb348c97df44	909
lypinator	0:bb348c97df44	910	/**
lypinator	0:bb348c97df44	911	* @brief Clears the SDIO's interrupt pending bits.
lypinator	0:bb348c97df44	912	* @param __INSTANCE__ Pointer to SDIO register base
lypinator	0:bb348c97df44	913	* @param __INTERRUPT__ specifies the interrupt pending bit to clear.
lypinator	0:bb348c97df44	914	* This parameter can be one or a combination of the following values:
lypinator	0:bb348c97df44	915	* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
lypinator	0:bb348c97df44	916	* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
lypinator	0:bb348c97df44	917	* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
lypinator	0:bb348c97df44	918	* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
lypinator	0:bb348c97df44	919	* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
lypinator	0:bb348c97df44	920	* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
lypinator	0:bb348c97df44	921	* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
lypinator	0:bb348c97df44	922	* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
lypinator	0:bb348c97df44	923	* @arg SDIO_IT_DATAEND: Data end (data counter, SDIO_DCOUNT, is zero) interrupt
lypinator	0:bb348c97df44	924	* @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
lypinator	0:bb348c97df44	925	* @retval None
lypinator	0:bb348c97df44	926	*/
lypinator	0:bb348c97df44	927	#define __SDIO_CLEAR_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->ICR = (__INTERRUPT__))
lypinator	0:bb348c97df44	928
lypinator	0:bb348c97df44	929	/**
lypinator	0:bb348c97df44	930	* @brief Enable Start the SD I/O Read Wait operation.
lypinator	0:bb348c97df44	931	* @param __INSTANCE__ Pointer to SDIO register base
lypinator	0:bb348c97df44	932	* @retval None
lypinator	0:bb348c97df44	933	*/
lypinator	0:bb348c97df44	934	#define __SDIO_START_READWAIT_ENABLE(__INSTANCE__) ((__IO uint32_t ) DCTRL_RWSTART_BB = ENABLE)
lypinator	0:bb348c97df44	935
lypinator	0:bb348c97df44	936	/**
lypinator	0:bb348c97df44	937	* @brief Disable Start the SD I/O Read Wait operations.
lypinator	0:bb348c97df44	938	* @param __INSTANCE__ Pointer to SDIO register base
lypinator	0:bb348c97df44	939	* @retval None
lypinator	0:bb348c97df44	940	*/
lypinator	0:bb348c97df44	941	#define __SDIO_START_READWAIT_DISABLE(__INSTANCE__) ((__IO uint32_t ) DCTRL_RWSTART_BB = DISABLE)
lypinator	0:bb348c97df44	942
lypinator	0:bb348c97df44	943	/**
lypinator	0:bb348c97df44	944	* @brief Enable Start the SD I/O Read Wait operation.
lypinator	0:bb348c97df44	945	* @param __INSTANCE__ Pointer to SDIO register base
lypinator	0:bb348c97df44	946	* @retval None
lypinator	0:bb348c97df44	947	*/
lypinator	0:bb348c97df44	948	#define __SDIO_STOP_READWAIT_ENABLE(__INSTANCE__) ((__IO uint32_t ) DCTRL_RWSTOP_BB = ENABLE)
lypinator	0:bb348c97df44	949
lypinator	0:bb348c97df44	950	/**
lypinator	0:bb348c97df44	951	* @brief Disable Stop the SD I/O Read Wait operations.
lypinator	0:bb348c97df44	952	* @param __INSTANCE__ Pointer to SDIO register base
lypinator	0:bb348c97df44	953	* @retval None
lypinator	0:bb348c97df44	954	*/
lypinator	0:bb348c97df44	955	#define __SDIO_STOP_READWAIT_DISABLE(__INSTANCE__) ((__IO uint32_t ) DCTRL_RWSTOP_BB = DISABLE)
lypinator	0:bb348c97df44	956
lypinator	0:bb348c97df44	957	/**
lypinator	0:bb348c97df44	958	* @brief Enable the SD I/O Mode Operation.
lypinator	0:bb348c97df44	959	* @param __INSTANCE__ Pointer to SDIO register base
lypinator	0:bb348c97df44	960	* @retval None
lypinator	0:bb348c97df44	961	*/
lypinator	0:bb348c97df44	962	#define __SDIO_OPERATION_ENABLE(__INSTANCE__) ((__IO uint32_t ) DCTRL_SDIOEN_BB = ENABLE)
lypinator	0:bb348c97df44	963
lypinator	0:bb348c97df44	964	/**
lypinator	0:bb348c97df44	965	* @brief Disable the SD I/O Mode Operation.
lypinator	0:bb348c97df44	966	* @param __INSTANCE__ Pointer to SDIO register base
lypinator	0:bb348c97df44	967	* @retval None
lypinator	0:bb348c97df44	968	*/
lypinator	0:bb348c97df44	969	#define __SDIO_OPERATION_DISABLE(__INSTANCE__) ((__IO uint32_t ) DCTRL_SDIOEN_BB = DISABLE)
lypinator	0:bb348c97df44	970
lypinator	0:bb348c97df44	971	/**
lypinator	0:bb348c97df44	972	* @brief Enable the SD I/O Suspend command sending.
lypinator	0:bb348c97df44	973	* @param __INSTANCE__ Pointer to SDIO register base
lypinator	0:bb348c97df44	974	* @retval None
lypinator	0:bb348c97df44	975	*/
lypinator	0:bb348c97df44	976	#define __SDIO_SUSPEND_CMD_ENABLE(__INSTANCE__) ((__IO uint32_t ) CMD_SDIOSUSPEND_BB = ENABLE)
lypinator	0:bb348c97df44	977
lypinator	0:bb348c97df44	978	/**
lypinator	0:bb348c97df44	979	* @brief Disable the SD I/O Suspend command sending.
lypinator	0:bb348c97df44	980	* @param __INSTANCE__ Pointer to SDIO register base
lypinator	0:bb348c97df44	981	* @retval None
lypinator	0:bb348c97df44	982	*/
lypinator	0:bb348c97df44	983	#define __SDIO_SUSPEND_CMD_DISABLE(__INSTANCE__) ((__IO uint32_t ) CMD_SDIOSUSPEND_BB = DISABLE)
lypinator	0:bb348c97df44	984
lypinator	0:bb348c97df44	985	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\|\
lypinator	0:bb348c97df44	986	defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\|\
lypinator	0:bb348c97df44	987	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE)
lypinator	0:bb348c97df44	988	/**
lypinator	0:bb348c97df44	989	* @brief Enable the command completion signal.
lypinator	0:bb348c97df44	990	* @retval None
lypinator	0:bb348c97df44	991	*/
lypinator	0:bb348c97df44	992	#define __SDIO_CEATA_CMD_COMPLETION_ENABLE() ((__IO uint32_t ) CMD_ENCMDCOMPL_BB = ENABLE)
lypinator	0:bb348c97df44	993
lypinator	0:bb348c97df44	994	/**
lypinator	0:bb348c97df44	995	* @brief Disable the command completion signal.
lypinator	0:bb348c97df44	996	* @retval None
lypinator	0:bb348c97df44	997	*/
lypinator	0:bb348c97df44	998	#define __SDIO_CEATA_CMD_COMPLETION_DISABLE() ((__IO uint32_t ) CMD_ENCMDCOMPL_BB = DISABLE)
lypinator	0:bb348c97df44	999
lypinator	0:bb348c97df44	1000	/**
lypinator	0:bb348c97df44	1001	* @brief Enable the CE-ATA interrupt.
lypinator	0:bb348c97df44	1002	* @retval None
lypinator	0:bb348c97df44	1003	*/
lypinator	0:bb348c97df44	1004	#define __SDIO_CEATA_ENABLE_IT() ((__IO uint32_t ) CMD_NIEN_BB = (uint32_t)0U)
lypinator	0:bb348c97df44	1005
lypinator	0:bb348c97df44	1006	/**
lypinator	0:bb348c97df44	1007	* @brief Disable the CE-ATA interrupt.
lypinator	0:bb348c97df44	1008	* @retval None
lypinator	0:bb348c97df44	1009	*/
lypinator	0:bb348c97df44	1010	#define __SDIO_CEATA_DISABLE_IT() ((__IO uint32_t ) CMD_NIEN_BB = (uint32_t)1U)
lypinator	0:bb348c97df44	1011
lypinator	0:bb348c97df44	1012	/**
lypinator	0:bb348c97df44	1013	* @brief Enable send CE-ATA command (CMD61).
lypinator	0:bb348c97df44	1014	* @retval None
lypinator	0:bb348c97df44	1015	*/
lypinator	0:bb348c97df44	1016	#define __SDIO_CEATA_SENDCMD_ENABLE() ((__IO uint32_t ) CMD_ATACMD_BB = ENABLE)
lypinator	0:bb348c97df44	1017
lypinator	0:bb348c97df44	1018	/**
lypinator	0:bb348c97df44	1019	* @brief Disable send CE-ATA command (CMD61).
lypinator	0:bb348c97df44	1020	* @retval None
lypinator	0:bb348c97df44	1021	*/
lypinator	0:bb348c97df44	1022	#define __SDIO_CEATA_SENDCMD_DISABLE() ((__IO uint32_t ) CMD_ATACMD_BB = DISABLE)
lypinator	0:bb348c97df44	1023	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F401xC \|\| STM32F401xE \|\| STM32F411xE \|\|\
lypinator	0:bb348c97df44	1024	STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
lypinator	0:bb348c97df44	1025
lypinator	0:bb348c97df44	1026	/**
lypinator	0:bb348c97df44	1027	* @}
lypinator	0:bb348c97df44	1028	*/
lypinator	0:bb348c97df44	1029
lypinator	0:bb348c97df44	1030	/**
lypinator	0:bb348c97df44	1031	* @}
lypinator	0:bb348c97df44	1032	*/
lypinator	0:bb348c97df44	1033
lypinator	0:bb348c97df44	1034	/* Exported functions --------------------------------------------------------*/
lypinator	0:bb348c97df44	1035	/** @addtogroup SDMMC_LL_Exported_Functions
lypinator	0:bb348c97df44	1036	* @{
lypinator	0:bb348c97df44	1037	*/
lypinator	0:bb348c97df44	1038
lypinator	0:bb348c97df44	1039	/* Initialization/de-initialization functions **********************************/
lypinator	0:bb348c97df44	1040	/** @addtogroup HAL_SDMMC_LL_Group1
lypinator	0:bb348c97df44	1041	* @{
lypinator	0:bb348c97df44	1042	*/
lypinator	0:bb348c97df44	1043	HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init);
lypinator	0:bb348c97df44	1044	/**
lypinator	0:bb348c97df44	1045	* @}
lypinator	0:bb348c97df44	1046	*/
lypinator	0:bb348c97df44	1047
lypinator	0:bb348c97df44	1048	/* I/O operation functions *****************************************************/
lypinator	0:bb348c97df44	1049	/** @addtogroup HAL_SDMMC_LL_Group2
lypinator	0:bb348c97df44	1050	* @{
lypinator	0:bb348c97df44	1051	*/
lypinator	0:bb348c97df44	1052	uint32_t SDIO_ReadFIFO(SDIO_TypeDef *SDIOx);
lypinator	0:bb348c97df44	1053	HAL_StatusTypeDef SDIO_WriteFIFO(SDIO_TypeDef SDIOx, uint32_t pWriteData);
lypinator	0:bb348c97df44	1054	/**
lypinator	0:bb348c97df44	1055	* @}
lypinator	0:bb348c97df44	1056	*/
lypinator	0:bb348c97df44	1057
lypinator	0:bb348c97df44	1058	/* Peripheral Control functions ************************************************/
lypinator	0:bb348c97df44	1059	/** @addtogroup HAL_SDMMC_LL_Group3
lypinator	0:bb348c97df44	1060	* @{
lypinator	0:bb348c97df44	1061	*/
lypinator	0:bb348c97df44	1062	HAL_StatusTypeDef SDIO_PowerState_ON(SDIO_TypeDef *SDIOx);
lypinator	0:bb348c97df44	1063	HAL_StatusTypeDef SDIO_PowerState_OFF(SDIO_TypeDef *SDIOx);
lypinator	0:bb348c97df44	1064	uint32_t SDIO_GetPowerState(SDIO_TypeDef *SDIOx);
lypinator	0:bb348c97df44	1065
lypinator	0:bb348c97df44	1066	/* Command path state machine (CPSM) management functions */
lypinator	0:bb348c97df44	1067	HAL_StatusTypeDef SDIO_SendCommand(SDIO_TypeDef SDIOx, SDIO_CmdInitTypeDef Command);
lypinator	0:bb348c97df44	1068	uint8_t SDIO_GetCommandResponse(SDIO_TypeDef *SDIOx);
lypinator	0:bb348c97df44	1069	uint32_t SDIO_GetResponse(SDIO_TypeDef *SDIOx, uint32_t Response);
lypinator	0:bb348c97df44	1070
lypinator	0:bb348c97df44	1071	/* Data path state machine (DPSM) management functions */
lypinator	0:bb348c97df44	1072	HAL_StatusTypeDef SDIO_ConfigData(SDIO_TypeDef SDIOx, SDIO_DataInitTypeDef Data);
lypinator	0:bb348c97df44	1073	uint32_t SDIO_GetDataCounter(SDIO_TypeDef *SDIOx);
lypinator	0:bb348c97df44	1074	uint32_t SDIO_GetFIFOCount(SDIO_TypeDef *SDIOx);
lypinator	0:bb348c97df44	1075
lypinator	0:bb348c97df44	1076	/* SDMMC Cards mode management functions */
lypinator	0:bb348c97df44	1077	HAL_StatusTypeDef SDIO_SetSDMMCReadWaitMode(SDIO_TypeDef *SDIOx, uint32_t SDIO_ReadWaitMode);
lypinator	0:bb348c97df44	1078
lypinator	0:bb348c97df44	1079	/* SDMMC Commands management functions */
lypinator	0:bb348c97df44	1080	uint32_t SDMMC_CmdBlockLength(SDIO_TypeDef *SDIOx, uint32_t BlockSize);
lypinator	0:bb348c97df44	1081	uint32_t SDMMC_CmdReadSingleBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd);
lypinator	0:bb348c97df44	1082	uint32_t SDMMC_CmdReadMultiBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd);
lypinator	0:bb348c97df44	1083	uint32_t SDMMC_CmdWriteSingleBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd);
lypinator	0:bb348c97df44	1084	uint32_t SDMMC_CmdWriteMultiBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd);
lypinator	0:bb348c97df44	1085	uint32_t SDMMC_CmdSDEraseStartAdd(SDIO_TypeDef *SDIOx, uint32_t StartAdd);
lypinator	0:bb348c97df44	1086	uint32_t SDMMC_CmdSDEraseEndAdd(SDIO_TypeDef *SDIOx, uint32_t EndAdd);
lypinator	0:bb348c97df44	1087	uint32_t SDMMC_CmdErase(SDIO_TypeDef *SDIOx);
lypinator	0:bb348c97df44	1088	uint32_t SDMMC_CmdStopTransfer(SDIO_TypeDef *SDIOx);
lypinator	0:bb348c97df44	1089	uint32_t SDMMC_CmdSelDesel(SDIO_TypeDef *SDIOx, uint64_t Addr);
lypinator	0:bb348c97df44	1090	uint32_t SDMMC_CmdGoIdleState(SDIO_TypeDef *SDIOx);
lypinator	0:bb348c97df44	1091	uint32_t SDMMC_CmdOperCond(SDIO_TypeDef *SDIOx);
lypinator	0:bb348c97df44	1092	uint32_t SDMMC_CmdAppCommand(SDIO_TypeDef *SDIOx, uint32_t Argument);
lypinator	0:bb348c97df44	1093	uint32_t SDMMC_CmdAppOperCommand(SDIO_TypeDef *SDIOx, uint32_t SdType);
lypinator	0:bb348c97df44	1094	uint32_t SDMMC_CmdBusWidth(SDIO_TypeDef *SDIOx, uint32_t BusWidth);
lypinator	0:bb348c97df44	1095	uint32_t SDMMC_CmdSendSCR(SDIO_TypeDef *SDIOx);
lypinator	0:bb348c97df44	1096	uint32_t SDMMC_CmdSendCID(SDIO_TypeDef *SDIOx);
lypinator	0:bb348c97df44	1097	uint32_t SDMMC_CmdSendCSD(SDIO_TypeDef *SDIOx, uint32_t Argument);
lypinator	0:bb348c97df44	1098	uint32_t SDMMC_CmdSetRelAdd(SDIO_TypeDef SDIOx, uint16_t pRCA);
lypinator	0:bb348c97df44	1099	uint32_t SDMMC_CmdSendStatus(SDIO_TypeDef *SDIOx, uint32_t Argument);
lypinator	0:bb348c97df44	1100	uint32_t SDMMC_CmdStatusRegister(SDIO_TypeDef *SDIOx);
lypinator	0:bb348c97df44	1101
lypinator	0:bb348c97df44	1102	uint32_t SDMMC_CmdOpCondition(SDIO_TypeDef *SDIOx, uint32_t Argument);
lypinator	0:bb348c97df44	1103	uint32_t SDMMC_CmdSwitch(SDIO_TypeDef *SDIOx, uint32_t Argument);
lypinator	0:bb348c97df44	1104	uint32_t SDMMC_CmdEraseStartAdd(SDIO_TypeDef *SDIOx, uint32_t StartAdd);
lypinator	0:bb348c97df44	1105	uint32_t SDMMC_CmdEraseEndAdd(SDIO_TypeDef *SDIOx, uint32_t EndAdd);
lypinator	0:bb348c97df44	1106
lypinator	0:bb348c97df44	1107	/**
lypinator	0:bb348c97df44	1108	* @}
lypinator	0:bb348c97df44	1109	*/
lypinator	0:bb348c97df44	1110
lypinator	0:bb348c97df44	1111	/**
lypinator	0:bb348c97df44	1112	* @}
lypinator	0:bb348c97df44	1113	*/
lypinator	0:bb348c97df44	1114
lypinator	0:bb348c97df44	1115	/**
lypinator	0:bb348c97df44	1116	* @}
lypinator	0:bb348c97df44	1117	*/
lypinator	0:bb348c97df44	1118
lypinator	0:bb348c97df44	1119	/**
lypinator	0:bb348c97df44	1120	* @}
lypinator	0:bb348c97df44	1121	*/
lypinator	0:bb348c97df44	1122
lypinator	0:bb348c97df44	1123	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\|
lypinator	0:bb348c97df44	1124	STM32F401xC \|\| STM32F401xE \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\| STM32F412Vx \|\|
lypinator	0:bb348c97df44	1125	STM32F412Rx \|\| STM32F412Cx \|\| STM32F413xx \|\| STM32F423xx */
lypinator	0:bb348c97df44	1126
lypinator	0:bb348c97df44	1127	#ifdef __cplusplus
lypinator	0:bb348c97df44	1128	}
lypinator	0:bb348c97df44	1129	#endif
lypinator	0:bb348c97df44	1130
lypinator	0:bb348c97df44	1131	#endif /* __STM32F4xx_LL_SDMMC_H */
lypinator	0:bb348c97df44	1132
lypinator	0:bb348c97df44	1133	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Program
Created:	16 Sep 2020
Imports:	1
Forks:	0
Commits:	1
Dependents:	0
Dependencies:	1
Followers:	1

mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_sdmmc.h@0:bb348c97df44, 2020-09-16 (annotated)

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