DevLibMemoryController - Initial commit

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Initial commit

mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_rcc.h@0:bb348c97df44, 2020-09-16 (annotated)

Committer:: lypinator
Date:: Wed Sep 16 01:11:49 2020 +0000
Revision:: 0:bb348c97df44

Added PWM

Who changed what in which revision?

User	Revision	Line number	New contents of line
lypinator	0:bb348c97df44	1	/**
lypinator	0:bb348c97df44	2	******************************************************************************
lypinator	0:bb348c97df44	3	* @file stm32f4xx_ll_rcc.h
lypinator	0:bb348c97df44	4	* @author MCD Application Team
lypinator	0:bb348c97df44	5	* @brief Header file of RCC LL module.
lypinator	0:bb348c97df44	6	******************************************************************************
lypinator	0:bb348c97df44	7	* @attention
lypinator	0:bb348c97df44	8	*
lypinator	0:bb348c97df44	9	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
lypinator	0:bb348c97df44	10	*
lypinator	0:bb348c97df44	11	* Redistribution and use in source and binary forms, with or without modification,
lypinator	0:bb348c97df44	12	* are permitted provided that the following conditions are met:
lypinator	0:bb348c97df44	13	* 1. Redistributions of source code must retain the above copyright notice,
lypinator	0:bb348c97df44	14	* this list of conditions and the following disclaimer.
lypinator	0:bb348c97df44	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
lypinator	0:bb348c97df44	16	* this list of conditions and the following disclaimer in the documentation
lypinator	0:bb348c97df44	17	* and/or other materials provided with the distribution.
lypinator	0:bb348c97df44	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
lypinator	0:bb348c97df44	19	* may be used to endorse or promote products derived from this software
lypinator	0:bb348c97df44	20	* without specific prior written permission.
lypinator	0:bb348c97df44	21	*
lypinator	0:bb348c97df44	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
lypinator	0:bb348c97df44	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
lypinator	0:bb348c97df44	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
lypinator	0:bb348c97df44	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
lypinator	0:bb348c97df44	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
lypinator	0:bb348c97df44	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
lypinator	0:bb348c97df44	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
lypinator	0:bb348c97df44	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
lypinator	0:bb348c97df44	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
lypinator	0:bb348c97df44	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
lypinator	0:bb348c97df44	32	*
lypinator	0:bb348c97df44	33	******************************************************************************
lypinator	0:bb348c97df44	34	*/
lypinator	0:bb348c97df44	35
lypinator	0:bb348c97df44	36	/* Define to prevent recursive inclusion -------------------------------------*/
lypinator	0:bb348c97df44	37	#ifndef __STM32F4xx_LL_RCC_H
lypinator	0:bb348c97df44	38	#define __STM32F4xx_LL_RCC_H
lypinator	0:bb348c97df44	39
lypinator	0:bb348c97df44	40	#ifdef __cplusplus
lypinator	0:bb348c97df44	41	extern "C" {
lypinator	0:bb348c97df44	42	#endif
lypinator	0:bb348c97df44	43
lypinator	0:bb348c97df44	44	/* Includes ------------------------------------------------------------------*/
lypinator	0:bb348c97df44	45	#include "stm32f4xx.h"
lypinator	0:bb348c97df44	46
lypinator	0:bb348c97df44	47	/** @addtogroup STM32F4xx_LL_Driver
lypinator	0:bb348c97df44	48	* @{
lypinator	0:bb348c97df44	49	*/
lypinator	0:bb348c97df44	50
lypinator	0:bb348c97df44	51	#if defined(RCC)
lypinator	0:bb348c97df44	52
lypinator	0:bb348c97df44	53	/** @defgroup RCC_LL RCC
lypinator	0:bb348c97df44	54	* @{
lypinator	0:bb348c97df44	55	*/
lypinator	0:bb348c97df44	56
lypinator	0:bb348c97df44	57	/* Private types -------------------------------------------------------------*/
lypinator	0:bb348c97df44	58	/* Private variables ---------------------------------------------------------*/
lypinator	0:bb348c97df44	59	/** @defgroup RCC_LL_Private_Variables RCC Private Variables
lypinator	0:bb348c97df44	60	* @{
lypinator	0:bb348c97df44	61	*/
lypinator	0:bb348c97df44	62
lypinator	0:bb348c97df44	63	#if defined(RCC_DCKCFGR_PLLSAIDIVR)
lypinator	0:bb348c97df44	64	static const uint8_t aRCC_PLLSAIDIVRPrescTable[4] = {2, 4, 8, 16};
lypinator	0:bb348c97df44	65	#endif /* RCC_DCKCFGR_PLLSAIDIVR */
lypinator	0:bb348c97df44	66
lypinator	0:bb348c97df44	67	/**
lypinator	0:bb348c97df44	68	* @}
lypinator	0:bb348c97df44	69	*/
lypinator	0:bb348c97df44	70	/* Private constants ---------------------------------------------------------*/
lypinator	0:bb348c97df44	71	/* Private macros ------------------------------------------------------------*/
lypinator	0:bb348c97df44	72	#if defined(USE_FULL_LL_DRIVER)
lypinator	0:bb348c97df44	73	/** @defgroup RCC_LL_Private_Macros RCC Private Macros
lypinator	0:bb348c97df44	74	* @{
lypinator	0:bb348c97df44	75	*/
lypinator	0:bb348c97df44	76	/**
lypinator	0:bb348c97df44	77	* @}
lypinator	0:bb348c97df44	78	*/
lypinator	0:bb348c97df44	79	#endif /USE_FULL_LL_DRIVER/
lypinator	0:bb348c97df44	80	/* Exported types ------------------------------------------------------------*/
lypinator	0:bb348c97df44	81	#if defined(USE_FULL_LL_DRIVER)
lypinator	0:bb348c97df44	82	/** @defgroup RCC_LL_Exported_Types RCC Exported Types
lypinator	0:bb348c97df44	83	* @{
lypinator	0:bb348c97df44	84	*/
lypinator	0:bb348c97df44	85
lypinator	0:bb348c97df44	86	/** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure
lypinator	0:bb348c97df44	87	* @{
lypinator	0:bb348c97df44	88	*/
lypinator	0:bb348c97df44	89
lypinator	0:bb348c97df44	90	/**
lypinator	0:bb348c97df44	91	* @brief RCC Clocks Frequency Structure
lypinator	0:bb348c97df44	92	*/
lypinator	0:bb348c97df44	93	typedef struct
lypinator	0:bb348c97df44	94	{
lypinator	0:bb348c97df44	95	uint32_t SYSCLK_Frequency; /!< SYSCLK clock frequency /
lypinator	0:bb348c97df44	96	uint32_t HCLK_Frequency; /!< HCLK clock frequency /
lypinator	0:bb348c97df44	97	uint32_t PCLK1_Frequency; /!< PCLK1 clock frequency /
lypinator	0:bb348c97df44	98	uint32_t PCLK2_Frequency; /!< PCLK2 clock frequency /
lypinator	0:bb348c97df44	99	} LL_RCC_ClocksTypeDef;
lypinator	0:bb348c97df44	100
lypinator	0:bb348c97df44	101	/**
lypinator	0:bb348c97df44	102	* @}
lypinator	0:bb348c97df44	103	*/
lypinator	0:bb348c97df44	104
lypinator	0:bb348c97df44	105	/**
lypinator	0:bb348c97df44	106	* @}
lypinator	0:bb348c97df44	107	*/
lypinator	0:bb348c97df44	108	#endif /* USE_FULL_LL_DRIVER */
lypinator	0:bb348c97df44	109
lypinator	0:bb348c97df44	110	/* Exported constants --------------------------------------------------------*/
lypinator	0:bb348c97df44	111	/** @defgroup RCC_LL_Exported_Constants RCC Exported Constants
lypinator	0:bb348c97df44	112	* @{
lypinator	0:bb348c97df44	113	*/
lypinator	0:bb348c97df44	114
lypinator	0:bb348c97df44	115	/** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation
lypinator	0:bb348c97df44	116	* @brief Defines used to adapt values of different oscillators
lypinator	0:bb348c97df44	117	* @note These values could be modified in the user environment according to
lypinator	0:bb348c97df44	118	* HW set-up.
lypinator	0:bb348c97df44	119	* @{
lypinator	0:bb348c97df44	120	*/
lypinator	0:bb348c97df44	121	#if !defined (HSE_VALUE)
lypinator	0:bb348c97df44	122	#define HSE_VALUE 25000000U /!< Value of the HSE oscillator in Hz /
lypinator	0:bb348c97df44	123	#endif /* HSE_VALUE */
lypinator	0:bb348c97df44	124
lypinator	0:bb348c97df44	125	#if !defined (HSI_VALUE)
lypinator	0:bb348c97df44	126	#define HSI_VALUE 16000000U /!< Value of the HSI oscillator in Hz /
lypinator	0:bb348c97df44	127	#endif /* HSI_VALUE */
lypinator	0:bb348c97df44	128
lypinator	0:bb348c97df44	129	#if !defined (LSE_VALUE)
lypinator	0:bb348c97df44	130	#define LSE_VALUE 32768U /!< Value of the LSE oscillator in Hz /
lypinator	0:bb348c97df44	131	#endif /* LSE_VALUE */
lypinator	0:bb348c97df44	132
lypinator	0:bb348c97df44	133	#if !defined (LSI_VALUE)
lypinator	0:bb348c97df44	134	#define LSI_VALUE 32000U /!< Value of the LSI oscillator in Hz /
lypinator	0:bb348c97df44	135	#endif /* LSI_VALUE */
lypinator	0:bb348c97df44	136
lypinator	0:bb348c97df44	137	#if !defined (EXTERNAL_CLOCK_VALUE)
lypinator	0:bb348c97df44	138	#define EXTERNAL_CLOCK_VALUE 12288000U /!< Value of the I2S_CKIN external oscillator in Hz /
lypinator	0:bb348c97df44	139	#endif /* EXTERNAL_CLOCK_VALUE */
lypinator	0:bb348c97df44	140	/**
lypinator	0:bb348c97df44	141	* @}
lypinator	0:bb348c97df44	142	*/
lypinator	0:bb348c97df44	143
lypinator	0:bb348c97df44	144	/** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines
lypinator	0:bb348c97df44	145	* @brief Flags defines which can be used with LL_RCC_WriteReg function
lypinator	0:bb348c97df44	146	* @{
lypinator	0:bb348c97df44	147	*/
lypinator	0:bb348c97df44	148	#define LL_RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC /!< LSI Ready Interrupt Clear /
lypinator	0:bb348c97df44	149	#define LL_RCC_CIR_LSERDYC RCC_CIR_LSERDYC /!< LSE Ready Interrupt Clear /
lypinator	0:bb348c97df44	150	#define LL_RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC /!< HSI Ready Interrupt Clear /
lypinator	0:bb348c97df44	151	#define LL_RCC_CIR_HSERDYC RCC_CIR_HSERDYC /!< HSE Ready Interrupt Clear /
lypinator	0:bb348c97df44	152	#define LL_RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC /!< PLL Ready Interrupt Clear /
lypinator	0:bb348c97df44	153	#if defined(RCC_PLLI2S_SUPPORT)
lypinator	0:bb348c97df44	154	#define LL_RCC_CIR_PLLI2SRDYC RCC_CIR_PLLI2SRDYC /!< PLLI2S Ready Interrupt Clear /
lypinator	0:bb348c97df44	155	#endif /* RCC_PLLI2S_SUPPORT */
lypinator	0:bb348c97df44	156	#if defined(RCC_PLLSAI_SUPPORT)
lypinator	0:bb348c97df44	157	#define LL_RCC_CIR_PLLSAIRDYC RCC_CIR_PLLSAIRDYC /!< PLLSAI Ready Interrupt Clear /
lypinator	0:bb348c97df44	158	#endif /* RCC_PLLSAI_SUPPORT */
lypinator	0:bb348c97df44	159	#define LL_RCC_CIR_CSSC RCC_CIR_CSSC /!< Clock Security System Interrupt Clear /
lypinator	0:bb348c97df44	160	/**
lypinator	0:bb348c97df44	161	* @}
lypinator	0:bb348c97df44	162	*/
lypinator	0:bb348c97df44	163
lypinator	0:bb348c97df44	164	/** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines
lypinator	0:bb348c97df44	165	* @brief Flags defines which can be used with LL_RCC_ReadReg function
lypinator	0:bb348c97df44	166	* @{
lypinator	0:bb348c97df44	167	*/
lypinator	0:bb348c97df44	168	#define LL_RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF /!< LSI Ready Interrupt flag /
lypinator	0:bb348c97df44	169	#define LL_RCC_CIR_LSERDYF RCC_CIR_LSERDYF /!< LSE Ready Interrupt flag /
lypinator	0:bb348c97df44	170	#define LL_RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF /!< HSI Ready Interrupt flag /
lypinator	0:bb348c97df44	171	#define LL_RCC_CIR_HSERDYF RCC_CIR_HSERDYF /!< HSE Ready Interrupt flag /
lypinator	0:bb348c97df44	172	#define LL_RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF /!< PLL Ready Interrupt flag /
lypinator	0:bb348c97df44	173	#if defined(RCC_PLLI2S_SUPPORT)
lypinator	0:bb348c97df44	174	#define LL_RCC_CIR_PLLI2SRDYF RCC_CIR_PLLI2SRDYF /!< PLLI2S Ready Interrupt flag /
lypinator	0:bb348c97df44	175	#endif /* RCC_PLLI2S_SUPPORT */
lypinator	0:bb348c97df44	176	#if defined(RCC_PLLSAI_SUPPORT)
lypinator	0:bb348c97df44	177	#define LL_RCC_CIR_PLLSAIRDYF RCC_CIR_PLLSAIRDYF /!< PLLSAI Ready Interrupt flag /
lypinator	0:bb348c97df44	178	#endif /* RCC_PLLSAI_SUPPORT */
lypinator	0:bb348c97df44	179	#define LL_RCC_CIR_CSSF RCC_CIR_CSSF /!< Clock Security System Interrupt flag /
lypinator	0:bb348c97df44	180	#define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /!< Low-Power reset flag /
lypinator	0:bb348c97df44	181	#define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /!< PIN reset flag /
lypinator	0:bb348c97df44	182	#define LL_RCC_CSR_PORRSTF RCC_CSR_PORRSTF /!< POR/PDR reset flag /
lypinator	0:bb348c97df44	183	#define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /!< Software Reset flag /
lypinator	0:bb348c97df44	184	#define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /!< Independent Watchdog reset flag /
lypinator	0:bb348c97df44	185	#define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /!< Window watchdog reset flag /
lypinator	0:bb348c97df44	186	#if defined(RCC_CSR_BORRSTF)
lypinator	0:bb348c97df44	187	#define LL_RCC_CSR_BORRSTF RCC_CSR_BORRSTF /!< BOR reset flag /
lypinator	0:bb348c97df44	188	#endif /* RCC_CSR_BORRSTF */
lypinator	0:bb348c97df44	189	/**
lypinator	0:bb348c97df44	190	* @}
lypinator	0:bb348c97df44	191	*/
lypinator	0:bb348c97df44	192
lypinator	0:bb348c97df44	193	/** @defgroup RCC_LL_EC_IT IT Defines
lypinator	0:bb348c97df44	194	* @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions
lypinator	0:bb348c97df44	195	* @{
lypinator	0:bb348c97df44	196	*/
lypinator	0:bb348c97df44	197	#define LL_RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE /!< LSI Ready Interrupt Enable /
lypinator	0:bb348c97df44	198	#define LL_RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE /!< LSE Ready Interrupt Enable /
lypinator	0:bb348c97df44	199	#define LL_RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE /!< HSI Ready Interrupt Enable /
lypinator	0:bb348c97df44	200	#define LL_RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE /!< HSE Ready Interrupt Enable /
lypinator	0:bb348c97df44	201	#define LL_RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE /!< PLL Ready Interrupt Enable /
lypinator	0:bb348c97df44	202	#if defined(RCC_PLLI2S_SUPPORT)
lypinator	0:bb348c97df44	203	#define LL_RCC_CIR_PLLI2SRDYIE RCC_CIR_PLLI2SRDYIE /!< PLLI2S Ready Interrupt Enable /
lypinator	0:bb348c97df44	204	#endif /* RCC_PLLI2S_SUPPORT */
lypinator	0:bb348c97df44	205	#if defined(RCC_PLLSAI_SUPPORT)
lypinator	0:bb348c97df44	206	#define LL_RCC_CIR_PLLSAIRDYIE RCC_CIR_PLLSAIRDYIE /!< PLLSAI Ready Interrupt Enable /
lypinator	0:bb348c97df44	207	#endif /* RCC_PLLSAI_SUPPORT */
lypinator	0:bb348c97df44	208	/**
lypinator	0:bb348c97df44	209	* @}
lypinator	0:bb348c97df44	210	*/
lypinator	0:bb348c97df44	211
lypinator	0:bb348c97df44	212	/** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch
lypinator	0:bb348c97df44	213	* @{
lypinator	0:bb348c97df44	214	*/
lypinator	0:bb348c97df44	215	#define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI /!< HSI selection as system clock /
lypinator	0:bb348c97df44	216	#define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE /!< HSE selection as system clock /
lypinator	0:bb348c97df44	217	#define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL /!< PLL selection as system clock /
lypinator	0:bb348c97df44	218	#if defined(RCC_CFGR_SW_PLLR)
lypinator	0:bb348c97df44	219	#define LL_RCC_SYS_CLKSOURCE_PLLR RCC_CFGR_SW_PLLR /!< PLLR selection as system clock /
lypinator	0:bb348c97df44	220	#endif /* RCC_CFGR_SW_PLLR */
lypinator	0:bb348c97df44	221	/**
lypinator	0:bb348c97df44	222	* @}
lypinator	0:bb348c97df44	223	*/
lypinator	0:bb348c97df44	224
lypinator	0:bb348c97df44	225	/** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status
lypinator	0:bb348c97df44	226	* @{
lypinator	0:bb348c97df44	227	*/
lypinator	0:bb348c97df44	228	#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /!< HSI used as system clock /
lypinator	0:bb348c97df44	229	#define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /!< HSE used as system clock /
lypinator	0:bb348c97df44	230	#define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL /!< PLL used as system clock /
lypinator	0:bb348c97df44	231	#if defined(RCC_PLLR_SYSCLK_SUPPORT)
lypinator	0:bb348c97df44	232	#define LL_RCC_SYS_CLKSOURCE_STATUS_PLLR RCC_CFGR_SWS_PLLR /!< PLLR used as system clock /
lypinator	0:bb348c97df44	233	#endif /* RCC_PLLR_SYSCLK_SUPPORT */
lypinator	0:bb348c97df44	234	/**
lypinator	0:bb348c97df44	235	* @}
lypinator	0:bb348c97df44	236	*/
lypinator	0:bb348c97df44	237
lypinator	0:bb348c97df44	238	/** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler
lypinator	0:bb348c97df44	239	* @{
lypinator	0:bb348c97df44	240	*/
lypinator	0:bb348c97df44	241	#define LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1 /!< SYSCLK not divided /
lypinator	0:bb348c97df44	242	#define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2 /!< SYSCLK divided by 2 /
lypinator	0:bb348c97df44	243	#define LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4 /!< SYSCLK divided by 4 /
lypinator	0:bb348c97df44	244	#define LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8 /!< SYSCLK divided by 8 /
lypinator	0:bb348c97df44	245	#define LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16 /!< SYSCLK divided by 16 /
lypinator	0:bb348c97df44	246	#define LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64 /!< SYSCLK divided by 64 /
lypinator	0:bb348c97df44	247	#define LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128 /!< SYSCLK divided by 128 /
lypinator	0:bb348c97df44	248	#define LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256 /!< SYSCLK divided by 256 /
lypinator	0:bb348c97df44	249	#define LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512 /!< SYSCLK divided by 512 /
lypinator	0:bb348c97df44	250	/**
lypinator	0:bb348c97df44	251	* @}
lypinator	0:bb348c97df44	252	*/
lypinator	0:bb348c97df44	253
lypinator	0:bb348c97df44	254	/** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1)
lypinator	0:bb348c97df44	255	* @{
lypinator	0:bb348c97df44	256	*/
lypinator	0:bb348c97df44	257	#define LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE1_DIV1 /!< HCLK not divided /
lypinator	0:bb348c97df44	258	#define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_DIV2 /!< HCLK divided by 2 /
lypinator	0:bb348c97df44	259	#define LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE1_DIV4 /!< HCLK divided by 4 /
lypinator	0:bb348c97df44	260	#define LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE1_DIV8 /!< HCLK divided by 8 /
lypinator	0:bb348c97df44	261	#define LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE1_DIV16 /!< HCLK divided by 16 /
lypinator	0:bb348c97df44	262	/**
lypinator	0:bb348c97df44	263	* @}
lypinator	0:bb348c97df44	264	*/
lypinator	0:bb348c97df44	265
lypinator	0:bb348c97df44	266	/** @defgroup RCC_LL_EC_APB2_DIV APB high-speed prescaler (APB2)
lypinator	0:bb348c97df44	267	* @{
lypinator	0:bb348c97df44	268	*/
lypinator	0:bb348c97df44	269	#define LL_RCC_APB2_DIV_1 RCC_CFGR_PPRE2_DIV1 /!< HCLK not divided /
lypinator	0:bb348c97df44	270	#define LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_DIV2 /!< HCLK divided by 2 /
lypinator	0:bb348c97df44	271	#define LL_RCC_APB2_DIV_4 RCC_CFGR_PPRE2_DIV4 /!< HCLK divided by 4 /
lypinator	0:bb348c97df44	272	#define LL_RCC_APB2_DIV_8 RCC_CFGR_PPRE2_DIV8 /!< HCLK divided by 8 /
lypinator	0:bb348c97df44	273	#define LL_RCC_APB2_DIV_16 RCC_CFGR_PPRE2_DIV16 /!< HCLK divided by 16 /
lypinator	0:bb348c97df44	274	/**
lypinator	0:bb348c97df44	275	* @}
lypinator	0:bb348c97df44	276	*/
lypinator	0:bb348c97df44	277
lypinator	0:bb348c97df44	278	/** @defgroup RCC_LL_EC_MCOxSOURCE MCO source selection
lypinator	0:bb348c97df44	279	* @{
lypinator	0:bb348c97df44	280	*/
lypinator	0:bb348c97df44	281	#define LL_RCC_MCO1SOURCE_HSI (uint32_t)(RCC_CFGR_MCO1\|0x00000000U) /!< HSI selection as MCO1 source /
lypinator	0:bb348c97df44	282	#define LL_RCC_MCO1SOURCE_LSE (uint32_t)(RCC_CFGR_MCO1\|(RCC_CFGR_MCO1_0 >> 16U)) /!< LSE selection as MCO1 source /
lypinator	0:bb348c97df44	283	#define LL_RCC_MCO1SOURCE_HSE (uint32_t)(RCC_CFGR_MCO1\|(RCC_CFGR_MCO1_1 >> 16U)) /!< HSE selection as MCO1 source /
lypinator	0:bb348c97df44	284	#define LL_RCC_MCO1SOURCE_PLLCLK (uint32_t)(RCC_CFGR_MCO1\|((RCC_CFGR_MCO1_1\|RCC_CFGR_MCO1_0) >> 16U)) /!< PLLCLK selection as MCO1 source /
lypinator	0:bb348c97df44	285	#if defined(RCC_CFGR_MCO2)
lypinator	0:bb348c97df44	286	#define LL_RCC_MCO2SOURCE_SYSCLK (uint32_t)(RCC_CFGR_MCO2\|0x00000000U) /!< SYSCLK selection as MCO2 source /
lypinator	0:bb348c97df44	287	#define LL_RCC_MCO2SOURCE_PLLI2S (uint32_t)(RCC_CFGR_MCO2\|(RCC_CFGR_MCO2_0 >> 16U)) /!< PLLI2S selection as MCO2 source /
lypinator	0:bb348c97df44	288	#define LL_RCC_MCO2SOURCE_HSE (uint32_t)(RCC_CFGR_MCO2\|(RCC_CFGR_MCO2_1 >> 16U)) /!< HSE selection as MCO2 source /
lypinator	0:bb348c97df44	289	#define LL_RCC_MCO2SOURCE_PLLCLK (uint32_t)(RCC_CFGR_MCO2\|((RCC_CFGR_MCO2_1\|RCC_CFGR_MCO2_0) >> 16U)) /!< PLLCLK selection as MCO2 source /
lypinator	0:bb348c97df44	290	#endif /* RCC_CFGR_MCO2 */
lypinator	0:bb348c97df44	291	/**
lypinator	0:bb348c97df44	292	* @}
lypinator	0:bb348c97df44	293	*/
lypinator	0:bb348c97df44	294
lypinator	0:bb348c97df44	295	/** @defgroup RCC_LL_EC_MCOx_DIV MCO prescaler
lypinator	0:bb348c97df44	296	* @{
lypinator	0:bb348c97df44	297	*/
lypinator	0:bb348c97df44	298	#define LL_RCC_MCO1_DIV_1 (uint32_t)(RCC_CFGR_MCO1PRE\|0x00000000U) /!< MCO1 not divided /
lypinator	0:bb348c97df44	299	#define LL_RCC_MCO1_DIV_2 (uint32_t)(RCC_CFGR_MCO1PRE\|(RCC_CFGR_MCO1PRE_2 >> 16U)) /!< MCO1 divided by 2 /
lypinator	0:bb348c97df44	300	#define LL_RCC_MCO1_DIV_3 (uint32_t)(RCC_CFGR_MCO1PRE\|((RCC_CFGR_MCO1PRE_2\|RCC_CFGR_MCO1PRE_0) >> 16U)) /!< MCO1 divided by 3 /
lypinator	0:bb348c97df44	301	#define LL_RCC_MCO1_DIV_4 (uint32_t)(RCC_CFGR_MCO1PRE\|((RCC_CFGR_MCO1PRE_2\|RCC_CFGR_MCO1PRE_1) >> 16U)) /!< MCO1 divided by 4 /
lypinator	0:bb348c97df44	302	#define LL_RCC_MCO1_DIV_5 (uint32_t)(RCC_CFGR_MCO1PRE\|(RCC_CFGR_MCO1PRE >> 16U)) /!< MCO1 divided by 5 /
lypinator	0:bb348c97df44	303	#if defined(RCC_CFGR_MCO2PRE)
lypinator	0:bb348c97df44	304	#define LL_RCC_MCO2_DIV_1 (uint32_t)(RCC_CFGR_MCO2PRE\|0x00000000U) /!< MCO2 not divided /
lypinator	0:bb348c97df44	305	#define LL_RCC_MCO2_DIV_2 (uint32_t)(RCC_CFGR_MCO2PRE\|(RCC_CFGR_MCO2PRE_2 >> 16U)) /!< MCO2 divided by 2 /
lypinator	0:bb348c97df44	306	#define LL_RCC_MCO2_DIV_3 (uint32_t)(RCC_CFGR_MCO2PRE\|((RCC_CFGR_MCO2PRE_2\|RCC_CFGR_MCO2PRE_0) >> 16U)) /!< MCO2 divided by 3 /
lypinator	0:bb348c97df44	307	#define LL_RCC_MCO2_DIV_4 (uint32_t)(RCC_CFGR_MCO2PRE\|((RCC_CFGR_MCO2PRE_2\|RCC_CFGR_MCO2PRE_1) >> 16U)) /!< MCO2 divided by 4 /
lypinator	0:bb348c97df44	308	#define LL_RCC_MCO2_DIV_5 (uint32_t)(RCC_CFGR_MCO2PRE\|(RCC_CFGR_MCO2PRE >> 16U)) /!< MCO2 divided by 5 /
lypinator	0:bb348c97df44	309	#endif /* RCC_CFGR_MCO2PRE */
lypinator	0:bb348c97df44	310	/**
lypinator	0:bb348c97df44	311	* @}
lypinator	0:bb348c97df44	312	*/
lypinator	0:bb348c97df44	313
lypinator	0:bb348c97df44	314	/** @defgroup RCC_LL_EC_RTC_HSEDIV HSE prescaler for RTC clock
lypinator	0:bb348c97df44	315	* @{
lypinator	0:bb348c97df44	316	*/
lypinator	0:bb348c97df44	317	#define LL_RCC_RTC_NOCLOCK 0x00000000U /!< HSE not divided /
lypinator	0:bb348c97df44	318	#define LL_RCC_RTC_HSE_DIV_2 RCC_CFGR_RTCPRE_1 /!< HSE clock divided by 2 /
lypinator	0:bb348c97df44	319	#define LL_RCC_RTC_HSE_DIV_3 (RCC_CFGR_RTCPRE_1\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 3 /
lypinator	0:bb348c97df44	320	#define LL_RCC_RTC_HSE_DIV_4 RCC_CFGR_RTCPRE_2 /!< HSE clock divided by 4 /
lypinator	0:bb348c97df44	321	#define LL_RCC_RTC_HSE_DIV_5 (RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 5 /
lypinator	0:bb348c97df44	322	#define LL_RCC_RTC_HSE_DIV_6 (RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_1) /!< HSE clock divided by 6 /
lypinator	0:bb348c97df44	323	#define LL_RCC_RTC_HSE_DIV_7 (RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_1\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 7 /
lypinator	0:bb348c97df44	324	#define LL_RCC_RTC_HSE_DIV_8 RCC_CFGR_RTCPRE_3 /!< HSE clock divided by 8 /
lypinator	0:bb348c97df44	325	#define LL_RCC_RTC_HSE_DIV_9 (RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 9 /
lypinator	0:bb348c97df44	326	#define LL_RCC_RTC_HSE_DIV_10 (RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_1) /!< HSE clock divided by 10 /
lypinator	0:bb348c97df44	327	#define LL_RCC_RTC_HSE_DIV_11 (RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_1\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 11 /
lypinator	0:bb348c97df44	328	#define LL_RCC_RTC_HSE_DIV_12 (RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_2) /!< HSE clock divided by 12 /
lypinator	0:bb348c97df44	329	#define LL_RCC_RTC_HSE_DIV_13 (RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 13 /
lypinator	0:bb348c97df44	330	#define LL_RCC_RTC_HSE_DIV_14 (RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_1) /!< HSE clock divided by 14 /
lypinator	0:bb348c97df44	331	#define LL_RCC_RTC_HSE_DIV_15 (RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_1\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 15 /
lypinator	0:bb348c97df44	332	#define LL_RCC_RTC_HSE_DIV_16 RCC_CFGR_RTCPRE_4 /!< HSE clock divided by 16 /
lypinator	0:bb348c97df44	333	#define LL_RCC_RTC_HSE_DIV_17 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 17 /
lypinator	0:bb348c97df44	334	#define LL_RCC_RTC_HSE_DIV_18 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_1) /!< HSE clock divided by 18 /
lypinator	0:bb348c97df44	335	#define LL_RCC_RTC_HSE_DIV_19 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_1\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 19 /
lypinator	0:bb348c97df44	336	#define LL_RCC_RTC_HSE_DIV_20 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_2) /!< HSE clock divided by 20 /
lypinator	0:bb348c97df44	337	#define LL_RCC_RTC_HSE_DIV_21 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 21 /
lypinator	0:bb348c97df44	338	#define LL_RCC_RTC_HSE_DIV_22 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_1) /!< HSE clock divided by 22 /
lypinator	0:bb348c97df44	339	#define LL_RCC_RTC_HSE_DIV_23 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_1\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 23 /
lypinator	0:bb348c97df44	340	#define LL_RCC_RTC_HSE_DIV_24 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_3) /!< HSE clock divided by 24 /
lypinator	0:bb348c97df44	341	#define LL_RCC_RTC_HSE_DIV_25 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 25 /
lypinator	0:bb348c97df44	342	#define LL_RCC_RTC_HSE_DIV_26 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_1) /!< HSE clock divided by 26 /
lypinator	0:bb348c97df44	343	#define LL_RCC_RTC_HSE_DIV_27 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_1\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 27 /
lypinator	0:bb348c97df44	344	#define LL_RCC_RTC_HSE_DIV_28 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_2) /!< HSE clock divided by 28 /
lypinator	0:bb348c97df44	345	#define LL_RCC_RTC_HSE_DIV_29 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 29 /
lypinator	0:bb348c97df44	346	#define LL_RCC_RTC_HSE_DIV_30 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_1) /!< HSE clock divided by 30 /
lypinator	0:bb348c97df44	347	#define LL_RCC_RTC_HSE_DIV_31 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_1\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 31 /
lypinator	0:bb348c97df44	348	/**
lypinator	0:bb348c97df44	349	* @}
lypinator	0:bb348c97df44	350	*/
lypinator	0:bb348c97df44	351
lypinator	0:bb348c97df44	352	#if defined(USE_FULL_LL_DRIVER)
lypinator	0:bb348c97df44	353	/** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
lypinator	0:bb348c97df44	354	* @{
lypinator	0:bb348c97df44	355	*/
lypinator	0:bb348c97df44	356	#define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /!< No clock enabled for the peripheral /
lypinator	0:bb348c97df44	357	#define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /!< Frequency cannot be provided as external clock /
lypinator	0:bb348c97df44	358	/**
lypinator	0:bb348c97df44	359	* @}
lypinator	0:bb348c97df44	360	*/
lypinator	0:bb348c97df44	361	#endif /* USE_FULL_LL_DRIVER */
lypinator	0:bb348c97df44	362
lypinator	0:bb348c97df44	363	#if defined(FMPI2C1)
lypinator	0:bb348c97df44	364	/** @defgroup RCC_LL_EC_FMPI2C1_CLKSOURCE Peripheral FMPI2C clock source selection
lypinator	0:bb348c97df44	365	* @{
lypinator	0:bb348c97df44	366	*/
lypinator	0:bb348c97df44	367	#define LL_RCC_FMPI2C1_CLKSOURCE_PCLK1 0x00000000U /!< PCLK1 clock used as FMPI2C1 clock source /
lypinator	0:bb348c97df44	368	#define LL_RCC_FMPI2C1_CLKSOURCE_SYSCLK RCC_DCKCFGR2_FMPI2C1SEL_0 /!< SYSCLK clock used as FMPI2C1 clock source /
lypinator	0:bb348c97df44	369	#define LL_RCC_FMPI2C1_CLKSOURCE_HSI RCC_DCKCFGR2_FMPI2C1SEL_1 /!< HSI clock used as FMPI2C1 clock source /
lypinator	0:bb348c97df44	370	/**
lypinator	0:bb348c97df44	371	* @}
lypinator	0:bb348c97df44	372	*/
lypinator	0:bb348c97df44	373	#endif /* FMPI2C1 */
lypinator	0:bb348c97df44	374
lypinator	0:bb348c97df44	375	#if defined(LPTIM1)
lypinator	0:bb348c97df44	376	/** @defgroup RCC_LL_EC_LPTIM1_CLKSOURCE Peripheral LPTIM clock source selection
lypinator	0:bb348c97df44	377	* @{
lypinator	0:bb348c97df44	378	*/
lypinator	0:bb348c97df44	379	#define LL_RCC_LPTIM1_CLKSOURCE_PCLK1 0x00000000U /!< PCLK1 clock used as LPTIM1 clock /
lypinator	0:bb348c97df44	380	#define LL_RCC_LPTIM1_CLKSOURCE_HSI RCC_DCKCFGR2_LPTIM1SEL_0 /!< LSI oscillator clock used as LPTIM1 clock /
lypinator	0:bb348c97df44	381	#define LL_RCC_LPTIM1_CLKSOURCE_LSI RCC_DCKCFGR2_LPTIM1SEL_1 /!< HSI oscillator clock used as LPTIM1 clock /
lypinator	0:bb348c97df44	382	#define LL_RCC_LPTIM1_CLKSOURCE_LSE (uint32_t)(RCC_DCKCFGR2_LPTIM1SEL_1 \| RCC_DCKCFGR2_LPTIM1SEL_0) /!< LSE oscillator clock used as LPTIM1 clock /
lypinator	0:bb348c97df44	383	/**
lypinator	0:bb348c97df44	384	* @}
lypinator	0:bb348c97df44	385	*/
lypinator	0:bb348c97df44	386	#endif /* LPTIM1 */
lypinator	0:bb348c97df44	387
lypinator	0:bb348c97df44	388	#if defined(SAI1)
lypinator	0:bb348c97df44	389	/** @defgroup RCC_LL_EC_SAIx_CLKSOURCE Peripheral SAI clock source selection
lypinator	0:bb348c97df44	390	* @{
lypinator	0:bb348c97df44	391	*/
lypinator	0:bb348c97df44	392	#if defined(RCC_DCKCFGR_SAI1SRC)
lypinator	0:bb348c97df44	393	#define LL_RCC_SAI1_CLKSOURCE_PLLSAI (uint32_t)(RCC_DCKCFGR_SAI1SRC \| 0x00000000U) /!< PLLSAI clock used as SAI1 clock source /
lypinator	0:bb348c97df44	394	#define LL_RCC_SAI1_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_SAI1SRC \| (RCC_DCKCFGR_SAI1SRC_0 >> 16)) /!< PLLI2S clock used as SAI1 clock source /
lypinator	0:bb348c97df44	395	#define LL_RCC_SAI1_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_SAI1SRC \| (RCC_DCKCFGR_SAI1SRC_1 >> 16)) /!< PLL clock used as SAI1 clock source /
lypinator	0:bb348c97df44	396	#define LL_RCC_SAI1_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_SAI1SRC \| (RCC_DCKCFGR_SAI1SRC >> 16)) /!< External pin clock used as SAI1 clock source /
lypinator	0:bb348c97df44	397	#endif /* RCC_DCKCFGR_SAI1SRC */
lypinator	0:bb348c97df44	398	#if defined(RCC_DCKCFGR_SAI2SRC)
lypinator	0:bb348c97df44	399	#define LL_RCC_SAI2_CLKSOURCE_PLLSAI (uint32_t)(RCC_DCKCFGR_SAI2SRC \| 0x00000000U) /!< PLLSAI clock used as SAI2 clock source /
lypinator	0:bb348c97df44	400	#define LL_RCC_SAI2_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_SAI2SRC \| (RCC_DCKCFGR_SAI2SRC_0 >> 16)) /!< PLLI2S clock used as SAI2 clock source /
lypinator	0:bb348c97df44	401	#define LL_RCC_SAI2_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_SAI2SRC \| (RCC_DCKCFGR_SAI2SRC_1 >> 16)) /!< PLL clock used as SAI2 clock source /
lypinator	0:bb348c97df44	402	#define LL_RCC_SAI2_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR_SAI2SRC \| (RCC_DCKCFGR_SAI2SRC >> 16)) /!< PLL Main clock used as SAI2 clock source /
lypinator	0:bb348c97df44	403	#endif /* RCC_DCKCFGR_SAI2SRC */
lypinator	0:bb348c97df44	404	#if defined(RCC_DCKCFGR_SAI1ASRC)
lypinator	0:bb348c97df44	405	#if defined(RCC_SAI1A_PLLSOURCE_SUPPORT)
lypinator	0:bb348c97df44	406	#define LL_RCC_SAI1_A_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_SAI1ASRC \| 0x00000000U) /!< PLLI2S clock used as SAI1 block A clock source /
lypinator	0:bb348c97df44	407	#define LL_RCC_SAI1_A_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_SAI1ASRC \| (RCC_DCKCFGR_SAI1ASRC_0 >> 16)) /!< External pin used as SAI1 block A clock source /
lypinator	0:bb348c97df44	408	#define LL_RCC_SAI1_A_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_SAI1ASRC \| (RCC_DCKCFGR_SAI1ASRC_1 >> 16)) /!< PLL clock used as SAI1 block A clock source /
lypinator	0:bb348c97df44	409	#define LL_RCC_SAI1_A_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR_SAI1ASRC \| (RCC_DCKCFGR_SAI1ASRC >> 16)) /!< PLL Main clock used as SAI1 block A clock source /
lypinator	0:bb348c97df44	410	#else
lypinator	0:bb348c97df44	411	#define LL_RCC_SAI1_A_CLKSOURCE_PLLSAI (uint32_t)(RCC_DCKCFGR_SAI1ASRC \| 0x00000000U) /!< PLLSAI clock used as SAI1 block A clock source /
lypinator	0:bb348c97df44	412	#define LL_RCC_SAI1_A_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_SAI1ASRC \| (RCC_DCKCFGR_SAI1ASRC_0 >> 16)) /!< PLLI2S clock used as SAI1 block A clock source /
lypinator	0:bb348c97df44	413	#define LL_RCC_SAI1_A_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_SAI1ASRC \| (RCC_DCKCFGR_SAI1ASRC_1 >> 16)) /!< External pin clock used as SAI1 block A clock source /
lypinator	0:bb348c97df44	414	#endif /* RCC_SAI1A_PLLSOURCE_SUPPORT */
lypinator	0:bb348c97df44	415	#endif /* RCC_DCKCFGR_SAI1ASRC */
lypinator	0:bb348c97df44	416	#if defined(RCC_DCKCFGR_SAI1BSRC)
lypinator	0:bb348c97df44	417	#if defined(RCC_SAI1B_PLLSOURCE_SUPPORT)
lypinator	0:bb348c97df44	418	#define LL_RCC_SAI1_B_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_SAI1BSRC \| 0x00000000U) /!< PLLI2S clock used as SAI1 block B clock source /
lypinator	0:bb348c97df44	419	#define LL_RCC_SAI1_B_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_SAI1BSRC \| (RCC_DCKCFGR_SAI1BSRC_0 >> 16)) /!< External pin used as SAI1 block B clock source /
lypinator	0:bb348c97df44	420	#define LL_RCC_SAI1_B_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_SAI1BSRC \| (RCC_DCKCFGR_SAI1BSRC_1 >> 16)) /!< PLL clock used as SAI1 block B clock source /
lypinator	0:bb348c97df44	421	#define LL_RCC_SAI1_B_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR_SAI1BSRC \| (RCC_DCKCFGR_SAI1BSRC >> 16)) /!< PLL Main clock used as SAI1 block B clock source /
lypinator	0:bb348c97df44	422	#else
lypinator	0:bb348c97df44	423	#define LL_RCC_SAI1_B_CLKSOURCE_PLLSAI (uint32_t)(RCC_DCKCFGR_SAI1BSRC \| 0x00000000U) /!< PLLSAI clock used as SAI1 block B clock source /
lypinator	0:bb348c97df44	424	#define LL_RCC_SAI1_B_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_SAI1BSRC \| (RCC_DCKCFGR_SAI1BSRC_0 >> 16)) /!< PLLI2S clock used as SAI1 block B clock source /
lypinator	0:bb348c97df44	425	#define LL_RCC_SAI1_B_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_SAI1BSRC \| (RCC_DCKCFGR_SAI1BSRC_1 >> 16)) /!< External pin clock used as SAI1 block B clock source /
lypinator	0:bb348c97df44	426	#endif /* RCC_SAI1B_PLLSOURCE_SUPPORT */
lypinator	0:bb348c97df44	427	#endif /* RCC_DCKCFGR_SAI1BSRC */
lypinator	0:bb348c97df44	428	/**
lypinator	0:bb348c97df44	429	* @}
lypinator	0:bb348c97df44	430	*/
lypinator	0:bb348c97df44	431	#endif /* SAI1 */
lypinator	0:bb348c97df44	432
lypinator	0:bb348c97df44	433	#if defined(RCC_DCKCFGR_SDIOSEL) \|\| defined(RCC_DCKCFGR2_SDIOSEL)
lypinator	0:bb348c97df44	434	/** @defgroup RCC_LL_EC_SDIOx_CLKSOURCE Peripheral SDIO clock source selection
lypinator	0:bb348c97df44	435	* @{
lypinator	0:bb348c97df44	436	*/
lypinator	0:bb348c97df44	437	#define LL_RCC_SDIO_CLKSOURCE_PLL48CLK 0x00000000U /!< PLL 48M domain clock used as SDIO clock /
lypinator	0:bb348c97df44	438	#if defined(RCC_DCKCFGR_SDIOSEL)
lypinator	0:bb348c97df44	439	#define LL_RCC_SDIO_CLKSOURCE_SYSCLK RCC_DCKCFGR_SDIOSEL /!< System clock clock used as SDIO clock /
lypinator	0:bb348c97df44	440	#else
lypinator	0:bb348c97df44	441	#define LL_RCC_SDIO_CLKSOURCE_SYSCLK RCC_DCKCFGR2_SDIOSEL /!< System clock clock used as SDIO clock /
lypinator	0:bb348c97df44	442	#endif /* RCC_DCKCFGR_SDIOSEL */
lypinator	0:bb348c97df44	443	/**
lypinator	0:bb348c97df44	444	* @}
lypinator	0:bb348c97df44	445	*/
lypinator	0:bb348c97df44	446	#endif /* RCC_DCKCFGR_SDIOSEL \|\| RCC_DCKCFGR2_SDIOSEL */
lypinator	0:bb348c97df44	447
lypinator	0:bb348c97df44	448	#if defined(DSI)
lypinator	0:bb348c97df44	449	/** @defgroup RCC_LL_EC_DSI_CLKSOURCE Peripheral DSI clock source selection
lypinator	0:bb348c97df44	450	* @{
lypinator	0:bb348c97df44	451	*/
lypinator	0:bb348c97df44	452	#define LL_RCC_DSI_CLKSOURCE_PHY 0x00000000U /!< DSI-PHY clock used as DSI byte lane clock source /
lypinator	0:bb348c97df44	453	#define LL_RCC_DSI_CLKSOURCE_PLL RCC_DCKCFGR_DSISEL /!< PLL clock used as DSI byte lane clock source /
lypinator	0:bb348c97df44	454	/**
lypinator	0:bb348c97df44	455	* @}
lypinator	0:bb348c97df44	456	*/
lypinator	0:bb348c97df44	457	#endif /* DSI */
lypinator	0:bb348c97df44	458
lypinator	0:bb348c97df44	459	#if defined(CEC)
lypinator	0:bb348c97df44	460	/** @defgroup RCC_LL_EC_CEC_CLKSOURCE Peripheral CEC clock source selection
lypinator	0:bb348c97df44	461	* @{
lypinator	0:bb348c97df44	462	*/
lypinator	0:bb348c97df44	463	#define LL_RCC_CEC_CLKSOURCE_HSI_DIV488 0x00000000U /!< HSI oscillator clock divided by 488 used as CEC clock /
lypinator	0:bb348c97df44	464	#define LL_RCC_CEC_CLKSOURCE_LSE RCC_DCKCFGR2_CECSEL /!< LSE oscillator clock used as CEC clock /
lypinator	0:bb348c97df44	465	/**
lypinator	0:bb348c97df44	466	* @}
lypinator	0:bb348c97df44	467	*/
lypinator	0:bb348c97df44	468	#endif /* CEC */
lypinator	0:bb348c97df44	469
lypinator	0:bb348c97df44	470	/** @defgroup RCC_LL_EC_I2S1_CLKSOURCE Peripheral I2S clock source selection
lypinator	0:bb348c97df44	471	* @{
lypinator	0:bb348c97df44	472	*/
lypinator	0:bb348c97df44	473	#if defined(RCC_CFGR_I2SSRC)
lypinator	0:bb348c97df44	474	#define LL_RCC_I2S1_CLKSOURCE_PLLI2S 0x00000000U /!< I2S oscillator clock used as I2S1 clock /
lypinator	0:bb348c97df44	475	#define LL_RCC_I2S1_CLKSOURCE_PIN RCC_CFGR_I2SSRC /!< External pin clock used as I2S1 clock /
lypinator	0:bb348c97df44	476	#endif /* RCC_CFGR_I2SSRC */
lypinator	0:bb348c97df44	477	#if defined(RCC_DCKCFGR_I2SSRC)
lypinator	0:bb348c97df44	478	#define LL_RCC_I2S1_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_I2SSRC \| 0x00000000U) /!< PLL clock used as I2S1 clock source /
lypinator	0:bb348c97df44	479	#define LL_RCC_I2S1_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_I2SSRC \| (RCC_DCKCFGR_I2SSRC_0 >> 16)) /!< External pin used as I2S1 clock source /
lypinator	0:bb348c97df44	480	#define LL_RCC_I2S1_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR_I2SSRC \| (RCC_DCKCFGR_I2SSRC_1 >> 16)) /!< PLL Main clock used as I2S1 clock source /
lypinator	0:bb348c97df44	481	#endif /* RCC_DCKCFGR_I2SSRC */
lypinator	0:bb348c97df44	482	#if defined(RCC_DCKCFGR_I2S1SRC)
lypinator	0:bb348c97df44	483	#define LL_RCC_I2S1_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_I2S1SRC \| 0x00000000U) /!< PLLI2S clock used as I2S1 clock source /
lypinator	0:bb348c97df44	484	#define LL_RCC_I2S1_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_I2S1SRC \| (RCC_DCKCFGR_I2S1SRC_0 >> 16)) /!< External pin used as I2S1 clock source /
lypinator	0:bb348c97df44	485	#define LL_RCC_I2S1_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_I2S1SRC \| (RCC_DCKCFGR_I2S1SRC_1 >> 16)) /!< PLL clock used as I2S1 clock source /
lypinator	0:bb348c97df44	486	#define LL_RCC_I2S1_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR_I2S1SRC \| (RCC_DCKCFGR_I2S1SRC >> 16)) /!< PLL Main clock used as I2S1 clock source /
lypinator	0:bb348c97df44	487	#endif /* RCC_DCKCFGR_I2S1SRC */
lypinator	0:bb348c97df44	488	#if defined(RCC_DCKCFGR_I2S2SRC)
lypinator	0:bb348c97df44	489	#define LL_RCC_I2S2_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_I2S2SRC \| 0x00000000U) /!< PLLI2S clock used as I2S2 clock source /
lypinator	0:bb348c97df44	490	#define LL_RCC_I2S2_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_I2S2SRC \| (RCC_DCKCFGR_I2S2SRC_0 >> 16)) /!< External pin used as I2S2 clock source /
lypinator	0:bb348c97df44	491	#define LL_RCC_I2S2_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_I2S2SRC \| (RCC_DCKCFGR_I2S2SRC_1 >> 16)) /!< PLL clock used as I2S2 clock source /
lypinator	0:bb348c97df44	492	#define LL_RCC_I2S2_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR_I2S2SRC \| (RCC_DCKCFGR_I2S2SRC >> 16)) /!< PLL Main clock used as I2S2 clock source /
lypinator	0:bb348c97df44	493	#endif /* RCC_DCKCFGR_I2S2SRC */
lypinator	0:bb348c97df44	494	/**
lypinator	0:bb348c97df44	495	* @}
lypinator	0:bb348c97df44	496	*/
lypinator	0:bb348c97df44	497
lypinator	0:bb348c97df44	498	#if defined(RCC_DCKCFGR_CK48MSEL) \|\| defined(RCC_DCKCFGR2_CK48MSEL)
lypinator	0:bb348c97df44	499	/** @defgroup RCC_LL_EC_CK48M_CLKSOURCE Peripheral 48Mhz domain clock source selection
lypinator	0:bb348c97df44	500	* @{
lypinator	0:bb348c97df44	501	*/
lypinator	0:bb348c97df44	502	#if defined(RCC_DCKCFGR_CK48MSEL)
lypinator	0:bb348c97df44	503	#define LL_RCC_CK48M_CLKSOURCE_PLL 0x00000000U /!< PLL oscillator clock used as 48Mhz domain clock /
lypinator	0:bb348c97df44	504	#define LL_RCC_CK48M_CLKSOURCE_PLLSAI RCC_DCKCFGR_CK48MSEL /!< PLLSAI oscillator clock used as 48Mhz domain clock /
lypinator	0:bb348c97df44	505	#endif /* RCC_DCKCFGR_CK48MSEL */
lypinator	0:bb348c97df44	506	#if defined(RCC_DCKCFGR2_CK48MSEL)
lypinator	0:bb348c97df44	507	#define LL_RCC_CK48M_CLKSOURCE_PLL 0x00000000U /!< PLL oscillator clock used as 48Mhz domain clock /
lypinator	0:bb348c97df44	508	#if defined(RCC_PLLSAI_SUPPORT)
lypinator	0:bb348c97df44	509	#define LL_RCC_CK48M_CLKSOURCE_PLLSAI RCC_DCKCFGR2_CK48MSEL /!< PLLSAI oscillator clock used as 48Mhz domain clock /
lypinator	0:bb348c97df44	510	#endif /* RCC_PLLSAI_SUPPORT */
lypinator	0:bb348c97df44	511	#if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
lypinator	0:bb348c97df44	512	#define LL_RCC_CK48M_CLKSOURCE_PLLI2S RCC_DCKCFGR2_CK48MSEL /!< PLLI2S oscillator clock used as 48Mhz domain clock /
lypinator	0:bb348c97df44	513	#endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
lypinator	0:bb348c97df44	514	#endif /* RCC_DCKCFGR2_CK48MSEL */
lypinator	0:bb348c97df44	515	/**
lypinator	0:bb348c97df44	516	* @}
lypinator	0:bb348c97df44	517	*/
lypinator	0:bb348c97df44	518
lypinator	0:bb348c97df44	519	#if defined(RNG)
lypinator	0:bb348c97df44	520	/** @defgroup RCC_LL_EC_RNG_CLKSOURCE Peripheral RNG clock source selection
lypinator	0:bb348c97df44	521	* @{
lypinator	0:bb348c97df44	522	*/
lypinator	0:bb348c97df44	523	#define LL_RCC_RNG_CLKSOURCE_PLL LL_RCC_CK48M_CLKSOURCE_PLL /!< PLL clock used as RNG clock source /
lypinator	0:bb348c97df44	524	#if defined(RCC_PLLSAI_SUPPORT)
lypinator	0:bb348c97df44	525	#define LL_RCC_RNG_CLKSOURCE_PLLSAI LL_RCC_CK48M_CLKSOURCE_PLLSAI /!< PLLSAI clock used as RNG clock source /
lypinator	0:bb348c97df44	526	#endif /* RCC_PLLSAI_SUPPORT */
lypinator	0:bb348c97df44	527	#if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
lypinator	0:bb348c97df44	528	#define LL_RCC_RNG_CLKSOURCE_PLLI2S LL_RCC_CK48M_CLKSOURCE_PLLI2S /!< PLLI2S clock used as RNG clock source /
lypinator	0:bb348c97df44	529	#endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
lypinator	0:bb348c97df44	530	/**
lypinator	0:bb348c97df44	531	* @}
lypinator	0:bb348c97df44	532	*/
lypinator	0:bb348c97df44	533	#endif /* RNG */
lypinator	0:bb348c97df44	534
lypinator	0:bb348c97df44	535	#if defined(USB_OTG_FS) \|\| defined(USB_OTG_HS)
lypinator	0:bb348c97df44	536	/** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection
lypinator	0:bb348c97df44	537	* @{
lypinator	0:bb348c97df44	538	*/
lypinator	0:bb348c97df44	539	#define LL_RCC_USB_CLKSOURCE_PLL LL_RCC_CK48M_CLKSOURCE_PLL /!< PLL clock used as USB clock source /
lypinator	0:bb348c97df44	540	#if defined(RCC_PLLSAI_SUPPORT)
lypinator	0:bb348c97df44	541	#define LL_RCC_USB_CLKSOURCE_PLLSAI LL_RCC_CK48M_CLKSOURCE_PLLSAI /!< PLLSAI clock used as USB clock source /
lypinator	0:bb348c97df44	542	#endif /* RCC_PLLSAI_SUPPORT */
lypinator	0:bb348c97df44	543	#if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
lypinator	0:bb348c97df44	544	#define LL_RCC_USB_CLKSOURCE_PLLI2S LL_RCC_CK48M_CLKSOURCE_PLLI2S /!< PLLI2S clock used as USB clock source /
lypinator	0:bb348c97df44	545	#endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
lypinator	0:bb348c97df44	546	/**
lypinator	0:bb348c97df44	547	* @}
lypinator	0:bb348c97df44	548	*/
lypinator	0:bb348c97df44	549	#endif /* USB_OTG_FS \|\| USB_OTG_HS */
lypinator	0:bb348c97df44	550
lypinator	0:bb348c97df44	551	#endif /* RCC_DCKCFGR_CK48MSEL \|\| RCC_DCKCFGR2_CK48MSEL */
lypinator	0:bb348c97df44	552
lypinator	0:bb348c97df44	553	#if defined(DFSDM1_Channel0) \|\| defined(DFSDM2_Channel0)
lypinator	0:bb348c97df44	554	/** @defgroup RCC_LL_EC_DFSDM1_AUDIO_CLKSOURCE Peripheral DFSDM Audio clock source selection
lypinator	0:bb348c97df44	555	* @{
lypinator	0:bb348c97df44	556	*/
lypinator	0:bb348c97df44	557	#define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S1 (uint32_t)(RCC_DCKCFGR_CKDFSDM1ASEL \| 0x00000000U) /!< I2S1 clock used as DFSDM1 Audio clock source /
lypinator	0:bb348c97df44	558	#define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S2 (uint32_t)(RCC_DCKCFGR_CKDFSDM1ASEL \| (RCC_DCKCFGR_CKDFSDM1ASEL << 16)) /!< I2S2 clock used as DFSDM1 Audio clock source /
lypinator	0:bb348c97df44	559	#if defined(DFSDM2_Channel0)
lypinator	0:bb348c97df44	560	#define LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S1 (uint32_t)(RCC_DCKCFGR_CKDFSDM2ASEL \| 0x00000000U) /!< I2S1 clock used as DFSDM2 Audio clock source /
lypinator	0:bb348c97df44	561	#define LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S2 (uint32_t)(RCC_DCKCFGR_CKDFSDM2ASEL \| (RCC_DCKCFGR_CKDFSDM2ASEL << 16)) /!< I2S2 clock used as DFSDM2 Audio clock source /
lypinator	0:bb348c97df44	562	#endif /* DFSDM2_Channel0 */
lypinator	0:bb348c97df44	563	/**
lypinator	0:bb348c97df44	564	* @}
lypinator	0:bb348c97df44	565	*/
lypinator	0:bb348c97df44	566
lypinator	0:bb348c97df44	567	/** @defgroup RCC_LL_EC_DFSDM1_CLKSOURCE Peripheral DFSDM clock source selection
lypinator	0:bb348c97df44	568	* @{
lypinator	0:bb348c97df44	569	*/
lypinator	0:bb348c97df44	570	#define LL_RCC_DFSDM1_CLKSOURCE_PCLK2 0x00000000U /!< PCLK2 clock used as DFSDM1 clock /
lypinator	0:bb348c97df44	571	#define LL_RCC_DFSDM1_CLKSOURCE_SYSCLK RCC_DCKCFGR_CKDFSDM1SEL /!< System clock used as DFSDM1 clock /
lypinator	0:bb348c97df44	572	#if defined(DFSDM2_Channel0)
lypinator	0:bb348c97df44	573	#define LL_RCC_DFSDM2_CLKSOURCE_PCLK2 0x00000000U /!< PCLK2 clock used as DFSDM2 clock /
lypinator	0:bb348c97df44	574	#define LL_RCC_DFSDM2_CLKSOURCE_SYSCLK RCC_DCKCFGR_CKDFSDM1SEL /!< System clock used as DFSDM2 clock /
lypinator	0:bb348c97df44	575	#endif /* DFSDM2_Channel0 */
lypinator	0:bb348c97df44	576	/**
lypinator	0:bb348c97df44	577	* @}
lypinator	0:bb348c97df44	578	*/
lypinator	0:bb348c97df44	579	#endif /* DFSDM1_Channel0 \|\| DFSDM2_Channel0 */
lypinator	0:bb348c97df44	580
lypinator	0:bb348c97df44	581	#if defined(FMPI2C1)
lypinator	0:bb348c97df44	582	/** @defgroup RCC_LL_EC_FMPI2C1 Peripheral FMPI2C get clock source
lypinator	0:bb348c97df44	583	* @{
lypinator	0:bb348c97df44	584	*/
lypinator	0:bb348c97df44	585	#define LL_RCC_FMPI2C1_CLKSOURCE RCC_DCKCFGR2_FMPI2C1SEL /!< FMPI2C1 Clock source selection /
lypinator	0:bb348c97df44	586	/**
lypinator	0:bb348c97df44	587	* @}
lypinator	0:bb348c97df44	588	*/
lypinator	0:bb348c97df44	589	#endif /* FMPI2C1 */
lypinator	0:bb348c97df44	590
lypinator	0:bb348c97df44	591	#if defined(SPDIFRX)
lypinator	0:bb348c97df44	592	/** @defgroup RCC_LL_EC_SPDIFRX_CLKSOURCE Peripheral SPDIFRX clock source selection
lypinator	0:bb348c97df44	593	* @{
lypinator	0:bb348c97df44	594	*/
lypinator	0:bb348c97df44	595	#define LL_RCC_SPDIFRX1_CLKSOURCE_PLL 0x00000000U /!< PLL clock used as SPDIFRX clock source /
lypinator	0:bb348c97df44	596	#define LL_RCC_SPDIFRX1_CLKSOURCE_PLLI2S RCC_DCKCFGR2_SPDIFRXSEL /!< PLLI2S clock used as SPDIFRX clock source /
lypinator	0:bb348c97df44	597	/**
lypinator	0:bb348c97df44	598	* @}
lypinator	0:bb348c97df44	599	*/
lypinator	0:bb348c97df44	600	#endif /* SPDIFRX */
lypinator	0:bb348c97df44	601
lypinator	0:bb348c97df44	602	#if defined(LPTIM1)
lypinator	0:bb348c97df44	603	/** @defgroup RCC_LL_EC_LPTIM1 Peripheral LPTIM get clock source
lypinator	0:bb348c97df44	604	* @{
lypinator	0:bb348c97df44	605	*/
lypinator	0:bb348c97df44	606	#define LL_RCC_LPTIM1_CLKSOURCE RCC_DCKCFGR2_LPTIM1SEL /!< LPTIM1 Clock source selection /
lypinator	0:bb348c97df44	607	/**
lypinator	0:bb348c97df44	608	* @}
lypinator	0:bb348c97df44	609	*/
lypinator	0:bb348c97df44	610	#endif /* LPTIM1 */
lypinator	0:bb348c97df44	611
lypinator	0:bb348c97df44	612	#if defined(SAI1)
lypinator	0:bb348c97df44	613	/** @defgroup RCC_LL_EC_SAIx Peripheral SAI get clock source
lypinator	0:bb348c97df44	614	* @{
lypinator	0:bb348c97df44	615	*/
lypinator	0:bb348c97df44	616	#if defined(RCC_DCKCFGR_SAI1ASRC)
lypinator	0:bb348c97df44	617	#define LL_RCC_SAI1_A_CLKSOURCE RCC_DCKCFGR_SAI1ASRC /!< SAI1 block A Clock source selection /
lypinator	0:bb348c97df44	618	#endif /* RCC_DCKCFGR_SAI1ASRC */
lypinator	0:bb348c97df44	619	#if defined(RCC_DCKCFGR_SAI1BSRC)
lypinator	0:bb348c97df44	620	#define LL_RCC_SAI1_B_CLKSOURCE RCC_DCKCFGR_SAI1BSRC /!< SAI1 block B Clock source selection /
lypinator	0:bb348c97df44	621	#endif /* RCC_DCKCFGR_SAI1BSRC */
lypinator	0:bb348c97df44	622	#if defined(RCC_DCKCFGR_SAI1SRC)
lypinator	0:bb348c97df44	623	#define LL_RCC_SAI1_CLKSOURCE RCC_DCKCFGR_SAI1SRC /!< SAI1 Clock source selection /
lypinator	0:bb348c97df44	624	#endif /* RCC_DCKCFGR_SAI1SRC */
lypinator	0:bb348c97df44	625	#if defined(RCC_DCKCFGR_SAI2SRC)
lypinator	0:bb348c97df44	626	#define LL_RCC_SAI2_CLKSOURCE RCC_DCKCFGR_SAI2SRC /!< SAI2 Clock source selection /
lypinator	0:bb348c97df44	627	#endif /* RCC_DCKCFGR_SAI2SRC */
lypinator	0:bb348c97df44	628	/**
lypinator	0:bb348c97df44	629	* @}
lypinator	0:bb348c97df44	630	*/
lypinator	0:bb348c97df44	631	#endif /* SAI1 */
lypinator	0:bb348c97df44	632
lypinator	0:bb348c97df44	633	#if defined(SDIO)
lypinator	0:bb348c97df44	634	/** @defgroup RCC_LL_EC_SDIOx Peripheral SDIO get clock source
lypinator	0:bb348c97df44	635	* @{
lypinator	0:bb348c97df44	636	*/
lypinator	0:bb348c97df44	637	#if defined(RCC_DCKCFGR_SDIOSEL)
lypinator	0:bb348c97df44	638	#define LL_RCC_SDIO_CLKSOURCE RCC_DCKCFGR_SDIOSEL /!< SDIO Clock source selection /
lypinator	0:bb348c97df44	639	#elif defined(RCC_DCKCFGR2_SDIOSEL)
lypinator	0:bb348c97df44	640	#define LL_RCC_SDIO_CLKSOURCE RCC_DCKCFGR2_SDIOSEL /!< SDIO Clock source selection /
lypinator	0:bb348c97df44	641	#else
lypinator	0:bb348c97df44	642	#define LL_RCC_SDIO_CLKSOURCE RCC_PLLCFGR_PLLQ /!< SDIO Clock source selection /
lypinator	0:bb348c97df44	643	#endif
lypinator	0:bb348c97df44	644	/**
lypinator	0:bb348c97df44	645	* @}
lypinator	0:bb348c97df44	646	*/
lypinator	0:bb348c97df44	647	#endif /* SDIO */
lypinator	0:bb348c97df44	648
lypinator	0:bb348c97df44	649	#if defined(RCC_DCKCFGR_CK48MSEL) \|\| defined(RCC_DCKCFGR2_CK48MSEL)
lypinator	0:bb348c97df44	650	/** @defgroup RCC_LL_EC_CK48M Peripheral CK48M get clock source
lypinator	0:bb348c97df44	651	* @{
lypinator	0:bb348c97df44	652	*/
lypinator	0:bb348c97df44	653	#if defined(RCC_DCKCFGR_CK48MSEL)
lypinator	0:bb348c97df44	654	#define LL_RCC_CK48M_CLKSOURCE RCC_DCKCFGR_CK48MSEL /!< CK48M Domain clock source selection /
lypinator	0:bb348c97df44	655	#endif /* RCC_DCKCFGR_CK48MSEL */
lypinator	0:bb348c97df44	656	#if defined(RCC_DCKCFGR2_CK48MSEL)
lypinator	0:bb348c97df44	657	#define LL_RCC_CK48M_CLKSOURCE RCC_DCKCFGR2_CK48MSEL /!< CK48M Domain clock source selection /
lypinator	0:bb348c97df44	658	#endif /* RCC_DCKCFGR_CK48MSEL */
lypinator	0:bb348c97df44	659	/**
lypinator	0:bb348c97df44	660	* @}
lypinator	0:bb348c97df44	661	*/
lypinator	0:bb348c97df44	662	#endif /* RCC_DCKCFGR_CK48MSEL \|\| RCC_DCKCFGR2_CK48MSEL */
lypinator	0:bb348c97df44	663
lypinator	0:bb348c97df44	664	#if defined(RNG)
lypinator	0:bb348c97df44	665	/** @defgroup RCC_LL_EC_RNG Peripheral RNG get clock source
lypinator	0:bb348c97df44	666	* @{
lypinator	0:bb348c97df44	667	*/
lypinator	0:bb348c97df44	668	#if defined(RCC_DCKCFGR_CK48MSEL) \|\| defined(RCC_DCKCFGR2_CK48MSEL)
lypinator	0:bb348c97df44	669	#define LL_RCC_RNG_CLKSOURCE LL_RCC_CK48M_CLKSOURCE /!< RNG Clock source selection /
lypinator	0:bb348c97df44	670	#else
lypinator	0:bb348c97df44	671	#define LL_RCC_RNG_CLKSOURCE RCC_PLLCFGR_PLLQ /!< RNG Clock source selection /
lypinator	0:bb348c97df44	672	#endif /* RCC_DCKCFGR_CK48MSEL \|\| RCC_DCKCFGR2_CK48MSEL */
lypinator	0:bb348c97df44	673	/**
lypinator	0:bb348c97df44	674	* @}
lypinator	0:bb348c97df44	675	*/
lypinator	0:bb348c97df44	676	#endif /* RNG */
lypinator	0:bb348c97df44	677
lypinator	0:bb348c97df44	678	#if defined(USB_OTG_FS) \|\| defined(USB_OTG_HS)
lypinator	0:bb348c97df44	679	/** @defgroup RCC_LL_EC_USB Peripheral USB get clock source
lypinator	0:bb348c97df44	680	* @{
lypinator	0:bb348c97df44	681	*/
lypinator	0:bb348c97df44	682	#if defined(RCC_DCKCFGR_CK48MSEL) \|\| defined(RCC_DCKCFGR2_CK48MSEL)
lypinator	0:bb348c97df44	683	#define LL_RCC_USB_CLKSOURCE LL_RCC_CK48M_CLKSOURCE /!< USB Clock source selection /
lypinator	0:bb348c97df44	684	#else
lypinator	0:bb348c97df44	685	#define LL_RCC_USB_CLKSOURCE RCC_PLLCFGR_PLLQ /!< USB Clock source selection /
lypinator	0:bb348c97df44	686	#endif /* RCC_DCKCFGR_CK48MSEL \|\| RCC_DCKCFGR2_CK48MSEL */
lypinator	0:bb348c97df44	687	/**
lypinator	0:bb348c97df44	688	* @}
lypinator	0:bb348c97df44	689	*/
lypinator	0:bb348c97df44	690	#endif /* USB_OTG_FS \|\| USB_OTG_HS */
lypinator	0:bb348c97df44	691
lypinator	0:bb348c97df44	692	#if defined(CEC)
lypinator	0:bb348c97df44	693	/** @defgroup RCC_LL_EC_CEC Peripheral CEC get clock source
lypinator	0:bb348c97df44	694	* @{
lypinator	0:bb348c97df44	695	*/
lypinator	0:bb348c97df44	696	#define LL_RCC_CEC_CLKSOURCE RCC_DCKCFGR2_CECSEL /!< CEC Clock source selection /
lypinator	0:bb348c97df44	697	/**
lypinator	0:bb348c97df44	698	* @}
lypinator	0:bb348c97df44	699	*/
lypinator	0:bb348c97df44	700	#endif /* CEC */
lypinator	0:bb348c97df44	701
lypinator	0:bb348c97df44	702	/** @defgroup RCC_LL_EC_I2S1 Peripheral I2S get clock source
lypinator	0:bb348c97df44	703	* @{
lypinator	0:bb348c97df44	704	*/
lypinator	0:bb348c97df44	705	#if defined(RCC_CFGR_I2SSRC)
lypinator	0:bb348c97df44	706	#define LL_RCC_I2S1_CLKSOURCE RCC_CFGR_I2SSRC /!< I2S1 Clock source selection /
lypinator	0:bb348c97df44	707	#endif /* RCC_CFGR_I2SSRC */
lypinator	0:bb348c97df44	708	#if defined(RCC_DCKCFGR_I2SSRC)
lypinator	0:bb348c97df44	709	#define LL_RCC_I2S1_CLKSOURCE RCC_DCKCFGR_I2SSRC /!< I2S1 Clock source selection /
lypinator	0:bb348c97df44	710	#endif /* RCC_DCKCFGR_I2SSRC */
lypinator	0:bb348c97df44	711	#if defined(RCC_DCKCFGR_I2S1SRC)
lypinator	0:bb348c97df44	712	#define LL_RCC_I2S1_CLKSOURCE RCC_DCKCFGR_I2S1SRC /!< I2S1 Clock source selection /
lypinator	0:bb348c97df44	713	#endif /* RCC_DCKCFGR_I2S1SRC */
lypinator	0:bb348c97df44	714	#if defined(RCC_DCKCFGR_I2S2SRC)
lypinator	0:bb348c97df44	715	#define LL_RCC_I2S2_CLKSOURCE RCC_DCKCFGR_I2S2SRC /!< I2S2 Clock source selection /
lypinator	0:bb348c97df44	716	#endif /* RCC_DCKCFGR_I2S2SRC */
lypinator	0:bb348c97df44	717	/**
lypinator	0:bb348c97df44	718	* @}
lypinator	0:bb348c97df44	719	*/
lypinator	0:bb348c97df44	720
lypinator	0:bb348c97df44	721	#if defined(DFSDM1_Channel0) \|\| defined(DFSDM2_Channel0)
lypinator	0:bb348c97df44	722	/** @defgroup RCC_LL_EC_DFSDM_AUDIO Peripheral DFSDM Audio get clock source
lypinator	0:bb348c97df44	723	* @{
lypinator	0:bb348c97df44	724	*/
lypinator	0:bb348c97df44	725	#define LL_RCC_DFSDM1_AUDIO_CLKSOURCE RCC_DCKCFGR_CKDFSDM1ASEL /!< DFSDM1 Audio Clock source selection /
lypinator	0:bb348c97df44	726	#if defined(DFSDM2_Channel0)
lypinator	0:bb348c97df44	727	#define LL_RCC_DFSDM2_AUDIO_CLKSOURCE RCC_DCKCFGR_CKDFSDM2ASEL /!< DFSDM2 Audio Clock source selection /
lypinator	0:bb348c97df44	728	#endif /* DFSDM2_Channel0 */
lypinator	0:bb348c97df44	729	/**
lypinator	0:bb348c97df44	730	* @}
lypinator	0:bb348c97df44	731	*/
lypinator	0:bb348c97df44	732
lypinator	0:bb348c97df44	733	/** @defgroup RCC_LL_EC_DFSDM Peripheral DFSDM get clock source
lypinator	0:bb348c97df44	734	* @{
lypinator	0:bb348c97df44	735	*/
lypinator	0:bb348c97df44	736	#define LL_RCC_DFSDM1_CLKSOURCE RCC_DCKCFGR_CKDFSDM1SEL /!< DFSDM1 Clock source selection /
lypinator	0:bb348c97df44	737	#if defined(DFSDM2_Channel0)
lypinator	0:bb348c97df44	738	#define LL_RCC_DFSDM2_CLKSOURCE RCC_DCKCFGR_CKDFSDM1SEL /!< DFSDM2 Clock source selection /
lypinator	0:bb348c97df44	739	#endif /* DFSDM2_Channel0 */
lypinator	0:bb348c97df44	740	/**
lypinator	0:bb348c97df44	741	* @}
lypinator	0:bb348c97df44	742	*/
lypinator	0:bb348c97df44	743	#endif /* DFSDM1_Channel0 \|\| DFSDM2_Channel0 */
lypinator	0:bb348c97df44	744
lypinator	0:bb348c97df44	745	#if defined(SPDIFRX)
lypinator	0:bb348c97df44	746	/** @defgroup RCC_LL_EC_SPDIFRX Peripheral SPDIFRX get clock source
lypinator	0:bb348c97df44	747	* @{
lypinator	0:bb348c97df44	748	*/
lypinator	0:bb348c97df44	749	#define LL_RCC_SPDIFRX1_CLKSOURCE RCC_DCKCFGR2_SPDIFRXSEL /!< SPDIFRX Clock source selection /
lypinator	0:bb348c97df44	750	/**
lypinator	0:bb348c97df44	751	* @}
lypinator	0:bb348c97df44	752	*/
lypinator	0:bb348c97df44	753	#endif /* SPDIFRX */
lypinator	0:bb348c97df44	754
lypinator	0:bb348c97df44	755	#if defined(DSI)
lypinator	0:bb348c97df44	756	/** @defgroup RCC_LL_EC_DSI Peripheral DSI get clock source
lypinator	0:bb348c97df44	757	* @{
lypinator	0:bb348c97df44	758	*/
lypinator	0:bb348c97df44	759	#define LL_RCC_DSI_CLKSOURCE RCC_DCKCFGR_DSISEL /!< DSI Clock source selection /
lypinator	0:bb348c97df44	760	/**
lypinator	0:bb348c97df44	761	* @}
lypinator	0:bb348c97df44	762	*/
lypinator	0:bb348c97df44	763	#endif /* DSI */
lypinator	0:bb348c97df44	764
lypinator	0:bb348c97df44	765	#if defined(LTDC)
lypinator	0:bb348c97df44	766	/** @defgroup RCC_LL_EC_LTDC Peripheral LTDC get clock source
lypinator	0:bb348c97df44	767	* @{
lypinator	0:bb348c97df44	768	*/
lypinator	0:bb348c97df44	769	#define LL_RCC_LTDC_CLKSOURCE RCC_DCKCFGR_PLLSAIDIVR /!< LTDC Clock source selection /
lypinator	0:bb348c97df44	770	/**
lypinator	0:bb348c97df44	771	* @}
lypinator	0:bb348c97df44	772	*/
lypinator	0:bb348c97df44	773	#endif /* LTDC */
lypinator	0:bb348c97df44	774
lypinator	0:bb348c97df44	775
lypinator	0:bb348c97df44	776	/** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection
lypinator	0:bb348c97df44	777	* @{
lypinator	0:bb348c97df44	778	*/
lypinator	0:bb348c97df44	779	#define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /!< No clock used as RTC clock /
lypinator	0:bb348c97df44	780	#define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /!< LSE oscillator clock used as RTC clock /
lypinator	0:bb348c97df44	781	#define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /!< LSI oscillator clock used as RTC clock /
lypinator	0:bb348c97df44	782	#define LL_RCC_RTC_CLKSOURCE_HSE RCC_BDCR_RTCSEL /!< HSE oscillator clock divided by HSE prescaler used as RTC clock /
lypinator	0:bb348c97df44	783	/**
lypinator	0:bb348c97df44	784	* @}
lypinator	0:bb348c97df44	785	*/
lypinator	0:bb348c97df44	786
lypinator	0:bb348c97df44	787	#if defined(RCC_DCKCFGR_TIMPRE)
lypinator	0:bb348c97df44	788	/** @defgroup RCC_LL_EC_TIM_CLKPRESCALER Timers clocks prescalers selection
lypinator	0:bb348c97df44	789	* @{
lypinator	0:bb348c97df44	790	*/
lypinator	0:bb348c97df44	791	#define LL_RCC_TIM_PRESCALER_TWICE 0x00000000U /!< Timers clock to twice PCLK /
lypinator	0:bb348c97df44	792	#define LL_RCC_TIM_PRESCALER_FOUR_TIMES RCC_DCKCFGR_TIMPRE /!< Timers clock to four time PCLK /
lypinator	0:bb348c97df44	793	/**
lypinator	0:bb348c97df44	794	* @}
lypinator	0:bb348c97df44	795	*/
lypinator	0:bb348c97df44	796	#endif /* RCC_DCKCFGR_TIMPRE */
lypinator	0:bb348c97df44	797
lypinator	0:bb348c97df44	798	/** @defgroup RCC_LL_EC_PLLSOURCE PLL, PLLI2S and PLLSAI entry clock source
lypinator	0:bb348c97df44	799	* @{
lypinator	0:bb348c97df44	800	*/
lypinator	0:bb348c97df44	801	#define LL_RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI /!< HSI16 clock selected as PLL entry clock source /
lypinator	0:bb348c97df44	802	#define LL_RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE /!< HSE clock selected as PLL entry clock source /
lypinator	0:bb348c97df44	803	#if defined(RCC_PLLI2SCFGR_PLLI2SSRC)
lypinator	0:bb348c97df44	804	#define LL_RCC_PLLI2SSOURCE_PIN (RCC_PLLI2SCFGR_PLLI2SSRC \| 0x80U) /!< I2S External pin input clock selected as PLLI2S entry clock source /
lypinator	0:bb348c97df44	805	#endif /* RCC_PLLI2SCFGR_PLLI2SSRC */
lypinator	0:bb348c97df44	806	/**
lypinator	0:bb348c97df44	807	* @}
lypinator	0:bb348c97df44	808	*/
lypinator	0:bb348c97df44	809
lypinator	0:bb348c97df44	810	/** @defgroup RCC_LL_EC_PLLM_DIV PLL, PLLI2S and PLLSAI division factor
lypinator	0:bb348c97df44	811	* @{
lypinator	0:bb348c97df44	812	*/
lypinator	0:bb348c97df44	813	#define LL_RCC_PLLM_DIV_2 (RCC_PLLCFGR_PLLM_1) /!< PLL, PLLI2S and PLLSAI division factor by 2 /
lypinator	0:bb348c97df44	814	#define LL_RCC_PLLM_DIV_3 (RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 3 /
lypinator	0:bb348c97df44	815	#define LL_RCC_PLLM_DIV_4 (RCC_PLLCFGR_PLLM_2) /!< PLL, PLLI2S and PLLSAI division factor by 4 /
lypinator	0:bb348c97df44	816	#define LL_RCC_PLLM_DIV_5 (RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 5 /
lypinator	0:bb348c97df44	817	#define LL_RCC_PLLM_DIV_6 (RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1) /!< PLL, PLLI2S and PLLSAI division factor by 6 /
lypinator	0:bb348c97df44	818	#define LL_RCC_PLLM_DIV_7 (RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 7 /
lypinator	0:bb348c97df44	819	#define LL_RCC_PLLM_DIV_8 (RCC_PLLCFGR_PLLM_3) /!< PLL, PLLI2S and PLLSAI division factor by 8 /
lypinator	0:bb348c97df44	820	#define LL_RCC_PLLM_DIV_9 (RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 9 /
lypinator	0:bb348c97df44	821	#define LL_RCC_PLLM_DIV_10 (RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_1) /!< PLL, PLLI2S and PLLSAI division factor by 10 /
lypinator	0:bb348c97df44	822	#define LL_RCC_PLLM_DIV_11 (RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 11 /
lypinator	0:bb348c97df44	823	#define LL_RCC_PLLM_DIV_12 (RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2) /!< PLL, PLLI2S and PLLSAI division factor by 12 /
lypinator	0:bb348c97df44	824	#define LL_RCC_PLLM_DIV_13 (RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 13 /
lypinator	0:bb348c97df44	825	#define LL_RCC_PLLM_DIV_14 (RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1) /!< PLL, PLLI2S and PLLSAI division factor by 14 /
lypinator	0:bb348c97df44	826	#define LL_RCC_PLLM_DIV_15 (RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 15 /
lypinator	0:bb348c97df44	827	#define LL_RCC_PLLM_DIV_16 (RCC_PLLCFGR_PLLM_4) /!< PLL, PLLI2S and PLLSAI division factor by 16 /
lypinator	0:bb348c97df44	828	#define LL_RCC_PLLM_DIV_17 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 17 /
lypinator	0:bb348c97df44	829	#define LL_RCC_PLLM_DIV_18 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_1) /!< PLL, PLLI2S and PLLSAI division factor by 18 /
lypinator	0:bb348c97df44	830	#define LL_RCC_PLLM_DIV_19 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 19 /
lypinator	0:bb348c97df44	831	#define LL_RCC_PLLM_DIV_20 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_2) /!< PLL, PLLI2S and PLLSAI division factor by 20 /
lypinator	0:bb348c97df44	832	#define LL_RCC_PLLM_DIV_21 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 21 /
lypinator	0:bb348c97df44	833	#define LL_RCC_PLLM_DIV_22 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1) /!< PLL, PLLI2S and PLLSAI division factor by 22 /
lypinator	0:bb348c97df44	834	#define LL_RCC_PLLM_DIV_23 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 23 /
lypinator	0:bb348c97df44	835	#define LL_RCC_PLLM_DIV_24 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3) /!< PLL, PLLI2S and PLLSAI division factor by 24 /
lypinator	0:bb348c97df44	836	#define LL_RCC_PLLM_DIV_25 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 25 /
lypinator	0:bb348c97df44	837	#define LL_RCC_PLLM_DIV_26 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_1) /!< PLL, PLLI2S and PLLSAI division factor by 26 /
lypinator	0:bb348c97df44	838	#define LL_RCC_PLLM_DIV_27 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 27 /
lypinator	0:bb348c97df44	839	#define LL_RCC_PLLM_DIV_28 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2) /!< PLL, PLLI2S and PLLSAI division factor by 28 /
lypinator	0:bb348c97df44	840	#define LL_RCC_PLLM_DIV_29 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 29 /
lypinator	0:bb348c97df44	841	#define LL_RCC_PLLM_DIV_30 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1) /!< PLL, PLLI2S and PLLSAI division factor by 30 /
lypinator	0:bb348c97df44	842	#define LL_RCC_PLLM_DIV_31 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 31 /
lypinator	0:bb348c97df44	843	#define LL_RCC_PLLM_DIV_32 (RCC_PLLCFGR_PLLM_5) /!< PLL, PLLI2S and PLLSAI division factor by 32 /
lypinator	0:bb348c97df44	844	#define LL_RCC_PLLM_DIV_33 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 33 /
lypinator	0:bb348c97df44	845	#define LL_RCC_PLLM_DIV_34 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_1) /!< PLL, PLLI2S and PLLSAI division factor by 34 /
lypinator	0:bb348c97df44	846	#define LL_RCC_PLLM_DIV_35 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 35 /
lypinator	0:bb348c97df44	847	#define LL_RCC_PLLM_DIV_36 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_2) /!< PLL, PLLI2S and PLLSAI division factor by 36 /
lypinator	0:bb348c97df44	848	#define LL_RCC_PLLM_DIV_37 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 37 /
lypinator	0:bb348c97df44	849	#define LL_RCC_PLLM_DIV_38 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1) /!< PLL, PLLI2S and PLLSAI division factor by 38 /
lypinator	0:bb348c97df44	850	#define LL_RCC_PLLM_DIV_39 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 39 /
lypinator	0:bb348c97df44	851	#define LL_RCC_PLLM_DIV_40 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_3) /!< PLL, PLLI2S and PLLSAI division factor by 40 /
lypinator	0:bb348c97df44	852	#define LL_RCC_PLLM_DIV_41 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 41 /
lypinator	0:bb348c97df44	853	#define LL_RCC_PLLM_DIV_42 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_1) /!< PLL, PLLI2S and PLLSAI division factor by 42 /
lypinator	0:bb348c97df44	854	#define LL_RCC_PLLM_DIV_43 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 43 /
lypinator	0:bb348c97df44	855	#define LL_RCC_PLLM_DIV_44 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2) /!< PLL, PLLI2S and PLLSAI division factor by 44 /
lypinator	0:bb348c97df44	856	#define LL_RCC_PLLM_DIV_45 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 45 /
lypinator	0:bb348c97df44	857	#define LL_RCC_PLLM_DIV_46 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1) /!< PLL, PLLI2S and PLLSAI division factor by 46 /
lypinator	0:bb348c97df44	858	#define LL_RCC_PLLM_DIV_47 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 47 /
lypinator	0:bb348c97df44	859	#define LL_RCC_PLLM_DIV_48 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4) /!< PLL, PLLI2S and PLLSAI division factor by 48 /
lypinator	0:bb348c97df44	860	#define LL_RCC_PLLM_DIV_49 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 49 /
lypinator	0:bb348c97df44	861	#define LL_RCC_PLLM_DIV_50 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_1) /!< PLL, PLLI2S and PLLSAI division factor by 50 /
lypinator	0:bb348c97df44	862	#define LL_RCC_PLLM_DIV_51 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 51 /
lypinator	0:bb348c97df44	863	#define LL_RCC_PLLM_DIV_52 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_2) /!< PLL, PLLI2S and PLLSAI division factor by 52 /
lypinator	0:bb348c97df44	864	#define LL_RCC_PLLM_DIV_53 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 53 /
lypinator	0:bb348c97df44	865	#define LL_RCC_PLLM_DIV_54 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1) /!< PLL, PLLI2S and PLLSAI division factor by 54 /
lypinator	0:bb348c97df44	866	#define LL_RCC_PLLM_DIV_55 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 55 /
lypinator	0:bb348c97df44	867	#define LL_RCC_PLLM_DIV_56 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3) /!< PLL, PLLI2S and PLLSAI division factor by 56 /
lypinator	0:bb348c97df44	868	#define LL_RCC_PLLM_DIV_57 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 57 /
lypinator	0:bb348c97df44	869	#define LL_RCC_PLLM_DIV_58 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_1) /!< PLL, PLLI2S and PLLSAI division factor by 58 /
lypinator	0:bb348c97df44	870	#define LL_RCC_PLLM_DIV_59 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 59 /
lypinator	0:bb348c97df44	871	#define LL_RCC_PLLM_DIV_60 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2) /!< PLL, PLLI2S and PLLSAI division factor by 60 /
lypinator	0:bb348c97df44	872	#define LL_RCC_PLLM_DIV_61 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 61 /
lypinator	0:bb348c97df44	873	#define LL_RCC_PLLM_DIV_62 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1) /!< PLL, PLLI2S and PLLSAI division factor by 62 /
lypinator	0:bb348c97df44	874	#define LL_RCC_PLLM_DIV_63 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 63 /
lypinator	0:bb348c97df44	875	/**
lypinator	0:bb348c97df44	876	* @}
lypinator	0:bb348c97df44	877	*/
lypinator	0:bb348c97df44	878
lypinator	0:bb348c97df44	879	#if defined(RCC_PLLCFGR_PLLR)
lypinator	0:bb348c97df44	880	/** @defgroup RCC_LL_EC_PLLR_DIV PLL division factor (PLLR)
lypinator	0:bb348c97df44	881	* @{
lypinator	0:bb348c97df44	882	*/
lypinator	0:bb348c97df44	883	#define LL_RCC_PLLR_DIV_2 (RCC_PLLCFGR_PLLR_1) /!< Main PLL division factor for PLLCLK (system clock) by 2 /
lypinator	0:bb348c97df44	884	#define LL_RCC_PLLR_DIV_3 (RCC_PLLCFGR_PLLR_1\|RCC_PLLCFGR_PLLR_0) /!< Main PLL division factor for PLLCLK (system clock) by 3 /
lypinator	0:bb348c97df44	885	#define LL_RCC_PLLR_DIV_4 (RCC_PLLCFGR_PLLR_2) /!< Main PLL division factor for PLLCLK (system clock) by 4 /
lypinator	0:bb348c97df44	886	#define LL_RCC_PLLR_DIV_5 (RCC_PLLCFGR_PLLR_2\|RCC_PLLCFGR_PLLR_0) /!< Main PLL division factor for PLLCLK (system clock) by 5 /
lypinator	0:bb348c97df44	887	#define LL_RCC_PLLR_DIV_6 (RCC_PLLCFGR_PLLR_2\|RCC_PLLCFGR_PLLR_1) /!< Main PLL division factor for PLLCLK (system clock) by 6 /
lypinator	0:bb348c97df44	888	#define LL_RCC_PLLR_DIV_7 (RCC_PLLCFGR_PLLR) /!< Main PLL division factor for PLLCLK (system clock) by 7 /
lypinator	0:bb348c97df44	889	/**
lypinator	0:bb348c97df44	890	* @}
lypinator	0:bb348c97df44	891	*/
lypinator	0:bb348c97df44	892	#endif /* RCC_PLLCFGR_PLLR */
lypinator	0:bb348c97df44	893
lypinator	0:bb348c97df44	894	#if defined(RCC_DCKCFGR_PLLDIVR)
lypinator	0:bb348c97df44	895	/** @defgroup RCC_LL_EC_PLLDIVR PLLDIVR division factor (PLLDIVR)
lypinator	0:bb348c97df44	896	* @{
lypinator	0:bb348c97df44	897	*/
lypinator	0:bb348c97df44	898	#define LL_RCC_PLLDIVR_DIV_1 (RCC_DCKCFGR_PLLDIVR_0) /!< PLL division factor for PLLDIVR output by 1 /
lypinator	0:bb348c97df44	899	#define LL_RCC_PLLDIVR_DIV_2 (RCC_DCKCFGR_PLLDIVR_1) /!< PLL division factor for PLLDIVR output by 2 /
lypinator	0:bb348c97df44	900	#define LL_RCC_PLLDIVR_DIV_3 (RCC_DCKCFGR_PLLDIVR_1 \| RCC_DCKCFGR_PLLDIVR_0) /!< PLL division factor for PLLDIVR output by 3 /
lypinator	0:bb348c97df44	901	#define LL_RCC_PLLDIVR_DIV_4 (RCC_DCKCFGR_PLLDIVR_2) /!< PLL division factor for PLLDIVR output by 4 /
lypinator	0:bb348c97df44	902	#define LL_RCC_PLLDIVR_DIV_5 (RCC_DCKCFGR_PLLDIVR_2 \| RCC_DCKCFGR_PLLDIVR_0) /!< PLL division factor for PLLDIVR output by 5 /
lypinator	0:bb348c97df44	903	#define LL_RCC_PLLDIVR_DIV_6 (RCC_DCKCFGR_PLLDIVR_2 \| RCC_DCKCFGR_PLLDIVR_1) /!< PLL division factor for PLLDIVR output by 6 /
lypinator	0:bb348c97df44	904	#define LL_RCC_PLLDIVR_DIV_7 (RCC_DCKCFGR_PLLDIVR_2 \| RCC_DCKCFGR_PLLDIVR_1 \| RCC_DCKCFGR_PLLDIVR_0) /!< PLL division factor for PLLDIVR output by 7 /
lypinator	0:bb348c97df44	905	#define LL_RCC_PLLDIVR_DIV_8 (RCC_DCKCFGR_PLLDIVR_3) /!< PLL division factor for PLLDIVR output by 8 /
lypinator	0:bb348c97df44	906	#define LL_RCC_PLLDIVR_DIV_9 (RCC_DCKCFGR_PLLDIVR_3 \| RCC_DCKCFGR_PLLDIVR_0) /!< PLL division factor for PLLDIVR output by 9 /
lypinator	0:bb348c97df44	907	#define LL_RCC_PLLDIVR_DIV_10 (RCC_DCKCFGR_PLLDIVR_3 \| RCC_DCKCFGR_PLLDIVR_1) /!< PLL division factor for PLLDIVR output by 10 /
lypinator	0:bb348c97df44	908	#define LL_RCC_PLLDIVR_DIV_11 (RCC_DCKCFGR_PLLDIVR_3 \| RCC_DCKCFGR_PLLDIVR_1 \| RCC_DCKCFGR_PLLDIVR_0) /!< PLL division factor for PLLDIVR output by 11 /
lypinator	0:bb348c97df44	909	#define LL_RCC_PLLDIVR_DIV_12 (RCC_DCKCFGR_PLLDIVR_3 \| RCC_DCKCFGR_PLLDIVR_2) /!< PLL division factor for PLLDIVR output by 12 /
lypinator	0:bb348c97df44	910	#define LL_RCC_PLLDIVR_DIV_13 (RCC_DCKCFGR_PLLDIVR_3 \| RCC_DCKCFGR_PLLDIVR_2 \| RCC_DCKCFGR_PLLDIVR_0) /!< PLL division factor for PLLDIVR output by 13 /
lypinator	0:bb348c97df44	911	#define LL_RCC_PLLDIVR_DIV_14 (RCC_DCKCFGR_PLLDIVR_3 \| RCC_DCKCFGR_PLLDIVR_2 \| RCC_DCKCFGR_PLLDIVR_1) /!< PLL division factor for PLLDIVR output by 14 /
lypinator	0:bb348c97df44	912	#define LL_RCC_PLLDIVR_DIV_15 (RCC_DCKCFGR_PLLDIVR_3 \| RCC_DCKCFGR_PLLDIVR_2 \| RCC_DCKCFGR_PLLDIVR_1 \| RCC_DCKCFGR_PLLDIVR_0) /!< PLL division factor for PLLDIVR output by 15 /
lypinator	0:bb348c97df44	913	#define LL_RCC_PLLDIVR_DIV_16 (RCC_DCKCFGR_PLLDIVR_4) /!< PLL division factor for PLLDIVR output by 16 /
lypinator	0:bb348c97df44	914	#define LL_RCC_PLLDIVR_DIV_17 (RCC_DCKCFGR_PLLDIVR_4 \| RCC_DCKCFGR_PLLDIVR_0) /!< PLL division factor for PLLDIVR output by 17 /
lypinator	0:bb348c97df44	915	#define LL_RCC_PLLDIVR_DIV_18 (RCC_DCKCFGR_PLLDIVR_4 \| RCC_DCKCFGR_PLLDIVR_1) /!< PLL division factor for PLLDIVR output by 18 /
lypinator	0:bb348c97df44	916	#define LL_RCC_PLLDIVR_DIV_19 (RCC_DCKCFGR_PLLDIVR_4 \| RCC_DCKCFGR_PLLDIVR_1 \| RCC_DCKCFGR_PLLDIVR_0) /!< PLL division factor for PLLDIVR output by 19 /
lypinator	0:bb348c97df44	917	#define LL_RCC_PLLDIVR_DIV_20 (RCC_DCKCFGR_PLLDIVR_4 \| RCC_DCKCFGR_PLLDIVR_2) /!< PLL division factor for PLLDIVR output by 20 /
lypinator	0:bb348c97df44	918	#define LL_RCC_PLLDIVR_DIV_21 (RCC_DCKCFGR_PLLDIVR_4 \| RCC_DCKCFGR_PLLDIVR_2 \| RCC_DCKCFGR_PLLDIVR_0) /!< PLL division factor for PLLDIVR output by 21 /
lypinator	0:bb348c97df44	919	#define LL_RCC_PLLDIVR_DIV_22 (RCC_DCKCFGR_PLLDIVR_4 \| RCC_DCKCFGR_PLLDIVR_2 \| RCC_DCKCFGR_PLLDIVR_1) /!< PLL division factor for PLLDIVR output by 22 /
lypinator	0:bb348c97df44	920	#define LL_RCC_PLLDIVR_DIV_23 (RCC_DCKCFGR_PLLDIVR_4 \| RCC_DCKCFGR_PLLDIVR_2 \| RCC_DCKCFGR_PLLDIVR_1 \| RCC_DCKCFGR_PLLDIVR_0) /!< PLL division factor for PLLDIVR output by 23 /
lypinator	0:bb348c97df44	921	#define LL_RCC_PLLDIVR_DIV_24 (RCC_DCKCFGR_PLLDIVR_4 \| RCC_DCKCFGR_PLLDIVR_3) /!< PLL division factor for PLLDIVR output by 24 /
lypinator	0:bb348c97df44	922	#define LL_RCC_PLLDIVR_DIV_25 (RCC_DCKCFGR_PLLDIVR_4 \| RCC_DCKCFGR_PLLDIVR_3 \| RCC_DCKCFGR_PLLDIVR_0) /!< PLL division factor for PLLDIVR output by 25 /
lypinator	0:bb348c97df44	923	#define LL_RCC_PLLDIVR_DIV_26 (RCC_DCKCFGR_PLLDIVR_4 \| RCC_DCKCFGR_PLLDIVR_3 \| RCC_DCKCFGR_PLLDIVR_1) /!< PLL division factor for PLLDIVR output by 26 /
lypinator	0:bb348c97df44	924	#define LL_RCC_PLLDIVR_DIV_27 (RCC_DCKCFGR_PLLDIVR_4 \| RCC_DCKCFGR_PLLDIVR_3 \| RCC_DCKCFGR_PLLDIVR_1 \| RCC_DCKCFGR_PLLDIVR_0) /!< PLL division factor for PLLDIVR output by 27 /
lypinator	0:bb348c97df44	925	#define LL_RCC_PLLDIVR_DIV_28 (RCC_DCKCFGR_PLLDIVR_4 \| RCC_DCKCFGR_PLLDIVR_3 \| RCC_DCKCFGR_PLLDIVR_2) /!< PLL division factor for PLLDIVR output by 28 /
lypinator	0:bb348c97df44	926	#define LL_RCC_PLLDIVR_DIV_29 (RCC_DCKCFGR_PLLDIVR_4 \| RCC_DCKCFGR_PLLDIVR_3 \| RCC_DCKCFGR_PLLDIVR_2 \| RCC_DCKCFGR_PLLDIVR_0) /!< PLL division factor for PLLDIVR output by 29 /
lypinator	0:bb348c97df44	927	#define LL_RCC_PLLDIVR_DIV_30 (RCC_DCKCFGR_PLLDIVR_4 \| RCC_DCKCFGR_PLLDIVR_3 \| RCC_DCKCFGR_PLLDIVR_2 \| RCC_DCKCFGR_PLLDIVR_1) /!< PLL division factor for PLLDIVR output by 30 /
lypinator	0:bb348c97df44	928	#define LL_RCC_PLLDIVR_DIV_31 (RCC_DCKCFGR_PLLDIVR_4 \| RCC_DCKCFGR_PLLDIVR_3 \| RCC_DCKCFGR_PLLDIVR_2 \| RCC_DCKCFGR_PLLDIVR_1 \| RCC_DCKCFGR_PLLDIVR_0) /!< PLL division factor for PLLDIVR output by 31 /
lypinator	0:bb348c97df44	929	/**
lypinator	0:bb348c97df44	930	* @}
lypinator	0:bb348c97df44	931	*/
lypinator	0:bb348c97df44	932	#endif /* RCC_DCKCFGR_PLLDIVR */
lypinator	0:bb348c97df44	933
lypinator	0:bb348c97df44	934	/** @defgroup RCC_LL_EC_PLLP_DIV PLL division factor (PLLP)
lypinator	0:bb348c97df44	935	* @{
lypinator	0:bb348c97df44	936	*/
lypinator	0:bb348c97df44	937	#define LL_RCC_PLLP_DIV_2 0x00000000U /!< Main PLL division factor for PLLP output by 2 /
lypinator	0:bb348c97df44	938	#define LL_RCC_PLLP_DIV_4 RCC_PLLCFGR_PLLP_0 /!< Main PLL division factor for PLLP output by 4 /
lypinator	0:bb348c97df44	939	#define LL_RCC_PLLP_DIV_6 RCC_PLLCFGR_PLLP_1 /!< Main PLL division factor for PLLP output by 6 /
lypinator	0:bb348c97df44	940	#define LL_RCC_PLLP_DIV_8 (RCC_PLLCFGR_PLLP_1 \| RCC_PLLCFGR_PLLP_0) /!< Main PLL division factor for PLLP output by 8 /
lypinator	0:bb348c97df44	941	/**
lypinator	0:bb348c97df44	942	* @}
lypinator	0:bb348c97df44	943	*/
lypinator	0:bb348c97df44	944
lypinator	0:bb348c97df44	945	/** @defgroup RCC_LL_EC_PLLQ_DIV PLL division factor (PLLQ)
lypinator	0:bb348c97df44	946	* @{
lypinator	0:bb348c97df44	947	*/
lypinator	0:bb348c97df44	948	#define LL_RCC_PLLQ_DIV_2 RCC_PLLCFGR_PLLQ_1 /!< Main PLL division factor for PLLQ output by 2 /
lypinator	0:bb348c97df44	949	#define LL_RCC_PLLQ_DIV_3 (RCC_PLLCFGR_PLLQ_1\|RCC_PLLCFGR_PLLQ_0) /!< Main PLL division factor for PLLQ output by 3 /
lypinator	0:bb348c97df44	950	#define LL_RCC_PLLQ_DIV_4 RCC_PLLCFGR_PLLQ_2 /!< Main PLL division factor for PLLQ output by 4 /
lypinator	0:bb348c97df44	951	#define LL_RCC_PLLQ_DIV_5 (RCC_PLLCFGR_PLLQ_2\|RCC_PLLCFGR_PLLQ_0) /!< Main PLL division factor for PLLQ output by 5 /
lypinator	0:bb348c97df44	952	#define LL_RCC_PLLQ_DIV_6 (RCC_PLLCFGR_PLLQ_2\|RCC_PLLCFGR_PLLQ_1) /!< Main PLL division factor for PLLQ output by 6 /
lypinator	0:bb348c97df44	953	#define LL_RCC_PLLQ_DIV_7 (RCC_PLLCFGR_PLLQ_2\|RCC_PLLCFGR_PLLQ_1\|RCC_PLLCFGR_PLLQ_0) /!< Main PLL division factor for PLLQ output by 7 /
lypinator	0:bb348c97df44	954	#define LL_RCC_PLLQ_DIV_8 RCC_PLLCFGR_PLLQ_3 /!< Main PLL division factor for PLLQ output by 8 /
lypinator	0:bb348c97df44	955	#define LL_RCC_PLLQ_DIV_9 (RCC_PLLCFGR_PLLQ_3\|RCC_PLLCFGR_PLLQ_0) /!< Main PLL division factor for PLLQ output by 9 /
lypinator	0:bb348c97df44	956	#define LL_RCC_PLLQ_DIV_10 (RCC_PLLCFGR_PLLQ_3\|RCC_PLLCFGR_PLLQ_1) /!< Main PLL division factor for PLLQ output by 10 /
lypinator	0:bb348c97df44	957	#define LL_RCC_PLLQ_DIV_11 (RCC_PLLCFGR_PLLQ_3\|RCC_PLLCFGR_PLLQ_1\|RCC_PLLCFGR_PLLQ_0) /!< Main PLL division factor for PLLQ output by 11 /
lypinator	0:bb348c97df44	958	#define LL_RCC_PLLQ_DIV_12 (RCC_PLLCFGR_PLLQ_3\|RCC_PLLCFGR_PLLQ_2) /!< Main PLL division factor for PLLQ output by 12 /
lypinator	0:bb348c97df44	959	#define LL_RCC_PLLQ_DIV_13 (RCC_PLLCFGR_PLLQ_3\|RCC_PLLCFGR_PLLQ_2\|RCC_PLLCFGR_PLLQ_0) /!< Main PLL division factor for PLLQ output by 13 /
lypinator	0:bb348c97df44	960	#define LL_RCC_PLLQ_DIV_14 (RCC_PLLCFGR_PLLQ_3\|RCC_PLLCFGR_PLLQ_2\|RCC_PLLCFGR_PLLQ_1) /!< Main PLL division factor for PLLQ output by 14 /
lypinator	0:bb348c97df44	961	#define LL_RCC_PLLQ_DIV_15 (RCC_PLLCFGR_PLLQ_3\|RCC_PLLCFGR_PLLQ_2\|RCC_PLLCFGR_PLLQ_1\|RCC_PLLCFGR_PLLQ_0) /!< Main PLL division factor for PLLQ output by 15 /
lypinator	0:bb348c97df44	962	/**
lypinator	0:bb348c97df44	963	* @}
lypinator	0:bb348c97df44	964	*/
lypinator	0:bb348c97df44	965
lypinator	0:bb348c97df44	966	/** @defgroup RCC_LL_EC_PLL_SPRE_SEL PLL Spread Spectrum Selection
lypinator	0:bb348c97df44	967	* @{
lypinator	0:bb348c97df44	968	*/
lypinator	0:bb348c97df44	969	#define LL_RCC_SPREAD_SELECT_CENTER 0x00000000U /!< PLL center spread spectrum selection /
lypinator	0:bb348c97df44	970	#define LL_RCC_SPREAD_SELECT_DOWN RCC_SSCGR_SPREADSEL /!< PLL down spread spectrum selection /
lypinator	0:bb348c97df44	971	/**
lypinator	0:bb348c97df44	972	* @}
lypinator	0:bb348c97df44	973	*/
lypinator	0:bb348c97df44	974
lypinator	0:bb348c97df44	975	#if defined(RCC_PLLI2S_SUPPORT)
lypinator	0:bb348c97df44	976	/** @defgroup RCC_LL_EC_PLLI2SM PLLI2SM division factor (PLLI2SM)
lypinator	0:bb348c97df44	977	* @{
lypinator	0:bb348c97df44	978	*/
lypinator	0:bb348c97df44	979	#if defined(RCC_PLLI2SCFGR_PLLI2SM)
lypinator	0:bb348c97df44	980	#define LL_RCC_PLLI2SM_DIV_2 (RCC_PLLI2SCFGR_PLLI2SM_1) /!< PLLI2S division factor for PLLI2SM output by 2 /
lypinator	0:bb348c97df44	981	#define LL_RCC_PLLI2SM_DIV_3 (RCC_PLLI2SCFGR_PLLI2SM_1 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 3 /
lypinator	0:bb348c97df44	982	#define LL_RCC_PLLI2SM_DIV_4 (RCC_PLLI2SCFGR_PLLI2SM_2) /!< PLLI2S division factor for PLLI2SM output by 4 /
lypinator	0:bb348c97df44	983	#define LL_RCC_PLLI2SM_DIV_5 (RCC_PLLI2SCFGR_PLLI2SM_2 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 5 /
lypinator	0:bb348c97df44	984	#define LL_RCC_PLLI2SM_DIV_6 (RCC_PLLI2SCFGR_PLLI2SM_2 \| RCC_PLLI2SCFGR_PLLI2SM_1) /!< PLLI2S division factor for PLLI2SM output by 6 /
lypinator	0:bb348c97df44	985	#define LL_RCC_PLLI2SM_DIV_7 (RCC_PLLI2SCFGR_PLLI2SM_2 \| RCC_PLLI2SCFGR_PLLI2SM_1 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 7 /
lypinator	0:bb348c97df44	986	#define LL_RCC_PLLI2SM_DIV_8 (RCC_PLLI2SCFGR_PLLI2SM_3) /!< PLLI2S division factor for PLLI2SM output by 8 /
lypinator	0:bb348c97df44	987	#define LL_RCC_PLLI2SM_DIV_9 (RCC_PLLI2SCFGR_PLLI2SM_3 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 9 /
lypinator	0:bb348c97df44	988	#define LL_RCC_PLLI2SM_DIV_10 (RCC_PLLI2SCFGR_PLLI2SM_3 \| RCC_PLLI2SCFGR_PLLI2SM_1) /!< PLLI2S division factor for PLLI2SM output by 10 /
lypinator	0:bb348c97df44	989	#define LL_RCC_PLLI2SM_DIV_11 (RCC_PLLI2SCFGR_PLLI2SM_3 \| RCC_PLLI2SCFGR_PLLI2SM_1 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 11 /
lypinator	0:bb348c97df44	990	#define LL_RCC_PLLI2SM_DIV_12 (RCC_PLLI2SCFGR_PLLI2SM_3 \| RCC_PLLI2SCFGR_PLLI2SM_2) /!< PLLI2S division factor for PLLI2SM output by 12 /
lypinator	0:bb348c97df44	991	#define LL_RCC_PLLI2SM_DIV_13 (RCC_PLLI2SCFGR_PLLI2SM_3 \| RCC_PLLI2SCFGR_PLLI2SM_2 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 13 /
lypinator	0:bb348c97df44	992	#define LL_RCC_PLLI2SM_DIV_14 (RCC_PLLI2SCFGR_PLLI2SM_3 \| RCC_PLLI2SCFGR_PLLI2SM_2 \| RCC_PLLI2SCFGR_PLLI2SM_1) /!< PLLI2S division factor for PLLI2SM output by 14 /
lypinator	0:bb348c97df44	993	#define LL_RCC_PLLI2SM_DIV_15 (RCC_PLLI2SCFGR_PLLI2SM_3 \| RCC_PLLI2SCFGR_PLLI2SM_2 \| RCC_PLLI2SCFGR_PLLI2SM_1 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 15 /
lypinator	0:bb348c97df44	994	#define LL_RCC_PLLI2SM_DIV_16 (RCC_PLLI2SCFGR_PLLI2SM_4) /!< PLLI2S division factor for PLLI2SM output by 16 /
lypinator	0:bb348c97df44	995	#define LL_RCC_PLLI2SM_DIV_17 (RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 17 /
lypinator	0:bb348c97df44	996	#define LL_RCC_PLLI2SM_DIV_18 (RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_1) /!< PLLI2S division factor for PLLI2SM output by 18 /
lypinator	0:bb348c97df44	997	#define LL_RCC_PLLI2SM_DIV_19 (RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_1 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 19 /
lypinator	0:bb348c97df44	998	#define LL_RCC_PLLI2SM_DIV_20 (RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_2) /!< PLLI2S division factor for PLLI2SM output by 20 /
lypinator	0:bb348c97df44	999	#define LL_RCC_PLLI2SM_DIV_21 (RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_2 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 21 /
lypinator	0:bb348c97df44	1000	#define LL_RCC_PLLI2SM_DIV_22 (RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_2 \| RCC_PLLI2SCFGR_PLLI2SM_1) /!< PLLI2S division factor for PLLI2SM output by 22 /
lypinator	0:bb348c97df44	1001	#define LL_RCC_PLLI2SM_DIV_23 (RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_2 \| RCC_PLLI2SCFGR_PLLI2SM_1 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 23 /
lypinator	0:bb348c97df44	1002	#define LL_RCC_PLLI2SM_DIV_24 (RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_3) /!< PLLI2S division factor for PLLI2SM output by 24 /
lypinator	0:bb348c97df44	1003	#define LL_RCC_PLLI2SM_DIV_25 (RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_3 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 25 /
lypinator	0:bb348c97df44	1004	#define LL_RCC_PLLI2SM_DIV_26 (RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_3 \| RCC_PLLI2SCFGR_PLLI2SM_1) /!< PLLI2S division factor for PLLI2SM output by 26 /
lypinator	0:bb348c97df44	1005	#define LL_RCC_PLLI2SM_DIV_27 (RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_3 \| RCC_PLLI2SCFGR_PLLI2SM_1 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 27 /
lypinator	0:bb348c97df44	1006	#define LL_RCC_PLLI2SM_DIV_28 (RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_3 \| RCC_PLLI2SCFGR_PLLI2SM_2) /!< PLLI2S division factor for PLLI2SM output by 28 /
lypinator	0:bb348c97df44	1007	#define LL_RCC_PLLI2SM_DIV_29 (RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_3 \| RCC_PLLI2SCFGR_PLLI2SM_2 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 29 /
lypinator	0:bb348c97df44	1008	#define LL_RCC_PLLI2SM_DIV_30 (RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_3 \| RCC_PLLI2SCFGR_PLLI2SM_2 \| RCC_PLLI2SCFGR_PLLI2SM_1) /!< PLLI2S division factor for PLLI2SM output by 30 /
lypinator	0:bb348c97df44	1009	#define LL_RCC_PLLI2SM_DIV_31 (RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_3 \| RCC_PLLI2SCFGR_PLLI2SM_2 \| RCC_PLLI2SCFGR_PLLI2SM_1 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 31 /
lypinator	0:bb348c97df44	1010	#define LL_RCC_PLLI2SM_DIV_32 (RCC_PLLI2SCFGR_PLLI2SM_5) /!< PLLI2S division factor for PLLI2SM output by 32 /
lypinator	0:bb348c97df44	1011	#define LL_RCC_PLLI2SM_DIV_33 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 33 /
lypinator	0:bb348c97df44	1012	#define LL_RCC_PLLI2SM_DIV_34 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_1) /!< PLLI2S division factor for PLLI2SM output by 34 /
lypinator	0:bb348c97df44	1013	#define LL_RCC_PLLI2SM_DIV_35 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_1 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 35 /
lypinator	0:bb348c97df44	1014	#define LL_RCC_PLLI2SM_DIV_36 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_2) /!< PLLI2S division factor for PLLI2SM output by 36 /
lypinator	0:bb348c97df44	1015	#define LL_RCC_PLLI2SM_DIV_37 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_2 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 37 /
lypinator	0:bb348c97df44	1016	#define LL_RCC_PLLI2SM_DIV_38 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_2 \| RCC_PLLI2SCFGR_PLLI2SM_1) /!< PLLI2S division factor for PLLI2SM output by 38 /
lypinator	0:bb348c97df44	1017	#define LL_RCC_PLLI2SM_DIV_39 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_2 \| RCC_PLLI2SCFGR_PLLI2SM_1 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 39 /
lypinator	0:bb348c97df44	1018	#define LL_RCC_PLLI2SM_DIV_40 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_3) /!< PLLI2S division factor for PLLI2SM output by 40 /
lypinator	0:bb348c97df44	1019	#define LL_RCC_PLLI2SM_DIV_41 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_3 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 41 /
lypinator	0:bb348c97df44	1020	#define LL_RCC_PLLI2SM_DIV_42 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_3 \| RCC_PLLI2SCFGR_PLLI2SM_1) /!< PLLI2S division factor for PLLI2SM output by 42 /
lypinator	0:bb348c97df44	1021	#define LL_RCC_PLLI2SM_DIV_43 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_3 \| RCC_PLLI2SCFGR_PLLI2SM_1 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 43 /
lypinator	0:bb348c97df44	1022	#define LL_RCC_PLLI2SM_DIV_44 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_3 \| RCC_PLLI2SCFGR_PLLI2SM_2) /!< PLLI2S division factor for PLLI2SM output by 44 /
lypinator	0:bb348c97df44	1023	#define LL_RCC_PLLI2SM_DIV_45 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_3 \| RCC_PLLI2SCFGR_PLLI2SM_2 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 45 /
lypinator	0:bb348c97df44	1024	#define LL_RCC_PLLI2SM_DIV_46 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_3 \| RCC_PLLI2SCFGR_PLLI2SM_2 \| RCC_PLLI2SCFGR_PLLI2SM_1) /!< PLLI2S division factor for PLLI2SM output by 46 /
lypinator	0:bb348c97df44	1025	#define LL_RCC_PLLI2SM_DIV_47 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_3 \| RCC_PLLI2SCFGR_PLLI2SM_2 \| RCC_PLLI2SCFGR_PLLI2SM_1 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 47 /
lypinator	0:bb348c97df44	1026	#define LL_RCC_PLLI2SM_DIV_48 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_4) /!< PLLI2S division factor for PLLI2SM output by 48 /
lypinator	0:bb348c97df44	1027	#define LL_RCC_PLLI2SM_DIV_49 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 49 /
lypinator	0:bb348c97df44	1028	#define LL_RCC_PLLI2SM_DIV_50 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_1) /!< PLLI2S division factor for PLLI2SM output by 50 /
lypinator	0:bb348c97df44	1029	#define LL_RCC_PLLI2SM_DIV_51 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_1 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 51 /
lypinator	0:bb348c97df44	1030	#define LL_RCC_PLLI2SM_DIV_52 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_2) /!< PLLI2S division factor for PLLI2SM output by 52 /
lypinator	0:bb348c97df44	1031	#define LL_RCC_PLLI2SM_DIV_53 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_2 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 53 /
lypinator	0:bb348c97df44	1032	#define LL_RCC_PLLI2SM_DIV_54 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_2 \| RCC_PLLI2SCFGR_PLLI2SM_1) /!< PLLI2S division factor for PLLI2SM output by 54 /
lypinator	0:bb348c97df44	1033	#define LL_RCC_PLLI2SM_DIV_55 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_2 \| RCC_PLLI2SCFGR_PLLI2SM_1 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 55 /
lypinator	0:bb348c97df44	1034	#define LL_RCC_PLLI2SM_DIV_56 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_3) /!< PLLI2S division factor for PLLI2SM output by 56 /
lypinator	0:bb348c97df44	1035	#define LL_RCC_PLLI2SM_DIV_57 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_3 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 57 /
lypinator	0:bb348c97df44	1036	#define LL_RCC_PLLI2SM_DIV_58 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_3 \| RCC_PLLI2SCFGR_PLLI2SM_1) /!< PLLI2S division factor for PLLI2SM output by 58 /
lypinator	0:bb348c97df44	1037	#define LL_RCC_PLLI2SM_DIV_59 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_3 \| RCC_PLLI2SCFGR_PLLI2SM_1 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 59 /
lypinator	0:bb348c97df44	1038	#define LL_RCC_PLLI2SM_DIV_60 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_3 \| RCC_PLLI2SCFGR_PLLI2SM_2) /!< PLLI2S division factor for PLLI2SM output by 60 /
lypinator	0:bb348c97df44	1039	#define LL_RCC_PLLI2SM_DIV_61 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_3 \| RCC_PLLI2SCFGR_PLLI2SM_2 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 61 /
lypinator	0:bb348c97df44	1040	#define LL_RCC_PLLI2SM_DIV_62 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_3 \| RCC_PLLI2SCFGR_PLLI2SM_2 \| RCC_PLLI2SCFGR_PLLI2SM_1) /!< PLLI2S division factor for PLLI2SM output by 62 /
lypinator	0:bb348c97df44	1041	#define LL_RCC_PLLI2SM_DIV_63 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_3 \| RCC_PLLI2SCFGR_PLLI2SM_2 \| RCC_PLLI2SCFGR_PLLI2SM_1 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 63 /
lypinator	0:bb348c97df44	1042	#else
lypinator	0:bb348c97df44	1043	#define LL_RCC_PLLI2SM_DIV_2 LL_RCC_PLLM_DIV_2 /!< PLLI2S division factor for PLLI2SM output by 2 /
lypinator	0:bb348c97df44	1044	#define LL_RCC_PLLI2SM_DIV_3 LL_RCC_PLLM_DIV_3 /!< PLLI2S division factor for PLLI2SM output by 3 /
lypinator	0:bb348c97df44	1045	#define LL_RCC_PLLI2SM_DIV_4 LL_RCC_PLLM_DIV_4 /!< PLLI2S division factor for PLLI2SM output by 4 /
lypinator	0:bb348c97df44	1046	#define LL_RCC_PLLI2SM_DIV_5 LL_RCC_PLLM_DIV_5 /!< PLLI2S division factor for PLLI2SM output by 5 /
lypinator	0:bb348c97df44	1047	#define LL_RCC_PLLI2SM_DIV_6 LL_RCC_PLLM_DIV_6 /!< PLLI2S division factor for PLLI2SM output by 6 /
lypinator	0:bb348c97df44	1048	#define LL_RCC_PLLI2SM_DIV_7 LL_RCC_PLLM_DIV_7 /!< PLLI2S division factor for PLLI2SM output by 7 /
lypinator	0:bb348c97df44	1049	#define LL_RCC_PLLI2SM_DIV_8 LL_RCC_PLLM_DIV_8 /!< PLLI2S division factor for PLLI2SM output by 8 /
lypinator	0:bb348c97df44	1050	#define LL_RCC_PLLI2SM_DIV_9 LL_RCC_PLLM_DIV_9 /!< PLLI2S division factor for PLLI2SM output by 9 /
lypinator	0:bb348c97df44	1051	#define LL_RCC_PLLI2SM_DIV_10 LL_RCC_PLLM_DIV_10 /!< PLLI2S division factor for PLLI2SM output by 10 /
lypinator	0:bb348c97df44	1052	#define LL_RCC_PLLI2SM_DIV_11 LL_RCC_PLLM_DIV_11 /!< PLLI2S division factor for PLLI2SM output by 11 /
lypinator	0:bb348c97df44	1053	#define LL_RCC_PLLI2SM_DIV_12 LL_RCC_PLLM_DIV_12 /!< PLLI2S division factor for PLLI2SM output by 12 /
lypinator	0:bb348c97df44	1054	#define LL_RCC_PLLI2SM_DIV_13 LL_RCC_PLLM_DIV_13 /!< PLLI2S division factor for PLLI2SM output by 13 /
lypinator	0:bb348c97df44	1055	#define LL_RCC_PLLI2SM_DIV_14 LL_RCC_PLLM_DIV_14 /!< PLLI2S division factor for PLLI2SM output by 14 /
lypinator	0:bb348c97df44	1056	#define LL_RCC_PLLI2SM_DIV_15 LL_RCC_PLLM_DIV_15 /!< PLLI2S division factor for PLLI2SM output by 15 /
lypinator	0:bb348c97df44	1057	#define LL_RCC_PLLI2SM_DIV_16 LL_RCC_PLLM_DIV_16 /!< PLLI2S division factor for PLLI2SM output by 16 /
lypinator	0:bb348c97df44	1058	#define LL_RCC_PLLI2SM_DIV_17 LL_RCC_PLLM_DIV_17 /!< PLLI2S division factor for PLLI2SM output by 17 /
lypinator	0:bb348c97df44	1059	#define LL_RCC_PLLI2SM_DIV_18 LL_RCC_PLLM_DIV_18 /!< PLLI2S division factor for PLLI2SM output by 18 /
lypinator	0:bb348c97df44	1060	#define LL_RCC_PLLI2SM_DIV_19 LL_RCC_PLLM_DIV_19 /!< PLLI2S division factor for PLLI2SM output by 19 /
lypinator	0:bb348c97df44	1061	#define LL_RCC_PLLI2SM_DIV_20 LL_RCC_PLLM_DIV_20 /!< PLLI2S division factor for PLLI2SM output by 20 /
lypinator	0:bb348c97df44	1062	#define LL_RCC_PLLI2SM_DIV_21 LL_RCC_PLLM_DIV_21 /!< PLLI2S division factor for PLLI2SM output by 21 /
lypinator	0:bb348c97df44	1063	#define LL_RCC_PLLI2SM_DIV_22 LL_RCC_PLLM_DIV_22 /!< PLLI2S division factor for PLLI2SM output by 22 /
lypinator	0:bb348c97df44	1064	#define LL_RCC_PLLI2SM_DIV_23 LL_RCC_PLLM_DIV_23 /!< PLLI2S division factor for PLLI2SM output by 23 /
lypinator	0:bb348c97df44	1065	#define LL_RCC_PLLI2SM_DIV_24 LL_RCC_PLLM_DIV_24 /!< PLLI2S division factor for PLLI2SM output by 24 /
lypinator	0:bb348c97df44	1066	#define LL_RCC_PLLI2SM_DIV_25 LL_RCC_PLLM_DIV_25 /!< PLLI2S division factor for PLLI2SM output by 25 /
lypinator	0:bb348c97df44	1067	#define LL_RCC_PLLI2SM_DIV_26 LL_RCC_PLLM_DIV_26 /!< PLLI2S division factor for PLLI2SM output by 26 /
lypinator	0:bb348c97df44	1068	#define LL_RCC_PLLI2SM_DIV_27 LL_RCC_PLLM_DIV_27 /!< PLLI2S division factor for PLLI2SM output by 27 /
lypinator	0:bb348c97df44	1069	#define LL_RCC_PLLI2SM_DIV_28 LL_RCC_PLLM_DIV_28 /!< PLLI2S division factor for PLLI2SM output by 28 /
lypinator	0:bb348c97df44	1070	#define LL_RCC_PLLI2SM_DIV_29 LL_RCC_PLLM_DIV_29 /!< PLLI2S division factor for PLLI2SM output by 29 /
lypinator	0:bb348c97df44	1071	#define LL_RCC_PLLI2SM_DIV_30 LL_RCC_PLLM_DIV_30 /!< PLLI2S division factor for PLLI2SM output by 30 /
lypinator	0:bb348c97df44	1072	#define LL_RCC_PLLI2SM_DIV_31 LL_RCC_PLLM_DIV_31 /!< PLLI2S division factor for PLLI2SM output by 31 /
lypinator	0:bb348c97df44	1073	#define LL_RCC_PLLI2SM_DIV_32 LL_RCC_PLLM_DIV_32 /!< PLLI2S division factor for PLLI2SM output by 32 /
lypinator	0:bb348c97df44	1074	#define LL_RCC_PLLI2SM_DIV_33 LL_RCC_PLLM_DIV_33 /!< PLLI2S division factor for PLLI2SM output by 33 /
lypinator	0:bb348c97df44	1075	#define LL_RCC_PLLI2SM_DIV_34 LL_RCC_PLLM_DIV_34 /!< PLLI2S division factor for PLLI2SM output by 34 /
lypinator	0:bb348c97df44	1076	#define LL_RCC_PLLI2SM_DIV_35 LL_RCC_PLLM_DIV_35 /!< PLLI2S division factor for PLLI2SM output by 35 /
lypinator	0:bb348c97df44	1077	#define LL_RCC_PLLI2SM_DIV_36 LL_RCC_PLLM_DIV_36 /!< PLLI2S division factor for PLLI2SM output by 36 /
lypinator	0:bb348c97df44	1078	#define LL_RCC_PLLI2SM_DIV_37 LL_RCC_PLLM_DIV_37 /!< PLLI2S division factor for PLLI2SM output by 37 /
lypinator	0:bb348c97df44	1079	#define LL_RCC_PLLI2SM_DIV_38 LL_RCC_PLLM_DIV_38 /!< PLLI2S division factor for PLLI2SM output by 38 /
lypinator	0:bb348c97df44	1080	#define LL_RCC_PLLI2SM_DIV_39 LL_RCC_PLLM_DIV_39 /!< PLLI2S division factor for PLLI2SM output by 39 /
lypinator	0:bb348c97df44	1081	#define LL_RCC_PLLI2SM_DIV_40 LL_RCC_PLLM_DIV_40 /!< PLLI2S division factor for PLLI2SM output by 40 /
lypinator	0:bb348c97df44	1082	#define LL_RCC_PLLI2SM_DIV_41 LL_RCC_PLLM_DIV_41 /!< PLLI2S division factor for PLLI2SM output by 41 /
lypinator	0:bb348c97df44	1083	#define LL_RCC_PLLI2SM_DIV_42 LL_RCC_PLLM_DIV_42 /!< PLLI2S division factor for PLLI2SM output by 42 /
lypinator	0:bb348c97df44	1084	#define LL_RCC_PLLI2SM_DIV_43 LL_RCC_PLLM_DIV_43 /!< PLLI2S division factor for PLLI2SM output by 43 /
lypinator	0:bb348c97df44	1085	#define LL_RCC_PLLI2SM_DIV_44 LL_RCC_PLLM_DIV_44 /!< PLLI2S division factor for PLLI2SM output by 44 /
lypinator	0:bb348c97df44	1086	#define LL_RCC_PLLI2SM_DIV_45 LL_RCC_PLLM_DIV_45 /!< PLLI2S division factor for PLLI2SM output by 45 /
lypinator	0:bb348c97df44	1087	#define LL_RCC_PLLI2SM_DIV_46 LL_RCC_PLLM_DIV_46 /!< PLLI2S division factor for PLLI2SM output by 46 /
lypinator	0:bb348c97df44	1088	#define LL_RCC_PLLI2SM_DIV_47 LL_RCC_PLLM_DIV_47 /!< PLLI2S division factor for PLLI2SM output by 47 /
lypinator	0:bb348c97df44	1089	#define LL_RCC_PLLI2SM_DIV_48 LL_RCC_PLLM_DIV_48 /!< PLLI2S division factor for PLLI2SM output by 48 /
lypinator	0:bb348c97df44	1090	#define LL_RCC_PLLI2SM_DIV_49 LL_RCC_PLLM_DIV_49 /!< PLLI2S division factor for PLLI2SM output by 49 /
lypinator	0:bb348c97df44	1091	#define LL_RCC_PLLI2SM_DIV_50 LL_RCC_PLLM_DIV_50 /!< PLLI2S division factor for PLLI2SM output by 50 /
lypinator	0:bb348c97df44	1092	#define LL_RCC_PLLI2SM_DIV_51 LL_RCC_PLLM_DIV_51 /!< PLLI2S division factor for PLLI2SM output by 51 /
lypinator	0:bb348c97df44	1093	#define LL_RCC_PLLI2SM_DIV_52 LL_RCC_PLLM_DIV_52 /!< PLLI2S division factor for PLLI2SM output by 52 /
lypinator	0:bb348c97df44	1094	#define LL_RCC_PLLI2SM_DIV_53 LL_RCC_PLLM_DIV_53 /!< PLLI2S division factor for PLLI2SM output by 53 /
lypinator	0:bb348c97df44	1095	#define LL_RCC_PLLI2SM_DIV_54 LL_RCC_PLLM_DIV_54 /!< PLLI2S division factor for PLLI2SM output by 54 /
lypinator	0:bb348c97df44	1096	#define LL_RCC_PLLI2SM_DIV_55 LL_RCC_PLLM_DIV_55 /!< PLLI2S division factor for PLLI2SM output by 55 /
lypinator	0:bb348c97df44	1097	#define LL_RCC_PLLI2SM_DIV_56 LL_RCC_PLLM_DIV_56 /!< PLLI2S division factor for PLLI2SM output by 56 /
lypinator	0:bb348c97df44	1098	#define LL_RCC_PLLI2SM_DIV_57 LL_RCC_PLLM_DIV_57 /!< PLLI2S division factor for PLLI2SM output by 57 /
lypinator	0:bb348c97df44	1099	#define LL_RCC_PLLI2SM_DIV_58 LL_RCC_PLLM_DIV_58 /!< PLLI2S division factor for PLLI2SM output by 58 /
lypinator	0:bb348c97df44	1100	#define LL_RCC_PLLI2SM_DIV_59 LL_RCC_PLLM_DIV_59 /!< PLLI2S division factor for PLLI2SM output by 59 /
lypinator	0:bb348c97df44	1101	#define LL_RCC_PLLI2SM_DIV_60 LL_RCC_PLLM_DIV_60 /!< PLLI2S division factor for PLLI2SM output by 60 /
lypinator	0:bb348c97df44	1102	#define LL_RCC_PLLI2SM_DIV_61 LL_RCC_PLLM_DIV_61 /!< PLLI2S division factor for PLLI2SM output by 61 /
lypinator	0:bb348c97df44	1103	#define LL_RCC_PLLI2SM_DIV_62 LL_RCC_PLLM_DIV_62 /!< PLLI2S division factor for PLLI2SM output by 62 /
lypinator	0:bb348c97df44	1104	#define LL_RCC_PLLI2SM_DIV_63 LL_RCC_PLLM_DIV_63 /!< PLLI2S division factor for PLLI2SM output by 63 /
lypinator	0:bb348c97df44	1105	#endif /* RCC_PLLI2SCFGR_PLLI2SM */
lypinator	0:bb348c97df44	1106	/**
lypinator	0:bb348c97df44	1107	* @}
lypinator	0:bb348c97df44	1108	*/
lypinator	0:bb348c97df44	1109
lypinator	0:bb348c97df44	1110	#if defined(RCC_PLLI2SCFGR_PLLI2SQ)
lypinator	0:bb348c97df44	1111	/** @defgroup RCC_LL_EC_PLLI2SQ PLLI2SQ division factor (PLLI2SQ)
lypinator	0:bb348c97df44	1112	* @{
lypinator	0:bb348c97df44	1113	*/
lypinator	0:bb348c97df44	1114	#define LL_RCC_PLLI2SQ_DIV_2 RCC_PLLI2SCFGR_PLLI2SQ_1 /!< PLLI2S division factor for PLLI2SQ output by 2 /
lypinator	0:bb348c97df44	1115	#define LL_RCC_PLLI2SQ_DIV_3 (RCC_PLLI2SCFGR_PLLI2SQ_1 \| RCC_PLLI2SCFGR_PLLI2SQ_0) /!< PLLI2S division factor for PLLI2SQ output by 3 /
lypinator	0:bb348c97df44	1116	#define LL_RCC_PLLI2SQ_DIV_4 RCC_PLLI2SCFGR_PLLI2SQ_2 /!< PLLI2S division factor for PLLI2SQ output by 4 /
lypinator	0:bb348c97df44	1117	#define LL_RCC_PLLI2SQ_DIV_5 (RCC_PLLI2SCFGR_PLLI2SQ_2 \| RCC_PLLI2SCFGR_PLLI2SQ_0) /!< PLLI2S division factor for PLLI2SQ output by 5 /
lypinator	0:bb348c97df44	1118	#define LL_RCC_PLLI2SQ_DIV_6 (RCC_PLLI2SCFGR_PLLI2SQ_2 \| RCC_PLLI2SCFGR_PLLI2SQ_1) /!< PLLI2S division factor for PLLI2SQ output by 6 /
lypinator	0:bb348c97df44	1119	#define LL_RCC_PLLI2SQ_DIV_7 (RCC_PLLI2SCFGR_PLLI2SQ_2 \| RCC_PLLI2SCFGR_PLLI2SQ_1 \| RCC_PLLI2SCFGR_PLLI2SQ_0) /!< PLLI2S division factor for PLLI2SQ output by 7 /
lypinator	0:bb348c97df44	1120	#define LL_RCC_PLLI2SQ_DIV_8 RCC_PLLI2SCFGR_PLLI2SQ_3 /!< PLLI2S division factor for PLLI2SQ output by 8 /
lypinator	0:bb348c97df44	1121	#define LL_RCC_PLLI2SQ_DIV_9 (RCC_PLLI2SCFGR_PLLI2SQ_3 \| RCC_PLLI2SCFGR_PLLI2SQ_0) /!< PLLI2S division factor for PLLI2SQ output by 9 /
lypinator	0:bb348c97df44	1122	#define LL_RCC_PLLI2SQ_DIV_10 (RCC_PLLI2SCFGR_PLLI2SQ_3 \| RCC_PLLI2SCFGR_PLLI2SQ_1) /!< PLLI2S division factor for PLLI2SQ output by 10 /
lypinator	0:bb348c97df44	1123	#define LL_RCC_PLLI2SQ_DIV_11 (RCC_PLLI2SCFGR_PLLI2SQ_3 \| RCC_PLLI2SCFGR_PLLI2SQ_1 \| RCC_PLLI2SCFGR_PLLI2SQ_0) /!< PLLI2S division factor for PLLI2SQ output by 11 /
lypinator	0:bb348c97df44	1124	#define LL_RCC_PLLI2SQ_DIV_12 (RCC_PLLI2SCFGR_PLLI2SQ_3 \| RCC_PLLI2SCFGR_PLLI2SQ_2) /!< PLLI2S division factor for PLLI2SQ output by 12 /
lypinator	0:bb348c97df44	1125	#define LL_RCC_PLLI2SQ_DIV_13 (RCC_PLLI2SCFGR_PLLI2SQ_3 \| RCC_PLLI2SCFGR_PLLI2SQ_2 \| RCC_PLLI2SCFGR_PLLI2SQ_0) /!< PLLI2S division factor for PLLI2SQ output by 13 /
lypinator	0:bb348c97df44	1126	#define LL_RCC_PLLI2SQ_DIV_14 (RCC_PLLI2SCFGR_PLLI2SQ_3 \| RCC_PLLI2SCFGR_PLLI2SQ_2 \| RCC_PLLI2SCFGR_PLLI2SQ_1) /!< PLLI2S division factor for PLLI2SQ output by 14 /
lypinator	0:bb348c97df44	1127	#define LL_RCC_PLLI2SQ_DIV_15 (RCC_PLLI2SCFGR_PLLI2SQ_3 \| RCC_PLLI2SCFGR_PLLI2SQ_2 \| RCC_PLLI2SCFGR_PLLI2SQ_1 \| RCC_PLLI2SCFGR_PLLI2SQ_0) /!< PLLI2S division factor for PLLI2SQ output by 15 /
lypinator	0:bb348c97df44	1128	/**
lypinator	0:bb348c97df44	1129	* @}
lypinator	0:bb348c97df44	1130	*/
lypinator	0:bb348c97df44	1131	#endif /* RCC_PLLI2SCFGR_PLLI2SQ */
lypinator	0:bb348c97df44	1132
lypinator	0:bb348c97df44	1133	#if defined(RCC_DCKCFGR_PLLI2SDIVQ)
lypinator	0:bb348c97df44	1134	/** @defgroup RCC_LL_EC_PLLI2SDIVQ PLLI2SDIVQ division factor (PLLI2SDIVQ)
lypinator	0:bb348c97df44	1135	* @{
lypinator	0:bb348c97df44	1136	*/
lypinator	0:bb348c97df44	1137	#define LL_RCC_PLLI2SDIVQ_DIV_1 0x00000000U /!< PLLI2S division factor for PLLI2SDIVQ output by 1 /
lypinator	0:bb348c97df44	1138	#define LL_RCC_PLLI2SDIVQ_DIV_2 RCC_DCKCFGR_PLLI2SDIVQ_0 /!< PLLI2S division factor for PLLI2SDIVQ output by 2 /
lypinator	0:bb348c97df44	1139	#define LL_RCC_PLLI2SDIVQ_DIV_3 RCC_DCKCFGR_PLLI2SDIVQ_1 /!< PLLI2S division factor for PLLI2SDIVQ output by 3 /
lypinator	0:bb348c97df44	1140	#define LL_RCC_PLLI2SDIVQ_DIV_4 (RCC_DCKCFGR_PLLI2SDIVQ_1 \| RCC_DCKCFGR_PLLI2SDIVQ_0) /!< PLLI2S division factor for PLLI2SDIVQ output by 4 /
lypinator	0:bb348c97df44	1141	#define LL_RCC_PLLI2SDIVQ_DIV_5 RCC_DCKCFGR_PLLI2SDIVQ_2 /!< PLLI2S division factor for PLLI2SDIVQ output by 5 /
lypinator	0:bb348c97df44	1142	#define LL_RCC_PLLI2SDIVQ_DIV_6 (RCC_DCKCFGR_PLLI2SDIVQ_2 \| RCC_DCKCFGR_PLLI2SDIVQ_0) /!< PLLI2S division factor for PLLI2SDIVQ output by 6 /
lypinator	0:bb348c97df44	1143	#define LL_RCC_PLLI2SDIVQ_DIV_7 (RCC_DCKCFGR_PLLI2SDIVQ_2 \| RCC_DCKCFGR_PLLI2SDIVQ_1) /!< PLLI2S division factor for PLLI2SDIVQ output by 7 /
lypinator	0:bb348c97df44	1144	#define LL_RCC_PLLI2SDIVQ_DIV_8 (RCC_DCKCFGR_PLLI2SDIVQ_2 \| RCC_DCKCFGR_PLLI2SDIVQ_1 \| RCC_DCKCFGR_PLLI2SDIVQ_0) /!< PLLI2S division factor for PLLI2SDIVQ output by 8 /
lypinator	0:bb348c97df44	1145	#define LL_RCC_PLLI2SDIVQ_DIV_9 RCC_DCKCFGR_PLLI2SDIVQ_3 /!< PLLI2S division factor for PLLI2SDIVQ output by 9 /
lypinator	0:bb348c97df44	1146	#define LL_RCC_PLLI2SDIVQ_DIV_10 (RCC_DCKCFGR_PLLI2SDIVQ_3 \| RCC_DCKCFGR_PLLI2SDIVQ_0) /!< PLLI2S division factor for PLLI2SDIVQ output by 10 /
lypinator	0:bb348c97df44	1147	#define LL_RCC_PLLI2SDIVQ_DIV_11 (RCC_DCKCFGR_PLLI2SDIVQ_3 \| RCC_DCKCFGR_PLLI2SDIVQ_1) /!< PLLI2S division factor for PLLI2SDIVQ output by 11 /
lypinator	0:bb348c97df44	1148	#define LL_RCC_PLLI2SDIVQ_DIV_12 (RCC_DCKCFGR_PLLI2SDIVQ_3 \| RCC_DCKCFGR_PLLI2SDIVQ_1 \| RCC_DCKCFGR_PLLI2SDIVQ_0) /!< PLLI2S division factor for PLLI2SDIVQ output by 12 /
lypinator	0:bb348c97df44	1149	#define LL_RCC_PLLI2SDIVQ_DIV_13 (RCC_DCKCFGR_PLLI2SDIVQ_3 \| RCC_DCKCFGR_PLLI2SDIVQ_2) /!< PLLI2S division factor for PLLI2SDIVQ output by 13 /
lypinator	0:bb348c97df44	1150	#define LL_RCC_PLLI2SDIVQ_DIV_14 (RCC_DCKCFGR_PLLI2SDIVQ_3 \| RCC_DCKCFGR_PLLI2SDIVQ_2 \| RCC_DCKCFGR_PLLI2SDIVQ_0) /!< PLLI2S division factor for PLLI2SDIVQ output by 14 /
lypinator	0:bb348c97df44	1151	#define LL_RCC_PLLI2SDIVQ_DIV_15 (RCC_DCKCFGR_PLLI2SDIVQ_3 \| RCC_DCKCFGR_PLLI2SDIVQ_2 \| RCC_DCKCFGR_PLLI2SDIVQ_1) /!< PLLI2S division factor for PLLI2SDIVQ output by 15 /
lypinator	0:bb348c97df44	1152	#define LL_RCC_PLLI2SDIVQ_DIV_16 (RCC_DCKCFGR_PLLI2SDIVQ_3 \| RCC_DCKCFGR_PLLI2SDIVQ_2 \| RCC_DCKCFGR_PLLI2SDIVQ_1 \| RCC_DCKCFGR_PLLI2SDIVQ_0) /!< PLLI2S division factor for PLLI2SDIVQ output by 16 /
lypinator	0:bb348c97df44	1153	#define LL_RCC_PLLI2SDIVQ_DIV_17 RCC_DCKCFGR_PLLI2SDIVQ_4 /!< PLLI2S division factor for PLLI2SDIVQ output by 17 /
lypinator	0:bb348c97df44	1154	#define LL_RCC_PLLI2SDIVQ_DIV_18 (RCC_DCKCFGR_PLLI2SDIVQ_4 \| RCC_DCKCFGR_PLLI2SDIVQ_0) /!< PLLI2S division factor for PLLI2SDIVQ output by 18 /
lypinator	0:bb348c97df44	1155	#define LL_RCC_PLLI2SDIVQ_DIV_19 (RCC_DCKCFGR_PLLI2SDIVQ_4 \| RCC_DCKCFGR_PLLI2SDIVQ_1) /!< PLLI2S division factor for PLLI2SDIVQ output by 19 /
lypinator	0:bb348c97df44	1156	#define LL_RCC_PLLI2SDIVQ_DIV_20 (RCC_DCKCFGR_PLLI2SDIVQ_4 \| RCC_DCKCFGR_PLLI2SDIVQ_1 \| RCC_DCKCFGR_PLLI2SDIVQ_0) /!< PLLI2S division factor for PLLI2SDIVQ output by 20 /
lypinator	0:bb348c97df44	1157	#define LL_RCC_PLLI2SDIVQ_DIV_21 (RCC_DCKCFGR_PLLI2SDIVQ_4 \| RCC_DCKCFGR_PLLI2SDIVQ_2) /!< PLLI2S division factor for PLLI2SDIVQ output by 21 /
lypinator	0:bb348c97df44	1158	#define LL_RCC_PLLI2SDIVQ_DIV_22 (RCC_DCKCFGR_PLLI2SDIVQ_4 \| RCC_DCKCFGR_PLLI2SDIVQ_2 \| RCC_DCKCFGR_PLLI2SDIVQ_0) /!< PLLI2S division factor for PLLI2SDIVQ output by 22 /
lypinator	0:bb348c97df44	1159	#define LL_RCC_PLLI2SDIVQ_DIV_23 (RCC_DCKCFGR_PLLI2SDIVQ_4 \| RCC_DCKCFGR_PLLI2SDIVQ_2 \| RCC_DCKCFGR_PLLI2SDIVQ_1) /!< PLLI2S division factor for PLLI2SDIVQ output by 23 /
lypinator	0:bb348c97df44	1160	#define LL_RCC_PLLI2SDIVQ_DIV_24 (RCC_DCKCFGR_PLLI2SDIVQ_4 \| RCC_DCKCFGR_PLLI2SDIVQ_2 \| RCC_DCKCFGR_PLLI2SDIVQ_1 \| RCC_DCKCFGR_PLLI2SDIVQ_0) /!< PLLI2S division factor for PLLI2SDIVQ output by 24 /
lypinator	0:bb348c97df44	1161	#define LL_RCC_PLLI2SDIVQ_DIV_25 (RCC_DCKCFGR_PLLI2SDIVQ_4 \| RCC_DCKCFGR_PLLI2SDIVQ_3) /!< PLLI2S division factor for PLLI2SDIVQ output by 25 /
lypinator	0:bb348c97df44	1162	#define LL_RCC_PLLI2SDIVQ_DIV_26 (RCC_DCKCFGR_PLLI2SDIVQ_4 \| RCC_DCKCFGR_PLLI2SDIVQ_3 \| RCC_DCKCFGR_PLLI2SDIVQ_0) /!< PLLI2S division factor for PLLI2SDIVQ output by 26 /
lypinator	0:bb348c97df44	1163	#define LL_RCC_PLLI2SDIVQ_DIV_27 (RCC_DCKCFGR_PLLI2SDIVQ_4 \| RCC_DCKCFGR_PLLI2SDIVQ_3 \| RCC_DCKCFGR_PLLI2SDIVQ_1) /!< PLLI2S division factor for PLLI2SDIVQ output by 27 /
lypinator	0:bb348c97df44	1164	#define LL_RCC_PLLI2SDIVQ_DIV_28 (RCC_DCKCFGR_PLLI2SDIVQ_4 \| RCC_DCKCFGR_PLLI2SDIVQ_3 \| RCC_DCKCFGR_PLLI2SDIVQ_1 \| RCC_DCKCFGR_PLLI2SDIVQ_0) /!< PLLI2S division factor for PLLI2SDIVQ output by 28 /
lypinator	0:bb348c97df44	1165	#define LL_RCC_PLLI2SDIVQ_DIV_29 (RCC_DCKCFGR_PLLI2SDIVQ_4 \| RCC_DCKCFGR_PLLI2SDIVQ_3 \| RCC_DCKCFGR_PLLI2SDIVQ_2) /!< PLLI2S division factor for PLLI2SDIVQ output by 29 /
lypinator	0:bb348c97df44	1166	#define LL_RCC_PLLI2SDIVQ_DIV_30 (RCC_DCKCFGR_PLLI2SDIVQ_4 \| RCC_DCKCFGR_PLLI2SDIVQ_3 \| RCC_DCKCFGR_PLLI2SDIVQ_2 \| RCC_DCKCFGR_PLLI2SDIVQ_0) /!< PLLI2S division factor for PLLI2SDIVQ output by 30 /
lypinator	0:bb348c97df44	1167	#define LL_RCC_PLLI2SDIVQ_DIV_31 (RCC_DCKCFGR_PLLI2SDIVQ_4 \| RCC_DCKCFGR_PLLI2SDIVQ_3 \| RCC_DCKCFGR_PLLI2SDIVQ_2 \| RCC_DCKCFGR_PLLI2SDIVQ_1) /!< PLLI2S division factor for PLLI2SDIVQ output by 31 /
lypinator	0:bb348c97df44	1168	#define LL_RCC_PLLI2SDIVQ_DIV_32 (RCC_DCKCFGR_PLLI2SDIVQ_4 \| RCC_DCKCFGR_PLLI2SDIVQ_3 \| RCC_DCKCFGR_PLLI2SDIVQ_2 \| RCC_DCKCFGR_PLLI2SDIVQ_1 \| RCC_DCKCFGR_PLLI2SDIVQ_0) /!< PLLI2S division factor for PLLI2SDIVQ output by 32 /
lypinator	0:bb348c97df44	1169	/**
lypinator	0:bb348c97df44	1170	* @}
lypinator	0:bb348c97df44	1171	*/
lypinator	0:bb348c97df44	1172	#endif /* RCC_DCKCFGR_PLLI2SDIVQ */
lypinator	0:bb348c97df44	1173
lypinator	0:bb348c97df44	1174	#if defined(RCC_DCKCFGR_PLLI2SDIVR)
lypinator	0:bb348c97df44	1175	/** @defgroup RCC_LL_EC_PLLI2SDIVR PLLI2SDIVR division factor (PLLI2SDIVR)
lypinator	0:bb348c97df44	1176	* @{
lypinator	0:bb348c97df44	1177	*/
lypinator	0:bb348c97df44	1178	#define LL_RCC_PLLI2SDIVR_DIV_1 (RCC_DCKCFGR_PLLI2SDIVR_0) /!< PLLI2S division factor for PLLI2SDIVR output by 1 /
lypinator	0:bb348c97df44	1179	#define LL_RCC_PLLI2SDIVR_DIV_2 (RCC_DCKCFGR_PLLI2SDIVR_1) /!< PLLI2S division factor for PLLI2SDIVR output by 2 /
lypinator	0:bb348c97df44	1180	#define LL_RCC_PLLI2SDIVR_DIV_3 (RCC_DCKCFGR_PLLI2SDIVR_1 \| RCC_DCKCFGR_PLLI2SDIVR_0) /!< PLLI2S division factor for PLLI2SDIVR output by 3 /
lypinator	0:bb348c97df44	1181	#define LL_RCC_PLLI2SDIVR_DIV_4 (RCC_DCKCFGR_PLLI2SDIVR_2) /!< PLLI2S division factor for PLLI2SDIVR output by 4 /
lypinator	0:bb348c97df44	1182	#define LL_RCC_PLLI2SDIVR_DIV_5 (RCC_DCKCFGR_PLLI2SDIVR_2 \| RCC_DCKCFGR_PLLI2SDIVR_0) /!< PLLI2S division factor for PLLI2SDIVR output by 5 /
lypinator	0:bb348c97df44	1183	#define LL_RCC_PLLI2SDIVR_DIV_6 (RCC_DCKCFGR_PLLI2SDIVR_2 \| RCC_DCKCFGR_PLLI2SDIVR_1) /!< PLLI2S division factor for PLLI2SDIVR output by 6 /
lypinator	0:bb348c97df44	1184	#define LL_RCC_PLLI2SDIVR_DIV_7 (RCC_DCKCFGR_PLLI2SDIVR_2 \| RCC_DCKCFGR_PLLI2SDIVR_1 \| RCC_DCKCFGR_PLLI2SDIVR_0) /!< PLLI2S division factor for PLLI2SDIVR output by 7 /
lypinator	0:bb348c97df44	1185	#define LL_RCC_PLLI2SDIVR_DIV_8 (RCC_DCKCFGR_PLLI2SDIVR_3) /!< PLLI2S division factor for PLLI2SDIVR output by 8 /
lypinator	0:bb348c97df44	1186	#define LL_RCC_PLLI2SDIVR_DIV_9 (RCC_DCKCFGR_PLLI2SDIVR_3 \| RCC_DCKCFGR_PLLI2SDIVR_0) /!< PLLI2S division factor for PLLI2SDIVR output by 9 /
lypinator	0:bb348c97df44	1187	#define LL_RCC_PLLI2SDIVR_DIV_10 (RCC_DCKCFGR_PLLI2SDIVR_3 \| RCC_DCKCFGR_PLLI2SDIVR_1) /!< PLLI2S division factor for PLLI2SDIVR output by 10 /
lypinator	0:bb348c97df44	1188	#define LL_RCC_PLLI2SDIVR_DIV_11 (RCC_DCKCFGR_PLLI2SDIVR_3 \| RCC_DCKCFGR_PLLI2SDIVR_1 \| RCC_DCKCFGR_PLLI2SDIVR_0) /!< PLLI2S division factor for PLLI2SDIVR output by 11 /
lypinator	0:bb348c97df44	1189	#define LL_RCC_PLLI2SDIVR_DIV_12 (RCC_DCKCFGR_PLLI2SDIVR_3 \| RCC_DCKCFGR_PLLI2SDIVR_2) /!< PLLI2S division factor for PLLI2SDIVR output by 12 /
lypinator	0:bb348c97df44	1190	#define LL_RCC_PLLI2SDIVR_DIV_13 (RCC_DCKCFGR_PLLI2SDIVR_3 \| RCC_DCKCFGR_PLLI2SDIVR_2 \| RCC_DCKCFGR_PLLI2SDIVR_0) /!< PLLI2S division factor for PLLI2SDIVR output by 13 /
lypinator	0:bb348c97df44	1191	#define LL_RCC_PLLI2SDIVR_DIV_14 (RCC_DCKCFGR_PLLI2SDIVR_3 \| RCC_DCKCFGR_PLLI2SDIVR_2 \| RCC_DCKCFGR_PLLI2SDIVR_1) /!< PLLI2S division factor for PLLI2SDIVR output by 14 /
lypinator	0:bb348c97df44	1192	#define LL_RCC_PLLI2SDIVR_DIV_15 (RCC_DCKCFGR_PLLI2SDIVR_3 \| RCC_DCKCFGR_PLLI2SDIVR_2 \| RCC_DCKCFGR_PLLI2SDIVR_1 \| RCC_DCKCFGR_PLLI2SDIVR_0) /!< PLLI2S division factor for PLLI2SDIVR output by 15 /
lypinator	0:bb348c97df44	1193	#define LL_RCC_PLLI2SDIVR_DIV_16 (RCC_DCKCFGR_PLLI2SDIVR_4) /!< PLLI2S division factor for PLLI2SDIVR output by 16 /
lypinator	0:bb348c97df44	1194	#define LL_RCC_PLLI2SDIVR_DIV_17 (RCC_DCKCFGR_PLLI2SDIVR_4 \| RCC_DCKCFGR_PLLI2SDIVR_0) /!< PLLI2S division factor for PLLI2SDIVR output by 17 /
lypinator	0:bb348c97df44	1195	#define LL_RCC_PLLI2SDIVR_DIV_18 (RCC_DCKCFGR_PLLI2SDIVR_4 \| RCC_DCKCFGR_PLLI2SDIVR_1) /!< PLLI2S division factor for PLLI2SDIVR output by 18 /
lypinator	0:bb348c97df44	1196	#define LL_RCC_PLLI2SDIVR_DIV_19 (RCC_DCKCFGR_PLLI2SDIVR_4 \| RCC_DCKCFGR_PLLI2SDIVR_1 \| RCC_DCKCFGR_PLLI2SDIVR_0) /!< PLLI2S division factor for PLLI2SDIVR output by 19 /
lypinator	0:bb348c97df44	1197	#define LL_RCC_PLLI2SDIVR_DIV_20 (RCC_DCKCFGR_PLLI2SDIVR_4 \| RCC_DCKCFGR_PLLI2SDIVR_2) /!< PLLI2S division factor for PLLI2SDIVR output by 20 /
lypinator	0:bb348c97df44	1198	#define LL_RCC_PLLI2SDIVR_DIV_21 (RCC_DCKCFGR_PLLI2SDIVR_4 \| RCC_DCKCFGR_PLLI2SDIVR_2 \| RCC_DCKCFGR_PLLI2SDIVR_0) /!< PLLI2S division factor for PLLI2SDIVR output by 21 /
lypinator	0:bb348c97df44	1199	#define LL_RCC_PLLI2SDIVR_DIV_22 (RCC_DCKCFGR_PLLI2SDIVR_4 \| RCC_DCKCFGR_PLLI2SDIVR_2 \| RCC_DCKCFGR_PLLI2SDIVR_1) /!< PLLI2S division factor for PLLI2SDIVR output by 22 /
lypinator	0:bb348c97df44	1200	#define LL_RCC_PLLI2SDIVR_DIV_23 (RCC_DCKCFGR_PLLI2SDIVR_4 \| RCC_DCKCFGR_PLLI2SDIVR_2 \| RCC_DCKCFGR_PLLI2SDIVR_1 \| RCC_DCKCFGR_PLLI2SDIVR_0) /!< PLLI2S division factor for PLLI2SDIVR output by 23 /
lypinator	0:bb348c97df44	1201	#define LL_RCC_PLLI2SDIVR_DIV_24 (RCC_DCKCFGR_PLLI2SDIVR_4 \| RCC_DCKCFGR_PLLI2SDIVR_3) /!< PLLI2S division factor for PLLI2SDIVR output by 24 /
lypinator	0:bb348c97df44	1202	#define LL_RCC_PLLI2SDIVR_DIV_25 (RCC_DCKCFGR_PLLI2SDIVR_4 \| RCC_DCKCFGR_PLLI2SDIVR_3 \| RCC_DCKCFGR_PLLI2SDIVR_0) /!< PLLI2S division factor for PLLI2SDIVR output by 25 /
lypinator	0:bb348c97df44	1203	#define LL_RCC_PLLI2SDIVR_DIV_26 (RCC_DCKCFGR_PLLI2SDIVR_4 \| RCC_DCKCFGR_PLLI2SDIVR_3 \| RCC_DCKCFGR_PLLI2SDIVR_1) /!< PLLI2S division factor for PLLI2SDIVR output by 26 /
lypinator	0:bb348c97df44	1204	#define LL_RCC_PLLI2SDIVR_DIV_27 (RCC_DCKCFGR_PLLI2SDIVR_4 \| RCC_DCKCFGR_PLLI2SDIVR_3 \| RCC_DCKCFGR_PLLI2SDIVR_1 \| RCC_DCKCFGR_PLLI2SDIVR_0) /!< PLLI2S division factor for PLLI2SDIVR output by 27 /
lypinator	0:bb348c97df44	1205	#define LL_RCC_PLLI2SDIVR_DIV_28 (RCC_DCKCFGR_PLLI2SDIVR_4 \| RCC_DCKCFGR_PLLI2SDIVR_3 \| RCC_DCKCFGR_PLLI2SDIVR_2) /!< PLLI2S division factor for PLLI2SDIVR output by 28 /
lypinator	0:bb348c97df44	1206	#define LL_RCC_PLLI2SDIVR_DIV_29 (RCC_DCKCFGR_PLLI2SDIVR_4 \| RCC_DCKCFGR_PLLI2SDIVR_3 \| RCC_DCKCFGR_PLLI2SDIVR_2 \| RCC_DCKCFGR_PLLI2SDIVR_0) /!< PLLI2S division factor for PLLI2SDIVR output by 29 /
lypinator	0:bb348c97df44	1207	#define LL_RCC_PLLI2SDIVR_DIV_30 (RCC_DCKCFGR_PLLI2SDIVR_4 \| RCC_DCKCFGR_PLLI2SDIVR_3 \| RCC_DCKCFGR_PLLI2SDIVR_2 \| RCC_DCKCFGR_PLLI2SDIVR_1) /!< PLLI2S division factor for PLLI2SDIVR output by 30 /
lypinator	0:bb348c97df44	1208	#define LL_RCC_PLLI2SDIVR_DIV_31 (RCC_DCKCFGR_PLLI2SDIVR_4 \| RCC_DCKCFGR_PLLI2SDIVR_3 \| RCC_DCKCFGR_PLLI2SDIVR_2 \| RCC_DCKCFGR_PLLI2SDIVR_1 \| RCC_DCKCFGR_PLLI2SDIVR_0) /!< PLLI2S division factor for PLLI2SDIVR output by 31 /
lypinator	0:bb348c97df44	1209	/**
lypinator	0:bb348c97df44	1210	* @}
lypinator	0:bb348c97df44	1211	*/
lypinator	0:bb348c97df44	1212	#endif /* RCC_DCKCFGR_PLLI2SDIVR */
lypinator	0:bb348c97df44	1213
lypinator	0:bb348c97df44	1214	/** @defgroup RCC_LL_EC_PLLI2SR PLLI2SR division factor (PLLI2SR)
lypinator	0:bb348c97df44	1215	* @{
lypinator	0:bb348c97df44	1216	*/
lypinator	0:bb348c97df44	1217	#define LL_RCC_PLLI2SR_DIV_2 RCC_PLLI2SCFGR_PLLI2SR_1 /!< PLLI2S division factor for PLLI2SR output by 2 /
lypinator	0:bb348c97df44	1218	#define LL_RCC_PLLI2SR_DIV_3 (RCC_PLLI2SCFGR_PLLI2SR_1 \| RCC_PLLI2SCFGR_PLLI2SR_0) /!< PLLI2S division factor for PLLI2SR output by 3 /
lypinator	0:bb348c97df44	1219	#define LL_RCC_PLLI2SR_DIV_4 RCC_PLLI2SCFGR_PLLI2SR_2 /!< PLLI2S division factor for PLLI2SR output by 4 /
lypinator	0:bb348c97df44	1220	#define LL_RCC_PLLI2SR_DIV_5 (RCC_PLLI2SCFGR_PLLI2SR_2 \| RCC_PLLI2SCFGR_PLLI2SR_0) /!< PLLI2S division factor for PLLI2SR output by 5 /
lypinator	0:bb348c97df44	1221	#define LL_RCC_PLLI2SR_DIV_6 (RCC_PLLI2SCFGR_PLLI2SR_2 \| RCC_PLLI2SCFGR_PLLI2SR_1) /!< PLLI2S division factor for PLLI2SR output by 6 /
lypinator	0:bb348c97df44	1222	#define LL_RCC_PLLI2SR_DIV_7 (RCC_PLLI2SCFGR_PLLI2SR_2 \| RCC_PLLI2SCFGR_PLLI2SR_1 \| RCC_PLLI2SCFGR_PLLI2SR_0) /!< PLLI2S division factor for PLLI2SR output by 7 /
lypinator	0:bb348c97df44	1223	/**
lypinator	0:bb348c97df44	1224	* @}
lypinator	0:bb348c97df44	1225	*/
lypinator	0:bb348c97df44	1226
lypinator	0:bb348c97df44	1227	#if defined(RCC_PLLI2SCFGR_PLLI2SP)
lypinator	0:bb348c97df44	1228	/** @defgroup RCC_LL_EC_PLLI2SP PLLI2SP division factor (PLLI2SP)
lypinator	0:bb348c97df44	1229	* @{
lypinator	0:bb348c97df44	1230	*/
lypinator	0:bb348c97df44	1231	#define LL_RCC_PLLI2SP_DIV_2 0x00000000U /!< PLLI2S division factor for PLLI2SP output by 2 /
lypinator	0:bb348c97df44	1232	#define LL_RCC_PLLI2SP_DIV_4 RCC_PLLI2SCFGR_PLLI2SP_0 /!< PLLI2S division factor for PLLI2SP output by 4 /
lypinator	0:bb348c97df44	1233	#define LL_RCC_PLLI2SP_DIV_6 RCC_PLLI2SCFGR_PLLI2SP_1 /!< PLLI2S division factor for PLLI2SP output by 6 /
lypinator	0:bb348c97df44	1234	#define LL_RCC_PLLI2SP_DIV_8 (RCC_PLLI2SCFGR_PLLI2SP_1 \| RCC_PLLI2SCFGR_PLLI2SP_0) /!< PLLI2S division factor for PLLI2SP output by 8 /
lypinator	0:bb348c97df44	1235	/**
lypinator	0:bb348c97df44	1236	* @}
lypinator	0:bb348c97df44	1237	*/
lypinator	0:bb348c97df44	1238	#endif /* RCC_PLLI2SCFGR_PLLI2SP */
lypinator	0:bb348c97df44	1239	#endif /* RCC_PLLI2S_SUPPORT */
lypinator	0:bb348c97df44	1240
lypinator	0:bb348c97df44	1241	#if defined(RCC_PLLSAI_SUPPORT)
lypinator	0:bb348c97df44	1242	/** @defgroup RCC_LL_EC_PLLSAIM PLLSAIM division factor (PLLSAIM or PLLM)
lypinator	0:bb348c97df44	1243	* @{
lypinator	0:bb348c97df44	1244	*/
lypinator	0:bb348c97df44	1245	#if defined(RCC_PLLSAICFGR_PLLSAIM)
lypinator	0:bb348c97df44	1246	#define LL_RCC_PLLSAIM_DIV_2 (RCC_PLLSAICFGR_PLLSAIM_1) /!< PLLSAI division factor for PLLSAIM output by 2 /
lypinator	0:bb348c97df44	1247	#define LL_RCC_PLLSAIM_DIV_3 (RCC_PLLSAICFGR_PLLSAIM_1 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 3 /
lypinator	0:bb348c97df44	1248	#define LL_RCC_PLLSAIM_DIV_4 (RCC_PLLSAICFGR_PLLSAIM_2) /!< PLLSAI division factor for PLLSAIM output by 4 /
lypinator	0:bb348c97df44	1249	#define LL_RCC_PLLSAIM_DIV_5 (RCC_PLLSAICFGR_PLLSAIM_2 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 5 /
lypinator	0:bb348c97df44	1250	#define LL_RCC_PLLSAIM_DIV_6 (RCC_PLLSAICFGR_PLLSAIM_2 \| RCC_PLLSAICFGR_PLLSAIM_1) /!< PLLSAI division factor for PLLSAIM output by 6 /
lypinator	0:bb348c97df44	1251	#define LL_RCC_PLLSAIM_DIV_7 (RCC_PLLSAICFGR_PLLSAIM_2 \| RCC_PLLSAICFGR_PLLSAIM_1 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 7 /
lypinator	0:bb348c97df44	1252	#define LL_RCC_PLLSAIM_DIV_8 (RCC_PLLSAICFGR_PLLSAIM_3) /!< PLLSAI division factor for PLLSAIM output by 8 /
lypinator	0:bb348c97df44	1253	#define LL_RCC_PLLSAIM_DIV_9 (RCC_PLLSAICFGR_PLLSAIM_3 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 9 /
lypinator	0:bb348c97df44	1254	#define LL_RCC_PLLSAIM_DIV_10 (RCC_PLLSAICFGR_PLLSAIM_3 \| RCC_PLLSAICFGR_PLLSAIM_1) /!< PLLSAI division factor for PLLSAIM output by 10 /
lypinator	0:bb348c97df44	1255	#define LL_RCC_PLLSAIM_DIV_11 (RCC_PLLSAICFGR_PLLSAIM_3 \| RCC_PLLSAICFGR_PLLSAIM_1 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 11 /
lypinator	0:bb348c97df44	1256	#define LL_RCC_PLLSAIM_DIV_12 (RCC_PLLSAICFGR_PLLSAIM_3 \| RCC_PLLSAICFGR_PLLSAIM_2) /!< PLLSAI division factor for PLLSAIM output by 12 /
lypinator	0:bb348c97df44	1257	#define LL_RCC_PLLSAIM_DIV_13 (RCC_PLLSAICFGR_PLLSAIM_3 \| RCC_PLLSAICFGR_PLLSAIM_2 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 13 /
lypinator	0:bb348c97df44	1258	#define LL_RCC_PLLSAIM_DIV_14 (RCC_PLLSAICFGR_PLLSAIM_3 \| RCC_PLLSAICFGR_PLLSAIM_2 \| RCC_PLLSAICFGR_PLLSAIM_1) /!< PLLSAI division factor for PLLSAIM output by 14 /
lypinator	0:bb348c97df44	1259	#define LL_RCC_PLLSAIM_DIV_15 (RCC_PLLSAICFGR_PLLSAIM_3 \| RCC_PLLSAICFGR_PLLSAIM_2 \| RCC_PLLSAICFGR_PLLSAIM_1 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 15 /
lypinator	0:bb348c97df44	1260	#define LL_RCC_PLLSAIM_DIV_16 (RCC_PLLSAICFGR_PLLSAIM_4) /!< PLLSAI division factor for PLLSAIM output by 16 /
lypinator	0:bb348c97df44	1261	#define LL_RCC_PLLSAIM_DIV_17 (RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 17 /
lypinator	0:bb348c97df44	1262	#define LL_RCC_PLLSAIM_DIV_18 (RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_1) /!< PLLSAI division factor for PLLSAIM output by 18 /
lypinator	0:bb348c97df44	1263	#define LL_RCC_PLLSAIM_DIV_19 (RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_1 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 19 /
lypinator	0:bb348c97df44	1264	#define LL_RCC_PLLSAIM_DIV_20 (RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_2) /!< PLLSAI division factor for PLLSAIM output by 20 /
lypinator	0:bb348c97df44	1265	#define LL_RCC_PLLSAIM_DIV_21 (RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_2 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 21 /
lypinator	0:bb348c97df44	1266	#define LL_RCC_PLLSAIM_DIV_22 (RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_2 \| RCC_PLLSAICFGR_PLLSAIM_1) /!< PLLSAI division factor for PLLSAIM output by 22 /
lypinator	0:bb348c97df44	1267	#define LL_RCC_PLLSAIM_DIV_23 (RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_2 \| RCC_PLLSAICFGR_PLLSAIM_1 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 23 /
lypinator	0:bb348c97df44	1268	#define LL_RCC_PLLSAIM_DIV_24 (RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_3) /!< PLLSAI division factor for PLLSAIM output by 24 /
lypinator	0:bb348c97df44	1269	#define LL_RCC_PLLSAIM_DIV_25 (RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_3 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 25 /
lypinator	0:bb348c97df44	1270	#define LL_RCC_PLLSAIM_DIV_26 (RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_3 \| RCC_PLLSAICFGR_PLLSAIM_1) /!< PLLSAI division factor for PLLSAIM output by 26 /
lypinator	0:bb348c97df44	1271	#define LL_RCC_PLLSAIM_DIV_27 (RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_3 \| RCC_PLLSAICFGR_PLLSAIM_1 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 27 /
lypinator	0:bb348c97df44	1272	#define LL_RCC_PLLSAIM_DIV_28 (RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_3 \| RCC_PLLSAICFGR_PLLSAIM_2) /!< PLLSAI division factor for PLLSAIM output by 28 /
lypinator	0:bb348c97df44	1273	#define LL_RCC_PLLSAIM_DIV_29 (RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_3 \| RCC_PLLSAICFGR_PLLSAIM_2 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 29 /
lypinator	0:bb348c97df44	1274	#define LL_RCC_PLLSAIM_DIV_30 (RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_3 \| RCC_PLLSAICFGR_PLLSAIM_2 \| RCC_PLLSAICFGR_PLLSAIM_1) /!< PLLSAI division factor for PLLSAIM output by 30 /
lypinator	0:bb348c97df44	1275	#define LL_RCC_PLLSAIM_DIV_31 (RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_3 \| RCC_PLLSAICFGR_PLLSAIM_2 \| RCC_PLLSAICFGR_PLLSAIM_1 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 31 /
lypinator	0:bb348c97df44	1276	#define LL_RCC_PLLSAIM_DIV_32 (RCC_PLLSAICFGR_PLLSAIM_5) /!< PLLSAI division factor for PLLSAIM output by 32 /
lypinator	0:bb348c97df44	1277	#define LL_RCC_PLLSAIM_DIV_33 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 33 /
lypinator	0:bb348c97df44	1278	#define LL_RCC_PLLSAIM_DIV_34 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_1) /!< PLLSAI division factor for PLLSAIM output by 34 /
lypinator	0:bb348c97df44	1279	#define LL_RCC_PLLSAIM_DIV_35 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_1 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 35 /
lypinator	0:bb348c97df44	1280	#define LL_RCC_PLLSAIM_DIV_36 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_2) /!< PLLSAI division factor for PLLSAIM output by 36 /
lypinator	0:bb348c97df44	1281	#define LL_RCC_PLLSAIM_DIV_37 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_2 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 37 /
lypinator	0:bb348c97df44	1282	#define LL_RCC_PLLSAIM_DIV_38 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_2 \| RCC_PLLSAICFGR_PLLSAIM_1) /!< PLLSAI division factor for PLLSAIM output by 38 /
lypinator	0:bb348c97df44	1283	#define LL_RCC_PLLSAIM_DIV_39 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_2 \| RCC_PLLSAICFGR_PLLSAIM_1 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 39 /
lypinator	0:bb348c97df44	1284	#define LL_RCC_PLLSAIM_DIV_40 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_3) /!< PLLSAI division factor for PLLSAIM output by 40 /
lypinator	0:bb348c97df44	1285	#define LL_RCC_PLLSAIM_DIV_41 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_3 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 41 /
lypinator	0:bb348c97df44	1286	#define LL_RCC_PLLSAIM_DIV_42 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_3 \| RCC_PLLSAICFGR_PLLSAIM_1) /!< PLLSAI division factor for PLLSAIM output by 42 /
lypinator	0:bb348c97df44	1287	#define LL_RCC_PLLSAIM_DIV_43 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_3 \| RCC_PLLSAICFGR_PLLSAIM_1 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 43 /
lypinator	0:bb348c97df44	1288	#define LL_RCC_PLLSAIM_DIV_44 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_3 \| RCC_PLLSAICFGR_PLLSAIM_2) /!< PLLSAI division factor for PLLSAIM output by 44 /
lypinator	0:bb348c97df44	1289	#define LL_RCC_PLLSAIM_DIV_45 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_3 \| RCC_PLLSAICFGR_PLLSAIM_2 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 45 /
lypinator	0:bb348c97df44	1290	#define LL_RCC_PLLSAIM_DIV_46 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_3 \| RCC_PLLSAICFGR_PLLSAIM_2 \| RCC_PLLSAICFGR_PLLSAIM_1) /!< PLLSAI division factor for PLLSAIM output by 46 /
lypinator	0:bb348c97df44	1291	#define LL_RCC_PLLSAIM_DIV_47 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_3 \| RCC_PLLSAICFGR_PLLSAIM_2 \| RCC_PLLSAICFGR_PLLSAIM_1 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 47 /
lypinator	0:bb348c97df44	1292	#define LL_RCC_PLLSAIM_DIV_48 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_4) /!< PLLSAI division factor for PLLSAIM output by 48 /
lypinator	0:bb348c97df44	1293	#define LL_RCC_PLLSAIM_DIV_49 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 49 /
lypinator	0:bb348c97df44	1294	#define LL_RCC_PLLSAIM_DIV_50 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_1) /!< PLLSAI division factor for PLLSAIM output by 50 /
lypinator	0:bb348c97df44	1295	#define LL_RCC_PLLSAIM_DIV_51 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_1 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 51 /
lypinator	0:bb348c97df44	1296	#define LL_RCC_PLLSAIM_DIV_52 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_2) /!< PLLSAI division factor for PLLSAIM output by 52 /
lypinator	0:bb348c97df44	1297	#define LL_RCC_PLLSAIM_DIV_53 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_2 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 53 /
lypinator	0:bb348c97df44	1298	#define LL_RCC_PLLSAIM_DIV_54 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_2 \| RCC_PLLSAICFGR_PLLSAIM_1) /!< PLLSAI division factor for PLLSAIM output by 54 /
lypinator	0:bb348c97df44	1299	#define LL_RCC_PLLSAIM_DIV_55 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_2 \| RCC_PLLSAICFGR_PLLSAIM_1 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 55 /
lypinator	0:bb348c97df44	1300	#define LL_RCC_PLLSAIM_DIV_56 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_3) /!< PLLSAI division factor for PLLSAIM output by 56 /
lypinator	0:bb348c97df44	1301	#define LL_RCC_PLLSAIM_DIV_57 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_3 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 57 /
lypinator	0:bb348c97df44	1302	#define LL_RCC_PLLSAIM_DIV_58 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_3 \| RCC_PLLSAICFGR_PLLSAIM_1) /!< PLLSAI division factor for PLLSAIM output by 58 /
lypinator	0:bb348c97df44	1303	#define LL_RCC_PLLSAIM_DIV_59 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_3 \| RCC_PLLSAICFGR_PLLSAIM_1 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 59 /
lypinator	0:bb348c97df44	1304	#define LL_RCC_PLLSAIM_DIV_60 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_3 \| RCC_PLLSAICFGR_PLLSAIM_2) /!< PLLSAI division factor for PLLSAIM output by 60 /
lypinator	0:bb348c97df44	1305	#define LL_RCC_PLLSAIM_DIV_61 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_3 \| RCC_PLLSAICFGR_PLLSAIM_2 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 61 /
lypinator	0:bb348c97df44	1306	#define LL_RCC_PLLSAIM_DIV_62 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_3 \| RCC_PLLSAICFGR_PLLSAIM_2 \| RCC_PLLSAICFGR_PLLSAIM_1) /!< PLLSAI division factor for PLLSAIM output by 62 /
lypinator	0:bb348c97df44	1307	#define LL_RCC_PLLSAIM_DIV_63 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_3 \| RCC_PLLSAICFGR_PLLSAIM_2 \| RCC_PLLSAICFGR_PLLSAIM_1 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 63 /
lypinator	0:bb348c97df44	1308	#else
lypinator	0:bb348c97df44	1309	#define LL_RCC_PLLSAIM_DIV_2 LL_RCC_PLLM_DIV_2 /!< PLLSAI division factor for PLLSAIM output by 2 /
lypinator	0:bb348c97df44	1310	#define LL_RCC_PLLSAIM_DIV_3 LL_RCC_PLLM_DIV_3 /!< PLLSAI division factor for PLLSAIM output by 3 /
lypinator	0:bb348c97df44	1311	#define LL_RCC_PLLSAIM_DIV_4 LL_RCC_PLLM_DIV_4 /!< PLLSAI division factor for PLLSAIM output by 4 /
lypinator	0:bb348c97df44	1312	#define LL_RCC_PLLSAIM_DIV_5 LL_RCC_PLLM_DIV_5 /!< PLLSAI division factor for PLLSAIM output by 5 /
lypinator	0:bb348c97df44	1313	#define LL_RCC_PLLSAIM_DIV_6 LL_RCC_PLLM_DIV_6 /!< PLLSAI division factor for PLLSAIM output by 6 /
lypinator	0:bb348c97df44	1314	#define LL_RCC_PLLSAIM_DIV_7 LL_RCC_PLLM_DIV_7 /!< PLLSAI division factor for PLLSAIM output by 7 /
lypinator	0:bb348c97df44	1315	#define LL_RCC_PLLSAIM_DIV_8 LL_RCC_PLLM_DIV_8 /!< PLLSAI division factor for PLLSAIM output by 8 /
lypinator	0:bb348c97df44	1316	#define LL_RCC_PLLSAIM_DIV_9 LL_RCC_PLLM_DIV_9 /!< PLLSAI division factor for PLLSAIM output by 9 /
lypinator	0:bb348c97df44	1317	#define LL_RCC_PLLSAIM_DIV_10 LL_RCC_PLLM_DIV_10 /!< PLLSAI division factor for PLLSAIM output by 10 /
lypinator	0:bb348c97df44	1318	#define LL_RCC_PLLSAIM_DIV_11 LL_RCC_PLLM_DIV_11 /!< PLLSAI division factor for PLLSAIM output by 11 /
lypinator	0:bb348c97df44	1319	#define LL_RCC_PLLSAIM_DIV_12 LL_RCC_PLLM_DIV_12 /!< PLLSAI division factor for PLLSAIM output by 12 /
lypinator	0:bb348c97df44	1320	#define LL_RCC_PLLSAIM_DIV_13 LL_RCC_PLLM_DIV_13 /!< PLLSAI division factor for PLLSAIM output by 13 /
lypinator	0:bb348c97df44	1321	#define LL_RCC_PLLSAIM_DIV_14 LL_RCC_PLLM_DIV_14 /!< PLLSAI division factor for PLLSAIM output by 14 /
lypinator	0:bb348c97df44	1322	#define LL_RCC_PLLSAIM_DIV_15 LL_RCC_PLLM_DIV_15 /!< PLLSAI division factor for PLLSAIM output by 15 /
lypinator	0:bb348c97df44	1323	#define LL_RCC_PLLSAIM_DIV_16 LL_RCC_PLLM_DIV_16 /!< PLLSAI division factor for PLLSAIM output by 16 /
lypinator	0:bb348c97df44	1324	#define LL_RCC_PLLSAIM_DIV_17 LL_RCC_PLLM_DIV_17 /!< PLLSAI division factor for PLLSAIM output by 17 /
lypinator	0:bb348c97df44	1325	#define LL_RCC_PLLSAIM_DIV_18 LL_RCC_PLLM_DIV_18 /!< PLLSAI division factor for PLLSAIM output by 18 /
lypinator	0:bb348c97df44	1326	#define LL_RCC_PLLSAIM_DIV_19 LL_RCC_PLLM_DIV_19 /!< PLLSAI division factor for PLLSAIM output by 19 /
lypinator	0:bb348c97df44	1327	#define LL_RCC_PLLSAIM_DIV_20 LL_RCC_PLLM_DIV_20 /!< PLLSAI division factor for PLLSAIM output by 20 /
lypinator	0:bb348c97df44	1328	#define LL_RCC_PLLSAIM_DIV_21 LL_RCC_PLLM_DIV_21 /!< PLLSAI division factor for PLLSAIM output by 21 /
lypinator	0:bb348c97df44	1329	#define LL_RCC_PLLSAIM_DIV_22 LL_RCC_PLLM_DIV_22 /!< PLLSAI division factor for PLLSAIM output by 22 /
lypinator	0:bb348c97df44	1330	#define LL_RCC_PLLSAIM_DIV_23 LL_RCC_PLLM_DIV_23 /!< PLLSAI division factor for PLLSAIM output by 23 /
lypinator	0:bb348c97df44	1331	#define LL_RCC_PLLSAIM_DIV_24 LL_RCC_PLLM_DIV_24 /!< PLLSAI division factor for PLLSAIM output by 24 /
lypinator	0:bb348c97df44	1332	#define LL_RCC_PLLSAIM_DIV_25 LL_RCC_PLLM_DIV_25 /!< PLLSAI division factor for PLLSAIM output by 25 /
lypinator	0:bb348c97df44	1333	#define LL_RCC_PLLSAIM_DIV_26 LL_RCC_PLLM_DIV_26 /!< PLLSAI division factor for PLLSAIM output by 26 /
lypinator	0:bb348c97df44	1334	#define LL_RCC_PLLSAIM_DIV_27 LL_RCC_PLLM_DIV_27 /!< PLLSAI division factor for PLLSAIM output by 27 /
lypinator	0:bb348c97df44	1335	#define LL_RCC_PLLSAIM_DIV_28 LL_RCC_PLLM_DIV_28 /!< PLLSAI division factor for PLLSAIM output by 28 /
lypinator	0:bb348c97df44	1336	#define LL_RCC_PLLSAIM_DIV_29 LL_RCC_PLLM_DIV_29 /!< PLLSAI division factor for PLLSAIM output by 29 /
lypinator	0:bb348c97df44	1337	#define LL_RCC_PLLSAIM_DIV_30 LL_RCC_PLLM_DIV_30 /!< PLLSAI division factor for PLLSAIM output by 30 /
lypinator	0:bb348c97df44	1338	#define LL_RCC_PLLSAIM_DIV_31 LL_RCC_PLLM_DIV_31 /!< PLLSAI division factor for PLLSAIM output by 31 /
lypinator	0:bb348c97df44	1339	#define LL_RCC_PLLSAIM_DIV_32 LL_RCC_PLLM_DIV_32 /!< PLLSAI division factor for PLLSAIM output by 32 /
lypinator	0:bb348c97df44	1340	#define LL_RCC_PLLSAIM_DIV_33 LL_RCC_PLLM_DIV_33 /!< PLLSAI division factor for PLLSAIM output by 33 /
lypinator	0:bb348c97df44	1341	#define LL_RCC_PLLSAIM_DIV_34 LL_RCC_PLLM_DIV_34 /!< PLLSAI division factor for PLLSAIM output by 34 /
lypinator	0:bb348c97df44	1342	#define LL_RCC_PLLSAIM_DIV_35 LL_RCC_PLLM_DIV_35 /!< PLLSAI division factor for PLLSAIM output by 35 /
lypinator	0:bb348c97df44	1343	#define LL_RCC_PLLSAIM_DIV_36 LL_RCC_PLLM_DIV_36 /!< PLLSAI division factor for PLLSAIM output by 36 /
lypinator	0:bb348c97df44	1344	#define LL_RCC_PLLSAIM_DIV_37 LL_RCC_PLLM_DIV_37 /!< PLLSAI division factor for PLLSAIM output by 37 /
lypinator	0:bb348c97df44	1345	#define LL_RCC_PLLSAIM_DIV_38 LL_RCC_PLLM_DIV_38 /!< PLLSAI division factor for PLLSAIM output by 38 /
lypinator	0:bb348c97df44	1346	#define LL_RCC_PLLSAIM_DIV_39 LL_RCC_PLLM_DIV_39 /!< PLLSAI division factor for PLLSAIM output by 39 /
lypinator	0:bb348c97df44	1347	#define LL_RCC_PLLSAIM_DIV_40 LL_RCC_PLLM_DIV_40 /!< PLLSAI division factor for PLLSAIM output by 40 /
lypinator	0:bb348c97df44	1348	#define LL_RCC_PLLSAIM_DIV_41 LL_RCC_PLLM_DIV_41 /!< PLLSAI division factor for PLLSAIM output by 41 /
lypinator	0:bb348c97df44	1349	#define LL_RCC_PLLSAIM_DIV_42 LL_RCC_PLLM_DIV_42 /!< PLLSAI division factor for PLLSAIM output by 42 /
lypinator	0:bb348c97df44	1350	#define LL_RCC_PLLSAIM_DIV_43 LL_RCC_PLLM_DIV_43 /!< PLLSAI division factor for PLLSAIM output by 43 /
lypinator	0:bb348c97df44	1351	#define LL_RCC_PLLSAIM_DIV_44 LL_RCC_PLLM_DIV_44 /!< PLLSAI division factor for PLLSAIM output by 44 /
lypinator	0:bb348c97df44	1352	#define LL_RCC_PLLSAIM_DIV_45 LL_RCC_PLLM_DIV_45 /!< PLLSAI division factor for PLLSAIM output by 45 /
lypinator	0:bb348c97df44	1353	#define LL_RCC_PLLSAIM_DIV_46 LL_RCC_PLLM_DIV_46 /!< PLLSAI division factor for PLLSAIM output by 46 /
lypinator	0:bb348c97df44	1354	#define LL_RCC_PLLSAIM_DIV_47 LL_RCC_PLLM_DIV_47 /!< PLLSAI division factor for PLLSAIM output by 47 /
lypinator	0:bb348c97df44	1355	#define LL_RCC_PLLSAIM_DIV_48 LL_RCC_PLLM_DIV_48 /!< PLLSAI division factor for PLLSAIM output by 48 /
lypinator	0:bb348c97df44	1356	#define LL_RCC_PLLSAIM_DIV_49 LL_RCC_PLLM_DIV_49 /!< PLLSAI division factor for PLLSAIM output by 49 /
lypinator	0:bb348c97df44	1357	#define LL_RCC_PLLSAIM_DIV_50 LL_RCC_PLLM_DIV_50 /!< PLLSAI division factor for PLLSAIM output by 50 /
lypinator	0:bb348c97df44	1358	#define LL_RCC_PLLSAIM_DIV_51 LL_RCC_PLLM_DIV_51 /!< PLLSAI division factor for PLLSAIM output by 51 /
lypinator	0:bb348c97df44	1359	#define LL_RCC_PLLSAIM_DIV_52 LL_RCC_PLLM_DIV_52 /!< PLLSAI division factor for PLLSAIM output by 52 /
lypinator	0:bb348c97df44	1360	#define LL_RCC_PLLSAIM_DIV_53 LL_RCC_PLLM_DIV_53 /!< PLLSAI division factor for PLLSAIM output by 53 /
lypinator	0:bb348c97df44	1361	#define LL_RCC_PLLSAIM_DIV_54 LL_RCC_PLLM_DIV_54 /!< PLLSAI division factor for PLLSAIM output by 54 /
lypinator	0:bb348c97df44	1362	#define LL_RCC_PLLSAIM_DIV_55 LL_RCC_PLLM_DIV_55 /!< PLLSAI division factor for PLLSAIM output by 55 /
lypinator	0:bb348c97df44	1363	#define LL_RCC_PLLSAIM_DIV_56 LL_RCC_PLLM_DIV_56 /!< PLLSAI division factor for PLLSAIM output by 56 /
lypinator	0:bb348c97df44	1364	#define LL_RCC_PLLSAIM_DIV_57 LL_RCC_PLLM_DIV_57 /!< PLLSAI division factor for PLLSAIM output by 57 /
lypinator	0:bb348c97df44	1365	#define LL_RCC_PLLSAIM_DIV_58 LL_RCC_PLLM_DIV_58 /!< PLLSAI division factor for PLLSAIM output by 58 /
lypinator	0:bb348c97df44	1366	#define LL_RCC_PLLSAIM_DIV_59 LL_RCC_PLLM_DIV_59 /!< PLLSAI division factor for PLLSAIM output by 59 /
lypinator	0:bb348c97df44	1367	#define LL_RCC_PLLSAIM_DIV_60 LL_RCC_PLLM_DIV_60 /!< PLLSAI division factor for PLLSAIM output by 60 /
lypinator	0:bb348c97df44	1368	#define LL_RCC_PLLSAIM_DIV_61 LL_RCC_PLLM_DIV_61 /!< PLLSAI division factor for PLLSAIM output by 61 /
lypinator	0:bb348c97df44	1369	#define LL_RCC_PLLSAIM_DIV_62 LL_RCC_PLLM_DIV_62 /!< PLLSAI division factor for PLLSAIM output by 62 /
lypinator	0:bb348c97df44	1370	#define LL_RCC_PLLSAIM_DIV_63 LL_RCC_PLLM_DIV_63 /!< PLLSAI division factor for PLLSAIM output by 63 /
lypinator	0:bb348c97df44	1371	#endif /* RCC_PLLSAICFGR_PLLSAIM */
lypinator	0:bb348c97df44	1372	/**
lypinator	0:bb348c97df44	1373	* @}
lypinator	0:bb348c97df44	1374	*/
lypinator	0:bb348c97df44	1375
lypinator	0:bb348c97df44	1376	/** @defgroup RCC_LL_EC_PLLSAIQ PLLSAIQ division factor (PLLSAIQ)
lypinator	0:bb348c97df44	1377	* @{
lypinator	0:bb348c97df44	1378	*/
lypinator	0:bb348c97df44	1379	#define LL_RCC_PLLSAIQ_DIV_2 RCC_PLLSAICFGR_PLLSAIQ_1 /!< PLLSAI division factor for PLLSAIQ output by 2 /
lypinator	0:bb348c97df44	1380	#define LL_RCC_PLLSAIQ_DIV_3 (RCC_PLLSAICFGR_PLLSAIQ_1 \| RCC_PLLSAICFGR_PLLSAIQ_0) /!< PLLSAI division factor for PLLSAIQ output by 3 /
lypinator	0:bb348c97df44	1381	#define LL_RCC_PLLSAIQ_DIV_4 RCC_PLLSAICFGR_PLLSAIQ_2 /!< PLLSAI division factor for PLLSAIQ output by 4 /
lypinator	0:bb348c97df44	1382	#define LL_RCC_PLLSAIQ_DIV_5 (RCC_PLLSAICFGR_PLLSAIQ_2 \| RCC_PLLSAICFGR_PLLSAIQ_0) /!< PLLSAI division factor for PLLSAIQ output by 5 /
lypinator	0:bb348c97df44	1383	#define LL_RCC_PLLSAIQ_DIV_6 (RCC_PLLSAICFGR_PLLSAIQ_2 \| RCC_PLLSAICFGR_PLLSAIQ_1) /!< PLLSAI division factor for PLLSAIQ output by 6 /
lypinator	0:bb348c97df44	1384	#define LL_RCC_PLLSAIQ_DIV_7 (RCC_PLLSAICFGR_PLLSAIQ_2 \| RCC_PLLSAICFGR_PLLSAIQ_1 \| RCC_PLLSAICFGR_PLLSAIQ_0) /!< PLLSAI division factor for PLLSAIQ output by 7 /
lypinator	0:bb348c97df44	1385	#define LL_RCC_PLLSAIQ_DIV_8 RCC_PLLSAICFGR_PLLSAIQ_3 /!< PLLSAI division factor for PLLSAIQ output by 8 /
lypinator	0:bb348c97df44	1386	#define LL_RCC_PLLSAIQ_DIV_9 (RCC_PLLSAICFGR_PLLSAIQ_3 \| RCC_PLLSAICFGR_PLLSAIQ_0) /!< PLLSAI division factor for PLLSAIQ output by 9 /
lypinator	0:bb348c97df44	1387	#define LL_RCC_PLLSAIQ_DIV_10 (RCC_PLLSAICFGR_PLLSAIQ_3 \| RCC_PLLSAICFGR_PLLSAIQ_1) /!< PLLSAI division factor for PLLSAIQ output by 10 /
lypinator	0:bb348c97df44	1388	#define LL_RCC_PLLSAIQ_DIV_11 (RCC_PLLSAICFGR_PLLSAIQ_3 \| RCC_PLLSAICFGR_PLLSAIQ_1 \| RCC_PLLSAICFGR_PLLSAIQ_0) /!< PLLSAI division factor for PLLSAIQ output by 11 /
lypinator	0:bb348c97df44	1389	#define LL_RCC_PLLSAIQ_DIV_12 (RCC_PLLSAICFGR_PLLSAIQ_3 \| RCC_PLLSAICFGR_PLLSAIQ_2) /!< PLLSAI division factor for PLLSAIQ output by 12 /
lypinator	0:bb348c97df44	1390	#define LL_RCC_PLLSAIQ_DIV_13 (RCC_PLLSAICFGR_PLLSAIQ_3 \| RCC_PLLSAICFGR_PLLSAIQ_2 \| RCC_PLLSAICFGR_PLLSAIQ_0) /!< PLLSAI division factor for PLLSAIQ output by 13 /
lypinator	0:bb348c97df44	1391	#define LL_RCC_PLLSAIQ_DIV_14 (RCC_PLLSAICFGR_PLLSAIQ_3 \| RCC_PLLSAICFGR_PLLSAIQ_2 \| RCC_PLLSAICFGR_PLLSAIQ_1) /!< PLLSAI division factor for PLLSAIQ output by 14 /
lypinator	0:bb348c97df44	1392	#define LL_RCC_PLLSAIQ_DIV_15 (RCC_PLLSAICFGR_PLLSAIQ_3 \| RCC_PLLSAICFGR_PLLSAIQ_2 \| RCC_PLLSAICFGR_PLLSAIQ_1 \| RCC_PLLSAICFGR_PLLSAIQ_0) /!< PLLSAI division factor for PLLSAIQ output by 15 /
lypinator	0:bb348c97df44	1393	/**
lypinator	0:bb348c97df44	1394	* @}
lypinator	0:bb348c97df44	1395	*/
lypinator	0:bb348c97df44	1396
lypinator	0:bb348c97df44	1397	#if defined(RCC_DCKCFGR_PLLSAIDIVQ)
lypinator	0:bb348c97df44	1398	/** @defgroup RCC_LL_EC_PLLSAIDIVQ PLLSAIDIVQ division factor (PLLSAIDIVQ)
lypinator	0:bb348c97df44	1399	* @{
lypinator	0:bb348c97df44	1400	*/
lypinator	0:bb348c97df44	1401	#define LL_RCC_PLLSAIDIVQ_DIV_1 0x00000000U /!< PLLSAI division factor for PLLSAIDIVQ output by 1 /
lypinator	0:bb348c97df44	1402	#define LL_RCC_PLLSAIDIVQ_DIV_2 RCC_DCKCFGR_PLLSAIDIVQ_0 /!< PLLSAI division factor for PLLSAIDIVQ output by 2 /
lypinator	0:bb348c97df44	1403	#define LL_RCC_PLLSAIDIVQ_DIV_3 RCC_DCKCFGR_PLLSAIDIVQ_1 /!< PLLSAI division factor for PLLSAIDIVQ output by 3 /
lypinator	0:bb348c97df44	1404	#define LL_RCC_PLLSAIDIVQ_DIV_4 (RCC_DCKCFGR_PLLSAIDIVQ_1 \| RCC_DCKCFGR_PLLSAIDIVQ_0) /!< PLLSAI division factor for PLLSAIDIVQ output by 4 /
lypinator	0:bb348c97df44	1405	#define LL_RCC_PLLSAIDIVQ_DIV_5 RCC_DCKCFGR_PLLSAIDIVQ_2 /!< PLLSAI division factor for PLLSAIDIVQ output by 5 /
lypinator	0:bb348c97df44	1406	#define LL_RCC_PLLSAIDIVQ_DIV_6 (RCC_DCKCFGR_PLLSAIDIVQ_2 \| RCC_DCKCFGR_PLLSAIDIVQ_0) /!< PLLSAI division factor for PLLSAIDIVQ output by 6 /
lypinator	0:bb348c97df44	1407	#define LL_RCC_PLLSAIDIVQ_DIV_7 (RCC_DCKCFGR_PLLSAIDIVQ_2 \| RCC_DCKCFGR_PLLSAIDIVQ_1) /!< PLLSAI division factor for PLLSAIDIVQ output by 7 /
lypinator	0:bb348c97df44	1408	#define LL_RCC_PLLSAIDIVQ_DIV_8 (RCC_DCKCFGR_PLLSAIDIVQ_2 \| RCC_DCKCFGR_PLLSAIDIVQ_1 \| RCC_DCKCFGR_PLLSAIDIVQ_0) /!< PLLSAI division factor for PLLSAIDIVQ output by 8 /
lypinator	0:bb348c97df44	1409	#define LL_RCC_PLLSAIDIVQ_DIV_9 RCC_DCKCFGR_PLLSAIDIVQ_3 /!< PLLSAI division factor for PLLSAIDIVQ output by 9 /
lypinator	0:bb348c97df44	1410	#define LL_RCC_PLLSAIDIVQ_DIV_10 (RCC_DCKCFGR_PLLSAIDIVQ_3 \| RCC_DCKCFGR_PLLSAIDIVQ_0) /!< PLLSAI division factor for PLLSAIDIVQ output by 10 /
lypinator	0:bb348c97df44	1411	#define LL_RCC_PLLSAIDIVQ_DIV_11 (RCC_DCKCFGR_PLLSAIDIVQ_3 \| RCC_DCKCFGR_PLLSAIDIVQ_1) /!< PLLSAI division factor for PLLSAIDIVQ output by 11 /
lypinator	0:bb348c97df44	1412	#define LL_RCC_PLLSAIDIVQ_DIV_12 (RCC_DCKCFGR_PLLSAIDIVQ_3 \| RCC_DCKCFGR_PLLSAIDIVQ_1 \| RCC_DCKCFGR_PLLSAIDIVQ_0) /!< PLLSAI division factor for PLLSAIDIVQ output by 12 /
lypinator	0:bb348c97df44	1413	#define LL_RCC_PLLSAIDIVQ_DIV_13 (RCC_DCKCFGR_PLLSAIDIVQ_3 \| RCC_DCKCFGR_PLLSAIDIVQ_2) /!< PLLSAI division factor for PLLSAIDIVQ output by 13 /
lypinator	0:bb348c97df44	1414	#define LL_RCC_PLLSAIDIVQ_DIV_14 (RCC_DCKCFGR_PLLSAIDIVQ_3 \| RCC_DCKCFGR_PLLSAIDIVQ_2 \| RCC_DCKCFGR_PLLSAIDIVQ_0) /!< PLLSAI division factor for PLLSAIDIVQ output by 14 /
lypinator	0:bb348c97df44	1415	#define LL_RCC_PLLSAIDIVQ_DIV_15 (RCC_DCKCFGR_PLLSAIDIVQ_3 \| RCC_DCKCFGR_PLLSAIDIVQ_2 \| RCC_DCKCFGR_PLLSAIDIVQ_1) /!< PLLSAI division factor for PLLSAIDIVQ output by 15 /
lypinator	0:bb348c97df44	1416	#define LL_RCC_PLLSAIDIVQ_DIV_16 (RCC_DCKCFGR_PLLSAIDIVQ_3 \| RCC_DCKCFGR_PLLSAIDIVQ_2 \| RCC_DCKCFGR_PLLSAIDIVQ_1 \| RCC_DCKCFGR_PLLSAIDIVQ_0) /!< PLLSAI division factor for PLLSAIDIVQ output by 16 /
lypinator	0:bb348c97df44	1417	#define LL_RCC_PLLSAIDIVQ_DIV_17 RCC_DCKCFGR_PLLSAIDIVQ_4 /!< PLLSAI division factor for PLLSAIDIVQ output by 17 /
lypinator	0:bb348c97df44	1418	#define LL_RCC_PLLSAIDIVQ_DIV_18 (RCC_DCKCFGR_PLLSAIDIVQ_4 \| RCC_DCKCFGR_PLLSAIDIVQ_0) /!< PLLSAI division factor for PLLSAIDIVQ output by 18 /
lypinator	0:bb348c97df44	1419	#define LL_RCC_PLLSAIDIVQ_DIV_19 (RCC_DCKCFGR_PLLSAIDIVQ_4 \| RCC_DCKCFGR_PLLSAIDIVQ_1) /!< PLLSAI division factor for PLLSAIDIVQ output by 19 /
lypinator	0:bb348c97df44	1420	#define LL_RCC_PLLSAIDIVQ_DIV_20 (RCC_DCKCFGR_PLLSAIDIVQ_4 \| RCC_DCKCFGR_PLLSAIDIVQ_1 \| RCC_DCKCFGR_PLLSAIDIVQ_0) /!< PLLSAI division factor for PLLSAIDIVQ output by 20 /
lypinator	0:bb348c97df44	1421	#define LL_RCC_PLLSAIDIVQ_DIV_21 (RCC_DCKCFGR_PLLSAIDIVQ_4 \| RCC_DCKCFGR_PLLSAIDIVQ_2) /!< PLLSAI division factor for PLLSAIDIVQ output by 21 /
lypinator	0:bb348c97df44	1422	#define LL_RCC_PLLSAIDIVQ_DIV_22 (RCC_DCKCFGR_PLLSAIDIVQ_4 \| RCC_DCKCFGR_PLLSAIDIVQ_2 \| RCC_DCKCFGR_PLLSAIDIVQ_0) /!< PLLSAI division factor for PLLSAIDIVQ output by 22 /
lypinator	0:bb348c97df44	1423	#define LL_RCC_PLLSAIDIVQ_DIV_23 (RCC_DCKCFGR_PLLSAIDIVQ_4 \| RCC_DCKCFGR_PLLSAIDIVQ_2 \| RCC_DCKCFGR_PLLSAIDIVQ_1) /!< PLLSAI division factor for PLLSAIDIVQ output by 23 /
lypinator	0:bb348c97df44	1424	#define LL_RCC_PLLSAIDIVQ_DIV_24 (RCC_DCKCFGR_PLLSAIDIVQ_4 \| RCC_DCKCFGR_PLLSAIDIVQ_2 \| RCC_DCKCFGR_PLLSAIDIVQ_1 \| RCC_DCKCFGR_PLLSAIDIVQ_0) /!< PLLSAI division factor for PLLSAIDIVQ output by 24 /
lypinator	0:bb348c97df44	1425	#define LL_RCC_PLLSAIDIVQ_DIV_25 (RCC_DCKCFGR_PLLSAIDIVQ_4 \| RCC_DCKCFGR_PLLSAIDIVQ_3) /!< PLLSAI division factor for PLLSAIDIVQ output by 25 /
lypinator	0:bb348c97df44	1426	#define LL_RCC_PLLSAIDIVQ_DIV_26 (RCC_DCKCFGR_PLLSAIDIVQ_4 \| RCC_DCKCFGR_PLLSAIDIVQ_3 \| RCC_DCKCFGR_PLLSAIDIVQ_0) /!< PLLSAI division factor for PLLSAIDIVQ output by 26 /
lypinator	0:bb348c97df44	1427	#define LL_RCC_PLLSAIDIVQ_DIV_27 (RCC_DCKCFGR_PLLSAIDIVQ_4 \| RCC_DCKCFGR_PLLSAIDIVQ_3 \| RCC_DCKCFGR_PLLSAIDIVQ_1) /!< PLLSAI division factor for PLLSAIDIVQ output by 27 /
lypinator	0:bb348c97df44	1428	#define LL_RCC_PLLSAIDIVQ_DIV_28 (RCC_DCKCFGR_PLLSAIDIVQ_4 \| RCC_DCKCFGR_PLLSAIDIVQ_3 \| RCC_DCKCFGR_PLLSAIDIVQ_1 \| RCC_DCKCFGR_PLLSAIDIVQ_0) /!< PLLSAI division factor for PLLSAIDIVQ output by 28 /
lypinator	0:bb348c97df44	1429	#define LL_RCC_PLLSAIDIVQ_DIV_29 (RCC_DCKCFGR_PLLSAIDIVQ_4 \| RCC_DCKCFGR_PLLSAIDIVQ_3 \| RCC_DCKCFGR_PLLSAIDIVQ_2) /!< PLLSAI division factor for PLLSAIDIVQ output by 29 /
lypinator	0:bb348c97df44	1430	#define LL_RCC_PLLSAIDIVQ_DIV_30 (RCC_DCKCFGR_PLLSAIDIVQ_4 \| RCC_DCKCFGR_PLLSAIDIVQ_3 \| RCC_DCKCFGR_PLLSAIDIVQ_2 \| RCC_DCKCFGR_PLLSAIDIVQ_0) /!< PLLSAI division factor for PLLSAIDIVQ output by 30 /
lypinator	0:bb348c97df44	1431	#define LL_RCC_PLLSAIDIVQ_DIV_31 (RCC_DCKCFGR_PLLSAIDIVQ_4 \| RCC_DCKCFGR_PLLSAIDIVQ_3 \| RCC_DCKCFGR_PLLSAIDIVQ_2 \| RCC_DCKCFGR_PLLSAIDIVQ_1) /!< PLLSAI division factor for PLLSAIDIVQ output by 31 /
lypinator	0:bb348c97df44	1432	#define LL_RCC_PLLSAIDIVQ_DIV_32 (RCC_DCKCFGR_PLLSAIDIVQ_4 \| RCC_DCKCFGR_PLLSAIDIVQ_3 \| RCC_DCKCFGR_PLLSAIDIVQ_2 \| RCC_DCKCFGR_PLLSAIDIVQ_1 \| RCC_DCKCFGR_PLLSAIDIVQ_0) /!< PLLSAI division factor for PLLSAIDIVQ output by 32 /
lypinator	0:bb348c97df44	1433	/**
lypinator	0:bb348c97df44	1434	* @}
lypinator	0:bb348c97df44	1435	*/
lypinator	0:bb348c97df44	1436	#endif /* RCC_DCKCFGR_PLLSAIDIVQ */
lypinator	0:bb348c97df44	1437
lypinator	0:bb348c97df44	1438	#if defined(RCC_PLLSAICFGR_PLLSAIR)
lypinator	0:bb348c97df44	1439	/** @defgroup RCC_LL_EC_PLLSAIR PLLSAIR division factor (PLLSAIR)
lypinator	0:bb348c97df44	1440	* @{
lypinator	0:bb348c97df44	1441	*/
lypinator	0:bb348c97df44	1442	#define LL_RCC_PLLSAIR_DIV_2 RCC_PLLSAICFGR_PLLSAIR_1 /!< PLLSAI division factor for PLLSAIR output by 2 /
lypinator	0:bb348c97df44	1443	#define LL_RCC_PLLSAIR_DIV_3 (RCC_PLLSAICFGR_PLLSAIR_1 \| RCC_PLLSAICFGR_PLLSAIR_0) /!< PLLSAI division factor for PLLSAIR output by 3 /
lypinator	0:bb348c97df44	1444	#define LL_RCC_PLLSAIR_DIV_4 RCC_PLLSAICFGR_PLLSAIR_2 /!< PLLSAI division factor for PLLSAIR output by 4 /
lypinator	0:bb348c97df44	1445	#define LL_RCC_PLLSAIR_DIV_5 (RCC_PLLSAICFGR_PLLSAIR_2 \| RCC_PLLSAICFGR_PLLSAIR_0) /!< PLLSAI division factor for PLLSAIR output by 5 /
lypinator	0:bb348c97df44	1446	#define LL_RCC_PLLSAIR_DIV_6 (RCC_PLLSAICFGR_PLLSAIR_2 \| RCC_PLLSAICFGR_PLLSAIR_1) /!< PLLSAI division factor for PLLSAIR output by 6 /
lypinator	0:bb348c97df44	1447	#define LL_RCC_PLLSAIR_DIV_7 (RCC_PLLSAICFGR_PLLSAIR_2 \| RCC_PLLSAICFGR_PLLSAIR_1 \| RCC_PLLSAICFGR_PLLSAIR_0) /!< PLLSAI division factor for PLLSAIR output by 7 /
lypinator	0:bb348c97df44	1448	/**
lypinator	0:bb348c97df44	1449	* @}
lypinator	0:bb348c97df44	1450	*/
lypinator	0:bb348c97df44	1451	#endif /* RCC_PLLSAICFGR_PLLSAIR */
lypinator	0:bb348c97df44	1452
lypinator	0:bb348c97df44	1453	#if defined(RCC_DCKCFGR_PLLSAIDIVR)
lypinator	0:bb348c97df44	1454	/** @defgroup RCC_LL_EC_PLLSAIDIVR PLLSAIDIVR division factor (PLLSAIDIVR)
lypinator	0:bb348c97df44	1455	* @{
lypinator	0:bb348c97df44	1456	*/
lypinator	0:bb348c97df44	1457	#define LL_RCC_PLLSAIDIVR_DIV_2 0x00000000U /!< PLLSAI division factor for PLLSAIDIVR output by 2 /
lypinator	0:bb348c97df44	1458	#define LL_RCC_PLLSAIDIVR_DIV_4 RCC_DCKCFGR_PLLSAIDIVR_0 /!< PLLSAI division factor for PLLSAIDIVR output by 4 /
lypinator	0:bb348c97df44	1459	#define LL_RCC_PLLSAIDIVR_DIV_8 RCC_DCKCFGR_PLLSAIDIVR_1 /!< PLLSAI division factor for PLLSAIDIVR output by 8 /
lypinator	0:bb348c97df44	1460	#define LL_RCC_PLLSAIDIVR_DIV_16 (RCC_DCKCFGR_PLLSAIDIVR_1 \| RCC_DCKCFGR_PLLSAIDIVR_0) /!< PLLSAI division factor for PLLSAIDIVR output by 16 /
lypinator	0:bb348c97df44	1461	/**
lypinator	0:bb348c97df44	1462	* @}
lypinator	0:bb348c97df44	1463	*/
lypinator	0:bb348c97df44	1464	#endif /* RCC_DCKCFGR_PLLSAIDIVR */
lypinator	0:bb348c97df44	1465
lypinator	0:bb348c97df44	1466	#if defined(RCC_PLLSAICFGR_PLLSAIP)
lypinator	0:bb348c97df44	1467	/** @defgroup RCC_LL_EC_PLLSAIP PLLSAIP division factor (PLLSAIP)
lypinator	0:bb348c97df44	1468	* @{
lypinator	0:bb348c97df44	1469	*/
lypinator	0:bb348c97df44	1470	#define LL_RCC_PLLSAIP_DIV_2 0x00000000U /!< PLLSAI division factor for PLLSAIP output by 2 /
lypinator	0:bb348c97df44	1471	#define LL_RCC_PLLSAIP_DIV_4 RCC_PLLSAICFGR_PLLSAIP_0 /!< PLLSAI division factor for PLLSAIP output by 4 /
lypinator	0:bb348c97df44	1472	#define LL_RCC_PLLSAIP_DIV_6 RCC_PLLSAICFGR_PLLSAIP_1 /!< PLLSAI division factor for PLLSAIP output by 6 /
lypinator	0:bb348c97df44	1473	#define LL_RCC_PLLSAIP_DIV_8 (RCC_PLLSAICFGR_PLLSAIP_1 \| RCC_PLLSAICFGR_PLLSAIP_0) /!< PLLSAI division factor for PLLSAIP output by 8 /
lypinator	0:bb348c97df44	1474	/**
lypinator	0:bb348c97df44	1475	* @}
lypinator	0:bb348c97df44	1476	*/
lypinator	0:bb348c97df44	1477	#endif /* RCC_PLLSAICFGR_PLLSAIP */
lypinator	0:bb348c97df44	1478	#endif /* RCC_PLLSAI_SUPPORT */
lypinator	0:bb348c97df44	1479	/**
lypinator	0:bb348c97df44	1480	* @}
lypinator	0:bb348c97df44	1481	*/
lypinator	0:bb348c97df44	1482
lypinator	0:bb348c97df44	1483	/* Exported macro ------------------------------------------------------------*/
lypinator	0:bb348c97df44	1484	/** @defgroup RCC_LL_Exported_Macros RCC Exported Macros
lypinator	0:bb348c97df44	1485	* @{
lypinator	0:bb348c97df44	1486	*/
lypinator	0:bb348c97df44	1487
lypinator	0:bb348c97df44	1488	/** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
lypinator	0:bb348c97df44	1489	* @{
lypinator	0:bb348c97df44	1490	*/
lypinator	0:bb348c97df44	1491
lypinator	0:bb348c97df44	1492	/**
lypinator	0:bb348c97df44	1493	* @brief Write a value in RCC register
lypinator	0:bb348c97df44	1494	* @param __REG__ Register to be written
lypinator	0:bb348c97df44	1495	* @param __VALUE__ Value to be written in the register
lypinator	0:bb348c97df44	1496	* @retval None
lypinator	0:bb348c97df44	1497	*/
lypinator	0:bb348c97df44	1498	#define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
lypinator	0:bb348c97df44	1499
lypinator	0:bb348c97df44	1500	/**
lypinator	0:bb348c97df44	1501	* @brief Read a value in RCC register
lypinator	0:bb348c97df44	1502	* @param __REG__ Register to be read
lypinator	0:bb348c97df44	1503	* @retval Register value
lypinator	0:bb348c97df44	1504	*/
lypinator	0:bb348c97df44	1505	#define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
lypinator	0:bb348c97df44	1506	/**
lypinator	0:bb348c97df44	1507	* @}
lypinator	0:bb348c97df44	1508	*/
lypinator	0:bb348c97df44	1509
lypinator	0:bb348c97df44	1510	/** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies
lypinator	0:bb348c97df44	1511	* @{
lypinator	0:bb348c97df44	1512	*/
lypinator	0:bb348c97df44	1513
lypinator	0:bb348c97df44	1514	/**
lypinator	0:bb348c97df44	1515	* @brief Helper macro to calculate the PLLCLK frequency on system domain
lypinator	0:bb348c97df44	1516	* @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
lypinator	0:bb348c97df44	1517	* @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ());
lypinator	0:bb348c97df44	1518	* @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
lypinator	0:bb348c97df44	1519	* @param __PLLM__ This parameter can be one of the following values:
lypinator	0:bb348c97df44	1520	* @arg @ref LL_RCC_PLLM_DIV_2
lypinator	0:bb348c97df44	1521	* @arg @ref LL_RCC_PLLM_DIV_3
lypinator	0:bb348c97df44	1522	* @arg @ref LL_RCC_PLLM_DIV_4
lypinator	0:bb348c97df44	1523	* @arg @ref LL_RCC_PLLM_DIV_5
lypinator	0:bb348c97df44	1524	* @arg @ref LL_RCC_PLLM_DIV_6
lypinator	0:bb348c97df44	1525	* @arg @ref LL_RCC_PLLM_DIV_7
lypinator	0:bb348c97df44	1526	* @arg @ref LL_RCC_PLLM_DIV_8
lypinator	0:bb348c97df44	1527	* @arg @ref LL_RCC_PLLM_DIV_9
lypinator	0:bb348c97df44	1528	* @arg @ref LL_RCC_PLLM_DIV_10
lypinator	0:bb348c97df44	1529	* @arg @ref LL_RCC_PLLM_DIV_11
lypinator	0:bb348c97df44	1530	* @arg @ref LL_RCC_PLLM_DIV_12
lypinator	0:bb348c97df44	1531	* @arg @ref LL_RCC_PLLM_DIV_13
lypinator	0:bb348c97df44	1532	* @arg @ref LL_RCC_PLLM_DIV_14
lypinator	0:bb348c97df44	1533	* @arg @ref LL_RCC_PLLM_DIV_15
lypinator	0:bb348c97df44	1534	* @arg @ref LL_RCC_PLLM_DIV_16
lypinator	0:bb348c97df44	1535	* @arg @ref LL_RCC_PLLM_DIV_17
lypinator	0:bb348c97df44	1536	* @arg @ref LL_RCC_PLLM_DIV_18
lypinator	0:bb348c97df44	1537	* @arg @ref LL_RCC_PLLM_DIV_19
lypinator	0:bb348c97df44	1538	* @arg @ref LL_RCC_PLLM_DIV_20
lypinator	0:bb348c97df44	1539	* @arg @ref LL_RCC_PLLM_DIV_21
lypinator	0:bb348c97df44	1540	* @arg @ref LL_RCC_PLLM_DIV_22
lypinator	0:bb348c97df44	1541	* @arg @ref LL_RCC_PLLM_DIV_23
lypinator	0:bb348c97df44	1542	* @arg @ref LL_RCC_PLLM_DIV_24
lypinator	0:bb348c97df44	1543	* @arg @ref LL_RCC_PLLM_DIV_25
lypinator	0:bb348c97df44	1544	* @arg @ref LL_RCC_PLLM_DIV_26
lypinator	0:bb348c97df44	1545	* @arg @ref LL_RCC_PLLM_DIV_27
lypinator	0:bb348c97df44	1546	* @arg @ref LL_RCC_PLLM_DIV_28
lypinator	0:bb348c97df44	1547	* @arg @ref LL_RCC_PLLM_DIV_29
lypinator	0:bb348c97df44	1548	* @arg @ref LL_RCC_PLLM_DIV_30
lypinator	0:bb348c97df44	1549	* @arg @ref LL_RCC_PLLM_DIV_31
lypinator	0:bb348c97df44	1550	* @arg @ref LL_RCC_PLLM_DIV_32
lypinator	0:bb348c97df44	1551	* @arg @ref LL_RCC_PLLM_DIV_33
lypinator	0:bb348c97df44	1552	* @arg @ref LL_RCC_PLLM_DIV_34
lypinator	0:bb348c97df44	1553	* @arg @ref LL_RCC_PLLM_DIV_35
lypinator	0:bb348c97df44	1554	* @arg @ref LL_RCC_PLLM_DIV_36
lypinator	0:bb348c97df44	1555	* @arg @ref LL_RCC_PLLM_DIV_37
lypinator	0:bb348c97df44	1556	* @arg @ref LL_RCC_PLLM_DIV_38
lypinator	0:bb348c97df44	1557	* @arg @ref LL_RCC_PLLM_DIV_39
lypinator	0:bb348c97df44	1558	* @arg @ref LL_RCC_PLLM_DIV_40
lypinator	0:bb348c97df44	1559	* @arg @ref LL_RCC_PLLM_DIV_41
lypinator	0:bb348c97df44	1560	* @arg @ref LL_RCC_PLLM_DIV_42
lypinator	0:bb348c97df44	1561	* @arg @ref LL_RCC_PLLM_DIV_43
lypinator	0:bb348c97df44	1562	* @arg @ref LL_RCC_PLLM_DIV_44
lypinator	0:bb348c97df44	1563	* @arg @ref LL_RCC_PLLM_DIV_45
lypinator	0:bb348c97df44	1564	* @arg @ref LL_RCC_PLLM_DIV_46
lypinator	0:bb348c97df44	1565	* @arg @ref LL_RCC_PLLM_DIV_47
lypinator	0:bb348c97df44	1566	* @arg @ref LL_RCC_PLLM_DIV_48
lypinator	0:bb348c97df44	1567	* @arg @ref LL_RCC_PLLM_DIV_49
lypinator	0:bb348c97df44	1568	* @arg @ref LL_RCC_PLLM_DIV_50
lypinator	0:bb348c97df44	1569	* @arg @ref LL_RCC_PLLM_DIV_51
lypinator	0:bb348c97df44	1570	* @arg @ref LL_RCC_PLLM_DIV_52
lypinator	0:bb348c97df44	1571	* @arg @ref LL_RCC_PLLM_DIV_53
lypinator	0:bb348c97df44	1572	* @arg @ref LL_RCC_PLLM_DIV_54
lypinator	0:bb348c97df44	1573	* @arg @ref LL_RCC_PLLM_DIV_55
lypinator	0:bb348c97df44	1574	* @arg @ref LL_RCC_PLLM_DIV_56
lypinator	0:bb348c97df44	1575	* @arg @ref LL_RCC_PLLM_DIV_57
lypinator	0:bb348c97df44	1576	* @arg @ref LL_RCC_PLLM_DIV_58
lypinator	0:bb348c97df44	1577	* @arg @ref LL_RCC_PLLM_DIV_59
lypinator	0:bb348c97df44	1578	* @arg @ref LL_RCC_PLLM_DIV_60
lypinator	0:bb348c97df44	1579	* @arg @ref LL_RCC_PLLM_DIV_61
lypinator	0:bb348c97df44	1580	* @arg @ref LL_RCC_PLLM_DIV_62
lypinator	0:bb348c97df44	1581	* @arg @ref LL_RCC_PLLM_DIV_63
lypinator	0:bb348c97df44	1582	* @param __PLLN__ Between 50/192(*) and 432
lypinator	0:bb348c97df44	1583	*
lypinator	0:bb348c97df44	1584	* (*) value not defined in all devices.
lypinator	0:bb348c97df44	1585	* @param __PLLP__ This parameter can be one of the following values:
lypinator	0:bb348c97df44	1586	* @arg @ref LL_RCC_PLLP_DIV_2
lypinator	0:bb348c97df44	1587	* @arg @ref LL_RCC_PLLP_DIV_4
lypinator	0:bb348c97df44	1588	* @arg @ref LL_RCC_PLLP_DIV_6
lypinator	0:bb348c97df44	1589	* @arg @ref LL_RCC_PLLP_DIV_8
lypinator	0:bb348c97df44	1590	* @retval PLL clock frequency (in Hz)
lypinator	0:bb348c97df44	1591	*/
lypinator	0:bb348c97df44	1592	#define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
lypinator	0:bb348c97df44	1593	((((__PLLP__) >> RCC_PLLCFGR_PLLP_Pos ) + 1U) * 2U))
lypinator	0:bb348c97df44	1594
lypinator	0:bb348c97df44	1595	#if defined(RCC_PLLR_SYSCLK_SUPPORT)
lypinator	0:bb348c97df44	1596	/**
lypinator	0:bb348c97df44	1597	* @brief Helper macro to calculate the PLLRCLK frequency on system domain
lypinator	0:bb348c97df44	1598	* @note ex: @ref __LL_RCC_CALC_PLLRCLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
lypinator	0:bb348c97df44	1599	* @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ());
lypinator	0:bb348c97df44	1600	* @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
lypinator	0:bb348c97df44	1601	* @param __PLLM__ This parameter can be one of the following values:
lypinator	0:bb348c97df44	1602	* @arg @ref LL_RCC_PLLM_DIV_2
lypinator	0:bb348c97df44	1603	* @arg @ref LL_RCC_PLLM_DIV_3
lypinator	0:bb348c97df44	1604	* @arg @ref LL_RCC_PLLM_DIV_4
lypinator	0:bb348c97df44	1605	* @arg @ref LL_RCC_PLLM_DIV_5
lypinator	0:bb348c97df44	1606	* @arg @ref LL_RCC_PLLM_DIV_6
lypinator	0:bb348c97df44	1607	* @arg @ref LL_RCC_PLLM_DIV_7
lypinator	0:bb348c97df44	1608	* @arg @ref LL_RCC_PLLM_DIV_8
lypinator	0:bb348c97df44	1609	* @arg @ref LL_RCC_PLLM_DIV_9
lypinator	0:bb348c97df44	1610	* @arg @ref LL_RCC_PLLM_DIV_10
lypinator	0:bb348c97df44	1611	* @arg @ref LL_RCC_PLLM_DIV_11
lypinator	0:bb348c97df44	1612	* @arg @ref LL_RCC_PLLM_DIV_12
lypinator	0:bb348c97df44	1613	* @arg @ref LL_RCC_PLLM_DIV_13
lypinator	0:bb348c97df44	1614	* @arg @ref LL_RCC_PLLM_DIV_14
lypinator	0:bb348c97df44	1615	* @arg @ref LL_RCC_PLLM_DIV_15
lypinator	0:bb348c97df44	1616	* @arg @ref LL_RCC_PLLM_DIV_16
lypinator	0:bb348c97df44	1617	* @arg @ref LL_RCC_PLLM_DIV_17
lypinator	0:bb348c97df44	1618	* @arg @ref LL_RCC_PLLM_DIV_18
lypinator	0:bb348c97df44	1619	* @arg @ref LL_RCC_PLLM_DIV_19
lypinator	0:bb348c97df44	1620	* @arg @ref LL_RCC_PLLM_DIV_20
lypinator	0:bb348c97df44	1621	* @arg @ref LL_RCC_PLLM_DIV_21
lypinator	0:bb348c97df44	1622	* @arg @ref LL_RCC_PLLM_DIV_22
lypinator	0:bb348c97df44	1623	* @arg @ref LL_RCC_PLLM_DIV_23
lypinator	0:bb348c97df44	1624	* @arg @ref LL_RCC_PLLM_DIV_24
lypinator	0:bb348c97df44	1625	* @arg @ref LL_RCC_PLLM_DIV_25
lypinator	0:bb348c97df44	1626	* @arg @ref LL_RCC_PLLM_DIV_26
lypinator	0:bb348c97df44	1627	* @arg @ref LL_RCC_PLLM_DIV_27
lypinator	0:bb348c97df44	1628	* @arg @ref LL_RCC_PLLM_DIV_28
lypinator	0:bb348c97df44	1629	* @arg @ref LL_RCC_PLLM_DIV_29
lypinator	0:bb348c97df44	1630	* @arg @ref LL_RCC_PLLM_DIV_30
lypinator	0:bb348c97df44	1631	* @arg @ref LL_RCC_PLLM_DIV_31
lypinator	0:bb348c97df44	1632	* @arg @ref LL_RCC_PLLM_DIV_32
lypinator	0:bb348c97df44	1633	* @arg @ref LL_RCC_PLLM_DIV_33
lypinator	0:bb348c97df44	1634	* @arg @ref LL_RCC_PLLM_DIV_34
lypinator	0:bb348c97df44	1635	* @arg @ref LL_RCC_PLLM_DIV_35
lypinator	0:bb348c97df44	1636	* @arg @ref LL_RCC_PLLM_DIV_36
lypinator	0:bb348c97df44	1637	* @arg @ref LL_RCC_PLLM_DIV_37
lypinator	0:bb348c97df44	1638	* @arg @ref LL_RCC_PLLM_DIV_38
lypinator	0:bb348c97df44	1639	* @arg @ref LL_RCC_PLLM_DIV_39
lypinator	0:bb348c97df44	1640	* @arg @ref LL_RCC_PLLM_DIV_40
lypinator	0:bb348c97df44	1641	* @arg @ref LL_RCC_PLLM_DIV_41
lypinator	0:bb348c97df44	1642	* @arg @ref LL_RCC_PLLM_DIV_42
lypinator	0:bb348c97df44	1643	* @arg @ref LL_RCC_PLLM_DIV_43
lypinator	0:bb348c97df44	1644	* @arg @ref LL_RCC_PLLM_DIV_44
lypinator	0:bb348c97df44	1645	* @arg @ref LL_RCC_PLLM_DIV_45
lypinator	0:bb348c97df44	1646	* @arg @ref LL_RCC_PLLM_DIV_46
lypinator	0:bb348c97df44	1647	* @arg @ref LL_RCC_PLLM_DIV_47
lypinator	0:bb348c97df44	1648	* @arg @ref LL_RCC_PLLM_DIV_48
lypinator	0:bb348c97df44	1649	* @arg @ref LL_RCC_PLLM_DIV_49
lypinator	0:bb348c97df44	1650	* @arg @ref LL_RCC_PLLM_DIV_50
lypinator	0:bb348c97df44	1651	* @arg @ref LL_RCC_PLLM_DIV_51
lypinator	0:bb348c97df44	1652	* @arg @ref LL_RCC_PLLM_DIV_52
lypinator	0:bb348c97df44	1653	* @arg @ref LL_RCC_PLLM_DIV_53
lypinator	0:bb348c97df44	1654	* @arg @ref LL_RCC_PLLM_DIV_54
lypinator	0:bb348c97df44	1655	* @arg @ref LL_RCC_PLLM_DIV_55
lypinator	0:bb348c97df44	1656	* @arg @ref LL_RCC_PLLM_DIV_56
lypinator	0:bb348c97df44	1657	* @arg @ref LL_RCC_PLLM_DIV_57
lypinator	0:bb348c97df44	1658	* @arg @ref LL_RCC_PLLM_DIV_58
lypinator	0:bb348c97df44	1659	* @arg @ref LL_RCC_PLLM_DIV_59
lypinator	0:bb348c97df44	1660	* @arg @ref LL_RCC_PLLM_DIV_60
lypinator	0:bb348c97df44	1661	* @arg @ref LL_RCC_PLLM_DIV_61
lypinator	0:bb348c97df44	1662	* @arg @ref LL_RCC_PLLM_DIV_62
lypinator	0:bb348c97df44	1663	* @arg @ref LL_RCC_PLLM_DIV_63
lypinator	0:bb348c97df44	1664	* @param __PLLN__ Between 50 and 432
lypinator	0:bb348c97df44	1665	* @param __PLLR__ This parameter can be one of the following values:
lypinator	0:bb348c97df44	1666	* @arg @ref LL_RCC_PLLR_DIV_2
lypinator	0:bb348c97df44	1667	* @arg @ref LL_RCC_PLLR_DIV_3
lypinator	0:bb348c97df44	1668	* @arg @ref LL_RCC_PLLR_DIV_4
lypinator	0:bb348c97df44	1669	* @arg @ref LL_RCC_PLLR_DIV_5
lypinator	0:bb348c97df44	1670	* @arg @ref LL_RCC_PLLR_DIV_6
lypinator	0:bb348c97df44	1671	* @arg @ref LL_RCC_PLLR_DIV_7
lypinator	0:bb348c97df44	1672	* @retval PLL clock frequency (in Hz)
lypinator	0:bb348c97df44	1673	*/
lypinator	0:bb348c97df44	1674	#define __LL_RCC_CALC_PLLRCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
lypinator	0:bb348c97df44	1675	((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos ))
lypinator	0:bb348c97df44	1676
lypinator	0:bb348c97df44	1677	#endif /* RCC_PLLR_SYSCLK_SUPPORT */
lypinator	0:bb348c97df44	1678
lypinator	0:bb348c97df44	1679	/**
lypinator	0:bb348c97df44	1680	* @brief Helper macro to calculate the PLLCLK frequency used on 48M domain
lypinator	0:bb348c97df44	1681	* @note ex: @ref __LL_RCC_CALC_PLLCLK_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
lypinator	0:bb348c97df44	1682	* @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetQ ());
lypinator	0:bb348c97df44	1683	* @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
lypinator	0:bb348c97df44	1684	* @param __PLLM__ This parameter can be one of the following values:
lypinator	0:bb348c97df44	1685	* @arg @ref LL_RCC_PLLM_DIV_2
lypinator	0:bb348c97df44	1686	* @arg @ref LL_RCC_PLLM_DIV_3
lypinator	0:bb348c97df44	1687	* @arg @ref LL_RCC_PLLM_DIV_4
lypinator	0:bb348c97df44	1688	* @arg @ref LL_RCC_PLLM_DIV_5
lypinator	0:bb348c97df44	1689	* @arg @ref LL_RCC_PLLM_DIV_6
lypinator	0:bb348c97df44	1690	* @arg @ref LL_RCC_PLLM_DIV_7
lypinator	0:bb348c97df44	1691	* @arg @ref LL_RCC_PLLM_DIV_8
lypinator	0:bb348c97df44	1692	* @arg @ref LL_RCC_PLLM_DIV_9
lypinator	0:bb348c97df44	1693	* @arg @ref LL_RCC_PLLM_DIV_10
lypinator	0:bb348c97df44	1694	* @arg @ref LL_RCC_PLLM_DIV_11
lypinator	0:bb348c97df44	1695	* @arg @ref LL_RCC_PLLM_DIV_12
lypinator	0:bb348c97df44	1696	* @arg @ref LL_RCC_PLLM_DIV_13
lypinator	0:bb348c97df44	1697	* @arg @ref LL_RCC_PLLM_DIV_14
lypinator	0:bb348c97df44	1698	* @arg @ref LL_RCC_PLLM_DIV_15
lypinator	0:bb348c97df44	1699	* @arg @ref LL_RCC_PLLM_DIV_16
lypinator	0:bb348c97df44	1700	* @arg @ref LL_RCC_PLLM_DIV_17
lypinator	0:bb348c97df44	1701	* @arg @ref LL_RCC_PLLM_DIV_18
lypinator	0:bb348c97df44	1702	* @arg @ref LL_RCC_PLLM_DIV_19
lypinator	0:bb348c97df44	1703	* @arg @ref LL_RCC_PLLM_DIV_20
lypinator	0:bb348c97df44	1704	* @arg @ref LL_RCC_PLLM_DIV_21
lypinator	0:bb348c97df44	1705	* @arg @ref LL_RCC_PLLM_DIV_22
lypinator	0:bb348c97df44	1706	* @arg @ref LL_RCC_PLLM_DIV_23
lypinator	0:bb348c97df44	1707	* @arg @ref LL_RCC_PLLM_DIV_24
lypinator	0:bb348c97df44	1708	* @arg @ref LL_RCC_PLLM_DIV_25
lypinator	0:bb348c97df44	1709	* @arg @ref LL_RCC_PLLM_DIV_26
lypinator	0:bb348c97df44	1710	* @arg @ref LL_RCC_PLLM_DIV_27
lypinator	0:bb348c97df44	1711	* @arg @ref LL_RCC_PLLM_DIV_28
lypinator	0:bb348c97df44	1712	* @arg @ref LL_RCC_PLLM_DIV_29
lypinator	0:bb348c97df44	1713	* @arg @ref LL_RCC_PLLM_DIV_30
lypinator	0:bb348c97df44	1714	* @arg @ref LL_RCC_PLLM_DIV_31
lypinator	0:bb348c97df44	1715	* @arg @ref LL_RCC_PLLM_DIV_32
lypinator	0:bb348c97df44	1716	* @arg @ref LL_RCC_PLLM_DIV_33
lypinator	0:bb348c97df44	1717	* @arg @ref LL_RCC_PLLM_DIV_34
lypinator	0:bb348c97df44	1718	* @arg @ref LL_RCC_PLLM_DIV_35
lypinator	0:bb348c97df44	1719	* @arg @ref LL_RCC_PLLM_DIV_36
lypinator	0:bb348c97df44	1720	* @arg @ref LL_RCC_PLLM_DIV_37
lypinator	0:bb348c97df44	1721	* @arg @ref LL_RCC_PLLM_DIV_38
lypinator	0:bb348c97df44	1722	* @arg @ref LL_RCC_PLLM_DIV_39
lypinator	0:bb348c97df44	1723	* @arg @ref LL_RCC_PLLM_DIV_40
lypinator	0:bb348c97df44	1724	* @arg @ref LL_RCC_PLLM_DIV_41
lypinator	0:bb348c97df44	1725	* @arg @ref LL_RCC_PLLM_DIV_42
lypinator	0:bb348c97df44	1726	* @arg @ref LL_RCC_PLLM_DIV_43
lypinator	0:bb348c97df44	1727	* @arg @ref LL_RCC_PLLM_DIV_44
lypinator	0:bb348c97df44	1728	* @arg @ref LL_RCC_PLLM_DIV_45
lypinator	0:bb348c97df44	1729	* @arg @ref LL_RCC_PLLM_DIV_46
lypinator	0:bb348c97df44	1730	* @arg @ref LL_RCC_PLLM_DIV_47
lypinator	0:bb348c97df44	1731	* @arg @ref LL_RCC_PLLM_DIV_48
lypinator	0:bb348c97df44	1732	* @arg @ref LL_RCC_PLLM_DIV_49
lypinator	0:bb348c97df44	1733	* @arg @ref LL_RCC_PLLM_DIV_50
lypinator	0:bb348c97df44	1734	* @arg @ref LL_RCC_PLLM_DIV_51
lypinator	0:bb348c97df44	1735	* @arg @ref LL_RCC_PLLM_DIV_52
lypinator	0:bb348c97df44	1736	* @arg @ref LL_RCC_PLLM_DIV_53
lypinator	0:bb348c97df44	1737	* @arg @ref LL_RCC_PLLM_DIV_54
lypinator	0:bb348c97df44	1738	* @arg @ref LL_RCC_PLLM_DIV_55
lypinator	0:bb348c97df44	1739	* @arg @ref LL_RCC_PLLM_DIV_56
lypinator	0:bb348c97df44	1740	* @arg @ref LL_RCC_PLLM_DIV_57
lypinator	0:bb348c97df44	1741	* @arg @ref LL_RCC_PLLM_DIV_58
lypinator	0:bb348c97df44	1742	* @arg @ref LL_RCC_PLLM_DIV_59
lypinator	0:bb348c97df44	1743	* @arg @ref LL_RCC_PLLM_DIV_60
lypinator	0:bb348c97df44	1744	* @arg @ref LL_RCC_PLLM_DIV_61
lypinator	0:bb348c97df44	1745	* @arg @ref LL_RCC_PLLM_DIV_62
lypinator	0:bb348c97df44	1746	* @arg @ref LL_RCC_PLLM_DIV_63
lypinator	0:bb348c97df44	1747	* @param __PLLN__ Between 50/192(*) and 432
lypinator	0:bb348c97df44	1748	*
lypinator	0:bb348c97df44	1749	* (*) value not defined in all devices.
lypinator	0:bb348c97df44	1750	* @param __PLLQ__ This parameter can be one of the following values:
lypinator	0:bb348c97df44	1751	* @arg @ref LL_RCC_PLLQ_DIV_2
lypinator	0:bb348c97df44	1752	* @arg @ref LL_RCC_PLLQ_DIV_3
lypinator	0:bb348c97df44	1753	* @arg @ref LL_RCC_PLLQ_DIV_4
lypinator	0:bb348c97df44	1754	* @arg @ref LL_RCC_PLLQ_DIV_5
lypinator	0:bb348c97df44	1755	* @arg @ref LL_RCC_PLLQ_DIV_6
lypinator	0:bb348c97df44	1756	* @arg @ref LL_RCC_PLLQ_DIV_7
lypinator	0:bb348c97df44	1757	* @arg @ref LL_RCC_PLLQ_DIV_8
lypinator	0:bb348c97df44	1758	* @arg @ref LL_RCC_PLLQ_DIV_9
lypinator	0:bb348c97df44	1759	* @arg @ref LL_RCC_PLLQ_DIV_10
lypinator	0:bb348c97df44	1760	* @arg @ref LL_RCC_PLLQ_DIV_11
lypinator	0:bb348c97df44	1761	* @arg @ref LL_RCC_PLLQ_DIV_12
lypinator	0:bb348c97df44	1762	* @arg @ref LL_RCC_PLLQ_DIV_13
lypinator	0:bb348c97df44	1763	* @arg @ref LL_RCC_PLLQ_DIV_14
lypinator	0:bb348c97df44	1764	* @arg @ref LL_RCC_PLLQ_DIV_15
lypinator	0:bb348c97df44	1765	* @retval PLL clock frequency (in Hz)
lypinator	0:bb348c97df44	1766	*/
lypinator	0:bb348c97df44	1767	#define __LL_RCC_CALC_PLLCLK_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
lypinator	0:bb348c97df44	1768	((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos ))
lypinator	0:bb348c97df44	1769
lypinator	0:bb348c97df44	1770	#if defined(DSI)
lypinator	0:bb348c97df44	1771	/**
lypinator	0:bb348c97df44	1772	* @brief Helper macro to calculate the PLLCLK frequency used on DSI
lypinator	0:bb348c97df44	1773	* @note ex: @ref __LL_RCC_CALC_PLLCLK_DSI_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetDivider (),
lypinator	0:bb348c97df44	1774	* @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ());
lypinator	0:bb348c97df44	1775	* @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
lypinator	0:bb348c97df44	1776	* @param __PLLM__ This parameter can be one of the following values:
lypinator	0:bb348c97df44	1777	* @arg @ref LL_RCC_PLLM_DIV_2
lypinator	0:bb348c97df44	1778	* @arg @ref LL_RCC_PLLM_DIV_3
lypinator	0:bb348c97df44	1779	* @arg @ref LL_RCC_PLLM_DIV_4
lypinator	0:bb348c97df44	1780	* @arg @ref LL_RCC_PLLM_DIV_5
lypinator	0:bb348c97df44	1781	* @arg @ref LL_RCC_PLLM_DIV_6
lypinator	0:bb348c97df44	1782	* @arg @ref LL_RCC_PLLM_DIV_7
lypinator	0:bb348c97df44	1783	* @arg @ref LL_RCC_PLLM_DIV_8
lypinator	0:bb348c97df44	1784	* @arg @ref LL_RCC_PLLM_DIV_9
lypinator	0:bb348c97df44	1785	* @arg @ref LL_RCC_PLLM_DIV_10
lypinator	0:bb348c97df44	1786	* @arg @ref LL_RCC_PLLM_DIV_11
lypinator	0:bb348c97df44	1787	* @arg @ref LL_RCC_PLLM_DIV_12
lypinator	0:bb348c97df44	1788	* @arg @ref LL_RCC_PLLM_DIV_13
lypinator	0:bb348c97df44	1789	* @arg @ref LL_RCC_PLLM_DIV_14
lypinator	0:bb348c97df44	1790	* @arg @ref LL_RCC_PLLM_DIV_15
lypinator	0:bb348c97df44	1791	* @arg @ref LL_RCC_PLLM_DIV_16
lypinator	0:bb348c97df44	1792	* @arg @ref LL_RCC_PLLM_DIV_17
lypinator	0:bb348c97df44	1793	* @arg @ref LL_RCC_PLLM_DIV_18
lypinator	0:bb348c97df44	1794	* @arg @ref LL_RCC_PLLM_DIV_19
lypinator	0:bb348c97df44	1795	* @arg @ref LL_RCC_PLLM_DIV_20
lypinator	0:bb348c97df44	1796	* @arg @ref LL_RCC_PLLM_DIV_21
lypinator	0:bb348c97df44	1797	* @arg @ref LL_RCC_PLLM_DIV_22
lypinator	0:bb348c97df44	1798	* @arg @ref LL_RCC_PLLM_DIV_23
lypinator	0:bb348c97df44	1799	* @arg @ref LL_RCC_PLLM_DIV_24
lypinator	0:bb348c97df44	1800	* @arg @ref LL_RCC_PLLM_DIV_25
lypinator	0:bb348c97df44	1801	* @arg @ref LL_RCC_PLLM_DIV_26
lypinator	0:bb348c97df44	1802	* @arg @ref LL_RCC_PLLM_DIV_27
lypinator	0:bb348c97df44	1803	* @arg @ref LL_RCC_PLLM_DIV_28
lypinator	0:bb348c97df44	1804	* @arg @ref LL_RCC_PLLM_DIV_29
lypinator	0:bb348c97df44	1805	* @arg @ref LL_RCC_PLLM_DIV_30
lypinator	0:bb348c97df44	1806	* @arg @ref LL_RCC_PLLM_DIV_31
lypinator	0:bb348c97df44	1807	* @arg @ref LL_RCC_PLLM_DIV_32
lypinator	0:bb348c97df44	1808	* @arg @ref LL_RCC_PLLM_DIV_33
lypinator	0:bb348c97df44	1809	* @arg @ref LL_RCC_PLLM_DIV_34
lypinator	0:bb348c97df44	1810	* @arg @ref LL_RCC_PLLM_DIV_35
lypinator	0:bb348c97df44	1811	* @arg @ref LL_RCC_PLLM_DIV_36
lypinator	0:bb348c97df44	1812	* @arg @ref LL_RCC_PLLM_DIV_37
lypinator	0:bb348c97df44	1813	* @arg @ref LL_RCC_PLLM_DIV_38
lypinator	0:bb348c97df44	1814	* @arg @ref LL_RCC_PLLM_DIV_39
lypinator	0:bb348c97df44	1815	* @arg @ref LL_RCC_PLLM_DIV_40
lypinator	0:bb348c97df44	1816	* @arg @ref LL_RCC_PLLM_DIV_41
lypinator	0:bb348c97df44	1817	* @arg @ref LL_RCC_PLLM_DIV_42
lypinator	0:bb348c97df44	1818	* @arg @ref LL_RCC_PLLM_DIV_43
lypinator	0:bb348c97df44	1819	* @arg @ref LL_RCC_PLLM_DIV_44
lypinator	0:bb348c97df44	1820	* @arg @ref LL_RCC_PLLM_DIV_45
lypinator	0:bb348c97df44	1821	* @arg @ref LL_RCC_PLLM_DIV_46
lypinator	0:bb348c97df44	1822	* @arg @ref LL_RCC_PLLM_DIV_47
lypinator	0:bb348c97df44	1823	* @arg @ref LL_RCC_PLLM_DIV_48
lypinator	0:bb348c97df44	1824	* @arg @ref LL_RCC_PLLM_DIV_49
lypinator	0:bb348c97df44	1825	* @arg @ref LL_RCC_PLLM_DIV_50
lypinator	0:bb348c97df44	1826	* @arg @ref LL_RCC_PLLM_DIV_51
lypinator	0:bb348c97df44	1827	* @arg @ref LL_RCC_PLLM_DIV_52
lypinator	0:bb348c97df44	1828	* @arg @ref LL_RCC_PLLM_DIV_53
lypinator	0:bb348c97df44	1829	* @arg @ref LL_RCC_PLLM_DIV_54
lypinator	0:bb348c97df44	1830	* @arg @ref LL_RCC_PLLM_DIV_55
lypinator	0:bb348c97df44	1831	* @arg @ref LL_RCC_PLLM_DIV_56
lypinator	0:bb348c97df44	1832	* @arg @ref LL_RCC_PLLM_DIV_57
lypinator	0:bb348c97df44	1833	* @arg @ref LL_RCC_PLLM_DIV_58
lypinator	0:bb348c97df44	1834	* @arg @ref LL_RCC_PLLM_DIV_59
lypinator	0:bb348c97df44	1835	* @arg @ref LL_RCC_PLLM_DIV_60
lypinator	0:bb348c97df44	1836	* @arg @ref LL_RCC_PLLM_DIV_61
lypinator	0:bb348c97df44	1837	* @arg @ref LL_RCC_PLLM_DIV_62
lypinator	0:bb348c97df44	1838	* @arg @ref LL_RCC_PLLM_DIV_63
lypinator	0:bb348c97df44	1839	* @param __PLLN__ Between 50 and 432
lypinator	0:bb348c97df44	1840	* @param __PLLR__ This parameter can be one of the following values:
lypinator	0:bb348c97df44	1841	* @arg @ref LL_RCC_PLLR_DIV_2
lypinator	0:bb348c97df44	1842	* @arg @ref LL_RCC_PLLR_DIV_3
lypinator	0:bb348c97df44	1843	* @arg @ref LL_RCC_PLLR_DIV_4
lypinator	0:bb348c97df44	1844	* @arg @ref LL_RCC_PLLR_DIV_5
lypinator	0:bb348c97df44	1845	* @arg @ref LL_RCC_PLLR_DIV_6
lypinator	0:bb348c97df44	1846	* @arg @ref LL_RCC_PLLR_DIV_7
lypinator	0:bb348c97df44	1847	* @retval PLL clock frequency (in Hz)
lypinator	0:bb348c97df44	1848	*/
lypinator	0:bb348c97df44	1849	#define __LL_RCC_CALC_PLLCLK_DSI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
lypinator	0:bb348c97df44	1850	((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos ))
lypinator	0:bb348c97df44	1851	#endif /* DSI */
lypinator	0:bb348c97df44	1852
lypinator	0:bb348c97df44	1853	#if defined(RCC_PLLR_I2S_CLKSOURCE_SUPPORT)
lypinator	0:bb348c97df44	1854	/**
lypinator	0:bb348c97df44	1855	* @brief Helper macro to calculate the PLLCLK frequency used on I2S
lypinator	0:bb348c97df44	1856	* @note ex: @ref __LL_RCC_CALC_PLLCLK_I2S_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetDivider (),
lypinator	0:bb348c97df44	1857	* @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ());
lypinator	0:bb348c97df44	1858	* @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
lypinator	0:bb348c97df44	1859	* @param __PLLM__ This parameter can be one of the following values:
lypinator	0:bb348c97df44	1860	* @arg @ref LL_RCC_PLLM_DIV_2
lypinator	0:bb348c97df44	1861	* @arg @ref LL_RCC_PLLM_DIV_3
lypinator	0:bb348c97df44	1862	* @arg @ref LL_RCC_PLLM_DIV_4
lypinator	0:bb348c97df44	1863	* @arg @ref LL_RCC_PLLM_DIV_5
lypinator	0:bb348c97df44	1864	* @arg @ref LL_RCC_PLLM_DIV_6
lypinator	0:bb348c97df44	1865	* @arg @ref LL_RCC_PLLM_DIV_7
lypinator	0:bb348c97df44	1866	* @arg @ref LL_RCC_PLLM_DIV_8
lypinator	0:bb348c97df44	1867	* @arg @ref LL_RCC_PLLM_DIV_9
lypinator	0:bb348c97df44	1868	* @arg @ref LL_RCC_PLLM_DIV_10
lypinator	0:bb348c97df44	1869	* @arg @ref LL_RCC_PLLM_DIV_11
lypinator	0:bb348c97df44	1870	* @arg @ref LL_RCC_PLLM_DIV_12
lypinator	0:bb348c97df44	1871	* @arg @ref LL_RCC_PLLM_DIV_13
lypinator	0:bb348c97df44	1872	* @arg @ref LL_RCC_PLLM_DIV_14
lypinator	0:bb348c97df44	1873	* @arg @ref LL_RCC_PLLM_DIV_15
lypinator	0:bb348c97df44	1874	* @arg @ref LL_RCC_PLLM_DIV_16
lypinator	0:bb348c97df44	1875	* @arg @ref LL_RCC_PLLM_DIV_17
lypinator	0:bb348c97df44	1876	* @arg @ref LL_RCC_PLLM_DIV_18
lypinator	0:bb348c97df44	1877	* @arg @ref LL_RCC_PLLM_DIV_19
lypinator	0:bb348c97df44	1878	* @arg @ref LL_RCC_PLLM_DIV_20
lypinator	0:bb348c97df44	1879	* @arg @ref LL_RCC_PLLM_DIV_21
lypinator	0:bb348c97df44	1880	* @arg @ref LL_RCC_PLLM_DIV_22
lypinator	0:bb348c97df44	1881	* @arg @ref LL_RCC_PLLM_DIV_23
lypinator	0:bb348c97df44	1882	* @arg @ref LL_RCC_PLLM_DIV_24
lypinator	0:bb348c97df44	1883	* @arg @ref LL_RCC_PLLM_DIV_25
lypinator	0:bb348c97df44	1884	* @arg @ref LL_RCC_PLLM_DIV_26
lypinator	0:bb348c97df44	1885	* @arg @ref LL_RCC_PLLM_DIV_27
lypinator	0:bb348c97df44	1886	* @arg @ref LL_RCC_PLLM_DIV_28
lypinator	0:bb348c97df44	1887	* @arg @ref LL_RCC_PLLM_DIV_29
lypinator	0:bb348c97df44	1888	* @arg @ref LL_RCC_PLLM_DIV_30
lypinator	0:bb348c97df44	1889	* @arg @ref LL_RCC_PLLM_DIV_31
lypinator	0:bb348c97df44	1890	* @arg @ref LL_RCC_PLLM_DIV_32
lypinator	0:bb348c97df44	1891	* @arg @ref LL_RCC_PLLM_DIV_33
lypinator	0:bb348c97df44	1892	* @arg @ref LL_RCC_PLLM_DIV_34
lypinator	0:bb348c97df44	1893	* @arg @ref LL_RCC_PLLM_DIV_35
lypinator	0:bb348c97df44	1894	* @arg @ref LL_RCC_PLLM_DIV_36
lypinator	0:bb348c97df44	1895	* @arg @ref LL_RCC_PLLM_DIV_37
lypinator	0:bb348c97df44	1896	* @arg @ref LL_RCC_PLLM_DIV_38
lypinator	0:bb348c97df44	1897	* @arg @ref LL_RCC_PLLM_DIV_39
lypinator	0:bb348c97df44	1898	* @arg @ref LL_RCC_PLLM_DIV_40
lypinator	0:bb348c97df44	1899	* @arg @ref LL_RCC_PLLM_DIV_41
lypinator	0:bb348c97df44	1900	* @arg @ref LL_RCC_PLLM_DIV_42
lypinator	0:bb348c97df44	1901	* @arg @ref LL_RCC_PLLM_DIV_43
lypinator	0:bb348c97df44	1902	* @arg @ref LL_RCC_PLLM_DIV_44
lypinator	0:bb348c97df44	1903	* @arg @ref LL_RCC_PLLM_DIV_45
lypinator	0:bb348c97df44	1904	* @arg @ref LL_RCC_PLLM_DIV_46
lypinator	0:bb348c97df44	1905	* @arg @ref LL_RCC_PLLM_DIV_47
lypinator	0:bb348c97df44	1906	* @arg @ref LL_RCC_PLLM_DIV_48
lypinator	0:bb348c97df44	1907	* @arg @ref LL_RCC_PLLM_DIV_49
lypinator	0:bb348c97df44	1908	* @arg @ref LL_RCC_PLLM_DIV_50
lypinator	0:bb348c97df44	1909	* @arg @ref LL_RCC_PLLM_DIV_51
lypinator	0:bb348c97df44	1910	* @arg @ref LL_RCC_PLLM_DIV_52
lypinator	0:bb348c97df44	1911	* @arg @ref LL_RCC_PLLM_DIV_53
lypinator	0:bb348c97df44	1912	* @arg @ref LL_RCC_PLLM_DIV_54
lypinator	0:bb348c97df44	1913	* @arg @ref LL_RCC_PLLM_DIV_55
lypinator	0:bb348c97df44	1914	* @arg @ref LL_RCC_PLLM_DIV_56
lypinator	0:bb348c97df44	1915	* @arg @ref LL_RCC_PLLM_DIV_57
lypinator	0:bb348c97df44	1916	* @arg @ref LL_RCC_PLLM_DIV_58
lypinator	0:bb348c97df44	1917	* @arg @ref LL_RCC_PLLM_DIV_59
lypinator	0:bb348c97df44	1918	* @arg @ref LL_RCC_PLLM_DIV_60
lypinator	0:bb348c97df44	1919	* @arg @ref LL_RCC_PLLM_DIV_61
lypinator	0:bb348c97df44	1920	* @arg @ref LL_RCC_PLLM_DIV_62
lypinator	0:bb348c97df44	1921	* @arg @ref LL_RCC_PLLM_DIV_63
lypinator	0:bb348c97df44	1922	* @param __PLLN__ Between 50 and 432
lypinator	0:bb348c97df44	1923	* @param __PLLR__ This parameter can be one of the following values:
lypinator	0:bb348c97df44	1924	* @arg @ref LL_RCC_PLLR_DIV_2
lypinator	0:bb348c97df44	1925	* @arg @ref LL_RCC_PLLR_DIV_3
lypinator	0:bb348c97df44	1926	* @arg @ref LL_RCC_PLLR_DIV_4
lypinator	0:bb348c97df44	1927	* @arg @ref LL_RCC_PLLR_DIV_5
lypinator	0:bb348c97df44	1928	* @arg @ref LL_RCC_PLLR_DIV_6
lypinator	0:bb348c97df44	1929	* @arg @ref LL_RCC_PLLR_DIV_7
lypinator	0:bb348c97df44	1930	* @retval PLL clock frequency (in Hz)
lypinator	0:bb348c97df44	1931	*/
lypinator	0:bb348c97df44	1932	#define __LL_RCC_CALC_PLLCLK_I2S_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
lypinator	0:bb348c97df44	1933	((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos ))
lypinator	0:bb348c97df44	1934	#endif /* RCC_PLLR_I2S_CLKSOURCE_SUPPORT */
lypinator	0:bb348c97df44	1935
lypinator	0:bb348c97df44	1936	#if defined(SPDIFRX)
lypinator	0:bb348c97df44	1937	/**
lypinator	0:bb348c97df44	1938	* @brief Helper macro to calculate the PLLCLK frequency used on SPDIFRX
lypinator	0:bb348c97df44	1939	* @note ex: @ref __LL_RCC_CALC_PLLCLK_SPDIFRX_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetDivider (),
lypinator	0:bb348c97df44	1940	* @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ());
lypinator	0:bb348c97df44	1941	* @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
lypinator	0:bb348c97df44	1942	* @param __PLLM__ This parameter can be one of the following values:
lypinator	0:bb348c97df44	1943	* @arg @ref LL_RCC_PLLM_DIV_2
lypinator	0:bb348c97df44	1944	* @arg @ref LL_RCC_PLLM_DIV_3
lypinator	0:bb348c97df44	1945	* @arg @ref LL_RCC_PLLM_DIV_4
lypinator	0:bb348c97df44	1946	* @arg @ref LL_RCC_PLLM_DIV_5
lypinator	0:bb348c97df44	1947	* @arg @ref LL_RCC_PLLM_DIV_6
lypinator	0:bb348c97df44	1948	* @arg @ref LL_RCC_PLLM_DIV_7
lypinator	0:bb348c97df44	1949	* @arg @ref LL_RCC_PLLM_DIV_8
lypinator	0:bb348c97df44	1950	* @arg @ref LL_RCC_PLLM_DIV_9
lypinator	0:bb348c97df44	1951	* @arg @ref LL_RCC_PLLM_DIV_10
lypinator	0:bb348c97df44	1952	* @arg @ref LL_RCC_PLLM_DIV_11
lypinator	0:bb348c97df44	1953	* @arg @ref LL_RCC_PLLM_DIV_12
lypinator	0:bb348c97df44	1954	* @arg @ref LL_RCC_PLLM_DIV_13
lypinator	0:bb348c97df44	1955	* @arg @ref LL_RCC_PLLM_DIV_14
lypinator	0:bb348c97df44	1956	* @arg @ref LL_RCC_PLLM_DIV_15
lypinator	0:bb348c97df44	1957	* @arg @ref LL_RCC_PLLM_DIV_16
lypinator	0:bb348c97df44	1958	* @arg @ref LL_RCC_PLLM_DIV_17
lypinator	0:bb348c97df44	1959	* @arg @ref LL_RCC_PLLM_DIV_18
lypinator	0:bb348c97df44	1960	* @arg @ref LL_RCC_PLLM_DIV_19
lypinator	0:bb348c97df44	1961	* @arg @ref LL_RCC_PLLM_DIV_20
lypinator	0:bb348c97df44	1962	* @arg @ref LL_RCC_PLLM_DIV_21
lypinator	0:bb348c97df44	1963	* @arg @ref LL_RCC_PLLM_DIV_22
lypinator	0:bb348c97df44	1964	* @arg @ref LL_RCC_PLLM_DIV_23
lypinator	0:bb348c97df44	1965	* @arg @ref LL_RCC_PLLM_DIV_24
lypinator	0:bb348c97df44	1966	* @arg @ref LL_RCC_PLLM_DIV_25
lypinator	0:bb348c97df44	1967	* @arg @ref LL_RCC_PLLM_DIV_26
lypinator	0:bb348c97df44	1968	* @arg @ref LL_RCC_PLLM_DIV_27
lypinator	0:bb348c97df44	1969	* @arg @ref LL_RCC_PLLM_DIV_28
lypinator	0:bb348c97df44	1970	* @arg @ref LL_RCC_PLLM_DIV_29
lypinator	0:bb348c97df44	1971	* @arg @ref LL_RCC_PLLM_DIV_30
lypinator	0:bb348c97df44	1972	* @arg @ref LL_RCC_PLLM_DIV_31
lypinator	0:bb348c97df44	1973	* @arg @ref LL_RCC_PLLM_DIV_32
lypinator	0:bb348c97df44	1974	* @arg @ref LL_RCC_PLLM_DIV_33
lypinator	0:bb348c97df44	1975	* @arg @ref LL_RCC_PLLM_DIV_34
lypinator	0:bb348c97df44	1976	* @arg @ref LL_RCC_PLLM_DIV_35
lypinator	0:bb348c97df44	1977	* @arg @ref LL_RCC_PLLM_DIV_36
lypinator	0:bb348c97df44	1978	* @arg @ref LL_RCC_PLLM_DIV_37
lypinator	0:bb348c97df44	1979	* @arg @ref LL_RCC_PLLM_DIV_38
lypinator	0:bb348c97df44	1980	* @arg @ref LL_RCC_PLLM_DIV_39
lypinator	0:bb348c97df44	1981	* @arg @ref LL_RCC_PLLM_DIV_40
lypinator	0:bb348c97df44	1982	* @arg @ref LL_RCC_PLLM_DIV_41
lypinator	0:bb348c97df44	1983	* @arg @ref LL_RCC_PLLM_DIV_42
lypinator	0:bb348c97df44	1984	* @arg @ref LL_RCC_PLLM_DIV_43
lypinator	0:bb348c97df44	1985	* @arg @ref LL_RCC_PLLM_DIV_44
lypinator	0:bb348c97df44	1986	* @arg @ref LL_RCC_PLLM_DIV_45
lypinator	0:bb348c97df44	1987	* @arg @ref LL_RCC_PLLM_DIV_46
lypinator	0:bb348c97df44	1988	* @arg @ref LL_RCC_PLLM_DIV_47
lypinator	0:bb348c97df44	1989	* @arg @ref LL_RCC_PLLM_DIV_48
lypinator	0:bb348c97df44	1990	* @arg @ref LL_RCC_PLLM_DIV_49
lypinator	0:bb348c97df44	1991	* @arg @ref LL_RCC_PLLM_DIV_50
lypinator	0:bb348c97df44	1992	* @arg @ref LL_RCC_PLLM_DIV_51
lypinator	0:bb348c97df44	1993	* @arg @ref LL_RCC_PLLM_DIV_52
lypinator	0:bb348c97df44	1994	* @arg @ref LL_RCC_PLLM_DIV_53
lypinator	0:bb348c97df44	1995	* @arg @ref LL_RCC_PLLM_DIV_54
lypinator	0:bb348c97df44	1996	* @arg @ref LL_RCC_PLLM_DIV_55
lypinator	0:bb348c97df44	1997	* @arg @ref LL_RCC_PLLM_DIV_56
lypinator	0:bb348c97df44	1998	* @arg @ref LL_RCC_PLLM_DIV_57
lypinator	0:bb348c97df44	1999	* @arg @ref LL_RCC_PLLM_DIV_58
lypinator	0:bb348c97df44	2000	* @arg @ref LL_RCC_PLLM_DIV_59
lypinator	0:bb348c97df44	2001	* @arg @ref LL_RCC_PLLM_DIV_60
lypinator	0:bb348c97df44	2002	* @arg @ref LL_RCC_PLLM_DIV_61
lypinator	0:bb348c97df44	2003	* @arg @ref LL_RCC_PLLM_DIV_62
lypinator	0:bb348c97df44	2004	* @arg @ref LL_RCC_PLLM_DIV_63
lypinator	0:bb348c97df44	2005	* @param __PLLN__ Between 50 and 432
lypinator	0:bb348c97df44	2006	* @param __PLLR__ This parameter can be one of the following values:
lypinator	0:bb348c97df44	2007	* @arg @ref LL_RCC_PLLR_DIV_2
lypinator	0:bb348c97df44	2008	* @arg @ref LL_RCC_PLLR_DIV_3
lypinator	0:bb348c97df44	2009	* @arg @ref LL_RCC_PLLR_DIV_4
lypinator	0:bb348c97df44	2010	* @arg @ref LL_RCC_PLLR_DIV_5
lypinator	0:bb348c97df44	2011	* @arg @ref LL_RCC_PLLR_DIV_6
lypinator	0:bb348c97df44	2012	* @arg @ref LL_RCC_PLLR_DIV_7
lypinator	0:bb348c97df44	2013	* @retval PLL clock frequency (in Hz)
lypinator	0:bb348c97df44	2014	*/
lypinator	0:bb348c97df44	2015	#define __LL_RCC_CALC_PLLCLK_SPDIFRX_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
lypinator	0:bb348c97df44	2016	((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos ))
lypinator	0:bb348c97df44	2017	#endif /* SPDIFRX */
lypinator	0:bb348c97df44	2018
lypinator	0:bb348c97df44	2019	#if defined(RCC_PLLCFGR_PLLR)
lypinator	0:bb348c97df44	2020	#if defined(SAI1)
lypinator	0:bb348c97df44	2021	/**
lypinator	0:bb348c97df44	2022	* @brief Helper macro to calculate the PLLCLK frequency used on SAI
lypinator	0:bb348c97df44	2023	* @note ex: @ref __LL_RCC_CALC_PLLCLK_SAI_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetDivider (),
lypinator	0:bb348c97df44	2024	* @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR (), @ref LL_RCC_PLL_GetDIVR ());
lypinator	0:bb348c97df44	2025	* @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
lypinator	0:bb348c97df44	2026	* @param __PLLM__ This parameter can be one of the following values:
lypinator	0:bb348c97df44	2027	* @arg @ref LL_RCC_PLLM_DIV_2
lypinator	0:bb348c97df44	2028	* @arg @ref LL_RCC_PLLM_DIV_3
lypinator	0:bb348c97df44	2029	* @arg @ref LL_RCC_PLLM_DIV_4
lypinator	0:bb348c97df44	2030	* @arg @ref LL_RCC_PLLM_DIV_5
lypinator	0:bb348c97df44	2031	* @arg @ref LL_RCC_PLLM_DIV_6
lypinator	0:bb348c97df44	2032	* @arg @ref LL_RCC_PLLM_DIV_7
lypinator	0:bb348c97df44	2033	* @arg @ref LL_RCC_PLLM_DIV_8
lypinator	0:bb348c97df44	2034	* @arg @ref LL_RCC_PLLM_DIV_9
lypinator	0:bb348c97df44	2035	* @arg @ref LL_RCC_PLLM_DIV_10
lypinator	0:bb348c97df44	2036	* @arg @ref LL_RCC_PLLM_DIV_11
lypinator	0:bb348c97df44	2037	* @arg @ref LL_RCC_PLLM_DIV_12
lypinator	0:bb348c97df44	2038	* @arg @ref LL_RCC_PLLM_DIV_13
lypinator	0:bb348c97df44	2039	* @arg @ref LL_RCC_PLLM_DIV_14
lypinator	0:bb348c97df44	2040	* @arg @ref LL_RCC_PLLM_DIV_15
lypinator	0:bb348c97df44	2041	* @arg @ref LL_RCC_PLLM_DIV_16
lypinator	0:bb348c97df44	2042	* @arg @ref LL_RCC_PLLM_DIV_17
lypinator	0:bb348c97df44	2043	* @arg @ref LL_RCC_PLLM_DIV_18
lypinator	0:bb348c97df44	2044	* @arg @ref LL_RCC_PLLM_DIV_19
lypinator	0:bb348c97df44	2045	* @arg @ref LL_RCC_PLLM_DIV_20
lypinator	0:bb348c97df44	2046	* @arg @ref LL_RCC_PLLM_DIV_21
lypinator	0:bb348c97df44	2047	* @arg @ref LL_RCC_PLLM_DIV_22
lypinator	0:bb348c97df44	2048	* @arg @ref LL_RCC_PLLM_DIV_23
lypinator	0:bb348c97df44	2049	* @arg @ref LL_RCC_PLLM_DIV_24
lypinator	0:bb348c97df44	2050	* @arg @ref LL_RCC_PLLM_DIV_25
lypinator	0:bb348c97df44	2051	* @arg @ref LL_RCC_PLLM_DIV_26
lypinator	0:bb348c97df44	2052	* @arg @ref LL_RCC_PLLM_DIV_27
lypinator	0:bb348c97df44	2053	* @arg @ref LL_RCC_PLLM_DIV_28
lypinator	0:bb348c97df44	2054	* @arg @ref LL_RCC_PLLM_DIV_29
lypinator	0:bb348c97df44	2055	* @arg @ref LL_RCC_PLLM_DIV_30
lypinator	0:bb348c97df44	2056	* @arg @ref LL_RCC_PLLM_DIV_31
lypinator	0:bb348c97df44	2057	* @arg @ref LL_RCC_PLLM_DIV_32
lypinator	0:bb348c97df44	2058	* @arg @ref LL_RCC_PLLM_DIV_33
lypinator	0:bb348c97df44	2059	* @arg @ref LL_RCC_PLLM_DIV_34
lypinator	0:bb348c97df44	2060	* @arg @ref LL_RCC_PLLM_DIV_35
lypinator	0:bb348c97df44	2061	* @arg @ref LL_RCC_PLLM_DIV_36
lypinator	0:bb348c97df44	2062	* @arg @ref LL_RCC_PLLM_DIV_37
lypinator	0:bb348c97df44	2063	* @arg @ref LL_RCC_PLLM_DIV_38
lypinator	0:bb348c97df44	2064	* @arg @ref LL_RCC_PLLM_DIV_39
lypinator	0:bb348c97df44	2065	* @arg @ref LL_RCC_PLLM_DIV_40
lypinator	0:bb348c97df44	2066	* @arg @ref LL_RCC_PLLM_DIV_41
lypinator	0:bb348c97df44	2067	* @arg @ref LL_RCC_PLLM_DIV_42
lypinator	0:bb348c97df44	2068	* @arg @ref LL_RCC_PLLM_DIV_43
lypinator	0:bb348c97df44	2069	* @arg @ref LL_RCC_PLLM_DIV_44
lypinator	0:bb348c97df44	2070	* @arg @ref LL_RCC_PLLM_DIV_45
lypinator	0:bb348c97df44	2071	* @arg @ref LL_RCC_PLLM_DIV_46
lypinator	0:bb348c97df44	2072	* @arg @ref LL_RCC_PLLM_DIV_47
lypinator	0:bb348c97df44	2073	* @arg @ref LL_RCC_PLLM_DIV_48
lypinator	0:bb348c97df44	2074	* @arg @ref LL_RCC_PLLM_DIV_49
lypinator	0:bb348c97df44	2075	* @arg @ref LL_RCC_PLLM_DIV_50
lypinator	0:bb348c97df44	2076	* @arg @ref LL_RCC_PLLM_DIV_51
lypinator	0:bb348c97df44	2077	* @arg @ref LL_RCC_PLLM_DIV_52
lypinator	0:bb348c97df44	2078	* @arg @ref LL_RCC_PLLM_DIV_53
lypinator	0:bb348c97df44	2079	* @arg @ref LL_RCC_PLLM_DIV_54
lypinator	0:bb348c97df44	2080	* @arg @ref LL_RCC_PLLM_DIV_55
lypinator	0:bb348c97df44	2081	* @arg @ref LL_RCC_PLLM_DIV_56
lypinator	0:bb348c97df44	2082	* @arg @ref LL_RCC_PLLM_DIV_57
lypinator	0:bb348c97df44	2083	* @arg @ref LL_RCC_PLLM_DIV_58
lypinator	0:bb348c97df44	2084	* @arg @ref LL_RCC_PLLM_DIV_59
lypinator	0:bb348c97df44	2085	* @arg @ref LL_RCC_PLLM_DIV_60
lypinator	0:bb348c97df44	2086	* @arg @ref LL_RCC_PLLM_DIV_61
lypinator	0:bb348c97df44	2087	* @arg @ref LL_RCC_PLLM_DIV_62
lypinator	0:bb348c97df44	2088	* @arg @ref LL_RCC_PLLM_DIV_63
lypinator	0:bb348c97df44	2089	* @param __PLLN__ Between 50 and 432
lypinator	0:bb348c97df44	2090	* @param __PLLR__ This parameter can be one of the following values:
lypinator	0:bb348c97df44	2091	* @arg @ref LL_RCC_PLLR_DIV_2
lypinator	0:bb348c97df44	2092	* @arg @ref LL_RCC_PLLR_DIV_3
lypinator	0:bb348c97df44	2093	* @arg @ref LL_RCC_PLLR_DIV_4
lypinator	0:bb348c97df44	2094	* @arg @ref LL_RCC_PLLR_DIV_5
lypinator	0:bb348c97df44	2095	* @arg @ref LL_RCC_PLLR_DIV_6
lypinator	0:bb348c97df44	2096	* @arg @ref LL_RCC_PLLR_DIV_7
lypinator	0:bb348c97df44	2097	* @param __PLLDIVR__ This parameter can be one of the following values:
lypinator	0:bb348c97df44	2098	* @arg @ref LL_RCC_PLLDIVR_DIV_1 (*)
lypinator	0:bb348c97df44	2099	* @arg @ref LL_RCC_PLLDIVR_DIV_2 (*)
lypinator	0:bb348c97df44	2100	* @arg @ref LL_RCC_PLLDIVR_DIV_3 (*)
lypinator	0:bb348c97df44	2101	* @arg @ref LL_RCC_PLLDIVR_DIV_4 (*)
lypinator	0:bb348c97df44	2102	* @arg @ref LL_RCC_PLLDIVR_DIV_5 (*)
lypinator	0:bb348c97df44	2103	* @arg @ref LL_RCC_PLLDIVR_DIV_6 (*)
lypinator	0:bb348c97df44	2104	* @arg @ref LL_RCC_PLLDIVR_DIV_7 (*)
lypinator	0:bb348c97df44	2105	* @arg @ref LL_RCC_PLLDIVR_DIV_8 (*)
lypinator	0:bb348c97df44	2106	* @arg @ref LL_RCC_PLLDIVR_DIV_9 (*)
lypinator	0:bb348c97df44	2107	* @arg @ref LL_RCC_PLLDIVR_DIV_10 (*)
lypinator	0:bb348c97df44	2108	* @arg @ref LL_RCC_PLLDIVR_DIV_11 (*)
lypinator	0:bb348c97df44	2109	* @arg @ref LL_RCC_PLLDIVR_DIV_12 (*)
lypinator	0:bb348c97df44	2110	* @arg @ref LL_RCC_PLLDIVR_DIV_13 (*)
lypinator	0:bb348c97df44	2111	* @arg @ref LL_RCC_PLLDIVR_DIV_14 (*)
lypinator	0:bb348c97df44	2112	* @arg @ref LL_RCC_PLLDIVR_DIV_15 (*)
lypinator	0:bb348c97df44	2113	* @arg @ref LL_RCC_PLLDIVR_DIV_16 (*)
lypinator	0:bb348c97df44	2114	* @arg @ref LL_RCC_PLLDIVR_DIV_17 (*)
lypinator	0:bb348c97df44	2115	* @arg @ref LL_RCC_PLLDIVR_DIV_18 (*)
lypinator	0:bb348c97df44	2116	* @arg @ref LL_RCC_PLLDIVR_DIV_19 (*)
lypinator	0:bb348c97df44	2117	* @arg @ref LL_RCC_PLLDIVR_DIV_20 (*)
lypinator	0:bb348c97df44	2118	* @arg @ref LL_RCC_PLLDIVR_DIV_21 (*)
lypinator	0:bb348c97df44	2119	* @arg @ref LL_RCC_PLLDIVR_DIV_22 (*)
lypinator	0:bb348c97df44	2120	* @arg @ref LL_RCC_PLLDIVR_DIV_23 (*)
lypinator	0:bb348c97df44	2121	* @arg @ref LL_RCC_PLLDIVR_DIV_24 (*)
lypinator	0:bb348c97df44	2122	* @arg @ref LL_RCC_PLLDIVR_DIV_25 (*)
lypinator	0:bb348c97df44	2123	* @arg @ref LL_RCC_PLLDIVR_DIV_26 (*)
lypinator	0:bb348c97df44	2124	* @arg @ref LL_RCC_PLLDIVR_DIV_27 (*)
lypinator	0:bb348c97df44	2125	* @arg @ref LL_RCC_PLLDIVR_DIV_28 (*)
lypinator	0:bb348c97df44	2126	* @arg @ref LL_RCC_PLLDIVR_DIV_29 (*)
lypinator	0:bb348c97df44	2127	* @arg @ref LL_RCC_PLLDIVR_DIV_30 (*)
lypinator	0:bb348c97df44	2128	* @arg @ref LL_RCC_PLLDIVR_DIV_31 (*)
lypinator	0:bb348c97df44	2129	*
lypinator	0:bb348c97df44	2130	* (*) value not defined in all devices.
lypinator	0:bb348c97df44	2131	* @retval PLL clock frequency (in Hz)
lypinator	0:bb348c97df44	2132	*/
lypinator	0:bb348c97df44	2133	#if defined(RCC_DCKCFGR_PLLDIVR)
lypinator	0:bb348c97df44	2134	#define __LL_RCC_CALC_PLLCLK_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__, __PLLDIVR__) (((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
lypinator	0:bb348c97df44	2135	((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos )) / ((__PLLDIVR__) >> RCC_DCKCFGR_PLLDIVR_Pos ))
lypinator	0:bb348c97df44	2136	#else
lypinator	0:bb348c97df44	2137	#define __LL_RCC_CALC_PLLCLK_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
lypinator	0:bb348c97df44	2138	((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos ))
lypinator	0:bb348c97df44	2139	#endif /* RCC_DCKCFGR_PLLDIVR */
lypinator	0:bb348c97df44	2140	#endif /* SAI1 */
lypinator	0:bb348c97df44	2141	#endif /* RCC_PLLCFGR_PLLR */
lypinator	0:bb348c97df44	2142
lypinator	0:bb348c97df44	2143	#if defined(RCC_PLLSAI_SUPPORT)
lypinator	0:bb348c97df44	2144	/**
lypinator	0:bb348c97df44	2145	* @brief Helper macro to calculate the PLLSAI frequency used for SAI domain
lypinator	0:bb348c97df44	2146	* @note ex: @ref __LL_RCC_CALC_PLLSAI_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI_GetDivider (),
lypinator	0:bb348c97df44	2147	* @ref LL_RCC_PLLSAI_GetN (), @ref LL_RCC_PLLSAI_GetQ (), @ref LL_RCC_PLLSAI_GetDIVQ ());
lypinator	0:bb348c97df44	2148	* @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
lypinator	0:bb348c97df44	2149	* @param __PLLM__ This parameter can be one of the following values:
lypinator	0:bb348c97df44	2150	* @arg @ref LL_RCC_PLLSAIM_DIV_2
lypinator	0:bb348c97df44	2151	* @arg @ref LL_RCC_PLLSAIM_DIV_3
lypinator	0:bb348c97df44	2152	* @arg @ref LL_RCC_PLLSAIM_DIV_4
lypinator	0:bb348c97df44	2153	* @arg @ref LL_RCC_PLLSAIM_DIV_5
lypinator	0:bb348c97df44	2154	* @arg @ref LL_RCC_PLLSAIM_DIV_6
lypinator	0:bb348c97df44	2155	* @arg @ref LL_RCC_PLLSAIM_DIV_7
lypinator	0:bb348c97df44	2156	* @arg @ref LL_RCC_PLLSAIM_DIV_8
lypinator	0:bb348c97df44	2157	* @arg @ref LL_RCC_PLLSAIM_DIV_9
lypinator	0:bb348c97df44	2158	* @arg @ref LL_RCC_PLLSAIM_DIV_10
lypinator	0:bb348c97df44	2159	* @arg @ref LL_RCC_PLLSAIM_DIV_11
lypinator	0:bb348c97df44	2160	* @arg @ref LL_RCC_PLLSAIM_DIV_12
lypinator	0:bb348c97df44	2161	* @arg @ref LL_RCC_PLLSAIM_DIV_13
lypinator	0:bb348c97df44	2162	* @arg @ref LL_RCC_PLLSAIM_DIV_14
lypinator	0:bb348c97df44	2163	* @arg @ref LL_RCC_PLLSAIM_DIV_15
lypinator	0:bb348c97df44	2164	* @arg @ref LL_RCC_PLLSAIM_DIV_16
lypinator	0:bb348c97df44	2165	* @arg @ref LL_RCC_PLLSAIM_DIV_17
lypinator	0:bb348c97df44	2166	* @arg @ref LL_RCC_PLLSAIM_DIV_18
lypinator	0:bb348c97df44	2167	* @arg @ref LL_RCC_PLLSAIM_DIV_19
lypinator	0:bb348c97df44	2168	* @arg @ref LL_RCC_PLLSAIM_DIV_20
lypinator	0:bb348c97df44	2169	* @arg @ref LL_RCC_PLLSAIM_DIV_21
lypinator	0:bb348c97df44	2170	* @arg @ref LL_RCC_PLLSAIM_DIV_22
lypinator	0:bb348c97df44	2171	* @arg @ref LL_RCC_PLLSAIM_DIV_23
lypinator	0:bb348c97df44	2172	* @arg @ref LL_RCC_PLLSAIM_DIV_24
lypinator	0:bb348c97df44	2173	* @arg @ref LL_RCC_PLLSAIM_DIV_25
lypinator	0:bb348c97df44	2174	* @arg @ref LL_RCC_PLLSAIM_DIV_26
lypinator	0:bb348c97df44	2175	* @arg @ref LL_RCC_PLLSAIM_DIV_27
lypinator	0:bb348c97df44	2176	* @arg @ref LL_RCC_PLLSAIM_DIV_28
lypinator	0:bb348c97df44	2177	* @arg @ref LL_RCC_PLLSAIM_DIV_29
lypinator	0:bb348c97df44	2178	* @arg @ref LL_RCC_PLLSAIM_DIV_30
lypinator	0:bb348c97df44	2179	* @arg @ref LL_RCC_PLLSAIM_DIV_31
lypinator	0:bb348c97df44	2180	* @arg @ref LL_RCC_PLLSAIM_DIV_32
lypinator	0:bb348c97df44	2181	* @arg @ref LL_RCC_PLLSAIM_DIV_33
lypinator	0:bb348c97df44	2182	* @arg @ref LL_RCC_PLLSAIM_DIV_34
lypinator	0:bb348c97df44	2183	* @arg @ref LL_RCC_PLLSAIM_DIV_35
lypinator	0:bb348c97df44	2184	* @arg @ref LL_RCC_PLLSAIM_DIV_36
lypinator	0:bb348c97df44	2185	* @arg @ref LL_RCC_PLLSAIM_DIV_37
lypinator	0:bb348c97df44	2186	* @arg @ref LL_RCC_PLLSAIM_DIV_38
lypinator	0:bb348c97df44	2187	* @arg @ref LL_RCC_PLLSAIM_DIV_39
lypinator	0:bb348c97df44	2188	* @arg @ref LL_RCC_PLLSAIM_DIV_40
lypinator	0:bb348c97df44	2189	* @arg @ref LL_RCC_PLLSAIM_DIV_41
lypinator	0:bb348c97df44	2190	* @arg @ref LL_RCC_PLLSAIM_DIV_42
lypinator	0:bb348c97df44	2191	* @arg @ref LL_RCC_PLLSAIM_DIV_43
lypinator	0:bb348c97df44	2192	* @arg @ref LL_RCC_PLLSAIM_DIV_44
lypinator	0:bb348c97df44	2193	* @arg @ref LL_RCC_PLLSAIM_DIV_45
lypinator	0:bb348c97df44	2194	* @arg @ref LL_RCC_PLLSAIM_DIV_46
lypinator	0:bb348c97df44	2195	* @arg @ref LL_RCC_PLLSAIM_DIV_47
lypinator	0:bb348c97df44	2196	* @arg @ref LL_RCC_PLLSAIM_DIV_48
lypinator	0:bb348c97df44	2197	* @arg @ref LL_RCC_PLLSAIM_DIV_49
lypinator	0:bb348c97df44	2198	* @arg @ref LL_RCC_PLLSAIM_DIV_50
lypinator	0:bb348c97df44	2199	* @arg @ref LL_RCC_PLLSAIM_DIV_51
lypinator	0:bb348c97df44	2200	* @arg @ref LL_RCC_PLLSAIM_DIV_52
lypinator	0:bb348c97df44	2201	* @arg @ref LL_RCC_PLLSAIM_DIV_53
lypinator	0:bb348c97df44	2202	* @arg @ref LL_RCC_PLLSAIM_DIV_54
lypinator	0:bb348c97df44	2203	* @arg @ref LL_RCC_PLLSAIM_DIV_55
lypinator	0:bb348c97df44	2204	* @arg @ref LL_RCC_PLLSAIM_DIV_56
lypinator	0:bb348c97df44	2205	* @arg @ref LL_RCC_PLLSAIM_DIV_57
lypinator	0:bb348c97df44	2206	* @arg @ref LL_RCC_PLLSAIM_DIV_58
lypinator	0:bb348c97df44	2207	* @arg @ref LL_RCC_PLLSAIM_DIV_59
lypinator	0:bb348c97df44	2208	* @arg @ref LL_RCC_PLLSAIM_DIV_60
lypinator	0:bb348c97df44	2209	* @arg @ref LL_RCC_PLLSAIM_DIV_61
lypinator	0:bb348c97df44	2210	* @arg @ref LL_RCC_PLLSAIM_DIV_62
lypinator	0:bb348c97df44	2211	* @arg @ref LL_RCC_PLLSAIM_DIV_63
lypinator	0:bb348c97df44	2212	* @param __PLLSAIN__ Between 49/50(*) and 432
lypinator	0:bb348c97df44	2213	*
lypinator	0:bb348c97df44	2214	* (*) value not defined in all devices.
lypinator	0:bb348c97df44	2215	* @param __PLLSAIQ__ This parameter can be one of the following values:
lypinator	0:bb348c97df44	2216	* @arg @ref LL_RCC_PLLSAIQ_DIV_2
lypinator	0:bb348c97df44	2217	* @arg @ref LL_RCC_PLLSAIQ_DIV_3
lypinator	0:bb348c97df44	2218	* @arg @ref LL_RCC_PLLSAIQ_DIV_4
lypinator	0:bb348c97df44	2219	* @arg @ref LL_RCC_PLLSAIQ_DIV_5
lypinator	0:bb348c97df44	2220	* @arg @ref LL_RCC_PLLSAIQ_DIV_6
lypinator	0:bb348c97df44	2221	* @arg @ref LL_RCC_PLLSAIQ_DIV_7
lypinator	0:bb348c97df44	2222	* @arg @ref LL_RCC_PLLSAIQ_DIV_8
lypinator	0:bb348c97df44	2223	* @arg @ref LL_RCC_PLLSAIQ_DIV_9
lypinator	0:bb348c97df44	2224	* @arg @ref LL_RCC_PLLSAIQ_DIV_10
lypinator	0:bb348c97df44	2225	* @arg @ref LL_RCC_PLLSAIQ_DIV_11
lypinator	0:bb348c97df44	2226	* @arg @ref LL_RCC_PLLSAIQ_DIV_12
lypinator	0:bb348c97df44	2227	* @arg @ref LL_RCC_PLLSAIQ_DIV_13
lypinator	0:bb348c97df44	2228	* @arg @ref LL_RCC_PLLSAIQ_DIV_14
lypinator	0:bb348c97df44	2229	* @arg @ref LL_RCC_PLLSAIQ_DIV_15
lypinator	0:bb348c97df44	2230	* @param __PLLSAIDIVQ__ This parameter can be one of the following values:
lypinator	0:bb348c97df44	2231	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_1
lypinator	0:bb348c97df44	2232	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_2
lypinator	0:bb348c97df44	2233	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_3
lypinator	0:bb348c97df44	2234	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_4
lypinator	0:bb348c97df44	2235	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_5
lypinator	0:bb348c97df44	2236	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_6
lypinator	0:bb348c97df44	2237	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_7
lypinator	0:bb348c97df44	2238	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_8
lypinator	0:bb348c97df44	2239	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_9
lypinator	0:bb348c97df44	2240	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_10
lypinator	0:bb348c97df44	2241	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_11
lypinator	0:bb348c97df44	2242	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_12
lypinator	0:bb348c97df44	2243	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_13
lypinator	0:bb348c97df44	2244	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_14
lypinator	0:bb348c97df44	2245	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_15
lypinator	0:bb348c97df44	2246	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_16
lypinator	0:bb348c97df44	2247	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_17
lypinator	0:bb348c97df44	2248	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_18
lypinator	0:bb348c97df44	2249	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_19
lypinator	0:bb348c97df44	2250	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_20
lypinator	0:bb348c97df44	2251	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_21
lypinator	0:bb348c97df44	2252	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_22
lypinator	0:bb348c97df44	2253	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_23
lypinator	0:bb348c97df44	2254	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_24
lypinator	0:bb348c97df44	2255	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_25
lypinator	0:bb348c97df44	2256	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_26
lypinator	0:bb348c97df44	2257	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_27
lypinator	0:bb348c97df44	2258	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_28
lypinator	0:bb348c97df44	2259	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_29
lypinator	0:bb348c97df44	2260	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_30
lypinator	0:bb348c97df44	2261	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_31
lypinator	0:bb348c97df44	2262	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_32
lypinator	0:bb348c97df44	2263	* @retval PLLSAI clock frequency (in Hz)
lypinator	0:bb348c97df44	2264	*/
lypinator	0:bb348c97df44	2265	#define __LL_RCC_CALC_PLLSAI_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAIN__, __PLLSAIQ__, __PLLSAIDIVQ__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLSAIN__) / \
lypinator	0:bb348c97df44	2266	(((__PLLSAIQ__) >> RCC_PLLSAICFGR_PLLSAIQ_Pos) * (((__PLLSAIDIVQ__) >> RCC_DCKCFGR_PLLSAIDIVQ_Pos) + 1U)))
lypinator	0:bb348c97df44	2267
lypinator	0:bb348c97df44	2268	#if defined(RCC_PLLSAICFGR_PLLSAIP)
lypinator	0:bb348c97df44	2269	/**
lypinator	0:bb348c97df44	2270	* @brief Helper macro to calculate the PLLSAI frequency used on 48Mhz domain
lypinator	0:bb348c97df44	2271	* @note ex: @ref __LL_RCC_CALC_PLLSAI_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI_GetDivider (),
lypinator	0:bb348c97df44	2272	* @ref LL_RCC_PLLSAI_GetN (), @ref LL_RCC_PLLSAI_GetP ());
lypinator	0:bb348c97df44	2273	* @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
lypinator	0:bb348c97df44	2274	* @param __PLLM__ This parameter can be one of the following values:
lypinator	0:bb348c97df44	2275	* @arg @ref LL_RCC_PLLSAIM_DIV_2
lypinator	0:bb348c97df44	2276	* @arg @ref LL_RCC_PLLSAIM_DIV_3
lypinator	0:bb348c97df44	2277	* @arg @ref LL_RCC_PLLSAIM_DIV_4
lypinator	0:bb348c97df44	2278	* @arg @ref LL_RCC_PLLSAIM_DIV_5
lypinator	0:bb348c97df44	2279	* @arg @ref LL_RCC_PLLSAIM_DIV_6
lypinator	0:bb348c97df44	2280	* @arg @ref LL_RCC_PLLSAIM_DIV_7
lypinator	0:bb348c97df44	2281	* @arg @ref LL_RCC_PLLSAIM_DIV_8
lypinator	0:bb348c97df44	2282	* @arg @ref LL_RCC_PLLSAIM_DIV_9
lypinator	0:bb348c97df44	2283	* @arg @ref LL_RCC_PLLSAIM_DIV_10
lypinator	0:bb348c97df44	2284	* @arg @ref LL_RCC_PLLSAIM_DIV_11
lypinator	0:bb348c97df44	2285	* @arg @ref LL_RCC_PLLSAIM_DIV_12
lypinator	0:bb348c97df44	2286	* @arg @ref LL_RCC_PLLSAIM_DIV_13
lypinator	0:bb348c97df44	2287	* @arg @ref LL_RCC_PLLSAIM_DIV_14
lypinator	0:bb348c97df44	2288	* @arg @ref LL_RCC_PLLSAIM_DIV_15
lypinator	0:bb348c97df44	2289	* @arg @ref LL_RCC_PLLSAIM_DIV_16
lypinator	0:bb348c97df44	2290	* @arg @ref LL_RCC_PLLSAIM_DIV_17
lypinator	0:bb348c97df44	2291	* @arg @ref LL_RCC_PLLSAIM_DIV_18
lypinator	0:bb348c97df44	2292	* @arg @ref LL_RCC_PLLSAIM_DIV_19
lypinator	0:bb348c97df44	2293	* @arg @ref LL_RCC_PLLSAIM_DIV_20
lypinator	0:bb348c97df44	2294	* @arg @ref LL_RCC_PLLSAIM_DIV_21
lypinator	0:bb348c97df44	2295	* @arg @ref LL_RCC_PLLSAIM_DIV_22
lypinator	0:bb348c97df44	2296	* @arg @ref LL_RCC_PLLSAIM_DIV_23
lypinator	0:bb348c97df44	2297	* @arg @ref LL_RCC_PLLSAIM_DIV_24
lypinator	0:bb348c97df44	2298	* @arg @ref LL_RCC_PLLSAIM_DIV_25
lypinator	0:bb348c97df44	2299	* @arg @ref LL_RCC_PLLSAIM_DIV_26
lypinator	0:bb348c97df44	2300	* @arg @ref LL_RCC_PLLSAIM_DIV_27
lypinator	0:bb348c97df44	2301	* @arg @ref LL_RCC_PLLSAIM_DIV_28
lypinator	0:bb348c97df44	2302	* @arg @ref LL_RCC_PLLSAIM_DIV_29
lypinator	0:bb348c97df44	2303	* @arg @ref LL_RCC_PLLSAIM_DIV_30
lypinator	0:bb348c97df44	2304	* @arg @ref LL_RCC_PLLSAIM_DIV_31
lypinator	0:bb348c97df44	2305	* @arg @ref LL_RCC_PLLSAIM_DIV_32
lypinator	0:bb348c97df44	2306	* @arg @ref LL_RCC_PLLSAIM_DIV_33
lypinator	0:bb348c97df44	2307	* @arg @ref LL_RCC_PLLSAIM_DIV_34
lypinator	0:bb348c97df44	2308	* @arg @ref LL_RCC_PLLSAIM_DIV_35
lypinator	0:bb348c97df44	2309	* @arg @ref LL_RCC_PLLSAIM_DIV_36
lypinator	0:bb348c97df44	2310	* @arg @ref LL_RCC_PLLSAIM_DIV_37
lypinator	0:bb348c97df44	2311	* @arg @ref LL_RCC_PLLSAIM_DIV_38
lypinator	0:bb348c97df44	2312	* @arg @ref LL_RCC_PLLSAIM_DIV_39
lypinator	0:bb348c97df44	2313	* @arg @ref LL_RCC_PLLSAIM_DIV_40
lypinator	0:bb348c97df44	2314	* @arg @ref LL_RCC_PLLSAIM_DIV_41
lypinator	0:bb348c97df44	2315	* @arg @ref LL_RCC_PLLSAIM_DIV_42
lypinator	0:bb348c97df44	2316	* @arg @ref LL_RCC_PLLSAIM_DIV_43
lypinator	0:bb348c97df44	2317	* @arg @ref LL_RCC_PLLSAIM_DIV_44
lypinator	0:bb348c97df44	2318	* @arg @ref LL_RCC_PLLSAIM_DIV_45
lypinator	0:bb348c97df44	2319	* @arg @ref LL_RCC_PLLSAIM_DIV_46
lypinator	0:bb348c97df44	2320	* @arg @ref LL_RCC_PLLSAIM_DIV_47
lypinator	0:bb348c97df44	2321	* @arg @ref LL_RCC_PLLSAIM_DIV_48
lypinator	0:bb348c97df44	2322	* @arg @ref LL_RCC_PLLSAIM_DIV_49
lypinator	0:bb348c97df44	2323	* @arg @ref LL_RCC_PLLSAIM_DIV_50
lypinator	0:bb348c97df44	2324	* @arg @ref LL_RCC_PLLSAIM_DIV_51
lypinator	0:bb348c97df44	2325	* @arg @ref LL_RCC_PLLSAIM_DIV_52
lypinator	0:bb348c97df44	2326	* @arg @ref LL_RCC_PLLSAIM_DIV_53
lypinator	0:bb348c97df44	2327	* @arg @ref LL_RCC_PLLSAIM_DIV_54
lypinator	0:bb348c97df44	2328	* @arg @ref LL_RCC_PLLSAIM_DIV_55
lypinator	0:bb348c97df44	2329	* @arg @ref LL_RCC_PLLSAIM_DIV_56
lypinator	0:bb348c97df44	2330	* @arg @ref LL_RCC_PLLSAIM_DIV_57
lypinator	0:bb348c97df44	2331	* @arg @ref LL_RCC_PLLSAIM_DIV_58
lypinator	0:bb348c97df44	2332	* @arg @ref LL_RCC_PLLSAIM_DIV_59
lypinator	0:bb348c97df44	2333	* @arg @ref LL_RCC_PLLSAIM_DIV_60
lypinator	0:bb348c97df44	2334	* @arg @ref LL_RCC_PLLSAIM_DIV_61
lypinator	0:bb348c97df44	2335	* @arg @ref LL_RCC_PLLSAIM_DIV_62
lypinator	0:bb348c97df44	2336	* @arg @ref LL_RCC_PLLSAIM_DIV_63
lypinator	0:bb348c97df44	2337	* @param __PLLSAIN__ Between 50 and 432
lypinator	0:bb348c97df44	2338	* @param __PLLSAIP__ This parameter can be one of the following values:
lypinator	0:bb348c97df44	2339	* @arg @ref LL_RCC_PLLSAIP_DIV_2
lypinator	0:bb348c97df44	2340	* @arg @ref LL_RCC_PLLSAIP_DIV_4
lypinator	0:bb348c97df44	2341	* @arg @ref LL_RCC_PLLSAIP_DIV_6
lypinator	0:bb348c97df44	2342	* @arg @ref LL_RCC_PLLSAIP_DIV_8
lypinator	0:bb348c97df44	2343	* @retval PLLSAI clock frequency (in Hz)
lypinator	0:bb348c97df44	2344	*/
lypinator	0:bb348c97df44	2345	#define __LL_RCC_CALC_PLLSAI_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAIN__, __PLLSAIP__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLSAIN__) / \
lypinator	0:bb348c97df44	2346	((((__PLLSAIP__) >> RCC_PLLSAICFGR_PLLSAIP_Pos) + 1U) * 2U))
lypinator	0:bb348c97df44	2347	#endif /* RCC_PLLSAICFGR_PLLSAIP */
lypinator	0:bb348c97df44	2348
lypinator	0:bb348c97df44	2349	#if defined(LTDC)
lypinator	0:bb348c97df44	2350	/**
lypinator	0:bb348c97df44	2351	* @brief Helper macro to calculate the PLLSAI frequency used for LTDC domain
lypinator	0:bb348c97df44	2352	* @note ex: @ref __LL_RCC_CALC_PLLSAI_LTDC_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI_GetDivider (),
lypinator	0:bb348c97df44	2353	* @ref LL_RCC_PLLSAI_GetN (), @ref LL_RCC_PLLSAI_GetR (), @ref LL_RCC_PLLSAI_GetDIVR ());
lypinator	0:bb348c97df44	2354	* @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
lypinator	0:bb348c97df44	2355	* @param __PLLM__ This parameter can be one of the following values:
lypinator	0:bb348c97df44	2356	* @arg @ref LL_RCC_PLLSAIM_DIV_2
lypinator	0:bb348c97df44	2357	* @arg @ref LL_RCC_PLLSAIM_DIV_3
lypinator	0:bb348c97df44	2358	* @arg @ref LL_RCC_PLLSAIM_DIV_4
lypinator	0:bb348c97df44	2359	* @arg @ref LL_RCC_PLLSAIM_DIV_5
lypinator	0:bb348c97df44	2360	* @arg @ref LL_RCC_PLLSAIM_DIV_6
lypinator	0:bb348c97df44	2361	* @arg @ref LL_RCC_PLLSAIM_DIV_7
lypinator	0:bb348c97df44	2362	* @arg @ref LL_RCC_PLLSAIM_DIV_8
lypinator	0:bb348c97df44	2363	* @arg @ref LL_RCC_PLLSAIM_DIV_9
lypinator	0:bb348c97df44	2364	* @arg @ref LL_RCC_PLLSAIM_DIV_10
lypinator	0:bb348c97df44	2365	* @arg @ref LL_RCC_PLLSAIM_DIV_11
lypinator	0:bb348c97df44	2366	* @arg @ref LL_RCC_PLLSAIM_DIV_12
lypinator	0:bb348c97df44	2367	* @arg @ref LL_RCC_PLLSAIM_DIV_13
lypinator	0:bb348c97df44	2368	* @arg @ref LL_RCC_PLLSAIM_DIV_14
lypinator	0:bb348c97df44	2369	* @arg @ref LL_RCC_PLLSAIM_DIV_15
lypinator	0:bb348c97df44	2370	* @arg @ref LL_RCC_PLLSAIM_DIV_16
lypinator	0:bb348c97df44	2371	* @arg @ref LL_RCC_PLLSAIM_DIV_17
lypinator	0:bb348c97df44	2372	* @arg @ref LL_RCC_PLLSAIM_DIV_18
lypinator	0:bb348c97df44	2373	* @arg @ref LL_RCC_PLLSAIM_DIV_19
lypinator	0:bb348c97df44	2374	* @arg @ref LL_RCC_PLLSAIM_DIV_20
lypinator	0:bb348c97df44	2375	* @arg @ref LL_RCC_PLLSAIM_DIV_21
lypinator	0:bb348c97df44	2376	* @arg @ref LL_RCC_PLLSAIM_DIV_22
lypinator	0:bb348c97df44	2377	* @arg @ref LL_RCC_PLLSAIM_DIV_23
lypinator	0:bb348c97df44	2378	* @arg @ref LL_RCC_PLLSAIM_DIV_24
lypinator	0:bb348c97df44	2379	* @arg @ref LL_RCC_PLLSAIM_DIV_25
lypinator	0:bb348c97df44	2380	* @arg @ref LL_RCC_PLLSAIM_DIV_26
lypinator	0:bb348c97df44	2381	* @arg @ref LL_RCC_PLLSAIM_DIV_27
lypinator	0:bb348c97df44	2382	* @arg @ref LL_RCC_PLLSAIM_DIV_28
lypinator	0:bb348c97df44	2383	* @arg @ref LL_RCC_PLLSAIM_DIV_29
lypinator	0:bb348c97df44	2384	* @arg @ref LL_RCC_PLLSAIM_DIV_30
lypinator	0:bb348c97df44	2385	* @arg @ref LL_RCC_PLLSAIM_DIV_31
lypinator	0:bb348c97df44	2386	* @arg @ref LL_RCC_PLLSAIM_DIV_32
lypinator	0:bb348c97df44	2387	* @arg @ref LL_RCC_PLLSAIM_DIV_33
lypinator	0:bb348c97df44	2388	* @arg @ref LL_RCC_PLLSAIM_DIV_34
lypinator	0:bb348c97df44	2389	* @arg @ref LL_RCC_PLLSAIM_DIV_35
lypinator	0:bb348c97df44	2390	* @arg @ref LL_RCC_PLLSAIM_DIV_36
lypinator	0:bb348c97df44	2391	* @arg @ref LL_RCC_PLLSAIM_DIV_37
lypinator	0:bb348c97df44	2392	* @arg @ref LL_RCC_PLLSAIM_DIV_38
lypinator	0:bb348c97df44	2393	* @arg @ref LL_RCC_PLLSAIM_DIV_39
lypinator	0:bb348c97df44	2394	* @arg @ref LL_RCC_PLLSAIM_DIV_40
lypinator	0:bb348c97df44	2395	* @arg @ref LL_RCC_PLLSAIM_DIV_41
lypinator	0:bb348c97df44	2396	* @arg @ref LL_RCC_PLLSAIM_DIV_42
lypinator	0:bb348c97df44	2397	* @arg @ref LL_RCC_PLLSAIM_DIV_43
lypinator	0:bb348c97df44	2398	* @arg @ref LL_RCC_PLLSAIM_DIV_44
lypinator	0:bb348c97df44	2399	* @arg @ref LL_RCC_PLLSAIM_DIV_45
lypinator	0:bb348c97df44	2400	* @arg @ref LL_RCC_PLLSAIM_DIV_46
lypinator	0:bb348c97df44	2401	* @arg @ref LL_RCC_PLLSAIM_DIV_47
lypinator	0:bb348c97df44	2402	* @arg @ref LL_RCC_PLLSAIM_DIV_48
lypinator	0:bb348c97df44	2403	* @arg @ref LL_RCC_PLLSAIM_DIV_49
lypinator	0:bb348c97df44	2404	* @arg @ref LL_RCC_PLLSAIM_DIV_50
lypinator	0:bb348c97df44	2405	* @arg @ref LL_RCC_PLLSAIM_DIV_51
lypinator	0:bb348c97df44	2406	* @arg @ref LL_RCC_PLLSAIM_DIV_52
lypinator	0:bb348c97df44	2407	* @arg @ref LL_RCC_PLLSAIM_DIV_53
lypinator	0:bb348c97df44	2408	* @arg @ref LL_RCC_PLLSAIM_DIV_54
lypinator	0:bb348c97df44	2409	* @arg @ref LL_RCC_PLLSAIM_DIV_55
lypinator	0:bb348c97df44	2410	* @arg @ref LL_RCC_PLLSAIM_DIV_56
lypinator	0:bb348c97df44	2411	* @arg @ref LL_RCC_PLLSAIM_DIV_57
lypinator	0:bb348c97df44	2412	* @arg @ref LL_RCC_PLLSAIM_DIV_58
lypinator	0:bb348c97df44	2413	* @arg @ref LL_RCC_PLLSAIM_DIV_59
lypinator	0:bb348c97df44	2414	* @arg @ref LL_RCC_PLLSAIM_DIV_60
lypinator	0:bb348c97df44	2415	* @arg @ref LL_RCC_PLLSAIM_DIV_61
lypinator	0:bb348c97df44	2416	* @arg @ref LL_RCC_PLLSAIM_DIV_62
lypinator	0:bb348c97df44	2417	* @arg @ref LL_RCC_PLLSAIM_DIV_63
lypinator	0:bb348c97df44	2418	* @param __PLLSAIN__ Between 49/50(*) and 432
lypinator	0:bb348c97df44	2419	*
lypinator	0:bb348c97df44	2420	* (*) value not defined in all devices.
lypinator	0:bb348c97df44	2421	* @param __PLLSAIR__ This parameter can be one of the following values:
lypinator	0:bb348c97df44	2422	* @arg @ref LL_RCC_PLLSAIR_DIV_2
lypinator	0:bb348c97df44	2423	* @arg @ref LL_RCC_PLLSAIR_DIV_3
lypinator	0:bb348c97df44	2424	* @arg @ref LL_RCC_PLLSAIR_DIV_4
lypinator	0:bb348c97df44	2425	* @arg @ref LL_RCC_PLLSAIR_DIV_5
lypinator	0:bb348c97df44	2426	* @arg @ref LL_RCC_PLLSAIR_DIV_6
lypinator	0:bb348c97df44	2427	* @arg @ref LL_RCC_PLLSAIR_DIV_7
lypinator	0:bb348c97df44	2428	* @param __PLLSAIDIVR__ This parameter can be one of the following values:
lypinator	0:bb348c97df44	2429	* @arg @ref LL_RCC_PLLSAIDIVR_DIV_2
lypinator	0:bb348c97df44	2430	* @arg @ref LL_RCC_PLLSAIDIVR_DIV_4
lypinator	0:bb348c97df44	2431	* @arg @ref LL_RCC_PLLSAIDIVR_DIV_8
lypinator	0:bb348c97df44	2432	* @arg @ref LL_RCC_PLLSAIDIVR_DIV_16
lypinator	0:bb348c97df44	2433	* @retval PLLSAI clock frequency (in Hz)
lypinator	0:bb348c97df44	2434	*/
lypinator	0:bb348c97df44	2435	#define __LL_RCC_CALC_PLLSAI_LTDC_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAIN__, __PLLSAIR__, __PLLSAIDIVR__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLSAIN__) / \
lypinator	0:bb348c97df44	2436	(((__PLLSAIR__) >> RCC_PLLSAICFGR_PLLSAIR_Pos) * (aRCC_PLLSAIDIVRPrescTable[(__PLLSAIDIVR__) >> RCC_DCKCFGR_PLLSAIDIVR_Pos])))
lypinator	0:bb348c97df44	2437	#endif /* LTDC */
lypinator	0:bb348c97df44	2438	#endif /* RCC_PLLSAI_SUPPORT */
lypinator	0:bb348c97df44	2439
lypinator	0:bb348c97df44	2440	#if defined(RCC_PLLI2S_SUPPORT)
lypinator	0:bb348c97df44	2441	#if defined(RCC_DCKCFGR_PLLI2SDIVQ) \|\| defined(RCC_DCKCFGR_PLLI2SDIVR)
lypinator	0:bb348c97df44	2442	/**
lypinator	0:bb348c97df44	2443	* @brief Helper macro to calculate the PLLI2S frequency used for SAI domain
lypinator	0:bb348c97df44	2444	* @note ex: @ref __LL_RCC_CALC_PLLI2S_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLLI2S_GetDivider (),
lypinator	0:bb348c97df44	2445	* @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetQ (), @ref LL_RCC_PLLI2S_GetDIVQ ());
lypinator	0:bb348c97df44	2446	* @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
lypinator	0:bb348c97df44	2447	* @param __PLLM__ This parameter can be one of the following values:
lypinator	0:bb348c97df44	2448	* @arg @ref LL_RCC_PLLI2SM_DIV_2
lypinator	0:bb348c97df44	2449	* @arg @ref LL_RCC_PLLI2SM_DIV_3
lypinator	0:bb348c97df44	2450	* @arg @ref LL_RCC_PLLI2SM_DIV_4
lypinator	0:bb348c97df44	2451	* @arg @ref LL_RCC_PLLI2SM_DIV_5
lypinator	0:bb348c97df44	2452	* @arg @ref LL_RCC_PLLI2SM_DIV_6
lypinator	0:bb348c97df44	2453	* @arg @ref LL_RCC_PLLI2SM_DIV_7
lypinator	0:bb348c97df44	2454	* @arg @ref LL_RCC_PLLI2SM_DIV_8
lypinator	0:bb348c97df44	2455	* @arg @ref LL_RCC_PLLI2SM_DIV_9
lypinator	0:bb348c97df44	2456	* @arg @ref LL_RCC_PLLI2SM_DIV_10
lypinator	0:bb348c97df44	2457	* @arg @ref LL_RCC_PLLI2SM_DIV_11
lypinator	0:bb348c97df44	2458	* @arg @ref LL_RCC_PLLI2SM_DIV_12
lypinator	0:bb348c97df44	2459	* @arg @ref LL_RCC_PLLI2SM_DIV_13
lypinator	0:bb348c97df44	2460	* @arg @ref LL_RCC_PLLI2SM_DIV_14
lypinator	0:bb348c97df44	2461	* @arg @ref LL_RCC_PLLI2SM_DIV_15
lypinator	0:bb348c97df44	2462	* @arg @ref LL_RCC_PLLI2SM_DIV_16
lypinator	0:bb348c97df44	2463	* @arg @ref LL_RCC_PLLI2SM_DIV_17
lypinator	0:bb348c97df44	2464	* @arg @ref LL_RCC_PLLI2SM_DIV_18
lypinator	0:bb348c97df44	2465	* @arg @ref LL_RCC_PLLI2SM_DIV_19
lypinator	0:bb348c97df44	2466	* @arg @ref LL_RCC_PLLI2SM_DIV_20
lypinator	0:bb348c97df44	2467	* @arg @ref LL_RCC_PLLI2SM_DIV_21
lypinator	0:bb348c97df44	2468	* @arg @ref LL_RCC_PLLI2SM_DIV_22
lypinator	0:bb348c97df44	2469	* @arg @ref LL_RCC_PLLI2SM_DIV_23
lypinator	0:bb348c97df44	2470	* @arg @ref LL_RCC_PLLI2SM_DIV_24
lypinator	0:bb348c97df44	2471	* @arg @ref LL_RCC_PLLI2SM_DIV_25
lypinator	0:bb348c97df44	2472	* @arg @ref LL_RCC_PLLI2SM_DIV_26
lypinator	0:bb348c97df44	2473	* @arg @ref LL_RCC_PLLI2SM_DIV_27
lypinator	0:bb348c97df44	2474	* @arg @ref LL_RCC_PLLI2SM_DIV_28
lypinator	0:bb348c97df44	2475	* @arg @ref LL_RCC_PLLI2SM_DIV_29
lypinator	0:bb348c97df44	2476	* @arg @ref LL_RCC_PLLI2SM_DIV_30
lypinator	0:bb348c97df44	2477	* @arg @ref LL_RCC_PLLI2SM_DIV_31
lypinator	0:bb348c97df44	2478	* @arg @ref LL_RCC_PLLI2SM_DIV_32
lypinator	0:bb348c97df44	2479	* @arg @ref LL_RCC_PLLI2SM_DIV_33
lypinator	0:bb348c97df44	2480	* @arg @ref LL_RCC_PLLI2SM_DIV_34
lypinator	0:bb348c97df44	2481	* @arg @ref LL_RCC_PLLI2SM_DIV_35
lypinator	0:bb348c97df44	2482	* @arg @ref LL_RCC_PLLI2SM_DIV_36
lypinator	0:bb348c97df44	2483	* @arg @ref LL_RCC_PLLI2SM_DIV_37
lypinator	0:bb348c97df44	2484	* @arg @ref LL_RCC_PLLI2SM_DIV_38
lypinator	0:bb348c97df44	2485	* @arg @ref LL_RCC_PLLI2SM_DIV_39
lypinator	0:bb348c97df44	2486	* @arg @ref LL_RCC_PLLI2SM_DIV_40
lypinator	0:bb348c97df44	2487	* @arg @ref LL_RCC_PLLI2SM_DIV_41
lypinator	0:bb348c97df44	2488	* @arg @ref LL_RCC_PLLI2SM_DIV_42
lypinator	0:bb348c97df44	2489	* @arg @ref LL_RCC_PLLI2SM_DIV_43
lypinator	0:bb348c97df44	2490	* @arg @ref LL_RCC_PLLI2SM_DIV_44
lypinator	0:bb348c97df44	2491	* @arg @ref LL_RCC_PLLI2SM_DIV_45
lypinator	0:bb348c97df44	2492	* @arg @ref LL_RCC_PLLI2SM_DIV_46
lypinator	0:bb348c97df44	2493	* @arg @ref LL_RCC_PLLI2SM_DIV_47
lypinator	0:bb348c97df44	2494	* @arg @ref LL_RCC_PLLI2SM_DIV_48
lypinator	0:bb348c97df44	2495	* @arg @ref LL_RCC_PLLI2SM_DIV_49
lypinator	0:bb348c97df44	2496	* @arg @ref LL_RCC_PLLI2SM_DIV_50
lypinator	0:bb348c97df44	2497	* @arg @ref LL_RCC_PLLI2SM_DIV_51
lypinator	0:bb348c97df44	2498	* @arg @ref LL_RCC_PLLI2SM_DIV_52
lypinator	0:bb348c97df44	2499	* @arg @ref LL_RCC_PLLI2SM_DIV_53
lypinator	0:bb348c97df44	2500	* @arg @ref LL_RCC_PLLI2SM_DIV_54
lypinator	0:bb348c97df44	2501	* @arg @ref LL_RCC_PLLI2SM_DIV_55
lypinator	0:bb348c97df44	2502	* @arg @ref LL_RCC_PLLI2SM_DIV_56
lypinator	0:bb348c97df44	2503	* @arg @ref LL_RCC_PLLI2SM_DIV_57
lypinator	0:bb348c97df44	2504	* @arg @ref LL_RCC_PLLI2SM_DIV_58
lypinator	0:bb348c97df44	2505	* @arg @ref LL_RCC_PLLI2SM_DIV_59
lypinator	0:bb348c97df44	2506	* @arg @ref LL_RCC_PLLI2SM_DIV_60
lypinator	0:bb348c97df44	2507	* @arg @ref LL_RCC_PLLI2SM_DIV_61
lypinator	0:bb348c97df44	2508	* @arg @ref LL_RCC_PLLI2SM_DIV_62
lypinator	0:bb348c97df44	2509	* @arg @ref LL_RCC_PLLI2SM_DIV_63
lypinator	0:bb348c97df44	2510	* @param __PLLI2SN__ Between 50/192(*) and 432
lypinator	0:bb348c97df44	2511	*
lypinator	0:bb348c97df44	2512	* (*) value not defined in all devices.
lypinator	0:bb348c97df44	2513	* @param __PLLI2SQ_R__ This parameter can be one of the following values:
lypinator	0:bb348c97df44	2514	* @arg @ref LL_RCC_PLLI2SQ_DIV_2 (*)
lypinator	0:bb348c97df44	2515	* @arg @ref LL_RCC_PLLI2SQ_DIV_3 (*)
lypinator	0:bb348c97df44	2516	* @arg @ref LL_RCC_PLLI2SQ_DIV_4 (*)
lypinator	0:bb348c97df44	2517	* @arg @ref LL_RCC_PLLI2SQ_DIV_5 (*)
lypinator	0:bb348c97df44	2518	* @arg @ref LL_RCC_PLLI2SQ_DIV_6 (*)
lypinator	0:bb348c97df44	2519	* @arg @ref LL_RCC_PLLI2SQ_DIV_7 (*)
lypinator	0:bb348c97df44	2520	* @arg @ref LL_RCC_PLLI2SQ_DIV_8 (*)
lypinator	0:bb348c97df44	2521	* @arg @ref LL_RCC_PLLI2SQ_DIV_9 (*)
lypinator	0:bb348c97df44	2522	* @arg @ref LL_RCC_PLLI2SQ_DIV_10 (*)
lypinator	0:bb348c97df44	2523	* @arg @ref LL_RCC_PLLI2SQ_DIV_11 (*)
lypinator	0:bb348c97df44	2524	* @arg @ref LL_RCC_PLLI2SQ_DIV_12 (*)
lypinator	0:bb348c97df44	2525	* @arg @ref LL_RCC_PLLI2SQ_DIV_13 (*)
lypinator	0:bb348c97df44	2526	* @arg @ref LL_RCC_PLLI2SQ_DIV_14 (*)
lypinator	0:bb348c97df44	2527	* @arg @ref LL_RCC_PLLI2SQ_DIV_15 (*)
lypinator	0:bb348c97df44	2528	* @arg @ref LL_RCC_PLLI2SR_DIV_2 (*)
lypinator	0:bb348c97df44	2529	* @arg @ref LL_RCC_PLLI2SR_DIV_3 (*)
lypinator	0:bb348c97df44	2530	* @arg @ref LL_RCC_PLLI2SR_DIV_4 (*)
lypinator	0:bb348c97df44	2531	* @arg @ref LL_RCC_PLLI2SR_DIV_5 (*)
lypinator	0:bb348c97df44	2532	* @arg @ref LL_RCC_PLLI2SR_DIV_6 (*)
lypinator	0:bb348c97df44	2533	* @arg @ref LL_RCC_PLLI2SR_DIV_7 (*)
lypinator	0:bb348c97df44	2534	*
lypinator	0:bb348c97df44	2535	* (*) value not defined in all devices.
lypinator	0:bb348c97df44	2536	* @param __PLLI2SDIVQ_R__ This parameter can be one of the following values:
lypinator	0:bb348c97df44	2537	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_1 (*)
lypinator	0:bb348c97df44	2538	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_2 (*)
lypinator	0:bb348c97df44	2539	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_3 (*)
lypinator	0:bb348c97df44	2540	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_4 (*)
lypinator	0:bb348c97df44	2541	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_5 (*)
lypinator	0:bb348c97df44	2542	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_6 (*)
lypinator	0:bb348c97df44	2543	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_7 (*)
lypinator	0:bb348c97df44	2544	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_8 (*)
lypinator	0:bb348c97df44	2545	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_9 (*)
lypinator	0:bb348c97df44	2546	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_10 (*)
lypinator	0:bb348c97df44	2547	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_11 (*)
lypinator	0:bb348c97df44	2548	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_12 (*)
lypinator	0:bb348c97df44	2549	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_13 (*)
lypinator	0:bb348c97df44	2550	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_14 (*)
lypinator	0:bb348c97df44	2551	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_15 (*)
lypinator	0:bb348c97df44	2552	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_16 (*)
lypinator	0:bb348c97df44	2553	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_17 (*)
lypinator	0:bb348c97df44	2554	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_18 (*)
lypinator	0:bb348c97df44	2555	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_19 (*)
lypinator	0:bb348c97df44	2556	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_20 (*)
lypinator	0:bb348c97df44	2557	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_21 (*)
lypinator	0:bb348c97df44	2558	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_22 (*)
lypinator	0:bb348c97df44	2559	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_23 (*)
lypinator	0:bb348c97df44	2560	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_24 (*)
lypinator	0:bb348c97df44	2561	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_25 (*)
lypinator	0:bb348c97df44	2562	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_26 (*)
lypinator	0:bb348c97df44	2563	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_27 (*)
lypinator	0:bb348c97df44	2564	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_28 (*)
lypinator	0:bb348c97df44	2565	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_29 (*)
lypinator	0:bb348c97df44	2566	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_30 (*)
lypinator	0:bb348c97df44	2567	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_31 (*)
lypinator	0:bb348c97df44	2568	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_32 (*)
lypinator	0:bb348c97df44	2569	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_1 (*)
lypinator	0:bb348c97df44	2570	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_2 (*)
lypinator	0:bb348c97df44	2571	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_3 (*)
lypinator	0:bb348c97df44	2572	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_4 (*)
lypinator	0:bb348c97df44	2573	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_5 (*)
lypinator	0:bb348c97df44	2574	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_6 (*)
lypinator	0:bb348c97df44	2575	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_7 (*)
lypinator	0:bb348c97df44	2576	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_8 (*)
lypinator	0:bb348c97df44	2577	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_9 (*)
lypinator	0:bb348c97df44	2578	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_10 (*)
lypinator	0:bb348c97df44	2579	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_11 (*)
lypinator	0:bb348c97df44	2580	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_12 (*)
lypinator	0:bb348c97df44	2581	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_13 (*)
lypinator	0:bb348c97df44	2582	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_14 (*)
lypinator	0:bb348c97df44	2583	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_15 (*)
lypinator	0:bb348c97df44	2584	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_16 (*)
lypinator	0:bb348c97df44	2585	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_17 (*)
lypinator	0:bb348c97df44	2586	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_18 (*)
lypinator	0:bb348c97df44	2587	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_19 (*)
lypinator	0:bb348c97df44	2588	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_20 (*)
lypinator	0:bb348c97df44	2589	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_21 (*)
lypinator	0:bb348c97df44	2590	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_22 (*)
lypinator	0:bb348c97df44	2591	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_23 (*)
lypinator	0:bb348c97df44	2592	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_24 (*)
lypinator	0:bb348c97df44	2593	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_25 (*)
lypinator	0:bb348c97df44	2594	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_26 (*)
lypinator	0:bb348c97df44	2595	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_27 (*)
lypinator	0:bb348c97df44	2596	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_28 (*)
lypinator	0:bb348c97df44	2597	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_29 (*)
lypinator	0:bb348c97df44	2598	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_30 (*)
lypinator	0:bb348c97df44	2599	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_31 (*)
lypinator	0:bb348c97df44	2600	*
lypinator	0:bb348c97df44	2601	* (*) value not defined in all devices.
lypinator	0:bb348c97df44	2602	* @retval PLLI2S clock frequency (in Hz)
lypinator	0:bb348c97df44	2603	*/
lypinator	0:bb348c97df44	2604	#if defined(RCC_DCKCFGR_PLLI2SDIVQ)
lypinator	0:bb348c97df44	2605	#define __LL_RCC_CALC_PLLI2S_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SQ_R__, __PLLI2SDIVQ_R__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \
lypinator	0:bb348c97df44	2606	(((__PLLI2SQ_R__) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos) * (((__PLLI2SDIVQ_R__) >> RCC_DCKCFGR_PLLI2SDIVQ_Pos) + 1U)))
lypinator	0:bb348c97df44	2607	#else
lypinator	0:bb348c97df44	2608	#define __LL_RCC_CALC_PLLI2S_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SQ_R__, __PLLI2SDIVQ_R__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \
lypinator	0:bb348c97df44	2609	(((__PLLI2SQ_R__) >> RCC_PLLI2SCFGR_PLLI2SR_Pos) * ((__PLLI2SDIVQ_R__) >> RCC_DCKCFGR_PLLI2SDIVR_Pos)))
lypinator	0:bb348c97df44	2610
lypinator	0:bb348c97df44	2611	#endif /* RCC_DCKCFGR_PLLI2SDIVQ */
lypinator	0:bb348c97df44	2612	#endif /* RCC_DCKCFGR_PLLI2SDIVQ \|\| RCC_DCKCFGR_PLLI2SDIVR */
lypinator	0:bb348c97df44	2613
lypinator	0:bb348c97df44	2614	#if defined(SPDIFRX)
lypinator	0:bb348c97df44	2615	/**
lypinator	0:bb348c97df44	2616	* @brief Helper macro to calculate the PLLI2S frequency used on SPDIFRX domain
lypinator	0:bb348c97df44	2617	* @note ex: @ref __LL_RCC_CALC_PLLI2S_SPDIFRX_FREQ (HSE_VALUE,@ref LL_RCC_PLLI2S_GetDivider (),
lypinator	0:bb348c97df44	2618	* @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetP ());
lypinator	0:bb348c97df44	2619	* @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
lypinator	0:bb348c97df44	2620	* @param __PLLM__ This parameter can be one of the following values:
lypinator	0:bb348c97df44	2621	* @arg @ref LL_RCC_PLLI2SM_DIV_2
lypinator	0:bb348c97df44	2622	* @arg @ref LL_RCC_PLLI2SM_DIV_3
lypinator	0:bb348c97df44	2623	* @arg @ref LL_RCC_PLLI2SM_DIV_4
lypinator	0:bb348c97df44	2624	* @arg @ref LL_RCC_PLLI2SM_DIV_5
lypinator	0:bb348c97df44	2625	* @arg @ref LL_RCC_PLLI2SM_DIV_6
lypinator	0:bb348c97df44	2626	* @arg @ref LL_RCC_PLLI2SM_DIV_7
lypinator	0:bb348c97df44	2627	* @arg @ref LL_RCC_PLLI2SM_DIV_8
lypinator	0:bb348c97df44	2628	* @arg @ref LL_RCC_PLLI2SM_DIV_9
lypinator	0:bb348c97df44	2629	* @arg @ref LL_RCC_PLLI2SM_DIV_10
lypinator	0:bb348c97df44	2630	* @arg @ref LL_RCC_PLLI2SM_DIV_11
lypinator	0:bb348c97df44	2631	* @arg @ref LL_RCC_PLLI2SM_DIV_12
lypinator	0:bb348c97df44	2632	* @arg @ref LL_RCC_PLLI2SM_DIV_13
lypinator	0:bb348c97df44	2633	* @arg @ref LL_RCC_PLLI2SM_DIV_14
lypinator	0:bb348c97df44	2634	* @arg @ref LL_RCC_PLLI2SM_DIV_15
lypinator	0:bb348c97df44	2635	* @arg @ref LL_RCC_PLLI2SM_DIV_16
lypinator	0:bb348c97df44	2636	* @arg @ref LL_RCC_PLLI2SM_DIV_17
lypinator	0:bb348c97df44	2637	* @arg @ref LL_RCC_PLLI2SM_DIV_18
lypinator	0:bb348c97df44	2638	* @arg @ref LL_RCC_PLLI2SM_DIV_19
lypinator	0:bb348c97df44	2639	* @arg @ref LL_RCC_PLLI2SM_DIV_20
lypinator	0:bb348c97df44	2640	* @arg @ref LL_RCC_PLLI2SM_DIV_21
lypinator	0:bb348c97df44	2641	* @arg @ref LL_RCC_PLLI2SM_DIV_22
lypinator	0:bb348c97df44	2642	* @arg @ref LL_RCC_PLLI2SM_DIV_23
lypinator	0:bb348c97df44	2643	* @arg @ref LL_RCC_PLLI2SM_DIV_24
lypinator	0:bb348c97df44	2644	* @arg @ref LL_RCC_PLLI2SM_DIV_25
lypinator	0:bb348c97df44	2645	* @arg @ref LL_RCC_PLLI2SM_DIV_26
lypinator	0:bb348c97df44	2646	* @arg @ref LL_RCC_PLLI2SM_DIV_27
lypinator	0:bb348c97df44	2647	* @arg @ref LL_RCC_PLLI2SM_DIV_28
lypinator	0:bb348c97df44	2648	* @arg @ref LL_RCC_PLLI2SM_DIV_29
lypinator	0:bb348c97df44	2649	* @arg @ref LL_RCC_PLLI2SM_DIV_30
lypinator	0:bb348c97df44	2650	* @arg @ref LL_RCC_PLLI2SM_DIV_31
lypinator	0:bb348c97df44	2651	* @arg @ref LL_RCC_PLLI2SM_DIV_32
lypinator	0:bb348c97df44	2652	* @arg @ref LL_RCC_PLLI2SM_DIV_33
lypinator	0:bb348c97df44	2653	* @arg @ref LL_RCC_PLLI2SM_DIV_34
lypinator	0:bb348c97df44	2654	* @arg @ref LL_RCC_PLLI2SM_DIV_35
lypinator	0:bb348c97df44	2655	* @arg @ref LL_RCC_PLLI2SM_DIV_36
lypinator	0:bb348c97df44	2656	* @arg @ref LL_RCC_PLLI2SM_DIV_37
lypinator	0:bb348c97df44	2657	* @arg @ref LL_RCC_PLLI2SM_DIV_38
lypinator	0:bb348c97df44	2658	* @arg @ref LL_RCC_PLLI2SM_DIV_39
lypinator	0:bb348c97df44	2659	* @arg @ref LL_RCC_PLLI2SM_DIV_40
lypinator	0:bb348c97df44	2660	* @arg @ref LL_RCC_PLLI2SM_DIV_41
lypinator	0:bb348c97df44	2661	* @arg @ref LL_RCC_PLLI2SM_DIV_42
lypinator	0:bb348c97df44	2662	* @arg @ref LL_RCC_PLLI2SM_DIV_43
lypinator	0:bb348c97df44	2663	* @arg @ref LL_RCC_PLLI2SM_DIV_44
lypinator	0:bb348c97df44	2664	* @arg @ref LL_RCC_PLLI2SM_DIV_45
lypinator	0:bb348c97df44	2665	* @arg @ref LL_RCC_PLLI2SM_DIV_46
lypinator	0:bb348c97df44	2666	* @arg @ref LL_RCC_PLLI2SM_DIV_47
lypinator	0:bb348c97df44	2667	* @arg @ref LL_RCC_PLLI2SM_DIV_48
lypinator	0:bb348c97df44	2668	* @arg @ref LL_RCC_PLLI2SM_DIV_49
lypinator	0:bb348c97df44	2669	* @arg @ref LL_RCC_PLLI2SM_DIV_50
lypinator	0:bb348c97df44	2670	* @arg @ref LL_RCC_PLLI2SM_DIV_51
lypinator	0:bb348c97df44	2671	* @arg @ref LL_RCC_PLLI2SM_DIV_52
lypinator	0:bb348c97df44	2672	* @arg @ref LL_RCC_PLLI2SM_DIV_53
lypinator	0:bb348c97df44	2673	* @arg @ref LL_RCC_PLLI2SM_DIV_54
lypinator	0:bb348c97df44	2674	* @arg @ref LL_RCC_PLLI2SM_DIV_55
lypinator	0:bb348c97df44	2675	* @arg @ref LL_RCC_PLLI2SM_DIV_56
lypinator	0:bb348c97df44	2676	* @arg @ref LL_RCC_PLLI2SM_DIV_57
lypinator	0:bb348c97df44	2677	* @arg @ref LL_RCC_PLLI2SM_DIV_58
lypinator	0:bb348c97df44	2678	* @arg @ref LL_RCC_PLLI2SM_DIV_59
lypinator	0:bb348c97df44	2679	* @arg @ref LL_RCC_PLLI2SM_DIV_60
lypinator	0:bb348c97df44	2680	* @arg @ref LL_RCC_PLLI2SM_DIV_61
lypinator	0:bb348c97df44	2681	* @arg @ref LL_RCC_PLLI2SM_DIV_62
lypinator	0:bb348c97df44	2682	* @arg @ref LL_RCC_PLLI2SM_DIV_63
lypinator	0:bb348c97df44	2683	* @param __PLLI2SN__ Between 50 and 432
lypinator	0:bb348c97df44	2684	* @param __PLLI2SP__ This parameter can be one of the following values:
lypinator	0:bb348c97df44	2685	* @arg @ref LL_RCC_PLLI2SP_DIV_2
lypinator	0:bb348c97df44	2686	* @arg @ref LL_RCC_PLLI2SP_DIV_4
lypinator	0:bb348c97df44	2687	* @arg @ref LL_RCC_PLLI2SP_DIV_6
lypinator	0:bb348c97df44	2688	* @arg @ref LL_RCC_PLLI2SP_DIV_8
lypinator	0:bb348c97df44	2689	* @retval PLLI2S clock frequency (in Hz)
lypinator	0:bb348c97df44	2690	*/
lypinator	0:bb348c97df44	2691	#define __LL_RCC_CALC_PLLI2S_SPDIFRX_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SP__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \
lypinator	0:bb348c97df44	2692	((((__PLLI2SP__) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) * 2U))
lypinator	0:bb348c97df44	2693
lypinator	0:bb348c97df44	2694	#endif /* SPDIFRX */
lypinator	0:bb348c97df44	2695
lypinator	0:bb348c97df44	2696	/**
lypinator	0:bb348c97df44	2697	* @brief Helper macro to calculate the PLLI2S frequency used for I2S domain
lypinator	0:bb348c97df44	2698	* @note ex: @ref __LL_RCC_CALC_PLLI2S_I2S_FREQ (HSE_VALUE,@ref LL_RCC_PLLI2S_GetDivider (),
lypinator	0:bb348c97df44	2699	* @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetR ());
lypinator	0:bb348c97df44	2700	* @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
lypinator	0:bb348c97df44	2701	* @param __PLLM__ This parameter can be one of the following values:
lypinator	0:bb348c97df44	2702	* @arg @ref LL_RCC_PLLI2SM_DIV_2
lypinator	0:bb348c97df44	2703	* @arg @ref LL_RCC_PLLI2SM_DIV_3
lypinator	0:bb348c97df44	2704	* @arg @ref LL_RCC_PLLI2SM_DIV_4
lypinator	0:bb348c97df44	2705	* @arg @ref LL_RCC_PLLI2SM_DIV_5
lypinator	0:bb348c97df44	2706	* @arg @ref LL_RCC_PLLI2SM_DIV_6
lypinator	0:bb348c97df44	2707	* @arg @ref LL_RCC_PLLI2SM_DIV_7
lypinator	0:bb348c97df44	2708	* @arg @ref LL_RCC_PLLI2SM_DIV_8
lypinator	0:bb348c97df44	2709	* @arg @ref LL_RCC_PLLI2SM_DIV_9
lypinator	0:bb348c97df44	2710	* @arg @ref LL_RCC_PLLI2SM_DIV_10
lypinator	0:bb348c97df44	2711	* @arg @ref LL_RCC_PLLI2SM_DIV_11
lypinator	0:bb348c97df44	2712	* @arg @ref LL_RCC_PLLI2SM_DIV_12
lypinator	0:bb348c97df44	2713	* @arg @ref LL_RCC_PLLI2SM_DIV_13
lypinator	0:bb348c97df44	2714	* @arg @ref LL_RCC_PLLI2SM_DIV_14
lypinator	0:bb348c97df44	2715	* @arg @ref LL_RCC_PLLI2SM_DIV_15
lypinator	0:bb348c97df44	2716	* @arg @ref LL_RCC_PLLI2SM_DIV_16
lypinator	0:bb348c97df44	2717	* @arg @ref LL_RCC_PLLI2SM_DIV_17
lypinator	0:bb348c97df44	2718	* @arg @ref LL_RCC_PLLI2SM_DIV_18
lypinator	0:bb348c97df44	2719	* @arg @ref LL_RCC_PLLI2SM_DIV_19
lypinator	0:bb348c97df44	2720	* @arg @ref LL_RCC_PLLI2SM_DIV_20
lypinator	0:bb348c97df44	2721	* @arg @ref LL_RCC_PLLI2SM_DIV_21
lypinator	0:bb348c97df44	2722	* @arg @ref LL_RCC_PLLI2SM_DIV_22
lypinator	0:bb348c97df44	2723	* @arg @ref LL_RCC_PLLI2SM_DIV_23
lypinator	0:bb348c97df44	2724	* @arg @ref LL_RCC_PLLI2SM_DIV_24
lypinator	0:bb348c97df44	2725	* @arg @ref LL_RCC_PLLI2SM_DIV_25
lypinator	0:bb348c97df44	2726	* @arg @ref LL_RCC_PLLI2SM_DIV_26
lypinator	0:bb348c97df44	2727	* @arg @ref LL_RCC_PLLI2SM_DIV_27
lypinator	0:bb348c97df44	2728	* @arg @ref LL_RCC_PLLI2SM_DIV_28
lypinator	0:bb348c97df44	2729	* @arg @ref LL_RCC_PLLI2SM_DIV_29
lypinator	0:bb348c97df44	2730	* @arg @ref LL_RCC_PLLI2SM_DIV_30
lypinator	0:bb348c97df44	2731	* @arg @ref LL_RCC_PLLI2SM_DIV_31
lypinator	0:bb348c97df44	2732	* @arg @ref LL_RCC_PLLI2SM_DIV_32
lypinator	0:bb348c97df44	2733	* @arg @ref LL_RCC_PLLI2SM_DIV_33
lypinator	0:bb348c97df44	2734	* @arg @ref LL_RCC_PLLI2SM_DIV_34
lypinator	0:bb348c97df44	2735	* @arg @ref LL_RCC_PLLI2SM_DIV_35
lypinator	0:bb348c97df44	2736	* @arg @ref LL_RCC_PLLI2SM_DIV_36
lypinator	0:bb348c97df44	2737	* @arg @ref LL_RCC_PLLI2SM_DIV_37
lypinator	0:bb348c97df44	2738	* @arg @ref LL_RCC_PLLI2SM_DIV_38
lypinator	0:bb348c97df44	2739	* @arg @ref LL_RCC_PLLI2SM_DIV_39
lypinator	0:bb348c97df44	2740	* @arg @ref LL_RCC_PLLI2SM_DIV_40
lypinator	0:bb348c97df44	2741	* @arg @ref LL_RCC_PLLI2SM_DIV_41
lypinator	0:bb348c97df44	2742	* @arg @ref LL_RCC_PLLI2SM_DIV_42
lypinator	0:bb348c97df44	2743	* @arg @ref LL_RCC_PLLI2SM_DIV_43
lypinator	0:bb348c97df44	2744	* @arg @ref LL_RCC_PLLI2SM_DIV_44
lypinator	0:bb348c97df44	2745	* @arg @ref LL_RCC_PLLI2SM_DIV_45
lypinator	0:bb348c97df44	2746	* @arg @ref LL_RCC_PLLI2SM_DIV_46
lypinator	0:bb348c97df44	2747	* @arg @ref LL_RCC_PLLI2SM_DIV_47
lypinator	0:bb348c97df44	2748	* @arg @ref LL_RCC_PLLI2SM_DIV_48
lypinator	0:bb348c97df44	2749	* @arg @ref LL_RCC_PLLI2SM_DIV_49
lypinator	0:bb348c97df44	2750	* @arg @ref LL_RCC_PLLI2SM_DIV_50
lypinator	0:bb348c97df44	2751	* @arg @ref LL_RCC_PLLI2SM_DIV_51
lypinator	0:bb348c97df44	2752	* @arg @ref LL_RCC_PLLI2SM_DIV_52
lypinator	0:bb348c97df44	2753	* @arg @ref LL_RCC_PLLI2SM_DIV_53
lypinator	0:bb348c97df44	2754	* @arg @ref LL_RCC_PLLI2SM_DIV_54
lypinator	0:bb348c97df44	2755	* @arg @ref LL_RCC_PLLI2SM_DIV_55
lypinator	0:bb348c97df44	2756	* @arg @ref LL_RCC_PLLI2SM_DIV_56
lypinator	0:bb348c97df44	2757	* @arg @ref LL_RCC_PLLI2SM_DIV_57
lypinator	0:bb348c97df44	2758	* @arg @ref LL_RCC_PLLI2SM_DIV_58
lypinator	0:bb348c97df44	2759	* @arg @ref LL_RCC_PLLI2SM_DIV_59
lypinator	0:bb348c97df44	2760	* @arg @ref LL_RCC_PLLI2SM_DIV_60
lypinator	0:bb348c97df44	2761	* @arg @ref LL_RCC_PLLI2SM_DIV_61
lypinator	0:bb348c97df44	2762	* @arg @ref LL_RCC_PLLI2SM_DIV_62
lypinator	0:bb348c97df44	2763	* @arg @ref LL_RCC_PLLI2SM_DIV_63
lypinator	0:bb348c97df44	2764	* @param __PLLI2SN__ Between 50/192(*) and 432
lypinator	0:bb348c97df44	2765	*
lypinator	0:bb348c97df44	2766	* (*) value not defined in all devices.
lypinator	0:bb348c97df44	2767	* @param __PLLI2SR__ This parameter can be one of the following values:
lypinator	0:bb348c97df44	2768	* @arg @ref LL_RCC_PLLI2SR_DIV_2
lypinator	0:bb348c97df44	2769	* @arg @ref LL_RCC_PLLI2SR_DIV_3
lypinator	0:bb348c97df44	2770	* @arg @ref LL_RCC_PLLI2SR_DIV_4
lypinator	0:bb348c97df44	2771	* @arg @ref LL_RCC_PLLI2SR_DIV_5
lypinator	0:bb348c97df44	2772	* @arg @ref LL_RCC_PLLI2SR_DIV_6
lypinator	0:bb348c97df44	2773	* @arg @ref LL_RCC_PLLI2SR_DIV_7
lypinator	0:bb348c97df44	2774	* @retval PLLI2S clock frequency (in Hz)
lypinator	0:bb348c97df44	2775	*/
lypinator	0:bb348c97df44	2776	#define __LL_RCC_CALC_PLLI2S_I2S_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SR__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \
lypinator	0:bb348c97df44	2777	((__PLLI2SR__) >> RCC_PLLI2SCFGR_PLLI2SR_Pos))
lypinator	0:bb348c97df44	2778
lypinator	0:bb348c97df44	2779	#if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
lypinator	0:bb348c97df44	2780	/**
lypinator	0:bb348c97df44	2781	* @brief Helper macro to calculate the PLLI2S frequency used for 48Mhz domain
lypinator	0:bb348c97df44	2782	* @note ex: @ref __LL_RCC_CALC_PLLI2S_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLLI2S_GetDivider (),
lypinator	0:bb348c97df44	2783	* @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetQ ());
lypinator	0:bb348c97df44	2784	* @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
lypinator	0:bb348c97df44	2785	* @param __PLLM__ This parameter can be one of the following values:
lypinator	0:bb348c97df44	2786	* @arg @ref LL_RCC_PLLI2SM_DIV_2
lypinator	0:bb348c97df44	2787	* @arg @ref LL_RCC_PLLI2SM_DIV_3
lypinator	0:bb348c97df44	2788	* @arg @ref LL_RCC_PLLI2SM_DIV_4
lypinator	0:bb348c97df44	2789	* @arg @ref LL_RCC_PLLI2SM_DIV_5
lypinator	0:bb348c97df44	2790	* @arg @ref LL_RCC_PLLI2SM_DIV_6
lypinator	0:bb348c97df44	2791	* @arg @ref LL_RCC_PLLI2SM_DIV_7
lypinator	0:bb348c97df44	2792	* @arg @ref LL_RCC_PLLI2SM_DIV_8
lypinator	0:bb348c97df44	2793	* @arg @ref LL_RCC_PLLI2SM_DIV_9
lypinator	0:bb348c97df44	2794	* @arg @ref LL_RCC_PLLI2SM_DIV_10
lypinator	0:bb348c97df44	2795	* @arg @ref LL_RCC_PLLI2SM_DIV_11
lypinator	0:bb348c97df44	2796	* @arg @ref LL_RCC_PLLI2SM_DIV_12
lypinator	0:bb348c97df44	2797	* @arg @ref LL_RCC_PLLI2SM_DIV_13
lypinator	0:bb348c97df44	2798	* @arg @ref LL_RCC_PLLI2SM_DIV_14
lypinator	0:bb348c97df44	2799	* @arg @ref LL_RCC_PLLI2SM_DIV_15
lypinator	0:bb348c97df44	2800	* @arg @ref LL_RCC_PLLI2SM_DIV_16
lypinator	0:bb348c97df44	2801	* @arg @ref LL_RCC_PLLI2SM_DIV_17
lypinator	0:bb348c97df44	2802	* @arg @ref LL_RCC_PLLI2SM_DIV_18
lypinator	0:bb348c97df44	2803	* @arg @ref LL_RCC_PLLI2SM_DIV_19
lypinator	0:bb348c97df44	2804	* @arg @ref LL_RCC_PLLI2SM_DIV_20
lypinator	0:bb348c97df44	2805	* @arg @ref LL_RCC_PLLI2SM_DIV_21
lypinator	0:bb348c97df44	2806	* @arg @ref LL_RCC_PLLI2SM_DIV_22
lypinator	0:bb348c97df44	2807	* @arg @ref LL_RCC_PLLI2SM_DIV_23
lypinator	0:bb348c97df44	2808	* @arg @ref LL_RCC_PLLI2SM_DIV_24
lypinator	0:bb348c97df44	2809	* @arg @ref LL_RCC_PLLI2SM_DIV_25
lypinator	0:bb348c97df44	2810	* @arg @ref LL_RCC_PLLI2SM_DIV_26
lypinator	0:bb348c97df44	2811	* @arg @ref LL_RCC_PLLI2SM_DIV_27
lypinator	0:bb348c97df44	2812	* @arg @ref LL_RCC_PLLI2SM_DIV_28
lypinator	0:bb348c97df44	2813	* @arg @ref LL_RCC_PLLI2SM_DIV_29
lypinator	0:bb348c97df44	2814	* @arg @ref LL_RCC_PLLI2SM_DIV_30
lypinator	0:bb348c97df44	2815	* @arg @ref LL_RCC_PLLI2SM_DIV_31
lypinator	0:bb348c97df44	2816	* @arg @ref LL_RCC_PLLI2SM_DIV_32
lypinator	0:bb348c97df44	2817	* @arg @ref LL_RCC_PLLI2SM_DIV_33
lypinator	0:bb348c97df44	2818	* @arg @ref LL_RCC_PLLI2SM_DIV_34
lypinator	0:bb348c97df44	2819	* @arg @ref LL_RCC_PLLI2SM_DIV_35
lypinator	0:bb348c97df44	2820	* @arg @ref LL_RCC_PLLI2SM_DIV_36
lypinator	0:bb348c97df44	2821	* @arg @ref LL_RCC_PLLI2SM_DIV_37
lypinator	0:bb348c97df44	2822	* @arg @ref LL_RCC_PLLI2SM_DIV_38
lypinator	0:bb348c97df44	2823	* @arg @ref LL_RCC_PLLI2SM_DIV_39
lypinator	0:bb348c97df44	2824	* @arg @ref LL_RCC_PLLI2SM_DIV_40
lypinator	0:bb348c97df44	2825	* @arg @ref LL_RCC_PLLI2SM_DIV_41
lypinator	0:bb348c97df44	2826	* @arg @ref LL_RCC_PLLI2SM_DIV_42
lypinator	0:bb348c97df44	2827	* @arg @ref LL_RCC_PLLI2SM_DIV_43
lypinator	0:bb348c97df44	2828	* @arg @ref LL_RCC_PLLI2SM_DIV_44
lypinator	0:bb348c97df44	2829	* @arg @ref LL_RCC_PLLI2SM_DIV_45
lypinator	0:bb348c97df44	2830	* @arg @ref LL_RCC_PLLI2SM_DIV_46
lypinator	0:bb348c97df44	2831	* @arg @ref LL_RCC_PLLI2SM_DIV_47
lypinator	0:bb348c97df44	2832	* @arg @ref LL_RCC_PLLI2SM_DIV_48
lypinator	0:bb348c97df44	2833	* @arg @ref LL_RCC_PLLI2SM_DIV_49
lypinator	0:bb348c97df44	2834	* @arg @ref LL_RCC_PLLI2SM_DIV_50
lypinator	0:bb348c97df44	2835	* @arg @ref LL_RCC_PLLI2SM_DIV_51
lypinator	0:bb348c97df44	2836	* @arg @ref LL_RCC_PLLI2SM_DIV_52
lypinator	0:bb348c97df44	2837	* @arg @ref LL_RCC_PLLI2SM_DIV_53
lypinator	0:bb348c97df44	2838	* @arg @ref LL_RCC_PLLI2SM_DIV_54
lypinator	0:bb348c97df44	2839	* @arg @ref LL_RCC_PLLI2SM_DIV_55
lypinator	0:bb348c97df44	2840	* @arg @ref LL_RCC_PLLI2SM_DIV_56
lypinator	0:bb348c97df44	2841	* @arg @ref LL_RCC_PLLI2SM_DIV_57
lypinator	0:bb348c97df44	2842	* @arg @ref LL_RCC_PLLI2SM_DIV_58
lypinator	0:bb348c97df44	2843	* @arg @ref LL_RCC_PLLI2SM_DIV_59
lypinator	0:bb348c97df44	2844	* @arg @ref LL_RCC_PLLI2SM_DIV_60
lypinator	0:bb348c97df44	2845	* @arg @ref LL_RCC_PLLI2SM_DIV_61
lypinator	0:bb348c97df44	2846	* @arg @ref LL_RCC_PLLI2SM_DIV_62
lypinator	0:bb348c97df44	2847	* @arg @ref LL_RCC_PLLI2SM_DIV_63
lypinator	0:bb348c97df44	2848	* @param __PLLI2SN__ Between 50 and 432
lypinator	0:bb348c97df44	2849	* @param __PLLI2SQ__ This parameter can be one of the following values:
lypinator	0:bb348c97df44	2850	* @arg @ref LL_RCC_PLLI2SQ_DIV_2
lypinator	0:bb348c97df44	2851	* @arg @ref LL_RCC_PLLI2SQ_DIV_3
lypinator	0:bb348c97df44	2852	* @arg @ref LL_RCC_PLLI2SQ_DIV_4
lypinator	0:bb348c97df44	2853	* @arg @ref LL_RCC_PLLI2SQ_DIV_5
lypinator	0:bb348c97df44	2854	* @arg @ref LL_RCC_PLLI2SQ_DIV_6
lypinator	0:bb348c97df44	2855	* @arg @ref LL_RCC_PLLI2SQ_DIV_7
lypinator	0:bb348c97df44	2856	* @arg @ref LL_RCC_PLLI2SQ_DIV_8
lypinator	0:bb348c97df44	2857	* @arg @ref LL_RCC_PLLI2SQ_DIV_9
lypinator	0:bb348c97df44	2858	* @arg @ref LL_RCC_PLLI2SQ_DIV_10
lypinator	0:bb348c97df44	2859	* @arg @ref LL_RCC_PLLI2SQ_DIV_11
lypinator	0:bb348c97df44	2860	* @arg @ref LL_RCC_PLLI2SQ_DIV_12
lypinator	0:bb348c97df44	2861	* @arg @ref LL_RCC_PLLI2SQ_DIV_13
lypinator	0:bb348c97df44	2862	* @arg @ref LL_RCC_PLLI2SQ_DIV_14
lypinator	0:bb348c97df44	2863	* @arg @ref LL_RCC_PLLI2SQ_DIV_15
lypinator	0:bb348c97df44	2864	* @retval PLLI2S clock frequency (in Hz)
lypinator	0:bb348c97df44	2865	*/
lypinator	0:bb348c97df44	2866	#define __LL_RCC_CALC_PLLI2S_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SQ__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \
lypinator	0:bb348c97df44	2867	((__PLLI2SQ__) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos))
lypinator	0:bb348c97df44	2868
lypinator	0:bb348c97df44	2869	#endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
lypinator	0:bb348c97df44	2870	#endif /* RCC_PLLI2S_SUPPORT */
lypinator	0:bb348c97df44	2871
lypinator	0:bb348c97df44	2872	/**
lypinator	0:bb348c97df44	2873	* @brief Helper macro to calculate the HCLK frequency
lypinator	0:bb348c97df44	2874	* @param __SYSCLKFREQ__ SYSCLK frequency (based on HSE/HSI/PLLCLK)
lypinator	0:bb348c97df44	2875	* @param __AHBPRESCALER__ This parameter can be one of the following values:
lypinator	0:bb348c97df44	2876	* @arg @ref LL_RCC_SYSCLK_DIV_1
lypinator	0:bb348c97df44	2877	* @arg @ref LL_RCC_SYSCLK_DIV_2
lypinator	0:bb348c97df44	2878	* @arg @ref LL_RCC_SYSCLK_DIV_4
lypinator	0:bb348c97df44	2879	* @arg @ref LL_RCC_SYSCLK_DIV_8
lypinator	0:bb348c97df44	2880	* @arg @ref LL_RCC_SYSCLK_DIV_16
lypinator	0:bb348c97df44	2881	* @arg @ref LL_RCC_SYSCLK_DIV_64
lypinator	0:bb348c97df44	2882	* @arg @ref LL_RCC_SYSCLK_DIV_128
lypinator	0:bb348c97df44	2883	* @arg @ref LL_RCC_SYSCLK_DIV_256
lypinator	0:bb348c97df44	2884	* @arg @ref LL_RCC_SYSCLK_DIV_512
lypinator	0:bb348c97df44	2885	* @retval HCLK clock frequency (in Hz)
lypinator	0:bb348c97df44	2886	*/
lypinator	0:bb348c97df44	2887	#define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos])
lypinator	0:bb348c97df44	2888
lypinator	0:bb348c97df44	2889	/**
lypinator	0:bb348c97df44	2890	* @brief Helper macro to calculate the PCLK1 frequency (ABP1)
lypinator	0:bb348c97df44	2891	* @param __HCLKFREQ__ HCLK frequency
lypinator	0:bb348c97df44	2892	* @param __APB1PRESCALER__ This parameter can be one of the following values:
lypinator	0:bb348c97df44	2893	* @arg @ref LL_RCC_APB1_DIV_1
lypinator	0:bb348c97df44	2894	* @arg @ref LL_RCC_APB1_DIV_2
lypinator	0:bb348c97df44	2895	* @arg @ref LL_RCC_APB1_DIV_4
lypinator	0:bb348c97df44	2896	* @arg @ref LL_RCC_APB1_DIV_8
lypinator	0:bb348c97df44	2897	* @arg @ref LL_RCC_APB1_DIV_16
lypinator	0:bb348c97df44	2898	* @retval PCLK1 clock frequency (in Hz)
lypinator	0:bb348c97df44	2899	*/
lypinator	0:bb348c97df44	2900	#define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE1_Pos])
lypinator	0:bb348c97df44	2901
lypinator	0:bb348c97df44	2902	/**
lypinator	0:bb348c97df44	2903	* @brief Helper macro to calculate the PCLK2 frequency (ABP2)
lypinator	0:bb348c97df44	2904	* @param __HCLKFREQ__ HCLK frequency
lypinator	0:bb348c97df44	2905	* @param __APB2PRESCALER__ This parameter can be one of the following values:
lypinator	0:bb348c97df44	2906	* @arg @ref LL_RCC_APB2_DIV_1
lypinator	0:bb348c97df44	2907	* @arg @ref LL_RCC_APB2_DIV_2
lypinator	0:bb348c97df44	2908	* @arg @ref LL_RCC_APB2_DIV_4
lypinator	0:bb348c97df44	2909	* @arg @ref LL_RCC_APB2_DIV_8
lypinator	0:bb348c97df44	2910	* @arg @ref LL_RCC_APB2_DIV_16
lypinator	0:bb348c97df44	2911	* @retval PCLK2 clock frequency (in Hz)
lypinator	0:bb348c97df44	2912	*/
lypinator	0:bb348c97df44	2913	#define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >> RCC_CFGR_PPRE2_Pos])
lypinator	0:bb348c97df44	2914
lypinator	0:bb348c97df44	2915	/**
lypinator	0:bb348c97df44	2916	* @}
lypinator	0:bb348c97df44	2917	*/
lypinator	0:bb348c97df44	2918
lypinator	0:bb348c97df44	2919	/**
lypinator	0:bb348c97df44	2920	* @}
lypinator	0:bb348c97df44	2921	*/
lypinator	0:bb348c97df44	2922
lypinator	0:bb348c97df44	2923	/* Exported functions --------------------------------------------------------*/
lypinator	0:bb348c97df44	2924	/** @defgroup RCC_LL_Exported_Functions RCC Exported Functions
lypinator	0:bb348c97df44	2925	* @{
lypinator	0:bb348c97df44	2926	*/
lypinator	0:bb348c97df44	2927
lypinator	0:bb348c97df44	2928	/** @defgroup RCC_LL_EF_HSE HSE
lypinator	0:bb348c97df44	2929	* @{
lypinator	0:bb348c97df44	2930	*/
lypinator	0:bb348c97df44	2931
lypinator	0:bb348c97df44	2932	/**
lypinator	0:bb348c97df44	2933	* @brief Enable the Clock Security System.
lypinator	0:bb348c97df44	2934	* @rmtoll CR CSSON LL_RCC_HSE_EnableCSS
lypinator	0:bb348c97df44	2935	* @retval None
lypinator	0:bb348c97df44	2936	*/
lypinator	0:bb348c97df44	2937	__STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)
lypinator	0:bb348c97df44	2938	{
lypinator	0:bb348c97df44	2939	SET_BIT(RCC->CR, RCC_CR_CSSON);
lypinator	0:bb348c97df44	2940	}
lypinator	0:bb348c97df44	2941
lypinator	0:bb348c97df44	2942	/**
lypinator	0:bb348c97df44	2943	* @brief Enable HSE external oscillator (HSE Bypass)
lypinator	0:bb348c97df44	2944	* @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass
lypinator	0:bb348c97df44	2945	* @retval None
lypinator	0:bb348c97df44	2946	*/
lypinator	0:bb348c97df44	2947	__STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)
lypinator	0:bb348c97df44	2948	{
lypinator	0:bb348c97df44	2949	SET_BIT(RCC->CR, RCC_CR_HSEBYP);
lypinator	0:bb348c97df44	2950	}
lypinator	0:bb348c97df44	2951
lypinator	0:bb348c97df44	2952	/**
lypinator	0:bb348c97df44	2953	* @brief Disable HSE external oscillator (HSE Bypass)
lypinator	0:bb348c97df44	2954	* @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass
lypinator	0:bb348c97df44	2955	* @retval None
lypinator	0:bb348c97df44	2956	*/
lypinator	0:bb348c97df44	2957	__STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)
lypinator	0:bb348c97df44	2958	{
lypinator	0:bb348c97df44	2959	CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
lypinator	0:bb348c97df44	2960	}
lypinator	0:bb348c97df44	2961
lypinator	0:bb348c97df44	2962	/**
lypinator	0:bb348c97df44	2963	* @brief Enable HSE crystal oscillator (HSE ON)
lypinator	0:bb348c97df44	2964	* @rmtoll CR HSEON LL_RCC_HSE_Enable
lypinator	0:bb348c97df44	2965	* @retval None
lypinator	0:bb348c97df44	2966	*/
lypinator	0:bb348c97df44	2967	__STATIC_INLINE void LL_RCC_HSE_Enable(void)
lypinator	0:bb348c97df44	2968	{
lypinator	0:bb348c97df44	2969	SET_BIT(RCC->CR, RCC_CR_HSEON);
lypinator	0:bb348c97df44	2970	}
lypinator	0:bb348c97df44	2971
lypinator	0:bb348c97df44	2972	/**
lypinator	0:bb348c97df44	2973	* @brief Disable HSE crystal oscillator (HSE ON)
lypinator	0:bb348c97df44	2974	* @rmtoll CR HSEON LL_RCC_HSE_Disable
lypinator	0:bb348c97df44	2975	* @retval None
lypinator	0:bb348c97df44	2976	*/
lypinator	0:bb348c97df44	2977	__STATIC_INLINE void LL_RCC_HSE_Disable(void)
lypinator	0:bb348c97df44	2978	{
lypinator	0:bb348c97df44	2979	CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
lypinator	0:bb348c97df44	2980	}
lypinator	0:bb348c97df44	2981
lypinator	0:bb348c97df44	2982	/**
lypinator	0:bb348c97df44	2983	* @brief Check if HSE oscillator Ready
lypinator	0:bb348c97df44	2984	* @rmtoll CR HSERDY LL_RCC_HSE_IsReady
lypinator	0:bb348c97df44	2985	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	2986	*/
lypinator	0:bb348c97df44	2987	__STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
lypinator	0:bb348c97df44	2988	{
lypinator	0:bb348c97df44	2989	return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY));
lypinator	0:bb348c97df44	2990	}
lypinator	0:bb348c97df44	2991
lypinator	0:bb348c97df44	2992	/**
lypinator	0:bb348c97df44	2993	* @}
lypinator	0:bb348c97df44	2994	*/
lypinator	0:bb348c97df44	2995
lypinator	0:bb348c97df44	2996	/** @defgroup RCC_LL_EF_HSI HSI
lypinator	0:bb348c97df44	2997	* @{
lypinator	0:bb348c97df44	2998	*/
lypinator	0:bb348c97df44	2999
lypinator	0:bb348c97df44	3000	/**
lypinator	0:bb348c97df44	3001	* @brief Enable HSI oscillator
lypinator	0:bb348c97df44	3002	* @rmtoll CR HSION LL_RCC_HSI_Enable
lypinator	0:bb348c97df44	3003	* @retval None
lypinator	0:bb348c97df44	3004	*/
lypinator	0:bb348c97df44	3005	__STATIC_INLINE void LL_RCC_HSI_Enable(void)
lypinator	0:bb348c97df44	3006	{
lypinator	0:bb348c97df44	3007	SET_BIT(RCC->CR, RCC_CR_HSION);
lypinator	0:bb348c97df44	3008	}
lypinator	0:bb348c97df44	3009
lypinator	0:bb348c97df44	3010	/**
lypinator	0:bb348c97df44	3011	* @brief Disable HSI oscillator
lypinator	0:bb348c97df44	3012	* @rmtoll CR HSION LL_RCC_HSI_Disable
lypinator	0:bb348c97df44	3013	* @retval None
lypinator	0:bb348c97df44	3014	*/
lypinator	0:bb348c97df44	3015	__STATIC_INLINE void LL_RCC_HSI_Disable(void)
lypinator	0:bb348c97df44	3016	{
lypinator	0:bb348c97df44	3017	CLEAR_BIT(RCC->CR, RCC_CR_HSION);
lypinator	0:bb348c97df44	3018	}
lypinator	0:bb348c97df44	3019
lypinator	0:bb348c97df44	3020	/**
lypinator	0:bb348c97df44	3021	* @brief Check if HSI clock is ready
lypinator	0:bb348c97df44	3022	* @rmtoll CR HSIRDY LL_RCC_HSI_IsReady
lypinator	0:bb348c97df44	3023	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	3024	*/
lypinator	0:bb348c97df44	3025	__STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
lypinator	0:bb348c97df44	3026	{
lypinator	0:bb348c97df44	3027	return (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY));
lypinator	0:bb348c97df44	3028	}
lypinator	0:bb348c97df44	3029
lypinator	0:bb348c97df44	3030	/**
lypinator	0:bb348c97df44	3031	* @brief Get HSI Calibration value
lypinator	0:bb348c97df44	3032	* @note When HSITRIM is written, HSICAL is updated with the sum of
lypinator	0:bb348c97df44	3033	* HSITRIM and the factory trim value
lypinator	0:bb348c97df44	3034	* @rmtoll CR HSICAL LL_RCC_HSI_GetCalibration
lypinator	0:bb348c97df44	3035	* @retval Between Min_Data = 0x00 and Max_Data = 0xFF
lypinator	0:bb348c97df44	3036	*/
lypinator	0:bb348c97df44	3037	__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
lypinator	0:bb348c97df44	3038	{
lypinator	0:bb348c97df44	3039	return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSICAL) >> RCC_CR_HSICAL_Pos);
lypinator	0:bb348c97df44	3040	}
lypinator	0:bb348c97df44	3041
lypinator	0:bb348c97df44	3042	/**
lypinator	0:bb348c97df44	3043	* @brief Set HSI Calibration trimming
lypinator	0:bb348c97df44	3044	* @note user-programmable trimming value that is added to the HSICAL
lypinator	0:bb348c97df44	3045	* @note Default value is 16, which, when added to the HSICAL value,
lypinator	0:bb348c97df44	3046	* should trim the HSI to 16 MHz +/- 1 %
lypinator	0:bb348c97df44	3047	* @rmtoll CR HSITRIM LL_RCC_HSI_SetCalibTrimming
lypinator	0:bb348c97df44	3048	* @param Value Between Min_Data = 0 and Max_Data = 31
lypinator	0:bb348c97df44	3049	* @retval None
lypinator	0:bb348c97df44	3050	*/
lypinator	0:bb348c97df44	3051	__STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
lypinator	0:bb348c97df44	3052	{
lypinator	0:bb348c97df44	3053	MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, Value << RCC_CR_HSITRIM_Pos);
lypinator	0:bb348c97df44	3054	}
lypinator	0:bb348c97df44	3055
lypinator	0:bb348c97df44	3056	/**
lypinator	0:bb348c97df44	3057	* @brief Get HSI Calibration trimming
lypinator	0:bb348c97df44	3058	* @rmtoll CR HSITRIM LL_RCC_HSI_GetCalibTrimming
lypinator	0:bb348c97df44	3059	* @retval Between Min_Data = 0 and Max_Data = 31
lypinator	0:bb348c97df44	3060	*/
lypinator	0:bb348c97df44	3061	__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
lypinator	0:bb348c97df44	3062	{
lypinator	0:bb348c97df44	3063	return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos);
lypinator	0:bb348c97df44	3064	}
lypinator	0:bb348c97df44	3065
lypinator	0:bb348c97df44	3066	/**
lypinator	0:bb348c97df44	3067	* @}
lypinator	0:bb348c97df44	3068	*/
lypinator	0:bb348c97df44	3069
lypinator	0:bb348c97df44	3070	/** @defgroup RCC_LL_EF_LSE LSE
lypinator	0:bb348c97df44	3071	* @{
lypinator	0:bb348c97df44	3072	*/
lypinator	0:bb348c97df44	3073
lypinator	0:bb348c97df44	3074	/**
lypinator	0:bb348c97df44	3075	* @brief Enable Low Speed External (LSE) crystal.
lypinator	0:bb348c97df44	3076	* @rmtoll BDCR LSEON LL_RCC_LSE_Enable
lypinator	0:bb348c97df44	3077	* @retval None
lypinator	0:bb348c97df44	3078	*/
lypinator	0:bb348c97df44	3079	__STATIC_INLINE void LL_RCC_LSE_Enable(void)
lypinator	0:bb348c97df44	3080	{
lypinator	0:bb348c97df44	3081	SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
lypinator	0:bb348c97df44	3082	}
lypinator	0:bb348c97df44	3083
lypinator	0:bb348c97df44	3084	/**
lypinator	0:bb348c97df44	3085	* @brief Disable Low Speed External (LSE) crystal.
lypinator	0:bb348c97df44	3086	* @rmtoll BDCR LSEON LL_RCC_LSE_Disable
lypinator	0:bb348c97df44	3087	* @retval None
lypinator	0:bb348c97df44	3088	*/
lypinator	0:bb348c97df44	3089	__STATIC_INLINE void LL_RCC_LSE_Disable(void)
lypinator	0:bb348c97df44	3090	{
lypinator	0:bb348c97df44	3091	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
lypinator	0:bb348c97df44	3092	}
lypinator	0:bb348c97df44	3093
lypinator	0:bb348c97df44	3094	/**
lypinator	0:bb348c97df44	3095	* @brief Enable external clock source (LSE bypass).
lypinator	0:bb348c97df44	3096	* @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass
lypinator	0:bb348c97df44	3097	* @retval None
lypinator	0:bb348c97df44	3098	*/
lypinator	0:bb348c97df44	3099	__STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
lypinator	0:bb348c97df44	3100	{
lypinator	0:bb348c97df44	3101	SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
lypinator	0:bb348c97df44	3102	}
lypinator	0:bb348c97df44	3103
lypinator	0:bb348c97df44	3104	/**
lypinator	0:bb348c97df44	3105	* @brief Disable external clock source (LSE bypass).
lypinator	0:bb348c97df44	3106	* @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass
lypinator	0:bb348c97df44	3107	* @retval None
lypinator	0:bb348c97df44	3108	*/
lypinator	0:bb348c97df44	3109	__STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
lypinator	0:bb348c97df44	3110	{
lypinator	0:bb348c97df44	3111	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
lypinator	0:bb348c97df44	3112	}
lypinator	0:bb348c97df44	3113
lypinator	0:bb348c97df44	3114	/**
lypinator	0:bb348c97df44	3115	* @brief Check if LSE oscillator Ready
lypinator	0:bb348c97df44	3116	* @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady
lypinator	0:bb348c97df44	3117	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	3118	*/
lypinator	0:bb348c97df44	3119	__STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
lypinator	0:bb348c97df44	3120	{
lypinator	0:bb348c97df44	3121	return (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY));
lypinator	0:bb348c97df44	3122	}
lypinator	0:bb348c97df44	3123
lypinator	0:bb348c97df44	3124	#if defined(RCC_BDCR_LSEMOD)
lypinator	0:bb348c97df44	3125	/**
lypinator	0:bb348c97df44	3126	* @brief Enable LSE high drive mode.
lypinator	0:bb348c97df44	3127	* @note LSE high drive mode can be enabled only when the LSE clock is disabled
lypinator	0:bb348c97df44	3128	* @rmtoll BDCR LSEMOD LL_RCC_LSE_EnableHighDriveMode
lypinator	0:bb348c97df44	3129	* @retval None
lypinator	0:bb348c97df44	3130	*/
lypinator	0:bb348c97df44	3131	__STATIC_INLINE void LL_RCC_LSE_EnableHighDriveMode(void)
lypinator	0:bb348c97df44	3132	{
lypinator	0:bb348c97df44	3133	SET_BIT(RCC->BDCR, RCC_BDCR_LSEMOD);
lypinator	0:bb348c97df44	3134	}
lypinator	0:bb348c97df44	3135
lypinator	0:bb348c97df44	3136	/**
lypinator	0:bb348c97df44	3137	* @brief Disable LSE high drive mode.
lypinator	0:bb348c97df44	3138	* @note LSE high drive mode can be disabled only when the LSE clock is disabled
lypinator	0:bb348c97df44	3139	* @rmtoll BDCR LSEMOD LL_RCC_LSE_DisableHighDriveMode
lypinator	0:bb348c97df44	3140	* @retval None
lypinator	0:bb348c97df44	3141	*/
lypinator	0:bb348c97df44	3142	__STATIC_INLINE void LL_RCC_LSE_DisableHighDriveMode(void)
lypinator	0:bb348c97df44	3143	{
lypinator	0:bb348c97df44	3144	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEMOD);
lypinator	0:bb348c97df44	3145	}
lypinator	0:bb348c97df44	3146	#endif /* RCC_BDCR_LSEMOD */
lypinator	0:bb348c97df44	3147
lypinator	0:bb348c97df44	3148	/**
lypinator	0:bb348c97df44	3149	* @}
lypinator	0:bb348c97df44	3150	*/
lypinator	0:bb348c97df44	3151
lypinator	0:bb348c97df44	3152	/** @defgroup RCC_LL_EF_LSI LSI
lypinator	0:bb348c97df44	3153	* @{
lypinator	0:bb348c97df44	3154	*/
lypinator	0:bb348c97df44	3155
lypinator	0:bb348c97df44	3156	/**
lypinator	0:bb348c97df44	3157	* @brief Enable LSI Oscillator
lypinator	0:bb348c97df44	3158	* @rmtoll CSR LSION LL_RCC_LSI_Enable
lypinator	0:bb348c97df44	3159	* @retval None
lypinator	0:bb348c97df44	3160	*/
lypinator	0:bb348c97df44	3161	__STATIC_INLINE void LL_RCC_LSI_Enable(void)
lypinator	0:bb348c97df44	3162	{
lypinator	0:bb348c97df44	3163	SET_BIT(RCC->CSR, RCC_CSR_LSION);
lypinator	0:bb348c97df44	3164	}
lypinator	0:bb348c97df44	3165
lypinator	0:bb348c97df44	3166	/**
lypinator	0:bb348c97df44	3167	* @brief Disable LSI Oscillator
lypinator	0:bb348c97df44	3168	* @rmtoll CSR LSION LL_RCC_LSI_Disable
lypinator	0:bb348c97df44	3169	* @retval None
lypinator	0:bb348c97df44	3170	*/
lypinator	0:bb348c97df44	3171	__STATIC_INLINE void LL_RCC_LSI_Disable(void)
lypinator	0:bb348c97df44	3172	{
lypinator	0:bb348c97df44	3173	CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
lypinator	0:bb348c97df44	3174	}
lypinator	0:bb348c97df44	3175
lypinator	0:bb348c97df44	3176	/**
lypinator	0:bb348c97df44	3177	* @brief Check if LSI is Ready
lypinator	0:bb348c97df44	3178	* @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady
lypinator	0:bb348c97df44	3179	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	3180	*/
lypinator	0:bb348c97df44	3181	__STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)
lypinator	0:bb348c97df44	3182	{
lypinator	0:bb348c97df44	3183	return (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY));
lypinator	0:bb348c97df44	3184	}
lypinator	0:bb348c97df44	3185
lypinator	0:bb348c97df44	3186	/**
lypinator	0:bb348c97df44	3187	* @}
lypinator	0:bb348c97df44	3188	*/
lypinator	0:bb348c97df44	3189
lypinator	0:bb348c97df44	3190	/** @defgroup RCC_LL_EF_System System
lypinator	0:bb348c97df44	3191	* @{
lypinator	0:bb348c97df44	3192	*/
lypinator	0:bb348c97df44	3193
lypinator	0:bb348c97df44	3194	/**
lypinator	0:bb348c97df44	3195	* @brief Configure the system clock source
lypinator	0:bb348c97df44	3196	* @rmtoll CFGR SW LL_RCC_SetSysClkSource
lypinator	0:bb348c97df44	3197	* @param Source This parameter can be one of the following values:
lypinator	0:bb348c97df44	3198	* @arg @ref LL_RCC_SYS_CLKSOURCE_HSI
lypinator	0:bb348c97df44	3199	* @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
lypinator	0:bb348c97df44	3200	* @arg @ref LL_RCC_SYS_CLKSOURCE_PLL
lypinator	0:bb348c97df44	3201	* @arg @ref LL_RCC_SYS_CLKSOURCE_PLLR (*)
lypinator	0:bb348c97df44	3202	*
lypinator	0:bb348c97df44	3203	* (*) value not defined in all devices.
lypinator	0:bb348c97df44	3204	* @retval None
lypinator	0:bb348c97df44	3205	*/
lypinator	0:bb348c97df44	3206	__STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
lypinator	0:bb348c97df44	3207	{
lypinator	0:bb348c97df44	3208	MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
lypinator	0:bb348c97df44	3209	}
lypinator	0:bb348c97df44	3210
lypinator	0:bb348c97df44	3211	/**
lypinator	0:bb348c97df44	3212	* @brief Get the system clock source
lypinator	0:bb348c97df44	3213	* @rmtoll CFGR SWS LL_RCC_GetSysClkSource
lypinator	0:bb348c97df44	3214	* @retval Returned value can be one of the following values:
lypinator	0:bb348c97df44	3215	* @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
lypinator	0:bb348c97df44	3216	* @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
lypinator	0:bb348c97df44	3217	* @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL
lypinator	0:bb348c97df44	3218	* @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLLR (*)
lypinator	0:bb348c97df44	3219	*
lypinator	0:bb348c97df44	3220	* (*) value not defined in all devices.
lypinator	0:bb348c97df44	3221	*/
lypinator	0:bb348c97df44	3222	__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
lypinator	0:bb348c97df44	3223	{
lypinator	0:bb348c97df44	3224	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
lypinator	0:bb348c97df44	3225	}
lypinator	0:bb348c97df44	3226
lypinator	0:bb348c97df44	3227	/**
lypinator	0:bb348c97df44	3228	* @brief Set AHB prescaler
lypinator	0:bb348c97df44	3229	* @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler
lypinator	0:bb348c97df44	3230	* @param Prescaler This parameter can be one of the following values:
lypinator	0:bb348c97df44	3231	* @arg @ref LL_RCC_SYSCLK_DIV_1
lypinator	0:bb348c97df44	3232	* @arg @ref LL_RCC_SYSCLK_DIV_2
lypinator	0:bb348c97df44	3233	* @arg @ref LL_RCC_SYSCLK_DIV_4
lypinator	0:bb348c97df44	3234	* @arg @ref LL_RCC_SYSCLK_DIV_8
lypinator	0:bb348c97df44	3235	* @arg @ref LL_RCC_SYSCLK_DIV_16
lypinator	0:bb348c97df44	3236	* @arg @ref LL_RCC_SYSCLK_DIV_64
lypinator	0:bb348c97df44	3237	* @arg @ref LL_RCC_SYSCLK_DIV_128
lypinator	0:bb348c97df44	3238	* @arg @ref LL_RCC_SYSCLK_DIV_256
lypinator	0:bb348c97df44	3239	* @arg @ref LL_RCC_SYSCLK_DIV_512
lypinator	0:bb348c97df44	3240	* @retval None
lypinator	0:bb348c97df44	3241	*/
lypinator	0:bb348c97df44	3242	__STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
lypinator	0:bb348c97df44	3243	{
lypinator	0:bb348c97df44	3244	MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);
lypinator	0:bb348c97df44	3245	}
lypinator	0:bb348c97df44	3246
lypinator	0:bb348c97df44	3247	/**
lypinator	0:bb348c97df44	3248	* @brief Set APB1 prescaler
lypinator	0:bb348c97df44	3249	* @rmtoll CFGR PPRE1 LL_RCC_SetAPB1Prescaler
lypinator	0:bb348c97df44	3250	* @param Prescaler This parameter can be one of the following values:
lypinator	0:bb348c97df44	3251	* @arg @ref LL_RCC_APB1_DIV_1
lypinator	0:bb348c97df44	3252	* @arg @ref LL_RCC_APB1_DIV_2
lypinator	0:bb348c97df44	3253	* @arg @ref LL_RCC_APB1_DIV_4
lypinator	0:bb348c97df44	3254	* @arg @ref LL_RCC_APB1_DIV_8
lypinator	0:bb348c97df44	3255	* @arg @ref LL_RCC_APB1_DIV_16
lypinator	0:bb348c97df44	3256	* @retval None
lypinator	0:bb348c97df44	3257	*/
lypinator	0:bb348c97df44	3258	__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
lypinator	0:bb348c97df44	3259	{
lypinator	0:bb348c97df44	3260	MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler);
lypinator	0:bb348c97df44	3261	}
lypinator	0:bb348c97df44	3262
lypinator	0:bb348c97df44	3263	/**
lypinator	0:bb348c97df44	3264	* @brief Set APB2 prescaler
lypinator	0:bb348c97df44	3265	* @rmtoll CFGR PPRE2 LL_RCC_SetAPB2Prescaler
lypinator	0:bb348c97df44	3266	* @param Prescaler This parameter can be one of the following values:
lypinator	0:bb348c97df44	3267	* @arg @ref LL_RCC_APB2_DIV_1
lypinator	0:bb348c97df44	3268	* @arg @ref LL_RCC_APB2_DIV_2
lypinator	0:bb348c97df44	3269	* @arg @ref LL_RCC_APB2_DIV_4
lypinator	0:bb348c97df44	3270	* @arg @ref LL_RCC_APB2_DIV_8
lypinator	0:bb348c97df44	3271	* @arg @ref LL_RCC_APB2_DIV_16
lypinator	0:bb348c97df44	3272	* @retval None
lypinator	0:bb348c97df44	3273	*/
lypinator	0:bb348c97df44	3274	__STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
lypinator	0:bb348c97df44	3275	{
lypinator	0:bb348c97df44	3276	MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler);
lypinator	0:bb348c97df44	3277	}
lypinator	0:bb348c97df44	3278
lypinator	0:bb348c97df44	3279	/**
lypinator	0:bb348c97df44	3280	* @brief Get AHB prescaler
lypinator	0:bb348c97df44	3281	* @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler
lypinator	0:bb348c97df44	3282	* @retval Returned value can be one of the following values:
lypinator	0:bb348c97df44	3283	* @arg @ref LL_RCC_SYSCLK_DIV_1
lypinator	0:bb348c97df44	3284	* @arg @ref LL_RCC_SYSCLK_DIV_2
lypinator	0:bb348c97df44	3285	* @arg @ref LL_RCC_SYSCLK_DIV_4
lypinator	0:bb348c97df44	3286	* @arg @ref LL_RCC_SYSCLK_DIV_8
lypinator	0:bb348c97df44	3287	* @arg @ref LL_RCC_SYSCLK_DIV_16
lypinator	0:bb348c97df44	3288	* @arg @ref LL_RCC_SYSCLK_DIV_64
lypinator	0:bb348c97df44	3289	* @arg @ref LL_RCC_SYSCLK_DIV_128
lypinator	0:bb348c97df44	3290	* @arg @ref LL_RCC_SYSCLK_DIV_256
lypinator	0:bb348c97df44	3291	* @arg @ref LL_RCC_SYSCLK_DIV_512
lypinator	0:bb348c97df44	3292	*/
lypinator	0:bb348c97df44	3293	__STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)
lypinator	0:bb348c97df44	3294	{
lypinator	0:bb348c97df44	3295	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE));
lypinator	0:bb348c97df44	3296	}
lypinator	0:bb348c97df44	3297
lypinator	0:bb348c97df44	3298	/**
lypinator	0:bb348c97df44	3299	* @brief Get APB1 prescaler
lypinator	0:bb348c97df44	3300	* @rmtoll CFGR PPRE1 LL_RCC_GetAPB1Prescaler
lypinator	0:bb348c97df44	3301	* @retval Returned value can be one of the following values:
lypinator	0:bb348c97df44	3302	* @arg @ref LL_RCC_APB1_DIV_1
lypinator	0:bb348c97df44	3303	* @arg @ref LL_RCC_APB1_DIV_2
lypinator	0:bb348c97df44	3304	* @arg @ref LL_RCC_APB1_DIV_4
lypinator	0:bb348c97df44	3305	* @arg @ref LL_RCC_APB1_DIV_8
lypinator	0:bb348c97df44	3306	* @arg @ref LL_RCC_APB1_DIV_16
lypinator	0:bb348c97df44	3307	*/
lypinator	0:bb348c97df44	3308	__STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
lypinator	0:bb348c97df44	3309	{
lypinator	0:bb348c97df44	3310	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1));
lypinator	0:bb348c97df44	3311	}
lypinator	0:bb348c97df44	3312
lypinator	0:bb348c97df44	3313	/**
lypinator	0:bb348c97df44	3314	* @brief Get APB2 prescaler
lypinator	0:bb348c97df44	3315	* @rmtoll CFGR PPRE2 LL_RCC_GetAPB2Prescaler
lypinator	0:bb348c97df44	3316	* @retval Returned value can be one of the following values:
lypinator	0:bb348c97df44	3317	* @arg @ref LL_RCC_APB2_DIV_1
lypinator	0:bb348c97df44	3318	* @arg @ref LL_RCC_APB2_DIV_2
lypinator	0:bb348c97df44	3319	* @arg @ref LL_RCC_APB2_DIV_4
lypinator	0:bb348c97df44	3320	* @arg @ref LL_RCC_APB2_DIV_8
lypinator	0:bb348c97df44	3321	* @arg @ref LL_RCC_APB2_DIV_16
lypinator	0:bb348c97df44	3322	*/
lypinator	0:bb348c97df44	3323	__STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void)
lypinator	0:bb348c97df44	3324	{
lypinator	0:bb348c97df44	3325	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2));
lypinator	0:bb348c97df44	3326	}
lypinator	0:bb348c97df44	3327
lypinator	0:bb348c97df44	3328	/**
lypinator	0:bb348c97df44	3329	* @}
lypinator	0:bb348c97df44	3330	*/
lypinator	0:bb348c97df44	3331
lypinator	0:bb348c97df44	3332	/** @defgroup RCC_LL_EF_MCO MCO
lypinator	0:bb348c97df44	3333	* @{
lypinator	0:bb348c97df44	3334	*/
lypinator	0:bb348c97df44	3335
lypinator	0:bb348c97df44	3336	#if defined(RCC_CFGR_MCO1EN)
lypinator	0:bb348c97df44	3337	/**
lypinator	0:bb348c97df44	3338	* @brief Enable MCO1 output
lypinator	0:bb348c97df44	3339	* @rmtoll CFGR RCC_CFGR_MCO1EN LL_RCC_MCO1_Enable
lypinator	0:bb348c97df44	3340	* @retval None
lypinator	0:bb348c97df44	3341	*/
lypinator	0:bb348c97df44	3342	__STATIC_INLINE void LL_RCC_MCO1_Enable(void)
lypinator	0:bb348c97df44	3343	{
lypinator	0:bb348c97df44	3344	SET_BIT(RCC->CFGR, RCC_CFGR_MCO1EN);
lypinator	0:bb348c97df44	3345	}
lypinator	0:bb348c97df44	3346
lypinator	0:bb348c97df44	3347	/**
lypinator	0:bb348c97df44	3348	* @brief Disable MCO1 output
lypinator	0:bb348c97df44	3349	* @rmtoll CFGR RCC_CFGR_MCO1EN LL_RCC_MCO1_Disable
lypinator	0:bb348c97df44	3350	* @retval None
lypinator	0:bb348c97df44	3351	*/
lypinator	0:bb348c97df44	3352	__STATIC_INLINE void LL_RCC_MCO1_Disable(void)
lypinator	0:bb348c97df44	3353	{
lypinator	0:bb348c97df44	3354	CLEAR_BIT(RCC->CFGR, RCC_CFGR_MCO1EN);
lypinator	0:bb348c97df44	3355	}
lypinator	0:bb348c97df44	3356	#endif /* RCC_CFGR_MCO1EN */
lypinator	0:bb348c97df44	3357
lypinator	0:bb348c97df44	3358	#if defined(RCC_CFGR_MCO2EN)
lypinator	0:bb348c97df44	3359	/**
lypinator	0:bb348c97df44	3360	* @brief Enable MCO2 output
lypinator	0:bb348c97df44	3361	* @rmtoll CFGR RCC_CFGR_MCO2EN LL_RCC_MCO2_Enable
lypinator	0:bb348c97df44	3362	* @retval None
lypinator	0:bb348c97df44	3363	*/
lypinator	0:bb348c97df44	3364	__STATIC_INLINE void LL_RCC_MCO2_Enable(void)
lypinator	0:bb348c97df44	3365	{
lypinator	0:bb348c97df44	3366	SET_BIT(RCC->CFGR, RCC_CFGR_MCO2EN);
lypinator	0:bb348c97df44	3367	}
lypinator	0:bb348c97df44	3368
lypinator	0:bb348c97df44	3369	/**
lypinator	0:bb348c97df44	3370	* @brief Disable MCO2 output
lypinator	0:bb348c97df44	3371	* @rmtoll CFGR RCC_CFGR_MCO2EN LL_RCC_MCO2_Disable
lypinator	0:bb348c97df44	3372	* @retval None
lypinator	0:bb348c97df44	3373	*/
lypinator	0:bb348c97df44	3374	__STATIC_INLINE void LL_RCC_MCO2_Disable(void)
lypinator	0:bb348c97df44	3375	{
lypinator	0:bb348c97df44	3376	CLEAR_BIT(RCC->CFGR, RCC_CFGR_MCO2EN);
lypinator	0:bb348c97df44	3377	}
lypinator	0:bb348c97df44	3378	#endif /* RCC_CFGR_MCO2EN */
lypinator	0:bb348c97df44	3379
lypinator	0:bb348c97df44	3380	/**
lypinator	0:bb348c97df44	3381	* @brief Configure MCOx
lypinator	0:bb348c97df44	3382	* @rmtoll CFGR MCO1 LL_RCC_ConfigMCO\n
lypinator	0:bb348c97df44	3383	* CFGR MCO1PRE LL_RCC_ConfigMCO\n
lypinator	0:bb348c97df44	3384	* CFGR MCO2 LL_RCC_ConfigMCO\n
lypinator	0:bb348c97df44	3385	* CFGR MCO2PRE LL_RCC_ConfigMCO
lypinator	0:bb348c97df44	3386	* @param MCOxSource This parameter can be one of the following values:
lypinator	0:bb348c97df44	3387	* @arg @ref LL_RCC_MCO1SOURCE_HSI
lypinator	0:bb348c97df44	3388	* @arg @ref LL_RCC_MCO1SOURCE_LSE
lypinator	0:bb348c97df44	3389	* @arg @ref LL_RCC_MCO1SOURCE_HSE
lypinator	0:bb348c97df44	3390	* @arg @ref LL_RCC_MCO1SOURCE_PLLCLK
lypinator	0:bb348c97df44	3391	* @arg @ref LL_RCC_MCO2SOURCE_SYSCLK
lypinator	0:bb348c97df44	3392	* @arg @ref LL_RCC_MCO2SOURCE_PLLI2S
lypinator	0:bb348c97df44	3393	* @arg @ref LL_RCC_MCO2SOURCE_HSE
lypinator	0:bb348c97df44	3394	* @arg @ref LL_RCC_MCO2SOURCE_PLLCLK
lypinator	0:bb348c97df44	3395	* @param MCOxPrescaler This parameter can be one of the following values:
lypinator	0:bb348c97df44	3396	* @arg @ref LL_RCC_MCO1_DIV_1
lypinator	0:bb348c97df44	3397	* @arg @ref LL_RCC_MCO1_DIV_2
lypinator	0:bb348c97df44	3398	* @arg @ref LL_RCC_MCO1_DIV_3
lypinator	0:bb348c97df44	3399	* @arg @ref LL_RCC_MCO1_DIV_4
lypinator	0:bb348c97df44	3400	* @arg @ref LL_RCC_MCO1_DIV_5
lypinator	0:bb348c97df44	3401	* @arg @ref LL_RCC_MCO2_DIV_1
lypinator	0:bb348c97df44	3402	* @arg @ref LL_RCC_MCO2_DIV_2
lypinator	0:bb348c97df44	3403	* @arg @ref LL_RCC_MCO2_DIV_3
lypinator	0:bb348c97df44	3404	* @arg @ref LL_RCC_MCO2_DIV_4
lypinator	0:bb348c97df44	3405	* @arg @ref LL_RCC_MCO2_DIV_5
lypinator	0:bb348c97df44	3406	* @retval None
lypinator	0:bb348c97df44	3407	*/
lypinator	0:bb348c97df44	3408	__STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler)
lypinator	0:bb348c97df44	3409	{
lypinator	0:bb348c97df44	3410	MODIFY_REG(RCC->CFGR, (MCOxSource & 0xFFFF0000U) \| (MCOxPrescaler & 0xFFFF0000U), (MCOxSource << 16U) \| (MCOxPrescaler << 16U));
lypinator	0:bb348c97df44	3411	}
lypinator	0:bb348c97df44	3412
lypinator	0:bb348c97df44	3413	/**
lypinator	0:bb348c97df44	3414	* @}
lypinator	0:bb348c97df44	3415	*/
lypinator	0:bb348c97df44	3416
lypinator	0:bb348c97df44	3417	/** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source
lypinator	0:bb348c97df44	3418	* @{
lypinator	0:bb348c97df44	3419	*/
lypinator	0:bb348c97df44	3420	#if defined(FMPI2C1)
lypinator	0:bb348c97df44	3421	/**
lypinator	0:bb348c97df44	3422	* @brief Configure FMPI2C clock source
lypinator	0:bb348c97df44	3423	* @rmtoll DCKCFGR2 FMPI2C1SEL LL_RCC_SetFMPI2CClockSource
lypinator	0:bb348c97df44	3424	* @param FMPI2CxSource This parameter can be one of the following values:
lypinator	0:bb348c97df44	3425	* @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_PCLK1
lypinator	0:bb348c97df44	3426	* @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_SYSCLK
lypinator	0:bb348c97df44	3427	* @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_HSI
lypinator	0:bb348c97df44	3428	* @retval None
lypinator	0:bb348c97df44	3429	*/
lypinator	0:bb348c97df44	3430	__STATIC_INLINE void LL_RCC_SetFMPI2CClockSource(uint32_t FMPI2CxSource)
lypinator	0:bb348c97df44	3431	{
lypinator	0:bb348c97df44	3432	MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, FMPI2CxSource);
lypinator	0:bb348c97df44	3433	}
lypinator	0:bb348c97df44	3434	#endif /* FMPI2C1 */
lypinator	0:bb348c97df44	3435
lypinator	0:bb348c97df44	3436	#if defined(LPTIM1)
lypinator	0:bb348c97df44	3437	/**
lypinator	0:bb348c97df44	3438	* @brief Configure LPTIMx clock source
lypinator	0:bb348c97df44	3439	* @rmtoll DCKCFGR2 LPTIM1SEL LL_RCC_SetLPTIMClockSource
lypinator	0:bb348c97df44	3440	* @param LPTIMxSource This parameter can be one of the following values:
lypinator	0:bb348c97df44	3441	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
lypinator	0:bb348c97df44	3442	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
lypinator	0:bb348c97df44	3443	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
lypinator	0:bb348c97df44	3444	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
lypinator	0:bb348c97df44	3445	* @retval None
lypinator	0:bb348c97df44	3446	*/
lypinator	0:bb348c97df44	3447	__STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource)
lypinator	0:bb348c97df44	3448	{
lypinator	0:bb348c97df44	3449	MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, LPTIMxSource);
lypinator	0:bb348c97df44	3450	}
lypinator	0:bb348c97df44	3451	#endif /* LPTIM1 */
lypinator	0:bb348c97df44	3452
lypinator	0:bb348c97df44	3453	#if defined(SAI1)
lypinator	0:bb348c97df44	3454	/**
lypinator	0:bb348c97df44	3455	* @brief Configure SAIx clock source
lypinator	0:bb348c97df44	3456	* @rmtoll DCKCFGR SAI1SRC LL_RCC_SetSAIClockSource\n
lypinator	0:bb348c97df44	3457	* DCKCFGR SAI2SRC LL_RCC_SetSAIClockSource\n
lypinator	0:bb348c97df44	3458	* DCKCFGR SAI1ASRC LL_RCC_SetSAIClockSource\n
lypinator	0:bb348c97df44	3459	* DCKCFGR SAI1BSRC LL_RCC_SetSAIClockSource
lypinator	0:bb348c97df44	3460	* @param SAIxSource This parameter can be one of the following values:
lypinator	0:bb348c97df44	3461	* @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI (*)
lypinator	0:bb348c97df44	3462	* @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLI2S (*)
lypinator	0:bb348c97df44	3463	* @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL (*)
lypinator	0:bb348c97df44	3464	* @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN (*)
lypinator	0:bb348c97df44	3465	* @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI (*)
lypinator	0:bb348c97df44	3466	* @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLI2S (*)
lypinator	0:bb348c97df44	3467	* @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL (*)
lypinator	0:bb348c97df44	3468	* @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSRC (*)
lypinator	0:bb348c97df44	3469	* @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLSAI (*)
lypinator	0:bb348c97df44	3470	* @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLI2S (*)
lypinator	0:bb348c97df44	3471	* @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PIN (*)
lypinator	0:bb348c97df44	3472	* @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLL (*)
lypinator	0:bb348c97df44	3473	* @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLSRC (*)
lypinator	0:bb348c97df44	3474	* @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLSAI (*)
lypinator	0:bb348c97df44	3475	* @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLI2S (*)
lypinator	0:bb348c97df44	3476	* @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PIN (*)
lypinator	0:bb348c97df44	3477	* @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLL (*)
lypinator	0:bb348c97df44	3478	* @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLSRC (*)
lypinator	0:bb348c97df44	3479	*
lypinator	0:bb348c97df44	3480	* (*) value not defined in all devices.
lypinator	0:bb348c97df44	3481	* @retval None
lypinator	0:bb348c97df44	3482	*/
lypinator	0:bb348c97df44	3483	__STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t SAIxSource)
lypinator	0:bb348c97df44	3484	{
lypinator	0:bb348c97df44	3485	MODIFY_REG(RCC->DCKCFGR, (SAIxSource & 0xFFFF0000U), (SAIxSource << 16U));
lypinator	0:bb348c97df44	3486	}
lypinator	0:bb348c97df44	3487	#endif /* SAI1 */
lypinator	0:bb348c97df44	3488
lypinator	0:bb348c97df44	3489	#if defined(RCC_DCKCFGR_SDIOSEL) \|\| defined(RCC_DCKCFGR2_SDIOSEL)
lypinator	0:bb348c97df44	3490	/**
lypinator	0:bb348c97df44	3491	* @brief Configure SDIO clock source
lypinator	0:bb348c97df44	3492	* @rmtoll DCKCFGR SDIOSEL LL_RCC_SetSDIOClockSource\n
lypinator	0:bb348c97df44	3493	* DCKCFGR2 SDIOSEL LL_RCC_SetSDIOClockSource
lypinator	0:bb348c97df44	3494	* @param SDIOxSource This parameter can be one of the following values:
lypinator	0:bb348c97df44	3495	* @arg @ref LL_RCC_SDIO_CLKSOURCE_PLL48CLK
lypinator	0:bb348c97df44	3496	* @arg @ref LL_RCC_SDIO_CLKSOURCE_SYSCLK
lypinator	0:bb348c97df44	3497	* @retval None
lypinator	0:bb348c97df44	3498	*/
lypinator	0:bb348c97df44	3499	__STATIC_INLINE void LL_RCC_SetSDIOClockSource(uint32_t SDIOxSource)
lypinator	0:bb348c97df44	3500	{
lypinator	0:bb348c97df44	3501	#if defined(RCC_DCKCFGR_SDIOSEL)
lypinator	0:bb348c97df44	3502	MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SDIOSEL, SDIOxSource);
lypinator	0:bb348c97df44	3503	#else
lypinator	0:bb348c97df44	3504	MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL, SDIOxSource);
lypinator	0:bb348c97df44	3505	#endif /* RCC_DCKCFGR_SDIOSEL */
lypinator	0:bb348c97df44	3506	}
lypinator	0:bb348c97df44	3507	#endif /* RCC_DCKCFGR_SDIOSEL \|\| RCC_DCKCFGR2_SDIOSEL */
lypinator	0:bb348c97df44	3508
lypinator	0:bb348c97df44	3509	#if defined(RCC_DCKCFGR_CK48MSEL) \|\| defined(RCC_DCKCFGR2_CK48MSEL)
lypinator	0:bb348c97df44	3510	/**
lypinator	0:bb348c97df44	3511	* @brief Configure 48Mhz domain clock source
lypinator	0:bb348c97df44	3512	* @rmtoll DCKCFGR CK48MSEL LL_RCC_SetCK48MClockSource\n
lypinator	0:bb348c97df44	3513	* DCKCFGR2 CK48MSEL LL_RCC_SetCK48MClockSource
lypinator	0:bb348c97df44	3514	* @param CK48MxSource This parameter can be one of the following values:
lypinator	0:bb348c97df44	3515	* @arg @ref LL_RCC_CK48M_CLKSOURCE_PLL
lypinator	0:bb348c97df44	3516	* @arg @ref LL_RCC_CK48M_CLKSOURCE_PLLSAI (*)
lypinator	0:bb348c97df44	3517	* @arg @ref LL_RCC_CK48M_CLKSOURCE_PLLI2S (*)
lypinator	0:bb348c97df44	3518	*
lypinator	0:bb348c97df44	3519	* (*) value not defined in all devices.
lypinator	0:bb348c97df44	3520	* @retval None
lypinator	0:bb348c97df44	3521	*/
lypinator	0:bb348c97df44	3522	__STATIC_INLINE void LL_RCC_SetCK48MClockSource(uint32_t CK48MxSource)
lypinator	0:bb348c97df44	3523	{
lypinator	0:bb348c97df44	3524	#if defined(RCC_DCKCFGR_CK48MSEL)
lypinator	0:bb348c97df44	3525	MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL, CK48MxSource);
lypinator	0:bb348c97df44	3526	#else
lypinator	0:bb348c97df44	3527	MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, CK48MxSource);
lypinator	0:bb348c97df44	3528	#endif /* RCC_DCKCFGR_CK48MSEL */
lypinator	0:bb348c97df44	3529	}
lypinator	0:bb348c97df44	3530
lypinator	0:bb348c97df44	3531	#if defined(RNG)
lypinator	0:bb348c97df44	3532	/**
lypinator	0:bb348c97df44	3533	* @brief Configure RNG clock source
lypinator	0:bb348c97df44	3534	* @rmtoll DCKCFGR CK48MSEL LL_RCC_SetRNGClockSource\n
lypinator	0:bb348c97df44	3535	* DCKCFGR2 CK48MSEL LL_RCC_SetRNGClockSource
lypinator	0:bb348c97df44	3536	* @param RNGxSource This parameter can be one of the following values:
lypinator	0:bb348c97df44	3537	* @arg @ref LL_RCC_RNG_CLKSOURCE_PLL
lypinator	0:bb348c97df44	3538	* @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI (*)
lypinator	0:bb348c97df44	3539	* @arg @ref LL_RCC_RNG_CLKSOURCE_PLLI2S (*)
lypinator	0:bb348c97df44	3540	*
lypinator	0:bb348c97df44	3541	* (*) value not defined in all devices.
lypinator	0:bb348c97df44	3542	* @retval None
lypinator	0:bb348c97df44	3543	*/
lypinator	0:bb348c97df44	3544	__STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t RNGxSource)
lypinator	0:bb348c97df44	3545	{
lypinator	0:bb348c97df44	3546	#if defined(RCC_DCKCFGR_CK48MSEL)
lypinator	0:bb348c97df44	3547	MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL, RNGxSource);
lypinator	0:bb348c97df44	3548	#else
lypinator	0:bb348c97df44	3549	MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, RNGxSource);
lypinator	0:bb348c97df44	3550	#endif /* RCC_DCKCFGR_CK48MSEL */
lypinator	0:bb348c97df44	3551	}
lypinator	0:bb348c97df44	3552	#endif /* RNG */
lypinator	0:bb348c97df44	3553
lypinator	0:bb348c97df44	3554	#if defined(USB_OTG_FS) \|\| defined(USB_OTG_HS)
lypinator	0:bb348c97df44	3555	/**
lypinator	0:bb348c97df44	3556	* @brief Configure USB clock source
lypinator	0:bb348c97df44	3557	* @rmtoll DCKCFGR CK48MSEL LL_RCC_SetUSBClockSource\n
lypinator	0:bb348c97df44	3558	* DCKCFGR2 CK48MSEL LL_RCC_SetUSBClockSource
lypinator	0:bb348c97df44	3559	* @param USBxSource This parameter can be one of the following values:
lypinator	0:bb348c97df44	3560	* @arg @ref LL_RCC_USB_CLKSOURCE_PLL
lypinator	0:bb348c97df44	3561	* @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI (*)
lypinator	0:bb348c97df44	3562	* @arg @ref LL_RCC_USB_CLKSOURCE_PLLI2S (*)
lypinator	0:bb348c97df44	3563	*
lypinator	0:bb348c97df44	3564	* (*) value not defined in all devices.
lypinator	0:bb348c97df44	3565	* @retval None
lypinator	0:bb348c97df44	3566	*/
lypinator	0:bb348c97df44	3567	__STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource)
lypinator	0:bb348c97df44	3568	{
lypinator	0:bb348c97df44	3569	#if defined(RCC_DCKCFGR_CK48MSEL)
lypinator	0:bb348c97df44	3570	MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL, USBxSource);
lypinator	0:bb348c97df44	3571	#else
lypinator	0:bb348c97df44	3572	MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, USBxSource);
lypinator	0:bb348c97df44	3573	#endif /* RCC_DCKCFGR_CK48MSEL */
lypinator	0:bb348c97df44	3574	}
lypinator	0:bb348c97df44	3575	#endif /* USB_OTG_FS \|\| USB_OTG_HS */
lypinator	0:bb348c97df44	3576	#endif /* RCC_DCKCFGR_CK48MSEL \|\| RCC_DCKCFGR2_CK48MSEL */
lypinator	0:bb348c97df44	3577
lypinator	0:bb348c97df44	3578	#if defined(CEC)
lypinator	0:bb348c97df44	3579	/**
lypinator	0:bb348c97df44	3580	* @brief Configure CEC clock source
lypinator	0:bb348c97df44	3581	* @rmtoll DCKCFGR2 CECSEL LL_RCC_SetCECClockSource
lypinator	0:bb348c97df44	3582	* @param Source This parameter can be one of the following values:
lypinator	0:bb348c97df44	3583	* @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV488
lypinator	0:bb348c97df44	3584	* @arg @ref LL_RCC_CEC_CLKSOURCE_LSE
lypinator	0:bb348c97df44	3585	* @retval None
lypinator	0:bb348c97df44	3586	*/
lypinator	0:bb348c97df44	3587	__STATIC_INLINE void LL_RCC_SetCECClockSource(uint32_t Source)
lypinator	0:bb348c97df44	3588	{
lypinator	0:bb348c97df44	3589	MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, Source);
lypinator	0:bb348c97df44	3590	}
lypinator	0:bb348c97df44	3591	#endif /* CEC */
lypinator	0:bb348c97df44	3592
lypinator	0:bb348c97df44	3593	/**
lypinator	0:bb348c97df44	3594	* @brief Configure I2S clock source
lypinator	0:bb348c97df44	3595	* @rmtoll CFGR I2SSRC LL_RCC_SetI2SClockSource\n
lypinator	0:bb348c97df44	3596	* DCKCFGR I2SSRC LL_RCC_SetI2SClockSource\n
lypinator	0:bb348c97df44	3597	* DCKCFGR I2S1SRC LL_RCC_SetI2SClockSource\n
lypinator	0:bb348c97df44	3598	* DCKCFGR I2S2SRC LL_RCC_SetI2SClockSource
lypinator	0:bb348c97df44	3599	* @param Source This parameter can be one of the following values:
lypinator	0:bb348c97df44	3600	* @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLI2S (*)
lypinator	0:bb348c97df44	3601	* @arg @ref LL_RCC_I2S1_CLKSOURCE_PIN
lypinator	0:bb348c97df44	3602	* @arg @ref LL_RCC_I2S1_CLKSOURCE_PLL (*)
lypinator	0:bb348c97df44	3603	* @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLSRC (*)
lypinator	0:bb348c97df44	3604	* @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLI2S (*)
lypinator	0:bb348c97df44	3605	* @arg @ref LL_RCC_I2S2_CLKSOURCE_PIN (*)
lypinator	0:bb348c97df44	3606	* @arg @ref LL_RCC_I2S2_CLKSOURCE_PLL (*)
lypinator	0:bb348c97df44	3607	* @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLSRC (*)
lypinator	0:bb348c97df44	3608	*
lypinator	0:bb348c97df44	3609	* (*) value not defined in all devices.
lypinator	0:bb348c97df44	3610	* @retval None
lypinator	0:bb348c97df44	3611	*/
lypinator	0:bb348c97df44	3612	__STATIC_INLINE void LL_RCC_SetI2SClockSource(uint32_t Source)
lypinator	0:bb348c97df44	3613	{
lypinator	0:bb348c97df44	3614	#if defined(RCC_CFGR_I2SSRC)
lypinator	0:bb348c97df44	3615	MODIFY_REG(RCC->CFGR, RCC_CFGR_I2SSRC, Source);
lypinator	0:bb348c97df44	3616	#else
lypinator	0:bb348c97df44	3617	MODIFY_REG(RCC->DCKCFGR, (Source & 0xFFFF0000U), (Source << 16U));
lypinator	0:bb348c97df44	3618	#endif /* RCC_CFGR_I2SSRC */
lypinator	0:bb348c97df44	3619	}
lypinator	0:bb348c97df44	3620
lypinator	0:bb348c97df44	3621	#if defined(DSI)
lypinator	0:bb348c97df44	3622	/**
lypinator	0:bb348c97df44	3623	* @brief Configure DSI clock source
lypinator	0:bb348c97df44	3624	* @rmtoll DCKCFGR DSISEL LL_RCC_SetDSIClockSource
lypinator	0:bb348c97df44	3625	* @param Source This parameter can be one of the following values:
lypinator	0:bb348c97df44	3626	* @arg @ref LL_RCC_DSI_CLKSOURCE_PHY
lypinator	0:bb348c97df44	3627	* @arg @ref LL_RCC_DSI_CLKSOURCE_PLL
lypinator	0:bb348c97df44	3628	* @retval None
lypinator	0:bb348c97df44	3629	*/
lypinator	0:bb348c97df44	3630	__STATIC_INLINE void LL_RCC_SetDSIClockSource(uint32_t Source)
lypinator	0:bb348c97df44	3631	{
lypinator	0:bb348c97df44	3632	MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_DSISEL, Source);
lypinator	0:bb348c97df44	3633	}
lypinator	0:bb348c97df44	3634	#endif /* DSI */
lypinator	0:bb348c97df44	3635
lypinator	0:bb348c97df44	3636	#if defined(DFSDM1_Channel0)
lypinator	0:bb348c97df44	3637	/**
lypinator	0:bb348c97df44	3638	* @brief Configure DFSDM Audio clock source
lypinator	0:bb348c97df44	3639	* @rmtoll DCKCFGR CKDFSDM1ASEL LL_RCC_SetDFSDMAudioClockSource\n
lypinator	0:bb348c97df44	3640	* DCKCFGR CKDFSDM2ASEL LL_RCC_SetDFSDMAudioClockSource
lypinator	0:bb348c97df44	3641	* @param Source This parameter can be one of the following values:
lypinator	0:bb348c97df44	3642	* @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S1
lypinator	0:bb348c97df44	3643	* @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S2
lypinator	0:bb348c97df44	3644	* @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S1 (*)
lypinator	0:bb348c97df44	3645	* @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S2 (*)
lypinator	0:bb348c97df44	3646	*
lypinator	0:bb348c97df44	3647	* (*) value not defined in all devices.
lypinator	0:bb348c97df44	3648	* @retval None
lypinator	0:bb348c97df44	3649	*/
lypinator	0:bb348c97df44	3650	__STATIC_INLINE void LL_RCC_SetDFSDMAudioClockSource(uint32_t Source)
lypinator	0:bb348c97df44	3651	{
lypinator	0:bb348c97df44	3652	MODIFY_REG(RCC->DCKCFGR, (Source & 0x0000FFFFU), (Source >> 16U));
lypinator	0:bb348c97df44	3653	}
lypinator	0:bb348c97df44	3654
lypinator	0:bb348c97df44	3655	/**
lypinator	0:bb348c97df44	3656	* @brief Configure DFSDM Kernel clock source
lypinator	0:bb348c97df44	3657	* @rmtoll DCKCFGR CKDFSDM1SEL LL_RCC_SetDFSDMClockSource
lypinator	0:bb348c97df44	3658	* @param Source This parameter can be one of the following values:
lypinator	0:bb348c97df44	3659	* @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2
lypinator	0:bb348c97df44	3660	* @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK
lypinator	0:bb348c97df44	3661	* @arg @ref LL_RCC_DFSDM2_CLKSOURCE_PCLK2 (*)
lypinator	0:bb348c97df44	3662	* @arg @ref LL_RCC_DFSDM2_CLKSOURCE_SYSCLK (*)
lypinator	0:bb348c97df44	3663	*
lypinator	0:bb348c97df44	3664	* (*) value not defined in all devices.
lypinator	0:bb348c97df44	3665	* @retval None
lypinator	0:bb348c97df44	3666	*/
lypinator	0:bb348c97df44	3667	__STATIC_INLINE void LL_RCC_SetDFSDMClockSource(uint32_t Source)
lypinator	0:bb348c97df44	3668	{
lypinator	0:bb348c97df44	3669	MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL, Source);
lypinator	0:bb348c97df44	3670	}
lypinator	0:bb348c97df44	3671	#endif /* DFSDM1_Channel0 */
lypinator	0:bb348c97df44	3672
lypinator	0:bb348c97df44	3673	#if defined(SPDIFRX)
lypinator	0:bb348c97df44	3674	/**
lypinator	0:bb348c97df44	3675	* @brief Configure SPDIFRX clock source
lypinator	0:bb348c97df44	3676	* @rmtoll DCKCFGR2 SPDIFRXSEL LL_RCC_SetSPDIFRXClockSource
lypinator	0:bb348c97df44	3677	* @param SPDIFRXxSource This parameter can be one of the following values:
lypinator	0:bb348c97df44	3678	* @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_PLL
lypinator	0:bb348c97df44	3679	* @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_PLLI2S
lypinator	0:bb348c97df44	3680	*
lypinator	0:bb348c97df44	3681	* (*) value not defined in all devices.
lypinator	0:bb348c97df44	3682	* @retval None
lypinator	0:bb348c97df44	3683	*/
lypinator	0:bb348c97df44	3684	__STATIC_INLINE void LL_RCC_SetSPDIFRXClockSource(uint32_t SPDIFRXxSource)
lypinator	0:bb348c97df44	3685	{
lypinator	0:bb348c97df44	3686	MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL, SPDIFRXxSource);
lypinator	0:bb348c97df44	3687	}
lypinator	0:bb348c97df44	3688	#endif /* SPDIFRX */
lypinator	0:bb348c97df44	3689
lypinator	0:bb348c97df44	3690	#if defined(FMPI2C1)
lypinator	0:bb348c97df44	3691	/**
lypinator	0:bb348c97df44	3692	* @brief Get FMPI2C clock source
lypinator	0:bb348c97df44	3693	* @rmtoll DCKCFGR2 FMPI2C1SEL LL_RCC_GetFMPI2CClockSource
lypinator	0:bb348c97df44	3694	* @param FMPI2Cx This parameter can be one of the following values:
lypinator	0:bb348c97df44	3695	* @arg @ref LL_RCC_FMPI2C1_CLKSOURCE
lypinator	0:bb348c97df44	3696	* @retval Returned value can be one of the following values:
lypinator	0:bb348c97df44	3697	* @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_PCLK1
lypinator	0:bb348c97df44	3698	* @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_SYSCLK
lypinator	0:bb348c97df44	3699	* @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_HSI
lypinator	0:bb348c97df44	3700	*/
lypinator	0:bb348c97df44	3701	__STATIC_INLINE uint32_t LL_RCC_GetFMPI2CClockSource(uint32_t FMPI2Cx)
lypinator	0:bb348c97df44	3702	{
lypinator	0:bb348c97df44	3703	return (uint32_t)(READ_BIT(RCC->DCKCFGR2, FMPI2Cx));
lypinator	0:bb348c97df44	3704	}
lypinator	0:bb348c97df44	3705	#endif /* FMPI2C1 */
lypinator	0:bb348c97df44	3706
lypinator	0:bb348c97df44	3707	#if defined(LPTIM1)
lypinator	0:bb348c97df44	3708	/**
lypinator	0:bb348c97df44	3709	* @brief Get LPTIMx clock source
lypinator	0:bb348c97df44	3710	* @rmtoll DCKCFGR2 LPTIM1SEL LL_RCC_GetLPTIMClockSource
lypinator	0:bb348c97df44	3711	* @param LPTIMx This parameter can be one of the following values:
lypinator	0:bb348c97df44	3712	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE
lypinator	0:bb348c97df44	3713	* @retval Returned value can be one of the following values:
lypinator	0:bb348c97df44	3714	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
lypinator	0:bb348c97df44	3715	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
lypinator	0:bb348c97df44	3716	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
lypinator	0:bb348c97df44	3717	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
lypinator	0:bb348c97df44	3718	*/
lypinator	0:bb348c97df44	3719	__STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx)
lypinator	0:bb348c97df44	3720	{
lypinator	0:bb348c97df44	3721	return (uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL));
lypinator	0:bb348c97df44	3722	}
lypinator	0:bb348c97df44	3723	#endif /* LPTIM1 */
lypinator	0:bb348c97df44	3724
lypinator	0:bb348c97df44	3725	#if defined(SAI1)
lypinator	0:bb348c97df44	3726	/**
lypinator	0:bb348c97df44	3727	* @brief Get SAIx clock source
lypinator	0:bb348c97df44	3728	* @rmtoll DCKCFGR SAI1SEL LL_RCC_GetSAIClockSource\n
lypinator	0:bb348c97df44	3729	* DCKCFGR SAI2SEL LL_RCC_GetSAIClockSource\n
lypinator	0:bb348c97df44	3730	* DCKCFGR SAI1ASRC LL_RCC_GetSAIClockSource\n
lypinator	0:bb348c97df44	3731	* DCKCFGR SAI1BSRC LL_RCC_GetSAIClockSource
lypinator	0:bb348c97df44	3732	* @param SAIx This parameter can be one of the following values:
lypinator	0:bb348c97df44	3733	* @arg @ref LL_RCC_SAI1_CLKSOURCE (*)
lypinator	0:bb348c97df44	3734	* @arg @ref LL_RCC_SAI2_CLKSOURCE (*)
lypinator	0:bb348c97df44	3735	* @arg @ref LL_RCC_SAI1_A_CLKSOURCE (*)
lypinator	0:bb348c97df44	3736	* @arg @ref LL_RCC_SAI1_B_CLKSOURCE (*)
lypinator	0:bb348c97df44	3737	*
lypinator	0:bb348c97df44	3738	* (*) value not defined in all devices.
lypinator	0:bb348c97df44	3739	* @retval Returned value can be one of the following values:
lypinator	0:bb348c97df44	3740	* @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI (*)
lypinator	0:bb348c97df44	3741	* @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLI2S (*)
lypinator	0:bb348c97df44	3742	* @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL (*)
lypinator	0:bb348c97df44	3743	* @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN (*)
lypinator	0:bb348c97df44	3744	* @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI (*)
lypinator	0:bb348c97df44	3745	* @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLI2S (*)
lypinator	0:bb348c97df44	3746	* @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL (*)
lypinator	0:bb348c97df44	3747	* @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSRC (*)
lypinator	0:bb348c97df44	3748	* @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLSAI (*)
lypinator	0:bb348c97df44	3749	* @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLI2S (*)
lypinator	0:bb348c97df44	3750	* @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PIN (*)
lypinator	0:bb348c97df44	3751	* @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLL (*)
lypinator	0:bb348c97df44	3752	* @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLSRC (*)
lypinator	0:bb348c97df44	3753	* @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLSAI (*)
lypinator	0:bb348c97df44	3754	* @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLI2S (*)
lypinator	0:bb348c97df44	3755	* @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PIN (*)
lypinator	0:bb348c97df44	3756	* @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLL (*)
lypinator	0:bb348c97df44	3757	* @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLSRC (*)
lypinator	0:bb348c97df44	3758	*
lypinator	0:bb348c97df44	3759	* (*) value not defined in all devices.
lypinator	0:bb348c97df44	3760	*/
lypinator	0:bb348c97df44	3761	__STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t SAIx)
lypinator	0:bb348c97df44	3762	{
lypinator	0:bb348c97df44	3763	return (uint32_t)(READ_BIT(RCC->DCKCFGR, SAIx) >> 16U \| SAIx);
lypinator	0:bb348c97df44	3764	}
lypinator	0:bb348c97df44	3765	#endif /* SAI1 */
lypinator	0:bb348c97df44	3766
lypinator	0:bb348c97df44	3767	#if defined(RCC_DCKCFGR_SDIOSEL) \|\| defined(RCC_DCKCFGR2_SDIOSEL)
lypinator	0:bb348c97df44	3768	/**
lypinator	0:bb348c97df44	3769	* @brief Get SDIOx clock source
lypinator	0:bb348c97df44	3770	* @rmtoll DCKCFGR SDIOSEL LL_RCC_GetSDIOClockSource\n
lypinator	0:bb348c97df44	3771	* DCKCFGR2 SDIOSEL LL_RCC_GetSDIOClockSource
lypinator	0:bb348c97df44	3772	* @param SDIOx This parameter can be one of the following values:
lypinator	0:bb348c97df44	3773	* @arg @ref LL_RCC_SDIO_CLKSOURCE
lypinator	0:bb348c97df44	3774	* @retval Returned value can be one of the following values:
lypinator	0:bb348c97df44	3775	* @arg @ref LL_RCC_SDIO_CLKSOURCE_PLL48CLK
lypinator	0:bb348c97df44	3776	* @arg @ref LL_RCC_SDIO_CLKSOURCE_SYSCLK
lypinator	0:bb348c97df44	3777	*/
lypinator	0:bb348c97df44	3778	__STATIC_INLINE uint32_t LL_RCC_GetSDIOClockSource(uint32_t SDIOx)
lypinator	0:bb348c97df44	3779	{
lypinator	0:bb348c97df44	3780	#if defined(RCC_DCKCFGR_SDIOSEL)
lypinator	0:bb348c97df44	3781	return (uint32_t)(READ_BIT(RCC->DCKCFGR, SDIOx));
lypinator	0:bb348c97df44	3782	#else
lypinator	0:bb348c97df44	3783	return (uint32_t)(READ_BIT(RCC->DCKCFGR2, SDIOx));
lypinator	0:bb348c97df44	3784	#endif /* RCC_DCKCFGR_SDIOSEL */
lypinator	0:bb348c97df44	3785	}
lypinator	0:bb348c97df44	3786	#endif /* RCC_DCKCFGR_SDIOSEL \|\| RCC_DCKCFGR2_SDIOSEL */
lypinator	0:bb348c97df44	3787
lypinator	0:bb348c97df44	3788	#if defined(RCC_DCKCFGR_CK48MSEL) \|\| defined(RCC_DCKCFGR2_CK48MSEL)
lypinator	0:bb348c97df44	3789	/**
lypinator	0:bb348c97df44	3790	* @brief Get 48Mhz domain clock source
lypinator	0:bb348c97df44	3791	* @rmtoll DCKCFGR CK48MSEL LL_RCC_GetCK48MClockSource\n
lypinator	0:bb348c97df44	3792	* DCKCFGR2 CK48MSEL LL_RCC_GetCK48MClockSource
lypinator	0:bb348c97df44	3793	* @param CK48Mx This parameter can be one of the following values:
lypinator	0:bb348c97df44	3794	* @arg @ref LL_RCC_CK48M_CLKSOURCE
lypinator	0:bb348c97df44	3795	* @retval Returned value can be one of the following values:
lypinator	0:bb348c97df44	3796	* @arg @ref LL_RCC_CK48M_CLKSOURCE_PLL
lypinator	0:bb348c97df44	3797	* @arg @ref LL_RCC_CK48M_CLKSOURCE_PLLSAI (*)
lypinator	0:bb348c97df44	3798	* @arg @ref LL_RCC_CK48M_CLKSOURCE_PLLI2S (*)
lypinator	0:bb348c97df44	3799	*
lypinator	0:bb348c97df44	3800	* (*) value not defined in all devices.
lypinator	0:bb348c97df44	3801	*/
lypinator	0:bb348c97df44	3802	__STATIC_INLINE uint32_t LL_RCC_GetCK48MClockSource(uint32_t CK48Mx)
lypinator	0:bb348c97df44	3803	{
lypinator	0:bb348c97df44	3804	#if defined(RCC_DCKCFGR_CK48MSEL)
lypinator	0:bb348c97df44	3805	return (uint32_t)(READ_BIT(RCC->DCKCFGR, CK48Mx));
lypinator	0:bb348c97df44	3806	#else
lypinator	0:bb348c97df44	3807	return (uint32_t)(READ_BIT(RCC->DCKCFGR2, CK48Mx));
lypinator	0:bb348c97df44	3808	#endif /* RCC_DCKCFGR_CK48MSEL */
lypinator	0:bb348c97df44	3809	}
lypinator	0:bb348c97df44	3810
lypinator	0:bb348c97df44	3811	#if defined(RNG)
lypinator	0:bb348c97df44	3812	/**
lypinator	0:bb348c97df44	3813	* @brief Get RNGx clock source
lypinator	0:bb348c97df44	3814	* @rmtoll DCKCFGR CK48MSEL LL_RCC_GetRNGClockSource\n
lypinator	0:bb348c97df44	3815	* DCKCFGR2 CK48MSEL LL_RCC_GetRNGClockSource
lypinator	0:bb348c97df44	3816	* @param RNGx This parameter can be one of the following values:
lypinator	0:bb348c97df44	3817	* @arg @ref LL_RCC_RNG_CLKSOURCE
lypinator	0:bb348c97df44	3818	* @retval Returned value can be one of the following values:
lypinator	0:bb348c97df44	3819	* @arg @ref LL_RCC_RNG_CLKSOURCE_PLL
lypinator	0:bb348c97df44	3820	* @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI (*)
lypinator	0:bb348c97df44	3821	* @arg @ref LL_RCC_RNG_CLKSOURCE_PLLI2S (*)
lypinator	0:bb348c97df44	3822	*
lypinator	0:bb348c97df44	3823	* (*) value not defined in all devices.
lypinator	0:bb348c97df44	3824	*/
lypinator	0:bb348c97df44	3825	__STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t RNGx)
lypinator	0:bb348c97df44	3826	{
lypinator	0:bb348c97df44	3827	#if defined(RCC_DCKCFGR_CK48MSEL)
lypinator	0:bb348c97df44	3828	return (uint32_t)(READ_BIT(RCC->DCKCFGR, RNGx));
lypinator	0:bb348c97df44	3829	#else
lypinator	0:bb348c97df44	3830	return (uint32_t)(READ_BIT(RCC->DCKCFGR2, RNGx));
lypinator	0:bb348c97df44	3831	#endif /* RCC_DCKCFGR_CK48MSEL */
lypinator	0:bb348c97df44	3832	}
lypinator	0:bb348c97df44	3833	#endif /* RNG */
lypinator	0:bb348c97df44	3834
lypinator	0:bb348c97df44	3835	#if defined(USB_OTG_FS) \|\| defined(USB_OTG_HS)
lypinator	0:bb348c97df44	3836	/**
lypinator	0:bb348c97df44	3837	* @brief Get USBx clock source
lypinator	0:bb348c97df44	3838	* @rmtoll DCKCFGR CK48MSEL LL_RCC_GetUSBClockSource\n
lypinator	0:bb348c97df44	3839	* DCKCFGR2 CK48MSEL LL_RCC_GetUSBClockSource
lypinator	0:bb348c97df44	3840	* @param USBx This parameter can be one of the following values:
lypinator	0:bb348c97df44	3841	* @arg @ref LL_RCC_USB_CLKSOURCE
lypinator	0:bb348c97df44	3842	* @retval Returned value can be one of the following values:
lypinator	0:bb348c97df44	3843	* @arg @ref LL_RCC_USB_CLKSOURCE_PLL
lypinator	0:bb348c97df44	3844	* @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI (*)
lypinator	0:bb348c97df44	3845	* @arg @ref LL_RCC_USB_CLKSOURCE_PLLI2S (*)
lypinator	0:bb348c97df44	3846	*
lypinator	0:bb348c97df44	3847	* (*) value not defined in all devices.
lypinator	0:bb348c97df44	3848	*/
lypinator	0:bb348c97df44	3849	__STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx)
lypinator	0:bb348c97df44	3850	{
lypinator	0:bb348c97df44	3851	#if defined(RCC_DCKCFGR_CK48MSEL)
lypinator	0:bb348c97df44	3852	return (uint32_t)(READ_BIT(RCC->DCKCFGR, USBx));
lypinator	0:bb348c97df44	3853	#else
lypinator	0:bb348c97df44	3854	return (uint32_t)(READ_BIT(RCC->DCKCFGR2, USBx));
lypinator	0:bb348c97df44	3855	#endif /* RCC_DCKCFGR_CK48MSEL */
lypinator	0:bb348c97df44	3856	}
lypinator	0:bb348c97df44	3857	#endif /* USB_OTG_FS \|\| USB_OTG_HS */
lypinator	0:bb348c97df44	3858	#endif /* RCC_DCKCFGR_CK48MSEL \|\| RCC_DCKCFGR2_CK48MSEL */
lypinator	0:bb348c97df44	3859
lypinator	0:bb348c97df44	3860	#if defined(CEC)
lypinator	0:bb348c97df44	3861	/**
lypinator	0:bb348c97df44	3862	* @brief Get CEC Clock Source
lypinator	0:bb348c97df44	3863	* @rmtoll DCKCFGR2 CECSEL LL_RCC_GetCECClockSource
lypinator	0:bb348c97df44	3864	* @param CECx This parameter can be one of the following values:
lypinator	0:bb348c97df44	3865	* @arg @ref LL_RCC_CEC_CLKSOURCE
lypinator	0:bb348c97df44	3866	* @retval Returned value can be one of the following values:
lypinator	0:bb348c97df44	3867	* @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV488
lypinator	0:bb348c97df44	3868	* @arg @ref LL_RCC_CEC_CLKSOURCE_LSE
lypinator	0:bb348c97df44	3869	*/
lypinator	0:bb348c97df44	3870	__STATIC_INLINE uint32_t LL_RCC_GetCECClockSource(uint32_t CECx)
lypinator	0:bb348c97df44	3871	{
lypinator	0:bb348c97df44	3872	return (uint32_t)(READ_BIT(RCC->DCKCFGR2, CECx));
lypinator	0:bb348c97df44	3873	}
lypinator	0:bb348c97df44	3874	#endif /* CEC */
lypinator	0:bb348c97df44	3875
lypinator	0:bb348c97df44	3876	/**
lypinator	0:bb348c97df44	3877	* @brief Get I2S Clock Source
lypinator	0:bb348c97df44	3878	* @rmtoll CFGR I2SSRC LL_RCC_GetI2SClockSource\n
lypinator	0:bb348c97df44	3879	* DCKCFGR I2SSRC LL_RCC_GetI2SClockSource\n
lypinator	0:bb348c97df44	3880	* DCKCFGR I2S1SRC LL_RCC_GetI2SClockSource\n
lypinator	0:bb348c97df44	3881	* DCKCFGR I2S2SRC LL_RCC_GetI2SClockSource
lypinator	0:bb348c97df44	3882	* @param I2Sx This parameter can be one of the following values:
lypinator	0:bb348c97df44	3883	* @arg @ref LL_RCC_I2S1_CLKSOURCE
lypinator	0:bb348c97df44	3884	* @arg @ref LL_RCC_I2S2_CLKSOURCE (*)
lypinator	0:bb348c97df44	3885	* @retval Returned value can be one of the following values:
lypinator	0:bb348c97df44	3886	* @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLI2S (*)
lypinator	0:bb348c97df44	3887	* @arg @ref LL_RCC_I2S1_CLKSOURCE_PIN
lypinator	0:bb348c97df44	3888	* @arg @ref LL_RCC_I2S1_CLKSOURCE_PLL (*)
lypinator	0:bb348c97df44	3889	* @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLSRC (*)
lypinator	0:bb348c97df44	3890	* @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLI2S (*)
lypinator	0:bb348c97df44	3891	* @arg @ref LL_RCC_I2S2_CLKSOURCE_PIN (*)
lypinator	0:bb348c97df44	3892	* @arg @ref LL_RCC_I2S2_CLKSOURCE_PLL (*)
lypinator	0:bb348c97df44	3893	* @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLSRC (*)
lypinator	0:bb348c97df44	3894	*
lypinator	0:bb348c97df44	3895	* (*) value not defined in all devices.
lypinator	0:bb348c97df44	3896	*/
lypinator	0:bb348c97df44	3897	__STATIC_INLINE uint32_t LL_RCC_GetI2SClockSource(uint32_t I2Sx)
lypinator	0:bb348c97df44	3898	{
lypinator	0:bb348c97df44	3899	#if defined(RCC_CFGR_I2SSRC)
lypinator	0:bb348c97df44	3900	return (uint32_t)(READ_BIT(RCC->CFGR, I2Sx));
lypinator	0:bb348c97df44	3901	#else
lypinator	0:bb348c97df44	3902	return (uint32_t)(READ_BIT(RCC->DCKCFGR, I2Sx) >> 16U \| I2Sx);
lypinator	0:bb348c97df44	3903	#endif /* RCC_CFGR_I2SSRC */
lypinator	0:bb348c97df44	3904	}
lypinator	0:bb348c97df44	3905
lypinator	0:bb348c97df44	3906	#if defined(DFSDM1_Channel0)
lypinator	0:bb348c97df44	3907	/**
lypinator	0:bb348c97df44	3908	* @brief Get DFSDM Audio Clock Source
lypinator	0:bb348c97df44	3909	* @rmtoll DCKCFGR CKDFSDM1ASEL LL_RCC_GetDFSDMAudioClockSource\n
lypinator	0:bb348c97df44	3910	* DCKCFGR CKDFSDM2ASEL LL_RCC_GetDFSDMAudioClockSource
lypinator	0:bb348c97df44	3911	* @param DFSDMx This parameter can be one of the following values:
lypinator	0:bb348c97df44	3912	* @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE
lypinator	0:bb348c97df44	3913	* @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE (*)
lypinator	0:bb348c97df44	3914	* @retval Returned value can be one of the following values:
lypinator	0:bb348c97df44	3915	* @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S1
lypinator	0:bb348c97df44	3916	* @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S2
lypinator	0:bb348c97df44	3917	* @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S1 (*)
lypinator	0:bb348c97df44	3918	* @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S2 (*)
lypinator	0:bb348c97df44	3919	*
lypinator	0:bb348c97df44	3920	* (*) value not defined in all devices.
lypinator	0:bb348c97df44	3921	*/
lypinator	0:bb348c97df44	3922	__STATIC_INLINE uint32_t LL_RCC_GetDFSDMAudioClockSource(uint32_t DFSDMx)
lypinator	0:bb348c97df44	3923	{
lypinator	0:bb348c97df44	3924	return (uint32_t)(READ_BIT(RCC->DCKCFGR, DFSDMx) << 16U \| DFSDMx);
lypinator	0:bb348c97df44	3925	}
lypinator	0:bb348c97df44	3926
lypinator	0:bb348c97df44	3927	/**
lypinator	0:bb348c97df44	3928	* @brief Get DFSDM Audio Clock Source
lypinator	0:bb348c97df44	3929	* @rmtoll DCKCFGR CKDFSDM1SEL LL_RCC_GetDFSDMClockSource
lypinator	0:bb348c97df44	3930	* @param DFSDMx This parameter can be one of the following values:
lypinator	0:bb348c97df44	3931	* @arg @ref LL_RCC_DFSDM1_CLKSOURCE
lypinator	0:bb348c97df44	3932	* @arg @ref LL_RCC_DFSDM2_CLKSOURCE (*)
lypinator	0:bb348c97df44	3933	* @retval Returned value can be one of the following values:
lypinator	0:bb348c97df44	3934	* @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2
lypinator	0:bb348c97df44	3935	* @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK
lypinator	0:bb348c97df44	3936	* @arg @ref LL_RCC_DFSDM2_CLKSOURCE_PCLK2 (*)
lypinator	0:bb348c97df44	3937	* @arg @ref LL_RCC_DFSDM2_CLKSOURCE_SYSCLK (*)
lypinator	0:bb348c97df44	3938	*
lypinator	0:bb348c97df44	3939	* (*) value not defined in all devices.
lypinator	0:bb348c97df44	3940	*/
lypinator	0:bb348c97df44	3941	__STATIC_INLINE uint32_t LL_RCC_GetDFSDMClockSource(uint32_t DFSDMx)
lypinator	0:bb348c97df44	3942	{
lypinator	0:bb348c97df44	3943	return (uint32_t)(READ_BIT(RCC->DCKCFGR, DFSDMx));
lypinator	0:bb348c97df44	3944	}
lypinator	0:bb348c97df44	3945	#endif /* DFSDM1_Channel0 */
lypinator	0:bb348c97df44	3946
lypinator	0:bb348c97df44	3947	#if defined(SPDIFRX)
lypinator	0:bb348c97df44	3948	/**
lypinator	0:bb348c97df44	3949	* @brief Get SPDIFRX clock source
lypinator	0:bb348c97df44	3950	* @rmtoll DCKCFGR2 SPDIFRXSEL LL_RCC_GetSPDIFRXClockSource
lypinator	0:bb348c97df44	3951	* @param SPDIFRXx This parameter can be one of the following values:
lypinator	0:bb348c97df44	3952	* @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE
lypinator	0:bb348c97df44	3953	* @retval Returned value can be one of the following values:
lypinator	0:bb348c97df44	3954	* @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_PLL
lypinator	0:bb348c97df44	3955	* @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_PLLI2S
lypinator	0:bb348c97df44	3956	*
lypinator	0:bb348c97df44	3957	* (*) value not defined in all devices.
lypinator	0:bb348c97df44	3958	*/
lypinator	0:bb348c97df44	3959	__STATIC_INLINE uint32_t LL_RCC_GetSPDIFRXClockSource(uint32_t SPDIFRXx)
lypinator	0:bb348c97df44	3960	{
lypinator	0:bb348c97df44	3961	return (uint32_t)(READ_BIT(RCC->DCKCFGR2, SPDIFRXx));
lypinator	0:bb348c97df44	3962	}
lypinator	0:bb348c97df44	3963	#endif /* SPDIFRX */
lypinator	0:bb348c97df44	3964
lypinator	0:bb348c97df44	3965	#if defined(DSI)
lypinator	0:bb348c97df44	3966	/**
lypinator	0:bb348c97df44	3967	* @brief Get DSI Clock Source
lypinator	0:bb348c97df44	3968	* @rmtoll DCKCFGR DSISEL LL_RCC_GetDSIClockSource
lypinator	0:bb348c97df44	3969	* @param DSIx This parameter can be one of the following values:
lypinator	0:bb348c97df44	3970	* @arg @ref LL_RCC_DSI_CLKSOURCE
lypinator	0:bb348c97df44	3971	* @retval Returned value can be one of the following values:
lypinator	0:bb348c97df44	3972	* @arg @ref LL_RCC_DSI_CLKSOURCE_PHY
lypinator	0:bb348c97df44	3973	* @arg @ref LL_RCC_DSI_CLKSOURCE_PLL
lypinator	0:bb348c97df44	3974	*/
lypinator	0:bb348c97df44	3975	__STATIC_INLINE uint32_t LL_RCC_GetDSIClockSource(uint32_t DSIx)
lypinator	0:bb348c97df44	3976	{
lypinator	0:bb348c97df44	3977	return (uint32_t)(READ_BIT(RCC->DCKCFGR, DSIx));
lypinator	0:bb348c97df44	3978	}
lypinator	0:bb348c97df44	3979	#endif /* DSI */
lypinator	0:bb348c97df44	3980
lypinator	0:bb348c97df44	3981	/**
lypinator	0:bb348c97df44	3982	* @}
lypinator	0:bb348c97df44	3983	*/
lypinator	0:bb348c97df44	3984
lypinator	0:bb348c97df44	3985	/** @defgroup RCC_LL_EF_RTC RTC
lypinator	0:bb348c97df44	3986	* @{
lypinator	0:bb348c97df44	3987	*/
lypinator	0:bb348c97df44	3988
lypinator	0:bb348c97df44	3989	/**
lypinator	0:bb348c97df44	3990	* @brief Set RTC Clock Source
lypinator	0:bb348c97df44	3991	* @note Once the RTC clock source has been selected, it cannot be changed anymore unless
lypinator	0:bb348c97df44	3992	* the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is
lypinator	0:bb348c97df44	3993	* set). The BDRST bit can be used to reset them.
lypinator	0:bb348c97df44	3994	* @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource
lypinator	0:bb348c97df44	3995	* @param Source This parameter can be one of the following values:
lypinator	0:bb348c97df44	3996	* @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
lypinator	0:bb348c97df44	3997	* @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
lypinator	0:bb348c97df44	3998	* @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
lypinator	0:bb348c97df44	3999	* @arg @ref LL_RCC_RTC_CLKSOURCE_HSE
lypinator	0:bb348c97df44	4000	* @retval None
lypinator	0:bb348c97df44	4001	*/
lypinator	0:bb348c97df44	4002	__STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
lypinator	0:bb348c97df44	4003	{
lypinator	0:bb348c97df44	4004	MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source);
lypinator	0:bb348c97df44	4005	}
lypinator	0:bb348c97df44	4006
lypinator	0:bb348c97df44	4007	/**
lypinator	0:bb348c97df44	4008	* @brief Get RTC Clock Source
lypinator	0:bb348c97df44	4009	* @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource
lypinator	0:bb348c97df44	4010	* @retval Returned value can be one of the following values:
lypinator	0:bb348c97df44	4011	* @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
lypinator	0:bb348c97df44	4012	* @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
lypinator	0:bb348c97df44	4013	* @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
lypinator	0:bb348c97df44	4014	* @arg @ref LL_RCC_RTC_CLKSOURCE_HSE
lypinator	0:bb348c97df44	4015	*/
lypinator	0:bb348c97df44	4016	__STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
lypinator	0:bb348c97df44	4017	{
lypinator	0:bb348c97df44	4018	return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL));
lypinator	0:bb348c97df44	4019	}
lypinator	0:bb348c97df44	4020
lypinator	0:bb348c97df44	4021	/**
lypinator	0:bb348c97df44	4022	* @brief Enable RTC
lypinator	0:bb348c97df44	4023	* @rmtoll BDCR RTCEN LL_RCC_EnableRTC
lypinator	0:bb348c97df44	4024	* @retval None
lypinator	0:bb348c97df44	4025	*/
lypinator	0:bb348c97df44	4026	__STATIC_INLINE void LL_RCC_EnableRTC(void)
lypinator	0:bb348c97df44	4027	{
lypinator	0:bb348c97df44	4028	SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
lypinator	0:bb348c97df44	4029	}
lypinator	0:bb348c97df44	4030
lypinator	0:bb348c97df44	4031	/**
lypinator	0:bb348c97df44	4032	* @brief Disable RTC
lypinator	0:bb348c97df44	4033	* @rmtoll BDCR RTCEN LL_RCC_DisableRTC
lypinator	0:bb348c97df44	4034	* @retval None
lypinator	0:bb348c97df44	4035	*/
lypinator	0:bb348c97df44	4036	__STATIC_INLINE void LL_RCC_DisableRTC(void)
lypinator	0:bb348c97df44	4037	{
lypinator	0:bb348c97df44	4038	CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
lypinator	0:bb348c97df44	4039	}
lypinator	0:bb348c97df44	4040
lypinator	0:bb348c97df44	4041	/**
lypinator	0:bb348c97df44	4042	* @brief Check if RTC has been enabled or not
lypinator	0:bb348c97df44	4043	* @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC
lypinator	0:bb348c97df44	4044	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	4045	*/
lypinator	0:bb348c97df44	4046	__STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)
lypinator	0:bb348c97df44	4047	{
lypinator	0:bb348c97df44	4048	return (READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN));
lypinator	0:bb348c97df44	4049	}
lypinator	0:bb348c97df44	4050
lypinator	0:bb348c97df44	4051	/**
lypinator	0:bb348c97df44	4052	* @brief Force the Backup domain reset
lypinator	0:bb348c97df44	4053	* @rmtoll BDCR BDRST LL_RCC_ForceBackupDomainReset
lypinator	0:bb348c97df44	4054	* @retval None
lypinator	0:bb348c97df44	4055	*/
lypinator	0:bb348c97df44	4056	__STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
lypinator	0:bb348c97df44	4057	{
lypinator	0:bb348c97df44	4058	SET_BIT(RCC->BDCR, RCC_BDCR_BDRST);
lypinator	0:bb348c97df44	4059	}
lypinator	0:bb348c97df44	4060
lypinator	0:bb348c97df44	4061	/**
lypinator	0:bb348c97df44	4062	* @brief Release the Backup domain reset
lypinator	0:bb348c97df44	4063	* @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset
lypinator	0:bb348c97df44	4064	* @retval None
lypinator	0:bb348c97df44	4065	*/
lypinator	0:bb348c97df44	4066	__STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
lypinator	0:bb348c97df44	4067	{
lypinator	0:bb348c97df44	4068	CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST);
lypinator	0:bb348c97df44	4069	}
lypinator	0:bb348c97df44	4070
lypinator	0:bb348c97df44	4071	/**
lypinator	0:bb348c97df44	4072	* @brief Set HSE Prescalers for RTC Clock
lypinator	0:bb348c97df44	4073	* @rmtoll CFGR RTCPRE LL_RCC_SetRTC_HSEPrescaler
lypinator	0:bb348c97df44	4074	* @param Prescaler This parameter can be one of the following values:
lypinator	0:bb348c97df44	4075	* @arg @ref LL_RCC_RTC_NOCLOCK
lypinator	0:bb348c97df44	4076	* @arg @ref LL_RCC_RTC_HSE_DIV_2
lypinator	0:bb348c97df44	4077	* @arg @ref LL_RCC_RTC_HSE_DIV_3
lypinator	0:bb348c97df44	4078	* @arg @ref LL_RCC_RTC_HSE_DIV_4
lypinator	0:bb348c97df44	4079	* @arg @ref LL_RCC_RTC_HSE_DIV_5
lypinator	0:bb348c97df44	4080	* @arg @ref LL_RCC_RTC_HSE_DIV_6
lypinator	0:bb348c97df44	4081	* @arg @ref LL_RCC_RTC_HSE_DIV_7
lypinator	0:bb348c97df44	4082	* @arg @ref LL_RCC_RTC_HSE_DIV_8
lypinator	0:bb348c97df44	4083	* @arg @ref LL_RCC_RTC_HSE_DIV_9
lypinator	0:bb348c97df44	4084	* @arg @ref LL_RCC_RTC_HSE_DIV_10
lypinator	0:bb348c97df44	4085	* @arg @ref LL_RCC_RTC_HSE_DIV_11
lypinator	0:bb348c97df44	4086	* @arg @ref LL_RCC_RTC_HSE_DIV_12
lypinator	0:bb348c97df44	4087	* @arg @ref LL_RCC_RTC_HSE_DIV_13
lypinator	0:bb348c97df44	4088	* @arg @ref LL_RCC_RTC_HSE_DIV_14
lypinator	0:bb348c97df44	4089	* @arg @ref LL_RCC_RTC_HSE_DIV_15
lypinator	0:bb348c97df44	4090	* @arg @ref LL_RCC_RTC_HSE_DIV_16
lypinator	0:bb348c97df44	4091	* @arg @ref LL_RCC_RTC_HSE_DIV_17
lypinator	0:bb348c97df44	4092	* @arg @ref LL_RCC_RTC_HSE_DIV_18
lypinator	0:bb348c97df44	4093	* @arg @ref LL_RCC_RTC_HSE_DIV_19
lypinator	0:bb348c97df44	4094	* @arg @ref LL_RCC_RTC_HSE_DIV_20
lypinator	0:bb348c97df44	4095	* @arg @ref LL_RCC_RTC_HSE_DIV_21
lypinator	0:bb348c97df44	4096	* @arg @ref LL_RCC_RTC_HSE_DIV_22
lypinator	0:bb348c97df44	4097	* @arg @ref LL_RCC_RTC_HSE_DIV_23
lypinator	0:bb348c97df44	4098	* @arg @ref LL_RCC_RTC_HSE_DIV_24
lypinator	0:bb348c97df44	4099	* @arg @ref LL_RCC_RTC_HSE_DIV_25
lypinator	0:bb348c97df44	4100	* @arg @ref LL_RCC_RTC_HSE_DIV_26
lypinator	0:bb348c97df44	4101	* @arg @ref LL_RCC_RTC_HSE_DIV_27
lypinator	0:bb348c97df44	4102	* @arg @ref LL_RCC_RTC_HSE_DIV_28
lypinator	0:bb348c97df44	4103	* @arg @ref LL_RCC_RTC_HSE_DIV_29
lypinator	0:bb348c97df44	4104	* @arg @ref LL_RCC_RTC_HSE_DIV_30
lypinator	0:bb348c97df44	4105	* @arg @ref LL_RCC_RTC_HSE_DIV_31
lypinator	0:bb348c97df44	4106	* @retval None
lypinator	0:bb348c97df44	4107	*/
lypinator	0:bb348c97df44	4108	__STATIC_INLINE void LL_RCC_SetRTC_HSEPrescaler(uint32_t Prescaler)
lypinator	0:bb348c97df44	4109	{
lypinator	0:bb348c97df44	4110	MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, Prescaler);
lypinator	0:bb348c97df44	4111	}
lypinator	0:bb348c97df44	4112
lypinator	0:bb348c97df44	4113	/**
lypinator	0:bb348c97df44	4114	* @brief Get HSE Prescalers for RTC Clock
lypinator	0:bb348c97df44	4115	* @rmtoll CFGR RTCPRE LL_RCC_GetRTC_HSEPrescaler
lypinator	0:bb348c97df44	4116	* @retval Returned value can be one of the following values:
lypinator	0:bb348c97df44	4117	* @arg @ref LL_RCC_RTC_NOCLOCK
lypinator	0:bb348c97df44	4118	* @arg @ref LL_RCC_RTC_HSE_DIV_2
lypinator	0:bb348c97df44	4119	* @arg @ref LL_RCC_RTC_HSE_DIV_3
lypinator	0:bb348c97df44	4120	* @arg @ref LL_RCC_RTC_HSE_DIV_4
lypinator	0:bb348c97df44	4121	* @arg @ref LL_RCC_RTC_HSE_DIV_5
lypinator	0:bb348c97df44	4122	* @arg @ref LL_RCC_RTC_HSE_DIV_6
lypinator	0:bb348c97df44	4123	* @arg @ref LL_RCC_RTC_HSE_DIV_7
lypinator	0:bb348c97df44	4124	* @arg @ref LL_RCC_RTC_HSE_DIV_8
lypinator	0:bb348c97df44	4125	* @arg @ref LL_RCC_RTC_HSE_DIV_9
lypinator	0:bb348c97df44	4126	* @arg @ref LL_RCC_RTC_HSE_DIV_10
lypinator	0:bb348c97df44	4127	* @arg @ref LL_RCC_RTC_HSE_DIV_11
lypinator	0:bb348c97df44	4128	* @arg @ref LL_RCC_RTC_HSE_DIV_12
lypinator	0:bb348c97df44	4129	* @arg @ref LL_RCC_RTC_HSE_DIV_13
lypinator	0:bb348c97df44	4130	* @arg @ref LL_RCC_RTC_HSE_DIV_14
lypinator	0:bb348c97df44	4131	* @arg @ref LL_RCC_RTC_HSE_DIV_15
lypinator	0:bb348c97df44	4132	* @arg @ref LL_RCC_RTC_HSE_DIV_16
lypinator	0:bb348c97df44	4133	* @arg @ref LL_RCC_RTC_HSE_DIV_17
lypinator	0:bb348c97df44	4134	* @arg @ref LL_RCC_RTC_HSE_DIV_18
lypinator	0:bb348c97df44	4135	* @arg @ref LL_RCC_RTC_HSE_DIV_19
lypinator	0:bb348c97df44	4136	* @arg @ref LL_RCC_RTC_HSE_DIV_20
lypinator	0:bb348c97df44	4137	* @arg @ref LL_RCC_RTC_HSE_DIV_21
lypinator	0:bb348c97df44	4138	* @arg @ref LL_RCC_RTC_HSE_DIV_22
lypinator	0:bb348c97df44	4139	* @arg @ref LL_RCC_RTC_HSE_DIV_23
lypinator	0:bb348c97df44	4140	* @arg @ref LL_RCC_RTC_HSE_DIV_24
lypinator	0:bb348c97df44	4141	* @arg @ref LL_RCC_RTC_HSE_DIV_25
lypinator	0:bb348c97df44	4142	* @arg @ref LL_RCC_RTC_HSE_DIV_26
lypinator	0:bb348c97df44	4143	* @arg @ref LL_RCC_RTC_HSE_DIV_27
lypinator	0:bb348c97df44	4144	* @arg @ref LL_RCC_RTC_HSE_DIV_28
lypinator	0:bb348c97df44	4145	* @arg @ref LL_RCC_RTC_HSE_DIV_29
lypinator	0:bb348c97df44	4146	* @arg @ref LL_RCC_RTC_HSE_DIV_30
lypinator	0:bb348c97df44	4147	* @arg @ref LL_RCC_RTC_HSE_DIV_31
lypinator	0:bb348c97df44	4148	*/
lypinator	0:bb348c97df44	4149	__STATIC_INLINE uint32_t LL_RCC_GetRTC_HSEPrescaler(void)
lypinator	0:bb348c97df44	4150	{
lypinator	0:bb348c97df44	4151	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_RTCPRE));
lypinator	0:bb348c97df44	4152	}
lypinator	0:bb348c97df44	4153
lypinator	0:bb348c97df44	4154	/**
lypinator	0:bb348c97df44	4155	* @}
lypinator	0:bb348c97df44	4156	*/
lypinator	0:bb348c97df44	4157
lypinator	0:bb348c97df44	4158	#if defined(RCC_DCKCFGR_TIMPRE)
lypinator	0:bb348c97df44	4159	/** @defgroup RCC_LL_EF_TIM_CLOCK_PRESCALER TIM
lypinator	0:bb348c97df44	4160	* @{
lypinator	0:bb348c97df44	4161	*/
lypinator	0:bb348c97df44	4162
lypinator	0:bb348c97df44	4163	/**
lypinator	0:bb348c97df44	4164	* @brief Set Timers Clock Prescalers
lypinator	0:bb348c97df44	4165	* @rmtoll DCKCFGR TIMPRE LL_RCC_SetTIMPrescaler
lypinator	0:bb348c97df44	4166	* @param Prescaler This parameter can be one of the following values:
lypinator	0:bb348c97df44	4167	* @arg @ref LL_RCC_TIM_PRESCALER_TWICE
lypinator	0:bb348c97df44	4168	* @arg @ref LL_RCC_TIM_PRESCALER_FOUR_TIMES
lypinator	0:bb348c97df44	4169	* @retval None
lypinator	0:bb348c97df44	4170	*/
lypinator	0:bb348c97df44	4171	__STATIC_INLINE void LL_RCC_SetTIMPrescaler(uint32_t Prescaler)
lypinator	0:bb348c97df44	4172	{
lypinator	0:bb348c97df44	4173	MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_TIMPRE, Prescaler);
lypinator	0:bb348c97df44	4174	}
lypinator	0:bb348c97df44	4175
lypinator	0:bb348c97df44	4176	/**
lypinator	0:bb348c97df44	4177	* @brief Get Timers Clock Prescalers
lypinator	0:bb348c97df44	4178	* @rmtoll DCKCFGR TIMPRE LL_RCC_GetTIMPrescaler
lypinator	0:bb348c97df44	4179	* @retval Returned value can be one of the following values:
lypinator	0:bb348c97df44	4180	* @arg @ref LL_RCC_TIM_PRESCALER_TWICE
lypinator	0:bb348c97df44	4181	* @arg @ref LL_RCC_TIM_PRESCALER_FOUR_TIMES
lypinator	0:bb348c97df44	4182	*/
lypinator	0:bb348c97df44	4183	__STATIC_INLINE uint32_t LL_RCC_GetTIMPrescaler(void)
lypinator	0:bb348c97df44	4184	{
lypinator	0:bb348c97df44	4185	return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_TIMPRE));
lypinator	0:bb348c97df44	4186	}
lypinator	0:bb348c97df44	4187
lypinator	0:bb348c97df44	4188	/**
lypinator	0:bb348c97df44	4189	* @}
lypinator	0:bb348c97df44	4190	*/
lypinator	0:bb348c97df44	4191	#endif /* RCC_DCKCFGR_TIMPRE */
lypinator	0:bb348c97df44	4192
lypinator	0:bb348c97df44	4193	/** @defgroup RCC_LL_EF_PLL PLL
lypinator	0:bb348c97df44	4194	* @{
lypinator	0:bb348c97df44	4195	*/
lypinator	0:bb348c97df44	4196
lypinator	0:bb348c97df44	4197	/**
lypinator	0:bb348c97df44	4198	* @brief Enable PLL
lypinator	0:bb348c97df44	4199	* @rmtoll CR PLLON LL_RCC_PLL_Enable
lypinator	0:bb348c97df44	4200	* @retval None
lypinator	0:bb348c97df44	4201	*/
lypinator	0:bb348c97df44	4202	__STATIC_INLINE void LL_RCC_PLL_Enable(void)
lypinator	0:bb348c97df44	4203	{
lypinator	0:bb348c97df44	4204	SET_BIT(RCC->CR, RCC_CR_PLLON);
lypinator	0:bb348c97df44	4205	}
lypinator	0:bb348c97df44	4206
lypinator	0:bb348c97df44	4207	/**
lypinator	0:bb348c97df44	4208	* @brief Disable PLL
lypinator	0:bb348c97df44	4209	* @note Cannot be disabled if the PLL clock is used as the system clock
lypinator	0:bb348c97df44	4210	* @rmtoll CR PLLON LL_RCC_PLL_Disable
lypinator	0:bb348c97df44	4211	* @retval None
lypinator	0:bb348c97df44	4212	*/
lypinator	0:bb348c97df44	4213	__STATIC_INLINE void LL_RCC_PLL_Disable(void)
lypinator	0:bb348c97df44	4214	{
lypinator	0:bb348c97df44	4215	CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
lypinator	0:bb348c97df44	4216	}
lypinator	0:bb348c97df44	4217
lypinator	0:bb348c97df44	4218	/**
lypinator	0:bb348c97df44	4219	* @brief Check if PLL Ready
lypinator	0:bb348c97df44	4220	* @rmtoll CR PLLRDY LL_RCC_PLL_IsReady
lypinator	0:bb348c97df44	4221	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	4222	*/
lypinator	0:bb348c97df44	4223	__STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void)
lypinator	0:bb348c97df44	4224	{
lypinator	0:bb348c97df44	4225	return (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY));
lypinator	0:bb348c97df44	4226	}
lypinator	0:bb348c97df44	4227
lypinator	0:bb348c97df44	4228	/**
lypinator	0:bb348c97df44	4229	* @brief Configure PLL used for SYSCLK Domain
lypinator	0:bb348c97df44	4230	* @note PLL Source and PLLM Divider can be written only when PLL,
lypinator	0:bb348c97df44	4231	* PLLI2S and PLLSAI(*) are disabled
lypinator	0:bb348c97df44	4232	* @note PLLN/PLLP can be written only when PLL is disabled
lypinator	0:bb348c97df44	4233	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n
lypinator	0:bb348c97df44	4234	* PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SYS\n
lypinator	0:bb348c97df44	4235	* PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SYS\n
lypinator	0:bb348c97df44	4236	* PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_SYS\n
lypinator	0:bb348c97df44	4237	* PLLCFGR PLLP LL_RCC_PLL_ConfigDomain_SYS
lypinator	0:bb348c97df44	4238	* @param Source This parameter can be one of the following values:
lypinator	0:bb348c97df44	4239	* @arg @ref LL_RCC_PLLSOURCE_HSI
lypinator	0:bb348c97df44	4240	* @arg @ref LL_RCC_PLLSOURCE_HSE
lypinator	0:bb348c97df44	4241	* @param PLLM This parameter can be one of the following values:
lypinator	0:bb348c97df44	4242	* @arg @ref LL_RCC_PLLM_DIV_2
lypinator	0:bb348c97df44	4243	* @arg @ref LL_RCC_PLLM_DIV_3
lypinator	0:bb348c97df44	4244	* @arg @ref LL_RCC_PLLM_DIV_4
lypinator	0:bb348c97df44	4245	* @arg @ref LL_RCC_PLLM_DIV_5
lypinator	0:bb348c97df44	4246	* @arg @ref LL_RCC_PLLM_DIV_6
lypinator	0:bb348c97df44	4247	* @arg @ref LL_RCC_PLLM_DIV_7
lypinator	0:bb348c97df44	4248	* @arg @ref LL_RCC_PLLM_DIV_8
lypinator	0:bb348c97df44	4249	* @arg @ref LL_RCC_PLLM_DIV_9
lypinator	0:bb348c97df44	4250	* @arg @ref LL_RCC_PLLM_DIV_10
lypinator	0:bb348c97df44	4251	* @arg @ref LL_RCC_PLLM_DIV_11
lypinator	0:bb348c97df44	4252	* @arg @ref LL_RCC_PLLM_DIV_12
lypinator	0:bb348c97df44	4253	* @arg @ref LL_RCC_PLLM_DIV_13
lypinator	0:bb348c97df44	4254	* @arg @ref LL_RCC_PLLM_DIV_14
lypinator	0:bb348c97df44	4255	* @arg @ref LL_RCC_PLLM_DIV_15
lypinator	0:bb348c97df44	4256	* @arg @ref LL_RCC_PLLM_DIV_16
lypinator	0:bb348c97df44	4257	* @arg @ref LL_RCC_PLLM_DIV_17
lypinator	0:bb348c97df44	4258	* @arg @ref LL_RCC_PLLM_DIV_18
lypinator	0:bb348c97df44	4259	* @arg @ref LL_RCC_PLLM_DIV_19
lypinator	0:bb348c97df44	4260	* @arg @ref LL_RCC_PLLM_DIV_20
lypinator	0:bb348c97df44	4261	* @arg @ref LL_RCC_PLLM_DIV_21
lypinator	0:bb348c97df44	4262	* @arg @ref LL_RCC_PLLM_DIV_22
lypinator	0:bb348c97df44	4263	* @arg @ref LL_RCC_PLLM_DIV_23
lypinator	0:bb348c97df44	4264	* @arg @ref LL_RCC_PLLM_DIV_24
lypinator	0:bb348c97df44	4265	* @arg @ref LL_RCC_PLLM_DIV_25
lypinator	0:bb348c97df44	4266	* @arg @ref LL_RCC_PLLM_DIV_26
lypinator	0:bb348c97df44	4267	* @arg @ref LL_RCC_PLLM_DIV_27
lypinator	0:bb348c97df44	4268	* @arg @ref LL_RCC_PLLM_DIV_28
lypinator	0:bb348c97df44	4269	* @arg @ref LL_RCC_PLLM_DIV_29
lypinator	0:bb348c97df44	4270	* @arg @ref LL_RCC_PLLM_DIV_30
lypinator	0:bb348c97df44	4271	* @arg @ref LL_RCC_PLLM_DIV_31
lypinator	0:bb348c97df44	4272	* @arg @ref LL_RCC_PLLM_DIV_32
lypinator	0:bb348c97df44	4273	* @arg @ref LL_RCC_PLLM_DIV_33
lypinator	0:bb348c97df44	4274	* @arg @ref LL_RCC_PLLM_DIV_34
lypinator	0:bb348c97df44	4275	* @arg @ref LL_RCC_PLLM_DIV_35
lypinator	0:bb348c97df44	4276	* @arg @ref LL_RCC_PLLM_DIV_36
lypinator	0:bb348c97df44	4277	* @arg @ref LL_RCC_PLLM_DIV_37
lypinator	0:bb348c97df44	4278	* @arg @ref LL_RCC_PLLM_DIV_38
lypinator	0:bb348c97df44	4279	* @arg @ref LL_RCC_PLLM_DIV_39
lypinator	0:bb348c97df44	4280	* @arg @ref LL_RCC_PLLM_DIV_40
lypinator	0:bb348c97df44	4281	* @arg @ref LL_RCC_PLLM_DIV_41
lypinator	0:bb348c97df44	4282	* @arg @ref LL_RCC_PLLM_DIV_42
lypinator	0:bb348c97df44	4283	* @arg @ref LL_RCC_PLLM_DIV_43
lypinator	0:bb348c97df44	4284	* @arg @ref LL_RCC_PLLM_DIV_44
lypinator	0:bb348c97df44	4285	* @arg @ref LL_RCC_PLLM_DIV_45
lypinator	0:bb348c97df44	4286	* @arg @ref LL_RCC_PLLM_DIV_46
lypinator	0:bb348c97df44	4287	* @arg @ref LL_RCC_PLLM_DIV_47
lypinator	0:bb348c97df44	4288	* @arg @ref LL_RCC_PLLM_DIV_48
lypinator	0:bb348c97df44	4289	* @arg @ref LL_RCC_PLLM_DIV_49
lypinator	0:bb348c97df44	4290	* @arg @ref LL_RCC_PLLM_DIV_50
lypinator	0:bb348c97df44	4291	* @arg @ref LL_RCC_PLLM_DIV_51
lypinator	0:bb348c97df44	4292	* @arg @ref LL_RCC_PLLM_DIV_52
lypinator	0:bb348c97df44	4293	* @arg @ref LL_RCC_PLLM_DIV_53
lypinator	0:bb348c97df44	4294	* @arg @ref LL_RCC_PLLM_DIV_54
lypinator	0:bb348c97df44	4295	* @arg @ref LL_RCC_PLLM_DIV_55
lypinator	0:bb348c97df44	4296	* @arg @ref LL_RCC_PLLM_DIV_56
lypinator	0:bb348c97df44	4297	* @arg @ref LL_RCC_PLLM_DIV_57
lypinator	0:bb348c97df44	4298	* @arg @ref LL_RCC_PLLM_DIV_58
lypinator	0:bb348c97df44	4299	* @arg @ref LL_RCC_PLLM_DIV_59
lypinator	0:bb348c97df44	4300	* @arg @ref LL_RCC_PLLM_DIV_60
lypinator	0:bb348c97df44	4301	* @arg @ref LL_RCC_PLLM_DIV_61
lypinator	0:bb348c97df44	4302	* @arg @ref LL_RCC_PLLM_DIV_62
lypinator	0:bb348c97df44	4303	* @arg @ref LL_RCC_PLLM_DIV_63
lypinator	0:bb348c97df44	4304	* @param PLLN Between 50/192(*) and 432
lypinator	0:bb348c97df44	4305	*
lypinator	0:bb348c97df44	4306	* (*) value not defined in all devices.
lypinator	0:bb348c97df44	4307	* @param PLLP_R This parameter can be one of the following values:
lypinator	0:bb348c97df44	4308	* @arg @ref LL_RCC_PLLP_DIV_2
lypinator	0:bb348c97df44	4309	* @arg @ref LL_RCC_PLLP_DIV_4
lypinator	0:bb348c97df44	4310	* @arg @ref LL_RCC_PLLP_DIV_6
lypinator	0:bb348c97df44	4311	* @arg @ref LL_RCC_PLLP_DIV_8
lypinator	0:bb348c97df44	4312	* @arg @ref LL_RCC_PLLR_DIV_2 (*)
lypinator	0:bb348c97df44	4313	* @arg @ref LL_RCC_PLLR_DIV_3 (*)
lypinator	0:bb348c97df44	4314	* @arg @ref LL_RCC_PLLR_DIV_4 (*)
lypinator	0:bb348c97df44	4315	* @arg @ref LL_RCC_PLLR_DIV_5 (*)
lypinator	0:bb348c97df44	4316	* @arg @ref LL_RCC_PLLR_DIV_6 (*)
lypinator	0:bb348c97df44	4317	* @arg @ref LL_RCC_PLLR_DIV_7 (*)
lypinator	0:bb348c97df44	4318	*
lypinator	0:bb348c97df44	4319	* (*) value not defined in all devices.
lypinator	0:bb348c97df44	4320	* @retval None
lypinator	0:bb348c97df44	4321	*/
lypinator	0:bb348c97df44	4322	__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP_R)
lypinator	0:bb348c97df44	4323	{
lypinator	0:bb348c97df44	4324	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC \| RCC_PLLCFGR_PLLM \| RCC_PLLCFGR_PLLN,
lypinator	0:bb348c97df44	4325	Source \| PLLM \| PLLN << RCC_PLLCFGR_PLLN_Pos);
lypinator	0:bb348c97df44	4326	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLP, PLLP_R);
lypinator	0:bb348c97df44	4327	#if defined(RCC_PLLR_SYSCLK_SUPPORT)
lypinator	0:bb348c97df44	4328	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLR, PLLP_R);
lypinator	0:bb348c97df44	4329	#endif /* RCC_PLLR_SYSCLK_SUPPORT */
lypinator	0:bb348c97df44	4330	}
lypinator	0:bb348c97df44	4331
lypinator	0:bb348c97df44	4332	/**
lypinator	0:bb348c97df44	4333	* @brief Configure PLL used for 48Mhz domain clock
lypinator	0:bb348c97df44	4334	* @note PLL Source and PLLM Divider can be written only when PLL,
lypinator	0:bb348c97df44	4335	* PLLI2S and PLLSAI(*) are disabled
lypinator	0:bb348c97df44	4336	* @note PLLN/PLLQ can be written only when PLL is disabled
lypinator	0:bb348c97df44	4337	* @note This can be selected for USB, RNG, SDIO
lypinator	0:bb348c97df44	4338	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_48M\n
lypinator	0:bb348c97df44	4339	* PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_48M\n
lypinator	0:bb348c97df44	4340	* PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_48M\n
lypinator	0:bb348c97df44	4341	* PLLCFGR PLLQ LL_RCC_PLL_ConfigDomain_48M
lypinator	0:bb348c97df44	4342	* @param Source This parameter can be one of the following values:
lypinator	0:bb348c97df44	4343	* @arg @ref LL_RCC_PLLSOURCE_HSI
lypinator	0:bb348c97df44	4344	* @arg @ref LL_RCC_PLLSOURCE_HSE
lypinator	0:bb348c97df44	4345	* @param PLLM This parameter can be one of the following values:
lypinator	0:bb348c97df44	4346	* @arg @ref LL_RCC_PLLM_DIV_2
lypinator	0:bb348c97df44	4347	* @arg @ref LL_RCC_PLLM_DIV_3
lypinator	0:bb348c97df44	4348	* @arg @ref LL_RCC_PLLM_DIV_4
lypinator	0:bb348c97df44	4349	* @arg @ref LL_RCC_PLLM_DIV_5
lypinator	0:bb348c97df44	4350	* @arg @ref LL_RCC_PLLM_DIV_6
lypinator	0:bb348c97df44	4351	* @arg @ref LL_RCC_PLLM_DIV_7
lypinator	0:bb348c97df44	4352	* @arg @ref LL_RCC_PLLM_DIV_8
lypinator	0:bb348c97df44	4353	* @arg @ref LL_RCC_PLLM_DIV_9
lypinator	0:bb348c97df44	4354	* @arg @ref LL_RCC_PLLM_DIV_10
lypinator	0:bb348c97df44	4355	* @arg @ref LL_RCC_PLLM_DIV_11
lypinator	0:bb348c97df44	4356	* @arg @ref LL_RCC_PLLM_DIV_12
lypinator	0:bb348c97df44	4357	* @arg @ref LL_RCC_PLLM_DIV_13
lypinator	0:bb348c97df44	4358	* @arg @ref LL_RCC_PLLM_DIV_14
lypinator	0:bb348c97df44	4359	* @arg @ref LL_RCC_PLLM_DIV_15
lypinator	0:bb348c97df44	4360	* @arg @ref LL_RCC_PLLM_DIV_16
lypinator	0:bb348c97df44	4361	* @arg @ref LL_RCC_PLLM_DIV_17
lypinator	0:bb348c97df44	4362	* @arg @ref LL_RCC_PLLM_DIV_18
lypinator	0:bb348c97df44	4363	* @arg @ref LL_RCC_PLLM_DIV_19
lypinator	0:bb348c97df44	4364	* @arg @ref LL_RCC_PLLM_DIV_20
lypinator	0:bb348c97df44	4365	* @arg @ref LL_RCC_PLLM_DIV_21
lypinator	0:bb348c97df44	4366	* @arg @ref LL_RCC_PLLM_DIV_22
lypinator	0:bb348c97df44	4367	* @arg @ref LL_RCC_PLLM_DIV_23
lypinator	0:bb348c97df44	4368	* @arg @ref LL_RCC_PLLM_DIV_24
lypinator	0:bb348c97df44	4369	* @arg @ref LL_RCC_PLLM_DIV_25
lypinator	0:bb348c97df44	4370	* @arg @ref LL_RCC_PLLM_DIV_26
lypinator	0:bb348c97df44	4371	* @arg @ref LL_RCC_PLLM_DIV_27
lypinator	0:bb348c97df44	4372	* @arg @ref LL_RCC_PLLM_DIV_28
lypinator	0:bb348c97df44	4373	* @arg @ref LL_RCC_PLLM_DIV_29
lypinator	0:bb348c97df44	4374	* @arg @ref LL_RCC_PLLM_DIV_30
lypinator	0:bb348c97df44	4375	* @arg @ref LL_RCC_PLLM_DIV_31
lypinator	0:bb348c97df44	4376	* @arg @ref LL_RCC_PLLM_DIV_32
lypinator	0:bb348c97df44	4377	* @arg @ref LL_RCC_PLLM_DIV_33
lypinator	0:bb348c97df44	4378	* @arg @ref LL_RCC_PLLM_DIV_34
lypinator	0:bb348c97df44	4379	* @arg @ref LL_RCC_PLLM_DIV_35
lypinator	0:bb348c97df44	4380	* @arg @ref LL_RCC_PLLM_DIV_36
lypinator	0:bb348c97df44	4381	* @arg @ref LL_RCC_PLLM_DIV_37
lypinator	0:bb348c97df44	4382	* @arg @ref LL_RCC_PLLM_DIV_38
lypinator	0:bb348c97df44	4383	* @arg @ref LL_RCC_PLLM_DIV_39
lypinator	0:bb348c97df44	4384	* @arg @ref LL_RCC_PLLM_DIV_40
lypinator	0:bb348c97df44	4385	* @arg @ref LL_RCC_PLLM_DIV_41
lypinator	0:bb348c97df44	4386	* @arg @ref LL_RCC_PLLM_DIV_42
lypinator	0:bb348c97df44	4387	* @arg @ref LL_RCC_PLLM_DIV_43
lypinator	0:bb348c97df44	4388	* @arg @ref LL_RCC_PLLM_DIV_44
lypinator	0:bb348c97df44	4389	* @arg @ref LL_RCC_PLLM_DIV_45
lypinator	0:bb348c97df44	4390	* @arg @ref LL_RCC_PLLM_DIV_46
lypinator	0:bb348c97df44	4391	* @arg @ref LL_RCC_PLLM_DIV_47
lypinator	0:bb348c97df44	4392	* @arg @ref LL_RCC_PLLM_DIV_48
lypinator	0:bb348c97df44	4393	* @arg @ref LL_RCC_PLLM_DIV_49
lypinator	0:bb348c97df44	4394	* @arg @ref LL_RCC_PLLM_DIV_50
lypinator	0:bb348c97df44	4395	* @arg @ref LL_RCC_PLLM_DIV_51
lypinator	0:bb348c97df44	4396	* @arg @ref LL_RCC_PLLM_DIV_52
lypinator	0:bb348c97df44	4397	* @arg @ref LL_RCC_PLLM_DIV_53
lypinator	0:bb348c97df44	4398	* @arg @ref LL_RCC_PLLM_DIV_54
lypinator	0:bb348c97df44	4399	* @arg @ref LL_RCC_PLLM_DIV_55
lypinator	0:bb348c97df44	4400	* @arg @ref LL_RCC_PLLM_DIV_56
lypinator	0:bb348c97df44	4401	* @arg @ref LL_RCC_PLLM_DIV_57
lypinator	0:bb348c97df44	4402	* @arg @ref LL_RCC_PLLM_DIV_58
lypinator	0:bb348c97df44	4403	* @arg @ref LL_RCC_PLLM_DIV_59
lypinator	0:bb348c97df44	4404	* @arg @ref LL_RCC_PLLM_DIV_60
lypinator	0:bb348c97df44	4405	* @arg @ref LL_RCC_PLLM_DIV_61
lypinator	0:bb348c97df44	4406	* @arg @ref LL_RCC_PLLM_DIV_62
lypinator	0:bb348c97df44	4407	* @arg @ref LL_RCC_PLLM_DIV_63
lypinator	0:bb348c97df44	4408	* @param PLLN Between 50/192(*) and 432
lypinator	0:bb348c97df44	4409	*
lypinator	0:bb348c97df44	4410	* (*) value not defined in all devices.
lypinator	0:bb348c97df44	4411	* @param PLLQ This parameter can be one of the following values:
lypinator	0:bb348c97df44	4412	* @arg @ref LL_RCC_PLLQ_DIV_2
lypinator	0:bb348c97df44	4413	* @arg @ref LL_RCC_PLLQ_DIV_3
lypinator	0:bb348c97df44	4414	* @arg @ref LL_RCC_PLLQ_DIV_4
lypinator	0:bb348c97df44	4415	* @arg @ref LL_RCC_PLLQ_DIV_5
lypinator	0:bb348c97df44	4416	* @arg @ref LL_RCC_PLLQ_DIV_6
lypinator	0:bb348c97df44	4417	* @arg @ref LL_RCC_PLLQ_DIV_7
lypinator	0:bb348c97df44	4418	* @arg @ref LL_RCC_PLLQ_DIV_8
lypinator	0:bb348c97df44	4419	* @arg @ref LL_RCC_PLLQ_DIV_9
lypinator	0:bb348c97df44	4420	* @arg @ref LL_RCC_PLLQ_DIV_10
lypinator	0:bb348c97df44	4421	* @arg @ref LL_RCC_PLLQ_DIV_11
lypinator	0:bb348c97df44	4422	* @arg @ref LL_RCC_PLLQ_DIV_12
lypinator	0:bb348c97df44	4423	* @arg @ref LL_RCC_PLLQ_DIV_13
lypinator	0:bb348c97df44	4424	* @arg @ref LL_RCC_PLLQ_DIV_14
lypinator	0:bb348c97df44	4425	* @arg @ref LL_RCC_PLLQ_DIV_15
lypinator	0:bb348c97df44	4426	* @retval None
lypinator	0:bb348c97df44	4427	*/
lypinator	0:bb348c97df44	4428	__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
lypinator	0:bb348c97df44	4429	{
lypinator	0:bb348c97df44	4430	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC \| RCC_PLLCFGR_PLLM \| RCC_PLLCFGR_PLLN \| RCC_PLLCFGR_PLLQ,
lypinator	0:bb348c97df44	4431	Source \| PLLM \| PLLN << RCC_PLLCFGR_PLLN_Pos \| PLLQ);
lypinator	0:bb348c97df44	4432	}
lypinator	0:bb348c97df44	4433
lypinator	0:bb348c97df44	4434	#if defined(DSI)
lypinator	0:bb348c97df44	4435	/**
lypinator	0:bb348c97df44	4436	* @brief Configure PLL used for DSI clock
lypinator	0:bb348c97df44	4437	* @note PLL Source and PLLM Divider can be written only when PLL,
lypinator	0:bb348c97df44	4438	* PLLI2S and PLLSAI are disabled
lypinator	0:bb348c97df44	4439	* @note PLLN/PLLR can be written only when PLL is disabled
lypinator	0:bb348c97df44	4440	* @note This can be selected for DSI
lypinator	0:bb348c97df44	4441	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_DSI\n
lypinator	0:bb348c97df44	4442	* PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_DSI\n
lypinator	0:bb348c97df44	4443	* PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_DSI\n
lypinator	0:bb348c97df44	4444	* PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_DSI
lypinator	0:bb348c97df44	4445	* @param Source This parameter can be one of the following values:
lypinator	0:bb348c97df44	4446	* @arg @ref LL_RCC_PLLSOURCE_HSI
lypinator	0:bb348c97df44	4447	* @arg @ref LL_RCC_PLLSOURCE_HSE
lypinator	0:bb348c97df44	4448	* @param PLLM This parameter can be one of the following values:
lypinator	0:bb348c97df44	4449	* @arg @ref LL_RCC_PLLM_DIV_2
lypinator	0:bb348c97df44	4450	* @arg @ref LL_RCC_PLLM_DIV_3
lypinator	0:bb348c97df44	4451	* @arg @ref LL_RCC_PLLM_DIV_4
lypinator	0:bb348c97df44	4452	* @arg @ref LL_RCC_PLLM_DIV_5
lypinator	0:bb348c97df44	4453	* @arg @ref LL_RCC_PLLM_DIV_6
lypinator	0:bb348c97df44	4454	* @arg @ref LL_RCC_PLLM_DIV_7
lypinator	0:bb348c97df44	4455	* @arg @ref LL_RCC_PLLM_DIV_8
lypinator	0:bb348c97df44	4456	* @arg @ref LL_RCC_PLLM_DIV_9
lypinator	0:bb348c97df44	4457	* @arg @ref LL_RCC_PLLM_DIV_10
lypinator	0:bb348c97df44	4458	* @arg @ref LL_RCC_PLLM_DIV_11
lypinator	0:bb348c97df44	4459	* @arg @ref LL_RCC_PLLM_DIV_12
lypinator	0:bb348c97df44	4460	* @arg @ref LL_RCC_PLLM_DIV_13
lypinator	0:bb348c97df44	4461	* @arg @ref LL_RCC_PLLM_DIV_14
lypinator	0:bb348c97df44	4462	* @arg @ref LL_RCC_PLLM_DIV_15
lypinator	0:bb348c97df44	4463	* @arg @ref LL_RCC_PLLM_DIV_16
lypinator	0:bb348c97df44	4464	* @arg @ref LL_RCC_PLLM_DIV_17
lypinator	0:bb348c97df44	4465	* @arg @ref LL_RCC_PLLM_DIV_18
lypinator	0:bb348c97df44	4466	* @arg @ref LL_RCC_PLLM_DIV_19
lypinator	0:bb348c97df44	4467	* @arg @ref LL_RCC_PLLM_DIV_20
lypinator	0:bb348c97df44	4468	* @arg @ref LL_RCC_PLLM_DIV_21
lypinator	0:bb348c97df44	4469	* @arg @ref LL_RCC_PLLM_DIV_22
lypinator	0:bb348c97df44	4470	* @arg @ref LL_RCC_PLLM_DIV_23
lypinator	0:bb348c97df44	4471	* @arg @ref LL_RCC_PLLM_DIV_24
lypinator	0:bb348c97df44	4472	* @arg @ref LL_RCC_PLLM_DIV_25
lypinator	0:bb348c97df44	4473	* @arg @ref LL_RCC_PLLM_DIV_26
lypinator	0:bb348c97df44	4474	* @arg @ref LL_RCC_PLLM_DIV_27
lypinator	0:bb348c97df44	4475	* @arg @ref LL_RCC_PLLM_DIV_28
lypinator	0:bb348c97df44	4476	* @arg @ref LL_RCC_PLLM_DIV_29
lypinator	0:bb348c97df44	4477	* @arg @ref LL_RCC_PLLM_DIV_30
lypinator	0:bb348c97df44	4478	* @arg @ref LL_RCC_PLLM_DIV_31
lypinator	0:bb348c97df44	4479	* @arg @ref LL_RCC_PLLM_DIV_32
lypinator	0:bb348c97df44	4480	* @arg @ref LL_RCC_PLLM_DIV_33
lypinator	0:bb348c97df44	4481	* @arg @ref LL_RCC_PLLM_DIV_34
lypinator	0:bb348c97df44	4482	* @arg @ref LL_RCC_PLLM_DIV_35
lypinator	0:bb348c97df44	4483	* @arg @ref LL_RCC_PLLM_DIV_36
lypinator	0:bb348c97df44	4484	* @arg @ref LL_RCC_PLLM_DIV_37
lypinator	0:bb348c97df44	4485	* @arg @ref LL_RCC_PLLM_DIV_38
lypinator	0:bb348c97df44	4486	* @arg @ref LL_RCC_PLLM_DIV_39
lypinator	0:bb348c97df44	4487	* @arg @ref LL_RCC_PLLM_DIV_40
lypinator	0:bb348c97df44	4488	* @arg @ref LL_RCC_PLLM_DIV_41
lypinator	0:bb348c97df44	4489	* @arg @ref LL_RCC_PLLM_DIV_42
lypinator	0:bb348c97df44	4490	* @arg @ref LL_RCC_PLLM_DIV_43
lypinator	0:bb348c97df44	4491	* @arg @ref LL_RCC_PLLM_DIV_44
lypinator	0:bb348c97df44	4492	* @arg @ref LL_RCC_PLLM_DIV_45
lypinator	0:bb348c97df44	4493	* @arg @ref LL_RCC_PLLM_DIV_46
lypinator	0:bb348c97df44	4494	* @arg @ref LL_RCC_PLLM_DIV_47
lypinator	0:bb348c97df44	4495	* @arg @ref LL_RCC_PLLM_DIV_48
lypinator	0:bb348c97df44	4496	* @arg @ref LL_RCC_PLLM_DIV_49
lypinator	0:bb348c97df44	4497	* @arg @ref LL_RCC_PLLM_DIV_50
lypinator	0:bb348c97df44	4498	* @arg @ref LL_RCC_PLLM_DIV_51
lypinator	0:bb348c97df44	4499	* @arg @ref LL_RCC_PLLM_DIV_52
lypinator	0:bb348c97df44	4500	* @arg @ref LL_RCC_PLLM_DIV_53
lypinator	0:bb348c97df44	4501	* @arg @ref LL_RCC_PLLM_DIV_54
lypinator	0:bb348c97df44	4502	* @arg @ref LL_RCC_PLLM_DIV_55
lypinator	0:bb348c97df44	4503	* @arg @ref LL_RCC_PLLM_DIV_56
lypinator	0:bb348c97df44	4504	* @arg @ref LL_RCC_PLLM_DIV_57
lypinator	0:bb348c97df44	4505	* @arg @ref LL_RCC_PLLM_DIV_58
lypinator	0:bb348c97df44	4506	* @arg @ref LL_RCC_PLLM_DIV_59
lypinator	0:bb348c97df44	4507	* @arg @ref LL_RCC_PLLM_DIV_60
lypinator	0:bb348c97df44	4508	* @arg @ref LL_RCC_PLLM_DIV_61
lypinator	0:bb348c97df44	4509	* @arg @ref LL_RCC_PLLM_DIV_62
lypinator	0:bb348c97df44	4510	* @arg @ref LL_RCC_PLLM_DIV_63
lypinator	0:bb348c97df44	4511	* @param PLLN Between 50 and 432
lypinator	0:bb348c97df44	4512	* @param PLLR This parameter can be one of the following values:
lypinator	0:bb348c97df44	4513	* @arg @ref LL_RCC_PLLR_DIV_2
lypinator	0:bb348c97df44	4514	* @arg @ref LL_RCC_PLLR_DIV_3
lypinator	0:bb348c97df44	4515	* @arg @ref LL_RCC_PLLR_DIV_4
lypinator	0:bb348c97df44	4516	* @arg @ref LL_RCC_PLLR_DIV_5
lypinator	0:bb348c97df44	4517	* @arg @ref LL_RCC_PLLR_DIV_6
lypinator	0:bb348c97df44	4518	* @arg @ref LL_RCC_PLLR_DIV_7
lypinator	0:bb348c97df44	4519	* @retval None
lypinator	0:bb348c97df44	4520	*/
lypinator	0:bb348c97df44	4521	__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_DSI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
lypinator	0:bb348c97df44	4522	{
lypinator	0:bb348c97df44	4523	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC \| RCC_PLLCFGR_PLLM \| RCC_PLLCFGR_PLLN \| RCC_PLLCFGR_PLLR,
lypinator	0:bb348c97df44	4524	Source \| PLLM \| PLLN << RCC_PLLCFGR_PLLN_Pos \| PLLR);
lypinator	0:bb348c97df44	4525	}
lypinator	0:bb348c97df44	4526	#endif /* DSI */
lypinator	0:bb348c97df44	4527
lypinator	0:bb348c97df44	4528	#if defined(RCC_PLLR_I2S_CLKSOURCE_SUPPORT)
lypinator	0:bb348c97df44	4529	/**
lypinator	0:bb348c97df44	4530	* @brief Configure PLL used for I2S clock
lypinator	0:bb348c97df44	4531	* @note PLL Source and PLLM Divider can be written only when PLL,
lypinator	0:bb348c97df44	4532	* PLLI2S and PLLSAI are disabled
lypinator	0:bb348c97df44	4533	* @note PLLN/PLLR can be written only when PLL is disabled
lypinator	0:bb348c97df44	4534	* @note This can be selected for I2S
lypinator	0:bb348c97df44	4535	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_I2S\n
lypinator	0:bb348c97df44	4536	* PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_I2S\n
lypinator	0:bb348c97df44	4537	* PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_I2S\n
lypinator	0:bb348c97df44	4538	* PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_I2S
lypinator	0:bb348c97df44	4539	* @param Source This parameter can be one of the following values:
lypinator	0:bb348c97df44	4540	* @arg @ref LL_RCC_PLLSOURCE_HSI
lypinator	0:bb348c97df44	4541	* @arg @ref LL_RCC_PLLSOURCE_HSE
lypinator	0:bb348c97df44	4542	* @param PLLM This parameter can be one of the following values:
lypinator	0:bb348c97df44	4543	* @arg @ref LL_RCC_PLLM_DIV_2
lypinator	0:bb348c97df44	4544	* @arg @ref LL_RCC_PLLM_DIV_3
lypinator	0:bb348c97df44	4545	* @arg @ref LL_RCC_PLLM_DIV_4
lypinator	0:bb348c97df44	4546	* @arg @ref LL_RCC_PLLM_DIV_5
lypinator	0:bb348c97df44	4547	* @arg @ref LL_RCC_PLLM_DIV_6
lypinator	0:bb348c97df44	4548	* @arg @ref LL_RCC_PLLM_DIV_7
lypinator	0:bb348c97df44	4549	* @arg @ref LL_RCC_PLLM_DIV_8
lypinator	0:bb348c97df44	4550	* @arg @ref LL_RCC_PLLM_DIV_9
lypinator	0:bb348c97df44	4551	* @arg @ref LL_RCC_PLLM_DIV_10
lypinator	0:bb348c97df44	4552	* @arg @ref LL_RCC_PLLM_DIV_11
lypinator	0:bb348c97df44	4553	* @arg @ref LL_RCC_PLLM_DIV_12
lypinator	0:bb348c97df44	4554	* @arg @ref LL_RCC_PLLM_DIV_13
lypinator	0:bb348c97df44	4555	* @arg @ref LL_RCC_PLLM_DIV_14
lypinator	0:bb348c97df44	4556	* @arg @ref LL_RCC_PLLM_DIV_15
lypinator	0:bb348c97df44	4557	* @arg @ref LL_RCC_PLLM_DIV_16
lypinator	0:bb348c97df44	4558	* @arg @ref LL_RCC_PLLM_DIV_17
lypinator	0:bb348c97df44	4559	* @arg @ref LL_RCC_PLLM_DIV_18
lypinator	0:bb348c97df44	4560	* @arg @ref LL_RCC_PLLM_DIV_19
lypinator	0:bb348c97df44	4561	* @arg @ref LL_RCC_PLLM_DIV_20
lypinator	0:bb348c97df44	4562	* @arg @ref LL_RCC_PLLM_DIV_21
lypinator	0:bb348c97df44	4563	* @arg @ref LL_RCC_PLLM_DIV_22
lypinator	0:bb348c97df44	4564	* @arg @ref LL_RCC_PLLM_DIV_23
lypinator	0:bb348c97df44	4565	* @arg @ref LL_RCC_PLLM_DIV_24
lypinator	0:bb348c97df44	4566	* @arg @ref LL_RCC_PLLM_DIV_25
lypinator	0:bb348c97df44	4567	* @arg @ref LL_RCC_PLLM_DIV_26
lypinator	0:bb348c97df44	4568	* @arg @ref LL_RCC_PLLM_DIV_27
lypinator	0:bb348c97df44	4569	* @arg @ref LL_RCC_PLLM_DIV_28
lypinator	0:bb348c97df44	4570	* @arg @ref LL_RCC_PLLM_DIV_29
lypinator	0:bb348c97df44	4571	* @arg @ref LL_RCC_PLLM_DIV_30
lypinator	0:bb348c97df44	4572	* @arg @ref LL_RCC_PLLM_DIV_31
lypinator	0:bb348c97df44	4573	* @arg @ref LL_RCC_PLLM_DIV_32
lypinator	0:bb348c97df44	4574	* @arg @ref LL_RCC_PLLM_DIV_33
lypinator	0:bb348c97df44	4575	* @arg @ref LL_RCC_PLLM_DIV_34
lypinator	0:bb348c97df44	4576	* @arg @ref LL_RCC_PLLM_DIV_35
lypinator	0:bb348c97df44	4577	* @arg @ref LL_RCC_PLLM_DIV_36
lypinator	0:bb348c97df44	4578	* @arg @ref LL_RCC_PLLM_DIV_37
lypinator	0:bb348c97df44	4579	* @arg @ref LL_RCC_PLLM_DIV_38
lypinator	0:bb348c97df44	4580	* @arg @ref LL_RCC_PLLM_DIV_39
lypinator	0:bb348c97df44	4581	* @arg @ref LL_RCC_PLLM_DIV_40
lypinator	0:bb348c97df44	4582	* @arg @ref LL_RCC_PLLM_DIV_41
lypinator	0:bb348c97df44	4583	* @arg @ref LL_RCC_PLLM_DIV_42
lypinator	0:bb348c97df44	4584	* @arg @ref LL_RCC_PLLM_DIV_43
lypinator	0:bb348c97df44	4585	* @arg @ref LL_RCC_PLLM_DIV_44
lypinator	0:bb348c97df44	4586	* @arg @ref LL_RCC_PLLM_DIV_45
lypinator	0:bb348c97df44	4587	* @arg @ref LL_RCC_PLLM_DIV_46
lypinator	0:bb348c97df44	4588	* @arg @ref LL_RCC_PLLM_DIV_47
lypinator	0:bb348c97df44	4589	* @arg @ref LL_RCC_PLLM_DIV_48
lypinator	0:bb348c97df44	4590	* @arg @ref LL_RCC_PLLM_DIV_49
lypinator	0:bb348c97df44	4591	* @arg @ref LL_RCC_PLLM_DIV_50
lypinator	0:bb348c97df44	4592	* @arg @ref LL_RCC_PLLM_DIV_51
lypinator	0:bb348c97df44	4593	* @arg @ref LL_RCC_PLLM_DIV_52
lypinator	0:bb348c97df44	4594	* @arg @ref LL_RCC_PLLM_DIV_53
lypinator	0:bb348c97df44	4595	* @arg @ref LL_RCC_PLLM_DIV_54
lypinator	0:bb348c97df44	4596	* @arg @ref LL_RCC_PLLM_DIV_55
lypinator	0:bb348c97df44	4597	* @arg @ref LL_RCC_PLLM_DIV_56
lypinator	0:bb348c97df44	4598	* @arg @ref LL_RCC_PLLM_DIV_57
lypinator	0:bb348c97df44	4599	* @arg @ref LL_RCC_PLLM_DIV_58
lypinator	0:bb348c97df44	4600	* @arg @ref LL_RCC_PLLM_DIV_59
lypinator	0:bb348c97df44	4601	* @arg @ref LL_RCC_PLLM_DIV_60
lypinator	0:bb348c97df44	4602	* @arg @ref LL_RCC_PLLM_DIV_61
lypinator	0:bb348c97df44	4603	* @arg @ref LL_RCC_PLLM_DIV_62
lypinator	0:bb348c97df44	4604	* @arg @ref LL_RCC_PLLM_DIV_63
lypinator	0:bb348c97df44	4605	* @param PLLN Between 50 and 432
lypinator	0:bb348c97df44	4606	* @param PLLR This parameter can be one of the following values:
lypinator	0:bb348c97df44	4607	* @arg @ref LL_RCC_PLLR_DIV_2
lypinator	0:bb348c97df44	4608	* @arg @ref LL_RCC_PLLR_DIV_3
lypinator	0:bb348c97df44	4609	* @arg @ref LL_RCC_PLLR_DIV_4
lypinator	0:bb348c97df44	4610	* @arg @ref LL_RCC_PLLR_DIV_5
lypinator	0:bb348c97df44	4611	* @arg @ref LL_RCC_PLLR_DIV_6
lypinator	0:bb348c97df44	4612	* @arg @ref LL_RCC_PLLR_DIV_7
lypinator	0:bb348c97df44	4613	* @retval None
lypinator	0:bb348c97df44	4614	*/
lypinator	0:bb348c97df44	4615	__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_I2S(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
lypinator	0:bb348c97df44	4616	{
lypinator	0:bb348c97df44	4617	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC \| RCC_PLLCFGR_PLLM \| RCC_PLLCFGR_PLLN \| RCC_PLLCFGR_PLLR,
lypinator	0:bb348c97df44	4618	Source \| PLLM \| PLLN << RCC_PLLCFGR_PLLN_Pos \| PLLR);
lypinator	0:bb348c97df44	4619	}
lypinator	0:bb348c97df44	4620	#endif /* RCC_PLLR_I2S_CLKSOURCE_SUPPORT */
lypinator	0:bb348c97df44	4621
lypinator	0:bb348c97df44	4622	#if defined(SPDIFRX)
lypinator	0:bb348c97df44	4623	/**
lypinator	0:bb348c97df44	4624	* @brief Configure PLL used for SPDIFRX clock
lypinator	0:bb348c97df44	4625	* @note PLL Source and PLLM Divider can be written only when PLL,
lypinator	0:bb348c97df44	4626	* PLLI2S and PLLSAI are disabled
lypinator	0:bb348c97df44	4627	* @note PLLN/PLLR can be written only when PLL is disabled
lypinator	0:bb348c97df44	4628	* @note This can be selected for SPDIFRX
lypinator	0:bb348c97df44	4629	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SPDIFRX\n
lypinator	0:bb348c97df44	4630	* PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SPDIFRX\n
lypinator	0:bb348c97df44	4631	* PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SPDIFRX\n
lypinator	0:bb348c97df44	4632	* PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_SPDIFRX
lypinator	0:bb348c97df44	4633	* @param Source This parameter can be one of the following values:
lypinator	0:bb348c97df44	4634	* @arg @ref LL_RCC_PLLSOURCE_HSI
lypinator	0:bb348c97df44	4635	* @arg @ref LL_RCC_PLLSOURCE_HSE
lypinator	0:bb348c97df44	4636	* @param PLLM This parameter can be one of the following values:
lypinator	0:bb348c97df44	4637	* @arg @ref LL_RCC_PLLM_DIV_2
lypinator	0:bb348c97df44	4638	* @arg @ref LL_RCC_PLLM_DIV_3
lypinator	0:bb348c97df44	4639	* @arg @ref LL_RCC_PLLM_DIV_4
lypinator	0:bb348c97df44	4640	* @arg @ref LL_RCC_PLLM_DIV_5
lypinator	0:bb348c97df44	4641	* @arg @ref LL_RCC_PLLM_DIV_6
lypinator	0:bb348c97df44	4642	* @arg @ref LL_RCC_PLLM_DIV_7
lypinator	0:bb348c97df44	4643	* @arg @ref LL_RCC_PLLM_DIV_8
lypinator	0:bb348c97df44	4644	* @arg @ref LL_RCC_PLLM_DIV_9
lypinator	0:bb348c97df44	4645	* @arg @ref LL_RCC_PLLM_DIV_10
lypinator	0:bb348c97df44	4646	* @arg @ref LL_RCC_PLLM_DIV_11
lypinator	0:bb348c97df44	4647	* @arg @ref LL_RCC_PLLM_DIV_12
lypinator	0:bb348c97df44	4648	* @arg @ref LL_RCC_PLLM_DIV_13
lypinator	0:bb348c97df44	4649	* @arg @ref LL_RCC_PLLM_DIV_14
lypinator	0:bb348c97df44	4650	* @arg @ref LL_RCC_PLLM_DIV_15
lypinator	0:bb348c97df44	4651	* @arg @ref LL_RCC_PLLM_DIV_16
lypinator	0:bb348c97df44	4652	* @arg @ref LL_RCC_PLLM_DIV_17
lypinator	0:bb348c97df44	4653	* @arg @ref LL_RCC_PLLM_DIV_18
lypinator	0:bb348c97df44	4654	* @arg @ref LL_RCC_PLLM_DIV_19
lypinator	0:bb348c97df44	4655	* @arg @ref LL_RCC_PLLM_DIV_20
lypinator	0:bb348c97df44	4656	* @arg @ref LL_RCC_PLLM_DIV_21
lypinator	0:bb348c97df44	4657	* @arg @ref LL_RCC_PLLM_DIV_22
lypinator	0:bb348c97df44	4658	* @arg @ref LL_RCC_PLLM_DIV_23
lypinator	0:bb348c97df44	4659	* @arg @ref LL_RCC_PLLM_DIV_24
lypinator	0:bb348c97df44	4660	* @arg @ref LL_RCC_PLLM_DIV_25
lypinator	0:bb348c97df44	4661	* @arg @ref LL_RCC_PLLM_DIV_26
lypinator	0:bb348c97df44	4662	* @arg @ref LL_RCC_PLLM_DIV_27
lypinator	0:bb348c97df44	4663	* @arg @ref LL_RCC_PLLM_DIV_28
lypinator	0:bb348c97df44	4664	* @arg @ref LL_RCC_PLLM_DIV_29
lypinator	0:bb348c97df44	4665	* @arg @ref LL_RCC_PLLM_DIV_30
lypinator	0:bb348c97df44	4666	* @arg @ref LL_RCC_PLLM_DIV_31
lypinator	0:bb348c97df44	4667	* @arg @ref LL_RCC_PLLM_DIV_32
lypinator	0:bb348c97df44	4668	* @arg @ref LL_RCC_PLLM_DIV_33
lypinator	0:bb348c97df44	4669	* @arg @ref LL_RCC_PLLM_DIV_34
lypinator	0:bb348c97df44	4670	* @arg @ref LL_RCC_PLLM_DIV_35
lypinator	0:bb348c97df44	4671	* @arg @ref LL_RCC_PLLM_DIV_36
lypinator	0:bb348c97df44	4672	* @arg @ref LL_RCC_PLLM_DIV_37
lypinator	0:bb348c97df44	4673	* @arg @ref LL_RCC_PLLM_DIV_38
lypinator	0:bb348c97df44	4674	* @arg @ref LL_RCC_PLLM_DIV_39
lypinator	0:bb348c97df44	4675	* @arg @ref LL_RCC_PLLM_DIV_40
lypinator	0:bb348c97df44	4676	* @arg @ref LL_RCC_PLLM_DIV_41
lypinator	0:bb348c97df44	4677	* @arg @ref LL_RCC_PLLM_DIV_42
lypinator	0:bb348c97df44	4678	* @arg @ref LL_RCC_PLLM_DIV_43
lypinator	0:bb348c97df44	4679	* @arg @ref LL_RCC_PLLM_DIV_44
lypinator	0:bb348c97df44	4680	* @arg @ref LL_RCC_PLLM_DIV_45
lypinator	0:bb348c97df44	4681	* @arg @ref LL_RCC_PLLM_DIV_46
lypinator	0:bb348c97df44	4682	* @arg @ref LL_RCC_PLLM_DIV_47
lypinator	0:bb348c97df44	4683	* @arg @ref LL_RCC_PLLM_DIV_48
lypinator	0:bb348c97df44	4684	* @arg @ref LL_RCC_PLLM_DIV_49
lypinator	0:bb348c97df44	4685	* @arg @ref LL_RCC_PLLM_DIV_50
lypinator	0:bb348c97df44	4686	* @arg @ref LL_RCC_PLLM_DIV_51
lypinator	0:bb348c97df44	4687	* @arg @ref LL_RCC_PLLM_DIV_52
lypinator	0:bb348c97df44	4688	* @arg @ref LL_RCC_PLLM_DIV_53
lypinator	0:bb348c97df44	4689	* @arg @ref LL_RCC_PLLM_DIV_54
lypinator	0:bb348c97df44	4690	* @arg @ref LL_RCC_PLLM_DIV_55
lypinator	0:bb348c97df44	4691	* @arg @ref LL_RCC_PLLM_DIV_56
lypinator	0:bb348c97df44	4692	* @arg @ref LL_RCC_PLLM_DIV_57
lypinator	0:bb348c97df44	4693	* @arg @ref LL_RCC_PLLM_DIV_58
lypinator	0:bb348c97df44	4694	* @arg @ref LL_RCC_PLLM_DIV_59
lypinator	0:bb348c97df44	4695	* @arg @ref LL_RCC_PLLM_DIV_60
lypinator	0:bb348c97df44	4696	* @arg @ref LL_RCC_PLLM_DIV_61
lypinator	0:bb348c97df44	4697	* @arg @ref LL_RCC_PLLM_DIV_62
lypinator	0:bb348c97df44	4698	* @arg @ref LL_RCC_PLLM_DIV_63
lypinator	0:bb348c97df44	4699	* @param PLLN Between 50 and 432
lypinator	0:bb348c97df44	4700	* @param PLLR This parameter can be one of the following values:
lypinator	0:bb348c97df44	4701	* @arg @ref LL_RCC_PLLR_DIV_2
lypinator	0:bb348c97df44	4702	* @arg @ref LL_RCC_PLLR_DIV_3
lypinator	0:bb348c97df44	4703	* @arg @ref LL_RCC_PLLR_DIV_4
lypinator	0:bb348c97df44	4704	* @arg @ref LL_RCC_PLLR_DIV_5
lypinator	0:bb348c97df44	4705	* @arg @ref LL_RCC_PLLR_DIV_6
lypinator	0:bb348c97df44	4706	* @arg @ref LL_RCC_PLLR_DIV_7
lypinator	0:bb348c97df44	4707	* @retval None
lypinator	0:bb348c97df44	4708	*/
lypinator	0:bb348c97df44	4709	__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SPDIFRX(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
lypinator	0:bb348c97df44	4710	{
lypinator	0:bb348c97df44	4711	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC \| RCC_PLLCFGR_PLLM \| RCC_PLLCFGR_PLLN \| RCC_PLLCFGR_PLLR,
lypinator	0:bb348c97df44	4712	Source \| PLLM \| PLLN << RCC_PLLCFGR_PLLN_Pos \| PLLR);
lypinator	0:bb348c97df44	4713	}
lypinator	0:bb348c97df44	4714	#endif /* SPDIFRX */
lypinator	0:bb348c97df44	4715
lypinator	0:bb348c97df44	4716	#if defined(RCC_PLLCFGR_PLLR)
lypinator	0:bb348c97df44	4717	#if defined(SAI1)
lypinator	0:bb348c97df44	4718	/**
lypinator	0:bb348c97df44	4719	* @brief Configure PLL used for SAI clock
lypinator	0:bb348c97df44	4720	* @note PLL Source and PLLM Divider can be written only when PLL,
lypinator	0:bb348c97df44	4721	* PLLI2S and PLLSAI are disabled
lypinator	0:bb348c97df44	4722	* @note PLLN/PLLR can be written only when PLL is disabled
lypinator	0:bb348c97df44	4723	* @note This can be selected for SAI
lypinator	0:bb348c97df44	4724	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SAI\n
lypinator	0:bb348c97df44	4725	* PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SAI\n
lypinator	0:bb348c97df44	4726	* PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SAI\n
lypinator	0:bb348c97df44	4727	* PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_SAI\n
lypinator	0:bb348c97df44	4728	* DCKCFGR PLLDIVR LL_RCC_PLL_ConfigDomain_SAI
lypinator	0:bb348c97df44	4729	* @param Source This parameter can be one of the following values:
lypinator	0:bb348c97df44	4730	* @arg @ref LL_RCC_PLLSOURCE_HSI
lypinator	0:bb348c97df44	4731	* @arg @ref LL_RCC_PLLSOURCE_HSE
lypinator	0:bb348c97df44	4732	* @param PLLM This parameter can be one of the following values:
lypinator	0:bb348c97df44	4733	* @arg @ref LL_RCC_PLLM_DIV_2
lypinator	0:bb348c97df44	4734	* @arg @ref LL_RCC_PLLM_DIV_3
lypinator	0:bb348c97df44	4735	* @arg @ref LL_RCC_PLLM_DIV_4
lypinator	0:bb348c97df44	4736	* @arg @ref LL_RCC_PLLM_DIV_5
lypinator	0:bb348c97df44	4737	* @arg @ref LL_RCC_PLLM_DIV_6
lypinator	0:bb348c97df44	4738	* @arg @ref LL_RCC_PLLM_DIV_7
lypinator	0:bb348c97df44	4739	* @arg @ref LL_RCC_PLLM_DIV_8
lypinator	0:bb348c97df44	4740	* @arg @ref LL_RCC_PLLM_DIV_9
lypinator	0:bb348c97df44	4741	* @arg @ref LL_RCC_PLLM_DIV_10
lypinator	0:bb348c97df44	4742	* @arg @ref LL_RCC_PLLM_DIV_11
lypinator	0:bb348c97df44	4743	* @arg @ref LL_RCC_PLLM_DIV_12
lypinator	0:bb348c97df44	4744	* @arg @ref LL_RCC_PLLM_DIV_13
lypinator	0:bb348c97df44	4745	* @arg @ref LL_RCC_PLLM_DIV_14
lypinator	0:bb348c97df44	4746	* @arg @ref LL_RCC_PLLM_DIV_15
lypinator	0:bb348c97df44	4747	* @arg @ref LL_RCC_PLLM_DIV_16
lypinator	0:bb348c97df44	4748	* @arg @ref LL_RCC_PLLM_DIV_17
lypinator	0:bb348c97df44	4749	* @arg @ref LL_RCC_PLLM_DIV_18
lypinator	0:bb348c97df44	4750	* @arg @ref LL_RCC_PLLM_DIV_19
lypinator	0:bb348c97df44	4751	* @arg @ref LL_RCC_PLLM_DIV_20
lypinator	0:bb348c97df44	4752	* @arg @ref LL_RCC_PLLM_DIV_21
lypinator	0:bb348c97df44	4753	* @arg @ref LL_RCC_PLLM_DIV_22
lypinator	0:bb348c97df44	4754	* @arg @ref LL_RCC_PLLM_DIV_23
lypinator	0:bb348c97df44	4755	* @arg @ref LL_RCC_PLLM_DIV_24
lypinator	0:bb348c97df44	4756	* @arg @ref LL_RCC_PLLM_DIV_25
lypinator	0:bb348c97df44	4757	* @arg @ref LL_RCC_PLLM_DIV_26
lypinator	0:bb348c97df44	4758	* @arg @ref LL_RCC_PLLM_DIV_27
lypinator	0:bb348c97df44	4759	* @arg @ref LL_RCC_PLLM_DIV_28
lypinator	0:bb348c97df44	4760	* @arg @ref LL_RCC_PLLM_DIV_29
lypinator	0:bb348c97df44	4761	* @arg @ref LL_RCC_PLLM_DIV_30
lypinator	0:bb348c97df44	4762	* @arg @ref LL_RCC_PLLM_DIV_31
lypinator	0:bb348c97df44	4763	* @arg @ref LL_RCC_PLLM_DIV_32
lypinator	0:bb348c97df44	4764	* @arg @ref LL_RCC_PLLM_DIV_33
lypinator	0:bb348c97df44	4765	* @arg @ref LL_RCC_PLLM_DIV_34
lypinator	0:bb348c97df44	4766	* @arg @ref LL_RCC_PLLM_DIV_35
lypinator	0:bb348c97df44	4767	* @arg @ref LL_RCC_PLLM_DIV_36
lypinator	0:bb348c97df44	4768	* @arg @ref LL_RCC_PLLM_DIV_37
lypinator	0:bb348c97df44	4769	* @arg @ref LL_RCC_PLLM_DIV_38
lypinator	0:bb348c97df44	4770	* @arg @ref LL_RCC_PLLM_DIV_39
lypinator	0:bb348c97df44	4771	* @arg @ref LL_RCC_PLLM_DIV_40
lypinator	0:bb348c97df44	4772	* @arg @ref LL_RCC_PLLM_DIV_41
lypinator	0:bb348c97df44	4773	* @arg @ref LL_RCC_PLLM_DIV_42
lypinator	0:bb348c97df44	4774	* @arg @ref LL_RCC_PLLM_DIV_43
lypinator	0:bb348c97df44	4775	* @arg @ref LL_RCC_PLLM_DIV_44
lypinator	0:bb348c97df44	4776	* @arg @ref LL_RCC_PLLM_DIV_45
lypinator	0:bb348c97df44	4777	* @arg @ref LL_RCC_PLLM_DIV_46
lypinator	0:bb348c97df44	4778	* @arg @ref LL_RCC_PLLM_DIV_47
lypinator	0:bb348c97df44	4779	* @arg @ref LL_RCC_PLLM_DIV_48
lypinator	0:bb348c97df44	4780	* @arg @ref LL_RCC_PLLM_DIV_49
lypinator	0:bb348c97df44	4781	* @arg @ref LL_RCC_PLLM_DIV_50
lypinator	0:bb348c97df44	4782	* @arg @ref LL_RCC_PLLM_DIV_51
lypinator	0:bb348c97df44	4783	* @arg @ref LL_RCC_PLLM_DIV_52
lypinator	0:bb348c97df44	4784	* @arg @ref LL_RCC_PLLM_DIV_53
lypinator	0:bb348c97df44	4785	* @arg @ref LL_RCC_PLLM_DIV_54
lypinator	0:bb348c97df44	4786	* @arg @ref LL_RCC_PLLM_DIV_55
lypinator	0:bb348c97df44	4787	* @arg @ref LL_RCC_PLLM_DIV_56
lypinator	0:bb348c97df44	4788	* @arg @ref LL_RCC_PLLM_DIV_57
lypinator	0:bb348c97df44	4789	* @arg @ref LL_RCC_PLLM_DIV_58
lypinator	0:bb348c97df44	4790	* @arg @ref LL_RCC_PLLM_DIV_59
lypinator	0:bb348c97df44	4791	* @arg @ref LL_RCC_PLLM_DIV_60
lypinator	0:bb348c97df44	4792	* @arg @ref LL_RCC_PLLM_DIV_61
lypinator	0:bb348c97df44	4793	* @arg @ref LL_RCC_PLLM_DIV_62
lypinator	0:bb348c97df44	4794	* @arg @ref LL_RCC_PLLM_DIV_63
lypinator	0:bb348c97df44	4795	* @param PLLN Between 50 and 432
lypinator	0:bb348c97df44	4796	* @param PLLR This parameter can be one of the following values:
lypinator	0:bb348c97df44	4797	* @arg @ref LL_RCC_PLLR_DIV_2
lypinator	0:bb348c97df44	4798	* @arg @ref LL_RCC_PLLR_DIV_3
lypinator	0:bb348c97df44	4799	* @arg @ref LL_RCC_PLLR_DIV_4
lypinator	0:bb348c97df44	4800	* @arg @ref LL_RCC_PLLR_DIV_5
lypinator	0:bb348c97df44	4801	* @arg @ref LL_RCC_PLLR_DIV_6
lypinator	0:bb348c97df44	4802	* @arg @ref LL_RCC_PLLR_DIV_7
lypinator	0:bb348c97df44	4803	* @param PLLDIVR This parameter can be one of the following values:
lypinator	0:bb348c97df44	4804	* @arg @ref LL_RCC_PLLDIVR_DIV_1 (*)
lypinator	0:bb348c97df44	4805	* @arg @ref LL_RCC_PLLDIVR_DIV_2 (*)
lypinator	0:bb348c97df44	4806	* @arg @ref LL_RCC_PLLDIVR_DIV_3 (*)
lypinator	0:bb348c97df44	4807	* @arg @ref LL_RCC_PLLDIVR_DIV_4 (*)
lypinator	0:bb348c97df44	4808	* @arg @ref LL_RCC_PLLDIVR_DIV_5 (*)
lypinator	0:bb348c97df44	4809	* @arg @ref LL_RCC_PLLDIVR_DIV_6 (*)
lypinator	0:bb348c97df44	4810	* @arg @ref LL_RCC_PLLDIVR_DIV_7 (*)
lypinator	0:bb348c97df44	4811	* @arg @ref LL_RCC_PLLDIVR_DIV_8 (*)
lypinator	0:bb348c97df44	4812	* @arg @ref LL_RCC_PLLDIVR_DIV_9 (*)
lypinator	0:bb348c97df44	4813	* @arg @ref LL_RCC_PLLDIVR_DIV_10 (*)
lypinator	0:bb348c97df44	4814	* @arg @ref LL_RCC_PLLDIVR_DIV_11 (*)
lypinator	0:bb348c97df44	4815	* @arg @ref LL_RCC_PLLDIVR_DIV_12 (*)
lypinator	0:bb348c97df44	4816	* @arg @ref LL_RCC_PLLDIVR_DIV_13 (*)
lypinator	0:bb348c97df44	4817	* @arg @ref LL_RCC_PLLDIVR_DIV_14 (*)
lypinator	0:bb348c97df44	4818	* @arg @ref LL_RCC_PLLDIVR_DIV_15 (*)
lypinator	0:bb348c97df44	4819	* @arg @ref LL_RCC_PLLDIVR_DIV_16 (*)
lypinator	0:bb348c97df44	4820	* @arg @ref LL_RCC_PLLDIVR_DIV_17 (*)
lypinator	0:bb348c97df44	4821	* @arg @ref LL_RCC_PLLDIVR_DIV_18 (*)
lypinator	0:bb348c97df44	4822	* @arg @ref LL_RCC_PLLDIVR_DIV_19 (*)
lypinator	0:bb348c97df44	4823	* @arg @ref LL_RCC_PLLDIVR_DIV_20 (*)
lypinator	0:bb348c97df44	4824	* @arg @ref LL_RCC_PLLDIVR_DIV_21 (*)
lypinator	0:bb348c97df44	4825	* @arg @ref LL_RCC_PLLDIVR_DIV_22 (*)
lypinator	0:bb348c97df44	4826	* @arg @ref LL_RCC_PLLDIVR_DIV_23 (*)
lypinator	0:bb348c97df44	4827	* @arg @ref LL_RCC_PLLDIVR_DIV_24 (*)
lypinator	0:bb348c97df44	4828	* @arg @ref LL_RCC_PLLDIVR_DIV_25 (*)
lypinator	0:bb348c97df44	4829	* @arg @ref LL_RCC_PLLDIVR_DIV_26 (*)
lypinator	0:bb348c97df44	4830	* @arg @ref LL_RCC_PLLDIVR_DIV_27 (*)
lypinator	0:bb348c97df44	4831	* @arg @ref LL_RCC_PLLDIVR_DIV_28 (*)
lypinator	0:bb348c97df44	4832	* @arg @ref LL_RCC_PLLDIVR_DIV_29 (*)
lypinator	0:bb348c97df44	4833	* @arg @ref LL_RCC_PLLDIVR_DIV_30 (*)
lypinator	0:bb348c97df44	4834	* @arg @ref LL_RCC_PLLDIVR_DIV_31 (*)
lypinator	0:bb348c97df44	4835	*
lypinator	0:bb348c97df44	4836	* (*) value not defined in all devices.
lypinator	0:bb348c97df44	4837	* @retval None
lypinator	0:bb348c97df44	4838	*/
lypinator	0:bb348c97df44	4839	#if defined(RCC_DCKCFGR_PLLDIVR)
lypinator	0:bb348c97df44	4840	__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR, uint32_t PLLDIVR)
lypinator	0:bb348c97df44	4841	#else
lypinator	0:bb348c97df44	4842	__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
lypinator	0:bb348c97df44	4843	#endif /* RCC_DCKCFGR_PLLDIVR */
lypinator	0:bb348c97df44	4844	{
lypinator	0:bb348c97df44	4845	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC \| RCC_PLLCFGR_PLLM \| RCC_PLLCFGR_PLLN \| RCC_PLLCFGR_PLLR,
lypinator	0:bb348c97df44	4846	Source \| PLLM \| PLLN << RCC_PLLCFGR_PLLN_Pos \| PLLR);
lypinator	0:bb348c97df44	4847	#if defined(RCC_DCKCFGR_PLLDIVR)
lypinator	0:bb348c97df44	4848	MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLDIVR, PLLDIVR);
lypinator	0:bb348c97df44	4849	#endif /* RCC_DCKCFGR_PLLDIVR */
lypinator	0:bb348c97df44	4850	}
lypinator	0:bb348c97df44	4851	#endif /* SAI1 */
lypinator	0:bb348c97df44	4852	#endif /* RCC_PLLCFGR_PLLR */
lypinator	0:bb348c97df44	4853
lypinator	0:bb348c97df44	4854	/**
lypinator	0:bb348c97df44	4855	* @brief Configure PLL clock source
lypinator	0:bb348c97df44	4856	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_SetMainSource
lypinator	0:bb348c97df44	4857	* @param PLLSource This parameter can be one of the following values:
lypinator	0:bb348c97df44	4858	* @arg @ref LL_RCC_PLLSOURCE_HSI
lypinator	0:bb348c97df44	4859	* @arg @ref LL_RCC_PLLSOURCE_HSE
lypinator	0:bb348c97df44	4860	* @retval None
lypinator	0:bb348c97df44	4861	*/
lypinator	0:bb348c97df44	4862	__STATIC_INLINE void LL_RCC_PLL_SetMainSource(uint32_t PLLSource)
lypinator	0:bb348c97df44	4863	{
lypinator	0:bb348c97df44	4864	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PLLSource);
lypinator	0:bb348c97df44	4865	}
lypinator	0:bb348c97df44	4866
lypinator	0:bb348c97df44	4867	/**
lypinator	0:bb348c97df44	4868	* @brief Get the oscillator used as PLL clock source.
lypinator	0:bb348c97df44	4869	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_GetMainSource
lypinator	0:bb348c97df44	4870	* @retval Returned value can be one of the following values:
lypinator	0:bb348c97df44	4871	* @arg @ref LL_RCC_PLLSOURCE_HSI
lypinator	0:bb348c97df44	4872	* @arg @ref LL_RCC_PLLSOURCE_HSE
lypinator	0:bb348c97df44	4873	*/
lypinator	0:bb348c97df44	4874	__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void)
lypinator	0:bb348c97df44	4875	{
lypinator	0:bb348c97df44	4876	return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC));
lypinator	0:bb348c97df44	4877	}
lypinator	0:bb348c97df44	4878
lypinator	0:bb348c97df44	4879	/**
lypinator	0:bb348c97df44	4880	* @brief Get Main PLL multiplication factor for VCO
lypinator	0:bb348c97df44	4881	* @rmtoll PLLCFGR PLLN LL_RCC_PLL_GetN
lypinator	0:bb348c97df44	4882	* @retval Between 50/192(*) and 432
lypinator	0:bb348c97df44	4883	*
lypinator	0:bb348c97df44	4884	* (*) value not defined in all devices.
lypinator	0:bb348c97df44	4885	*/
lypinator	0:bb348c97df44	4886	__STATIC_INLINE uint32_t LL_RCC_PLL_GetN(void)
lypinator	0:bb348c97df44	4887	{
lypinator	0:bb348c97df44	4888	return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
lypinator	0:bb348c97df44	4889	}
lypinator	0:bb348c97df44	4890
lypinator	0:bb348c97df44	4891	/**
lypinator	0:bb348c97df44	4892	* @brief Get Main PLL division factor for PLLP
lypinator	0:bb348c97df44	4893	* @rmtoll PLLCFGR PLLP LL_RCC_PLL_GetP
lypinator	0:bb348c97df44	4894	* @retval Returned value can be one of the following values:
lypinator	0:bb348c97df44	4895	* @arg @ref LL_RCC_PLLP_DIV_2
lypinator	0:bb348c97df44	4896	* @arg @ref LL_RCC_PLLP_DIV_4
lypinator	0:bb348c97df44	4897	* @arg @ref LL_RCC_PLLP_DIV_6
lypinator	0:bb348c97df44	4898	* @arg @ref LL_RCC_PLLP_DIV_8
lypinator	0:bb348c97df44	4899	*/
lypinator	0:bb348c97df44	4900	__STATIC_INLINE uint32_t LL_RCC_PLL_GetP(void)
lypinator	0:bb348c97df44	4901	{
lypinator	0:bb348c97df44	4902	return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP));
lypinator	0:bb348c97df44	4903	}
lypinator	0:bb348c97df44	4904
lypinator	0:bb348c97df44	4905	/**
lypinator	0:bb348c97df44	4906	* @brief Get Main PLL division factor for PLLQ
lypinator	0:bb348c97df44	4907	* @note used for PLL48MCLK selected for USB, RNG, SDIO (48 MHz clock)
lypinator	0:bb348c97df44	4908	* @rmtoll PLLCFGR PLLQ LL_RCC_PLL_GetQ
lypinator	0:bb348c97df44	4909	* @retval Returned value can be one of the following values:
lypinator	0:bb348c97df44	4910	* @arg @ref LL_RCC_PLLQ_DIV_2
lypinator	0:bb348c97df44	4911	* @arg @ref LL_RCC_PLLQ_DIV_3
lypinator	0:bb348c97df44	4912	* @arg @ref LL_RCC_PLLQ_DIV_4
lypinator	0:bb348c97df44	4913	* @arg @ref LL_RCC_PLLQ_DIV_5
lypinator	0:bb348c97df44	4914	* @arg @ref LL_RCC_PLLQ_DIV_6
lypinator	0:bb348c97df44	4915	* @arg @ref LL_RCC_PLLQ_DIV_7
lypinator	0:bb348c97df44	4916	* @arg @ref LL_RCC_PLLQ_DIV_8
lypinator	0:bb348c97df44	4917	* @arg @ref LL_RCC_PLLQ_DIV_9
lypinator	0:bb348c97df44	4918	* @arg @ref LL_RCC_PLLQ_DIV_10
lypinator	0:bb348c97df44	4919	* @arg @ref LL_RCC_PLLQ_DIV_11
lypinator	0:bb348c97df44	4920	* @arg @ref LL_RCC_PLLQ_DIV_12
lypinator	0:bb348c97df44	4921	* @arg @ref LL_RCC_PLLQ_DIV_13
lypinator	0:bb348c97df44	4922	* @arg @ref LL_RCC_PLLQ_DIV_14
lypinator	0:bb348c97df44	4923	* @arg @ref LL_RCC_PLLQ_DIV_15
lypinator	0:bb348c97df44	4924	*/
lypinator	0:bb348c97df44	4925	__STATIC_INLINE uint32_t LL_RCC_PLL_GetQ(void)
lypinator	0:bb348c97df44	4926	{
lypinator	0:bb348c97df44	4927	return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ));
lypinator	0:bb348c97df44	4928	}
lypinator	0:bb348c97df44	4929
lypinator	0:bb348c97df44	4930	#if defined(RCC_PLLCFGR_PLLR)
lypinator	0:bb348c97df44	4931	/**
lypinator	0:bb348c97df44	4932	* @brief Get Main PLL division factor for PLLR
lypinator	0:bb348c97df44	4933	* @note used for PLLCLK (system clock)
lypinator	0:bb348c97df44	4934	* @rmtoll PLLCFGR PLLR LL_RCC_PLL_GetR
lypinator	0:bb348c97df44	4935	* @retval Returned value can be one of the following values:
lypinator	0:bb348c97df44	4936	* @arg @ref LL_RCC_PLLR_DIV_2
lypinator	0:bb348c97df44	4937	* @arg @ref LL_RCC_PLLR_DIV_3
lypinator	0:bb348c97df44	4938	* @arg @ref LL_RCC_PLLR_DIV_4
lypinator	0:bb348c97df44	4939	* @arg @ref LL_RCC_PLLR_DIV_5
lypinator	0:bb348c97df44	4940	* @arg @ref LL_RCC_PLLR_DIV_6
lypinator	0:bb348c97df44	4941	* @arg @ref LL_RCC_PLLR_DIV_7
lypinator	0:bb348c97df44	4942	*/
lypinator	0:bb348c97df44	4943	__STATIC_INLINE uint32_t LL_RCC_PLL_GetR(void)
lypinator	0:bb348c97df44	4944	{
lypinator	0:bb348c97df44	4945	return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR));
lypinator	0:bb348c97df44	4946	}
lypinator	0:bb348c97df44	4947	#endif /* RCC_PLLCFGR_PLLR */
lypinator	0:bb348c97df44	4948
lypinator	0:bb348c97df44	4949	#if defined(RCC_DCKCFGR_PLLDIVR)
lypinator	0:bb348c97df44	4950	/**
lypinator	0:bb348c97df44	4951	* @brief Get Main PLL division factor for PLLDIVR
lypinator	0:bb348c97df44	4952	* @note used for PLLSAICLK (SAI1 and SAI2 clock)
lypinator	0:bb348c97df44	4953	* @rmtoll DCKCFGR PLLDIVR LL_RCC_PLL_GetDIVR
lypinator	0:bb348c97df44	4954	* @retval Returned value can be one of the following values:
lypinator	0:bb348c97df44	4955	* @arg @ref LL_RCC_PLLDIVR_DIV_1
lypinator	0:bb348c97df44	4956	* @arg @ref LL_RCC_PLLDIVR_DIV_2
lypinator	0:bb348c97df44	4957	* @arg @ref LL_RCC_PLLDIVR_DIV_3
lypinator	0:bb348c97df44	4958	* @arg @ref LL_RCC_PLLDIVR_DIV_4
lypinator	0:bb348c97df44	4959	* @arg @ref LL_RCC_PLLDIVR_DIV_5
lypinator	0:bb348c97df44	4960	* @arg @ref LL_RCC_PLLDIVR_DIV_6
lypinator	0:bb348c97df44	4961	* @arg @ref LL_RCC_PLLDIVR_DIV_7
lypinator	0:bb348c97df44	4962	* @arg @ref LL_RCC_PLLDIVR_DIV_8
lypinator	0:bb348c97df44	4963	* @arg @ref LL_RCC_PLLDIVR_DIV_9
lypinator	0:bb348c97df44	4964	* @arg @ref LL_RCC_PLLDIVR_DIV_10
lypinator	0:bb348c97df44	4965	* @arg @ref LL_RCC_PLLDIVR_DIV_11
lypinator	0:bb348c97df44	4966	* @arg @ref LL_RCC_PLLDIVR_DIV_12
lypinator	0:bb348c97df44	4967	* @arg @ref LL_RCC_PLLDIVR_DIV_13
lypinator	0:bb348c97df44	4968	* @arg @ref LL_RCC_PLLDIVR_DIV_14
lypinator	0:bb348c97df44	4969	* @arg @ref LL_RCC_PLLDIVR_DIV_15
lypinator	0:bb348c97df44	4970	* @arg @ref LL_RCC_PLLDIVR_DIV_16
lypinator	0:bb348c97df44	4971	* @arg @ref LL_RCC_PLLDIVR_DIV_17
lypinator	0:bb348c97df44	4972	* @arg @ref LL_RCC_PLLDIVR_DIV_18
lypinator	0:bb348c97df44	4973	* @arg @ref LL_RCC_PLLDIVR_DIV_19
lypinator	0:bb348c97df44	4974	* @arg @ref LL_RCC_PLLDIVR_DIV_20
lypinator	0:bb348c97df44	4975	* @arg @ref LL_RCC_PLLDIVR_DIV_21
lypinator	0:bb348c97df44	4976	* @arg @ref LL_RCC_PLLDIVR_DIV_22
lypinator	0:bb348c97df44	4977	* @arg @ref LL_RCC_PLLDIVR_DIV_23
lypinator	0:bb348c97df44	4978	* @arg @ref LL_RCC_PLLDIVR_DIV_24
lypinator	0:bb348c97df44	4979	* @arg @ref LL_RCC_PLLDIVR_DIV_25
lypinator	0:bb348c97df44	4980	* @arg @ref LL_RCC_PLLDIVR_DIV_26
lypinator	0:bb348c97df44	4981	* @arg @ref LL_RCC_PLLDIVR_DIV_27
lypinator	0:bb348c97df44	4982	* @arg @ref LL_RCC_PLLDIVR_DIV_28
lypinator	0:bb348c97df44	4983	* @arg @ref LL_RCC_PLLDIVR_DIV_29
lypinator	0:bb348c97df44	4984	* @arg @ref LL_RCC_PLLDIVR_DIV_30
lypinator	0:bb348c97df44	4985	* @arg @ref LL_RCC_PLLDIVR_DIV_31
lypinator	0:bb348c97df44	4986	*/
lypinator	0:bb348c97df44	4987	__STATIC_INLINE uint32_t LL_RCC_PLL_GetDIVR(void)
lypinator	0:bb348c97df44	4988	{
lypinator	0:bb348c97df44	4989	return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_PLLDIVR));
lypinator	0:bb348c97df44	4990	}
lypinator	0:bb348c97df44	4991	#endif /* RCC_DCKCFGR_PLLDIVR */
lypinator	0:bb348c97df44	4992
lypinator	0:bb348c97df44	4993	/**
lypinator	0:bb348c97df44	4994	* @brief Get Division factor for the main PLL and other PLL
lypinator	0:bb348c97df44	4995	* @rmtoll PLLCFGR PLLM LL_RCC_PLL_GetDivider
lypinator	0:bb348c97df44	4996	* @retval Returned value can be one of the following values:
lypinator	0:bb348c97df44	4997	* @arg @ref LL_RCC_PLLM_DIV_2
lypinator	0:bb348c97df44	4998	* @arg @ref LL_RCC_PLLM_DIV_3
lypinator	0:bb348c97df44	4999	* @arg @ref LL_RCC_PLLM_DIV_4
lypinator	0:bb348c97df44	5000	* @arg @ref LL_RCC_PLLM_DIV_5
lypinator	0:bb348c97df44	5001	* @arg @ref LL_RCC_PLLM_DIV_6
lypinator	0:bb348c97df44	5002	* @arg @ref LL_RCC_PLLM_DIV_7
lypinator	0:bb348c97df44	5003	* @arg @ref LL_RCC_PLLM_DIV_8
lypinator	0:bb348c97df44	5004	* @arg @ref LL_RCC_PLLM_DIV_9
lypinator	0:bb348c97df44	5005	* @arg @ref LL_RCC_PLLM_DIV_10
lypinator	0:bb348c97df44	5006	* @arg @ref LL_RCC_PLLM_DIV_11
lypinator	0:bb348c97df44	5007	* @arg @ref LL_RCC_PLLM_DIV_12
lypinator	0:bb348c97df44	5008	* @arg @ref LL_RCC_PLLM_DIV_13
lypinator	0:bb348c97df44	5009	* @arg @ref LL_RCC_PLLM_DIV_14
lypinator	0:bb348c97df44	5010	* @arg @ref LL_RCC_PLLM_DIV_15
lypinator	0:bb348c97df44	5011	* @arg @ref LL_RCC_PLLM_DIV_16
lypinator	0:bb348c97df44	5012	* @arg @ref LL_RCC_PLLM_DIV_17
lypinator	0:bb348c97df44	5013	* @arg @ref LL_RCC_PLLM_DIV_18
lypinator	0:bb348c97df44	5014	* @arg @ref LL_RCC_PLLM_DIV_19
lypinator	0:bb348c97df44	5015	* @arg @ref LL_RCC_PLLM_DIV_20
lypinator	0:bb348c97df44	5016	* @arg @ref LL_RCC_PLLM_DIV_21
lypinator	0:bb348c97df44	5017	* @arg @ref LL_RCC_PLLM_DIV_22
lypinator	0:bb348c97df44	5018	* @arg @ref LL_RCC_PLLM_DIV_23
lypinator	0:bb348c97df44	5019	* @arg @ref LL_RCC_PLLM_DIV_24
lypinator	0:bb348c97df44	5020	* @arg @ref LL_RCC_PLLM_DIV_25
lypinator	0:bb348c97df44	5021	* @arg @ref LL_RCC_PLLM_DIV_26
lypinator	0:bb348c97df44	5022	* @arg @ref LL_RCC_PLLM_DIV_27
lypinator	0:bb348c97df44	5023	* @arg @ref LL_RCC_PLLM_DIV_28
lypinator	0:bb348c97df44	5024	* @arg @ref LL_RCC_PLLM_DIV_29
lypinator	0:bb348c97df44	5025	* @arg @ref LL_RCC_PLLM_DIV_30
lypinator	0:bb348c97df44	5026	* @arg @ref LL_RCC_PLLM_DIV_31
lypinator	0:bb348c97df44	5027	* @arg @ref LL_RCC_PLLM_DIV_32
lypinator	0:bb348c97df44	5028	* @arg @ref LL_RCC_PLLM_DIV_33
lypinator	0:bb348c97df44	5029	* @arg @ref LL_RCC_PLLM_DIV_34
lypinator	0:bb348c97df44	5030	* @arg @ref LL_RCC_PLLM_DIV_35
lypinator	0:bb348c97df44	5031	* @arg @ref LL_RCC_PLLM_DIV_36
lypinator	0:bb348c97df44	5032	* @arg @ref LL_RCC_PLLM_DIV_37
lypinator	0:bb348c97df44	5033	* @arg @ref LL_RCC_PLLM_DIV_38
lypinator	0:bb348c97df44	5034	* @arg @ref LL_RCC_PLLM_DIV_39
lypinator	0:bb348c97df44	5035	* @arg @ref LL_RCC_PLLM_DIV_40
lypinator	0:bb348c97df44	5036	* @arg @ref LL_RCC_PLLM_DIV_41
lypinator	0:bb348c97df44	5037	* @arg @ref LL_RCC_PLLM_DIV_42
lypinator	0:bb348c97df44	5038	* @arg @ref LL_RCC_PLLM_DIV_43
lypinator	0:bb348c97df44	5039	* @arg @ref LL_RCC_PLLM_DIV_44
lypinator	0:bb348c97df44	5040	* @arg @ref LL_RCC_PLLM_DIV_45
lypinator	0:bb348c97df44	5041	* @arg @ref LL_RCC_PLLM_DIV_46
lypinator	0:bb348c97df44	5042	* @arg @ref LL_RCC_PLLM_DIV_47
lypinator	0:bb348c97df44	5043	* @arg @ref LL_RCC_PLLM_DIV_48
lypinator	0:bb348c97df44	5044	* @arg @ref LL_RCC_PLLM_DIV_49
lypinator	0:bb348c97df44	5045	* @arg @ref LL_RCC_PLLM_DIV_50
lypinator	0:bb348c97df44	5046	* @arg @ref LL_RCC_PLLM_DIV_51
lypinator	0:bb348c97df44	5047	* @arg @ref LL_RCC_PLLM_DIV_52
lypinator	0:bb348c97df44	5048	* @arg @ref LL_RCC_PLLM_DIV_53
lypinator	0:bb348c97df44	5049	* @arg @ref LL_RCC_PLLM_DIV_54
lypinator	0:bb348c97df44	5050	* @arg @ref LL_RCC_PLLM_DIV_55
lypinator	0:bb348c97df44	5051	* @arg @ref LL_RCC_PLLM_DIV_56
lypinator	0:bb348c97df44	5052	* @arg @ref LL_RCC_PLLM_DIV_57
lypinator	0:bb348c97df44	5053	* @arg @ref LL_RCC_PLLM_DIV_58
lypinator	0:bb348c97df44	5054	* @arg @ref LL_RCC_PLLM_DIV_59
lypinator	0:bb348c97df44	5055	* @arg @ref LL_RCC_PLLM_DIV_60
lypinator	0:bb348c97df44	5056	* @arg @ref LL_RCC_PLLM_DIV_61
lypinator	0:bb348c97df44	5057	* @arg @ref LL_RCC_PLLM_DIV_62
lypinator	0:bb348c97df44	5058	* @arg @ref LL_RCC_PLLM_DIV_63
lypinator	0:bb348c97df44	5059	*/
lypinator	0:bb348c97df44	5060	__STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void)
lypinator	0:bb348c97df44	5061	{
lypinator	0:bb348c97df44	5062	return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM));
lypinator	0:bb348c97df44	5063	}
lypinator	0:bb348c97df44	5064
lypinator	0:bb348c97df44	5065	/**
lypinator	0:bb348c97df44	5066	* @brief Configure Spread Spectrum used for PLL
lypinator	0:bb348c97df44	5067	* @note These bits must be written before enabling PLL
lypinator	0:bb348c97df44	5068	* @rmtoll SSCGR MODPER LL_RCC_PLL_ConfigSpreadSpectrum\n
lypinator	0:bb348c97df44	5069	* SSCGR INCSTEP LL_RCC_PLL_ConfigSpreadSpectrum\n
lypinator	0:bb348c97df44	5070	* SSCGR SPREADSEL LL_RCC_PLL_ConfigSpreadSpectrum
lypinator	0:bb348c97df44	5071	* @param Mod Between Min_Data=0 and Max_Data=8191
lypinator	0:bb348c97df44	5072	* @param Inc Between Min_Data=0 and Max_Data=32767
lypinator	0:bb348c97df44	5073	* @param Sel This parameter can be one of the following values:
lypinator	0:bb348c97df44	5074	* @arg @ref LL_RCC_SPREAD_SELECT_CENTER
lypinator	0:bb348c97df44	5075	* @arg @ref LL_RCC_SPREAD_SELECT_DOWN
lypinator	0:bb348c97df44	5076	* @retval None
lypinator	0:bb348c97df44	5077	*/
lypinator	0:bb348c97df44	5078	__STATIC_INLINE void LL_RCC_PLL_ConfigSpreadSpectrum(uint32_t Mod, uint32_t Inc, uint32_t Sel)
lypinator	0:bb348c97df44	5079	{
lypinator	0:bb348c97df44	5080	MODIFY_REG(RCC->SSCGR, RCC_SSCGR_MODPER \| RCC_SSCGR_INCSTEP \| RCC_SSCGR_SPREADSEL, Mod \| (Inc << RCC_SSCGR_INCSTEP_Pos) \| Sel);
lypinator	0:bb348c97df44	5081	}
lypinator	0:bb348c97df44	5082
lypinator	0:bb348c97df44	5083	/**
lypinator	0:bb348c97df44	5084	* @brief Get Spread Spectrum Modulation Period for PLL
lypinator	0:bb348c97df44	5085	* @rmtoll SSCGR MODPER LL_RCC_PLL_GetPeriodModulation
lypinator	0:bb348c97df44	5086	* @retval Between Min_Data=0 and Max_Data=8191
lypinator	0:bb348c97df44	5087	*/
lypinator	0:bb348c97df44	5088	__STATIC_INLINE uint32_t LL_RCC_PLL_GetPeriodModulation(void)
lypinator	0:bb348c97df44	5089	{
lypinator	0:bb348c97df44	5090	return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_MODPER));
lypinator	0:bb348c97df44	5091	}
lypinator	0:bb348c97df44	5092
lypinator	0:bb348c97df44	5093	/**
lypinator	0:bb348c97df44	5094	* @brief Get Spread Spectrum Incrementation Step for PLL
lypinator	0:bb348c97df44	5095	* @note Must be written before enabling PLL
lypinator	0:bb348c97df44	5096	* @rmtoll SSCGR INCSTEP LL_RCC_PLL_GetStepIncrementation
lypinator	0:bb348c97df44	5097	* @retval Between Min_Data=0 and Max_Data=32767
lypinator	0:bb348c97df44	5098	*/
lypinator	0:bb348c97df44	5099	__STATIC_INLINE uint32_t LL_RCC_PLL_GetStepIncrementation(void)
lypinator	0:bb348c97df44	5100	{
lypinator	0:bb348c97df44	5101	return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_INCSTEP) >> RCC_SSCGR_INCSTEP_Pos);
lypinator	0:bb348c97df44	5102	}
lypinator	0:bb348c97df44	5103
lypinator	0:bb348c97df44	5104	/**
lypinator	0:bb348c97df44	5105	* @brief Get Spread Spectrum Selection for PLL
lypinator	0:bb348c97df44	5106	* @note Must be written before enabling PLL
lypinator	0:bb348c97df44	5107	* @rmtoll SSCGR SPREADSEL LL_RCC_PLL_GetSpreadSelection
lypinator	0:bb348c97df44	5108	* @retval Returned value can be one of the following values:
lypinator	0:bb348c97df44	5109	* @arg @ref LL_RCC_SPREAD_SELECT_CENTER
lypinator	0:bb348c97df44	5110	* @arg @ref LL_RCC_SPREAD_SELECT_DOWN
lypinator	0:bb348c97df44	5111	*/
lypinator	0:bb348c97df44	5112	__STATIC_INLINE uint32_t LL_RCC_PLL_GetSpreadSelection(void)
lypinator	0:bb348c97df44	5113	{
lypinator	0:bb348c97df44	5114	return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_SPREADSEL));
lypinator	0:bb348c97df44	5115	}
lypinator	0:bb348c97df44	5116
lypinator	0:bb348c97df44	5117	/**
lypinator	0:bb348c97df44	5118	* @brief Enable Spread Spectrum for PLL.
lypinator	0:bb348c97df44	5119	* @rmtoll SSCGR SSCGEN LL_RCC_PLL_SpreadSpectrum_Enable
lypinator	0:bb348c97df44	5120	* @retval None
lypinator	0:bb348c97df44	5121	*/
lypinator	0:bb348c97df44	5122	__STATIC_INLINE void LL_RCC_PLL_SpreadSpectrum_Enable(void)
lypinator	0:bb348c97df44	5123	{
lypinator	0:bb348c97df44	5124	SET_BIT(RCC->SSCGR, RCC_SSCGR_SSCGEN);
lypinator	0:bb348c97df44	5125	}
lypinator	0:bb348c97df44	5126
lypinator	0:bb348c97df44	5127	/**
lypinator	0:bb348c97df44	5128	* @brief Disable Spread Spectrum for PLL.
lypinator	0:bb348c97df44	5129	* @rmtoll SSCGR SSCGEN LL_RCC_PLL_SpreadSpectrum_Disable
lypinator	0:bb348c97df44	5130	* @retval None
lypinator	0:bb348c97df44	5131	*/
lypinator	0:bb348c97df44	5132	__STATIC_INLINE void LL_RCC_PLL_SpreadSpectrum_Disable(void)
lypinator	0:bb348c97df44	5133	{
lypinator	0:bb348c97df44	5134	CLEAR_BIT(RCC->SSCGR, RCC_SSCGR_SSCGEN);
lypinator	0:bb348c97df44	5135	}
lypinator	0:bb348c97df44	5136
lypinator	0:bb348c97df44	5137	/**
lypinator	0:bb348c97df44	5138	* @}
lypinator	0:bb348c97df44	5139	*/
lypinator	0:bb348c97df44	5140
lypinator	0:bb348c97df44	5141	#if defined(RCC_PLLI2S_SUPPORT)
lypinator	0:bb348c97df44	5142	/** @defgroup RCC_LL_EF_PLLI2S PLLI2S
lypinator	0:bb348c97df44	5143	* @{
lypinator	0:bb348c97df44	5144	*/
lypinator	0:bb348c97df44	5145
lypinator	0:bb348c97df44	5146	/**
lypinator	0:bb348c97df44	5147	* @brief Enable PLLI2S
lypinator	0:bb348c97df44	5148	* @rmtoll CR PLLI2SON LL_RCC_PLLI2S_Enable
lypinator	0:bb348c97df44	5149	* @retval None
lypinator	0:bb348c97df44	5150	*/
lypinator	0:bb348c97df44	5151	__STATIC_INLINE void LL_RCC_PLLI2S_Enable(void)
lypinator	0:bb348c97df44	5152	{
lypinator	0:bb348c97df44	5153	SET_BIT(RCC->CR, RCC_CR_PLLI2SON);
lypinator	0:bb348c97df44	5154	}
lypinator	0:bb348c97df44	5155
lypinator	0:bb348c97df44	5156	/**
lypinator	0:bb348c97df44	5157	* @brief Disable PLLI2S
lypinator	0:bb348c97df44	5158	* @rmtoll CR PLLI2SON LL_RCC_PLLI2S_Disable
lypinator	0:bb348c97df44	5159	* @retval None
lypinator	0:bb348c97df44	5160	*/
lypinator	0:bb348c97df44	5161	__STATIC_INLINE void LL_RCC_PLLI2S_Disable(void)
lypinator	0:bb348c97df44	5162	{
lypinator	0:bb348c97df44	5163	CLEAR_BIT(RCC->CR, RCC_CR_PLLI2SON);
lypinator	0:bb348c97df44	5164	}
lypinator	0:bb348c97df44	5165
lypinator	0:bb348c97df44	5166	/**
lypinator	0:bb348c97df44	5167	* @brief Check if PLLI2S Ready
lypinator	0:bb348c97df44	5168	* @rmtoll CR PLLI2SRDY LL_RCC_PLLI2S_IsReady
lypinator	0:bb348c97df44	5169	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	5170	*/
lypinator	0:bb348c97df44	5171	__STATIC_INLINE uint32_t LL_RCC_PLLI2S_IsReady(void)
lypinator	0:bb348c97df44	5172	{
lypinator	0:bb348c97df44	5173	return (READ_BIT(RCC->CR, RCC_CR_PLLI2SRDY) == (RCC_CR_PLLI2SRDY));
lypinator	0:bb348c97df44	5174	}
lypinator	0:bb348c97df44	5175
lypinator	0:bb348c97df44	5176	#if (defined(RCC_DCKCFGR_PLLI2SDIVQ) \|\| defined(RCC_DCKCFGR_PLLI2SDIVR))
lypinator	0:bb348c97df44	5177	/**
lypinator	0:bb348c97df44	5178	* @brief Configure PLLI2S used for SAI domain clock
lypinator	0:bb348c97df44	5179	* @note PLL Source and PLLM Divider can be written only when PLL,
lypinator	0:bb348c97df44	5180	* PLLI2S and PLLSAI(*) are disabled
lypinator	0:bb348c97df44	5181	* @note PLLN/PLLQ/PLLR can be written only when PLLI2S is disabled
lypinator	0:bb348c97df44	5182	* @note This can be selected for SAI
lypinator	0:bb348c97df44	5183	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_ConfigDomain_SAI\n
lypinator	0:bb348c97df44	5184	* PLLI2SCFGR PLLI2SSRC LL_RCC_PLLI2S_ConfigDomain_SAI\n
lypinator	0:bb348c97df44	5185	* PLLCFGR PLLM LL_RCC_PLLI2S_ConfigDomain_SAI\n
lypinator	0:bb348c97df44	5186	* PLLI2SCFGR PLLI2SM LL_RCC_PLLI2S_ConfigDomain_SAI\n
lypinator	0:bb348c97df44	5187	* PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_ConfigDomain_SAI\n
lypinator	0:bb348c97df44	5188	* PLLI2SCFGR PLLI2SQ LL_RCC_PLLI2S_ConfigDomain_SAI\n
lypinator	0:bb348c97df44	5189	* PLLI2SCFGR PLLI2SR LL_RCC_PLLI2S_ConfigDomain_SAI\n
lypinator	0:bb348c97df44	5190	* DCKCFGR PLLI2SDIVQ LL_RCC_PLLI2S_ConfigDomain_SAI\n
lypinator	0:bb348c97df44	5191	* DCKCFGR PLLI2SDIVR LL_RCC_PLLI2S_ConfigDomain_SAI
lypinator	0:bb348c97df44	5192	* @param Source This parameter can be one of the following values:
lypinator	0:bb348c97df44	5193	* @arg @ref LL_RCC_PLLSOURCE_HSI
lypinator	0:bb348c97df44	5194	* @arg @ref LL_RCC_PLLSOURCE_HSE
lypinator	0:bb348c97df44	5195	* @arg @ref LL_RCC_PLLI2SSOURCE_PIN (*)
lypinator	0:bb348c97df44	5196	*
lypinator	0:bb348c97df44	5197	* (*) value not defined in all devices.
lypinator	0:bb348c97df44	5198	* @param PLLM This parameter can be one of the following values:
lypinator	0:bb348c97df44	5199	* @arg @ref LL_RCC_PLLI2SM_DIV_2
lypinator	0:bb348c97df44	5200	* @arg @ref LL_RCC_PLLI2SM_DIV_3
lypinator	0:bb348c97df44	5201	* @arg @ref LL_RCC_PLLI2SM_DIV_4
lypinator	0:bb348c97df44	5202	* @arg @ref LL_RCC_PLLI2SM_DIV_5
lypinator	0:bb348c97df44	5203	* @arg @ref LL_RCC_PLLI2SM_DIV_6
lypinator	0:bb348c97df44	5204	* @arg @ref LL_RCC_PLLI2SM_DIV_7
lypinator	0:bb348c97df44	5205	* @arg @ref LL_RCC_PLLI2SM_DIV_8
lypinator	0:bb348c97df44	5206	* @arg @ref LL_RCC_PLLI2SM_DIV_9
lypinator	0:bb348c97df44	5207	* @arg @ref LL_RCC_PLLI2SM_DIV_10
lypinator	0:bb348c97df44	5208	* @arg @ref LL_RCC_PLLI2SM_DIV_11
lypinator	0:bb348c97df44	5209	* @arg @ref LL_RCC_PLLI2SM_DIV_12
lypinator	0:bb348c97df44	5210	* @arg @ref LL_RCC_PLLI2SM_DIV_13
lypinator	0:bb348c97df44	5211	* @arg @ref LL_RCC_PLLI2SM_DIV_14
lypinator	0:bb348c97df44	5212	* @arg @ref LL_RCC_PLLI2SM_DIV_15
lypinator	0:bb348c97df44	5213	* @arg @ref LL_RCC_PLLI2SM_DIV_16
lypinator	0:bb348c97df44	5214	* @arg @ref LL_RCC_PLLI2SM_DIV_17
lypinator	0:bb348c97df44	5215	* @arg @ref LL_RCC_PLLI2SM_DIV_18
lypinator	0:bb348c97df44	5216	* @arg @ref LL_RCC_PLLI2SM_DIV_19
lypinator	0:bb348c97df44	5217	* @arg @ref LL_RCC_PLLI2SM_DIV_20
lypinator	0:bb348c97df44	5218	* @arg @ref LL_RCC_PLLI2SM_DIV_21
lypinator	0:bb348c97df44	5219	* @arg @ref LL_RCC_PLLI2SM_DIV_22
lypinator	0:bb348c97df44	5220	* @arg @ref LL_RCC_PLLI2SM_DIV_23
lypinator	0:bb348c97df44	5221	* @arg @ref LL_RCC_PLLI2SM_DIV_24
lypinator	0:bb348c97df44	5222	* @arg @ref LL_RCC_PLLI2SM_DIV_25
lypinator	0:bb348c97df44	5223	* @arg @ref LL_RCC_PLLI2SM_DIV_26
lypinator	0:bb348c97df44	5224	* @arg @ref LL_RCC_PLLI2SM_DIV_27
lypinator	0:bb348c97df44	5225	* @arg @ref LL_RCC_PLLI2SM_DIV_28
lypinator	0:bb348c97df44	5226	* @arg @ref LL_RCC_PLLI2SM_DIV_29
lypinator	0:bb348c97df44	5227	* @arg @ref LL_RCC_PLLI2SM_DIV_30
lypinator	0:bb348c97df44	5228	* @arg @ref LL_RCC_PLLI2SM_DIV_31
lypinator	0:bb348c97df44	5229	* @arg @ref LL_RCC_PLLI2SM_DIV_32
lypinator	0:bb348c97df44	5230	* @arg @ref LL_RCC_PLLI2SM_DIV_33
lypinator	0:bb348c97df44	5231	* @arg @ref LL_RCC_PLLI2SM_DIV_34
lypinator	0:bb348c97df44	5232	* @arg @ref LL_RCC_PLLI2SM_DIV_35
lypinator	0:bb348c97df44	5233	* @arg @ref LL_RCC_PLLI2SM_DIV_36
lypinator	0:bb348c97df44	5234	* @arg @ref LL_RCC_PLLI2SM_DIV_37
lypinator	0:bb348c97df44	5235	* @arg @ref LL_RCC_PLLI2SM_DIV_38
lypinator	0:bb348c97df44	5236	* @arg @ref LL_RCC_PLLI2SM_DIV_39
lypinator	0:bb348c97df44	5237	* @arg @ref LL_RCC_PLLI2SM_DIV_40
lypinator	0:bb348c97df44	5238	* @arg @ref LL_RCC_PLLI2SM_DIV_41
lypinator	0:bb348c97df44	5239	* @arg @ref LL_RCC_PLLI2SM_DIV_42
lypinator	0:bb348c97df44	5240	* @arg @ref LL_RCC_PLLI2SM_DIV_43
lypinator	0:bb348c97df44	5241	* @arg @ref LL_RCC_PLLI2SM_DIV_44
lypinator	0:bb348c97df44	5242	* @arg @ref LL_RCC_PLLI2SM_DIV_45
lypinator	0:bb348c97df44	5243	* @arg @ref LL_RCC_PLLI2SM_DIV_46
lypinator	0:bb348c97df44	5244	* @arg @ref LL_RCC_PLLI2SM_DIV_47
lypinator	0:bb348c97df44	5245	* @arg @ref LL_RCC_PLLI2SM_DIV_48
lypinator	0:bb348c97df44	5246	* @arg @ref LL_RCC_PLLI2SM_DIV_49
lypinator	0:bb348c97df44	5247	* @arg @ref LL_RCC_PLLI2SM_DIV_50
lypinator	0:bb348c97df44	5248	* @arg @ref LL_RCC_PLLI2SM_DIV_51
lypinator	0:bb348c97df44	5249	* @arg @ref LL_RCC_PLLI2SM_DIV_52
lypinator	0:bb348c97df44	5250	* @arg @ref LL_RCC_PLLI2SM_DIV_53
lypinator	0:bb348c97df44	5251	* @arg @ref LL_RCC_PLLI2SM_DIV_54
lypinator	0:bb348c97df44	5252	* @arg @ref LL_RCC_PLLI2SM_DIV_55
lypinator	0:bb348c97df44	5253	* @arg @ref LL_RCC_PLLI2SM_DIV_56
lypinator	0:bb348c97df44	5254	* @arg @ref LL_RCC_PLLI2SM_DIV_57
lypinator	0:bb348c97df44	5255	* @arg @ref LL_RCC_PLLI2SM_DIV_58
lypinator	0:bb348c97df44	5256	* @arg @ref LL_RCC_PLLI2SM_DIV_59
lypinator	0:bb348c97df44	5257	* @arg @ref LL_RCC_PLLI2SM_DIV_60
lypinator	0:bb348c97df44	5258	* @arg @ref LL_RCC_PLLI2SM_DIV_61
lypinator	0:bb348c97df44	5259	* @arg @ref LL_RCC_PLLI2SM_DIV_62
lypinator	0:bb348c97df44	5260	* @arg @ref LL_RCC_PLLI2SM_DIV_63
lypinator	0:bb348c97df44	5261	* @param PLLN Between 50/192(*) and 432
lypinator	0:bb348c97df44	5262	*
lypinator	0:bb348c97df44	5263	* (*) value not defined in all devices.
lypinator	0:bb348c97df44	5264	* @param PLLQ_R This parameter can be one of the following values:
lypinator	0:bb348c97df44	5265	* @arg @ref LL_RCC_PLLI2SQ_DIV_2 (*)
lypinator	0:bb348c97df44	5266	* @arg @ref LL_RCC_PLLI2SQ_DIV_3 (*)
lypinator	0:bb348c97df44	5267	* @arg @ref LL_RCC_PLLI2SQ_DIV_4 (*)
lypinator	0:bb348c97df44	5268	* @arg @ref LL_RCC_PLLI2SQ_DIV_5 (*)
lypinator	0:bb348c97df44	5269	* @arg @ref LL_RCC_PLLI2SQ_DIV_6 (*)
lypinator	0:bb348c97df44	5270	* @arg @ref LL_RCC_PLLI2SQ_DIV_7 (*)
lypinator	0:bb348c97df44	5271	* @arg @ref LL_RCC_PLLI2SQ_DIV_8 (*)
lypinator	0:bb348c97df44	5272	* @arg @ref LL_RCC_PLLI2SQ_DIV_9 (*)
lypinator	0:bb348c97df44	5273	* @arg @ref LL_RCC_PLLI2SQ_DIV_10 (*)
lypinator	0:bb348c97df44	5274	* @arg @ref LL_RCC_PLLI2SQ_DIV_11 (*)
lypinator	0:bb348c97df44	5275	* @arg @ref LL_RCC_PLLI2SQ_DIV_12 (*)
lypinator	0:bb348c97df44	5276	* @arg @ref LL_RCC_PLLI2SQ_DIV_13 (*)
lypinator	0:bb348c97df44	5277	* @arg @ref LL_RCC_PLLI2SQ_DIV_14 (*)
lypinator	0:bb348c97df44	5278	* @arg @ref LL_RCC_PLLI2SQ_DIV_15 (*)
lypinator	0:bb348c97df44	5279	* @arg @ref LL_RCC_PLLI2SR_DIV_2 (*)
lypinator	0:bb348c97df44	5280	* @arg @ref LL_RCC_PLLI2SR_DIV_3 (*)
lypinator	0:bb348c97df44	5281	* @arg @ref LL_RCC_PLLI2SR_DIV_4 (*)
lypinator	0:bb348c97df44	5282	* @arg @ref LL_RCC_PLLI2SR_DIV_5 (*)
lypinator	0:bb348c97df44	5283	* @arg @ref LL_RCC_PLLI2SR_DIV_6 (*)
lypinator	0:bb348c97df44	5284	* @arg @ref LL_RCC_PLLI2SR_DIV_7 (*)
lypinator	0:bb348c97df44	5285	*
lypinator	0:bb348c97df44	5286	* (*) value not defined in all devices.
lypinator	0:bb348c97df44	5287	* @param PLLDIVQ_R This parameter can be one of the following values:
lypinator	0:bb348c97df44	5288	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_1 (*)
lypinator	0:bb348c97df44	5289	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_2 (*)
lypinator	0:bb348c97df44	5290	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_3 (*)
lypinator	0:bb348c97df44	5291	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_4 (*)
lypinator	0:bb348c97df44	5292	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_5 (*)
lypinator	0:bb348c97df44	5293	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_6 (*)
lypinator	0:bb348c97df44	5294	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_7 (*)
lypinator	0:bb348c97df44	5295	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_8 (*)
lypinator	0:bb348c97df44	5296	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_9 (*)
lypinator	0:bb348c97df44	5297	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_10 (*)
lypinator	0:bb348c97df44	5298	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_11 (*)
lypinator	0:bb348c97df44	5299	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_12 (*)
lypinator	0:bb348c97df44	5300	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_13 (*)
lypinator	0:bb348c97df44	5301	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_14 (*)
lypinator	0:bb348c97df44	5302	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_15 (*)
lypinator	0:bb348c97df44	5303	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_16 (*)
lypinator	0:bb348c97df44	5304	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_17 (*)
lypinator	0:bb348c97df44	5305	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_18 (*)
lypinator	0:bb348c97df44	5306	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_19 (*)
lypinator	0:bb348c97df44	5307	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_20 (*)
lypinator	0:bb348c97df44	5308	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_21 (*)
lypinator	0:bb348c97df44	5309	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_22 (*)
lypinator	0:bb348c97df44	5310	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_23 (*)
lypinator	0:bb348c97df44	5311	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_24 (*)
lypinator	0:bb348c97df44	5312	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_25 (*)
lypinator	0:bb348c97df44	5313	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_26 (*)
lypinator	0:bb348c97df44	5314	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_27 (*)
lypinator	0:bb348c97df44	5315	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_28 (*)
lypinator	0:bb348c97df44	5316	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_29 (*)
lypinator	0:bb348c97df44	5317	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_30 (*)
lypinator	0:bb348c97df44	5318	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_31 (*)
lypinator	0:bb348c97df44	5319	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_32 (*)
lypinator	0:bb348c97df44	5320	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_1 (*)
lypinator	0:bb348c97df44	5321	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_2 (*)
lypinator	0:bb348c97df44	5322	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_3 (*)
lypinator	0:bb348c97df44	5323	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_4 (*)
lypinator	0:bb348c97df44	5324	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_5 (*)
lypinator	0:bb348c97df44	5325	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_6 (*)
lypinator	0:bb348c97df44	5326	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_7 (*)
lypinator	0:bb348c97df44	5327	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_8 (*)
lypinator	0:bb348c97df44	5328	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_9 (*)
lypinator	0:bb348c97df44	5329	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_10 (*)
lypinator	0:bb348c97df44	5330	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_11 (*)
lypinator	0:bb348c97df44	5331	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_12 (*)
lypinator	0:bb348c97df44	5332	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_13 (*)
lypinator	0:bb348c97df44	5333	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_14 (*)
lypinator	0:bb348c97df44	5334	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_15 (*)
lypinator	0:bb348c97df44	5335	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_16 (*)
lypinator	0:bb348c97df44	5336	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_17 (*)
lypinator	0:bb348c97df44	5337	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_18 (*)
lypinator	0:bb348c97df44	5338	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_19 (*)
lypinator	0:bb348c97df44	5339	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_20 (*)
lypinator	0:bb348c97df44	5340	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_21 (*)
lypinator	0:bb348c97df44	5341	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_22 (*)
lypinator	0:bb348c97df44	5342	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_23 (*)
lypinator	0:bb348c97df44	5343	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_24 (*)
lypinator	0:bb348c97df44	5344	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_25 (*)
lypinator	0:bb348c97df44	5345	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_26 (*)
lypinator	0:bb348c97df44	5346	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_27 (*)
lypinator	0:bb348c97df44	5347	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_28 (*)
lypinator	0:bb348c97df44	5348	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_29 (*)
lypinator	0:bb348c97df44	5349	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_30 (*)
lypinator	0:bb348c97df44	5350	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_31 (*)
lypinator	0:bb348c97df44	5351	*
lypinator	0:bb348c97df44	5352	* (*) value not defined in all devices.
lypinator	0:bb348c97df44	5353	* @retval None
lypinator	0:bb348c97df44	5354	*/
lypinator	0:bb348c97df44	5355	__STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ_R, uint32_t PLLDIVQ_R)
lypinator	0:bb348c97df44	5356	{
lypinator	0:bb348c97df44	5357	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&RCC->PLLCFGR) + (Source & 0x80U)));
lypinator	0:bb348c97df44	5358	MODIFY_REG(*pReg, RCC_PLLCFGR_PLLSRC, (Source & (~0x80U)));
lypinator	0:bb348c97df44	5359	#if defined(RCC_PLLI2SCFGR_PLLI2SM)
lypinator	0:bb348c97df44	5360	MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM, PLLM);
lypinator	0:bb348c97df44	5361	#else
lypinator	0:bb348c97df44	5362	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM);
lypinator	0:bb348c97df44	5363	#endif /* RCC_PLLI2SCFGR_PLLI2SM */
lypinator	0:bb348c97df44	5364	MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos);
lypinator	0:bb348c97df44	5365	#if defined(RCC_DCKCFGR_PLLI2SDIVQ)
lypinator	0:bb348c97df44	5366	MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SQ, PLLQ_R);
lypinator	0:bb348c97df44	5367	MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVQ, PLLDIVQ_R);
lypinator	0:bb348c97df44	5368	#else
lypinator	0:bb348c97df44	5369	MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SR, PLLQ_R);
lypinator	0:bb348c97df44	5370	MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVR, PLLDIVQ_R);
lypinator	0:bb348c97df44	5371	#endif /* RCC_DCKCFGR_PLLI2SDIVQ */
lypinator	0:bb348c97df44	5372	}
lypinator	0:bb348c97df44	5373	#endif /* RCC_DCKCFGR_PLLI2SDIVQ && RCC_DCKCFGR_PLLI2SDIVR */
lypinator	0:bb348c97df44	5374
lypinator	0:bb348c97df44	5375	#if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
lypinator	0:bb348c97df44	5376	/**
lypinator	0:bb348c97df44	5377	* @brief Configure PLLI2S used for 48Mhz domain clock
lypinator	0:bb348c97df44	5378	* @note PLL Source and PLLM Divider can be written only when PLL,
lypinator	0:bb348c97df44	5379	* PLLI2S and PLLSAI(*) are disabled
lypinator	0:bb348c97df44	5380	* @note PLLN/PLLQ can be written only when PLLI2S is disabled
lypinator	0:bb348c97df44	5381	* @note This can be selected for RNG, USB, SDIO
lypinator	0:bb348c97df44	5382	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_ConfigDomain_48M\n
lypinator	0:bb348c97df44	5383	* PLLI2SCFGR PLLI2SSRC LL_RCC_PLLI2S_ConfigDomain_48M\n
lypinator	0:bb348c97df44	5384	* PLLCFGR PLLM LL_RCC_PLLI2S_ConfigDomain_48M\n
lypinator	0:bb348c97df44	5385	* PLLI2SCFGR PLLI2SM LL_RCC_PLLI2S_ConfigDomain_48M\n
lypinator	0:bb348c97df44	5386	* PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_ConfigDomain_48M\n
lypinator	0:bb348c97df44	5387	* PLLI2SCFGR PLLI2SQ LL_RCC_PLLI2S_ConfigDomain_48M
lypinator	0:bb348c97df44	5388	* @param Source This parameter can be one of the following values:
lypinator	0:bb348c97df44	5389	* @arg @ref LL_RCC_PLLSOURCE_HSI
lypinator	0:bb348c97df44	5390	* @arg @ref LL_RCC_PLLSOURCE_HSE
lypinator	0:bb348c97df44	5391	* @arg @ref LL_RCC_PLLI2SSOURCE_PIN (*)
lypinator	0:bb348c97df44	5392	*
lypinator	0:bb348c97df44	5393	* (*) value not defined in all devices.
lypinator	0:bb348c97df44	5394	* @param PLLM This parameter can be one of the following values:
lypinator	0:bb348c97df44	5395	* @arg @ref LL_RCC_PLLI2SM_DIV_2
lypinator	0:bb348c97df44	5396	* @arg @ref LL_RCC_PLLI2SM_DIV_3
lypinator	0:bb348c97df44	5397	* @arg @ref LL_RCC_PLLI2SM_DIV_4
lypinator	0:bb348c97df44	5398	* @arg @ref LL_RCC_PLLI2SM_DIV_5
lypinator	0:bb348c97df44	5399	* @arg @ref LL_RCC_PLLI2SM_DIV_6
lypinator	0:bb348c97df44	5400	* @arg @ref LL_RCC_PLLI2SM_DIV_7
lypinator	0:bb348c97df44	5401	* @arg @ref LL_RCC_PLLI2SM_DIV_8
lypinator	0:bb348c97df44	5402	* @arg @ref LL_RCC_PLLI2SM_DIV_9
lypinator	0:bb348c97df44	5403	* @arg @ref LL_RCC_PLLI2SM_DIV_10
lypinator	0:bb348c97df44	5404	* @arg @ref LL_RCC_PLLI2SM_DIV_11
lypinator	0:bb348c97df44	5405	* @arg @ref LL_RCC_PLLI2SM_DIV_12
lypinator	0:bb348c97df44	5406	* @arg @ref LL_RCC_PLLI2SM_DIV_13
lypinator	0:bb348c97df44	5407	* @arg @ref LL_RCC_PLLI2SM_DIV_14
lypinator	0:bb348c97df44	5408	* @arg @ref LL_RCC_PLLI2SM_DIV_15
lypinator	0:bb348c97df44	5409	* @arg @ref LL_RCC_PLLI2SM_DIV_16
lypinator	0:bb348c97df44	5410	* @arg @ref LL_RCC_PLLI2SM_DIV_17
lypinator	0:bb348c97df44	5411	* @arg @ref LL_RCC_PLLI2SM_DIV_18
lypinator	0:bb348c97df44	5412	* @arg @ref LL_RCC_PLLI2SM_DIV_19
lypinator	0:bb348c97df44	5413	* @arg @ref LL_RCC_PLLI2SM_DIV_20
lypinator	0:bb348c97df44	5414	* @arg @ref LL_RCC_PLLI2SM_DIV_21
lypinator	0:bb348c97df44	5415	* @arg @ref LL_RCC_PLLI2SM_DIV_22
lypinator	0:bb348c97df44	5416	* @arg @ref LL_RCC_PLLI2SM_DIV_23
lypinator	0:bb348c97df44	5417	* @arg @ref LL_RCC_PLLI2SM_DIV_24
lypinator	0:bb348c97df44	5418	* @arg @ref LL_RCC_PLLI2SM_DIV_25
lypinator	0:bb348c97df44	5419	* @arg @ref LL_RCC_PLLI2SM_DIV_26
lypinator	0:bb348c97df44	5420	* @arg @ref LL_RCC_PLLI2SM_DIV_27
lypinator	0:bb348c97df44	5421	* @arg @ref LL_RCC_PLLI2SM_DIV_28
lypinator	0:bb348c97df44	5422	* @arg @ref LL_RCC_PLLI2SM_DIV_29
lypinator	0:bb348c97df44	5423	* @arg @ref LL_RCC_PLLI2SM_DIV_30
lypinator	0:bb348c97df44	5424	* @arg @ref LL_RCC_PLLI2SM_DIV_31
lypinator	0:bb348c97df44	5425	* @arg @ref LL_RCC_PLLI2SM_DIV_32
lypinator	0:bb348c97df44	5426	* @arg @ref LL_RCC_PLLI2SM_DIV_33
lypinator	0:bb348c97df44	5427	* @arg @ref LL_RCC_PLLI2SM_DIV_34
lypinator	0:bb348c97df44	5428	* @arg @ref LL_RCC_PLLI2SM_DIV_35
lypinator	0:bb348c97df44	5429	* @arg @ref LL_RCC_PLLI2SM_DIV_36
lypinator	0:bb348c97df44	5430	* @arg @ref LL_RCC_PLLI2SM_DIV_37
lypinator	0:bb348c97df44	5431	* @arg @ref LL_RCC_PLLI2SM_DIV_38
lypinator	0:bb348c97df44	5432	* @arg @ref LL_RCC_PLLI2SM_DIV_39
lypinator	0:bb348c97df44	5433	* @arg @ref LL_RCC_PLLI2SM_DIV_40
lypinator	0:bb348c97df44	5434	* @arg @ref LL_RCC_PLLI2SM_DIV_41
lypinator	0:bb348c97df44	5435	* @arg @ref LL_RCC_PLLI2SM_DIV_42
lypinator	0:bb348c97df44	5436	* @arg @ref LL_RCC_PLLI2SM_DIV_43
lypinator	0:bb348c97df44	5437	* @arg @ref LL_RCC_PLLI2SM_DIV_44
lypinator	0:bb348c97df44	5438	* @arg @ref LL_RCC_PLLI2SM_DIV_45
lypinator	0:bb348c97df44	5439	* @arg @ref LL_RCC_PLLI2SM_DIV_46
lypinator	0:bb348c97df44	5440	* @arg @ref LL_RCC_PLLI2SM_DIV_47
lypinator	0:bb348c97df44	5441	* @arg @ref LL_RCC_PLLI2SM_DIV_48
lypinator	0:bb348c97df44	5442	* @arg @ref LL_RCC_PLLI2SM_DIV_49
lypinator	0:bb348c97df44	5443	* @arg @ref LL_RCC_PLLI2SM_DIV_50
lypinator	0:bb348c97df44	5444	* @arg @ref LL_RCC_PLLI2SM_DIV_51
lypinator	0:bb348c97df44	5445	* @arg @ref LL_RCC_PLLI2SM_DIV_52
lypinator	0:bb348c97df44	5446	* @arg @ref LL_RCC_PLLI2SM_DIV_53
lypinator	0:bb348c97df44	5447	* @arg @ref LL_RCC_PLLI2SM_DIV_54
lypinator	0:bb348c97df44	5448	* @arg @ref LL_RCC_PLLI2SM_DIV_55
lypinator	0:bb348c97df44	5449	* @arg @ref LL_RCC_PLLI2SM_DIV_56
lypinator	0:bb348c97df44	5450	* @arg @ref LL_RCC_PLLI2SM_DIV_57
lypinator	0:bb348c97df44	5451	* @arg @ref LL_RCC_PLLI2SM_DIV_58
lypinator	0:bb348c97df44	5452	* @arg @ref LL_RCC_PLLI2SM_DIV_59
lypinator	0:bb348c97df44	5453	* @arg @ref LL_RCC_PLLI2SM_DIV_60
lypinator	0:bb348c97df44	5454	* @arg @ref LL_RCC_PLLI2SM_DIV_61
lypinator	0:bb348c97df44	5455	* @arg @ref LL_RCC_PLLI2SM_DIV_62
lypinator	0:bb348c97df44	5456	* @arg @ref LL_RCC_PLLI2SM_DIV_63
lypinator	0:bb348c97df44	5457	* @param PLLN Between 50 and 432
lypinator	0:bb348c97df44	5458	* @param PLLQ This parameter can be one of the following values:
lypinator	0:bb348c97df44	5459	* @arg @ref LL_RCC_PLLI2SQ_DIV_2
lypinator	0:bb348c97df44	5460	* @arg @ref LL_RCC_PLLI2SQ_DIV_3
lypinator	0:bb348c97df44	5461	* @arg @ref LL_RCC_PLLI2SQ_DIV_4
lypinator	0:bb348c97df44	5462	* @arg @ref LL_RCC_PLLI2SQ_DIV_5
lypinator	0:bb348c97df44	5463	* @arg @ref LL_RCC_PLLI2SQ_DIV_6
lypinator	0:bb348c97df44	5464	* @arg @ref LL_RCC_PLLI2SQ_DIV_7
lypinator	0:bb348c97df44	5465	* @arg @ref LL_RCC_PLLI2SQ_DIV_8
lypinator	0:bb348c97df44	5466	* @arg @ref LL_RCC_PLLI2SQ_DIV_9
lypinator	0:bb348c97df44	5467	* @arg @ref LL_RCC_PLLI2SQ_DIV_10
lypinator	0:bb348c97df44	5468	* @arg @ref LL_RCC_PLLI2SQ_DIV_11
lypinator	0:bb348c97df44	5469	* @arg @ref LL_RCC_PLLI2SQ_DIV_12
lypinator	0:bb348c97df44	5470	* @arg @ref LL_RCC_PLLI2SQ_DIV_13
lypinator	0:bb348c97df44	5471	* @arg @ref LL_RCC_PLLI2SQ_DIV_14
lypinator	0:bb348c97df44	5472	* @arg @ref LL_RCC_PLLI2SQ_DIV_15
lypinator	0:bb348c97df44	5473	* @retval None
lypinator	0:bb348c97df44	5474	*/
lypinator	0:bb348c97df44	5475	__STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
lypinator	0:bb348c97df44	5476	{
lypinator	0:bb348c97df44	5477	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&RCC->PLLCFGR) + (Source & 0x80U)));
lypinator	0:bb348c97df44	5478	MODIFY_REG(*pReg, RCC_PLLCFGR_PLLSRC, (Source & (~0x80U)));
lypinator	0:bb348c97df44	5479	#if defined(RCC_PLLI2SCFGR_PLLI2SM)
lypinator	0:bb348c97df44	5480	MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM, PLLM);
lypinator	0:bb348c97df44	5481	#else
lypinator	0:bb348c97df44	5482	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM);
lypinator	0:bb348c97df44	5483	#endif /* RCC_PLLI2SCFGR_PLLI2SM */
lypinator	0:bb348c97df44	5484	MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN \| RCC_PLLI2SCFGR_PLLI2SQ, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos \| PLLQ);
lypinator	0:bb348c97df44	5485	}
lypinator	0:bb348c97df44	5486	#endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
lypinator	0:bb348c97df44	5487
lypinator	0:bb348c97df44	5488	#if defined(SPDIFRX)
lypinator	0:bb348c97df44	5489	/**
lypinator	0:bb348c97df44	5490	* @brief Configure PLLI2S used for SPDIFRX domain clock
lypinator	0:bb348c97df44	5491	* @note PLL Source and PLLM Divider can be written only when PLL,
lypinator	0:bb348c97df44	5492	* PLLI2S and PLLSAI(*) are disabled
lypinator	0:bb348c97df44	5493	* @note PLLN/PLLP can be written only when PLLI2S is disabled
lypinator	0:bb348c97df44	5494	* @note This can be selected for SPDIFRX
lypinator	0:bb348c97df44	5495	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n
lypinator	0:bb348c97df44	5496	* PLLCFGR PLLM LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n
lypinator	0:bb348c97df44	5497	* PLLI2SCFGR PLLI2SM LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n
lypinator	0:bb348c97df44	5498	* PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n
lypinator	0:bb348c97df44	5499	* PLLI2SCFGR PLLI2SP LL_RCC_PLLI2S_ConfigDomain_SPDIFRX
lypinator	0:bb348c97df44	5500	* @param Source This parameter can be one of the following values:
lypinator	0:bb348c97df44	5501	* @arg @ref LL_RCC_PLLSOURCE_HSI
lypinator	0:bb348c97df44	5502	* @arg @ref LL_RCC_PLLSOURCE_HSE
lypinator	0:bb348c97df44	5503	* @param PLLM This parameter can be one of the following values:
lypinator	0:bb348c97df44	5504	* @arg @ref LL_RCC_PLLI2SM_DIV_2
lypinator	0:bb348c97df44	5505	* @arg @ref LL_RCC_PLLI2SM_DIV_3
lypinator	0:bb348c97df44	5506	* @arg @ref LL_RCC_PLLI2SM_DIV_4
lypinator	0:bb348c97df44	5507	* @arg @ref LL_RCC_PLLI2SM_DIV_5
lypinator	0:bb348c97df44	5508	* @arg @ref LL_RCC_PLLI2SM_DIV_6
lypinator	0:bb348c97df44	5509	* @arg @ref LL_RCC_PLLI2SM_DIV_7
lypinator	0:bb348c97df44	5510	* @arg @ref LL_RCC_PLLI2SM_DIV_8
lypinator	0:bb348c97df44	5511	* @arg @ref LL_RCC_PLLI2SM_DIV_9
lypinator	0:bb348c97df44	5512	* @arg @ref LL_RCC_PLLI2SM_DIV_10
lypinator	0:bb348c97df44	5513	* @arg @ref LL_RCC_PLLI2SM_DIV_11
lypinator	0:bb348c97df44	5514	* @arg @ref LL_RCC_PLLI2SM_DIV_12
lypinator	0:bb348c97df44	5515	* @arg @ref LL_RCC_PLLI2SM_DIV_13
lypinator	0:bb348c97df44	5516	* @arg @ref LL_RCC_PLLI2SM_DIV_14
lypinator	0:bb348c97df44	5517	* @arg @ref LL_RCC_PLLI2SM_DIV_15
lypinator	0:bb348c97df44	5518	* @arg @ref LL_RCC_PLLI2SM_DIV_16
lypinator	0:bb348c97df44	5519	* @arg @ref LL_RCC_PLLI2SM_DIV_17
lypinator	0:bb348c97df44	5520	* @arg @ref LL_RCC_PLLI2SM_DIV_18
lypinator	0:bb348c97df44	5521	* @arg @ref LL_RCC_PLLI2SM_DIV_19
lypinator	0:bb348c97df44	5522	* @arg @ref LL_RCC_PLLI2SM_DIV_20
lypinator	0:bb348c97df44	5523	* @arg @ref LL_RCC_PLLI2SM_DIV_21
lypinator	0:bb348c97df44	5524	* @arg @ref LL_RCC_PLLI2SM_DIV_22
lypinator	0:bb348c97df44	5525	* @arg @ref LL_RCC_PLLI2SM_DIV_23
lypinator	0:bb348c97df44	5526	* @arg @ref LL_RCC_PLLI2SM_DIV_24
lypinator	0:bb348c97df44	5527	* @arg @ref LL_RCC_PLLI2SM_DIV_25
lypinator	0:bb348c97df44	5528	* @arg @ref LL_RCC_PLLI2SM_DIV_26
lypinator	0:bb348c97df44	5529	* @arg @ref LL_RCC_PLLI2SM_DIV_27
lypinator	0:bb348c97df44	5530	* @arg @ref LL_RCC_PLLI2SM_DIV_28
lypinator	0:bb348c97df44	5531	* @arg @ref LL_RCC_PLLI2SM_DIV_29
lypinator	0:bb348c97df44	5532	* @arg @ref LL_RCC_PLLI2SM_DIV_30
lypinator	0:bb348c97df44	5533	* @arg @ref LL_RCC_PLLI2SM_DIV_31
lypinator	0:bb348c97df44	5534	* @arg @ref LL_RCC_PLLI2SM_DIV_32
lypinator	0:bb348c97df44	5535	* @arg @ref LL_RCC_PLLI2SM_DIV_33
lypinator	0:bb348c97df44	5536	* @arg @ref LL_RCC_PLLI2SM_DIV_34
lypinator	0:bb348c97df44	5537	* @arg @ref LL_RCC_PLLI2SM_DIV_35
lypinator	0:bb348c97df44	5538	* @arg @ref LL_RCC_PLLI2SM_DIV_36
lypinator	0:bb348c97df44	5539	* @arg @ref LL_RCC_PLLI2SM_DIV_37
lypinator	0:bb348c97df44	5540	* @arg @ref LL_RCC_PLLI2SM_DIV_38
lypinator	0:bb348c97df44	5541	* @arg @ref LL_RCC_PLLI2SM_DIV_39
lypinator	0:bb348c97df44	5542	* @arg @ref LL_RCC_PLLI2SM_DIV_40
lypinator	0:bb348c97df44	5543	* @arg @ref LL_RCC_PLLI2SM_DIV_41
lypinator	0:bb348c97df44	5544	* @arg @ref LL_RCC_PLLI2SM_DIV_42
lypinator	0:bb348c97df44	5545	* @arg @ref LL_RCC_PLLI2SM_DIV_43
lypinator	0:bb348c97df44	5546	* @arg @ref LL_RCC_PLLI2SM_DIV_44
lypinator	0:bb348c97df44	5547	* @arg @ref LL_RCC_PLLI2SM_DIV_45
lypinator	0:bb348c97df44	5548	* @arg @ref LL_RCC_PLLI2SM_DIV_46
lypinator	0:bb348c97df44	5549	* @arg @ref LL_RCC_PLLI2SM_DIV_47
lypinator	0:bb348c97df44	5550	* @arg @ref LL_RCC_PLLI2SM_DIV_48
lypinator	0:bb348c97df44	5551	* @arg @ref LL_RCC_PLLI2SM_DIV_49
lypinator	0:bb348c97df44	5552	* @arg @ref LL_RCC_PLLI2SM_DIV_50
lypinator	0:bb348c97df44	5553	* @arg @ref LL_RCC_PLLI2SM_DIV_51
lypinator	0:bb348c97df44	5554	* @arg @ref LL_RCC_PLLI2SM_DIV_52
lypinator	0:bb348c97df44	5555	* @arg @ref LL_RCC_PLLI2SM_DIV_53
lypinator	0:bb348c97df44	5556	* @arg @ref LL_RCC_PLLI2SM_DIV_54
lypinator	0:bb348c97df44	5557	* @arg @ref LL_RCC_PLLI2SM_DIV_55
lypinator	0:bb348c97df44	5558	* @arg @ref LL_RCC_PLLI2SM_DIV_56
lypinator	0:bb348c97df44	5559	* @arg @ref LL_RCC_PLLI2SM_DIV_57
lypinator	0:bb348c97df44	5560	* @arg @ref LL_RCC_PLLI2SM_DIV_58
lypinator	0:bb348c97df44	5561	* @arg @ref LL_RCC_PLLI2SM_DIV_59
lypinator	0:bb348c97df44	5562	* @arg @ref LL_RCC_PLLI2SM_DIV_60
lypinator	0:bb348c97df44	5563	* @arg @ref LL_RCC_PLLI2SM_DIV_61
lypinator	0:bb348c97df44	5564	* @arg @ref LL_RCC_PLLI2SM_DIV_62
lypinator	0:bb348c97df44	5565	* @arg @ref LL_RCC_PLLI2SM_DIV_63
lypinator	0:bb348c97df44	5566	* @param PLLN Between 50 and 432
lypinator	0:bb348c97df44	5567	* @param PLLP This parameter can be one of the following values:
lypinator	0:bb348c97df44	5568	* @arg @ref LL_RCC_PLLI2SP_DIV_2
lypinator	0:bb348c97df44	5569	* @arg @ref LL_RCC_PLLI2SP_DIV_4
lypinator	0:bb348c97df44	5570	* @arg @ref LL_RCC_PLLI2SP_DIV_6
lypinator	0:bb348c97df44	5571	* @arg @ref LL_RCC_PLLI2SP_DIV_8
lypinator	0:bb348c97df44	5572	* @retval None
lypinator	0:bb348c97df44	5573	*/
lypinator	0:bb348c97df44	5574	__STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_SPDIFRX(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
lypinator	0:bb348c97df44	5575	{
lypinator	0:bb348c97df44	5576	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source);
lypinator	0:bb348c97df44	5577	#if defined(RCC_PLLI2SCFGR_PLLI2SM)
lypinator	0:bb348c97df44	5578	MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM, PLLM);
lypinator	0:bb348c97df44	5579	#else
lypinator	0:bb348c97df44	5580	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM);
lypinator	0:bb348c97df44	5581	#endif /* RCC_PLLI2SCFGR_PLLI2SM */
lypinator	0:bb348c97df44	5582	MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN \| RCC_PLLI2SCFGR_PLLI2SP, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos \| PLLP);
lypinator	0:bb348c97df44	5583	}
lypinator	0:bb348c97df44	5584	#endif /* SPDIFRX */
lypinator	0:bb348c97df44	5585
lypinator	0:bb348c97df44	5586	/**
lypinator	0:bb348c97df44	5587	* @brief Configure PLLI2S used for I2S1 domain clock
lypinator	0:bb348c97df44	5588	* @note PLL Source and PLLM Divider can be written only when PLL,
lypinator	0:bb348c97df44	5589	* PLLI2S and PLLSAI(*) are disabled
lypinator	0:bb348c97df44	5590	* @note PLLN/PLLR can be written only when PLLI2S is disabled
lypinator	0:bb348c97df44	5591	* @note This can be selected for I2S
lypinator	0:bb348c97df44	5592	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_ConfigDomain_I2S\n
lypinator	0:bb348c97df44	5593	* PLLCFGR PLLM LL_RCC_PLLI2S_ConfigDomain_I2S\n
lypinator	0:bb348c97df44	5594	* PLLI2SCFGR PLLI2SSRC LL_RCC_PLLI2S_ConfigDomain_I2S\n
lypinator	0:bb348c97df44	5595	* PLLI2SCFGR PLLI2SM LL_RCC_PLLI2S_ConfigDomain_I2S\n
lypinator	0:bb348c97df44	5596	* PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_ConfigDomain_I2S\n
lypinator	0:bb348c97df44	5597	* PLLI2SCFGR PLLI2SR LL_RCC_PLLI2S_ConfigDomain_I2S
lypinator	0:bb348c97df44	5598	* @param Source This parameter can be one of the following values:
lypinator	0:bb348c97df44	5599	* @arg @ref LL_RCC_PLLSOURCE_HSI
lypinator	0:bb348c97df44	5600	* @arg @ref LL_RCC_PLLSOURCE_HSE
lypinator	0:bb348c97df44	5601	* @arg @ref LL_RCC_PLLI2SSOURCE_PIN (*)
lypinator	0:bb348c97df44	5602	*
lypinator	0:bb348c97df44	5603	* (*) value not defined in all devices.
lypinator	0:bb348c97df44	5604	* @param PLLM This parameter can be one of the following values:
lypinator	0:bb348c97df44	5605	* @arg @ref LL_RCC_PLLI2SM_DIV_2
lypinator	0:bb348c97df44	5606	* @arg @ref LL_RCC_PLLI2SM_DIV_3
lypinator	0:bb348c97df44	5607	* @arg @ref LL_RCC_PLLI2SM_DIV_4
lypinator	0:bb348c97df44	5608	* @arg @ref LL_RCC_PLLI2SM_DIV_5
lypinator	0:bb348c97df44	5609	* @arg @ref LL_RCC_PLLI2SM_DIV_6
lypinator	0:bb348c97df44	5610	* @arg @ref LL_RCC_PLLI2SM_DIV_7
lypinator	0:bb348c97df44	5611	* @arg @ref LL_RCC_PLLI2SM_DIV_8
lypinator	0:bb348c97df44	5612	* @arg @ref LL_RCC_PLLI2SM_DIV_9
lypinator	0:bb348c97df44	5613	* @arg @ref LL_RCC_PLLI2SM_DIV_10
lypinator	0:bb348c97df44	5614	* @arg @ref LL_RCC_PLLI2SM_DIV_11
lypinator	0:bb348c97df44	5615	* @arg @ref LL_RCC_PLLI2SM_DIV_12
lypinator	0:bb348c97df44	5616	* @arg @ref LL_RCC_PLLI2SM_DIV_13
lypinator	0:bb348c97df44	5617	* @arg @ref LL_RCC_PLLI2SM_DIV_14
lypinator	0:bb348c97df44	5618	* @arg @ref LL_RCC_PLLI2SM_DIV_15
lypinator	0:bb348c97df44	5619	* @arg @ref LL_RCC_PLLI2SM_DIV_16
lypinator	0:bb348c97df44	5620	* @arg @ref LL_RCC_PLLI2SM_DIV_17
lypinator	0:bb348c97df44	5621	* @arg @ref LL_RCC_PLLI2SM_DIV_18
lypinator	0:bb348c97df44	5622	* @arg @ref LL_RCC_PLLI2SM_DIV_19
lypinator	0:bb348c97df44	5623	* @arg @ref LL_RCC_PLLI2SM_DIV_20
lypinator	0:bb348c97df44	5624	* @arg @ref LL_RCC_PLLI2SM_DIV_21
lypinator	0:bb348c97df44	5625	* @arg @ref LL_RCC_PLLI2SM_DIV_22
lypinator	0:bb348c97df44	5626	* @arg @ref LL_RCC_PLLI2SM_DIV_23
lypinator	0:bb348c97df44	5627	* @arg @ref LL_RCC_PLLI2SM_DIV_24
lypinator	0:bb348c97df44	5628	* @arg @ref LL_RCC_PLLI2SM_DIV_25
lypinator	0:bb348c97df44	5629	* @arg @ref LL_RCC_PLLI2SM_DIV_26
lypinator	0:bb348c97df44	5630	* @arg @ref LL_RCC_PLLI2SM_DIV_27
lypinator	0:bb348c97df44	5631	* @arg @ref LL_RCC_PLLI2SM_DIV_28
lypinator	0:bb348c97df44	5632	* @arg @ref LL_RCC_PLLI2SM_DIV_29
lypinator	0:bb348c97df44	5633	* @arg @ref LL_RCC_PLLI2SM_DIV_30
lypinator	0:bb348c97df44	5634	* @arg @ref LL_RCC_PLLI2SM_DIV_31
lypinator	0:bb348c97df44	5635	* @arg @ref LL_RCC_PLLI2SM_DIV_32
lypinator	0:bb348c97df44	5636	* @arg @ref LL_RCC_PLLI2SM_DIV_33
lypinator	0:bb348c97df44	5637	* @arg @ref LL_RCC_PLLI2SM_DIV_34
lypinator	0:bb348c97df44	5638	* @arg @ref LL_RCC_PLLI2SM_DIV_35
lypinator	0:bb348c97df44	5639	* @arg @ref LL_RCC_PLLI2SM_DIV_36
lypinator	0:bb348c97df44	5640	* @arg @ref LL_RCC_PLLI2SM_DIV_37
lypinator	0:bb348c97df44	5641	* @arg @ref LL_RCC_PLLI2SM_DIV_38
lypinator	0:bb348c97df44	5642	* @arg @ref LL_RCC_PLLI2SM_DIV_39
lypinator	0:bb348c97df44	5643	* @arg @ref LL_RCC_PLLI2SM_DIV_40
lypinator	0:bb348c97df44	5644	* @arg @ref LL_RCC_PLLI2SM_DIV_41
lypinator	0:bb348c97df44	5645	* @arg @ref LL_RCC_PLLI2SM_DIV_42
lypinator	0:bb348c97df44	5646	* @arg @ref LL_RCC_PLLI2SM_DIV_43
lypinator	0:bb348c97df44	5647	* @arg @ref LL_RCC_PLLI2SM_DIV_44
lypinator	0:bb348c97df44	5648	* @arg @ref LL_RCC_PLLI2SM_DIV_45
lypinator	0:bb348c97df44	5649	* @arg @ref LL_RCC_PLLI2SM_DIV_46
lypinator	0:bb348c97df44	5650	* @arg @ref LL_RCC_PLLI2SM_DIV_47
lypinator	0:bb348c97df44	5651	* @arg @ref LL_RCC_PLLI2SM_DIV_48
lypinator	0:bb348c97df44	5652	* @arg @ref LL_RCC_PLLI2SM_DIV_49
lypinator	0:bb348c97df44	5653	* @arg @ref LL_RCC_PLLI2SM_DIV_50
lypinator	0:bb348c97df44	5654	* @arg @ref LL_RCC_PLLI2SM_DIV_51
lypinator	0:bb348c97df44	5655	* @arg @ref LL_RCC_PLLI2SM_DIV_52
lypinator	0:bb348c97df44	5656	* @arg @ref LL_RCC_PLLI2SM_DIV_53
lypinator	0:bb348c97df44	5657	* @arg @ref LL_RCC_PLLI2SM_DIV_54
lypinator	0:bb348c97df44	5658	* @arg @ref LL_RCC_PLLI2SM_DIV_55
lypinator	0:bb348c97df44	5659	* @arg @ref LL_RCC_PLLI2SM_DIV_56
lypinator	0:bb348c97df44	5660	* @arg @ref LL_RCC_PLLI2SM_DIV_57
lypinator	0:bb348c97df44	5661	* @arg @ref LL_RCC_PLLI2SM_DIV_58
lypinator	0:bb348c97df44	5662	* @arg @ref LL_RCC_PLLI2SM_DIV_59
lypinator	0:bb348c97df44	5663	* @arg @ref LL_RCC_PLLI2SM_DIV_60
lypinator	0:bb348c97df44	5664	* @arg @ref LL_RCC_PLLI2SM_DIV_61
lypinator	0:bb348c97df44	5665	* @arg @ref LL_RCC_PLLI2SM_DIV_62
lypinator	0:bb348c97df44	5666	* @arg @ref LL_RCC_PLLI2SM_DIV_63
lypinator	0:bb348c97df44	5667	* @param PLLN Between 50/192(*) and 432
lypinator	0:bb348c97df44	5668	*
lypinator	0:bb348c97df44	5669	* (*) value not defined in all devices.
lypinator	0:bb348c97df44	5670	* @param PLLR This parameter can be one of the following values:
lypinator	0:bb348c97df44	5671	* @arg @ref LL_RCC_PLLI2SR_DIV_2
lypinator	0:bb348c97df44	5672	* @arg @ref LL_RCC_PLLI2SR_DIV_3
lypinator	0:bb348c97df44	5673	* @arg @ref LL_RCC_PLLI2SR_DIV_4
lypinator	0:bb348c97df44	5674	* @arg @ref LL_RCC_PLLI2SR_DIV_5
lypinator	0:bb348c97df44	5675	* @arg @ref LL_RCC_PLLI2SR_DIV_6
lypinator	0:bb348c97df44	5676	* @arg @ref LL_RCC_PLLI2SR_DIV_7
lypinator	0:bb348c97df44	5677	* @retval None
lypinator	0:bb348c97df44	5678	*/
lypinator	0:bb348c97df44	5679	__STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_I2S(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
lypinator	0:bb348c97df44	5680	{
lypinator	0:bb348c97df44	5681	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&RCC->PLLCFGR) + (Source & 0x80U)));
lypinator	0:bb348c97df44	5682	MODIFY_REG(*pReg, RCC_PLLCFGR_PLLSRC, (Source & (~0x80U)));
lypinator	0:bb348c97df44	5683	#if defined(RCC_PLLI2SCFGR_PLLI2SM)
lypinator	0:bb348c97df44	5684	MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM, PLLM);
lypinator	0:bb348c97df44	5685	#else
lypinator	0:bb348c97df44	5686	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM);
lypinator	0:bb348c97df44	5687	#endif /* RCC_PLLI2SCFGR_PLLI2SM */
lypinator	0:bb348c97df44	5688	MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN \| RCC_PLLI2SCFGR_PLLI2SR, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos \| PLLR);
lypinator	0:bb348c97df44	5689	}
lypinator	0:bb348c97df44	5690
lypinator	0:bb348c97df44	5691	/**
lypinator	0:bb348c97df44	5692	* @brief Get I2SPLL multiplication factor for VCO
lypinator	0:bb348c97df44	5693	* @rmtoll PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_GetN
lypinator	0:bb348c97df44	5694	* @retval Between 50/192(*) and 432
lypinator	0:bb348c97df44	5695	*
lypinator	0:bb348c97df44	5696	* (*) value not defined in all devices.
lypinator	0:bb348c97df44	5697	*/
lypinator	0:bb348c97df44	5698	__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetN(void)
lypinator	0:bb348c97df44	5699	{
lypinator	0:bb348c97df44	5700	return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos);
lypinator	0:bb348c97df44	5701	}
lypinator	0:bb348c97df44	5702
lypinator	0:bb348c97df44	5703	#if defined(RCC_PLLI2SCFGR_PLLI2SQ)
lypinator	0:bb348c97df44	5704	/**
lypinator	0:bb348c97df44	5705	* @brief Get I2SPLL division factor for PLLI2SQ
lypinator	0:bb348c97df44	5706	* @rmtoll PLLI2SCFGR PLLI2SQ LL_RCC_PLLI2S_GetQ
lypinator	0:bb348c97df44	5707	* @retval Returned value can be one of the following values:
lypinator	0:bb348c97df44	5708	* @arg @ref LL_RCC_PLLI2SQ_DIV_2
lypinator	0:bb348c97df44	5709	* @arg @ref LL_RCC_PLLI2SQ_DIV_3
lypinator	0:bb348c97df44	5710	* @arg @ref LL_RCC_PLLI2SQ_DIV_4
lypinator	0:bb348c97df44	5711	* @arg @ref LL_RCC_PLLI2SQ_DIV_5
lypinator	0:bb348c97df44	5712	* @arg @ref LL_RCC_PLLI2SQ_DIV_6
lypinator	0:bb348c97df44	5713	* @arg @ref LL_RCC_PLLI2SQ_DIV_7
lypinator	0:bb348c97df44	5714	* @arg @ref LL_RCC_PLLI2SQ_DIV_8
lypinator	0:bb348c97df44	5715	* @arg @ref LL_RCC_PLLI2SQ_DIV_9
lypinator	0:bb348c97df44	5716	* @arg @ref LL_RCC_PLLI2SQ_DIV_10
lypinator	0:bb348c97df44	5717	* @arg @ref LL_RCC_PLLI2SQ_DIV_11
lypinator	0:bb348c97df44	5718	* @arg @ref LL_RCC_PLLI2SQ_DIV_12
lypinator	0:bb348c97df44	5719	* @arg @ref LL_RCC_PLLI2SQ_DIV_13
lypinator	0:bb348c97df44	5720	* @arg @ref LL_RCC_PLLI2SQ_DIV_14
lypinator	0:bb348c97df44	5721	* @arg @ref LL_RCC_PLLI2SQ_DIV_15
lypinator	0:bb348c97df44	5722	*/
lypinator	0:bb348c97df44	5723	__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetQ(void)
lypinator	0:bb348c97df44	5724	{
lypinator	0:bb348c97df44	5725	return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SQ));
lypinator	0:bb348c97df44	5726	}
lypinator	0:bb348c97df44	5727	#endif /* RCC_PLLI2SCFGR_PLLI2SQ */
lypinator	0:bb348c97df44	5728
lypinator	0:bb348c97df44	5729	/**
lypinator	0:bb348c97df44	5730	* @brief Get I2SPLL division factor for PLLI2SR
lypinator	0:bb348c97df44	5731	* @note used for PLLI2SCLK (I2S clock)
lypinator	0:bb348c97df44	5732	* @rmtoll PLLI2SCFGR PLLI2SR LL_RCC_PLLI2S_GetR
lypinator	0:bb348c97df44	5733	* @retval Returned value can be one of the following values:
lypinator	0:bb348c97df44	5734	* @arg @ref LL_RCC_PLLI2SR_DIV_2
lypinator	0:bb348c97df44	5735	* @arg @ref LL_RCC_PLLI2SR_DIV_3
lypinator	0:bb348c97df44	5736	* @arg @ref LL_RCC_PLLI2SR_DIV_4
lypinator	0:bb348c97df44	5737	* @arg @ref LL_RCC_PLLI2SR_DIV_5
lypinator	0:bb348c97df44	5738	* @arg @ref LL_RCC_PLLI2SR_DIV_6
lypinator	0:bb348c97df44	5739	* @arg @ref LL_RCC_PLLI2SR_DIV_7
lypinator	0:bb348c97df44	5740	*/
lypinator	0:bb348c97df44	5741	__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetR(void)
lypinator	0:bb348c97df44	5742	{
lypinator	0:bb348c97df44	5743	return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SR));
lypinator	0:bb348c97df44	5744	}
lypinator	0:bb348c97df44	5745
lypinator	0:bb348c97df44	5746	#if defined(RCC_PLLI2SCFGR_PLLI2SP)
lypinator	0:bb348c97df44	5747	/**
lypinator	0:bb348c97df44	5748	* @brief Get I2SPLL division factor for PLLI2SP
lypinator	0:bb348c97df44	5749	* @note used for PLLSPDIFRXCLK (SPDIFRX clock)
lypinator	0:bb348c97df44	5750	* @rmtoll PLLI2SCFGR PLLI2SP LL_RCC_PLLI2S_GetP
lypinator	0:bb348c97df44	5751	* @retval Returned value can be one of the following values:
lypinator	0:bb348c97df44	5752	* @arg @ref LL_RCC_PLLI2SP_DIV_2
lypinator	0:bb348c97df44	5753	* @arg @ref LL_RCC_PLLI2SP_DIV_4
lypinator	0:bb348c97df44	5754	* @arg @ref LL_RCC_PLLI2SP_DIV_6
lypinator	0:bb348c97df44	5755	* @arg @ref LL_RCC_PLLI2SP_DIV_8
lypinator	0:bb348c97df44	5756	*/
lypinator	0:bb348c97df44	5757	__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetP(void)
lypinator	0:bb348c97df44	5758	{
lypinator	0:bb348c97df44	5759	return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SP));
lypinator	0:bb348c97df44	5760	}
lypinator	0:bb348c97df44	5761	#endif /* RCC_PLLI2SCFGR_PLLI2SP */
lypinator	0:bb348c97df44	5762
lypinator	0:bb348c97df44	5763	#if defined(RCC_DCKCFGR_PLLI2SDIVQ)
lypinator	0:bb348c97df44	5764	/**
lypinator	0:bb348c97df44	5765	* @brief Get I2SPLL division factor for PLLI2SDIVQ
lypinator	0:bb348c97df44	5766	* @note used PLLSAICLK selected (SAI clock)
lypinator	0:bb348c97df44	5767	* @rmtoll DCKCFGR PLLI2SDIVQ LL_RCC_PLLI2S_GetDIVQ
lypinator	0:bb348c97df44	5768	* @retval Returned value can be one of the following values:
lypinator	0:bb348c97df44	5769	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_1
lypinator	0:bb348c97df44	5770	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_2
lypinator	0:bb348c97df44	5771	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_3
lypinator	0:bb348c97df44	5772	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_4
lypinator	0:bb348c97df44	5773	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_5
lypinator	0:bb348c97df44	5774	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_6
lypinator	0:bb348c97df44	5775	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_7
lypinator	0:bb348c97df44	5776	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_8
lypinator	0:bb348c97df44	5777	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_9
lypinator	0:bb348c97df44	5778	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_10
lypinator	0:bb348c97df44	5779	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_11
lypinator	0:bb348c97df44	5780	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_12
lypinator	0:bb348c97df44	5781	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_13
lypinator	0:bb348c97df44	5782	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_14
lypinator	0:bb348c97df44	5783	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_15
lypinator	0:bb348c97df44	5784	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_16
lypinator	0:bb348c97df44	5785	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_17
lypinator	0:bb348c97df44	5786	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_18
lypinator	0:bb348c97df44	5787	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_19
lypinator	0:bb348c97df44	5788	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_20
lypinator	0:bb348c97df44	5789	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_21
lypinator	0:bb348c97df44	5790	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_22
lypinator	0:bb348c97df44	5791	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_23
lypinator	0:bb348c97df44	5792	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_24
lypinator	0:bb348c97df44	5793	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_25
lypinator	0:bb348c97df44	5794	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_26
lypinator	0:bb348c97df44	5795	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_27
lypinator	0:bb348c97df44	5796	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_28
lypinator	0:bb348c97df44	5797	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_29
lypinator	0:bb348c97df44	5798	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_30
lypinator	0:bb348c97df44	5799	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_31
lypinator	0:bb348c97df44	5800	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_32
lypinator	0:bb348c97df44	5801	*/
lypinator	0:bb348c97df44	5802	__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetDIVQ(void)
lypinator	0:bb348c97df44	5803	{
lypinator	0:bb348c97df44	5804	return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVQ));
lypinator	0:bb348c97df44	5805	}
lypinator	0:bb348c97df44	5806	#endif /* RCC_DCKCFGR_PLLI2SDIVQ */
lypinator	0:bb348c97df44	5807
lypinator	0:bb348c97df44	5808	#if defined(RCC_DCKCFGR_PLLI2SDIVR)
lypinator	0:bb348c97df44	5809	/**
lypinator	0:bb348c97df44	5810	* @brief Get I2SPLL division factor for PLLI2SDIVR
lypinator	0:bb348c97df44	5811	* @note used PLLSAICLK selected (SAI clock)
lypinator	0:bb348c97df44	5812	* @rmtoll DCKCFGR PLLI2SDIVR LL_RCC_PLLI2S_GetDIVR
lypinator	0:bb348c97df44	5813	* @retval Returned value can be one of the following values:
lypinator	0:bb348c97df44	5814	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_1
lypinator	0:bb348c97df44	5815	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_2
lypinator	0:bb348c97df44	5816	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_3
lypinator	0:bb348c97df44	5817	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_4
lypinator	0:bb348c97df44	5818	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_5
lypinator	0:bb348c97df44	5819	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_6
lypinator	0:bb348c97df44	5820	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_7
lypinator	0:bb348c97df44	5821	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_8
lypinator	0:bb348c97df44	5822	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_9
lypinator	0:bb348c97df44	5823	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_10
lypinator	0:bb348c97df44	5824	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_11
lypinator	0:bb348c97df44	5825	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_12
lypinator	0:bb348c97df44	5826	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_13
lypinator	0:bb348c97df44	5827	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_14
lypinator	0:bb348c97df44	5828	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_15
lypinator	0:bb348c97df44	5829	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_16
lypinator	0:bb348c97df44	5830	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_17
lypinator	0:bb348c97df44	5831	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_18
lypinator	0:bb348c97df44	5832	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_19
lypinator	0:bb348c97df44	5833	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_20
lypinator	0:bb348c97df44	5834	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_21
lypinator	0:bb348c97df44	5835	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_22
lypinator	0:bb348c97df44	5836	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_23
lypinator	0:bb348c97df44	5837	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_24
lypinator	0:bb348c97df44	5838	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_25
lypinator	0:bb348c97df44	5839	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_26
lypinator	0:bb348c97df44	5840	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_27
lypinator	0:bb348c97df44	5841	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_28
lypinator	0:bb348c97df44	5842	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_29
lypinator	0:bb348c97df44	5843	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_30
lypinator	0:bb348c97df44	5844	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_31
lypinator	0:bb348c97df44	5845	*/
lypinator	0:bb348c97df44	5846	__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetDIVR(void)
lypinator	0:bb348c97df44	5847	{
lypinator	0:bb348c97df44	5848	return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVR));
lypinator	0:bb348c97df44	5849	}
lypinator	0:bb348c97df44	5850	#endif /* RCC_DCKCFGR_PLLI2SDIVR */
lypinator	0:bb348c97df44	5851
lypinator	0:bb348c97df44	5852	/**
lypinator	0:bb348c97df44	5853	* @brief Get division factor for PLLI2S input clock
lypinator	0:bb348c97df44	5854	* @rmtoll PLLCFGR PLLM LL_RCC_PLLI2S_GetDivider\n
lypinator	0:bb348c97df44	5855	* PLLI2SCFGR PLLI2SM LL_RCC_PLLI2S_GetDivider
lypinator	0:bb348c97df44	5856	* @retval Returned value can be one of the following values:
lypinator	0:bb348c97df44	5857	* @arg @ref LL_RCC_PLLI2SM_DIV_2
lypinator	0:bb348c97df44	5858	* @arg @ref LL_RCC_PLLI2SM_DIV_3
lypinator	0:bb348c97df44	5859	* @arg @ref LL_RCC_PLLI2SM_DIV_4
lypinator	0:bb348c97df44	5860	* @arg @ref LL_RCC_PLLI2SM_DIV_5
lypinator	0:bb348c97df44	5861	* @arg @ref LL_RCC_PLLI2SM_DIV_6
lypinator	0:bb348c97df44	5862	* @arg @ref LL_RCC_PLLI2SM_DIV_7
lypinator	0:bb348c97df44	5863	* @arg @ref LL_RCC_PLLI2SM_DIV_8
lypinator	0:bb348c97df44	5864	* @arg @ref LL_RCC_PLLI2SM_DIV_9
lypinator	0:bb348c97df44	5865	* @arg @ref LL_RCC_PLLI2SM_DIV_10
lypinator	0:bb348c97df44	5866	* @arg @ref LL_RCC_PLLI2SM_DIV_11
lypinator	0:bb348c97df44	5867	* @arg @ref LL_RCC_PLLI2SM_DIV_12
lypinator	0:bb348c97df44	5868	* @arg @ref LL_RCC_PLLI2SM_DIV_13
lypinator	0:bb348c97df44	5869	* @arg @ref LL_RCC_PLLI2SM_DIV_14
lypinator	0:bb348c97df44	5870	* @arg @ref LL_RCC_PLLI2SM_DIV_15
lypinator	0:bb348c97df44	5871	* @arg @ref LL_RCC_PLLI2SM_DIV_16
lypinator	0:bb348c97df44	5872	* @arg @ref LL_RCC_PLLI2SM_DIV_17
lypinator	0:bb348c97df44	5873	* @arg @ref LL_RCC_PLLI2SM_DIV_18
lypinator	0:bb348c97df44	5874	* @arg @ref LL_RCC_PLLI2SM_DIV_19
lypinator	0:bb348c97df44	5875	* @arg @ref LL_RCC_PLLI2SM_DIV_20
lypinator	0:bb348c97df44	5876	* @arg @ref LL_RCC_PLLI2SM_DIV_21
lypinator	0:bb348c97df44	5877	* @arg @ref LL_RCC_PLLI2SM_DIV_22
lypinator	0:bb348c97df44	5878	* @arg @ref LL_RCC_PLLI2SM_DIV_23
lypinator	0:bb348c97df44	5879	* @arg @ref LL_RCC_PLLI2SM_DIV_24
lypinator	0:bb348c97df44	5880	* @arg @ref LL_RCC_PLLI2SM_DIV_25
lypinator	0:bb348c97df44	5881	* @arg @ref LL_RCC_PLLI2SM_DIV_26
lypinator	0:bb348c97df44	5882	* @arg @ref LL_RCC_PLLI2SM_DIV_27
lypinator	0:bb348c97df44	5883	* @arg @ref LL_RCC_PLLI2SM_DIV_28
lypinator	0:bb348c97df44	5884	* @arg @ref LL_RCC_PLLI2SM_DIV_29
lypinator	0:bb348c97df44	5885	* @arg @ref LL_RCC_PLLI2SM_DIV_30
lypinator	0:bb348c97df44	5886	* @arg @ref LL_RCC_PLLI2SM_DIV_31
lypinator	0:bb348c97df44	5887	* @arg @ref LL_RCC_PLLI2SM_DIV_32
lypinator	0:bb348c97df44	5888	* @arg @ref LL_RCC_PLLI2SM_DIV_33
lypinator	0:bb348c97df44	5889	* @arg @ref LL_RCC_PLLI2SM_DIV_34
lypinator	0:bb348c97df44	5890	* @arg @ref LL_RCC_PLLI2SM_DIV_35
lypinator	0:bb348c97df44	5891	* @arg @ref LL_RCC_PLLI2SM_DIV_36
lypinator	0:bb348c97df44	5892	* @arg @ref LL_RCC_PLLI2SM_DIV_37
lypinator	0:bb348c97df44	5893	* @arg @ref LL_RCC_PLLI2SM_DIV_38
lypinator	0:bb348c97df44	5894	* @arg @ref LL_RCC_PLLI2SM_DIV_39
lypinator	0:bb348c97df44	5895	* @arg @ref LL_RCC_PLLI2SM_DIV_40
lypinator	0:bb348c97df44	5896	* @arg @ref LL_RCC_PLLI2SM_DIV_41
lypinator	0:bb348c97df44	5897	* @arg @ref LL_RCC_PLLI2SM_DIV_42
lypinator	0:bb348c97df44	5898	* @arg @ref LL_RCC_PLLI2SM_DIV_43
lypinator	0:bb348c97df44	5899	* @arg @ref LL_RCC_PLLI2SM_DIV_44
lypinator	0:bb348c97df44	5900	* @arg @ref LL_RCC_PLLI2SM_DIV_45
lypinator	0:bb348c97df44	5901	* @arg @ref LL_RCC_PLLI2SM_DIV_46
lypinator	0:bb348c97df44	5902	* @arg @ref LL_RCC_PLLI2SM_DIV_47
lypinator	0:bb348c97df44	5903	* @arg @ref LL_RCC_PLLI2SM_DIV_48
lypinator	0:bb348c97df44	5904	* @arg @ref LL_RCC_PLLI2SM_DIV_49
lypinator	0:bb348c97df44	5905	* @arg @ref LL_RCC_PLLI2SM_DIV_50
lypinator	0:bb348c97df44	5906	* @arg @ref LL_RCC_PLLI2SM_DIV_51
lypinator	0:bb348c97df44	5907	* @arg @ref LL_RCC_PLLI2SM_DIV_52
lypinator	0:bb348c97df44	5908	* @arg @ref LL_RCC_PLLI2SM_DIV_53
lypinator	0:bb348c97df44	5909	* @arg @ref LL_RCC_PLLI2SM_DIV_54
lypinator	0:bb348c97df44	5910	* @arg @ref LL_RCC_PLLI2SM_DIV_55
lypinator	0:bb348c97df44	5911	* @arg @ref LL_RCC_PLLI2SM_DIV_56
lypinator	0:bb348c97df44	5912	* @arg @ref LL_RCC_PLLI2SM_DIV_57
lypinator	0:bb348c97df44	5913	* @arg @ref LL_RCC_PLLI2SM_DIV_58
lypinator	0:bb348c97df44	5914	* @arg @ref LL_RCC_PLLI2SM_DIV_59
lypinator	0:bb348c97df44	5915	* @arg @ref LL_RCC_PLLI2SM_DIV_60
lypinator	0:bb348c97df44	5916	* @arg @ref LL_RCC_PLLI2SM_DIV_61
lypinator	0:bb348c97df44	5917	* @arg @ref LL_RCC_PLLI2SM_DIV_62
lypinator	0:bb348c97df44	5918	* @arg @ref LL_RCC_PLLI2SM_DIV_63
lypinator	0:bb348c97df44	5919	*/
lypinator	0:bb348c97df44	5920	__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetDivider(void)
lypinator	0:bb348c97df44	5921	{
lypinator	0:bb348c97df44	5922	#if defined(RCC_PLLI2SCFGR_PLLI2SM)
lypinator	0:bb348c97df44	5923	return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM));
lypinator	0:bb348c97df44	5924	#else
lypinator	0:bb348c97df44	5925	return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM));
lypinator	0:bb348c97df44	5926	#endif /* RCC_PLLI2SCFGR_PLLI2SM */
lypinator	0:bb348c97df44	5927	}
lypinator	0:bb348c97df44	5928
lypinator	0:bb348c97df44	5929	/**
lypinator	0:bb348c97df44	5930	* @brief Get the oscillator used as PLL clock source.
lypinator	0:bb348c97df44	5931	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_GetMainSource\n
lypinator	0:bb348c97df44	5932	* PLLI2SCFGR PLLI2SSRC LL_RCC_PLLI2S_GetMainSource
lypinator	0:bb348c97df44	5933	* @retval Returned value can be one of the following values:
lypinator	0:bb348c97df44	5934	* @arg @ref LL_RCC_PLLSOURCE_HSI
lypinator	0:bb348c97df44	5935	* @arg @ref LL_RCC_PLLSOURCE_HSE
lypinator	0:bb348c97df44	5936	* @arg @ref LL_RCC_PLLI2SSOURCE_PIN (*)
lypinator	0:bb348c97df44	5937	*
lypinator	0:bb348c97df44	5938	* (*) value not defined in all devices.
lypinator	0:bb348c97df44	5939	*/
lypinator	0:bb348c97df44	5940	__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetMainSource(void)
lypinator	0:bb348c97df44	5941	{
lypinator	0:bb348c97df44	5942	#if defined(RCC_PLLI2SCFGR_PLLI2SSRC)
lypinator	0:bb348c97df44	5943	register uint32_t pllsrc = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC);
lypinator	0:bb348c97df44	5944	register uint32_t plli2sssrc0 = READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SSRC);
lypinator	0:bb348c97df44	5945	register uint32_t plli2sssrc1 = READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SSRC) >> 15U;
lypinator	0:bb348c97df44	5946	return (uint32_t)(pllsrc \| plli2sssrc0 \| plli2sssrc1);
lypinator	0:bb348c97df44	5947	#else
lypinator	0:bb348c97df44	5948	return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC));
lypinator	0:bb348c97df44	5949	#endif /* RCC_PLLI2SCFGR_PLLI2SSRC */
lypinator	0:bb348c97df44	5950	}
lypinator	0:bb348c97df44	5951
lypinator	0:bb348c97df44	5952	/**
lypinator	0:bb348c97df44	5953	* @}
lypinator	0:bb348c97df44	5954	*/
lypinator	0:bb348c97df44	5955	#endif /* RCC_PLLI2S_SUPPORT */
lypinator	0:bb348c97df44	5956
lypinator	0:bb348c97df44	5957	#if defined(RCC_PLLSAI_SUPPORT)
lypinator	0:bb348c97df44	5958	/** @defgroup RCC_LL_EF_PLLSAI PLLSAI
lypinator	0:bb348c97df44	5959	* @{
lypinator	0:bb348c97df44	5960	*/
lypinator	0:bb348c97df44	5961
lypinator	0:bb348c97df44	5962	/**
lypinator	0:bb348c97df44	5963	* @brief Enable PLLSAI
lypinator	0:bb348c97df44	5964	* @rmtoll CR PLLSAION LL_RCC_PLLSAI_Enable
lypinator	0:bb348c97df44	5965	* @retval None
lypinator	0:bb348c97df44	5966	*/
lypinator	0:bb348c97df44	5967	__STATIC_INLINE void LL_RCC_PLLSAI_Enable(void)
lypinator	0:bb348c97df44	5968	{
lypinator	0:bb348c97df44	5969	SET_BIT(RCC->CR, RCC_CR_PLLSAION);
lypinator	0:bb348c97df44	5970	}
lypinator	0:bb348c97df44	5971
lypinator	0:bb348c97df44	5972	/**
lypinator	0:bb348c97df44	5973	* @brief Disable PLLSAI
lypinator	0:bb348c97df44	5974	* @rmtoll CR PLLSAION LL_RCC_PLLSAI_Disable
lypinator	0:bb348c97df44	5975	* @retval None
lypinator	0:bb348c97df44	5976	*/
lypinator	0:bb348c97df44	5977	__STATIC_INLINE void LL_RCC_PLLSAI_Disable(void)
lypinator	0:bb348c97df44	5978	{
lypinator	0:bb348c97df44	5979	CLEAR_BIT(RCC->CR, RCC_CR_PLLSAION);
lypinator	0:bb348c97df44	5980	}
lypinator	0:bb348c97df44	5981
lypinator	0:bb348c97df44	5982	/**
lypinator	0:bb348c97df44	5983	* @brief Check if PLLSAI Ready
lypinator	0:bb348c97df44	5984	* @rmtoll CR PLLSAIRDY LL_RCC_PLLSAI_IsReady
lypinator	0:bb348c97df44	5985	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	5986	*/
lypinator	0:bb348c97df44	5987	__STATIC_INLINE uint32_t LL_RCC_PLLSAI_IsReady(void)
lypinator	0:bb348c97df44	5988	{
lypinator	0:bb348c97df44	5989	return (READ_BIT(RCC->CR, RCC_CR_PLLSAIRDY) == (RCC_CR_PLLSAIRDY));
lypinator	0:bb348c97df44	5990	}
lypinator	0:bb348c97df44	5991
lypinator	0:bb348c97df44	5992	/**
lypinator	0:bb348c97df44	5993	* @brief Configure PLLSAI used for SAI domain clock
lypinator	0:bb348c97df44	5994	* @note PLL Source and PLLM Divider can be written only when PLL,
lypinator	0:bb348c97df44	5995	* PLLI2S and PLLSAI(*) are disabled
lypinator	0:bb348c97df44	5996	* @note PLLN/PLLQ can be written only when PLLSAI is disabled
lypinator	0:bb348c97df44	5997	* @note This can be selected for SAI
lypinator	0:bb348c97df44	5998	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI_ConfigDomain_SAI\n
lypinator	0:bb348c97df44	5999	* PLLCFGR PLLM LL_RCC_PLLSAI_ConfigDomain_SAI\n
lypinator	0:bb348c97df44	6000	* PLLSAICFGR PLLSAIM LL_RCC_PLLSAI_ConfigDomain_SAI\n
lypinator	0:bb348c97df44	6001	* PLLSAICFGR PLLSAIN LL_RCC_PLLSAI_ConfigDomain_SAI\n
lypinator	0:bb348c97df44	6002	* PLLSAICFGR PLLSAIQ LL_RCC_PLLSAI_ConfigDomain_SAI\n
lypinator	0:bb348c97df44	6003	* DCKCFGR PLLSAIDIVQ LL_RCC_PLLSAI_ConfigDomain_SAI
lypinator	0:bb348c97df44	6004	* @param Source This parameter can be one of the following values:
lypinator	0:bb348c97df44	6005	* @arg @ref LL_RCC_PLLSOURCE_HSI
lypinator	0:bb348c97df44	6006	* @arg @ref LL_RCC_PLLSOURCE_HSE
lypinator	0:bb348c97df44	6007	* @param PLLM This parameter can be one of the following values:
lypinator	0:bb348c97df44	6008	* @arg @ref LL_RCC_PLLSAIM_DIV_2
lypinator	0:bb348c97df44	6009	* @arg @ref LL_RCC_PLLSAIM_DIV_3
lypinator	0:bb348c97df44	6010	* @arg @ref LL_RCC_PLLSAIM_DIV_4
lypinator	0:bb348c97df44	6011	* @arg @ref LL_RCC_PLLSAIM_DIV_5
lypinator	0:bb348c97df44	6012	* @arg @ref LL_RCC_PLLSAIM_DIV_6
lypinator	0:bb348c97df44	6013	* @arg @ref LL_RCC_PLLSAIM_DIV_7
lypinator	0:bb348c97df44	6014	* @arg @ref LL_RCC_PLLSAIM_DIV_8
lypinator	0:bb348c97df44	6015	* @arg @ref LL_RCC_PLLSAIM_DIV_9
lypinator	0:bb348c97df44	6016	* @arg @ref LL_RCC_PLLSAIM_DIV_10
lypinator	0:bb348c97df44	6017	* @arg @ref LL_RCC_PLLSAIM_DIV_11
lypinator	0:bb348c97df44	6018	* @arg @ref LL_RCC_PLLSAIM_DIV_12
lypinator	0:bb348c97df44	6019	* @arg @ref LL_RCC_PLLSAIM_DIV_13
lypinator	0:bb348c97df44	6020	* @arg @ref LL_RCC_PLLSAIM_DIV_14
lypinator	0:bb348c97df44	6021	* @arg @ref LL_RCC_PLLSAIM_DIV_15
lypinator	0:bb348c97df44	6022	* @arg @ref LL_RCC_PLLSAIM_DIV_16
lypinator	0:bb348c97df44	6023	* @arg @ref LL_RCC_PLLSAIM_DIV_17
lypinator	0:bb348c97df44	6024	* @arg @ref LL_RCC_PLLSAIM_DIV_18
lypinator	0:bb348c97df44	6025	* @arg @ref LL_RCC_PLLSAIM_DIV_19
lypinator	0:bb348c97df44	6026	* @arg @ref LL_RCC_PLLSAIM_DIV_20
lypinator	0:bb348c97df44	6027	* @arg @ref LL_RCC_PLLSAIM_DIV_21
lypinator	0:bb348c97df44	6028	* @arg @ref LL_RCC_PLLSAIM_DIV_22
lypinator	0:bb348c97df44	6029	* @arg @ref LL_RCC_PLLSAIM_DIV_23
lypinator	0:bb348c97df44	6030	* @arg @ref LL_RCC_PLLSAIM_DIV_24
lypinator	0:bb348c97df44	6031	* @arg @ref LL_RCC_PLLSAIM_DIV_25
lypinator	0:bb348c97df44	6032	* @arg @ref LL_RCC_PLLSAIM_DIV_26
lypinator	0:bb348c97df44	6033	* @arg @ref LL_RCC_PLLSAIM_DIV_27
lypinator	0:bb348c97df44	6034	* @arg @ref LL_RCC_PLLSAIM_DIV_28
lypinator	0:bb348c97df44	6035	* @arg @ref LL_RCC_PLLSAIM_DIV_29
lypinator	0:bb348c97df44	6036	* @arg @ref LL_RCC_PLLSAIM_DIV_30
lypinator	0:bb348c97df44	6037	* @arg @ref LL_RCC_PLLSAIM_DIV_31
lypinator	0:bb348c97df44	6038	* @arg @ref LL_RCC_PLLSAIM_DIV_32
lypinator	0:bb348c97df44	6039	* @arg @ref LL_RCC_PLLSAIM_DIV_33
lypinator	0:bb348c97df44	6040	* @arg @ref LL_RCC_PLLSAIM_DIV_34
lypinator	0:bb348c97df44	6041	* @arg @ref LL_RCC_PLLSAIM_DIV_35
lypinator	0:bb348c97df44	6042	* @arg @ref LL_RCC_PLLSAIM_DIV_36
lypinator	0:bb348c97df44	6043	* @arg @ref LL_RCC_PLLSAIM_DIV_37
lypinator	0:bb348c97df44	6044	* @arg @ref LL_RCC_PLLSAIM_DIV_38
lypinator	0:bb348c97df44	6045	* @arg @ref LL_RCC_PLLSAIM_DIV_39
lypinator	0:bb348c97df44	6046	* @arg @ref LL_RCC_PLLSAIM_DIV_40
lypinator	0:bb348c97df44	6047	* @arg @ref LL_RCC_PLLSAIM_DIV_41
lypinator	0:bb348c97df44	6048	* @arg @ref LL_RCC_PLLSAIM_DIV_42
lypinator	0:bb348c97df44	6049	* @arg @ref LL_RCC_PLLSAIM_DIV_43
lypinator	0:bb348c97df44	6050	* @arg @ref LL_RCC_PLLSAIM_DIV_44
lypinator	0:bb348c97df44	6051	* @arg @ref LL_RCC_PLLSAIM_DIV_45
lypinator	0:bb348c97df44	6052	* @arg @ref LL_RCC_PLLSAIM_DIV_46
lypinator	0:bb348c97df44	6053	* @arg @ref LL_RCC_PLLSAIM_DIV_47
lypinator	0:bb348c97df44	6054	* @arg @ref LL_RCC_PLLSAIM_DIV_48
lypinator	0:bb348c97df44	6055	* @arg @ref LL_RCC_PLLSAIM_DIV_49
lypinator	0:bb348c97df44	6056	* @arg @ref LL_RCC_PLLSAIM_DIV_50
lypinator	0:bb348c97df44	6057	* @arg @ref LL_RCC_PLLSAIM_DIV_51
lypinator	0:bb348c97df44	6058	* @arg @ref LL_RCC_PLLSAIM_DIV_52
lypinator	0:bb348c97df44	6059	* @arg @ref LL_RCC_PLLSAIM_DIV_53
lypinator	0:bb348c97df44	6060	* @arg @ref LL_RCC_PLLSAIM_DIV_54
lypinator	0:bb348c97df44	6061	* @arg @ref LL_RCC_PLLSAIM_DIV_55
lypinator	0:bb348c97df44	6062	* @arg @ref LL_RCC_PLLSAIM_DIV_56
lypinator	0:bb348c97df44	6063	* @arg @ref LL_RCC_PLLSAIM_DIV_57
lypinator	0:bb348c97df44	6064	* @arg @ref LL_RCC_PLLSAIM_DIV_58
lypinator	0:bb348c97df44	6065	* @arg @ref LL_RCC_PLLSAIM_DIV_59
lypinator	0:bb348c97df44	6066	* @arg @ref LL_RCC_PLLSAIM_DIV_60
lypinator	0:bb348c97df44	6067	* @arg @ref LL_RCC_PLLSAIM_DIV_61
lypinator	0:bb348c97df44	6068	* @arg @ref LL_RCC_PLLSAIM_DIV_62
lypinator	0:bb348c97df44	6069	* @arg @ref LL_RCC_PLLSAIM_DIV_63
lypinator	0:bb348c97df44	6070	* @param PLLN Between 49/50(*) and 432
lypinator	0:bb348c97df44	6071	*
lypinator	0:bb348c97df44	6072	* (*) value not defined in all devices.
lypinator	0:bb348c97df44	6073	* @param PLLQ This parameter can be one of the following values:
lypinator	0:bb348c97df44	6074	* @arg @ref LL_RCC_PLLSAIQ_DIV_2
lypinator	0:bb348c97df44	6075	* @arg @ref LL_RCC_PLLSAIQ_DIV_3
lypinator	0:bb348c97df44	6076	* @arg @ref LL_RCC_PLLSAIQ_DIV_4
lypinator	0:bb348c97df44	6077	* @arg @ref LL_RCC_PLLSAIQ_DIV_5
lypinator	0:bb348c97df44	6078	* @arg @ref LL_RCC_PLLSAIQ_DIV_6
lypinator	0:bb348c97df44	6079	* @arg @ref LL_RCC_PLLSAIQ_DIV_7
lypinator	0:bb348c97df44	6080	* @arg @ref LL_RCC_PLLSAIQ_DIV_8
lypinator	0:bb348c97df44	6081	* @arg @ref LL_RCC_PLLSAIQ_DIV_9
lypinator	0:bb348c97df44	6082	* @arg @ref LL_RCC_PLLSAIQ_DIV_10
lypinator	0:bb348c97df44	6083	* @arg @ref LL_RCC_PLLSAIQ_DIV_11
lypinator	0:bb348c97df44	6084	* @arg @ref LL_RCC_PLLSAIQ_DIV_12
lypinator	0:bb348c97df44	6085	* @arg @ref LL_RCC_PLLSAIQ_DIV_13
lypinator	0:bb348c97df44	6086	* @arg @ref LL_RCC_PLLSAIQ_DIV_14
lypinator	0:bb348c97df44	6087	* @arg @ref LL_RCC_PLLSAIQ_DIV_15
lypinator	0:bb348c97df44	6088	* @param PLLDIVQ This parameter can be one of the following values:
lypinator	0:bb348c97df44	6089	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_1
lypinator	0:bb348c97df44	6090	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_2
lypinator	0:bb348c97df44	6091	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_3
lypinator	0:bb348c97df44	6092	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_4
lypinator	0:bb348c97df44	6093	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_5
lypinator	0:bb348c97df44	6094	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_6
lypinator	0:bb348c97df44	6095	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_7
lypinator	0:bb348c97df44	6096	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_8
lypinator	0:bb348c97df44	6097	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_9
lypinator	0:bb348c97df44	6098	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_10
lypinator	0:bb348c97df44	6099	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_11
lypinator	0:bb348c97df44	6100	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_12
lypinator	0:bb348c97df44	6101	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_13
lypinator	0:bb348c97df44	6102	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_14
lypinator	0:bb348c97df44	6103	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_15
lypinator	0:bb348c97df44	6104	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_16
lypinator	0:bb348c97df44	6105	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_17
lypinator	0:bb348c97df44	6106	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_18
lypinator	0:bb348c97df44	6107	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_19
lypinator	0:bb348c97df44	6108	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_20
lypinator	0:bb348c97df44	6109	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_21
lypinator	0:bb348c97df44	6110	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_22
lypinator	0:bb348c97df44	6111	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_23
lypinator	0:bb348c97df44	6112	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_24
lypinator	0:bb348c97df44	6113	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_25
lypinator	0:bb348c97df44	6114	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_26
lypinator	0:bb348c97df44	6115	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_27
lypinator	0:bb348c97df44	6116	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_28
lypinator	0:bb348c97df44	6117	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_29
lypinator	0:bb348c97df44	6118	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_30
lypinator	0:bb348c97df44	6119	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_31
lypinator	0:bb348c97df44	6120	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_32
lypinator	0:bb348c97df44	6121	* @retval None
lypinator	0:bb348c97df44	6122	*/
lypinator	0:bb348c97df44	6123	__STATIC_INLINE void LL_RCC_PLLSAI_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ, uint32_t PLLDIVQ)
lypinator	0:bb348c97df44	6124	{
lypinator	0:bb348c97df44	6125	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source);
lypinator	0:bb348c97df44	6126	#if defined(RCC_PLLSAICFGR_PLLSAIM)
lypinator	0:bb348c97df44	6127	MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIM, PLLM);
lypinator	0:bb348c97df44	6128	#else
lypinator	0:bb348c97df44	6129	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM);
lypinator	0:bb348c97df44	6130	#endif /* RCC_PLLSAICFGR_PLLSAIM */
lypinator	0:bb348c97df44	6131	MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN \| RCC_PLLSAICFGR_PLLSAIQ, PLLN << RCC_PLLSAICFGR_PLLSAIN_Pos \| PLLQ);
lypinator	0:bb348c97df44	6132	MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVQ, PLLDIVQ);
lypinator	0:bb348c97df44	6133	}
lypinator	0:bb348c97df44	6134
lypinator	0:bb348c97df44	6135	#if defined(RCC_PLLSAICFGR_PLLSAIP)
lypinator	0:bb348c97df44	6136	/**
lypinator	0:bb348c97df44	6137	* @brief Configure PLLSAI used for 48Mhz domain clock
lypinator	0:bb348c97df44	6138	* @note PLL Source and PLLM Divider can be written only when PLL,
lypinator	0:bb348c97df44	6139	* PLLI2S and PLLSAI(*) are disabled
lypinator	0:bb348c97df44	6140	* @note PLLN/PLLP can be written only when PLLSAI is disabled
lypinator	0:bb348c97df44	6141	* @note This can be selected for USB, RNG, SDIO
lypinator	0:bb348c97df44	6142	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI_ConfigDomain_48M\n
lypinator	0:bb348c97df44	6143	* PLLCFGR PLLM LL_RCC_PLLSAI_ConfigDomain_48M\n
lypinator	0:bb348c97df44	6144	* PLLSAICFGR PLLSAIM LL_RCC_PLLSAI_ConfigDomain_48M\n
lypinator	0:bb348c97df44	6145	* PLLSAICFGR PLLSAIN LL_RCC_PLLSAI_ConfigDomain_48M\n
lypinator	0:bb348c97df44	6146	* PLLSAICFGR PLLSAIP LL_RCC_PLLSAI_ConfigDomain_48M
lypinator	0:bb348c97df44	6147	* @param Source This parameter can be one of the following values:
lypinator	0:bb348c97df44	6148	* @arg @ref LL_RCC_PLLSOURCE_HSI
lypinator	0:bb348c97df44	6149	* @arg @ref LL_RCC_PLLSOURCE_HSE
lypinator	0:bb348c97df44	6150	* @param PLLM This parameter can be one of the following values:
lypinator	0:bb348c97df44	6151	* @arg @ref LL_RCC_PLLSAIM_DIV_2
lypinator	0:bb348c97df44	6152	* @arg @ref LL_RCC_PLLSAIM_DIV_3
lypinator	0:bb348c97df44	6153	* @arg @ref LL_RCC_PLLSAIM_DIV_4
lypinator	0:bb348c97df44	6154	* @arg @ref LL_RCC_PLLSAIM_DIV_5
lypinator	0:bb348c97df44	6155	* @arg @ref LL_RCC_PLLSAIM_DIV_6
lypinator	0:bb348c97df44	6156	* @arg @ref LL_RCC_PLLSAIM_DIV_7
lypinator	0:bb348c97df44	6157	* @arg @ref LL_RCC_PLLSAIM_DIV_8
lypinator	0:bb348c97df44	6158	* @arg @ref LL_RCC_PLLSAIM_DIV_9
lypinator	0:bb348c97df44	6159	* @arg @ref LL_RCC_PLLSAIM_DIV_10
lypinator	0:bb348c97df44	6160	* @arg @ref LL_RCC_PLLSAIM_DIV_11
lypinator	0:bb348c97df44	6161	* @arg @ref LL_RCC_PLLSAIM_DIV_12
lypinator	0:bb348c97df44	6162	* @arg @ref LL_RCC_PLLSAIM_DIV_13
lypinator	0:bb348c97df44	6163	* @arg @ref LL_RCC_PLLSAIM_DIV_14
lypinator	0:bb348c97df44	6164	* @arg @ref LL_RCC_PLLSAIM_DIV_15
lypinator	0:bb348c97df44	6165	* @arg @ref LL_RCC_PLLSAIM_DIV_16
lypinator	0:bb348c97df44	6166	* @arg @ref LL_RCC_PLLSAIM_DIV_17
lypinator	0:bb348c97df44	6167	* @arg @ref LL_RCC_PLLSAIM_DIV_18
lypinator	0:bb348c97df44	6168	* @arg @ref LL_RCC_PLLSAIM_DIV_19
lypinator	0:bb348c97df44	6169	* @arg @ref LL_RCC_PLLSAIM_DIV_20
lypinator	0:bb348c97df44	6170	* @arg @ref LL_RCC_PLLSAIM_DIV_21
lypinator	0:bb348c97df44	6171	* @arg @ref LL_RCC_PLLSAIM_DIV_22
lypinator	0:bb348c97df44	6172	* @arg @ref LL_RCC_PLLSAIM_DIV_23
lypinator	0:bb348c97df44	6173	* @arg @ref LL_RCC_PLLSAIM_DIV_24
lypinator	0:bb348c97df44	6174	* @arg @ref LL_RCC_PLLSAIM_DIV_25
lypinator	0:bb348c97df44	6175	* @arg @ref LL_RCC_PLLSAIM_DIV_26
lypinator	0:bb348c97df44	6176	* @arg @ref LL_RCC_PLLSAIM_DIV_27
lypinator	0:bb348c97df44	6177	* @arg @ref LL_RCC_PLLSAIM_DIV_28
lypinator	0:bb348c97df44	6178	* @arg @ref LL_RCC_PLLSAIM_DIV_29
lypinator	0:bb348c97df44	6179	* @arg @ref LL_RCC_PLLSAIM_DIV_30
lypinator	0:bb348c97df44	6180	* @arg @ref LL_RCC_PLLSAIM_DIV_31
lypinator	0:bb348c97df44	6181	* @arg @ref LL_RCC_PLLSAIM_DIV_32
lypinator	0:bb348c97df44	6182	* @arg @ref LL_RCC_PLLSAIM_DIV_33
lypinator	0:bb348c97df44	6183	* @arg @ref LL_RCC_PLLSAIM_DIV_34
lypinator	0:bb348c97df44	6184	* @arg @ref LL_RCC_PLLSAIM_DIV_35
lypinator	0:bb348c97df44	6185	* @arg @ref LL_RCC_PLLSAIM_DIV_36
lypinator	0:bb348c97df44	6186	* @arg @ref LL_RCC_PLLSAIM_DIV_37
lypinator	0:bb348c97df44	6187	* @arg @ref LL_RCC_PLLSAIM_DIV_38
lypinator	0:bb348c97df44	6188	* @arg @ref LL_RCC_PLLSAIM_DIV_39
lypinator	0:bb348c97df44	6189	* @arg @ref LL_RCC_PLLSAIM_DIV_40
lypinator	0:bb348c97df44	6190	* @arg @ref LL_RCC_PLLSAIM_DIV_41
lypinator	0:bb348c97df44	6191	* @arg @ref LL_RCC_PLLSAIM_DIV_42
lypinator	0:bb348c97df44	6192	* @arg @ref LL_RCC_PLLSAIM_DIV_43
lypinator	0:bb348c97df44	6193	* @arg @ref LL_RCC_PLLSAIM_DIV_44
lypinator	0:bb348c97df44	6194	* @arg @ref LL_RCC_PLLSAIM_DIV_45
lypinator	0:bb348c97df44	6195	* @arg @ref LL_RCC_PLLSAIM_DIV_46
lypinator	0:bb348c97df44	6196	* @arg @ref LL_RCC_PLLSAIM_DIV_47
lypinator	0:bb348c97df44	6197	* @arg @ref LL_RCC_PLLSAIM_DIV_48
lypinator	0:bb348c97df44	6198	* @arg @ref LL_RCC_PLLSAIM_DIV_49
lypinator	0:bb348c97df44	6199	* @arg @ref LL_RCC_PLLSAIM_DIV_50
lypinator	0:bb348c97df44	6200	* @arg @ref LL_RCC_PLLSAIM_DIV_51
lypinator	0:bb348c97df44	6201	* @arg @ref LL_RCC_PLLSAIM_DIV_52
lypinator	0:bb348c97df44	6202	* @arg @ref LL_RCC_PLLSAIM_DIV_53
lypinator	0:bb348c97df44	6203	* @arg @ref LL_RCC_PLLSAIM_DIV_54
lypinator	0:bb348c97df44	6204	* @arg @ref LL_RCC_PLLSAIM_DIV_55
lypinator	0:bb348c97df44	6205	* @arg @ref LL_RCC_PLLSAIM_DIV_56
lypinator	0:bb348c97df44	6206	* @arg @ref LL_RCC_PLLSAIM_DIV_57
lypinator	0:bb348c97df44	6207	* @arg @ref LL_RCC_PLLSAIM_DIV_58
lypinator	0:bb348c97df44	6208	* @arg @ref LL_RCC_PLLSAIM_DIV_59
lypinator	0:bb348c97df44	6209	* @arg @ref LL_RCC_PLLSAIM_DIV_60
lypinator	0:bb348c97df44	6210	* @arg @ref LL_RCC_PLLSAIM_DIV_61
lypinator	0:bb348c97df44	6211	* @arg @ref LL_RCC_PLLSAIM_DIV_62
lypinator	0:bb348c97df44	6212	* @arg @ref LL_RCC_PLLSAIM_DIV_63
lypinator	0:bb348c97df44	6213	* @param PLLN Between 50 and 432
lypinator	0:bb348c97df44	6214	* @param PLLP This parameter can be one of the following values:
lypinator	0:bb348c97df44	6215	* @arg @ref LL_RCC_PLLSAIP_DIV_2
lypinator	0:bb348c97df44	6216	* @arg @ref LL_RCC_PLLSAIP_DIV_4
lypinator	0:bb348c97df44	6217	* @arg @ref LL_RCC_PLLSAIP_DIV_6
lypinator	0:bb348c97df44	6218	* @arg @ref LL_RCC_PLLSAIP_DIV_8
lypinator	0:bb348c97df44	6219	* @retval None
lypinator	0:bb348c97df44	6220	*/
lypinator	0:bb348c97df44	6221	__STATIC_INLINE void LL_RCC_PLLSAI_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
lypinator	0:bb348c97df44	6222	{
lypinator	0:bb348c97df44	6223	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source);
lypinator	0:bb348c97df44	6224	#if defined(RCC_PLLSAICFGR_PLLSAIM)
lypinator	0:bb348c97df44	6225	MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIM, PLLM);
lypinator	0:bb348c97df44	6226	#else
lypinator	0:bb348c97df44	6227	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM);
lypinator	0:bb348c97df44	6228	#endif /* RCC_PLLSAICFGR_PLLSAIM */
lypinator	0:bb348c97df44	6229	MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN \| RCC_PLLSAICFGR_PLLSAIP, PLLN << RCC_PLLSAICFGR_PLLSAIN_Pos \| PLLP);
lypinator	0:bb348c97df44	6230	}
lypinator	0:bb348c97df44	6231	#endif /* RCC_PLLSAICFGR_PLLSAIP */
lypinator	0:bb348c97df44	6232
lypinator	0:bb348c97df44	6233	#if defined(LTDC)
lypinator	0:bb348c97df44	6234	/**
lypinator	0:bb348c97df44	6235	* @brief Configure PLLSAI used for LTDC domain clock
lypinator	0:bb348c97df44	6236	* @note PLL Source and PLLM Divider can be written only when PLL,
lypinator	0:bb348c97df44	6237	* PLLI2S and PLLSAI(*) are disabled
lypinator	0:bb348c97df44	6238	* @note PLLN/PLLR can be written only when PLLSAI is disabled
lypinator	0:bb348c97df44	6239	* @note This can be selected for LTDC
lypinator	0:bb348c97df44	6240	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI_ConfigDomain_LTDC\n
lypinator	0:bb348c97df44	6241	* PLLCFGR PLLM LL_RCC_PLLSAI_ConfigDomain_LTDC\n
lypinator	0:bb348c97df44	6242	* PLLSAICFGR PLLSAIN LL_RCC_PLLSAI_ConfigDomain_LTDC\n
lypinator	0:bb348c97df44	6243	* PLLSAICFGR PLLSAIR LL_RCC_PLLSAI_ConfigDomain_LTDC\n
lypinator	0:bb348c97df44	6244	* DCKCFGR PLLSAIDIVR LL_RCC_PLLSAI_ConfigDomain_LTDC
lypinator	0:bb348c97df44	6245	* @param Source This parameter can be one of the following values:
lypinator	0:bb348c97df44	6246	* @arg @ref LL_RCC_PLLSOURCE_HSI
lypinator	0:bb348c97df44	6247	* @arg @ref LL_RCC_PLLSOURCE_HSE
lypinator	0:bb348c97df44	6248	* @param PLLM This parameter can be one of the following values:
lypinator	0:bb348c97df44	6249	* @arg @ref LL_RCC_PLLSAIM_DIV_2
lypinator	0:bb348c97df44	6250	* @arg @ref LL_RCC_PLLSAIM_DIV_3
lypinator	0:bb348c97df44	6251	* @arg @ref LL_RCC_PLLSAIM_DIV_4
lypinator	0:bb348c97df44	6252	* @arg @ref LL_RCC_PLLSAIM_DIV_5
lypinator	0:bb348c97df44	6253	* @arg @ref LL_RCC_PLLSAIM_DIV_6
lypinator	0:bb348c97df44	6254	* @arg @ref LL_RCC_PLLSAIM_DIV_7
lypinator	0:bb348c97df44	6255	* @arg @ref LL_RCC_PLLSAIM_DIV_8
lypinator	0:bb348c97df44	6256	* @arg @ref LL_RCC_PLLSAIM_DIV_9
lypinator	0:bb348c97df44	6257	* @arg @ref LL_RCC_PLLSAIM_DIV_10
lypinator	0:bb348c97df44	6258	* @arg @ref LL_RCC_PLLSAIM_DIV_11
lypinator	0:bb348c97df44	6259	* @arg @ref LL_RCC_PLLSAIM_DIV_12
lypinator	0:bb348c97df44	6260	* @arg @ref LL_RCC_PLLSAIM_DIV_13
lypinator	0:bb348c97df44	6261	* @arg @ref LL_RCC_PLLSAIM_DIV_14
lypinator	0:bb348c97df44	6262	* @arg @ref LL_RCC_PLLSAIM_DIV_15
lypinator	0:bb348c97df44	6263	* @arg @ref LL_RCC_PLLSAIM_DIV_16
lypinator	0:bb348c97df44	6264	* @arg @ref LL_RCC_PLLSAIM_DIV_17
lypinator	0:bb348c97df44	6265	* @arg @ref LL_RCC_PLLSAIM_DIV_18
lypinator	0:bb348c97df44	6266	* @arg @ref LL_RCC_PLLSAIM_DIV_19
lypinator	0:bb348c97df44	6267	* @arg @ref LL_RCC_PLLSAIM_DIV_20
lypinator	0:bb348c97df44	6268	* @arg @ref LL_RCC_PLLSAIM_DIV_21
lypinator	0:bb348c97df44	6269	* @arg @ref LL_RCC_PLLSAIM_DIV_22
lypinator	0:bb348c97df44	6270	* @arg @ref LL_RCC_PLLSAIM_DIV_23
lypinator	0:bb348c97df44	6271	* @arg @ref LL_RCC_PLLSAIM_DIV_24
lypinator	0:bb348c97df44	6272	* @arg @ref LL_RCC_PLLSAIM_DIV_25
lypinator	0:bb348c97df44	6273	* @arg @ref LL_RCC_PLLSAIM_DIV_26
lypinator	0:bb348c97df44	6274	* @arg @ref LL_RCC_PLLSAIM_DIV_27
lypinator	0:bb348c97df44	6275	* @arg @ref LL_RCC_PLLSAIM_DIV_28
lypinator	0:bb348c97df44	6276	* @arg @ref LL_RCC_PLLSAIM_DIV_29
lypinator	0:bb348c97df44	6277	* @arg @ref LL_RCC_PLLSAIM_DIV_30
lypinator	0:bb348c97df44	6278	* @arg @ref LL_RCC_PLLSAIM_DIV_31
lypinator	0:bb348c97df44	6279	* @arg @ref LL_RCC_PLLSAIM_DIV_32
lypinator	0:bb348c97df44	6280	* @arg @ref LL_RCC_PLLSAIM_DIV_33
lypinator	0:bb348c97df44	6281	* @arg @ref LL_RCC_PLLSAIM_DIV_34
lypinator	0:bb348c97df44	6282	* @arg @ref LL_RCC_PLLSAIM_DIV_35
lypinator	0:bb348c97df44	6283	* @arg @ref LL_RCC_PLLSAIM_DIV_36
lypinator	0:bb348c97df44	6284	* @arg @ref LL_RCC_PLLSAIM_DIV_37
lypinator	0:bb348c97df44	6285	* @arg @ref LL_RCC_PLLSAIM_DIV_38
lypinator	0:bb348c97df44	6286	* @arg @ref LL_RCC_PLLSAIM_DIV_39
lypinator	0:bb348c97df44	6287	* @arg @ref LL_RCC_PLLSAIM_DIV_40
lypinator	0:bb348c97df44	6288	* @arg @ref LL_RCC_PLLSAIM_DIV_41
lypinator	0:bb348c97df44	6289	* @arg @ref LL_RCC_PLLSAIM_DIV_42
lypinator	0:bb348c97df44	6290	* @arg @ref LL_RCC_PLLSAIM_DIV_43
lypinator	0:bb348c97df44	6291	* @arg @ref LL_RCC_PLLSAIM_DIV_44
lypinator	0:bb348c97df44	6292	* @arg @ref LL_RCC_PLLSAIM_DIV_45
lypinator	0:bb348c97df44	6293	* @arg @ref LL_RCC_PLLSAIM_DIV_46
lypinator	0:bb348c97df44	6294	* @arg @ref LL_RCC_PLLSAIM_DIV_47
lypinator	0:bb348c97df44	6295	* @arg @ref LL_RCC_PLLSAIM_DIV_48
lypinator	0:bb348c97df44	6296	* @arg @ref LL_RCC_PLLSAIM_DIV_49
lypinator	0:bb348c97df44	6297	* @arg @ref LL_RCC_PLLSAIM_DIV_50
lypinator	0:bb348c97df44	6298	* @arg @ref LL_RCC_PLLSAIM_DIV_51
lypinator	0:bb348c97df44	6299	* @arg @ref LL_RCC_PLLSAIM_DIV_52
lypinator	0:bb348c97df44	6300	* @arg @ref LL_RCC_PLLSAIM_DIV_53
lypinator	0:bb348c97df44	6301	* @arg @ref LL_RCC_PLLSAIM_DIV_54
lypinator	0:bb348c97df44	6302	* @arg @ref LL_RCC_PLLSAIM_DIV_55
lypinator	0:bb348c97df44	6303	* @arg @ref LL_RCC_PLLSAIM_DIV_56
lypinator	0:bb348c97df44	6304	* @arg @ref LL_RCC_PLLSAIM_DIV_57
lypinator	0:bb348c97df44	6305	* @arg @ref LL_RCC_PLLSAIM_DIV_58
lypinator	0:bb348c97df44	6306	* @arg @ref LL_RCC_PLLSAIM_DIV_59
lypinator	0:bb348c97df44	6307	* @arg @ref LL_RCC_PLLSAIM_DIV_60
lypinator	0:bb348c97df44	6308	* @arg @ref LL_RCC_PLLSAIM_DIV_61
lypinator	0:bb348c97df44	6309	* @arg @ref LL_RCC_PLLSAIM_DIV_62
lypinator	0:bb348c97df44	6310	* @arg @ref LL_RCC_PLLSAIM_DIV_63
lypinator	0:bb348c97df44	6311	* @param PLLN Between 49/50(*) and 432
lypinator	0:bb348c97df44	6312	*
lypinator	0:bb348c97df44	6313	* (*) value not defined in all devices.
lypinator	0:bb348c97df44	6314	* @param PLLR This parameter can be one of the following values:
lypinator	0:bb348c97df44	6315	* @arg @ref LL_RCC_PLLSAIR_DIV_2
lypinator	0:bb348c97df44	6316	* @arg @ref LL_RCC_PLLSAIR_DIV_3
lypinator	0:bb348c97df44	6317	* @arg @ref LL_RCC_PLLSAIR_DIV_4
lypinator	0:bb348c97df44	6318	* @arg @ref LL_RCC_PLLSAIR_DIV_5
lypinator	0:bb348c97df44	6319	* @arg @ref LL_RCC_PLLSAIR_DIV_6
lypinator	0:bb348c97df44	6320	* @arg @ref LL_RCC_PLLSAIR_DIV_7
lypinator	0:bb348c97df44	6321	* @param PLLDIVR This parameter can be one of the following values:
lypinator	0:bb348c97df44	6322	* @arg @ref LL_RCC_PLLSAIDIVR_DIV_2
lypinator	0:bb348c97df44	6323	* @arg @ref LL_RCC_PLLSAIDIVR_DIV_4
lypinator	0:bb348c97df44	6324	* @arg @ref LL_RCC_PLLSAIDIVR_DIV_8
lypinator	0:bb348c97df44	6325	* @arg @ref LL_RCC_PLLSAIDIVR_DIV_16
lypinator	0:bb348c97df44	6326	* @retval None
lypinator	0:bb348c97df44	6327	*/
lypinator	0:bb348c97df44	6328	__STATIC_INLINE void LL_RCC_PLLSAI_ConfigDomain_LTDC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR, uint32_t PLLDIVR)
lypinator	0:bb348c97df44	6329	{
lypinator	0:bb348c97df44	6330	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC \| RCC_PLLCFGR_PLLM, Source \| PLLM);
lypinator	0:bb348c97df44	6331	MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN \| RCC_PLLSAICFGR_PLLSAIR, PLLN << RCC_PLLSAICFGR_PLLSAIN_Pos \| PLLR);
lypinator	0:bb348c97df44	6332	MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVR, PLLDIVR);
lypinator	0:bb348c97df44	6333	}
lypinator	0:bb348c97df44	6334	#endif /* LTDC */
lypinator	0:bb348c97df44	6335
lypinator	0:bb348c97df44	6336	/**
lypinator	0:bb348c97df44	6337	* @brief Get division factor for PLLSAI input clock
lypinator	0:bb348c97df44	6338	* @rmtoll PLLCFGR PLLM LL_RCC_PLLSAI_GetDivider\n
lypinator	0:bb348c97df44	6339	* PLLSAICFGR PLLSAIM LL_RCC_PLLSAI_GetDivider
lypinator	0:bb348c97df44	6340	* @retval Returned value can be one of the following values:
lypinator	0:bb348c97df44	6341	* @arg @ref LL_RCC_PLLSAIM_DIV_2
lypinator	0:bb348c97df44	6342	* @arg @ref LL_RCC_PLLSAIM_DIV_3
lypinator	0:bb348c97df44	6343	* @arg @ref LL_RCC_PLLSAIM_DIV_4
lypinator	0:bb348c97df44	6344	* @arg @ref LL_RCC_PLLSAIM_DIV_5
lypinator	0:bb348c97df44	6345	* @arg @ref LL_RCC_PLLSAIM_DIV_6
lypinator	0:bb348c97df44	6346	* @arg @ref LL_RCC_PLLSAIM_DIV_7
lypinator	0:bb348c97df44	6347	* @arg @ref LL_RCC_PLLSAIM_DIV_8
lypinator	0:bb348c97df44	6348	* @arg @ref LL_RCC_PLLSAIM_DIV_9
lypinator	0:bb348c97df44	6349	* @arg @ref LL_RCC_PLLSAIM_DIV_10
lypinator	0:bb348c97df44	6350	* @arg @ref LL_RCC_PLLSAIM_DIV_11
lypinator	0:bb348c97df44	6351	* @arg @ref LL_RCC_PLLSAIM_DIV_12
lypinator	0:bb348c97df44	6352	* @arg @ref LL_RCC_PLLSAIM_DIV_13
lypinator	0:bb348c97df44	6353	* @arg @ref LL_RCC_PLLSAIM_DIV_14
lypinator	0:bb348c97df44	6354	* @arg @ref LL_RCC_PLLSAIM_DIV_15
lypinator	0:bb348c97df44	6355	* @arg @ref LL_RCC_PLLSAIM_DIV_16
lypinator	0:bb348c97df44	6356	* @arg @ref LL_RCC_PLLSAIM_DIV_17
lypinator	0:bb348c97df44	6357	* @arg @ref LL_RCC_PLLSAIM_DIV_18
lypinator	0:bb348c97df44	6358	* @arg @ref LL_RCC_PLLSAIM_DIV_19
lypinator	0:bb348c97df44	6359	* @arg @ref LL_RCC_PLLSAIM_DIV_20
lypinator	0:bb348c97df44	6360	* @arg @ref LL_RCC_PLLSAIM_DIV_21
lypinator	0:bb348c97df44	6361	* @arg @ref LL_RCC_PLLSAIM_DIV_22
lypinator	0:bb348c97df44	6362	* @arg @ref LL_RCC_PLLSAIM_DIV_23
lypinator	0:bb348c97df44	6363	* @arg @ref LL_RCC_PLLSAIM_DIV_24
lypinator	0:bb348c97df44	6364	* @arg @ref LL_RCC_PLLSAIM_DIV_25
lypinator	0:bb348c97df44	6365	* @arg @ref LL_RCC_PLLSAIM_DIV_26
lypinator	0:bb348c97df44	6366	* @arg @ref LL_RCC_PLLSAIM_DIV_27
lypinator	0:bb348c97df44	6367	* @arg @ref LL_RCC_PLLSAIM_DIV_28
lypinator	0:bb348c97df44	6368	* @arg @ref LL_RCC_PLLSAIM_DIV_29
lypinator	0:bb348c97df44	6369	* @arg @ref LL_RCC_PLLSAIM_DIV_30
lypinator	0:bb348c97df44	6370	* @arg @ref LL_RCC_PLLSAIM_DIV_31
lypinator	0:bb348c97df44	6371	* @arg @ref LL_RCC_PLLSAIM_DIV_32
lypinator	0:bb348c97df44	6372	* @arg @ref LL_RCC_PLLSAIM_DIV_33
lypinator	0:bb348c97df44	6373	* @arg @ref LL_RCC_PLLSAIM_DIV_34
lypinator	0:bb348c97df44	6374	* @arg @ref LL_RCC_PLLSAIM_DIV_35
lypinator	0:bb348c97df44	6375	* @arg @ref LL_RCC_PLLSAIM_DIV_36
lypinator	0:bb348c97df44	6376	* @arg @ref LL_RCC_PLLSAIM_DIV_37
lypinator	0:bb348c97df44	6377	* @arg @ref LL_RCC_PLLSAIM_DIV_38
lypinator	0:bb348c97df44	6378	* @arg @ref LL_RCC_PLLSAIM_DIV_39
lypinator	0:bb348c97df44	6379	* @arg @ref LL_RCC_PLLSAIM_DIV_40
lypinator	0:bb348c97df44	6380	* @arg @ref LL_RCC_PLLSAIM_DIV_41
lypinator	0:bb348c97df44	6381	* @arg @ref LL_RCC_PLLSAIM_DIV_42
lypinator	0:bb348c97df44	6382	* @arg @ref LL_RCC_PLLSAIM_DIV_43
lypinator	0:bb348c97df44	6383	* @arg @ref LL_RCC_PLLSAIM_DIV_44
lypinator	0:bb348c97df44	6384	* @arg @ref LL_RCC_PLLSAIM_DIV_45
lypinator	0:bb348c97df44	6385	* @arg @ref LL_RCC_PLLSAIM_DIV_46
lypinator	0:bb348c97df44	6386	* @arg @ref LL_RCC_PLLSAIM_DIV_47
lypinator	0:bb348c97df44	6387	* @arg @ref LL_RCC_PLLSAIM_DIV_48
lypinator	0:bb348c97df44	6388	* @arg @ref LL_RCC_PLLSAIM_DIV_49
lypinator	0:bb348c97df44	6389	* @arg @ref LL_RCC_PLLSAIM_DIV_50
lypinator	0:bb348c97df44	6390	* @arg @ref LL_RCC_PLLSAIM_DIV_51
lypinator	0:bb348c97df44	6391	* @arg @ref LL_RCC_PLLSAIM_DIV_52
lypinator	0:bb348c97df44	6392	* @arg @ref LL_RCC_PLLSAIM_DIV_53
lypinator	0:bb348c97df44	6393	* @arg @ref LL_RCC_PLLSAIM_DIV_54
lypinator	0:bb348c97df44	6394	* @arg @ref LL_RCC_PLLSAIM_DIV_55
lypinator	0:bb348c97df44	6395	* @arg @ref LL_RCC_PLLSAIM_DIV_56
lypinator	0:bb348c97df44	6396	* @arg @ref LL_RCC_PLLSAIM_DIV_57
lypinator	0:bb348c97df44	6397	* @arg @ref LL_RCC_PLLSAIM_DIV_58
lypinator	0:bb348c97df44	6398	* @arg @ref LL_RCC_PLLSAIM_DIV_59
lypinator	0:bb348c97df44	6399	* @arg @ref LL_RCC_PLLSAIM_DIV_60
lypinator	0:bb348c97df44	6400	* @arg @ref LL_RCC_PLLSAIM_DIV_61
lypinator	0:bb348c97df44	6401	* @arg @ref LL_RCC_PLLSAIM_DIV_62
lypinator	0:bb348c97df44	6402	* @arg @ref LL_RCC_PLLSAIM_DIV_63
lypinator	0:bb348c97df44	6403	*/
lypinator	0:bb348c97df44	6404	__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetDivider(void)
lypinator	0:bb348c97df44	6405	{
lypinator	0:bb348c97df44	6406	#if defined(RCC_PLLSAICFGR_PLLSAIM)
lypinator	0:bb348c97df44	6407	return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIM));
lypinator	0:bb348c97df44	6408	#else
lypinator	0:bb348c97df44	6409	return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM));
lypinator	0:bb348c97df44	6410	#endif /* RCC_PLLSAICFGR_PLLSAIM */
lypinator	0:bb348c97df44	6411	}
lypinator	0:bb348c97df44	6412
lypinator	0:bb348c97df44	6413	/**
lypinator	0:bb348c97df44	6414	* @brief Get SAIPLL multiplication factor for VCO
lypinator	0:bb348c97df44	6415	* @rmtoll PLLSAICFGR PLLSAIN LL_RCC_PLLSAI_GetN
lypinator	0:bb348c97df44	6416	* @retval Between 49/50(*) and 432
lypinator	0:bb348c97df44	6417	*
lypinator	0:bb348c97df44	6418	* (*) value not defined in all devices.
lypinator	0:bb348c97df44	6419	*/
lypinator	0:bb348c97df44	6420	__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetN(void)
lypinator	0:bb348c97df44	6421	{
lypinator	0:bb348c97df44	6422	return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN) >> RCC_PLLSAICFGR_PLLSAIN_Pos);
lypinator	0:bb348c97df44	6423	}
lypinator	0:bb348c97df44	6424
lypinator	0:bb348c97df44	6425	/**
lypinator	0:bb348c97df44	6426	* @brief Get SAIPLL division factor for PLLSAIQ
lypinator	0:bb348c97df44	6427	* @rmtoll PLLSAICFGR PLLSAIQ LL_RCC_PLLSAI_GetQ
lypinator	0:bb348c97df44	6428	* @retval Returned value can be one of the following values:
lypinator	0:bb348c97df44	6429	* @arg @ref LL_RCC_PLLSAIQ_DIV_2
lypinator	0:bb348c97df44	6430	* @arg @ref LL_RCC_PLLSAIQ_DIV_3
lypinator	0:bb348c97df44	6431	* @arg @ref LL_RCC_PLLSAIQ_DIV_4
lypinator	0:bb348c97df44	6432	* @arg @ref LL_RCC_PLLSAIQ_DIV_5
lypinator	0:bb348c97df44	6433	* @arg @ref LL_RCC_PLLSAIQ_DIV_6
lypinator	0:bb348c97df44	6434	* @arg @ref LL_RCC_PLLSAIQ_DIV_7
lypinator	0:bb348c97df44	6435	* @arg @ref LL_RCC_PLLSAIQ_DIV_8
lypinator	0:bb348c97df44	6436	* @arg @ref LL_RCC_PLLSAIQ_DIV_9
lypinator	0:bb348c97df44	6437	* @arg @ref LL_RCC_PLLSAIQ_DIV_10
lypinator	0:bb348c97df44	6438	* @arg @ref LL_RCC_PLLSAIQ_DIV_11
lypinator	0:bb348c97df44	6439	* @arg @ref LL_RCC_PLLSAIQ_DIV_12
lypinator	0:bb348c97df44	6440	* @arg @ref LL_RCC_PLLSAIQ_DIV_13
lypinator	0:bb348c97df44	6441	* @arg @ref LL_RCC_PLLSAIQ_DIV_14
lypinator	0:bb348c97df44	6442	* @arg @ref LL_RCC_PLLSAIQ_DIV_15
lypinator	0:bb348c97df44	6443	*/
lypinator	0:bb348c97df44	6444	__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetQ(void)
lypinator	0:bb348c97df44	6445	{
lypinator	0:bb348c97df44	6446	return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIQ));
lypinator	0:bb348c97df44	6447	}
lypinator	0:bb348c97df44	6448
lypinator	0:bb348c97df44	6449	#if defined(RCC_PLLSAICFGR_PLLSAIR)
lypinator	0:bb348c97df44	6450	/**
lypinator	0:bb348c97df44	6451	* @brief Get SAIPLL division factor for PLLSAIR
lypinator	0:bb348c97df44	6452	* @note used for PLLSAICLK (SAI clock)
lypinator	0:bb348c97df44	6453	* @rmtoll PLLSAICFGR PLLSAIR LL_RCC_PLLSAI_GetR
lypinator	0:bb348c97df44	6454	* @retval Returned value can be one of the following values:
lypinator	0:bb348c97df44	6455	* @arg @ref LL_RCC_PLLSAIR_DIV_2
lypinator	0:bb348c97df44	6456	* @arg @ref LL_RCC_PLLSAIR_DIV_3
lypinator	0:bb348c97df44	6457	* @arg @ref LL_RCC_PLLSAIR_DIV_4
lypinator	0:bb348c97df44	6458	* @arg @ref LL_RCC_PLLSAIR_DIV_5
lypinator	0:bb348c97df44	6459	* @arg @ref LL_RCC_PLLSAIR_DIV_6
lypinator	0:bb348c97df44	6460	* @arg @ref LL_RCC_PLLSAIR_DIV_7
lypinator	0:bb348c97df44	6461	*/
lypinator	0:bb348c97df44	6462	__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetR(void)
lypinator	0:bb348c97df44	6463	{
lypinator	0:bb348c97df44	6464	return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIR));
lypinator	0:bb348c97df44	6465	}
lypinator	0:bb348c97df44	6466	#endif /* RCC_PLLSAICFGR_PLLSAIR */
lypinator	0:bb348c97df44	6467
lypinator	0:bb348c97df44	6468	#if defined(RCC_PLLSAICFGR_PLLSAIP)
lypinator	0:bb348c97df44	6469	/**
lypinator	0:bb348c97df44	6470	* @brief Get SAIPLL division factor for PLLSAIP
lypinator	0:bb348c97df44	6471	* @note used for PLL48MCLK (48M domain clock)
lypinator	0:bb348c97df44	6472	* @rmtoll PLLSAICFGR PLLSAIP LL_RCC_PLLSAI_GetP
lypinator	0:bb348c97df44	6473	* @retval Returned value can be one of the following values:
lypinator	0:bb348c97df44	6474	* @arg @ref LL_RCC_PLLSAIP_DIV_2
lypinator	0:bb348c97df44	6475	* @arg @ref LL_RCC_PLLSAIP_DIV_4
lypinator	0:bb348c97df44	6476	* @arg @ref LL_RCC_PLLSAIP_DIV_6
lypinator	0:bb348c97df44	6477	* @arg @ref LL_RCC_PLLSAIP_DIV_8
lypinator	0:bb348c97df44	6478	*/
lypinator	0:bb348c97df44	6479	__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetP(void)
lypinator	0:bb348c97df44	6480	{
lypinator	0:bb348c97df44	6481	return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIP));
lypinator	0:bb348c97df44	6482	}
lypinator	0:bb348c97df44	6483	#endif /* RCC_PLLSAICFGR_PLLSAIP */
lypinator	0:bb348c97df44	6484
lypinator	0:bb348c97df44	6485	/**
lypinator	0:bb348c97df44	6486	* @brief Get SAIPLL division factor for PLLSAIDIVQ
lypinator	0:bb348c97df44	6487	* @note used PLLSAICLK selected (SAI clock)
lypinator	0:bb348c97df44	6488	* @rmtoll DCKCFGR PLLSAIDIVQ LL_RCC_PLLSAI_GetDIVQ
lypinator	0:bb348c97df44	6489	* @retval Returned value can be one of the following values:
lypinator	0:bb348c97df44	6490	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_1
lypinator	0:bb348c97df44	6491	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_2
lypinator	0:bb348c97df44	6492	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_3
lypinator	0:bb348c97df44	6493	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_4
lypinator	0:bb348c97df44	6494	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_5
lypinator	0:bb348c97df44	6495	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_6
lypinator	0:bb348c97df44	6496	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_7
lypinator	0:bb348c97df44	6497	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_8
lypinator	0:bb348c97df44	6498	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_9
lypinator	0:bb348c97df44	6499	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_10
lypinator	0:bb348c97df44	6500	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_11
lypinator	0:bb348c97df44	6501	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_12
lypinator	0:bb348c97df44	6502	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_13
lypinator	0:bb348c97df44	6503	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_14
lypinator	0:bb348c97df44	6504	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_15
lypinator	0:bb348c97df44	6505	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_16
lypinator	0:bb348c97df44	6506	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_17
lypinator	0:bb348c97df44	6507	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_18
lypinator	0:bb348c97df44	6508	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_19
lypinator	0:bb348c97df44	6509	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_20
lypinator	0:bb348c97df44	6510	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_21
lypinator	0:bb348c97df44	6511	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_22
lypinator	0:bb348c97df44	6512	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_23
lypinator	0:bb348c97df44	6513	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_24
lypinator	0:bb348c97df44	6514	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_25
lypinator	0:bb348c97df44	6515	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_26
lypinator	0:bb348c97df44	6516	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_27
lypinator	0:bb348c97df44	6517	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_28
lypinator	0:bb348c97df44	6518	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_29
lypinator	0:bb348c97df44	6519	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_30
lypinator	0:bb348c97df44	6520	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_31
lypinator	0:bb348c97df44	6521	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_32
lypinator	0:bb348c97df44	6522	*/
lypinator	0:bb348c97df44	6523	__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetDIVQ(void)
lypinator	0:bb348c97df44	6524	{
lypinator	0:bb348c97df44	6525	return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVQ));
lypinator	0:bb348c97df44	6526	}
lypinator	0:bb348c97df44	6527
lypinator	0:bb348c97df44	6528	#if defined(RCC_DCKCFGR_PLLSAIDIVR)
lypinator	0:bb348c97df44	6529	/**
lypinator	0:bb348c97df44	6530	* @brief Get SAIPLL division factor for PLLSAIDIVR
lypinator	0:bb348c97df44	6531	* @note used for LTDC domain clock
lypinator	0:bb348c97df44	6532	* @rmtoll DCKCFGR PLLSAIDIVR LL_RCC_PLLSAI_GetDIVR
lypinator	0:bb348c97df44	6533	* @retval Returned value can be one of the following values:
lypinator	0:bb348c97df44	6534	* @arg @ref LL_RCC_PLLSAIDIVR_DIV_2
lypinator	0:bb348c97df44	6535	* @arg @ref LL_RCC_PLLSAIDIVR_DIV_4
lypinator	0:bb348c97df44	6536	* @arg @ref LL_RCC_PLLSAIDIVR_DIV_8
lypinator	0:bb348c97df44	6537	* @arg @ref LL_RCC_PLLSAIDIVR_DIV_16
lypinator	0:bb348c97df44	6538	*/
lypinator	0:bb348c97df44	6539	__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetDIVR(void)
lypinator	0:bb348c97df44	6540	{
lypinator	0:bb348c97df44	6541	return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVR));
lypinator	0:bb348c97df44	6542	}
lypinator	0:bb348c97df44	6543	#endif /* RCC_DCKCFGR_PLLSAIDIVR */
lypinator	0:bb348c97df44	6544
lypinator	0:bb348c97df44	6545	/**
lypinator	0:bb348c97df44	6546	* @}
lypinator	0:bb348c97df44	6547	*/
lypinator	0:bb348c97df44	6548	#endif /* RCC_PLLSAI_SUPPORT */
lypinator	0:bb348c97df44	6549
lypinator	0:bb348c97df44	6550	/** @defgroup RCC_LL_EF_FLAG_Management FLAG Management
lypinator	0:bb348c97df44	6551	* @{
lypinator	0:bb348c97df44	6552	*/
lypinator	0:bb348c97df44	6553
lypinator	0:bb348c97df44	6554	/**
lypinator	0:bb348c97df44	6555	* @brief Clear LSI ready interrupt flag
lypinator	0:bb348c97df44	6556	* @rmtoll CIR LSIRDYC LL_RCC_ClearFlag_LSIRDY
lypinator	0:bb348c97df44	6557	* @retval None
lypinator	0:bb348c97df44	6558	*/
lypinator	0:bb348c97df44	6559	__STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void)
lypinator	0:bb348c97df44	6560	{
lypinator	0:bb348c97df44	6561	SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC);
lypinator	0:bb348c97df44	6562	}
lypinator	0:bb348c97df44	6563
lypinator	0:bb348c97df44	6564	/**
lypinator	0:bb348c97df44	6565	* @brief Clear LSE ready interrupt flag
lypinator	0:bb348c97df44	6566	* @rmtoll CIR LSERDYC LL_RCC_ClearFlag_LSERDY
lypinator	0:bb348c97df44	6567	* @retval None
lypinator	0:bb348c97df44	6568	*/
lypinator	0:bb348c97df44	6569	__STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)
lypinator	0:bb348c97df44	6570	{
lypinator	0:bb348c97df44	6571	SET_BIT(RCC->CIR, RCC_CIR_LSERDYC);
lypinator	0:bb348c97df44	6572	}
lypinator	0:bb348c97df44	6573
lypinator	0:bb348c97df44	6574	/**
lypinator	0:bb348c97df44	6575	* @brief Clear HSI ready interrupt flag
lypinator	0:bb348c97df44	6576	* @rmtoll CIR HSIRDYC LL_RCC_ClearFlag_HSIRDY
lypinator	0:bb348c97df44	6577	* @retval None
lypinator	0:bb348c97df44	6578	*/
lypinator	0:bb348c97df44	6579	__STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)
lypinator	0:bb348c97df44	6580	{
lypinator	0:bb348c97df44	6581	SET_BIT(RCC->CIR, RCC_CIR_HSIRDYC);
lypinator	0:bb348c97df44	6582	}
lypinator	0:bb348c97df44	6583
lypinator	0:bb348c97df44	6584	/**
lypinator	0:bb348c97df44	6585	* @brief Clear HSE ready interrupt flag
lypinator	0:bb348c97df44	6586	* @rmtoll CIR HSERDYC LL_RCC_ClearFlag_HSERDY
lypinator	0:bb348c97df44	6587	* @retval None
lypinator	0:bb348c97df44	6588	*/
lypinator	0:bb348c97df44	6589	__STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)
lypinator	0:bb348c97df44	6590	{
lypinator	0:bb348c97df44	6591	SET_BIT(RCC->CIR, RCC_CIR_HSERDYC);
lypinator	0:bb348c97df44	6592	}
lypinator	0:bb348c97df44	6593
lypinator	0:bb348c97df44	6594	/**
lypinator	0:bb348c97df44	6595	* @brief Clear PLL ready interrupt flag
lypinator	0:bb348c97df44	6596	* @rmtoll CIR PLLRDYC LL_RCC_ClearFlag_PLLRDY
lypinator	0:bb348c97df44	6597	* @retval None
lypinator	0:bb348c97df44	6598	*/
lypinator	0:bb348c97df44	6599	__STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void)
lypinator	0:bb348c97df44	6600	{
lypinator	0:bb348c97df44	6601	SET_BIT(RCC->CIR, RCC_CIR_PLLRDYC);
lypinator	0:bb348c97df44	6602	}
lypinator	0:bb348c97df44	6603
lypinator	0:bb348c97df44	6604	#if defined(RCC_PLLI2S_SUPPORT)
lypinator	0:bb348c97df44	6605	/**
lypinator	0:bb348c97df44	6606	* @brief Clear PLLI2S ready interrupt flag
lypinator	0:bb348c97df44	6607	* @rmtoll CIR PLLI2SRDYC LL_RCC_ClearFlag_PLLI2SRDY
lypinator	0:bb348c97df44	6608	* @retval None
lypinator	0:bb348c97df44	6609	*/
lypinator	0:bb348c97df44	6610	__STATIC_INLINE void LL_RCC_ClearFlag_PLLI2SRDY(void)
lypinator	0:bb348c97df44	6611	{
lypinator	0:bb348c97df44	6612	SET_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYC);
lypinator	0:bb348c97df44	6613	}
lypinator	0:bb348c97df44	6614
lypinator	0:bb348c97df44	6615	#endif /* RCC_PLLI2S_SUPPORT */
lypinator	0:bb348c97df44	6616
lypinator	0:bb348c97df44	6617	#if defined(RCC_PLLSAI_SUPPORT)
lypinator	0:bb348c97df44	6618	/**
lypinator	0:bb348c97df44	6619	* @brief Clear PLLSAI ready interrupt flag
lypinator	0:bb348c97df44	6620	* @rmtoll CIR PLLSAIRDYC LL_RCC_ClearFlag_PLLSAIRDY
lypinator	0:bb348c97df44	6621	* @retval None
lypinator	0:bb348c97df44	6622	*/
lypinator	0:bb348c97df44	6623	__STATIC_INLINE void LL_RCC_ClearFlag_PLLSAIRDY(void)
lypinator	0:bb348c97df44	6624	{
lypinator	0:bb348c97df44	6625	SET_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYC);
lypinator	0:bb348c97df44	6626	}
lypinator	0:bb348c97df44	6627
lypinator	0:bb348c97df44	6628	#endif /* RCC_PLLSAI_SUPPORT */
lypinator	0:bb348c97df44	6629
lypinator	0:bb348c97df44	6630	/**
lypinator	0:bb348c97df44	6631	* @brief Clear Clock security system interrupt flag
lypinator	0:bb348c97df44	6632	* @rmtoll CIR CSSC LL_RCC_ClearFlag_HSECSS
lypinator	0:bb348c97df44	6633	* @retval None
lypinator	0:bb348c97df44	6634	*/
lypinator	0:bb348c97df44	6635	__STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)
lypinator	0:bb348c97df44	6636	{
lypinator	0:bb348c97df44	6637	SET_BIT(RCC->CIR, RCC_CIR_CSSC);
lypinator	0:bb348c97df44	6638	}
lypinator	0:bb348c97df44	6639
lypinator	0:bb348c97df44	6640	/**
lypinator	0:bb348c97df44	6641	* @brief Check if LSI ready interrupt occurred or not
lypinator	0:bb348c97df44	6642	* @rmtoll CIR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY
lypinator	0:bb348c97df44	6643	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	6644	*/
lypinator	0:bb348c97df44	6645	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void)
lypinator	0:bb348c97df44	6646	{
lypinator	0:bb348c97df44	6647	return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYF) == (RCC_CIR_LSIRDYF));
lypinator	0:bb348c97df44	6648	}
lypinator	0:bb348c97df44	6649
lypinator	0:bb348c97df44	6650	/**
lypinator	0:bb348c97df44	6651	* @brief Check if LSE ready interrupt occurred or not
lypinator	0:bb348c97df44	6652	* @rmtoll CIR LSERDYF LL_RCC_IsActiveFlag_LSERDY
lypinator	0:bb348c97df44	6653	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	6654	*/
lypinator	0:bb348c97df44	6655	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
lypinator	0:bb348c97df44	6656	{
lypinator	0:bb348c97df44	6657	return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYF) == (RCC_CIR_LSERDYF));
lypinator	0:bb348c97df44	6658	}
lypinator	0:bb348c97df44	6659
lypinator	0:bb348c97df44	6660	/**
lypinator	0:bb348c97df44	6661	* @brief Check if HSI ready interrupt occurred or not
lypinator	0:bb348c97df44	6662	* @rmtoll CIR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY
lypinator	0:bb348c97df44	6663	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	6664	*/
lypinator	0:bb348c97df44	6665	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
lypinator	0:bb348c97df44	6666	{
lypinator	0:bb348c97df44	6667	return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYF) == (RCC_CIR_HSIRDYF));
lypinator	0:bb348c97df44	6668	}
lypinator	0:bb348c97df44	6669
lypinator	0:bb348c97df44	6670	/**
lypinator	0:bb348c97df44	6671	* @brief Check if HSE ready interrupt occurred or not
lypinator	0:bb348c97df44	6672	* @rmtoll CIR HSERDYF LL_RCC_IsActiveFlag_HSERDY
lypinator	0:bb348c97df44	6673	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	6674	*/
lypinator	0:bb348c97df44	6675	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
lypinator	0:bb348c97df44	6676	{
lypinator	0:bb348c97df44	6677	return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYF) == (RCC_CIR_HSERDYF));
lypinator	0:bb348c97df44	6678	}
lypinator	0:bb348c97df44	6679
lypinator	0:bb348c97df44	6680	/**
lypinator	0:bb348c97df44	6681	* @brief Check if PLL ready interrupt occurred or not
lypinator	0:bb348c97df44	6682	* @rmtoll CIR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY
lypinator	0:bb348c97df44	6683	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	6684	*/
lypinator	0:bb348c97df44	6685	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void)
lypinator	0:bb348c97df44	6686	{
lypinator	0:bb348c97df44	6687	return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYF) == (RCC_CIR_PLLRDYF));
lypinator	0:bb348c97df44	6688	}
lypinator	0:bb348c97df44	6689
lypinator	0:bb348c97df44	6690	#if defined(RCC_PLLI2S_SUPPORT)
lypinator	0:bb348c97df44	6691	/**
lypinator	0:bb348c97df44	6692	* @brief Check if PLLI2S ready interrupt occurred or not
lypinator	0:bb348c97df44	6693	* @rmtoll CIR PLLI2SRDYF LL_RCC_IsActiveFlag_PLLI2SRDY
lypinator	0:bb348c97df44	6694	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	6695	*/
lypinator	0:bb348c97df44	6696	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLI2SRDY(void)
lypinator	0:bb348c97df44	6697	{
lypinator	0:bb348c97df44	6698	return (READ_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYF) == (RCC_CIR_PLLI2SRDYF));
lypinator	0:bb348c97df44	6699	}
lypinator	0:bb348c97df44	6700	#endif /* RCC_PLLI2S_SUPPORT */
lypinator	0:bb348c97df44	6701
lypinator	0:bb348c97df44	6702	#if defined(RCC_PLLSAI_SUPPORT)
lypinator	0:bb348c97df44	6703	/**
lypinator	0:bb348c97df44	6704	* @brief Check if PLLSAI ready interrupt occurred or not
lypinator	0:bb348c97df44	6705	* @rmtoll CIR PLLSAIRDYF LL_RCC_IsActiveFlag_PLLSAIRDY
lypinator	0:bb348c97df44	6706	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	6707	*/
lypinator	0:bb348c97df44	6708	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLSAIRDY(void)
lypinator	0:bb348c97df44	6709	{
lypinator	0:bb348c97df44	6710	return (READ_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYF) == (RCC_CIR_PLLSAIRDYF));
lypinator	0:bb348c97df44	6711	}
lypinator	0:bb348c97df44	6712	#endif /* RCC_PLLSAI_SUPPORT */
lypinator	0:bb348c97df44	6713
lypinator	0:bb348c97df44	6714	/**
lypinator	0:bb348c97df44	6715	* @brief Check if Clock security system interrupt occurred or not
lypinator	0:bb348c97df44	6716	* @rmtoll CIR CSSF LL_RCC_IsActiveFlag_HSECSS
lypinator	0:bb348c97df44	6717	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	6718	*/
lypinator	0:bb348c97df44	6719	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)
lypinator	0:bb348c97df44	6720	{
lypinator	0:bb348c97df44	6721	return (READ_BIT(RCC->CIR, RCC_CIR_CSSF) == (RCC_CIR_CSSF));
lypinator	0:bb348c97df44	6722	}
lypinator	0:bb348c97df44	6723
lypinator	0:bb348c97df44	6724	/**
lypinator	0:bb348c97df44	6725	* @brief Check if RCC flag Independent Watchdog reset is set or not.
lypinator	0:bb348c97df44	6726	* @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST
lypinator	0:bb348c97df44	6727	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	6728	*/
lypinator	0:bb348c97df44	6729	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void)
lypinator	0:bb348c97df44	6730	{
lypinator	0:bb348c97df44	6731	return (READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF));
lypinator	0:bb348c97df44	6732	}
lypinator	0:bb348c97df44	6733
lypinator	0:bb348c97df44	6734	/**
lypinator	0:bb348c97df44	6735	* @brief Check if RCC flag Low Power reset is set or not.
lypinator	0:bb348c97df44	6736	* @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST
lypinator	0:bb348c97df44	6737	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	6738	*/
lypinator	0:bb348c97df44	6739	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)
lypinator	0:bb348c97df44	6740	{
lypinator	0:bb348c97df44	6741	return (READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF));
lypinator	0:bb348c97df44	6742	}
lypinator	0:bb348c97df44	6743
lypinator	0:bb348c97df44	6744	/**
lypinator	0:bb348c97df44	6745	* @brief Check if RCC flag Pin reset is set or not.
lypinator	0:bb348c97df44	6746	* @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST
lypinator	0:bb348c97df44	6747	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	6748	*/
lypinator	0:bb348c97df44	6749	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)
lypinator	0:bb348c97df44	6750	{
lypinator	0:bb348c97df44	6751	return (READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF));
lypinator	0:bb348c97df44	6752	}
lypinator	0:bb348c97df44	6753
lypinator	0:bb348c97df44	6754	/**
lypinator	0:bb348c97df44	6755	* @brief Check if RCC flag POR/PDR reset is set or not.
lypinator	0:bb348c97df44	6756	* @rmtoll CSR PORRSTF LL_RCC_IsActiveFlag_PORRST
lypinator	0:bb348c97df44	6757	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	6758	*/
lypinator	0:bb348c97df44	6759	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void)
lypinator	0:bb348c97df44	6760	{
lypinator	0:bb348c97df44	6761	return (READ_BIT(RCC->CSR, RCC_CSR_PORRSTF) == (RCC_CSR_PORRSTF));
lypinator	0:bb348c97df44	6762	}
lypinator	0:bb348c97df44	6763
lypinator	0:bb348c97df44	6764	/**
lypinator	0:bb348c97df44	6765	* @brief Check if RCC flag Software reset is set or not.
lypinator	0:bb348c97df44	6766	* @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST
lypinator	0:bb348c97df44	6767	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	6768	*/
lypinator	0:bb348c97df44	6769	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
lypinator	0:bb348c97df44	6770	{
lypinator	0:bb348c97df44	6771	return (READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF));
lypinator	0:bb348c97df44	6772	}
lypinator	0:bb348c97df44	6773
lypinator	0:bb348c97df44	6774	/**
lypinator	0:bb348c97df44	6775	* @brief Check if RCC flag Window Watchdog reset is set or not.
lypinator	0:bb348c97df44	6776	* @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST
lypinator	0:bb348c97df44	6777	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	6778	*/
lypinator	0:bb348c97df44	6779	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void)
lypinator	0:bb348c97df44	6780	{
lypinator	0:bb348c97df44	6781	return (READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF));
lypinator	0:bb348c97df44	6782	}
lypinator	0:bb348c97df44	6783
lypinator	0:bb348c97df44	6784	#if defined(RCC_CSR_BORRSTF)
lypinator	0:bb348c97df44	6785	/**
lypinator	0:bb348c97df44	6786	* @brief Check if RCC flag BOR reset is set or not.
lypinator	0:bb348c97df44	6787	* @rmtoll CSR BORRSTF LL_RCC_IsActiveFlag_BORRST
lypinator	0:bb348c97df44	6788	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	6789	*/
lypinator	0:bb348c97df44	6790	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void)
lypinator	0:bb348c97df44	6791	{
lypinator	0:bb348c97df44	6792	return (READ_BIT(RCC->CSR, RCC_CSR_BORRSTF) == (RCC_CSR_BORRSTF));
lypinator	0:bb348c97df44	6793	}
lypinator	0:bb348c97df44	6794	#endif /* RCC_CSR_BORRSTF */
lypinator	0:bb348c97df44	6795
lypinator	0:bb348c97df44	6796	/**
lypinator	0:bb348c97df44	6797	* @brief Set RMVF bit to clear the reset flags.
lypinator	0:bb348c97df44	6798	* @rmtoll CSR RMVF LL_RCC_ClearResetFlags
lypinator	0:bb348c97df44	6799	* @retval None
lypinator	0:bb348c97df44	6800	*/
lypinator	0:bb348c97df44	6801	__STATIC_INLINE void LL_RCC_ClearResetFlags(void)
lypinator	0:bb348c97df44	6802	{
lypinator	0:bb348c97df44	6803	SET_BIT(RCC->CSR, RCC_CSR_RMVF);
lypinator	0:bb348c97df44	6804	}
lypinator	0:bb348c97df44	6805
lypinator	0:bb348c97df44	6806	/**
lypinator	0:bb348c97df44	6807	* @}
lypinator	0:bb348c97df44	6808	*/
lypinator	0:bb348c97df44	6809
lypinator	0:bb348c97df44	6810	/** @defgroup RCC_LL_EF_IT_Management IT Management
lypinator	0:bb348c97df44	6811	* @{
lypinator	0:bb348c97df44	6812	*/
lypinator	0:bb348c97df44	6813
lypinator	0:bb348c97df44	6814	/**
lypinator	0:bb348c97df44	6815	* @brief Enable LSI ready interrupt
lypinator	0:bb348c97df44	6816	* @rmtoll CIR LSIRDYIE LL_RCC_EnableIT_LSIRDY
lypinator	0:bb348c97df44	6817	* @retval None
lypinator	0:bb348c97df44	6818	*/
lypinator	0:bb348c97df44	6819	__STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void)
lypinator	0:bb348c97df44	6820	{
lypinator	0:bb348c97df44	6821	SET_BIT(RCC->CIR, RCC_CIR_LSIRDYIE);
lypinator	0:bb348c97df44	6822	}
lypinator	0:bb348c97df44	6823
lypinator	0:bb348c97df44	6824	/**
lypinator	0:bb348c97df44	6825	* @brief Enable LSE ready interrupt
lypinator	0:bb348c97df44	6826	* @rmtoll CIR LSERDYIE LL_RCC_EnableIT_LSERDY
lypinator	0:bb348c97df44	6827	* @retval None
lypinator	0:bb348c97df44	6828	*/
lypinator	0:bb348c97df44	6829	__STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)
lypinator	0:bb348c97df44	6830	{
lypinator	0:bb348c97df44	6831	SET_BIT(RCC->CIR, RCC_CIR_LSERDYIE);
lypinator	0:bb348c97df44	6832	}
lypinator	0:bb348c97df44	6833
lypinator	0:bb348c97df44	6834	/**
lypinator	0:bb348c97df44	6835	* @brief Enable HSI ready interrupt
lypinator	0:bb348c97df44	6836	* @rmtoll CIR HSIRDYIE LL_RCC_EnableIT_HSIRDY
lypinator	0:bb348c97df44	6837	* @retval None
lypinator	0:bb348c97df44	6838	*/
lypinator	0:bb348c97df44	6839	__STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)
lypinator	0:bb348c97df44	6840	{
lypinator	0:bb348c97df44	6841	SET_BIT(RCC->CIR, RCC_CIR_HSIRDYIE);
lypinator	0:bb348c97df44	6842	}
lypinator	0:bb348c97df44	6843
lypinator	0:bb348c97df44	6844	/**
lypinator	0:bb348c97df44	6845	* @brief Enable HSE ready interrupt
lypinator	0:bb348c97df44	6846	* @rmtoll CIR HSERDYIE LL_RCC_EnableIT_HSERDY
lypinator	0:bb348c97df44	6847	* @retval None
lypinator	0:bb348c97df44	6848	*/
lypinator	0:bb348c97df44	6849	__STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)
lypinator	0:bb348c97df44	6850	{
lypinator	0:bb348c97df44	6851	SET_BIT(RCC->CIR, RCC_CIR_HSERDYIE);
lypinator	0:bb348c97df44	6852	}
lypinator	0:bb348c97df44	6853
lypinator	0:bb348c97df44	6854	/**
lypinator	0:bb348c97df44	6855	* @brief Enable PLL ready interrupt
lypinator	0:bb348c97df44	6856	* @rmtoll CIR PLLRDYIE LL_RCC_EnableIT_PLLRDY
lypinator	0:bb348c97df44	6857	* @retval None
lypinator	0:bb348c97df44	6858	*/
lypinator	0:bb348c97df44	6859	__STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void)
lypinator	0:bb348c97df44	6860	{
lypinator	0:bb348c97df44	6861	SET_BIT(RCC->CIR, RCC_CIR_PLLRDYIE);
lypinator	0:bb348c97df44	6862	}
lypinator	0:bb348c97df44	6863
lypinator	0:bb348c97df44	6864	#if defined(RCC_PLLI2S_SUPPORT)
lypinator	0:bb348c97df44	6865	/**
lypinator	0:bb348c97df44	6866	* @brief Enable PLLI2S ready interrupt
lypinator	0:bb348c97df44	6867	* @rmtoll CIR PLLI2SRDYIE LL_RCC_EnableIT_PLLI2SRDY
lypinator	0:bb348c97df44	6868	* @retval None
lypinator	0:bb348c97df44	6869	*/
lypinator	0:bb348c97df44	6870	__STATIC_INLINE void LL_RCC_EnableIT_PLLI2SRDY(void)
lypinator	0:bb348c97df44	6871	{
lypinator	0:bb348c97df44	6872	SET_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE);
lypinator	0:bb348c97df44	6873	}
lypinator	0:bb348c97df44	6874	#endif /* RCC_PLLI2S_SUPPORT */
lypinator	0:bb348c97df44	6875
lypinator	0:bb348c97df44	6876	#if defined(RCC_PLLSAI_SUPPORT)
lypinator	0:bb348c97df44	6877	/**
lypinator	0:bb348c97df44	6878	* @brief Enable PLLSAI ready interrupt
lypinator	0:bb348c97df44	6879	* @rmtoll CIR PLLSAIRDYIE LL_RCC_EnableIT_PLLSAIRDY
lypinator	0:bb348c97df44	6880	* @retval None
lypinator	0:bb348c97df44	6881	*/
lypinator	0:bb348c97df44	6882	__STATIC_INLINE void LL_RCC_EnableIT_PLLSAIRDY(void)
lypinator	0:bb348c97df44	6883	{
lypinator	0:bb348c97df44	6884	SET_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE);
lypinator	0:bb348c97df44	6885	}
lypinator	0:bb348c97df44	6886	#endif /* RCC_PLLSAI_SUPPORT */
lypinator	0:bb348c97df44	6887
lypinator	0:bb348c97df44	6888	/**
lypinator	0:bb348c97df44	6889	* @brief Disable LSI ready interrupt
lypinator	0:bb348c97df44	6890	* @rmtoll CIR LSIRDYIE LL_RCC_DisableIT_LSIRDY
lypinator	0:bb348c97df44	6891	* @retval None
lypinator	0:bb348c97df44	6892	*/
lypinator	0:bb348c97df44	6893	__STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void)
lypinator	0:bb348c97df44	6894	{
lypinator	0:bb348c97df44	6895	CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE);
lypinator	0:bb348c97df44	6896	}
lypinator	0:bb348c97df44	6897
lypinator	0:bb348c97df44	6898	/**
lypinator	0:bb348c97df44	6899	* @brief Disable LSE ready interrupt
lypinator	0:bb348c97df44	6900	* @rmtoll CIR LSERDYIE LL_RCC_DisableIT_LSERDY
lypinator	0:bb348c97df44	6901	* @retval None
lypinator	0:bb348c97df44	6902	*/
lypinator	0:bb348c97df44	6903	__STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)
lypinator	0:bb348c97df44	6904	{
lypinator	0:bb348c97df44	6905	CLEAR_BIT(RCC->CIR, RCC_CIR_LSERDYIE);
lypinator	0:bb348c97df44	6906	}
lypinator	0:bb348c97df44	6907
lypinator	0:bb348c97df44	6908	/**
lypinator	0:bb348c97df44	6909	* @brief Disable HSI ready interrupt
lypinator	0:bb348c97df44	6910	* @rmtoll CIR HSIRDYIE LL_RCC_DisableIT_HSIRDY
lypinator	0:bb348c97df44	6911	* @retval None
lypinator	0:bb348c97df44	6912	*/
lypinator	0:bb348c97df44	6913	__STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)
lypinator	0:bb348c97df44	6914	{
lypinator	0:bb348c97df44	6915	CLEAR_BIT(RCC->CIR, RCC_CIR_HSIRDYIE);
lypinator	0:bb348c97df44	6916	}
lypinator	0:bb348c97df44	6917
lypinator	0:bb348c97df44	6918	/**
lypinator	0:bb348c97df44	6919	* @brief Disable HSE ready interrupt
lypinator	0:bb348c97df44	6920	* @rmtoll CIR HSERDYIE LL_RCC_DisableIT_HSERDY
lypinator	0:bb348c97df44	6921	* @retval None
lypinator	0:bb348c97df44	6922	*/
lypinator	0:bb348c97df44	6923	__STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)
lypinator	0:bb348c97df44	6924	{
lypinator	0:bb348c97df44	6925	CLEAR_BIT(RCC->CIR, RCC_CIR_HSERDYIE);
lypinator	0:bb348c97df44	6926	}
lypinator	0:bb348c97df44	6927
lypinator	0:bb348c97df44	6928	/**
lypinator	0:bb348c97df44	6929	* @brief Disable PLL ready interrupt
lypinator	0:bb348c97df44	6930	* @rmtoll CIR PLLRDYIE LL_RCC_DisableIT_PLLRDY
lypinator	0:bb348c97df44	6931	* @retval None
lypinator	0:bb348c97df44	6932	*/
lypinator	0:bb348c97df44	6933	__STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void)
lypinator	0:bb348c97df44	6934	{
lypinator	0:bb348c97df44	6935	CLEAR_BIT(RCC->CIR, RCC_CIR_PLLRDYIE);
lypinator	0:bb348c97df44	6936	}
lypinator	0:bb348c97df44	6937
lypinator	0:bb348c97df44	6938	#if defined(RCC_PLLI2S_SUPPORT)
lypinator	0:bb348c97df44	6939	/**
lypinator	0:bb348c97df44	6940	* @brief Disable PLLI2S ready interrupt
lypinator	0:bb348c97df44	6941	* @rmtoll CIR PLLI2SRDYIE LL_RCC_DisableIT_PLLI2SRDY
lypinator	0:bb348c97df44	6942	* @retval None
lypinator	0:bb348c97df44	6943	*/
lypinator	0:bb348c97df44	6944	__STATIC_INLINE void LL_RCC_DisableIT_PLLI2SRDY(void)
lypinator	0:bb348c97df44	6945	{
lypinator	0:bb348c97df44	6946	CLEAR_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE);
lypinator	0:bb348c97df44	6947	}
lypinator	0:bb348c97df44	6948
lypinator	0:bb348c97df44	6949	#endif /* RCC_PLLI2S_SUPPORT */
lypinator	0:bb348c97df44	6950
lypinator	0:bb348c97df44	6951	#if defined(RCC_PLLSAI_SUPPORT)
lypinator	0:bb348c97df44	6952	/**
lypinator	0:bb348c97df44	6953	* @brief Disable PLLSAI ready interrupt
lypinator	0:bb348c97df44	6954	* @rmtoll CIR PLLSAIRDYIE LL_RCC_DisableIT_PLLSAIRDY
lypinator	0:bb348c97df44	6955	* @retval None
lypinator	0:bb348c97df44	6956	*/
lypinator	0:bb348c97df44	6957	__STATIC_INLINE void LL_RCC_DisableIT_PLLSAIRDY(void)
lypinator	0:bb348c97df44	6958	{
lypinator	0:bb348c97df44	6959	CLEAR_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE);
lypinator	0:bb348c97df44	6960	}
lypinator	0:bb348c97df44	6961	#endif /* RCC_PLLSAI_SUPPORT */
lypinator	0:bb348c97df44	6962
lypinator	0:bb348c97df44	6963	/**
lypinator	0:bb348c97df44	6964	* @brief Checks if LSI ready interrupt source is enabled or disabled.
lypinator	0:bb348c97df44	6965	* @rmtoll CIR LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY
lypinator	0:bb348c97df44	6966	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	6967	*/
lypinator	0:bb348c97df44	6968	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void)
lypinator	0:bb348c97df44	6969	{
lypinator	0:bb348c97df44	6970	return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYIE) == (RCC_CIR_LSIRDYIE));
lypinator	0:bb348c97df44	6971	}
lypinator	0:bb348c97df44	6972
lypinator	0:bb348c97df44	6973	/**
lypinator	0:bb348c97df44	6974	* @brief Checks if LSE ready interrupt source is enabled or disabled.
lypinator	0:bb348c97df44	6975	* @rmtoll CIR LSERDYIE LL_RCC_IsEnabledIT_LSERDY
lypinator	0:bb348c97df44	6976	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	6977	*/
lypinator	0:bb348c97df44	6978	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void)
lypinator	0:bb348c97df44	6979	{
lypinator	0:bb348c97df44	6980	return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYIE) == (RCC_CIR_LSERDYIE));
lypinator	0:bb348c97df44	6981	}
lypinator	0:bb348c97df44	6982
lypinator	0:bb348c97df44	6983	/**
lypinator	0:bb348c97df44	6984	* @brief Checks if HSI ready interrupt source is enabled or disabled.
lypinator	0:bb348c97df44	6985	* @rmtoll CIR HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY
lypinator	0:bb348c97df44	6986	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	6987	*/
lypinator	0:bb348c97df44	6988	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void)
lypinator	0:bb348c97df44	6989	{
lypinator	0:bb348c97df44	6990	return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYIE) == (RCC_CIR_HSIRDYIE));
lypinator	0:bb348c97df44	6991	}
lypinator	0:bb348c97df44	6992
lypinator	0:bb348c97df44	6993	/**
lypinator	0:bb348c97df44	6994	* @brief Checks if HSE ready interrupt source is enabled or disabled.
lypinator	0:bb348c97df44	6995	* @rmtoll CIR HSERDYIE LL_RCC_IsEnabledIT_HSERDY
lypinator	0:bb348c97df44	6996	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	6997	*/
lypinator	0:bb348c97df44	6998	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void)
lypinator	0:bb348c97df44	6999	{
lypinator	0:bb348c97df44	7000	return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYIE) == (RCC_CIR_HSERDYIE));
lypinator	0:bb348c97df44	7001	}
lypinator	0:bb348c97df44	7002
lypinator	0:bb348c97df44	7003	/**
lypinator	0:bb348c97df44	7004	* @brief Checks if PLL ready interrupt source is enabled or disabled.
lypinator	0:bb348c97df44	7005	* @rmtoll CIR PLLRDYIE LL_RCC_IsEnabledIT_PLLRDY
lypinator	0:bb348c97df44	7006	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	7007	*/
lypinator	0:bb348c97df44	7008	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void)
lypinator	0:bb348c97df44	7009	{
lypinator	0:bb348c97df44	7010	return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYIE) == (RCC_CIR_PLLRDYIE));
lypinator	0:bb348c97df44	7011	}
lypinator	0:bb348c97df44	7012
lypinator	0:bb348c97df44	7013	#if defined(RCC_PLLI2S_SUPPORT)
lypinator	0:bb348c97df44	7014	/**
lypinator	0:bb348c97df44	7015	* @brief Checks if PLLI2S ready interrupt source is enabled or disabled.
lypinator	0:bb348c97df44	7016	* @rmtoll CIR PLLI2SRDYIE LL_RCC_IsEnabledIT_PLLI2SRDY
lypinator	0:bb348c97df44	7017	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	7018	*/
lypinator	0:bb348c97df44	7019	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLI2SRDY(void)
lypinator	0:bb348c97df44	7020	{
lypinator	0:bb348c97df44	7021	return (READ_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE) == (RCC_CIR_PLLI2SRDYIE));
lypinator	0:bb348c97df44	7022	}
lypinator	0:bb348c97df44	7023
lypinator	0:bb348c97df44	7024	#endif /* RCC_PLLI2S_SUPPORT */
lypinator	0:bb348c97df44	7025
lypinator	0:bb348c97df44	7026	#if defined(RCC_PLLSAI_SUPPORT)
lypinator	0:bb348c97df44	7027	/**
lypinator	0:bb348c97df44	7028	* @brief Checks if PLLSAI ready interrupt source is enabled or disabled.
lypinator	0:bb348c97df44	7029	* @rmtoll CIR PLLSAIRDYIE LL_RCC_IsEnabledIT_PLLSAIRDY
lypinator	0:bb348c97df44	7030	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	7031	*/
lypinator	0:bb348c97df44	7032	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLSAIRDY(void)
lypinator	0:bb348c97df44	7033	{
lypinator	0:bb348c97df44	7034	return (READ_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE) == (RCC_CIR_PLLSAIRDYIE));
lypinator	0:bb348c97df44	7035	}
lypinator	0:bb348c97df44	7036	#endif /* RCC_PLLSAI_SUPPORT */
lypinator	0:bb348c97df44	7037
lypinator	0:bb348c97df44	7038	/**
lypinator	0:bb348c97df44	7039	* @}
lypinator	0:bb348c97df44	7040	*/
lypinator	0:bb348c97df44	7041
lypinator	0:bb348c97df44	7042	#if defined(USE_FULL_LL_DRIVER)
lypinator	0:bb348c97df44	7043	/** @defgroup RCC_LL_EF_Init De-initialization function
lypinator	0:bb348c97df44	7044	* @{
lypinator	0:bb348c97df44	7045	*/
lypinator	0:bb348c97df44	7046	ErrorStatus LL_RCC_DeInit(void);
lypinator	0:bb348c97df44	7047	/**
lypinator	0:bb348c97df44	7048	* @}
lypinator	0:bb348c97df44	7049	*/
lypinator	0:bb348c97df44	7050
lypinator	0:bb348c97df44	7051	/** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions
lypinator	0:bb348c97df44	7052	* @{
lypinator	0:bb348c97df44	7053	*/
lypinator	0:bb348c97df44	7054	void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);
lypinator	0:bb348c97df44	7055	#if defined(FMPI2C1)
lypinator	0:bb348c97df44	7056	uint32_t LL_RCC_GetFMPI2CClockFreq(uint32_t FMPI2CxSource);
lypinator	0:bb348c97df44	7057	#endif /* FMPI2C1 */
lypinator	0:bb348c97df44	7058	#if defined(LPTIM1)
lypinator	0:bb348c97df44	7059	uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource);
lypinator	0:bb348c97df44	7060	#endif /* LPTIM1 */
lypinator	0:bb348c97df44	7061	#if defined(SAI1)
lypinator	0:bb348c97df44	7062	uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource);
lypinator	0:bb348c97df44	7063	#endif /* SAI1 */
lypinator	0:bb348c97df44	7064	#if defined(SDIO)
lypinator	0:bb348c97df44	7065	uint32_t LL_RCC_GetSDIOClockFreq(uint32_t SDIOxSource);
lypinator	0:bb348c97df44	7066	#endif /* SDIO */
lypinator	0:bb348c97df44	7067	#if defined(RNG)
lypinator	0:bb348c97df44	7068	uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource);
lypinator	0:bb348c97df44	7069	#endif /* RNG */
lypinator	0:bb348c97df44	7070	#if defined(USB_OTG_FS) \|\| defined(USB_OTG_HS)
lypinator	0:bb348c97df44	7071	uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource);
lypinator	0:bb348c97df44	7072	#endif /* USB_OTG_FS \|\| USB_OTG_HS */
lypinator	0:bb348c97df44	7073	#if defined(DFSDM1_Channel0)
lypinator	0:bb348c97df44	7074	uint32_t LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource);
lypinator	0:bb348c97df44	7075	uint32_t LL_RCC_GetDFSDMAudioClockFreq(uint32_t DFSDMxSource);
lypinator	0:bb348c97df44	7076	#endif /* DFSDM1_Channel0 */
lypinator	0:bb348c97df44	7077	uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource);
lypinator	0:bb348c97df44	7078	#if defined(CEC)
lypinator	0:bb348c97df44	7079	uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource);
lypinator	0:bb348c97df44	7080	#endif /* CEC */
lypinator	0:bb348c97df44	7081	#if defined(LTDC)
lypinator	0:bb348c97df44	7082	uint32_t LL_RCC_GetLTDCClockFreq(uint32_t LTDCxSource);
lypinator	0:bb348c97df44	7083	#endif /* LTDC */
lypinator	0:bb348c97df44	7084	#if defined(SPDIFRX)
lypinator	0:bb348c97df44	7085	uint32_t LL_RCC_GetSPDIFRXClockFreq(uint32_t SPDIFRXxSource);
lypinator	0:bb348c97df44	7086	#endif /* SPDIFRX */
lypinator	0:bb348c97df44	7087	#if defined(DSI)
lypinator	0:bb348c97df44	7088	uint32_t LL_RCC_GetDSIClockFreq(uint32_t DSIxSource);
lypinator	0:bb348c97df44	7089	#endif /* DSI */
lypinator	0:bb348c97df44	7090	/**
lypinator	0:bb348c97df44	7091	* @}
lypinator	0:bb348c97df44	7092	*/
lypinator	0:bb348c97df44	7093	#endif /* USE_FULL_LL_DRIVER */
lypinator	0:bb348c97df44	7094
lypinator	0:bb348c97df44	7095	/**
lypinator	0:bb348c97df44	7096	* @}
lypinator	0:bb348c97df44	7097	*/
lypinator	0:bb348c97df44	7098
lypinator	0:bb348c97df44	7099	/**
lypinator	0:bb348c97df44	7100	* @}
lypinator	0:bb348c97df44	7101	*/
lypinator	0:bb348c97df44	7102
lypinator	0:bb348c97df44	7103	#endif /* defined(RCC) */
lypinator	0:bb348c97df44	7104
lypinator	0:bb348c97df44	7105	/**
lypinator	0:bb348c97df44	7106	* @}
lypinator	0:bb348c97df44	7107	*/
lypinator	0:bb348c97df44	7108
lypinator	0:bb348c97df44	7109	#ifdef __cplusplus
lypinator	0:bb348c97df44	7110	}
lypinator	0:bb348c97df44	7111	#endif
lypinator	0:bb348c97df44	7112
lypinator	0:bb348c97df44	7113	#endif /* __STM32F4xx_LL_RCC_H */
lypinator	0:bb348c97df44	7114
lypinator	0:bb348c97df44	7115	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Program
Created:	16 Sep 2020
Imports:	1
Forks:	0
Commits:	1
Dependents:	0
Dependencies:	1
Followers:	1

mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_rcc.h@0:bb348c97df44, 2020-09-16 (annotated)

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