Thomas Lyp / DevLibMemoryController

Initial commit

Dependencies:   FastPWM

mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_rcc.c@0:bb348c97df44, 2020-09-16 (annotated)

Committer:
lypinator
Date:
Wed Sep 16 01:11:49 2020 +0000
Revision:
0:bb348c97df44
Added PWM

Who changed what in which revision?

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lypinator 0:bb348c97df44 1 /**
lypinator 0:bb348c97df44 2 ******************************************************************************
lypinator 0:bb348c97df44 3 * @file stm32f4xx_ll_rcc.c
lypinator 0:bb348c97df44 4 * @author MCD Application Team
lypinator 0:bb348c97df44 5 * @brief RCC LL module driver.
lypinator 0:bb348c97df44 6 ******************************************************************************
lypinator 0:bb348c97df44 7 * @attention
lypinator 0:bb348c97df44 8 *
lypinator 0:bb348c97df44 9 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
lypinator 0:bb348c97df44 10 *
lypinator 0:bb348c97df44 11 * Redistribution and use in source and binary forms, with or without modification,
lypinator 0:bb348c97df44 12 * are permitted provided that the following conditions are met:
lypinator 0:bb348c97df44 13 * 1. Redistributions of source code must retain the above copyright notice,
lypinator 0:bb348c97df44 14 * this list of conditions and the following disclaimer.
lypinator 0:bb348c97df44 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
lypinator 0:bb348c97df44 16 * this list of conditions and the following disclaimer in the documentation
lypinator 0:bb348c97df44 17 * and/or other materials provided with the distribution.
lypinator 0:bb348c97df44 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
lypinator 0:bb348c97df44 19 * may be used to endorse or promote products derived from this software
lypinator 0:bb348c97df44 20 * without specific prior written permission.
lypinator 0:bb348c97df44 21 *
lypinator 0:bb348c97df44 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
lypinator 0:bb348c97df44 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
lypinator 0:bb348c97df44 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
lypinator 0:bb348c97df44 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
lypinator 0:bb348c97df44 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
lypinator 0:bb348c97df44 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
lypinator 0:bb348c97df44 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
lypinator 0:bb348c97df44 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
lypinator 0:bb348c97df44 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
lypinator 0:bb348c97df44 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
lypinator 0:bb348c97df44 32 *
lypinator 0:bb348c97df44 33 ******************************************************************************
lypinator 0:bb348c97df44 34 */
lypinator 0:bb348c97df44 35 #if defined(USE_FULL_LL_DRIVER)
lypinator 0:bb348c97df44 36
lypinator 0:bb348c97df44 37 /* Includes ------------------------------------------------------------------*/
lypinator 0:bb348c97df44 38 #include "stm32f4xx_ll_rcc.h"
lypinator 0:bb348c97df44 39 #ifdef USE_FULL_ASSERT
lypinator 0:bb348c97df44 40 #include "stm32_assert.h"
lypinator 0:bb348c97df44 41 #else
lypinator 0:bb348c97df44 42 #define assert_param(expr) ((void)0U)
lypinator 0:bb348c97df44 43 #endif
lypinator 0:bb348c97df44 44 /** @addtogroup STM32F4xx_LL_Driver
lypinator 0:bb348c97df44 45 * @{
lypinator 0:bb348c97df44 46 */
lypinator 0:bb348c97df44 47
lypinator 0:bb348c97df44 48 #if defined(RCC)
lypinator 0:bb348c97df44 49
lypinator 0:bb348c97df44 50 /** @addtogroup RCC_LL
lypinator 0:bb348c97df44 51 * @{
lypinator 0:bb348c97df44 52 */
lypinator 0:bb348c97df44 53
lypinator 0:bb348c97df44 54 /* Private types -------------------------------------------------------------*/
lypinator 0:bb348c97df44 55 /* Private variables ---------------------------------------------------------*/
lypinator 0:bb348c97df44 56 /* Private constants ---------------------------------------------------------*/
lypinator 0:bb348c97df44 57 /* Private macros ------------------------------------------------------------*/
lypinator 0:bb348c97df44 58 /** @addtogroup RCC_LL_Private_Macros
lypinator 0:bb348c97df44 59 * @{
lypinator 0:bb348c97df44 60 */
lypinator 0:bb348c97df44 61 #if defined(FMPI2C1)
lypinator 0:bb348c97df44 62 #define IS_LL_RCC_FMPI2C_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_FMPI2C1_CLKSOURCE)
lypinator 0:bb348c97df44 63 #endif /* FMPI2C1 */
lypinator 0:bb348c97df44 64
lypinator 0:bb348c97df44 65 #if defined(LPTIM1)
lypinator 0:bb348c97df44 66 #define IS_LL_RCC_LPTIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LPTIM1_CLKSOURCE))
lypinator 0:bb348c97df44 67 #endif /* LPTIM1 */
lypinator 0:bb348c97df44 68
lypinator 0:bb348c97df44 69 #if defined(SAI1)
lypinator 0:bb348c97df44 70 #if defined(RCC_DCKCFGR_SAI1SRC)
lypinator 0:bb348c97df44 71 #define IS_LL_RCC_SAI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SAI1_CLKSOURCE) \
lypinator 0:bb348c97df44 72 || ((__VALUE__) == LL_RCC_SAI2_CLKSOURCE))
lypinator 0:bb348c97df44 73 #elif defined(RCC_DCKCFGR_SAI1ASRC)
lypinator 0:bb348c97df44 74 #define IS_LL_RCC_SAI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SAI1_A_CLKSOURCE) \
lypinator 0:bb348c97df44 75 || ((__VALUE__) == LL_RCC_SAI1_B_CLKSOURCE))
lypinator 0:bb348c97df44 76 #endif /* RCC_DCKCFGR_SAI1SRC */
lypinator 0:bb348c97df44 77 #endif /* SAI1 */
lypinator 0:bb348c97df44 78
lypinator 0:bb348c97df44 79 #if defined(SDIO)
lypinator 0:bb348c97df44 80 #define IS_LL_RCC_SDIO_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SDIO_CLKSOURCE))
lypinator 0:bb348c97df44 81 #endif /* SDIO */
lypinator 0:bb348c97df44 82
lypinator 0:bb348c97df44 83 #if defined(RNG)
lypinator 0:bb348c97df44 84 #define IS_LL_RCC_RNG_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_RNG_CLKSOURCE))
lypinator 0:bb348c97df44 85 #endif /* RNG */
lypinator 0:bb348c97df44 86
lypinator 0:bb348c97df44 87 #if defined(USB_OTG_FS) || defined(USB_OTG_HS)
lypinator 0:bb348c97df44 88 #define IS_LL_RCC_USB_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USB_CLKSOURCE))
lypinator 0:bb348c97df44 89 #endif /* USB_OTG_FS || USB_OTG_HS */
lypinator 0:bb348c97df44 90
lypinator 0:bb348c97df44 91 #if defined(DFSDM2_Channel0)
lypinator 0:bb348c97df44 92 #define IS_LL_RCC_DFSDM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_DFSDM1_CLKSOURCE))
lypinator 0:bb348c97df44 93
lypinator 0:bb348c97df44 94 #define IS_LL_RCC_DFSDM_AUDIO_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_DFSDM1_AUDIO_CLKSOURCE) \
lypinator 0:bb348c97df44 95 || ((__VALUE__) == LL_RCC_DFSDM2_AUDIO_CLKSOURCE))
lypinator 0:bb348c97df44 96 #elif defined(DFSDM1_Channel0)
lypinator 0:bb348c97df44 97 #define IS_LL_RCC_DFSDM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_DFSDM1_CLKSOURCE))
lypinator 0:bb348c97df44 98
lypinator 0:bb348c97df44 99 #define IS_LL_RCC_DFSDM_AUDIO_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_DFSDM1_AUDIO_CLKSOURCE))
lypinator 0:bb348c97df44 100 #endif /* DFSDM2_Channel0 */
lypinator 0:bb348c97df44 101
lypinator 0:bb348c97df44 102 #if defined(RCC_DCKCFGR_I2S2SRC)
lypinator 0:bb348c97df44 103 #define IS_LL_RCC_I2S_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2S1_CLKSOURCE) \
lypinator 0:bb348c97df44 104 || ((__VALUE__) == LL_RCC_I2S2_CLKSOURCE))
lypinator 0:bb348c97df44 105 #else
lypinator 0:bb348c97df44 106 #define IS_LL_RCC_I2S_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2S1_CLKSOURCE))
lypinator 0:bb348c97df44 107 #endif /* RCC_DCKCFGR_I2S2SRC */
lypinator 0:bb348c97df44 108
lypinator 0:bb348c97df44 109 #if defined(CEC)
lypinator 0:bb348c97df44 110 #define IS_LL_RCC_CEC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_CEC_CLKSOURCE))
lypinator 0:bb348c97df44 111 #endif /* CEC */
lypinator 0:bb348c97df44 112
lypinator 0:bb348c97df44 113 #if defined(DSI)
lypinator 0:bb348c97df44 114 #define IS_LL_RCC_DSI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_DSI_CLKSOURCE))
lypinator 0:bb348c97df44 115 #endif /* DSI */
lypinator 0:bb348c97df44 116
lypinator 0:bb348c97df44 117 #if defined(LTDC)
lypinator 0:bb348c97df44 118 #define IS_LL_RCC_LTDC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LTDC_CLKSOURCE))
lypinator 0:bb348c97df44 119 #endif /* LTDC */
lypinator 0:bb348c97df44 120
lypinator 0:bb348c97df44 121 #if defined(SPDIFRX)
lypinator 0:bb348c97df44 122 #define IS_LL_RCC_SPDIFRX_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SPDIFRX1_CLKSOURCE))
lypinator 0:bb348c97df44 123 #endif /* SPDIFRX */
lypinator 0:bb348c97df44 124 /**
lypinator 0:bb348c97df44 125 * @}
lypinator 0:bb348c97df44 126 */
lypinator 0:bb348c97df44 127
lypinator 0:bb348c97df44 128 /* Private function prototypes -----------------------------------------------*/
lypinator 0:bb348c97df44 129 /** @defgroup RCC_LL_Private_Functions RCC Private functions
lypinator 0:bb348c97df44 130 * @{
lypinator 0:bb348c97df44 131 */
lypinator 0:bb348c97df44 132 uint32_t RCC_GetSystemClockFreq(void);
lypinator 0:bb348c97df44 133 uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency);
lypinator 0:bb348c97df44 134 uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency);
lypinator 0:bb348c97df44 135 uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency);
lypinator 0:bb348c97df44 136 uint32_t RCC_PLL_GetFreqDomain_SYS(uint32_t SYSCLK_Source);
lypinator 0:bb348c97df44 137 uint32_t RCC_PLL_GetFreqDomain_48M(void);
lypinator 0:bb348c97df44 138 #if defined(RCC_DCKCFGR_I2SSRC) || defined(RCC_DCKCFGR_I2S1SRC)
lypinator 0:bb348c97df44 139 uint32_t RCC_PLL_GetFreqDomain_I2S(void);
lypinator 0:bb348c97df44 140 #endif /* RCC_DCKCFGR_I2SSRC || RCC_DCKCFGR_I2S1SRC */
lypinator 0:bb348c97df44 141 #if defined(SPDIFRX)
lypinator 0:bb348c97df44 142 uint32_t RCC_PLL_GetFreqDomain_SPDIFRX(void);
lypinator 0:bb348c97df44 143 #endif /* SPDIFRX */
lypinator 0:bb348c97df44 144 #if defined(RCC_PLLCFGR_PLLR)
lypinator 0:bb348c97df44 145 #if defined(SAI1)
lypinator 0:bb348c97df44 146 uint32_t RCC_PLL_GetFreqDomain_SAI(void);
lypinator 0:bb348c97df44 147 #endif /* SAI1 */
lypinator 0:bb348c97df44 148 #endif /* RCC_PLLCFGR_PLLR */
lypinator 0:bb348c97df44 149 #if defined(DSI)
lypinator 0:bb348c97df44 150 uint32_t RCC_PLL_GetFreqDomain_DSI(void);
lypinator 0:bb348c97df44 151 #endif /* DSI */
lypinator 0:bb348c97df44 152 #if defined(RCC_PLLSAI_SUPPORT)
lypinator 0:bb348c97df44 153 uint32_t RCC_PLLSAI_GetFreqDomain_SAI(void);
lypinator 0:bb348c97df44 154 #if defined(RCC_PLLSAICFGR_PLLSAIP)
lypinator 0:bb348c97df44 155 uint32_t RCC_PLLSAI_GetFreqDomain_48M(void);
lypinator 0:bb348c97df44 156 #endif /* RCC_PLLSAICFGR_PLLSAIP */
lypinator 0:bb348c97df44 157 #if defined(LTDC)
lypinator 0:bb348c97df44 158 uint32_t RCC_PLLSAI_GetFreqDomain_LTDC(void);
lypinator 0:bb348c97df44 159 #endif /* LTDC */
lypinator 0:bb348c97df44 160 #endif /* RCC_PLLSAI_SUPPORT */
lypinator 0:bb348c97df44 161 #if defined(RCC_PLLI2S_SUPPORT)
lypinator 0:bb348c97df44 162 uint32_t RCC_PLLI2S_GetFreqDomain_I2S(void);
lypinator 0:bb348c97df44 163 #if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
lypinator 0:bb348c97df44 164 uint32_t RCC_PLLI2S_GetFreqDomain_48M(void);
lypinator 0:bb348c97df44 165 #endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
lypinator 0:bb348c97df44 166 #if defined(SAI1)
lypinator 0:bb348c97df44 167 uint32_t RCC_PLLI2S_GetFreqDomain_SAI(void);
lypinator 0:bb348c97df44 168 #endif /* SAI1 */
lypinator 0:bb348c97df44 169 #if defined(SPDIFRX)
lypinator 0:bb348c97df44 170 uint32_t RCC_PLLI2S_GetFreqDomain_SPDIFRX(void);
lypinator 0:bb348c97df44 171 #endif /* SPDIFRX */
lypinator 0:bb348c97df44 172 #endif /* RCC_PLLI2S_SUPPORT */
lypinator 0:bb348c97df44 173 /**
lypinator 0:bb348c97df44 174 * @}
lypinator 0:bb348c97df44 175 */
lypinator 0:bb348c97df44 176
lypinator 0:bb348c97df44 177
lypinator 0:bb348c97df44 178 /* Exported functions --------------------------------------------------------*/
lypinator 0:bb348c97df44 179 /** @addtogroup RCC_LL_Exported_Functions
lypinator 0:bb348c97df44 180 * @{
lypinator 0:bb348c97df44 181 */
lypinator 0:bb348c97df44 182
lypinator 0:bb348c97df44 183 /** @addtogroup RCC_LL_EF_Init
lypinator 0:bb348c97df44 184 * @{
lypinator 0:bb348c97df44 185 */
lypinator 0:bb348c97df44 186
lypinator 0:bb348c97df44 187 /**
lypinator 0:bb348c97df44 188 * @brief Reset the RCC clock configuration to the default reset state.
lypinator 0:bb348c97df44 189 * @note The default reset state of the clock configuration is given below:
lypinator 0:bb348c97df44 190 * - HSI ON and used as system clock source
lypinator 0:bb348c97df44 191 * - HSE and PLL OFF
lypinator 0:bb348c97df44 192 * - AHB, APB1 and APB2 prescaler set to 1.
lypinator 0:bb348c97df44 193 * - CSS, MCO OFF
lypinator 0:bb348c97df44 194 * - All interrupts disabled
lypinator 0:bb348c97df44 195 * @note This function doesn't modify the configuration of the
lypinator 0:bb348c97df44 196 * - Peripheral clocks
lypinator 0:bb348c97df44 197 * - LSI, LSE and RTC clocks
lypinator 0:bb348c97df44 198 * @retval An ErrorStatus enumeration value:
lypinator 0:bb348c97df44 199 * - SUCCESS: RCC registers are de-initialized
lypinator 0:bb348c97df44 200 * - ERROR: not applicable
lypinator 0:bb348c97df44 201 */
lypinator 0:bb348c97df44 202 ErrorStatus LL_RCC_DeInit(void)
lypinator 0:bb348c97df44 203 {
lypinator 0:bb348c97df44 204 uint32_t vl_mask = 0U;
lypinator 0:bb348c97df44 205
lypinator 0:bb348c97df44 206 /* Set HSION bit */
lypinator 0:bb348c97df44 207 LL_RCC_HSI_Enable();
lypinator 0:bb348c97df44 208
lypinator 0:bb348c97df44 209 /* Wait for HSI READY bit */
lypinator 0:bb348c97df44 210 while(LL_RCC_HSI_IsReady() != 1U)
lypinator 0:bb348c97df44 211 {}
lypinator 0:bb348c97df44 212
lypinator 0:bb348c97df44 213 /* Reset CFGR register */
lypinator 0:bb348c97df44 214 LL_RCC_WriteReg(CFGR, 0x00000000U);
lypinator 0:bb348c97df44 215
lypinator 0:bb348c97df44 216 vl_mask = 0xFFFFFFFFU;
lypinator 0:bb348c97df44 217
lypinator 0:bb348c97df44 218 /* Reset HSEON, PLLSYSON bits */
lypinator 0:bb348c97df44 219 CLEAR_BIT(vl_mask, (RCC_CR_HSEON | RCC_CR_HSEBYP | RCC_CR_PLLON | RCC_CR_CSSON));
lypinator 0:bb348c97df44 220
lypinator 0:bb348c97df44 221 #if defined(RCC_PLLSAI_SUPPORT)
lypinator 0:bb348c97df44 222 /* Reset PLLSAION bit */
lypinator 0:bb348c97df44 223 CLEAR_BIT(vl_mask, RCC_CR_PLLSAION);
lypinator 0:bb348c97df44 224 #endif /* RCC_PLLSAI_SUPPORT */
lypinator 0:bb348c97df44 225
lypinator 0:bb348c97df44 226 #if defined(RCC_PLLI2S_SUPPORT)
lypinator 0:bb348c97df44 227 /* Reset PLLI2SON bit */
lypinator 0:bb348c97df44 228 CLEAR_BIT(vl_mask, RCC_CR_PLLI2SON);
lypinator 0:bb348c97df44 229 #endif /* RCC_PLLI2S_SUPPORT */
lypinator 0:bb348c97df44 230
lypinator 0:bb348c97df44 231 /* Write new mask in CR register */
lypinator 0:bb348c97df44 232 LL_RCC_WriteReg(CR, vl_mask);
lypinator 0:bb348c97df44 233
lypinator 0:bb348c97df44 234 /* Set HSITRIM bits to the reset value*/
lypinator 0:bb348c97df44 235 LL_RCC_HSI_SetCalibTrimming(0x10U);
lypinator 0:bb348c97df44 236
lypinator 0:bb348c97df44 237 /* Wait for PLL READY bit to be reset */
lypinator 0:bb348c97df44 238 while(LL_RCC_PLL_IsReady() != 0U)
lypinator 0:bb348c97df44 239 {}
lypinator 0:bb348c97df44 240
lypinator 0:bb348c97df44 241 /* Reset PLLCFGR register */
lypinator 0:bb348c97df44 242 LL_RCC_WriteReg(PLLCFGR, RCC_PLLCFGR_RST_VALUE);
lypinator 0:bb348c97df44 243
lypinator 0:bb348c97df44 244 #if defined(RCC_PLLI2S_SUPPORT)
lypinator 0:bb348c97df44 245 /* Reset PLLI2SCFGR register */
lypinator 0:bb348c97df44 246 LL_RCC_WriteReg(PLLI2SCFGR, RCC_PLLI2SCFGR_RST_VALUE);
lypinator 0:bb348c97df44 247 #endif /* RCC_PLLI2S_SUPPORT */
lypinator 0:bb348c97df44 248
lypinator 0:bb348c97df44 249 #if defined(RCC_PLLSAI_SUPPORT)
lypinator 0:bb348c97df44 250 /* Reset PLLSAICFGR register */
lypinator 0:bb348c97df44 251 LL_RCC_WriteReg(PLLSAICFGR, RCC_PLLSAICFGR_RST_VALUE);
lypinator 0:bb348c97df44 252 #endif /* RCC_PLLSAI_SUPPORT */
lypinator 0:bb348c97df44 253
lypinator 0:bb348c97df44 254 /* Disable all interrupts */
lypinator 0:bb348c97df44 255 CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE | RCC_CIR_LSERDYIE | RCC_CIR_HSIRDYIE | RCC_CIR_HSERDYIE | RCC_CIR_PLLRDYIE);
lypinator 0:bb348c97df44 256
lypinator 0:bb348c97df44 257 #if defined(RCC_CIR_PLLI2SRDYIE)
lypinator 0:bb348c97df44 258 CLEAR_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE);
lypinator 0:bb348c97df44 259 #endif /* RCC_CIR_PLLI2SRDYIE */
lypinator 0:bb348c97df44 260
lypinator 0:bb348c97df44 261 #if defined(RCC_CIR_PLLSAIRDYIE)
lypinator 0:bb348c97df44 262 CLEAR_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE);
lypinator 0:bb348c97df44 263 #endif /* RCC_CIR_PLLSAIRDYIE */
lypinator 0:bb348c97df44 264
lypinator 0:bb348c97df44 265 /* Clear all interrupt flags */
lypinator 0:bb348c97df44 266 SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC | RCC_CIR_LSERDYC | RCC_CIR_HSIRDYC | RCC_CIR_HSERDYC | RCC_CIR_PLLRDYC | RCC_CIR_CSSC);
lypinator 0:bb348c97df44 267
lypinator 0:bb348c97df44 268 #if defined(RCC_CIR_PLLI2SRDYC)
lypinator 0:bb348c97df44 269 SET_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYC);
lypinator 0:bb348c97df44 270 #endif /* RCC_CIR_PLLI2SRDYC */
lypinator 0:bb348c97df44 271
lypinator 0:bb348c97df44 272 #if defined(RCC_CIR_PLLSAIRDYC)
lypinator 0:bb348c97df44 273 SET_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYC);
lypinator 0:bb348c97df44 274 #endif /* RCC_CIR_PLLSAIRDYC */
lypinator 0:bb348c97df44 275
lypinator 0:bb348c97df44 276 /* Clear LSION bit */
lypinator 0:bb348c97df44 277 CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
lypinator 0:bb348c97df44 278
lypinator 0:bb348c97df44 279 /* Reset all CSR flags */
lypinator 0:bb348c97df44 280 SET_BIT(RCC->CSR, RCC_CSR_RMVF);
lypinator 0:bb348c97df44 281
lypinator 0:bb348c97df44 282 return SUCCESS;
lypinator 0:bb348c97df44 283 }
lypinator 0:bb348c97df44 284
lypinator 0:bb348c97df44 285 /**
lypinator 0:bb348c97df44 286 * @}
lypinator 0:bb348c97df44 287 */
lypinator 0:bb348c97df44 288
lypinator 0:bb348c97df44 289 /** @addtogroup RCC_LL_EF_Get_Freq
lypinator 0:bb348c97df44 290 * @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks
lypinator 0:bb348c97df44 291 * and different peripheral clocks available on the device.
lypinator 0:bb348c97df44 292 * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(**)
lypinator 0:bb348c97df44 293 * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(***)
lypinator 0:bb348c97df44 294 * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(***)
lypinator 0:bb348c97df44 295 * or HSI_VALUE(**) multiplied/divided by the PLL factors.
lypinator 0:bb348c97df44 296 * @note (**) HSI_VALUE is a constant defined in this file (default value
lypinator 0:bb348c97df44 297 * 16 MHz) but the real value may vary depending on the variations
lypinator 0:bb348c97df44 298 * in voltage and temperature.
lypinator 0:bb348c97df44 299 * @note (***) HSE_VALUE is a constant defined in this file (default value
lypinator 0:bb348c97df44 300 * 25 MHz), user has to ensure that HSE_VALUE is same as the real
lypinator 0:bb348c97df44 301 * frequency of the crystal used. Otherwise, this function may
lypinator 0:bb348c97df44 302 * have wrong result.
lypinator 0:bb348c97df44 303 * @note The result of this function could be incorrect when using fractional
lypinator 0:bb348c97df44 304 * value for HSE crystal.
lypinator 0:bb348c97df44 305 * @note This function can be used by the user application to compute the
lypinator 0:bb348c97df44 306 * baud-rate for the communication peripherals or configure other parameters.
lypinator 0:bb348c97df44 307 * @{
lypinator 0:bb348c97df44 308 */
lypinator 0:bb348c97df44 309
lypinator 0:bb348c97df44 310 /**
lypinator 0:bb348c97df44 311 * @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks
lypinator 0:bb348c97df44 312 * @note Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function
lypinator 0:bb348c97df44 313 * must be called to update structure fields. Otherwise, any
lypinator 0:bb348c97df44 314 * configuration based on this function will be incorrect.
lypinator 0:bb348c97df44 315 * @param RCC_Clocks pointer to a @ref LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies
lypinator 0:bb348c97df44 316 * @retval None
lypinator 0:bb348c97df44 317 */
lypinator 0:bb348c97df44 318 void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks)
lypinator 0:bb348c97df44 319 {
lypinator 0:bb348c97df44 320 /* Get SYSCLK frequency */
lypinator 0:bb348c97df44 321 RCC_Clocks->SYSCLK_Frequency = RCC_GetSystemClockFreq();
lypinator 0:bb348c97df44 322
lypinator 0:bb348c97df44 323 /* HCLK clock frequency */
lypinator 0:bb348c97df44 324 RCC_Clocks->HCLK_Frequency = RCC_GetHCLKClockFreq(RCC_Clocks->SYSCLK_Frequency);
lypinator 0:bb348c97df44 325
lypinator 0:bb348c97df44 326 /* PCLK1 clock frequency */
lypinator 0:bb348c97df44 327 RCC_Clocks->PCLK1_Frequency = RCC_GetPCLK1ClockFreq(RCC_Clocks->HCLK_Frequency);
lypinator 0:bb348c97df44 328
lypinator 0:bb348c97df44 329 /* PCLK2 clock frequency */
lypinator 0:bb348c97df44 330 RCC_Clocks->PCLK2_Frequency = RCC_GetPCLK2ClockFreq(RCC_Clocks->HCLK_Frequency);
lypinator 0:bb348c97df44 331 }
lypinator 0:bb348c97df44 332
lypinator 0:bb348c97df44 333 #if defined(FMPI2C1)
lypinator 0:bb348c97df44 334 /**
lypinator 0:bb348c97df44 335 * @brief Return FMPI2Cx clock frequency
lypinator 0:bb348c97df44 336 * @param FMPI2CxSource This parameter can be one of the following values:
lypinator 0:bb348c97df44 337 * @arg @ref LL_RCC_FMPI2C1_CLKSOURCE
lypinator 0:bb348c97df44 338 * @retval FMPI2C clock frequency (in Hz)
lypinator 0:bb348c97df44 339 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that HSI oscillator is not ready
lypinator 0:bb348c97df44 340 */
lypinator 0:bb348c97df44 341 uint32_t LL_RCC_GetFMPI2CClockFreq(uint32_t FMPI2CxSource)
lypinator 0:bb348c97df44 342 {
lypinator 0:bb348c97df44 343 uint32_t FMPI2C_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
lypinator 0:bb348c97df44 344
lypinator 0:bb348c97df44 345 /* Check parameter */
lypinator 0:bb348c97df44 346 assert_param(IS_LL_RCC_FMPI2C_CLKSOURCE(FMPI2CxSource));
lypinator 0:bb348c97df44 347
lypinator 0:bb348c97df44 348 if (FMPI2CxSource == LL_RCC_FMPI2C1_CLKSOURCE)
lypinator 0:bb348c97df44 349 {
lypinator 0:bb348c97df44 350 /* FMPI2C1 CLK clock frequency */
lypinator 0:bb348c97df44 351 switch (LL_RCC_GetFMPI2CClockSource(FMPI2CxSource))
lypinator 0:bb348c97df44 352 {
lypinator 0:bb348c97df44 353 case LL_RCC_FMPI2C1_CLKSOURCE_SYSCLK: /* FMPI2C1 Clock is System Clock */
lypinator 0:bb348c97df44 354 FMPI2C_frequency = RCC_GetSystemClockFreq();
lypinator 0:bb348c97df44 355 break;
lypinator 0:bb348c97df44 356
lypinator 0:bb348c97df44 357 case LL_RCC_FMPI2C1_CLKSOURCE_HSI: /* FMPI2C1 Clock is HSI Osc. */
lypinator 0:bb348c97df44 358 if (LL_RCC_HSI_IsReady())
lypinator 0:bb348c97df44 359 {
lypinator 0:bb348c97df44 360 FMPI2C_frequency = HSI_VALUE;
lypinator 0:bb348c97df44 361 }
lypinator 0:bb348c97df44 362 break;
lypinator 0:bb348c97df44 363
lypinator 0:bb348c97df44 364 case LL_RCC_FMPI2C1_CLKSOURCE_PCLK1: /* FMPI2C1 Clock is PCLK1 */
lypinator 0:bb348c97df44 365 default:
lypinator 0:bb348c97df44 366 FMPI2C_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
lypinator 0:bb348c97df44 367 break;
lypinator 0:bb348c97df44 368 }
lypinator 0:bb348c97df44 369 }
lypinator 0:bb348c97df44 370
lypinator 0:bb348c97df44 371 return FMPI2C_frequency;
lypinator 0:bb348c97df44 372 }
lypinator 0:bb348c97df44 373 #endif /* FMPI2C1 */
lypinator 0:bb348c97df44 374
lypinator 0:bb348c97df44 375 /**
lypinator 0:bb348c97df44 376 * @brief Return I2Sx clock frequency
lypinator 0:bb348c97df44 377 * @param I2SxSource This parameter can be one of the following values:
lypinator 0:bb348c97df44 378 * @arg @ref LL_RCC_I2S1_CLKSOURCE
lypinator 0:bb348c97df44 379 * @arg @ref LL_RCC_I2S2_CLKSOURCE (*)
lypinator 0:bb348c97df44 380 *
lypinator 0:bb348c97df44 381 * (*) value not defined in all devices.
lypinator 0:bb348c97df44 382 * @retval I2S clock frequency (in Hz)
lypinator 0:bb348c97df44 383 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
lypinator 0:bb348c97df44 384 */
lypinator 0:bb348c97df44 385 uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource)
lypinator 0:bb348c97df44 386 {
lypinator 0:bb348c97df44 387 uint32_t i2s_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
lypinator 0:bb348c97df44 388
lypinator 0:bb348c97df44 389 /* Check parameter */
lypinator 0:bb348c97df44 390 assert_param(IS_LL_RCC_I2S_CLKSOURCE(I2SxSource));
lypinator 0:bb348c97df44 391
lypinator 0:bb348c97df44 392 if (I2SxSource == LL_RCC_I2S1_CLKSOURCE)
lypinator 0:bb348c97df44 393 {
lypinator 0:bb348c97df44 394 /* I2S1 CLK clock frequency */
lypinator 0:bb348c97df44 395 switch (LL_RCC_GetI2SClockSource(I2SxSource))
lypinator 0:bb348c97df44 396 {
lypinator 0:bb348c97df44 397 #if defined(RCC_PLLI2S_SUPPORT)
lypinator 0:bb348c97df44 398 case LL_RCC_I2S1_CLKSOURCE_PLLI2S: /* I2S1 Clock is PLLI2S */
lypinator 0:bb348c97df44 399 if (LL_RCC_PLLI2S_IsReady())
lypinator 0:bb348c97df44 400 {
lypinator 0:bb348c97df44 401 i2s_frequency = RCC_PLLI2S_GetFreqDomain_I2S();
lypinator 0:bb348c97df44 402 }
lypinator 0:bb348c97df44 403 break;
lypinator 0:bb348c97df44 404 #endif /* RCC_PLLI2S_SUPPORT */
lypinator 0:bb348c97df44 405
lypinator 0:bb348c97df44 406 #if defined(RCC_DCKCFGR_I2SSRC) || defined(RCC_DCKCFGR_I2S1SRC)
lypinator 0:bb348c97df44 407 case LL_RCC_I2S1_CLKSOURCE_PLL: /* I2S1 Clock is PLL */
lypinator 0:bb348c97df44 408 if (LL_RCC_PLL_IsReady())
lypinator 0:bb348c97df44 409 {
lypinator 0:bb348c97df44 410 i2s_frequency = RCC_PLL_GetFreqDomain_I2S();
lypinator 0:bb348c97df44 411 }
lypinator 0:bb348c97df44 412 break;
lypinator 0:bb348c97df44 413
lypinator 0:bb348c97df44 414 case LL_RCC_I2S1_CLKSOURCE_PLLSRC: /* I2S1 Clock is PLL Main source */
lypinator 0:bb348c97df44 415 switch (LL_RCC_PLL_GetMainSource())
lypinator 0:bb348c97df44 416 {
lypinator 0:bb348c97df44 417 case LL_RCC_PLLSOURCE_HSE: /* I2S1 Clock is HSE Osc. */
lypinator 0:bb348c97df44 418 if (LL_RCC_HSE_IsReady())
lypinator 0:bb348c97df44 419 {
lypinator 0:bb348c97df44 420 i2s_frequency = HSE_VALUE;
lypinator 0:bb348c97df44 421 }
lypinator 0:bb348c97df44 422 break;
lypinator 0:bb348c97df44 423
lypinator 0:bb348c97df44 424 case LL_RCC_PLLSOURCE_HSI: /* I2S1 Clock is HSI Osc. */
lypinator 0:bb348c97df44 425 default:
lypinator 0:bb348c97df44 426 if (LL_RCC_HSI_IsReady())
lypinator 0:bb348c97df44 427 {
lypinator 0:bb348c97df44 428 i2s_frequency = HSI_VALUE;
lypinator 0:bb348c97df44 429 }
lypinator 0:bb348c97df44 430 break;
lypinator 0:bb348c97df44 431 }
lypinator 0:bb348c97df44 432 break;
lypinator 0:bb348c97df44 433 #endif /* RCC_DCKCFGR_I2SSRC || RCC_DCKCFGR_I2S1SRC */
lypinator 0:bb348c97df44 434
lypinator 0:bb348c97df44 435 case LL_RCC_I2S1_CLKSOURCE_PIN: /* I2S1 Clock is External clock */
lypinator 0:bb348c97df44 436 default:
lypinator 0:bb348c97df44 437 i2s_frequency = EXTERNAL_CLOCK_VALUE;
lypinator 0:bb348c97df44 438 break;
lypinator 0:bb348c97df44 439 }
lypinator 0:bb348c97df44 440 }
lypinator 0:bb348c97df44 441 #if defined(RCC_DCKCFGR_I2S2SRC)
lypinator 0:bb348c97df44 442 else
lypinator 0:bb348c97df44 443 {
lypinator 0:bb348c97df44 444 /* I2S2 CLK clock frequency */
lypinator 0:bb348c97df44 445 switch (LL_RCC_GetI2SClockSource(I2SxSource))
lypinator 0:bb348c97df44 446 {
lypinator 0:bb348c97df44 447 case LL_RCC_I2S2_CLKSOURCE_PLLI2S: /* I2S2 Clock is PLLI2S */
lypinator 0:bb348c97df44 448 if (LL_RCC_PLLI2S_IsReady())
lypinator 0:bb348c97df44 449 {
lypinator 0:bb348c97df44 450 i2s_frequency = RCC_PLLI2S_GetFreqDomain_I2S();
lypinator 0:bb348c97df44 451 }
lypinator 0:bb348c97df44 452 break;
lypinator 0:bb348c97df44 453
lypinator 0:bb348c97df44 454 case LL_RCC_I2S2_CLKSOURCE_PLL: /* I2S2 Clock is PLL */
lypinator 0:bb348c97df44 455 if (LL_RCC_PLL_IsReady())
lypinator 0:bb348c97df44 456 {
lypinator 0:bb348c97df44 457 i2s_frequency = RCC_PLL_GetFreqDomain_I2S();
lypinator 0:bb348c97df44 458 }
lypinator 0:bb348c97df44 459 break;
lypinator 0:bb348c97df44 460
lypinator 0:bb348c97df44 461 case LL_RCC_I2S2_CLKSOURCE_PLLSRC: /* I2S2 Clock is PLL Main source */
lypinator 0:bb348c97df44 462 switch (LL_RCC_PLL_GetMainSource())
lypinator 0:bb348c97df44 463 {
lypinator 0:bb348c97df44 464 case LL_RCC_PLLSOURCE_HSE: /* I2S2 Clock is HSE Osc. */
lypinator 0:bb348c97df44 465 if (LL_RCC_HSE_IsReady())
lypinator 0:bb348c97df44 466 {
lypinator 0:bb348c97df44 467 i2s_frequency = HSE_VALUE;
lypinator 0:bb348c97df44 468 }
lypinator 0:bb348c97df44 469 break;
lypinator 0:bb348c97df44 470
lypinator 0:bb348c97df44 471 case LL_RCC_PLLSOURCE_HSI: /* I2S2 Clock is HSI Osc. */
lypinator 0:bb348c97df44 472 default:
lypinator 0:bb348c97df44 473 if (LL_RCC_HSI_IsReady())
lypinator 0:bb348c97df44 474 {
lypinator 0:bb348c97df44 475 i2s_frequency = HSI_VALUE;
lypinator 0:bb348c97df44 476 }
lypinator 0:bb348c97df44 477 break;
lypinator 0:bb348c97df44 478 }
lypinator 0:bb348c97df44 479 break;
lypinator 0:bb348c97df44 480
lypinator 0:bb348c97df44 481 case LL_RCC_I2S2_CLKSOURCE_PIN: /* I2S2 Clock is External clock */
lypinator 0:bb348c97df44 482 default:
lypinator 0:bb348c97df44 483 i2s_frequency = EXTERNAL_CLOCK_VALUE;
lypinator 0:bb348c97df44 484 break;
lypinator 0:bb348c97df44 485 }
lypinator 0:bb348c97df44 486 }
lypinator 0:bb348c97df44 487 #endif /* RCC_DCKCFGR_I2S2SRC */
lypinator 0:bb348c97df44 488
lypinator 0:bb348c97df44 489 return i2s_frequency;
lypinator 0:bb348c97df44 490 }
lypinator 0:bb348c97df44 491
lypinator 0:bb348c97df44 492 #if defined(LPTIM1)
lypinator 0:bb348c97df44 493 /**
lypinator 0:bb348c97df44 494 * @brief Return LPTIMx clock frequency
lypinator 0:bb348c97df44 495 * @param LPTIMxSource This parameter can be one of the following values:
lypinator 0:bb348c97df44 496 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE
lypinator 0:bb348c97df44 497 * @retval LPTIM clock frequency (in Hz)
lypinator 0:bb348c97df44 498 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI, LSI or LSE) is not ready
lypinator 0:bb348c97df44 499 */
lypinator 0:bb348c97df44 500 uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource)
lypinator 0:bb348c97df44 501 {
lypinator 0:bb348c97df44 502 uint32_t lptim_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
lypinator 0:bb348c97df44 503
lypinator 0:bb348c97df44 504 /* Check parameter */
lypinator 0:bb348c97df44 505 assert_param(IS_LL_RCC_LPTIM_CLKSOURCE(LPTIMxSource));
lypinator 0:bb348c97df44 506
lypinator 0:bb348c97df44 507 if (LPTIMxSource == LL_RCC_LPTIM1_CLKSOURCE)
lypinator 0:bb348c97df44 508 {
lypinator 0:bb348c97df44 509 /* LPTIM1CLK clock frequency */
lypinator 0:bb348c97df44 510 switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource))
lypinator 0:bb348c97df44 511 {
lypinator 0:bb348c97df44 512 case LL_RCC_LPTIM1_CLKSOURCE_LSI: /* LPTIM1 Clock is LSI Osc. */
lypinator 0:bb348c97df44 513 if (LL_RCC_LSI_IsReady())
lypinator 0:bb348c97df44 514 {
lypinator 0:bb348c97df44 515 lptim_frequency = LSI_VALUE;
lypinator 0:bb348c97df44 516 }
lypinator 0:bb348c97df44 517 break;
lypinator 0:bb348c97df44 518
lypinator 0:bb348c97df44 519 case LL_RCC_LPTIM1_CLKSOURCE_HSI: /* LPTIM1 Clock is HSI Osc. */
lypinator 0:bb348c97df44 520 if (LL_RCC_HSI_IsReady())
lypinator 0:bb348c97df44 521 {
lypinator 0:bb348c97df44 522 lptim_frequency = HSI_VALUE;
lypinator 0:bb348c97df44 523 }
lypinator 0:bb348c97df44 524 break;
lypinator 0:bb348c97df44 525
lypinator 0:bb348c97df44 526 case LL_RCC_LPTIM1_CLKSOURCE_LSE: /* LPTIM1 Clock is LSE Osc. */
lypinator 0:bb348c97df44 527 if (LL_RCC_LSE_IsReady())
lypinator 0:bb348c97df44 528 {
lypinator 0:bb348c97df44 529 lptim_frequency = LSE_VALUE;
lypinator 0:bb348c97df44 530 }
lypinator 0:bb348c97df44 531 break;
lypinator 0:bb348c97df44 532
lypinator 0:bb348c97df44 533 case LL_RCC_LPTIM1_CLKSOURCE_PCLK1: /* LPTIM1 Clock is PCLK1 */
lypinator 0:bb348c97df44 534 default:
lypinator 0:bb348c97df44 535 lptim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
lypinator 0:bb348c97df44 536 break;
lypinator 0:bb348c97df44 537 }
lypinator 0:bb348c97df44 538 }
lypinator 0:bb348c97df44 539
lypinator 0:bb348c97df44 540 return lptim_frequency;
lypinator 0:bb348c97df44 541 }
lypinator 0:bb348c97df44 542 #endif /* LPTIM1 */
lypinator 0:bb348c97df44 543
lypinator 0:bb348c97df44 544 #if defined(SAI1)
lypinator 0:bb348c97df44 545 /**
lypinator 0:bb348c97df44 546 * @brief Return SAIx clock frequency
lypinator 0:bb348c97df44 547 * @param SAIxSource This parameter can be one of the following values:
lypinator 0:bb348c97df44 548 * @arg @ref LL_RCC_SAI1_CLKSOURCE (*)
lypinator 0:bb348c97df44 549 * @arg @ref LL_RCC_SAI2_CLKSOURCE (*)
lypinator 0:bb348c97df44 550 * @arg @ref LL_RCC_SAI1_A_CLKSOURCE (*)
lypinator 0:bb348c97df44 551 * @arg @ref LL_RCC_SAI1_B_CLKSOURCE (*)
lypinator 0:bb348c97df44 552 *
lypinator 0:bb348c97df44 553 * (*) value not defined in all devices.
lypinator 0:bb348c97df44 554 * @retval SAI clock frequency (in Hz)
lypinator 0:bb348c97df44 555 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
lypinator 0:bb348c97df44 556 */
lypinator 0:bb348c97df44 557 uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource)
lypinator 0:bb348c97df44 558 {
lypinator 0:bb348c97df44 559 uint32_t sai_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
lypinator 0:bb348c97df44 560
lypinator 0:bb348c97df44 561 /* Check parameter */
lypinator 0:bb348c97df44 562 assert_param(IS_LL_RCC_SAI_CLKSOURCE(SAIxSource));
lypinator 0:bb348c97df44 563
lypinator 0:bb348c97df44 564 #if defined(RCC_DCKCFGR_SAI1SRC)
lypinator 0:bb348c97df44 565 if ((SAIxSource == LL_RCC_SAI1_CLKSOURCE) || (SAIxSource == LL_RCC_SAI2_CLKSOURCE))
lypinator 0:bb348c97df44 566 {
lypinator 0:bb348c97df44 567 /* SAI1CLK clock frequency */
lypinator 0:bb348c97df44 568 switch (LL_RCC_GetSAIClockSource(SAIxSource))
lypinator 0:bb348c97df44 569 {
lypinator 0:bb348c97df44 570 case LL_RCC_SAI1_CLKSOURCE_PLLSAI: /* PLLSAI clock used as SAI1 clock source */
lypinator 0:bb348c97df44 571 case LL_RCC_SAI2_CLKSOURCE_PLLSAI: /* PLLSAI clock used as SAI2 clock source */
lypinator 0:bb348c97df44 572 if (LL_RCC_PLLSAI_IsReady())
lypinator 0:bb348c97df44 573 {
lypinator 0:bb348c97df44 574 sai_frequency = RCC_PLLSAI_GetFreqDomain_SAI();
lypinator 0:bb348c97df44 575 }
lypinator 0:bb348c97df44 576 break;
lypinator 0:bb348c97df44 577
lypinator 0:bb348c97df44 578 case LL_RCC_SAI1_CLKSOURCE_PLLI2S: /* PLLI2S clock used as SAI1 clock source */
lypinator 0:bb348c97df44 579 case LL_RCC_SAI2_CLKSOURCE_PLLI2S: /* PLLI2S clock used as SAI2 clock source */
lypinator 0:bb348c97df44 580 if (LL_RCC_PLLI2S_IsReady())
lypinator 0:bb348c97df44 581 {
lypinator 0:bb348c97df44 582 sai_frequency = RCC_PLLI2S_GetFreqDomain_SAI();
lypinator 0:bb348c97df44 583 }
lypinator 0:bb348c97df44 584 break;
lypinator 0:bb348c97df44 585
lypinator 0:bb348c97df44 586 case LL_RCC_SAI1_CLKSOURCE_PLL: /* PLL clock used as SAI1 clock source */
lypinator 0:bb348c97df44 587 case LL_RCC_SAI2_CLKSOURCE_PLL: /* PLL clock used as SAI2 clock source */
lypinator 0:bb348c97df44 588 if (LL_RCC_PLL_IsReady())
lypinator 0:bb348c97df44 589 {
lypinator 0:bb348c97df44 590 sai_frequency = RCC_PLL_GetFreqDomain_SAI();
lypinator 0:bb348c97df44 591 }
lypinator 0:bb348c97df44 592 break;
lypinator 0:bb348c97df44 593
lypinator 0:bb348c97df44 594 case LL_RCC_SAI2_CLKSOURCE_PLLSRC:
lypinator 0:bb348c97df44 595 switch (LL_RCC_PLL_GetMainSource())
lypinator 0:bb348c97df44 596 {
lypinator 0:bb348c97df44 597 case LL_RCC_PLLSOURCE_HSE: /* HSE clock used as SAI2 clock source */
lypinator 0:bb348c97df44 598 if (LL_RCC_HSE_IsReady())
lypinator 0:bb348c97df44 599 {
lypinator 0:bb348c97df44 600 sai_frequency = HSE_VALUE;
lypinator 0:bb348c97df44 601 }
lypinator 0:bb348c97df44 602 break;
lypinator 0:bb348c97df44 603
lypinator 0:bb348c97df44 604 case LL_RCC_PLLSOURCE_HSI: /* HSI clock used as SAI2 clock source */
lypinator 0:bb348c97df44 605 default:
lypinator 0:bb348c97df44 606 if (LL_RCC_HSI_IsReady())
lypinator 0:bb348c97df44 607 {
lypinator 0:bb348c97df44 608 sai_frequency = HSI_VALUE;
lypinator 0:bb348c97df44 609 }
lypinator 0:bb348c97df44 610 break;
lypinator 0:bb348c97df44 611 }
lypinator 0:bb348c97df44 612 break;
lypinator 0:bb348c97df44 613
lypinator 0:bb348c97df44 614 case LL_RCC_SAI1_CLKSOURCE_PIN: /* External input clock used as SAI1 clock source */
lypinator 0:bb348c97df44 615 default:
lypinator 0:bb348c97df44 616 sai_frequency = EXTERNAL_CLOCK_VALUE;
lypinator 0:bb348c97df44 617 break;
lypinator 0:bb348c97df44 618 }
lypinator 0:bb348c97df44 619 }
lypinator 0:bb348c97df44 620 #endif /* RCC_DCKCFGR_SAI1SRC */
lypinator 0:bb348c97df44 621 #if defined(RCC_DCKCFGR_SAI1ASRC)
lypinator 0:bb348c97df44 622 if ((SAIxSource == LL_RCC_SAI1_A_CLKSOURCE) || (SAIxSource == LL_RCC_SAI1_B_CLKSOURCE))
lypinator 0:bb348c97df44 623 {
lypinator 0:bb348c97df44 624 /* SAI1CLK clock frequency */
lypinator 0:bb348c97df44 625 switch (LL_RCC_GetSAIClockSource(SAIxSource))
lypinator 0:bb348c97df44 626 {
lypinator 0:bb348c97df44 627 #if defined(RCC_PLLSAI_SUPPORT)
lypinator 0:bb348c97df44 628 case LL_RCC_SAI1_A_CLKSOURCE_PLLSAI: /* PLLSAI clock used as SAI1 Block A clock source */
lypinator 0:bb348c97df44 629 case LL_RCC_SAI1_B_CLKSOURCE_PLLSAI: /* PLLSAI clock used as SAI1 Block B clock source */
lypinator 0:bb348c97df44 630 if (LL_RCC_PLLSAI_IsReady())
lypinator 0:bb348c97df44 631 {
lypinator 0:bb348c97df44 632 sai_frequency = RCC_PLLSAI_GetFreqDomain_SAI();
lypinator 0:bb348c97df44 633 }
lypinator 0:bb348c97df44 634 break;
lypinator 0:bb348c97df44 635 #endif /* RCC_PLLSAI_SUPPORT */
lypinator 0:bb348c97df44 636
lypinator 0:bb348c97df44 637 case LL_RCC_SAI1_A_CLKSOURCE_PLLI2S: /* PLLI2S clock used as SAI1 Block A clock source */
lypinator 0:bb348c97df44 638 case LL_RCC_SAI1_B_CLKSOURCE_PLLI2S: /* PLLI2S clock used as SAI1 Block B clock source */
lypinator 0:bb348c97df44 639 if (LL_RCC_PLLI2S_IsReady())
lypinator 0:bb348c97df44 640 {
lypinator 0:bb348c97df44 641 sai_frequency = RCC_PLLI2S_GetFreqDomain_SAI();
lypinator 0:bb348c97df44 642 }
lypinator 0:bb348c97df44 643 break;
lypinator 0:bb348c97df44 644
lypinator 0:bb348c97df44 645 #if defined(RCC_SAI1A_PLLSOURCE_SUPPORT)
lypinator 0:bb348c97df44 646 case LL_RCC_SAI1_A_CLKSOURCE_PLL: /* PLL clock used as SAI1 Block A clock source */
lypinator 0:bb348c97df44 647 case LL_RCC_SAI1_B_CLKSOURCE_PLL: /* PLL clock used as SAI1 Block B clock source */
lypinator 0:bb348c97df44 648 if (LL_RCC_PLL_IsReady())
lypinator 0:bb348c97df44 649 {
lypinator 0:bb348c97df44 650 sai_frequency = RCC_PLL_GetFreqDomain_SAI();
lypinator 0:bb348c97df44 651 }
lypinator 0:bb348c97df44 652 break;
lypinator 0:bb348c97df44 653
lypinator 0:bb348c97df44 654 case LL_RCC_SAI1_A_CLKSOURCE_PLLSRC:
lypinator 0:bb348c97df44 655 case LL_RCC_SAI1_B_CLKSOURCE_PLLSRC:
lypinator 0:bb348c97df44 656 switch (LL_RCC_PLL_GetMainSource())
lypinator 0:bb348c97df44 657 {
lypinator 0:bb348c97df44 658 case LL_RCC_PLLSOURCE_HSE: /* HSE clock used as SAI1 Block A or B clock source */
lypinator 0:bb348c97df44 659 if (LL_RCC_HSE_IsReady())
lypinator 0:bb348c97df44 660 {
lypinator 0:bb348c97df44 661 sai_frequency = HSE_VALUE;
lypinator 0:bb348c97df44 662 }
lypinator 0:bb348c97df44 663 break;
lypinator 0:bb348c97df44 664
lypinator 0:bb348c97df44 665 case LL_RCC_PLLSOURCE_HSI: /* HSI clock used as SAI1 Block A or B clock source */
lypinator 0:bb348c97df44 666 default:
lypinator 0:bb348c97df44 667 if (LL_RCC_HSI_IsReady())
lypinator 0:bb348c97df44 668 {
lypinator 0:bb348c97df44 669 sai_frequency = HSI_VALUE;
lypinator 0:bb348c97df44 670 }
lypinator 0:bb348c97df44 671 break;
lypinator 0:bb348c97df44 672 }
lypinator 0:bb348c97df44 673 break;
lypinator 0:bb348c97df44 674 #endif /* RCC_SAI1A_PLLSOURCE_SUPPORT */
lypinator 0:bb348c97df44 675
lypinator 0:bb348c97df44 676 case LL_RCC_SAI1_A_CLKSOURCE_PIN: /* External input clock used as SAI1 Block A clock source */
lypinator 0:bb348c97df44 677 case LL_RCC_SAI1_B_CLKSOURCE_PIN: /* External input clock used as SAI1 Block B clock source */
lypinator 0:bb348c97df44 678 default:
lypinator 0:bb348c97df44 679 sai_frequency = EXTERNAL_CLOCK_VALUE;
lypinator 0:bb348c97df44 680 break;
lypinator 0:bb348c97df44 681 }
lypinator 0:bb348c97df44 682 }
lypinator 0:bb348c97df44 683 #endif /* RCC_DCKCFGR_SAI1ASRC */
lypinator 0:bb348c97df44 684
lypinator 0:bb348c97df44 685 return sai_frequency;
lypinator 0:bb348c97df44 686 }
lypinator 0:bb348c97df44 687 #endif /* SAI1 */
lypinator 0:bb348c97df44 688
lypinator 0:bb348c97df44 689 #if defined(SDIO)
lypinator 0:bb348c97df44 690 /**
lypinator 0:bb348c97df44 691 * @brief Return SDIOx clock frequency
lypinator 0:bb348c97df44 692 * @param SDIOxSource This parameter can be one of the following values:
lypinator 0:bb348c97df44 693 * @arg @ref LL_RCC_SDIO_CLKSOURCE
lypinator 0:bb348c97df44 694 * @retval SDIO clock frequency (in Hz)
lypinator 0:bb348c97df44 695 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
lypinator 0:bb348c97df44 696 */
lypinator 0:bb348c97df44 697 uint32_t LL_RCC_GetSDIOClockFreq(uint32_t SDIOxSource)
lypinator 0:bb348c97df44 698 {
lypinator 0:bb348c97df44 699 uint32_t SDIO_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
lypinator 0:bb348c97df44 700
lypinator 0:bb348c97df44 701 /* Check parameter */
lypinator 0:bb348c97df44 702 assert_param(IS_LL_RCC_SDIO_CLKSOURCE(SDIOxSource));
lypinator 0:bb348c97df44 703
lypinator 0:bb348c97df44 704 if (SDIOxSource == LL_RCC_SDIO_CLKSOURCE)
lypinator 0:bb348c97df44 705 {
lypinator 0:bb348c97df44 706 #if defined(RCC_DCKCFGR_SDIOSEL) || defined(RCC_DCKCFGR2_SDIOSEL)
lypinator 0:bb348c97df44 707 /* SDIOCLK clock frequency */
lypinator 0:bb348c97df44 708 switch (LL_RCC_GetSDIOClockSource(SDIOxSource))
lypinator 0:bb348c97df44 709 {
lypinator 0:bb348c97df44 710 case LL_RCC_SDIO_CLKSOURCE_PLL48CLK: /* PLL48M clock used as SDIO clock source */
lypinator 0:bb348c97df44 711 switch (LL_RCC_GetCK48MClockSource(LL_RCC_CK48M_CLKSOURCE))
lypinator 0:bb348c97df44 712 {
lypinator 0:bb348c97df44 713 case LL_RCC_CK48M_CLKSOURCE_PLL: /* PLL clock used as 48Mhz domain clock */
lypinator 0:bb348c97df44 714 if (LL_RCC_PLL_IsReady())
lypinator 0:bb348c97df44 715 {
lypinator 0:bb348c97df44 716 SDIO_frequency = RCC_PLL_GetFreqDomain_48M();
lypinator 0:bb348c97df44 717 }
lypinator 0:bb348c97df44 718 break;
lypinator 0:bb348c97df44 719
lypinator 0:bb348c97df44 720 #if defined(RCC_PLLSAI_SUPPORT)
lypinator 0:bb348c97df44 721 case LL_RCC_CK48M_CLKSOURCE_PLLSAI: /* PLLSAI clock used as 48Mhz domain clock */
lypinator 0:bb348c97df44 722 default:
lypinator 0:bb348c97df44 723 if (LL_RCC_PLLSAI_IsReady())
lypinator 0:bb348c97df44 724 {
lypinator 0:bb348c97df44 725 SDIO_frequency = RCC_PLLSAI_GetFreqDomain_48M();
lypinator 0:bb348c97df44 726 }
lypinator 0:bb348c97df44 727 break;
lypinator 0:bb348c97df44 728 #endif /* RCC_PLLSAI_SUPPORT */
lypinator 0:bb348c97df44 729
lypinator 0:bb348c97df44 730 #if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
lypinator 0:bb348c97df44 731 case LL_RCC_CK48M_CLKSOURCE_PLLI2S: /* PLLI2S clock used as 48Mhz domain clock */
lypinator 0:bb348c97df44 732 default:
lypinator 0:bb348c97df44 733 if (LL_RCC_PLLI2S_IsReady())
lypinator 0:bb348c97df44 734 {
lypinator 0:bb348c97df44 735 SDIO_frequency = RCC_PLLI2S_GetFreqDomain_48M();
lypinator 0:bb348c97df44 736 }
lypinator 0:bb348c97df44 737 break;
lypinator 0:bb348c97df44 738 #endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
lypinator 0:bb348c97df44 739 }
lypinator 0:bb348c97df44 740 break;
lypinator 0:bb348c97df44 741
lypinator 0:bb348c97df44 742 case LL_RCC_SDIO_CLKSOURCE_SYSCLK: /* PLL clock used as SDIO clock source */
lypinator 0:bb348c97df44 743 default:
lypinator 0:bb348c97df44 744 SDIO_frequency = RCC_GetSystemClockFreq();
lypinator 0:bb348c97df44 745 break;
lypinator 0:bb348c97df44 746 }
lypinator 0:bb348c97df44 747 #else
lypinator 0:bb348c97df44 748 /* PLL clock used as 48Mhz domain clock */
lypinator 0:bb348c97df44 749 if (LL_RCC_PLL_IsReady())
lypinator 0:bb348c97df44 750 {
lypinator 0:bb348c97df44 751 SDIO_frequency = RCC_PLL_GetFreqDomain_48M();
lypinator 0:bb348c97df44 752 }
lypinator 0:bb348c97df44 753 #endif /* RCC_DCKCFGR_SDIOSEL || RCC_DCKCFGR2_SDIOSEL */
lypinator 0:bb348c97df44 754 }
lypinator 0:bb348c97df44 755
lypinator 0:bb348c97df44 756 return SDIO_frequency;
lypinator 0:bb348c97df44 757 }
lypinator 0:bb348c97df44 758 #endif /* SDIO */
lypinator 0:bb348c97df44 759
lypinator 0:bb348c97df44 760 #if defined(RNG)
lypinator 0:bb348c97df44 761 /**
lypinator 0:bb348c97df44 762 * @brief Return RNGx clock frequency
lypinator 0:bb348c97df44 763 * @param RNGxSource This parameter can be one of the following values:
lypinator 0:bb348c97df44 764 * @arg @ref LL_RCC_RNG_CLKSOURCE
lypinator 0:bb348c97df44 765 * @retval RNG clock frequency (in Hz)
lypinator 0:bb348c97df44 766 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
lypinator 0:bb348c97df44 767 */
lypinator 0:bb348c97df44 768 uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource)
lypinator 0:bb348c97df44 769 {
lypinator 0:bb348c97df44 770 uint32_t rng_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
lypinator 0:bb348c97df44 771
lypinator 0:bb348c97df44 772 /* Check parameter */
lypinator 0:bb348c97df44 773 assert_param(IS_LL_RCC_RNG_CLKSOURCE(RNGxSource));
lypinator 0:bb348c97df44 774
lypinator 0:bb348c97df44 775 #if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL)
lypinator 0:bb348c97df44 776 /* RNGCLK clock frequency */
lypinator 0:bb348c97df44 777 switch (LL_RCC_GetRNGClockSource(RNGxSource))
lypinator 0:bb348c97df44 778 {
lypinator 0:bb348c97df44 779 #if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
lypinator 0:bb348c97df44 780 case LL_RCC_RNG_CLKSOURCE_PLLI2S: /* PLLI2S clock used as RNG clock source */
lypinator 0:bb348c97df44 781 if (LL_RCC_PLLI2S_IsReady())
lypinator 0:bb348c97df44 782 {
lypinator 0:bb348c97df44 783 rng_frequency = RCC_PLLI2S_GetFreqDomain_48M();
lypinator 0:bb348c97df44 784 }
lypinator 0:bb348c97df44 785 break;
lypinator 0:bb348c97df44 786 #endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
lypinator 0:bb348c97df44 787
lypinator 0:bb348c97df44 788 #if defined(RCC_PLLSAI_SUPPORT)
lypinator 0:bb348c97df44 789 case LL_RCC_RNG_CLKSOURCE_PLLSAI: /* PLLSAI clock used as RNG clock source */
lypinator 0:bb348c97df44 790 if (LL_RCC_PLLSAI_IsReady())
lypinator 0:bb348c97df44 791 {
lypinator 0:bb348c97df44 792 rng_frequency = RCC_PLLSAI_GetFreqDomain_48M();
lypinator 0:bb348c97df44 793 }
lypinator 0:bb348c97df44 794 break;
lypinator 0:bb348c97df44 795 #endif /* RCC_PLLSAI_SUPPORT */
lypinator 0:bb348c97df44 796
lypinator 0:bb348c97df44 797 case LL_RCC_RNG_CLKSOURCE_PLL: /* PLL clock used as RNG clock source */
lypinator 0:bb348c97df44 798 default:
lypinator 0:bb348c97df44 799 if (LL_RCC_PLL_IsReady())
lypinator 0:bb348c97df44 800 {
lypinator 0:bb348c97df44 801 rng_frequency = RCC_PLL_GetFreqDomain_48M();
lypinator 0:bb348c97df44 802 }
lypinator 0:bb348c97df44 803 break;
lypinator 0:bb348c97df44 804 }
lypinator 0:bb348c97df44 805 #else
lypinator 0:bb348c97df44 806 /* PLL clock used as RNG clock source */
lypinator 0:bb348c97df44 807 if (LL_RCC_PLL_IsReady())
lypinator 0:bb348c97df44 808 {
lypinator 0:bb348c97df44 809 rng_frequency = RCC_PLL_GetFreqDomain_48M();
lypinator 0:bb348c97df44 810 }
lypinator 0:bb348c97df44 811 #endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */
lypinator 0:bb348c97df44 812
lypinator 0:bb348c97df44 813 return rng_frequency;
lypinator 0:bb348c97df44 814 }
lypinator 0:bb348c97df44 815 #endif /* RNG */
lypinator 0:bb348c97df44 816
lypinator 0:bb348c97df44 817 #if defined(CEC)
lypinator 0:bb348c97df44 818 /**
lypinator 0:bb348c97df44 819 * @brief Return CEC clock frequency
lypinator 0:bb348c97df44 820 * @param CECxSource This parameter can be one of the following values:
lypinator 0:bb348c97df44 821 * @arg @ref LL_RCC_CEC_CLKSOURCE
lypinator 0:bb348c97df44 822 * @retval CEC clock frequency (in Hz)
lypinator 0:bb348c97df44 823 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
lypinator 0:bb348c97df44 824 */
lypinator 0:bb348c97df44 825 uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource)
lypinator 0:bb348c97df44 826 {
lypinator 0:bb348c97df44 827 uint32_t cec_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
lypinator 0:bb348c97df44 828
lypinator 0:bb348c97df44 829 /* Check parameter */
lypinator 0:bb348c97df44 830 assert_param(IS_LL_RCC_CEC_CLKSOURCE(CECxSource));
lypinator 0:bb348c97df44 831
lypinator 0:bb348c97df44 832 /* CECCLK clock frequency */
lypinator 0:bb348c97df44 833 switch (LL_RCC_GetCECClockSource(CECxSource))
lypinator 0:bb348c97df44 834 {
lypinator 0:bb348c97df44 835 case LL_RCC_CEC_CLKSOURCE_LSE: /* CEC Clock is LSE Osc. */
lypinator 0:bb348c97df44 836 if (LL_RCC_LSE_IsReady())
lypinator 0:bb348c97df44 837 {
lypinator 0:bb348c97df44 838 cec_frequency = LSE_VALUE;
lypinator 0:bb348c97df44 839 }
lypinator 0:bb348c97df44 840 break;
lypinator 0:bb348c97df44 841
lypinator 0:bb348c97df44 842 case LL_RCC_CEC_CLKSOURCE_HSI_DIV488: /* CEC Clock is HSI Osc. */
lypinator 0:bb348c97df44 843 default:
lypinator 0:bb348c97df44 844 if (LL_RCC_HSI_IsReady())
lypinator 0:bb348c97df44 845 {
lypinator 0:bb348c97df44 846 cec_frequency = HSI_VALUE/488U;
lypinator 0:bb348c97df44 847 }
lypinator 0:bb348c97df44 848 break;
lypinator 0:bb348c97df44 849 }
lypinator 0:bb348c97df44 850
lypinator 0:bb348c97df44 851 return cec_frequency;
lypinator 0:bb348c97df44 852 }
lypinator 0:bb348c97df44 853 #endif /* CEC */
lypinator 0:bb348c97df44 854
lypinator 0:bb348c97df44 855 #if defined(USB_OTG_FS) || defined(USB_OTG_HS)
lypinator 0:bb348c97df44 856 /**
lypinator 0:bb348c97df44 857 * @brief Return USBx clock frequency
lypinator 0:bb348c97df44 858 * @param USBxSource This parameter can be one of the following values:
lypinator 0:bb348c97df44 859 * @arg @ref LL_RCC_USB_CLKSOURCE
lypinator 0:bb348c97df44 860 * @retval USB clock frequency (in Hz)
lypinator 0:bb348c97df44 861 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
lypinator 0:bb348c97df44 862 */
lypinator 0:bb348c97df44 863 uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource)
lypinator 0:bb348c97df44 864 {
lypinator 0:bb348c97df44 865 uint32_t usb_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
lypinator 0:bb348c97df44 866
lypinator 0:bb348c97df44 867 /* Check parameter */
lypinator 0:bb348c97df44 868 assert_param(IS_LL_RCC_USB_CLKSOURCE(USBxSource));
lypinator 0:bb348c97df44 869
lypinator 0:bb348c97df44 870 #if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL)
lypinator 0:bb348c97df44 871 /* USBCLK clock frequency */
lypinator 0:bb348c97df44 872 switch (LL_RCC_GetUSBClockSource(USBxSource))
lypinator 0:bb348c97df44 873 {
lypinator 0:bb348c97df44 874 #if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
lypinator 0:bb348c97df44 875 case LL_RCC_USB_CLKSOURCE_PLLI2S: /* PLLI2S clock used as USB clock source */
lypinator 0:bb348c97df44 876 if (LL_RCC_PLLI2S_IsReady())
lypinator 0:bb348c97df44 877 {
lypinator 0:bb348c97df44 878 usb_frequency = RCC_PLLI2S_GetFreqDomain_48M();
lypinator 0:bb348c97df44 879 }
lypinator 0:bb348c97df44 880 break;
lypinator 0:bb348c97df44 881
lypinator 0:bb348c97df44 882 #endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
lypinator 0:bb348c97df44 883
lypinator 0:bb348c97df44 884 #if defined(RCC_PLLSAI_SUPPORT)
lypinator 0:bb348c97df44 885 case LL_RCC_USB_CLKSOURCE_PLLSAI: /* PLLSAI clock used as USB clock source */
lypinator 0:bb348c97df44 886 if (LL_RCC_PLLSAI_IsReady())
lypinator 0:bb348c97df44 887 {
lypinator 0:bb348c97df44 888 usb_frequency = RCC_PLLSAI_GetFreqDomain_48M();
lypinator 0:bb348c97df44 889 }
lypinator 0:bb348c97df44 890 break;
lypinator 0:bb348c97df44 891 #endif /* RCC_PLLSAI_SUPPORT */
lypinator 0:bb348c97df44 892
lypinator 0:bb348c97df44 893 case LL_RCC_USB_CLKSOURCE_PLL: /* PLL clock used as USB clock source */
lypinator 0:bb348c97df44 894 default:
lypinator 0:bb348c97df44 895 if (LL_RCC_PLL_IsReady())
lypinator 0:bb348c97df44 896 {
lypinator 0:bb348c97df44 897 usb_frequency = RCC_PLL_GetFreqDomain_48M();
lypinator 0:bb348c97df44 898 }
lypinator 0:bb348c97df44 899 break;
lypinator 0:bb348c97df44 900 }
lypinator 0:bb348c97df44 901 #else
lypinator 0:bb348c97df44 902 /* PLL clock used as USB clock source */
lypinator 0:bb348c97df44 903 if (LL_RCC_PLL_IsReady())
lypinator 0:bb348c97df44 904 {
lypinator 0:bb348c97df44 905 usb_frequency = RCC_PLL_GetFreqDomain_48M();
lypinator 0:bb348c97df44 906 }
lypinator 0:bb348c97df44 907 #endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */
lypinator 0:bb348c97df44 908
lypinator 0:bb348c97df44 909 return usb_frequency;
lypinator 0:bb348c97df44 910 }
lypinator 0:bb348c97df44 911 #endif /* USB_OTG_FS || USB_OTG_HS */
lypinator 0:bb348c97df44 912
lypinator 0:bb348c97df44 913 #if defined(DFSDM1_Channel0)
lypinator 0:bb348c97df44 914 /**
lypinator 0:bb348c97df44 915 * @brief Return DFSDMx clock frequency
lypinator 0:bb348c97df44 916 * @param DFSDMxSource This parameter can be one of the following values:
lypinator 0:bb348c97df44 917 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE
lypinator 0:bb348c97df44 918 * @arg @ref LL_RCC_DFSDM2_CLKSOURCE (*)
lypinator 0:bb348c97df44 919 *
lypinator 0:bb348c97df44 920 * (*) value not defined in all devices.
lypinator 0:bb348c97df44 921 * @retval DFSDM clock frequency (in Hz)
lypinator 0:bb348c97df44 922 */
lypinator 0:bb348c97df44 923 uint32_t LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource)
lypinator 0:bb348c97df44 924 {
lypinator 0:bb348c97df44 925 uint32_t dfsdm_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
lypinator 0:bb348c97df44 926
lypinator 0:bb348c97df44 927 /* Check parameter */
lypinator 0:bb348c97df44 928 assert_param(IS_LL_RCC_DFSDM_CLKSOURCE(DFSDMxSource));
lypinator 0:bb348c97df44 929
lypinator 0:bb348c97df44 930 if (DFSDMxSource == LL_RCC_DFSDM1_CLKSOURCE)
lypinator 0:bb348c97df44 931 {
lypinator 0:bb348c97df44 932 /* DFSDM1CLK clock frequency */
lypinator 0:bb348c97df44 933 switch (LL_RCC_GetDFSDMClockSource(DFSDMxSource))
lypinator 0:bb348c97df44 934 {
lypinator 0:bb348c97df44 935 case LL_RCC_DFSDM1_CLKSOURCE_SYSCLK: /* DFSDM1 Clock is SYSCLK */
lypinator 0:bb348c97df44 936 dfsdm_frequency = RCC_GetSystemClockFreq();
lypinator 0:bb348c97df44 937 break;
lypinator 0:bb348c97df44 938
lypinator 0:bb348c97df44 939 case LL_RCC_DFSDM1_CLKSOURCE_PCLK2: /* DFSDM1 Clock is PCLK2 */
lypinator 0:bb348c97df44 940 default:
lypinator 0:bb348c97df44 941 dfsdm_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
lypinator 0:bb348c97df44 942 break;
lypinator 0:bb348c97df44 943 }
lypinator 0:bb348c97df44 944 }
lypinator 0:bb348c97df44 945 #if defined(DFSDM2_Channel0)
lypinator 0:bb348c97df44 946 else
lypinator 0:bb348c97df44 947 {
lypinator 0:bb348c97df44 948 /* DFSDM2CLK clock frequency */
lypinator 0:bb348c97df44 949 switch (LL_RCC_GetDFSDMClockSource(DFSDMxSource))
lypinator 0:bb348c97df44 950 {
lypinator 0:bb348c97df44 951 case LL_RCC_DFSDM2_CLKSOURCE_SYSCLK: /* DFSDM2 Clock is SYSCLK */
lypinator 0:bb348c97df44 952 dfsdm_frequency = RCC_GetSystemClockFreq();
lypinator 0:bb348c97df44 953 break;
lypinator 0:bb348c97df44 954
lypinator 0:bb348c97df44 955 case LL_RCC_DFSDM2_CLKSOURCE_PCLK2: /* DFSDM2 Clock is PCLK2 */
lypinator 0:bb348c97df44 956 default:
lypinator 0:bb348c97df44 957 dfsdm_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
lypinator 0:bb348c97df44 958 break;
lypinator 0:bb348c97df44 959 }
lypinator 0:bb348c97df44 960 }
lypinator 0:bb348c97df44 961 #endif /* DFSDM2_Channel0 */
lypinator 0:bb348c97df44 962
lypinator 0:bb348c97df44 963 return dfsdm_frequency;
lypinator 0:bb348c97df44 964 }
lypinator 0:bb348c97df44 965
lypinator 0:bb348c97df44 966 /**
lypinator 0:bb348c97df44 967 * @brief Return DFSDMx Audio clock frequency
lypinator 0:bb348c97df44 968 * @param DFSDMxSource This parameter can be one of the following values:
lypinator 0:bb348c97df44 969 * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE
lypinator 0:bb348c97df44 970 * @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE (*)
lypinator 0:bb348c97df44 971 *
lypinator 0:bb348c97df44 972 * (*) value not defined in all devices.
lypinator 0:bb348c97df44 973 * @retval DFSDM clock frequency (in Hz)
lypinator 0:bb348c97df44 974 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
lypinator 0:bb348c97df44 975 */
lypinator 0:bb348c97df44 976 uint32_t LL_RCC_GetDFSDMAudioClockFreq(uint32_t DFSDMxSource)
lypinator 0:bb348c97df44 977 {
lypinator 0:bb348c97df44 978 uint32_t dfsdm_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
lypinator 0:bb348c97df44 979
lypinator 0:bb348c97df44 980 /* Check parameter */
lypinator 0:bb348c97df44 981 assert_param(IS_LL_RCC_DFSDM_AUDIO_CLKSOURCE(DFSDMxSource));
lypinator 0:bb348c97df44 982
lypinator 0:bb348c97df44 983 if (DFSDMxSource == LL_RCC_DFSDM1_AUDIO_CLKSOURCE)
lypinator 0:bb348c97df44 984 {
lypinator 0:bb348c97df44 985 /* DFSDM1CLK clock frequency */
lypinator 0:bb348c97df44 986 switch (LL_RCC_GetDFSDMAudioClockSource(DFSDMxSource))
lypinator 0:bb348c97df44 987 {
lypinator 0:bb348c97df44 988 case LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S1: /* I2S1 clock used as DFSDM1 clock */
lypinator 0:bb348c97df44 989 dfsdm_frequency = LL_RCC_GetI2SClockFreq(LL_RCC_I2S1_CLKSOURCE);
lypinator 0:bb348c97df44 990 break;
lypinator 0:bb348c97df44 991
lypinator 0:bb348c97df44 992 case LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S2: /* I2S2 clock used as DFSDM1 clock */
lypinator 0:bb348c97df44 993 default:
lypinator 0:bb348c97df44 994 dfsdm_frequency = LL_RCC_GetI2SClockFreq(LL_RCC_I2S2_CLKSOURCE);
lypinator 0:bb348c97df44 995 break;
lypinator 0:bb348c97df44 996 }
lypinator 0:bb348c97df44 997 }
lypinator 0:bb348c97df44 998 #if defined(DFSDM2_Channel0)
lypinator 0:bb348c97df44 999 else
lypinator 0:bb348c97df44 1000 {
lypinator 0:bb348c97df44 1001 /* DFSDM2CLK clock frequency */
lypinator 0:bb348c97df44 1002 switch (LL_RCC_GetDFSDMAudioClockSource(DFSDMxSource))
lypinator 0:bb348c97df44 1003 {
lypinator 0:bb348c97df44 1004 case LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S1: /* I2S1 clock used as DFSDM2 clock */
lypinator 0:bb348c97df44 1005 dfsdm_frequency = LL_RCC_GetI2SClockFreq(LL_RCC_I2S1_CLKSOURCE);
lypinator 0:bb348c97df44 1006 break;
lypinator 0:bb348c97df44 1007
lypinator 0:bb348c97df44 1008 case LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S2: /* I2S2 clock used as DFSDM2 clock */
lypinator 0:bb348c97df44 1009 default:
lypinator 0:bb348c97df44 1010 dfsdm_frequency = LL_RCC_GetI2SClockFreq(LL_RCC_I2S2_CLKSOURCE);
lypinator 0:bb348c97df44 1011 break;
lypinator 0:bb348c97df44 1012 }
lypinator 0:bb348c97df44 1013 }
lypinator 0:bb348c97df44 1014 #endif /* DFSDM2_Channel0 */
lypinator 0:bb348c97df44 1015
lypinator 0:bb348c97df44 1016 return dfsdm_frequency;
lypinator 0:bb348c97df44 1017 }
lypinator 0:bb348c97df44 1018 #endif /* DFSDM1_Channel0 */
lypinator 0:bb348c97df44 1019
lypinator 0:bb348c97df44 1020 #if defined(DSI)
lypinator 0:bb348c97df44 1021 /**
lypinator 0:bb348c97df44 1022 * @brief Return DSI clock frequency
lypinator 0:bb348c97df44 1023 * @param DSIxSource This parameter can be one of the following values:
lypinator 0:bb348c97df44 1024 * @arg @ref LL_RCC_DSI_CLKSOURCE
lypinator 0:bb348c97df44 1025 * @retval DSI clock frequency (in Hz)
lypinator 0:bb348c97df44 1026 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
lypinator 0:bb348c97df44 1027 * - @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that external clock is used
lypinator 0:bb348c97df44 1028 */
lypinator 0:bb348c97df44 1029 uint32_t LL_RCC_GetDSIClockFreq(uint32_t DSIxSource)
lypinator 0:bb348c97df44 1030 {
lypinator 0:bb348c97df44 1031 uint32_t dsi_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
lypinator 0:bb348c97df44 1032
lypinator 0:bb348c97df44 1033 /* Check parameter */
lypinator 0:bb348c97df44 1034 assert_param(IS_LL_RCC_DSI_CLKSOURCE(DSIxSource));
lypinator 0:bb348c97df44 1035
lypinator 0:bb348c97df44 1036 /* DSICLK clock frequency */
lypinator 0:bb348c97df44 1037 switch (LL_RCC_GetDSIClockSource(DSIxSource))
lypinator 0:bb348c97df44 1038 {
lypinator 0:bb348c97df44 1039 case LL_RCC_DSI_CLKSOURCE_PLL: /* DSI Clock is PLL Osc. */
lypinator 0:bb348c97df44 1040 if (LL_RCC_PLL_IsReady())
lypinator 0:bb348c97df44 1041 {
lypinator 0:bb348c97df44 1042 dsi_frequency = RCC_PLL_GetFreqDomain_DSI();
lypinator 0:bb348c97df44 1043 }
lypinator 0:bb348c97df44 1044 break;
lypinator 0:bb348c97df44 1045
lypinator 0:bb348c97df44 1046 case LL_RCC_DSI_CLKSOURCE_PHY: /* DSI Clock is DSI physical clock. */
lypinator 0:bb348c97df44 1047 default:
lypinator 0:bb348c97df44 1048 dsi_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
lypinator 0:bb348c97df44 1049 break;
lypinator 0:bb348c97df44 1050 }
lypinator 0:bb348c97df44 1051
lypinator 0:bb348c97df44 1052 return dsi_frequency;
lypinator 0:bb348c97df44 1053 }
lypinator 0:bb348c97df44 1054 #endif /* DSI */
lypinator 0:bb348c97df44 1055
lypinator 0:bb348c97df44 1056 #if defined(LTDC)
lypinator 0:bb348c97df44 1057 /**
lypinator 0:bb348c97df44 1058 * @brief Return LTDC clock frequency
lypinator 0:bb348c97df44 1059 * @param LTDCxSource This parameter can be one of the following values:
lypinator 0:bb348c97df44 1060 * @arg @ref LL_RCC_LTDC_CLKSOURCE
lypinator 0:bb348c97df44 1061 * @retval LTDC clock frequency (in Hz)
lypinator 0:bb348c97df44 1062 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator PLLSAI is not ready
lypinator 0:bb348c97df44 1063 */
lypinator 0:bb348c97df44 1064 uint32_t LL_RCC_GetLTDCClockFreq(uint32_t LTDCxSource)
lypinator 0:bb348c97df44 1065 {
lypinator 0:bb348c97df44 1066 uint32_t ltdc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
lypinator 0:bb348c97df44 1067
lypinator 0:bb348c97df44 1068 /* Check parameter */
lypinator 0:bb348c97df44 1069 assert_param(IS_LL_RCC_LTDC_CLKSOURCE(LTDCxSource));
lypinator 0:bb348c97df44 1070
lypinator 0:bb348c97df44 1071 if (LL_RCC_PLLSAI_IsReady())
lypinator 0:bb348c97df44 1072 {
lypinator 0:bb348c97df44 1073 ltdc_frequency = RCC_PLLSAI_GetFreqDomain_LTDC();
lypinator 0:bb348c97df44 1074 }
lypinator 0:bb348c97df44 1075
lypinator 0:bb348c97df44 1076 return ltdc_frequency;
lypinator 0:bb348c97df44 1077 }
lypinator 0:bb348c97df44 1078 #endif /* LTDC */
lypinator 0:bb348c97df44 1079
lypinator 0:bb348c97df44 1080 #if defined(SPDIFRX)
lypinator 0:bb348c97df44 1081 /**
lypinator 0:bb348c97df44 1082 * @brief Return SPDIFRX clock frequency
lypinator 0:bb348c97df44 1083 * @param SPDIFRXxSource This parameter can be one of the following values:
lypinator 0:bb348c97df44 1084 * @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE
lypinator 0:bb348c97df44 1085 * @retval SPDIFRX clock frequency (in Hz)
lypinator 0:bb348c97df44 1086 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
lypinator 0:bb348c97df44 1087 */
lypinator 0:bb348c97df44 1088 uint32_t LL_RCC_GetSPDIFRXClockFreq(uint32_t SPDIFRXxSource)
lypinator 0:bb348c97df44 1089 {
lypinator 0:bb348c97df44 1090 uint32_t spdifrx_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
lypinator 0:bb348c97df44 1091
lypinator 0:bb348c97df44 1092 /* Check parameter */
lypinator 0:bb348c97df44 1093 assert_param(IS_LL_RCC_SPDIFRX_CLKSOURCE(SPDIFRXxSource));
lypinator 0:bb348c97df44 1094
lypinator 0:bb348c97df44 1095 /* SPDIFRX1CLK clock frequency */
lypinator 0:bb348c97df44 1096 switch (LL_RCC_GetSPDIFRXClockSource(SPDIFRXxSource))
lypinator 0:bb348c97df44 1097 {
lypinator 0:bb348c97df44 1098 case LL_RCC_SPDIFRX1_CLKSOURCE_PLLI2S: /* SPDIFRX Clock is PLLI2S Osc. */
lypinator 0:bb348c97df44 1099 if (LL_RCC_PLLI2S_IsReady())
lypinator 0:bb348c97df44 1100 {
lypinator 0:bb348c97df44 1101 spdifrx_frequency = RCC_PLLI2S_GetFreqDomain_SPDIFRX();
lypinator 0:bb348c97df44 1102 }
lypinator 0:bb348c97df44 1103 break;
lypinator 0:bb348c97df44 1104
lypinator 0:bb348c97df44 1105 case LL_RCC_SPDIFRX1_CLKSOURCE_PLL: /* SPDIFRX Clock is PLL Osc. */
lypinator 0:bb348c97df44 1106 default:
lypinator 0:bb348c97df44 1107 if (LL_RCC_PLL_IsReady())
lypinator 0:bb348c97df44 1108 {
lypinator 0:bb348c97df44 1109 spdifrx_frequency = RCC_PLL_GetFreqDomain_SPDIFRX();
lypinator 0:bb348c97df44 1110 }
lypinator 0:bb348c97df44 1111 break;
lypinator 0:bb348c97df44 1112 }
lypinator 0:bb348c97df44 1113
lypinator 0:bb348c97df44 1114 return spdifrx_frequency;
lypinator 0:bb348c97df44 1115 }
lypinator 0:bb348c97df44 1116 #endif /* SPDIFRX */
lypinator 0:bb348c97df44 1117
lypinator 0:bb348c97df44 1118 /**
lypinator 0:bb348c97df44 1119 * @}
lypinator 0:bb348c97df44 1120 */
lypinator 0:bb348c97df44 1121
lypinator 0:bb348c97df44 1122 /**
lypinator 0:bb348c97df44 1123 * @}
lypinator 0:bb348c97df44 1124 */
lypinator 0:bb348c97df44 1125
lypinator 0:bb348c97df44 1126 /** @addtogroup RCC_LL_Private_Functions
lypinator 0:bb348c97df44 1127 * @{
lypinator 0:bb348c97df44 1128 */
lypinator 0:bb348c97df44 1129
lypinator 0:bb348c97df44 1130 /**
lypinator 0:bb348c97df44 1131 * @brief Return SYSTEM clock frequency
lypinator 0:bb348c97df44 1132 * @retval SYSTEM clock frequency (in Hz)
lypinator 0:bb348c97df44 1133 */
lypinator 0:bb348c97df44 1134 uint32_t RCC_GetSystemClockFreq(void)
lypinator 0:bb348c97df44 1135 {
lypinator 0:bb348c97df44 1136 uint32_t frequency = 0U;
lypinator 0:bb348c97df44 1137
lypinator 0:bb348c97df44 1138 /* Get SYSCLK source -------------------------------------------------------*/
lypinator 0:bb348c97df44 1139 switch (LL_RCC_GetSysClkSource())
lypinator 0:bb348c97df44 1140 {
lypinator 0:bb348c97df44 1141 case LL_RCC_SYS_CLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
lypinator 0:bb348c97df44 1142 frequency = HSI_VALUE;
lypinator 0:bb348c97df44 1143 break;
lypinator 0:bb348c97df44 1144
lypinator 0:bb348c97df44 1145 case LL_RCC_SYS_CLKSOURCE_STATUS_HSE: /* HSE used as system clock source */
lypinator 0:bb348c97df44 1146 frequency = HSE_VALUE;
lypinator 0:bb348c97df44 1147 break;
lypinator 0:bb348c97df44 1148
lypinator 0:bb348c97df44 1149 case LL_RCC_SYS_CLKSOURCE_STATUS_PLL: /* PLL used as system clock source */
lypinator 0:bb348c97df44 1150 frequency = RCC_PLL_GetFreqDomain_SYS(LL_RCC_SYS_CLKSOURCE_STATUS_PLL);
lypinator 0:bb348c97df44 1151 break;
lypinator 0:bb348c97df44 1152
lypinator 0:bb348c97df44 1153 #if defined(RCC_PLLR_SYSCLK_SUPPORT)
lypinator 0:bb348c97df44 1154 case LL_RCC_SYS_CLKSOURCE_STATUS_PLLR: /* PLLR used as system clock source */
lypinator 0:bb348c97df44 1155 frequency = RCC_PLL_GetFreqDomain_SYS(LL_RCC_SYS_CLKSOURCE_STATUS_PLLR);
lypinator 0:bb348c97df44 1156 break;
lypinator 0:bb348c97df44 1157 #endif /* RCC_PLLR_SYSCLK_SUPPORT */
lypinator 0:bb348c97df44 1158
lypinator 0:bb348c97df44 1159 default:
lypinator 0:bb348c97df44 1160 frequency = HSI_VALUE;
lypinator 0:bb348c97df44 1161 break;
lypinator 0:bb348c97df44 1162 }
lypinator 0:bb348c97df44 1163
lypinator 0:bb348c97df44 1164 return frequency;
lypinator 0:bb348c97df44 1165 }
lypinator 0:bb348c97df44 1166
lypinator 0:bb348c97df44 1167 /**
lypinator 0:bb348c97df44 1168 * @brief Return HCLK clock frequency
lypinator 0:bb348c97df44 1169 * @param SYSCLK_Frequency SYSCLK clock frequency
lypinator 0:bb348c97df44 1170 * @retval HCLK clock frequency (in Hz)
lypinator 0:bb348c97df44 1171 */
lypinator 0:bb348c97df44 1172 uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)
lypinator 0:bb348c97df44 1173 {
lypinator 0:bb348c97df44 1174 /* HCLK clock frequency */
lypinator 0:bb348c97df44 1175 return __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler());
lypinator 0:bb348c97df44 1176 }
lypinator 0:bb348c97df44 1177
lypinator 0:bb348c97df44 1178 /**
lypinator 0:bb348c97df44 1179 * @brief Return PCLK1 clock frequency
lypinator 0:bb348c97df44 1180 * @param HCLK_Frequency HCLK clock frequency
lypinator 0:bb348c97df44 1181 * @retval PCLK1 clock frequency (in Hz)
lypinator 0:bb348c97df44 1182 */
lypinator 0:bb348c97df44 1183 uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)
lypinator 0:bb348c97df44 1184 {
lypinator 0:bb348c97df44 1185 /* PCLK1 clock frequency */
lypinator 0:bb348c97df44 1186 return __LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler());
lypinator 0:bb348c97df44 1187 }
lypinator 0:bb348c97df44 1188
lypinator 0:bb348c97df44 1189 /**
lypinator 0:bb348c97df44 1190 * @brief Return PCLK2 clock frequency
lypinator 0:bb348c97df44 1191 * @param HCLK_Frequency HCLK clock frequency
lypinator 0:bb348c97df44 1192 * @retval PCLK2 clock frequency (in Hz)
lypinator 0:bb348c97df44 1193 */
lypinator 0:bb348c97df44 1194 uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency)
lypinator 0:bb348c97df44 1195 {
lypinator 0:bb348c97df44 1196 /* PCLK2 clock frequency */
lypinator 0:bb348c97df44 1197 return __LL_RCC_CALC_PCLK2_FREQ(HCLK_Frequency, LL_RCC_GetAPB2Prescaler());
lypinator 0:bb348c97df44 1198 }
lypinator 0:bb348c97df44 1199
lypinator 0:bb348c97df44 1200 /**
lypinator 0:bb348c97df44 1201 * @brief Return PLL clock frequency used for system domain
lypinator 0:bb348c97df44 1202 * @param SYSCLK_Source System clock source
lypinator 0:bb348c97df44 1203 * @retval PLL clock frequency (in Hz)
lypinator 0:bb348c97df44 1204 */
lypinator 0:bb348c97df44 1205 uint32_t RCC_PLL_GetFreqDomain_SYS(uint32_t SYSCLK_Source)
lypinator 0:bb348c97df44 1206 {
lypinator 0:bb348c97df44 1207 uint32_t pllinputfreq = 0U, pllsource = 0U, plloutputfreq = 0U;
lypinator 0:bb348c97df44 1208
lypinator 0:bb348c97df44 1209 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
lypinator 0:bb348c97df44 1210 SYSCLK = PLL_VCO / (PLLP or PLLR)
lypinator 0:bb348c97df44 1211 */
lypinator 0:bb348c97df44 1212 pllsource = LL_RCC_PLL_GetMainSource();
lypinator 0:bb348c97df44 1213
lypinator 0:bb348c97df44 1214 switch (pllsource)
lypinator 0:bb348c97df44 1215 {
lypinator 0:bb348c97df44 1216 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
lypinator 0:bb348c97df44 1217 pllinputfreq = HSI_VALUE;
lypinator 0:bb348c97df44 1218 break;
lypinator 0:bb348c97df44 1219
lypinator 0:bb348c97df44 1220 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
lypinator 0:bb348c97df44 1221 pllinputfreq = HSE_VALUE;
lypinator 0:bb348c97df44 1222 break;
lypinator 0:bb348c97df44 1223
lypinator 0:bb348c97df44 1224 default:
lypinator 0:bb348c97df44 1225 pllinputfreq = HSI_VALUE;
lypinator 0:bb348c97df44 1226 break;
lypinator 0:bb348c97df44 1227 }
lypinator 0:bb348c97df44 1228
lypinator 0:bb348c97df44 1229 if (SYSCLK_Source == LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
lypinator 0:bb348c97df44 1230 {
lypinator 0:bb348c97df44 1231 plloutputfreq = __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
lypinator 0:bb348c97df44 1232 LL_RCC_PLL_GetN(), LL_RCC_PLL_GetP());
lypinator 0:bb348c97df44 1233 }
lypinator 0:bb348c97df44 1234 #if defined(RCC_PLLR_SYSCLK_SUPPORT)
lypinator 0:bb348c97df44 1235 else
lypinator 0:bb348c97df44 1236 {
lypinator 0:bb348c97df44 1237 plloutputfreq = __LL_RCC_CALC_PLLRCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
lypinator 0:bb348c97df44 1238 LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR());
lypinator 0:bb348c97df44 1239 }
lypinator 0:bb348c97df44 1240 #endif /* RCC_PLLR_SYSCLK_SUPPORT */
lypinator 0:bb348c97df44 1241
lypinator 0:bb348c97df44 1242 return plloutputfreq;
lypinator 0:bb348c97df44 1243 }
lypinator 0:bb348c97df44 1244
lypinator 0:bb348c97df44 1245 /**
lypinator 0:bb348c97df44 1246 * @brief Return PLL clock frequency used for 48 MHz domain
lypinator 0:bb348c97df44 1247 * @retval PLL clock frequency (in Hz)
lypinator 0:bb348c97df44 1248 */
lypinator 0:bb348c97df44 1249 uint32_t RCC_PLL_GetFreqDomain_48M(void)
lypinator 0:bb348c97df44 1250 {
lypinator 0:bb348c97df44 1251 uint32_t pllinputfreq = 0U, pllsource = 0U;
lypinator 0:bb348c97df44 1252
lypinator 0:bb348c97df44 1253 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM ) * PLLN
lypinator 0:bb348c97df44 1254 48M Domain clock = PLL_VCO / PLLQ
lypinator 0:bb348c97df44 1255 */
lypinator 0:bb348c97df44 1256 pllsource = LL_RCC_PLL_GetMainSource();
lypinator 0:bb348c97df44 1257
lypinator 0:bb348c97df44 1258 switch (pllsource)
lypinator 0:bb348c97df44 1259 {
lypinator 0:bb348c97df44 1260 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
lypinator 0:bb348c97df44 1261 pllinputfreq = HSI_VALUE;
lypinator 0:bb348c97df44 1262 break;
lypinator 0:bb348c97df44 1263
lypinator 0:bb348c97df44 1264 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
lypinator 0:bb348c97df44 1265 pllinputfreq = HSE_VALUE;
lypinator 0:bb348c97df44 1266 break;
lypinator 0:bb348c97df44 1267
lypinator 0:bb348c97df44 1268 default:
lypinator 0:bb348c97df44 1269 pllinputfreq = HSI_VALUE;
lypinator 0:bb348c97df44 1270 break;
lypinator 0:bb348c97df44 1271 }
lypinator 0:bb348c97df44 1272 return __LL_RCC_CALC_PLLCLK_48M_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
lypinator 0:bb348c97df44 1273 LL_RCC_PLL_GetN(), LL_RCC_PLL_GetQ());
lypinator 0:bb348c97df44 1274 }
lypinator 0:bb348c97df44 1275
lypinator 0:bb348c97df44 1276 #if defined(DSI)
lypinator 0:bb348c97df44 1277 /**
lypinator 0:bb348c97df44 1278 * @brief Return PLL clock frequency used for DSI clock
lypinator 0:bb348c97df44 1279 * @retval PLL clock frequency (in Hz)
lypinator 0:bb348c97df44 1280 */
lypinator 0:bb348c97df44 1281 uint32_t RCC_PLL_GetFreqDomain_DSI(void)
lypinator 0:bb348c97df44 1282 {
lypinator 0:bb348c97df44 1283 uint32_t pllinputfreq = 0U, pllsource = 0U;
lypinator 0:bb348c97df44 1284
lypinator 0:bb348c97df44 1285 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
lypinator 0:bb348c97df44 1286 DSICLK = PLL_VCO / PLLR
lypinator 0:bb348c97df44 1287 */
lypinator 0:bb348c97df44 1288 pllsource = LL_RCC_PLL_GetMainSource();
lypinator 0:bb348c97df44 1289
lypinator 0:bb348c97df44 1290 switch (pllsource)
lypinator 0:bb348c97df44 1291 {
lypinator 0:bb348c97df44 1292 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
lypinator 0:bb348c97df44 1293 pllinputfreq = HSE_VALUE;
lypinator 0:bb348c97df44 1294 break;
lypinator 0:bb348c97df44 1295
lypinator 0:bb348c97df44 1296 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
lypinator 0:bb348c97df44 1297 default:
lypinator 0:bb348c97df44 1298 pllinputfreq = HSI_VALUE;
lypinator 0:bb348c97df44 1299 break;
lypinator 0:bb348c97df44 1300 }
lypinator 0:bb348c97df44 1301 return __LL_RCC_CALC_PLLCLK_DSI_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
lypinator 0:bb348c97df44 1302 LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR());
lypinator 0:bb348c97df44 1303 }
lypinator 0:bb348c97df44 1304 #endif /* DSI */
lypinator 0:bb348c97df44 1305
lypinator 0:bb348c97df44 1306 #if defined(RCC_DCKCFGR_I2SSRC) || defined(RCC_DCKCFGR_I2S1SRC)
lypinator 0:bb348c97df44 1307 /**
lypinator 0:bb348c97df44 1308 * @brief Return PLL clock frequency used for I2S clock
lypinator 0:bb348c97df44 1309 * @retval PLL clock frequency (in Hz)
lypinator 0:bb348c97df44 1310 */
lypinator 0:bb348c97df44 1311 uint32_t RCC_PLL_GetFreqDomain_I2S(void)
lypinator 0:bb348c97df44 1312 {
lypinator 0:bb348c97df44 1313 uint32_t pllinputfreq = 0U, pllsource = 0U;
lypinator 0:bb348c97df44 1314
lypinator 0:bb348c97df44 1315 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
lypinator 0:bb348c97df44 1316 I2SCLK = PLL_VCO / PLLR
lypinator 0:bb348c97df44 1317 */
lypinator 0:bb348c97df44 1318 pllsource = LL_RCC_PLL_GetMainSource();
lypinator 0:bb348c97df44 1319
lypinator 0:bb348c97df44 1320 switch (pllsource)
lypinator 0:bb348c97df44 1321 {
lypinator 0:bb348c97df44 1322 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
lypinator 0:bb348c97df44 1323 pllinputfreq = HSE_VALUE;
lypinator 0:bb348c97df44 1324 break;
lypinator 0:bb348c97df44 1325
lypinator 0:bb348c97df44 1326 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
lypinator 0:bb348c97df44 1327 default:
lypinator 0:bb348c97df44 1328 pllinputfreq = HSI_VALUE;
lypinator 0:bb348c97df44 1329 break;
lypinator 0:bb348c97df44 1330 }
lypinator 0:bb348c97df44 1331 return __LL_RCC_CALC_PLLCLK_I2S_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
lypinator 0:bb348c97df44 1332 LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR());
lypinator 0:bb348c97df44 1333 }
lypinator 0:bb348c97df44 1334 #endif /* RCC_DCKCFGR_I2SSRC || RCC_DCKCFGR_I2S1SRC */
lypinator 0:bb348c97df44 1335
lypinator 0:bb348c97df44 1336 #if defined(SPDIFRX)
lypinator 0:bb348c97df44 1337 /**
lypinator 0:bb348c97df44 1338 * @brief Return PLL clock frequency used for SPDIFRX clock
lypinator 0:bb348c97df44 1339 * @retval PLL clock frequency (in Hz)
lypinator 0:bb348c97df44 1340 */
lypinator 0:bb348c97df44 1341 uint32_t RCC_PLL_GetFreqDomain_SPDIFRX(void)
lypinator 0:bb348c97df44 1342 {
lypinator 0:bb348c97df44 1343 uint32_t pllinputfreq = 0U, pllsource = 0U;
lypinator 0:bb348c97df44 1344
lypinator 0:bb348c97df44 1345 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
lypinator 0:bb348c97df44 1346 SPDIFRXCLK = PLL_VCO / PLLR
lypinator 0:bb348c97df44 1347 */
lypinator 0:bb348c97df44 1348 pllsource = LL_RCC_PLL_GetMainSource();
lypinator 0:bb348c97df44 1349
lypinator 0:bb348c97df44 1350 switch (pllsource)
lypinator 0:bb348c97df44 1351 {
lypinator 0:bb348c97df44 1352 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
lypinator 0:bb348c97df44 1353 pllinputfreq = HSE_VALUE;
lypinator 0:bb348c97df44 1354 break;
lypinator 0:bb348c97df44 1355
lypinator 0:bb348c97df44 1356 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
lypinator 0:bb348c97df44 1357 default:
lypinator 0:bb348c97df44 1358 pllinputfreq = HSI_VALUE;
lypinator 0:bb348c97df44 1359 break;
lypinator 0:bb348c97df44 1360 }
lypinator 0:bb348c97df44 1361 return __LL_RCC_CALC_PLLCLK_SPDIFRX_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
lypinator 0:bb348c97df44 1362 LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR());
lypinator 0:bb348c97df44 1363 }
lypinator 0:bb348c97df44 1364 #endif /* SPDIFRX */
lypinator 0:bb348c97df44 1365
lypinator 0:bb348c97df44 1366 #if defined(RCC_PLLCFGR_PLLR)
lypinator 0:bb348c97df44 1367 #if defined(SAI1)
lypinator 0:bb348c97df44 1368 /**
lypinator 0:bb348c97df44 1369 * @brief Return PLL clock frequency used for SAI clock
lypinator 0:bb348c97df44 1370 * @retval PLL clock frequency (in Hz)
lypinator 0:bb348c97df44 1371 */
lypinator 0:bb348c97df44 1372 uint32_t RCC_PLL_GetFreqDomain_SAI(void)
lypinator 0:bb348c97df44 1373 {
lypinator 0:bb348c97df44 1374 uint32_t pllinputfreq = 0U, pllsource = 0U, plloutputfreq = 0U;
lypinator 0:bb348c97df44 1375
lypinator 0:bb348c97df44 1376 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
lypinator 0:bb348c97df44 1377 SAICLK = (PLL_VCO / PLLR) / PLLDIVR
lypinator 0:bb348c97df44 1378 or
lypinator 0:bb348c97df44 1379 SAICLK = PLL_VCO / PLLR
lypinator 0:bb348c97df44 1380 */
lypinator 0:bb348c97df44 1381 pllsource = LL_RCC_PLL_GetMainSource();
lypinator 0:bb348c97df44 1382
lypinator 0:bb348c97df44 1383 switch (pllsource)
lypinator 0:bb348c97df44 1384 {
lypinator 0:bb348c97df44 1385 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
lypinator 0:bb348c97df44 1386 pllinputfreq = HSE_VALUE;
lypinator 0:bb348c97df44 1387 break;
lypinator 0:bb348c97df44 1388
lypinator 0:bb348c97df44 1389 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
lypinator 0:bb348c97df44 1390 default:
lypinator 0:bb348c97df44 1391 pllinputfreq = HSI_VALUE;
lypinator 0:bb348c97df44 1392 break;
lypinator 0:bb348c97df44 1393 }
lypinator 0:bb348c97df44 1394
lypinator 0:bb348c97df44 1395 #if defined(RCC_DCKCFGR_PLLDIVR)
lypinator 0:bb348c97df44 1396 plloutputfreq = __LL_RCC_CALC_PLLCLK_SAI_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
lypinator 0:bb348c97df44 1397 LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR(), LL_RCC_PLL_GetDIVR());
lypinator 0:bb348c97df44 1398 #else
lypinator 0:bb348c97df44 1399 plloutputfreq = __LL_RCC_CALC_PLLCLK_SAI_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
lypinator 0:bb348c97df44 1400 LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR());
lypinator 0:bb348c97df44 1401 #endif /* RCC_DCKCFGR_PLLDIVR */
lypinator 0:bb348c97df44 1402
lypinator 0:bb348c97df44 1403 return plloutputfreq;
lypinator 0:bb348c97df44 1404 }
lypinator 0:bb348c97df44 1405 #endif /* SAI1 */
lypinator 0:bb348c97df44 1406 #endif /* RCC_PLLCFGR_PLLR */
lypinator 0:bb348c97df44 1407
lypinator 0:bb348c97df44 1408 #if defined(RCC_PLLSAI_SUPPORT)
lypinator 0:bb348c97df44 1409 /**
lypinator 0:bb348c97df44 1410 * @brief Return PLLSAI clock frequency used for SAI domain
lypinator 0:bb348c97df44 1411 * @retval PLLSAI clock frequency (in Hz)
lypinator 0:bb348c97df44 1412 */
lypinator 0:bb348c97df44 1413 uint32_t RCC_PLLSAI_GetFreqDomain_SAI(void)
lypinator 0:bb348c97df44 1414 {
lypinator 0:bb348c97df44 1415 uint32_t pllinputfreq = 0U, pllsource = 0U;
lypinator 0:bb348c97df44 1416
lypinator 0:bb348c97df44 1417 /* PLLSAI_VCO = (HSE_VALUE or HSI_VALUE / PLLSAIM) * PLLSAIN
lypinator 0:bb348c97df44 1418 SAI domain clock = (PLLSAI_VCO / PLLSAIQ) / PLLSAIDIVQ
lypinator 0:bb348c97df44 1419 */
lypinator 0:bb348c97df44 1420 pllsource = LL_RCC_PLL_GetMainSource();
lypinator 0:bb348c97df44 1421
lypinator 0:bb348c97df44 1422 switch (pllsource)
lypinator 0:bb348c97df44 1423 {
lypinator 0:bb348c97df44 1424 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLSAI clock source */
lypinator 0:bb348c97df44 1425 pllinputfreq = HSI_VALUE;
lypinator 0:bb348c97df44 1426 break;
lypinator 0:bb348c97df44 1427
lypinator 0:bb348c97df44 1428 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI clock source */
lypinator 0:bb348c97df44 1429 pllinputfreq = HSE_VALUE;
lypinator 0:bb348c97df44 1430 break;
lypinator 0:bb348c97df44 1431
lypinator 0:bb348c97df44 1432 default:
lypinator 0:bb348c97df44 1433 pllinputfreq = HSI_VALUE;
lypinator 0:bb348c97df44 1434 break;
lypinator 0:bb348c97df44 1435 }
lypinator 0:bb348c97df44 1436 return __LL_RCC_CALC_PLLSAI_SAI_FREQ(pllinputfreq, LL_RCC_PLLSAI_GetDivider(),
lypinator 0:bb348c97df44 1437 LL_RCC_PLLSAI_GetN(), LL_RCC_PLLSAI_GetQ(), LL_RCC_PLLSAI_GetDIVQ());
lypinator 0:bb348c97df44 1438 }
lypinator 0:bb348c97df44 1439
lypinator 0:bb348c97df44 1440 #if defined(RCC_PLLSAICFGR_PLLSAIP)
lypinator 0:bb348c97df44 1441 /**
lypinator 0:bb348c97df44 1442 * @brief Return PLLSAI clock frequency used for 48Mhz domain
lypinator 0:bb348c97df44 1443 * @retval PLLSAI clock frequency (in Hz)
lypinator 0:bb348c97df44 1444 */
lypinator 0:bb348c97df44 1445 uint32_t RCC_PLLSAI_GetFreqDomain_48M(void)
lypinator 0:bb348c97df44 1446 {
lypinator 0:bb348c97df44 1447 uint32_t pllinputfreq = 0U, pllsource = 0U;
lypinator 0:bb348c97df44 1448
lypinator 0:bb348c97df44 1449 /* PLLSAI_VCO = (HSE_VALUE or HSI_VALUE / PLLSAIM) * PLLSAIN
lypinator 0:bb348c97df44 1450 48M Domain clock = PLLSAI_VCO / PLLSAIP
lypinator 0:bb348c97df44 1451 */
lypinator 0:bb348c97df44 1452 pllsource = LL_RCC_PLL_GetMainSource();
lypinator 0:bb348c97df44 1453
lypinator 0:bb348c97df44 1454 switch (pllsource)
lypinator 0:bb348c97df44 1455 {
lypinator 0:bb348c97df44 1456 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLSAI clock source */
lypinator 0:bb348c97df44 1457 pllinputfreq = HSI_VALUE;
lypinator 0:bb348c97df44 1458 break;
lypinator 0:bb348c97df44 1459
lypinator 0:bb348c97df44 1460 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI clock source */
lypinator 0:bb348c97df44 1461 pllinputfreq = HSE_VALUE;
lypinator 0:bb348c97df44 1462 break;
lypinator 0:bb348c97df44 1463
lypinator 0:bb348c97df44 1464 default:
lypinator 0:bb348c97df44 1465 pllinputfreq = HSI_VALUE;
lypinator 0:bb348c97df44 1466 break;
lypinator 0:bb348c97df44 1467 }
lypinator 0:bb348c97df44 1468 return __LL_RCC_CALC_PLLSAI_48M_FREQ(pllinputfreq, LL_RCC_PLLSAI_GetDivider(),
lypinator 0:bb348c97df44 1469 LL_RCC_PLLSAI_GetN(), LL_RCC_PLLSAI_GetP());
lypinator 0:bb348c97df44 1470 }
lypinator 0:bb348c97df44 1471 #endif /* RCC_PLLSAICFGR_PLLSAIP */
lypinator 0:bb348c97df44 1472
lypinator 0:bb348c97df44 1473 #if defined(LTDC)
lypinator 0:bb348c97df44 1474 /**
lypinator 0:bb348c97df44 1475 * @brief Return PLLSAI clock frequency used for LTDC domain
lypinator 0:bb348c97df44 1476 * @retval PLLSAI clock frequency (in Hz)
lypinator 0:bb348c97df44 1477 */
lypinator 0:bb348c97df44 1478 uint32_t RCC_PLLSAI_GetFreqDomain_LTDC(void)
lypinator 0:bb348c97df44 1479 {
lypinator 0:bb348c97df44 1480 uint32_t pllinputfreq = 0U, pllsource = 0U;
lypinator 0:bb348c97df44 1481
lypinator 0:bb348c97df44 1482 /* PLLSAI_VCO = (HSE_VALUE or HSI_VALUE / PLLSAIM) * PLLSAIN
lypinator 0:bb348c97df44 1483 LTDC Domain clock = (PLLSAI_VCO / PLLSAIR) / PLLSAIDIVR
lypinator 0:bb348c97df44 1484 */
lypinator 0:bb348c97df44 1485 pllsource = LL_RCC_PLL_GetMainSource();
lypinator 0:bb348c97df44 1486
lypinator 0:bb348c97df44 1487 switch (pllsource)
lypinator 0:bb348c97df44 1488 {
lypinator 0:bb348c97df44 1489 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLSAI clock source */
lypinator 0:bb348c97df44 1490 pllinputfreq = HSI_VALUE;
lypinator 0:bb348c97df44 1491 break;
lypinator 0:bb348c97df44 1492
lypinator 0:bb348c97df44 1493 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI clock source */
lypinator 0:bb348c97df44 1494 pllinputfreq = HSE_VALUE;
lypinator 0:bb348c97df44 1495 break;
lypinator 0:bb348c97df44 1496
lypinator 0:bb348c97df44 1497 default:
lypinator 0:bb348c97df44 1498 pllinputfreq = HSI_VALUE;
lypinator 0:bb348c97df44 1499 break;
lypinator 0:bb348c97df44 1500 }
lypinator 0:bb348c97df44 1501 return __LL_RCC_CALC_PLLSAI_LTDC_FREQ(pllinputfreq, LL_RCC_PLLSAI_GetDivider(),
lypinator 0:bb348c97df44 1502 LL_RCC_PLLSAI_GetN(), LL_RCC_PLLSAI_GetR(), LL_RCC_PLLSAI_GetDIVR());
lypinator 0:bb348c97df44 1503 }
lypinator 0:bb348c97df44 1504 #endif /* LTDC */
lypinator 0:bb348c97df44 1505 #endif /* RCC_PLLSAI_SUPPORT */
lypinator 0:bb348c97df44 1506
lypinator 0:bb348c97df44 1507 #if defined(RCC_PLLI2S_SUPPORT)
lypinator 0:bb348c97df44 1508 #if defined(SAI1)
lypinator 0:bb348c97df44 1509 /**
lypinator 0:bb348c97df44 1510 * @brief Return PLLI2S clock frequency used for SAI domains
lypinator 0:bb348c97df44 1511 * @retval PLLI2S clock frequency (in Hz)
lypinator 0:bb348c97df44 1512 */
lypinator 0:bb348c97df44 1513 uint32_t RCC_PLLI2S_GetFreqDomain_SAI(void)
lypinator 0:bb348c97df44 1514 {
lypinator 0:bb348c97df44 1515 uint32_t plli2sinputfreq = 0U, plli2ssource = 0U, plli2soutputfreq = 0U;
lypinator 0:bb348c97df44 1516
lypinator 0:bb348c97df44 1517 /* PLLI2S_VCO = (HSE_VALUE or HSI_VALUE / PLLI2SM) * PLLI2SN
lypinator 0:bb348c97df44 1518 SAI domain clock = (PLLI2S_VCO / PLLI2SQ) / PLLI2SDIVQ
lypinator 0:bb348c97df44 1519 or
lypinator 0:bb348c97df44 1520 SAI domain clock = (PLLI2S_VCO / PLLI2SR) / PLLI2SDIVR
lypinator 0:bb348c97df44 1521 */
lypinator 0:bb348c97df44 1522 plli2ssource = LL_RCC_PLLI2S_GetMainSource();
lypinator 0:bb348c97df44 1523
lypinator 0:bb348c97df44 1524 switch (plli2ssource)
lypinator 0:bb348c97df44 1525 {
lypinator 0:bb348c97df44 1526 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLI2S clock source */
lypinator 0:bb348c97df44 1527 plli2sinputfreq = HSE_VALUE;
lypinator 0:bb348c97df44 1528 break;
lypinator 0:bb348c97df44 1529
lypinator 0:bb348c97df44 1530 #if defined(RCC_PLLI2SCFGR_PLLI2SSRC)
lypinator 0:bb348c97df44 1531 case LL_RCC_PLLI2SSOURCE_PIN: /* External pin input clock used as PLLI2S clock source */
lypinator 0:bb348c97df44 1532 plli2sinputfreq = EXTERNAL_CLOCK_VALUE;
lypinator 0:bb348c97df44 1533 break;
lypinator 0:bb348c97df44 1534 #endif /* RCC_PLLI2SCFGR_PLLI2SSRC */
lypinator 0:bb348c97df44 1535
lypinator 0:bb348c97df44 1536 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLI2S clock source */
lypinator 0:bb348c97df44 1537 default:
lypinator 0:bb348c97df44 1538 plli2sinputfreq = HSI_VALUE;
lypinator 0:bb348c97df44 1539 break;
lypinator 0:bb348c97df44 1540 }
lypinator 0:bb348c97df44 1541
lypinator 0:bb348c97df44 1542 #if defined(RCC_DCKCFGR_PLLI2SDIVQ)
lypinator 0:bb348c97df44 1543 plli2soutputfreq = __LL_RCC_CALC_PLLI2S_SAI_FREQ(plli2sinputfreq, LL_RCC_PLLI2S_GetDivider(),
lypinator 0:bb348c97df44 1544 LL_RCC_PLLI2S_GetN(), LL_RCC_PLLI2S_GetQ(), LL_RCC_PLLI2S_GetDIVQ());
lypinator 0:bb348c97df44 1545 #else
lypinator 0:bb348c97df44 1546 plli2soutputfreq = __LL_RCC_CALC_PLLI2S_SAI_FREQ(plli2sinputfreq, LL_RCC_PLLI2S_GetDivider(),
lypinator 0:bb348c97df44 1547 LL_RCC_PLLI2S_GetN(), LL_RCC_PLLI2S_GetR(), LL_RCC_PLLI2S_GetDIVR());
lypinator 0:bb348c97df44 1548 #endif /* RCC_DCKCFGR_PLLI2SDIVQ */
lypinator 0:bb348c97df44 1549
lypinator 0:bb348c97df44 1550 return plli2soutputfreq;
lypinator 0:bb348c97df44 1551 }
lypinator 0:bb348c97df44 1552 #endif /* SAI1 */
lypinator 0:bb348c97df44 1553
lypinator 0:bb348c97df44 1554 #if defined(SPDIFRX)
lypinator 0:bb348c97df44 1555 /**
lypinator 0:bb348c97df44 1556 * @brief Return PLLI2S clock frequency used for SPDIFRX domain
lypinator 0:bb348c97df44 1557 * @retval PLLI2S clock frequency (in Hz)
lypinator 0:bb348c97df44 1558 */
lypinator 0:bb348c97df44 1559 uint32_t RCC_PLLI2S_GetFreqDomain_SPDIFRX(void)
lypinator 0:bb348c97df44 1560 {
lypinator 0:bb348c97df44 1561 uint32_t pllinputfreq = 0U, pllsource = 0U;
lypinator 0:bb348c97df44 1562
lypinator 0:bb348c97df44 1563 /* PLLI2S_VCO = (HSE_VALUE or HSI_VALUE / PLLI2SM) * PLLI2SN
lypinator 0:bb348c97df44 1564 SPDIFRX Domain clock = PLLI2S_VCO / PLLI2SP
lypinator 0:bb348c97df44 1565 */
lypinator 0:bb348c97df44 1566 pllsource = LL_RCC_PLLI2S_GetMainSource();
lypinator 0:bb348c97df44 1567
lypinator 0:bb348c97df44 1568 switch (pllsource)
lypinator 0:bb348c97df44 1569 {
lypinator 0:bb348c97df44 1570 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLI2S clock source */
lypinator 0:bb348c97df44 1571 pllinputfreq = HSE_VALUE;
lypinator 0:bb348c97df44 1572 break;
lypinator 0:bb348c97df44 1573
lypinator 0:bb348c97df44 1574 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLI2S clock source */
lypinator 0:bb348c97df44 1575 default:
lypinator 0:bb348c97df44 1576 pllinputfreq = HSI_VALUE;
lypinator 0:bb348c97df44 1577 break;
lypinator 0:bb348c97df44 1578 }
lypinator 0:bb348c97df44 1579
lypinator 0:bb348c97df44 1580 return __LL_RCC_CALC_PLLI2S_SPDIFRX_FREQ(pllinputfreq, LL_RCC_PLLI2S_GetDivider(),
lypinator 0:bb348c97df44 1581 LL_RCC_PLLI2S_GetN(), LL_RCC_PLLI2S_GetP());
lypinator 0:bb348c97df44 1582 }
lypinator 0:bb348c97df44 1583 #endif /* SPDIFRX */
lypinator 0:bb348c97df44 1584
lypinator 0:bb348c97df44 1585 /**
lypinator 0:bb348c97df44 1586 * @brief Return PLLI2S clock frequency used for I2S domain
lypinator 0:bb348c97df44 1587 * @retval PLLI2S clock frequency (in Hz)
lypinator 0:bb348c97df44 1588 */
lypinator 0:bb348c97df44 1589 uint32_t RCC_PLLI2S_GetFreqDomain_I2S(void)
lypinator 0:bb348c97df44 1590 {
lypinator 0:bb348c97df44 1591 uint32_t plli2sinputfreq = 0U, plli2ssource = 0U, plli2soutputfreq = 0U;
lypinator 0:bb348c97df44 1592
lypinator 0:bb348c97df44 1593 /* PLLI2S_VCO = (HSE_VALUE or HSI_VALUE / PLLI2SM) * PLLI2SN
lypinator 0:bb348c97df44 1594 I2S Domain clock = PLLI2S_VCO / PLLI2SR
lypinator 0:bb348c97df44 1595 */
lypinator 0:bb348c97df44 1596 plli2ssource = LL_RCC_PLLI2S_GetMainSource();
lypinator 0:bb348c97df44 1597
lypinator 0:bb348c97df44 1598 switch (plli2ssource)
lypinator 0:bb348c97df44 1599 {
lypinator 0:bb348c97df44 1600 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLI2S clock source */
lypinator 0:bb348c97df44 1601 plli2sinputfreq = HSE_VALUE;
lypinator 0:bb348c97df44 1602 break;
lypinator 0:bb348c97df44 1603
lypinator 0:bb348c97df44 1604 #if defined(RCC_PLLI2SCFGR_PLLI2SSRC)
lypinator 0:bb348c97df44 1605 case LL_RCC_PLLI2SSOURCE_PIN: /* External pin input clock used as PLLI2S clock source */
lypinator 0:bb348c97df44 1606 plli2sinputfreq = EXTERNAL_CLOCK_VALUE;
lypinator 0:bb348c97df44 1607 break;
lypinator 0:bb348c97df44 1608 #endif /* RCC_PLLI2SCFGR_PLLI2SSRC */
lypinator 0:bb348c97df44 1609
lypinator 0:bb348c97df44 1610 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLI2S clock source */
lypinator 0:bb348c97df44 1611 default:
lypinator 0:bb348c97df44 1612 plli2sinputfreq = HSI_VALUE;
lypinator 0:bb348c97df44 1613 break;
lypinator 0:bb348c97df44 1614 }
lypinator 0:bb348c97df44 1615
lypinator 0:bb348c97df44 1616 plli2soutputfreq = __LL_RCC_CALC_PLLI2S_I2S_FREQ(plli2sinputfreq, LL_RCC_PLLI2S_GetDivider(),
lypinator 0:bb348c97df44 1617 LL_RCC_PLLI2S_GetN(), LL_RCC_PLLI2S_GetR());
lypinator 0:bb348c97df44 1618
lypinator 0:bb348c97df44 1619 return plli2soutputfreq;
lypinator 0:bb348c97df44 1620 }
lypinator 0:bb348c97df44 1621
lypinator 0:bb348c97df44 1622 #if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
lypinator 0:bb348c97df44 1623 /**
lypinator 0:bb348c97df44 1624 * @brief Return PLLI2S clock frequency used for 48Mhz domain
lypinator 0:bb348c97df44 1625 * @retval PLLI2S clock frequency (in Hz)
lypinator 0:bb348c97df44 1626 */
lypinator 0:bb348c97df44 1627 uint32_t RCC_PLLI2S_GetFreqDomain_48M(void)
lypinator 0:bb348c97df44 1628 {
lypinator 0:bb348c97df44 1629 uint32_t plli2sinputfreq = 0U, plli2ssource = 0U, plli2soutputfreq = 0U;
lypinator 0:bb348c97df44 1630
lypinator 0:bb348c97df44 1631 /* PLL48M_VCO = (HSE_VALUE or HSI_VALUE / PLLI2SM) * PLLI2SN
lypinator 0:bb348c97df44 1632 48M Domain clock = PLLI2S_VCO / PLLI2SQ
lypinator 0:bb348c97df44 1633 */
lypinator 0:bb348c97df44 1634 plli2ssource = LL_RCC_PLLI2S_GetMainSource();
lypinator 0:bb348c97df44 1635
lypinator 0:bb348c97df44 1636 switch (plli2ssource)
lypinator 0:bb348c97df44 1637 {
lypinator 0:bb348c97df44 1638 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLI2S clock source */
lypinator 0:bb348c97df44 1639 plli2sinputfreq = HSE_VALUE;
lypinator 0:bb348c97df44 1640 break;
lypinator 0:bb348c97df44 1641
lypinator 0:bb348c97df44 1642 #if defined(RCC_PLLI2SCFGR_PLLI2SSRC)
lypinator 0:bb348c97df44 1643 case LL_RCC_PLLI2SSOURCE_PIN: /* External pin input clock used as PLLI2S clock source */
lypinator 0:bb348c97df44 1644 plli2sinputfreq = EXTERNAL_CLOCK_VALUE;
lypinator 0:bb348c97df44 1645 break;
lypinator 0:bb348c97df44 1646 #endif /* RCC_PLLI2SCFGR_PLLI2SSRC */
lypinator 0:bb348c97df44 1647
lypinator 0:bb348c97df44 1648 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLI2S clock source */
lypinator 0:bb348c97df44 1649 default:
lypinator 0:bb348c97df44 1650 plli2sinputfreq = HSI_VALUE;
lypinator 0:bb348c97df44 1651 break;
lypinator 0:bb348c97df44 1652 }
lypinator 0:bb348c97df44 1653
lypinator 0:bb348c97df44 1654 plli2soutputfreq = __LL_RCC_CALC_PLLI2S_48M_FREQ(plli2sinputfreq, LL_RCC_PLLI2S_GetDivider(),
lypinator 0:bb348c97df44 1655 LL_RCC_PLLI2S_GetN(), LL_RCC_PLLI2S_GetQ());
lypinator 0:bb348c97df44 1656
lypinator 0:bb348c97df44 1657 return plli2soutputfreq;
lypinator 0:bb348c97df44 1658 }
lypinator 0:bb348c97df44 1659 #endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
lypinator 0:bb348c97df44 1660 #endif /* RCC_PLLI2S_SUPPORT */
lypinator 0:bb348c97df44 1661 /**
lypinator 0:bb348c97df44 1662 * @}
lypinator 0:bb348c97df44 1663 */
lypinator 0:bb348c97df44 1664
lypinator 0:bb348c97df44 1665 /**
lypinator 0:bb348c97df44 1666 * @}
lypinator 0:bb348c97df44 1667 */
lypinator 0:bb348c97df44 1668
lypinator 0:bb348c97df44 1669 #endif /* defined(RCC) */
lypinator 0:bb348c97df44 1670
lypinator 0:bb348c97df44 1671 /**
lypinator 0:bb348c97df44 1672 * @}
lypinator 0:bb348c97df44 1673 */
lypinator 0:bb348c97df44 1674
lypinator 0:bb348c97df44 1675 #endif /* USE_FULL_LL_DRIVER */
lypinator 0:bb348c97df44 1676
lypinator 0:bb348c97df44 1677 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/