Thomas Lyp / DevLibMemoryController

Initial commit

Dependencies:   FastPWM

mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_pwr.h@0:bb348c97df44, 2020-09-16 (annotated)

Committer:
lypinator
Date:
Wed Sep 16 01:11:49 2020 +0000
Revision:
0:bb348c97df44
Added PWM

Who changed what in which revision?

UserRevisionLine numberNew contents of line
lypinator 0:bb348c97df44 1 /**
lypinator 0:bb348c97df44 2 ******************************************************************************
lypinator 0:bb348c97df44 3 * @file stm32f4xx_ll_pwr.h
lypinator 0:bb348c97df44 4 * @author MCD Application Team
lypinator 0:bb348c97df44 5 * @brief Header file of PWR LL module.
lypinator 0:bb348c97df44 6 ******************************************************************************
lypinator 0:bb348c97df44 7 * @attention
lypinator 0:bb348c97df44 8 *
lypinator 0:bb348c97df44 9 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
lypinator 0:bb348c97df44 10 *
lypinator 0:bb348c97df44 11 * Redistribution and use in source and binary forms, with or without modification,
lypinator 0:bb348c97df44 12 * are permitted provided that the following conditions are met:
lypinator 0:bb348c97df44 13 * 1. Redistributions of source code must retain the above copyright notice,
lypinator 0:bb348c97df44 14 * this list of conditions and the following disclaimer.
lypinator 0:bb348c97df44 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
lypinator 0:bb348c97df44 16 * this list of conditions and the following disclaimer in the documentation
lypinator 0:bb348c97df44 17 * and/or other materials provided with the distribution.
lypinator 0:bb348c97df44 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
lypinator 0:bb348c97df44 19 * may be used to endorse or promote products derived from this software
lypinator 0:bb348c97df44 20 * without specific prior written permission.
lypinator 0:bb348c97df44 21 *
lypinator 0:bb348c97df44 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
lypinator 0:bb348c97df44 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
lypinator 0:bb348c97df44 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
lypinator 0:bb348c97df44 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
lypinator 0:bb348c97df44 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
lypinator 0:bb348c97df44 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
lypinator 0:bb348c97df44 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
lypinator 0:bb348c97df44 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
lypinator 0:bb348c97df44 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
lypinator 0:bb348c97df44 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
lypinator 0:bb348c97df44 32 *
lypinator 0:bb348c97df44 33 ******************************************************************************
lypinator 0:bb348c97df44 34 */
lypinator 0:bb348c97df44 35
lypinator 0:bb348c97df44 36 /* Define to prevent recursive inclusion -------------------------------------*/
lypinator 0:bb348c97df44 37 #ifndef __STM32F4xx_LL_PWR_H
lypinator 0:bb348c97df44 38 #define __STM32F4xx_LL_PWR_H
lypinator 0:bb348c97df44 39
lypinator 0:bb348c97df44 40 #ifdef __cplusplus
lypinator 0:bb348c97df44 41 extern "C" {
lypinator 0:bb348c97df44 42 #endif
lypinator 0:bb348c97df44 43
lypinator 0:bb348c97df44 44 /* Includes ------------------------------------------------------------------*/
lypinator 0:bb348c97df44 45 #include "stm32f4xx.h"
lypinator 0:bb348c97df44 46
lypinator 0:bb348c97df44 47 /** @addtogroup STM32F4xx_LL_Driver
lypinator 0:bb348c97df44 48 * @{
lypinator 0:bb348c97df44 49 */
lypinator 0:bb348c97df44 50
lypinator 0:bb348c97df44 51 #if defined(PWR)
lypinator 0:bb348c97df44 52
lypinator 0:bb348c97df44 53 /** @defgroup PWR_LL PWR
lypinator 0:bb348c97df44 54 * @{
lypinator 0:bb348c97df44 55 */
lypinator 0:bb348c97df44 56
lypinator 0:bb348c97df44 57 /* Private types -------------------------------------------------------------*/
lypinator 0:bb348c97df44 58 /* Private variables ---------------------------------------------------------*/
lypinator 0:bb348c97df44 59 /* Private constants ---------------------------------------------------------*/
lypinator 0:bb348c97df44 60 /* Private macros ------------------------------------------------------------*/
lypinator 0:bb348c97df44 61 /* Exported types ------------------------------------------------------------*/
lypinator 0:bb348c97df44 62 /* Exported constants --------------------------------------------------------*/
lypinator 0:bb348c97df44 63 /** @defgroup PWR_LL_Exported_Constants PWR Exported Constants
lypinator 0:bb348c97df44 64 * @{
lypinator 0:bb348c97df44 65 */
lypinator 0:bb348c97df44 66
lypinator 0:bb348c97df44 67 /** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines
lypinator 0:bb348c97df44 68 * @brief Flags defines which can be used with LL_PWR_WriteReg function
lypinator 0:bb348c97df44 69 * @{
lypinator 0:bb348c97df44 70 */
lypinator 0:bb348c97df44 71 #define LL_PWR_CR_CSBF PWR_CR_CSBF /*!< Clear standby flag */
lypinator 0:bb348c97df44 72 #define LL_PWR_CR_CWUF PWR_CR_CWUF /*!< Clear wakeup flag */
lypinator 0:bb348c97df44 73 /**
lypinator 0:bb348c97df44 74 * @}
lypinator 0:bb348c97df44 75 */
lypinator 0:bb348c97df44 76
lypinator 0:bb348c97df44 77 /** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines
lypinator 0:bb348c97df44 78 * @brief Flags defines which can be used with LL_PWR_ReadReg function
lypinator 0:bb348c97df44 79 * @{
lypinator 0:bb348c97df44 80 */
lypinator 0:bb348c97df44 81 #define LL_PWR_CSR_WUF PWR_CSR_WUF /*!< Wakeup flag */
lypinator 0:bb348c97df44 82 #define LL_PWR_CSR_SBF PWR_CSR_SBF /*!< Standby flag */
lypinator 0:bb348c97df44 83 #define LL_PWR_CSR_PVDO PWR_CSR_PVDO /*!< Power voltage detector output flag */
lypinator 0:bb348c97df44 84 #define LL_PWR_CSR_VOS PWR_CSR_VOSRDY /*!< Voltage scaling select flag */
lypinator 0:bb348c97df44 85 #if defined(PWR_CSR_EWUP)
lypinator 0:bb348c97df44 86 #define LL_PWR_CSR_EWUP1 PWR_CSR_EWUP /*!< Enable WKUP pin */
lypinator 0:bb348c97df44 87 #elif defined(PWR_CSR_EWUP1)
lypinator 0:bb348c97df44 88 #define LL_PWR_CSR_EWUP1 PWR_CSR_EWUP1 /*!< Enable WKUP pin 1 */
lypinator 0:bb348c97df44 89 #endif /* PWR_CSR_EWUP */
lypinator 0:bb348c97df44 90 #if defined(PWR_CSR_EWUP2)
lypinator 0:bb348c97df44 91 #define LL_PWR_CSR_EWUP2 PWR_CSR_EWUP2 /*!< Enable WKUP pin 2 */
lypinator 0:bb348c97df44 92 #endif /* PWR_CSR_EWUP2 */
lypinator 0:bb348c97df44 93 #if defined(PWR_CSR_EWUP3)
lypinator 0:bb348c97df44 94 #define LL_PWR_CSR_EWUP3 PWR_CSR_EWUP3 /*!< Enable WKUP pin 3 */
lypinator 0:bb348c97df44 95 #endif /* PWR_CSR_EWUP3 */
lypinator 0:bb348c97df44 96 /**
lypinator 0:bb348c97df44 97 * @}
lypinator 0:bb348c97df44 98 */
lypinator 0:bb348c97df44 99
lypinator 0:bb348c97df44 100 /** @defgroup PWR_LL_EC_REGU_VOLTAGE Regulator Voltage
lypinator 0:bb348c97df44 101 * @{
lypinator 0:bb348c97df44 102 */
lypinator 0:bb348c97df44 103 #if defined(PWR_CR_VOS_0)
lypinator 0:bb348c97df44 104 #define LL_PWR_REGU_VOLTAGE_SCALE3 (PWR_CR_VOS_0)
lypinator 0:bb348c97df44 105 #define LL_PWR_REGU_VOLTAGE_SCALE2 (PWR_CR_VOS_1)
lypinator 0:bb348c97df44 106 #define LL_PWR_REGU_VOLTAGE_SCALE1 (PWR_CR_VOS_0 | PWR_CR_VOS_1) /* The SCALE1 is not available for STM32F401xx devices */
lypinator 0:bb348c97df44 107 #else
lypinator 0:bb348c97df44 108 #define LL_PWR_REGU_VOLTAGE_SCALE1 (PWR_CR_VOS)
lypinator 0:bb348c97df44 109 #define LL_PWR_REGU_VOLTAGE_SCALE2 0x00000000U
lypinator 0:bb348c97df44 110 #endif /* PWR_CR_VOS_0 */
lypinator 0:bb348c97df44 111 /**
lypinator 0:bb348c97df44 112 * @}
lypinator 0:bb348c97df44 113 */
lypinator 0:bb348c97df44 114
lypinator 0:bb348c97df44 115 /** @defgroup PWR_LL_EC_MODE_PWR Mode Power
lypinator 0:bb348c97df44 116 * @{
lypinator 0:bb348c97df44 117 */
lypinator 0:bb348c97df44 118 #define LL_PWR_MODE_STOP_MAINREGU 0x00000000U /*!< Enter Stop mode when the CPU enters deepsleep */
lypinator 0:bb348c97df44 119 #define LL_PWR_MODE_STOP_LPREGU (PWR_CR_LPDS) /*!< Enter Stop mode (with low power Regulator ON) when the CPU enters deepsleep */
lypinator 0:bb348c97df44 120 #if defined(PWR_CR_MRUDS) && defined(PWR_CR_LPUDS) && defined(PWR_CR_FPDS)
lypinator 0:bb348c97df44 121 #define LL_PWR_MODE_STOP_MAINREGU_UNDERDRIVE (PWR_CR_MRUDS | PWR_CR_FPDS) /*!< Enter Stop mode (with main Regulator in under-drive mode) when the CPU enters deepsleep */
lypinator 0:bb348c97df44 122 #define LL_PWR_MODE_STOP_LPREGU_UNDERDRIVE (PWR_CR_LPDS | PWR_CR_LPUDS | PWR_CR_FPDS) /*!< Enter Stop mode (with low power Regulator in under-drive mode) when the CPU enters deepsleep */
lypinator 0:bb348c97df44 123 #endif /* PWR_CR_MRUDS && PWR_CR_LPUDS && PWR_CR_FPDS */
lypinator 0:bb348c97df44 124 #if defined(PWR_CR_MRLVDS) && defined(PWR_CR_LPLVDS) && defined(PWR_CR_FPDS)
lypinator 0:bb348c97df44 125 #define LL_PWR_MODE_STOP_MAINREGU_DEEPSLEEP (PWR_CR_MRLVDS | PWR_CR_FPDS) /*!< Enter Stop mode (with main Regulator in Deep Sleep mode) when the CPU enters deepsleep */
lypinator 0:bb348c97df44 126 #define LL_PWR_MODE_STOP_LPREGU_DEEPSLEEP (PWR_CR_LPDS | PWR_CR_LPLVDS | PWR_CR_FPDS) /*!< Enter Stop mode (with low power Regulator in Deep Sleep mode) when the CPU enters deepsleep */
lypinator 0:bb348c97df44 127 #endif /* PWR_CR_MRLVDS && PWR_CR_LPLVDS && PWR_CR_FPDS */
lypinator 0:bb348c97df44 128 #define LL_PWR_MODE_STANDBY (PWR_CR_PDDS) /*!< Enter Standby mode when the CPU enters deepsleep */
lypinator 0:bb348c97df44 129 /**
lypinator 0:bb348c97df44 130 * @}
lypinator 0:bb348c97df44 131 */
lypinator 0:bb348c97df44 132
lypinator 0:bb348c97df44 133 /** @defgroup PWR_LL_EC_REGU_MODE_DS_MODE Regulator Mode In Deep Sleep Mode
lypinator 0:bb348c97df44 134 * @{
lypinator 0:bb348c97df44 135 */
lypinator 0:bb348c97df44 136 #define LL_PWR_REGU_DSMODE_MAIN 0x00000000U /*!< Voltage Regulator in main mode during deepsleep mode */
lypinator 0:bb348c97df44 137 #define LL_PWR_REGU_DSMODE_LOW_POWER (PWR_CR_LPDS) /*!< Voltage Regulator in low-power mode during deepsleep mode */
lypinator 0:bb348c97df44 138 /**
lypinator 0:bb348c97df44 139 * @}
lypinator 0:bb348c97df44 140 */
lypinator 0:bb348c97df44 141
lypinator 0:bb348c97df44 142 /** @defgroup PWR_LL_EC_PVDLEVEL Power Voltage Detector Level
lypinator 0:bb348c97df44 143 * @{
lypinator 0:bb348c97df44 144 */
lypinator 0:bb348c97df44 145 #define LL_PWR_PVDLEVEL_0 (PWR_CR_PLS_LEV0) /*!< Voltage threshold detected by PVD 2.2 V */
lypinator 0:bb348c97df44 146 #define LL_PWR_PVDLEVEL_1 (PWR_CR_PLS_LEV1) /*!< Voltage threshold detected by PVD 2.3 V */
lypinator 0:bb348c97df44 147 #define LL_PWR_PVDLEVEL_2 (PWR_CR_PLS_LEV2) /*!< Voltage threshold detected by PVD 2.4 V */
lypinator 0:bb348c97df44 148 #define LL_PWR_PVDLEVEL_3 (PWR_CR_PLS_LEV3) /*!< Voltage threshold detected by PVD 2.5 V */
lypinator 0:bb348c97df44 149 #define LL_PWR_PVDLEVEL_4 (PWR_CR_PLS_LEV4) /*!< Voltage threshold detected by PVD 2.6 V */
lypinator 0:bb348c97df44 150 #define LL_PWR_PVDLEVEL_5 (PWR_CR_PLS_LEV5) /*!< Voltage threshold detected by PVD 2.7 V */
lypinator 0:bb348c97df44 151 #define LL_PWR_PVDLEVEL_6 (PWR_CR_PLS_LEV6) /*!< Voltage threshold detected by PVD 2.8 V */
lypinator 0:bb348c97df44 152 #define LL_PWR_PVDLEVEL_7 (PWR_CR_PLS_LEV7) /*!< Voltage threshold detected by PVD 2.9 V */
lypinator 0:bb348c97df44 153 /**
lypinator 0:bb348c97df44 154 * @}
lypinator 0:bb348c97df44 155 */
lypinator 0:bb348c97df44 156 /** @defgroup PWR_LL_EC_WAKEUP_PIN Wakeup Pins
lypinator 0:bb348c97df44 157 * @{
lypinator 0:bb348c97df44 158 */
lypinator 0:bb348c97df44 159 #if defined(PWR_CSR_EWUP)
lypinator 0:bb348c97df44 160 #define LL_PWR_WAKEUP_PIN1 (PWR_CSR_EWUP) /*!< WKUP pin : PA0 */
lypinator 0:bb348c97df44 161 #endif /* PWR_CSR_EWUP */
lypinator 0:bb348c97df44 162 #if defined(PWR_CSR_EWUP1)
lypinator 0:bb348c97df44 163 #define LL_PWR_WAKEUP_PIN1 (PWR_CSR_EWUP1) /*!< WKUP pin 1 : PA0 */
lypinator 0:bb348c97df44 164 #endif /* PWR_CSR_EWUP1 */
lypinator 0:bb348c97df44 165 #if defined(PWR_CSR_EWUP2)
lypinator 0:bb348c97df44 166 #define LL_PWR_WAKEUP_PIN2 (PWR_CSR_EWUP2) /*!< WKUP pin 2 : PC0 or PC13 according to device */
lypinator 0:bb348c97df44 167 #endif /* PWR_CSR_EWUP2 */
lypinator 0:bb348c97df44 168 #if defined(PWR_CSR_EWUP3)
lypinator 0:bb348c97df44 169 #define LL_PWR_WAKEUP_PIN3 (PWR_CSR_EWUP3) /*!< WKUP pin 3 : PC1 */
lypinator 0:bb348c97df44 170 #endif /* PWR_CSR_EWUP3 */
lypinator 0:bb348c97df44 171 /**
lypinator 0:bb348c97df44 172 * @}
lypinator 0:bb348c97df44 173 */
lypinator 0:bb348c97df44 174
lypinator 0:bb348c97df44 175 /**
lypinator 0:bb348c97df44 176 * @}
lypinator 0:bb348c97df44 177 */
lypinator 0:bb348c97df44 178
lypinator 0:bb348c97df44 179
lypinator 0:bb348c97df44 180 /* Exported macro ------------------------------------------------------------*/
lypinator 0:bb348c97df44 181 /** @defgroup PWR_LL_Exported_Macros PWR Exported Macros
lypinator 0:bb348c97df44 182 * @{
lypinator 0:bb348c97df44 183 */
lypinator 0:bb348c97df44 184
lypinator 0:bb348c97df44 185 /** @defgroup PWR_LL_EM_WRITE_READ Common write and read registers Macros
lypinator 0:bb348c97df44 186 * @{
lypinator 0:bb348c97df44 187 */
lypinator 0:bb348c97df44 188
lypinator 0:bb348c97df44 189 /**
lypinator 0:bb348c97df44 190 * @brief Write a value in PWR register
lypinator 0:bb348c97df44 191 * @param __REG__ Register to be written
lypinator 0:bb348c97df44 192 * @param __VALUE__ Value to be written in the register
lypinator 0:bb348c97df44 193 * @retval None
lypinator 0:bb348c97df44 194 */
lypinator 0:bb348c97df44 195 #define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
lypinator 0:bb348c97df44 196
lypinator 0:bb348c97df44 197 /**
lypinator 0:bb348c97df44 198 * @brief Read a value in PWR register
lypinator 0:bb348c97df44 199 * @param __REG__ Register to be read
lypinator 0:bb348c97df44 200 * @retval Register value
lypinator 0:bb348c97df44 201 */
lypinator 0:bb348c97df44 202 #define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
lypinator 0:bb348c97df44 203 /**
lypinator 0:bb348c97df44 204 * @}
lypinator 0:bb348c97df44 205 */
lypinator 0:bb348c97df44 206
lypinator 0:bb348c97df44 207 /**
lypinator 0:bb348c97df44 208 * @}
lypinator 0:bb348c97df44 209 */
lypinator 0:bb348c97df44 210
lypinator 0:bb348c97df44 211 /* Exported functions --------------------------------------------------------*/
lypinator 0:bb348c97df44 212 /** @defgroup PWR_LL_Exported_Functions PWR Exported Functions
lypinator 0:bb348c97df44 213 * @{
lypinator 0:bb348c97df44 214 */
lypinator 0:bb348c97df44 215
lypinator 0:bb348c97df44 216 /** @defgroup PWR_LL_EF_Configuration Configuration
lypinator 0:bb348c97df44 217 * @{
lypinator 0:bb348c97df44 218 */
lypinator 0:bb348c97df44 219 #if defined(PWR_CR_FISSR)
lypinator 0:bb348c97df44 220 /**
lypinator 0:bb348c97df44 221 * @brief Enable FLASH interface STOP while system Run is ON
lypinator 0:bb348c97df44 222 * @rmtoll CR FISSR LL_PWR_EnableFLASHInterfaceSTOP
lypinator 0:bb348c97df44 223 * @note This mode is enabled only with STOP low power mode.
lypinator 0:bb348c97df44 224 * @retval None
lypinator 0:bb348c97df44 225 */
lypinator 0:bb348c97df44 226 __STATIC_INLINE void LL_PWR_EnableFLASHInterfaceSTOP(void)
lypinator 0:bb348c97df44 227 {
lypinator 0:bb348c97df44 228 SET_BIT(PWR->CR, PWR_CR_FISSR);
lypinator 0:bb348c97df44 229 }
lypinator 0:bb348c97df44 230
lypinator 0:bb348c97df44 231 /**
lypinator 0:bb348c97df44 232 * @brief Disable FLASH Interface STOP while system Run is ON
lypinator 0:bb348c97df44 233 * @rmtoll CR FISSR LL_PWR_DisableFLASHInterfaceSTOP
lypinator 0:bb348c97df44 234 * @retval None
lypinator 0:bb348c97df44 235 */
lypinator 0:bb348c97df44 236 __STATIC_INLINE void LL_PWR_DisableFLASHInterfaceSTOP(void)
lypinator 0:bb348c97df44 237 {
lypinator 0:bb348c97df44 238 CLEAR_BIT(PWR->CR, PWR_CR_FISSR);
lypinator 0:bb348c97df44 239 }
lypinator 0:bb348c97df44 240
lypinator 0:bb348c97df44 241 /**
lypinator 0:bb348c97df44 242 * @brief Check if FLASH Interface STOP while system Run feature is enabled
lypinator 0:bb348c97df44 243 * @rmtoll CR FISSR LL_PWR_IsEnabledFLASHInterfaceSTOP
lypinator 0:bb348c97df44 244 * @retval State of bit (1 or 0).
lypinator 0:bb348c97df44 245 */
lypinator 0:bb348c97df44 246 __STATIC_INLINE uint32_t LL_PWR_IsEnabledFLASHInterfaceSTOP(void)
lypinator 0:bb348c97df44 247 {
lypinator 0:bb348c97df44 248 return (READ_BIT(PWR->CR, PWR_CR_FISSR) == (PWR_CR_FISSR));
lypinator 0:bb348c97df44 249 }
lypinator 0:bb348c97df44 250 #endif /* PWR_CR_FISSR */
lypinator 0:bb348c97df44 251
lypinator 0:bb348c97df44 252 #if defined(PWR_CR_FMSSR)
lypinator 0:bb348c97df44 253 /**
lypinator 0:bb348c97df44 254 * @brief Enable FLASH Memory STOP while system Run is ON
lypinator 0:bb348c97df44 255 * @rmtoll CR FMSSR LL_PWR_EnableFLASHMemorySTOP
lypinator 0:bb348c97df44 256 * @note This mode is enabled only with STOP low power mode.
lypinator 0:bb348c97df44 257 * @retval None
lypinator 0:bb348c97df44 258 */
lypinator 0:bb348c97df44 259 __STATIC_INLINE void LL_PWR_EnableFLASHMemorySTOP(void)
lypinator 0:bb348c97df44 260 {
lypinator 0:bb348c97df44 261 SET_BIT(PWR->CR, PWR_CR_FMSSR);
lypinator 0:bb348c97df44 262 }
lypinator 0:bb348c97df44 263
lypinator 0:bb348c97df44 264 /**
lypinator 0:bb348c97df44 265 * @brief Disable FLASH Memory STOP while system Run is ON
lypinator 0:bb348c97df44 266 * @rmtoll CR FMSSR LL_PWR_DisableFLASHMemorySTOP
lypinator 0:bb348c97df44 267 * @retval None
lypinator 0:bb348c97df44 268 */
lypinator 0:bb348c97df44 269 __STATIC_INLINE void LL_PWR_DisableFLASHMemorySTOP(void)
lypinator 0:bb348c97df44 270 {
lypinator 0:bb348c97df44 271 CLEAR_BIT(PWR->CR, PWR_CR_FMSSR);
lypinator 0:bb348c97df44 272 }
lypinator 0:bb348c97df44 273
lypinator 0:bb348c97df44 274 /**
lypinator 0:bb348c97df44 275 * @brief Check if FLASH Memory STOP while system Run feature is enabled
lypinator 0:bb348c97df44 276 * @rmtoll CR FMSSR LL_PWR_IsEnabledFLASHMemorySTOP
lypinator 0:bb348c97df44 277 * @retval State of bit (1 or 0).
lypinator 0:bb348c97df44 278 */
lypinator 0:bb348c97df44 279 __STATIC_INLINE uint32_t LL_PWR_IsEnabledFLASHMemorySTOP(void)
lypinator 0:bb348c97df44 280 {
lypinator 0:bb348c97df44 281 return (READ_BIT(PWR->CR, PWR_CR_FMSSR) == (PWR_CR_FMSSR));
lypinator 0:bb348c97df44 282 }
lypinator 0:bb348c97df44 283 #endif /* PWR_CR_FMSSR */
lypinator 0:bb348c97df44 284 #if defined(PWR_CR_UDEN)
lypinator 0:bb348c97df44 285 /**
lypinator 0:bb348c97df44 286 * @brief Enable Under Drive Mode
lypinator 0:bb348c97df44 287 * @rmtoll CR UDEN LL_PWR_EnableUnderDriveMode
lypinator 0:bb348c97df44 288 * @note This mode is enabled only with STOP low power mode.
lypinator 0:bb348c97df44 289 * In this mode, the 1.2V domain is preserved in reduced leakage mode. This
lypinator 0:bb348c97df44 290 * mode is only available when the main Regulator or the low power Regulator
lypinator 0:bb348c97df44 291 * is in low voltage mode.
lypinator 0:bb348c97df44 292 * @note If the Under-drive mode was enabled, it is automatically disabled after
lypinator 0:bb348c97df44 293 * exiting Stop mode.
lypinator 0:bb348c97df44 294 * When the voltage Regulator operates in Under-drive mode, an additional
lypinator 0:bb348c97df44 295 * startup delay is induced when waking up from Stop mode.
lypinator 0:bb348c97df44 296 * @retval None
lypinator 0:bb348c97df44 297 */
lypinator 0:bb348c97df44 298 __STATIC_INLINE void LL_PWR_EnableUnderDriveMode(void)
lypinator 0:bb348c97df44 299 {
lypinator 0:bb348c97df44 300 SET_BIT(PWR->CR, PWR_CR_UDEN);
lypinator 0:bb348c97df44 301 }
lypinator 0:bb348c97df44 302
lypinator 0:bb348c97df44 303 /**
lypinator 0:bb348c97df44 304 * @brief Disable Under Drive Mode
lypinator 0:bb348c97df44 305 * @rmtoll CR UDEN LL_PWR_DisableUnderDriveMode
lypinator 0:bb348c97df44 306 * @retval None
lypinator 0:bb348c97df44 307 */
lypinator 0:bb348c97df44 308 __STATIC_INLINE void LL_PWR_DisableUnderDriveMode(void)
lypinator 0:bb348c97df44 309 {
lypinator 0:bb348c97df44 310 CLEAR_BIT(PWR->CR, PWR_CR_UDEN);
lypinator 0:bb348c97df44 311 }
lypinator 0:bb348c97df44 312
lypinator 0:bb348c97df44 313 /**
lypinator 0:bb348c97df44 314 * @brief Check if Under Drive Mode is enabled
lypinator 0:bb348c97df44 315 * @rmtoll CR UDEN LL_PWR_IsEnabledUnderDriveMode
lypinator 0:bb348c97df44 316 * @retval State of bit (1 or 0).
lypinator 0:bb348c97df44 317 */
lypinator 0:bb348c97df44 318 __STATIC_INLINE uint32_t LL_PWR_IsEnabledUnderDriveMode(void)
lypinator 0:bb348c97df44 319 {
lypinator 0:bb348c97df44 320 return (READ_BIT(PWR->CR, PWR_CR_UDEN) == (PWR_CR_UDEN));
lypinator 0:bb348c97df44 321 }
lypinator 0:bb348c97df44 322 #endif /* PWR_CR_UDEN */
lypinator 0:bb348c97df44 323
lypinator 0:bb348c97df44 324 #if defined(PWR_CR_ODSWEN)
lypinator 0:bb348c97df44 325 /**
lypinator 0:bb348c97df44 326 * @brief Enable Over drive switching
lypinator 0:bb348c97df44 327 * @rmtoll CR ODSWEN LL_PWR_EnableOverDriveSwitching
lypinator 0:bb348c97df44 328 * @retval None
lypinator 0:bb348c97df44 329 */
lypinator 0:bb348c97df44 330 __STATIC_INLINE void LL_PWR_EnableOverDriveSwitching(void)
lypinator 0:bb348c97df44 331 {
lypinator 0:bb348c97df44 332 SET_BIT(PWR->CR, PWR_CR_ODSWEN);
lypinator 0:bb348c97df44 333 }
lypinator 0:bb348c97df44 334
lypinator 0:bb348c97df44 335 /**
lypinator 0:bb348c97df44 336 * @brief Disable Over drive switching
lypinator 0:bb348c97df44 337 * @rmtoll CR ODSWEN LL_PWR_DisableOverDriveSwitching
lypinator 0:bb348c97df44 338 * @retval None
lypinator 0:bb348c97df44 339 */
lypinator 0:bb348c97df44 340 __STATIC_INLINE void LL_PWR_DisableOverDriveSwitching(void)
lypinator 0:bb348c97df44 341 {
lypinator 0:bb348c97df44 342 CLEAR_BIT(PWR->CR, PWR_CR_ODSWEN);
lypinator 0:bb348c97df44 343 }
lypinator 0:bb348c97df44 344
lypinator 0:bb348c97df44 345 /**
lypinator 0:bb348c97df44 346 * @brief Check if Over drive switching is enabled
lypinator 0:bb348c97df44 347 * @rmtoll CR ODSWEN LL_PWR_IsEnabledOverDriveSwitching
lypinator 0:bb348c97df44 348 * @retval State of bit (1 or 0).
lypinator 0:bb348c97df44 349 */
lypinator 0:bb348c97df44 350 __STATIC_INLINE uint32_t LL_PWR_IsEnabledOverDriveSwitching(void)
lypinator 0:bb348c97df44 351 {
lypinator 0:bb348c97df44 352 return (READ_BIT(PWR->CR, PWR_CR_ODSWEN) == (PWR_CR_ODSWEN));
lypinator 0:bb348c97df44 353 }
lypinator 0:bb348c97df44 354 #endif /* PWR_CR_ODSWEN */
lypinator 0:bb348c97df44 355 #if defined(PWR_CR_ODEN)
lypinator 0:bb348c97df44 356 /**
lypinator 0:bb348c97df44 357 * @brief Enable Over drive Mode
lypinator 0:bb348c97df44 358 * @rmtoll CR ODEN LL_PWR_EnableOverDriveMode
lypinator 0:bb348c97df44 359 * @retval None
lypinator 0:bb348c97df44 360 */
lypinator 0:bb348c97df44 361 __STATIC_INLINE void LL_PWR_EnableOverDriveMode(void)
lypinator 0:bb348c97df44 362 {
lypinator 0:bb348c97df44 363 SET_BIT(PWR->CR, PWR_CR_ODEN);
lypinator 0:bb348c97df44 364 }
lypinator 0:bb348c97df44 365
lypinator 0:bb348c97df44 366 /**
lypinator 0:bb348c97df44 367 * @brief Disable Over drive Mode
lypinator 0:bb348c97df44 368 * @rmtoll CR ODEN LL_PWR_DisableOverDriveMode
lypinator 0:bb348c97df44 369 * @retval None
lypinator 0:bb348c97df44 370 */
lypinator 0:bb348c97df44 371 __STATIC_INLINE void LL_PWR_DisableOverDriveMode(void)
lypinator 0:bb348c97df44 372 {
lypinator 0:bb348c97df44 373 CLEAR_BIT(PWR->CR, PWR_CR_ODEN);
lypinator 0:bb348c97df44 374 }
lypinator 0:bb348c97df44 375
lypinator 0:bb348c97df44 376 /**
lypinator 0:bb348c97df44 377 * @brief Check if Over drive switching is enabled
lypinator 0:bb348c97df44 378 * @rmtoll CR ODEN LL_PWR_IsEnabledOverDriveMode
lypinator 0:bb348c97df44 379 * @retval State of bit (1 or 0).
lypinator 0:bb348c97df44 380 */
lypinator 0:bb348c97df44 381 __STATIC_INLINE uint32_t LL_PWR_IsEnabledOverDriveMode(void)
lypinator 0:bb348c97df44 382 {
lypinator 0:bb348c97df44 383 return (READ_BIT(PWR->CR, PWR_CR_ODEN) == (PWR_CR_ODEN));
lypinator 0:bb348c97df44 384 }
lypinator 0:bb348c97df44 385 #endif /* PWR_CR_ODEN */
lypinator 0:bb348c97df44 386 #if defined(PWR_CR_MRUDS)
lypinator 0:bb348c97df44 387 /**
lypinator 0:bb348c97df44 388 * @brief Enable Main Regulator in deepsleep under-drive Mode
lypinator 0:bb348c97df44 389 * @rmtoll CR MRUDS LL_PWR_EnableMainRegulatorDeepSleepUDMode
lypinator 0:bb348c97df44 390 * @retval None
lypinator 0:bb348c97df44 391 */
lypinator 0:bb348c97df44 392 __STATIC_INLINE void LL_PWR_EnableMainRegulatorDeepSleepUDMode(void)
lypinator 0:bb348c97df44 393 {
lypinator 0:bb348c97df44 394 SET_BIT(PWR->CR, PWR_CR_MRUDS);
lypinator 0:bb348c97df44 395 }
lypinator 0:bb348c97df44 396
lypinator 0:bb348c97df44 397 /**
lypinator 0:bb348c97df44 398 * @brief Disable Main Regulator in deepsleep under-drive Mode
lypinator 0:bb348c97df44 399 * @rmtoll CR MRUDS LL_PWR_DisableMainRegulatorDeepSleepUDMode
lypinator 0:bb348c97df44 400 * @retval None
lypinator 0:bb348c97df44 401 */
lypinator 0:bb348c97df44 402 __STATIC_INLINE void LL_PWR_DisableMainRegulatorDeepSleepUDMode(void)
lypinator 0:bb348c97df44 403 {
lypinator 0:bb348c97df44 404 CLEAR_BIT(PWR->CR, PWR_CR_MRUDS);
lypinator 0:bb348c97df44 405 }
lypinator 0:bb348c97df44 406
lypinator 0:bb348c97df44 407 /**
lypinator 0:bb348c97df44 408 * @brief Check if Main Regulator in deepsleep under-drive Mode is enabled
lypinator 0:bb348c97df44 409 * @rmtoll CR MRUDS LL_PWR_IsEnabledMainRegulatorDeepSleepUDMode
lypinator 0:bb348c97df44 410 * @retval State of bit (1 or 0).
lypinator 0:bb348c97df44 411 */
lypinator 0:bb348c97df44 412 __STATIC_INLINE uint32_t LL_PWR_IsEnabledMainRegulatorDeepSleepUDMode(void)
lypinator 0:bb348c97df44 413 {
lypinator 0:bb348c97df44 414 return (READ_BIT(PWR->CR, PWR_CR_MRUDS) == (PWR_CR_MRUDS));
lypinator 0:bb348c97df44 415 }
lypinator 0:bb348c97df44 416 #endif /* PWR_CR_MRUDS */
lypinator 0:bb348c97df44 417
lypinator 0:bb348c97df44 418 #if defined(PWR_CR_LPUDS)
lypinator 0:bb348c97df44 419 /**
lypinator 0:bb348c97df44 420 * @brief Enable Low Power Regulator in deepsleep under-drive Mode
lypinator 0:bb348c97df44 421 * @rmtoll CR LPUDS LL_PWR_EnableLowPowerRegulatorDeepSleepUDMode
lypinator 0:bb348c97df44 422 * @retval None
lypinator 0:bb348c97df44 423 */
lypinator 0:bb348c97df44 424 __STATIC_INLINE void LL_PWR_EnableLowPowerRegulatorDeepSleepUDMode(void)
lypinator 0:bb348c97df44 425 {
lypinator 0:bb348c97df44 426 SET_BIT(PWR->CR, PWR_CR_LPUDS);
lypinator 0:bb348c97df44 427 }
lypinator 0:bb348c97df44 428
lypinator 0:bb348c97df44 429 /**
lypinator 0:bb348c97df44 430 * @brief Disable Low Power Regulator in deepsleep under-drive Mode
lypinator 0:bb348c97df44 431 * @rmtoll CR LPUDS LL_PWR_DisableLowPowerRegulatorDeepSleepUDMode
lypinator 0:bb348c97df44 432 * @retval None
lypinator 0:bb348c97df44 433 */
lypinator 0:bb348c97df44 434 __STATIC_INLINE void LL_PWR_DisableLowPowerRegulatorDeepSleepUDMode(void)
lypinator 0:bb348c97df44 435 {
lypinator 0:bb348c97df44 436 CLEAR_BIT(PWR->CR, PWR_CR_LPUDS);
lypinator 0:bb348c97df44 437 }
lypinator 0:bb348c97df44 438
lypinator 0:bb348c97df44 439 /**
lypinator 0:bb348c97df44 440 * @brief Check if Low Power Regulator in deepsleep under-drive Mode is enabled
lypinator 0:bb348c97df44 441 * @rmtoll CR LPUDS LL_PWR_IsEnabledLowPowerRegulatorDeepSleepUDMode
lypinator 0:bb348c97df44 442 * @retval State of bit (1 or 0).
lypinator 0:bb348c97df44 443 */
lypinator 0:bb348c97df44 444 __STATIC_INLINE uint32_t LL_PWR_IsEnabledLowPowerRegulatorDeepSleepUDMode(void)
lypinator 0:bb348c97df44 445 {
lypinator 0:bb348c97df44 446 return (READ_BIT(PWR->CR, PWR_CR_LPUDS) == (PWR_CR_LPUDS));
lypinator 0:bb348c97df44 447 }
lypinator 0:bb348c97df44 448 #endif /* PWR_CR_LPUDS */
lypinator 0:bb348c97df44 449
lypinator 0:bb348c97df44 450 #if defined(PWR_CR_MRLVDS)
lypinator 0:bb348c97df44 451 /**
lypinator 0:bb348c97df44 452 * @brief Enable Main Regulator low voltage Mode
lypinator 0:bb348c97df44 453 * @rmtoll CR MRLVDS LL_PWR_EnableMainRegulatorLowVoltageMode
lypinator 0:bb348c97df44 454 * @retval None
lypinator 0:bb348c97df44 455 */
lypinator 0:bb348c97df44 456 __STATIC_INLINE void LL_PWR_EnableMainRegulatorLowVoltageMode(void)
lypinator 0:bb348c97df44 457 {
lypinator 0:bb348c97df44 458 SET_BIT(PWR->CR, PWR_CR_MRLVDS);
lypinator 0:bb348c97df44 459 }
lypinator 0:bb348c97df44 460
lypinator 0:bb348c97df44 461 /**
lypinator 0:bb348c97df44 462 * @brief Disable Main Regulator low voltage Mode
lypinator 0:bb348c97df44 463 * @rmtoll CR MRLVDS LL_PWR_DisableMainRegulatorLowVoltageMode
lypinator 0:bb348c97df44 464 * @retval None
lypinator 0:bb348c97df44 465 */
lypinator 0:bb348c97df44 466 __STATIC_INLINE void LL_PWR_DisableMainRegulatorLowVoltageMode(void)
lypinator 0:bb348c97df44 467 {
lypinator 0:bb348c97df44 468 CLEAR_BIT(PWR->CR, PWR_CR_MRLVDS);
lypinator 0:bb348c97df44 469 }
lypinator 0:bb348c97df44 470
lypinator 0:bb348c97df44 471 /**
lypinator 0:bb348c97df44 472 * @brief Check if Main Regulator low voltage Mode is enabled
lypinator 0:bb348c97df44 473 * @rmtoll CR MRLVDS LL_PWR_IsEnabledMainRegulatorLowVoltageMode
lypinator 0:bb348c97df44 474 * @retval State of bit (1 or 0).
lypinator 0:bb348c97df44 475 */
lypinator 0:bb348c97df44 476 __STATIC_INLINE uint32_t LL_PWR_IsEnabledMainRegulatorLowVoltageMode(void)
lypinator 0:bb348c97df44 477 {
lypinator 0:bb348c97df44 478 return (READ_BIT(PWR->CR, PWR_CR_MRLVDS) == (PWR_CR_MRLVDS));
lypinator 0:bb348c97df44 479 }
lypinator 0:bb348c97df44 480 #endif /* PWR_CR_MRLVDS */
lypinator 0:bb348c97df44 481
lypinator 0:bb348c97df44 482 #if defined(PWR_CR_LPLVDS)
lypinator 0:bb348c97df44 483 /**
lypinator 0:bb348c97df44 484 * @brief Enable Low Power Regulator low voltage Mode
lypinator 0:bb348c97df44 485 * @rmtoll CR LPLVDS LL_PWR_EnableLowPowerRegulatorLowVoltageMode
lypinator 0:bb348c97df44 486 * @retval None
lypinator 0:bb348c97df44 487 */
lypinator 0:bb348c97df44 488 __STATIC_INLINE void LL_PWR_EnableLowPowerRegulatorLowVoltageMode(void)
lypinator 0:bb348c97df44 489 {
lypinator 0:bb348c97df44 490 SET_BIT(PWR->CR, PWR_CR_LPLVDS);
lypinator 0:bb348c97df44 491 }
lypinator 0:bb348c97df44 492
lypinator 0:bb348c97df44 493 /**
lypinator 0:bb348c97df44 494 * @brief Disable Low Power Regulator low voltage Mode
lypinator 0:bb348c97df44 495 * @rmtoll CR LPLVDS LL_PWR_DisableLowPowerRegulatorLowVoltageMode
lypinator 0:bb348c97df44 496 * @retval None
lypinator 0:bb348c97df44 497 */
lypinator 0:bb348c97df44 498 __STATIC_INLINE void LL_PWR_DisableLowPowerRegulatorLowVoltageMode(void)
lypinator 0:bb348c97df44 499 {
lypinator 0:bb348c97df44 500 CLEAR_BIT(PWR->CR, PWR_CR_LPLVDS);
lypinator 0:bb348c97df44 501 }
lypinator 0:bb348c97df44 502
lypinator 0:bb348c97df44 503 /**
lypinator 0:bb348c97df44 504 * @brief Check if Low Power Regulator low voltage Mode is enabled
lypinator 0:bb348c97df44 505 * @rmtoll CR LPLVDS LL_PWR_IsEnabledLowPowerRegulatorLowVoltageMode
lypinator 0:bb348c97df44 506 * @retval State of bit (1 or 0).
lypinator 0:bb348c97df44 507 */
lypinator 0:bb348c97df44 508 __STATIC_INLINE uint32_t LL_PWR_IsEnabledLowPowerRegulatorLowVoltageMode(void)
lypinator 0:bb348c97df44 509 {
lypinator 0:bb348c97df44 510 return (READ_BIT(PWR->CR, PWR_CR_LPLVDS) == (PWR_CR_LPLVDS));
lypinator 0:bb348c97df44 511 }
lypinator 0:bb348c97df44 512 #endif /* PWR_CR_LPLVDS */
lypinator 0:bb348c97df44 513 /**
lypinator 0:bb348c97df44 514 * @brief Set the main internal Regulator output voltage
lypinator 0:bb348c97df44 515 * @rmtoll CR VOS LL_PWR_SetRegulVoltageScaling
lypinator 0:bb348c97df44 516 * @param VoltageScaling This parameter can be one of the following values:
lypinator 0:bb348c97df44 517 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1 (*)
lypinator 0:bb348c97df44 518 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
lypinator 0:bb348c97df44 519 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3
lypinator 0:bb348c97df44 520 * (*) LL_PWR_REGU_VOLTAGE_SCALE1 is not available for STM32F401xx devices
lypinator 0:bb348c97df44 521 * @retval None
lypinator 0:bb348c97df44 522 */
lypinator 0:bb348c97df44 523 __STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling)
lypinator 0:bb348c97df44 524 {
lypinator 0:bb348c97df44 525 MODIFY_REG(PWR->CR, PWR_CR_VOS, VoltageScaling);
lypinator 0:bb348c97df44 526 }
lypinator 0:bb348c97df44 527
lypinator 0:bb348c97df44 528 /**
lypinator 0:bb348c97df44 529 * @brief Get the main internal Regulator output voltage
lypinator 0:bb348c97df44 530 * @rmtoll CR VOS LL_PWR_GetRegulVoltageScaling
lypinator 0:bb348c97df44 531 * @retval Returned value can be one of the following values:
lypinator 0:bb348c97df44 532 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1 (*)
lypinator 0:bb348c97df44 533 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
lypinator 0:bb348c97df44 534 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3
lypinator 0:bb348c97df44 535 * (*) LL_PWR_REGU_VOLTAGE_SCALE1 is not available for STM32F401xx devices
lypinator 0:bb348c97df44 536 */
lypinator 0:bb348c97df44 537 __STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void)
lypinator 0:bb348c97df44 538 {
lypinator 0:bb348c97df44 539 return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_VOS));
lypinator 0:bb348c97df44 540 }
lypinator 0:bb348c97df44 541 /**
lypinator 0:bb348c97df44 542 * @brief Enable the Flash Power Down in Stop Mode
lypinator 0:bb348c97df44 543 * @rmtoll CR FPDS LL_PWR_EnableFlashPowerDown
lypinator 0:bb348c97df44 544 * @retval None
lypinator 0:bb348c97df44 545 */
lypinator 0:bb348c97df44 546 __STATIC_INLINE void LL_PWR_EnableFlashPowerDown(void)
lypinator 0:bb348c97df44 547 {
lypinator 0:bb348c97df44 548 SET_BIT(PWR->CR, PWR_CR_FPDS);
lypinator 0:bb348c97df44 549 }
lypinator 0:bb348c97df44 550
lypinator 0:bb348c97df44 551 /**
lypinator 0:bb348c97df44 552 * @brief Disable the Flash Power Down in Stop Mode
lypinator 0:bb348c97df44 553 * @rmtoll CR FPDS LL_PWR_DisableFlashPowerDown
lypinator 0:bb348c97df44 554 * @retval None
lypinator 0:bb348c97df44 555 */
lypinator 0:bb348c97df44 556 __STATIC_INLINE void LL_PWR_DisableFlashPowerDown(void)
lypinator 0:bb348c97df44 557 {
lypinator 0:bb348c97df44 558 CLEAR_BIT(PWR->CR, PWR_CR_FPDS);
lypinator 0:bb348c97df44 559 }
lypinator 0:bb348c97df44 560
lypinator 0:bb348c97df44 561 /**
lypinator 0:bb348c97df44 562 * @brief Check if the Flash Power Down in Stop Mode is enabled
lypinator 0:bb348c97df44 563 * @rmtoll CR FPDS LL_PWR_IsEnabledFlashPowerDown
lypinator 0:bb348c97df44 564 * @retval State of bit (1 or 0).
lypinator 0:bb348c97df44 565 */
lypinator 0:bb348c97df44 566 __STATIC_INLINE uint32_t LL_PWR_IsEnabledFlashPowerDown(void)
lypinator 0:bb348c97df44 567 {
lypinator 0:bb348c97df44 568 return (READ_BIT(PWR->CR, PWR_CR_FPDS) == (PWR_CR_FPDS));
lypinator 0:bb348c97df44 569 }
lypinator 0:bb348c97df44 570
lypinator 0:bb348c97df44 571 /**
lypinator 0:bb348c97df44 572 * @brief Enable access to the backup domain
lypinator 0:bb348c97df44 573 * @rmtoll CR DBP LL_PWR_EnableBkUpAccess
lypinator 0:bb348c97df44 574 * @retval None
lypinator 0:bb348c97df44 575 */
lypinator 0:bb348c97df44 576 __STATIC_INLINE void LL_PWR_EnableBkUpAccess(void)
lypinator 0:bb348c97df44 577 {
lypinator 0:bb348c97df44 578 SET_BIT(PWR->CR, PWR_CR_DBP);
lypinator 0:bb348c97df44 579 }
lypinator 0:bb348c97df44 580
lypinator 0:bb348c97df44 581 /**
lypinator 0:bb348c97df44 582 * @brief Disable access to the backup domain
lypinator 0:bb348c97df44 583 * @rmtoll CR DBP LL_PWR_DisableBkUpAccess
lypinator 0:bb348c97df44 584 * @retval None
lypinator 0:bb348c97df44 585 */
lypinator 0:bb348c97df44 586 __STATIC_INLINE void LL_PWR_DisableBkUpAccess(void)
lypinator 0:bb348c97df44 587 {
lypinator 0:bb348c97df44 588 CLEAR_BIT(PWR->CR, PWR_CR_DBP);
lypinator 0:bb348c97df44 589 }
lypinator 0:bb348c97df44 590
lypinator 0:bb348c97df44 591 /**
lypinator 0:bb348c97df44 592 * @brief Check if the backup domain is enabled
lypinator 0:bb348c97df44 593 * @rmtoll CR DBP LL_PWR_IsEnabledBkUpAccess
lypinator 0:bb348c97df44 594 * @retval State of bit (1 or 0).
lypinator 0:bb348c97df44 595 */
lypinator 0:bb348c97df44 596 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void)
lypinator 0:bb348c97df44 597 {
lypinator 0:bb348c97df44 598 return (READ_BIT(PWR->CR, PWR_CR_DBP) == (PWR_CR_DBP));
lypinator 0:bb348c97df44 599 }
lypinator 0:bb348c97df44 600 /**
lypinator 0:bb348c97df44 601 * @brief Enable the backup Regulator
lypinator 0:bb348c97df44 602 * @rmtoll CSR BRE LL_PWR_EnableBkUpRegulator
lypinator 0:bb348c97df44 603 * @note The BRE bit of the PWR_CSR register is protected against parasitic write access.
lypinator 0:bb348c97df44 604 * The LL_PWR_EnableBkUpAccess() must be called before using this API.
lypinator 0:bb348c97df44 605 * @retval None
lypinator 0:bb348c97df44 606 */
lypinator 0:bb348c97df44 607 __STATIC_INLINE void LL_PWR_EnableBkUpRegulator(void)
lypinator 0:bb348c97df44 608 {
lypinator 0:bb348c97df44 609 SET_BIT(PWR->CSR, PWR_CSR_BRE);
lypinator 0:bb348c97df44 610 }
lypinator 0:bb348c97df44 611
lypinator 0:bb348c97df44 612 /**
lypinator 0:bb348c97df44 613 * @brief Disable the backup Regulator
lypinator 0:bb348c97df44 614 * @rmtoll CSR BRE LL_PWR_DisableBkUpRegulator
lypinator 0:bb348c97df44 615 * @note The BRE bit of the PWR_CSR register is protected against parasitic write access.
lypinator 0:bb348c97df44 616 * The LL_PWR_EnableBkUpAccess() must be called before using this API.
lypinator 0:bb348c97df44 617 * @retval None
lypinator 0:bb348c97df44 618 */
lypinator 0:bb348c97df44 619 __STATIC_INLINE void LL_PWR_DisableBkUpRegulator(void)
lypinator 0:bb348c97df44 620 {
lypinator 0:bb348c97df44 621 CLEAR_BIT(PWR->CSR, PWR_CSR_BRE);
lypinator 0:bb348c97df44 622 }
lypinator 0:bb348c97df44 623
lypinator 0:bb348c97df44 624 /**
lypinator 0:bb348c97df44 625 * @brief Check if the backup Regulator is enabled
lypinator 0:bb348c97df44 626 * @rmtoll CSR BRE LL_PWR_IsEnabledBkUpRegulator
lypinator 0:bb348c97df44 627 * @retval State of bit (1 or 0).
lypinator 0:bb348c97df44 628 */
lypinator 0:bb348c97df44 629 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpRegulator(void)
lypinator 0:bb348c97df44 630 {
lypinator 0:bb348c97df44 631 return (READ_BIT(PWR->CSR, PWR_CSR_BRE) == (PWR_CSR_BRE));
lypinator 0:bb348c97df44 632 }
lypinator 0:bb348c97df44 633
lypinator 0:bb348c97df44 634 /**
lypinator 0:bb348c97df44 635 * @brief Set voltage Regulator mode during deep sleep mode
lypinator 0:bb348c97df44 636 * @rmtoll CR LPDS LL_PWR_SetRegulModeDS
lypinator 0:bb348c97df44 637 * @param RegulMode This parameter can be one of the following values:
lypinator 0:bb348c97df44 638 * @arg @ref LL_PWR_REGU_DSMODE_MAIN
lypinator 0:bb348c97df44 639 * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
lypinator 0:bb348c97df44 640 * @retval None
lypinator 0:bb348c97df44 641 */
lypinator 0:bb348c97df44 642 __STATIC_INLINE void LL_PWR_SetRegulModeDS(uint32_t RegulMode)
lypinator 0:bb348c97df44 643 {
lypinator 0:bb348c97df44 644 MODIFY_REG(PWR->CR, PWR_CR_LPDS, RegulMode);
lypinator 0:bb348c97df44 645 }
lypinator 0:bb348c97df44 646
lypinator 0:bb348c97df44 647 /**
lypinator 0:bb348c97df44 648 * @brief Get voltage Regulator mode during deep sleep mode
lypinator 0:bb348c97df44 649 * @rmtoll CR LPDS LL_PWR_GetRegulModeDS
lypinator 0:bb348c97df44 650 * @retval Returned value can be one of the following values:
lypinator 0:bb348c97df44 651 * @arg @ref LL_PWR_REGU_DSMODE_MAIN
lypinator 0:bb348c97df44 652 * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
lypinator 0:bb348c97df44 653 */
lypinator 0:bb348c97df44 654 __STATIC_INLINE uint32_t LL_PWR_GetRegulModeDS(void)
lypinator 0:bb348c97df44 655 {
lypinator 0:bb348c97df44 656 return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_LPDS));
lypinator 0:bb348c97df44 657 }
lypinator 0:bb348c97df44 658
lypinator 0:bb348c97df44 659 /**
lypinator 0:bb348c97df44 660 * @brief Set Power Down mode when CPU enters deepsleep
lypinator 0:bb348c97df44 661 * @rmtoll CR PDDS LL_PWR_SetPowerMode\n
lypinator 0:bb348c97df44 662 * @rmtoll CR MRUDS LL_PWR_SetPowerMode\n
lypinator 0:bb348c97df44 663 * @rmtoll CR LPUDS LL_PWR_SetPowerMode\n
lypinator 0:bb348c97df44 664 * @rmtoll CR FPDS LL_PWR_SetPowerMode\n
lypinator 0:bb348c97df44 665 * @rmtoll CR MRLVDS LL_PWR_SetPowerMode\n
lypinator 0:bb348c97df44 666 * @rmtoll CR LPlVDS LL_PWR_SetPowerMode\n
lypinator 0:bb348c97df44 667 * @rmtoll CR FPDS LL_PWR_SetPowerMode\n
lypinator 0:bb348c97df44 668 * @rmtoll CR LPDS LL_PWR_SetPowerMode
lypinator 0:bb348c97df44 669 * @param PDMode This parameter can be one of the following values:
lypinator 0:bb348c97df44 670 * @arg @ref LL_PWR_MODE_STOP_MAINREGU
lypinator 0:bb348c97df44 671 * @arg @ref LL_PWR_MODE_STOP_LPREGU
lypinator 0:bb348c97df44 672 * @arg @ref LL_PWR_MODE_STOP_MAINREGU_UNDERDRIVE (*)
lypinator 0:bb348c97df44 673 * @arg @ref LL_PWR_MODE_STOP_LPREGU_UNDERDRIVE (*)
lypinator 0:bb348c97df44 674 * @arg @ref LL_PWR_MODE_STOP_MAINREGU_DEEPSLEEP (*)
lypinator 0:bb348c97df44 675 * @arg @ref LL_PWR_MODE_STOP_LPREGU_DEEPSLEEP (*)
lypinator 0:bb348c97df44 676 *
lypinator 0:bb348c97df44 677 * (*) not available on all devices
lypinator 0:bb348c97df44 678 * @arg @ref LL_PWR_MODE_STANDBY
lypinator 0:bb348c97df44 679 * @retval None
lypinator 0:bb348c97df44 680 */
lypinator 0:bb348c97df44 681 __STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t PDMode)
lypinator 0:bb348c97df44 682 {
lypinator 0:bb348c97df44 683 #if defined(PWR_CR_MRUDS) && defined(PWR_CR_LPUDS) && defined(PWR_CR_FPDS)
lypinator 0:bb348c97df44 684 MODIFY_REG(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_FPDS | PWR_CR_LPUDS | PWR_CR_MRUDS), PDMode);
lypinator 0:bb348c97df44 685 #elif defined(PWR_CR_MRLVDS) && defined(PWR_CR_LPLVDS) && defined(PWR_CR_FPDS)
lypinator 0:bb348c97df44 686 MODIFY_REG(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_FPDS | PWR_CR_LPLVDS | PWR_CR_MRLVDS), PDMode);
lypinator 0:bb348c97df44 687 #else
lypinator 0:bb348c97df44 688 MODIFY_REG(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS), PDMode);
lypinator 0:bb348c97df44 689 #endif /* PWR_CR_MRUDS && PWR_CR_LPUDS && PWR_CR_FPDS */
lypinator 0:bb348c97df44 690 }
lypinator 0:bb348c97df44 691
lypinator 0:bb348c97df44 692 /**
lypinator 0:bb348c97df44 693 * @brief Get Power Down mode when CPU enters deepsleep
lypinator 0:bb348c97df44 694 * @rmtoll CR PDDS LL_PWR_GetPowerMode\n
lypinator 0:bb348c97df44 695 * @rmtoll CR MRUDS LL_PWR_GetPowerMode\n
lypinator 0:bb348c97df44 696 * @rmtoll CR LPUDS LL_PWR_GetPowerMode\n
lypinator 0:bb348c97df44 697 * @rmtoll CR FPDS LL_PWR_GetPowerMode\n
lypinator 0:bb348c97df44 698 * @rmtoll CR MRLVDS LL_PWR_GetPowerMode\n
lypinator 0:bb348c97df44 699 * @rmtoll CR LPLVDS LL_PWR_GetPowerMode\n
lypinator 0:bb348c97df44 700 * @rmtoll CR FPDS LL_PWR_GetPowerMode\n
lypinator 0:bb348c97df44 701 * @rmtoll CR LPDS LL_PWR_GetPowerMode
lypinator 0:bb348c97df44 702 * @retval Returned value can be one of the following values:
lypinator 0:bb348c97df44 703 * @arg @ref LL_PWR_MODE_STOP_MAINREGU
lypinator 0:bb348c97df44 704 * @arg @ref LL_PWR_MODE_STOP_LPREGU
lypinator 0:bb348c97df44 705 * @arg @ref LL_PWR_MODE_STOP_MAINREGU_UNDERDRIVE (*)
lypinator 0:bb348c97df44 706 * @arg @ref LL_PWR_MODE_STOP_LPREGU_UNDERDRIVE (*)
lypinator 0:bb348c97df44 707 * @arg @ref LL_PWR_MODE_STOP_MAINREGU_DEEPSLEEP (*)
lypinator 0:bb348c97df44 708 * @arg @ref LL_PWR_MODE_STOP_LPREGU_DEEPSLEEP (*)
lypinator 0:bb348c97df44 709 *
lypinator 0:bb348c97df44 710 * (*) not available on all devices
lypinator 0:bb348c97df44 711 * @arg @ref LL_PWR_MODE_STANDBY
lypinator 0:bb348c97df44 712 */
lypinator 0:bb348c97df44 713 __STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void)
lypinator 0:bb348c97df44 714 {
lypinator 0:bb348c97df44 715 #if defined(PWR_CR_MRUDS) && defined(PWR_CR_LPUDS) && defined(PWR_CR_FPDS)
lypinator 0:bb348c97df44 716 return (uint32_t)(READ_BIT(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_FPDS | PWR_CR_LPUDS | PWR_CR_MRUDS)));
lypinator 0:bb348c97df44 717 #elif defined(PWR_CR_MRLVDS) && defined(PWR_CR_LPLVDS) && defined(PWR_CR_FPDS)
lypinator 0:bb348c97df44 718 return (uint32_t)(READ_BIT(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_FPDS | PWR_CR_LPLVDS | PWR_CR_MRLVDS)));
lypinator 0:bb348c97df44 719 #else
lypinator 0:bb348c97df44 720 return (uint32_t)(READ_BIT(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS)));
lypinator 0:bb348c97df44 721 #endif /* PWR_CR_MRUDS && PWR_CR_LPUDS && PWR_CR_FPDS */
lypinator 0:bb348c97df44 722 }
lypinator 0:bb348c97df44 723
lypinator 0:bb348c97df44 724 /**
lypinator 0:bb348c97df44 725 * @brief Configure the voltage threshold detected by the Power Voltage Detector
lypinator 0:bb348c97df44 726 * @rmtoll CR PLS LL_PWR_SetPVDLevel
lypinator 0:bb348c97df44 727 * @param PVDLevel This parameter can be one of the following values:
lypinator 0:bb348c97df44 728 * @arg @ref LL_PWR_PVDLEVEL_0
lypinator 0:bb348c97df44 729 * @arg @ref LL_PWR_PVDLEVEL_1
lypinator 0:bb348c97df44 730 * @arg @ref LL_PWR_PVDLEVEL_2
lypinator 0:bb348c97df44 731 * @arg @ref LL_PWR_PVDLEVEL_3
lypinator 0:bb348c97df44 732 * @arg @ref LL_PWR_PVDLEVEL_4
lypinator 0:bb348c97df44 733 * @arg @ref LL_PWR_PVDLEVEL_5
lypinator 0:bb348c97df44 734 * @arg @ref LL_PWR_PVDLEVEL_6
lypinator 0:bb348c97df44 735 * @arg @ref LL_PWR_PVDLEVEL_7
lypinator 0:bb348c97df44 736 * @retval None
lypinator 0:bb348c97df44 737 */
lypinator 0:bb348c97df44 738 __STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel)
lypinator 0:bb348c97df44 739 {
lypinator 0:bb348c97df44 740 MODIFY_REG(PWR->CR, PWR_CR_PLS, PVDLevel);
lypinator 0:bb348c97df44 741 }
lypinator 0:bb348c97df44 742
lypinator 0:bb348c97df44 743 /**
lypinator 0:bb348c97df44 744 * @brief Get the voltage threshold detection
lypinator 0:bb348c97df44 745 * @rmtoll CR PLS LL_PWR_GetPVDLevel
lypinator 0:bb348c97df44 746 * @retval Returned value can be one of the following values:
lypinator 0:bb348c97df44 747 * @arg @ref LL_PWR_PVDLEVEL_0
lypinator 0:bb348c97df44 748 * @arg @ref LL_PWR_PVDLEVEL_1
lypinator 0:bb348c97df44 749 * @arg @ref LL_PWR_PVDLEVEL_2
lypinator 0:bb348c97df44 750 * @arg @ref LL_PWR_PVDLEVEL_3
lypinator 0:bb348c97df44 751 * @arg @ref LL_PWR_PVDLEVEL_4
lypinator 0:bb348c97df44 752 * @arg @ref LL_PWR_PVDLEVEL_5
lypinator 0:bb348c97df44 753 * @arg @ref LL_PWR_PVDLEVEL_6
lypinator 0:bb348c97df44 754 * @arg @ref LL_PWR_PVDLEVEL_7
lypinator 0:bb348c97df44 755 */
lypinator 0:bb348c97df44 756 __STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void)
lypinator 0:bb348c97df44 757 {
lypinator 0:bb348c97df44 758 return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_PLS));
lypinator 0:bb348c97df44 759 }
lypinator 0:bb348c97df44 760
lypinator 0:bb348c97df44 761 /**
lypinator 0:bb348c97df44 762 * @brief Enable Power Voltage Detector
lypinator 0:bb348c97df44 763 * @rmtoll CR PVDE LL_PWR_EnablePVD
lypinator 0:bb348c97df44 764 * @retval None
lypinator 0:bb348c97df44 765 */
lypinator 0:bb348c97df44 766 __STATIC_INLINE void LL_PWR_EnablePVD(void)
lypinator 0:bb348c97df44 767 {
lypinator 0:bb348c97df44 768 SET_BIT(PWR->CR, PWR_CR_PVDE);
lypinator 0:bb348c97df44 769 }
lypinator 0:bb348c97df44 770
lypinator 0:bb348c97df44 771 /**
lypinator 0:bb348c97df44 772 * @brief Disable Power Voltage Detector
lypinator 0:bb348c97df44 773 * @rmtoll CR PVDE LL_PWR_DisablePVD
lypinator 0:bb348c97df44 774 * @retval None
lypinator 0:bb348c97df44 775 */
lypinator 0:bb348c97df44 776 __STATIC_INLINE void LL_PWR_DisablePVD(void)
lypinator 0:bb348c97df44 777 {
lypinator 0:bb348c97df44 778 CLEAR_BIT(PWR->CR, PWR_CR_PVDE);
lypinator 0:bb348c97df44 779 }
lypinator 0:bb348c97df44 780
lypinator 0:bb348c97df44 781 /**
lypinator 0:bb348c97df44 782 * @brief Check if Power Voltage Detector is enabled
lypinator 0:bb348c97df44 783 * @rmtoll CR PVDE LL_PWR_IsEnabledPVD
lypinator 0:bb348c97df44 784 * @retval State of bit (1 or 0).
lypinator 0:bb348c97df44 785 */
lypinator 0:bb348c97df44 786 __STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void)
lypinator 0:bb348c97df44 787 {
lypinator 0:bb348c97df44 788 return (READ_BIT(PWR->CR, PWR_CR_PVDE) == (PWR_CR_PVDE));
lypinator 0:bb348c97df44 789 }
lypinator 0:bb348c97df44 790
lypinator 0:bb348c97df44 791 /**
lypinator 0:bb348c97df44 792 * @brief Enable the WakeUp PINx functionality
lypinator 0:bb348c97df44 793 * @rmtoll CSR EWUP LL_PWR_EnableWakeUpPin\n
lypinator 0:bb348c97df44 794 * @rmtoll CSR EWUP1 LL_PWR_EnableWakeUpPin\n
lypinator 0:bb348c97df44 795 * @rmtoll CSR EWUP2 LL_PWR_EnableWakeUpPin\n
lypinator 0:bb348c97df44 796 * @rmtoll CSR EWUP3 LL_PWR_EnableWakeUpPin
lypinator 0:bb348c97df44 797 * @param WakeUpPin This parameter can be one of the following values:
lypinator 0:bb348c97df44 798 * @arg @ref LL_PWR_WAKEUP_PIN1
lypinator 0:bb348c97df44 799 * @arg @ref LL_PWR_WAKEUP_PIN2 (*)
lypinator 0:bb348c97df44 800 * @arg @ref LL_PWR_WAKEUP_PIN3 (*)
lypinator 0:bb348c97df44 801 *
lypinator 0:bb348c97df44 802 * (*) not available on all devices
lypinator 0:bb348c97df44 803 * @retval None
lypinator 0:bb348c97df44 804 */
lypinator 0:bb348c97df44 805 __STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
lypinator 0:bb348c97df44 806 {
lypinator 0:bb348c97df44 807 SET_BIT(PWR->CSR, WakeUpPin);
lypinator 0:bb348c97df44 808 }
lypinator 0:bb348c97df44 809
lypinator 0:bb348c97df44 810 /**
lypinator 0:bb348c97df44 811 * @brief Disable the WakeUp PINx functionality
lypinator 0:bb348c97df44 812 * @rmtoll CSR EWUP LL_PWR_DisableWakeUpPin\n
lypinator 0:bb348c97df44 813 * @rmtoll CSR EWUP1 LL_PWR_DisableWakeUpPin\n
lypinator 0:bb348c97df44 814 * @rmtoll CSR EWUP2 LL_PWR_DisableWakeUpPin\n
lypinator 0:bb348c97df44 815 * @rmtoll CSR EWUP3 LL_PWR_DisableWakeUpPin
lypinator 0:bb348c97df44 816 * @param WakeUpPin This parameter can be one of the following values:
lypinator 0:bb348c97df44 817 * @arg @ref LL_PWR_WAKEUP_PIN1
lypinator 0:bb348c97df44 818 * @arg @ref LL_PWR_WAKEUP_PIN2 (*)
lypinator 0:bb348c97df44 819 * @arg @ref LL_PWR_WAKEUP_PIN3 (*)
lypinator 0:bb348c97df44 820 *
lypinator 0:bb348c97df44 821 * (*) not available on all devices
lypinator 0:bb348c97df44 822 * @retval None
lypinator 0:bb348c97df44 823 */
lypinator 0:bb348c97df44 824 __STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
lypinator 0:bb348c97df44 825 {
lypinator 0:bb348c97df44 826 CLEAR_BIT(PWR->CSR, WakeUpPin);
lypinator 0:bb348c97df44 827 }
lypinator 0:bb348c97df44 828
lypinator 0:bb348c97df44 829 /**
lypinator 0:bb348c97df44 830 * @brief Check if the WakeUp PINx functionality is enabled
lypinator 0:bb348c97df44 831 * @rmtoll CSR EWUP LL_PWR_IsEnabledWakeUpPin\n
lypinator 0:bb348c97df44 832 * @rmtoll CSR EWUP1 LL_PWR_IsEnabledWakeUpPin\n
lypinator 0:bb348c97df44 833 * @rmtoll CSR EWUP2 LL_PWR_IsEnabledWakeUpPin\n
lypinator 0:bb348c97df44 834 * @rmtoll CSR EWUP3 LL_PWR_IsEnabledWakeUpPin
lypinator 0:bb348c97df44 835 * @param WakeUpPin This parameter can be one of the following values:
lypinator 0:bb348c97df44 836 * @arg @ref LL_PWR_WAKEUP_PIN1
lypinator 0:bb348c97df44 837 * @arg @ref LL_PWR_WAKEUP_PIN2 (*)
lypinator 0:bb348c97df44 838 * @arg @ref LL_PWR_WAKEUP_PIN3 (*)
lypinator 0:bb348c97df44 839 *
lypinator 0:bb348c97df44 840 * (*) not available on all devices
lypinator 0:bb348c97df44 841 * @retval State of bit (1 or 0).
lypinator 0:bb348c97df44 842 */
lypinator 0:bb348c97df44 843 __STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)
lypinator 0:bb348c97df44 844 {
lypinator 0:bb348c97df44 845 return (READ_BIT(PWR->CSR, WakeUpPin) == (WakeUpPin));
lypinator 0:bb348c97df44 846 }
lypinator 0:bb348c97df44 847
lypinator 0:bb348c97df44 848
lypinator 0:bb348c97df44 849 /**
lypinator 0:bb348c97df44 850 * @}
lypinator 0:bb348c97df44 851 */
lypinator 0:bb348c97df44 852
lypinator 0:bb348c97df44 853 /** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management
lypinator 0:bb348c97df44 854 * @{
lypinator 0:bb348c97df44 855 */
lypinator 0:bb348c97df44 856
lypinator 0:bb348c97df44 857 /**
lypinator 0:bb348c97df44 858 * @brief Get Wake-up Flag
lypinator 0:bb348c97df44 859 * @rmtoll CSR WUF LL_PWR_IsActiveFlag_WU
lypinator 0:bb348c97df44 860 * @retval State of bit (1 or 0).
lypinator 0:bb348c97df44 861 */
lypinator 0:bb348c97df44 862 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU(void)
lypinator 0:bb348c97df44 863 {
lypinator 0:bb348c97df44 864 return (READ_BIT(PWR->CSR, PWR_CSR_WUF) == (PWR_CSR_WUF));
lypinator 0:bb348c97df44 865 }
lypinator 0:bb348c97df44 866
lypinator 0:bb348c97df44 867 /**
lypinator 0:bb348c97df44 868 * @brief Get Standby Flag
lypinator 0:bb348c97df44 869 * @rmtoll CSR SBF LL_PWR_IsActiveFlag_SB
lypinator 0:bb348c97df44 870 * @retval State of bit (1 or 0).
lypinator 0:bb348c97df44 871 */
lypinator 0:bb348c97df44 872 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void)
lypinator 0:bb348c97df44 873 {
lypinator 0:bb348c97df44 874 return (READ_BIT(PWR->CSR, PWR_CSR_SBF) == (PWR_CSR_SBF));
lypinator 0:bb348c97df44 875 }
lypinator 0:bb348c97df44 876
lypinator 0:bb348c97df44 877 /**
lypinator 0:bb348c97df44 878 * @brief Get Backup Regulator ready Flag
lypinator 0:bb348c97df44 879 * @rmtoll CSR BRR LL_PWR_IsActiveFlag_BRR
lypinator 0:bb348c97df44 880 * @retval State of bit (1 or 0).
lypinator 0:bb348c97df44 881 */
lypinator 0:bb348c97df44 882 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_BRR(void)
lypinator 0:bb348c97df44 883 {
lypinator 0:bb348c97df44 884 return (READ_BIT(PWR->CSR, PWR_CSR_BRR) == (PWR_CSR_BRR));
lypinator 0:bb348c97df44 885 }
lypinator 0:bb348c97df44 886 /**
lypinator 0:bb348c97df44 887 * @brief Indicate whether VDD voltage is below the selected PVD threshold
lypinator 0:bb348c97df44 888 * @rmtoll CSR PVDO LL_PWR_IsActiveFlag_PVDO
lypinator 0:bb348c97df44 889 * @retval State of bit (1 or 0).
lypinator 0:bb348c97df44 890 */
lypinator 0:bb348c97df44 891 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void)
lypinator 0:bb348c97df44 892 {
lypinator 0:bb348c97df44 893 return (READ_BIT(PWR->CSR, PWR_CSR_PVDO) == (PWR_CSR_PVDO));
lypinator 0:bb348c97df44 894 }
lypinator 0:bb348c97df44 895
lypinator 0:bb348c97df44 896 /**
lypinator 0:bb348c97df44 897 * @brief Indicate whether the Regulator is ready in the selected voltage range or if its output voltage is still changing to the required voltage level
lypinator 0:bb348c97df44 898 * @rmtoll CSR VOS LL_PWR_IsActiveFlag_VOS
lypinator 0:bb348c97df44 899 * @retval State of bit (1 or 0).
lypinator 0:bb348c97df44 900 */
lypinator 0:bb348c97df44 901 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOS(void)
lypinator 0:bb348c97df44 902 {
lypinator 0:bb348c97df44 903 return (READ_BIT(PWR->CSR, LL_PWR_CSR_VOS) == (LL_PWR_CSR_VOS));
lypinator 0:bb348c97df44 904 }
lypinator 0:bb348c97df44 905 #if defined(PWR_CR_ODEN)
lypinator 0:bb348c97df44 906 /**
lypinator 0:bb348c97df44 907 * @brief Indicate whether the Over-Drive mode is ready or not
lypinator 0:bb348c97df44 908 * @rmtoll CSR ODRDY LL_PWR_IsActiveFlag_OD
lypinator 0:bb348c97df44 909 * @retval State of bit (1 or 0).
lypinator 0:bb348c97df44 910 */
lypinator 0:bb348c97df44 911 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_OD(void)
lypinator 0:bb348c97df44 912 {
lypinator 0:bb348c97df44 913 return (READ_BIT(PWR->CSR, PWR_CSR_ODRDY) == (PWR_CSR_ODRDY));
lypinator 0:bb348c97df44 914 }
lypinator 0:bb348c97df44 915 #endif /* PWR_CR_ODEN */
lypinator 0:bb348c97df44 916
lypinator 0:bb348c97df44 917 #if defined(PWR_CR_ODSWEN)
lypinator 0:bb348c97df44 918 /**
lypinator 0:bb348c97df44 919 * @brief Indicate whether the Over-Drive mode switching is ready or not
lypinator 0:bb348c97df44 920 * @rmtoll CSR ODSWRDY LL_PWR_IsActiveFlag_ODSW
lypinator 0:bb348c97df44 921 * @retval State of bit (1 or 0).
lypinator 0:bb348c97df44 922 */
lypinator 0:bb348c97df44 923 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_ODSW(void)
lypinator 0:bb348c97df44 924 {
lypinator 0:bb348c97df44 925 return (READ_BIT(PWR->CSR, PWR_CSR_ODSWRDY) == (PWR_CSR_ODSWRDY));
lypinator 0:bb348c97df44 926 }
lypinator 0:bb348c97df44 927 #endif /* PWR_CR_ODSWEN */
lypinator 0:bb348c97df44 928
lypinator 0:bb348c97df44 929 #if defined(PWR_CR_UDEN)
lypinator 0:bb348c97df44 930 /**
lypinator 0:bb348c97df44 931 * @brief Indicate whether the Under-Drive mode is ready or not
lypinator 0:bb348c97df44 932 * @rmtoll CSR UDRDY LL_PWR_IsActiveFlag_UD
lypinator 0:bb348c97df44 933 * @retval State of bit (1 or 0).
lypinator 0:bb348c97df44 934 */
lypinator 0:bb348c97df44 935 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_UD(void)
lypinator 0:bb348c97df44 936 {
lypinator 0:bb348c97df44 937 return (READ_BIT(PWR->CSR, PWR_CSR_UDRDY) == (PWR_CSR_UDRDY));
lypinator 0:bb348c97df44 938 }
lypinator 0:bb348c97df44 939 #endif /* PWR_CR_UDEN */
lypinator 0:bb348c97df44 940 /**
lypinator 0:bb348c97df44 941 * @brief Clear Standby Flag
lypinator 0:bb348c97df44 942 * @rmtoll CR CSBF LL_PWR_ClearFlag_SB
lypinator 0:bb348c97df44 943 * @retval None
lypinator 0:bb348c97df44 944 */
lypinator 0:bb348c97df44 945 __STATIC_INLINE void LL_PWR_ClearFlag_SB(void)
lypinator 0:bb348c97df44 946 {
lypinator 0:bb348c97df44 947 SET_BIT(PWR->CR, PWR_CR_CSBF);
lypinator 0:bb348c97df44 948 }
lypinator 0:bb348c97df44 949
lypinator 0:bb348c97df44 950 /**
lypinator 0:bb348c97df44 951 * @brief Clear Wake-up Flags
lypinator 0:bb348c97df44 952 * @rmtoll CR CWUF LL_PWR_ClearFlag_WU
lypinator 0:bb348c97df44 953 * @retval None
lypinator 0:bb348c97df44 954 */
lypinator 0:bb348c97df44 955 __STATIC_INLINE void LL_PWR_ClearFlag_WU(void)
lypinator 0:bb348c97df44 956 {
lypinator 0:bb348c97df44 957 SET_BIT(PWR->CR, PWR_CR_CWUF);
lypinator 0:bb348c97df44 958 }
lypinator 0:bb348c97df44 959 #if defined(PWR_CSR_UDRDY)
lypinator 0:bb348c97df44 960 /**
lypinator 0:bb348c97df44 961 * @brief Clear Under-Drive ready Flag
lypinator 0:bb348c97df44 962 * @rmtoll CSR UDRDY LL_PWR_ClearFlag_UD
lypinator 0:bb348c97df44 963 * @retval None
lypinator 0:bb348c97df44 964 */
lypinator 0:bb348c97df44 965 __STATIC_INLINE void LL_PWR_ClearFlag_UD(void)
lypinator 0:bb348c97df44 966 {
lypinator 0:bb348c97df44 967 WRITE_REG(PWR->CSR, PWR_CSR_UDRDY);
lypinator 0:bb348c97df44 968 }
lypinator 0:bb348c97df44 969 #endif /* PWR_CSR_UDRDY */
lypinator 0:bb348c97df44 970
lypinator 0:bb348c97df44 971 /**
lypinator 0:bb348c97df44 972 * @}
lypinator 0:bb348c97df44 973 */
lypinator 0:bb348c97df44 974
lypinator 0:bb348c97df44 975 #if defined(USE_FULL_LL_DRIVER)
lypinator 0:bb348c97df44 976 /** @defgroup PWR_LL_EF_Init De-initialization function
lypinator 0:bb348c97df44 977 * @{
lypinator 0:bb348c97df44 978 */
lypinator 0:bb348c97df44 979 ErrorStatus LL_PWR_DeInit(void);
lypinator 0:bb348c97df44 980 /**
lypinator 0:bb348c97df44 981 * @}
lypinator 0:bb348c97df44 982 */
lypinator 0:bb348c97df44 983 #endif /* USE_FULL_LL_DRIVER */
lypinator 0:bb348c97df44 984
lypinator 0:bb348c97df44 985 /**
lypinator 0:bb348c97df44 986 * @}
lypinator 0:bb348c97df44 987 */
lypinator 0:bb348c97df44 988
lypinator 0:bb348c97df44 989 /**
lypinator 0:bb348c97df44 990 * @}
lypinator 0:bb348c97df44 991 */
lypinator 0:bb348c97df44 992
lypinator 0:bb348c97df44 993 #endif /* defined(PWR) */
lypinator 0:bb348c97df44 994
lypinator 0:bb348c97df44 995 /**
lypinator 0:bb348c97df44 996 * @}
lypinator 0:bb348c97df44 997 */
lypinator 0:bb348c97df44 998
lypinator 0:bb348c97df44 999 #ifdef __cplusplus
lypinator 0:bb348c97df44 1000 }
lypinator 0:bb348c97df44 1001 #endif
lypinator 0:bb348c97df44 1002
lypinator 0:bb348c97df44 1003 #endif /* __STM32F4xx_LL_PWR_H */
lypinator 0:bb348c97df44 1004
lypinator 0:bb348c97df44 1005 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/