Thomas Lyp / DevLibMemoryController

Initial commit

Dependencies:   FastPWM

mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_i2c.h@0:bb348c97df44, 2020-09-16 (annotated)

Committer:
lypinator
Date:
Wed Sep 16 01:11:49 2020 +0000
Revision:
0:bb348c97df44
Added PWM

Who changed what in which revision?

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lypinator 0:bb348c97df44 1 /**
lypinator 0:bb348c97df44 2 ******************************************************************************
lypinator 0:bb348c97df44 3 * @file stm32f4xx_ll_i2c.h
lypinator 0:bb348c97df44 4 * @author MCD Application Team
lypinator 0:bb348c97df44 5 * @brief Header file of I2C LL module.
lypinator 0:bb348c97df44 6 ******************************************************************************
lypinator 0:bb348c97df44 7 * @attention
lypinator 0:bb348c97df44 8 *
lypinator 0:bb348c97df44 9 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
lypinator 0:bb348c97df44 10 *
lypinator 0:bb348c97df44 11 * Redistribution and use in source and binary forms, with or without modification,
lypinator 0:bb348c97df44 12 * are permitted provided that the following conditions are met:
lypinator 0:bb348c97df44 13 * 1. Redistributions of source code must retain the above copyright notice,
lypinator 0:bb348c97df44 14 * this list of conditions and the following disclaimer.
lypinator 0:bb348c97df44 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
lypinator 0:bb348c97df44 16 * this list of conditions and the following disclaimer in the documentation
lypinator 0:bb348c97df44 17 * and/or other materials provided with the distribution.
lypinator 0:bb348c97df44 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
lypinator 0:bb348c97df44 19 * may be used to endorse or promote products derived from this software
lypinator 0:bb348c97df44 20 * without specific prior written permission.
lypinator 0:bb348c97df44 21 *
lypinator 0:bb348c97df44 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
lypinator 0:bb348c97df44 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
lypinator 0:bb348c97df44 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
lypinator 0:bb348c97df44 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
lypinator 0:bb348c97df44 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
lypinator 0:bb348c97df44 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
lypinator 0:bb348c97df44 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
lypinator 0:bb348c97df44 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
lypinator 0:bb348c97df44 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
lypinator 0:bb348c97df44 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
lypinator 0:bb348c97df44 32 *
lypinator 0:bb348c97df44 33 ******************************************************************************
lypinator 0:bb348c97df44 34 */
lypinator 0:bb348c97df44 35
lypinator 0:bb348c97df44 36 /* Define to prevent recursive inclusion -------------------------------------*/
lypinator 0:bb348c97df44 37 #ifndef __STM32F4xx_LL_I2C_H
lypinator 0:bb348c97df44 38 #define __STM32F4xx_LL_I2C_H
lypinator 0:bb348c97df44 39
lypinator 0:bb348c97df44 40 #ifdef __cplusplus
lypinator 0:bb348c97df44 41 extern "C" {
lypinator 0:bb348c97df44 42 #endif
lypinator 0:bb348c97df44 43
lypinator 0:bb348c97df44 44 /* Includes ------------------------------------------------------------------*/
lypinator 0:bb348c97df44 45 #include "stm32f4xx.h"
lypinator 0:bb348c97df44 46
lypinator 0:bb348c97df44 47 /** @addtogroup STM32F4xx_LL_Driver
lypinator 0:bb348c97df44 48 * @{
lypinator 0:bb348c97df44 49 */
lypinator 0:bb348c97df44 50
lypinator 0:bb348c97df44 51 #if defined (I2C1) || defined (I2C2) || defined (I2C3)
lypinator 0:bb348c97df44 52
lypinator 0:bb348c97df44 53 /** @defgroup I2C_LL I2C
lypinator 0:bb348c97df44 54 * @{
lypinator 0:bb348c97df44 55 */
lypinator 0:bb348c97df44 56
lypinator 0:bb348c97df44 57 /* Private types -------------------------------------------------------------*/
lypinator 0:bb348c97df44 58 /* Private variables ---------------------------------------------------------*/
lypinator 0:bb348c97df44 59
lypinator 0:bb348c97df44 60 /* Private constants ---------------------------------------------------------*/
lypinator 0:bb348c97df44 61 /** @defgroup I2C_LL_Private_Constants I2C Private Constants
lypinator 0:bb348c97df44 62 * @{
lypinator 0:bb348c97df44 63 */
lypinator 0:bb348c97df44 64
lypinator 0:bb348c97df44 65 /* Defines used to perform compute and check in the macros */
lypinator 0:bb348c97df44 66 #define LL_I2C_MAX_SPEED_STANDARD 100000U
lypinator 0:bb348c97df44 67 #define LL_I2C_MAX_SPEED_FAST 400000U
lypinator 0:bb348c97df44 68 /**
lypinator 0:bb348c97df44 69 * @}
lypinator 0:bb348c97df44 70 */
lypinator 0:bb348c97df44 71
lypinator 0:bb348c97df44 72 /* Private macros ------------------------------------------------------------*/
lypinator 0:bb348c97df44 73 #if defined(USE_FULL_LL_DRIVER)
lypinator 0:bb348c97df44 74 /** @defgroup I2C_LL_Private_Macros I2C Private Macros
lypinator 0:bb348c97df44 75 * @{
lypinator 0:bb348c97df44 76 */
lypinator 0:bb348c97df44 77 /**
lypinator 0:bb348c97df44 78 * @}
lypinator 0:bb348c97df44 79 */
lypinator 0:bb348c97df44 80 #endif /*USE_FULL_LL_DRIVER*/
lypinator 0:bb348c97df44 81
lypinator 0:bb348c97df44 82 /* Exported types ------------------------------------------------------------*/
lypinator 0:bb348c97df44 83 #if defined(USE_FULL_LL_DRIVER)
lypinator 0:bb348c97df44 84 /** @defgroup I2C_LL_ES_INIT I2C Exported Init structure
lypinator 0:bb348c97df44 85 * @{
lypinator 0:bb348c97df44 86 */
lypinator 0:bb348c97df44 87 typedef struct
lypinator 0:bb348c97df44 88 {
lypinator 0:bb348c97df44 89 uint32_t PeripheralMode; /*!< Specifies the peripheral mode.
lypinator 0:bb348c97df44 90 This parameter can be a value of @ref I2C_LL_EC_PERIPHERAL_MODE
lypinator 0:bb348c97df44 91
lypinator 0:bb348c97df44 92 This feature can be modified afterwards using unitary function @ref LL_I2C_SetMode(). */
lypinator 0:bb348c97df44 93
lypinator 0:bb348c97df44 94 uint32_t ClockSpeed; /*!< Specifies the clock frequency.
lypinator 0:bb348c97df44 95 This parameter must be set to a value lower than 400kHz (in Hz)
lypinator 0:bb348c97df44 96
lypinator 0:bb348c97df44 97 This feature can be modified afterwards using unitary function @ref LL_I2C_SetClockPeriod()
lypinator 0:bb348c97df44 98 or @ref LL_I2C_SetDutyCycle() or @ref LL_I2C_SetClockSpeedMode() or @ref LL_I2C_ConfigSpeed(). */
lypinator 0:bb348c97df44 99
lypinator 0:bb348c97df44 100 uint32_t DutyCycle; /*!< Specifies the I2C fast mode duty cycle.
lypinator 0:bb348c97df44 101 This parameter can be a value of @ref I2C_LL_EC_DUTYCYCLE
lypinator 0:bb348c97df44 102
lypinator 0:bb348c97df44 103 This feature can be modified afterwards using unitary function @ref LL_I2C_SetDutyCycle(). */
lypinator 0:bb348c97df44 104
lypinator 0:bb348c97df44 105 #if defined(I2C_FLTR_ANOFF)&&defined(I2C_FLTR_DNF)
lypinator 0:bb348c97df44 106 uint32_t AnalogFilter; /*!< Enables or disables analog noise filter.
lypinator 0:bb348c97df44 107 This parameter can be a value of @ref I2C_LL_EC_ANALOGFILTER_SELECTION
lypinator 0:bb348c97df44 108
lypinator 0:bb348c97df44 109 This feature can be modified afterwards using unitary functions @ref LL_I2C_EnableAnalogFilter() or LL_I2C_DisableAnalogFilter(). */
lypinator 0:bb348c97df44 110
lypinator 0:bb348c97df44 111 uint32_t DigitalFilter; /*!< Configures the digital noise filter.
lypinator 0:bb348c97df44 112 This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x0F
lypinator 0:bb348c97df44 113
lypinator 0:bb348c97df44 114 This feature can be modified afterwards using unitary function @ref LL_I2C_SetDigitalFilter(). */
lypinator 0:bb348c97df44 115
lypinator 0:bb348c97df44 116 #endif
lypinator 0:bb348c97df44 117 uint32_t OwnAddress1; /*!< Specifies the device own address 1.
lypinator 0:bb348c97df44 118 This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF
lypinator 0:bb348c97df44 119
lypinator 0:bb348c97df44 120 This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */
lypinator 0:bb348c97df44 121
lypinator 0:bb348c97df44 122 uint32_t TypeAcknowledge; /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
lypinator 0:bb348c97df44 123 This parameter can be a value of @ref I2C_LL_EC_I2C_ACKNOWLEDGE
lypinator 0:bb348c97df44 124
lypinator 0:bb348c97df44 125 This feature can be modified afterwards using unitary function @ref LL_I2C_AcknowledgeNextData(). */
lypinator 0:bb348c97df44 126
lypinator 0:bb348c97df44 127 uint32_t OwnAddrSize; /*!< Specifies the device own address 1 size (7-bit or 10-bit).
lypinator 0:bb348c97df44 128 This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS1
lypinator 0:bb348c97df44 129
lypinator 0:bb348c97df44 130 This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */
lypinator 0:bb348c97df44 131 } LL_I2C_InitTypeDef;
lypinator 0:bb348c97df44 132 /**
lypinator 0:bb348c97df44 133 * @}
lypinator 0:bb348c97df44 134 */
lypinator 0:bb348c97df44 135 #endif /*USE_FULL_LL_DRIVER*/
lypinator 0:bb348c97df44 136
lypinator 0:bb348c97df44 137 /* Exported constants --------------------------------------------------------*/
lypinator 0:bb348c97df44 138 /** @defgroup I2C_LL_Exported_Constants I2C Exported Constants
lypinator 0:bb348c97df44 139 * @{
lypinator 0:bb348c97df44 140 */
lypinator 0:bb348c97df44 141
lypinator 0:bb348c97df44 142 /** @defgroup I2C_LL_EC_GET_FLAG Get Flags Defines
lypinator 0:bb348c97df44 143 * @brief Flags defines which can be used with LL_I2C_ReadReg function
lypinator 0:bb348c97df44 144 * @{
lypinator 0:bb348c97df44 145 */
lypinator 0:bb348c97df44 146 #define LL_I2C_SR1_SB I2C_SR1_SB /*!< Start Bit (master mode) */
lypinator 0:bb348c97df44 147 #define LL_I2C_SR1_ADDR I2C_SR1_ADDR /*!< Address sent (master mode) or
lypinator 0:bb348c97df44 148 Address matched flag (slave mode) */
lypinator 0:bb348c97df44 149 #define LL_I2C_SR1_BTF I2C_SR1_BTF /*!< Byte Transfer Finished flag */
lypinator 0:bb348c97df44 150 #define LL_I2C_SR1_ADD10 I2C_SR1_ADD10 /*!< 10-bit header sent (master mode) */
lypinator 0:bb348c97df44 151 #define LL_I2C_SR1_STOPF I2C_SR1_STOPF /*!< Stop detection flag (slave mode) */
lypinator 0:bb348c97df44 152 #define LL_I2C_SR1_RXNE I2C_SR1_RXNE /*!< Data register not empty (receivers) */
lypinator 0:bb348c97df44 153 #define LL_I2C_SR1_TXE I2C_SR1_TXE /*!< Data register empty (transmitters) */
lypinator 0:bb348c97df44 154 #define LL_I2C_SR1_BERR I2C_SR1_BERR /*!< Bus error */
lypinator 0:bb348c97df44 155 #define LL_I2C_SR1_ARLO I2C_SR1_ARLO /*!< Arbitration lost */
lypinator 0:bb348c97df44 156 #define LL_I2C_SR1_AF I2C_SR1_AF /*!< Acknowledge failure flag */
lypinator 0:bb348c97df44 157 #define LL_I2C_SR1_OVR I2C_SR1_OVR /*!< Overrun/Underrun */
lypinator 0:bb348c97df44 158 #define LL_I2C_SR1_PECERR I2C_ISR_PECERR /*!< PEC Error in reception (SMBus mode) */
lypinator 0:bb348c97df44 159 #define LL_I2C_SR1_TIMEOUT I2C_ISR_TIMEOUT /*!< Timeout detection flag (SMBus mode) */
lypinator 0:bb348c97df44 160 #define LL_I2C_SR1_SMALERT I2C_ISR_SMALERT /*!< SMBus alert (SMBus mode) */
lypinator 0:bb348c97df44 161 #define LL_I2C_SR2_MSL I2C_SR2_MSL /*!< Master/Slave flag */
lypinator 0:bb348c97df44 162 #define LL_I2C_SR2_BUSY I2C_SR2_BUSY /*!< Bus busy flag */
lypinator 0:bb348c97df44 163 #define LL_I2C_SR2_TRA I2C_SR2_TRA /*!< Transmitter/receiver direction */
lypinator 0:bb348c97df44 164 #define LL_I2C_SR2_GENCALL I2C_SR2_GENCALL /*!< General call address (Slave mode) */
lypinator 0:bb348c97df44 165 #define LL_I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT /*!< SMBus Device default address (Slave mode) */
lypinator 0:bb348c97df44 166 #define LL_I2C_SR2_SMBHOST I2C_SR2_SMBHOST /*!< SMBus Host address (Slave mode) */
lypinator 0:bb348c97df44 167 #define LL_I2C_SR2_DUALF I2C_SR2_DUALF /*!< Dual flag (Slave mode) */
lypinator 0:bb348c97df44 168 /**
lypinator 0:bb348c97df44 169 * @}
lypinator 0:bb348c97df44 170 */
lypinator 0:bb348c97df44 171
lypinator 0:bb348c97df44 172 /** @defgroup I2C_LL_EC_IT IT Defines
lypinator 0:bb348c97df44 173 * @brief IT defines which can be used with LL_I2C_ReadReg and LL_I2C_WriteReg functions
lypinator 0:bb348c97df44 174 * @{
lypinator 0:bb348c97df44 175 */
lypinator 0:bb348c97df44 176 #define LL_I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN /*!< Events interrupts enable */
lypinator 0:bb348c97df44 177 #define LL_I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN /*!< Buffer interrupts enable */
lypinator 0:bb348c97df44 178 #define LL_I2C_CR2_ITERREN I2C_CR2_ITERREN /*!< Error interrupts enable */
lypinator 0:bb348c97df44 179 /**
lypinator 0:bb348c97df44 180 * @}
lypinator 0:bb348c97df44 181 */
lypinator 0:bb348c97df44 182
lypinator 0:bb348c97df44 183 #if defined(I2C_FLTR_ANOFF)
lypinator 0:bb348c97df44 184 /** @defgroup I2C_LL_EC_ANALOGFILTER_SELECTION Analog Filter Selection
lypinator 0:bb348c97df44 185 * @{
lypinator 0:bb348c97df44 186 */
lypinator 0:bb348c97df44 187 #define LL_I2C_ANALOGFILTER_ENABLE 0x00000000U /*!< Analog filter is enabled. */
lypinator 0:bb348c97df44 188 #define LL_I2C_ANALOGFILTER_DISABLE I2C_FLTR_ANOFF /*!< Analog filter is disabled.*/
lypinator 0:bb348c97df44 189 /**
lypinator 0:bb348c97df44 190 * @}
lypinator 0:bb348c97df44 191 */
lypinator 0:bb348c97df44 192
lypinator 0:bb348c97df44 193 #endif
lypinator 0:bb348c97df44 194 /** @defgroup I2C_LL_EC_OWNADDRESS1 Own Address 1 Length
lypinator 0:bb348c97df44 195 * @{
lypinator 0:bb348c97df44 196 */
lypinator 0:bb348c97df44 197 #define LL_I2C_OWNADDRESS1_7BIT 0x00004000U /*!< Own address 1 is a 7-bit address. */
lypinator 0:bb348c97df44 198 #define LL_I2C_OWNADDRESS1_10BIT (uint32_t)(I2C_OAR1_ADDMODE | 0x00004000U) /*!< Own address 1 is a 10-bit address. */
lypinator 0:bb348c97df44 199 /**
lypinator 0:bb348c97df44 200 * @}
lypinator 0:bb348c97df44 201 */
lypinator 0:bb348c97df44 202
lypinator 0:bb348c97df44 203 /** @defgroup I2C_LL_EC_DUTYCYCLE Fast Mode Duty Cycle
lypinator 0:bb348c97df44 204 * @{
lypinator 0:bb348c97df44 205 */
lypinator 0:bb348c97df44 206 #define LL_I2C_DUTYCYCLE_2 0x00000000U /*!< I2C fast mode Tlow/Thigh = 2 */
lypinator 0:bb348c97df44 207 #define LL_I2C_DUTYCYCLE_16_9 I2C_CCR_DUTY /*!< I2C fast mode Tlow/Thigh = 16/9 */
lypinator 0:bb348c97df44 208 /**
lypinator 0:bb348c97df44 209 * @}
lypinator 0:bb348c97df44 210 */
lypinator 0:bb348c97df44 211
lypinator 0:bb348c97df44 212 /** @defgroup I2C_LL_EC_CLOCK_SPEED_MODE Master Clock Speed Mode
lypinator 0:bb348c97df44 213 * @{
lypinator 0:bb348c97df44 214 */
lypinator 0:bb348c97df44 215 #define LL_I2C_CLOCK_SPEED_STANDARD_MODE 0x00000000U /*!< Master clock speed range is standard mode */
lypinator 0:bb348c97df44 216 #define LL_I2C_CLOCK_SPEED_FAST_MODE I2C_CCR_FS /*!< Master clock speed range is fast mode */
lypinator 0:bb348c97df44 217 /**
lypinator 0:bb348c97df44 218 * @}
lypinator 0:bb348c97df44 219 */
lypinator 0:bb348c97df44 220
lypinator 0:bb348c97df44 221 /** @defgroup I2C_LL_EC_PERIPHERAL_MODE Peripheral Mode
lypinator 0:bb348c97df44 222 * @{
lypinator 0:bb348c97df44 223 */
lypinator 0:bb348c97df44 224 #define LL_I2C_MODE_I2C 0x00000000U /*!< I2C Master or Slave mode */
lypinator 0:bb348c97df44 225 #define LL_I2C_MODE_SMBUS_HOST (uint32_t)(I2C_CR1_SMBUS | I2C_CR1_SMBTYPE | I2C_CR1_ENARP) /*!< SMBus Host address acknowledge */
lypinator 0:bb348c97df44 226 #define LL_I2C_MODE_SMBUS_DEVICE I2C_CR1_SMBUS /*!< SMBus Device default mode (Default address not acknowledge) */
lypinator 0:bb348c97df44 227 #define LL_I2C_MODE_SMBUS_DEVICE_ARP (uint32_t)(I2C_CR1_SMBUS | I2C_CR1_ENARP) /*!< SMBus Device Default address acknowledge */
lypinator 0:bb348c97df44 228 /**
lypinator 0:bb348c97df44 229 * @}
lypinator 0:bb348c97df44 230 */
lypinator 0:bb348c97df44 231
lypinator 0:bb348c97df44 232 /** @defgroup I2C_LL_EC_I2C_ACKNOWLEDGE Acknowledge Generation
lypinator 0:bb348c97df44 233 * @{
lypinator 0:bb348c97df44 234 */
lypinator 0:bb348c97df44 235 #define LL_I2C_ACK I2C_CR1_ACK /*!< ACK is sent after current received byte. */
lypinator 0:bb348c97df44 236 #define LL_I2C_NACK 0x00000000U /*!< NACK is sent after current received byte.*/
lypinator 0:bb348c97df44 237 /**
lypinator 0:bb348c97df44 238 * @}
lypinator 0:bb348c97df44 239 */
lypinator 0:bb348c97df44 240
lypinator 0:bb348c97df44 241 /** @defgroup I2C_LL_EC_DIRECTION Read Write Direction
lypinator 0:bb348c97df44 242 * @{
lypinator 0:bb348c97df44 243 */
lypinator 0:bb348c97df44 244 #define LL_I2C_DIRECTION_WRITE I2C_SR2_TRA /*!< Bus is in write transfer */
lypinator 0:bb348c97df44 245 #define LL_I2C_DIRECTION_READ 0x00000000U /*!< Bus is in read transfer */
lypinator 0:bb348c97df44 246 /**
lypinator 0:bb348c97df44 247 * @}
lypinator 0:bb348c97df44 248 */
lypinator 0:bb348c97df44 249
lypinator 0:bb348c97df44 250 /**
lypinator 0:bb348c97df44 251 * @}
lypinator 0:bb348c97df44 252 */
lypinator 0:bb348c97df44 253
lypinator 0:bb348c97df44 254 /* Exported macro ------------------------------------------------------------*/
lypinator 0:bb348c97df44 255 /** @defgroup I2C_LL_Exported_Macros I2C Exported Macros
lypinator 0:bb348c97df44 256 * @{
lypinator 0:bb348c97df44 257 */
lypinator 0:bb348c97df44 258
lypinator 0:bb348c97df44 259 /** @defgroup I2C_LL_EM_WRITE_READ Common Write and read registers Macros
lypinator 0:bb348c97df44 260 * @{
lypinator 0:bb348c97df44 261 */
lypinator 0:bb348c97df44 262
lypinator 0:bb348c97df44 263 /**
lypinator 0:bb348c97df44 264 * @brief Write a value in I2C register
lypinator 0:bb348c97df44 265 * @param __INSTANCE__ I2C Instance
lypinator 0:bb348c97df44 266 * @param __REG__ Register to be written
lypinator 0:bb348c97df44 267 * @param __VALUE__ Value to be written in the register
lypinator 0:bb348c97df44 268 * @retval None
lypinator 0:bb348c97df44 269 */
lypinator 0:bb348c97df44 270 #define LL_I2C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
lypinator 0:bb348c97df44 271
lypinator 0:bb348c97df44 272 /**
lypinator 0:bb348c97df44 273 * @brief Read a value in I2C register
lypinator 0:bb348c97df44 274 * @param __INSTANCE__ I2C Instance
lypinator 0:bb348c97df44 275 * @param __REG__ Register to be read
lypinator 0:bb348c97df44 276 * @retval Register value
lypinator 0:bb348c97df44 277 */
lypinator 0:bb348c97df44 278 #define LL_I2C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
lypinator 0:bb348c97df44 279 /**
lypinator 0:bb348c97df44 280 * @}
lypinator 0:bb348c97df44 281 */
lypinator 0:bb348c97df44 282
lypinator 0:bb348c97df44 283 /** @defgroup I2C_LL_EM_Exported_Macros_Helper Exported_Macros_Helper
lypinator 0:bb348c97df44 284 * @{
lypinator 0:bb348c97df44 285 */
lypinator 0:bb348c97df44 286
lypinator 0:bb348c97df44 287 /**
lypinator 0:bb348c97df44 288 * @brief Convert Peripheral Clock Frequency in Mhz.
lypinator 0:bb348c97df44 289 * @param __PCLK__ This parameter must be a value of peripheral clock (in Hz).
lypinator 0:bb348c97df44 290 * @retval Value of peripheral clock (in Mhz)
lypinator 0:bb348c97df44 291 */
lypinator 0:bb348c97df44 292 #define __LL_I2C_FREQ_HZ_TO_MHZ(__PCLK__) (uint32_t)((__PCLK__)/1000000U)
lypinator 0:bb348c97df44 293
lypinator 0:bb348c97df44 294 /**
lypinator 0:bb348c97df44 295 * @brief Convert Peripheral Clock Frequency in Hz.
lypinator 0:bb348c97df44 296 * @param __PCLK__ This parameter must be a value of peripheral clock (in Mhz).
lypinator 0:bb348c97df44 297 * @retval Value of peripheral clock (in Hz)
lypinator 0:bb348c97df44 298 */
lypinator 0:bb348c97df44 299 #define __LL_I2C_FREQ_MHZ_TO_HZ(__PCLK__) (uint32_t)((__PCLK__)*1000000U)
lypinator 0:bb348c97df44 300
lypinator 0:bb348c97df44 301 /**
lypinator 0:bb348c97df44 302 * @brief Compute I2C Clock rising time.
lypinator 0:bb348c97df44 303 * @param __FREQRANGE__ This parameter must be a value of peripheral clock (in Mhz).
lypinator 0:bb348c97df44 304 * @param __SPEED__ This parameter must be a value lower than 400kHz (in Hz).
lypinator 0:bb348c97df44 305 * @retval Value between Min_Data=0x02 and Max_Data=0x3F
lypinator 0:bb348c97df44 306 */
lypinator 0:bb348c97df44 307 #define __LL_I2C_RISE_TIME(__FREQRANGE__, __SPEED__) (uint32_t)(((__SPEED__) <= LL_I2C_MAX_SPEED_STANDARD) ? ((__FREQRANGE__) + 1U) : ((((__FREQRANGE__) * 300U) / 1000U) + 1U))
lypinator 0:bb348c97df44 308
lypinator 0:bb348c97df44 309 /**
lypinator 0:bb348c97df44 310 * @brief Compute Speed clock range to a Clock Control Register (I2C_CCR_CCR) value.
lypinator 0:bb348c97df44 311 * @param __PCLK__ This parameter must be a value of peripheral clock (in Hz).
lypinator 0:bb348c97df44 312 * @param __SPEED__ This parameter must be a value lower than 400kHz (in Hz).
lypinator 0:bb348c97df44 313 * @param __DUTYCYCLE__ This parameter can be one of the following values:
lypinator 0:bb348c97df44 314 * @arg @ref LL_I2C_DUTYCYCLE_2
lypinator 0:bb348c97df44 315 * @arg @ref LL_I2C_DUTYCYCLE_16_9
lypinator 0:bb348c97df44 316 * @retval Value between Min_Data=0x004 and Max_Data=0xFFF, except in FAST DUTY mode where Min_Data=0x001.
lypinator 0:bb348c97df44 317 */
lypinator 0:bb348c97df44 318 #define __LL_I2C_SPEED_TO_CCR(__PCLK__, __SPEED__, __DUTYCYCLE__) (uint32_t)(((__SPEED__) <= LL_I2C_MAX_SPEED_STANDARD)? \
lypinator 0:bb348c97df44 319 (__LL_I2C_SPEED_STANDARD_TO_CCR((__PCLK__), (__SPEED__))) : \
lypinator 0:bb348c97df44 320 (__LL_I2C_SPEED_FAST_TO_CCR((__PCLK__), (__SPEED__), (__DUTYCYCLE__))))
lypinator 0:bb348c97df44 321
lypinator 0:bb348c97df44 322 /**
lypinator 0:bb348c97df44 323 * @brief Compute Speed Standard clock range to a Clock Control Register (I2C_CCR_CCR) value.
lypinator 0:bb348c97df44 324 * @param __PCLK__ This parameter must be a value of peripheral clock (in Hz).
lypinator 0:bb348c97df44 325 * @param __SPEED__ This parameter must be a value lower than 100kHz (in Hz).
lypinator 0:bb348c97df44 326 * @retval Value between Min_Data=0x004 and Max_Data=0xFFF.
lypinator 0:bb348c97df44 327 */
lypinator 0:bb348c97df44 328 #define __LL_I2C_SPEED_STANDARD_TO_CCR(__PCLK__, __SPEED__) (uint32_t)(((((__PCLK__)/((__SPEED__) << 1U)) & I2C_CCR_CCR) < 4U)? 4U:((__PCLK__) / ((__SPEED__) << 1U)))
lypinator 0:bb348c97df44 329
lypinator 0:bb348c97df44 330 /**
lypinator 0:bb348c97df44 331 * @brief Compute Speed Fast clock range to a Clock Control Register (I2C_CCR_CCR) value.
lypinator 0:bb348c97df44 332 * @param __PCLK__ This parameter must be a value of peripheral clock (in Hz).
lypinator 0:bb348c97df44 333 * @param __SPEED__ This parameter must be a value between Min_Data=100Khz and Max_Data=400Khz (in Hz).
lypinator 0:bb348c97df44 334 * @param __DUTYCYCLE__ This parameter can be one of the following values:
lypinator 0:bb348c97df44 335 * @arg @ref LL_I2C_DUTYCYCLE_2
lypinator 0:bb348c97df44 336 * @arg @ref LL_I2C_DUTYCYCLE_16_9
lypinator 0:bb348c97df44 337 * @retval Value between Min_Data=0x001 and Max_Data=0xFFF
lypinator 0:bb348c97df44 338 */
lypinator 0:bb348c97df44 339 #define __LL_I2C_SPEED_FAST_TO_CCR(__PCLK__, __SPEED__, __DUTYCYCLE__) (uint32_t)(((__DUTYCYCLE__) == LL_I2C_DUTYCYCLE_2)? \
lypinator 0:bb348c97df44 340 (((((__PCLK__) / ((__SPEED__) * 3U)) & I2C_CCR_CCR) == 0U)? 1U:((__PCLK__) / ((__SPEED__) * 3U))) : \
lypinator 0:bb348c97df44 341 (((((__PCLK__) / ((__SPEED__) * 25U)) & I2C_CCR_CCR) == 0U)? 1U:((__PCLK__) / ((__SPEED__) * 25U))))
lypinator 0:bb348c97df44 342
lypinator 0:bb348c97df44 343 /**
lypinator 0:bb348c97df44 344 * @brief Get the Least significant bits of a 10-Bits address.
lypinator 0:bb348c97df44 345 * @param __ADDRESS__ This parameter must be a value of a 10-Bits slave address.
lypinator 0:bb348c97df44 346 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
lypinator 0:bb348c97df44 347 */
lypinator 0:bb348c97df44 348 #define __LL_I2C_10BIT_ADDRESS(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF))))
lypinator 0:bb348c97df44 349
lypinator 0:bb348c97df44 350 /**
lypinator 0:bb348c97df44 351 * @brief Convert a 10-Bits address to a 10-Bits header with Write direction.
lypinator 0:bb348c97df44 352 * @param __ADDRESS__ This parameter must be a value of a 10-Bits slave address.
lypinator 0:bb348c97df44 353 * @retval Value between Min_Data=0xF0 and Max_Data=0xF6
lypinator 0:bb348c97df44 354 */
lypinator 0:bb348c97df44 355 #define __LL_I2C_10BIT_HEADER_WRITE(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF0))))
lypinator 0:bb348c97df44 356
lypinator 0:bb348c97df44 357 /**
lypinator 0:bb348c97df44 358 * @brief Convert a 10-Bits address to a 10-Bits header with Read direction.
lypinator 0:bb348c97df44 359 * @param __ADDRESS__ This parameter must be a value of a 10-Bits slave address.
lypinator 0:bb348c97df44 360 * @retval Value between Min_Data=0xF1 and Max_Data=0xF7
lypinator 0:bb348c97df44 361 */
lypinator 0:bb348c97df44 362 #define __LL_I2C_10BIT_HEADER_READ(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF1))))
lypinator 0:bb348c97df44 363
lypinator 0:bb348c97df44 364 /**
lypinator 0:bb348c97df44 365 * @}
lypinator 0:bb348c97df44 366 */
lypinator 0:bb348c97df44 367
lypinator 0:bb348c97df44 368 /**
lypinator 0:bb348c97df44 369 * @}
lypinator 0:bb348c97df44 370 */
lypinator 0:bb348c97df44 371
lypinator 0:bb348c97df44 372 /* Exported functions --------------------------------------------------------*/
lypinator 0:bb348c97df44 373
lypinator 0:bb348c97df44 374 /** @defgroup I2C_LL_Exported_Functions I2C Exported Functions
lypinator 0:bb348c97df44 375 * @{
lypinator 0:bb348c97df44 376 */
lypinator 0:bb348c97df44 377
lypinator 0:bb348c97df44 378 /** @defgroup I2C_LL_EF_Configuration Configuration
lypinator 0:bb348c97df44 379 * @{
lypinator 0:bb348c97df44 380 */
lypinator 0:bb348c97df44 381
lypinator 0:bb348c97df44 382 /**
lypinator 0:bb348c97df44 383 * @brief Enable I2C peripheral (PE = 1).
lypinator 0:bb348c97df44 384 * @rmtoll CR1 PE LL_I2C_Enable
lypinator 0:bb348c97df44 385 * @param I2Cx I2C Instance.
lypinator 0:bb348c97df44 386 * @retval None
lypinator 0:bb348c97df44 387 */
lypinator 0:bb348c97df44 388 __STATIC_INLINE void LL_I2C_Enable(I2C_TypeDef *I2Cx)
lypinator 0:bb348c97df44 389 {
lypinator 0:bb348c97df44 390 SET_BIT(I2Cx->CR1, I2C_CR1_PE);
lypinator 0:bb348c97df44 391 }
lypinator 0:bb348c97df44 392
lypinator 0:bb348c97df44 393 /**
lypinator 0:bb348c97df44 394 * @brief Disable I2C peripheral (PE = 0).
lypinator 0:bb348c97df44 395 * @rmtoll CR1 PE LL_I2C_Disable
lypinator 0:bb348c97df44 396 * @param I2Cx I2C Instance.
lypinator 0:bb348c97df44 397 * @retval None
lypinator 0:bb348c97df44 398 */
lypinator 0:bb348c97df44 399 __STATIC_INLINE void LL_I2C_Disable(I2C_TypeDef *I2Cx)
lypinator 0:bb348c97df44 400 {
lypinator 0:bb348c97df44 401 CLEAR_BIT(I2Cx->CR1, I2C_CR1_PE);
lypinator 0:bb348c97df44 402 }
lypinator 0:bb348c97df44 403
lypinator 0:bb348c97df44 404 /**
lypinator 0:bb348c97df44 405 * @brief Check if the I2C peripheral is enabled or disabled.
lypinator 0:bb348c97df44 406 * @rmtoll CR1 PE LL_I2C_IsEnabled
lypinator 0:bb348c97df44 407 * @param I2Cx I2C Instance.
lypinator 0:bb348c97df44 408 * @retval State of bit (1 or 0).
lypinator 0:bb348c97df44 409 */
lypinator 0:bb348c97df44 410 __STATIC_INLINE uint32_t LL_I2C_IsEnabled(I2C_TypeDef *I2Cx)
lypinator 0:bb348c97df44 411 {
lypinator 0:bb348c97df44 412 return (READ_BIT(I2Cx->CR1, I2C_CR1_PE) == (I2C_CR1_PE));
lypinator 0:bb348c97df44 413 }
lypinator 0:bb348c97df44 414
lypinator 0:bb348c97df44 415 #if defined(I2C_FLTR_ANOFF)&&defined(I2C_FLTR_DNF)
lypinator 0:bb348c97df44 416 /**
lypinator 0:bb348c97df44 417 * @brief Configure Noise Filters (Analog and Digital).
lypinator 0:bb348c97df44 418 * @note If the analog filter is also enabled, the digital filter is added to analog filter.
lypinator 0:bb348c97df44 419 * The filters can only be programmed when the I2C is disabled (PE = 0).
lypinator 0:bb348c97df44 420 * @rmtoll FLTR ANOFF LL_I2C_ConfigFilters\n
lypinator 0:bb348c97df44 421 * FLTR DNF LL_I2C_ConfigFilters
lypinator 0:bb348c97df44 422 * @param I2Cx I2C Instance.
lypinator 0:bb348c97df44 423 * @param AnalogFilter This parameter can be one of the following values:
lypinator 0:bb348c97df44 424 * @arg @ref LL_I2C_ANALOGFILTER_ENABLE
lypinator 0:bb348c97df44 425 * @arg @ref LL_I2C_ANALOGFILTER_DISABLE
lypinator 0:bb348c97df44 426 * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*TPCLK1)
lypinator 0:bb348c97df44 427 * This parameter is used to configure the digital noise filter on SDA and SCL input. The digital filter will suppress the spikes with a length of up to DNF[3:0]*TPCLK1.
lypinator 0:bb348c97df44 428 * @retval None
lypinator 0:bb348c97df44 429 */
lypinator 0:bb348c97df44 430 __STATIC_INLINE void LL_I2C_ConfigFilters(I2C_TypeDef *I2Cx, uint32_t AnalogFilter, uint32_t DigitalFilter)
lypinator 0:bb348c97df44 431 {
lypinator 0:bb348c97df44 432 MODIFY_REG(I2Cx->FLTR, I2C_FLTR_ANOFF | I2C_FLTR_DNF, AnalogFilter | DigitalFilter);
lypinator 0:bb348c97df44 433 }
lypinator 0:bb348c97df44 434 #endif
lypinator 0:bb348c97df44 435 #if defined(I2C_FLTR_DNF)
lypinator 0:bb348c97df44 436
lypinator 0:bb348c97df44 437 /**
lypinator 0:bb348c97df44 438 * @brief Configure Digital Noise Filter.
lypinator 0:bb348c97df44 439 * @note If the analog filter is also enabled, the digital filter is added to analog filter.
lypinator 0:bb348c97df44 440 * This filter can only be programmed when the I2C is disabled (PE = 0).
lypinator 0:bb348c97df44 441 * @rmtoll FLTR DNF LL_I2C_SetDigitalFilter
lypinator 0:bb348c97df44 442 * @param I2Cx I2C Instance.
lypinator 0:bb348c97df44 443 * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*TPCLK1)
lypinator 0:bb348c97df44 444 * This parameter is used to configure the digital noise filter on SDA and SCL input. The digital filter will suppress the spikes with a length of up to DNF[3:0]*TPCLK1.
lypinator 0:bb348c97df44 445 * @retval None
lypinator 0:bb348c97df44 446 */
lypinator 0:bb348c97df44 447 __STATIC_INLINE void LL_I2C_SetDigitalFilter(I2C_TypeDef *I2Cx, uint32_t DigitalFilter)
lypinator 0:bb348c97df44 448 {
lypinator 0:bb348c97df44 449 MODIFY_REG(I2Cx->FLTR, I2C_FLTR_DNF, DigitalFilter);
lypinator 0:bb348c97df44 450 }
lypinator 0:bb348c97df44 451
lypinator 0:bb348c97df44 452 /**
lypinator 0:bb348c97df44 453 * @brief Get the current Digital Noise Filter configuration.
lypinator 0:bb348c97df44 454 * @rmtoll FLTR DNF LL_I2C_GetDigitalFilter
lypinator 0:bb348c97df44 455 * @param I2Cx I2C Instance.
lypinator 0:bb348c97df44 456 * @retval Value between Min_Data=0x0 and Max_Data=0xF
lypinator 0:bb348c97df44 457 */
lypinator 0:bb348c97df44 458 __STATIC_INLINE uint32_t LL_I2C_GetDigitalFilter(I2C_TypeDef *I2Cx)
lypinator 0:bb348c97df44 459 {
lypinator 0:bb348c97df44 460 return (uint32_t)(READ_BIT(I2Cx->FLTR, I2C_FLTR_DNF));
lypinator 0:bb348c97df44 461 }
lypinator 0:bb348c97df44 462 #endif
lypinator 0:bb348c97df44 463 #if defined(I2C_FLTR_ANOFF)
lypinator 0:bb348c97df44 464
lypinator 0:bb348c97df44 465 /**
lypinator 0:bb348c97df44 466 * @brief Enable Analog Noise Filter.
lypinator 0:bb348c97df44 467 * @note This filter can only be programmed when the I2C is disabled (PE = 0).
lypinator 0:bb348c97df44 468 * @rmtoll FLTR ANOFF LL_I2C_EnableAnalogFilter
lypinator 0:bb348c97df44 469 * @param I2Cx I2C Instance.
lypinator 0:bb348c97df44 470 * @retval None
lypinator 0:bb348c97df44 471 */
lypinator 0:bb348c97df44 472 __STATIC_INLINE void LL_I2C_EnableAnalogFilter(I2C_TypeDef *I2Cx)
lypinator 0:bb348c97df44 473 {
lypinator 0:bb348c97df44 474 CLEAR_BIT(I2Cx->FLTR, I2C_FLTR_ANOFF);
lypinator 0:bb348c97df44 475 }
lypinator 0:bb348c97df44 476
lypinator 0:bb348c97df44 477 /**
lypinator 0:bb348c97df44 478 * @brief Disable Analog Noise Filter.
lypinator 0:bb348c97df44 479 * @note This filter can only be programmed when the I2C is disabled (PE = 0).
lypinator 0:bb348c97df44 480 * @rmtoll FLTR ANOFF LL_I2C_DisableAnalogFilter
lypinator 0:bb348c97df44 481 * @param I2Cx I2C Instance.
lypinator 0:bb348c97df44 482 * @retval None
lypinator 0:bb348c97df44 483 */
lypinator 0:bb348c97df44 484 __STATIC_INLINE void LL_I2C_DisableAnalogFilter(I2C_TypeDef *I2Cx)
lypinator 0:bb348c97df44 485 {
lypinator 0:bb348c97df44 486 SET_BIT(I2Cx->FLTR, I2C_FLTR_ANOFF);
lypinator 0:bb348c97df44 487 }
lypinator 0:bb348c97df44 488
lypinator 0:bb348c97df44 489 /**
lypinator 0:bb348c97df44 490 * @brief Check if Analog Noise Filter is enabled or disabled.
lypinator 0:bb348c97df44 491 * @rmtoll FLTR ANOFF LL_I2C_IsEnabledAnalogFilter
lypinator 0:bb348c97df44 492 * @param I2Cx I2C Instance.
lypinator 0:bb348c97df44 493 * @retval State of bit (1 or 0).
lypinator 0:bb348c97df44 494 */
lypinator 0:bb348c97df44 495 __STATIC_INLINE uint32_t LL_I2C_IsEnabledAnalogFilter(I2C_TypeDef *I2Cx)
lypinator 0:bb348c97df44 496 {
lypinator 0:bb348c97df44 497 return (READ_BIT(I2Cx->FLTR, I2C_FLTR_ANOFF) == (I2C_FLTR_ANOFF));
lypinator 0:bb348c97df44 498 }
lypinator 0:bb348c97df44 499 #endif
lypinator 0:bb348c97df44 500
lypinator 0:bb348c97df44 501 /**
lypinator 0:bb348c97df44 502 * @brief Enable DMA transmission requests.
lypinator 0:bb348c97df44 503 * @rmtoll CR2 DMAEN LL_I2C_EnableDMAReq_TX
lypinator 0:bb348c97df44 504 * @param I2Cx I2C Instance.
lypinator 0:bb348c97df44 505 * @retval None
lypinator 0:bb348c97df44 506 */
lypinator 0:bb348c97df44 507 __STATIC_INLINE void LL_I2C_EnableDMAReq_TX(I2C_TypeDef *I2Cx)
lypinator 0:bb348c97df44 508 {
lypinator 0:bb348c97df44 509 SET_BIT(I2Cx->CR2, I2C_CR2_DMAEN);
lypinator 0:bb348c97df44 510 }
lypinator 0:bb348c97df44 511
lypinator 0:bb348c97df44 512 /**
lypinator 0:bb348c97df44 513 * @brief Disable DMA transmission requests.
lypinator 0:bb348c97df44 514 * @rmtoll CR2 DMAEN LL_I2C_DisableDMAReq_TX
lypinator 0:bb348c97df44 515 * @param I2Cx I2C Instance.
lypinator 0:bb348c97df44 516 * @retval None
lypinator 0:bb348c97df44 517 */
lypinator 0:bb348c97df44 518 __STATIC_INLINE void LL_I2C_DisableDMAReq_TX(I2C_TypeDef *I2Cx)
lypinator 0:bb348c97df44 519 {
lypinator 0:bb348c97df44 520 CLEAR_BIT(I2Cx->CR2, I2C_CR2_DMAEN);
lypinator 0:bb348c97df44 521 }
lypinator 0:bb348c97df44 522
lypinator 0:bb348c97df44 523 /**
lypinator 0:bb348c97df44 524 * @brief Check if DMA transmission requests are enabled or disabled.
lypinator 0:bb348c97df44 525 * @rmtoll CR2 DMAEN LL_I2C_IsEnabledDMAReq_TX
lypinator 0:bb348c97df44 526 * @param I2Cx I2C Instance.
lypinator 0:bb348c97df44 527 * @retval State of bit (1 or 0).
lypinator 0:bb348c97df44 528 */
lypinator 0:bb348c97df44 529 __STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(I2C_TypeDef *I2Cx)
lypinator 0:bb348c97df44 530 {
lypinator 0:bb348c97df44 531 return (READ_BIT(I2Cx->CR2, I2C_CR2_DMAEN) == (I2C_CR2_DMAEN));
lypinator 0:bb348c97df44 532 }
lypinator 0:bb348c97df44 533
lypinator 0:bb348c97df44 534 /**
lypinator 0:bb348c97df44 535 * @brief Enable DMA reception requests.
lypinator 0:bb348c97df44 536 * @rmtoll CR2 DMAEN LL_I2C_EnableDMAReq_RX
lypinator 0:bb348c97df44 537 * @param I2Cx I2C Instance.
lypinator 0:bb348c97df44 538 * @retval None
lypinator 0:bb348c97df44 539 */
lypinator 0:bb348c97df44 540 __STATIC_INLINE void LL_I2C_EnableDMAReq_RX(I2C_TypeDef *I2Cx)
lypinator 0:bb348c97df44 541 {
lypinator 0:bb348c97df44 542 SET_BIT(I2Cx->CR2, I2C_CR2_DMAEN);
lypinator 0:bb348c97df44 543 }
lypinator 0:bb348c97df44 544
lypinator 0:bb348c97df44 545 /**
lypinator 0:bb348c97df44 546 * @brief Disable DMA reception requests.
lypinator 0:bb348c97df44 547 * @rmtoll CR2 DMAEN LL_I2C_DisableDMAReq_RX
lypinator 0:bb348c97df44 548 * @param I2Cx I2C Instance.
lypinator 0:bb348c97df44 549 * @retval None
lypinator 0:bb348c97df44 550 */
lypinator 0:bb348c97df44 551 __STATIC_INLINE void LL_I2C_DisableDMAReq_RX(I2C_TypeDef *I2Cx)
lypinator 0:bb348c97df44 552 {
lypinator 0:bb348c97df44 553 CLEAR_BIT(I2Cx->CR2, I2C_CR2_DMAEN);
lypinator 0:bb348c97df44 554 }
lypinator 0:bb348c97df44 555
lypinator 0:bb348c97df44 556 /**
lypinator 0:bb348c97df44 557 * @brief Check if DMA reception requests are enabled or disabled.
lypinator 0:bb348c97df44 558 * @rmtoll CR2 DMAEN LL_I2C_IsEnabledDMAReq_RX
lypinator 0:bb348c97df44 559 * @param I2Cx I2C Instance.
lypinator 0:bb348c97df44 560 * @retval State of bit (1 or 0).
lypinator 0:bb348c97df44 561 */
lypinator 0:bb348c97df44 562 __STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef *I2Cx)
lypinator 0:bb348c97df44 563 {
lypinator 0:bb348c97df44 564 return (READ_BIT(I2Cx->CR2, I2C_CR2_DMAEN) == (I2C_CR2_DMAEN));
lypinator 0:bb348c97df44 565 }
lypinator 0:bb348c97df44 566
lypinator 0:bb348c97df44 567 /**
lypinator 0:bb348c97df44 568 * @brief Get the data register address used for DMA transfer.
lypinator 0:bb348c97df44 569 * @rmtoll DR DR LL_I2C_DMA_GetRegAddr
lypinator 0:bb348c97df44 570 * @param I2Cx I2C Instance.
lypinator 0:bb348c97df44 571 * @retval Address of data register
lypinator 0:bb348c97df44 572 */
lypinator 0:bb348c97df44 573 __STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(I2C_TypeDef *I2Cx)
lypinator 0:bb348c97df44 574 {
lypinator 0:bb348c97df44 575 return (uint32_t) & (I2Cx->DR);
lypinator 0:bb348c97df44 576 }
lypinator 0:bb348c97df44 577
lypinator 0:bb348c97df44 578 /**
lypinator 0:bb348c97df44 579 * @brief Enable Clock stretching.
lypinator 0:bb348c97df44 580 * @note This bit can only be programmed when the I2C is disabled (PE = 0).
lypinator 0:bb348c97df44 581 * @rmtoll CR1 NOSTRETCH LL_I2C_EnableClockStretching
lypinator 0:bb348c97df44 582 * @param I2Cx I2C Instance.
lypinator 0:bb348c97df44 583 * @retval None
lypinator 0:bb348c97df44 584 */
lypinator 0:bb348c97df44 585 __STATIC_INLINE void LL_I2C_EnableClockStretching(I2C_TypeDef *I2Cx)
lypinator 0:bb348c97df44 586 {
lypinator 0:bb348c97df44 587 CLEAR_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
lypinator 0:bb348c97df44 588 }
lypinator 0:bb348c97df44 589
lypinator 0:bb348c97df44 590 /**
lypinator 0:bb348c97df44 591 * @brief Disable Clock stretching.
lypinator 0:bb348c97df44 592 * @note This bit can only be programmed when the I2C is disabled (PE = 0).
lypinator 0:bb348c97df44 593 * @rmtoll CR1 NOSTRETCH LL_I2C_DisableClockStretching
lypinator 0:bb348c97df44 594 * @param I2Cx I2C Instance.
lypinator 0:bb348c97df44 595 * @retval None
lypinator 0:bb348c97df44 596 */
lypinator 0:bb348c97df44 597 __STATIC_INLINE void LL_I2C_DisableClockStretching(I2C_TypeDef *I2Cx)
lypinator 0:bb348c97df44 598 {
lypinator 0:bb348c97df44 599 SET_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
lypinator 0:bb348c97df44 600 }
lypinator 0:bb348c97df44 601
lypinator 0:bb348c97df44 602 /**
lypinator 0:bb348c97df44 603 * @brief Check if Clock stretching is enabled or disabled.
lypinator 0:bb348c97df44 604 * @rmtoll CR1 NOSTRETCH LL_I2C_IsEnabledClockStretching
lypinator 0:bb348c97df44 605 * @param I2Cx I2C Instance.
lypinator 0:bb348c97df44 606 * @retval State of bit (1 or 0).
lypinator 0:bb348c97df44 607 */
lypinator 0:bb348c97df44 608 __STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(I2C_TypeDef *I2Cx)
lypinator 0:bb348c97df44 609 {
lypinator 0:bb348c97df44 610 return (READ_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH));
lypinator 0:bb348c97df44 611 }
lypinator 0:bb348c97df44 612
lypinator 0:bb348c97df44 613 /**
lypinator 0:bb348c97df44 614 * @brief Enable General Call.
lypinator 0:bb348c97df44 615 * @note When enabled the Address 0x00 is ACKed.
lypinator 0:bb348c97df44 616 * @rmtoll CR1 ENGC LL_I2C_EnableGeneralCall
lypinator 0:bb348c97df44 617 * @param I2Cx I2C Instance.
lypinator 0:bb348c97df44 618 * @retval None
lypinator 0:bb348c97df44 619 */
lypinator 0:bb348c97df44 620 __STATIC_INLINE void LL_I2C_EnableGeneralCall(I2C_TypeDef *I2Cx)
lypinator 0:bb348c97df44 621 {
lypinator 0:bb348c97df44 622 SET_BIT(I2Cx->CR1, I2C_CR1_ENGC);
lypinator 0:bb348c97df44 623 }
lypinator 0:bb348c97df44 624
lypinator 0:bb348c97df44 625 /**
lypinator 0:bb348c97df44 626 * @brief Disable General Call.
lypinator 0:bb348c97df44 627 * @note When disabled the Address 0x00 is NACKed.
lypinator 0:bb348c97df44 628 * @rmtoll CR1 ENGC LL_I2C_DisableGeneralCall
lypinator 0:bb348c97df44 629 * @param I2Cx I2C Instance.
lypinator 0:bb348c97df44 630 * @retval None
lypinator 0:bb348c97df44 631 */
lypinator 0:bb348c97df44 632 __STATIC_INLINE void LL_I2C_DisableGeneralCall(I2C_TypeDef *I2Cx)
lypinator 0:bb348c97df44 633 {
lypinator 0:bb348c97df44 634 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ENGC);
lypinator 0:bb348c97df44 635 }
lypinator 0:bb348c97df44 636
lypinator 0:bb348c97df44 637 /**
lypinator 0:bb348c97df44 638 * @brief Check if General Call is enabled or disabled.
lypinator 0:bb348c97df44 639 * @rmtoll CR1 ENGC LL_I2C_IsEnabledGeneralCall
lypinator 0:bb348c97df44 640 * @param I2Cx I2C Instance.
lypinator 0:bb348c97df44 641 * @retval State of bit (1 or 0).
lypinator 0:bb348c97df44 642 */
lypinator 0:bb348c97df44 643 __STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(I2C_TypeDef *I2Cx)
lypinator 0:bb348c97df44 644 {
lypinator 0:bb348c97df44 645 return (READ_BIT(I2Cx->CR1, I2C_CR1_ENGC) == (I2C_CR1_ENGC));
lypinator 0:bb348c97df44 646 }
lypinator 0:bb348c97df44 647
lypinator 0:bb348c97df44 648 /**
lypinator 0:bb348c97df44 649 * @brief Set the Own Address1.
lypinator 0:bb348c97df44 650 * @rmtoll OAR1 ADD0 LL_I2C_SetOwnAddress1\n
lypinator 0:bb348c97df44 651 * OAR1 ADD1_7 LL_I2C_SetOwnAddress1\n
lypinator 0:bb348c97df44 652 * OAR1 ADD8_9 LL_I2C_SetOwnAddress1\n
lypinator 0:bb348c97df44 653 * OAR1 ADDMODE LL_I2C_SetOwnAddress1
lypinator 0:bb348c97df44 654 * @param I2Cx I2C Instance.
lypinator 0:bb348c97df44 655 * @param OwnAddress1 This parameter must be a value between Min_Data=0 and Max_Data=0x3FF.
lypinator 0:bb348c97df44 656 * @param OwnAddrSize This parameter can be one of the following values:
lypinator 0:bb348c97df44 657 * @arg @ref LL_I2C_OWNADDRESS1_7BIT
lypinator 0:bb348c97df44 658 * @arg @ref LL_I2C_OWNADDRESS1_10BIT
lypinator 0:bb348c97df44 659 * @retval None
lypinator 0:bb348c97df44 660 */
lypinator 0:bb348c97df44 661 __STATIC_INLINE void LL_I2C_SetOwnAddress1(I2C_TypeDef *I2Cx, uint32_t OwnAddress1, uint32_t OwnAddrSize)
lypinator 0:bb348c97df44 662 {
lypinator 0:bb348c97df44 663 MODIFY_REG(I2Cx->OAR1, I2C_OAR1_ADD0 | I2C_OAR1_ADD1_7 | I2C_OAR1_ADD8_9 | I2C_OAR1_ADDMODE, OwnAddress1 | OwnAddrSize);
lypinator 0:bb348c97df44 664 }
lypinator 0:bb348c97df44 665
lypinator 0:bb348c97df44 666 /**
lypinator 0:bb348c97df44 667 * @brief Set the 7bits Own Address2.
lypinator 0:bb348c97df44 668 * @note This action has no effect if own address2 is enabled.
lypinator 0:bb348c97df44 669 * @rmtoll OAR2 ADD2 LL_I2C_SetOwnAddress2
lypinator 0:bb348c97df44 670 * @param I2Cx I2C Instance.
lypinator 0:bb348c97df44 671 * @param OwnAddress2 This parameter must be a value between Min_Data=0 and Max_Data=0x7F.
lypinator 0:bb348c97df44 672 * @retval None
lypinator 0:bb348c97df44 673 */
lypinator 0:bb348c97df44 674 __STATIC_INLINE void LL_I2C_SetOwnAddress2(I2C_TypeDef *I2Cx, uint32_t OwnAddress2)
lypinator 0:bb348c97df44 675 {
lypinator 0:bb348c97df44 676 MODIFY_REG(I2Cx->OAR2, I2C_OAR2_ADD2, OwnAddress2);
lypinator 0:bb348c97df44 677 }
lypinator 0:bb348c97df44 678
lypinator 0:bb348c97df44 679 /**
lypinator 0:bb348c97df44 680 * @brief Enable acknowledge on Own Address2 match address.
lypinator 0:bb348c97df44 681 * @rmtoll OAR2 ENDUAL LL_I2C_EnableOwnAddress2
lypinator 0:bb348c97df44 682 * @param I2Cx I2C Instance.
lypinator 0:bb348c97df44 683 * @retval None
lypinator 0:bb348c97df44 684 */
lypinator 0:bb348c97df44 685 __STATIC_INLINE void LL_I2C_EnableOwnAddress2(I2C_TypeDef *I2Cx)
lypinator 0:bb348c97df44 686 {
lypinator 0:bb348c97df44 687 SET_BIT(I2Cx->OAR2, I2C_OAR2_ENDUAL);
lypinator 0:bb348c97df44 688 }
lypinator 0:bb348c97df44 689
lypinator 0:bb348c97df44 690 /**
lypinator 0:bb348c97df44 691 * @brief Disable acknowledge on Own Address2 match address.
lypinator 0:bb348c97df44 692 * @rmtoll OAR2 ENDUAL LL_I2C_DisableOwnAddress2
lypinator 0:bb348c97df44 693 * @param I2Cx I2C Instance.
lypinator 0:bb348c97df44 694 * @retval None
lypinator 0:bb348c97df44 695 */
lypinator 0:bb348c97df44 696 __STATIC_INLINE void LL_I2C_DisableOwnAddress2(I2C_TypeDef *I2Cx)
lypinator 0:bb348c97df44 697 {
lypinator 0:bb348c97df44 698 CLEAR_BIT(I2Cx->OAR2, I2C_OAR2_ENDUAL);
lypinator 0:bb348c97df44 699 }
lypinator 0:bb348c97df44 700
lypinator 0:bb348c97df44 701 /**
lypinator 0:bb348c97df44 702 * @brief Check if Own Address1 acknowledge is enabled or disabled.
lypinator 0:bb348c97df44 703 * @rmtoll OAR2 ENDUAL LL_I2C_IsEnabledOwnAddress2
lypinator 0:bb348c97df44 704 * @param I2Cx I2C Instance.
lypinator 0:bb348c97df44 705 * @retval State of bit (1 or 0).
lypinator 0:bb348c97df44 706 */
lypinator 0:bb348c97df44 707 __STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(I2C_TypeDef *I2Cx)
lypinator 0:bb348c97df44 708 {
lypinator 0:bb348c97df44 709 return (READ_BIT(I2Cx->OAR2, I2C_OAR2_ENDUAL) == (I2C_OAR2_ENDUAL));
lypinator 0:bb348c97df44 710 }
lypinator 0:bb348c97df44 711
lypinator 0:bb348c97df44 712 /**
lypinator 0:bb348c97df44 713 * @brief Configure the Peripheral clock frequency.
lypinator 0:bb348c97df44 714 * @rmtoll CR2 FREQ LL_I2C_SetPeriphClock
lypinator 0:bb348c97df44 715 * @param I2Cx I2C Instance.
lypinator 0:bb348c97df44 716 * @param PeriphClock Peripheral Clock (in Hz)
lypinator 0:bb348c97df44 717 * @retval None
lypinator 0:bb348c97df44 718 */
lypinator 0:bb348c97df44 719 __STATIC_INLINE void LL_I2C_SetPeriphClock(I2C_TypeDef *I2Cx, uint32_t PeriphClock)
lypinator 0:bb348c97df44 720 {
lypinator 0:bb348c97df44 721 MODIFY_REG(I2Cx->CR2, I2C_CR2_FREQ, __LL_I2C_FREQ_HZ_TO_MHZ(PeriphClock));
lypinator 0:bb348c97df44 722 }
lypinator 0:bb348c97df44 723
lypinator 0:bb348c97df44 724 /**
lypinator 0:bb348c97df44 725 * @brief Get the Peripheral clock frequency.
lypinator 0:bb348c97df44 726 * @rmtoll CR2 FREQ LL_I2C_GetPeriphClock
lypinator 0:bb348c97df44 727 * @param I2Cx I2C Instance.
lypinator 0:bb348c97df44 728 * @retval Value of Peripheral Clock (in Hz)
lypinator 0:bb348c97df44 729 */
lypinator 0:bb348c97df44 730 __STATIC_INLINE uint32_t LL_I2C_GetPeriphClock(I2C_TypeDef *I2Cx)
lypinator 0:bb348c97df44 731 {
lypinator 0:bb348c97df44 732 return (uint32_t)(__LL_I2C_FREQ_MHZ_TO_HZ(READ_BIT(I2Cx->CR2, I2C_CR2_FREQ)));
lypinator 0:bb348c97df44 733 }
lypinator 0:bb348c97df44 734
lypinator 0:bb348c97df44 735 /**
lypinator 0:bb348c97df44 736 * @brief Configure the Duty cycle (Fast mode only).
lypinator 0:bb348c97df44 737 * @rmtoll CCR DUTY LL_I2C_SetDutyCycle
lypinator 0:bb348c97df44 738 * @param I2Cx I2C Instance.
lypinator 0:bb348c97df44 739 * @param DutyCycle This parameter can be one of the following values:
lypinator 0:bb348c97df44 740 * @arg @ref LL_I2C_DUTYCYCLE_2
lypinator 0:bb348c97df44 741 * @arg @ref LL_I2C_DUTYCYCLE_16_9
lypinator 0:bb348c97df44 742 * @retval None
lypinator 0:bb348c97df44 743 */
lypinator 0:bb348c97df44 744 __STATIC_INLINE void LL_I2C_SetDutyCycle(I2C_TypeDef *I2Cx, uint32_t DutyCycle)
lypinator 0:bb348c97df44 745 {
lypinator 0:bb348c97df44 746 MODIFY_REG(I2Cx->CCR, I2C_CCR_DUTY, DutyCycle);
lypinator 0:bb348c97df44 747 }
lypinator 0:bb348c97df44 748
lypinator 0:bb348c97df44 749 /**
lypinator 0:bb348c97df44 750 * @brief Get the Duty cycle (Fast mode only).
lypinator 0:bb348c97df44 751 * @rmtoll CCR DUTY LL_I2C_GetDutyCycle
lypinator 0:bb348c97df44 752 * @param I2Cx I2C Instance.
lypinator 0:bb348c97df44 753 * @retval Returned value can be one of the following values:
lypinator 0:bb348c97df44 754 * @arg @ref LL_I2C_DUTYCYCLE_2
lypinator 0:bb348c97df44 755 * @arg @ref LL_I2C_DUTYCYCLE_16_9
lypinator 0:bb348c97df44 756 */
lypinator 0:bb348c97df44 757 __STATIC_INLINE uint32_t LL_I2C_GetDutyCycle(I2C_TypeDef *I2Cx)
lypinator 0:bb348c97df44 758 {
lypinator 0:bb348c97df44 759 return (uint32_t)(READ_BIT(I2Cx->CCR, I2C_CCR_DUTY));
lypinator 0:bb348c97df44 760 }
lypinator 0:bb348c97df44 761
lypinator 0:bb348c97df44 762 /**
lypinator 0:bb348c97df44 763 * @brief Configure the I2C master clock speed mode.
lypinator 0:bb348c97df44 764 * @rmtoll CCR FS LL_I2C_SetClockSpeedMode
lypinator 0:bb348c97df44 765 * @param I2Cx I2C Instance.
lypinator 0:bb348c97df44 766 * @param ClockSpeedMode This parameter can be one of the following values:
lypinator 0:bb348c97df44 767 * @arg @ref LL_I2C_CLOCK_SPEED_STANDARD_MODE
lypinator 0:bb348c97df44 768 * @arg @ref LL_I2C_CLOCK_SPEED_FAST_MODE
lypinator 0:bb348c97df44 769 * @retval None
lypinator 0:bb348c97df44 770 */
lypinator 0:bb348c97df44 771 __STATIC_INLINE void LL_I2C_SetClockSpeedMode(I2C_TypeDef *I2Cx, uint32_t ClockSpeedMode)
lypinator 0:bb348c97df44 772 {
lypinator 0:bb348c97df44 773 MODIFY_REG(I2Cx->CCR, I2C_CCR_FS, ClockSpeedMode);
lypinator 0:bb348c97df44 774 }
lypinator 0:bb348c97df44 775
lypinator 0:bb348c97df44 776 /**
lypinator 0:bb348c97df44 777 * @brief Get the the I2C master speed mode.
lypinator 0:bb348c97df44 778 * @rmtoll CCR FS LL_I2C_GetClockSpeedMode
lypinator 0:bb348c97df44 779 * @param I2Cx I2C Instance.
lypinator 0:bb348c97df44 780 * @retval Returned value can be one of the following values:
lypinator 0:bb348c97df44 781 * @arg @ref LL_I2C_CLOCK_SPEED_STANDARD_MODE
lypinator 0:bb348c97df44 782 * @arg @ref LL_I2C_CLOCK_SPEED_FAST_MODE
lypinator 0:bb348c97df44 783 */
lypinator 0:bb348c97df44 784 __STATIC_INLINE uint32_t LL_I2C_GetClockSpeedMode(I2C_TypeDef *I2Cx)
lypinator 0:bb348c97df44 785 {
lypinator 0:bb348c97df44 786 return (uint32_t)(READ_BIT(I2Cx->CCR, I2C_CCR_FS));
lypinator 0:bb348c97df44 787 }
lypinator 0:bb348c97df44 788
lypinator 0:bb348c97df44 789 /**
lypinator 0:bb348c97df44 790 * @brief Configure the SCL, SDA rising time.
lypinator 0:bb348c97df44 791 * @note This bit can only be programmed when the I2C is disabled (PE = 0).
lypinator 0:bb348c97df44 792 * @rmtoll TRISE TRISE LL_I2C_SetRiseTime
lypinator 0:bb348c97df44 793 * @param I2Cx I2C Instance.
lypinator 0:bb348c97df44 794 * @param RiseTime This parameter must be a value between Min_Data=0x02 and Max_Data=0x3F.
lypinator 0:bb348c97df44 795 * @retval None
lypinator 0:bb348c97df44 796 */
lypinator 0:bb348c97df44 797 __STATIC_INLINE void LL_I2C_SetRiseTime(I2C_TypeDef *I2Cx, uint32_t RiseTime)
lypinator 0:bb348c97df44 798 {
lypinator 0:bb348c97df44 799 MODIFY_REG(I2Cx->TRISE, I2C_TRISE_TRISE, RiseTime);
lypinator 0:bb348c97df44 800 }
lypinator 0:bb348c97df44 801
lypinator 0:bb348c97df44 802 /**
lypinator 0:bb348c97df44 803 * @brief Get the SCL, SDA rising time.
lypinator 0:bb348c97df44 804 * @rmtoll TRISE TRISE LL_I2C_GetRiseTime
lypinator 0:bb348c97df44 805 * @param I2Cx I2C Instance.
lypinator 0:bb348c97df44 806 * @retval Value between Min_Data=0x02 and Max_Data=0x3F
lypinator 0:bb348c97df44 807 */
lypinator 0:bb348c97df44 808 __STATIC_INLINE uint32_t LL_I2C_GetRiseTime(I2C_TypeDef *I2Cx)
lypinator 0:bb348c97df44 809 {
lypinator 0:bb348c97df44 810 return (uint32_t)(READ_BIT(I2Cx->TRISE, I2C_TRISE_TRISE));
lypinator 0:bb348c97df44 811 }
lypinator 0:bb348c97df44 812
lypinator 0:bb348c97df44 813 /**
lypinator 0:bb348c97df44 814 * @brief Configure the SCL high and low period.
lypinator 0:bb348c97df44 815 * @note This bit can only be programmed when the I2C is disabled (PE = 0).
lypinator 0:bb348c97df44 816 * @rmtoll CCR CCR LL_I2C_SetClockPeriod
lypinator 0:bb348c97df44 817 * @param I2Cx I2C Instance.
lypinator 0:bb348c97df44 818 * @param ClockPeriod This parameter must be a value between Min_Data=0x004 and Max_Data=0xFFF, except in FAST DUTY mode where Min_Data=0x001.
lypinator 0:bb348c97df44 819 * @retval None
lypinator 0:bb348c97df44 820 */
lypinator 0:bb348c97df44 821 __STATIC_INLINE void LL_I2C_SetClockPeriod(I2C_TypeDef *I2Cx, uint32_t ClockPeriod)
lypinator 0:bb348c97df44 822 {
lypinator 0:bb348c97df44 823 MODIFY_REG(I2Cx->CCR, I2C_CCR_CCR, ClockPeriod);
lypinator 0:bb348c97df44 824 }
lypinator 0:bb348c97df44 825
lypinator 0:bb348c97df44 826 /**
lypinator 0:bb348c97df44 827 * @brief Get the SCL high and low period.
lypinator 0:bb348c97df44 828 * @rmtoll CCR CCR LL_I2C_GetClockPeriod
lypinator 0:bb348c97df44 829 * @param I2Cx I2C Instance.
lypinator 0:bb348c97df44 830 * @retval Value between Min_Data=0x004 and Max_Data=0xFFF, except in FAST DUTY mode where Min_Data=0x001.
lypinator 0:bb348c97df44 831 */
lypinator 0:bb348c97df44 832 __STATIC_INLINE uint32_t LL_I2C_GetClockPeriod(I2C_TypeDef *I2Cx)
lypinator 0:bb348c97df44 833 {
lypinator 0:bb348c97df44 834 return (uint32_t)(READ_BIT(I2Cx->CCR, I2C_CCR_CCR));
lypinator 0:bb348c97df44 835 }
lypinator 0:bb348c97df44 836
lypinator 0:bb348c97df44 837 /**
lypinator 0:bb348c97df44 838 * @brief Configure the SCL speed.
lypinator 0:bb348c97df44 839 * @note This bit can only be programmed when the I2C is disabled (PE = 0).
lypinator 0:bb348c97df44 840 * @rmtoll CR2 FREQ LL_I2C_ConfigSpeed\n
lypinator 0:bb348c97df44 841 * TRISE TRISE LL_I2C_ConfigSpeed\n
lypinator 0:bb348c97df44 842 * CCR FS LL_I2C_ConfigSpeed\n
lypinator 0:bb348c97df44 843 * CCR DUTY LL_I2C_ConfigSpeed\n
lypinator 0:bb348c97df44 844 * CCR CCR LL_I2C_ConfigSpeed
lypinator 0:bb348c97df44 845 * @param I2Cx I2C Instance.
lypinator 0:bb348c97df44 846 * @param PeriphClock Peripheral Clock (in Hz)
lypinator 0:bb348c97df44 847 * @param ClockSpeed This parameter must be a value lower than 400kHz (in Hz).
lypinator 0:bb348c97df44 848 * @param DutyCycle This parameter can be one of the following values:
lypinator 0:bb348c97df44 849 * @arg @ref LL_I2C_DUTYCYCLE_2
lypinator 0:bb348c97df44 850 * @arg @ref LL_I2C_DUTYCYCLE_16_9
lypinator 0:bb348c97df44 851 * @retval None
lypinator 0:bb348c97df44 852 */
lypinator 0:bb348c97df44 853 __STATIC_INLINE void LL_I2C_ConfigSpeed(I2C_TypeDef *I2Cx, uint32_t PeriphClock, uint32_t ClockSpeed,
lypinator 0:bb348c97df44 854 uint32_t DutyCycle)
lypinator 0:bb348c97df44 855 {
lypinator 0:bb348c97df44 856 register uint32_t freqrange = 0x0U;
lypinator 0:bb348c97df44 857 register uint32_t clockconfig = 0x0U;
lypinator 0:bb348c97df44 858
lypinator 0:bb348c97df44 859 /* Compute frequency range */
lypinator 0:bb348c97df44 860 freqrange = __LL_I2C_FREQ_HZ_TO_MHZ(PeriphClock);
lypinator 0:bb348c97df44 861
lypinator 0:bb348c97df44 862 /* Configure I2Cx: Frequency range register */
lypinator 0:bb348c97df44 863 MODIFY_REG(I2Cx->CR2, I2C_CR2_FREQ, freqrange);
lypinator 0:bb348c97df44 864
lypinator 0:bb348c97df44 865 /* Configure I2Cx: Rise Time register */
lypinator 0:bb348c97df44 866 MODIFY_REG(I2Cx->TRISE, I2C_TRISE_TRISE, __LL_I2C_RISE_TIME(freqrange, ClockSpeed));
lypinator 0:bb348c97df44 867
lypinator 0:bb348c97df44 868 /* Configure Speed mode, Duty Cycle and Clock control register value */
lypinator 0:bb348c97df44 869 if (ClockSpeed > LL_I2C_MAX_SPEED_STANDARD)
lypinator 0:bb348c97df44 870 {
lypinator 0:bb348c97df44 871 /* Set Speed mode at fast and duty cycle for Clock Speed request in fast clock range */
lypinator 0:bb348c97df44 872 clockconfig = LL_I2C_CLOCK_SPEED_FAST_MODE | \
lypinator 0:bb348c97df44 873 __LL_I2C_SPEED_FAST_TO_CCR(PeriphClock, ClockSpeed, DutyCycle) | \
lypinator 0:bb348c97df44 874 DutyCycle;
lypinator 0:bb348c97df44 875 }
lypinator 0:bb348c97df44 876 else
lypinator 0:bb348c97df44 877 {
lypinator 0:bb348c97df44 878 /* Set Speed mode at standard for Clock Speed request in standard clock range */
lypinator 0:bb348c97df44 879 clockconfig = LL_I2C_CLOCK_SPEED_STANDARD_MODE | \
lypinator 0:bb348c97df44 880 __LL_I2C_SPEED_STANDARD_TO_CCR(PeriphClock, ClockSpeed);
lypinator 0:bb348c97df44 881 }
lypinator 0:bb348c97df44 882
lypinator 0:bb348c97df44 883 /* Configure I2Cx: Clock control register */
lypinator 0:bb348c97df44 884 MODIFY_REG(I2Cx->CCR, (I2C_CCR_FS | I2C_CCR_DUTY | I2C_CCR_CCR), clockconfig);
lypinator 0:bb348c97df44 885 }
lypinator 0:bb348c97df44 886
lypinator 0:bb348c97df44 887 /**
lypinator 0:bb348c97df44 888 * @brief Configure peripheral mode.
lypinator 0:bb348c97df44 889 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
lypinator 0:bb348c97df44 890 * SMBus feature is supported by the I2Cx Instance.
lypinator 0:bb348c97df44 891 * @rmtoll CR1 SMBUS LL_I2C_SetMode\n
lypinator 0:bb348c97df44 892 * CR1 SMBTYPE LL_I2C_SetMode\n
lypinator 0:bb348c97df44 893 * CR1 ENARP LL_I2C_SetMode
lypinator 0:bb348c97df44 894 * @param I2Cx I2C Instance.
lypinator 0:bb348c97df44 895 * @param PeripheralMode This parameter can be one of the following values:
lypinator 0:bb348c97df44 896 * @arg @ref LL_I2C_MODE_I2C
lypinator 0:bb348c97df44 897 * @arg @ref LL_I2C_MODE_SMBUS_HOST
lypinator 0:bb348c97df44 898 * @arg @ref LL_I2C_MODE_SMBUS_DEVICE
lypinator 0:bb348c97df44 899 * @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
lypinator 0:bb348c97df44 900 * @retval None
lypinator 0:bb348c97df44 901 */
lypinator 0:bb348c97df44 902 __STATIC_INLINE void LL_I2C_SetMode(I2C_TypeDef *I2Cx, uint32_t PeripheralMode)
lypinator 0:bb348c97df44 903 {
lypinator 0:bb348c97df44 904 MODIFY_REG(I2Cx->CR1, I2C_CR1_SMBUS | I2C_CR1_SMBTYPE | I2C_CR1_ENARP, PeripheralMode);
lypinator 0:bb348c97df44 905 }
lypinator 0:bb348c97df44 906
lypinator 0:bb348c97df44 907 /**
lypinator 0:bb348c97df44 908 * @brief Get peripheral mode.
lypinator 0:bb348c97df44 909 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
lypinator 0:bb348c97df44 910 * SMBus feature is supported by the I2Cx Instance.
lypinator 0:bb348c97df44 911 * @rmtoll CR1 SMBUS LL_I2C_GetMode\n
lypinator 0:bb348c97df44 912 * CR1 SMBTYPE LL_I2C_GetMode\n
lypinator 0:bb348c97df44 913 * CR1 ENARP LL_I2C_GetMode
lypinator 0:bb348c97df44 914 * @param I2Cx I2C Instance.
lypinator 0:bb348c97df44 915 * @retval Returned value can be one of the following values:
lypinator 0:bb348c97df44 916 * @arg @ref LL_I2C_MODE_I2C
lypinator 0:bb348c97df44 917 * @arg @ref LL_I2C_MODE_SMBUS_HOST
lypinator 0:bb348c97df44 918 * @arg @ref LL_I2C_MODE_SMBUS_DEVICE
lypinator 0:bb348c97df44 919 * @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
lypinator 0:bb348c97df44 920 */
lypinator 0:bb348c97df44 921 __STATIC_INLINE uint32_t LL_I2C_GetMode(I2C_TypeDef *I2Cx)
lypinator 0:bb348c97df44 922 {
lypinator 0:bb348c97df44 923 return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_SMBUS | I2C_CR1_SMBTYPE | I2C_CR1_ENARP));
lypinator 0:bb348c97df44 924 }
lypinator 0:bb348c97df44 925
lypinator 0:bb348c97df44 926 /**
lypinator 0:bb348c97df44 927 * @brief Enable SMBus alert (Host or Device mode)
lypinator 0:bb348c97df44 928 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
lypinator 0:bb348c97df44 929 * SMBus feature is supported by the I2Cx Instance.
lypinator 0:bb348c97df44 930 * @note SMBus Device mode:
lypinator 0:bb348c97df44 931 * - SMBus Alert pin is drived low and
lypinator 0:bb348c97df44 932 * Alert Response Address Header acknowledge is enabled.
lypinator 0:bb348c97df44 933 * SMBus Host mode:
lypinator 0:bb348c97df44 934 * - SMBus Alert pin management is supported.
lypinator 0:bb348c97df44 935 * @rmtoll CR1 ALERT LL_I2C_EnableSMBusAlert
lypinator 0:bb348c97df44 936 * @param I2Cx I2C Instance.
lypinator 0:bb348c97df44 937 * @retval None
lypinator 0:bb348c97df44 938 */
lypinator 0:bb348c97df44 939 __STATIC_INLINE void LL_I2C_EnableSMBusAlert(I2C_TypeDef *I2Cx)
lypinator 0:bb348c97df44 940 {
lypinator 0:bb348c97df44 941 SET_BIT(I2Cx->CR1, I2C_CR1_ALERT);
lypinator 0:bb348c97df44 942 }
lypinator 0:bb348c97df44 943
lypinator 0:bb348c97df44 944 /**
lypinator 0:bb348c97df44 945 * @brief Disable SMBus alert (Host or Device mode)
lypinator 0:bb348c97df44 946 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
lypinator 0:bb348c97df44 947 * SMBus feature is supported by the I2Cx Instance.
lypinator 0:bb348c97df44 948 * @note SMBus Device mode:
lypinator 0:bb348c97df44 949 * - SMBus Alert pin is not drived (can be used as a standard GPIO) and
lypinator 0:bb348c97df44 950 * Alert Response Address Header acknowledge is disabled.
lypinator 0:bb348c97df44 951 * SMBus Host mode:
lypinator 0:bb348c97df44 952 * - SMBus Alert pin management is not supported.
lypinator 0:bb348c97df44 953 * @rmtoll CR1 ALERT LL_I2C_DisableSMBusAlert
lypinator 0:bb348c97df44 954 * @param I2Cx I2C Instance.
lypinator 0:bb348c97df44 955 * @retval None
lypinator 0:bb348c97df44 956 */
lypinator 0:bb348c97df44 957 __STATIC_INLINE void LL_I2C_DisableSMBusAlert(I2C_TypeDef *I2Cx)
lypinator 0:bb348c97df44 958 {
lypinator 0:bb348c97df44 959 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ALERT);
lypinator 0:bb348c97df44 960 }
lypinator 0:bb348c97df44 961
lypinator 0:bb348c97df44 962 /**
lypinator 0:bb348c97df44 963 * @brief Check if SMBus alert (Host or Device mode) is enabled or disabled.
lypinator 0:bb348c97df44 964 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
lypinator 0:bb348c97df44 965 * SMBus feature is supported by the I2Cx Instance.
lypinator 0:bb348c97df44 966 * @rmtoll CR1 ALERT LL_I2C_IsEnabledSMBusAlert
lypinator 0:bb348c97df44 967 * @param I2Cx I2C Instance.
lypinator 0:bb348c97df44 968 * @retval State of bit (1 or 0).
lypinator 0:bb348c97df44 969 */
lypinator 0:bb348c97df44 970 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(I2C_TypeDef *I2Cx)
lypinator 0:bb348c97df44 971 {
lypinator 0:bb348c97df44 972 return (READ_BIT(I2Cx->CR1, I2C_CR1_ALERT) == (I2C_CR1_ALERT));
lypinator 0:bb348c97df44 973 }
lypinator 0:bb348c97df44 974
lypinator 0:bb348c97df44 975 /**
lypinator 0:bb348c97df44 976 * @brief Enable SMBus Packet Error Calculation (PEC).
lypinator 0:bb348c97df44 977 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
lypinator 0:bb348c97df44 978 * SMBus feature is supported by the I2Cx Instance.
lypinator 0:bb348c97df44 979 * @rmtoll CR1 ENPEC LL_I2C_EnableSMBusPEC
lypinator 0:bb348c97df44 980 * @param I2Cx I2C Instance.
lypinator 0:bb348c97df44 981 * @retval None
lypinator 0:bb348c97df44 982 */
lypinator 0:bb348c97df44 983 __STATIC_INLINE void LL_I2C_EnableSMBusPEC(I2C_TypeDef *I2Cx)
lypinator 0:bb348c97df44 984 {
lypinator 0:bb348c97df44 985 SET_BIT(I2Cx->CR1, I2C_CR1_ENPEC);
lypinator 0:bb348c97df44 986 }
lypinator 0:bb348c97df44 987
lypinator 0:bb348c97df44 988 /**
lypinator 0:bb348c97df44 989 * @brief Disable SMBus Packet Error Calculation (PEC).
lypinator 0:bb348c97df44 990 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
lypinator 0:bb348c97df44 991 * SMBus feature is supported by the I2Cx Instance.
lypinator 0:bb348c97df44 992 * @rmtoll CR1 ENPEC LL_I2C_DisableSMBusPEC
lypinator 0:bb348c97df44 993 * @param I2Cx I2C Instance.
lypinator 0:bb348c97df44 994 * @retval None
lypinator 0:bb348c97df44 995 */
lypinator 0:bb348c97df44 996 __STATIC_INLINE void LL_I2C_DisableSMBusPEC(I2C_TypeDef *I2Cx)
lypinator 0:bb348c97df44 997 {
lypinator 0:bb348c97df44 998 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ENPEC);
lypinator 0:bb348c97df44 999 }
lypinator 0:bb348c97df44 1000
lypinator 0:bb348c97df44 1001 /**
lypinator 0:bb348c97df44 1002 * @brief Check if SMBus Packet Error Calculation (PEC) is enabled or disabled.
lypinator 0:bb348c97df44 1003 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
lypinator 0:bb348c97df44 1004 * SMBus feature is supported by the I2Cx Instance.
lypinator 0:bb348c97df44 1005 * @rmtoll CR1 ENPEC LL_I2C_IsEnabledSMBusPEC
lypinator 0:bb348c97df44 1006 * @param I2Cx I2C Instance.
lypinator 0:bb348c97df44 1007 * @retval State of bit (1 or 0).
lypinator 0:bb348c97df44 1008 */
lypinator 0:bb348c97df44 1009 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(I2C_TypeDef *I2Cx)
lypinator 0:bb348c97df44 1010 {
lypinator 0:bb348c97df44 1011 return (READ_BIT(I2Cx->CR1, I2C_CR1_ENPEC) == (I2C_CR1_ENPEC));
lypinator 0:bb348c97df44 1012 }
lypinator 0:bb348c97df44 1013
lypinator 0:bb348c97df44 1014 /**
lypinator 0:bb348c97df44 1015 * @}
lypinator 0:bb348c97df44 1016 */
lypinator 0:bb348c97df44 1017
lypinator 0:bb348c97df44 1018 /** @defgroup I2C_LL_EF_IT_Management IT_Management
lypinator 0:bb348c97df44 1019 * @{
lypinator 0:bb348c97df44 1020 */
lypinator 0:bb348c97df44 1021
lypinator 0:bb348c97df44 1022 /**
lypinator 0:bb348c97df44 1023 * @brief Enable TXE interrupt.
lypinator 0:bb348c97df44 1024 * @rmtoll CR2 ITEVTEN LL_I2C_EnableIT_TX\n
lypinator 0:bb348c97df44 1025 * CR2 ITBUFEN LL_I2C_EnableIT_TX
lypinator 0:bb348c97df44 1026 * @param I2Cx I2C Instance.
lypinator 0:bb348c97df44 1027 * @retval None
lypinator 0:bb348c97df44 1028 */
lypinator 0:bb348c97df44 1029 __STATIC_INLINE void LL_I2C_EnableIT_TX(I2C_TypeDef *I2Cx)
lypinator 0:bb348c97df44 1030 {
lypinator 0:bb348c97df44 1031 SET_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN);
lypinator 0:bb348c97df44 1032 }
lypinator 0:bb348c97df44 1033
lypinator 0:bb348c97df44 1034 /**
lypinator 0:bb348c97df44 1035 * @brief Disable TXE interrupt.
lypinator 0:bb348c97df44 1036 * @rmtoll CR2 ITEVTEN LL_I2C_DisableIT_TX\n
lypinator 0:bb348c97df44 1037 * CR2 ITBUFEN LL_I2C_DisableIT_TX
lypinator 0:bb348c97df44 1038 * @param I2Cx I2C Instance.
lypinator 0:bb348c97df44 1039 * @retval None
lypinator 0:bb348c97df44 1040 */
lypinator 0:bb348c97df44 1041 __STATIC_INLINE void LL_I2C_DisableIT_TX(I2C_TypeDef *I2Cx)
lypinator 0:bb348c97df44 1042 {
lypinator 0:bb348c97df44 1043 CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN);
lypinator 0:bb348c97df44 1044 }
lypinator 0:bb348c97df44 1045
lypinator 0:bb348c97df44 1046 /**
lypinator 0:bb348c97df44 1047 * @brief Check if the TXE Interrupt is enabled or disabled.
lypinator 0:bb348c97df44 1048 * @rmtoll CR2 ITEVTEN LL_I2C_IsEnabledIT_TX\n
lypinator 0:bb348c97df44 1049 * CR2 ITBUFEN LL_I2C_IsEnabledIT_TX
lypinator 0:bb348c97df44 1050 * @param I2Cx I2C Instance.
lypinator 0:bb348c97df44 1051 * @retval State of bit (1 or 0).
lypinator 0:bb348c97df44 1052 */
lypinator 0:bb348c97df44 1053 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(I2C_TypeDef *I2Cx)
lypinator 0:bb348c97df44 1054 {
lypinator 0:bb348c97df44 1055 return (READ_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN) == (I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN));
lypinator 0:bb348c97df44 1056 }
lypinator 0:bb348c97df44 1057
lypinator 0:bb348c97df44 1058 /**
lypinator 0:bb348c97df44 1059 * @brief Enable RXNE interrupt.
lypinator 0:bb348c97df44 1060 * @rmtoll CR2 ITEVTEN LL_I2C_EnableIT_RX\n
lypinator 0:bb348c97df44 1061 * CR2 ITBUFEN LL_I2C_EnableIT_RX
lypinator 0:bb348c97df44 1062 * @param I2Cx I2C Instance.
lypinator 0:bb348c97df44 1063 * @retval None
lypinator 0:bb348c97df44 1064 */
lypinator 0:bb348c97df44 1065 __STATIC_INLINE void LL_I2C_EnableIT_RX(I2C_TypeDef *I2Cx)
lypinator 0:bb348c97df44 1066 {
lypinator 0:bb348c97df44 1067 SET_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN);
lypinator 0:bb348c97df44 1068 }
lypinator 0:bb348c97df44 1069
lypinator 0:bb348c97df44 1070 /**
lypinator 0:bb348c97df44 1071 * @brief Disable RXNE interrupt.
lypinator 0:bb348c97df44 1072 * @rmtoll CR2 ITEVTEN LL_I2C_DisableIT_RX\n
lypinator 0:bb348c97df44 1073 * CR2 ITBUFEN LL_I2C_DisableIT_RX
lypinator 0:bb348c97df44 1074 * @param I2Cx I2C Instance.
lypinator 0:bb348c97df44 1075 * @retval None
lypinator 0:bb348c97df44 1076 */
lypinator 0:bb348c97df44 1077 __STATIC_INLINE void LL_I2C_DisableIT_RX(I2C_TypeDef *I2Cx)
lypinator 0:bb348c97df44 1078 {
lypinator 0:bb348c97df44 1079 CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN);
lypinator 0:bb348c97df44 1080 }
lypinator 0:bb348c97df44 1081
lypinator 0:bb348c97df44 1082 /**
lypinator 0:bb348c97df44 1083 * @brief Check if the RXNE Interrupt is enabled or disabled.
lypinator 0:bb348c97df44 1084 * @rmtoll CR2 ITEVTEN LL_I2C_IsEnabledIT_RX\n
lypinator 0:bb348c97df44 1085 * CR2 ITBUFEN LL_I2C_IsEnabledIT_RX
lypinator 0:bb348c97df44 1086 * @param I2Cx I2C Instance.
lypinator 0:bb348c97df44 1087 * @retval State of bit (1 or 0).
lypinator 0:bb348c97df44 1088 */
lypinator 0:bb348c97df44 1089 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(I2C_TypeDef *I2Cx)
lypinator 0:bb348c97df44 1090 {
lypinator 0:bb348c97df44 1091 return (READ_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN) == (I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN));
lypinator 0:bb348c97df44 1092 }
lypinator 0:bb348c97df44 1093
lypinator 0:bb348c97df44 1094 /**
lypinator 0:bb348c97df44 1095 * @brief Enable Events interrupts.
lypinator 0:bb348c97df44 1096 * @note Any of these events will generate interrupt :
lypinator 0:bb348c97df44 1097 * Start Bit (SB)
lypinator 0:bb348c97df44 1098 * Address sent, Address matched (ADDR)
lypinator 0:bb348c97df44 1099 * 10-bit header sent (ADD10)
lypinator 0:bb348c97df44 1100 * Stop detection (STOPF)
lypinator 0:bb348c97df44 1101 * Byte transfer finished (BTF)
lypinator 0:bb348c97df44 1102 *
lypinator 0:bb348c97df44 1103 * @note Any of these events will generate interrupt if Buffer interrupts are enabled too(using unitary function @ref LL_I2C_EnableIT_BUF()) :
lypinator 0:bb348c97df44 1104 * Receive buffer not empty (RXNE)
lypinator 0:bb348c97df44 1105 * Transmit buffer empty (TXE)
lypinator 0:bb348c97df44 1106 * @rmtoll CR2 ITEVTEN LL_I2C_EnableIT_EVT
lypinator 0:bb348c97df44 1107 * @param I2Cx I2C Instance.
lypinator 0:bb348c97df44 1108 * @retval None
lypinator 0:bb348c97df44 1109 */
lypinator 0:bb348c97df44 1110 __STATIC_INLINE void LL_I2C_EnableIT_EVT(I2C_TypeDef *I2Cx)
lypinator 0:bb348c97df44 1111 {
lypinator 0:bb348c97df44 1112 SET_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN);
lypinator 0:bb348c97df44 1113 }
lypinator 0:bb348c97df44 1114
lypinator 0:bb348c97df44 1115 /**
lypinator 0:bb348c97df44 1116 * @brief Disable Events interrupts.
lypinator 0:bb348c97df44 1117 * @note Any of these events will generate interrupt :
lypinator 0:bb348c97df44 1118 * Start Bit (SB)
lypinator 0:bb348c97df44 1119 * Address sent, Address matched (ADDR)
lypinator 0:bb348c97df44 1120 * 10-bit header sent (ADD10)
lypinator 0:bb348c97df44 1121 * Stop detection (STOPF)
lypinator 0:bb348c97df44 1122 * Byte transfer finished (BTF)
lypinator 0:bb348c97df44 1123 * Receive buffer not empty (RXNE)
lypinator 0:bb348c97df44 1124 * Transmit buffer empty (TXE)
lypinator 0:bb348c97df44 1125 * @rmtoll CR2 ITEVTEN LL_I2C_DisableIT_EVT
lypinator 0:bb348c97df44 1126 * @param I2Cx I2C Instance.
lypinator 0:bb348c97df44 1127 * @retval None
lypinator 0:bb348c97df44 1128 */
lypinator 0:bb348c97df44 1129 __STATIC_INLINE void LL_I2C_DisableIT_EVT(I2C_TypeDef *I2Cx)
lypinator 0:bb348c97df44 1130 {
lypinator 0:bb348c97df44 1131 CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN);
lypinator 0:bb348c97df44 1132 }
lypinator 0:bb348c97df44 1133
lypinator 0:bb348c97df44 1134 /**
lypinator 0:bb348c97df44 1135 * @brief Check if Events interrupts are enabled or disabled.
lypinator 0:bb348c97df44 1136 * @rmtoll CR2 ITEVTEN LL_I2C_IsEnabledIT_EVT
lypinator 0:bb348c97df44 1137 * @param I2Cx I2C Instance.
lypinator 0:bb348c97df44 1138 * @retval State of bit (1 or 0).
lypinator 0:bb348c97df44 1139 */
lypinator 0:bb348c97df44 1140 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_EVT(I2C_TypeDef *I2Cx)
lypinator 0:bb348c97df44 1141 {
lypinator 0:bb348c97df44 1142 return (READ_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN) == (I2C_CR2_ITEVTEN));
lypinator 0:bb348c97df44 1143 }
lypinator 0:bb348c97df44 1144
lypinator 0:bb348c97df44 1145 /**
lypinator 0:bb348c97df44 1146 * @brief Enable Buffer interrupts.
lypinator 0:bb348c97df44 1147 * @note Any of these Buffer events will generate interrupt if Events interrupts are enabled too(using unitary function @ref LL_I2C_EnableIT_EVT()) :
lypinator 0:bb348c97df44 1148 * Receive buffer not empty (RXNE)
lypinator 0:bb348c97df44 1149 * Transmit buffer empty (TXE)
lypinator 0:bb348c97df44 1150 * @rmtoll CR2 ITBUFEN LL_I2C_EnableIT_BUF
lypinator 0:bb348c97df44 1151 * @param I2Cx I2C Instance.
lypinator 0:bb348c97df44 1152 * @retval None
lypinator 0:bb348c97df44 1153 */
lypinator 0:bb348c97df44 1154 __STATIC_INLINE void LL_I2C_EnableIT_BUF(I2C_TypeDef *I2Cx)
lypinator 0:bb348c97df44 1155 {
lypinator 0:bb348c97df44 1156 SET_BIT(I2Cx->CR2, I2C_CR2_ITBUFEN);
lypinator 0:bb348c97df44 1157 }
lypinator 0:bb348c97df44 1158
lypinator 0:bb348c97df44 1159 /**
lypinator 0:bb348c97df44 1160 * @brief Disable Buffer interrupts.
lypinator 0:bb348c97df44 1161 * @note Any of these Buffer events will generate interrupt :
lypinator 0:bb348c97df44 1162 * Receive buffer not empty (RXNE)
lypinator 0:bb348c97df44 1163 * Transmit buffer empty (TXE)
lypinator 0:bb348c97df44 1164 * @rmtoll CR2 ITBUFEN LL_I2C_DisableIT_BUF
lypinator 0:bb348c97df44 1165 * @param I2Cx I2C Instance.
lypinator 0:bb348c97df44 1166 * @retval None
lypinator 0:bb348c97df44 1167 */
lypinator 0:bb348c97df44 1168 __STATIC_INLINE void LL_I2C_DisableIT_BUF(I2C_TypeDef *I2Cx)
lypinator 0:bb348c97df44 1169 {
lypinator 0:bb348c97df44 1170 CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITBUFEN);
lypinator 0:bb348c97df44 1171 }
lypinator 0:bb348c97df44 1172
lypinator 0:bb348c97df44 1173 /**
lypinator 0:bb348c97df44 1174 * @brief Check if Buffer interrupts are enabled or disabled.
lypinator 0:bb348c97df44 1175 * @rmtoll CR2 ITBUFEN LL_I2C_IsEnabledIT_BUF
lypinator 0:bb348c97df44 1176 * @param I2Cx I2C Instance.
lypinator 0:bb348c97df44 1177 * @retval State of bit (1 or 0).
lypinator 0:bb348c97df44 1178 */
lypinator 0:bb348c97df44 1179 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_BUF(I2C_TypeDef *I2Cx)
lypinator 0:bb348c97df44 1180 {
lypinator 0:bb348c97df44 1181 return (READ_BIT(I2Cx->CR2, I2C_CR2_ITBUFEN) == (I2C_CR2_ITBUFEN));
lypinator 0:bb348c97df44 1182 }
lypinator 0:bb348c97df44 1183
lypinator 0:bb348c97df44 1184 /**
lypinator 0:bb348c97df44 1185 * @brief Enable Error interrupts.
lypinator 0:bb348c97df44 1186 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
lypinator 0:bb348c97df44 1187 * SMBus feature is supported by the I2Cx Instance.
lypinator 0:bb348c97df44 1188 * @note Any of these errors will generate interrupt :
lypinator 0:bb348c97df44 1189 * Bus Error detection (BERR)
lypinator 0:bb348c97df44 1190 * Arbitration Loss (ARLO)
lypinator 0:bb348c97df44 1191 * Acknowledge Failure(AF)
lypinator 0:bb348c97df44 1192 * Overrun/Underrun (OVR)
lypinator 0:bb348c97df44 1193 * SMBus Timeout detection (TIMEOUT)
lypinator 0:bb348c97df44 1194 * SMBus PEC error detection (PECERR)
lypinator 0:bb348c97df44 1195 * SMBus Alert pin event detection (SMBALERT)
lypinator 0:bb348c97df44 1196 * @rmtoll CR2 ITERREN LL_I2C_EnableIT_ERR
lypinator 0:bb348c97df44 1197 * @param I2Cx I2C Instance.
lypinator 0:bb348c97df44 1198 * @retval None
lypinator 0:bb348c97df44 1199 */
lypinator 0:bb348c97df44 1200 __STATIC_INLINE void LL_I2C_EnableIT_ERR(I2C_TypeDef *I2Cx)
lypinator 0:bb348c97df44 1201 {
lypinator 0:bb348c97df44 1202 SET_BIT(I2Cx->CR2, I2C_CR2_ITERREN);
lypinator 0:bb348c97df44 1203 }
lypinator 0:bb348c97df44 1204
lypinator 0:bb348c97df44 1205 /**
lypinator 0:bb348c97df44 1206 * @brief Disable Error interrupts.
lypinator 0:bb348c97df44 1207 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
lypinator 0:bb348c97df44 1208 * SMBus feature is supported by the I2Cx Instance.
lypinator 0:bb348c97df44 1209 * @note Any of these errors will generate interrupt :
lypinator 0:bb348c97df44 1210 * Bus Error detection (BERR)
lypinator 0:bb348c97df44 1211 * Arbitration Loss (ARLO)
lypinator 0:bb348c97df44 1212 * Acknowledge Failure(AF)
lypinator 0:bb348c97df44 1213 * Overrun/Underrun (OVR)
lypinator 0:bb348c97df44 1214 * SMBus Timeout detection (TIMEOUT)
lypinator 0:bb348c97df44 1215 * SMBus PEC error detection (PECERR)
lypinator 0:bb348c97df44 1216 * SMBus Alert pin event detection (SMBALERT)
lypinator 0:bb348c97df44 1217 * @rmtoll CR2 ITERREN LL_I2C_DisableIT_ERR
lypinator 0:bb348c97df44 1218 * @param I2Cx I2C Instance.
lypinator 0:bb348c97df44 1219 * @retval None
lypinator 0:bb348c97df44 1220 */
lypinator 0:bb348c97df44 1221 __STATIC_INLINE void LL_I2C_DisableIT_ERR(I2C_TypeDef *I2Cx)
lypinator 0:bb348c97df44 1222 {
lypinator 0:bb348c97df44 1223 CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITERREN);
lypinator 0:bb348c97df44 1224 }
lypinator 0:bb348c97df44 1225
lypinator 0:bb348c97df44 1226 /**
lypinator 0:bb348c97df44 1227 * @brief Check if Error interrupts are enabled or disabled.
lypinator 0:bb348c97df44 1228 * @rmtoll CR2 ITERREN LL_I2C_IsEnabledIT_ERR
lypinator 0:bb348c97df44 1229 * @param I2Cx I2C Instance.
lypinator 0:bb348c97df44 1230 * @retval State of bit (1 or 0).
lypinator 0:bb348c97df44 1231 */
lypinator 0:bb348c97df44 1232 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(I2C_TypeDef *I2Cx)
lypinator 0:bb348c97df44 1233 {
lypinator 0:bb348c97df44 1234 return (READ_BIT(I2Cx->CR2, I2C_CR2_ITERREN) == (I2C_CR2_ITERREN));
lypinator 0:bb348c97df44 1235 }
lypinator 0:bb348c97df44 1236
lypinator 0:bb348c97df44 1237 /**
lypinator 0:bb348c97df44 1238 * @}
lypinator 0:bb348c97df44 1239 */
lypinator 0:bb348c97df44 1240
lypinator 0:bb348c97df44 1241 /** @defgroup I2C_LL_EF_FLAG_management FLAG_management
lypinator 0:bb348c97df44 1242 * @{
lypinator 0:bb348c97df44 1243 */
lypinator 0:bb348c97df44 1244
lypinator 0:bb348c97df44 1245 /**
lypinator 0:bb348c97df44 1246 * @brief Indicate the status of Transmit data register empty flag.
lypinator 0:bb348c97df44 1247 * @note RESET: When next data is written in Transmit data register.
lypinator 0:bb348c97df44 1248 * SET: When Transmit data register is empty.
lypinator 0:bb348c97df44 1249 * @rmtoll SR1 TXE LL_I2C_IsActiveFlag_TXE
lypinator 0:bb348c97df44 1250 * @param I2Cx I2C Instance.
lypinator 0:bb348c97df44 1251 * @retval State of bit (1 or 0).
lypinator 0:bb348c97df44 1252 */
lypinator 0:bb348c97df44 1253 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(I2C_TypeDef *I2Cx)
lypinator 0:bb348c97df44 1254 {
lypinator 0:bb348c97df44 1255 return (READ_BIT(I2Cx->SR1, I2C_SR1_TXE) == (I2C_SR1_TXE));
lypinator 0:bb348c97df44 1256 }
lypinator 0:bb348c97df44 1257
lypinator 0:bb348c97df44 1258 /**
lypinator 0:bb348c97df44 1259 * @brief Indicate the status of Byte Transfer Finished flag.
lypinator 0:bb348c97df44 1260 * RESET: When Data byte transfer not done.
lypinator 0:bb348c97df44 1261 * SET: When Data byte transfer succeeded.
lypinator 0:bb348c97df44 1262 * @rmtoll SR1 BTF LL_I2C_IsActiveFlag_BTF
lypinator 0:bb348c97df44 1263 * @param I2Cx I2C Instance.
lypinator 0:bb348c97df44 1264 * @retval State of bit (1 or 0).
lypinator 0:bb348c97df44 1265 */
lypinator 0:bb348c97df44 1266 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BTF(I2C_TypeDef *I2Cx)
lypinator 0:bb348c97df44 1267 {
lypinator 0:bb348c97df44 1268 return (READ_BIT(I2Cx->SR1, I2C_SR1_BTF) == (I2C_SR1_BTF));
lypinator 0:bb348c97df44 1269 }
lypinator 0:bb348c97df44 1270
lypinator 0:bb348c97df44 1271 /**
lypinator 0:bb348c97df44 1272 * @brief Indicate the status of Receive data register not empty flag.
lypinator 0:bb348c97df44 1273 * @note RESET: When Receive data register is read.
lypinator 0:bb348c97df44 1274 * SET: When the received data is copied in Receive data register.
lypinator 0:bb348c97df44 1275 * @rmtoll SR1 RXNE LL_I2C_IsActiveFlag_RXNE
lypinator 0:bb348c97df44 1276 * @param I2Cx I2C Instance.
lypinator 0:bb348c97df44 1277 * @retval State of bit (1 or 0).
lypinator 0:bb348c97df44 1278 */
lypinator 0:bb348c97df44 1279 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef *I2Cx)
lypinator 0:bb348c97df44 1280 {
lypinator 0:bb348c97df44 1281 return (READ_BIT(I2Cx->SR1, I2C_SR1_RXNE) == (I2C_SR1_RXNE));
lypinator 0:bb348c97df44 1282 }
lypinator 0:bb348c97df44 1283
lypinator 0:bb348c97df44 1284 /**
lypinator 0:bb348c97df44 1285 * @brief Indicate the status of Start Bit (master mode).
lypinator 0:bb348c97df44 1286 * @note RESET: When No Start condition.
lypinator 0:bb348c97df44 1287 * SET: When Start condition is generated.
lypinator 0:bb348c97df44 1288 * @rmtoll SR1 SB LL_I2C_IsActiveFlag_SB
lypinator 0:bb348c97df44 1289 * @param I2Cx I2C Instance.
lypinator 0:bb348c97df44 1290 * @retval State of bit (1 or 0).
lypinator 0:bb348c97df44 1291 */
lypinator 0:bb348c97df44 1292 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_SB(I2C_TypeDef *I2Cx)
lypinator 0:bb348c97df44 1293 {
lypinator 0:bb348c97df44 1294 return (READ_BIT(I2Cx->SR1, I2C_SR1_SB) == (I2C_SR1_SB));
lypinator 0:bb348c97df44 1295 }
lypinator 0:bb348c97df44 1296
lypinator 0:bb348c97df44 1297 /**
lypinator 0:bb348c97df44 1298 * @brief Indicate the status of Address sent (master mode) or Address matched flag (slave mode).
lypinator 0:bb348c97df44 1299 * @note RESET: Clear default value.
lypinator 0:bb348c97df44 1300 * SET: When the address is fully sent (master mode) or when the received slave address matched with one of the enabled slave address (slave mode).
lypinator 0:bb348c97df44 1301 * @rmtoll SR1 ADDR LL_I2C_IsActiveFlag_ADDR
lypinator 0:bb348c97df44 1302 * @param I2Cx I2C Instance.
lypinator 0:bb348c97df44 1303 * @retval State of bit (1 or 0).
lypinator 0:bb348c97df44 1304 */
lypinator 0:bb348c97df44 1305 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx)
lypinator 0:bb348c97df44 1306 {
lypinator 0:bb348c97df44 1307 return (READ_BIT(I2Cx->SR1, I2C_SR1_ADDR) == (I2C_SR1_ADDR));
lypinator 0:bb348c97df44 1308 }
lypinator 0:bb348c97df44 1309
lypinator 0:bb348c97df44 1310 /**
lypinator 0:bb348c97df44 1311 * @brief Indicate the status of 10-bit header sent (master mode).
lypinator 0:bb348c97df44 1312 * @note RESET: When no ADD10 event occured.
lypinator 0:bb348c97df44 1313 * SET: When the master has sent the first address byte (header).
lypinator 0:bb348c97df44 1314 * @rmtoll SR1 ADD10 LL_I2C_IsActiveFlag_ADD10
lypinator 0:bb348c97df44 1315 * @param I2Cx I2C Instance.
lypinator 0:bb348c97df44 1316 * @retval State of bit (1 or 0).
lypinator 0:bb348c97df44 1317 */
lypinator 0:bb348c97df44 1318 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADD10(I2C_TypeDef *I2Cx)
lypinator 0:bb348c97df44 1319 {
lypinator 0:bb348c97df44 1320 return (READ_BIT(I2Cx->SR1, I2C_SR1_ADD10) == (I2C_SR1_ADD10));
lypinator 0:bb348c97df44 1321 }
lypinator 0:bb348c97df44 1322
lypinator 0:bb348c97df44 1323 /**
lypinator 0:bb348c97df44 1324 * @brief Indicate the status of Acknowledge failure flag.
lypinator 0:bb348c97df44 1325 * @note RESET: No acknowledge failure.
lypinator 0:bb348c97df44 1326 * SET: When an acknowledge failure is received after a byte transmission.
lypinator 0:bb348c97df44 1327 * @rmtoll SR1 AF LL_I2C_IsActiveFlag_AF
lypinator 0:bb348c97df44 1328 * @param I2Cx I2C Instance.
lypinator 0:bb348c97df44 1329 * @retval State of bit (1 or 0).
lypinator 0:bb348c97df44 1330 */
lypinator 0:bb348c97df44 1331 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_AF(I2C_TypeDef *I2Cx)
lypinator 0:bb348c97df44 1332 {
lypinator 0:bb348c97df44 1333 return (READ_BIT(I2Cx->SR1, I2C_SR1_AF) == (I2C_SR1_AF));
lypinator 0:bb348c97df44 1334 }
lypinator 0:bb348c97df44 1335
lypinator 0:bb348c97df44 1336 /**
lypinator 0:bb348c97df44 1337 * @brief Indicate the status of Stop detection flag (slave mode).
lypinator 0:bb348c97df44 1338 * @note RESET: Clear default value.
lypinator 0:bb348c97df44 1339 * SET: When a Stop condition is detected.
lypinator 0:bb348c97df44 1340 * @rmtoll SR1 STOPF LL_I2C_IsActiveFlag_STOP
lypinator 0:bb348c97df44 1341 * @param I2Cx I2C Instance.
lypinator 0:bb348c97df44 1342 * @retval State of bit (1 or 0).
lypinator 0:bb348c97df44 1343 */
lypinator 0:bb348c97df44 1344 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(I2C_TypeDef *I2Cx)
lypinator 0:bb348c97df44 1345 {
lypinator 0:bb348c97df44 1346 return (READ_BIT(I2Cx->SR1, I2C_SR1_STOPF) == (I2C_SR1_STOPF));
lypinator 0:bb348c97df44 1347 }
lypinator 0:bb348c97df44 1348
lypinator 0:bb348c97df44 1349 /**
lypinator 0:bb348c97df44 1350 * @brief Indicate the status of Bus error flag.
lypinator 0:bb348c97df44 1351 * @note RESET: Clear default value.
lypinator 0:bb348c97df44 1352 * SET: When a misplaced Start or Stop condition is detected.
lypinator 0:bb348c97df44 1353 * @rmtoll SR1 BERR LL_I2C_IsActiveFlag_BERR
lypinator 0:bb348c97df44 1354 * @param I2Cx I2C Instance.
lypinator 0:bb348c97df44 1355 * @retval State of bit (1 or 0).
lypinator 0:bb348c97df44 1356 */
lypinator 0:bb348c97df44 1357 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(I2C_TypeDef *I2Cx)
lypinator 0:bb348c97df44 1358 {
lypinator 0:bb348c97df44 1359 return (READ_BIT(I2Cx->SR1, I2C_SR1_BERR) == (I2C_SR1_BERR));
lypinator 0:bb348c97df44 1360 }
lypinator 0:bb348c97df44 1361
lypinator 0:bb348c97df44 1362 /**
lypinator 0:bb348c97df44 1363 * @brief Indicate the status of Arbitration lost flag.
lypinator 0:bb348c97df44 1364 * @note RESET: Clear default value.
lypinator 0:bb348c97df44 1365 * SET: When arbitration lost.
lypinator 0:bb348c97df44 1366 * @rmtoll SR1 ARLO LL_I2C_IsActiveFlag_ARLO
lypinator 0:bb348c97df44 1367 * @param I2Cx I2C Instance.
lypinator 0:bb348c97df44 1368 * @retval State of bit (1 or 0).
lypinator 0:bb348c97df44 1369 */
lypinator 0:bb348c97df44 1370 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef *I2Cx)
lypinator 0:bb348c97df44 1371 {
lypinator 0:bb348c97df44 1372 return (READ_BIT(I2Cx->SR1, I2C_SR1_ARLO) == (I2C_SR1_ARLO));
lypinator 0:bb348c97df44 1373 }
lypinator 0:bb348c97df44 1374
lypinator 0:bb348c97df44 1375 /**
lypinator 0:bb348c97df44 1376 * @brief Indicate the status of Overrun/Underrun flag.
lypinator 0:bb348c97df44 1377 * @note RESET: Clear default value.
lypinator 0:bb348c97df44 1378 * SET: When an overrun/underrun error occurs (Clock Stretching Disabled).
lypinator 0:bb348c97df44 1379 * @rmtoll SR1 OVR LL_I2C_IsActiveFlag_OVR
lypinator 0:bb348c97df44 1380 * @param I2Cx I2C Instance.
lypinator 0:bb348c97df44 1381 * @retval State of bit (1 or 0).
lypinator 0:bb348c97df44 1382 */
lypinator 0:bb348c97df44 1383 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx)
lypinator 0:bb348c97df44 1384 {
lypinator 0:bb348c97df44 1385 return (READ_BIT(I2Cx->SR1, I2C_SR1_OVR) == (I2C_SR1_OVR));
lypinator 0:bb348c97df44 1386 }
lypinator 0:bb348c97df44 1387
lypinator 0:bb348c97df44 1388 /**
lypinator 0:bb348c97df44 1389 * @brief Indicate the status of SMBus PEC error flag in reception.
lypinator 0:bb348c97df44 1390 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
lypinator 0:bb348c97df44 1391 * SMBus feature is supported by the I2Cx Instance.
lypinator 0:bb348c97df44 1392 * @rmtoll SR1 PECERR LL_I2C_IsActiveSMBusFlag_PECERR
lypinator 0:bb348c97df44 1393 * @param I2Cx I2C Instance.
lypinator 0:bb348c97df44 1394 * @retval State of bit (1 or 0).
lypinator 0:bb348c97df44 1395 */
lypinator 0:bb348c97df44 1396 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
lypinator 0:bb348c97df44 1397 {
lypinator 0:bb348c97df44 1398 return (READ_BIT(I2Cx->SR1, I2C_SR1_PECERR) == (I2C_SR1_PECERR));
lypinator 0:bb348c97df44 1399 }
lypinator 0:bb348c97df44 1400
lypinator 0:bb348c97df44 1401 /**
lypinator 0:bb348c97df44 1402 * @brief Indicate the status of SMBus Timeout detection flag.
lypinator 0:bb348c97df44 1403 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
lypinator 0:bb348c97df44 1404 * SMBus feature is supported by the I2Cx Instance.
lypinator 0:bb348c97df44 1405 * @rmtoll SR1 TIMEOUT LL_I2C_IsActiveSMBusFlag_TIMEOUT
lypinator 0:bb348c97df44 1406 * @param I2Cx I2C Instance.
lypinator 0:bb348c97df44 1407 * @retval State of bit (1 or 0).
lypinator 0:bb348c97df44 1408 */
lypinator 0:bb348c97df44 1409 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
lypinator 0:bb348c97df44 1410 {
lypinator 0:bb348c97df44 1411 return (READ_BIT(I2Cx->SR1, I2C_SR1_TIMEOUT) == (I2C_SR1_TIMEOUT));
lypinator 0:bb348c97df44 1412 }
lypinator 0:bb348c97df44 1413
lypinator 0:bb348c97df44 1414 /**
lypinator 0:bb348c97df44 1415 * @brief Indicate the status of SMBus alert flag.
lypinator 0:bb348c97df44 1416 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
lypinator 0:bb348c97df44 1417 * SMBus feature is supported by the I2Cx Instance.
lypinator 0:bb348c97df44 1418 * @rmtoll SR1 SMBALERT LL_I2C_IsActiveSMBusFlag_ALERT
lypinator 0:bb348c97df44 1419 * @param I2Cx I2C Instance.
lypinator 0:bb348c97df44 1420 * @retval State of bit (1 or 0).
lypinator 0:bb348c97df44 1421 */
lypinator 0:bb348c97df44 1422 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
lypinator 0:bb348c97df44 1423 {
lypinator 0:bb348c97df44 1424 return (READ_BIT(I2Cx->SR1, I2C_SR1_SMBALERT) == (I2C_SR1_SMBALERT));
lypinator 0:bb348c97df44 1425 }
lypinator 0:bb348c97df44 1426
lypinator 0:bb348c97df44 1427 /**
lypinator 0:bb348c97df44 1428 * @brief Indicate the status of Bus Busy flag.
lypinator 0:bb348c97df44 1429 * @note RESET: Clear default value.
lypinator 0:bb348c97df44 1430 * SET: When a Start condition is detected.
lypinator 0:bb348c97df44 1431 * @rmtoll SR2 BUSY LL_I2C_IsActiveFlag_BUSY
lypinator 0:bb348c97df44 1432 * @param I2Cx I2C Instance.
lypinator 0:bb348c97df44 1433 * @retval State of bit (1 or 0).
lypinator 0:bb348c97df44 1434 */
lypinator 0:bb348c97df44 1435 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(I2C_TypeDef *I2Cx)
lypinator 0:bb348c97df44 1436 {
lypinator 0:bb348c97df44 1437 return (READ_BIT(I2Cx->SR2, I2C_SR2_BUSY) == (I2C_SR2_BUSY));
lypinator 0:bb348c97df44 1438 }
lypinator 0:bb348c97df44 1439
lypinator 0:bb348c97df44 1440 /**
lypinator 0:bb348c97df44 1441 * @brief Indicate the status of Dual flag.
lypinator 0:bb348c97df44 1442 * @note RESET: Received address matched with OAR1.
lypinator 0:bb348c97df44 1443 * SET: Received address matched with OAR2.
lypinator 0:bb348c97df44 1444 * @rmtoll SR2 DUALF LL_I2C_IsActiveFlag_DUAL
lypinator 0:bb348c97df44 1445 * @param I2Cx I2C Instance.
lypinator 0:bb348c97df44 1446 * @retval State of bit (1 or 0).
lypinator 0:bb348c97df44 1447 */
lypinator 0:bb348c97df44 1448 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_DUAL(I2C_TypeDef *I2Cx)
lypinator 0:bb348c97df44 1449 {
lypinator 0:bb348c97df44 1450 return (READ_BIT(I2Cx->SR2, I2C_SR2_DUALF) == (I2C_SR2_DUALF));
lypinator 0:bb348c97df44 1451 }
lypinator 0:bb348c97df44 1452
lypinator 0:bb348c97df44 1453 /**
lypinator 0:bb348c97df44 1454 * @brief Indicate the status of SMBus Host address reception (Slave mode).
lypinator 0:bb348c97df44 1455 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
lypinator 0:bb348c97df44 1456 * SMBus feature is supported by the I2Cx Instance.
lypinator 0:bb348c97df44 1457 * @note RESET: No SMBus Host address
lypinator 0:bb348c97df44 1458 * SET: SMBus Host address received.
lypinator 0:bb348c97df44 1459 * @note This status is cleared by hardware after a STOP condition or repeated START condition.
lypinator 0:bb348c97df44 1460 * @rmtoll SR2 SMBHOST LL_I2C_IsActiveSMBusFlag_SMBHOST
lypinator 0:bb348c97df44 1461 * @param I2Cx I2C Instance.
lypinator 0:bb348c97df44 1462 * @retval State of bit (1 or 0).
lypinator 0:bb348c97df44 1463 */
lypinator 0:bb348c97df44 1464 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_SMBHOST(I2C_TypeDef *I2Cx)
lypinator 0:bb348c97df44 1465 {
lypinator 0:bb348c97df44 1466 return (READ_BIT(I2Cx->SR2, I2C_SR2_SMBHOST) == (I2C_SR2_SMBHOST));
lypinator 0:bb348c97df44 1467 }
lypinator 0:bb348c97df44 1468
lypinator 0:bb348c97df44 1469 /**
lypinator 0:bb348c97df44 1470 * @brief Indicate the status of SMBus Device default address reception (Slave mode).
lypinator 0:bb348c97df44 1471 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
lypinator 0:bb348c97df44 1472 * SMBus feature is supported by the I2Cx Instance.
lypinator 0:bb348c97df44 1473 * @note RESET: No SMBus Device default address
lypinator 0:bb348c97df44 1474 * SET: SMBus Device default address received.
lypinator 0:bb348c97df44 1475 * @note This status is cleared by hardware after a STOP condition or repeated START condition.
lypinator 0:bb348c97df44 1476 * @rmtoll SR2 SMBDEFAULT LL_I2C_IsActiveSMBusFlag_SMBDEFAULT
lypinator 0:bb348c97df44 1477 * @param I2Cx I2C Instance.
lypinator 0:bb348c97df44 1478 * @retval State of bit (1 or 0).
lypinator 0:bb348c97df44 1479 */
lypinator 0:bb348c97df44 1480 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_SMBDEFAULT(I2C_TypeDef *I2Cx)
lypinator 0:bb348c97df44 1481 {
lypinator 0:bb348c97df44 1482 return (READ_BIT(I2Cx->SR2, I2C_SR2_SMBDEFAULT) == (I2C_SR2_SMBDEFAULT));
lypinator 0:bb348c97df44 1483 }
lypinator 0:bb348c97df44 1484
lypinator 0:bb348c97df44 1485 /**
lypinator 0:bb348c97df44 1486 * @brief Indicate the status of General call address reception (Slave mode).
lypinator 0:bb348c97df44 1487 * @note RESET: No Generall call address
lypinator 0:bb348c97df44 1488 * SET: General call address received.
lypinator 0:bb348c97df44 1489 * @note This status is cleared by hardware after a STOP condition or repeated START condition.
lypinator 0:bb348c97df44 1490 * @rmtoll SR2 GENCALL LL_I2C_IsActiveFlag_GENCALL
lypinator 0:bb348c97df44 1491 * @param I2Cx I2C Instance.
lypinator 0:bb348c97df44 1492 * @retval State of bit (1 or 0).
lypinator 0:bb348c97df44 1493 */
lypinator 0:bb348c97df44 1494 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_GENCALL(I2C_TypeDef *I2Cx)
lypinator 0:bb348c97df44 1495 {
lypinator 0:bb348c97df44 1496 return (READ_BIT(I2Cx->SR2, I2C_SR2_GENCALL) == (I2C_SR2_GENCALL));
lypinator 0:bb348c97df44 1497 }
lypinator 0:bb348c97df44 1498
lypinator 0:bb348c97df44 1499 /**
lypinator 0:bb348c97df44 1500 * @brief Indicate the status of Master/Slave flag.
lypinator 0:bb348c97df44 1501 * @note RESET: Slave Mode.
lypinator 0:bb348c97df44 1502 * SET: Master Mode.
lypinator 0:bb348c97df44 1503 * @rmtoll SR2 MSL LL_I2C_IsActiveFlag_MSL
lypinator 0:bb348c97df44 1504 * @param I2Cx I2C Instance.
lypinator 0:bb348c97df44 1505 * @retval State of bit (1 or 0).
lypinator 0:bb348c97df44 1506 */
lypinator 0:bb348c97df44 1507 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_MSL(I2C_TypeDef *I2Cx)
lypinator 0:bb348c97df44 1508 {
lypinator 0:bb348c97df44 1509 return (READ_BIT(I2Cx->SR2, I2C_SR2_MSL) == (I2C_SR2_MSL));
lypinator 0:bb348c97df44 1510 }
lypinator 0:bb348c97df44 1511
lypinator 0:bb348c97df44 1512 /**
lypinator 0:bb348c97df44 1513 * @brief Clear Address Matched flag.
lypinator 0:bb348c97df44 1514 * @note Clearing this flag is done by a read access to the I2Cx_SR1
lypinator 0:bb348c97df44 1515 * register followed by a read access to the I2Cx_SR2 register.
lypinator 0:bb348c97df44 1516 * @rmtoll SR1 ADDR LL_I2C_ClearFlag_ADDR
lypinator 0:bb348c97df44 1517 * @param I2Cx I2C Instance.
lypinator 0:bb348c97df44 1518 * @retval None
lypinator 0:bb348c97df44 1519 */
lypinator 0:bb348c97df44 1520 __STATIC_INLINE void LL_I2C_ClearFlag_ADDR(I2C_TypeDef *I2Cx)
lypinator 0:bb348c97df44 1521 {
lypinator 0:bb348c97df44 1522 __IO uint32_t tmpreg;
lypinator 0:bb348c97df44 1523 tmpreg = I2Cx->SR1;
lypinator 0:bb348c97df44 1524 (void) tmpreg;
lypinator 0:bb348c97df44 1525 tmpreg = I2Cx->SR2;
lypinator 0:bb348c97df44 1526 (void) tmpreg;
lypinator 0:bb348c97df44 1527 }
lypinator 0:bb348c97df44 1528
lypinator 0:bb348c97df44 1529 /**
lypinator 0:bb348c97df44 1530 * @brief Clear Acknowledge failure flag.
lypinator 0:bb348c97df44 1531 * @rmtoll SR1 AF LL_I2C_ClearFlag_AF
lypinator 0:bb348c97df44 1532 * @param I2Cx I2C Instance.
lypinator 0:bb348c97df44 1533 * @retval None
lypinator 0:bb348c97df44 1534 */
lypinator 0:bb348c97df44 1535 __STATIC_INLINE void LL_I2C_ClearFlag_AF(I2C_TypeDef *I2Cx)
lypinator 0:bb348c97df44 1536 {
lypinator 0:bb348c97df44 1537 CLEAR_BIT(I2Cx->SR1, I2C_SR1_AF);
lypinator 0:bb348c97df44 1538 }
lypinator 0:bb348c97df44 1539
lypinator 0:bb348c97df44 1540 /**
lypinator 0:bb348c97df44 1541 * @brief Clear Stop detection flag.
lypinator 0:bb348c97df44 1542 * @note Clearing this flag is done by a read access to the I2Cx_SR1
lypinator 0:bb348c97df44 1543 * register followed by a write access to I2Cx_CR1 register.
lypinator 0:bb348c97df44 1544 * @rmtoll SR1 STOPF LL_I2C_ClearFlag_STOP\n
lypinator 0:bb348c97df44 1545 * CR1 PE LL_I2C_ClearFlag_STOP
lypinator 0:bb348c97df44 1546 * @param I2Cx I2C Instance.
lypinator 0:bb348c97df44 1547 * @retval None
lypinator 0:bb348c97df44 1548 */
lypinator 0:bb348c97df44 1549 __STATIC_INLINE void LL_I2C_ClearFlag_STOP(I2C_TypeDef *I2Cx)
lypinator 0:bb348c97df44 1550 {
lypinator 0:bb348c97df44 1551 __IO uint32_t tmpreg;
lypinator 0:bb348c97df44 1552 tmpreg = I2Cx->SR1;
lypinator 0:bb348c97df44 1553 (void) tmpreg;
lypinator 0:bb348c97df44 1554 SET_BIT(I2Cx->CR1, I2C_CR1_PE);
lypinator 0:bb348c97df44 1555 }
lypinator 0:bb348c97df44 1556
lypinator 0:bb348c97df44 1557 /**
lypinator 0:bb348c97df44 1558 * @brief Clear Bus error flag.
lypinator 0:bb348c97df44 1559 * @rmtoll SR1 BERR LL_I2C_ClearFlag_BERR
lypinator 0:bb348c97df44 1560 * @param I2Cx I2C Instance.
lypinator 0:bb348c97df44 1561 * @retval None
lypinator 0:bb348c97df44 1562 */
lypinator 0:bb348c97df44 1563 __STATIC_INLINE void LL_I2C_ClearFlag_BERR(I2C_TypeDef *I2Cx)
lypinator 0:bb348c97df44 1564 {
lypinator 0:bb348c97df44 1565 CLEAR_BIT(I2Cx->SR1, I2C_SR1_BERR);
lypinator 0:bb348c97df44 1566 }
lypinator 0:bb348c97df44 1567
lypinator 0:bb348c97df44 1568 /**
lypinator 0:bb348c97df44 1569 * @brief Clear Arbitration lost flag.
lypinator 0:bb348c97df44 1570 * @rmtoll SR1 ARLO LL_I2C_ClearFlag_ARLO
lypinator 0:bb348c97df44 1571 * @param I2Cx I2C Instance.
lypinator 0:bb348c97df44 1572 * @retval None
lypinator 0:bb348c97df44 1573 */
lypinator 0:bb348c97df44 1574 __STATIC_INLINE void LL_I2C_ClearFlag_ARLO(I2C_TypeDef *I2Cx)
lypinator 0:bb348c97df44 1575 {
lypinator 0:bb348c97df44 1576 CLEAR_BIT(I2Cx->SR1, I2C_SR1_ARLO);
lypinator 0:bb348c97df44 1577 }
lypinator 0:bb348c97df44 1578
lypinator 0:bb348c97df44 1579 /**
lypinator 0:bb348c97df44 1580 * @brief Clear Overrun/Underrun flag.
lypinator 0:bb348c97df44 1581 * @rmtoll SR1 OVR LL_I2C_ClearFlag_OVR
lypinator 0:bb348c97df44 1582 * @param I2Cx I2C Instance.
lypinator 0:bb348c97df44 1583 * @retval None
lypinator 0:bb348c97df44 1584 */
lypinator 0:bb348c97df44 1585 __STATIC_INLINE void LL_I2C_ClearFlag_OVR(I2C_TypeDef *I2Cx)
lypinator 0:bb348c97df44 1586 {
lypinator 0:bb348c97df44 1587 CLEAR_BIT(I2Cx->SR1, I2C_SR1_OVR);
lypinator 0:bb348c97df44 1588 }
lypinator 0:bb348c97df44 1589
lypinator 0:bb348c97df44 1590 /**
lypinator 0:bb348c97df44 1591 * @brief Clear SMBus PEC error flag.
lypinator 0:bb348c97df44 1592 * @rmtoll SR1 PECERR LL_I2C_ClearSMBusFlag_PECERR
lypinator 0:bb348c97df44 1593 * @param I2Cx I2C Instance.
lypinator 0:bb348c97df44 1594 * @retval None
lypinator 0:bb348c97df44 1595 */
lypinator 0:bb348c97df44 1596 __STATIC_INLINE void LL_I2C_ClearSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
lypinator 0:bb348c97df44 1597 {
lypinator 0:bb348c97df44 1598 CLEAR_BIT(I2Cx->SR1, I2C_SR1_PECERR);
lypinator 0:bb348c97df44 1599 }
lypinator 0:bb348c97df44 1600
lypinator 0:bb348c97df44 1601 /**
lypinator 0:bb348c97df44 1602 * @brief Clear SMBus Timeout detection flag.
lypinator 0:bb348c97df44 1603 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
lypinator 0:bb348c97df44 1604 * SMBus feature is supported by the I2Cx Instance.
lypinator 0:bb348c97df44 1605 * @rmtoll SR1 TIMEOUT LL_I2C_ClearSMBusFlag_TIMEOUT
lypinator 0:bb348c97df44 1606 * @param I2Cx I2C Instance.
lypinator 0:bb348c97df44 1607 * @retval None
lypinator 0:bb348c97df44 1608 */
lypinator 0:bb348c97df44 1609 __STATIC_INLINE void LL_I2C_ClearSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
lypinator 0:bb348c97df44 1610 {
lypinator 0:bb348c97df44 1611 CLEAR_BIT(I2Cx->SR1, I2C_SR1_TIMEOUT);
lypinator 0:bb348c97df44 1612 }
lypinator 0:bb348c97df44 1613
lypinator 0:bb348c97df44 1614 /**
lypinator 0:bb348c97df44 1615 * @brief Clear SMBus Alert flag.
lypinator 0:bb348c97df44 1616 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
lypinator 0:bb348c97df44 1617 * SMBus feature is supported by the I2Cx Instance.
lypinator 0:bb348c97df44 1618 * @rmtoll SR1 SMBALERT LL_I2C_ClearSMBusFlag_ALERT
lypinator 0:bb348c97df44 1619 * @param I2Cx I2C Instance.
lypinator 0:bb348c97df44 1620 * @retval None
lypinator 0:bb348c97df44 1621 */
lypinator 0:bb348c97df44 1622 __STATIC_INLINE void LL_I2C_ClearSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
lypinator 0:bb348c97df44 1623 {
lypinator 0:bb348c97df44 1624 CLEAR_BIT(I2Cx->SR1, I2C_SR1_SMBALERT);
lypinator 0:bb348c97df44 1625 }
lypinator 0:bb348c97df44 1626
lypinator 0:bb348c97df44 1627 /**
lypinator 0:bb348c97df44 1628 * @}
lypinator 0:bb348c97df44 1629 */
lypinator 0:bb348c97df44 1630
lypinator 0:bb348c97df44 1631 /** @defgroup I2C_LL_EF_Data_Management Data_Management
lypinator 0:bb348c97df44 1632 * @{
lypinator 0:bb348c97df44 1633 */
lypinator 0:bb348c97df44 1634
lypinator 0:bb348c97df44 1635 /**
lypinator 0:bb348c97df44 1636 * @brief Enable Reset of I2C peripheral.
lypinator 0:bb348c97df44 1637 * @rmtoll CR1 SWRST LL_I2C_EnableReset
lypinator 0:bb348c97df44 1638 * @param I2Cx I2C Instance.
lypinator 0:bb348c97df44 1639 * @retval None
lypinator 0:bb348c97df44 1640 */
lypinator 0:bb348c97df44 1641 __STATIC_INLINE void LL_I2C_EnableReset(I2C_TypeDef *I2Cx)
lypinator 0:bb348c97df44 1642 {
lypinator 0:bb348c97df44 1643 SET_BIT(I2Cx->CR1, I2C_CR1_SWRST);
lypinator 0:bb348c97df44 1644 }
lypinator 0:bb348c97df44 1645
lypinator 0:bb348c97df44 1646 /**
lypinator 0:bb348c97df44 1647 * @brief Disable Reset of I2C peripheral.
lypinator 0:bb348c97df44 1648 * @rmtoll CR1 SWRST LL_I2C_DisableReset
lypinator 0:bb348c97df44 1649 * @param I2Cx I2C Instance.
lypinator 0:bb348c97df44 1650 * @retval None
lypinator 0:bb348c97df44 1651 */
lypinator 0:bb348c97df44 1652 __STATIC_INLINE void LL_I2C_DisableReset(I2C_TypeDef *I2Cx)
lypinator 0:bb348c97df44 1653 {
lypinator 0:bb348c97df44 1654 CLEAR_BIT(I2Cx->CR1, I2C_CR1_SWRST);
lypinator 0:bb348c97df44 1655 }
lypinator 0:bb348c97df44 1656
lypinator 0:bb348c97df44 1657 /**
lypinator 0:bb348c97df44 1658 * @brief Check if the I2C peripheral is under reset state or not.
lypinator 0:bb348c97df44 1659 * @rmtoll CR1 SWRST LL_I2C_IsResetEnabled
lypinator 0:bb348c97df44 1660 * @param I2Cx I2C Instance.
lypinator 0:bb348c97df44 1661 * @retval State of bit (1 or 0).
lypinator 0:bb348c97df44 1662 */
lypinator 0:bb348c97df44 1663 __STATIC_INLINE uint32_t LL_I2C_IsResetEnabled(I2C_TypeDef *I2Cx)
lypinator 0:bb348c97df44 1664 {
lypinator 0:bb348c97df44 1665 return (READ_BIT(I2Cx->CR1, I2C_CR1_SWRST) == (I2C_CR1_SWRST));
lypinator 0:bb348c97df44 1666 }
lypinator 0:bb348c97df44 1667
lypinator 0:bb348c97df44 1668 /**
lypinator 0:bb348c97df44 1669 * @brief Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
lypinator 0:bb348c97df44 1670 * @note Usage in Slave or Master mode.
lypinator 0:bb348c97df44 1671 * @rmtoll CR1 ACK LL_I2C_AcknowledgeNextData
lypinator 0:bb348c97df44 1672 * @param I2Cx I2C Instance.
lypinator 0:bb348c97df44 1673 * @param TypeAcknowledge This parameter can be one of the following values:
lypinator 0:bb348c97df44 1674 * @arg @ref LL_I2C_ACK
lypinator 0:bb348c97df44 1675 * @arg @ref LL_I2C_NACK
lypinator 0:bb348c97df44 1676 * @retval None
lypinator 0:bb348c97df44 1677 */
lypinator 0:bb348c97df44 1678 __STATIC_INLINE void LL_I2C_AcknowledgeNextData(I2C_TypeDef *I2Cx, uint32_t TypeAcknowledge)
lypinator 0:bb348c97df44 1679 {
lypinator 0:bb348c97df44 1680 MODIFY_REG(I2Cx->CR1, I2C_CR1_ACK, TypeAcknowledge);
lypinator 0:bb348c97df44 1681 }
lypinator 0:bb348c97df44 1682
lypinator 0:bb348c97df44 1683 /**
lypinator 0:bb348c97df44 1684 * @brief Generate a START or RESTART condition
lypinator 0:bb348c97df44 1685 * @note The START bit can be set even if bus is BUSY or I2C is in slave mode.
lypinator 0:bb348c97df44 1686 * This action has no effect when RELOAD is set.
lypinator 0:bb348c97df44 1687 * @rmtoll CR1 START LL_I2C_GenerateStartCondition
lypinator 0:bb348c97df44 1688 * @param I2Cx I2C Instance.
lypinator 0:bb348c97df44 1689 * @retval None
lypinator 0:bb348c97df44 1690 */
lypinator 0:bb348c97df44 1691 __STATIC_INLINE void LL_I2C_GenerateStartCondition(I2C_TypeDef *I2Cx)
lypinator 0:bb348c97df44 1692 {
lypinator 0:bb348c97df44 1693 SET_BIT(I2Cx->CR1, I2C_CR1_START);
lypinator 0:bb348c97df44 1694 }
lypinator 0:bb348c97df44 1695
lypinator 0:bb348c97df44 1696 /**
lypinator 0:bb348c97df44 1697 * @brief Generate a STOP condition after the current byte transfer (master mode).
lypinator 0:bb348c97df44 1698 * @rmtoll CR1 STOP LL_I2C_GenerateStopCondition
lypinator 0:bb348c97df44 1699 * @param I2Cx I2C Instance.
lypinator 0:bb348c97df44 1700 * @retval None
lypinator 0:bb348c97df44 1701 */
lypinator 0:bb348c97df44 1702 __STATIC_INLINE void LL_I2C_GenerateStopCondition(I2C_TypeDef *I2Cx)
lypinator 0:bb348c97df44 1703 {
lypinator 0:bb348c97df44 1704 SET_BIT(I2Cx->CR1, I2C_CR1_STOP);
lypinator 0:bb348c97df44 1705 }
lypinator 0:bb348c97df44 1706
lypinator 0:bb348c97df44 1707 /**
lypinator 0:bb348c97df44 1708 * @brief Enable bit POS (master/host mode).
lypinator 0:bb348c97df44 1709 * @note In that case, the ACK bit controls the (N)ACK of the next byte received or the PEC bit indicates that the next byte in shift register is a PEC.
lypinator 0:bb348c97df44 1710 * @rmtoll CR1 POS LL_I2C_EnableBitPOS
lypinator 0:bb348c97df44 1711 * @param I2Cx I2C Instance.
lypinator 0:bb348c97df44 1712 * @retval None
lypinator 0:bb348c97df44 1713 */
lypinator 0:bb348c97df44 1714 __STATIC_INLINE void LL_I2C_EnableBitPOS(I2C_TypeDef *I2Cx)
lypinator 0:bb348c97df44 1715 {
lypinator 0:bb348c97df44 1716 SET_BIT(I2Cx->CR1, I2C_CR1_POS);
lypinator 0:bb348c97df44 1717 }
lypinator 0:bb348c97df44 1718
lypinator 0:bb348c97df44 1719 /**
lypinator 0:bb348c97df44 1720 * @brief Disable bit POS (master/host mode).
lypinator 0:bb348c97df44 1721 * @note In that case, the ACK bit controls the (N)ACK of the current byte received or the PEC bit indicates that the current byte in shift register is a PEC.
lypinator 0:bb348c97df44 1722 * @rmtoll CR1 POS LL_I2C_DisableBitPOS
lypinator 0:bb348c97df44 1723 * @param I2Cx I2C Instance.
lypinator 0:bb348c97df44 1724 * @retval None
lypinator 0:bb348c97df44 1725 */
lypinator 0:bb348c97df44 1726 __STATIC_INLINE void LL_I2C_DisableBitPOS(I2C_TypeDef *I2Cx)
lypinator 0:bb348c97df44 1727 {
lypinator 0:bb348c97df44 1728 CLEAR_BIT(I2Cx->CR1, I2C_CR1_POS);
lypinator 0:bb348c97df44 1729 }
lypinator 0:bb348c97df44 1730
lypinator 0:bb348c97df44 1731 /**
lypinator 0:bb348c97df44 1732 * @brief Check if bit POS is enabled or disabled.
lypinator 0:bb348c97df44 1733 * @rmtoll CR1 POS LL_I2C_IsEnabledBitPOS
lypinator 0:bb348c97df44 1734 * @param I2Cx I2C Instance.
lypinator 0:bb348c97df44 1735 * @retval State of bit (1 or 0).
lypinator 0:bb348c97df44 1736 */
lypinator 0:bb348c97df44 1737 __STATIC_INLINE uint32_t LL_I2C_IsEnabledBitPOS(I2C_TypeDef *I2Cx)
lypinator 0:bb348c97df44 1738 {
lypinator 0:bb348c97df44 1739 return (READ_BIT(I2Cx->CR1, I2C_CR1_POS) == (I2C_CR1_POS));
lypinator 0:bb348c97df44 1740 }
lypinator 0:bb348c97df44 1741
lypinator 0:bb348c97df44 1742 /**
lypinator 0:bb348c97df44 1743 * @brief Indicate the value of transfer direction.
lypinator 0:bb348c97df44 1744 * @note RESET: Bus is in read transfer (peripheral point of view).
lypinator 0:bb348c97df44 1745 * SET: Bus is in write transfer (peripheral point of view).
lypinator 0:bb348c97df44 1746 * @rmtoll SR2 TRA LL_I2C_GetTransferDirection
lypinator 0:bb348c97df44 1747 * @param I2Cx I2C Instance.
lypinator 0:bb348c97df44 1748 * @retval Returned value can be one of the following values:
lypinator 0:bb348c97df44 1749 * @arg @ref LL_I2C_DIRECTION_WRITE
lypinator 0:bb348c97df44 1750 * @arg @ref LL_I2C_DIRECTION_READ
lypinator 0:bb348c97df44 1751 */
lypinator 0:bb348c97df44 1752 __STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(I2C_TypeDef *I2Cx)
lypinator 0:bb348c97df44 1753 {
lypinator 0:bb348c97df44 1754 return (uint32_t)(READ_BIT(I2Cx->SR2, I2C_SR2_TRA));
lypinator 0:bb348c97df44 1755 }
lypinator 0:bb348c97df44 1756
lypinator 0:bb348c97df44 1757 /**
lypinator 0:bb348c97df44 1758 * @brief Enable DMA last transfer.
lypinator 0:bb348c97df44 1759 * @note This action mean that next DMA EOT is the last transfer.
lypinator 0:bb348c97df44 1760 * @rmtoll CR2 LAST LL_I2C_EnableLastDMA
lypinator 0:bb348c97df44 1761 * @param I2Cx I2C Instance.
lypinator 0:bb348c97df44 1762 * @retval None
lypinator 0:bb348c97df44 1763 */
lypinator 0:bb348c97df44 1764 __STATIC_INLINE void LL_I2C_EnableLastDMA(I2C_TypeDef *I2Cx)
lypinator 0:bb348c97df44 1765 {
lypinator 0:bb348c97df44 1766 SET_BIT(I2Cx->CR2, I2C_CR2_LAST);
lypinator 0:bb348c97df44 1767 }
lypinator 0:bb348c97df44 1768
lypinator 0:bb348c97df44 1769 /**
lypinator 0:bb348c97df44 1770 * @brief Disable DMA last transfer.
lypinator 0:bb348c97df44 1771 * @note This action mean that next DMA EOT is not the last transfer.
lypinator 0:bb348c97df44 1772 * @rmtoll CR2 LAST LL_I2C_DisableLastDMA
lypinator 0:bb348c97df44 1773 * @param I2Cx I2C Instance.
lypinator 0:bb348c97df44 1774 * @retval None
lypinator 0:bb348c97df44 1775 */
lypinator 0:bb348c97df44 1776 __STATIC_INLINE void LL_I2C_DisableLastDMA(I2C_TypeDef *I2Cx)
lypinator 0:bb348c97df44 1777 {
lypinator 0:bb348c97df44 1778 CLEAR_BIT(I2Cx->CR2, I2C_CR2_LAST);
lypinator 0:bb348c97df44 1779 }
lypinator 0:bb348c97df44 1780
lypinator 0:bb348c97df44 1781 /**
lypinator 0:bb348c97df44 1782 * @brief Check if DMA last transfer is enabled or disabled.
lypinator 0:bb348c97df44 1783 * @rmtoll CR2 LAST LL_I2C_IsEnabledLastDMA
lypinator 0:bb348c97df44 1784 * @param I2Cx I2C Instance.
lypinator 0:bb348c97df44 1785 * @retval State of bit (1 or 0).
lypinator 0:bb348c97df44 1786 */
lypinator 0:bb348c97df44 1787 __STATIC_INLINE uint32_t LL_I2C_IsEnabledLastDMA(I2C_TypeDef *I2Cx)
lypinator 0:bb348c97df44 1788 {
lypinator 0:bb348c97df44 1789 return (READ_BIT(I2Cx->CR2, I2C_CR2_LAST) == (I2C_CR2_LAST));
lypinator 0:bb348c97df44 1790 }
lypinator 0:bb348c97df44 1791
lypinator 0:bb348c97df44 1792 /**
lypinator 0:bb348c97df44 1793 * @brief Enable transfer or internal comparison of the SMBus Packet Error byte (transmission or reception mode).
lypinator 0:bb348c97df44 1794 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
lypinator 0:bb348c97df44 1795 * SMBus feature is supported by the I2Cx Instance.
lypinator 0:bb348c97df44 1796 * @note This feature is cleared by hardware when the PEC byte is transferred or compared,
lypinator 0:bb348c97df44 1797 * or by a START or STOP condition, it is also cleared by software.
lypinator 0:bb348c97df44 1798 * @rmtoll CR1 PEC LL_I2C_EnableSMBusPECCompare
lypinator 0:bb348c97df44 1799 * @param I2Cx I2C Instance.
lypinator 0:bb348c97df44 1800 * @retval None
lypinator 0:bb348c97df44 1801 */
lypinator 0:bb348c97df44 1802 __STATIC_INLINE void LL_I2C_EnableSMBusPECCompare(I2C_TypeDef *I2Cx)
lypinator 0:bb348c97df44 1803 {
lypinator 0:bb348c97df44 1804 SET_BIT(I2Cx->CR1, I2C_CR1_PEC);
lypinator 0:bb348c97df44 1805 }
lypinator 0:bb348c97df44 1806
lypinator 0:bb348c97df44 1807 /**
lypinator 0:bb348c97df44 1808 * @brief Disable transfer or internal comparison of the SMBus Packet Error byte (transmission or reception mode).
lypinator 0:bb348c97df44 1809 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
lypinator 0:bb348c97df44 1810 * SMBus feature is supported by the I2Cx Instance.
lypinator 0:bb348c97df44 1811 * @rmtoll CR1 PEC LL_I2C_DisableSMBusPECCompare
lypinator 0:bb348c97df44 1812 * @param I2Cx I2C Instance.
lypinator 0:bb348c97df44 1813 * @retval None
lypinator 0:bb348c97df44 1814 */
lypinator 0:bb348c97df44 1815 __STATIC_INLINE void LL_I2C_DisableSMBusPECCompare(I2C_TypeDef *I2Cx)
lypinator 0:bb348c97df44 1816 {
lypinator 0:bb348c97df44 1817 CLEAR_BIT(I2Cx->CR1, I2C_CR1_PEC);
lypinator 0:bb348c97df44 1818 }
lypinator 0:bb348c97df44 1819
lypinator 0:bb348c97df44 1820 /**
lypinator 0:bb348c97df44 1821 * @brief Check if the SMBus Packet Error byte transfer or internal comparison is requested or not.
lypinator 0:bb348c97df44 1822 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
lypinator 0:bb348c97df44 1823 * SMBus feature is supported by the I2Cx Instance.
lypinator 0:bb348c97df44 1824 * @rmtoll CR1 PEC LL_I2C_IsEnabledSMBusPECCompare
lypinator 0:bb348c97df44 1825 * @param I2Cx I2C Instance.
lypinator 0:bb348c97df44 1826 * @retval State of bit (1 or 0).
lypinator 0:bb348c97df44 1827 */
lypinator 0:bb348c97df44 1828 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef *I2Cx)
lypinator 0:bb348c97df44 1829 {
lypinator 0:bb348c97df44 1830 return (READ_BIT(I2Cx->CR1, I2C_CR1_PEC) == (I2C_CR1_PEC));
lypinator 0:bb348c97df44 1831 }
lypinator 0:bb348c97df44 1832
lypinator 0:bb348c97df44 1833 /**
lypinator 0:bb348c97df44 1834 * @brief Get the SMBus Packet Error byte calculated.
lypinator 0:bb348c97df44 1835 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
lypinator 0:bb348c97df44 1836 * SMBus feature is supported by the I2Cx Instance.
lypinator 0:bb348c97df44 1837 * @rmtoll SR2 PEC LL_I2C_GetSMBusPEC
lypinator 0:bb348c97df44 1838 * @param I2Cx I2C Instance.
lypinator 0:bb348c97df44 1839 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
lypinator 0:bb348c97df44 1840 */
lypinator 0:bb348c97df44 1841 __STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(I2C_TypeDef *I2Cx)
lypinator 0:bb348c97df44 1842 {
lypinator 0:bb348c97df44 1843 return (uint32_t)(READ_BIT(I2Cx->SR2, I2C_SR2_PEC) >> I2C_SR2_PEC_Pos);
lypinator 0:bb348c97df44 1844 }
lypinator 0:bb348c97df44 1845
lypinator 0:bb348c97df44 1846 /**
lypinator 0:bb348c97df44 1847 * @brief Read Receive Data register.
lypinator 0:bb348c97df44 1848 * @rmtoll DR DR LL_I2C_ReceiveData8
lypinator 0:bb348c97df44 1849 * @param I2Cx I2C Instance.
lypinator 0:bb348c97df44 1850 * @retval Value between Min_Data=0x0 and Max_Data=0xFF
lypinator 0:bb348c97df44 1851 */
lypinator 0:bb348c97df44 1852 __STATIC_INLINE uint8_t LL_I2C_ReceiveData8(I2C_TypeDef *I2Cx)
lypinator 0:bb348c97df44 1853 {
lypinator 0:bb348c97df44 1854 return (uint8_t)(READ_BIT(I2Cx->DR, I2C_DR_DR));
lypinator 0:bb348c97df44 1855 }
lypinator 0:bb348c97df44 1856
lypinator 0:bb348c97df44 1857 /**
lypinator 0:bb348c97df44 1858 * @brief Write in Transmit Data Register .
lypinator 0:bb348c97df44 1859 * @rmtoll DR DR LL_I2C_TransmitData8
lypinator 0:bb348c97df44 1860 * @param I2Cx I2C Instance.
lypinator 0:bb348c97df44 1861 * @param Data Value between Min_Data=0x0 and Max_Data=0xFF
lypinator 0:bb348c97df44 1862 * @retval None
lypinator 0:bb348c97df44 1863 */
lypinator 0:bb348c97df44 1864 __STATIC_INLINE void LL_I2C_TransmitData8(I2C_TypeDef *I2Cx, uint8_t Data)
lypinator 0:bb348c97df44 1865 {
lypinator 0:bb348c97df44 1866 MODIFY_REG(I2Cx->DR, I2C_DR_DR, Data);
lypinator 0:bb348c97df44 1867 }
lypinator 0:bb348c97df44 1868
lypinator 0:bb348c97df44 1869 /**
lypinator 0:bb348c97df44 1870 * @}
lypinator 0:bb348c97df44 1871 */
lypinator 0:bb348c97df44 1872
lypinator 0:bb348c97df44 1873 #if defined(USE_FULL_LL_DRIVER)
lypinator 0:bb348c97df44 1874 /** @defgroup I2C_LL_EF_Init Initialization and de-initialization functions
lypinator 0:bb348c97df44 1875 * @{
lypinator 0:bb348c97df44 1876 */
lypinator 0:bb348c97df44 1877
lypinator 0:bb348c97df44 1878 uint32_t LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct);
lypinator 0:bb348c97df44 1879 uint32_t LL_I2C_DeInit(I2C_TypeDef *I2Cx);
lypinator 0:bb348c97df44 1880 void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct);
lypinator 0:bb348c97df44 1881
lypinator 0:bb348c97df44 1882
lypinator 0:bb348c97df44 1883 /**
lypinator 0:bb348c97df44 1884 * @}
lypinator 0:bb348c97df44 1885 */
lypinator 0:bb348c97df44 1886 #endif /* USE_FULL_LL_DRIVER */
lypinator 0:bb348c97df44 1887
lypinator 0:bb348c97df44 1888 /**
lypinator 0:bb348c97df44 1889 * @}
lypinator 0:bb348c97df44 1890 */
lypinator 0:bb348c97df44 1891
lypinator 0:bb348c97df44 1892 /**
lypinator 0:bb348c97df44 1893 * @}
lypinator 0:bb348c97df44 1894 */
lypinator 0:bb348c97df44 1895
lypinator 0:bb348c97df44 1896 #endif /* I2C1 || I2C2 || I2C3 */
lypinator 0:bb348c97df44 1897
lypinator 0:bb348c97df44 1898 /**
lypinator 0:bb348c97df44 1899 * @}
lypinator 0:bb348c97df44 1900 */
lypinator 0:bb348c97df44 1901
lypinator 0:bb348c97df44 1902 #ifdef __cplusplus
lypinator 0:bb348c97df44 1903 }
lypinator 0:bb348c97df44 1904 #endif
lypinator 0:bb348c97df44 1905
lypinator 0:bb348c97df44 1906 #endif /* __STM32F4xx_LL_I2C_H */
lypinator 0:bb348c97df44 1907
lypinator 0:bb348c97df44 1908 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/