DevLibMemoryController - Initial commit

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Initial commit

mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_fsmc.h@0:bb348c97df44, 2020-09-16 (annotated)

Committer:: lypinator
Date:: Wed Sep 16 01:11:49 2020 +0000
Revision:: 0:bb348c97df44

Added PWM

Who changed what in which revision?

User	Revision	Line number	New contents of line
lypinator	0:bb348c97df44	1	/**
lypinator	0:bb348c97df44	2	******************************************************************************
lypinator	0:bb348c97df44	3	* @file stm32f4xx_ll_fsmc.h
lypinator	0:bb348c97df44	4	* @author MCD Application Team
lypinator	0:bb348c97df44	5	* @brief Header file of FSMC HAL module.
lypinator	0:bb348c97df44	6	******************************************************************************
lypinator	0:bb348c97df44	7	* @attention
lypinator	0:bb348c97df44	8	*
lypinator	0:bb348c97df44	9	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
lypinator	0:bb348c97df44	10	*
lypinator	0:bb348c97df44	11	* Redistribution and use in source and binary forms, with or without modification,
lypinator	0:bb348c97df44	12	* are permitted provided that the following conditions are met:
lypinator	0:bb348c97df44	13	* 1. Redistributions of source code must retain the above copyright notice,
lypinator	0:bb348c97df44	14	* this list of conditions and the following disclaimer.
lypinator	0:bb348c97df44	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
lypinator	0:bb348c97df44	16	* this list of conditions and the following disclaimer in the documentation
lypinator	0:bb348c97df44	17	* and/or other materials provided with the distribution.
lypinator	0:bb348c97df44	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
lypinator	0:bb348c97df44	19	* may be used to endorse or promote products derived from this software
lypinator	0:bb348c97df44	20	* without specific prior written permission.
lypinator	0:bb348c97df44	21	*
lypinator	0:bb348c97df44	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
lypinator	0:bb348c97df44	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
lypinator	0:bb348c97df44	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
lypinator	0:bb348c97df44	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
lypinator	0:bb348c97df44	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
lypinator	0:bb348c97df44	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
lypinator	0:bb348c97df44	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
lypinator	0:bb348c97df44	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
lypinator	0:bb348c97df44	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
lypinator	0:bb348c97df44	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
lypinator	0:bb348c97df44	32	*
lypinator	0:bb348c97df44	33	******************************************************************************
lypinator	0:bb348c97df44	34	*/
lypinator	0:bb348c97df44	35
lypinator	0:bb348c97df44	36	/* Define to prevent recursive inclusion -------------------------------------*/
lypinator	0:bb348c97df44	37	#ifndef __STM32F4xx_LL_FSMC_H
lypinator	0:bb348c97df44	38	#define __STM32F4xx_LL_FSMC_H
lypinator	0:bb348c97df44	39
lypinator	0:bb348c97df44	40	#ifdef __cplusplus
lypinator	0:bb348c97df44	41	extern "C" {
lypinator	0:bb348c97df44	42	#endif
lypinator	0:bb348c97df44	43
lypinator	0:bb348c97df44	44	/* Includes ------------------------------------------------------------------*/
lypinator	0:bb348c97df44	45	#include "stm32f4xx_hal_def.h"
lypinator	0:bb348c97df44	46
lypinator	0:bb348c97df44	47	/** @addtogroup STM32F4xx_HAL_Driver
lypinator	0:bb348c97df44	48	* @{
lypinator	0:bb348c97df44	49	*/
lypinator	0:bb348c97df44	50
lypinator	0:bb348c97df44	51	/** @addtogroup FSMC_LL
lypinator	0:bb348c97df44	52	* @{
lypinator	0:bb348c97df44	53	*/
lypinator	0:bb348c97df44	54
lypinator	0:bb348c97df44	55	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\| defined(STM32F412Zx) \|\|\
lypinator	0:bb348c97df44	56	defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
lypinator	0:bb348c97df44	57	/* Private types -------------------------------------------------------------*/
lypinator	0:bb348c97df44	58	/** @defgroup FSMC_LL_Private_Types FSMC Private Types
lypinator	0:bb348c97df44	59	* @{
lypinator	0:bb348c97df44	60	*/
lypinator	0:bb348c97df44	61
lypinator	0:bb348c97df44	62	/**
lypinator	0:bb348c97df44	63	* @brief FSMC NORSRAM Configuration Structure definition
lypinator	0:bb348c97df44	64	*/
lypinator	0:bb348c97df44	65	typedef struct
lypinator	0:bb348c97df44	66	{
lypinator	0:bb348c97df44	67	uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used.
lypinator	0:bb348c97df44	68	This parameter can be a value of @ref FSMC_NORSRAM_Bank */
lypinator	0:bb348c97df44	69
lypinator	0:bb348c97df44	70	uint32_t DataAddressMux; /*!< Specifies whether the address and data values are
lypinator	0:bb348c97df44	71	multiplexed on the data bus or not.
lypinator	0:bb348c97df44	72	This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */
lypinator	0:bb348c97df44	73
lypinator	0:bb348c97df44	74	uint32_t MemoryType; /*!< Specifies the type of external memory attached to
lypinator	0:bb348c97df44	75	the corresponding memory device.
lypinator	0:bb348c97df44	76	This parameter can be a value of @ref FSMC_Memory_Type */
lypinator	0:bb348c97df44	77
lypinator	0:bb348c97df44	78	uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
lypinator	0:bb348c97df44	79	This parameter can be a value of @ref FSMC_NORSRAM_Data_Width */
lypinator	0:bb348c97df44	80
lypinator	0:bb348c97df44	81	uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
lypinator	0:bb348c97df44	82	valid only with synchronous burst Flash memories.
lypinator	0:bb348c97df44	83	This parameter can be a value of @ref FSMC_Burst_Access_Mode */
lypinator	0:bb348c97df44	84
lypinator	0:bb348c97df44	85	uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
lypinator	0:bb348c97df44	86	the Flash memory in burst mode.
lypinator	0:bb348c97df44	87	This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */
lypinator	0:bb348c97df44	88
lypinator	0:bb348c97df44	89	uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
lypinator	0:bb348c97df44	90	memory, valid only when accessing Flash memories in burst mode.
lypinator	0:bb348c97df44	91	This parameter can be a value of @ref FSMC_Wrap_Mode
lypinator	0:bb348c97df44	92	This mode is available only for the STM32F405/407/4015/417xx devices */
lypinator	0:bb348c97df44	93
lypinator	0:bb348c97df44	94	uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
lypinator	0:bb348c97df44	95	clock cycle before the wait state or during the wait state,
lypinator	0:bb348c97df44	96	valid only when accessing memories in burst mode.
lypinator	0:bb348c97df44	97	This parameter can be a value of @ref FSMC_Wait_Timing */
lypinator	0:bb348c97df44	98
lypinator	0:bb348c97df44	99	uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FSMC.
lypinator	0:bb348c97df44	100	This parameter can be a value of @ref FSMC_Write_Operation */
lypinator	0:bb348c97df44	101
lypinator	0:bb348c97df44	102	uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait
lypinator	0:bb348c97df44	103	signal, valid for Flash memory access in burst mode.
lypinator	0:bb348c97df44	104	This parameter can be a value of @ref FSMC_Wait_Signal */
lypinator	0:bb348c97df44	105
lypinator	0:bb348c97df44	106	uint32_t ExtendedMode; /*!< Enables or disables the extended mode.
lypinator	0:bb348c97df44	107	This parameter can be a value of @ref FSMC_Extended_Mode */
lypinator	0:bb348c97df44	108
lypinator	0:bb348c97df44	109	uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
lypinator	0:bb348c97df44	110	valid only with asynchronous Flash memories.
lypinator	0:bb348c97df44	111	This parameter can be a value of @ref FSMC_AsynchronousWait */
lypinator	0:bb348c97df44	112
lypinator	0:bb348c97df44	113	uint32_t WriteBurst; /*!< Enables or disables the write burst operation.
lypinator	0:bb348c97df44	114	This parameter can be a value of @ref FSMC_Write_Burst */
lypinator	0:bb348c97df44	115
lypinator	0:bb348c97df44	116	uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices.
lypinator	0:bb348c97df44	117	This parameter is only enabled through the FMC_BCR1 register, and don't care
lypinator	0:bb348c97df44	118	through FMC_BCR2..4 registers.
lypinator	0:bb348c97df44	119	This parameter can be a value of @ref FMC_Continous_Clock
lypinator	0:bb348c97df44	120	This mode is available only for the STM32F412Vx/Zx/Rx devices */
lypinator	0:bb348c97df44	121
lypinator	0:bb348c97df44	122	uint32_t WriteFifo; /*!< Enables or disables the write FIFO used by the FMC controller.
lypinator	0:bb348c97df44	123	This parameter is only enabled through the FMC_BCR1 register, and don't care
lypinator	0:bb348c97df44	124	through FMC_BCR2..4 registers.
lypinator	0:bb348c97df44	125	This parameter can be a value of @ref FMC_Write_FIFO
lypinator	0:bb348c97df44	126	This mode is available only for the STM32F412Vx/Vx devices */
lypinator	0:bb348c97df44	127
lypinator	0:bb348c97df44	128	uint32_t PageSize; /*!< Specifies the memory page size.
lypinator	0:bb348c97df44	129	This parameter can be a value of @ref FMC_Page_Size */
lypinator	0:bb348c97df44	130	}FSMC_NORSRAM_InitTypeDef;
lypinator	0:bb348c97df44	131
lypinator	0:bb348c97df44	132	/**
lypinator	0:bb348c97df44	133	* @brief FSMC NORSRAM Timing parameters structure definition
lypinator	0:bb348c97df44	134	*/
lypinator	0:bb348c97df44	135	typedef struct
lypinator	0:bb348c97df44	136	{
lypinator	0:bb348c97df44	137	uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
lypinator	0:bb348c97df44	138	the duration of the address setup time.
lypinator	0:bb348c97df44	139	This parameter can be a value between Min_Data = 0 and Max_Data = 15.
lypinator	0:bb348c97df44	140	@note This parameter is not used with synchronous NOR Flash memories. */
lypinator	0:bb348c97df44	141
lypinator	0:bb348c97df44	142	uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
lypinator	0:bb348c97df44	143	the duration of the address hold time.
lypinator	0:bb348c97df44	144	This parameter can be a value between Min_Data = 1 and Max_Data = 15.
lypinator	0:bb348c97df44	145	@note This parameter is not used with synchronous NOR Flash memories. */
lypinator	0:bb348c97df44	146
lypinator	0:bb348c97df44	147	uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure
lypinator	0:bb348c97df44	148	the duration of the data setup time.
lypinator	0:bb348c97df44	149	This parameter can be a value between Min_Data = 1 and Max_Data = 255.
lypinator	0:bb348c97df44	150	@note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
lypinator	0:bb348c97df44	151	NOR Flash memories. */
lypinator	0:bb348c97df44	152
lypinator	0:bb348c97df44	153	uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
lypinator	0:bb348c97df44	154	the duration of the bus turnaround.
lypinator	0:bb348c97df44	155	This parameter can be a value between Min_Data = 0 and Max_Data = 15.
lypinator	0:bb348c97df44	156	@note This parameter is only used for multiplexed NOR Flash memories. */
lypinator	0:bb348c97df44	157
lypinator	0:bb348c97df44	158	uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of
lypinator	0:bb348c97df44	159	HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
lypinator	0:bb348c97df44	160	@note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
lypinator	0:bb348c97df44	161	accesses. */
lypinator	0:bb348c97df44	162
lypinator	0:bb348c97df44	163	uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue
lypinator	0:bb348c97df44	164	to the memory before getting the first data.
lypinator	0:bb348c97df44	165	The parameter value depends on the memory type as shown below:
lypinator	0:bb348c97df44	166	- It must be set to 0 in case of a CRAM
lypinator	0:bb348c97df44	167	- It is don't care in asynchronous NOR, SRAM or ROM accesses
lypinator	0:bb348c97df44	168	- It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
lypinator	0:bb348c97df44	169	with synchronous burst mode enable */
lypinator	0:bb348c97df44	170
lypinator	0:bb348c97df44	171	uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
lypinator	0:bb348c97df44	172	This parameter can be a value of @ref FSMC_Access_Mode */
lypinator	0:bb348c97df44	173
lypinator	0:bb348c97df44	174	}FSMC_NORSRAM_TimingTypeDef;
lypinator	0:bb348c97df44	175
lypinator	0:bb348c97df44	176	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx)
lypinator	0:bb348c97df44	177	/**
lypinator	0:bb348c97df44	178	* @brief FSMC NAND Configuration Structure definition
lypinator	0:bb348c97df44	179	*/
lypinator	0:bb348c97df44	180	typedef struct
lypinator	0:bb348c97df44	181	{
lypinator	0:bb348c97df44	182	uint32_t NandBank; /*!< Specifies the NAND memory device that will be used.
lypinator	0:bb348c97df44	183	This parameter can be a value of @ref FSMC_NAND_Bank */
lypinator	0:bb348c97df44	184
lypinator	0:bb348c97df44	185	uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device.
lypinator	0:bb348c97df44	186	This parameter can be any value of @ref FSMC_Wait_feature */
lypinator	0:bb348c97df44	187
lypinator	0:bb348c97df44	188	uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
lypinator	0:bb348c97df44	189	This parameter can be any value of @ref FSMC_NAND_Data_Width */
lypinator	0:bb348c97df44	190
lypinator	0:bb348c97df44	191	uint32_t EccComputation; /*!< Enables or disables the ECC computation.
lypinator	0:bb348c97df44	192	This parameter can be any value of @ref FSMC_ECC */
lypinator	0:bb348c97df44	193
lypinator	0:bb348c97df44	194	uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC.
lypinator	0:bb348c97df44	195	This parameter can be any value of @ref FSMC_ECC_Page_Size */
lypinator	0:bb348c97df44	196
lypinator	0:bb348c97df44	197	uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
lypinator	0:bb348c97df44	198	delay between CLE low and RE low.
lypinator	0:bb348c97df44	199	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
lypinator	0:bb348c97df44	200
lypinator	0:bb348c97df44	201	uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
lypinator	0:bb348c97df44	202	delay between ALE low and RE low.
lypinator	0:bb348c97df44	203	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
lypinator	0:bb348c97df44	204
lypinator	0:bb348c97df44	205	}FSMC_NAND_InitTypeDef;
lypinator	0:bb348c97df44	206
lypinator	0:bb348c97df44	207	/**
lypinator	0:bb348c97df44	208	* @brief FSMC NAND/PCCARD Timing parameters structure definition
lypinator	0:bb348c97df44	209	*/
lypinator	0:bb348c97df44	210	typedef struct
lypinator	0:bb348c97df44	211	{
lypinator	0:bb348c97df44	212	uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before
lypinator	0:bb348c97df44	213	the command assertion for NAND-Flash read or write access
lypinator	0:bb348c97df44	214	to common/Attribute or I/O memory space (depending on
lypinator	0:bb348c97df44	215	the memory space timing to be configured).
lypinator	0:bb348c97df44	216	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
lypinator	0:bb348c97df44	217
lypinator	0:bb348c97df44	218	uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
lypinator	0:bb348c97df44	219	command for NAND-Flash read or write access to
lypinator	0:bb348c97df44	220	common/Attribute or I/O memory space (depending on the
lypinator	0:bb348c97df44	221	memory space timing to be configured).
lypinator	0:bb348c97df44	222	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
lypinator	0:bb348c97df44	223
lypinator	0:bb348c97df44	224	uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
lypinator	0:bb348c97df44	225	(and data for write access) after the command de-assertion
lypinator	0:bb348c97df44	226	for NAND-Flash read or write access to common/Attribute
lypinator	0:bb348c97df44	227	or I/O memory space (depending on the memory space timing
lypinator	0:bb348c97df44	228	to be configured).
lypinator	0:bb348c97df44	229	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
lypinator	0:bb348c97df44	230
lypinator	0:bb348c97df44	231	uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
lypinator	0:bb348c97df44	232	data bus is kept in HiZ after the start of a NAND-Flash
lypinator	0:bb348c97df44	233	write access to common/Attribute or I/O memory space (depending
lypinator	0:bb348c97df44	234	on the memory space timing to be configured).
lypinator	0:bb348c97df44	235	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
lypinator	0:bb348c97df44	236
lypinator	0:bb348c97df44	237	}FSMC_NAND_PCC_TimingTypeDef;
lypinator	0:bb348c97df44	238
lypinator	0:bb348c97df44	239	/**
lypinator	0:bb348c97df44	240	* @brief FSMC NAND Configuration Structure definition
lypinator	0:bb348c97df44	241	*/
lypinator	0:bb348c97df44	242	typedef struct
lypinator	0:bb348c97df44	243	{
lypinator	0:bb348c97df44	244	uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the PCCARD Memory device.
lypinator	0:bb348c97df44	245	This parameter can be any value of @ref FSMC_Wait_feature */
lypinator	0:bb348c97df44	246
lypinator	0:bb348c97df44	247	uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
lypinator	0:bb348c97df44	248	delay between CLE low and RE low.
lypinator	0:bb348c97df44	249	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
lypinator	0:bb348c97df44	250
lypinator	0:bb348c97df44	251	uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
lypinator	0:bb348c97df44	252	delay between ALE low and RE low.
lypinator	0:bb348c97df44	253	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
lypinator	0:bb348c97df44	254
lypinator	0:bb348c97df44	255	}FSMC_PCCARD_InitTypeDef;
lypinator	0:bb348c97df44	256	/**
lypinator	0:bb348c97df44	257	* @}
lypinator	0:bb348c97df44	258	*/
lypinator	0:bb348c97df44	259	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx */
lypinator	0:bb348c97df44	260
lypinator	0:bb348c97df44	261	/* Private constants ---------------------------------------------------------*/
lypinator	0:bb348c97df44	262	/** @defgroup FSMC_LL_Private_Constants FSMC Private Constants
lypinator	0:bb348c97df44	263	* @{
lypinator	0:bb348c97df44	264	*/
lypinator	0:bb348c97df44	265
lypinator	0:bb348c97df44	266	/** @defgroup FSMC_LL_NOR_SRAM_Controller FSMC NOR/SRAM Controller
lypinator	0:bb348c97df44	267	* @{
lypinator	0:bb348c97df44	268	*/
lypinator	0:bb348c97df44	269	/** @defgroup FSMC_NORSRAM_Bank FSMC NOR/SRAM Bank
lypinator	0:bb348c97df44	270	* @{
lypinator	0:bb348c97df44	271	*/
lypinator	0:bb348c97df44	272	#define FSMC_NORSRAM_BANK1 0x00000000U
lypinator	0:bb348c97df44	273	#define FSMC_NORSRAM_BANK2 0x00000002U
lypinator	0:bb348c97df44	274	#define FSMC_NORSRAM_BANK3 0x00000004U
lypinator	0:bb348c97df44	275	#define FSMC_NORSRAM_BANK4 0x00000006U
lypinator	0:bb348c97df44	276	/**
lypinator	0:bb348c97df44	277	* @}
lypinator	0:bb348c97df44	278	*/
lypinator	0:bb348c97df44	279
lypinator	0:bb348c97df44	280	/** @defgroup FSMC_Data_Address_Bus_Multiplexing FSMC Data Address Bus Multiplexing
lypinator	0:bb348c97df44	281	* @{
lypinator	0:bb348c97df44	282	*/
lypinator	0:bb348c97df44	283	#define FSMC_DATA_ADDRESS_MUX_DISABLE 0x00000000U
lypinator	0:bb348c97df44	284	#define FSMC_DATA_ADDRESS_MUX_ENABLE 0x00000002U
lypinator	0:bb348c97df44	285	/**
lypinator	0:bb348c97df44	286	* @}
lypinator	0:bb348c97df44	287	*/
lypinator	0:bb348c97df44	288
lypinator	0:bb348c97df44	289	/** @defgroup FSMC_Memory_Type FSMC Memory Type
lypinator	0:bb348c97df44	290	* @{
lypinator	0:bb348c97df44	291	*/
lypinator	0:bb348c97df44	292	#define FSMC_MEMORY_TYPE_SRAM 0x00000000U
lypinator	0:bb348c97df44	293	#define FSMC_MEMORY_TYPE_PSRAM 0x00000004U
lypinator	0:bb348c97df44	294	#define FSMC_MEMORY_TYPE_NOR 0x00000008U
lypinator	0:bb348c97df44	295	/**
lypinator	0:bb348c97df44	296	* @}
lypinator	0:bb348c97df44	297	*/
lypinator	0:bb348c97df44	298
lypinator	0:bb348c97df44	299	/** @defgroup FSMC_NORSRAM_Data_Width FSMC NOR/SRAM Data Width
lypinator	0:bb348c97df44	300	* @{
lypinator	0:bb348c97df44	301	*/
lypinator	0:bb348c97df44	302	#define FSMC_NORSRAM_MEM_BUS_WIDTH_8 0x00000000U
lypinator	0:bb348c97df44	303	#define FSMC_NORSRAM_MEM_BUS_WIDTH_16 0x00000010U
lypinator	0:bb348c97df44	304	#define FSMC_NORSRAM_MEM_BUS_WIDTH_32 0x00000020U
lypinator	0:bb348c97df44	305	/**
lypinator	0:bb348c97df44	306	* @}
lypinator	0:bb348c97df44	307	*/
lypinator	0:bb348c97df44	308
lypinator	0:bb348c97df44	309	/** @defgroup FSMC_NORSRAM_Flash_Access FSMC NOR/SRAM Flash Access
lypinator	0:bb348c97df44	310	* @{
lypinator	0:bb348c97df44	311	*/
lypinator	0:bb348c97df44	312	#define FSMC_NORSRAM_FLASH_ACCESS_ENABLE 0x00000040U
lypinator	0:bb348c97df44	313	#define FSMC_NORSRAM_FLASH_ACCESS_DISABLE 0x00000000U
lypinator	0:bb348c97df44	314	/**
lypinator	0:bb348c97df44	315	* @}
lypinator	0:bb348c97df44	316	*/
lypinator	0:bb348c97df44	317
lypinator	0:bb348c97df44	318	/** @defgroup FSMC_Burst_Access_Mode FSMC Burst Access Mode
lypinator	0:bb348c97df44	319	* @{
lypinator	0:bb348c97df44	320	*/
lypinator	0:bb348c97df44	321	#define FSMC_BURST_ACCESS_MODE_DISABLE 0x00000000U
lypinator	0:bb348c97df44	322	#define FSMC_BURST_ACCESS_MODE_ENABLE 0x00000100U
lypinator	0:bb348c97df44	323	/**
lypinator	0:bb348c97df44	324	* @}
lypinator	0:bb348c97df44	325	*/
lypinator	0:bb348c97df44	326
lypinator	0:bb348c97df44	327	/** @defgroup FSMC_Wait_Signal_Polarity FSMC Wait Signal Polarity
lypinator	0:bb348c97df44	328	* @{
lypinator	0:bb348c97df44	329	*/
lypinator	0:bb348c97df44	330	#define FSMC_WAIT_SIGNAL_POLARITY_LOW 0x00000000U
lypinator	0:bb348c97df44	331	#define FSMC_WAIT_SIGNAL_POLARITY_HIGH 0x00000200U
lypinator	0:bb348c97df44	332	/**
lypinator	0:bb348c97df44	333	* @}
lypinator	0:bb348c97df44	334	*/
lypinator	0:bb348c97df44	335
lypinator	0:bb348c97df44	336	/** @defgroup FSMC_Wrap_Mode FSMC Wrap Mode
lypinator	0:bb348c97df44	337	* @note These values are available only for the STM32F405/415/407/417xx devices.
lypinator	0:bb348c97df44	338	* @{
lypinator	0:bb348c97df44	339	*/
lypinator	0:bb348c97df44	340	#define FSMC_WRAP_MODE_DISABLE 0x00000000U
lypinator	0:bb348c97df44	341	#define FSMC_WRAP_MODE_ENABLE 0x00000400U
lypinator	0:bb348c97df44	342	/**
lypinator	0:bb348c97df44	343	* @}
lypinator	0:bb348c97df44	344	*/
lypinator	0:bb348c97df44	345
lypinator	0:bb348c97df44	346	/** @defgroup FSMC_Wait_Timing FSMC Wait Timing
lypinator	0:bb348c97df44	347	* @{
lypinator	0:bb348c97df44	348	*/
lypinator	0:bb348c97df44	349	#define FSMC_WAIT_TIMING_BEFORE_WS 0x00000000U
lypinator	0:bb348c97df44	350	#define FSMC_WAIT_TIMING_DURING_WS 0x00000800U
lypinator	0:bb348c97df44	351	/**
lypinator	0:bb348c97df44	352	* @}
lypinator	0:bb348c97df44	353	*/
lypinator	0:bb348c97df44	354
lypinator	0:bb348c97df44	355	/** @defgroup FSMC_Write_Operation FSMC Write Operation
lypinator	0:bb348c97df44	356	* @{
lypinator	0:bb348c97df44	357	*/
lypinator	0:bb348c97df44	358	#define FSMC_WRITE_OPERATION_DISABLE 0x00000000U
lypinator	0:bb348c97df44	359	#define FSMC_WRITE_OPERATION_ENABLE 0x00001000U
lypinator	0:bb348c97df44	360	/**
lypinator	0:bb348c97df44	361	* @}
lypinator	0:bb348c97df44	362	*/
lypinator	0:bb348c97df44	363
lypinator	0:bb348c97df44	364	/** @defgroup FSMC_Wait_Signal FSMC Wait Signal
lypinator	0:bb348c97df44	365	* @{
lypinator	0:bb348c97df44	366	*/
lypinator	0:bb348c97df44	367	#define FSMC_WAIT_SIGNAL_DISABLE 0x00000000U
lypinator	0:bb348c97df44	368	#define FSMC_WAIT_SIGNAL_ENABLE 0x00002000U
lypinator	0:bb348c97df44	369	/**
lypinator	0:bb348c97df44	370	* @}
lypinator	0:bb348c97df44	371	*/
lypinator	0:bb348c97df44	372
lypinator	0:bb348c97df44	373	/** @defgroup FSMC_Extended_Mode FSMC Extended Mode
lypinator	0:bb348c97df44	374	* @{
lypinator	0:bb348c97df44	375	*/
lypinator	0:bb348c97df44	376	#define FSMC_EXTENDED_MODE_DISABLE 0x00000000U
lypinator	0:bb348c97df44	377	#define FSMC_EXTENDED_MODE_ENABLE 0x00004000U
lypinator	0:bb348c97df44	378	/**
lypinator	0:bb348c97df44	379	* @}
lypinator	0:bb348c97df44	380	*/
lypinator	0:bb348c97df44	381
lypinator	0:bb348c97df44	382	/** @defgroup FSMC_AsynchronousWait FSMC Asynchronous Wait
lypinator	0:bb348c97df44	383	* @{
lypinator	0:bb348c97df44	384	*/
lypinator	0:bb348c97df44	385	#define FSMC_ASYNCHRONOUS_WAIT_DISABLE 0x00000000U
lypinator	0:bb348c97df44	386	#define FSMC_ASYNCHRONOUS_WAIT_ENABLE 0x00008000U
lypinator	0:bb348c97df44	387	/**
lypinator	0:bb348c97df44	388	* @}
lypinator	0:bb348c97df44	389	*/
lypinator	0:bb348c97df44	390
lypinator	0:bb348c97df44	391	/** @defgroup FSMC_Page_Size FSMC Page Size
lypinator	0:bb348c97df44	392	* @{
lypinator	0:bb348c97df44	393	*/
lypinator	0:bb348c97df44	394	#define FSMC_PAGE_SIZE_NONE 0x00000000U
lypinator	0:bb348c97df44	395	#define FSMC_PAGE_SIZE_128 ((uint32_t)FSMC_BCR1_CPSIZE_0)
lypinator	0:bb348c97df44	396	#define FSMC_PAGE_SIZE_256 ((uint32_t)FSMC_BCR1_CPSIZE_1)
lypinator	0:bb348c97df44	397	#define FSMC_PAGE_SIZE_512 ((uint32_t)(FSMC_BCR1_CPSIZE_0 \| FSMC_BCR1_CPSIZE_1))
lypinator	0:bb348c97df44	398	#define FSMC_PAGE_SIZE_1024 ((uint32_t)FSMC_BCR1_CPSIZE_2)
lypinator	0:bb348c97df44	399	/**
lypinator	0:bb348c97df44	400	* @}
lypinator	0:bb348c97df44	401	*/
lypinator	0:bb348c97df44	402
lypinator	0:bb348c97df44	403	/** @defgroup FSMC_Write_FIFO FSMC Write FIFO
lypinator	0:bb348c97df44	404	* @note These values are available only for the STM32F412Vx/Zx/Rx devices.
lypinator	0:bb348c97df44	405	* @{
lypinator	0:bb348c97df44	406	*/
lypinator	0:bb348c97df44	407	#define FSMC_WRITE_FIFO_DISABLE ((uint32_t)FSMC_BCR1_WFDIS)
lypinator	0:bb348c97df44	408	#define FSMC_WRITE_FIFO_ENABLE 0x00000000U
lypinator	0:bb348c97df44	409	/**
lypinator	0:bb348c97df44	410	* @}
lypinator	0:bb348c97df44	411	*/
lypinator	0:bb348c97df44	412
lypinator	0:bb348c97df44	413	/** @defgroup FSMC_Write_Burst FSMC Write Burst
lypinator	0:bb348c97df44	414	* @{
lypinator	0:bb348c97df44	415	*/
lypinator	0:bb348c97df44	416	#define FSMC_WRITE_BURST_DISABLE 0x00000000U
lypinator	0:bb348c97df44	417	#define FSMC_WRITE_BURST_ENABLE 0x00080000U
lypinator	0:bb348c97df44	418	/**
lypinator	0:bb348c97df44	419	* @}
lypinator	0:bb348c97df44	420	*/
lypinator	0:bb348c97df44	421
lypinator	0:bb348c97df44	422	/** @defgroup FSMC_Continous_Clock FSMC Continous Clock
lypinator	0:bb348c97df44	423	* @note These values are available only for the STM32F412Vx/Zx/Rx devices.
lypinator	0:bb348c97df44	424	* @{
lypinator	0:bb348c97df44	425	*/
lypinator	0:bb348c97df44	426	#define FSMC_CONTINUOUS_CLOCK_SYNC_ONLY 0x00000000U
lypinator	0:bb348c97df44	427	#define FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC 0x00100000U
lypinator	0:bb348c97df44	428	/**
lypinator	0:bb348c97df44	429	* @}
lypinator	0:bb348c97df44	430	*/
lypinator	0:bb348c97df44	431
lypinator	0:bb348c97df44	432	/** @defgroup FSMC_Access_Mode FSMC Access Mode
lypinator	0:bb348c97df44	433	* @{
lypinator	0:bb348c97df44	434	*/
lypinator	0:bb348c97df44	435	#define FSMC_ACCESS_MODE_A 0x00000000U
lypinator	0:bb348c97df44	436	#define FSMC_ACCESS_MODE_B 0x10000000U
lypinator	0:bb348c97df44	437	#define FSMC_ACCESS_MODE_C 0x20000000U
lypinator	0:bb348c97df44	438	#define FSMC_ACCESS_MODE_D 0x30000000U
lypinator	0:bb348c97df44	439	/**
lypinator	0:bb348c97df44	440	* @}
lypinator	0:bb348c97df44	441	*/
lypinator	0:bb348c97df44	442	/**
lypinator	0:bb348c97df44	443	* @}
lypinator	0:bb348c97df44	444	*/
lypinator	0:bb348c97df44	445
lypinator	0:bb348c97df44	446	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx)
lypinator	0:bb348c97df44	447	/** @defgroup FSMC_LL_NAND_Controller FSMC NAND and PCCARD Controller
lypinator	0:bb348c97df44	448	* @{
lypinator	0:bb348c97df44	449	*/
lypinator	0:bb348c97df44	450	/** @defgroup FSMC_NAND_Bank FSMC NAND Bank
lypinator	0:bb348c97df44	451	* @{
lypinator	0:bb348c97df44	452	*/
lypinator	0:bb348c97df44	453	#define FSMC_NAND_BANK2 0x00000010U
lypinator	0:bb348c97df44	454	#define FSMC_NAND_BANK3 0x00000100U
lypinator	0:bb348c97df44	455	/**
lypinator	0:bb348c97df44	456	* @}
lypinator	0:bb348c97df44	457	*/
lypinator	0:bb348c97df44	458
lypinator	0:bb348c97df44	459	/** @defgroup FSMC_Wait_feature FSMC Wait feature
lypinator	0:bb348c97df44	460	* @{
lypinator	0:bb348c97df44	461	*/
lypinator	0:bb348c97df44	462	#define FSMC_NAND_PCC_WAIT_FEATURE_DISABLE 0x00000000U
lypinator	0:bb348c97df44	463	#define FSMC_NAND_PCC_WAIT_FEATURE_ENABLE 0x00000002U
lypinator	0:bb348c97df44	464	/**
lypinator	0:bb348c97df44	465	* @}
lypinator	0:bb348c97df44	466	*/
lypinator	0:bb348c97df44	467
lypinator	0:bb348c97df44	468	/** @defgroup FSMC_PCR_Memory_Type FSMC PCR Memory Type
lypinator	0:bb348c97df44	469	* @{
lypinator	0:bb348c97df44	470	*/
lypinator	0:bb348c97df44	471	#define FSMC_PCR_MEMORY_TYPE_PCCARD 0x00000000U
lypinator	0:bb348c97df44	472	#define FSMC_PCR_MEMORY_TYPE_NAND 0x00000008U
lypinator	0:bb348c97df44	473	/**
lypinator	0:bb348c97df44	474	* @}
lypinator	0:bb348c97df44	475	*/
lypinator	0:bb348c97df44	476
lypinator	0:bb348c97df44	477	/** @defgroup FSMC_NAND_Data_Width FSMC NAND Data Width
lypinator	0:bb348c97df44	478	* @{
lypinator	0:bb348c97df44	479	*/
lypinator	0:bb348c97df44	480	#define FSMC_NAND_PCC_MEM_BUS_WIDTH_8 0x00000000U
lypinator	0:bb348c97df44	481	#define FSMC_NAND_PCC_MEM_BUS_WIDTH_16 0x00000010U
lypinator	0:bb348c97df44	482	/**
lypinator	0:bb348c97df44	483	* @}
lypinator	0:bb348c97df44	484	*/
lypinator	0:bb348c97df44	485
lypinator	0:bb348c97df44	486	/** @defgroup FSMC_ECC FSMC ECC
lypinator	0:bb348c97df44	487	* @{
lypinator	0:bb348c97df44	488	*/
lypinator	0:bb348c97df44	489	#define FSMC_NAND_ECC_DISABLE 0x00000000U
lypinator	0:bb348c97df44	490	#define FSMC_NAND_ECC_ENABLE 0x00000040U
lypinator	0:bb348c97df44	491	/**
lypinator	0:bb348c97df44	492	* @}
lypinator	0:bb348c97df44	493	*/
lypinator	0:bb348c97df44	494
lypinator	0:bb348c97df44	495	/** @defgroup FSMC_ECC_Page_Size FSMC ECC Page Size
lypinator	0:bb348c97df44	496	* @{
lypinator	0:bb348c97df44	497	*/
lypinator	0:bb348c97df44	498	#define FSMC_NAND_ECC_PAGE_SIZE_256BYTE 0x00000000U
lypinator	0:bb348c97df44	499	#define FSMC_NAND_ECC_PAGE_SIZE_512BYTE 0x00020000U
lypinator	0:bb348c97df44	500	#define FSMC_NAND_ECC_PAGE_SIZE_1024BYTE 0x00040000U
lypinator	0:bb348c97df44	501	#define FSMC_NAND_ECC_PAGE_SIZE_2048BYTE 0x00060000U
lypinator	0:bb348c97df44	502	#define FSMC_NAND_ECC_PAGE_SIZE_4096BYTE 0x00080000U
lypinator	0:bb348c97df44	503	#define FSMC_NAND_ECC_PAGE_SIZE_8192BYTE 0x000A0000U
lypinator	0:bb348c97df44	504	/**
lypinator	0:bb348c97df44	505	* @}
lypinator	0:bb348c97df44	506	*/
lypinator	0:bb348c97df44	507	/**
lypinator	0:bb348c97df44	508	* @}
lypinator	0:bb348c97df44	509	*/
lypinator	0:bb348c97df44	510	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx */
lypinator	0:bb348c97df44	511
lypinator	0:bb348c97df44	512	/** @defgroup FSMC_LL_Interrupt_definition FSMC Interrupt definition
lypinator	0:bb348c97df44	513	* @{
lypinator	0:bb348c97df44	514	*/
lypinator	0:bb348c97df44	515	#define FSMC_IT_RISING_EDGE 0x00000008U
lypinator	0:bb348c97df44	516	#define FSMC_IT_LEVEL 0x00000010U
lypinator	0:bb348c97df44	517	#define FSMC_IT_FALLING_EDGE 0x00000020U
lypinator	0:bb348c97df44	518	#define FSMC_IT_REFRESH_ERROR 0x00004000U
lypinator	0:bb348c97df44	519	/**
lypinator	0:bb348c97df44	520	* @}
lypinator	0:bb348c97df44	521	*/
lypinator	0:bb348c97df44	522
lypinator	0:bb348c97df44	523	/** @defgroup FSMC_LL_Flag_definition FSMC Flag definition
lypinator	0:bb348c97df44	524	* @{
lypinator	0:bb348c97df44	525	*/
lypinator	0:bb348c97df44	526	#define FSMC_FLAG_RISING_EDGE 0x00000001U
lypinator	0:bb348c97df44	527	#define FSMC_FLAG_LEVEL 0x00000002U
lypinator	0:bb348c97df44	528	#define FSMC_FLAG_FALLING_EDGE 0x00000004U
lypinator	0:bb348c97df44	529	#define FSMC_FLAG_FEMPT 0x00000040U
lypinator	0:bb348c97df44	530	/**
lypinator	0:bb348c97df44	531	* @}
lypinator	0:bb348c97df44	532	*/
lypinator	0:bb348c97df44	533
lypinator	0:bb348c97df44	534	/** @defgroup FSMC_LL_Alias_definition FSMC Alias definition
lypinator	0:bb348c97df44	535	* @{
lypinator	0:bb348c97df44	536	*/
lypinator	0:bb348c97df44	537	#define FSMC_NORSRAM_TypeDef FSMC_Bank1_TypeDef
lypinator	0:bb348c97df44	538	#define FSMC_NORSRAM_EXTENDED_TypeDef FSMC_Bank1E_TypeDef
lypinator	0:bb348c97df44	539	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx)
lypinator	0:bb348c97df44	540	#define FSMC_NAND_TypeDef FSMC_Bank2_3_TypeDef
lypinator	0:bb348c97df44	541	#define FSMC_PCCARD_TypeDef FSMC_Bank4_TypeDef
lypinator	0:bb348c97df44	542	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx */
lypinator	0:bb348c97df44	543
lypinator	0:bb348c97df44	544	#define FSMC_NORSRAM_DEVICE FSMC_Bank1
lypinator	0:bb348c97df44	545	#define FSMC_NORSRAM_EXTENDED_DEVICE FSMC_Bank1E
lypinator	0:bb348c97df44	546	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx)
lypinator	0:bb348c97df44	547	#define FSMC_NAND_DEVICE FSMC_Bank2_3
lypinator	0:bb348c97df44	548	#define FSMC_PCCARD_DEVICE FSMC_Bank4
lypinator	0:bb348c97df44	549	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx */
lypinator	0:bb348c97df44	550
lypinator	0:bb348c97df44	551	#define FMC_NORSRAM_MEM_BUS_WIDTH_8 FSMC_NORSRAM_MEM_BUS_WIDTH_8
lypinator	0:bb348c97df44	552	#define FMC_NORSRAM_MEM_BUS_WIDTH_16 FSMC_NORSRAM_MEM_BUS_WIDTH_16
lypinator	0:bb348c97df44	553	#define FMC_NORSRAM_MEM_BUS_WIDTH_32 FSMC_NORSRAM_MEM_BUS_WIDTH_32
lypinator	0:bb348c97df44	554
lypinator	0:bb348c97df44	555	#define FMC_NORSRAM_TypeDef FSMC_NORSRAM_TypeDef
lypinator	0:bb348c97df44	556	#define FMC_NORSRAM_EXTENDED_TypeDef FSMC_NORSRAM_EXTENDED_TypeDef
lypinator	0:bb348c97df44	557	#define FMC_NORSRAM_InitTypeDef FSMC_NORSRAM_InitTypeDef
lypinator	0:bb348c97df44	558	#define FMC_NORSRAM_TimingTypeDef FSMC_NORSRAM_TimingTypeDef
lypinator	0:bb348c97df44	559
lypinator	0:bb348c97df44	560	#define FMC_NORSRAM_Init FSMC_NORSRAM_Init
lypinator	0:bb348c97df44	561	#define FMC_NORSRAM_Timing_Init FSMC_NORSRAM_Timing_Init
lypinator	0:bb348c97df44	562	#define FMC_NORSRAM_Extended_Timing_Init FSMC_NORSRAM_Extended_Timing_Init
lypinator	0:bb348c97df44	563	#define FMC_NORSRAM_DeInit FSMC_NORSRAM_DeInit
lypinator	0:bb348c97df44	564	#define FMC_NORSRAM_WriteOperation_Enable FSMC_NORSRAM_WriteOperation_Enable
lypinator	0:bb348c97df44	565	#define FMC_NORSRAM_WriteOperation_Disable FSMC_NORSRAM_WriteOperation_Disable
lypinator	0:bb348c97df44	566
lypinator	0:bb348c97df44	567	#define __FMC_NORSRAM_ENABLE __FSMC_NORSRAM_ENABLE
lypinator	0:bb348c97df44	568	#define __FMC_NORSRAM_DISABLE __FSMC_NORSRAM_DISABLE
lypinator	0:bb348c97df44	569
lypinator	0:bb348c97df44	570	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx)
lypinator	0:bb348c97df44	571	#define FMC_NAND_InitTypeDef FSMC_NAND_InitTypeDef
lypinator	0:bb348c97df44	572	#define FMC_PCCARD_InitTypeDef FSMC_PCCARD_InitTypeDef
lypinator	0:bb348c97df44	573	#define FMC_NAND_PCC_TimingTypeDef FSMC_NAND_PCC_TimingTypeDef
lypinator	0:bb348c97df44	574
lypinator	0:bb348c97df44	575	#define FMC_NAND_Init FSMC_NAND_Init
lypinator	0:bb348c97df44	576	#define FMC_NAND_CommonSpace_Timing_Init FSMC_NAND_CommonSpace_Timing_Init
lypinator	0:bb348c97df44	577	#define FMC_NAND_AttributeSpace_Timing_Init FSMC_NAND_AttributeSpace_Timing_Init
lypinator	0:bb348c97df44	578	#define FMC_NAND_DeInit FSMC_NAND_DeInit
lypinator	0:bb348c97df44	579	#define FMC_NAND_ECC_Enable FSMC_NAND_ECC_Enable
lypinator	0:bb348c97df44	580	#define FMC_NAND_ECC_Disable FSMC_NAND_ECC_Disable
lypinator	0:bb348c97df44	581	#define FMC_NAND_GetECC FSMC_NAND_GetECC
lypinator	0:bb348c97df44	582	#define FMC_PCCARD_Init FSMC_PCCARD_Init
lypinator	0:bb348c97df44	583	#define FMC_PCCARD_CommonSpace_Timing_Init FSMC_PCCARD_CommonSpace_Timing_Init
lypinator	0:bb348c97df44	584	#define FMC_PCCARD_AttributeSpace_Timing_Init FSMC_PCCARD_AttributeSpace_Timing_Init
lypinator	0:bb348c97df44	585	#define FMC_PCCARD_IOSpace_Timing_Init FSMC_PCCARD_IOSpace_Timing_Init
lypinator	0:bb348c97df44	586	#define FMC_PCCARD_DeInit FSMC_PCCARD_DeInit
lypinator	0:bb348c97df44	587
lypinator	0:bb348c97df44	588	#define __FMC_NAND_ENABLE __FSMC_NAND_ENABLE
lypinator	0:bb348c97df44	589	#define __FMC_NAND_DISABLE __FSMC_NAND_DISABLE
lypinator	0:bb348c97df44	590	#define __FMC_PCCARD_ENABLE __FSMC_PCCARD_ENABLE
lypinator	0:bb348c97df44	591	#define __FMC_PCCARD_DISABLE __FSMC_PCCARD_DISABLE
lypinator	0:bb348c97df44	592	#define __FMC_NAND_ENABLE_IT __FSMC_NAND_ENABLE_IT
lypinator	0:bb348c97df44	593	#define __FMC_NAND_DISABLE_IT __FSMC_NAND_DISABLE_IT
lypinator	0:bb348c97df44	594	#define __FMC_NAND_GET_FLAG __FSMC_NAND_GET_FLAG
lypinator	0:bb348c97df44	595	#define __FMC_NAND_CLEAR_FLAG __FSMC_NAND_CLEAR_FLAG
lypinator	0:bb348c97df44	596	#define __FMC_PCCARD_ENABLE_IT __FSMC_PCCARD_ENABLE_IT
lypinator	0:bb348c97df44	597	#define __FMC_PCCARD_DISABLE_IT __FSMC_PCCARD_DISABLE_IT
lypinator	0:bb348c97df44	598	#define __FMC_PCCARD_GET_FLAG __FSMC_PCCARD_GET_FLAG
lypinator	0:bb348c97df44	599	#define __FMC_PCCARD_CLEAR_FLAG __FSMC_PCCARD_CLEAR_FLAG
lypinator	0:bb348c97df44	600	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx */
lypinator	0:bb348c97df44	601
lypinator	0:bb348c97df44	602	#define FMC_NORSRAM_TypeDef FSMC_NORSRAM_TypeDef
lypinator	0:bb348c97df44	603	#define FMC_NORSRAM_EXTENDED_TypeDef FSMC_NORSRAM_EXTENDED_TypeDef
lypinator	0:bb348c97df44	604	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx)
lypinator	0:bb348c97df44	605	#define FMC_NAND_TypeDef FSMC_NAND_TypeDef
lypinator	0:bb348c97df44	606	#define FMC_PCCARD_TypeDef FSMC_PCCARD_TypeDef
lypinator	0:bb348c97df44	607	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx */
lypinator	0:bb348c97df44	608
lypinator	0:bb348c97df44	609	#define FMC_NORSRAM_DEVICE FSMC_NORSRAM_DEVICE
lypinator	0:bb348c97df44	610	#define FMC_NORSRAM_EXTENDED_DEVICE FSMC_NORSRAM_EXTENDED_DEVICE
lypinator	0:bb348c97df44	611	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx)
lypinator	0:bb348c97df44	612	#define FMC_NAND_DEVICE FSMC_NAND_DEVICE
lypinator	0:bb348c97df44	613	#define FMC_PCCARD_DEVICE FSMC_PCCARD_DEVICE
lypinator	0:bb348c97df44	614
lypinator	0:bb348c97df44	615	#define FMC_NAND_BANK2 FSMC_NAND_BANK2
lypinator	0:bb348c97df44	616	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx */
lypinator	0:bb348c97df44	617
lypinator	0:bb348c97df44	618	#define FMC_NORSRAM_BANK1 FSMC_NORSRAM_BANK1
lypinator	0:bb348c97df44	619	#define FMC_NORSRAM_BANK2 FSMC_NORSRAM_BANK2
lypinator	0:bb348c97df44	620	#define FMC_NORSRAM_BANK3 FSMC_NORSRAM_BANK3
lypinator	0:bb348c97df44	621
lypinator	0:bb348c97df44	622	#define FMC_IT_RISING_EDGE FSMC_IT_RISING_EDGE
lypinator	0:bb348c97df44	623	#define FMC_IT_LEVEL FSMC_IT_LEVEL
lypinator	0:bb348c97df44	624	#define FMC_IT_FALLING_EDGE FSMC_IT_FALLING_EDGE
lypinator	0:bb348c97df44	625	#define FMC_IT_REFRESH_ERROR FSMC_IT_REFRESH_ERROR
lypinator	0:bb348c97df44	626
lypinator	0:bb348c97df44	627	#define FMC_FLAG_RISING_EDGE FSMC_FLAG_RISING_EDGE
lypinator	0:bb348c97df44	628	#define FMC_FLAG_LEVEL FSMC_FLAG_LEVEL
lypinator	0:bb348c97df44	629	#define FMC_FLAG_FALLING_EDGE FSMC_FLAG_FALLING_EDGE
lypinator	0:bb348c97df44	630	#define FMC_FLAG_FEMPT FSMC_FLAG_FEMPT
lypinator	0:bb348c97df44	631	/**
lypinator	0:bb348c97df44	632	* @}
lypinator	0:bb348c97df44	633	*/
lypinator	0:bb348c97df44	634
lypinator	0:bb348c97df44	635	/**
lypinator	0:bb348c97df44	636	* @}
lypinator	0:bb348c97df44	637	*/
lypinator	0:bb348c97df44	638
lypinator	0:bb348c97df44	639	/* Private macro -------------------------------------------------------------*/
lypinator	0:bb348c97df44	640	/** @defgroup FSMC_LL_Private_Macros FSMC Private Macros
lypinator	0:bb348c97df44	641	* @{
lypinator	0:bb348c97df44	642	*/
lypinator	0:bb348c97df44	643
lypinator	0:bb348c97df44	644	/** @defgroup FSMC_LL_NOR_Macros FSMC NOR/SRAM Exported Macros
lypinator	0:bb348c97df44	645	* @brief macros to handle NOR device enable/disable and read/write operations
lypinator	0:bb348c97df44	646	* @{
lypinator	0:bb348c97df44	647	*/
lypinator	0:bb348c97df44	648	/**
lypinator	0:bb348c97df44	649	* @brief Enable the NORSRAM device access.
lypinator	0:bb348c97df44	650	* @param __INSTANCE__ FSMC_NORSRAM Instance
lypinator	0:bb348c97df44	651	* @param __BANK__ FSMC_NORSRAM Bank
lypinator	0:bb348c97df44	652	* @retval none
lypinator	0:bb348c97df44	653	*/
lypinator	0:bb348c97df44	654	#define __FSMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] \|= FSMC_BCR1_MBKEN)
lypinator	0:bb348c97df44	655
lypinator	0:bb348c97df44	656	/**
lypinator	0:bb348c97df44	657	* @brief Disable the NORSRAM device access.
lypinator	0:bb348c97df44	658	* @param __INSTANCE__ FSMC_NORSRAM Instance
lypinator	0:bb348c97df44	659	* @param __BANK__ FSMC_NORSRAM Bank
lypinator	0:bb348c97df44	660	* @retval none
lypinator	0:bb348c97df44	661	*/
lypinator	0:bb348c97df44	662	#define __FSMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FSMC_BCR1_MBKEN)
lypinator	0:bb348c97df44	663	/**
lypinator	0:bb348c97df44	664	* @}
lypinator	0:bb348c97df44	665	*/
lypinator	0:bb348c97df44	666
lypinator	0:bb348c97df44	667	/** @defgroup FSMC_LL_NAND_Macros FSMC NAND Macros
lypinator	0:bb348c97df44	668	* @brief macros to handle NAND device enable/disable
lypinator	0:bb348c97df44	669	* @{
lypinator	0:bb348c97df44	670	*/
lypinator	0:bb348c97df44	671	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx)
lypinator	0:bb348c97df44	672	/**
lypinator	0:bb348c97df44	673	* @brief Enable the NAND device access.
lypinator	0:bb348c97df44	674	* @param __INSTANCE__ FSMC_NAND Instance
lypinator	0:bb348c97df44	675	* @param __BANK__ FSMC_NAND Bank
lypinator	0:bb348c97df44	676	* @retval none
lypinator	0:bb348c97df44	677	*/
lypinator	0:bb348c97df44	678	#define __FSMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 \|= FSMC_PCR2_PBKEN): \
lypinator	0:bb348c97df44	679	((__INSTANCE__)->PCR3 \|= FSMC_PCR3_PBKEN))
lypinator	0:bb348c97df44	680
lypinator	0:bb348c97df44	681	/**
lypinator	0:bb348c97df44	682	* @brief Disable the NAND device access.
lypinator	0:bb348c97df44	683	* @param __INSTANCE__ FSMC_NAND Instance
lypinator	0:bb348c97df44	684	* @param __BANK__ FSMC_NAND Bank
lypinator	0:bb348c97df44	685	* @retval none
lypinator	0:bb348c97df44	686	*/
lypinator	0:bb348c97df44	687	#define __FSMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 &= ~FSMC_PCR2_PBKEN): \
lypinator	0:bb348c97df44	688	((__INSTANCE__)->PCR3 &= ~FSMC_PCR3_PBKEN))
lypinator	0:bb348c97df44	689	/**
lypinator	0:bb348c97df44	690	* @}
lypinator	0:bb348c97df44	691	*/
lypinator	0:bb348c97df44	692
lypinator	0:bb348c97df44	693	/** @defgroup FSMC_LL_PCCARD_Macros FSMC PCCARD Macros
lypinator	0:bb348c97df44	694	* @brief macros to handle SRAM read/write operations
lypinator	0:bb348c97df44	695	* @{
lypinator	0:bb348c97df44	696	*/
lypinator	0:bb348c97df44	697	/**
lypinator	0:bb348c97df44	698	* @brief Enable the PCCARD device access.
lypinator	0:bb348c97df44	699	* @param __INSTANCE__ FSMC_PCCARD Instance
lypinator	0:bb348c97df44	700	* @retval none
lypinator	0:bb348c97df44	701	*/
lypinator	0:bb348c97df44	702	#define __FSMC_PCCARD_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 \|= FSMC_PCR4_PBKEN)
lypinator	0:bb348c97df44	703
lypinator	0:bb348c97df44	704	/**
lypinator	0:bb348c97df44	705	* @brief Disable the PCCARD device access.
lypinator	0:bb348c97df44	706	* @param __INSTANCE__ FSMC_PCCARD Instance
lypinator	0:bb348c97df44	707	* @retval none
lypinator	0:bb348c97df44	708	*/
lypinator	0:bb348c97df44	709	#define __FSMC_PCCARD_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 &= ~FSMC_PCR4_PBKEN)
lypinator	0:bb348c97df44	710	/**
lypinator	0:bb348c97df44	711	* @}
lypinator	0:bb348c97df44	712	*/
lypinator	0:bb348c97df44	713
lypinator	0:bb348c97df44	714	/** @defgroup FSMC_LL_Flag_Interrupt_Macros FSMC Flag&Interrupt Macros
lypinator	0:bb348c97df44	715	* @brief macros to handle FSMC flags and interrupts
lypinator	0:bb348c97df44	716	* @{
lypinator	0:bb348c97df44	717	*/
lypinator	0:bb348c97df44	718	/**
lypinator	0:bb348c97df44	719	* @brief Enable the NAND device interrupt.
lypinator	0:bb348c97df44	720	* @param __INSTANCE__ FSMC_NAND Instance
lypinator	0:bb348c97df44	721	* @param __BANK__ FSMC_NAND Bank
lypinator	0:bb348c97df44	722	* @param __INTERRUPT__ FSMC_NAND interrupt
lypinator	0:bb348c97df44	723	* This parameter can be any combination of the following values:
lypinator	0:bb348c97df44	724	* @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
lypinator	0:bb348c97df44	725	* @arg FSMC_IT_LEVEL: Interrupt level.
lypinator	0:bb348c97df44	726	* @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
lypinator	0:bb348c97df44	727	* @retval None
lypinator	0:bb348c97df44	728	*/
lypinator	0:bb348c97df44	729	#define __FSMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 \|= (__INTERRUPT__)): \
lypinator	0:bb348c97df44	730	((__INSTANCE__)->SR3 \|= (__INTERRUPT__)))
lypinator	0:bb348c97df44	731
lypinator	0:bb348c97df44	732	/**
lypinator	0:bb348c97df44	733	* @brief Disable the NAND device interrupt.
lypinator	0:bb348c97df44	734	* @param __INSTANCE__ FSMC_NAND Instance
lypinator	0:bb348c97df44	735	* @param __BANK__ FSMC_NAND Bank
lypinator	0:bb348c97df44	736	* @param __INTERRUPT__ FSMC_NAND interrupt
lypinator	0:bb348c97df44	737	* This parameter can be any combination of the following values:
lypinator	0:bb348c97df44	738	* @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
lypinator	0:bb348c97df44	739	* @arg FSMC_IT_LEVEL: Interrupt level.
lypinator	0:bb348c97df44	740	* @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
lypinator	0:bb348c97df44	741	* @retval None
lypinator	0:bb348c97df44	742	*/
lypinator	0:bb348c97df44	743	#define __FSMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)): \
lypinator	0:bb348c97df44	744	((__INSTANCE__)->SR3 &= ~(__INTERRUPT__)))
lypinator	0:bb348c97df44	745
lypinator	0:bb348c97df44	746	/**
lypinator	0:bb348c97df44	747	* @brief Get flag status of the NAND device.
lypinator	0:bb348c97df44	748	* @param __INSTANCE__ FSMC_NAND Instance
lypinator	0:bb348c97df44	749	* @param __BANK__ FSMC_NAND Bank
lypinator	0:bb348c97df44	750	* @param __FLAG__ FSMC_NAND flag
lypinator	0:bb348c97df44	751	* This parameter can be any combination of the following values:
lypinator	0:bb348c97df44	752	* @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
lypinator	0:bb348c97df44	753	* @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
lypinator	0:bb348c97df44	754	* @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
lypinator	0:bb348c97df44	755	* @arg FSMC_FLAG_FEMPT: FIFO empty flag.
lypinator	0:bb348c97df44	756	* @retval The state of FLAG (SET or RESET).
lypinator	0:bb348c97df44	757	*/
lypinator	0:bb348c97df44	758	#define __FSMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \
lypinator	0:bb348c97df44	759	(((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
lypinator	0:bb348c97df44	760
lypinator	0:bb348c97df44	761	/**
lypinator	0:bb348c97df44	762	* @brief Clear flag status of the NAND device.
lypinator	0:bb348c97df44	763	* @param __INSTANCE__ FSMC_NAND Instance
lypinator	0:bb348c97df44	764	* @param __BANK__ FSMC_NAND Bank
lypinator	0:bb348c97df44	765	* @param __FLAG__ FSMC_NAND flag
lypinator	0:bb348c97df44	766	* This parameter can be any combination of the following values:
lypinator	0:bb348c97df44	767	* @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
lypinator	0:bb348c97df44	768	* @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
lypinator	0:bb348c97df44	769	* @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
lypinator	0:bb348c97df44	770	* @arg FSMC_FLAG_FEMPT: FIFO empty flag.
lypinator	0:bb348c97df44	771	* @retval None
lypinator	0:bb348c97df44	772	*/
lypinator	0:bb348c97df44	773	#define __FSMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__FLAG__)): \
lypinator	0:bb348c97df44	774	((__INSTANCE__)->SR3 &= ~(__FLAG__)))
lypinator	0:bb348c97df44	775
lypinator	0:bb348c97df44	776	/**
lypinator	0:bb348c97df44	777	* @brief Enable the PCCARD device interrupt.
lypinator	0:bb348c97df44	778	* @param __INSTANCE__ FSMC_PCCARD Instance
lypinator	0:bb348c97df44	779	* @param __INTERRUPT__ FSMC_PCCARD interrupt
lypinator	0:bb348c97df44	780	* This parameter can be any combination of the following values:
lypinator	0:bb348c97df44	781	* @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
lypinator	0:bb348c97df44	782	* @arg FSMC_IT_LEVEL: Interrupt level.
lypinator	0:bb348c97df44	783	* @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
lypinator	0:bb348c97df44	784	* @retval None
lypinator	0:bb348c97df44	785	*/
lypinator	0:bb348c97df44	786	#define __FSMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 \|= (__INTERRUPT__))
lypinator	0:bb348c97df44	787
lypinator	0:bb348c97df44	788	/**
lypinator	0:bb348c97df44	789	* @brief Disable the PCCARD device interrupt.
lypinator	0:bb348c97df44	790	* @param __INSTANCE__ FSMC_PCCARD Instance
lypinator	0:bb348c97df44	791	* @param __INTERRUPT__ FSMC_PCCARD interrupt
lypinator	0:bb348c97df44	792	* This parameter can be any combination of the following values:
lypinator	0:bb348c97df44	793	* @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
lypinator	0:bb348c97df44	794	* @arg FSMC_IT_LEVEL: Interrupt level.
lypinator	0:bb348c97df44	795	* @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
lypinator	0:bb348c97df44	796	* @retval None
lypinator	0:bb348c97df44	797	*/
lypinator	0:bb348c97df44	798	#define __FSMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 &= ~(__INTERRUPT__))
lypinator	0:bb348c97df44	799
lypinator	0:bb348c97df44	800	/**
lypinator	0:bb348c97df44	801	* @brief Get flag status of the PCCARD device.
lypinator	0:bb348c97df44	802	* @param __INSTANCE__ FSMC_PCCARD Instance
lypinator	0:bb348c97df44	803	* @param __FLAG__ FSMC_PCCARD flag
lypinator	0:bb348c97df44	804	* This parameter can be any combination of the following values:
lypinator	0:bb348c97df44	805	* @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
lypinator	0:bb348c97df44	806	* @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
lypinator	0:bb348c97df44	807	* @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
lypinator	0:bb348c97df44	808	* @arg FSMC_FLAG_FEMPT: FIFO empty flag.
lypinator	0:bb348c97df44	809	* @retval The state of FLAG (SET or RESET).
lypinator	0:bb348c97df44	810	*/
lypinator	0:bb348c97df44	811	#define __FSMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__))
lypinator	0:bb348c97df44	812
lypinator	0:bb348c97df44	813	/**
lypinator	0:bb348c97df44	814	* @brief Clear flag status of the PCCARD device.
lypinator	0:bb348c97df44	815	* @param __INSTANCE__ FSMC_PCCARD Instance
lypinator	0:bb348c97df44	816	* @param __FLAG__ FSMC_PCCARD flag
lypinator	0:bb348c97df44	817	* This parameter can be any combination of the following values:
lypinator	0:bb348c97df44	818	* @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
lypinator	0:bb348c97df44	819	* @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
lypinator	0:bb348c97df44	820	* @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
lypinator	0:bb348c97df44	821	* @arg FSMC_FLAG_FEMPT: FIFO empty flag.
lypinator	0:bb348c97df44	822	* @retval None
lypinator	0:bb348c97df44	823	*/
lypinator	0:bb348c97df44	824	#define __FSMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR4 &= ~(__FLAG__))
lypinator	0:bb348c97df44	825	/**
lypinator	0:bb348c97df44	826	* @}
lypinator	0:bb348c97df44	827	*/
lypinator	0:bb348c97df44	828	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx */
lypinator	0:bb348c97df44	829
lypinator	0:bb348c97df44	830	/** @defgroup FSMC_LL_Assert_Macros FSMC Assert Macros
lypinator	0:bb348c97df44	831	* @{
lypinator	0:bb348c97df44	832	*/
lypinator	0:bb348c97df44	833	#define IS_FSMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FSMC_NORSRAM_BANK1) \|\| \
lypinator	0:bb348c97df44	834	((__BANK__) == FSMC_NORSRAM_BANK2) \|\| \
lypinator	0:bb348c97df44	835	((__BANK__) == FSMC_NORSRAM_BANK3) \|\| \
lypinator	0:bb348c97df44	836	((__BANK__) == FSMC_NORSRAM_BANK4))
lypinator	0:bb348c97df44	837
lypinator	0:bb348c97df44	838	#define IS_FSMC_MUX(__MUX__) (((__MUX__) == FSMC_DATA_ADDRESS_MUX_DISABLE) \|\| \
lypinator	0:bb348c97df44	839	((__MUX__) == FSMC_DATA_ADDRESS_MUX_ENABLE))
lypinator	0:bb348c97df44	840
lypinator	0:bb348c97df44	841	#define IS_FSMC_MEMORY(__MEMORY__) (((__MEMORY__) == FSMC_MEMORY_TYPE_SRAM) \|\| \
lypinator	0:bb348c97df44	842	((__MEMORY__) == FSMC_MEMORY_TYPE_PSRAM)\|\| \
lypinator	0:bb348c97df44	843	((__MEMORY__) == FSMC_MEMORY_TYPE_NOR))
lypinator	0:bb348c97df44	844
lypinator	0:bb348c97df44	845	#define IS_FSMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_8) \|\| \
lypinator	0:bb348c97df44	846	((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_16) \|\| \
lypinator	0:bb348c97df44	847	((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_32))
lypinator	0:bb348c97df44	848
lypinator	0:bb348c97df44	849	#define IS_FSMC_ACCESS_MODE(__MODE__) (((__MODE__) == FSMC_ACCESS_MODE_A) \|\| \
lypinator	0:bb348c97df44	850	((__MODE__) == FSMC_ACCESS_MODE_B) \|\| \
lypinator	0:bb348c97df44	851	((__MODE__) == FSMC_ACCESS_MODE_C) \|\| \
lypinator	0:bb348c97df44	852	((__MODE__) == FSMC_ACCESS_MODE_D))
lypinator	0:bb348c97df44	853
lypinator	0:bb348c97df44	854	#define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_NAND_BANK2) \|\| \
lypinator	0:bb348c97df44	855	((BANK) == FSMC_NAND_BANK3))
lypinator	0:bb348c97df44	856
lypinator	0:bb348c97df44	857	#define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_NAND_PCC_WAIT_FEATURE_DISABLE) \|\| \
lypinator	0:bb348c97df44	858	((FEATURE) == FSMC_NAND_PCC_WAIT_FEATURE_ENABLE))
lypinator	0:bb348c97df44	859
lypinator	0:bb348c97df44	860	#define IS_FSMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_NAND_PCC_MEM_BUS_WIDTH_8) \|\| \
lypinator	0:bb348c97df44	861	((WIDTH) == FSMC_NAND_PCC_MEM_BUS_WIDTH_16))
lypinator	0:bb348c97df44	862
lypinator	0:bb348c97df44	863	#define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_NAND_ECC_DISABLE) \|\| \
lypinator	0:bb348c97df44	864	((STATE) == FSMC_NAND_ECC_ENABLE))
lypinator	0:bb348c97df44	865
lypinator	0:bb348c97df44	866	#define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_256BYTE) \|\| \
lypinator	0:bb348c97df44	867	((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_512BYTE) \|\| \
lypinator	0:bb348c97df44	868	((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_1024BYTE) \|\| \
lypinator	0:bb348c97df44	869	((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_2048BYTE) \|\| \
lypinator	0:bb348c97df44	870	((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_4096BYTE) \|\| \
lypinator	0:bb348c97df44	871	((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_8192BYTE))
lypinator	0:bb348c97df44	872
lypinator	0:bb348c97df44	873	#define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 255U)
lypinator	0:bb348c97df44	874
lypinator	0:bb348c97df44	875	#define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 255U)
lypinator	0:bb348c97df44	876
lypinator	0:bb348c97df44	877	#define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 255U)
lypinator	0:bb348c97df44	878
lypinator	0:bb348c97df44	879	#define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 255U)
lypinator	0:bb348c97df44	880
lypinator	0:bb348c97df44	881	#define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 255U)
lypinator	0:bb348c97df44	882
lypinator	0:bb348c97df44	883	#define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 255U)
lypinator	0:bb348c97df44	884
lypinator	0:bb348c97df44	885	#define IS_FSMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_DEVICE)
lypinator	0:bb348c97df44	886
lypinator	0:bb348c97df44	887	#define IS_FSMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_EXTENDED_DEVICE)
lypinator	0:bb348c97df44	888
lypinator	0:bb348c97df44	889	#define IS_FSMC_NAND_DEVICE(INSTANCE) ((INSTANCE) == FSMC_NAND_DEVICE)
lypinator	0:bb348c97df44	890
lypinator	0:bb348c97df44	891	#define IS_FSMC_PCCARD_DEVICE(INSTANCE) ((INSTANCE) == FSMC_PCCARD_DEVICE)
lypinator	0:bb348c97df44	892
lypinator	0:bb348c97df44	893	#define IS_FSMC_BURSTMODE(__STATE__) (((__STATE__) == FSMC_BURST_ACCESS_MODE_DISABLE) \|\| \
lypinator	0:bb348c97df44	894	((__STATE__) == FSMC_BURST_ACCESS_MODE_ENABLE))
lypinator	0:bb348c97df44	895
lypinator	0:bb348c97df44	896	#define IS_FSMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_LOW) \|\| \
lypinator	0:bb348c97df44	897	((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_HIGH))
lypinator	0:bb348c97df44	898
lypinator	0:bb348c97df44	899	#define IS_FSMC_WRAP_MODE(__MODE__) (((__MODE__) == FSMC_WRAP_MODE_DISABLE) \|\| \
lypinator	0:bb348c97df44	900	((__MODE__) == FSMC_WRAP_MODE_ENABLE))
lypinator	0:bb348c97df44	901
lypinator	0:bb348c97df44	902	#define IS_FSMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FSMC_WAIT_TIMING_BEFORE_WS) \|\| \
lypinator	0:bb348c97df44	903	((__ACTIVE__) == FSMC_WAIT_TIMING_DURING_WS))
lypinator	0:bb348c97df44	904
lypinator	0:bb348c97df44	905	#define IS_FSMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FSMC_WRITE_OPERATION_DISABLE) \|\| \
lypinator	0:bb348c97df44	906	((__OPERATION__) == FSMC_WRITE_OPERATION_ENABLE))
lypinator	0:bb348c97df44	907
lypinator	0:bb348c97df44	908	#define IS_FSMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FSMC_WAIT_SIGNAL_DISABLE) \|\| \
lypinator	0:bb348c97df44	909	((__SIGNAL__) == FSMC_WAIT_SIGNAL_ENABLE))
lypinator	0:bb348c97df44	910
lypinator	0:bb348c97df44	911	#define IS_FSMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FSMC_EXTENDED_MODE_DISABLE) \|\| \
lypinator	0:bb348c97df44	912	((__MODE__) == FSMC_EXTENDED_MODE_ENABLE))
lypinator	0:bb348c97df44	913
lypinator	0:bb348c97df44	914	#define IS_FSMC_ASYNWAIT(__STATE__) (((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_DISABLE) \|\| \
lypinator	0:bb348c97df44	915	((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_ENABLE))
lypinator	0:bb348c97df44	916
lypinator	0:bb348c97df44	917	#define IS_FSMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U))
lypinator	0:bb348c97df44	918
lypinator	0:bb348c97df44	919	#define IS_FSMC_WRITE_BURST(__BURST__) (((__BURST__) == FSMC_WRITE_BURST_DISABLE) \|\| \
lypinator	0:bb348c97df44	920	((__BURST__) == FSMC_WRITE_BURST_ENABLE))
lypinator	0:bb348c97df44	921
lypinator	0:bb348c97df44	922	#define IS_FSMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15U)
lypinator	0:bb348c97df44	923
lypinator	0:bb348c97df44	924	#define IS_FSMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 15U))
lypinator	0:bb348c97df44	925
lypinator	0:bb348c97df44	926	#define IS_FSMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 255U))
lypinator	0:bb348c97df44	927
lypinator	0:bb348c97df44	928	#define IS_FSMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15U)
lypinator	0:bb348c97df44	929
lypinator	0:bb348c97df44	930	#define IS_FSMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FSMC_CONTINUOUS_CLOCK_SYNC_ONLY) \|\| \
lypinator	0:bb348c97df44	931	((CCLOCK) == FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
lypinator	0:bb348c97df44	932
lypinator	0:bb348c97df44	933	#define IS_FSMC_CLK_DIV(DIV) (((DIV) > 1U) && ((DIV) <= 16U))
lypinator	0:bb348c97df44	934
lypinator	0:bb348c97df44	935	#define IS_FSMC_PAGESIZE(SIZE) (((SIZE) == FSMC_PAGE_SIZE_NONE) \|\| \
lypinator	0:bb348c97df44	936	((SIZE) == FSMC_PAGE_SIZE_128) \|\| \
lypinator	0:bb348c97df44	937	((SIZE) == FSMC_PAGE_SIZE_256) \|\| \
lypinator	0:bb348c97df44	938	((SIZE) == FSMC_PAGE_SIZE_512) \|\| \
lypinator	0:bb348c97df44	939	((SIZE) == FSMC_PAGE_SIZE_1024))
lypinator	0:bb348c97df44	940
lypinator	0:bb348c97df44	941	#define IS_FSMC_WRITE_FIFO(FIFO) (((FIFO) == FSMC_WRITE_FIFO_DISABLE) \|\| \
lypinator	0:bb348c97df44	942	((FIFO) == FSMC_WRITE_FIFO_ENABLE))
lypinator	0:bb348c97df44	943
lypinator	0:bb348c97df44	944	/**
lypinator	0:bb348c97df44	945	* @}
lypinator	0:bb348c97df44	946	*/
lypinator	0:bb348c97df44	947	/**
lypinator	0:bb348c97df44	948	* @}
lypinator	0:bb348c97df44	949	*/
lypinator	0:bb348c97df44	950
lypinator	0:bb348c97df44	951	/* Private functions ---------------------------------------------------------*/
lypinator	0:bb348c97df44	952	/** @defgroup FSMC_LL_Private_Functions FSMC LL Private Functions
lypinator	0:bb348c97df44	953	* @{
lypinator	0:bb348c97df44	954	*/
lypinator	0:bb348c97df44	955
lypinator	0:bb348c97df44	956	/** @defgroup FSMC_LL_NORSRAM NOR SRAM
lypinator	0:bb348c97df44	957	* @{
lypinator	0:bb348c97df44	958	*/
lypinator	0:bb348c97df44	959
lypinator	0:bb348c97df44	960	/** @defgroup FSMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions
lypinator	0:bb348c97df44	961	* @{
lypinator	0:bb348c97df44	962	*/
lypinator	0:bb348c97df44	963	HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef Device, FSMC_NORSRAM_InitTypeDef Init);
lypinator	0:bb348c97df44	964	HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef Device, FSMC_NORSRAM_TimingTypeDef Timing, uint32_t Bank);
lypinator	0:bb348c97df44	965	HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef Device, FSMC_NORSRAM_TimingTypeDef Timing, uint32_t Bank, uint32_t ExtendedMode);
lypinator	0:bb348c97df44	966	HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef Device, FSMC_NORSRAM_EXTENDED_TypeDef ExDevice, uint32_t Bank);
lypinator	0:bb348c97df44	967	/**
lypinator	0:bb348c97df44	968	* @}
lypinator	0:bb348c97df44	969	*/
lypinator	0:bb348c97df44	970
lypinator	0:bb348c97df44	971	/** @defgroup FSMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions
lypinator	0:bb348c97df44	972	* @{
lypinator	0:bb348c97df44	973	*/
lypinator	0:bb348c97df44	974	HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
lypinator	0:bb348c97df44	975	HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
lypinator	0:bb348c97df44	976	/**
lypinator	0:bb348c97df44	977	* @}
lypinator	0:bb348c97df44	978	*/
lypinator	0:bb348c97df44	979	/**
lypinator	0:bb348c97df44	980	* @}
lypinator	0:bb348c97df44	981	*/
lypinator	0:bb348c97df44	982
lypinator	0:bb348c97df44	983	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx)
lypinator	0:bb348c97df44	984	/** @defgroup FSMC_LL_NAND NAND
lypinator	0:bb348c97df44	985	* @{
lypinator	0:bb348c97df44	986	*/
lypinator	0:bb348c97df44	987	/** @defgroup FSMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions
lypinator	0:bb348c97df44	988	* @{
lypinator	0:bb348c97df44	989	*/
lypinator	0:bb348c97df44	990	HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef Device, FSMC_NAND_InitTypeDef Init);
lypinator	0:bb348c97df44	991	HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef Device, FSMC_NAND_PCC_TimingTypeDef Timing, uint32_t Bank);
lypinator	0:bb348c97df44	992	HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef Device, FSMC_NAND_PCC_TimingTypeDef Timing, uint32_t Bank);
lypinator	0:bb348c97df44	993	HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank);
lypinator	0:bb348c97df44	994	/**
lypinator	0:bb348c97df44	995	* @}
lypinator	0:bb348c97df44	996	*/
lypinator	0:bb348c97df44	997
lypinator	0:bb348c97df44	998	/** @defgroup FSMC_LL_NAND_Private_Functions_Group2 NAND Control functions
lypinator	0:bb348c97df44	999	* @{
lypinator	0:bb348c97df44	1000	*/
lypinator	0:bb348c97df44	1001	HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank);
lypinator	0:bb348c97df44	1002	HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank);
lypinator	0:bb348c97df44	1003	HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef Device, uint32_t ECCval, uint32_t Bank, uint32_t Timeout);
lypinator	0:bb348c97df44	1004	/**
lypinator	0:bb348c97df44	1005	* @}
lypinator	0:bb348c97df44	1006	*/
lypinator	0:bb348c97df44	1007	/**
lypinator	0:bb348c97df44	1008	* @}
lypinator	0:bb348c97df44	1009	*/
lypinator	0:bb348c97df44	1010
lypinator	0:bb348c97df44	1011	/** @defgroup FSMC_LL_PCCARD PCCARD
lypinator	0:bb348c97df44	1012	* @{
lypinator	0:bb348c97df44	1013	*/
lypinator	0:bb348c97df44	1014	/** @defgroup FSMC_LL_PCCARD_Private_Functions_Group1 PCCARD Initialization/de-initialization functions
lypinator	0:bb348c97df44	1015	* @{
lypinator	0:bb348c97df44	1016	*/
lypinator	0:bb348c97df44	1017	HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef Device, FSMC_PCCARD_InitTypeDef Init);
lypinator	0:bb348c97df44	1018	HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef Device, FSMC_NAND_PCC_TimingTypeDef Timing);
lypinator	0:bb348c97df44	1019	HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef Device, FSMC_NAND_PCC_TimingTypeDef Timing);
lypinator	0:bb348c97df44	1020	HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef Device, FSMC_NAND_PCC_TimingTypeDef Timing);
lypinator	0:bb348c97df44	1021	HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device);
lypinator	0:bb348c97df44	1022	/**
lypinator	0:bb348c97df44	1023	* @}
lypinator	0:bb348c97df44	1024	*/
lypinator	0:bb348c97df44	1025	/**
lypinator	0:bb348c97df44	1026	* @}
lypinator	0:bb348c97df44	1027	*/
lypinator	0:bb348c97df44	1028	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx */
lypinator	0:bb348c97df44	1029
lypinator	0:bb348c97df44	1030	/**
lypinator	0:bb348c97df44	1031	* @}
lypinator	0:bb348c97df44	1032	*/
lypinator	0:bb348c97df44	1033	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx \|\| STM32F413xx \|\| STM32F423xx */
lypinator	0:bb348c97df44	1034
lypinator	0:bb348c97df44	1035	/**
lypinator	0:bb348c97df44	1036	* @}
lypinator	0:bb348c97df44	1037	*/
lypinator	0:bb348c97df44	1038
lypinator	0:bb348c97df44	1039	/**
lypinator	0:bb348c97df44	1040	* @}
lypinator	0:bb348c97df44	1041	*/
lypinator	0:bb348c97df44	1042
lypinator	0:bb348c97df44	1043	#ifdef __cplusplus
lypinator	0:bb348c97df44	1044	}
lypinator	0:bb348c97df44	1045	#endif
lypinator	0:bb348c97df44	1046
lypinator	0:bb348c97df44	1047	#endif /* __STM32F4xx_LL_FSMC_H */
lypinator	0:bb348c97df44	1048
lypinator	0:bb348c97df44	1049	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Program
Created:	16 Sep 2020
Imports:	1
Forks:	0
Commits:	1
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Dependencies:	1
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mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_fsmc.h@0:bb348c97df44, 2020-09-16 (annotated)

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