DevLibMemoryController - Initial commit

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Initial commit

mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_fmc.h@0:bb348c97df44, 2020-09-16 (annotated)

Committer:: lypinator
Date:: Wed Sep 16 01:11:49 2020 +0000
Revision:: 0:bb348c97df44

Added PWM

Who changed what in which revision?

User	Revision	Line number	New contents of line
lypinator	0:bb348c97df44	1	/**
lypinator	0:bb348c97df44	2	******************************************************************************
lypinator	0:bb348c97df44	3	* @file stm32f4xx_ll_fmc.h
lypinator	0:bb348c97df44	4	* @author MCD Application Team
lypinator	0:bb348c97df44	5	* @brief Header file of FMC HAL module.
lypinator	0:bb348c97df44	6	******************************************************************************
lypinator	0:bb348c97df44	7	* @attention
lypinator	0:bb348c97df44	8	*
lypinator	0:bb348c97df44	9	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
lypinator	0:bb348c97df44	10	*
lypinator	0:bb348c97df44	11	* Redistribution and use in source and binary forms, with or without modification,
lypinator	0:bb348c97df44	12	* are permitted provided that the following conditions are met:
lypinator	0:bb348c97df44	13	* 1. Redistributions of source code must retain the above copyright notice,
lypinator	0:bb348c97df44	14	* this list of conditions and the following disclaimer.
lypinator	0:bb348c97df44	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
lypinator	0:bb348c97df44	16	* this list of conditions and the following disclaimer in the documentation
lypinator	0:bb348c97df44	17	* and/or other materials provided with the distribution.
lypinator	0:bb348c97df44	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
lypinator	0:bb348c97df44	19	* may be used to endorse or promote products derived from this software
lypinator	0:bb348c97df44	20	* without specific prior written permission.
lypinator	0:bb348c97df44	21	*
lypinator	0:bb348c97df44	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
lypinator	0:bb348c97df44	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
lypinator	0:bb348c97df44	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
lypinator	0:bb348c97df44	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
lypinator	0:bb348c97df44	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
lypinator	0:bb348c97df44	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
lypinator	0:bb348c97df44	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
lypinator	0:bb348c97df44	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
lypinator	0:bb348c97df44	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
lypinator	0:bb348c97df44	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
lypinator	0:bb348c97df44	32	*
lypinator	0:bb348c97df44	33	******************************************************************************
lypinator	0:bb348c97df44	34	*/
lypinator	0:bb348c97df44	35
lypinator	0:bb348c97df44	36	/* Define to prevent recursive inclusion -------------------------------------*/
lypinator	0:bb348c97df44	37	#ifndef __STM32F4xx_LL_FMC_H
lypinator	0:bb348c97df44	38	#define __STM32F4xx_LL_FMC_H
lypinator	0:bb348c97df44	39
lypinator	0:bb348c97df44	40	#ifdef __cplusplus
lypinator	0:bb348c97df44	41	extern "C" {
lypinator	0:bb348c97df44	42	#endif
lypinator	0:bb348c97df44	43
lypinator	0:bb348c97df44	44	/* Includes ------------------------------------------------------------------*/
lypinator	0:bb348c97df44	45	#include "stm32f4xx_hal_def.h"
lypinator	0:bb348c97df44	46
lypinator	0:bb348c97df44	47	/** @addtogroup STM32F4xx_HAL_Driver
lypinator	0:bb348c97df44	48	* @{
lypinator	0:bb348c97df44	49	*/
lypinator	0:bb348c97df44	50
lypinator	0:bb348c97df44	51	/** @addtogroup FMC_LL
lypinator	0:bb348c97df44	52	* @{
lypinator	0:bb348c97df44	53	*/
lypinator	0:bb348c97df44	54	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\|\
lypinator	0:bb348c97df44	55	defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
lypinator	0:bb348c97df44	56	/* Private types -------------------------------------------------------------*/
lypinator	0:bb348c97df44	57	/** @defgroup FMC_LL_Private_Types FMC Private Types
lypinator	0:bb348c97df44	58	* @{
lypinator	0:bb348c97df44	59	*/
lypinator	0:bb348c97df44	60
lypinator	0:bb348c97df44	61	/**
lypinator	0:bb348c97df44	62	* @brief FMC NORSRAM Configuration Structure definition
lypinator	0:bb348c97df44	63	*/
lypinator	0:bb348c97df44	64	typedef struct
lypinator	0:bb348c97df44	65	{
lypinator	0:bb348c97df44	66	uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used.
lypinator	0:bb348c97df44	67	This parameter can be a value of @ref FMC_NORSRAM_Bank */
lypinator	0:bb348c97df44	68
lypinator	0:bb348c97df44	69	uint32_t DataAddressMux; /*!< Specifies whether the address and data values are
lypinator	0:bb348c97df44	70	multiplexed on the data bus or not.
lypinator	0:bb348c97df44	71	This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */
lypinator	0:bb348c97df44	72
lypinator	0:bb348c97df44	73	uint32_t MemoryType; /*!< Specifies the type of external memory attached to
lypinator	0:bb348c97df44	74	the corresponding memory device.
lypinator	0:bb348c97df44	75	This parameter can be a value of @ref FMC_Memory_Type */
lypinator	0:bb348c97df44	76
lypinator	0:bb348c97df44	77	uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
lypinator	0:bb348c97df44	78	This parameter can be a value of @ref FMC_NORSRAM_Data_Width */
lypinator	0:bb348c97df44	79
lypinator	0:bb348c97df44	80	uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
lypinator	0:bb348c97df44	81	valid only with synchronous burst Flash memories.
lypinator	0:bb348c97df44	82	This parameter can be a value of @ref FMC_Burst_Access_Mode */
lypinator	0:bb348c97df44	83
lypinator	0:bb348c97df44	84	uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
lypinator	0:bb348c97df44	85	the Flash memory in burst mode.
lypinator	0:bb348c97df44	86	This parameter can be a value of @ref FMC_Wait_Signal_Polarity */
lypinator	0:bb348c97df44	87
lypinator	0:bb348c97df44	88	uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
lypinator	0:bb348c97df44	89	memory, valid only when accessing Flash memories in burst mode.
lypinator	0:bb348c97df44	90	This parameter can be a value of @ref FMC_Wrap_Mode
lypinator	0:bb348c97df44	91	This mode is not available for the STM32F446/467/479xx devices */
lypinator	0:bb348c97df44	92
lypinator	0:bb348c97df44	93	uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
lypinator	0:bb348c97df44	94	clock cycle before the wait state or during the wait state,
lypinator	0:bb348c97df44	95	valid only when accessing memories in burst mode.
lypinator	0:bb348c97df44	96	This parameter can be a value of @ref FMC_Wait_Timing */
lypinator	0:bb348c97df44	97
lypinator	0:bb348c97df44	98	uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC.
lypinator	0:bb348c97df44	99	This parameter can be a value of @ref FMC_Write_Operation */
lypinator	0:bb348c97df44	100
lypinator	0:bb348c97df44	101	uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait
lypinator	0:bb348c97df44	102	signal, valid for Flash memory access in burst mode.
lypinator	0:bb348c97df44	103	This parameter can be a value of @ref FMC_Wait_Signal */
lypinator	0:bb348c97df44	104
lypinator	0:bb348c97df44	105	uint32_t ExtendedMode; /*!< Enables or disables the extended mode.
lypinator	0:bb348c97df44	106	This parameter can be a value of @ref FMC_Extended_Mode */
lypinator	0:bb348c97df44	107
lypinator	0:bb348c97df44	108	uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
lypinator	0:bb348c97df44	109	valid only with asynchronous Flash memories.
lypinator	0:bb348c97df44	110	This parameter can be a value of @ref FMC_AsynchronousWait */
lypinator	0:bb348c97df44	111
lypinator	0:bb348c97df44	112	uint32_t WriteBurst; /*!< Enables or disables the write burst operation.
lypinator	0:bb348c97df44	113	This parameter can be a value of @ref FMC_Write_Burst */
lypinator	0:bb348c97df44	114
lypinator	0:bb348c97df44	115	uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices.
lypinator	0:bb348c97df44	116	This parameter is only enabled through the FMC_BCR1 register, and don't care
lypinator	0:bb348c97df44	117	through FMC_BCR2..4 registers.
lypinator	0:bb348c97df44	118	This parameter can be a value of @ref FMC_Continous_Clock */
lypinator	0:bb348c97df44	119
lypinator	0:bb348c97df44	120	uint32_t WriteFifo; /*!< Enables or disables the write FIFO used by the FMC controller.
lypinator	0:bb348c97df44	121	This parameter is only enabled through the FMC_BCR1 register, and don't care
lypinator	0:bb348c97df44	122	through FMC_BCR2..4 registers.
lypinator	0:bb348c97df44	123	This parameter can be a value of @ref FMC_Write_FIFO
lypinator	0:bb348c97df44	124	This mode is available only for the STM32F446/469/479xx devices */
lypinator	0:bb348c97df44	125
lypinator	0:bb348c97df44	126	uint32_t PageSize; /*!< Specifies the memory page size.
lypinator	0:bb348c97df44	127	This parameter can be a value of @ref FMC_Page_Size */
lypinator	0:bb348c97df44	128	}FMC_NORSRAM_InitTypeDef;
lypinator	0:bb348c97df44	129
lypinator	0:bb348c97df44	130	/**
lypinator	0:bb348c97df44	131	* @brief FMC NORSRAM Timing parameters structure definition
lypinator	0:bb348c97df44	132	*/
lypinator	0:bb348c97df44	133	typedef struct
lypinator	0:bb348c97df44	134	{
lypinator	0:bb348c97df44	135	uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
lypinator	0:bb348c97df44	136	the duration of the address setup time.
lypinator	0:bb348c97df44	137	This parameter can be a value between Min_Data = 0 and Max_Data = 15.
lypinator	0:bb348c97df44	138	@note This parameter is not used with synchronous NOR Flash memories. */
lypinator	0:bb348c97df44	139
lypinator	0:bb348c97df44	140	uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
lypinator	0:bb348c97df44	141	the duration of the address hold time.
lypinator	0:bb348c97df44	142	This parameter can be a value between Min_Data = 1 and Max_Data = 15.
lypinator	0:bb348c97df44	143	@note This parameter is not used with synchronous NOR Flash memories. */
lypinator	0:bb348c97df44	144
lypinator	0:bb348c97df44	145	uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure
lypinator	0:bb348c97df44	146	the duration of the data setup time.
lypinator	0:bb348c97df44	147	This parameter can be a value between Min_Data = 1 and Max_Data = 255.
lypinator	0:bb348c97df44	148	@note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
lypinator	0:bb348c97df44	149	NOR Flash memories. */
lypinator	0:bb348c97df44	150
lypinator	0:bb348c97df44	151	uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
lypinator	0:bb348c97df44	152	the duration of the bus turnaround.
lypinator	0:bb348c97df44	153	This parameter can be a value between Min_Data = 0 and Max_Data = 15.
lypinator	0:bb348c97df44	154	@note This parameter is only used for multiplexed NOR Flash memories. */
lypinator	0:bb348c97df44	155
lypinator	0:bb348c97df44	156	uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of
lypinator	0:bb348c97df44	157	HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
lypinator	0:bb348c97df44	158	@note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
lypinator	0:bb348c97df44	159	accesses. */
lypinator	0:bb348c97df44	160
lypinator	0:bb348c97df44	161	uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue
lypinator	0:bb348c97df44	162	to the memory before getting the first data.
lypinator	0:bb348c97df44	163	The parameter value depends on the memory type as shown below:
lypinator	0:bb348c97df44	164	- It must be set to 0 in case of a CRAM
lypinator	0:bb348c97df44	165	- It is don't care in asynchronous NOR, SRAM or ROM accesses
lypinator	0:bb348c97df44	166	- It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
lypinator	0:bb348c97df44	167	with synchronous burst mode enable */
lypinator	0:bb348c97df44	168
lypinator	0:bb348c97df44	169	uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
lypinator	0:bb348c97df44	170	This parameter can be a value of @ref FMC_Access_Mode */
lypinator	0:bb348c97df44	171	}FMC_NORSRAM_TimingTypeDef;
lypinator	0:bb348c97df44	172
lypinator	0:bb348c97df44	173	/**
lypinator	0:bb348c97df44	174	* @brief FMC NAND Configuration Structure definition
lypinator	0:bb348c97df44	175	*/
lypinator	0:bb348c97df44	176	typedef struct
lypinator	0:bb348c97df44	177	{
lypinator	0:bb348c97df44	178	uint32_t NandBank; /*!< Specifies the NAND memory device that will be used.
lypinator	0:bb348c97df44	179	This parameter can be a value of @ref FMC_NAND_Bank */
lypinator	0:bb348c97df44	180
lypinator	0:bb348c97df44	181	uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device.
lypinator	0:bb348c97df44	182	This parameter can be any value of @ref FMC_Wait_feature */
lypinator	0:bb348c97df44	183
lypinator	0:bb348c97df44	184	uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
lypinator	0:bb348c97df44	185	This parameter can be any value of @ref FMC_NAND_Data_Width */
lypinator	0:bb348c97df44	186
lypinator	0:bb348c97df44	187	uint32_t EccComputation; /*!< Enables or disables the ECC computation.
lypinator	0:bb348c97df44	188	This parameter can be any value of @ref FMC_ECC */
lypinator	0:bb348c97df44	189
lypinator	0:bb348c97df44	190	uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC.
lypinator	0:bb348c97df44	191	This parameter can be any value of @ref FMC_ECC_Page_Size */
lypinator	0:bb348c97df44	192
lypinator	0:bb348c97df44	193	uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
lypinator	0:bb348c97df44	194	delay between CLE low and RE low.
lypinator	0:bb348c97df44	195	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
lypinator	0:bb348c97df44	196
lypinator	0:bb348c97df44	197	uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
lypinator	0:bb348c97df44	198	delay between ALE low and RE low.
lypinator	0:bb348c97df44	199	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
lypinator	0:bb348c97df44	200	}FMC_NAND_InitTypeDef;
lypinator	0:bb348c97df44	201
lypinator	0:bb348c97df44	202	/**
lypinator	0:bb348c97df44	203	* @brief FMC NAND/PCCARD Timing parameters structure definition
lypinator	0:bb348c97df44	204	*/
lypinator	0:bb348c97df44	205	typedef struct
lypinator	0:bb348c97df44	206	{
lypinator	0:bb348c97df44	207	uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before
lypinator	0:bb348c97df44	208	the command assertion for NAND-Flash read or write access
lypinator	0:bb348c97df44	209	to common/Attribute or I/O memory space (depending on
lypinator	0:bb348c97df44	210	the memory space timing to be configured).
lypinator	0:bb348c97df44	211	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
lypinator	0:bb348c97df44	212
lypinator	0:bb348c97df44	213	uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
lypinator	0:bb348c97df44	214	command for NAND-Flash read or write access to
lypinator	0:bb348c97df44	215	common/Attribute or I/O memory space (depending on the
lypinator	0:bb348c97df44	216	memory space timing to be configured).
lypinator	0:bb348c97df44	217	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
lypinator	0:bb348c97df44	218
lypinator	0:bb348c97df44	219	uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
lypinator	0:bb348c97df44	220	(and data for write access) after the command de-assertion
lypinator	0:bb348c97df44	221	for NAND-Flash read or write access to common/Attribute
lypinator	0:bb348c97df44	222	or I/O memory space (depending on the memory space timing
lypinator	0:bb348c97df44	223	to be configured).
lypinator	0:bb348c97df44	224	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
lypinator	0:bb348c97df44	225
lypinator	0:bb348c97df44	226	uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
lypinator	0:bb348c97df44	227	data bus is kept in HiZ after the start of a NAND-Flash
lypinator	0:bb348c97df44	228	write access to common/Attribute or I/O memory space (depending
lypinator	0:bb348c97df44	229	on the memory space timing to be configured).
lypinator	0:bb348c97df44	230	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
lypinator	0:bb348c97df44	231	}FMC_NAND_PCC_TimingTypeDef;
lypinator	0:bb348c97df44	232
lypinator	0:bb348c97df44	233	/**
lypinator	0:bb348c97df44	234	* @brief FMC NAND Configuration Structure definition
lypinator	0:bb348c97df44	235	*/
lypinator	0:bb348c97df44	236	typedef struct
lypinator	0:bb348c97df44	237	{
lypinator	0:bb348c97df44	238	uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the PCCARD Memory device.
lypinator	0:bb348c97df44	239	This parameter can be any value of @ref FMC_Wait_feature */
lypinator	0:bb348c97df44	240
lypinator	0:bb348c97df44	241	uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
lypinator	0:bb348c97df44	242	delay between CLE low and RE low.
lypinator	0:bb348c97df44	243	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
lypinator	0:bb348c97df44	244
lypinator	0:bb348c97df44	245	uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
lypinator	0:bb348c97df44	246	delay between ALE low and RE low.
lypinator	0:bb348c97df44	247	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
lypinator	0:bb348c97df44	248	}FMC_PCCARD_InitTypeDef;
lypinator	0:bb348c97df44	249
lypinator	0:bb348c97df44	250	/**
lypinator	0:bb348c97df44	251	* @brief FMC SDRAM Configuration Structure definition
lypinator	0:bb348c97df44	252	*/
lypinator	0:bb348c97df44	253	typedef struct
lypinator	0:bb348c97df44	254	{
lypinator	0:bb348c97df44	255	uint32_t SDBank; /*!< Specifies the SDRAM memory device that will be used.
lypinator	0:bb348c97df44	256	This parameter can be a value of @ref FMC_SDRAM_Bank */
lypinator	0:bb348c97df44	257
lypinator	0:bb348c97df44	258	uint32_t ColumnBitsNumber; /*!< Defines the number of bits of column address.
lypinator	0:bb348c97df44	259	This parameter can be a value of @ref FMC_SDRAM_Column_Bits_number. */
lypinator	0:bb348c97df44	260
lypinator	0:bb348c97df44	261	uint32_t RowBitsNumber; /*!< Defines the number of bits of column address.
lypinator	0:bb348c97df44	262	This parameter can be a value of @ref FMC_SDRAM_Row_Bits_number. */
lypinator	0:bb348c97df44	263
lypinator	0:bb348c97df44	264	uint32_t MemoryDataWidth; /*!< Defines the memory device width.
lypinator	0:bb348c97df44	265	This parameter can be a value of @ref FMC_SDRAM_Memory_Bus_Width. */
lypinator	0:bb348c97df44	266
lypinator	0:bb348c97df44	267	uint32_t InternalBankNumber; /*!< Defines the number of the device's internal banks.
lypinator	0:bb348c97df44	268	This parameter can be of @ref FMC_SDRAM_Internal_Banks_Number. */
lypinator	0:bb348c97df44	269
lypinator	0:bb348c97df44	270	uint32_t CASLatency; /*!< Defines the SDRAM CAS latency in number of memory clock cycles.
lypinator	0:bb348c97df44	271	This parameter can be a value of @ref FMC_SDRAM_CAS_Latency. */
lypinator	0:bb348c97df44	272
lypinator	0:bb348c97df44	273	uint32_t WriteProtection; /*!< Enables the SDRAM device to be accessed in write mode.
lypinator	0:bb348c97df44	274	This parameter can be a value of @ref FMC_SDRAM_Write_Protection. */
lypinator	0:bb348c97df44	275
lypinator	0:bb348c97df44	276	uint32_t SDClockPeriod; /*!< Define the SDRAM Clock Period for both SDRAM devices and they allow
lypinator	0:bb348c97df44	277	to disable the clock before changing frequency.
lypinator	0:bb348c97df44	278	This parameter can be a value of @ref FMC_SDRAM_Clock_Period. */
lypinator	0:bb348c97df44	279
lypinator	0:bb348c97df44	280	uint32_t ReadBurst; /*!< This bit enable the SDRAM controller to anticipate the next read
lypinator	0:bb348c97df44	281	commands during the CAS latency and stores data in the Read FIFO.
lypinator	0:bb348c97df44	282	This parameter can be a value of @ref FMC_SDRAM_Read_Burst. */
lypinator	0:bb348c97df44	283
lypinator	0:bb348c97df44	284	uint32_t ReadPipeDelay; /*!< Define the delay in system clock cycles on read data path.
lypinator	0:bb348c97df44	285	This parameter can be a value of @ref FMC_SDRAM_Read_Pipe_Delay. */
lypinator	0:bb348c97df44	286	}FMC_SDRAM_InitTypeDef;
lypinator	0:bb348c97df44	287
lypinator	0:bb348c97df44	288	/**
lypinator	0:bb348c97df44	289	* @brief FMC SDRAM Timing parameters structure definition
lypinator	0:bb348c97df44	290	*/
lypinator	0:bb348c97df44	291	typedef struct
lypinator	0:bb348c97df44	292	{
lypinator	0:bb348c97df44	293	uint32_t LoadToActiveDelay; /*!< Defines the delay between a Load Mode Register command and
lypinator	0:bb348c97df44	294	an active or Refresh command in number of memory clock cycles.
lypinator	0:bb348c97df44	295	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
lypinator	0:bb348c97df44	296
lypinator	0:bb348c97df44	297	uint32_t ExitSelfRefreshDelay; /*!< Defines the delay from releasing the self refresh command to
lypinator	0:bb348c97df44	298	issuing the Activate command in number of memory clock cycles.
lypinator	0:bb348c97df44	299	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
lypinator	0:bb348c97df44	300
lypinator	0:bb348c97df44	301	uint32_t SelfRefreshTime; /*!< Defines the minimum Self Refresh period in number of memory clock
lypinator	0:bb348c97df44	302	cycles.
lypinator	0:bb348c97df44	303	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
lypinator	0:bb348c97df44	304
lypinator	0:bb348c97df44	305	uint32_t RowCycleDelay; /*!< Defines the delay between the Refresh command and the Activate command
lypinator	0:bb348c97df44	306	and the delay between two consecutive Refresh commands in number of
lypinator	0:bb348c97df44	307	memory clock cycles.
lypinator	0:bb348c97df44	308	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
lypinator	0:bb348c97df44	309
lypinator	0:bb348c97df44	310	uint32_t WriteRecoveryTime; /*!< Defines the Write recovery Time in number of memory clock cycles.
lypinator	0:bb348c97df44	311	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
lypinator	0:bb348c97df44	312
lypinator	0:bb348c97df44	313	uint32_t RPDelay; /*!< Defines the delay between a Precharge Command and an other command
lypinator	0:bb348c97df44	314	in number of memory clock cycles.
lypinator	0:bb348c97df44	315	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
lypinator	0:bb348c97df44	316
lypinator	0:bb348c97df44	317	uint32_t RCDDelay; /*!< Defines the delay between the Activate Command and a Read/Write
lypinator	0:bb348c97df44	318	command in number of memory clock cycles.
lypinator	0:bb348c97df44	319	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
lypinator	0:bb348c97df44	320	}FMC_SDRAM_TimingTypeDef;
lypinator	0:bb348c97df44	321
lypinator	0:bb348c97df44	322	/**
lypinator	0:bb348c97df44	323	* @brief SDRAM command parameters structure definition
lypinator	0:bb348c97df44	324	*/
lypinator	0:bb348c97df44	325	typedef struct
lypinator	0:bb348c97df44	326	{
lypinator	0:bb348c97df44	327	uint32_t CommandMode; /*!< Defines the command issued to the SDRAM device.
lypinator	0:bb348c97df44	328	This parameter can be a value of @ref FMC_SDRAM_Command_Mode. */
lypinator	0:bb348c97df44	329
lypinator	0:bb348c97df44	330	uint32_t CommandTarget; /*!< Defines which device (1 or 2) the command will be issued to.
lypinator	0:bb348c97df44	331	This parameter can be a value of @ref FMC_SDRAM_Command_Target. */
lypinator	0:bb348c97df44	332
lypinator	0:bb348c97df44	333	uint32_t AutoRefreshNumber; /*!< Defines the number of consecutive auto refresh command issued
lypinator	0:bb348c97df44	334	in auto refresh mode.
lypinator	0:bb348c97df44	335	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
lypinator	0:bb348c97df44	336	uint32_t ModeRegisterDefinition; /!< Defines the SDRAM Mode register content /
lypinator	0:bb348c97df44	337	}FMC_SDRAM_CommandTypeDef;
lypinator	0:bb348c97df44	338	/**
lypinator	0:bb348c97df44	339	* @}
lypinator	0:bb348c97df44	340	*/
lypinator	0:bb348c97df44	341
lypinator	0:bb348c97df44	342	/* Private constants ---------------------------------------------------------*/
lypinator	0:bb348c97df44	343	/** @defgroup FMC_LL_Private_Constants FMC Private Constants
lypinator	0:bb348c97df44	344	* @{
lypinator	0:bb348c97df44	345	*/
lypinator	0:bb348c97df44	346
lypinator	0:bb348c97df44	347	/** @defgroup FMC_LL_NOR_SRAM_Controller FMC NOR/SRAM Controller
lypinator	0:bb348c97df44	348	* @{
lypinator	0:bb348c97df44	349	*/
lypinator	0:bb348c97df44	350	/** @defgroup FMC_NORSRAM_Bank FMC NOR/SRAM Bank
lypinator	0:bb348c97df44	351	* @{
lypinator	0:bb348c97df44	352	*/
lypinator	0:bb348c97df44	353	#define FMC_NORSRAM_BANK1 0x00000000U
lypinator	0:bb348c97df44	354	#define FMC_NORSRAM_BANK2 0x00000002U
lypinator	0:bb348c97df44	355	#define FMC_NORSRAM_BANK3 0x00000004U
lypinator	0:bb348c97df44	356	#define FMC_NORSRAM_BANK4 0x00000006U
lypinator	0:bb348c97df44	357	/**
lypinator	0:bb348c97df44	358	* @}
lypinator	0:bb348c97df44	359	*/
lypinator	0:bb348c97df44	360
lypinator	0:bb348c97df44	361	/** @defgroup FMC_Data_Address_Bus_Multiplexing FMC Data Address Bus Multiplexing
lypinator	0:bb348c97df44	362	* @{
lypinator	0:bb348c97df44	363	*/
lypinator	0:bb348c97df44	364	#define FMC_DATA_ADDRESS_MUX_DISABLE 0x00000000U
lypinator	0:bb348c97df44	365	#define FMC_DATA_ADDRESS_MUX_ENABLE 0x00000002U
lypinator	0:bb348c97df44	366	/**
lypinator	0:bb348c97df44	367	* @}
lypinator	0:bb348c97df44	368	*/
lypinator	0:bb348c97df44	369
lypinator	0:bb348c97df44	370	/** @defgroup FMC_Memory_Type FMC Memory Type
lypinator	0:bb348c97df44	371	* @{
lypinator	0:bb348c97df44	372	*/
lypinator	0:bb348c97df44	373	#define FMC_MEMORY_TYPE_SRAM 0x00000000U
lypinator	0:bb348c97df44	374	#define FMC_MEMORY_TYPE_PSRAM 0x00000004U
lypinator	0:bb348c97df44	375	#define FMC_MEMORY_TYPE_NOR 0x00000008U
lypinator	0:bb348c97df44	376	/**
lypinator	0:bb348c97df44	377	* @}
lypinator	0:bb348c97df44	378	*/
lypinator	0:bb348c97df44	379
lypinator	0:bb348c97df44	380	/** @defgroup FMC_NORSRAM_Data_Width FMC NORSRAM Data Width
lypinator	0:bb348c97df44	381	* @{
lypinator	0:bb348c97df44	382	*/
lypinator	0:bb348c97df44	383	#define FMC_NORSRAM_MEM_BUS_WIDTH_8 0x00000000U
lypinator	0:bb348c97df44	384	#define FMC_NORSRAM_MEM_BUS_WIDTH_16 0x00000010U
lypinator	0:bb348c97df44	385	#define FMC_NORSRAM_MEM_BUS_WIDTH_32 0x00000020U
lypinator	0:bb348c97df44	386	/**
lypinator	0:bb348c97df44	387	* @}
lypinator	0:bb348c97df44	388	*/
lypinator	0:bb348c97df44	389
lypinator	0:bb348c97df44	390	/** @defgroup FMC_NORSRAM_Flash_Access FMC NOR/SRAM Flash Access
lypinator	0:bb348c97df44	391	* @{
lypinator	0:bb348c97df44	392	*/
lypinator	0:bb348c97df44	393	#define FMC_NORSRAM_FLASH_ACCESS_ENABLE 0x00000040U
lypinator	0:bb348c97df44	394	#define FMC_NORSRAM_FLASH_ACCESS_DISABLE 0x00000000U
lypinator	0:bb348c97df44	395	/**
lypinator	0:bb348c97df44	396	* @}
lypinator	0:bb348c97df44	397	*/
lypinator	0:bb348c97df44	398
lypinator	0:bb348c97df44	399	/** @defgroup FMC_Burst_Access_Mode FMC Burst Access Mode
lypinator	0:bb348c97df44	400	* @{
lypinator	0:bb348c97df44	401	*/
lypinator	0:bb348c97df44	402	#define FMC_BURST_ACCESS_MODE_DISABLE 0x00000000U
lypinator	0:bb348c97df44	403	#define FMC_BURST_ACCESS_MODE_ENABLE 0x00000100U
lypinator	0:bb348c97df44	404	/**
lypinator	0:bb348c97df44	405	* @}
lypinator	0:bb348c97df44	406	*/
lypinator	0:bb348c97df44	407
lypinator	0:bb348c97df44	408	/** @defgroup FMC_Wait_Signal_Polarity FMC Wait Signal Polarity
lypinator	0:bb348c97df44	409	* @{
lypinator	0:bb348c97df44	410	*/
lypinator	0:bb348c97df44	411	#define FMC_WAIT_SIGNAL_POLARITY_LOW 0x00000000U
lypinator	0:bb348c97df44	412	#define FMC_WAIT_SIGNAL_POLARITY_HIGH 0x00000200U
lypinator	0:bb348c97df44	413	/**
lypinator	0:bb348c97df44	414	* @}
lypinator	0:bb348c97df44	415	*/
lypinator	0:bb348c97df44	416
lypinator	0:bb348c97df44	417	/** @defgroup FMC_Wrap_Mode FMC Wrap Mode
lypinator	0:bb348c97df44	418	* @{
lypinator	0:bb348c97df44	419	*/
lypinator	0:bb348c97df44	420	/** @note This mode is not available for the STM32F446/469/479xx devices
lypinator	0:bb348c97df44	421	*/
lypinator	0:bb348c97df44	422	#define FMC_WRAP_MODE_DISABLE 0x00000000U
lypinator	0:bb348c97df44	423	#define FMC_WRAP_MODE_ENABLE 0x00000400U
lypinator	0:bb348c97df44	424	/**
lypinator	0:bb348c97df44	425	* @}
lypinator	0:bb348c97df44	426	*/
lypinator	0:bb348c97df44	427
lypinator	0:bb348c97df44	428	/** @defgroup FMC_Wait_Timing FMC Wait Timing
lypinator	0:bb348c97df44	429	* @{
lypinator	0:bb348c97df44	430	*/
lypinator	0:bb348c97df44	431	#define FMC_WAIT_TIMING_BEFORE_WS 0x00000000U
lypinator	0:bb348c97df44	432	#define FMC_WAIT_TIMING_DURING_WS 0x00000800U
lypinator	0:bb348c97df44	433	/**
lypinator	0:bb348c97df44	434	* @}
lypinator	0:bb348c97df44	435	*/
lypinator	0:bb348c97df44	436
lypinator	0:bb348c97df44	437	/** @defgroup FMC_Write_Operation FMC Write Operation
lypinator	0:bb348c97df44	438	* @{
lypinator	0:bb348c97df44	439	*/
lypinator	0:bb348c97df44	440	#define FMC_WRITE_OPERATION_DISABLE 0x00000000U
lypinator	0:bb348c97df44	441	#define FMC_WRITE_OPERATION_ENABLE 0x00001000U
lypinator	0:bb348c97df44	442	/**
lypinator	0:bb348c97df44	443	* @}
lypinator	0:bb348c97df44	444	*/
lypinator	0:bb348c97df44	445
lypinator	0:bb348c97df44	446	/** @defgroup FMC_Wait_Signal FMC Wait Signal
lypinator	0:bb348c97df44	447	* @{
lypinator	0:bb348c97df44	448	*/
lypinator	0:bb348c97df44	449	#define FMC_WAIT_SIGNAL_DISABLE 0x00000000U
lypinator	0:bb348c97df44	450	#define FMC_WAIT_SIGNAL_ENABLE 0x00002000U
lypinator	0:bb348c97df44	451	/**
lypinator	0:bb348c97df44	452	* @}
lypinator	0:bb348c97df44	453	*/
lypinator	0:bb348c97df44	454
lypinator	0:bb348c97df44	455	/** @defgroup FMC_Extended_Mode FMC Extended Mode
lypinator	0:bb348c97df44	456	* @{
lypinator	0:bb348c97df44	457	*/
lypinator	0:bb348c97df44	458	#define FMC_EXTENDED_MODE_DISABLE 0x00000000U
lypinator	0:bb348c97df44	459	#define FMC_EXTENDED_MODE_ENABLE 0x00004000U
lypinator	0:bb348c97df44	460	/**
lypinator	0:bb348c97df44	461	* @}
lypinator	0:bb348c97df44	462	*/
lypinator	0:bb348c97df44	463
lypinator	0:bb348c97df44	464	/** @defgroup FMC_AsynchronousWait FMC Asynchronous Wait
lypinator	0:bb348c97df44	465	* @{
lypinator	0:bb348c97df44	466	*/
lypinator	0:bb348c97df44	467	#define FMC_ASYNCHRONOUS_WAIT_DISABLE 0x00000000U
lypinator	0:bb348c97df44	468	#define FMC_ASYNCHRONOUS_WAIT_ENABLE 0x00008000U
lypinator	0:bb348c97df44	469	/**
lypinator	0:bb348c97df44	470	* @}
lypinator	0:bb348c97df44	471	*/
lypinator	0:bb348c97df44	472
lypinator	0:bb348c97df44	473	/** @defgroup FMC_Page_Size FMC Page Size
lypinator	0:bb348c97df44	474	* @{
lypinator	0:bb348c97df44	475	*/
lypinator	0:bb348c97df44	476	#define FMC_PAGE_SIZE_NONE 0x00000000U
lypinator	0:bb348c97df44	477	#define FMC_PAGE_SIZE_128 ((uint32_t)FMC_BCR1_CPSIZE_0)
lypinator	0:bb348c97df44	478	#define FMC_PAGE_SIZE_256 ((uint32_t)FMC_BCR1_CPSIZE_1)
lypinator	0:bb348c97df44	479	#define FMC_PAGE_SIZE_512 ((uint32_t)(FMC_BCR1_CPSIZE_0 \| FMC_BCR1_CPSIZE_1))
lypinator	0:bb348c97df44	480	#define FMC_PAGE_SIZE_1024 ((uint32_t)FMC_BCR1_CPSIZE_2)
lypinator	0:bb348c97df44	481	/**
lypinator	0:bb348c97df44	482	* @}
lypinator	0:bb348c97df44	483	*/
lypinator	0:bb348c97df44	484
lypinator	0:bb348c97df44	485	/** @defgroup FMC_Write_FIFO FMC Write FIFO
lypinator	0:bb348c97df44	486	* @note These values are available only for the STM32F446/469/479xx devices.
lypinator	0:bb348c97df44	487	* @{
lypinator	0:bb348c97df44	488	*/
lypinator	0:bb348c97df44	489	#define FMC_WRITE_FIFO_DISABLE ((uint32_t)FMC_BCR1_WFDIS)
lypinator	0:bb348c97df44	490	#define FMC_WRITE_FIFO_ENABLE 0x00000000U
lypinator	0:bb348c97df44	491	/**
lypinator	0:bb348c97df44	492	* @}
lypinator	0:bb348c97df44	493	*/
lypinator	0:bb348c97df44	494
lypinator	0:bb348c97df44	495	/** @defgroup FMC_Write_Burst FMC Write Burst
lypinator	0:bb348c97df44	496	* @{
lypinator	0:bb348c97df44	497	*/
lypinator	0:bb348c97df44	498	#define FMC_WRITE_BURST_DISABLE 0x00000000U
lypinator	0:bb348c97df44	499	#define FMC_WRITE_BURST_ENABLE 0x00080000U
lypinator	0:bb348c97df44	500	/**
lypinator	0:bb348c97df44	501	* @}
lypinator	0:bb348c97df44	502	*/
lypinator	0:bb348c97df44	503
lypinator	0:bb348c97df44	504	/** @defgroup FMC_Continous_Clock FMC Continuous Clock
lypinator	0:bb348c97df44	505	* @{
lypinator	0:bb348c97df44	506	*/
lypinator	0:bb348c97df44	507	#define FMC_CONTINUOUS_CLOCK_SYNC_ONLY 0x00000000U
lypinator	0:bb348c97df44	508	#define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC 0x00100000U
lypinator	0:bb348c97df44	509	/**
lypinator	0:bb348c97df44	510	* @}
lypinator	0:bb348c97df44	511	*/
lypinator	0:bb348c97df44	512
lypinator	0:bb348c97df44	513	/** @defgroup FMC_Access_Mode FMC Access Mode
lypinator	0:bb348c97df44	514	* @{
lypinator	0:bb348c97df44	515	*/
lypinator	0:bb348c97df44	516	#define FMC_ACCESS_MODE_A 0x00000000U
lypinator	0:bb348c97df44	517	#define FMC_ACCESS_MODE_B 0x10000000U
lypinator	0:bb348c97df44	518	#define FMC_ACCESS_MODE_C 0x20000000U
lypinator	0:bb348c97df44	519	#define FMC_ACCESS_MODE_D 0x30000000U
lypinator	0:bb348c97df44	520	/**
lypinator	0:bb348c97df44	521	* @}
lypinator	0:bb348c97df44	522	*/
lypinator	0:bb348c97df44	523
lypinator	0:bb348c97df44	524	/**
lypinator	0:bb348c97df44	525	* @}
lypinator	0:bb348c97df44	526	*/
lypinator	0:bb348c97df44	527
lypinator	0:bb348c97df44	528	/** @defgroup FMC_LL_NAND_Controller FMC NAND Controller
lypinator	0:bb348c97df44	529	* @{
lypinator	0:bb348c97df44	530	*/
lypinator	0:bb348c97df44	531	/** @defgroup FMC_NAND_Bank FMC NAND Bank
lypinator	0:bb348c97df44	532	* @{
lypinator	0:bb348c97df44	533	*/
lypinator	0:bb348c97df44	534	#define FMC_NAND_BANK2 0x00000010U
lypinator	0:bb348c97df44	535	#define FMC_NAND_BANK3 0x00000100U
lypinator	0:bb348c97df44	536	/**
lypinator	0:bb348c97df44	537	* @}
lypinator	0:bb348c97df44	538	*/
lypinator	0:bb348c97df44	539
lypinator	0:bb348c97df44	540	/** @defgroup FMC_Wait_feature FMC Wait feature
lypinator	0:bb348c97df44	541	* @{
lypinator	0:bb348c97df44	542	*/
lypinator	0:bb348c97df44	543	#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE 0x00000000U
lypinator	0:bb348c97df44	544	#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE 0x00000002U
lypinator	0:bb348c97df44	545	/**
lypinator	0:bb348c97df44	546	* @}
lypinator	0:bb348c97df44	547	*/
lypinator	0:bb348c97df44	548
lypinator	0:bb348c97df44	549	/** @defgroup FMC_PCR_Memory_Type FMC PCR Memory Type
lypinator	0:bb348c97df44	550	* @{
lypinator	0:bb348c97df44	551	*/
lypinator	0:bb348c97df44	552	#define FMC_PCR_MEMORY_TYPE_PCCARD 0x00000000U
lypinator	0:bb348c97df44	553	#define FMC_PCR_MEMORY_TYPE_NAND 0x00000008U
lypinator	0:bb348c97df44	554	/**
lypinator	0:bb348c97df44	555	* @}
lypinator	0:bb348c97df44	556	*/
lypinator	0:bb348c97df44	557
lypinator	0:bb348c97df44	558	/** @defgroup FMC_NAND_Data_Width FMC NAND Data Width
lypinator	0:bb348c97df44	559	* @{
lypinator	0:bb348c97df44	560	*/
lypinator	0:bb348c97df44	561	#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 0x00000000U
lypinator	0:bb348c97df44	562	#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 0x00000010U
lypinator	0:bb348c97df44	563	/**
lypinator	0:bb348c97df44	564	* @}
lypinator	0:bb348c97df44	565	*/
lypinator	0:bb348c97df44	566
lypinator	0:bb348c97df44	567	/** @defgroup FMC_ECC FMC ECC
lypinator	0:bb348c97df44	568	* @{
lypinator	0:bb348c97df44	569	*/
lypinator	0:bb348c97df44	570	#define FMC_NAND_ECC_DISABLE 0x00000000U
lypinator	0:bb348c97df44	571	#define FMC_NAND_ECC_ENABLE 0x00000040U
lypinator	0:bb348c97df44	572	/**
lypinator	0:bb348c97df44	573	* @}
lypinator	0:bb348c97df44	574	*/
lypinator	0:bb348c97df44	575
lypinator	0:bb348c97df44	576	/** @defgroup FMC_ECC_Page_Size FMC ECC Page Size
lypinator	0:bb348c97df44	577	* @{
lypinator	0:bb348c97df44	578	*/
lypinator	0:bb348c97df44	579	#define FMC_NAND_ECC_PAGE_SIZE_256BYTE 0x00000000U
lypinator	0:bb348c97df44	580	#define FMC_NAND_ECC_PAGE_SIZE_512BYTE 0x00020000U
lypinator	0:bb348c97df44	581	#define FMC_NAND_ECC_PAGE_SIZE_1024BYTE 0x00040000U
lypinator	0:bb348c97df44	582	#define FMC_NAND_ECC_PAGE_SIZE_2048BYTE 0x00060000U
lypinator	0:bb348c97df44	583	#define FMC_NAND_ECC_PAGE_SIZE_4096BYTE 0x00080000U
lypinator	0:bb348c97df44	584	#define FMC_NAND_ECC_PAGE_SIZE_8192BYTE 0x000A0000U
lypinator	0:bb348c97df44	585	/**
lypinator	0:bb348c97df44	586	* @}
lypinator	0:bb348c97df44	587	*/
lypinator	0:bb348c97df44	588
lypinator	0:bb348c97df44	589	/**
lypinator	0:bb348c97df44	590	* @}
lypinator	0:bb348c97df44	591	*/
lypinator	0:bb348c97df44	592
lypinator	0:bb348c97df44	593	/** @defgroup FMC_LL_SDRAM_Controller FMC SDRAM Controller
lypinator	0:bb348c97df44	594	* @{
lypinator	0:bb348c97df44	595	*/
lypinator	0:bb348c97df44	596	/** @defgroup FMC_SDRAM_Bank FMC SDRAM Bank
lypinator	0:bb348c97df44	597	* @{
lypinator	0:bb348c97df44	598	*/
lypinator	0:bb348c97df44	599	#define FMC_SDRAM_BANK1 0x00000000U
lypinator	0:bb348c97df44	600	#define FMC_SDRAM_BANK2 0x00000001U
lypinator	0:bb348c97df44	601	/**
lypinator	0:bb348c97df44	602	* @}
lypinator	0:bb348c97df44	603	*/
lypinator	0:bb348c97df44	604
lypinator	0:bb348c97df44	605	/** @defgroup FMC_SDRAM_Column_Bits_number FMC SDRAM Column Bits number
lypinator	0:bb348c97df44	606	* @{
lypinator	0:bb348c97df44	607	*/
lypinator	0:bb348c97df44	608	#define FMC_SDRAM_COLUMN_BITS_NUM_8 0x00000000U
lypinator	0:bb348c97df44	609	#define FMC_SDRAM_COLUMN_BITS_NUM_9 0x00000001U
lypinator	0:bb348c97df44	610	#define FMC_SDRAM_COLUMN_BITS_NUM_10 0x00000002U
lypinator	0:bb348c97df44	611	#define FMC_SDRAM_COLUMN_BITS_NUM_11 0x00000003U
lypinator	0:bb348c97df44	612	/**
lypinator	0:bb348c97df44	613	* @}
lypinator	0:bb348c97df44	614	*/
lypinator	0:bb348c97df44	615
lypinator	0:bb348c97df44	616	/** @defgroup FMC_SDRAM_Row_Bits_number FMC SDRAM Row Bits number
lypinator	0:bb348c97df44	617	* @{
lypinator	0:bb348c97df44	618	*/
lypinator	0:bb348c97df44	619	#define FMC_SDRAM_ROW_BITS_NUM_11 0x00000000U
lypinator	0:bb348c97df44	620	#define FMC_SDRAM_ROW_BITS_NUM_12 0x00000004U
lypinator	0:bb348c97df44	621	#define FMC_SDRAM_ROW_BITS_NUM_13 0x00000008U
lypinator	0:bb348c97df44	622	/**
lypinator	0:bb348c97df44	623	* @}
lypinator	0:bb348c97df44	624	*/
lypinator	0:bb348c97df44	625
lypinator	0:bb348c97df44	626	/** @defgroup FMC_SDRAM_Memory_Bus_Width FMC SDRAM Memory Bus Width
lypinator	0:bb348c97df44	627	* @{
lypinator	0:bb348c97df44	628	*/
lypinator	0:bb348c97df44	629	#define FMC_SDRAM_MEM_BUS_WIDTH_8 0x00000000U
lypinator	0:bb348c97df44	630	#define FMC_SDRAM_MEM_BUS_WIDTH_16 0x00000010U
lypinator	0:bb348c97df44	631	#define FMC_SDRAM_MEM_BUS_WIDTH_32 0x00000020U
lypinator	0:bb348c97df44	632	/**
lypinator	0:bb348c97df44	633	* @}
lypinator	0:bb348c97df44	634	*/
lypinator	0:bb348c97df44	635
lypinator	0:bb348c97df44	636	/** @defgroup FMC_SDRAM_Internal_Banks_Number FMC SDRAM Internal Banks Number
lypinator	0:bb348c97df44	637	* @{
lypinator	0:bb348c97df44	638	*/
lypinator	0:bb348c97df44	639	#define FMC_SDRAM_INTERN_BANKS_NUM_2 0x00000000U
lypinator	0:bb348c97df44	640	#define FMC_SDRAM_INTERN_BANKS_NUM_4 0x00000040U
lypinator	0:bb348c97df44	641	/**
lypinator	0:bb348c97df44	642	* @}
lypinator	0:bb348c97df44	643	*/
lypinator	0:bb348c97df44	644
lypinator	0:bb348c97df44	645	/** @defgroup FMC_SDRAM_CAS_Latency FMC SDRAM CAS Latency
lypinator	0:bb348c97df44	646	* @{
lypinator	0:bb348c97df44	647	*/
lypinator	0:bb348c97df44	648	#define FMC_SDRAM_CAS_LATENCY_1 0x00000080U
lypinator	0:bb348c97df44	649	#define FMC_SDRAM_CAS_LATENCY_2 0x00000100U
lypinator	0:bb348c97df44	650	#define FMC_SDRAM_CAS_LATENCY_3 0x00000180U
lypinator	0:bb348c97df44	651	/**
lypinator	0:bb348c97df44	652	* @}
lypinator	0:bb348c97df44	653	*/
lypinator	0:bb348c97df44	654
lypinator	0:bb348c97df44	655	/** @defgroup FMC_SDRAM_Write_Protection FMC SDRAM Write Protection
lypinator	0:bb348c97df44	656	* @{
lypinator	0:bb348c97df44	657	*/
lypinator	0:bb348c97df44	658	#define FMC_SDRAM_WRITE_PROTECTION_DISABLE 0x00000000U
lypinator	0:bb348c97df44	659	#define FMC_SDRAM_WRITE_PROTECTION_ENABLE 0x00000200U
lypinator	0:bb348c97df44	660
lypinator	0:bb348c97df44	661	/**
lypinator	0:bb348c97df44	662	* @}
lypinator	0:bb348c97df44	663	*/
lypinator	0:bb348c97df44	664
lypinator	0:bb348c97df44	665	/** @defgroup FMC_SDRAM_Clock_Period FMC SDRAM Clock Period
lypinator	0:bb348c97df44	666	* @{
lypinator	0:bb348c97df44	667	*/
lypinator	0:bb348c97df44	668	#define FMC_SDRAM_CLOCK_DISABLE 0x00000000U
lypinator	0:bb348c97df44	669	#define FMC_SDRAM_CLOCK_PERIOD_2 0x00000800U
lypinator	0:bb348c97df44	670	#define FMC_SDRAM_CLOCK_PERIOD_3 0x00000C00U
lypinator	0:bb348c97df44	671	/**
lypinator	0:bb348c97df44	672	* @}
lypinator	0:bb348c97df44	673	*/
lypinator	0:bb348c97df44	674
lypinator	0:bb348c97df44	675	/** @defgroup FMC_SDRAM_Read_Burst FMC SDRAM Read Burst
lypinator	0:bb348c97df44	676	* @{
lypinator	0:bb348c97df44	677	*/
lypinator	0:bb348c97df44	678	#define FMC_SDRAM_RBURST_DISABLE 0x00000000U
lypinator	0:bb348c97df44	679	#define FMC_SDRAM_RBURST_ENABLE 0x00001000U
lypinator	0:bb348c97df44	680	/**
lypinator	0:bb348c97df44	681	* @}
lypinator	0:bb348c97df44	682	*/
lypinator	0:bb348c97df44	683
lypinator	0:bb348c97df44	684	/** @defgroup FMC_SDRAM_Read_Pipe_Delay FMC SDRAM Read Pipe Delay
lypinator	0:bb348c97df44	685	* @{
lypinator	0:bb348c97df44	686	*/
lypinator	0:bb348c97df44	687	#define FMC_SDRAM_RPIPE_DELAY_0 0x00000000U
lypinator	0:bb348c97df44	688	#define FMC_SDRAM_RPIPE_DELAY_1 0x00002000U
lypinator	0:bb348c97df44	689	#define FMC_SDRAM_RPIPE_DELAY_2 0x00004000U
lypinator	0:bb348c97df44	690	/**
lypinator	0:bb348c97df44	691	* @}
lypinator	0:bb348c97df44	692	*/
lypinator	0:bb348c97df44	693
lypinator	0:bb348c97df44	694	/** @defgroup FMC_SDRAM_Command_Mode FMC SDRAM Command Mode
lypinator	0:bb348c97df44	695	* @{
lypinator	0:bb348c97df44	696	*/
lypinator	0:bb348c97df44	697	#define FMC_SDRAM_CMD_NORMAL_MODE 0x00000000U
lypinator	0:bb348c97df44	698	#define FMC_SDRAM_CMD_CLK_ENABLE 0x00000001U
lypinator	0:bb348c97df44	699	#define FMC_SDRAM_CMD_PALL 0x00000002U
lypinator	0:bb348c97df44	700	#define FMC_SDRAM_CMD_AUTOREFRESH_MODE 0x00000003U
lypinator	0:bb348c97df44	701	#define FMC_SDRAM_CMD_LOAD_MODE 0x00000004U
lypinator	0:bb348c97df44	702	#define FMC_SDRAM_CMD_SELFREFRESH_MODE 0x00000005U
lypinator	0:bb348c97df44	703	#define FMC_SDRAM_CMD_POWERDOWN_MODE 0x00000006U
lypinator	0:bb348c97df44	704	/**
lypinator	0:bb348c97df44	705	* @}
lypinator	0:bb348c97df44	706	*/
lypinator	0:bb348c97df44	707
lypinator	0:bb348c97df44	708	/** @defgroup FMC_SDRAM_Command_Target FMC SDRAM Command Target
lypinator	0:bb348c97df44	709	* @{
lypinator	0:bb348c97df44	710	*/
lypinator	0:bb348c97df44	711	#define FMC_SDRAM_CMD_TARGET_BANK2 FMC_SDCMR_CTB2
lypinator	0:bb348c97df44	712	#define FMC_SDRAM_CMD_TARGET_BANK1 FMC_SDCMR_CTB1
lypinator	0:bb348c97df44	713	#define FMC_SDRAM_CMD_TARGET_BANK1_2 0x00000018U
lypinator	0:bb348c97df44	714	/**
lypinator	0:bb348c97df44	715	* @}
lypinator	0:bb348c97df44	716	*/
lypinator	0:bb348c97df44	717
lypinator	0:bb348c97df44	718	/** @defgroup FMC_SDRAM_Mode_Status FMC SDRAM Mode Status
lypinator	0:bb348c97df44	719	* @{
lypinator	0:bb348c97df44	720	*/
lypinator	0:bb348c97df44	721	#define FMC_SDRAM_NORMAL_MODE 0x00000000U
lypinator	0:bb348c97df44	722	#define FMC_SDRAM_SELF_REFRESH_MODE FMC_SDSR_MODES1_0
lypinator	0:bb348c97df44	723	#define FMC_SDRAM_POWER_DOWN_MODE FMC_SDSR_MODES1_1
lypinator	0:bb348c97df44	724	/**
lypinator	0:bb348c97df44	725	* @}
lypinator	0:bb348c97df44	726	*/
lypinator	0:bb348c97df44	727
lypinator	0:bb348c97df44	728	/**
lypinator	0:bb348c97df44	729	* @}
lypinator	0:bb348c97df44	730	*/
lypinator	0:bb348c97df44	731
lypinator	0:bb348c97df44	732	/** @defgroup FMC_LL_Interrupt_definition FMC Interrupt definition
lypinator	0:bb348c97df44	733	* @{
lypinator	0:bb348c97df44	734	*/
lypinator	0:bb348c97df44	735	#define FMC_IT_RISING_EDGE 0x00000008U
lypinator	0:bb348c97df44	736	#define FMC_IT_LEVEL 0x00000010U
lypinator	0:bb348c97df44	737	#define FMC_IT_FALLING_EDGE 0x00000020U
lypinator	0:bb348c97df44	738	#define FMC_IT_REFRESH_ERROR 0x00004000U
lypinator	0:bb348c97df44	739	/**
lypinator	0:bb348c97df44	740	* @}
lypinator	0:bb348c97df44	741	*/
lypinator	0:bb348c97df44	742
lypinator	0:bb348c97df44	743	/** @defgroup FMC_LL_Flag_definition FMC Flag definition
lypinator	0:bb348c97df44	744	* @{
lypinator	0:bb348c97df44	745	*/
lypinator	0:bb348c97df44	746	#define FMC_FLAG_RISING_EDGE 0x00000001U
lypinator	0:bb348c97df44	747	#define FMC_FLAG_LEVEL 0x00000002U
lypinator	0:bb348c97df44	748	#define FMC_FLAG_FALLING_EDGE 0x00000004U
lypinator	0:bb348c97df44	749	#define FMC_FLAG_FEMPT 0x00000040U
lypinator	0:bb348c97df44	750	#define FMC_SDRAM_FLAG_REFRESH_IT FMC_SDSR_RE
lypinator	0:bb348c97df44	751	#define FMC_SDRAM_FLAG_BUSY FMC_SDSR_BUSY
lypinator	0:bb348c97df44	752	#define FMC_SDRAM_FLAG_REFRESH_ERROR FMC_SDRTR_CRE
lypinator	0:bb348c97df44	753	/**
lypinator	0:bb348c97df44	754	* @}
lypinator	0:bb348c97df44	755	*/
lypinator	0:bb348c97df44	756
lypinator	0:bb348c97df44	757	/** @defgroup FMC_LL_Alias_definition FMC Alias definition
lypinator	0:bb348c97df44	758	* @{
lypinator	0:bb348c97df44	759	*/
lypinator	0:bb348c97df44	760	#if defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
lypinator	0:bb348c97df44	761	#define FMC_NAND_TypeDef FMC_Bank3_TypeDef
lypinator	0:bb348c97df44	762	#else
lypinator	0:bb348c97df44	763	#define FMC_NAND_TypeDef FMC_Bank2_3_TypeDef
lypinator	0:bb348c97df44	764	#define FMC_PCCARD_TypeDef FMC_Bank4_TypeDef
lypinator	0:bb348c97df44	765	#endif /* STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
lypinator	0:bb348c97df44	766	#define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef
lypinator	0:bb348c97df44	767	#define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef
lypinator	0:bb348c97df44	768	#define FMC_SDRAM_TypeDef FMC_Bank5_6_TypeDef
lypinator	0:bb348c97df44	769
lypinator	0:bb348c97df44	770
lypinator	0:bb348c97df44	771	#if defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
lypinator	0:bb348c97df44	772	#define FMC_NAND_DEVICE FMC_Bank3
lypinator	0:bb348c97df44	773	#else
lypinator	0:bb348c97df44	774	#define FMC_NAND_DEVICE FMC_Bank2_3
lypinator	0:bb348c97df44	775	#define FMC_PCCARD_DEVICE FMC_Bank4
lypinator	0:bb348c97df44	776	#endif /* STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
lypinator	0:bb348c97df44	777	#define FMC_NORSRAM_DEVICE FMC_Bank1
lypinator	0:bb348c97df44	778	#define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E
lypinator	0:bb348c97df44	779	#define FMC_SDRAM_DEVICE FMC_Bank5_6
lypinator	0:bb348c97df44	780	/**
lypinator	0:bb348c97df44	781	* @}
lypinator	0:bb348c97df44	782	*/
lypinator	0:bb348c97df44	783
lypinator	0:bb348c97df44	784	/**
lypinator	0:bb348c97df44	785	* @}
lypinator	0:bb348c97df44	786	*/
lypinator	0:bb348c97df44	787
lypinator	0:bb348c97df44	788	/* Private macro -------------------------------------------------------------*/
lypinator	0:bb348c97df44	789	/** @defgroup FMC_LL_Private_Macros FMC Private Macros
lypinator	0:bb348c97df44	790	* @{
lypinator	0:bb348c97df44	791	*/
lypinator	0:bb348c97df44	792
lypinator	0:bb348c97df44	793	/** @defgroup FMC_LL_NOR_Macros FMC NOR/SRAM Macros
lypinator	0:bb348c97df44	794	* @brief macros to handle NOR device enable/disable and read/write operations
lypinator	0:bb348c97df44	795	* @{
lypinator	0:bb348c97df44	796	*/
lypinator	0:bb348c97df44	797	/**
lypinator	0:bb348c97df44	798	* @brief Enable the NORSRAM device access.
lypinator	0:bb348c97df44	799	* @param __INSTANCE__ FMC_NORSRAM Instance
lypinator	0:bb348c97df44	800	* @param __BANK__ FMC_NORSRAM Bank
lypinator	0:bb348c97df44	801	* @retval None
lypinator	0:bb348c97df44	802	*/
lypinator	0:bb348c97df44	803	#define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] \|= FMC_BCR1_MBKEN)
lypinator	0:bb348c97df44	804
lypinator	0:bb348c97df44	805	/**
lypinator	0:bb348c97df44	806	* @brief Disable the NORSRAM device access.
lypinator	0:bb348c97df44	807	* @param __INSTANCE__ FMC_NORSRAM Instance
lypinator	0:bb348c97df44	808	* @param __BANK__ FMC_NORSRAM Bank
lypinator	0:bb348c97df44	809	* @retval None
lypinator	0:bb348c97df44	810	*/
lypinator	0:bb348c97df44	811	#define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FMC_BCR1_MBKEN)
lypinator	0:bb348c97df44	812	/**
lypinator	0:bb348c97df44	813	* @}
lypinator	0:bb348c97df44	814	*/
lypinator	0:bb348c97df44	815
lypinator	0:bb348c97df44	816	/** @defgroup FMC_LL_NAND_Macros FMC NAND Macros
lypinator	0:bb348c97df44	817	* @brief macros to handle NAND device enable/disable
lypinator	0:bb348c97df44	818	* @{
lypinator	0:bb348c97df44	819	*/
lypinator	0:bb348c97df44	820	#if defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
lypinator	0:bb348c97df44	821	/**
lypinator	0:bb348c97df44	822	* @brief Enable the NAND device access.
lypinator	0:bb348c97df44	823	* @param __INSTANCE__ FMC_NAND Instance
lypinator	0:bb348c97df44	824	* @param __BANK__ FMC_NAND Bank
lypinator	0:bb348c97df44	825	* @retval None
lypinator	0:bb348c97df44	826	*/
lypinator	0:bb348c97df44	827	#define __FMC_NAND_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->PCR \|= FMC_PCR_PBKEN)
lypinator	0:bb348c97df44	828
lypinator	0:bb348c97df44	829	/**
lypinator	0:bb348c97df44	830	* @brief Disable the NAND device access.
lypinator	0:bb348c97df44	831	* @param __INSTANCE__ FMC_NAND Instance
lypinator	0:bb348c97df44	832	* @param __BANK__ FMC_NAND Bank
lypinator	0:bb348c97df44	833	* @retval None
lypinator	0:bb348c97df44	834	*/
lypinator	0:bb348c97df44	835	#define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->PCR &= ~FMC_PCR_PBKEN)
lypinator	0:bb348c97df44	836	#else /* defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) */
lypinator	0:bb348c97df44	837	/**
lypinator	0:bb348c97df44	838	* @brief Enable the NAND device access.
lypinator	0:bb348c97df44	839	* @param __INSTANCE__ FMC_NAND Instance
lypinator	0:bb348c97df44	840	* @param __BANK__ FMC_NAND Bank
lypinator	0:bb348c97df44	841	* @retval None
lypinator	0:bb348c97df44	842	*/
lypinator	0:bb348c97df44	843	#define __FMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 \|= FMC_PCR2_PBKEN): \
lypinator	0:bb348c97df44	844	((__INSTANCE__)->PCR3 \|= FMC_PCR3_PBKEN))
lypinator	0:bb348c97df44	845
lypinator	0:bb348c97df44	846	/**
lypinator	0:bb348c97df44	847	* @brief Disable the NAND device access.
lypinator	0:bb348c97df44	848	* @param __INSTANCE__ FMC_NAND Instance
lypinator	0:bb348c97df44	849	* @param __BANK__ FMC_NAND Bank
lypinator	0:bb348c97df44	850	* @retval None
lypinator	0:bb348c97df44	851	*/
lypinator	0:bb348c97df44	852	#define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 &= ~FMC_PCR2_PBKEN): \
lypinator	0:bb348c97df44	853	((__INSTANCE__)->PCR3 &= ~FMC_PCR3_PBKEN))
lypinator	0:bb348c97df44	854
lypinator	0:bb348c97df44	855	#endif /* defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx) */
lypinator	0:bb348c97df44	856	/**
lypinator	0:bb348c97df44	857	* @}
lypinator	0:bb348c97df44	858	*/
lypinator	0:bb348c97df44	859	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
lypinator	0:bb348c97df44	860	/** @defgroup FMC_LL_PCCARD_Macros FMC PCCARD Macros
lypinator	0:bb348c97df44	861	* @brief macros to handle SRAM read/write operations
lypinator	0:bb348c97df44	862	* @{
lypinator	0:bb348c97df44	863	*/
lypinator	0:bb348c97df44	864	/**
lypinator	0:bb348c97df44	865	* @brief Enable the PCCARD device access.
lypinator	0:bb348c97df44	866	* @param __INSTANCE__ FMC_PCCARD Instance
lypinator	0:bb348c97df44	867	* @retval None
lypinator	0:bb348c97df44	868	*/
lypinator	0:bb348c97df44	869	#define __FMC_PCCARD_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 \|= FMC_PCR4_PBKEN)
lypinator	0:bb348c97df44	870
lypinator	0:bb348c97df44	871	/**
lypinator	0:bb348c97df44	872	* @brief Disable the PCCARD device access.
lypinator	0:bb348c97df44	873	* @param __INSTANCE__ FMC_PCCARD Instance
lypinator	0:bb348c97df44	874	* @retval None
lypinator	0:bb348c97df44	875	*/
lypinator	0:bb348c97df44	876	#define __FMC_PCCARD_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 &= ~FMC_PCR4_PBKEN)
lypinator	0:bb348c97df44	877	/**
lypinator	0:bb348c97df44	878	* @}
lypinator	0:bb348c97df44	879	*/
lypinator	0:bb348c97df44	880	#endif /* defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) */
lypinator	0:bb348c97df44	881
lypinator	0:bb348c97df44	882	/** @defgroup FMC_LL_Flag_Interrupt_Macros FMC Flag&Interrupt Macros
lypinator	0:bb348c97df44	883	* @brief macros to handle FMC flags and interrupts
lypinator	0:bb348c97df44	884	* @{
lypinator	0:bb348c97df44	885	*/
lypinator	0:bb348c97df44	886	#if defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
lypinator	0:bb348c97df44	887	/**
lypinator	0:bb348c97df44	888	* @brief Enable the NAND device interrupt.
lypinator	0:bb348c97df44	889	* @param __INSTANCE__ FMC_NAND instance
lypinator	0:bb348c97df44	890	* @param __BANK__ FMC_NAND Bank
lypinator	0:bb348c97df44	891	* @param __INTERRUPT__ FMC_NAND interrupt
lypinator	0:bb348c97df44	892	* This parameter can be any combination of the following values:
lypinator	0:bb348c97df44	893	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
lypinator	0:bb348c97df44	894	* @arg FMC_IT_LEVEL: Interrupt level.
lypinator	0:bb348c97df44	895	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
lypinator	0:bb348c97df44	896	* @retval None
lypinator	0:bb348c97df44	897	*/
lypinator	0:bb348c97df44	898	#define __FMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) ((__INSTANCE__)->SR \|= (__INTERRUPT__))
lypinator	0:bb348c97df44	899
lypinator	0:bb348c97df44	900	/**
lypinator	0:bb348c97df44	901	* @brief Disable the NAND device interrupt.
lypinator	0:bb348c97df44	902	* @param __INSTANCE__ FMC_NAND Instance
lypinator	0:bb348c97df44	903	* @param __BANK__ FMC_NAND Bank
lypinator	0:bb348c97df44	904	* @param __INTERRUPT__ FMC_NAND interrupt
lypinator	0:bb348c97df44	905	* This parameter can be any combination of the following values:
lypinator	0:bb348c97df44	906	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
lypinator	0:bb348c97df44	907	* @arg FMC_IT_LEVEL: Interrupt level.
lypinator	0:bb348c97df44	908	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
lypinator	0:bb348c97df44	909	* @retval None
lypinator	0:bb348c97df44	910	*/
lypinator	0:bb348c97df44	911	#define __FMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) ((__INSTANCE__)->SR &= ~(__INTERRUPT__))
lypinator	0:bb348c97df44	912
lypinator	0:bb348c97df44	913	/**
lypinator	0:bb348c97df44	914	* @brief Get flag status of the NAND device.
lypinator	0:bb348c97df44	915	* @param __INSTANCE__ FMC_NAND Instance
lypinator	0:bb348c97df44	916	* @param __BANK__ FMC_NAND Bank
lypinator	0:bb348c97df44	917	* @param __FLAG__ FMC_NAND flag
lypinator	0:bb348c97df44	918	* This parameter can be any combination of the following values:
lypinator	0:bb348c97df44	919	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
lypinator	0:bb348c97df44	920	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
lypinator	0:bb348c97df44	921	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
lypinator	0:bb348c97df44	922	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
lypinator	0:bb348c97df44	923	* @retval The state of FLAG (SET or RESET).
lypinator	0:bb348c97df44	924	*/
lypinator	0:bb348c97df44	925	#define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__INSTANCE__)->SR &(__FLAG__)) == (__FLAG__))
lypinator	0:bb348c97df44	926	/**
lypinator	0:bb348c97df44	927	* @brief Clear flag status of the NAND device.
lypinator	0:bb348c97df44	928	* @param __INSTANCE__ FMC_NAND Instance
lypinator	0:bb348c97df44	929	* @param __BANK__ FMC_NAND Bank
lypinator	0:bb348c97df44	930	* @param __FLAG__ FMC_NAND flag
lypinator	0:bb348c97df44	931	* This parameter can be any combination of the following values:
lypinator	0:bb348c97df44	932	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
lypinator	0:bb348c97df44	933	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
lypinator	0:bb348c97df44	934	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
lypinator	0:bb348c97df44	935	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
lypinator	0:bb348c97df44	936	* @retval None
lypinator	0:bb348c97df44	937	*/
lypinator	0:bb348c97df44	938	#define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) ((__INSTANCE__)->SR &= ~(__FLAG__))
lypinator	0:bb348c97df44	939	#else /* defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) */
lypinator	0:bb348c97df44	940	/**
lypinator	0:bb348c97df44	941	* @brief Enable the NAND device interrupt.
lypinator	0:bb348c97df44	942	* @param __INSTANCE__ FMC_NAND instance
lypinator	0:bb348c97df44	943	* @param __BANK__ FMC_NAND Bank
lypinator	0:bb348c97df44	944	* @param __INTERRUPT__ FMC_NAND interrupt
lypinator	0:bb348c97df44	945	* This parameter can be any combination of the following values:
lypinator	0:bb348c97df44	946	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
lypinator	0:bb348c97df44	947	* @arg FMC_IT_LEVEL: Interrupt level.
lypinator	0:bb348c97df44	948	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
lypinator	0:bb348c97df44	949	* @retval None
lypinator	0:bb348c97df44	950	*/
lypinator	0:bb348c97df44	951	#define __FMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 \|= (__INTERRUPT__)): \
lypinator	0:bb348c97df44	952	((__INSTANCE__)->SR3 \|= (__INTERRUPT__)))
lypinator	0:bb348c97df44	953
lypinator	0:bb348c97df44	954	/**
lypinator	0:bb348c97df44	955	* @brief Disable the NAND device interrupt.
lypinator	0:bb348c97df44	956	* @param __INSTANCE__ FMC_NAND Instance
lypinator	0:bb348c97df44	957	* @param __BANK__ FMC_NAND Bank
lypinator	0:bb348c97df44	958	* @param __INTERRUPT__ FMC_NAND interrupt
lypinator	0:bb348c97df44	959	* This parameter can be any combination of the following values:
lypinator	0:bb348c97df44	960	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
lypinator	0:bb348c97df44	961	* @arg FMC_IT_LEVEL: Interrupt level.
lypinator	0:bb348c97df44	962	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
lypinator	0:bb348c97df44	963	* @retval None
lypinator	0:bb348c97df44	964	*/
lypinator	0:bb348c97df44	965	#define __FMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)): \
lypinator	0:bb348c97df44	966	((__INSTANCE__)->SR3 &= ~(__INTERRUPT__)))
lypinator	0:bb348c97df44	967
lypinator	0:bb348c97df44	968	/**
lypinator	0:bb348c97df44	969	* @brief Get flag status of the NAND device.
lypinator	0:bb348c97df44	970	* @param __INSTANCE__ FMC_NAND Instance
lypinator	0:bb348c97df44	971	* @param __BANK__ FMC_NAND Bank
lypinator	0:bb348c97df44	972	* @param __FLAG__ FMC_NAND flag
lypinator	0:bb348c97df44	973	* This parameter can be any combination of the following values:
lypinator	0:bb348c97df44	974	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
lypinator	0:bb348c97df44	975	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
lypinator	0:bb348c97df44	976	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
lypinator	0:bb348c97df44	977	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
lypinator	0:bb348c97df44	978	* @retval The state of FLAG (SET or RESET).
lypinator	0:bb348c97df44	979	*/
lypinator	0:bb348c97df44	980	#define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \
lypinator	0:bb348c97df44	981	(((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
lypinator	0:bb348c97df44	982	/**
lypinator	0:bb348c97df44	983	* @brief Clear flag status of the NAND device.
lypinator	0:bb348c97df44	984	* @param __INSTANCE__ FMC_NAND Instance
lypinator	0:bb348c97df44	985	* @param __BANK__ FMC_NAND Bank
lypinator	0:bb348c97df44	986	* @param __FLAG__ FMC_NAND flag
lypinator	0:bb348c97df44	987	* This parameter can be any combination of the following values:
lypinator	0:bb348c97df44	988	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
lypinator	0:bb348c97df44	989	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
lypinator	0:bb348c97df44	990	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
lypinator	0:bb348c97df44	991	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
lypinator	0:bb348c97df44	992	* @retval None
lypinator	0:bb348c97df44	993	*/
lypinator	0:bb348c97df44	994	#define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__FLAG__)): \
lypinator	0:bb348c97df44	995	((__INSTANCE__)->SR3 &= ~(__FLAG__)))
lypinator	0:bb348c97df44	996	#endif /* defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx) */
lypinator	0:bb348c97df44	997
lypinator	0:bb348c97df44	998	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
lypinator	0:bb348c97df44	999	/**
lypinator	0:bb348c97df44	1000	* @brief Enable the PCCARD device interrupt.
lypinator	0:bb348c97df44	1001	* @param __INSTANCE__ FMC_PCCARD instance
lypinator	0:bb348c97df44	1002	* @param __INTERRUPT__ FMC_PCCARD interrupt
lypinator	0:bb348c97df44	1003	* This parameter can be any combination of the following values:
lypinator	0:bb348c97df44	1004	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
lypinator	0:bb348c97df44	1005	* @arg FMC_IT_LEVEL: Interrupt level.
lypinator	0:bb348c97df44	1006	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
lypinator	0:bb348c97df44	1007	* @retval None
lypinator	0:bb348c97df44	1008	*/
lypinator	0:bb348c97df44	1009	#define __FMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 \|= (__INTERRUPT__))
lypinator	0:bb348c97df44	1010
lypinator	0:bb348c97df44	1011	/**
lypinator	0:bb348c97df44	1012	* @brief Disable the PCCARD device interrupt.
lypinator	0:bb348c97df44	1013	* @param __INSTANCE__ FMC_PCCARD instance
lypinator	0:bb348c97df44	1014	* @param __INTERRUPT__ FMC_PCCARD interrupt
lypinator	0:bb348c97df44	1015	* This parameter can be any combination of the following values:
lypinator	0:bb348c97df44	1016	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
lypinator	0:bb348c97df44	1017	* @arg FMC_IT_LEVEL: Interrupt level.
lypinator	0:bb348c97df44	1018	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
lypinator	0:bb348c97df44	1019	* @retval None
lypinator	0:bb348c97df44	1020	*/
lypinator	0:bb348c97df44	1021	#define __FMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 &= ~(__INTERRUPT__))
lypinator	0:bb348c97df44	1022
lypinator	0:bb348c97df44	1023	/**
lypinator	0:bb348c97df44	1024	* @brief Get flag status of the PCCARD device.
lypinator	0:bb348c97df44	1025	* @param __INSTANCE__ FMC_PCCARD instance
lypinator	0:bb348c97df44	1026	* @param __FLAG__ FMC_PCCARD flag
lypinator	0:bb348c97df44	1027	* This parameter can be any combination of the following values:
lypinator	0:bb348c97df44	1028	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
lypinator	0:bb348c97df44	1029	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
lypinator	0:bb348c97df44	1030	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
lypinator	0:bb348c97df44	1031	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
lypinator	0:bb348c97df44	1032	* @retval The state of FLAG (SET or RESET).
lypinator	0:bb348c97df44	1033	*/
lypinator	0:bb348c97df44	1034	#define __FMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__))
lypinator	0:bb348c97df44	1035
lypinator	0:bb348c97df44	1036	/**
lypinator	0:bb348c97df44	1037	* @brief Clear flag status of the PCCARD device.
lypinator	0:bb348c97df44	1038	* @param __INSTANCE__ FMC_PCCARD instance
lypinator	0:bb348c97df44	1039	* @param __FLAG__ FMC_PCCARD flag
lypinator	0:bb348c97df44	1040	* This parameter can be any combination of the following values:
lypinator	0:bb348c97df44	1041	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
lypinator	0:bb348c97df44	1042	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
lypinator	0:bb348c97df44	1043	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
lypinator	0:bb348c97df44	1044	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
lypinator	0:bb348c97df44	1045	* @retval None
lypinator	0:bb348c97df44	1046	*/
lypinator	0:bb348c97df44	1047	#define __FMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR4 &= ~(__FLAG__))
lypinator	0:bb348c97df44	1048	#endif /* defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) */
lypinator	0:bb348c97df44	1049
lypinator	0:bb348c97df44	1050	/**
lypinator	0:bb348c97df44	1051	* @brief Enable the SDRAM device interrupt.
lypinator	0:bb348c97df44	1052	* @param __INSTANCE__ FMC_SDRAM instance
lypinator	0:bb348c97df44	1053	* @param __INTERRUPT__ FMC_SDRAM interrupt
lypinator	0:bb348c97df44	1054	* This parameter can be any combination of the following values:
lypinator	0:bb348c97df44	1055	* @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error
lypinator	0:bb348c97df44	1056	* @retval None
lypinator	0:bb348c97df44	1057	*/
lypinator	0:bb348c97df44	1058	#define __FMC_SDRAM_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR \|= (__INTERRUPT__))
lypinator	0:bb348c97df44	1059
lypinator	0:bb348c97df44	1060	/**
lypinator	0:bb348c97df44	1061	* @brief Disable the SDRAM device interrupt.
lypinator	0:bb348c97df44	1062	* @param __INSTANCE__ FMC_SDRAM instance
lypinator	0:bb348c97df44	1063	* @param __INTERRUPT__ FMC_SDRAM interrupt
lypinator	0:bb348c97df44	1064	* This parameter can be any combination of the following values:
lypinator	0:bb348c97df44	1065	* @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error
lypinator	0:bb348c97df44	1066	* @retval None
lypinator	0:bb348c97df44	1067	*/
lypinator	0:bb348c97df44	1068	#define __FMC_SDRAM_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR &= ~(__INTERRUPT__))
lypinator	0:bb348c97df44	1069
lypinator	0:bb348c97df44	1070	/**
lypinator	0:bb348c97df44	1071	* @brief Get flag status of the SDRAM device.
lypinator	0:bb348c97df44	1072	* @param __INSTANCE__ FMC_SDRAM instance
lypinator	0:bb348c97df44	1073	* @param __FLAG__ FMC_SDRAM flag
lypinator	0:bb348c97df44	1074	* This parameter can be any combination of the following values:
lypinator	0:bb348c97df44	1075	* @arg FMC_SDRAM_FLAG_REFRESH_IT: Interrupt refresh error.
lypinator	0:bb348c97df44	1076	* @arg FMC_SDRAM_FLAG_BUSY: SDRAM busy flag.
lypinator	0:bb348c97df44	1077	* @arg FMC_SDRAM_FLAG_REFRESH_ERROR: Refresh error flag.
lypinator	0:bb348c97df44	1078	* @retval The state of FLAG (SET or RESET).
lypinator	0:bb348c97df44	1079	*/
lypinator	0:bb348c97df44	1080	#define __FMC_SDRAM_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SDSR &(__FLAG__)) == (__FLAG__))
lypinator	0:bb348c97df44	1081
lypinator	0:bb348c97df44	1082	/**
lypinator	0:bb348c97df44	1083	* @brief Clear flag status of the SDRAM device.
lypinator	0:bb348c97df44	1084	* @param __INSTANCE__ FMC_SDRAM instance
lypinator	0:bb348c97df44	1085	* @param __FLAG__ FMC_SDRAM flag
lypinator	0:bb348c97df44	1086	* This parameter can be any combination of the following values:
lypinator	0:bb348c97df44	1087	* @arg FMC_SDRAM_FLAG_REFRESH_ERROR
lypinator	0:bb348c97df44	1088	* @retval None
lypinator	0:bb348c97df44	1089	*/
lypinator	0:bb348c97df44	1090	#define __FMC_SDRAM_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SDRTR \|= (__FLAG__))
lypinator	0:bb348c97df44	1091	/**
lypinator	0:bb348c97df44	1092	* @}
lypinator	0:bb348c97df44	1093	*/
lypinator	0:bb348c97df44	1094
lypinator	0:bb348c97df44	1095	/** @defgroup FSMC_LL_Assert_Macros FSMC Assert Macros
lypinator	0:bb348c97df44	1096	* @{
lypinator	0:bb348c97df44	1097	*/
lypinator	0:bb348c97df44	1098	#define IS_FMC_NORSRAM_BANK(BANK) (((BANK) == FMC_NORSRAM_BANK1) \|\| \
lypinator	0:bb348c97df44	1099	((BANK) == FMC_NORSRAM_BANK2) \|\| \
lypinator	0:bb348c97df44	1100	((BANK) == FMC_NORSRAM_BANK3) \|\| \
lypinator	0:bb348c97df44	1101	((BANK) == FMC_NORSRAM_BANK4))
lypinator	0:bb348c97df44	1102
lypinator	0:bb348c97df44	1103	#define IS_FMC_MUX(__MUX__) (((__MUX__) == FMC_DATA_ADDRESS_MUX_DISABLE) \|\| \
lypinator	0:bb348c97df44	1104	((__MUX__) == FMC_DATA_ADDRESS_MUX_ENABLE))
lypinator	0:bb348c97df44	1105
lypinator	0:bb348c97df44	1106	#define IS_FMC_MEMORY(__MEMORY__) (((__MEMORY__) == FMC_MEMORY_TYPE_SRAM) \|\| \
lypinator	0:bb348c97df44	1107	((__MEMORY__) == FMC_MEMORY_TYPE_PSRAM)\|\| \
lypinator	0:bb348c97df44	1108	((__MEMORY__) == FMC_MEMORY_TYPE_NOR))
lypinator	0:bb348c97df44	1109
lypinator	0:bb348c97df44	1110	#define IS_FMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_8) \|\| \
lypinator	0:bb348c97df44	1111	((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_16) \|\| \
lypinator	0:bb348c97df44	1112	((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_32))
lypinator	0:bb348c97df44	1113
lypinator	0:bb348c97df44	1114	#define IS_FMC_ACCESS_MODE(__MODE__) (((__MODE__) == FMC_ACCESS_MODE_A) \|\| \
lypinator	0:bb348c97df44	1115	((__MODE__) == FMC_ACCESS_MODE_B) \|\| \
lypinator	0:bb348c97df44	1116	((__MODE__) == FMC_ACCESS_MODE_C) \|\| \
lypinator	0:bb348c97df44	1117	((__MODE__) == FMC_ACCESS_MODE_D))
lypinator	0:bb348c97df44	1118
lypinator	0:bb348c97df44	1119	#define IS_FMC_NAND_BANK(BANK) (((BANK) == FMC_NAND_BANK2) \|\| \
lypinator	0:bb348c97df44	1120	((BANK) == FMC_NAND_BANK3))
lypinator	0:bb348c97df44	1121
lypinator	0:bb348c97df44	1122	#define IS_FMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FMC_NAND_PCC_WAIT_FEATURE_DISABLE) \|\| \
lypinator	0:bb348c97df44	1123	((FEATURE) == FMC_NAND_PCC_WAIT_FEATURE_ENABLE))
lypinator	0:bb348c97df44	1124
lypinator	0:bb348c97df44	1125	#define IS_FMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NAND_PCC_MEM_BUS_WIDTH_8) \|\| \
lypinator	0:bb348c97df44	1126	((WIDTH) == FMC_NAND_PCC_MEM_BUS_WIDTH_16))
lypinator	0:bb348c97df44	1127
lypinator	0:bb348c97df44	1128	#define IS_FMC_ECC_STATE(STATE) (((STATE) == FMC_NAND_ECC_DISABLE) \|\| \
lypinator	0:bb348c97df44	1129	((STATE) == FMC_NAND_ECC_ENABLE))
lypinator	0:bb348c97df44	1130
lypinator	0:bb348c97df44	1131	#define IS_FMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FMC_NAND_ECC_PAGE_SIZE_256BYTE) \|\| \
lypinator	0:bb348c97df44	1132	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) \|\| \
lypinator	0:bb348c97df44	1133	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) \|\| \
lypinator	0:bb348c97df44	1134	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) \|\| \
lypinator	0:bb348c97df44	1135	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) \|\| \
lypinator	0:bb348c97df44	1136	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE))
lypinator	0:bb348c97df44	1137
lypinator	0:bb348c97df44	1138	#define IS_FMC_TCLR_TIME(TIME) ((TIME) <= 255U)
lypinator	0:bb348c97df44	1139
lypinator	0:bb348c97df44	1140	#define IS_FMC_TAR_TIME(TIME) ((TIME) <= 255U)
lypinator	0:bb348c97df44	1141
lypinator	0:bb348c97df44	1142	#define IS_FMC_SETUP_TIME(TIME) ((TIME) <= 255U)
lypinator	0:bb348c97df44	1143
lypinator	0:bb348c97df44	1144	#define IS_FMC_WAIT_TIME(TIME) ((TIME) <= 255U)
lypinator	0:bb348c97df44	1145
lypinator	0:bb348c97df44	1146	#define IS_FMC_HOLD_TIME(TIME) ((TIME) <= 255U)
lypinator	0:bb348c97df44	1147
lypinator	0:bb348c97df44	1148	#define IS_FMC_HIZ_TIME(TIME) ((TIME) <= 255U)
lypinator	0:bb348c97df44	1149
lypinator	0:bb348c97df44	1150	#define IS_FMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_DEVICE)
lypinator	0:bb348c97df44	1151
lypinator	0:bb348c97df44	1152	#define IS_FMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_EXTENDED_DEVICE)
lypinator	0:bb348c97df44	1153
lypinator	0:bb348c97df44	1154	#define IS_FMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NAND_DEVICE)
lypinator	0:bb348c97df44	1155
lypinator	0:bb348c97df44	1156	#define IS_FMC_PCCARD_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_PCCARD_DEVICE)
lypinator	0:bb348c97df44	1157
lypinator	0:bb348c97df44	1158	#define IS_FMC_BURSTMODE(__STATE__) (((__STATE__) == FMC_BURST_ACCESS_MODE_DISABLE) \|\| \
lypinator	0:bb348c97df44	1159	((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE))
lypinator	0:bb348c97df44	1160
lypinator	0:bb348c97df44	1161	#define IS_FMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) \|\| \
lypinator	0:bb348c97df44	1162	((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH))
lypinator	0:bb348c97df44	1163
lypinator	0:bb348c97df44	1164	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
lypinator	0:bb348c97df44	1165	#define IS_FMC_WRAP_MODE(__MODE__) (((__MODE__) == FMC_WRAP_MODE_DISABLE) \|\| \
lypinator	0:bb348c97df44	1166	((__MODE__) == FMC_WRAP_MODE_ENABLE))
lypinator	0:bb348c97df44	1167	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
lypinator	0:bb348c97df44	1168
lypinator	0:bb348c97df44	1169	#define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) \|\| \
lypinator	0:bb348c97df44	1170	((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS))
lypinator	0:bb348c97df44	1171
lypinator	0:bb348c97df44	1172	#define IS_FMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FMC_WRITE_OPERATION_DISABLE) \|\| \
lypinator	0:bb348c97df44	1173	((__OPERATION__) == FMC_WRITE_OPERATION_ENABLE))
lypinator	0:bb348c97df44	1174
lypinator	0:bb348c97df44	1175	#define IS_FMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FMC_WAIT_SIGNAL_DISABLE) \|\| \
lypinator	0:bb348c97df44	1176	((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE))
lypinator	0:bb348c97df44	1177
lypinator	0:bb348c97df44	1178	#define IS_FMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FMC_EXTENDED_MODE_DISABLE) \|\| \
lypinator	0:bb348c97df44	1179	((__MODE__) == FMC_EXTENDED_MODE_ENABLE))
lypinator	0:bb348c97df44	1180
lypinator	0:bb348c97df44	1181	#define IS_FMC_ASYNWAIT(__STATE__) (((__STATE__) == FMC_ASYNCHRONOUS_WAIT_DISABLE) \|\| \
lypinator	0:bb348c97df44	1182	((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE))
lypinator	0:bb348c97df44	1183
lypinator	0:bb348c97df44	1184	#define IS_FMC_WRITE_BURST(__BURST__) (((__BURST__) == FMC_WRITE_BURST_DISABLE) \|\| \
lypinator	0:bb348c97df44	1185	((__BURST__) == FMC_WRITE_BURST_ENABLE))
lypinator	0:bb348c97df44	1186
lypinator	0:bb348c97df44	1187	#define IS_FMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) \|\| \
lypinator	0:bb348c97df44	1188	((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
lypinator	0:bb348c97df44	1189
lypinator	0:bb348c97df44	1190	#define IS_FMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15U)
lypinator	0:bb348c97df44	1191
lypinator	0:bb348c97df44	1192	#define IS_FMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 15U))
lypinator	0:bb348c97df44	1193
lypinator	0:bb348c97df44	1194	#define IS_FMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 255U))
lypinator	0:bb348c97df44	1195
lypinator	0:bb348c97df44	1196	#define IS_FMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15U)
lypinator	0:bb348c97df44	1197
lypinator	0:bb348c97df44	1198	#define IS_FMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U))
lypinator	0:bb348c97df44	1199
lypinator	0:bb348c97df44	1200	#define IS_FMC_CLK_DIV(DIV) (((DIV) > 1U) && ((DIV) <= 16U))
lypinator	0:bb348c97df44	1201
lypinator	0:bb348c97df44	1202	#define IS_FMC_SDRAM_BANK(BANK) (((BANK) == FMC_SDRAM_BANK1) \|\| \
lypinator	0:bb348c97df44	1203	((BANK) == FMC_SDRAM_BANK2))
lypinator	0:bb348c97df44	1204
lypinator	0:bb348c97df44	1205	#define IS_FMC_COLUMNBITS_NUMBER(COLUMN) (((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_8) \|\| \
lypinator	0:bb348c97df44	1206	((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_9) \|\| \
lypinator	0:bb348c97df44	1207	((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_10) \|\| \
lypinator	0:bb348c97df44	1208	((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_11))
lypinator	0:bb348c97df44	1209
lypinator	0:bb348c97df44	1210	#define IS_FMC_ROWBITS_NUMBER(ROW) (((ROW) == FMC_SDRAM_ROW_BITS_NUM_11) \|\| \
lypinator	0:bb348c97df44	1211	((ROW) == FMC_SDRAM_ROW_BITS_NUM_12) \|\| \
lypinator	0:bb348c97df44	1212	((ROW) == FMC_SDRAM_ROW_BITS_NUM_13))
lypinator	0:bb348c97df44	1213
lypinator	0:bb348c97df44	1214	#define IS_FMC_SDMEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_8) \|\| \
lypinator	0:bb348c97df44	1215	((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_16) \|\| \
lypinator	0:bb348c97df44	1216	((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_32))
lypinator	0:bb348c97df44	1217
lypinator	0:bb348c97df44	1218	#define IS_FMC_INTERNALBANK_NUMBER(NUMBER) (((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_2) \|\| \
lypinator	0:bb348c97df44	1219	((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_4))
lypinator	0:bb348c97df44	1220
lypinator	0:bb348c97df44	1221
lypinator	0:bb348c97df44	1222	#define IS_FMC_CAS_LATENCY(LATENCY) (((LATENCY) == FMC_SDRAM_CAS_LATENCY_1) \|\| \
lypinator	0:bb348c97df44	1223	((LATENCY) == FMC_SDRAM_CAS_LATENCY_2) \|\| \
lypinator	0:bb348c97df44	1224	((LATENCY) == FMC_SDRAM_CAS_LATENCY_3))
lypinator	0:bb348c97df44	1225
lypinator	0:bb348c97df44	1226	#define IS_FMC_SDCLOCK_PERIOD(PERIOD) (((PERIOD) == FMC_SDRAM_CLOCK_DISABLE) \|\| \
lypinator	0:bb348c97df44	1227	((PERIOD) == FMC_SDRAM_CLOCK_PERIOD_2) \|\| \
lypinator	0:bb348c97df44	1228	((PERIOD) == FMC_SDRAM_CLOCK_PERIOD_3))
lypinator	0:bb348c97df44	1229
lypinator	0:bb348c97df44	1230	#define IS_FMC_READ_BURST(RBURST) (((RBURST) == FMC_SDRAM_RBURST_DISABLE) \|\| \
lypinator	0:bb348c97df44	1231	((RBURST) == FMC_SDRAM_RBURST_ENABLE))
lypinator	0:bb348c97df44	1232
lypinator	0:bb348c97df44	1233
lypinator	0:bb348c97df44	1234	#define IS_FMC_READPIPE_DELAY(DELAY) (((DELAY) == FMC_SDRAM_RPIPE_DELAY_0) \|\| \
lypinator	0:bb348c97df44	1235	((DELAY) == FMC_SDRAM_RPIPE_DELAY_1) \|\| \
lypinator	0:bb348c97df44	1236	((DELAY) == FMC_SDRAM_RPIPE_DELAY_2))
lypinator	0:bb348c97df44	1237
lypinator	0:bb348c97df44	1238	#define IS_FMC_LOADTOACTIVE_DELAY(DELAY) (((DELAY) > 0U) && ((DELAY) <= 16U))
lypinator	0:bb348c97df44	1239
lypinator	0:bb348c97df44	1240	#define IS_FMC_EXITSELFREFRESH_DELAY(DELAY) (((DELAY) > 0U) && ((DELAY) <= 16U))
lypinator	0:bb348c97df44	1241
lypinator	0:bb348c97df44	1242	#define IS_FMC_SELFREFRESH_TIME(TIME) (((TIME) > 0U) && ((TIME) <= 16U))
lypinator	0:bb348c97df44	1243
lypinator	0:bb348c97df44	1244	#define IS_FMC_ROWCYCLE_DELAY(DELAY) (((DELAY) > 0U) && ((DELAY) <= 16U))
lypinator	0:bb348c97df44	1245
lypinator	0:bb348c97df44	1246	#define IS_FMC_WRITE_RECOVERY_TIME(TIME) (((TIME) > 0U) && ((TIME) <= 16U))
lypinator	0:bb348c97df44	1247
lypinator	0:bb348c97df44	1248	#define IS_FMC_RP_DELAY(DELAY) (((DELAY) > 0U) && ((DELAY) <= 16U))
lypinator	0:bb348c97df44	1249
lypinator	0:bb348c97df44	1250	#define IS_FMC_RCD_DELAY(DELAY) (((DELAY) > 0U) && ((DELAY) <= 16U))
lypinator	0:bb348c97df44	1251
lypinator	0:bb348c97df44	1252	#define IS_FMC_COMMAND_MODE(COMMAND) (((COMMAND) == FMC_SDRAM_CMD_NORMAL_MODE) \|\| \
lypinator	0:bb348c97df44	1253	((COMMAND) == FMC_SDRAM_CMD_CLK_ENABLE) \|\| \
lypinator	0:bb348c97df44	1254	((COMMAND) == FMC_SDRAM_CMD_PALL) \|\| \
lypinator	0:bb348c97df44	1255	((COMMAND) == FMC_SDRAM_CMD_AUTOREFRESH_MODE) \|\| \
lypinator	0:bb348c97df44	1256	((COMMAND) == FMC_SDRAM_CMD_LOAD_MODE) \|\| \
lypinator	0:bb348c97df44	1257	((COMMAND) == FMC_SDRAM_CMD_SELFREFRESH_MODE) \|\| \
lypinator	0:bb348c97df44	1258	((COMMAND) == FMC_SDRAM_CMD_POWERDOWN_MODE))
lypinator	0:bb348c97df44	1259
lypinator	0:bb348c97df44	1260	#define IS_FMC_COMMAND_TARGET(TARGET) (((TARGET) == FMC_SDRAM_CMD_TARGET_BANK1) \|\| \
lypinator	0:bb348c97df44	1261	((TARGET) == FMC_SDRAM_CMD_TARGET_BANK2) \|\| \
lypinator	0:bb348c97df44	1262	((TARGET) == FMC_SDRAM_CMD_TARGET_BANK1_2))
lypinator	0:bb348c97df44	1263
lypinator	0:bb348c97df44	1264	#define IS_FMC_AUTOREFRESH_NUMBER(NUMBER) (((NUMBER) > 0U) && ((NUMBER) <= 16U))
lypinator	0:bb348c97df44	1265
lypinator	0:bb348c97df44	1266	#define IS_FMC_MODE_REGISTER(CONTENT) ((CONTENT) <= 8191U)
lypinator	0:bb348c97df44	1267
lypinator	0:bb348c97df44	1268	#define IS_FMC_REFRESH_RATE(RATE) ((RATE) <= 8191U)
lypinator	0:bb348c97df44	1269
lypinator	0:bb348c97df44	1270	#define IS_FMC_SDRAM_DEVICE(INSTANCE) ((INSTANCE) == FMC_SDRAM_DEVICE)
lypinator	0:bb348c97df44	1271
lypinator	0:bb348c97df44	1272	#define IS_FMC_WRITE_PROTECTION(WRITE) (((WRITE) == FMC_SDRAM_WRITE_PROTECTION_DISABLE) \|\| \
lypinator	0:bb348c97df44	1273	((WRITE) == FMC_SDRAM_WRITE_PROTECTION_ENABLE))
lypinator	0:bb348c97df44	1274
lypinator	0:bb348c97df44	1275	#define IS_FMC_PAGESIZE(SIZE) (((SIZE) == FMC_PAGE_SIZE_NONE) \|\| \
lypinator	0:bb348c97df44	1276	((SIZE) == FMC_PAGE_SIZE_128) \|\| \
lypinator	0:bb348c97df44	1277	((SIZE) == FMC_PAGE_SIZE_256) \|\| \
lypinator	0:bb348c97df44	1278	((SIZE) == FMC_PAGE_SIZE_512) \|\| \
lypinator	0:bb348c97df44	1279	((SIZE) == FMC_PAGE_SIZE_1024))
lypinator	0:bb348c97df44	1280
lypinator	0:bb348c97df44	1281	#if defined (STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
lypinator	0:bb348c97df44	1282	#define IS_FMC_WRITE_FIFO(FIFO) (((FIFO) == FMC_WRITE_FIFO_DISABLE) \|\| \
lypinator	0:bb348c97df44	1283	((FIFO) == FMC_WRITE_FIFO_ENABLE))
lypinator	0:bb348c97df44	1284	#endif /* STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
lypinator	0:bb348c97df44	1285
lypinator	0:bb348c97df44	1286	/**
lypinator	0:bb348c97df44	1287	* @}
lypinator	0:bb348c97df44	1288	*/
lypinator	0:bb348c97df44	1289
lypinator	0:bb348c97df44	1290	/**
lypinator	0:bb348c97df44	1291	* @}
lypinator	0:bb348c97df44	1292	*/
lypinator	0:bb348c97df44	1293
lypinator	0:bb348c97df44	1294	/* Private functions ---------------------------------------------------------*/
lypinator	0:bb348c97df44	1295	/** @defgroup FMC_LL_Private_Functions FMC LL Private Functions
lypinator	0:bb348c97df44	1296	* @{
lypinator	0:bb348c97df44	1297	*/
lypinator	0:bb348c97df44	1298
lypinator	0:bb348c97df44	1299	/** @defgroup FMC_LL_NORSRAM NOR SRAM
lypinator	0:bb348c97df44	1300	* @{
lypinator	0:bb348c97df44	1301	*/
lypinator	0:bb348c97df44	1302	/** @defgroup FMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions
lypinator	0:bb348c97df44	1303	* @{
lypinator	0:bb348c97df44	1304	*/
lypinator	0:bb348c97df44	1305	HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef Device, FMC_NORSRAM_InitTypeDef Init);
lypinator	0:bb348c97df44	1306	HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef Device, FMC_NORSRAM_TimingTypeDef Timing, uint32_t Bank);
lypinator	0:bb348c97df44	1307	HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef Device, FMC_NORSRAM_TimingTypeDef Timing, uint32_t Bank, uint32_t ExtendedMode);
lypinator	0:bb348c97df44	1308	HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef Device, FMC_NORSRAM_EXTENDED_TypeDef ExDevice, uint32_t Bank);
lypinator	0:bb348c97df44	1309	/**
lypinator	0:bb348c97df44	1310	* @}
lypinator	0:bb348c97df44	1311	*/
lypinator	0:bb348c97df44	1312
lypinator	0:bb348c97df44	1313	/** @defgroup FMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions
lypinator	0:bb348c97df44	1314	* @{
lypinator	0:bb348c97df44	1315	*/
lypinator	0:bb348c97df44	1316	HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
lypinator	0:bb348c97df44	1317	HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
lypinator	0:bb348c97df44	1318	/**
lypinator	0:bb348c97df44	1319	* @}
lypinator	0:bb348c97df44	1320	*/
lypinator	0:bb348c97df44	1321	/**
lypinator	0:bb348c97df44	1322	* @}
lypinator	0:bb348c97df44	1323	*/
lypinator	0:bb348c97df44	1324
lypinator	0:bb348c97df44	1325	/** @defgroup FMC_LL_NAND NAND
lypinator	0:bb348c97df44	1326	* @{
lypinator	0:bb348c97df44	1327	*/
lypinator	0:bb348c97df44	1328	/** @defgroup FMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions
lypinator	0:bb348c97df44	1329	* @{
lypinator	0:bb348c97df44	1330	*/
lypinator	0:bb348c97df44	1331	HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef Device, FMC_NAND_InitTypeDef Init);
lypinator	0:bb348c97df44	1332	HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing, uint32_t Bank);
lypinator	0:bb348c97df44	1333	HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing, uint32_t Bank);
lypinator	0:bb348c97df44	1334	HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank);
lypinator	0:bb348c97df44	1335	/**
lypinator	0:bb348c97df44	1336	* @}
lypinator	0:bb348c97df44	1337	*/
lypinator	0:bb348c97df44	1338
lypinator	0:bb348c97df44	1339	/** @defgroup FMC_LL_NAND_Private_Functions_Group2 NAND Control functions
lypinator	0:bb348c97df44	1340	* @{
lypinator	0:bb348c97df44	1341	*/
lypinator	0:bb348c97df44	1342	HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank);
lypinator	0:bb348c97df44	1343	HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank);
lypinator	0:bb348c97df44	1344	HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef Device, uint32_t ECCval, uint32_t Bank, uint32_t Timeout);
lypinator	0:bb348c97df44	1345
lypinator	0:bb348c97df44	1346	/**
lypinator	0:bb348c97df44	1347	* @}
lypinator	0:bb348c97df44	1348	*/
lypinator	0:bb348c97df44	1349	/**
lypinator	0:bb348c97df44	1350	* @}
lypinator	0:bb348c97df44	1351	*/
lypinator	0:bb348c97df44	1352	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
lypinator	0:bb348c97df44	1353	/** @defgroup FMC_LL_PCCARD PCCARD
lypinator	0:bb348c97df44	1354	* @{
lypinator	0:bb348c97df44	1355	*/
lypinator	0:bb348c97df44	1356	/** @defgroup FMC_LL_PCCARD_Private_Functions_Group1 PCCARD Initialization/de-initialization functions
lypinator	0:bb348c97df44	1357	* @{
lypinator	0:bb348c97df44	1358	*/
lypinator	0:bb348c97df44	1359	HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef Device, FMC_PCCARD_InitTypeDef Init);
lypinator	0:bb348c97df44	1360	HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing);
lypinator	0:bb348c97df44	1361	HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing);
lypinator	0:bb348c97df44	1362	HAL_StatusTypeDef FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing);
lypinator	0:bb348c97df44	1363	HAL_StatusTypeDef FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device);
lypinator	0:bb348c97df44	1364	/**
lypinator	0:bb348c97df44	1365	* @}
lypinator	0:bb348c97df44	1366	*/
lypinator	0:bb348c97df44	1367	/**
lypinator	0:bb348c97df44	1368	* @}
lypinator	0:bb348c97df44	1369	*/
lypinator	0:bb348c97df44	1370	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
lypinator	0:bb348c97df44	1371
lypinator	0:bb348c97df44	1372	/** @defgroup FMC_LL_SDRAM SDRAM
lypinator	0:bb348c97df44	1373	* @{
lypinator	0:bb348c97df44	1374	*/
lypinator	0:bb348c97df44	1375	/** @defgroup FMC_LL_SDRAM_Private_Functions_Group1 SDRAM Initialization/de-initialization functions
lypinator	0:bb348c97df44	1376	* @{
lypinator	0:bb348c97df44	1377	*/
lypinator	0:bb348c97df44	1378	HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef Device, FMC_SDRAM_InitTypeDef Init);
lypinator	0:bb348c97df44	1379	HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef Device, FMC_SDRAM_TimingTypeDef Timing, uint32_t Bank);
lypinator	0:bb348c97df44	1380	HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
lypinator	0:bb348c97df44	1381	/**
lypinator	0:bb348c97df44	1382	* @}
lypinator	0:bb348c97df44	1383	*/
lypinator	0:bb348c97df44	1384
lypinator	0:bb348c97df44	1385	/** @defgroup FMC_LL_SDRAM_Private_Functions_Group2 SDRAM Control functions
lypinator	0:bb348c97df44	1386	* @{
lypinator	0:bb348c97df44	1387	*/
lypinator	0:bb348c97df44	1388	HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
lypinator	0:bb348c97df44	1389	HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
lypinator	0:bb348c97df44	1390	HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef Device, FMC_SDRAM_CommandTypeDef Command, uint32_t Timeout);
lypinator	0:bb348c97df44	1391	HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate);
lypinator	0:bb348c97df44	1392	HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber);
lypinator	0:bb348c97df44	1393	uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
lypinator	0:bb348c97df44	1394	/**
lypinator	0:bb348c97df44	1395	* @}
lypinator	0:bb348c97df44	1396	*/
lypinator	0:bb348c97df44	1397	/**
lypinator	0:bb348c97df44	1398	* @}
lypinator	0:bb348c97df44	1399	*/
lypinator	0:bb348c97df44	1400
lypinator	0:bb348c97df44	1401	/**
lypinator	0:bb348c97df44	1402	* @}
lypinator	0:bb348c97df44	1403	*/
lypinator	0:bb348c97df44	1404
lypinator	0:bb348c97df44	1405	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
lypinator	0:bb348c97df44	1406	/**
lypinator	0:bb348c97df44	1407	* @}
lypinator	0:bb348c97df44	1408	*/
lypinator	0:bb348c97df44	1409
lypinator	0:bb348c97df44	1410	/**
lypinator	0:bb348c97df44	1411	* @}
lypinator	0:bb348c97df44	1412	*/
lypinator	0:bb348c97df44	1413	#ifdef __cplusplus
lypinator	0:bb348c97df44	1414	}
lypinator	0:bb348c97df44	1415	#endif
lypinator	0:bb348c97df44	1416
lypinator	0:bb348c97df44	1417	#endif /* __STM32F4xx_LL_FMC_H */
lypinator	0:bb348c97df44	1418
lypinator	0:bb348c97df44	1419	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Program
Created:	16 Sep 2020
Imports:	1
Forks:	0
Commits:	1
Dependents:	0
Dependencies:	1
Followers:	1

mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_fmc.h@0:bb348c97df44, 2020-09-16 (annotated)

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