DevLibMemoryController - Initial commit

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Initial commit

mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_fmc.c@0:bb348c97df44, 2020-09-16 (annotated)

Committer:: lypinator
Date:: Wed Sep 16 01:11:49 2020 +0000
Revision:: 0:bb348c97df44

Added PWM

Who changed what in which revision?

User	Revision	Line number	New contents of line
lypinator	0:bb348c97df44	1	/**
lypinator	0:bb348c97df44	2	******************************************************************************
lypinator	0:bb348c97df44	3	* @file stm32f4xx_ll_fmc.c
lypinator	0:bb348c97df44	4	* @author MCD Application Team
lypinator	0:bb348c97df44	5	* @brief FMC Low Layer HAL module driver.
lypinator	0:bb348c97df44	6	*
lypinator	0:bb348c97df44	7	* This file provides firmware functions to manage the following
lypinator	0:bb348c97df44	8	* functionalities of the Flexible Memory Controller (FMC) peripheral memories:
lypinator	0:bb348c97df44	9	* + Initialization/de-initialization functions
lypinator	0:bb348c97df44	10	* + Peripheral Control functions
lypinator	0:bb348c97df44	11	* + Peripheral State functions
lypinator	0:bb348c97df44	12	*
lypinator	0:bb348c97df44	13	@verbatim
lypinator	0:bb348c97df44	14	==============================================================================
lypinator	0:bb348c97df44	15	##### FMC peripheral features #####
lypinator	0:bb348c97df44	16	==============================================================================
lypinator	0:bb348c97df44	17	[..] The Flexible memory controller (FMC) includes three memory controllers:
lypinator	0:bb348c97df44	18	(+) The NOR/PSRAM memory controller
lypinator	0:bb348c97df44	19	(+) The NAND/PC Card memory controller
lypinator	0:bb348c97df44	20	(+) The Synchronous DRAM (SDRAM) controller
lypinator	0:bb348c97df44	21
lypinator	0:bb348c97df44	22	[..] The FMC functional block makes the interface with synchronous and asynchronous static
lypinator	0:bb348c97df44	23	memories, SDRAM memories, and 16-bit PC memory cards. Its main purposes are:
lypinator	0:bb348c97df44	24	(+) to translate AHB transactions into the appropriate external device protocol
lypinator	0:bb348c97df44	25	(+) to meet the access time requirements of the external memory devices
lypinator	0:bb348c97df44	26
lypinator	0:bb348c97df44	27	[..] All external memories share the addresses, data and control signals with the controller.
lypinator	0:bb348c97df44	28	Each external device is accessed by means of a unique Chip Select. The FMC performs
lypinator	0:bb348c97df44	29	only one access at a time to an external device.
lypinator	0:bb348c97df44	30	The main features of the FMC controller are the following:
lypinator	0:bb348c97df44	31	(+) Interface with static-memory mapped devices including:
lypinator	0:bb348c97df44	32	(++) Static random access memory (SRAM)
lypinator	0:bb348c97df44	33	(++) Read-only memory (ROM)
lypinator	0:bb348c97df44	34	(++) NOR Flash memory/OneNAND Flash memory
lypinator	0:bb348c97df44	35	(++) PSRAM (4 memory banks)
lypinator	0:bb348c97df44	36	(++) 16-bit PC Card compatible devices
lypinator	0:bb348c97df44	37	(++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of
lypinator	0:bb348c97df44	38	data
lypinator	0:bb348c97df44	39	(+) Interface with synchronous DRAM (SDRAM) memories
lypinator	0:bb348c97df44	40	(+) Independent Chip Select control for each memory bank
lypinator	0:bb348c97df44	41	(+) Independent configuration for each memory bank
lypinator	0:bb348c97df44	42
lypinator	0:bb348c97df44	43	@endverbatim
lypinator	0:bb348c97df44	44	******************************************************************************
lypinator	0:bb348c97df44	45	* @attention
lypinator	0:bb348c97df44	46	*
lypinator	0:bb348c97df44	47	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
lypinator	0:bb348c97df44	48	*
lypinator	0:bb348c97df44	49	* Redistribution and use in source and binary forms, with or without modification,
lypinator	0:bb348c97df44	50	* are permitted provided that the following conditions are met:
lypinator	0:bb348c97df44	51	* 1. Redistributions of source code must retain the above copyright notice,
lypinator	0:bb348c97df44	52	* this list of conditions and the following disclaimer.
lypinator	0:bb348c97df44	53	* 2. Redistributions in binary form must reproduce the above copyright notice,
lypinator	0:bb348c97df44	54	* this list of conditions and the following disclaimer in the documentation
lypinator	0:bb348c97df44	55	* and/or other materials provided with the distribution.
lypinator	0:bb348c97df44	56	* 3. Neither the name of STMicroelectronics nor the names of its contributors
lypinator	0:bb348c97df44	57	* may be used to endorse or promote products derived from this software
lypinator	0:bb348c97df44	58	* without specific prior written permission.
lypinator	0:bb348c97df44	59	*
lypinator	0:bb348c97df44	60	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
lypinator	0:bb348c97df44	61	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
lypinator	0:bb348c97df44	62	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
lypinator	0:bb348c97df44	63	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
lypinator	0:bb348c97df44	64	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
lypinator	0:bb348c97df44	65	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
lypinator	0:bb348c97df44	66	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
lypinator	0:bb348c97df44	67	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
lypinator	0:bb348c97df44	68	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
lypinator	0:bb348c97df44	69	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
lypinator	0:bb348c97df44	70	*
lypinator	0:bb348c97df44	71	******************************************************************************
lypinator	0:bb348c97df44	72	*/
lypinator	0:bb348c97df44	73
lypinator	0:bb348c97df44	74	/* Includes ------------------------------------------------------------------*/
lypinator	0:bb348c97df44	75	#include "stm32f4xx_hal.h"
lypinator	0:bb348c97df44	76
lypinator	0:bb348c97df44	77	/** @addtogroup STM32F4xx_HAL_Driver
lypinator	0:bb348c97df44	78	* @{
lypinator	0:bb348c97df44	79	*/
lypinator	0:bb348c97df44	80
lypinator	0:bb348c97df44	81	/** @defgroup FMC_LL FMC Low Layer
lypinator	0:bb348c97df44	82	* @brief FMC driver modules
lypinator	0:bb348c97df44	83	* @{
lypinator	0:bb348c97df44	84	*/
lypinator	0:bb348c97df44	85
lypinator	0:bb348c97df44	86	#if defined (HAL_SRAM_MODULE_ENABLED) \|\| defined(HAL_NOR_MODULE_ENABLED) \|\| defined(HAL_NAND_MODULE_ENABLED) \|\| defined(HAL_PCCARD_MODULE_ENABLED) \|\| defined(HAL_SDRAM_MODULE_ENABLED)
lypinator	0:bb348c97df44	87
lypinator	0:bb348c97df44	88	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
lypinator	0:bb348c97df44	89
lypinator	0:bb348c97df44	90	/* Private typedef -----------------------------------------------------------*/
lypinator	0:bb348c97df44	91	/* Private define ------------------------------------------------------------*/
lypinator	0:bb348c97df44	92	/* Private macro -------------------------------------------------------------*/
lypinator	0:bb348c97df44	93	/* Private variables ---------------------------------------------------------*/
lypinator	0:bb348c97df44	94	/* Private function prototypes -----------------------------------------------*/
lypinator	0:bb348c97df44	95	/* Private functions ---------------------------------------------------------*/
lypinator	0:bb348c97df44	96	/** @addtogroup FMC_LL_Private_Functions
lypinator	0:bb348c97df44	97	* @{
lypinator	0:bb348c97df44	98	*/
lypinator	0:bb348c97df44	99
lypinator	0:bb348c97df44	100	/** @addtogroup FMC_LL_NORSRAM
lypinator	0:bb348c97df44	101	* @brief NORSRAM Controller functions
lypinator	0:bb348c97df44	102	*
lypinator	0:bb348c97df44	103	@verbatim
lypinator	0:bb348c97df44	104	==============================================================================
lypinator	0:bb348c97df44	105	##### How to use NORSRAM device driver #####
lypinator	0:bb348c97df44	106	==============================================================================
lypinator	0:bb348c97df44	107
lypinator	0:bb348c97df44	108	[..]
lypinator	0:bb348c97df44	109	This driver contains a set of APIs to interface with the FMC NORSRAM banks in order
lypinator	0:bb348c97df44	110	to run the NORSRAM external devices.
lypinator	0:bb348c97df44	111
lypinator	0:bb348c97df44	112	(+) FMC NORSRAM bank reset using the function FMC_NORSRAM_DeInit()
lypinator	0:bb348c97df44	113	(+) FMC NORSRAM bank control configuration using the function FMC_NORSRAM_Init()
lypinator	0:bb348c97df44	114	(+) FMC NORSRAM bank timing configuration using the function FMC_NORSRAM_Timing_Init()
lypinator	0:bb348c97df44	115	(+) FMC NORSRAM bank extended timing configuration using the function
lypinator	0:bb348c97df44	116	FMC_NORSRAM_Extended_Timing_Init()
lypinator	0:bb348c97df44	117	(+) FMC NORSRAM bank enable/disable write operation using the functions
lypinator	0:bb348c97df44	118	FMC_NORSRAM_WriteOperation_Enable()/FMC_NORSRAM_WriteOperation_Disable()
lypinator	0:bb348c97df44	119
lypinator	0:bb348c97df44	120
lypinator	0:bb348c97df44	121	@endverbatim
lypinator	0:bb348c97df44	122	* @{
lypinator	0:bb348c97df44	123	*/
lypinator	0:bb348c97df44	124
lypinator	0:bb348c97df44	125	/** @addtogroup FMC_LL_NORSRAM_Private_Functions_Group1
lypinator	0:bb348c97df44	126	* @brief Initialization and Configuration functions
lypinator	0:bb348c97df44	127	*
lypinator	0:bb348c97df44	128	@verbatim
lypinator	0:bb348c97df44	129	==============================================================================
lypinator	0:bb348c97df44	130	##### Initialization and de_initialization functions #####
lypinator	0:bb348c97df44	131	==============================================================================
lypinator	0:bb348c97df44	132	[..]
lypinator	0:bb348c97df44	133	This section provides functions allowing to:
lypinator	0:bb348c97df44	134	(+) Initialize and configure the FMC NORSRAM interface
lypinator	0:bb348c97df44	135	(+) De-initialize the FMC NORSRAM interface
lypinator	0:bb348c97df44	136	(+) Configure the FMC clock and associated GPIOs
lypinator	0:bb348c97df44	137
lypinator	0:bb348c97df44	138	@endverbatim
lypinator	0:bb348c97df44	139	* @{
lypinator	0:bb348c97df44	140	*/
lypinator	0:bb348c97df44	141
lypinator	0:bb348c97df44	142	/**
lypinator	0:bb348c97df44	143	* @brief Initialize the FMC_NORSRAM device according to the specified
lypinator	0:bb348c97df44	144	* control parameters in the FMC_NORSRAM_InitTypeDef
lypinator	0:bb348c97df44	145	* @param Device Pointer to NORSRAM device instance
lypinator	0:bb348c97df44	146	* @param Init Pointer to NORSRAM Initialization structure
lypinator	0:bb348c97df44	147	* @retval HAL status
lypinator	0:bb348c97df44	148	*/
lypinator	0:bb348c97df44	149	HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef Device, FMC_NORSRAM_InitTypeDef Init)
lypinator	0:bb348c97df44	150	{
lypinator	0:bb348c97df44	151	uint32_t tmpr = 0U;
lypinator	0:bb348c97df44	152
lypinator	0:bb348c97df44	153	/* Check the parameters */
lypinator	0:bb348c97df44	154	assert_param(IS_FMC_NORSRAM_DEVICE(Device));
lypinator	0:bb348c97df44	155	assert_param(IS_FMC_NORSRAM_BANK(Init->NSBank));
lypinator	0:bb348c97df44	156	assert_param(IS_FMC_MUX(Init->DataAddressMux));
lypinator	0:bb348c97df44	157	assert_param(IS_FMC_MEMORY(Init->MemoryType));
lypinator	0:bb348c97df44	158	assert_param(IS_FMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth));
lypinator	0:bb348c97df44	159	assert_param(IS_FMC_BURSTMODE(Init->BurstAccessMode));
lypinator	0:bb348c97df44	160	assert_param(IS_FMC_WAIT_POLARITY(Init->WaitSignalPolarity));
lypinator	0:bb348c97df44	161	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
lypinator	0:bb348c97df44	162	assert_param(IS_FMC_WRAP_MODE(Init->WrapMode));
lypinator	0:bb348c97df44	163	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
lypinator	0:bb348c97df44	164	assert_param(IS_FMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive));
lypinator	0:bb348c97df44	165	assert_param(IS_FMC_WRITE_OPERATION(Init->WriteOperation));
lypinator	0:bb348c97df44	166	assert_param(IS_FMC_WAITE_SIGNAL(Init->WaitSignal));
lypinator	0:bb348c97df44	167	assert_param(IS_FMC_EXTENDED_MODE(Init->ExtendedMode));
lypinator	0:bb348c97df44	168	assert_param(IS_FMC_ASYNWAIT(Init->AsynchronousWait));
lypinator	0:bb348c97df44	169	assert_param(IS_FMC_WRITE_BURST(Init->WriteBurst));
lypinator	0:bb348c97df44	170	assert_param(IS_FMC_CONTINOUS_CLOCK(Init->ContinuousClock));
lypinator	0:bb348c97df44	171	assert_param(IS_FMC_PAGESIZE(Init->PageSize));
lypinator	0:bb348c97df44	172	#if defined (STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
lypinator	0:bb348c97df44	173	assert_param(IS_FMC_WRITE_FIFO(Init->WriteFifo));
lypinator	0:bb348c97df44	174	#endif /* STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
lypinator	0:bb348c97df44	175
lypinator	0:bb348c97df44	176	/* Get the BTCR register value */
lypinator	0:bb348c97df44	177	tmpr = Device->BTCR[Init->NSBank];
lypinator	0:bb348c97df44	178
lypinator	0:bb348c97df44	179	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
lypinator	0:bb348c97df44	180	/* Clear MBKEN, MUXEN, MTYP, MWID, FACCEN, BURSTEN, WAITPOL, WRAPMOD, WAITCFG, WREN,
lypinator	0:bb348c97df44	181	WAITEN, EXTMOD, ASYNCWAIT, CPSIZE, CBURSTRW and CCLKEN bits */
lypinator	0:bb348c97df44	182	tmpr &= ((uint32_t)~(FMC_BCR1_MBKEN \| FMC_BCR1_MUXEN \| FMC_BCR1_MTYP \| \
lypinator	0:bb348c97df44	183	FMC_BCR1_MWID \| FMC_BCR1_FACCEN \| FMC_BCR1_BURSTEN \| \
lypinator	0:bb348c97df44	184	FMC_BCR1_WAITPOL \| FMC_BCR1_WRAPMOD \| FMC_BCR1_WAITCFG \| \
lypinator	0:bb348c97df44	185	FMC_BCR1_WREN \| FMC_BCR1_WAITEN \| FMC_BCR1_EXTMOD \| \
lypinator	0:bb348c97df44	186	FMC_BCR1_ASYNCWAIT \| FMC_BCR1_CPSIZE \| FMC_BCR1_CBURSTRW \| \
lypinator	0:bb348c97df44	187	FMC_BCR1_CCLKEN));
lypinator	0:bb348c97df44	188
lypinator	0:bb348c97df44	189	/* Set NORSRAM device control parameters */
lypinator	0:bb348c97df44	190	tmpr \|= (uint32_t)(Init->DataAddressMux \|\
lypinator	0:bb348c97df44	191	Init->MemoryType \|\
lypinator	0:bb348c97df44	192	Init->MemoryDataWidth \|\
lypinator	0:bb348c97df44	193	Init->BurstAccessMode \|\
lypinator	0:bb348c97df44	194	Init->WaitSignalPolarity \|\
lypinator	0:bb348c97df44	195	Init->WrapMode \|\
lypinator	0:bb348c97df44	196	Init->WaitSignalActive \|\
lypinator	0:bb348c97df44	197	Init->WriteOperation \|\
lypinator	0:bb348c97df44	198	Init->WaitSignal \|\
lypinator	0:bb348c97df44	199	Init->ExtendedMode \|\
lypinator	0:bb348c97df44	200	Init->AsynchronousWait \|\
lypinator	0:bb348c97df44	201	Init->PageSize \|\
lypinator	0:bb348c97df44	202	Init->WriteBurst \|\
lypinator	0:bb348c97df44	203	Init->ContinuousClock);
lypinator	0:bb348c97df44	204	#else /* defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx) */
lypinator	0:bb348c97df44	205	/* Clear MBKEN, MUXEN, MTYP, MWID, FACCEN, BURSTEN, WAITPOL, CPSIZE, WAITCFG, WREN,
lypinator	0:bb348c97df44	206	WAITEN, EXTMOD, ASYNCWAIT, CBURSTRW, CCLKEN and WFDIS bits */
lypinator	0:bb348c97df44	207	tmpr &= ((uint32_t)~(FMC_BCR1_MBKEN \| FMC_BCR1_MUXEN \| FMC_BCR1_MTYP \| \
lypinator	0:bb348c97df44	208	FMC_BCR1_MWID \| FMC_BCR1_FACCEN \| FMC_BCR1_BURSTEN \| \
lypinator	0:bb348c97df44	209	FMC_BCR1_WAITPOL \| FMC_BCR1_WAITCFG \| FMC_BCR1_CPSIZE \| \
lypinator	0:bb348c97df44	210	FMC_BCR1_WREN \| FMC_BCR1_WAITEN \| FMC_BCR1_EXTMOD \| \
lypinator	0:bb348c97df44	211	FMC_BCR1_ASYNCWAIT \| FMC_BCR1_CBURSTRW \| FMC_BCR1_CCLKEN \| \
lypinator	0:bb348c97df44	212	FMC_BCR1_WFDIS));
lypinator	0:bb348c97df44	213
lypinator	0:bb348c97df44	214	/* Set NORSRAM device control parameters */
lypinator	0:bb348c97df44	215	tmpr \|= (uint32_t)(Init->DataAddressMux \|\
lypinator	0:bb348c97df44	216	Init->MemoryType \|\
lypinator	0:bb348c97df44	217	Init->MemoryDataWidth \|\
lypinator	0:bb348c97df44	218	Init->BurstAccessMode \|\
lypinator	0:bb348c97df44	219	Init->WaitSignalPolarity \|\
lypinator	0:bb348c97df44	220	Init->WaitSignalActive \|\
lypinator	0:bb348c97df44	221	Init->WriteOperation \|\
lypinator	0:bb348c97df44	222	Init->WaitSignal \|\
lypinator	0:bb348c97df44	223	Init->ExtendedMode \|\
lypinator	0:bb348c97df44	224	Init->AsynchronousWait \|\
lypinator	0:bb348c97df44	225	Init->WriteBurst \|\
lypinator	0:bb348c97df44	226	Init->ContinuousClock \|\
lypinator	0:bb348c97df44	227	Init->PageSize \|\
lypinator	0:bb348c97df44	228	Init->WriteFifo);
lypinator	0:bb348c97df44	229	#endif /* defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) */
lypinator	0:bb348c97df44	230
lypinator	0:bb348c97df44	231	if(Init->MemoryType == FMC_MEMORY_TYPE_NOR)
lypinator	0:bb348c97df44	232	{
lypinator	0:bb348c97df44	233	tmpr \|= (uint32_t)FMC_NORSRAM_FLASH_ACCESS_ENABLE;
lypinator	0:bb348c97df44	234	}
lypinator	0:bb348c97df44	235
lypinator	0:bb348c97df44	236	Device->BTCR[Init->NSBank] = tmpr;
lypinator	0:bb348c97df44	237
lypinator	0:bb348c97df44	238	/* Configure synchronous mode when Continuous clock is enabled for bank2..4 */
lypinator	0:bb348c97df44	239	if((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BANK1))
lypinator	0:bb348c97df44	240	{
lypinator	0:bb348c97df44	241	Device->BTCR[FMC_NORSRAM_BANK1] \|= (uint32_t)(Init->ContinuousClock);
lypinator	0:bb348c97df44	242	}
lypinator	0:bb348c97df44	243
lypinator	0:bb348c97df44	244	#if defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
lypinator	0:bb348c97df44	245	if(Init->NSBank != FMC_NORSRAM_BANK1)
lypinator	0:bb348c97df44	246	{
lypinator	0:bb348c97df44	247	Device->BTCR[FMC_NORSRAM_BANK1] \|= (uint32_t)(Init->WriteFifo);
lypinator	0:bb348c97df44	248	}
lypinator	0:bb348c97df44	249	#endif /* STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
lypinator	0:bb348c97df44	250
lypinator	0:bb348c97df44	251	return HAL_OK;
lypinator	0:bb348c97df44	252	}
lypinator	0:bb348c97df44	253
lypinator	0:bb348c97df44	254	/**
lypinator	0:bb348c97df44	255	* @brief DeInitialize the FMC_NORSRAM peripheral
lypinator	0:bb348c97df44	256	* @param Device Pointer to NORSRAM device instance
lypinator	0:bb348c97df44	257	* @param ExDevice Pointer to NORSRAM extended mode device instance
lypinator	0:bb348c97df44	258	* @param Bank NORSRAM bank number
lypinator	0:bb348c97df44	259	* @retval HAL status
lypinator	0:bb348c97df44	260	*/
lypinator	0:bb348c97df44	261	HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef Device, FMC_NORSRAM_EXTENDED_TypeDef ExDevice, uint32_t Bank)
lypinator	0:bb348c97df44	262	{
lypinator	0:bb348c97df44	263	/* Check the parameters */
lypinator	0:bb348c97df44	264	assert_param(IS_FMC_NORSRAM_DEVICE(Device));
lypinator	0:bb348c97df44	265	assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(ExDevice));
lypinator	0:bb348c97df44	266	assert_param(IS_FMC_NORSRAM_BANK(Bank));
lypinator	0:bb348c97df44	267
lypinator	0:bb348c97df44	268	/* Disable the FMC_NORSRAM device */
lypinator	0:bb348c97df44	269	__FMC_NORSRAM_DISABLE(Device, Bank);
lypinator	0:bb348c97df44	270
lypinator	0:bb348c97df44	271	/* De-initialize the FMC_NORSRAM device */
lypinator	0:bb348c97df44	272	/* FMC_NORSRAM_BANK1 */
lypinator	0:bb348c97df44	273	if(Bank == FMC_NORSRAM_BANK1)
lypinator	0:bb348c97df44	274	{
lypinator	0:bb348c97df44	275	Device->BTCR[Bank] = 0x000030DBU;
lypinator	0:bb348c97df44	276	}
lypinator	0:bb348c97df44	277	/* FMC_NORSRAM_BANK2, FMC_NORSRAM_BANK3 or FMC_NORSRAM_BANK4 */
lypinator	0:bb348c97df44	278	else
lypinator	0:bb348c97df44	279	{
lypinator	0:bb348c97df44	280	Device->BTCR[Bank] = 0x000030D2U;
lypinator	0:bb348c97df44	281	}
lypinator	0:bb348c97df44	282
lypinator	0:bb348c97df44	283	Device->BTCR[Bank + 1U] = 0x0FFFFFFFU;
lypinator	0:bb348c97df44	284	ExDevice->BWTR[Bank] = 0x0FFFFFFFU;
lypinator	0:bb348c97df44	285
lypinator	0:bb348c97df44	286	return HAL_OK;
lypinator	0:bb348c97df44	287	}
lypinator	0:bb348c97df44	288
lypinator	0:bb348c97df44	289	/**
lypinator	0:bb348c97df44	290	* @brief Initialize the FMC_NORSRAM Timing according to the specified
lypinator	0:bb348c97df44	291	* parameters in the FMC_NORSRAM_TimingTypeDef
lypinator	0:bb348c97df44	292	* @param Device Pointer to NORSRAM device instance
lypinator	0:bb348c97df44	293	* @param Timing Pointer to NORSRAM Timing structure
lypinator	0:bb348c97df44	294	* @param Bank NORSRAM bank number
lypinator	0:bb348c97df44	295	* @retval HAL status
lypinator	0:bb348c97df44	296	*/
lypinator	0:bb348c97df44	297	HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef Device, FMC_NORSRAM_TimingTypeDef Timing, uint32_t Bank)
lypinator	0:bb348c97df44	298	{
lypinator	0:bb348c97df44	299	uint32_t tmpr = 0U;
lypinator	0:bb348c97df44	300
lypinator	0:bb348c97df44	301	/* Check the parameters */
lypinator	0:bb348c97df44	302	assert_param(IS_FMC_NORSRAM_DEVICE(Device));
lypinator	0:bb348c97df44	303	assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
lypinator	0:bb348c97df44	304	assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
lypinator	0:bb348c97df44	305	assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));
lypinator	0:bb348c97df44	306	assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
lypinator	0:bb348c97df44	307	assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision));
lypinator	0:bb348c97df44	308	assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency));
lypinator	0:bb348c97df44	309	assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
lypinator	0:bb348c97df44	310	assert_param(IS_FMC_NORSRAM_BANK(Bank));
lypinator	0:bb348c97df44	311
lypinator	0:bb348c97df44	312	/* Get the BTCR register value */
lypinator	0:bb348c97df44	313	tmpr = Device->BTCR[Bank + 1U];
lypinator	0:bb348c97df44	314
lypinator	0:bb348c97df44	315	/* Clear ADDSET, ADDHLD, DATAST, BUSTURN, CLKDIV, DATLAT and ACCMOD bits */
lypinator	0:bb348c97df44	316	tmpr &= ((uint32_t)~(FMC_BTR1_ADDSET \| FMC_BTR1_ADDHLD \| FMC_BTR1_DATAST \| \
lypinator	0:bb348c97df44	317	FMC_BTR1_BUSTURN \| FMC_BTR1_CLKDIV \| FMC_BTR1_DATLAT \| \
lypinator	0:bb348c97df44	318	FMC_BTR1_ACCMOD));
lypinator	0:bb348c97df44	319
lypinator	0:bb348c97df44	320	/* Set FMC_NORSRAM device timing parameters */
lypinator	0:bb348c97df44	321	tmpr \|= (uint32_t)(Timing->AddressSetupTime \|\
lypinator	0:bb348c97df44	322	((Timing->AddressHoldTime) << 4U) \|\
lypinator	0:bb348c97df44	323	((Timing->DataSetupTime) << 8U) \|\
lypinator	0:bb348c97df44	324	((Timing->BusTurnAroundDuration) << 16U) \|\
lypinator	0:bb348c97df44	325	(((Timing->CLKDivision) - 1U) << 20U) \|\
lypinator	0:bb348c97df44	326	(((Timing->DataLatency) - 2U) << 24U) \|\
lypinator	0:bb348c97df44	327	(Timing->AccessMode));
lypinator	0:bb348c97df44	328
lypinator	0:bb348c97df44	329	Device->BTCR[Bank + 1U] = tmpr;
lypinator	0:bb348c97df44	330
lypinator	0:bb348c97df44	331	/* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */
lypinator	0:bb348c97df44	332	if(HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN))
lypinator	0:bb348c97df44	333	{
lypinator	0:bb348c97df44	334	tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1U] & ~(0x0FU << 20U));
lypinator	0:bb348c97df44	335	tmpr \|= (uint32_t)(((Timing->CLKDivision) - 1U) << 20U);
lypinator	0:bb348c97df44	336	Device->BTCR[FMC_NORSRAM_BANK1 + 1U] = tmpr;
lypinator	0:bb348c97df44	337	}
lypinator	0:bb348c97df44	338
lypinator	0:bb348c97df44	339	return HAL_OK;
lypinator	0:bb348c97df44	340	}
lypinator	0:bb348c97df44	341
lypinator	0:bb348c97df44	342	/**
lypinator	0:bb348c97df44	343	* @brief Initialize the FMC_NORSRAM Extended mode Timing according to the specified
lypinator	0:bb348c97df44	344	* parameters in the FMC_NORSRAM_TimingTypeDef
lypinator	0:bb348c97df44	345	* @param Device Pointer to NORSRAM device instance
lypinator	0:bb348c97df44	346	* @param Timing Pointer to NORSRAM Timing structure
lypinator	0:bb348c97df44	347	* @param Bank NORSRAM bank number
lypinator	0:bb348c97df44	348	* @retval HAL status
lypinator	0:bb348c97df44	349	*/
lypinator	0:bb348c97df44	350	HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef Device, FMC_NORSRAM_TimingTypeDef Timing, uint32_t Bank, uint32_t ExtendedMode)
lypinator	0:bb348c97df44	351	{
lypinator	0:bb348c97df44	352	uint32_t tmpr = 0U;
lypinator	0:bb348c97df44	353
lypinator	0:bb348c97df44	354	/* Check the parameters */
lypinator	0:bb348c97df44	355	assert_param(IS_FMC_EXTENDED_MODE(ExtendedMode));
lypinator	0:bb348c97df44	356
lypinator	0:bb348c97df44	357	/* Set NORSRAM device timing register for write configuration, if extended mode is used */
lypinator	0:bb348c97df44	358	if(ExtendedMode == FMC_EXTENDED_MODE_ENABLE)
lypinator	0:bb348c97df44	359	{
lypinator	0:bb348c97df44	360	/* Check the parameters */
lypinator	0:bb348c97df44	361	assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(Device));
lypinator	0:bb348c97df44	362	assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
lypinator	0:bb348c97df44	363	assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
lypinator	0:bb348c97df44	364	assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));
lypinator	0:bb348c97df44	365	assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
lypinator	0:bb348c97df44	366	assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
lypinator	0:bb348c97df44	367	assert_param(IS_FMC_NORSRAM_BANK(Bank));
lypinator	0:bb348c97df44	368
lypinator	0:bb348c97df44	369	/* Get the BWTR register value */
lypinator	0:bb348c97df44	370	tmpr = Device->BWTR[Bank];
lypinator	0:bb348c97df44	371
lypinator	0:bb348c97df44	372	/* Clear ADDSET, ADDHLD, DATAST, BUSTURN and ACCMOD bits */
lypinator	0:bb348c97df44	373	tmpr &= ((uint32_t)~(FMC_BWTR1_ADDSET \| FMC_BWTR1_ADDHLD \| FMC_BWTR1_DATAST \| \
lypinator	0:bb348c97df44	374	FMC_BWTR1_BUSTURN \| FMC_BWTR1_ACCMOD));
lypinator	0:bb348c97df44	375
lypinator	0:bb348c97df44	376	tmpr \|= (uint32_t)(Timing->AddressSetupTime \|\
lypinator	0:bb348c97df44	377	((Timing->AddressHoldTime) << 4U) \|\
lypinator	0:bb348c97df44	378	((Timing->DataSetupTime) << 8U) \|\
lypinator	0:bb348c97df44	379	((Timing->BusTurnAroundDuration) << 16U) \|\
lypinator	0:bb348c97df44	380	(Timing->AccessMode));
lypinator	0:bb348c97df44	381
lypinator	0:bb348c97df44	382	Device->BWTR[Bank] = tmpr;
lypinator	0:bb348c97df44	383	}
lypinator	0:bb348c97df44	384	else
lypinator	0:bb348c97df44	385	{
lypinator	0:bb348c97df44	386	Device->BWTR[Bank] = 0x0FFFFFFFU;
lypinator	0:bb348c97df44	387	}
lypinator	0:bb348c97df44	388
lypinator	0:bb348c97df44	389	return HAL_OK;
lypinator	0:bb348c97df44	390	}
lypinator	0:bb348c97df44	391	/**
lypinator	0:bb348c97df44	392	* @}
lypinator	0:bb348c97df44	393	*/
lypinator	0:bb348c97df44	394
lypinator	0:bb348c97df44	395	/** @addtogroup FMC_LL_NORSRAM_Private_Functions_Group2
lypinator	0:bb348c97df44	396	* @brief management functions
lypinator	0:bb348c97df44	397	*
lypinator	0:bb348c97df44	398	@verbatim
lypinator	0:bb348c97df44	399	==============================================================================
lypinator	0:bb348c97df44	400	##### FMC_NORSRAM Control functions #####
lypinator	0:bb348c97df44	401	==============================================================================
lypinator	0:bb348c97df44	402	[..]
lypinator	0:bb348c97df44	403	This subsection provides a set of functions allowing to control dynamically
lypinator	0:bb348c97df44	404	the FMC NORSRAM interface.
lypinator	0:bb348c97df44	405
lypinator	0:bb348c97df44	406	@endverbatim
lypinator	0:bb348c97df44	407	* @{
lypinator	0:bb348c97df44	408	*/
lypinator	0:bb348c97df44	409	/**
lypinator	0:bb348c97df44	410	* @brief Enables dynamically FMC_NORSRAM write operation.
lypinator	0:bb348c97df44	411	* @param Device Pointer to NORSRAM device instance
lypinator	0:bb348c97df44	412	* @param Bank NORSRAM bank number
lypinator	0:bb348c97df44	413	* @retval HAL status
lypinator	0:bb348c97df44	414	*/
lypinator	0:bb348c97df44	415	HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)
lypinator	0:bb348c97df44	416	{
lypinator	0:bb348c97df44	417	/* Check the parameters */
lypinator	0:bb348c97df44	418	assert_param(IS_FMC_NORSRAM_DEVICE(Device));
lypinator	0:bb348c97df44	419	assert_param(IS_FMC_NORSRAM_BANK(Bank));
lypinator	0:bb348c97df44	420
lypinator	0:bb348c97df44	421	/* Enable write operation */
lypinator	0:bb348c97df44	422	Device->BTCR[Bank] \|= FMC_WRITE_OPERATION_ENABLE;
lypinator	0:bb348c97df44	423
lypinator	0:bb348c97df44	424	return HAL_OK;
lypinator	0:bb348c97df44	425	}
lypinator	0:bb348c97df44	426
lypinator	0:bb348c97df44	427	/**
lypinator	0:bb348c97df44	428	* @brief Disables dynamically FMC_NORSRAM write operation.
lypinator	0:bb348c97df44	429	* @param Device Pointer to NORSRAM device instance
lypinator	0:bb348c97df44	430	* @param Bank NORSRAM bank number
lypinator	0:bb348c97df44	431	* @retval HAL status
lypinator	0:bb348c97df44	432	*/
lypinator	0:bb348c97df44	433	HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)
lypinator	0:bb348c97df44	434	{
lypinator	0:bb348c97df44	435	/* Check the parameters */
lypinator	0:bb348c97df44	436	assert_param(IS_FMC_NORSRAM_DEVICE(Device));
lypinator	0:bb348c97df44	437	assert_param(IS_FMC_NORSRAM_BANK(Bank));
lypinator	0:bb348c97df44	438
lypinator	0:bb348c97df44	439	/* Disable write operation */
lypinator	0:bb348c97df44	440	Device->BTCR[Bank] &= ~FMC_WRITE_OPERATION_ENABLE;
lypinator	0:bb348c97df44	441
lypinator	0:bb348c97df44	442	return HAL_OK;
lypinator	0:bb348c97df44	443	}
lypinator	0:bb348c97df44	444
lypinator	0:bb348c97df44	445	/**
lypinator	0:bb348c97df44	446	* @}
lypinator	0:bb348c97df44	447	*/
lypinator	0:bb348c97df44	448
lypinator	0:bb348c97df44	449	/**
lypinator	0:bb348c97df44	450	* @}
lypinator	0:bb348c97df44	451	*/
lypinator	0:bb348c97df44	452
lypinator	0:bb348c97df44	453	/** @addtogroup FMC_LL_NAND
lypinator	0:bb348c97df44	454	* @brief NAND Controller functions
lypinator	0:bb348c97df44	455	*
lypinator	0:bb348c97df44	456	@verbatim
lypinator	0:bb348c97df44	457	==============================================================================
lypinator	0:bb348c97df44	458	##### How to use NAND device driver #####
lypinator	0:bb348c97df44	459	==============================================================================
lypinator	0:bb348c97df44	460	[..]
lypinator	0:bb348c97df44	461	This driver contains a set of APIs to interface with the FMC NAND banks in order
lypinator	0:bb348c97df44	462	to run the NAND external devices.
lypinator	0:bb348c97df44	463
lypinator	0:bb348c97df44	464	(+) FMC NAND bank reset using the function FMC_NAND_DeInit()
lypinator	0:bb348c97df44	465	(+) FMC NAND bank control configuration using the function FMC_NAND_Init()
lypinator	0:bb348c97df44	466	(+) FMC NAND bank common space timing configuration using the function
lypinator	0:bb348c97df44	467	FMC_NAND_CommonSpace_Timing_Init()
lypinator	0:bb348c97df44	468	(+) FMC NAND bank attribute space timing configuration using the function
lypinator	0:bb348c97df44	469	FMC_NAND_AttributeSpace_Timing_Init()
lypinator	0:bb348c97df44	470	(+) FMC NAND bank enable/disable ECC correction feature using the functions
lypinator	0:bb348c97df44	471	FMC_NAND_ECC_Enable()/FMC_NAND_ECC_Disable()
lypinator	0:bb348c97df44	472	(+) FMC NAND bank get ECC correction code using the function FMC_NAND_GetECC()
lypinator	0:bb348c97df44	473
lypinator	0:bb348c97df44	474	@endverbatim
lypinator	0:bb348c97df44	475	* @{
lypinator	0:bb348c97df44	476	*/
lypinator	0:bb348c97df44	477
lypinator	0:bb348c97df44	478	#if defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
lypinator	0:bb348c97df44	479	/** @defgroup HAL_FMC_NAND_Group1 Initialization/de-initialization functions
lypinator	0:bb348c97df44	480	* @brief Initialization and Configuration functions
lypinator	0:bb348c97df44	481	*
lypinator	0:bb348c97df44	482	@verbatim
lypinator	0:bb348c97df44	483	==============================================================================
lypinator	0:bb348c97df44	484	##### Initialization and de_initialization functions #####
lypinator	0:bb348c97df44	485	==============================================================================
lypinator	0:bb348c97df44	486	[..]
lypinator	0:bb348c97df44	487	This section provides functions allowing to:
lypinator	0:bb348c97df44	488	(+) Initialize and configure the FMC NAND interface
lypinator	0:bb348c97df44	489	(+) De-initialize the FMC NAND interface
lypinator	0:bb348c97df44	490	(+) Configure the FMC clock and associated GPIOs
lypinator	0:bb348c97df44	491
lypinator	0:bb348c97df44	492	@endverbatim
lypinator	0:bb348c97df44	493	* @{
lypinator	0:bb348c97df44	494	*/
lypinator	0:bb348c97df44	495
lypinator	0:bb348c97df44	496	/**
lypinator	0:bb348c97df44	497	* @brief Initializes the FMC_NAND device according to the specified
lypinator	0:bb348c97df44	498	* control parameters in the FMC_NAND_HandleTypeDef
lypinator	0:bb348c97df44	499	* @param Device Pointer to NAND device instance
lypinator	0:bb348c97df44	500	* @param Init Pointer to NAND Initialization structure
lypinator	0:bb348c97df44	501	* @retval HAL status
lypinator	0:bb348c97df44	502	*/
lypinator	0:bb348c97df44	503	HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef Device, FMC_NAND_InitTypeDef Init)
lypinator	0:bb348c97df44	504	{
lypinator	0:bb348c97df44	505	uint32_t tmpr = 0U;
lypinator	0:bb348c97df44	506
lypinator	0:bb348c97df44	507	/* Check the parameters */
lypinator	0:bb348c97df44	508	assert_param(IS_FMC_NAND_DEVICE(Device));
lypinator	0:bb348c97df44	509	assert_param(IS_FMC_NAND_BANK(Init->NandBank));
lypinator	0:bb348c97df44	510	assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature));
lypinator	0:bb348c97df44	511	assert_param(IS_FMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth));
lypinator	0:bb348c97df44	512	assert_param(IS_FMC_ECC_STATE(Init->EccComputation));
lypinator	0:bb348c97df44	513	assert_param(IS_FMC_ECCPAGE_SIZE(Init->ECCPageSize));
lypinator	0:bb348c97df44	514	assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime));
lypinator	0:bb348c97df44	515	assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime));
lypinator	0:bb348c97df44	516
lypinator	0:bb348c97df44	517	/* Get the NAND bank register value */
lypinator	0:bb348c97df44	518	tmpr = Device->PCR;
lypinator	0:bb348c97df44	519
lypinator	0:bb348c97df44	520	/* Clear PWAITEN, PBKEN, PTYP, PWID, ECCEN, TCLR, TAR and ECCPS bits */
lypinator	0:bb348c97df44	521	tmpr &= ((uint32_t)~(FMC_PCR_PWAITEN \| FMC_PCR_PBKEN \| FMC_PCR_PTYP \| \
lypinator	0:bb348c97df44	522	FMC_PCR_PWID \| FMC_PCR_ECCEN \| FMC_PCR_TCLR \| \
lypinator	0:bb348c97df44	523	FMC_PCR_TAR \| FMC_PCR_ECCPS));
lypinator	0:bb348c97df44	524
lypinator	0:bb348c97df44	525	/* Set NAND device control parameters */
lypinator	0:bb348c97df44	526	tmpr \|= (uint32_t)(Init->Waitfeature \|\
lypinator	0:bb348c97df44	527	FMC_PCR_MEMORY_TYPE_NAND \|\
lypinator	0:bb348c97df44	528	Init->MemoryDataWidth \|\
lypinator	0:bb348c97df44	529	Init->EccComputation \|\
lypinator	0:bb348c97df44	530	Init->ECCPageSize \|\
lypinator	0:bb348c97df44	531	((Init->TCLRSetupTime) << 9U) \|\
lypinator	0:bb348c97df44	532	((Init->TARSetupTime) << 13U));
lypinator	0:bb348c97df44	533
lypinator	0:bb348c97df44	534	/* NAND bank registers configuration */
lypinator	0:bb348c97df44	535	Device->PCR = tmpr;
lypinator	0:bb348c97df44	536
lypinator	0:bb348c97df44	537	return HAL_OK;
lypinator	0:bb348c97df44	538	}
lypinator	0:bb348c97df44	539
lypinator	0:bb348c97df44	540	/**
lypinator	0:bb348c97df44	541	* @brief Initializes the FMC_NAND Common space Timing according to the specified
lypinator	0:bb348c97df44	542	* parameters in the FMC_NAND_PCC_TimingTypeDef
lypinator	0:bb348c97df44	543	* @param Device Pointer to NAND device instance
lypinator	0:bb348c97df44	544	* @param Timing Pointer to NAND timing structure
lypinator	0:bb348c97df44	545	* @param Bank NAND bank number
lypinator	0:bb348c97df44	546	* @retval HAL status
lypinator	0:bb348c97df44	547	*/
lypinator	0:bb348c97df44	548	HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing, uint32_t Bank)
lypinator	0:bb348c97df44	549	{
lypinator	0:bb348c97df44	550	uint32_t tmpr = 0U;
lypinator	0:bb348c97df44	551
lypinator	0:bb348c97df44	552	/* Check the parameters */
lypinator	0:bb348c97df44	553	assert_param(IS_FMC_NAND_DEVICE(Device));
lypinator	0:bb348c97df44	554	assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
lypinator	0:bb348c97df44	555	assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
lypinator	0:bb348c97df44	556	assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
lypinator	0:bb348c97df44	557	assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
lypinator	0:bb348c97df44	558	assert_param(IS_FMC_NAND_BANK(Bank));
lypinator	0:bb348c97df44	559
lypinator	0:bb348c97df44	560	/* Get the NAND bank 2 register value */
lypinator	0:bb348c97df44	561	tmpr = Device->PMEM;
lypinator	0:bb348c97df44	562
lypinator	0:bb348c97df44	563
lypinator	0:bb348c97df44	564	/* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */
lypinator	0:bb348c97df44	565	tmpr &= ((uint32_t)~(FMC_PMEM_MEMSET2 \| FMC_PMEM_MEMWAIT2 \| FMC_PMEM_MEMHOLD2 \| \
lypinator	0:bb348c97df44	566	FMC_PMEM_MEMHIZ2));
lypinator	0:bb348c97df44	567
lypinator	0:bb348c97df44	568	/* Set FMC_NAND device timing parameters */
lypinator	0:bb348c97df44	569	tmpr \|= (uint32_t)(Timing->SetupTime \|\
lypinator	0:bb348c97df44	570	((Timing->WaitSetupTime) << 8U) \|\
lypinator	0:bb348c97df44	571	((Timing->HoldSetupTime) << 16U) \|\
lypinator	0:bb348c97df44	572	((Timing->HiZSetupTime) << 24U)
lypinator	0:bb348c97df44	573	);
lypinator	0:bb348c97df44	574
lypinator	0:bb348c97df44	575	/* NAND bank registers configuration */
lypinator	0:bb348c97df44	576	Device->PMEM = tmpr;
lypinator	0:bb348c97df44	577
lypinator	0:bb348c97df44	578	return HAL_OK;
lypinator	0:bb348c97df44	579	}
lypinator	0:bb348c97df44	580
lypinator	0:bb348c97df44	581	/**
lypinator	0:bb348c97df44	582	* @brief Initializes the FMC_NAND Attribute space Timing according to the specified
lypinator	0:bb348c97df44	583	* parameters in the FMC_NAND_PCC_TimingTypeDef
lypinator	0:bb348c97df44	584	* @param Device Pointer to NAND device instance
lypinator	0:bb348c97df44	585	* @param Timing Pointer to NAND timing structure
lypinator	0:bb348c97df44	586	* @param Bank NAND bank number
lypinator	0:bb348c97df44	587	* @retval HAL status
lypinator	0:bb348c97df44	588	*/
lypinator	0:bb348c97df44	589	HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing, uint32_t Bank)
lypinator	0:bb348c97df44	590	{
lypinator	0:bb348c97df44	591	uint32_t tmpr = 0U;
lypinator	0:bb348c97df44	592
lypinator	0:bb348c97df44	593	/* Check the parameters */
lypinator	0:bb348c97df44	594	assert_param(IS_FMC_NAND_DEVICE(Device));
lypinator	0:bb348c97df44	595	assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
lypinator	0:bb348c97df44	596	assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
lypinator	0:bb348c97df44	597	assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
lypinator	0:bb348c97df44	598	assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
lypinator	0:bb348c97df44	599	assert_param(IS_FMC_NAND_BANK(Bank));
lypinator	0:bb348c97df44	600
lypinator	0:bb348c97df44	601	/* Get the NAND bank register value */
lypinator	0:bb348c97df44	602	tmpr = Device->PATT;
lypinator	0:bb348c97df44	603
lypinator	0:bb348c97df44	604	/* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */
lypinator	0:bb348c97df44	605	tmpr &= ((uint32_t)~(FMC_PATT_ATTSET2 \| FMC_PATT_ATTWAIT2 \| FMC_PATT_ATTHOLD2 \| \
lypinator	0:bb348c97df44	606	FMC_PATT_ATTHIZ2));
lypinator	0:bb348c97df44	607
lypinator	0:bb348c97df44	608	/* Set FMC_NAND device timing parameters */
lypinator	0:bb348c97df44	609	tmpr \|= (uint32_t)(Timing->SetupTime \|\
lypinator	0:bb348c97df44	610	((Timing->WaitSetupTime) << 8U) \|\
lypinator	0:bb348c97df44	611	((Timing->HoldSetupTime) << 16U) \|\
lypinator	0:bb348c97df44	612	((Timing->HiZSetupTime) << 24U));
lypinator	0:bb348c97df44	613
lypinator	0:bb348c97df44	614	/* NAND bank registers configuration */
lypinator	0:bb348c97df44	615	Device->PATT = tmpr;
lypinator	0:bb348c97df44	616
lypinator	0:bb348c97df44	617	return HAL_OK;
lypinator	0:bb348c97df44	618	}
lypinator	0:bb348c97df44	619
lypinator	0:bb348c97df44	620
lypinator	0:bb348c97df44	621	/**
lypinator	0:bb348c97df44	622	* @brief DeInitializes the FMC_NAND device
lypinator	0:bb348c97df44	623	* @param Device Pointer to NAND device instance
lypinator	0:bb348c97df44	624	* @param Bank NAND bank number
lypinator	0:bb348c97df44	625	* @retval HAL status
lypinator	0:bb348c97df44	626	*/
lypinator	0:bb348c97df44	627	HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank)
lypinator	0:bb348c97df44	628	{
lypinator	0:bb348c97df44	629	/* Check the parameters */
lypinator	0:bb348c97df44	630	assert_param(IS_FMC_NAND_DEVICE(Device));
lypinator	0:bb348c97df44	631	assert_param(IS_FMC_NAND_BANK(Bank));
lypinator	0:bb348c97df44	632
lypinator	0:bb348c97df44	633	/* Disable the NAND Bank */
lypinator	0:bb348c97df44	634	__FMC_NAND_DISABLE(Device, Bank);
lypinator	0:bb348c97df44	635
lypinator	0:bb348c97df44	636	/* De-initialize the NAND Bank */
lypinator	0:bb348c97df44	637	/* Set the FMC_NAND_BANK registers to their reset values */
lypinator	0:bb348c97df44	638	Device->PCR = 0x00000018U;
lypinator	0:bb348c97df44	639	Device->SR = 0x00000040U;
lypinator	0:bb348c97df44	640	Device->PMEM = 0xFCFCFCFCU;
lypinator	0:bb348c97df44	641	Device->PATT = 0xFCFCFCFCU;
lypinator	0:bb348c97df44	642
lypinator	0:bb348c97df44	643	return HAL_OK;
lypinator	0:bb348c97df44	644	}
lypinator	0:bb348c97df44	645
lypinator	0:bb348c97df44	646	/**
lypinator	0:bb348c97df44	647	* @}
lypinator	0:bb348c97df44	648	*/
lypinator	0:bb348c97df44	649
lypinator	0:bb348c97df44	650
lypinator	0:bb348c97df44	651	/** @defgroup HAL_FMC_NAND_Group2 Control functions
lypinator	0:bb348c97df44	652	* @brief management functions
lypinator	0:bb348c97df44	653	*
lypinator	0:bb348c97df44	654	@verbatim
lypinator	0:bb348c97df44	655	==============================================================================
lypinator	0:bb348c97df44	656	##### FMC_NAND Control functions #####
lypinator	0:bb348c97df44	657	==============================================================================
lypinator	0:bb348c97df44	658	[..]
lypinator	0:bb348c97df44	659	This subsection provides a set of functions allowing to control dynamically
lypinator	0:bb348c97df44	660	the FMC NAND interface.
lypinator	0:bb348c97df44	661
lypinator	0:bb348c97df44	662	@endverbatim
lypinator	0:bb348c97df44	663	* @{
lypinator	0:bb348c97df44	664	*/
lypinator	0:bb348c97df44	665
lypinator	0:bb348c97df44	666
lypinator	0:bb348c97df44	667	/**
lypinator	0:bb348c97df44	668	* @brief Enables dynamically FMC_NAND ECC feature.
lypinator	0:bb348c97df44	669	* @param Device Pointer to NAND device instance
lypinator	0:bb348c97df44	670	* @param Bank NAND bank number
lypinator	0:bb348c97df44	671	* @retval HAL status
lypinator	0:bb348c97df44	672	*/
lypinator	0:bb348c97df44	673	HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank)
lypinator	0:bb348c97df44	674	{
lypinator	0:bb348c97df44	675	/* Check the parameters */
lypinator	0:bb348c97df44	676	assert_param(IS_FMC_NAND_DEVICE(Device));
lypinator	0:bb348c97df44	677	assert_param(IS_FMC_NAND_BANK(Bank));
lypinator	0:bb348c97df44	678
lypinator	0:bb348c97df44	679	/* Enable ECC feature */
lypinator	0:bb348c97df44	680	Device->PCR \|= FMC_PCR_ECCEN;
lypinator	0:bb348c97df44	681
lypinator	0:bb348c97df44	682	return HAL_OK;
lypinator	0:bb348c97df44	683	}
lypinator	0:bb348c97df44	684
lypinator	0:bb348c97df44	685
lypinator	0:bb348c97df44	686	/**
lypinator	0:bb348c97df44	687	* @brief Disables dynamically FMC_NAND ECC feature.
lypinator	0:bb348c97df44	688	* @param Device Pointer to NAND device instance
lypinator	0:bb348c97df44	689	* @param Bank NAND bank number
lypinator	0:bb348c97df44	690	* @retval HAL status
lypinator	0:bb348c97df44	691	*/
lypinator	0:bb348c97df44	692	HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank)
lypinator	0:bb348c97df44	693	{
lypinator	0:bb348c97df44	694	/* Check the parameters */
lypinator	0:bb348c97df44	695	assert_param(IS_FMC_NAND_DEVICE(Device));
lypinator	0:bb348c97df44	696	assert_param(IS_FMC_NAND_BANK(Bank));
lypinator	0:bb348c97df44	697
lypinator	0:bb348c97df44	698	/* Disable ECC feature */
lypinator	0:bb348c97df44	699	Device->PCR &= ~FMC_PCR_ECCEN;
lypinator	0:bb348c97df44	700
lypinator	0:bb348c97df44	701	return HAL_OK;
lypinator	0:bb348c97df44	702	}
lypinator	0:bb348c97df44	703
lypinator	0:bb348c97df44	704	/**
lypinator	0:bb348c97df44	705	* @brief Disables dynamically FMC_NAND ECC feature.
lypinator	0:bb348c97df44	706	* @param Device Pointer to NAND device instance
lypinator	0:bb348c97df44	707	* @param ECCval Pointer to ECC value
lypinator	0:bb348c97df44	708	* @param Bank NAND bank number
lypinator	0:bb348c97df44	709	* @param Timeout Timeout wait value
lypinator	0:bb348c97df44	710	* @retval HAL status
lypinator	0:bb348c97df44	711	*/
lypinator	0:bb348c97df44	712	HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef Device, uint32_t ECCval, uint32_t Bank, uint32_t Timeout)
lypinator	0:bb348c97df44	713	{
lypinator	0:bb348c97df44	714	uint32_t tickstart = 0U;
lypinator	0:bb348c97df44	715
lypinator	0:bb348c97df44	716	/* Check the parameters */
lypinator	0:bb348c97df44	717	assert_param(IS_FMC_NAND_DEVICE(Device));
lypinator	0:bb348c97df44	718	assert_param(IS_FMC_NAND_BANK(Bank));
lypinator	0:bb348c97df44	719
lypinator	0:bb348c97df44	720	/* Get tick */
lypinator	0:bb348c97df44	721	tickstart = HAL_GetTick();
lypinator	0:bb348c97df44	722
lypinator	0:bb348c97df44	723	/* Wait until FIFO is empty */
lypinator	0:bb348c97df44	724	while(__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT) == RESET)
lypinator	0:bb348c97df44	725	{
lypinator	0:bb348c97df44	726	/* Check for the Timeout */
lypinator	0:bb348c97df44	727	if(Timeout != HAL_MAX_DELAY)
lypinator	0:bb348c97df44	728	{
lypinator	0:bb348c97df44	729	if((Timeout == 0U)\|\|((HAL_GetTick() - tickstart ) > Timeout))
lypinator	0:bb348c97df44	730	{
lypinator	0:bb348c97df44	731	return HAL_TIMEOUT;
lypinator	0:bb348c97df44	732	}
lypinator	0:bb348c97df44	733	}
lypinator	0:bb348c97df44	734	}
lypinator	0:bb348c97df44	735
lypinator	0:bb348c97df44	736	/* Get the ECCR register value */
lypinator	0:bb348c97df44	737	*ECCval = (uint32_t)Device->ECCR;
lypinator	0:bb348c97df44	738
lypinator	0:bb348c97df44	739	return HAL_OK;
lypinator	0:bb348c97df44	740	}
lypinator	0:bb348c97df44	741
lypinator	0:bb348c97df44	742	/**
lypinator	0:bb348c97df44	743	* @}
lypinator	0:bb348c97df44	744	*/
lypinator	0:bb348c97df44	745
lypinator	0:bb348c97df44	746	#else /* defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) */
lypinator	0:bb348c97df44	747	/** @defgroup HAL_FMC_NAND_Group1 Initialization/de-initialization functions
lypinator	0:bb348c97df44	748	* @brief Initialization and Configuration functions
lypinator	0:bb348c97df44	749	*
lypinator	0:bb348c97df44	750	@verbatim
lypinator	0:bb348c97df44	751	==============================================================================
lypinator	0:bb348c97df44	752	##### Initialization and de_initialization functions #####
lypinator	0:bb348c97df44	753	==============================================================================
lypinator	0:bb348c97df44	754	[..]
lypinator	0:bb348c97df44	755	This section provides functions allowing to:
lypinator	0:bb348c97df44	756	(+) Initialize and configure the FMC NAND interface
lypinator	0:bb348c97df44	757	(+) De-initialize the FMC NAND interface
lypinator	0:bb348c97df44	758	(+) Configure the FMC clock and associated GPIOs
lypinator	0:bb348c97df44	759
lypinator	0:bb348c97df44	760	@endverbatim
lypinator	0:bb348c97df44	761	* @{
lypinator	0:bb348c97df44	762	*/
lypinator	0:bb348c97df44	763	/**
lypinator	0:bb348c97df44	764	* @brief Initializes the FMC_NAND device according to the specified
lypinator	0:bb348c97df44	765	* control parameters in the FMC_NAND_HandleTypeDef
lypinator	0:bb348c97df44	766	* @param Device Pointer to NAND device instance
lypinator	0:bb348c97df44	767	* @param Init Pointer to NAND Initialization structure
lypinator	0:bb348c97df44	768	* @retval HAL status
lypinator	0:bb348c97df44	769	*/
lypinator	0:bb348c97df44	770	HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef Device, FMC_NAND_InitTypeDef Init)
lypinator	0:bb348c97df44	771	{
lypinator	0:bb348c97df44	772	uint32_t tmpr = 0U;
lypinator	0:bb348c97df44	773
lypinator	0:bb348c97df44	774	/* Check the parameters */
lypinator	0:bb348c97df44	775	assert_param(IS_FMC_NAND_DEVICE(Device));
lypinator	0:bb348c97df44	776	assert_param(IS_FMC_NAND_BANK(Init->NandBank));
lypinator	0:bb348c97df44	777	assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature));
lypinator	0:bb348c97df44	778	assert_param(IS_FMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth));
lypinator	0:bb348c97df44	779	assert_param(IS_FMC_ECC_STATE(Init->EccComputation));
lypinator	0:bb348c97df44	780	assert_param(IS_FMC_ECCPAGE_SIZE(Init->ECCPageSize));
lypinator	0:bb348c97df44	781	assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime));
lypinator	0:bb348c97df44	782	assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime));
lypinator	0:bb348c97df44	783
lypinator	0:bb348c97df44	784	if(Init->NandBank == FMC_NAND_BANK2)
lypinator	0:bb348c97df44	785	{
lypinator	0:bb348c97df44	786	/* Get the NAND bank 2 register value */
lypinator	0:bb348c97df44	787	tmpr = Device->PCR2;
lypinator	0:bb348c97df44	788	}
lypinator	0:bb348c97df44	789	else
lypinator	0:bb348c97df44	790	{
lypinator	0:bb348c97df44	791	/* Get the NAND bank 3 register value */
lypinator	0:bb348c97df44	792	tmpr = Device->PCR3;
lypinator	0:bb348c97df44	793	}
lypinator	0:bb348c97df44	794
lypinator	0:bb348c97df44	795	/* Clear PWAITEN, PBKEN, PTYP, PWID, ECCEN, TCLR, TAR and ECCPS bits */
lypinator	0:bb348c97df44	796	tmpr &= ((uint32_t)~(FMC_PCR2_PWAITEN \| FMC_PCR2_PBKEN \| FMC_PCR2_PTYP \| \
lypinator	0:bb348c97df44	797	FMC_PCR2_PWID \| FMC_PCR2_ECCEN \| FMC_PCR2_TCLR \| \
lypinator	0:bb348c97df44	798	FMC_PCR2_TAR \| FMC_PCR2_ECCPS));
lypinator	0:bb348c97df44	799
lypinator	0:bb348c97df44	800	/* Set NAND device control parameters */
lypinator	0:bb348c97df44	801	tmpr \|= (uint32_t)(Init->Waitfeature \|\
lypinator	0:bb348c97df44	802	FMC_PCR_MEMORY_TYPE_NAND \|\
lypinator	0:bb348c97df44	803	Init->MemoryDataWidth \|\
lypinator	0:bb348c97df44	804	Init->EccComputation \|\
lypinator	0:bb348c97df44	805	Init->ECCPageSize \|\
lypinator	0:bb348c97df44	806	((Init->TCLRSetupTime) << 9U) \|\
lypinator	0:bb348c97df44	807	((Init->TARSetupTime) << 13U));
lypinator	0:bb348c97df44	808
lypinator	0:bb348c97df44	809	if(Init->NandBank == FMC_NAND_BANK2)
lypinator	0:bb348c97df44	810	{
lypinator	0:bb348c97df44	811	/* NAND bank 2 registers configuration */
lypinator	0:bb348c97df44	812	Device->PCR2 = tmpr;
lypinator	0:bb348c97df44	813	}
lypinator	0:bb348c97df44	814	else
lypinator	0:bb348c97df44	815	{
lypinator	0:bb348c97df44	816	/* NAND bank 3 registers configuration */
lypinator	0:bb348c97df44	817	Device->PCR3 = tmpr;
lypinator	0:bb348c97df44	818	}
lypinator	0:bb348c97df44	819
lypinator	0:bb348c97df44	820	return HAL_OK;
lypinator	0:bb348c97df44	821
lypinator	0:bb348c97df44	822	}
lypinator	0:bb348c97df44	823
lypinator	0:bb348c97df44	824	/**
lypinator	0:bb348c97df44	825	* @brief Initializes the FMC_NAND Common space Timing according to the specified
lypinator	0:bb348c97df44	826	* parameters in the FMC_NAND_PCC_TimingTypeDef
lypinator	0:bb348c97df44	827	* @param Device Pointer to NAND device instance
lypinator	0:bb348c97df44	828	* @param Timing Pointer to NAND timing structure
lypinator	0:bb348c97df44	829	* @param Bank NAND bank number
lypinator	0:bb348c97df44	830	* @retval HAL status
lypinator	0:bb348c97df44	831	*/
lypinator	0:bb348c97df44	832	HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing, uint32_t Bank)
lypinator	0:bb348c97df44	833	{
lypinator	0:bb348c97df44	834	uint32_t tmpr = 0U;
lypinator	0:bb348c97df44	835
lypinator	0:bb348c97df44	836	/* Check the parameters */
lypinator	0:bb348c97df44	837	assert_param(IS_FMC_NAND_DEVICE(Device));
lypinator	0:bb348c97df44	838	assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
lypinator	0:bb348c97df44	839	assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
lypinator	0:bb348c97df44	840	assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
lypinator	0:bb348c97df44	841	assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
lypinator	0:bb348c97df44	842	assert_param(IS_FMC_NAND_BANK(Bank));
lypinator	0:bb348c97df44	843
lypinator	0:bb348c97df44	844	if(Bank == FMC_NAND_BANK2)
lypinator	0:bb348c97df44	845	{
lypinator	0:bb348c97df44	846	/* Get the NAND bank 2 register value */
lypinator	0:bb348c97df44	847	tmpr = Device->PMEM2;
lypinator	0:bb348c97df44	848	}
lypinator	0:bb348c97df44	849	else
lypinator	0:bb348c97df44	850	{
lypinator	0:bb348c97df44	851	/* Get the NAND bank 3 register value */
lypinator	0:bb348c97df44	852	tmpr = Device->PMEM3;
lypinator	0:bb348c97df44	853	}
lypinator	0:bb348c97df44	854
lypinator	0:bb348c97df44	855	/* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */
lypinator	0:bb348c97df44	856	tmpr &= ((uint32_t)~(FMC_PMEM2_MEMSET2 \| FMC_PMEM2_MEMWAIT2 \| FMC_PMEM2_MEMHOLD2 \| \
lypinator	0:bb348c97df44	857	FMC_PMEM2_MEMHIZ2));
lypinator	0:bb348c97df44	858
lypinator	0:bb348c97df44	859	/* Set FMC_NAND device timing parameters */
lypinator	0:bb348c97df44	860	tmpr \|= (uint32_t)(Timing->SetupTime \|\
lypinator	0:bb348c97df44	861	((Timing->WaitSetupTime) << 8U) \|\
lypinator	0:bb348c97df44	862	((Timing->HoldSetupTime) << 16U) \|\
lypinator	0:bb348c97df44	863	((Timing->HiZSetupTime) << 24U)
lypinator	0:bb348c97df44	864	);
lypinator	0:bb348c97df44	865
lypinator	0:bb348c97df44	866	if(Bank == FMC_NAND_BANK2)
lypinator	0:bb348c97df44	867	{
lypinator	0:bb348c97df44	868	/* NAND bank 2 registers configuration */
lypinator	0:bb348c97df44	869	Device->PMEM2 = tmpr;
lypinator	0:bb348c97df44	870	}
lypinator	0:bb348c97df44	871	else
lypinator	0:bb348c97df44	872	{
lypinator	0:bb348c97df44	873	/* NAND bank 3 registers configuration */
lypinator	0:bb348c97df44	874	Device->PMEM3 = tmpr;
lypinator	0:bb348c97df44	875	}
lypinator	0:bb348c97df44	876
lypinator	0:bb348c97df44	877	return HAL_OK;
lypinator	0:bb348c97df44	878	}
lypinator	0:bb348c97df44	879
lypinator	0:bb348c97df44	880	/**
lypinator	0:bb348c97df44	881	* @brief Initializes the FMC_NAND Attribute space Timing according to the specified
lypinator	0:bb348c97df44	882	* parameters in the FMC_NAND_PCC_TimingTypeDef
lypinator	0:bb348c97df44	883	* @param Device Pointer to NAND device instance
lypinator	0:bb348c97df44	884	* @param Timing Pointer to NAND timing structure
lypinator	0:bb348c97df44	885	* @param Bank NAND bank number
lypinator	0:bb348c97df44	886	* @retval HAL status
lypinator	0:bb348c97df44	887	*/
lypinator	0:bb348c97df44	888	HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing, uint32_t Bank)
lypinator	0:bb348c97df44	889	{
lypinator	0:bb348c97df44	890	uint32_t tmpr = 0U;
lypinator	0:bb348c97df44	891
lypinator	0:bb348c97df44	892	/* Check the parameters */
lypinator	0:bb348c97df44	893	assert_param(IS_FMC_NAND_DEVICE(Device));
lypinator	0:bb348c97df44	894	assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
lypinator	0:bb348c97df44	895	assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
lypinator	0:bb348c97df44	896	assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
lypinator	0:bb348c97df44	897	assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
lypinator	0:bb348c97df44	898	assert_param(IS_FMC_NAND_BANK(Bank));
lypinator	0:bb348c97df44	899
lypinator	0:bb348c97df44	900	if(Bank == FMC_NAND_BANK2)
lypinator	0:bb348c97df44	901	{
lypinator	0:bb348c97df44	902	/* Get the NAND bank 2 register value */
lypinator	0:bb348c97df44	903	tmpr = Device->PATT2;
lypinator	0:bb348c97df44	904	}
lypinator	0:bb348c97df44	905	else
lypinator	0:bb348c97df44	906	{
lypinator	0:bb348c97df44	907	/* Get the NAND bank 3 register value */
lypinator	0:bb348c97df44	908	tmpr = Device->PATT3;
lypinator	0:bb348c97df44	909	}
lypinator	0:bb348c97df44	910
lypinator	0:bb348c97df44	911	/* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */
lypinator	0:bb348c97df44	912	tmpr &= ((uint32_t)~(FMC_PATT2_ATTSET2 \| FMC_PATT2_ATTWAIT2 \| FMC_PATT2_ATTHOLD2 \| \
lypinator	0:bb348c97df44	913	FMC_PATT2_ATTHIZ2));
lypinator	0:bb348c97df44	914
lypinator	0:bb348c97df44	915	/* Set FMC_NAND device timing parameters */
lypinator	0:bb348c97df44	916	tmpr \|= (uint32_t)(Timing->SetupTime \|\
lypinator	0:bb348c97df44	917	((Timing->WaitSetupTime) << 8U) \|\
lypinator	0:bb348c97df44	918	((Timing->HoldSetupTime) << 16U) \|\
lypinator	0:bb348c97df44	919	((Timing->HiZSetupTime) << 24U));
lypinator	0:bb348c97df44	920
lypinator	0:bb348c97df44	921	if(Bank == FMC_NAND_BANK2)
lypinator	0:bb348c97df44	922	{
lypinator	0:bb348c97df44	923	/* NAND bank 2 registers configuration */
lypinator	0:bb348c97df44	924	Device->PATT2 = tmpr;
lypinator	0:bb348c97df44	925	}
lypinator	0:bb348c97df44	926	else
lypinator	0:bb348c97df44	927	{
lypinator	0:bb348c97df44	928	/* NAND bank 3 registers configuration */
lypinator	0:bb348c97df44	929	Device->PATT3 = tmpr;
lypinator	0:bb348c97df44	930	}
lypinator	0:bb348c97df44	931
lypinator	0:bb348c97df44	932	return HAL_OK;
lypinator	0:bb348c97df44	933	}
lypinator	0:bb348c97df44	934
lypinator	0:bb348c97df44	935	/**
lypinator	0:bb348c97df44	936	* @brief DeInitializes the FMC_NAND device
lypinator	0:bb348c97df44	937	* @param Device Pointer to NAND device instance
lypinator	0:bb348c97df44	938	* @param Bank NAND bank number
lypinator	0:bb348c97df44	939	* @retval HAL status
lypinator	0:bb348c97df44	940	*/
lypinator	0:bb348c97df44	941	HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank)
lypinator	0:bb348c97df44	942	{
lypinator	0:bb348c97df44	943	/* Check the parameters */
lypinator	0:bb348c97df44	944	assert_param(IS_FMC_NAND_DEVICE(Device));
lypinator	0:bb348c97df44	945	assert_param(IS_FMC_NAND_BANK(Bank));
lypinator	0:bb348c97df44	946
lypinator	0:bb348c97df44	947	/* Disable the NAND Bank */
lypinator	0:bb348c97df44	948	__FMC_NAND_DISABLE(Device, Bank);
lypinator	0:bb348c97df44	949
lypinator	0:bb348c97df44	950	/* De-initialize the NAND Bank */
lypinator	0:bb348c97df44	951	if(Bank == FMC_NAND_BANK2)
lypinator	0:bb348c97df44	952	{
lypinator	0:bb348c97df44	953	/* Set the FMC_NAND_BANK2 registers to their reset values */
lypinator	0:bb348c97df44	954	Device->PCR2 = 0x00000018U;
lypinator	0:bb348c97df44	955	Device->SR2 = 0x00000040U;
lypinator	0:bb348c97df44	956	Device->PMEM2 = 0xFCFCFCFCU;
lypinator	0:bb348c97df44	957	Device->PATT2 = 0xFCFCFCFCU;
lypinator	0:bb348c97df44	958	}
lypinator	0:bb348c97df44	959	/* FMC_Bank3_NAND */
lypinator	0:bb348c97df44	960	else
lypinator	0:bb348c97df44	961	{
lypinator	0:bb348c97df44	962	/* Set the FMC_NAND_BANK3 registers to their reset values */
lypinator	0:bb348c97df44	963	Device->PCR3 = 0x00000018U;
lypinator	0:bb348c97df44	964	Device->SR3 = 0x00000040U;
lypinator	0:bb348c97df44	965	Device->PMEM3 = 0xFCFCFCFCU;
lypinator	0:bb348c97df44	966	Device->PATT3 = 0xFCFCFCFCU;
lypinator	0:bb348c97df44	967	}
lypinator	0:bb348c97df44	968
lypinator	0:bb348c97df44	969	return HAL_OK;
lypinator	0:bb348c97df44	970	}
lypinator	0:bb348c97df44	971
lypinator	0:bb348c97df44	972	/**
lypinator	0:bb348c97df44	973	* @}
lypinator	0:bb348c97df44	974	*/
lypinator	0:bb348c97df44	975
lypinator	0:bb348c97df44	976	/** @addtogroup FMC_LL_NAND_Private_Functions_Group2
lypinator	0:bb348c97df44	977	* @brief management functions
lypinator	0:bb348c97df44	978	*
lypinator	0:bb348c97df44	979	@verbatim
lypinator	0:bb348c97df44	980	==============================================================================
lypinator	0:bb348c97df44	981	##### FMC_NAND Control functions #####
lypinator	0:bb348c97df44	982	==============================================================================
lypinator	0:bb348c97df44	983	[..]
lypinator	0:bb348c97df44	984	This subsection provides a set of functions allowing to control dynamically
lypinator	0:bb348c97df44	985	the FMC NAND interface.
lypinator	0:bb348c97df44	986
lypinator	0:bb348c97df44	987	@endverbatim
lypinator	0:bb348c97df44	988	* @{
lypinator	0:bb348c97df44	989	*/
lypinator	0:bb348c97df44	990	/**
lypinator	0:bb348c97df44	991	* @brief Enables dynamically FMC_NAND ECC feature.
lypinator	0:bb348c97df44	992	* @param Device Pointer to NAND device instance
lypinator	0:bb348c97df44	993	* @param Bank NAND bank number
lypinator	0:bb348c97df44	994	* @retval HAL status
lypinator	0:bb348c97df44	995	*/
lypinator	0:bb348c97df44	996	HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank)
lypinator	0:bb348c97df44	997	{
lypinator	0:bb348c97df44	998	/* Check the parameters */
lypinator	0:bb348c97df44	999	assert_param(IS_FMC_NAND_DEVICE(Device));
lypinator	0:bb348c97df44	1000	assert_param(IS_FMC_NAND_BANK(Bank));
lypinator	0:bb348c97df44	1001
lypinator	0:bb348c97df44	1002	/* Enable ECC feature */
lypinator	0:bb348c97df44	1003	if(Bank == FMC_NAND_BANK2)
lypinator	0:bb348c97df44	1004	{
lypinator	0:bb348c97df44	1005	Device->PCR2 \|= FMC_PCR2_ECCEN;
lypinator	0:bb348c97df44	1006	}
lypinator	0:bb348c97df44	1007	else
lypinator	0:bb348c97df44	1008	{
lypinator	0:bb348c97df44	1009	Device->PCR3 \|= FMC_PCR3_ECCEN;
lypinator	0:bb348c97df44	1010	}
lypinator	0:bb348c97df44	1011
lypinator	0:bb348c97df44	1012	return HAL_OK;
lypinator	0:bb348c97df44	1013	}
lypinator	0:bb348c97df44	1014
lypinator	0:bb348c97df44	1015	/**
lypinator	0:bb348c97df44	1016	* @brief Disables dynamically FMC_NAND ECC feature.
lypinator	0:bb348c97df44	1017	* @param Device Pointer to NAND device instance
lypinator	0:bb348c97df44	1018	* @param Bank NAND bank number
lypinator	0:bb348c97df44	1019	* @retval HAL status
lypinator	0:bb348c97df44	1020	*/
lypinator	0:bb348c97df44	1021	HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank)
lypinator	0:bb348c97df44	1022	{
lypinator	0:bb348c97df44	1023	/* Check the parameters */
lypinator	0:bb348c97df44	1024	assert_param(IS_FMC_NAND_DEVICE(Device));
lypinator	0:bb348c97df44	1025	assert_param(IS_FMC_NAND_BANK(Bank));
lypinator	0:bb348c97df44	1026
lypinator	0:bb348c97df44	1027	/* Disable ECC feature */
lypinator	0:bb348c97df44	1028	if(Bank == FMC_NAND_BANK2)
lypinator	0:bb348c97df44	1029	{
lypinator	0:bb348c97df44	1030	Device->PCR2 &= ~FMC_PCR2_ECCEN;
lypinator	0:bb348c97df44	1031	}
lypinator	0:bb348c97df44	1032	else
lypinator	0:bb348c97df44	1033	{
lypinator	0:bb348c97df44	1034	Device->PCR3 &= ~FMC_PCR3_ECCEN;
lypinator	0:bb348c97df44	1035	}
lypinator	0:bb348c97df44	1036
lypinator	0:bb348c97df44	1037	return HAL_OK;
lypinator	0:bb348c97df44	1038	}
lypinator	0:bb348c97df44	1039
lypinator	0:bb348c97df44	1040	/**
lypinator	0:bb348c97df44	1041	* @brief Disables dynamically FMC_NAND ECC feature.
lypinator	0:bb348c97df44	1042	* @param Device Pointer to NAND device instance
lypinator	0:bb348c97df44	1043	* @param ECCval Pointer to ECC value
lypinator	0:bb348c97df44	1044	* @param Bank NAND bank number
lypinator	0:bb348c97df44	1045	* @param Timeout Timeout wait value
lypinator	0:bb348c97df44	1046	* @retval HAL status
lypinator	0:bb348c97df44	1047	*/
lypinator	0:bb348c97df44	1048	HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef Device, uint32_t ECCval, uint32_t Bank, uint32_t Timeout)
lypinator	0:bb348c97df44	1049	{
lypinator	0:bb348c97df44	1050	uint32_t tickstart = 0U;
lypinator	0:bb348c97df44	1051
lypinator	0:bb348c97df44	1052	/* Check the parameters */
lypinator	0:bb348c97df44	1053	assert_param(IS_FMC_NAND_DEVICE(Device));
lypinator	0:bb348c97df44	1054	assert_param(IS_FMC_NAND_BANK(Bank));
lypinator	0:bb348c97df44	1055
lypinator	0:bb348c97df44	1056	/* Get tick */
lypinator	0:bb348c97df44	1057	tickstart = HAL_GetTick();
lypinator	0:bb348c97df44	1058
lypinator	0:bb348c97df44	1059	/* Wait until FIFO is empty */
lypinator	0:bb348c97df44	1060	while(__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT) == RESET)
lypinator	0:bb348c97df44	1061	{
lypinator	0:bb348c97df44	1062	/* Check for the Timeout */
lypinator	0:bb348c97df44	1063	if(Timeout != HAL_MAX_DELAY)
lypinator	0:bb348c97df44	1064	{
lypinator	0:bb348c97df44	1065	if((Timeout == 0U)\|\|((HAL_GetTick() - tickstart ) > Timeout))
lypinator	0:bb348c97df44	1066	{
lypinator	0:bb348c97df44	1067	return HAL_TIMEOUT;
lypinator	0:bb348c97df44	1068	}
lypinator	0:bb348c97df44	1069	}
lypinator	0:bb348c97df44	1070	}
lypinator	0:bb348c97df44	1071
lypinator	0:bb348c97df44	1072	if(Bank == FMC_NAND_BANK2)
lypinator	0:bb348c97df44	1073	{
lypinator	0:bb348c97df44	1074	/* Get the ECCR2 register value */
lypinator	0:bb348c97df44	1075	*ECCval = (uint32_t)Device->ECCR2;
lypinator	0:bb348c97df44	1076	}
lypinator	0:bb348c97df44	1077	else
lypinator	0:bb348c97df44	1078	{
lypinator	0:bb348c97df44	1079	/* Get the ECCR3 register value */
lypinator	0:bb348c97df44	1080	*ECCval = (uint32_t)Device->ECCR3;
lypinator	0:bb348c97df44	1081	}
lypinator	0:bb348c97df44	1082
lypinator	0:bb348c97df44	1083	return HAL_OK;
lypinator	0:bb348c97df44	1084	}
lypinator	0:bb348c97df44	1085
lypinator	0:bb348c97df44	1086	/**
lypinator	0:bb348c97df44	1087	* @}
lypinator	0:bb348c97df44	1088	*/
lypinator	0:bb348c97df44	1089
lypinator	0:bb348c97df44	1090	#endif /* defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx) */
lypinator	0:bb348c97df44	1091	/**
lypinator	0:bb348c97df44	1092	* @}
lypinator	0:bb348c97df44	1093	*/
lypinator	0:bb348c97df44	1094
lypinator	0:bb348c97df44	1095	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
lypinator	0:bb348c97df44	1096	/** @addtogroup FMC_LL_PCCARD
lypinator	0:bb348c97df44	1097	* @brief PCCARD Controller functions
lypinator	0:bb348c97df44	1098	*
lypinator	0:bb348c97df44	1099	@verbatim
lypinator	0:bb348c97df44	1100	==============================================================================
lypinator	0:bb348c97df44	1101	##### How to use PCCARD device driver #####
lypinator	0:bb348c97df44	1102	==============================================================================
lypinator	0:bb348c97df44	1103	[..]
lypinator	0:bb348c97df44	1104	This driver contains a set of APIs to interface with the FMC PCCARD bank in order
lypinator	0:bb348c97df44	1105	to run the PCCARD/compact flash external devices.
lypinator	0:bb348c97df44	1106
lypinator	0:bb348c97df44	1107	(+) FMC PCCARD bank reset using the function FMC_PCCARD_DeInit()
lypinator	0:bb348c97df44	1108	(+) FMC PCCARD bank control configuration using the function FMC_PCCARD_Init()
lypinator	0:bb348c97df44	1109	(+) FMC PCCARD bank common space timing configuration using the function
lypinator	0:bb348c97df44	1110	FMC_PCCARD_CommonSpace_Timing_Init()
lypinator	0:bb348c97df44	1111	(+) FMC PCCARD bank attribute space timing configuration using the function
lypinator	0:bb348c97df44	1112	FMC_PCCARD_AttributeSpace_Timing_Init()
lypinator	0:bb348c97df44	1113	(+) FMC PCCARD bank IO space timing configuration using the function
lypinator	0:bb348c97df44	1114	FMC_PCCARD_IOSpace_Timing_Init()
lypinator	0:bb348c97df44	1115	@endverbatim
lypinator	0:bb348c97df44	1116	* @{
lypinator	0:bb348c97df44	1117	*/
lypinator	0:bb348c97df44	1118
lypinator	0:bb348c97df44	1119	/** @addtogroup FMC_LL_PCCARD_Private_Functions_Group1
lypinator	0:bb348c97df44	1120	* @brief Initialization and Configuration functions
lypinator	0:bb348c97df44	1121	*
lypinator	0:bb348c97df44	1122	@verbatim
lypinator	0:bb348c97df44	1123	==============================================================================
lypinator	0:bb348c97df44	1124	##### Initialization and de_initialization functions #####
lypinator	0:bb348c97df44	1125	==============================================================================
lypinator	0:bb348c97df44	1126	[..]
lypinator	0:bb348c97df44	1127	This section provides functions allowing to:
lypinator	0:bb348c97df44	1128	(+) Initialize and configure the FMC PCCARD interface
lypinator	0:bb348c97df44	1129	(+) De-initialize the FMC PCCARD interface
lypinator	0:bb348c97df44	1130	(+) Configure the FMC clock and associated GPIOs
lypinator	0:bb348c97df44	1131
lypinator	0:bb348c97df44	1132	@endverbatim
lypinator	0:bb348c97df44	1133	* @{
lypinator	0:bb348c97df44	1134	*/
lypinator	0:bb348c97df44	1135
lypinator	0:bb348c97df44	1136	/**
lypinator	0:bb348c97df44	1137	* @brief Initializes the FMC_PCCARD device according to the specified
lypinator	0:bb348c97df44	1138	* control parameters in the FMC_PCCARD_HandleTypeDef
lypinator	0:bb348c97df44	1139	* @param Device Pointer to PCCARD device instance
lypinator	0:bb348c97df44	1140	* @param Init Pointer to PCCARD Initialization structure
lypinator	0:bb348c97df44	1141	* @retval HAL status
lypinator	0:bb348c97df44	1142	*/
lypinator	0:bb348c97df44	1143	HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef Device, FMC_PCCARD_InitTypeDef Init)
lypinator	0:bb348c97df44	1144	{
lypinator	0:bb348c97df44	1145	uint32_t tmpr = 0U;
lypinator	0:bb348c97df44	1146
lypinator	0:bb348c97df44	1147	/* Check the parameters */
lypinator	0:bb348c97df44	1148	assert_param(IS_FMC_PCCARD_DEVICE(Device));
lypinator	0:bb348c97df44	1149	assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature));
lypinator	0:bb348c97df44	1150	assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime));
lypinator	0:bb348c97df44	1151	assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime));
lypinator	0:bb348c97df44	1152
lypinator	0:bb348c97df44	1153	/* Get PCCARD control register value */
lypinator	0:bb348c97df44	1154	tmpr = Device->PCR4;
lypinator	0:bb348c97df44	1155
lypinator	0:bb348c97df44	1156	/* Clear TAR, TCLR, PWAITEN and PWID bits */
lypinator	0:bb348c97df44	1157	tmpr &= ((uint32_t)~(FMC_PCR4_TAR \| FMC_PCR4_TCLR \| FMC_PCR4_PWAITEN \| \
lypinator	0:bb348c97df44	1158	FMC_PCR4_PWID \| FMC_PCR4_PTYP));
lypinator	0:bb348c97df44	1159
lypinator	0:bb348c97df44	1160	/* Set FMC_PCCARD device control parameters */
lypinator	0:bb348c97df44	1161	tmpr \|= (uint32_t)(Init->Waitfeature \|\
lypinator	0:bb348c97df44	1162	FMC_NAND_PCC_MEM_BUS_WIDTH_16 \|\
lypinator	0:bb348c97df44	1163	(Init->TCLRSetupTime << 9U) \|\
lypinator	0:bb348c97df44	1164	(Init->TARSetupTime << 13U));
lypinator	0:bb348c97df44	1165
lypinator	0:bb348c97df44	1166	Device->PCR4 = tmpr;
lypinator	0:bb348c97df44	1167
lypinator	0:bb348c97df44	1168	return HAL_OK;
lypinator	0:bb348c97df44	1169	}
lypinator	0:bb348c97df44	1170
lypinator	0:bb348c97df44	1171	/**
lypinator	0:bb348c97df44	1172	* @brief Initializes the FMC_PCCARD Common space Timing according to the specified
lypinator	0:bb348c97df44	1173	* parameters in the FMC_NAND_PCC_TimingTypeDef
lypinator	0:bb348c97df44	1174	* @param Device Pointer to PCCARD device instance
lypinator	0:bb348c97df44	1175	* @param Timing Pointer to PCCARD timing structure
lypinator	0:bb348c97df44	1176	* @retval HAL status
lypinator	0:bb348c97df44	1177	*/
lypinator	0:bb348c97df44	1178	HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing)
lypinator	0:bb348c97df44	1179	{
lypinator	0:bb348c97df44	1180	uint32_t tmpr = 0U;
lypinator	0:bb348c97df44	1181
lypinator	0:bb348c97df44	1182	/* Check the parameters */
lypinator	0:bb348c97df44	1183	assert_param(IS_FMC_PCCARD_DEVICE(Device));
lypinator	0:bb348c97df44	1184	assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
lypinator	0:bb348c97df44	1185	assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
lypinator	0:bb348c97df44	1186	assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
lypinator	0:bb348c97df44	1187	assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
lypinator	0:bb348c97df44	1188
lypinator	0:bb348c97df44	1189	/* Get PCCARD common space timing register value */
lypinator	0:bb348c97df44	1190	tmpr = Device->PMEM4;
lypinator	0:bb348c97df44	1191
lypinator	0:bb348c97df44	1192	/* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */
lypinator	0:bb348c97df44	1193	tmpr &= ((uint32_t)~(FMC_PMEM4_MEMSET4 \| FMC_PMEM4_MEMWAIT4 \| FMC_PMEM4_MEMHOLD4 \| \
lypinator	0:bb348c97df44	1194	FMC_PMEM4_MEMHIZ4));
lypinator	0:bb348c97df44	1195	/* Set PCCARD timing parameters */
lypinator	0:bb348c97df44	1196	tmpr \|= (uint32_t)(Timing->SetupTime \|\
lypinator	0:bb348c97df44	1197	((Timing->WaitSetupTime) << 8U) \|\
lypinator	0:bb348c97df44	1198	((Timing->HoldSetupTime) << 16U) \|\
lypinator	0:bb348c97df44	1199	((Timing->HiZSetupTime) << 24U));
lypinator	0:bb348c97df44	1200
lypinator	0:bb348c97df44	1201	Device->PMEM4 = tmpr;
lypinator	0:bb348c97df44	1202
lypinator	0:bb348c97df44	1203	return HAL_OK;
lypinator	0:bb348c97df44	1204	}
lypinator	0:bb348c97df44	1205
lypinator	0:bb348c97df44	1206	/**
lypinator	0:bb348c97df44	1207	* @brief Initializes the FMC_PCCARD Attribute space Timing according to the specified
lypinator	0:bb348c97df44	1208	* parameters in the FMC_NAND_PCC_TimingTypeDef
lypinator	0:bb348c97df44	1209	* @param Device Pointer to PCCARD device instance
lypinator	0:bb348c97df44	1210	* @param Timing Pointer to PCCARD timing structure
lypinator	0:bb348c97df44	1211	* @retval HAL status
lypinator	0:bb348c97df44	1212	*/
lypinator	0:bb348c97df44	1213	HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing)
lypinator	0:bb348c97df44	1214	{
lypinator	0:bb348c97df44	1215	uint32_t tmpr = 0U;
lypinator	0:bb348c97df44	1216
lypinator	0:bb348c97df44	1217	/* Check the parameters */
lypinator	0:bb348c97df44	1218	assert_param(IS_FMC_PCCARD_DEVICE(Device));
lypinator	0:bb348c97df44	1219	assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
lypinator	0:bb348c97df44	1220	assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
lypinator	0:bb348c97df44	1221	assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
lypinator	0:bb348c97df44	1222	assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
lypinator	0:bb348c97df44	1223
lypinator	0:bb348c97df44	1224	/* Get PCCARD timing parameters */
lypinator	0:bb348c97df44	1225	tmpr = Device->PATT4;
lypinator	0:bb348c97df44	1226
lypinator	0:bb348c97df44	1227	/* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */
lypinator	0:bb348c97df44	1228	tmpr &= ((uint32_t)~(FMC_PATT4_ATTSET4 \| FMC_PATT4_ATTWAIT4 \| FMC_PATT4_ATTHOLD4 \| \
lypinator	0:bb348c97df44	1229	FMC_PATT4_ATTHIZ4));
lypinator	0:bb348c97df44	1230
lypinator	0:bb348c97df44	1231	/* Set PCCARD timing parameters */
lypinator	0:bb348c97df44	1232	tmpr \|= (uint32_t)(Timing->SetupTime \|\
lypinator	0:bb348c97df44	1233	((Timing->WaitSetupTime) << 8U) \|\
lypinator	0:bb348c97df44	1234	((Timing->HoldSetupTime) << 16U) \|\
lypinator	0:bb348c97df44	1235	((Timing->HiZSetupTime) << 24U));
lypinator	0:bb348c97df44	1236	Device->PATT4 = tmpr;
lypinator	0:bb348c97df44	1237
lypinator	0:bb348c97df44	1238	return HAL_OK;
lypinator	0:bb348c97df44	1239	}
lypinator	0:bb348c97df44	1240
lypinator	0:bb348c97df44	1241	/**
lypinator	0:bb348c97df44	1242	* @brief Initializes the FMC_PCCARD IO space Timing according to the specified
lypinator	0:bb348c97df44	1243	* parameters in the FMC_NAND_PCC_TimingTypeDef
lypinator	0:bb348c97df44	1244	* @param Device Pointer to PCCARD device instance
lypinator	0:bb348c97df44	1245	* @param Timing Pointer to PCCARD timing structure
lypinator	0:bb348c97df44	1246	* @retval HAL status
lypinator	0:bb348c97df44	1247	*/
lypinator	0:bb348c97df44	1248	HAL_StatusTypeDef FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing)
lypinator	0:bb348c97df44	1249	{
lypinator	0:bb348c97df44	1250	uint32_t tmpr = 0;
lypinator	0:bb348c97df44	1251
lypinator	0:bb348c97df44	1252	/* Check the parameters */
lypinator	0:bb348c97df44	1253	assert_param(IS_FMC_PCCARD_DEVICE(Device));
lypinator	0:bb348c97df44	1254	assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
lypinator	0:bb348c97df44	1255	assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
lypinator	0:bb348c97df44	1256	assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
lypinator	0:bb348c97df44	1257	assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
lypinator	0:bb348c97df44	1258
lypinator	0:bb348c97df44	1259	/* Get FMC_PCCARD device timing parameters */
lypinator	0:bb348c97df44	1260	tmpr = Device->PIO4;
lypinator	0:bb348c97df44	1261
lypinator	0:bb348c97df44	1262	/* Clear IOSET4, IOWAIT4, IOHOLD4 and IOHIZ4 bits */
lypinator	0:bb348c97df44	1263	tmpr &= ((uint32_t)~(FMC_PIO4_IOSET4 \| FMC_PIO4_IOWAIT4 \| FMC_PIO4_IOHOLD4 \| \
lypinator	0:bb348c97df44	1264	FMC_PIO4_IOHIZ4));
lypinator	0:bb348c97df44	1265
lypinator	0:bb348c97df44	1266	/* Set FMC_PCCARD device timing parameters */
lypinator	0:bb348c97df44	1267	tmpr \|= (uint32_t)(Timing->SetupTime \|\
lypinator	0:bb348c97df44	1268	((Timing->WaitSetupTime) << 8U) \|\
lypinator	0:bb348c97df44	1269	((Timing->HoldSetupTime) << 16U) \|\
lypinator	0:bb348c97df44	1270	((Timing->HiZSetupTime) << 24U));
lypinator	0:bb348c97df44	1271
lypinator	0:bb348c97df44	1272	Device->PIO4 = tmpr;
lypinator	0:bb348c97df44	1273
lypinator	0:bb348c97df44	1274	return HAL_OK;
lypinator	0:bb348c97df44	1275	}
lypinator	0:bb348c97df44	1276
lypinator	0:bb348c97df44	1277	/**
lypinator	0:bb348c97df44	1278	* @brief DeInitializes the FMC_PCCARD device
lypinator	0:bb348c97df44	1279	* @param Device Pointer to PCCARD device instance
lypinator	0:bb348c97df44	1280	* @retval HAL status
lypinator	0:bb348c97df44	1281	*/
lypinator	0:bb348c97df44	1282	HAL_StatusTypeDef FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device)
lypinator	0:bb348c97df44	1283	{
lypinator	0:bb348c97df44	1284	/* Check the parameters */
lypinator	0:bb348c97df44	1285	assert_param(IS_FMC_PCCARD_DEVICE(Device));
lypinator	0:bb348c97df44	1286
lypinator	0:bb348c97df44	1287	/* Disable the FMC_PCCARD device */
lypinator	0:bb348c97df44	1288	__FMC_PCCARD_DISABLE(Device);
lypinator	0:bb348c97df44	1289
lypinator	0:bb348c97df44	1290	/* De-initialize the FMC_PCCARD device */
lypinator	0:bb348c97df44	1291	Device->PCR4 = 0x00000018U;
lypinator	0:bb348c97df44	1292	Device->SR4 = 0x00000000U;
lypinator	0:bb348c97df44	1293	Device->PMEM4 = 0xFCFCFCFCU;
lypinator	0:bb348c97df44	1294	Device->PATT4 = 0xFCFCFCFCU;
lypinator	0:bb348c97df44	1295	Device->PIO4 = 0xFCFCFCFCU;
lypinator	0:bb348c97df44	1296
lypinator	0:bb348c97df44	1297	return HAL_OK;
lypinator	0:bb348c97df44	1298	}
lypinator	0:bb348c97df44	1299
lypinator	0:bb348c97df44	1300	/**
lypinator	0:bb348c97df44	1301	* @}
lypinator	0:bb348c97df44	1302	*/
lypinator	0:bb348c97df44	1303	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
lypinator	0:bb348c97df44	1304
lypinator	0:bb348c97df44	1305
lypinator	0:bb348c97df44	1306	/** @addtogroup FMC_LL_SDRAM
lypinator	0:bb348c97df44	1307	* @brief SDRAM Controller functions
lypinator	0:bb348c97df44	1308	*
lypinator	0:bb348c97df44	1309	@verbatim
lypinator	0:bb348c97df44	1310	==============================================================================
lypinator	0:bb348c97df44	1311	##### How to use SDRAM device driver #####
lypinator	0:bb348c97df44	1312	==============================================================================
lypinator	0:bb348c97df44	1313	[..]
lypinator	0:bb348c97df44	1314	This driver contains a set of APIs to interface with the FMC SDRAM banks in order
lypinator	0:bb348c97df44	1315	to run the SDRAM external devices.
lypinator	0:bb348c97df44	1316
lypinator	0:bb348c97df44	1317	(+) FMC SDRAM bank reset using the function FMC_SDRAM_DeInit()
lypinator	0:bb348c97df44	1318	(+) FMC SDRAM bank control configuration using the function FMC_SDRAM_Init()
lypinator	0:bb348c97df44	1319	(+) FMC SDRAM bank timing configuration using the function FMC_SDRAM_Timing_Init()
lypinator	0:bb348c97df44	1320	(+) FMC SDRAM bank enable/disable write operation using the functions
lypinator	0:bb348c97df44	1321	FMC_SDRAM_WriteOperation_Enable()/FMC_SDRAM_WriteOperation_Disable()
lypinator	0:bb348c97df44	1322	(+) FMC SDRAM bank send command using the function FMC_SDRAM_SendCommand()
lypinator	0:bb348c97df44	1323
lypinator	0:bb348c97df44	1324	@endverbatim
lypinator	0:bb348c97df44	1325	* @{
lypinator	0:bb348c97df44	1326	*/
lypinator	0:bb348c97df44	1327
lypinator	0:bb348c97df44	1328	/** @addtogroup FMC_LL_SDRAM_Private_Functions_Group1
lypinator	0:bb348c97df44	1329	* @brief Initialization and Configuration functions
lypinator	0:bb348c97df44	1330	*
lypinator	0:bb348c97df44	1331	@verbatim
lypinator	0:bb348c97df44	1332	==============================================================================
lypinator	0:bb348c97df44	1333	##### Initialization and de_initialization functions #####
lypinator	0:bb348c97df44	1334	==============================================================================
lypinator	0:bb348c97df44	1335	[..]
lypinator	0:bb348c97df44	1336	This section provides functions allowing to:
lypinator	0:bb348c97df44	1337	(+) Initialize and configure the FMC SDRAM interface
lypinator	0:bb348c97df44	1338	(+) De-initialize the FMC SDRAM interface
lypinator	0:bb348c97df44	1339	(+) Configure the FMC clock and associated GPIOs
lypinator	0:bb348c97df44	1340
lypinator	0:bb348c97df44	1341	@endverbatim
lypinator	0:bb348c97df44	1342	* @{
lypinator	0:bb348c97df44	1343	*/
lypinator	0:bb348c97df44	1344
lypinator	0:bb348c97df44	1345	/**
lypinator	0:bb348c97df44	1346	* @brief Initializes the FMC_SDRAM device according to the specified
lypinator	0:bb348c97df44	1347	* control parameters in the FMC_SDRAM_InitTypeDef
lypinator	0:bb348c97df44	1348	* @param Device Pointer to SDRAM device instance
lypinator	0:bb348c97df44	1349	* @param Init Pointer to SDRAM Initialization structure
lypinator	0:bb348c97df44	1350	* @retval HAL status
lypinator	0:bb348c97df44	1351	*/
lypinator	0:bb348c97df44	1352	HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef Device, FMC_SDRAM_InitTypeDef Init)
lypinator	0:bb348c97df44	1353	{
lypinator	0:bb348c97df44	1354	uint32_t tmpr1 = 0U;
lypinator	0:bb348c97df44	1355	uint32_t tmpr2 = 0U;
lypinator	0:bb348c97df44	1356
lypinator	0:bb348c97df44	1357	/* Check the parameters */
lypinator	0:bb348c97df44	1358	assert_param(IS_FMC_SDRAM_DEVICE(Device));
lypinator	0:bb348c97df44	1359	assert_param(IS_FMC_SDRAM_BANK(Init->SDBank));
lypinator	0:bb348c97df44	1360	assert_param(IS_FMC_COLUMNBITS_NUMBER(Init->ColumnBitsNumber));
lypinator	0:bb348c97df44	1361	assert_param(IS_FMC_ROWBITS_NUMBER(Init->RowBitsNumber));
lypinator	0:bb348c97df44	1362	assert_param(IS_FMC_SDMEMORY_WIDTH(Init->MemoryDataWidth));
lypinator	0:bb348c97df44	1363	assert_param(IS_FMC_INTERNALBANK_NUMBER(Init->InternalBankNumber));
lypinator	0:bb348c97df44	1364	assert_param(IS_FMC_CAS_LATENCY(Init->CASLatency));
lypinator	0:bb348c97df44	1365	assert_param(IS_FMC_WRITE_PROTECTION(Init->WriteProtection));
lypinator	0:bb348c97df44	1366	assert_param(IS_FMC_SDCLOCK_PERIOD(Init->SDClockPeriod));
lypinator	0:bb348c97df44	1367	assert_param(IS_FMC_READ_BURST(Init->ReadBurst));
lypinator	0:bb348c97df44	1368	assert_param(IS_FMC_READPIPE_DELAY(Init->ReadPipeDelay));
lypinator	0:bb348c97df44	1369
lypinator	0:bb348c97df44	1370	/* Set SDRAM bank configuration parameters */
lypinator	0:bb348c97df44	1371	if (Init->SDBank != FMC_SDRAM_BANK2)
lypinator	0:bb348c97df44	1372	{
lypinator	0:bb348c97df44	1373	tmpr1 = Device->SDCR[FMC_SDRAM_BANK1];
lypinator	0:bb348c97df44	1374
lypinator	0:bb348c97df44	1375	/* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */
lypinator	0:bb348c97df44	1376	tmpr1 &= ((uint32_t)~(FMC_SDCR1_NC \| FMC_SDCR1_NR \| FMC_SDCR1_MWID \| \
lypinator	0:bb348c97df44	1377	FMC_SDCR1_NB \| FMC_SDCR1_CAS \| FMC_SDCR1_WP \| \
lypinator	0:bb348c97df44	1378	FMC_SDCR1_SDCLK \| FMC_SDCR1_RBURST \| FMC_SDCR1_RPIPE));
lypinator	0:bb348c97df44	1379
lypinator	0:bb348c97df44	1380
lypinator	0:bb348c97df44	1381	tmpr1 \|= (uint32_t)(Init->ColumnBitsNumber \|\
lypinator	0:bb348c97df44	1382	Init->RowBitsNumber \|\
lypinator	0:bb348c97df44	1383	Init->MemoryDataWidth \|\
lypinator	0:bb348c97df44	1384	Init->InternalBankNumber \|\
lypinator	0:bb348c97df44	1385	Init->CASLatency \|\
lypinator	0:bb348c97df44	1386	Init->WriteProtection \|\
lypinator	0:bb348c97df44	1387	Init->SDClockPeriod \|\
lypinator	0:bb348c97df44	1388	Init->ReadBurst \|\
lypinator	0:bb348c97df44	1389	Init->ReadPipeDelay
lypinator	0:bb348c97df44	1390	);
lypinator	0:bb348c97df44	1391	Device->SDCR[FMC_SDRAM_BANK1] = tmpr1;
lypinator	0:bb348c97df44	1392	}
lypinator	0:bb348c97df44	1393	else /* FMC_Bank2_SDRAM */
lypinator	0:bb348c97df44	1394	{
lypinator	0:bb348c97df44	1395	tmpr1 = Device->SDCR[FMC_SDRAM_BANK1];
lypinator	0:bb348c97df44	1396
lypinator	0:bb348c97df44	1397	/* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */
lypinator	0:bb348c97df44	1398	tmpr1 &= ((uint32_t)~(FMC_SDCR1_SDCLK \| FMC_SDCR1_RBURST \| FMC_SDCR1_RPIPE));
lypinator	0:bb348c97df44	1399
lypinator	0:bb348c97df44	1400	tmpr1 \|= (uint32_t)(Init->SDClockPeriod \|\
lypinator	0:bb348c97df44	1401	Init->ReadBurst \|\
lypinator	0:bb348c97df44	1402	Init->ReadPipeDelay);
lypinator	0:bb348c97df44	1403
lypinator	0:bb348c97df44	1404	tmpr2 = Device->SDCR[FMC_SDRAM_BANK2];
lypinator	0:bb348c97df44	1405
lypinator	0:bb348c97df44	1406	/* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */
lypinator	0:bb348c97df44	1407	tmpr2 &= ((uint32_t)~(FMC_SDCR1_NC \| FMC_SDCR1_NR \| FMC_SDCR1_MWID \| \
lypinator	0:bb348c97df44	1408	FMC_SDCR1_NB \| FMC_SDCR1_CAS \| FMC_SDCR1_WP \| \
lypinator	0:bb348c97df44	1409	FMC_SDCR1_SDCLK \| FMC_SDCR1_RBURST \| FMC_SDCR1_RPIPE));
lypinator	0:bb348c97df44	1410
lypinator	0:bb348c97df44	1411	tmpr2 \|= (uint32_t)(Init->ColumnBitsNumber \|\
lypinator	0:bb348c97df44	1412	Init->RowBitsNumber \|\
lypinator	0:bb348c97df44	1413	Init->MemoryDataWidth \|\
lypinator	0:bb348c97df44	1414	Init->InternalBankNumber \|\
lypinator	0:bb348c97df44	1415	Init->CASLatency \|\
lypinator	0:bb348c97df44	1416	Init->WriteProtection);
lypinator	0:bb348c97df44	1417
lypinator	0:bb348c97df44	1418	Device->SDCR[FMC_SDRAM_BANK1] = tmpr1;
lypinator	0:bb348c97df44	1419	Device->SDCR[FMC_SDRAM_BANK2] = tmpr2;
lypinator	0:bb348c97df44	1420	}
lypinator	0:bb348c97df44	1421
lypinator	0:bb348c97df44	1422	return HAL_OK;
lypinator	0:bb348c97df44	1423	}
lypinator	0:bb348c97df44	1424
lypinator	0:bb348c97df44	1425	/**
lypinator	0:bb348c97df44	1426	* @brief Initializes the FMC_SDRAM device timing according to the specified
lypinator	0:bb348c97df44	1427	* parameters in the FMC_SDRAM_TimingTypeDef
lypinator	0:bb348c97df44	1428	* @param Device Pointer to SDRAM device instance
lypinator	0:bb348c97df44	1429	* @param Timing Pointer to SDRAM Timing structure
lypinator	0:bb348c97df44	1430	* @param Bank SDRAM bank number
lypinator	0:bb348c97df44	1431	* @retval HAL status
lypinator	0:bb348c97df44	1432	*/
lypinator	0:bb348c97df44	1433	HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef Device, FMC_SDRAM_TimingTypeDef Timing, uint32_t Bank)
lypinator	0:bb348c97df44	1434	{
lypinator	0:bb348c97df44	1435	uint32_t tmpr1 = 0U;
lypinator	0:bb348c97df44	1436	uint32_t tmpr2 = 0U;
lypinator	0:bb348c97df44	1437
lypinator	0:bb348c97df44	1438	/* Check the parameters */
lypinator	0:bb348c97df44	1439	assert_param(IS_FMC_SDRAM_DEVICE(Device));
lypinator	0:bb348c97df44	1440	assert_param(IS_FMC_LOADTOACTIVE_DELAY(Timing->LoadToActiveDelay));
lypinator	0:bb348c97df44	1441	assert_param(IS_FMC_EXITSELFREFRESH_DELAY(Timing->ExitSelfRefreshDelay));
lypinator	0:bb348c97df44	1442	assert_param(IS_FMC_SELFREFRESH_TIME(Timing->SelfRefreshTime));
lypinator	0:bb348c97df44	1443	assert_param(IS_FMC_ROWCYCLE_DELAY(Timing->RowCycleDelay));
lypinator	0:bb348c97df44	1444	assert_param(IS_FMC_WRITE_RECOVERY_TIME(Timing->WriteRecoveryTime));
lypinator	0:bb348c97df44	1445	assert_param(IS_FMC_RP_DELAY(Timing->RPDelay));
lypinator	0:bb348c97df44	1446	assert_param(IS_FMC_RCD_DELAY(Timing->RCDDelay));
lypinator	0:bb348c97df44	1447	assert_param(IS_FMC_SDRAM_BANK(Bank));
lypinator	0:bb348c97df44	1448
lypinator	0:bb348c97df44	1449	/* Set SDRAM device timing parameters */
lypinator	0:bb348c97df44	1450	if (Bank != FMC_SDRAM_BANK2)
lypinator	0:bb348c97df44	1451	{
lypinator	0:bb348c97df44	1452	tmpr1 = Device->SDTR[FMC_SDRAM_BANK1];
lypinator	0:bb348c97df44	1453
lypinator	0:bb348c97df44	1454	/* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */
lypinator	0:bb348c97df44	1455	tmpr1 &= ((uint32_t)~(FMC_SDTR1_TMRD \| FMC_SDTR1_TXSR \| FMC_SDTR1_TRAS \| \
lypinator	0:bb348c97df44	1456	FMC_SDTR1_TRC \| FMC_SDTR1_TWR \| FMC_SDTR1_TRP \| \
lypinator	0:bb348c97df44	1457	FMC_SDTR1_TRCD));
lypinator	0:bb348c97df44	1458
lypinator	0:bb348c97df44	1459	tmpr1 \|= (uint32_t)(((Timing->LoadToActiveDelay)-1U) \|\
lypinator	0:bb348c97df44	1460	(((Timing->ExitSelfRefreshDelay)-1U) << 4U) \|\
lypinator	0:bb348c97df44	1461	(((Timing->SelfRefreshTime)-1U) << 8U) \|\
lypinator	0:bb348c97df44	1462	(((Timing->RowCycleDelay)-1U) << 12U) \|\
lypinator	0:bb348c97df44	1463	(((Timing->WriteRecoveryTime)-1U) <<16U) \|\
lypinator	0:bb348c97df44	1464	(((Timing->RPDelay)-1U) << 20U) \|\
lypinator	0:bb348c97df44	1465	(((Timing->RCDDelay)-1U) << 24U));
lypinator	0:bb348c97df44	1466	Device->SDTR[FMC_SDRAM_BANK1] = tmpr1;
lypinator	0:bb348c97df44	1467	}
lypinator	0:bb348c97df44	1468	else /* FMC_Bank2_SDRAM */
lypinator	0:bb348c97df44	1469	{
lypinator	0:bb348c97df44	1470	tmpr1 = Device->SDTR[FMC_SDRAM_BANK1];
lypinator	0:bb348c97df44	1471
lypinator	0:bb348c97df44	1472	/* Clear TRC and TRP bits */
lypinator	0:bb348c97df44	1473	tmpr1 &= ((uint32_t)~(FMC_SDTR1_TRC \| FMC_SDTR1_TRP));
lypinator	0:bb348c97df44	1474
lypinator	0:bb348c97df44	1475	tmpr1 \|= (uint32_t)((((Timing->RowCycleDelay)-1U) << 12U) \|\
lypinator	0:bb348c97df44	1476	(((Timing->RPDelay)-1U) << 20U));
lypinator	0:bb348c97df44	1477
lypinator	0:bb348c97df44	1478	tmpr2 = Device->SDTR[FMC_SDRAM_BANK2];
lypinator	0:bb348c97df44	1479
lypinator	0:bb348c97df44	1480	/* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */
lypinator	0:bb348c97df44	1481	tmpr2 &= ((uint32_t)~(FMC_SDTR1_TMRD \| FMC_SDTR1_TXSR \| FMC_SDTR1_TRAS \| \
lypinator	0:bb348c97df44	1482	FMC_SDTR1_TRC \| FMC_SDTR1_TWR \| FMC_SDTR1_TRP \| \
lypinator	0:bb348c97df44	1483	FMC_SDTR1_TRCD));
lypinator	0:bb348c97df44	1484
lypinator	0:bb348c97df44	1485	tmpr2 \|= (uint32_t)((((Timing->LoadToActiveDelay)-1U) \|\
lypinator	0:bb348c97df44	1486	(((Timing->ExitSelfRefreshDelay)-1U) << 4U) \|\
lypinator	0:bb348c97df44	1487	(((Timing->SelfRefreshTime)-1U) << 8U) \|\
lypinator	0:bb348c97df44	1488	(((Timing->WriteRecoveryTime)-1U) <<16U) \|\
lypinator	0:bb348c97df44	1489	(((Timing->RCDDelay)-1U) << 24U)));
lypinator	0:bb348c97df44	1490
lypinator	0:bb348c97df44	1491	Device->SDTR[FMC_SDRAM_BANK1] = tmpr1;
lypinator	0:bb348c97df44	1492	Device->SDTR[FMC_SDRAM_BANK2] = tmpr2;
lypinator	0:bb348c97df44	1493	}
lypinator	0:bb348c97df44	1494	return HAL_OK;
lypinator	0:bb348c97df44	1495	}
lypinator	0:bb348c97df44	1496
lypinator	0:bb348c97df44	1497	/**
lypinator	0:bb348c97df44	1498	* @brief DeInitializes the FMC_SDRAM peripheral
lypinator	0:bb348c97df44	1499	* @param Device Pointer to SDRAM device instance
lypinator	0:bb348c97df44	1500	* @retval HAL status
lypinator	0:bb348c97df44	1501	*/
lypinator	0:bb348c97df44	1502	HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
lypinator	0:bb348c97df44	1503	{
lypinator	0:bb348c97df44	1504	/* Check the parameters */
lypinator	0:bb348c97df44	1505	assert_param(IS_FMC_SDRAM_DEVICE(Device));
lypinator	0:bb348c97df44	1506	assert_param(IS_FMC_SDRAM_BANK(Bank));
lypinator	0:bb348c97df44	1507
lypinator	0:bb348c97df44	1508	/* De-initialize the SDRAM device */
lypinator	0:bb348c97df44	1509	Device->SDCR[Bank] = 0x000002D0U;
lypinator	0:bb348c97df44	1510	Device->SDTR[Bank] = 0x0FFFFFFFU;
lypinator	0:bb348c97df44	1511	Device->SDCMR = 0x00000000U;
lypinator	0:bb348c97df44	1512	Device->SDRTR = 0x00000000U;
lypinator	0:bb348c97df44	1513	Device->SDSR = 0x00000000U;
lypinator	0:bb348c97df44	1514
lypinator	0:bb348c97df44	1515	return HAL_OK;
lypinator	0:bb348c97df44	1516	}
lypinator	0:bb348c97df44	1517
lypinator	0:bb348c97df44	1518	/**
lypinator	0:bb348c97df44	1519	* @}
lypinator	0:bb348c97df44	1520	*/
lypinator	0:bb348c97df44	1521
lypinator	0:bb348c97df44	1522	/** @addtogroup FMC_LL_SDRAMPrivate_Functions_Group2
lypinator	0:bb348c97df44	1523	* @brief management functions
lypinator	0:bb348c97df44	1524	*
lypinator	0:bb348c97df44	1525	@verbatim
lypinator	0:bb348c97df44	1526	==============================================================================
lypinator	0:bb348c97df44	1527	##### FMC_SDRAM Control functions #####
lypinator	0:bb348c97df44	1528	==============================================================================
lypinator	0:bb348c97df44	1529	[..]
lypinator	0:bb348c97df44	1530	This subsection provides a set of functions allowing to control dynamically
lypinator	0:bb348c97df44	1531	the FMC SDRAM interface.
lypinator	0:bb348c97df44	1532
lypinator	0:bb348c97df44	1533	@endverbatim
lypinator	0:bb348c97df44	1534	* @{
lypinator	0:bb348c97df44	1535	*/
lypinator	0:bb348c97df44	1536	/**
lypinator	0:bb348c97df44	1537	* @brief Enables dynamically FMC_SDRAM write protection.
lypinator	0:bb348c97df44	1538	* @param Device Pointer to SDRAM device instance
lypinator	0:bb348c97df44	1539	* @param Bank SDRAM bank number
lypinator	0:bb348c97df44	1540	* @retval HAL status
lypinator	0:bb348c97df44	1541	*/
lypinator	0:bb348c97df44	1542	HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
lypinator	0:bb348c97df44	1543	{
lypinator	0:bb348c97df44	1544	/* Check the parameters */
lypinator	0:bb348c97df44	1545	assert_param(IS_FMC_SDRAM_DEVICE(Device));
lypinator	0:bb348c97df44	1546	assert_param(IS_FMC_SDRAM_BANK(Bank));
lypinator	0:bb348c97df44	1547
lypinator	0:bb348c97df44	1548	/* Enable write protection */
lypinator	0:bb348c97df44	1549	Device->SDCR[Bank] \|= FMC_SDRAM_WRITE_PROTECTION_ENABLE;
lypinator	0:bb348c97df44	1550
lypinator	0:bb348c97df44	1551	return HAL_OK;
lypinator	0:bb348c97df44	1552	}
lypinator	0:bb348c97df44	1553
lypinator	0:bb348c97df44	1554	/**
lypinator	0:bb348c97df44	1555	* @brief Disables dynamically FMC_SDRAM write protection.
lypinator	0:bb348c97df44	1556	* @param hsdram FMC_SDRAM handle
lypinator	0:bb348c97df44	1557	* @retval HAL status
lypinator	0:bb348c97df44	1558	*/
lypinator	0:bb348c97df44	1559	HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
lypinator	0:bb348c97df44	1560	{
lypinator	0:bb348c97df44	1561	/* Check the parameters */
lypinator	0:bb348c97df44	1562	assert_param(IS_FMC_SDRAM_DEVICE(Device));
lypinator	0:bb348c97df44	1563	assert_param(IS_FMC_SDRAM_BANK(Bank));
lypinator	0:bb348c97df44	1564
lypinator	0:bb348c97df44	1565	/* Disable write protection */
lypinator	0:bb348c97df44	1566	Device->SDCR[Bank] &= ~FMC_SDRAM_WRITE_PROTECTION_ENABLE;
lypinator	0:bb348c97df44	1567
lypinator	0:bb348c97df44	1568	return HAL_OK;
lypinator	0:bb348c97df44	1569	}
lypinator	0:bb348c97df44	1570
lypinator	0:bb348c97df44	1571	/**
lypinator	0:bb348c97df44	1572	* @brief Send Command to the FMC SDRAM bank
lypinator	0:bb348c97df44	1573	* @param Device Pointer to SDRAM device instance
lypinator	0:bb348c97df44	1574	* @param Command Pointer to SDRAM command structure
lypinator	0:bb348c97df44	1575	* @param Timing Pointer to SDRAM Timing structure
lypinator	0:bb348c97df44	1576	* @param Timeout Timeout wait value
lypinator	0:bb348c97df44	1577	* @retval HAL state
lypinator	0:bb348c97df44	1578	*/
lypinator	0:bb348c97df44	1579	HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef Device, FMC_SDRAM_CommandTypeDef Command, uint32_t Timeout)
lypinator	0:bb348c97df44	1580	{
lypinator	0:bb348c97df44	1581	__IO uint32_t tmpr = 0U;
lypinator	0:bb348c97df44	1582	uint32_t tickstart = 0U;
lypinator	0:bb348c97df44	1583
lypinator	0:bb348c97df44	1584	/* Check the parameters */
lypinator	0:bb348c97df44	1585	assert_param(IS_FMC_SDRAM_DEVICE(Device));
lypinator	0:bb348c97df44	1586	assert_param(IS_FMC_COMMAND_MODE(Command->CommandMode));
lypinator	0:bb348c97df44	1587	assert_param(IS_FMC_COMMAND_TARGET(Command->CommandTarget));
lypinator	0:bb348c97df44	1588	assert_param(IS_FMC_AUTOREFRESH_NUMBER(Command->AutoRefreshNumber));
lypinator	0:bb348c97df44	1589	assert_param(IS_FMC_MODE_REGISTER(Command->ModeRegisterDefinition));
lypinator	0:bb348c97df44	1590
lypinator	0:bb348c97df44	1591	/* Set command register */
lypinator	0:bb348c97df44	1592	tmpr = (uint32_t)((Command->CommandMode) \|\
lypinator	0:bb348c97df44	1593	(Command->CommandTarget) \|\
lypinator	0:bb348c97df44	1594	(((Command->AutoRefreshNumber)-1U) << 5U) \|\
lypinator	0:bb348c97df44	1595	((Command->ModeRegisterDefinition) << 9U)
lypinator	0:bb348c97df44	1596	);
lypinator	0:bb348c97df44	1597
lypinator	0:bb348c97df44	1598	Device->SDCMR = tmpr;
lypinator	0:bb348c97df44	1599
lypinator	0:bb348c97df44	1600	/* Get tick */
lypinator	0:bb348c97df44	1601	tickstart = HAL_GetTick();
lypinator	0:bb348c97df44	1602
lypinator	0:bb348c97df44	1603	/* Wait until command is send */
lypinator	0:bb348c97df44	1604	while(HAL_IS_BIT_SET(Device->SDSR, FMC_SDSR_BUSY))
lypinator	0:bb348c97df44	1605	{
lypinator	0:bb348c97df44	1606	/* Check for the Timeout */
lypinator	0:bb348c97df44	1607	if(Timeout != HAL_MAX_DELAY)
lypinator	0:bb348c97df44	1608	{
lypinator	0:bb348c97df44	1609	if((Timeout == 0U)\|\|((HAL_GetTick() - tickstart ) > Timeout))
lypinator	0:bb348c97df44	1610	{
lypinator	0:bb348c97df44	1611	return HAL_TIMEOUT;
lypinator	0:bb348c97df44	1612	}
lypinator	0:bb348c97df44	1613	}
lypinator	0:bb348c97df44	1614	}
lypinator	0:bb348c97df44	1615
lypinator	0:bb348c97df44	1616	return HAL_OK;
lypinator	0:bb348c97df44	1617	}
lypinator	0:bb348c97df44	1618
lypinator	0:bb348c97df44	1619	/**
lypinator	0:bb348c97df44	1620	* @brief Program the SDRAM Memory Refresh rate.
lypinator	0:bb348c97df44	1621	* @param Device Pointer to SDRAM device instance
lypinator	0:bb348c97df44	1622	* @param RefreshRate The SDRAM refresh rate value.
lypinator	0:bb348c97df44	1623	* @retval HAL state
lypinator	0:bb348c97df44	1624	*/
lypinator	0:bb348c97df44	1625	HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate)
lypinator	0:bb348c97df44	1626	{
lypinator	0:bb348c97df44	1627	/* Check the parameters */
lypinator	0:bb348c97df44	1628	assert_param(IS_FMC_SDRAM_DEVICE(Device));
lypinator	0:bb348c97df44	1629	assert_param(IS_FMC_REFRESH_RATE(RefreshRate));
lypinator	0:bb348c97df44	1630
lypinator	0:bb348c97df44	1631	/* Set the refresh rate in command register */
lypinator	0:bb348c97df44	1632	Device->SDRTR \|= (RefreshRate<<1U);
lypinator	0:bb348c97df44	1633
lypinator	0:bb348c97df44	1634	return HAL_OK;
lypinator	0:bb348c97df44	1635	}
lypinator	0:bb348c97df44	1636
lypinator	0:bb348c97df44	1637	/**
lypinator	0:bb348c97df44	1638	* @brief Set the Number of consecutive SDRAM Memory auto Refresh commands.
lypinator	0:bb348c97df44	1639	* @param Device Pointer to SDRAM device instance
lypinator	0:bb348c97df44	1640	* @param AutoRefreshNumber Specifies the auto Refresh number.
lypinator	0:bb348c97df44	1641	* @retval None
lypinator	0:bb348c97df44	1642	*/
lypinator	0:bb348c97df44	1643	HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber)
lypinator	0:bb348c97df44	1644	{
lypinator	0:bb348c97df44	1645	/* Check the parameters */
lypinator	0:bb348c97df44	1646	assert_param(IS_FMC_SDRAM_DEVICE(Device));
lypinator	0:bb348c97df44	1647	assert_param(IS_FMC_AUTOREFRESH_NUMBER(AutoRefreshNumber));
lypinator	0:bb348c97df44	1648
lypinator	0:bb348c97df44	1649	/* Set the Auto-refresh number in command register */
lypinator	0:bb348c97df44	1650	Device->SDCMR \|= (AutoRefreshNumber << 5U);
lypinator	0:bb348c97df44	1651
lypinator	0:bb348c97df44	1652	return HAL_OK;
lypinator	0:bb348c97df44	1653	}
lypinator	0:bb348c97df44	1654
lypinator	0:bb348c97df44	1655	/**
lypinator	0:bb348c97df44	1656	* @brief Returns the indicated FMC SDRAM bank mode status.
lypinator	0:bb348c97df44	1657	* @param Device Pointer to SDRAM device instance
lypinator	0:bb348c97df44	1658	* @param Bank Defines the FMC SDRAM bank. This parameter can be
lypinator	0:bb348c97df44	1659	* FMC_Bank1_SDRAM or FMC_Bank2_SDRAM.
lypinator	0:bb348c97df44	1660	* @retval The FMC SDRAM bank mode status, could be on of the following values:
lypinator	0:bb348c97df44	1661	* FMC_SDRAM_NORMAL_MODE, FMC_SDRAM_SELF_REFRESH_MODE or
lypinator	0:bb348c97df44	1662	* FMC_SDRAM_POWER_DOWN_MODE.
lypinator	0:bb348c97df44	1663	*/
lypinator	0:bb348c97df44	1664	uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
lypinator	0:bb348c97df44	1665	{
lypinator	0:bb348c97df44	1666	uint32_t tmpreg = 0U;
lypinator	0:bb348c97df44	1667
lypinator	0:bb348c97df44	1668	/* Check the parameters */
lypinator	0:bb348c97df44	1669	assert_param(IS_FMC_SDRAM_DEVICE(Device));
lypinator	0:bb348c97df44	1670	assert_param(IS_FMC_SDRAM_BANK(Bank));
lypinator	0:bb348c97df44	1671
lypinator	0:bb348c97df44	1672	/* Get the corresponding bank mode */
lypinator	0:bb348c97df44	1673	if(Bank == FMC_SDRAM_BANK1)
lypinator	0:bb348c97df44	1674	{
lypinator	0:bb348c97df44	1675	tmpreg = (uint32_t)(Device->SDSR & FMC_SDSR_MODES1);
lypinator	0:bb348c97df44	1676	}
lypinator	0:bb348c97df44	1677	else
lypinator	0:bb348c97df44	1678	{
lypinator	0:bb348c97df44	1679	tmpreg = ((uint32_t)(Device->SDSR & FMC_SDSR_MODES2) >> 2U);
lypinator	0:bb348c97df44	1680	}
lypinator	0:bb348c97df44	1681
lypinator	0:bb348c97df44	1682	/* Return the mode status */
lypinator	0:bb348c97df44	1683	return tmpreg;
lypinator	0:bb348c97df44	1684	}
lypinator	0:bb348c97df44	1685
lypinator	0:bb348c97df44	1686	/**
lypinator	0:bb348c97df44	1687	* @}
lypinator	0:bb348c97df44	1688	*/
lypinator	0:bb348c97df44	1689
lypinator	0:bb348c97df44	1690	/**
lypinator	0:bb348c97df44	1691	* @}
lypinator	0:bb348c97df44	1692	*/
lypinator	0:bb348c97df44	1693
lypinator	0:bb348c97df44	1694	/**
lypinator	0:bb348c97df44	1695	* @}
lypinator	0:bb348c97df44	1696	*/
lypinator	0:bb348c97df44	1697	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
lypinator	0:bb348c97df44	1698	#endif /* HAL_SRAM_MODULE_ENABLED \|\| HAL_NOR_MODULE_ENABLED \|\| HAL_NAND_MODULE_ENABLED \|\| HAL_PCCARD_MODULE_ENABLED \|\| HAL_SDRAM_MODULE_ENABLED */
lypinator	0:bb348c97df44	1699
lypinator	0:bb348c97df44	1700	/**
lypinator	0:bb348c97df44	1701	* @}
lypinator	0:bb348c97df44	1702	*/
lypinator	0:bb348c97df44	1703
lypinator	0:bb348c97df44	1704	/**
lypinator	0:bb348c97df44	1705	* @}
lypinator	0:bb348c97df44	1706	*/
lypinator	0:bb348c97df44	1707
lypinator	0:bb348c97df44	1708	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Program
Created:	16 Sep 2020
Imports:	1
Forks:	0
Commits:	1
Dependents:	0
Dependencies:	1
Followers:	1

mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_fmc.c@0:bb348c97df44, 2020-09-16 (annotated)

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