DevLibMemoryController - Initial commit

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Initial commit

mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_dma.h@0:bb348c97df44, 2020-09-16 (annotated)

Committer:: lypinator
Date:: Wed Sep 16 01:11:49 2020 +0000
Revision:: 0:bb348c97df44

Added PWM

Who changed what in which revision?

User	Revision	Line number	New contents of line
lypinator	0:bb348c97df44	1	/**
lypinator	0:bb348c97df44	2	******************************************************************************
lypinator	0:bb348c97df44	3	* @file stm32f4xx_ll_dma.h
lypinator	0:bb348c97df44	4	* @author MCD Application Team
lypinator	0:bb348c97df44	5	* @brief Header file of DMA LL module.
lypinator	0:bb348c97df44	6	******************************************************************************
lypinator	0:bb348c97df44	7	* @attention
lypinator	0:bb348c97df44	8	*
lypinator	0:bb348c97df44	9	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
lypinator	0:bb348c97df44	10	*
lypinator	0:bb348c97df44	11	* Redistribution and use in source and binary forms, with or without modification,
lypinator	0:bb348c97df44	12	* are permitted provided that the following conditions are met:
lypinator	0:bb348c97df44	13	* 1. Redistributions of source code must retain the above copyright notice,
lypinator	0:bb348c97df44	14	* this list of conditions and the following disclaimer.
lypinator	0:bb348c97df44	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
lypinator	0:bb348c97df44	16	* this list of conditions and the following disclaimer in the documentation
lypinator	0:bb348c97df44	17	* and/or other materials provided with the distribution.
lypinator	0:bb348c97df44	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
lypinator	0:bb348c97df44	19	* may be used to endorse or promote products derived from this software
lypinator	0:bb348c97df44	20	* without specific prior written permission.
lypinator	0:bb348c97df44	21	*
lypinator	0:bb348c97df44	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
lypinator	0:bb348c97df44	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
lypinator	0:bb348c97df44	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
lypinator	0:bb348c97df44	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
lypinator	0:bb348c97df44	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
lypinator	0:bb348c97df44	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
lypinator	0:bb348c97df44	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
lypinator	0:bb348c97df44	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
lypinator	0:bb348c97df44	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
lypinator	0:bb348c97df44	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
lypinator	0:bb348c97df44	32	*
lypinator	0:bb348c97df44	33	******************************************************************************
lypinator	0:bb348c97df44	34	*/
lypinator	0:bb348c97df44	35
lypinator	0:bb348c97df44	36	/* Define to prevent recursive inclusion -------------------------------------*/
lypinator	0:bb348c97df44	37	#ifndef __STM32F4xx_LL_DMA_H
lypinator	0:bb348c97df44	38	#define __STM32F4xx_LL_DMA_H
lypinator	0:bb348c97df44	39
lypinator	0:bb348c97df44	40	#ifdef __cplusplus
lypinator	0:bb348c97df44	41	extern "C" {
lypinator	0:bb348c97df44	42	#endif
lypinator	0:bb348c97df44	43
lypinator	0:bb348c97df44	44	/* Includes ------------------------------------------------------------------*/
lypinator	0:bb348c97df44	45	#include "stm32f4xx.h"
lypinator	0:bb348c97df44	46
lypinator	0:bb348c97df44	47	/** @addtogroup STM32F4xx_LL_Driver
lypinator	0:bb348c97df44	48	* @{
lypinator	0:bb348c97df44	49	*/
lypinator	0:bb348c97df44	50
lypinator	0:bb348c97df44	51	#if defined (DMA1) \|\| defined (DMA2)
lypinator	0:bb348c97df44	52
lypinator	0:bb348c97df44	53	/** @defgroup DMA_LL DMA
lypinator	0:bb348c97df44	54	* @{
lypinator	0:bb348c97df44	55	*/
lypinator	0:bb348c97df44	56
lypinator	0:bb348c97df44	57	/* Private types -------------------------------------------------------------*/
lypinator	0:bb348c97df44	58	/* Private variables ---------------------------------------------------------*/
lypinator	0:bb348c97df44	59	/** @defgroup DMA_LL_Private_Variables DMA Private Variables
lypinator	0:bb348c97df44	60	* @{
lypinator	0:bb348c97df44	61	*/
lypinator	0:bb348c97df44	62	/* Array used to get the DMA stream register offset versus stream index LL_DMA_STREAM_x */
lypinator	0:bb348c97df44	63	static const uint8_t STREAM_OFFSET_TAB[] =
lypinator	0:bb348c97df44	64	{
lypinator	0:bb348c97df44	65	(uint8_t)(DMA1_Stream0_BASE - DMA1_BASE),
lypinator	0:bb348c97df44	66	(uint8_t)(DMA1_Stream1_BASE - DMA1_BASE),
lypinator	0:bb348c97df44	67	(uint8_t)(DMA1_Stream2_BASE - DMA1_BASE),
lypinator	0:bb348c97df44	68	(uint8_t)(DMA1_Stream3_BASE - DMA1_BASE),
lypinator	0:bb348c97df44	69	(uint8_t)(DMA1_Stream4_BASE - DMA1_BASE),
lypinator	0:bb348c97df44	70	(uint8_t)(DMA1_Stream5_BASE - DMA1_BASE),
lypinator	0:bb348c97df44	71	(uint8_t)(DMA1_Stream6_BASE - DMA1_BASE),
lypinator	0:bb348c97df44	72	(uint8_t)(DMA1_Stream7_BASE - DMA1_BASE)
lypinator	0:bb348c97df44	73	};
lypinator	0:bb348c97df44	74
lypinator	0:bb348c97df44	75	/**
lypinator	0:bb348c97df44	76	* @}
lypinator	0:bb348c97df44	77	*/
lypinator	0:bb348c97df44	78
lypinator	0:bb348c97df44	79	/* Private constants ---------------------------------------------------------*/
lypinator	0:bb348c97df44	80	/** @defgroup DMA_LL_Private_Constants DMA Private Constants
lypinator	0:bb348c97df44	81	* @{
lypinator	0:bb348c97df44	82	*/
lypinator	0:bb348c97df44	83	/**
lypinator	0:bb348c97df44	84	* @}
lypinator	0:bb348c97df44	85	*/
lypinator	0:bb348c97df44	86
lypinator	0:bb348c97df44	87
lypinator	0:bb348c97df44	88	/* Private macros ------------------------------------------------------------*/
lypinator	0:bb348c97df44	89	/* Exported types ------------------------------------------------------------*/
lypinator	0:bb348c97df44	90	#if defined(USE_FULL_LL_DRIVER)
lypinator	0:bb348c97df44	91	/** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
lypinator	0:bb348c97df44	92	* @{
lypinator	0:bb348c97df44	93	*/
lypinator	0:bb348c97df44	94	typedef struct
lypinator	0:bb348c97df44	95	{
lypinator	0:bb348c97df44	96	uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer
lypinator	0:bb348c97df44	97	or as Source base address in case of memory to memory transfer direction.
lypinator	0:bb348c97df44	98
lypinator	0:bb348c97df44	99	This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
lypinator	0:bb348c97df44	100
lypinator	0:bb348c97df44	101	uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer
lypinator	0:bb348c97df44	102	or as Destination base address in case of memory to memory transfer direction.
lypinator	0:bb348c97df44	103
lypinator	0:bb348c97df44	104	This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
lypinator	0:bb348c97df44	105
lypinator	0:bb348c97df44	106	uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
lypinator	0:bb348c97df44	107	from memory to memory or from peripheral to memory.
lypinator	0:bb348c97df44	108	This parameter can be a value of @ref DMA_LL_EC_DIRECTION
lypinator	0:bb348c97df44	109
lypinator	0:bb348c97df44	110	This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */
lypinator	0:bb348c97df44	111
lypinator	0:bb348c97df44	112	uint32_t Mode; /*!< Specifies the normal or circular operation mode.
lypinator	0:bb348c97df44	113	This parameter can be a value of @ref DMA_LL_EC_MODE
lypinator	0:bb348c97df44	114	@note The circular buffer mode cannot be used if the memory to memory
lypinator	0:bb348c97df44	115	data transfer direction is configured on the selected Stream
lypinator	0:bb348c97df44	116
lypinator	0:bb348c97df44	117	This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */
lypinator	0:bb348c97df44	118
lypinator	0:bb348c97df44	119	uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
lypinator	0:bb348c97df44	120	is incremented or not.
lypinator	0:bb348c97df44	121	This parameter can be a value of @ref DMA_LL_EC_PERIPH
lypinator	0:bb348c97df44	122
lypinator	0:bb348c97df44	123	This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */
lypinator	0:bb348c97df44	124
lypinator	0:bb348c97df44	125	uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
lypinator	0:bb348c97df44	126	is incremented or not.
lypinator	0:bb348c97df44	127	This parameter can be a value of @ref DMA_LL_EC_MEMORY
lypinator	0:bb348c97df44	128
lypinator	0:bb348c97df44	129	This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */
lypinator	0:bb348c97df44	130
lypinator	0:bb348c97df44	131	uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
lypinator	0:bb348c97df44	132	in case of memory to memory transfer direction.
lypinator	0:bb348c97df44	133	This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN
lypinator	0:bb348c97df44	134
lypinator	0:bb348c97df44	135	This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */
lypinator	0:bb348c97df44	136
lypinator	0:bb348c97df44	137	uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
lypinator	0:bb348c97df44	138	in case of memory to memory transfer direction.
lypinator	0:bb348c97df44	139	This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN
lypinator	0:bb348c97df44	140
lypinator	0:bb348c97df44	141	This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */
lypinator	0:bb348c97df44	142
lypinator	0:bb348c97df44	143	uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit.
lypinator	0:bb348c97df44	144	The data unit is equal to the source buffer configuration set in PeripheralSize
lypinator	0:bb348c97df44	145	or MemorySize parameters depending in the transfer direction.
lypinator	0:bb348c97df44	146	This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
lypinator	0:bb348c97df44	147
lypinator	0:bb348c97df44	148	This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */
lypinator	0:bb348c97df44	149
lypinator	0:bb348c97df44	150	uint32_t Channel; /*!< Specifies the peripheral channel.
lypinator	0:bb348c97df44	151	This parameter can be a value of @ref DMA_LL_EC_CHANNEL
lypinator	0:bb348c97df44	152
lypinator	0:bb348c97df44	153	This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelSelection(). */
lypinator	0:bb348c97df44	154
lypinator	0:bb348c97df44	155	uint32_t Priority; /*!< Specifies the channel priority level.
lypinator	0:bb348c97df44	156	This parameter can be a value of @ref DMA_LL_EC_PRIORITY
lypinator	0:bb348c97df44	157
lypinator	0:bb348c97df44	158	This feature can be modified afterwards using unitary function @ref LL_DMA_SetStreamPriorityLevel(). */
lypinator	0:bb348c97df44	159
lypinator	0:bb348c97df44	160	uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream.
lypinator	0:bb348c97df44	161	This parameter can be a value of @ref DMA_LL_FIFOMODE
lypinator	0:bb348c97df44	162	@note The Direct mode (FIFO mode disabled) cannot be used if the
lypinator	0:bb348c97df44	163	memory-to-memory data transfer is configured on the selected stream
lypinator	0:bb348c97df44	164
lypinator	0:bb348c97df44	165	This feature can be modified afterwards using unitary functions @ref LL_DMA_EnableFifoMode() or @ref LL_DMA_EnableFifoMode() . */
lypinator	0:bb348c97df44	166
lypinator	0:bb348c97df44	167	uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level.
lypinator	0:bb348c97df44	168	This parameter can be a value of @ref DMA_LL_EC_FIFOTHRESHOLD
lypinator	0:bb348c97df44	169
lypinator	0:bb348c97df44	170	This feature can be modified afterwards using unitary function @ref LL_DMA_SetFIFOThreshold(). */
lypinator	0:bb348c97df44	171
lypinator	0:bb348c97df44	172	uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers.
lypinator	0:bb348c97df44	173	It specifies the amount of data to be transferred in a single non interruptible
lypinator	0:bb348c97df44	174	transaction.
lypinator	0:bb348c97df44	175	This parameter can be a value of @ref DMA_LL_EC_MBURST
lypinator	0:bb348c97df44	176	@note The burst mode is possible only if the address Increment mode is enabled.
lypinator	0:bb348c97df44	177
lypinator	0:bb348c97df44	178	This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryBurstxfer(). */
lypinator	0:bb348c97df44	179
lypinator	0:bb348c97df44	180	uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers.
lypinator	0:bb348c97df44	181	It specifies the amount of data to be transferred in a single non interruptible
lypinator	0:bb348c97df44	182	transaction.
lypinator	0:bb348c97df44	183	This parameter can be a value of @ref DMA_LL_EC_PBURST
lypinator	0:bb348c97df44	184	@note The burst mode is possible only if the address Increment mode is enabled.
lypinator	0:bb348c97df44	185
lypinator	0:bb348c97df44	186	This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphBurstxfer(). */
lypinator	0:bb348c97df44	187
lypinator	0:bb348c97df44	188	} LL_DMA_InitTypeDef;
lypinator	0:bb348c97df44	189	/**
lypinator	0:bb348c97df44	190	* @}
lypinator	0:bb348c97df44	191	*/
lypinator	0:bb348c97df44	192	#endif /USE_FULL_LL_DRIVER/
lypinator	0:bb348c97df44	193	/* Exported constants --------------------------------------------------------*/
lypinator	0:bb348c97df44	194	/** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
lypinator	0:bb348c97df44	195	* @{
lypinator	0:bb348c97df44	196	*/
lypinator	0:bb348c97df44	197
lypinator	0:bb348c97df44	198	/** @defgroup DMA_LL_EC_STREAM STREAM
lypinator	0:bb348c97df44	199	* @{
lypinator	0:bb348c97df44	200	*/
lypinator	0:bb348c97df44	201	#define LL_DMA_STREAM_0 0x00000000U
lypinator	0:bb348c97df44	202	#define LL_DMA_STREAM_1 0x00000001U
lypinator	0:bb348c97df44	203	#define LL_DMA_STREAM_2 0x00000002U
lypinator	0:bb348c97df44	204	#define LL_DMA_STREAM_3 0x00000003U
lypinator	0:bb348c97df44	205	#define LL_DMA_STREAM_4 0x00000004U
lypinator	0:bb348c97df44	206	#define LL_DMA_STREAM_5 0x00000005U
lypinator	0:bb348c97df44	207	#define LL_DMA_STREAM_6 0x00000006U
lypinator	0:bb348c97df44	208	#define LL_DMA_STREAM_7 0x00000007U
lypinator	0:bb348c97df44	209	#define LL_DMA_STREAM_ALL 0xFFFF0000U
lypinator	0:bb348c97df44	210	/**
lypinator	0:bb348c97df44	211	* @}
lypinator	0:bb348c97df44	212	*/
lypinator	0:bb348c97df44	213
lypinator	0:bb348c97df44	214	/** @defgroup DMA_LL_EC_DIRECTION DIRECTION
lypinator	0:bb348c97df44	215	* @{
lypinator	0:bb348c97df44	216	*/
lypinator	0:bb348c97df44	217	#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /!< Peripheral to memory direction /
lypinator	0:bb348c97df44	218	#define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_SxCR_DIR_0 /!< Memory to peripheral direction /
lypinator	0:bb348c97df44	219	#define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_SxCR_DIR_1 /!< Memory to memory direction /
lypinator	0:bb348c97df44	220	/**
lypinator	0:bb348c97df44	221	* @}
lypinator	0:bb348c97df44	222	*/
lypinator	0:bb348c97df44	223
lypinator	0:bb348c97df44	224	/** @defgroup DMA_LL_EC_MODE MODE
lypinator	0:bb348c97df44	225	* @{
lypinator	0:bb348c97df44	226	*/
lypinator	0:bb348c97df44	227	#define LL_DMA_MODE_NORMAL 0x00000000U /!< Normal Mode /
lypinator	0:bb348c97df44	228	#define LL_DMA_MODE_CIRCULAR DMA_SxCR_CIRC /!< Circular Mode /
lypinator	0:bb348c97df44	229	#define LL_DMA_MODE_PFCTRL DMA_SxCR_PFCTRL /!< Peripheral flow control mode /
lypinator	0:bb348c97df44	230	/**
lypinator	0:bb348c97df44	231	* @}
lypinator	0:bb348c97df44	232	*/
lypinator	0:bb348c97df44	233
lypinator	0:bb348c97df44	234	/** @defgroup DMA_LL_EC_DOUBLEBUFFER_MODE DOUBLEBUFFER MODE
lypinator	0:bb348c97df44	235	* @{
lypinator	0:bb348c97df44	236	*/
lypinator	0:bb348c97df44	237	#define LL_DMA_DOUBLEBUFFER_MODE_DISABLE 0x00000000U /!< Disable double buffering mode /
lypinator	0:bb348c97df44	238	#define LL_DMA_DOUBLEBUFFER_MODE_ENABLE DMA_SxCR_DBM /!< Enable double buffering mode /
lypinator	0:bb348c97df44	239	/**
lypinator	0:bb348c97df44	240	* @}
lypinator	0:bb348c97df44	241	*/
lypinator	0:bb348c97df44	242
lypinator	0:bb348c97df44	243	/** @defgroup DMA_LL_EC_PERIPH PERIPH
lypinator	0:bb348c97df44	244	* @{
lypinator	0:bb348c97df44	245	*/
lypinator	0:bb348c97df44	246	#define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /!< Peripheral increment mode Disable /
lypinator	0:bb348c97df44	247	#define LL_DMA_PERIPH_INCREMENT DMA_SxCR_PINC /!< Peripheral increment mode Enable /
lypinator	0:bb348c97df44	248	/**
lypinator	0:bb348c97df44	249	* @}
lypinator	0:bb348c97df44	250	*/
lypinator	0:bb348c97df44	251
lypinator	0:bb348c97df44	252	/** @defgroup DMA_LL_EC_MEMORY MEMORY
lypinator	0:bb348c97df44	253	* @{
lypinator	0:bb348c97df44	254	*/
lypinator	0:bb348c97df44	255	#define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /!< Memory increment mode Disable /
lypinator	0:bb348c97df44	256	#define LL_DMA_MEMORY_INCREMENT DMA_SxCR_MINC /!< Memory increment mode Enable /
lypinator	0:bb348c97df44	257	/**
lypinator	0:bb348c97df44	258	* @}
lypinator	0:bb348c97df44	259	*/
lypinator	0:bb348c97df44	260
lypinator	0:bb348c97df44	261	/** @defgroup DMA_LL_EC_PDATAALIGN PDATAALIGN
lypinator	0:bb348c97df44	262	* @{
lypinator	0:bb348c97df44	263	*/
lypinator	0:bb348c97df44	264	#define LL_DMA_PDATAALIGN_BYTE 0x00000000U /!< Peripheral data alignment : Byte /
lypinator	0:bb348c97df44	265	#define LL_DMA_PDATAALIGN_HALFWORD DMA_SxCR_PSIZE_0 /!< Peripheral data alignment : HalfWord /
lypinator	0:bb348c97df44	266	#define LL_DMA_PDATAALIGN_WORD DMA_SxCR_PSIZE_1 /!< Peripheral data alignment : Word /
lypinator	0:bb348c97df44	267	/**
lypinator	0:bb348c97df44	268	* @}
lypinator	0:bb348c97df44	269	*/
lypinator	0:bb348c97df44	270
lypinator	0:bb348c97df44	271	/** @defgroup DMA_LL_EC_MDATAALIGN MDATAALIGN
lypinator	0:bb348c97df44	272	* @{
lypinator	0:bb348c97df44	273	*/
lypinator	0:bb348c97df44	274	#define LL_DMA_MDATAALIGN_BYTE 0x00000000U /!< Memory data alignment : Byte /
lypinator	0:bb348c97df44	275	#define LL_DMA_MDATAALIGN_HALFWORD DMA_SxCR_MSIZE_0 /!< Memory data alignment : HalfWord /
lypinator	0:bb348c97df44	276	#define LL_DMA_MDATAALIGN_WORD DMA_SxCR_MSIZE_1 /!< Memory data alignment : Word /
lypinator	0:bb348c97df44	277	/**
lypinator	0:bb348c97df44	278	* @}
lypinator	0:bb348c97df44	279	*/
lypinator	0:bb348c97df44	280
lypinator	0:bb348c97df44	281	/** @defgroup DMA_LL_EC_OFFSETSIZE OFFSETSIZE
lypinator	0:bb348c97df44	282	* @{
lypinator	0:bb348c97df44	283	*/
lypinator	0:bb348c97df44	284	#define LL_DMA_OFFSETSIZE_PSIZE 0x00000000U /!< Peripheral increment offset size is linked to the PSIZE /
lypinator	0:bb348c97df44	285	#define LL_DMA_OFFSETSIZE_FIXEDTO4 DMA_SxCR_PINCOS /!< Peripheral increment offset size is fixed to 4 (32-bit alignment) /
lypinator	0:bb348c97df44	286	/**
lypinator	0:bb348c97df44	287	* @}
lypinator	0:bb348c97df44	288	*/
lypinator	0:bb348c97df44	289
lypinator	0:bb348c97df44	290	/** @defgroup DMA_LL_EC_PRIORITY PRIORITY
lypinator	0:bb348c97df44	291	* @{
lypinator	0:bb348c97df44	292	*/
lypinator	0:bb348c97df44	293	#define LL_DMA_PRIORITY_LOW 0x00000000U /!< Priority level : Low /
lypinator	0:bb348c97df44	294	#define LL_DMA_PRIORITY_MEDIUM DMA_SxCR_PL_0 /!< Priority level : Medium /
lypinator	0:bb348c97df44	295	#define LL_DMA_PRIORITY_HIGH DMA_SxCR_PL_1 /!< Priority level : High /
lypinator	0:bb348c97df44	296	#define LL_DMA_PRIORITY_VERYHIGH DMA_SxCR_PL /!< Priority level : Very_High /
lypinator	0:bb348c97df44	297	/**
lypinator	0:bb348c97df44	298	* @}
lypinator	0:bb348c97df44	299	*/
lypinator	0:bb348c97df44	300
lypinator	0:bb348c97df44	301	/** @defgroup DMA_LL_EC_CHANNEL CHANNEL
lypinator	0:bb348c97df44	302	* @{
lypinator	0:bb348c97df44	303	*/
lypinator	0:bb348c97df44	304	#define LL_DMA_CHANNEL_0 0x00000000U /* Select Channel0 of DMA Instance */
lypinator	0:bb348c97df44	305	#define LL_DMA_CHANNEL_1 DMA_SxCR_CHSEL_0 /* Select Channel1 of DMA Instance */
lypinator	0:bb348c97df44	306	#define LL_DMA_CHANNEL_2 DMA_SxCR_CHSEL_1 /* Select Channel2 of DMA Instance */
lypinator	0:bb348c97df44	307	#define LL_DMA_CHANNEL_3 (DMA_SxCR_CHSEL_0 \| DMA_SxCR_CHSEL_1) /* Select Channel3 of DMA Instance */
lypinator	0:bb348c97df44	308	#define LL_DMA_CHANNEL_4 DMA_SxCR_CHSEL_2 /* Select Channel4 of DMA Instance */
lypinator	0:bb348c97df44	309	#define LL_DMA_CHANNEL_5 (DMA_SxCR_CHSEL_2 \| DMA_SxCR_CHSEL_0) /* Select Channel5 of DMA Instance */
lypinator	0:bb348c97df44	310	#define LL_DMA_CHANNEL_6 (DMA_SxCR_CHSEL_2 \| DMA_SxCR_CHSEL_1) /* Select Channel6 of DMA Instance */
lypinator	0:bb348c97df44	311	#define LL_DMA_CHANNEL_7 (DMA_SxCR_CHSEL_2 \| DMA_SxCR_CHSEL_1 \| DMA_SxCR_CHSEL_0) /* Select Channel7 of DMA Instance */
lypinator	0:bb348c97df44	312	/**
lypinator	0:bb348c97df44	313	* @}
lypinator	0:bb348c97df44	314	*/
lypinator	0:bb348c97df44	315
lypinator	0:bb348c97df44	316	/** @defgroup DMA_LL_EC_MBURST MBURST
lypinator	0:bb348c97df44	317	* @{
lypinator	0:bb348c97df44	318	*/
lypinator	0:bb348c97df44	319	#define LL_DMA_MBURST_SINGLE 0x00000000U /!< Memory burst single transfer configuration /
lypinator	0:bb348c97df44	320	#define LL_DMA_MBURST_INC4 DMA_SxCR_MBURST_0 /!< Memory burst of 4 beats transfer configuration /
lypinator	0:bb348c97df44	321	#define LL_DMA_MBURST_INC8 DMA_SxCR_MBURST_1 /!< Memory burst of 8 beats transfer configuration /
lypinator	0:bb348c97df44	322	#define LL_DMA_MBURST_INC16 (DMA_SxCR_MBURST_0 \| DMA_SxCR_MBURST_1) /!< Memory burst of 16 beats transfer configuration /
lypinator	0:bb348c97df44	323	/**
lypinator	0:bb348c97df44	324	* @}
lypinator	0:bb348c97df44	325	*/
lypinator	0:bb348c97df44	326
lypinator	0:bb348c97df44	327	/** @defgroup DMA_LL_EC_PBURST PBURST
lypinator	0:bb348c97df44	328	* @{
lypinator	0:bb348c97df44	329	*/
lypinator	0:bb348c97df44	330	#define LL_DMA_PBURST_SINGLE 0x00000000U /!< Peripheral burst single transfer configuration /
lypinator	0:bb348c97df44	331	#define LL_DMA_PBURST_INC4 DMA_SxCR_PBURST_0 /!< Peripheral burst of 4 beats transfer configuration /
lypinator	0:bb348c97df44	332	#define LL_DMA_PBURST_INC8 DMA_SxCR_PBURST_1 /!< Peripheral burst of 8 beats transfer configuration /
lypinator	0:bb348c97df44	333	#define LL_DMA_PBURST_INC16 (DMA_SxCR_PBURST_0 \| DMA_SxCR_PBURST_1) /!< Peripheral burst of 16 beats transfer configuration /
lypinator	0:bb348c97df44	334	/**
lypinator	0:bb348c97df44	335	* @}
lypinator	0:bb348c97df44	336	*/
lypinator	0:bb348c97df44	337
lypinator	0:bb348c97df44	338	/** @defgroup DMA_LL_FIFOMODE DMA_LL_FIFOMODE
lypinator	0:bb348c97df44	339	* @{
lypinator	0:bb348c97df44	340	*/
lypinator	0:bb348c97df44	341	#define LL_DMA_FIFOMODE_DISABLE 0x00000000U /!< FIFO mode disable (direct mode is enabled) /
lypinator	0:bb348c97df44	342	#define LL_DMA_FIFOMODE_ENABLE DMA_SxFCR_DMDIS /!< FIFO mode enable /
lypinator	0:bb348c97df44	343	/**
lypinator	0:bb348c97df44	344	* @}
lypinator	0:bb348c97df44	345	*/
lypinator	0:bb348c97df44	346
lypinator	0:bb348c97df44	347	/** @defgroup DMA_LL_EC_FIFOSTATUS_0 FIFOSTATUS 0
lypinator	0:bb348c97df44	348	* @{
lypinator	0:bb348c97df44	349	*/
lypinator	0:bb348c97df44	350	#define LL_DMA_FIFOSTATUS_0_25 0x00000000U /!< 0 < fifo_level < 1/4 /
lypinator	0:bb348c97df44	351	#define LL_DMA_FIFOSTATUS_25_50 DMA_SxFCR_FS_0 /!< 1/4 < fifo_level < 1/2 /
lypinator	0:bb348c97df44	352	#define LL_DMA_FIFOSTATUS_50_75 DMA_SxFCR_FS_1 /!< 1/2 < fifo_level < 3/4 /
lypinator	0:bb348c97df44	353	#define LL_DMA_FIFOSTATUS_75_100 (DMA_SxFCR_FS_1 \| DMA_SxFCR_FS_0) /!< 3/4 < fifo_level < full /
lypinator	0:bb348c97df44	354	#define LL_DMA_FIFOSTATUS_EMPTY DMA_SxFCR_FS_2 /!< FIFO is empty /
lypinator	0:bb348c97df44	355	#define LL_DMA_FIFOSTATUS_FULL (DMA_SxFCR_FS_2 \| DMA_SxFCR_FS_0) /!< FIFO is full /
lypinator	0:bb348c97df44	356	/**
lypinator	0:bb348c97df44	357	* @}
lypinator	0:bb348c97df44	358	*/
lypinator	0:bb348c97df44	359
lypinator	0:bb348c97df44	360	/** @defgroup DMA_LL_EC_FIFOTHRESHOLD FIFOTHRESHOLD
lypinator	0:bb348c97df44	361	* @{
lypinator	0:bb348c97df44	362	*/
lypinator	0:bb348c97df44	363	#define LL_DMA_FIFOTHRESHOLD_1_4 0x00000000U /!< FIFO threshold 1 quart full configuration /
lypinator	0:bb348c97df44	364	#define LL_DMA_FIFOTHRESHOLD_1_2 DMA_SxFCR_FTH_0 /!< FIFO threshold half full configuration /
lypinator	0:bb348c97df44	365	#define LL_DMA_FIFOTHRESHOLD_3_4 DMA_SxFCR_FTH_1 /!< FIFO threshold 3 quarts full configuration /
lypinator	0:bb348c97df44	366	#define LL_DMA_FIFOTHRESHOLD_FULL DMA_SxFCR_FTH /!< FIFO threshold full configuration /
lypinator	0:bb348c97df44	367	/**
lypinator	0:bb348c97df44	368	* @}
lypinator	0:bb348c97df44	369	*/
lypinator	0:bb348c97df44	370
lypinator	0:bb348c97df44	371	/** @defgroup DMA_LL_EC_CURRENTTARGETMEM CURRENTTARGETMEM
lypinator	0:bb348c97df44	372	* @{
lypinator	0:bb348c97df44	373	*/
lypinator	0:bb348c97df44	374	#define LL_DMA_CURRENTTARGETMEM0 0x00000000U /!< Set CurrentTarget Memory to Memory 0 /
lypinator	0:bb348c97df44	375	#define LL_DMA_CURRENTTARGETMEM1 DMA_SxCR_CT /!< Set CurrentTarget Memory to Memory 1 /
lypinator	0:bb348c97df44	376	/**
lypinator	0:bb348c97df44	377	* @}
lypinator	0:bb348c97df44	378	*/
lypinator	0:bb348c97df44	379
lypinator	0:bb348c97df44	380	/**
lypinator	0:bb348c97df44	381	* @}
lypinator	0:bb348c97df44	382	*/
lypinator	0:bb348c97df44	383
lypinator	0:bb348c97df44	384	/* Exported macro ------------------------------------------------------------*/
lypinator	0:bb348c97df44	385	/** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
lypinator	0:bb348c97df44	386	* @{
lypinator	0:bb348c97df44	387	*/
lypinator	0:bb348c97df44	388
lypinator	0:bb348c97df44	389	/** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros
lypinator	0:bb348c97df44	390	* @{
lypinator	0:bb348c97df44	391	*/
lypinator	0:bb348c97df44	392	/**
lypinator	0:bb348c97df44	393	* @brief Write a value in DMA register
lypinator	0:bb348c97df44	394	* @param __INSTANCE__ DMA Instance
lypinator	0:bb348c97df44	395	* @param __REG__ Register to be written
lypinator	0:bb348c97df44	396	* @param __VALUE__ Value to be written in the register
lypinator	0:bb348c97df44	397	* @retval None
lypinator	0:bb348c97df44	398	*/
lypinator	0:bb348c97df44	399	#define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
lypinator	0:bb348c97df44	400
lypinator	0:bb348c97df44	401	/**
lypinator	0:bb348c97df44	402	* @brief Read a value in DMA register
lypinator	0:bb348c97df44	403	* @param __INSTANCE__ DMA Instance
lypinator	0:bb348c97df44	404	* @param __REG__ Register to be read
lypinator	0:bb348c97df44	405	* @retval Register value
lypinator	0:bb348c97df44	406	*/
lypinator	0:bb348c97df44	407	#define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
lypinator	0:bb348c97df44	408	/**
lypinator	0:bb348c97df44	409	* @}
lypinator	0:bb348c97df44	410	*/
lypinator	0:bb348c97df44	411
lypinator	0:bb348c97df44	412	/** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxStreamy
lypinator	0:bb348c97df44	413	* @{
lypinator	0:bb348c97df44	414	*/
lypinator	0:bb348c97df44	415	/**
lypinator	0:bb348c97df44	416	* @brief Convert DMAx_Streamy into DMAx
lypinator	0:bb348c97df44	417	* @param __STREAM_INSTANCE__ DMAx_Streamy
lypinator	0:bb348c97df44	418	* @retval DMAx
lypinator	0:bb348c97df44	419	*/
lypinator	0:bb348c97df44	420	#define __LL_DMA_GET_INSTANCE(__STREAM_INSTANCE__) \
lypinator	0:bb348c97df44	421	(((uint32_t)(__STREAM_INSTANCE__) > ((uint32_t)DMA1_Stream7)) ? DMA2 : DMA1)
lypinator	0:bb348c97df44	422
lypinator	0:bb348c97df44	423	/**
lypinator	0:bb348c97df44	424	* @brief Convert DMAx_Streamy into LL_DMA_STREAM_y
lypinator	0:bb348c97df44	425	* @param __STREAM_INSTANCE__ DMAx_Streamy
lypinator	0:bb348c97df44	426	* @retval LL_DMA_CHANNEL_y
lypinator	0:bb348c97df44	427	*/
lypinator	0:bb348c97df44	428	#define __LL_DMA_GET_STREAM(__STREAM_INSTANCE__) \
lypinator	0:bb348c97df44	429	(((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream0)) ? LL_DMA_STREAM_0 : \
lypinator	0:bb348c97df44	430	((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream0)) ? LL_DMA_STREAM_0 : \
lypinator	0:bb348c97df44	431	((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream1)) ? LL_DMA_STREAM_1 : \
lypinator	0:bb348c97df44	432	((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream1)) ? LL_DMA_STREAM_1 : \
lypinator	0:bb348c97df44	433	((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream2)) ? LL_DMA_STREAM_2 : \
lypinator	0:bb348c97df44	434	((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream2)) ? LL_DMA_STREAM_2 : \
lypinator	0:bb348c97df44	435	((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream3)) ? LL_DMA_STREAM_3 : \
lypinator	0:bb348c97df44	436	((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream3)) ? LL_DMA_STREAM_3 : \
lypinator	0:bb348c97df44	437	((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream4)) ? LL_DMA_STREAM_4 : \
lypinator	0:bb348c97df44	438	((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream4)) ? LL_DMA_STREAM_4 : \
lypinator	0:bb348c97df44	439	((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream5)) ? LL_DMA_STREAM_5 : \
lypinator	0:bb348c97df44	440	((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream5)) ? LL_DMA_STREAM_5 : \
lypinator	0:bb348c97df44	441	((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream6)) ? LL_DMA_STREAM_6 : \
lypinator	0:bb348c97df44	442	((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream6)) ? LL_DMA_STREAM_6 : \
lypinator	0:bb348c97df44	443	LL_DMA_STREAM_7)
lypinator	0:bb348c97df44	444
lypinator	0:bb348c97df44	445	/**
lypinator	0:bb348c97df44	446	* @brief Convert DMA Instance DMAx and LL_DMA_STREAM_y into DMAx_Streamy
lypinator	0:bb348c97df44	447	* @param __DMA_INSTANCE__ DMAx
lypinator	0:bb348c97df44	448	* @param __STREAM__ LL_DMA_STREAM_y
lypinator	0:bb348c97df44	449	* @retval DMAx_Streamy
lypinator	0:bb348c97df44	450	*/
lypinator	0:bb348c97df44	451	#define __LL_DMA_GET_STREAM_INSTANCE(__DMA_INSTANCE__, __STREAM__) \
lypinator	0:bb348c97df44	452	((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_0))) ? DMA1_Stream0 : \
lypinator	0:bb348c97df44	453	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_0))) ? DMA2_Stream0 : \
lypinator	0:bb348c97df44	454	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_1))) ? DMA1_Stream1 : \
lypinator	0:bb348c97df44	455	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_1))) ? DMA2_Stream1 : \
lypinator	0:bb348c97df44	456	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_2))) ? DMA1_Stream2 : \
lypinator	0:bb348c97df44	457	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_2))) ? DMA2_Stream2 : \
lypinator	0:bb348c97df44	458	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_3))) ? DMA1_Stream3 : \
lypinator	0:bb348c97df44	459	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_3))) ? DMA2_Stream3 : \
lypinator	0:bb348c97df44	460	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_4))) ? DMA1_Stream4 : \
lypinator	0:bb348c97df44	461	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_4))) ? DMA2_Stream4 : \
lypinator	0:bb348c97df44	462	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_5))) ? DMA1_Stream5 : \
lypinator	0:bb348c97df44	463	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_5))) ? DMA2_Stream5 : \
lypinator	0:bb348c97df44	464	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_6))) ? DMA1_Stream6 : \
lypinator	0:bb348c97df44	465	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_6))) ? DMA2_Stream6 : \
lypinator	0:bb348c97df44	466	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_7))) ? DMA1_Stream7 : \
lypinator	0:bb348c97df44	467	DMA2_Stream7)
lypinator	0:bb348c97df44	468
lypinator	0:bb348c97df44	469	/**
lypinator	0:bb348c97df44	470	* @}
lypinator	0:bb348c97df44	471	*/
lypinator	0:bb348c97df44	472
lypinator	0:bb348c97df44	473	/**
lypinator	0:bb348c97df44	474	* @}
lypinator	0:bb348c97df44	475	*/
lypinator	0:bb348c97df44	476
lypinator	0:bb348c97df44	477
lypinator	0:bb348c97df44	478	/* Exported functions --------------------------------------------------------*/
lypinator	0:bb348c97df44	479	/** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
lypinator	0:bb348c97df44	480	* @{
lypinator	0:bb348c97df44	481	*/
lypinator	0:bb348c97df44	482
lypinator	0:bb348c97df44	483	/** @defgroup DMA_LL_EF_Configuration Configuration
lypinator	0:bb348c97df44	484	* @{
lypinator	0:bb348c97df44	485	*/
lypinator	0:bb348c97df44	486	/**
lypinator	0:bb348c97df44	487	* @brief Enable DMA stream.
lypinator	0:bb348c97df44	488	* @rmtoll CR EN LL_DMA_EnableStream
lypinator	0:bb348c97df44	489	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	490	* @param Stream This parameter can be one of the following values:
lypinator	0:bb348c97df44	491	* @arg @ref LL_DMA_STREAM_0
lypinator	0:bb348c97df44	492	* @arg @ref LL_DMA_STREAM_1
lypinator	0:bb348c97df44	493	* @arg @ref LL_DMA_STREAM_2
lypinator	0:bb348c97df44	494	* @arg @ref LL_DMA_STREAM_3
lypinator	0:bb348c97df44	495	* @arg @ref LL_DMA_STREAM_4
lypinator	0:bb348c97df44	496	* @arg @ref LL_DMA_STREAM_5
lypinator	0:bb348c97df44	497	* @arg @ref LL_DMA_STREAM_6
lypinator	0:bb348c97df44	498	* @arg @ref LL_DMA_STREAM_7
lypinator	0:bb348c97df44	499	* @retval None
lypinator	0:bb348c97df44	500	*/
lypinator	0:bb348c97df44	501	__STATIC_INLINE void LL_DMA_EnableStream(DMA_TypeDef *DMAx, uint32_t Stream)
lypinator	0:bb348c97df44	502	{
lypinator	0:bb348c97df44	503	SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_EN);
lypinator	0:bb348c97df44	504	}
lypinator	0:bb348c97df44	505
lypinator	0:bb348c97df44	506	/**
lypinator	0:bb348c97df44	507	* @brief Disable DMA stream.
lypinator	0:bb348c97df44	508	* @rmtoll CR EN LL_DMA_DisableStream
lypinator	0:bb348c97df44	509	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	510	* @param Stream This parameter can be one of the following values:
lypinator	0:bb348c97df44	511	* @arg @ref LL_DMA_STREAM_0
lypinator	0:bb348c97df44	512	* @arg @ref LL_DMA_STREAM_1
lypinator	0:bb348c97df44	513	* @arg @ref LL_DMA_STREAM_2
lypinator	0:bb348c97df44	514	* @arg @ref LL_DMA_STREAM_3
lypinator	0:bb348c97df44	515	* @arg @ref LL_DMA_STREAM_4
lypinator	0:bb348c97df44	516	* @arg @ref LL_DMA_STREAM_5
lypinator	0:bb348c97df44	517	* @arg @ref LL_DMA_STREAM_6
lypinator	0:bb348c97df44	518	* @arg @ref LL_DMA_STREAM_7
lypinator	0:bb348c97df44	519	* @retval None
lypinator	0:bb348c97df44	520	*/
lypinator	0:bb348c97df44	521	__STATIC_INLINE void LL_DMA_DisableStream(DMA_TypeDef *DMAx, uint32_t Stream)
lypinator	0:bb348c97df44	522	{
lypinator	0:bb348c97df44	523	CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_EN);
lypinator	0:bb348c97df44	524	}
lypinator	0:bb348c97df44	525
lypinator	0:bb348c97df44	526	/**
lypinator	0:bb348c97df44	527	* @brief Check if DMA stream is enabled or disabled.
lypinator	0:bb348c97df44	528	* @rmtoll CR EN LL_DMA_IsEnabledStream
lypinator	0:bb348c97df44	529	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	530	* @param Stream This parameter can be one of the following values:
lypinator	0:bb348c97df44	531	* @arg @ref LL_DMA_STREAM_0
lypinator	0:bb348c97df44	532	* @arg @ref LL_DMA_STREAM_1
lypinator	0:bb348c97df44	533	* @arg @ref LL_DMA_STREAM_2
lypinator	0:bb348c97df44	534	* @arg @ref LL_DMA_STREAM_3
lypinator	0:bb348c97df44	535	* @arg @ref LL_DMA_STREAM_4
lypinator	0:bb348c97df44	536	* @arg @ref LL_DMA_STREAM_5
lypinator	0:bb348c97df44	537	* @arg @ref LL_DMA_STREAM_6
lypinator	0:bb348c97df44	538	* @arg @ref LL_DMA_STREAM_7
lypinator	0:bb348c97df44	539	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	540	*/
lypinator	0:bb348c97df44	541	__STATIC_INLINE uint32_t LL_DMA_IsEnabledStream(DMA_TypeDef *DMAx, uint32_t Stream)
lypinator	0:bb348c97df44	542	{
lypinator	0:bb348c97df44	543	return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_EN) == (DMA_SxCR_EN));
lypinator	0:bb348c97df44	544	}
lypinator	0:bb348c97df44	545
lypinator	0:bb348c97df44	546	/**
lypinator	0:bb348c97df44	547	* @brief Configure all parameters linked to DMA transfer.
lypinator	0:bb348c97df44	548	* @rmtoll CR DIR LL_DMA_ConfigTransfer\n
lypinator	0:bb348c97df44	549	* CR CIRC LL_DMA_ConfigTransfer\n
lypinator	0:bb348c97df44	550	* CR PINC LL_DMA_ConfigTransfer\n
lypinator	0:bb348c97df44	551	* CR MINC LL_DMA_ConfigTransfer\n
lypinator	0:bb348c97df44	552	* CR PSIZE LL_DMA_ConfigTransfer\n
lypinator	0:bb348c97df44	553	* CR MSIZE LL_DMA_ConfigTransfer\n
lypinator	0:bb348c97df44	554	* CR PL LL_DMA_ConfigTransfer\n
lypinator	0:bb348c97df44	555	* CR PFCTRL LL_DMA_ConfigTransfer
lypinator	0:bb348c97df44	556	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	557	* @param Stream This parameter can be one of the following values:
lypinator	0:bb348c97df44	558	* @arg @ref LL_DMA_STREAM_0
lypinator	0:bb348c97df44	559	* @arg @ref LL_DMA_STREAM_1
lypinator	0:bb348c97df44	560	* @arg @ref LL_DMA_STREAM_2
lypinator	0:bb348c97df44	561	* @arg @ref LL_DMA_STREAM_3
lypinator	0:bb348c97df44	562	* @arg @ref LL_DMA_STREAM_4
lypinator	0:bb348c97df44	563	* @arg @ref LL_DMA_STREAM_5
lypinator	0:bb348c97df44	564	* @arg @ref LL_DMA_STREAM_6
lypinator	0:bb348c97df44	565	* @arg @ref LL_DMA_STREAM_7
lypinator	0:bb348c97df44	566	* @param Configuration This parameter must be a combination of all the following values:
lypinator	0:bb348c97df44	567	* @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
lypinator	0:bb348c97df44	568	* @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR or @ref LL_DMA_MODE_PFCTRL
lypinator	0:bb348c97df44	569	* @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT
lypinator	0:bb348c97df44	570	* @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT
lypinator	0:bb348c97df44	571	* @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD
lypinator	0:bb348c97df44	572	* @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD
lypinator	0:bb348c97df44	573	* @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH
lypinator	0:bb348c97df44	574	*@retval None
lypinator	0:bb348c97df44	575	*/
lypinator	0:bb348c97df44	576	__STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Configuration)
lypinator	0:bb348c97df44	577	{
lypinator	0:bb348c97df44	578	MODIFY_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR,
lypinator	0:bb348c97df44	579	DMA_SxCR_DIR \| DMA_SxCR_CIRC \| DMA_SxCR_PINC \| DMA_SxCR_MINC \| DMA_SxCR_PSIZE \| DMA_SxCR_MSIZE \| DMA_SxCR_PL \| DMA_SxCR_PFCTRL,
lypinator	0:bb348c97df44	580	Configuration);
lypinator	0:bb348c97df44	581	}
lypinator	0:bb348c97df44	582
lypinator	0:bb348c97df44	583	/**
lypinator	0:bb348c97df44	584	* @brief Set Data transfer direction (read from peripheral or from memory).
lypinator	0:bb348c97df44	585	* @rmtoll CR DIR LL_DMA_SetDataTransferDirection
lypinator	0:bb348c97df44	586	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	587	* @param Stream This parameter can be one of the following values:
lypinator	0:bb348c97df44	588	* @arg @ref LL_DMA_STREAM_0
lypinator	0:bb348c97df44	589	* @arg @ref LL_DMA_STREAM_1
lypinator	0:bb348c97df44	590	* @arg @ref LL_DMA_STREAM_2
lypinator	0:bb348c97df44	591	* @arg @ref LL_DMA_STREAM_3
lypinator	0:bb348c97df44	592	* @arg @ref LL_DMA_STREAM_4
lypinator	0:bb348c97df44	593	* @arg @ref LL_DMA_STREAM_5
lypinator	0:bb348c97df44	594	* @arg @ref LL_DMA_STREAM_6
lypinator	0:bb348c97df44	595	* @arg @ref LL_DMA_STREAM_7
lypinator	0:bb348c97df44	596	* @param Direction This parameter can be one of the following values:
lypinator	0:bb348c97df44	597	* @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
lypinator	0:bb348c97df44	598	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
lypinator	0:bb348c97df44	599	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
lypinator	0:bb348c97df44	600	* @retval None
lypinator	0:bb348c97df44	601	*/
lypinator	0:bb348c97df44	602	__STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Direction)
lypinator	0:bb348c97df44	603	{
lypinator	0:bb348c97df44	604	MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DIR, Direction);
lypinator	0:bb348c97df44	605	}
lypinator	0:bb348c97df44	606
lypinator	0:bb348c97df44	607	/**
lypinator	0:bb348c97df44	608	* @brief Get Data transfer direction (read from peripheral or from memory).
lypinator	0:bb348c97df44	609	* @rmtoll CR DIR LL_DMA_GetDataTransferDirection
lypinator	0:bb348c97df44	610	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	611	* @param Stream This parameter can be one of the following values:
lypinator	0:bb348c97df44	612	* @arg @ref LL_DMA_STREAM_0
lypinator	0:bb348c97df44	613	* @arg @ref LL_DMA_STREAM_1
lypinator	0:bb348c97df44	614	* @arg @ref LL_DMA_STREAM_2
lypinator	0:bb348c97df44	615	* @arg @ref LL_DMA_STREAM_3
lypinator	0:bb348c97df44	616	* @arg @ref LL_DMA_STREAM_4
lypinator	0:bb348c97df44	617	* @arg @ref LL_DMA_STREAM_5
lypinator	0:bb348c97df44	618	* @arg @ref LL_DMA_STREAM_6
lypinator	0:bb348c97df44	619	* @arg @ref LL_DMA_STREAM_7
lypinator	0:bb348c97df44	620	* @retval Returned value can be one of the following values:
lypinator	0:bb348c97df44	621	* @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
lypinator	0:bb348c97df44	622	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
lypinator	0:bb348c97df44	623	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
lypinator	0:bb348c97df44	624	*/
lypinator	0:bb348c97df44	625	__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream)
lypinator	0:bb348c97df44	626	{
lypinator	0:bb348c97df44	627	return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DIR));
lypinator	0:bb348c97df44	628	}
lypinator	0:bb348c97df44	629
lypinator	0:bb348c97df44	630	/**
lypinator	0:bb348c97df44	631	* @brief Set DMA mode normal, circular or peripheral flow control.
lypinator	0:bb348c97df44	632	* @rmtoll CR CIRC LL_DMA_SetMode\n
lypinator	0:bb348c97df44	633	* CR PFCTRL LL_DMA_SetMode
lypinator	0:bb348c97df44	634	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	635	* @param Stream This parameter can be one of the following values:
lypinator	0:bb348c97df44	636	* @arg @ref LL_DMA_STREAM_0
lypinator	0:bb348c97df44	637	* @arg @ref LL_DMA_STREAM_1
lypinator	0:bb348c97df44	638	* @arg @ref LL_DMA_STREAM_2
lypinator	0:bb348c97df44	639	* @arg @ref LL_DMA_STREAM_3
lypinator	0:bb348c97df44	640	* @arg @ref LL_DMA_STREAM_4
lypinator	0:bb348c97df44	641	* @arg @ref LL_DMA_STREAM_5
lypinator	0:bb348c97df44	642	* @arg @ref LL_DMA_STREAM_6
lypinator	0:bb348c97df44	643	* @arg @ref LL_DMA_STREAM_7
lypinator	0:bb348c97df44	644	* @param Mode This parameter can be one of the following values:
lypinator	0:bb348c97df44	645	* @arg @ref LL_DMA_MODE_NORMAL
lypinator	0:bb348c97df44	646	* @arg @ref LL_DMA_MODE_CIRCULAR
lypinator	0:bb348c97df44	647	* @arg @ref LL_DMA_MODE_PFCTRL
lypinator	0:bb348c97df44	648	* @retval None
lypinator	0:bb348c97df44	649	*/
lypinator	0:bb348c97df44	650	__STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mode)
lypinator	0:bb348c97df44	651	{
lypinator	0:bb348c97df44	652	MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CIRC \| DMA_SxCR_PFCTRL, Mode);
lypinator	0:bb348c97df44	653	}
lypinator	0:bb348c97df44	654
lypinator	0:bb348c97df44	655	/**
lypinator	0:bb348c97df44	656	* @brief Get DMA mode normal, circular or peripheral flow control.
lypinator	0:bb348c97df44	657	* @rmtoll CR CIRC LL_DMA_GetMode\n
lypinator	0:bb348c97df44	658	* CR PFCTRL LL_DMA_GetMode
lypinator	0:bb348c97df44	659	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	660	* @param Stream This parameter can be one of the following values:
lypinator	0:bb348c97df44	661	* @arg @ref LL_DMA_STREAM_0
lypinator	0:bb348c97df44	662	* @arg @ref LL_DMA_STREAM_1
lypinator	0:bb348c97df44	663	* @arg @ref LL_DMA_STREAM_2
lypinator	0:bb348c97df44	664	* @arg @ref LL_DMA_STREAM_3
lypinator	0:bb348c97df44	665	* @arg @ref LL_DMA_STREAM_4
lypinator	0:bb348c97df44	666	* @arg @ref LL_DMA_STREAM_5
lypinator	0:bb348c97df44	667	* @arg @ref LL_DMA_STREAM_6
lypinator	0:bb348c97df44	668	* @arg @ref LL_DMA_STREAM_7
lypinator	0:bb348c97df44	669	* @retval Returned value can be one of the following values:
lypinator	0:bb348c97df44	670	* @arg @ref LL_DMA_MODE_NORMAL
lypinator	0:bb348c97df44	671	* @arg @ref LL_DMA_MODE_CIRCULAR
lypinator	0:bb348c97df44	672	* @arg @ref LL_DMA_MODE_PFCTRL
lypinator	0:bb348c97df44	673	*/
lypinator	0:bb348c97df44	674	__STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Stream)
lypinator	0:bb348c97df44	675	{
lypinator	0:bb348c97df44	676	return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CIRC \| DMA_SxCR_PFCTRL));
lypinator	0:bb348c97df44	677	}
lypinator	0:bb348c97df44	678
lypinator	0:bb348c97df44	679	/**
lypinator	0:bb348c97df44	680	* @brief Set Peripheral increment mode.
lypinator	0:bb348c97df44	681	* @rmtoll CR PINC LL_DMA_SetPeriphIncMode
lypinator	0:bb348c97df44	682	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	683	* @param Stream This parameter can be one of the following values:
lypinator	0:bb348c97df44	684	* @arg @ref LL_DMA_STREAM_0
lypinator	0:bb348c97df44	685	* @arg @ref LL_DMA_STREAM_1
lypinator	0:bb348c97df44	686	* @arg @ref LL_DMA_STREAM_2
lypinator	0:bb348c97df44	687	* @arg @ref LL_DMA_STREAM_3
lypinator	0:bb348c97df44	688	* @arg @ref LL_DMA_STREAM_4
lypinator	0:bb348c97df44	689	* @arg @ref LL_DMA_STREAM_5
lypinator	0:bb348c97df44	690	* @arg @ref LL_DMA_STREAM_6
lypinator	0:bb348c97df44	691	* @arg @ref LL_DMA_STREAM_7
lypinator	0:bb348c97df44	692	* @param IncrementMode This parameter can be one of the following values:
lypinator	0:bb348c97df44	693	* @arg @ref LL_DMA_PERIPH_NOINCREMENT
lypinator	0:bb348c97df44	694	* @arg @ref LL_DMA_PERIPH_INCREMENT
lypinator	0:bb348c97df44	695	* @retval None
lypinator	0:bb348c97df44	696	*/
lypinator	0:bb348c97df44	697	__STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode)
lypinator	0:bb348c97df44	698	{
lypinator	0:bb348c97df44	699	MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINC, IncrementMode);
lypinator	0:bb348c97df44	700	}
lypinator	0:bb348c97df44	701
lypinator	0:bb348c97df44	702	/**
lypinator	0:bb348c97df44	703	* @brief Get Peripheral increment mode.
lypinator	0:bb348c97df44	704	* @rmtoll CR PINC LL_DMA_GetPeriphIncMode
lypinator	0:bb348c97df44	705	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	706	* @param Stream This parameter can be one of the following values:
lypinator	0:bb348c97df44	707	* @arg @ref LL_DMA_STREAM_0
lypinator	0:bb348c97df44	708	* @arg @ref LL_DMA_STREAM_1
lypinator	0:bb348c97df44	709	* @arg @ref LL_DMA_STREAM_2
lypinator	0:bb348c97df44	710	* @arg @ref LL_DMA_STREAM_3
lypinator	0:bb348c97df44	711	* @arg @ref LL_DMA_STREAM_4
lypinator	0:bb348c97df44	712	* @arg @ref LL_DMA_STREAM_5
lypinator	0:bb348c97df44	713	* @arg @ref LL_DMA_STREAM_6
lypinator	0:bb348c97df44	714	* @arg @ref LL_DMA_STREAM_7
lypinator	0:bb348c97df44	715	* @retval Returned value can be one of the following values:
lypinator	0:bb348c97df44	716	* @arg @ref LL_DMA_PERIPH_NOINCREMENT
lypinator	0:bb348c97df44	717	* @arg @ref LL_DMA_PERIPH_INCREMENT
lypinator	0:bb348c97df44	718	*/
lypinator	0:bb348c97df44	719	__STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream)
lypinator	0:bb348c97df44	720	{
lypinator	0:bb348c97df44	721	return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINC));
lypinator	0:bb348c97df44	722	}
lypinator	0:bb348c97df44	723
lypinator	0:bb348c97df44	724	/**
lypinator	0:bb348c97df44	725	* @brief Set Memory increment mode.
lypinator	0:bb348c97df44	726	* @rmtoll CR MINC LL_DMA_SetMemoryIncMode
lypinator	0:bb348c97df44	727	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	728	* @param Stream This parameter can be one of the following values:
lypinator	0:bb348c97df44	729	* @arg @ref LL_DMA_STREAM_0
lypinator	0:bb348c97df44	730	* @arg @ref LL_DMA_STREAM_1
lypinator	0:bb348c97df44	731	* @arg @ref LL_DMA_STREAM_2
lypinator	0:bb348c97df44	732	* @arg @ref LL_DMA_STREAM_3
lypinator	0:bb348c97df44	733	* @arg @ref LL_DMA_STREAM_4
lypinator	0:bb348c97df44	734	* @arg @ref LL_DMA_STREAM_5
lypinator	0:bb348c97df44	735	* @arg @ref LL_DMA_STREAM_6
lypinator	0:bb348c97df44	736	* @arg @ref LL_DMA_STREAM_7
lypinator	0:bb348c97df44	737	* @param IncrementMode This parameter can be one of the following values:
lypinator	0:bb348c97df44	738	* @arg @ref LL_DMA_MEMORY_NOINCREMENT
lypinator	0:bb348c97df44	739	* @arg @ref LL_DMA_MEMORY_INCREMENT
lypinator	0:bb348c97df44	740	* @retval None
lypinator	0:bb348c97df44	741	*/
lypinator	0:bb348c97df44	742	__STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode)
lypinator	0:bb348c97df44	743	{
lypinator	0:bb348c97df44	744	MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MINC, IncrementMode);
lypinator	0:bb348c97df44	745	}
lypinator	0:bb348c97df44	746
lypinator	0:bb348c97df44	747	/**
lypinator	0:bb348c97df44	748	* @brief Get Memory increment mode.
lypinator	0:bb348c97df44	749	* @rmtoll CR MINC LL_DMA_GetMemoryIncMode
lypinator	0:bb348c97df44	750	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	751	* @param Stream This parameter can be one of the following values:
lypinator	0:bb348c97df44	752	* @arg @ref LL_DMA_STREAM_0
lypinator	0:bb348c97df44	753	* @arg @ref LL_DMA_STREAM_1
lypinator	0:bb348c97df44	754	* @arg @ref LL_DMA_STREAM_2
lypinator	0:bb348c97df44	755	* @arg @ref LL_DMA_STREAM_3
lypinator	0:bb348c97df44	756	* @arg @ref LL_DMA_STREAM_4
lypinator	0:bb348c97df44	757	* @arg @ref LL_DMA_STREAM_5
lypinator	0:bb348c97df44	758	* @arg @ref LL_DMA_STREAM_6
lypinator	0:bb348c97df44	759	* @arg @ref LL_DMA_STREAM_7
lypinator	0:bb348c97df44	760	* @retval Returned value can be one of the following values:
lypinator	0:bb348c97df44	761	* @arg @ref LL_DMA_MEMORY_NOINCREMENT
lypinator	0:bb348c97df44	762	* @arg @ref LL_DMA_MEMORY_INCREMENT
lypinator	0:bb348c97df44	763	*/
lypinator	0:bb348c97df44	764	__STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream)
lypinator	0:bb348c97df44	765	{
lypinator	0:bb348c97df44	766	return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MINC));
lypinator	0:bb348c97df44	767	}
lypinator	0:bb348c97df44	768
lypinator	0:bb348c97df44	769	/**
lypinator	0:bb348c97df44	770	* @brief Set Peripheral size.
lypinator	0:bb348c97df44	771	* @rmtoll CR PSIZE LL_DMA_SetPeriphSize
lypinator	0:bb348c97df44	772	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	773	* @param Stream This parameter can be one of the following values:
lypinator	0:bb348c97df44	774	* @arg @ref LL_DMA_STREAM_0
lypinator	0:bb348c97df44	775	* @arg @ref LL_DMA_STREAM_1
lypinator	0:bb348c97df44	776	* @arg @ref LL_DMA_STREAM_2
lypinator	0:bb348c97df44	777	* @arg @ref LL_DMA_STREAM_3
lypinator	0:bb348c97df44	778	* @arg @ref LL_DMA_STREAM_4
lypinator	0:bb348c97df44	779	* @arg @ref LL_DMA_STREAM_5
lypinator	0:bb348c97df44	780	* @arg @ref LL_DMA_STREAM_6
lypinator	0:bb348c97df44	781	* @arg @ref LL_DMA_STREAM_7
lypinator	0:bb348c97df44	782	* @param Size This parameter can be one of the following values:
lypinator	0:bb348c97df44	783	* @arg @ref LL_DMA_PDATAALIGN_BYTE
lypinator	0:bb348c97df44	784	* @arg @ref LL_DMA_PDATAALIGN_HALFWORD
lypinator	0:bb348c97df44	785	* @arg @ref LL_DMA_PDATAALIGN_WORD
lypinator	0:bb348c97df44	786	* @retval None
lypinator	0:bb348c97df44	787	*/
lypinator	0:bb348c97df44	788	__STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size)
lypinator	0:bb348c97df44	789	{
lypinator	0:bb348c97df44	790	MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PSIZE, Size);
lypinator	0:bb348c97df44	791	}
lypinator	0:bb348c97df44	792
lypinator	0:bb348c97df44	793	/**
lypinator	0:bb348c97df44	794	* @brief Get Peripheral size.
lypinator	0:bb348c97df44	795	* @rmtoll CR PSIZE LL_DMA_GetPeriphSize
lypinator	0:bb348c97df44	796	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	797	* @param Stream This parameter can be one of the following values:
lypinator	0:bb348c97df44	798	* @arg @ref LL_DMA_STREAM_0
lypinator	0:bb348c97df44	799	* @arg @ref LL_DMA_STREAM_1
lypinator	0:bb348c97df44	800	* @arg @ref LL_DMA_STREAM_2
lypinator	0:bb348c97df44	801	* @arg @ref LL_DMA_STREAM_3
lypinator	0:bb348c97df44	802	* @arg @ref LL_DMA_STREAM_4
lypinator	0:bb348c97df44	803	* @arg @ref LL_DMA_STREAM_5
lypinator	0:bb348c97df44	804	* @arg @ref LL_DMA_STREAM_6
lypinator	0:bb348c97df44	805	* @arg @ref LL_DMA_STREAM_7
lypinator	0:bb348c97df44	806	* @retval Returned value can be one of the following values:
lypinator	0:bb348c97df44	807	* @arg @ref LL_DMA_PDATAALIGN_BYTE
lypinator	0:bb348c97df44	808	* @arg @ref LL_DMA_PDATAALIGN_HALFWORD
lypinator	0:bb348c97df44	809	* @arg @ref LL_DMA_PDATAALIGN_WORD
lypinator	0:bb348c97df44	810	*/
lypinator	0:bb348c97df44	811	__STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream)
lypinator	0:bb348c97df44	812	{
lypinator	0:bb348c97df44	813	return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PSIZE));
lypinator	0:bb348c97df44	814	}
lypinator	0:bb348c97df44	815
lypinator	0:bb348c97df44	816	/**
lypinator	0:bb348c97df44	817	* @brief Set Memory size.
lypinator	0:bb348c97df44	818	* @rmtoll CR MSIZE LL_DMA_SetMemorySize
lypinator	0:bb348c97df44	819	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	820	* @param Stream This parameter can be one of the following values:
lypinator	0:bb348c97df44	821	* @arg @ref LL_DMA_STREAM_0
lypinator	0:bb348c97df44	822	* @arg @ref LL_DMA_STREAM_1
lypinator	0:bb348c97df44	823	* @arg @ref LL_DMA_STREAM_2
lypinator	0:bb348c97df44	824	* @arg @ref LL_DMA_STREAM_3
lypinator	0:bb348c97df44	825	* @arg @ref LL_DMA_STREAM_4
lypinator	0:bb348c97df44	826	* @arg @ref LL_DMA_STREAM_5
lypinator	0:bb348c97df44	827	* @arg @ref LL_DMA_STREAM_6
lypinator	0:bb348c97df44	828	* @arg @ref LL_DMA_STREAM_7
lypinator	0:bb348c97df44	829	* @param Size This parameter can be one of the following values:
lypinator	0:bb348c97df44	830	* @arg @ref LL_DMA_MDATAALIGN_BYTE
lypinator	0:bb348c97df44	831	* @arg @ref LL_DMA_MDATAALIGN_HALFWORD
lypinator	0:bb348c97df44	832	* @arg @ref LL_DMA_MDATAALIGN_WORD
lypinator	0:bb348c97df44	833	* @retval None
lypinator	0:bb348c97df44	834	*/
lypinator	0:bb348c97df44	835	__STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size)
lypinator	0:bb348c97df44	836	{
lypinator	0:bb348c97df44	837	MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MSIZE, Size);
lypinator	0:bb348c97df44	838	}
lypinator	0:bb348c97df44	839
lypinator	0:bb348c97df44	840	/**
lypinator	0:bb348c97df44	841	* @brief Get Memory size.
lypinator	0:bb348c97df44	842	* @rmtoll CR MSIZE LL_DMA_GetMemorySize
lypinator	0:bb348c97df44	843	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	844	* @param Stream This parameter can be one of the following values:
lypinator	0:bb348c97df44	845	* @arg @ref LL_DMA_STREAM_0
lypinator	0:bb348c97df44	846	* @arg @ref LL_DMA_STREAM_1
lypinator	0:bb348c97df44	847	* @arg @ref LL_DMA_STREAM_2
lypinator	0:bb348c97df44	848	* @arg @ref LL_DMA_STREAM_3
lypinator	0:bb348c97df44	849	* @arg @ref LL_DMA_STREAM_4
lypinator	0:bb348c97df44	850	* @arg @ref LL_DMA_STREAM_5
lypinator	0:bb348c97df44	851	* @arg @ref LL_DMA_STREAM_6
lypinator	0:bb348c97df44	852	* @arg @ref LL_DMA_STREAM_7
lypinator	0:bb348c97df44	853	* @retval Returned value can be one of the following values:
lypinator	0:bb348c97df44	854	* @arg @ref LL_DMA_MDATAALIGN_BYTE
lypinator	0:bb348c97df44	855	* @arg @ref LL_DMA_MDATAALIGN_HALFWORD
lypinator	0:bb348c97df44	856	* @arg @ref LL_DMA_MDATAALIGN_WORD
lypinator	0:bb348c97df44	857	*/
lypinator	0:bb348c97df44	858	__STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream)
lypinator	0:bb348c97df44	859	{
lypinator	0:bb348c97df44	860	return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MSIZE));
lypinator	0:bb348c97df44	861	}
lypinator	0:bb348c97df44	862
lypinator	0:bb348c97df44	863	/**
lypinator	0:bb348c97df44	864	* @brief Set Peripheral increment offset size.
lypinator	0:bb348c97df44	865	* @rmtoll CR PINCOS LL_DMA_SetIncOffsetSize
lypinator	0:bb348c97df44	866	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	867	* @param Stream This parameter can be one of the following values:
lypinator	0:bb348c97df44	868	* @arg @ref LL_DMA_STREAM_0
lypinator	0:bb348c97df44	869	* @arg @ref LL_DMA_STREAM_1
lypinator	0:bb348c97df44	870	* @arg @ref LL_DMA_STREAM_2
lypinator	0:bb348c97df44	871	* @arg @ref LL_DMA_STREAM_3
lypinator	0:bb348c97df44	872	* @arg @ref LL_DMA_STREAM_4
lypinator	0:bb348c97df44	873	* @arg @ref LL_DMA_STREAM_5
lypinator	0:bb348c97df44	874	* @arg @ref LL_DMA_STREAM_6
lypinator	0:bb348c97df44	875	* @arg @ref LL_DMA_STREAM_7
lypinator	0:bb348c97df44	876	* @param OffsetSize This parameter can be one of the following values:
lypinator	0:bb348c97df44	877	* @arg @ref LL_DMA_OFFSETSIZE_PSIZE
lypinator	0:bb348c97df44	878	* @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4
lypinator	0:bb348c97df44	879	* @retval None
lypinator	0:bb348c97df44	880	*/
lypinator	0:bb348c97df44	881	__STATIC_INLINE void LL_DMA_SetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t OffsetSize)
lypinator	0:bb348c97df44	882	{
lypinator	0:bb348c97df44	883	MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINCOS, OffsetSize);
lypinator	0:bb348c97df44	884	}
lypinator	0:bb348c97df44	885
lypinator	0:bb348c97df44	886	/**
lypinator	0:bb348c97df44	887	* @brief Get Peripheral increment offset size.
lypinator	0:bb348c97df44	888	* @rmtoll CR PINCOS LL_DMA_GetIncOffsetSize
lypinator	0:bb348c97df44	889	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	890	* @param Stream This parameter can be one of the following values:
lypinator	0:bb348c97df44	891	* @arg @ref LL_DMA_STREAM_0
lypinator	0:bb348c97df44	892	* @arg @ref LL_DMA_STREAM_1
lypinator	0:bb348c97df44	893	* @arg @ref LL_DMA_STREAM_2
lypinator	0:bb348c97df44	894	* @arg @ref LL_DMA_STREAM_3
lypinator	0:bb348c97df44	895	* @arg @ref LL_DMA_STREAM_4
lypinator	0:bb348c97df44	896	* @arg @ref LL_DMA_STREAM_5
lypinator	0:bb348c97df44	897	* @arg @ref LL_DMA_STREAM_6
lypinator	0:bb348c97df44	898	* @arg @ref LL_DMA_STREAM_7
lypinator	0:bb348c97df44	899	* @retval Returned value can be one of the following values:
lypinator	0:bb348c97df44	900	* @arg @ref LL_DMA_OFFSETSIZE_PSIZE
lypinator	0:bb348c97df44	901	* @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4
lypinator	0:bb348c97df44	902	*/
lypinator	0:bb348c97df44	903	__STATIC_INLINE uint32_t LL_DMA_GetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream)
lypinator	0:bb348c97df44	904	{
lypinator	0:bb348c97df44	905	return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINCOS));
lypinator	0:bb348c97df44	906	}
lypinator	0:bb348c97df44	907
lypinator	0:bb348c97df44	908	/**
lypinator	0:bb348c97df44	909	* @brief Set Stream priority level.
lypinator	0:bb348c97df44	910	* @rmtoll CR PL LL_DMA_SetStreamPriorityLevel
lypinator	0:bb348c97df44	911	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	912	* @param Stream This parameter can be one of the following values:
lypinator	0:bb348c97df44	913	* @arg @ref LL_DMA_STREAM_0
lypinator	0:bb348c97df44	914	* @arg @ref LL_DMA_STREAM_1
lypinator	0:bb348c97df44	915	* @arg @ref LL_DMA_STREAM_2
lypinator	0:bb348c97df44	916	* @arg @ref LL_DMA_STREAM_3
lypinator	0:bb348c97df44	917	* @arg @ref LL_DMA_STREAM_4
lypinator	0:bb348c97df44	918	* @arg @ref LL_DMA_STREAM_5
lypinator	0:bb348c97df44	919	* @arg @ref LL_DMA_STREAM_6
lypinator	0:bb348c97df44	920	* @arg @ref LL_DMA_STREAM_7
lypinator	0:bb348c97df44	921	* @param Priority This parameter can be one of the following values:
lypinator	0:bb348c97df44	922	* @arg @ref LL_DMA_PRIORITY_LOW
lypinator	0:bb348c97df44	923	* @arg @ref LL_DMA_PRIORITY_MEDIUM
lypinator	0:bb348c97df44	924	* @arg @ref LL_DMA_PRIORITY_HIGH
lypinator	0:bb348c97df44	925	* @arg @ref LL_DMA_PRIORITY_VERYHIGH
lypinator	0:bb348c97df44	926	* @retval None
lypinator	0:bb348c97df44	927	*/
lypinator	0:bb348c97df44	928	__STATIC_INLINE void LL_DMA_SetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Priority)
lypinator	0:bb348c97df44	929	{
lypinator	0:bb348c97df44	930	MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PL, Priority);
lypinator	0:bb348c97df44	931	}
lypinator	0:bb348c97df44	932
lypinator	0:bb348c97df44	933	/**
lypinator	0:bb348c97df44	934	* @brief Get Stream priority level.
lypinator	0:bb348c97df44	935	* @rmtoll CR PL LL_DMA_GetStreamPriorityLevel
lypinator	0:bb348c97df44	936	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	937	* @param Stream This parameter can be one of the following values:
lypinator	0:bb348c97df44	938	* @arg @ref LL_DMA_STREAM_0
lypinator	0:bb348c97df44	939	* @arg @ref LL_DMA_STREAM_1
lypinator	0:bb348c97df44	940	* @arg @ref LL_DMA_STREAM_2
lypinator	0:bb348c97df44	941	* @arg @ref LL_DMA_STREAM_3
lypinator	0:bb348c97df44	942	* @arg @ref LL_DMA_STREAM_4
lypinator	0:bb348c97df44	943	* @arg @ref LL_DMA_STREAM_5
lypinator	0:bb348c97df44	944	* @arg @ref LL_DMA_STREAM_6
lypinator	0:bb348c97df44	945	* @arg @ref LL_DMA_STREAM_7
lypinator	0:bb348c97df44	946	* @retval Returned value can be one of the following values:
lypinator	0:bb348c97df44	947	* @arg @ref LL_DMA_PRIORITY_LOW
lypinator	0:bb348c97df44	948	* @arg @ref LL_DMA_PRIORITY_MEDIUM
lypinator	0:bb348c97df44	949	* @arg @ref LL_DMA_PRIORITY_HIGH
lypinator	0:bb348c97df44	950	* @arg @ref LL_DMA_PRIORITY_VERYHIGH
lypinator	0:bb348c97df44	951	*/
lypinator	0:bb348c97df44	952	__STATIC_INLINE uint32_t LL_DMA_GetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream)
lypinator	0:bb348c97df44	953	{
lypinator	0:bb348c97df44	954	return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PL));
lypinator	0:bb348c97df44	955	}
lypinator	0:bb348c97df44	956
lypinator	0:bb348c97df44	957	/**
lypinator	0:bb348c97df44	958	* @brief Set Number of data to transfer.
lypinator	0:bb348c97df44	959	* @rmtoll NDTR NDT LL_DMA_SetDataLength
lypinator	0:bb348c97df44	960	* @note This action has no effect if
lypinator	0:bb348c97df44	961	* stream is enabled.
lypinator	0:bb348c97df44	962	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	963	* @param Stream This parameter can be one of the following values:
lypinator	0:bb348c97df44	964	* @arg @ref LL_DMA_STREAM_0
lypinator	0:bb348c97df44	965	* @arg @ref LL_DMA_STREAM_1
lypinator	0:bb348c97df44	966	* @arg @ref LL_DMA_STREAM_2
lypinator	0:bb348c97df44	967	* @arg @ref LL_DMA_STREAM_3
lypinator	0:bb348c97df44	968	* @arg @ref LL_DMA_STREAM_4
lypinator	0:bb348c97df44	969	* @arg @ref LL_DMA_STREAM_5
lypinator	0:bb348c97df44	970	* @arg @ref LL_DMA_STREAM_6
lypinator	0:bb348c97df44	971	* @arg @ref LL_DMA_STREAM_7
lypinator	0:bb348c97df44	972	* @param NbData Between 0 to 0xFFFFFFFF
lypinator	0:bb348c97df44	973	* @retval None
lypinator	0:bb348c97df44	974	*/
lypinator	0:bb348c97df44	975	__STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t NbData)
lypinator	0:bb348c97df44	976	{
lypinator	0:bb348c97df44	977	MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->NDTR, DMA_SxNDT, NbData);
lypinator	0:bb348c97df44	978	}
lypinator	0:bb348c97df44	979
lypinator	0:bb348c97df44	980	/**
lypinator	0:bb348c97df44	981	* @brief Get Number of data to transfer.
lypinator	0:bb348c97df44	982	* @rmtoll NDTR NDT LL_DMA_GetDataLength
lypinator	0:bb348c97df44	983	* @note Once the stream is enabled, the return value indicate the
lypinator	0:bb348c97df44	984	* remaining bytes to be transmitted.
lypinator	0:bb348c97df44	985	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	986	* @param Stream This parameter can be one of the following values:
lypinator	0:bb348c97df44	987	* @arg @ref LL_DMA_STREAM_0
lypinator	0:bb348c97df44	988	* @arg @ref LL_DMA_STREAM_1
lypinator	0:bb348c97df44	989	* @arg @ref LL_DMA_STREAM_2
lypinator	0:bb348c97df44	990	* @arg @ref LL_DMA_STREAM_3
lypinator	0:bb348c97df44	991	* @arg @ref LL_DMA_STREAM_4
lypinator	0:bb348c97df44	992	* @arg @ref LL_DMA_STREAM_5
lypinator	0:bb348c97df44	993	* @arg @ref LL_DMA_STREAM_6
lypinator	0:bb348c97df44	994	* @arg @ref LL_DMA_STREAM_7
lypinator	0:bb348c97df44	995	* @retval Between 0 to 0xFFFFFFFF
lypinator	0:bb348c97df44	996	*/
lypinator	0:bb348c97df44	997	__STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef* DMAx, uint32_t Stream)
lypinator	0:bb348c97df44	998	{
lypinator	0:bb348c97df44	999	return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->NDTR, DMA_SxNDT));
lypinator	0:bb348c97df44	1000	}
lypinator	0:bb348c97df44	1001
lypinator	0:bb348c97df44	1002	/**
lypinator	0:bb348c97df44	1003	* @brief Select Channel number associated to the Stream.
lypinator	0:bb348c97df44	1004	* @rmtoll CR CHSEL LL_DMA_SetChannelSelection
lypinator	0:bb348c97df44	1005	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	1006	* @param Stream This parameter can be one of the following values:
lypinator	0:bb348c97df44	1007	* @arg @ref LL_DMA_STREAM_0
lypinator	0:bb348c97df44	1008	* @arg @ref LL_DMA_STREAM_1
lypinator	0:bb348c97df44	1009	* @arg @ref LL_DMA_STREAM_2
lypinator	0:bb348c97df44	1010	* @arg @ref LL_DMA_STREAM_3
lypinator	0:bb348c97df44	1011	* @arg @ref LL_DMA_STREAM_4
lypinator	0:bb348c97df44	1012	* @arg @ref LL_DMA_STREAM_5
lypinator	0:bb348c97df44	1013	* @arg @ref LL_DMA_STREAM_6
lypinator	0:bb348c97df44	1014	* @arg @ref LL_DMA_STREAM_7
lypinator	0:bb348c97df44	1015	* @param Channel This parameter can be one of the following values:
lypinator	0:bb348c97df44	1016	* @arg @ref LL_DMA_CHANNEL_0
lypinator	0:bb348c97df44	1017	* @arg @ref LL_DMA_CHANNEL_1
lypinator	0:bb348c97df44	1018	* @arg @ref LL_DMA_CHANNEL_2
lypinator	0:bb348c97df44	1019	* @arg @ref LL_DMA_CHANNEL_3
lypinator	0:bb348c97df44	1020	* @arg @ref LL_DMA_CHANNEL_4
lypinator	0:bb348c97df44	1021	* @arg @ref LL_DMA_CHANNEL_5
lypinator	0:bb348c97df44	1022	* @arg @ref LL_DMA_CHANNEL_6
lypinator	0:bb348c97df44	1023	* @arg @ref LL_DMA_CHANNEL_7
lypinator	0:bb348c97df44	1024	* @retval None
lypinator	0:bb348c97df44	1025	*/
lypinator	0:bb348c97df44	1026	__STATIC_INLINE void LL_DMA_SetChannelSelection(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Channel)
lypinator	0:bb348c97df44	1027	{
lypinator	0:bb348c97df44	1028	MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CHSEL, Channel);
lypinator	0:bb348c97df44	1029	}
lypinator	0:bb348c97df44	1030
lypinator	0:bb348c97df44	1031	/**
lypinator	0:bb348c97df44	1032	* @brief Get the Channel number associated to the Stream.
lypinator	0:bb348c97df44	1033	* @rmtoll CR CHSEL LL_DMA_GetChannelSelection
lypinator	0:bb348c97df44	1034	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	1035	* @param Stream This parameter can be one of the following values:
lypinator	0:bb348c97df44	1036	* @arg @ref LL_DMA_STREAM_0
lypinator	0:bb348c97df44	1037	* @arg @ref LL_DMA_STREAM_1
lypinator	0:bb348c97df44	1038	* @arg @ref LL_DMA_STREAM_2
lypinator	0:bb348c97df44	1039	* @arg @ref LL_DMA_STREAM_3
lypinator	0:bb348c97df44	1040	* @arg @ref LL_DMA_STREAM_4
lypinator	0:bb348c97df44	1041	* @arg @ref LL_DMA_STREAM_5
lypinator	0:bb348c97df44	1042	* @arg @ref LL_DMA_STREAM_6
lypinator	0:bb348c97df44	1043	* @arg @ref LL_DMA_STREAM_7
lypinator	0:bb348c97df44	1044	* @retval Returned value can be one of the following values:
lypinator	0:bb348c97df44	1045	* @arg @ref LL_DMA_CHANNEL_0
lypinator	0:bb348c97df44	1046	* @arg @ref LL_DMA_CHANNEL_1
lypinator	0:bb348c97df44	1047	* @arg @ref LL_DMA_CHANNEL_2
lypinator	0:bb348c97df44	1048	* @arg @ref LL_DMA_CHANNEL_3
lypinator	0:bb348c97df44	1049	* @arg @ref LL_DMA_CHANNEL_4
lypinator	0:bb348c97df44	1050	* @arg @ref LL_DMA_CHANNEL_5
lypinator	0:bb348c97df44	1051	* @arg @ref LL_DMA_CHANNEL_6
lypinator	0:bb348c97df44	1052	* @arg @ref LL_DMA_CHANNEL_7
lypinator	0:bb348c97df44	1053	*/
lypinator	0:bb348c97df44	1054	__STATIC_INLINE uint32_t LL_DMA_GetChannelSelection(DMA_TypeDef *DMAx, uint32_t Stream)
lypinator	0:bb348c97df44	1055	{
lypinator	0:bb348c97df44	1056	return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CHSEL));
lypinator	0:bb348c97df44	1057	}
lypinator	0:bb348c97df44	1058
lypinator	0:bb348c97df44	1059	/**
lypinator	0:bb348c97df44	1060	* @brief Set Memory burst transfer configuration.
lypinator	0:bb348c97df44	1061	* @rmtoll CR MBURST LL_DMA_SetMemoryBurstxfer
lypinator	0:bb348c97df44	1062	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	1063	* @param Stream This parameter can be one of the following values:
lypinator	0:bb348c97df44	1064	* @arg @ref LL_DMA_STREAM_0
lypinator	0:bb348c97df44	1065	* @arg @ref LL_DMA_STREAM_1
lypinator	0:bb348c97df44	1066	* @arg @ref LL_DMA_STREAM_2
lypinator	0:bb348c97df44	1067	* @arg @ref LL_DMA_STREAM_3
lypinator	0:bb348c97df44	1068	* @arg @ref LL_DMA_STREAM_4
lypinator	0:bb348c97df44	1069	* @arg @ref LL_DMA_STREAM_5
lypinator	0:bb348c97df44	1070	* @arg @ref LL_DMA_STREAM_6
lypinator	0:bb348c97df44	1071	* @arg @ref LL_DMA_STREAM_7
lypinator	0:bb348c97df44	1072	* @param Mburst This parameter can be one of the following values:
lypinator	0:bb348c97df44	1073	* @arg @ref LL_DMA_MBURST_SINGLE
lypinator	0:bb348c97df44	1074	* @arg @ref LL_DMA_MBURST_INC4
lypinator	0:bb348c97df44	1075	* @arg @ref LL_DMA_MBURST_INC8
lypinator	0:bb348c97df44	1076	* @arg @ref LL_DMA_MBURST_INC16
lypinator	0:bb348c97df44	1077	* @retval None
lypinator	0:bb348c97df44	1078	*/
lypinator	0:bb348c97df44	1079	__STATIC_INLINE void LL_DMA_SetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mburst)
lypinator	0:bb348c97df44	1080	{
lypinator	0:bb348c97df44	1081	MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MBURST, Mburst);
lypinator	0:bb348c97df44	1082	}
lypinator	0:bb348c97df44	1083
lypinator	0:bb348c97df44	1084	/**
lypinator	0:bb348c97df44	1085	* @brief Get Memory burst transfer configuration.
lypinator	0:bb348c97df44	1086	* @rmtoll CR MBURST LL_DMA_GetMemoryBurstxfer
lypinator	0:bb348c97df44	1087	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	1088	* @param Stream This parameter can be one of the following values:
lypinator	0:bb348c97df44	1089	* @arg @ref LL_DMA_STREAM_0
lypinator	0:bb348c97df44	1090	* @arg @ref LL_DMA_STREAM_1
lypinator	0:bb348c97df44	1091	* @arg @ref LL_DMA_STREAM_2
lypinator	0:bb348c97df44	1092	* @arg @ref LL_DMA_STREAM_3
lypinator	0:bb348c97df44	1093	* @arg @ref LL_DMA_STREAM_4
lypinator	0:bb348c97df44	1094	* @arg @ref LL_DMA_STREAM_5
lypinator	0:bb348c97df44	1095	* @arg @ref LL_DMA_STREAM_6
lypinator	0:bb348c97df44	1096	* @arg @ref LL_DMA_STREAM_7
lypinator	0:bb348c97df44	1097	* @retval Returned value can be one of the following values:
lypinator	0:bb348c97df44	1098	* @arg @ref LL_DMA_MBURST_SINGLE
lypinator	0:bb348c97df44	1099	* @arg @ref LL_DMA_MBURST_INC4
lypinator	0:bb348c97df44	1100	* @arg @ref LL_DMA_MBURST_INC8
lypinator	0:bb348c97df44	1101	* @arg @ref LL_DMA_MBURST_INC16
lypinator	0:bb348c97df44	1102	*/
lypinator	0:bb348c97df44	1103	__STATIC_INLINE uint32_t LL_DMA_GetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream)
lypinator	0:bb348c97df44	1104	{
lypinator	0:bb348c97df44	1105	return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MBURST));
lypinator	0:bb348c97df44	1106	}
lypinator	0:bb348c97df44	1107
lypinator	0:bb348c97df44	1108	/**
lypinator	0:bb348c97df44	1109	* @brief Set Peripheral burst transfer configuration.
lypinator	0:bb348c97df44	1110	* @rmtoll CR PBURST LL_DMA_SetPeriphBurstxfer
lypinator	0:bb348c97df44	1111	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	1112	* @param Stream This parameter can be one of the following values:
lypinator	0:bb348c97df44	1113	* @arg @ref LL_DMA_STREAM_0
lypinator	0:bb348c97df44	1114	* @arg @ref LL_DMA_STREAM_1
lypinator	0:bb348c97df44	1115	* @arg @ref LL_DMA_STREAM_2
lypinator	0:bb348c97df44	1116	* @arg @ref LL_DMA_STREAM_3
lypinator	0:bb348c97df44	1117	* @arg @ref LL_DMA_STREAM_4
lypinator	0:bb348c97df44	1118	* @arg @ref LL_DMA_STREAM_5
lypinator	0:bb348c97df44	1119	* @arg @ref LL_DMA_STREAM_6
lypinator	0:bb348c97df44	1120	* @arg @ref LL_DMA_STREAM_7
lypinator	0:bb348c97df44	1121	* @param Pburst This parameter can be one of the following values:
lypinator	0:bb348c97df44	1122	* @arg @ref LL_DMA_PBURST_SINGLE
lypinator	0:bb348c97df44	1123	* @arg @ref LL_DMA_PBURST_INC4
lypinator	0:bb348c97df44	1124	* @arg @ref LL_DMA_PBURST_INC8
lypinator	0:bb348c97df44	1125	* @arg @ref LL_DMA_PBURST_INC16
lypinator	0:bb348c97df44	1126	* @retval None
lypinator	0:bb348c97df44	1127	*/
lypinator	0:bb348c97df44	1128	__STATIC_INLINE void LL_DMA_SetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Pburst)
lypinator	0:bb348c97df44	1129	{
lypinator	0:bb348c97df44	1130	MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PBURST, Pburst);
lypinator	0:bb348c97df44	1131	}
lypinator	0:bb348c97df44	1132
lypinator	0:bb348c97df44	1133	/**
lypinator	0:bb348c97df44	1134	* @brief Get Peripheral burst transfer configuration.
lypinator	0:bb348c97df44	1135	* @rmtoll CR PBURST LL_DMA_GetPeriphBurstxfer
lypinator	0:bb348c97df44	1136	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	1137	* @param Stream This parameter can be one of the following values:
lypinator	0:bb348c97df44	1138	* @arg @ref LL_DMA_STREAM_0
lypinator	0:bb348c97df44	1139	* @arg @ref LL_DMA_STREAM_1
lypinator	0:bb348c97df44	1140	* @arg @ref LL_DMA_STREAM_2
lypinator	0:bb348c97df44	1141	* @arg @ref LL_DMA_STREAM_3
lypinator	0:bb348c97df44	1142	* @arg @ref LL_DMA_STREAM_4
lypinator	0:bb348c97df44	1143	* @arg @ref LL_DMA_STREAM_5
lypinator	0:bb348c97df44	1144	* @arg @ref LL_DMA_STREAM_6
lypinator	0:bb348c97df44	1145	* @arg @ref LL_DMA_STREAM_7
lypinator	0:bb348c97df44	1146	* @retval Returned value can be one of the following values:
lypinator	0:bb348c97df44	1147	* @arg @ref LL_DMA_PBURST_SINGLE
lypinator	0:bb348c97df44	1148	* @arg @ref LL_DMA_PBURST_INC4
lypinator	0:bb348c97df44	1149	* @arg @ref LL_DMA_PBURST_INC8
lypinator	0:bb348c97df44	1150	* @arg @ref LL_DMA_PBURST_INC16
lypinator	0:bb348c97df44	1151	*/
lypinator	0:bb348c97df44	1152	__STATIC_INLINE uint32_t LL_DMA_GetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream)
lypinator	0:bb348c97df44	1153	{
lypinator	0:bb348c97df44	1154	return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PBURST));
lypinator	0:bb348c97df44	1155	}
lypinator	0:bb348c97df44	1156
lypinator	0:bb348c97df44	1157	/**
lypinator	0:bb348c97df44	1158	* @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0.
lypinator	0:bb348c97df44	1159	* @rmtoll CR CT LL_DMA_SetCurrentTargetMem
lypinator	0:bb348c97df44	1160	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	1161	* @param Stream This parameter can be one of the following values:
lypinator	0:bb348c97df44	1162	* @arg @ref LL_DMA_STREAM_0
lypinator	0:bb348c97df44	1163	* @arg @ref LL_DMA_STREAM_1
lypinator	0:bb348c97df44	1164	* @arg @ref LL_DMA_STREAM_2
lypinator	0:bb348c97df44	1165	* @arg @ref LL_DMA_STREAM_3
lypinator	0:bb348c97df44	1166	* @arg @ref LL_DMA_STREAM_4
lypinator	0:bb348c97df44	1167	* @arg @ref LL_DMA_STREAM_5
lypinator	0:bb348c97df44	1168	* @arg @ref LL_DMA_STREAM_6
lypinator	0:bb348c97df44	1169	* @arg @ref LL_DMA_STREAM_7
lypinator	0:bb348c97df44	1170	* @param CurrentMemory This parameter can be one of the following values:
lypinator	0:bb348c97df44	1171	* @arg @ref LL_DMA_CURRENTTARGETMEM0
lypinator	0:bb348c97df44	1172	* @arg @ref LL_DMA_CURRENTTARGETMEM1
lypinator	0:bb348c97df44	1173	* @retval None
lypinator	0:bb348c97df44	1174	*/
lypinator	0:bb348c97df44	1175	__STATIC_INLINE void LL_DMA_SetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t CurrentMemory)
lypinator	0:bb348c97df44	1176	{
lypinator	0:bb348c97df44	1177	MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CT, CurrentMemory);
lypinator	0:bb348c97df44	1178	}
lypinator	0:bb348c97df44	1179
lypinator	0:bb348c97df44	1180	/**
lypinator	0:bb348c97df44	1181	* @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0.
lypinator	0:bb348c97df44	1182	* @rmtoll CR CT LL_DMA_GetCurrentTargetMem
lypinator	0:bb348c97df44	1183	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	1184	* @param Stream This parameter can be one of the following values:
lypinator	0:bb348c97df44	1185	* @arg @ref LL_DMA_STREAM_0
lypinator	0:bb348c97df44	1186	* @arg @ref LL_DMA_STREAM_1
lypinator	0:bb348c97df44	1187	* @arg @ref LL_DMA_STREAM_2
lypinator	0:bb348c97df44	1188	* @arg @ref LL_DMA_STREAM_3
lypinator	0:bb348c97df44	1189	* @arg @ref LL_DMA_STREAM_4
lypinator	0:bb348c97df44	1190	* @arg @ref LL_DMA_STREAM_5
lypinator	0:bb348c97df44	1191	* @arg @ref LL_DMA_STREAM_6
lypinator	0:bb348c97df44	1192	* @arg @ref LL_DMA_STREAM_7
lypinator	0:bb348c97df44	1193	* @retval Returned value can be one of the following values:
lypinator	0:bb348c97df44	1194	* @arg @ref LL_DMA_CURRENTTARGETMEM0
lypinator	0:bb348c97df44	1195	* @arg @ref LL_DMA_CURRENTTARGETMEM1
lypinator	0:bb348c97df44	1196	*/
lypinator	0:bb348c97df44	1197	__STATIC_INLINE uint32_t LL_DMA_GetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream)
lypinator	0:bb348c97df44	1198	{
lypinator	0:bb348c97df44	1199	return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CT));
lypinator	0:bb348c97df44	1200	}
lypinator	0:bb348c97df44	1201
lypinator	0:bb348c97df44	1202	/**
lypinator	0:bb348c97df44	1203	* @brief Enable the double buffer mode.
lypinator	0:bb348c97df44	1204	* @rmtoll CR DBM LL_DMA_EnableDoubleBufferMode
lypinator	0:bb348c97df44	1205	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	1206	* @param Stream This parameter can be one of the following values:
lypinator	0:bb348c97df44	1207	* @arg @ref LL_DMA_STREAM_0
lypinator	0:bb348c97df44	1208	* @arg @ref LL_DMA_STREAM_1
lypinator	0:bb348c97df44	1209	* @arg @ref LL_DMA_STREAM_2
lypinator	0:bb348c97df44	1210	* @arg @ref LL_DMA_STREAM_3
lypinator	0:bb348c97df44	1211	* @arg @ref LL_DMA_STREAM_4
lypinator	0:bb348c97df44	1212	* @arg @ref LL_DMA_STREAM_5
lypinator	0:bb348c97df44	1213	* @arg @ref LL_DMA_STREAM_6
lypinator	0:bb348c97df44	1214	* @arg @ref LL_DMA_STREAM_7
lypinator	0:bb348c97df44	1215	* @retval None
lypinator	0:bb348c97df44	1216	*/
lypinator	0:bb348c97df44	1217	__STATIC_INLINE void LL_DMA_EnableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream)
lypinator	0:bb348c97df44	1218	{
lypinator	0:bb348c97df44	1219	SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DBM);
lypinator	0:bb348c97df44	1220	}
lypinator	0:bb348c97df44	1221
lypinator	0:bb348c97df44	1222	/**
lypinator	0:bb348c97df44	1223	* @brief Disable the double buffer mode.
lypinator	0:bb348c97df44	1224	* @rmtoll CR DBM LL_DMA_DisableDoubleBufferMode
lypinator	0:bb348c97df44	1225	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	1226	* @param Stream This parameter can be one of the following values:
lypinator	0:bb348c97df44	1227	* @arg @ref LL_DMA_STREAM_0
lypinator	0:bb348c97df44	1228	* @arg @ref LL_DMA_STREAM_1
lypinator	0:bb348c97df44	1229	* @arg @ref LL_DMA_STREAM_2
lypinator	0:bb348c97df44	1230	* @arg @ref LL_DMA_STREAM_3
lypinator	0:bb348c97df44	1231	* @arg @ref LL_DMA_STREAM_4
lypinator	0:bb348c97df44	1232	* @arg @ref LL_DMA_STREAM_5
lypinator	0:bb348c97df44	1233	* @arg @ref LL_DMA_STREAM_6
lypinator	0:bb348c97df44	1234	* @arg @ref LL_DMA_STREAM_7
lypinator	0:bb348c97df44	1235	* @retval None
lypinator	0:bb348c97df44	1236	*/
lypinator	0:bb348c97df44	1237	__STATIC_INLINE void LL_DMA_DisableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream)
lypinator	0:bb348c97df44	1238	{
lypinator	0:bb348c97df44	1239	CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DBM);
lypinator	0:bb348c97df44	1240	}
lypinator	0:bb348c97df44	1241
lypinator	0:bb348c97df44	1242	/**
lypinator	0:bb348c97df44	1243	* @brief Get FIFO status.
lypinator	0:bb348c97df44	1244	* @rmtoll FCR FS LL_DMA_GetFIFOStatus
lypinator	0:bb348c97df44	1245	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	1246	* @param Stream This parameter can be one of the following values:
lypinator	0:bb348c97df44	1247	* @arg @ref LL_DMA_STREAM_0
lypinator	0:bb348c97df44	1248	* @arg @ref LL_DMA_STREAM_1
lypinator	0:bb348c97df44	1249	* @arg @ref LL_DMA_STREAM_2
lypinator	0:bb348c97df44	1250	* @arg @ref LL_DMA_STREAM_3
lypinator	0:bb348c97df44	1251	* @arg @ref LL_DMA_STREAM_4
lypinator	0:bb348c97df44	1252	* @arg @ref LL_DMA_STREAM_5
lypinator	0:bb348c97df44	1253	* @arg @ref LL_DMA_STREAM_6
lypinator	0:bb348c97df44	1254	* @arg @ref LL_DMA_STREAM_7
lypinator	0:bb348c97df44	1255	* @retval Returned value can be one of the following values:
lypinator	0:bb348c97df44	1256	* @arg @ref LL_DMA_FIFOSTATUS_0_25
lypinator	0:bb348c97df44	1257	* @arg @ref LL_DMA_FIFOSTATUS_25_50
lypinator	0:bb348c97df44	1258	* @arg @ref LL_DMA_FIFOSTATUS_50_75
lypinator	0:bb348c97df44	1259	* @arg @ref LL_DMA_FIFOSTATUS_75_100
lypinator	0:bb348c97df44	1260	* @arg @ref LL_DMA_FIFOSTATUS_EMPTY
lypinator	0:bb348c97df44	1261	* @arg @ref LL_DMA_FIFOSTATUS_FULL
lypinator	0:bb348c97df44	1262	*/
lypinator	0:bb348c97df44	1263	__STATIC_INLINE uint32_t LL_DMA_GetFIFOStatus(DMA_TypeDef *DMAx, uint32_t Stream)
lypinator	0:bb348c97df44	1264	{
lypinator	0:bb348c97df44	1265	return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FS));
lypinator	0:bb348c97df44	1266	}
lypinator	0:bb348c97df44	1267
lypinator	0:bb348c97df44	1268	/**
lypinator	0:bb348c97df44	1269	* @brief Disable Fifo mode.
lypinator	0:bb348c97df44	1270	* @rmtoll FCR DMDIS LL_DMA_DisableFifoMode
lypinator	0:bb348c97df44	1271	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	1272	* @param Stream This parameter can be one of the following values:
lypinator	0:bb348c97df44	1273	* @arg @ref LL_DMA_STREAM_0
lypinator	0:bb348c97df44	1274	* @arg @ref LL_DMA_STREAM_1
lypinator	0:bb348c97df44	1275	* @arg @ref LL_DMA_STREAM_2
lypinator	0:bb348c97df44	1276	* @arg @ref LL_DMA_STREAM_3
lypinator	0:bb348c97df44	1277	* @arg @ref LL_DMA_STREAM_4
lypinator	0:bb348c97df44	1278	* @arg @ref LL_DMA_STREAM_5
lypinator	0:bb348c97df44	1279	* @arg @ref LL_DMA_STREAM_6
lypinator	0:bb348c97df44	1280	* @arg @ref LL_DMA_STREAM_7
lypinator	0:bb348c97df44	1281	* @retval None
lypinator	0:bb348c97df44	1282	*/
lypinator	0:bb348c97df44	1283	__STATIC_INLINE void LL_DMA_DisableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream)
lypinator	0:bb348c97df44	1284	{
lypinator	0:bb348c97df44	1285	CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_DMDIS);
lypinator	0:bb348c97df44	1286	}
lypinator	0:bb348c97df44	1287
lypinator	0:bb348c97df44	1288	/**
lypinator	0:bb348c97df44	1289	* @brief Enable Fifo mode.
lypinator	0:bb348c97df44	1290	* @rmtoll FCR DMDIS LL_DMA_EnableFifoMode
lypinator	0:bb348c97df44	1291	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	1292	* @param Stream This parameter can be one of the following values:
lypinator	0:bb348c97df44	1293	* @arg @ref LL_DMA_STREAM_0
lypinator	0:bb348c97df44	1294	* @arg @ref LL_DMA_STREAM_1
lypinator	0:bb348c97df44	1295	* @arg @ref LL_DMA_STREAM_2
lypinator	0:bb348c97df44	1296	* @arg @ref LL_DMA_STREAM_3
lypinator	0:bb348c97df44	1297	* @arg @ref LL_DMA_STREAM_4
lypinator	0:bb348c97df44	1298	* @arg @ref LL_DMA_STREAM_5
lypinator	0:bb348c97df44	1299	* @arg @ref LL_DMA_STREAM_6
lypinator	0:bb348c97df44	1300	* @arg @ref LL_DMA_STREAM_7
lypinator	0:bb348c97df44	1301	* @retval None
lypinator	0:bb348c97df44	1302	*/
lypinator	0:bb348c97df44	1303	__STATIC_INLINE void LL_DMA_EnableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream)
lypinator	0:bb348c97df44	1304	{
lypinator	0:bb348c97df44	1305	SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_DMDIS);
lypinator	0:bb348c97df44	1306	}
lypinator	0:bb348c97df44	1307
lypinator	0:bb348c97df44	1308	/**
lypinator	0:bb348c97df44	1309	* @brief Select FIFO threshold.
lypinator	0:bb348c97df44	1310	* @rmtoll FCR FTH LL_DMA_SetFIFOThreshold
lypinator	0:bb348c97df44	1311	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	1312	* @param Stream This parameter can be one of the following values:
lypinator	0:bb348c97df44	1313	* @arg @ref LL_DMA_STREAM_0
lypinator	0:bb348c97df44	1314	* @arg @ref LL_DMA_STREAM_1
lypinator	0:bb348c97df44	1315	* @arg @ref LL_DMA_STREAM_2
lypinator	0:bb348c97df44	1316	* @arg @ref LL_DMA_STREAM_3
lypinator	0:bb348c97df44	1317	* @arg @ref LL_DMA_STREAM_4
lypinator	0:bb348c97df44	1318	* @arg @ref LL_DMA_STREAM_5
lypinator	0:bb348c97df44	1319	* @arg @ref LL_DMA_STREAM_6
lypinator	0:bb348c97df44	1320	* @arg @ref LL_DMA_STREAM_7
lypinator	0:bb348c97df44	1321	* @param Threshold This parameter can be one of the following values:
lypinator	0:bb348c97df44	1322	* @arg @ref LL_DMA_FIFOTHRESHOLD_1_4
lypinator	0:bb348c97df44	1323	* @arg @ref LL_DMA_FIFOTHRESHOLD_1_2
lypinator	0:bb348c97df44	1324	* @arg @ref LL_DMA_FIFOTHRESHOLD_3_4
lypinator	0:bb348c97df44	1325	* @arg @ref LL_DMA_FIFOTHRESHOLD_FULL
lypinator	0:bb348c97df44	1326	* @retval None
lypinator	0:bb348c97df44	1327	*/
lypinator	0:bb348c97df44	1328	__STATIC_INLINE void LL_DMA_SetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Threshold)
lypinator	0:bb348c97df44	1329	{
lypinator	0:bb348c97df44	1330	MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FTH, Threshold);
lypinator	0:bb348c97df44	1331	}
lypinator	0:bb348c97df44	1332
lypinator	0:bb348c97df44	1333	/**
lypinator	0:bb348c97df44	1334	* @brief Get FIFO threshold.
lypinator	0:bb348c97df44	1335	* @rmtoll FCR FTH LL_DMA_GetFIFOThreshold
lypinator	0:bb348c97df44	1336	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	1337	* @param Stream This parameter can be one of the following values:
lypinator	0:bb348c97df44	1338	* @arg @ref LL_DMA_STREAM_0
lypinator	0:bb348c97df44	1339	* @arg @ref LL_DMA_STREAM_1
lypinator	0:bb348c97df44	1340	* @arg @ref LL_DMA_STREAM_2
lypinator	0:bb348c97df44	1341	* @arg @ref LL_DMA_STREAM_3
lypinator	0:bb348c97df44	1342	* @arg @ref LL_DMA_STREAM_4
lypinator	0:bb348c97df44	1343	* @arg @ref LL_DMA_STREAM_5
lypinator	0:bb348c97df44	1344	* @arg @ref LL_DMA_STREAM_6
lypinator	0:bb348c97df44	1345	* @arg @ref LL_DMA_STREAM_7
lypinator	0:bb348c97df44	1346	* @retval Returned value can be one of the following values:
lypinator	0:bb348c97df44	1347	* @arg @ref LL_DMA_FIFOTHRESHOLD_1_4
lypinator	0:bb348c97df44	1348	* @arg @ref LL_DMA_FIFOTHRESHOLD_1_2
lypinator	0:bb348c97df44	1349	* @arg @ref LL_DMA_FIFOTHRESHOLD_3_4
lypinator	0:bb348c97df44	1350	* @arg @ref LL_DMA_FIFOTHRESHOLD_FULL
lypinator	0:bb348c97df44	1351	*/
lypinator	0:bb348c97df44	1352	__STATIC_INLINE uint32_t LL_DMA_GetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream)
lypinator	0:bb348c97df44	1353	{
lypinator	0:bb348c97df44	1354	return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FTH));
lypinator	0:bb348c97df44	1355	}
lypinator	0:bb348c97df44	1356
lypinator	0:bb348c97df44	1357	/**
lypinator	0:bb348c97df44	1358	* @brief Configure the FIFO .
lypinator	0:bb348c97df44	1359	* @rmtoll FCR FTH LL_DMA_ConfigFifo\n
lypinator	0:bb348c97df44	1360	* FCR DMDIS LL_DMA_ConfigFifo
lypinator	0:bb348c97df44	1361	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	1362	* @param Stream This parameter can be one of the following values:
lypinator	0:bb348c97df44	1363	* @arg @ref LL_DMA_STREAM_0
lypinator	0:bb348c97df44	1364	* @arg @ref LL_DMA_STREAM_1
lypinator	0:bb348c97df44	1365	* @arg @ref LL_DMA_STREAM_2
lypinator	0:bb348c97df44	1366	* @arg @ref LL_DMA_STREAM_3
lypinator	0:bb348c97df44	1367	* @arg @ref LL_DMA_STREAM_4
lypinator	0:bb348c97df44	1368	* @arg @ref LL_DMA_STREAM_5
lypinator	0:bb348c97df44	1369	* @arg @ref LL_DMA_STREAM_6
lypinator	0:bb348c97df44	1370	* @arg @ref LL_DMA_STREAM_7
lypinator	0:bb348c97df44	1371	* @param FifoMode This parameter can be one of the following values:
lypinator	0:bb348c97df44	1372	* @arg @ref LL_DMA_FIFOMODE_ENABLE
lypinator	0:bb348c97df44	1373	* @arg @ref LL_DMA_FIFOMODE_DISABLE
lypinator	0:bb348c97df44	1374	* @param FifoThreshold This parameter can be one of the following values:
lypinator	0:bb348c97df44	1375	* @arg @ref LL_DMA_FIFOTHRESHOLD_1_4
lypinator	0:bb348c97df44	1376	* @arg @ref LL_DMA_FIFOTHRESHOLD_1_2
lypinator	0:bb348c97df44	1377	* @arg @ref LL_DMA_FIFOTHRESHOLD_3_4
lypinator	0:bb348c97df44	1378	* @arg @ref LL_DMA_FIFOTHRESHOLD_FULL
lypinator	0:bb348c97df44	1379	* @retval None
lypinator	0:bb348c97df44	1380	*/
lypinator	0:bb348c97df44	1381	__STATIC_INLINE void LL_DMA_ConfigFifo(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t FifoMode, uint32_t FifoThreshold)
lypinator	0:bb348c97df44	1382	{
lypinator	0:bb348c97df44	1383	MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FTH\|DMA_SxFCR_DMDIS, FifoMode\|FifoThreshold);
lypinator	0:bb348c97df44	1384	}
lypinator	0:bb348c97df44	1385
lypinator	0:bb348c97df44	1386	/**
lypinator	0:bb348c97df44	1387	* @brief Configure the Source and Destination addresses.
lypinator	0:bb348c97df44	1388	* @note This API must not be called when the DMA stream is enabled.
lypinator	0:bb348c97df44	1389	* @rmtoll M0AR M0A LL_DMA_ConfigAddresses\n
lypinator	0:bb348c97df44	1390	* PAR PA LL_DMA_ConfigAddresses
lypinator	0:bb348c97df44	1391	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	1392	* @param Stream This parameter can be one of the following values:
lypinator	0:bb348c97df44	1393	* @arg @ref LL_DMA_STREAM_0
lypinator	0:bb348c97df44	1394	* @arg @ref LL_DMA_STREAM_1
lypinator	0:bb348c97df44	1395	* @arg @ref LL_DMA_STREAM_2
lypinator	0:bb348c97df44	1396	* @arg @ref LL_DMA_STREAM_3
lypinator	0:bb348c97df44	1397	* @arg @ref LL_DMA_STREAM_4
lypinator	0:bb348c97df44	1398	* @arg @ref LL_DMA_STREAM_5
lypinator	0:bb348c97df44	1399	* @arg @ref LL_DMA_STREAM_6
lypinator	0:bb348c97df44	1400	* @arg @ref LL_DMA_STREAM_7
lypinator	0:bb348c97df44	1401	* @param SrcAddress Between 0 to 0xFFFFFFFF
lypinator	0:bb348c97df44	1402	* @param DstAddress Between 0 to 0xFFFFFFFF
lypinator	0:bb348c97df44	1403	* @param Direction This parameter can be one of the following values:
lypinator	0:bb348c97df44	1404	* @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
lypinator	0:bb348c97df44	1405	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
lypinator	0:bb348c97df44	1406	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
lypinator	0:bb348c97df44	1407	* @retval None
lypinator	0:bb348c97df44	1408	*/
lypinator	0:bb348c97df44	1409	__STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t SrcAddress, uint32_t DstAddress, uint32_t Direction)
lypinator	0:bb348c97df44	1410	{
lypinator	0:bb348c97df44	1411	/* Direction Memory to Periph */
lypinator	0:bb348c97df44	1412	if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)
lypinator	0:bb348c97df44	1413	{
lypinator	0:bb348c97df44	1414	WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, SrcAddress);
lypinator	0:bb348c97df44	1415	WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, DstAddress);
lypinator	0:bb348c97df44	1416	}
lypinator	0:bb348c97df44	1417	/* Direction Periph to Memory and Memory to Memory */
lypinator	0:bb348c97df44	1418	else
lypinator	0:bb348c97df44	1419	{
lypinator	0:bb348c97df44	1420	WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, SrcAddress);
lypinator	0:bb348c97df44	1421	WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, DstAddress);
lypinator	0:bb348c97df44	1422	}
lypinator	0:bb348c97df44	1423	}
lypinator	0:bb348c97df44	1424
lypinator	0:bb348c97df44	1425	/**
lypinator	0:bb348c97df44	1426	* @brief Set the Memory address.
lypinator	0:bb348c97df44	1427	* @rmtoll M0AR M0A LL_DMA_SetMemoryAddress
lypinator	0:bb348c97df44	1428	* @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
lypinator	0:bb348c97df44	1429	* @note This API must not be called when the DMA channel is enabled.
lypinator	0:bb348c97df44	1430	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	1431	* @param Stream This parameter can be one of the following values:
lypinator	0:bb348c97df44	1432	* @arg @ref LL_DMA_STREAM_0
lypinator	0:bb348c97df44	1433	* @arg @ref LL_DMA_STREAM_1
lypinator	0:bb348c97df44	1434	* @arg @ref LL_DMA_STREAM_2
lypinator	0:bb348c97df44	1435	* @arg @ref LL_DMA_STREAM_3
lypinator	0:bb348c97df44	1436	* @arg @ref LL_DMA_STREAM_4
lypinator	0:bb348c97df44	1437	* @arg @ref LL_DMA_STREAM_5
lypinator	0:bb348c97df44	1438	* @arg @ref LL_DMA_STREAM_6
lypinator	0:bb348c97df44	1439	* @arg @ref LL_DMA_STREAM_7
lypinator	0:bb348c97df44	1440	* @param MemoryAddress Between 0 to 0xFFFFFFFF
lypinator	0:bb348c97df44	1441	* @retval None
lypinator	0:bb348c97df44	1442	*/
lypinator	0:bb348c97df44	1443	__STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAddress)
lypinator	0:bb348c97df44	1444	{
lypinator	0:bb348c97df44	1445	WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, MemoryAddress);
lypinator	0:bb348c97df44	1446	}
lypinator	0:bb348c97df44	1447
lypinator	0:bb348c97df44	1448	/**
lypinator	0:bb348c97df44	1449	* @brief Set the Peripheral address.
lypinator	0:bb348c97df44	1450	* @rmtoll PAR PA LL_DMA_SetPeriphAddress
lypinator	0:bb348c97df44	1451	* @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
lypinator	0:bb348c97df44	1452	* @note This API must not be called when the DMA channel is enabled.
lypinator	0:bb348c97df44	1453	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	1454	* @param Stream This parameter can be one of the following values:
lypinator	0:bb348c97df44	1455	* @arg @ref LL_DMA_STREAM_0
lypinator	0:bb348c97df44	1456	* @arg @ref LL_DMA_STREAM_1
lypinator	0:bb348c97df44	1457	* @arg @ref LL_DMA_STREAM_2
lypinator	0:bb348c97df44	1458	* @arg @ref LL_DMA_STREAM_3
lypinator	0:bb348c97df44	1459	* @arg @ref LL_DMA_STREAM_4
lypinator	0:bb348c97df44	1460	* @arg @ref LL_DMA_STREAM_5
lypinator	0:bb348c97df44	1461	* @arg @ref LL_DMA_STREAM_6
lypinator	0:bb348c97df44	1462	* @arg @ref LL_DMA_STREAM_7
lypinator	0:bb348c97df44	1463	* @param PeriphAddress Between 0 to 0xFFFFFFFF
lypinator	0:bb348c97df44	1464	* @retval None
lypinator	0:bb348c97df44	1465	*/
lypinator	0:bb348c97df44	1466	__STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t PeriphAddress)
lypinator	0:bb348c97df44	1467	{
lypinator	0:bb348c97df44	1468	WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, PeriphAddress);
lypinator	0:bb348c97df44	1469	}
lypinator	0:bb348c97df44	1470
lypinator	0:bb348c97df44	1471	/**
lypinator	0:bb348c97df44	1472	* @brief Get the Memory address.
lypinator	0:bb348c97df44	1473	* @rmtoll M0AR M0A LL_DMA_GetMemoryAddress
lypinator	0:bb348c97df44	1474	* @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
lypinator	0:bb348c97df44	1475	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	1476	* @param Stream This parameter can be one of the following values:
lypinator	0:bb348c97df44	1477	* @arg @ref LL_DMA_STREAM_0
lypinator	0:bb348c97df44	1478	* @arg @ref LL_DMA_STREAM_1
lypinator	0:bb348c97df44	1479	* @arg @ref LL_DMA_STREAM_2
lypinator	0:bb348c97df44	1480	* @arg @ref LL_DMA_STREAM_3
lypinator	0:bb348c97df44	1481	* @arg @ref LL_DMA_STREAM_4
lypinator	0:bb348c97df44	1482	* @arg @ref LL_DMA_STREAM_5
lypinator	0:bb348c97df44	1483	* @arg @ref LL_DMA_STREAM_6
lypinator	0:bb348c97df44	1484	* @arg @ref LL_DMA_STREAM_7
lypinator	0:bb348c97df44	1485	* @retval Between 0 to 0xFFFFFFFF
lypinator	0:bb348c97df44	1486	*/
lypinator	0:bb348c97df44	1487	__STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef* DMAx, uint32_t Stream)
lypinator	0:bb348c97df44	1488	{
lypinator	0:bb348c97df44	1489	return (READ_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR));
lypinator	0:bb348c97df44	1490	}
lypinator	0:bb348c97df44	1491
lypinator	0:bb348c97df44	1492	/**
lypinator	0:bb348c97df44	1493	* @brief Get the Peripheral address.
lypinator	0:bb348c97df44	1494	* @rmtoll PAR PA LL_DMA_GetPeriphAddress
lypinator	0:bb348c97df44	1495	* @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
lypinator	0:bb348c97df44	1496	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	1497	* @param Stream This parameter can be one of the following values:
lypinator	0:bb348c97df44	1498	* @arg @ref LL_DMA_STREAM_0
lypinator	0:bb348c97df44	1499	* @arg @ref LL_DMA_STREAM_1
lypinator	0:bb348c97df44	1500	* @arg @ref LL_DMA_STREAM_2
lypinator	0:bb348c97df44	1501	* @arg @ref LL_DMA_STREAM_3
lypinator	0:bb348c97df44	1502	* @arg @ref LL_DMA_STREAM_4
lypinator	0:bb348c97df44	1503	* @arg @ref LL_DMA_STREAM_5
lypinator	0:bb348c97df44	1504	* @arg @ref LL_DMA_STREAM_6
lypinator	0:bb348c97df44	1505	* @arg @ref LL_DMA_STREAM_7
lypinator	0:bb348c97df44	1506	* @retval Between 0 to 0xFFFFFFFF
lypinator	0:bb348c97df44	1507	*/
lypinator	0:bb348c97df44	1508	__STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef* DMAx, uint32_t Stream)
lypinator	0:bb348c97df44	1509	{
lypinator	0:bb348c97df44	1510	return (READ_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR));
lypinator	0:bb348c97df44	1511	}
lypinator	0:bb348c97df44	1512
lypinator	0:bb348c97df44	1513	/**
lypinator	0:bb348c97df44	1514	* @brief Set the Memory to Memory Source address.
lypinator	0:bb348c97df44	1515	* @rmtoll PAR PA LL_DMA_SetM2MSrcAddress
lypinator	0:bb348c97df44	1516	* @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
lypinator	0:bb348c97df44	1517	* @note This API must not be called when the DMA channel is enabled.
lypinator	0:bb348c97df44	1518	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	1519	* @param Stream This parameter can be one of the following values:
lypinator	0:bb348c97df44	1520	* @arg @ref LL_DMA_STREAM_0
lypinator	0:bb348c97df44	1521	* @arg @ref LL_DMA_STREAM_1
lypinator	0:bb348c97df44	1522	* @arg @ref LL_DMA_STREAM_2
lypinator	0:bb348c97df44	1523	* @arg @ref LL_DMA_STREAM_3
lypinator	0:bb348c97df44	1524	* @arg @ref LL_DMA_STREAM_4
lypinator	0:bb348c97df44	1525	* @arg @ref LL_DMA_STREAM_5
lypinator	0:bb348c97df44	1526	* @arg @ref LL_DMA_STREAM_6
lypinator	0:bb348c97df44	1527	* @arg @ref LL_DMA_STREAM_7
lypinator	0:bb348c97df44	1528	* @param MemoryAddress Between 0 to 0xFFFFFFFF
lypinator	0:bb348c97df44	1529	* @retval None
lypinator	0:bb348c97df44	1530	*/
lypinator	0:bb348c97df44	1531	__STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAddress)
lypinator	0:bb348c97df44	1532	{
lypinator	0:bb348c97df44	1533	WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, MemoryAddress);
lypinator	0:bb348c97df44	1534	}
lypinator	0:bb348c97df44	1535
lypinator	0:bb348c97df44	1536	/**
lypinator	0:bb348c97df44	1537	* @brief Set the Memory to Memory Destination address.
lypinator	0:bb348c97df44	1538	* @rmtoll M0AR M0A LL_DMA_SetM2MDstAddress
lypinator	0:bb348c97df44	1539	* @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
lypinator	0:bb348c97df44	1540	* @note This API must not be called when the DMA channel is enabled.
lypinator	0:bb348c97df44	1541	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	1542	* @param Stream This parameter can be one of the following values:
lypinator	0:bb348c97df44	1543	* @arg @ref LL_DMA_STREAM_0
lypinator	0:bb348c97df44	1544	* @arg @ref LL_DMA_STREAM_1
lypinator	0:bb348c97df44	1545	* @arg @ref LL_DMA_STREAM_2
lypinator	0:bb348c97df44	1546	* @arg @ref LL_DMA_STREAM_3
lypinator	0:bb348c97df44	1547	* @arg @ref LL_DMA_STREAM_4
lypinator	0:bb348c97df44	1548	* @arg @ref LL_DMA_STREAM_5
lypinator	0:bb348c97df44	1549	* @arg @ref LL_DMA_STREAM_6
lypinator	0:bb348c97df44	1550	* @arg @ref LL_DMA_STREAM_7
lypinator	0:bb348c97df44	1551	* @param MemoryAddress Between 0 to 0xFFFFFFFF
lypinator	0:bb348c97df44	1552	* @retval None
lypinator	0:bb348c97df44	1553	*/
lypinator	0:bb348c97df44	1554	__STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAddress)
lypinator	0:bb348c97df44	1555	{
lypinator	0:bb348c97df44	1556	WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, MemoryAddress);
lypinator	0:bb348c97df44	1557	}
lypinator	0:bb348c97df44	1558
lypinator	0:bb348c97df44	1559	/**
lypinator	0:bb348c97df44	1560	* @brief Get the Memory to Memory Source address.
lypinator	0:bb348c97df44	1561	* @rmtoll PAR PA LL_DMA_GetM2MSrcAddress
lypinator	0:bb348c97df44	1562	* @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
lypinator	0:bb348c97df44	1563	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	1564	* @param Stream This parameter can be one of the following values:
lypinator	0:bb348c97df44	1565	* @arg @ref LL_DMA_STREAM_0
lypinator	0:bb348c97df44	1566	* @arg @ref LL_DMA_STREAM_1
lypinator	0:bb348c97df44	1567	* @arg @ref LL_DMA_STREAM_2
lypinator	0:bb348c97df44	1568	* @arg @ref LL_DMA_STREAM_3
lypinator	0:bb348c97df44	1569	* @arg @ref LL_DMA_STREAM_4
lypinator	0:bb348c97df44	1570	* @arg @ref LL_DMA_STREAM_5
lypinator	0:bb348c97df44	1571	* @arg @ref LL_DMA_STREAM_6
lypinator	0:bb348c97df44	1572	* @arg @ref LL_DMA_STREAM_7
lypinator	0:bb348c97df44	1573	* @retval Between 0 to 0xFFFFFFFF
lypinator	0:bb348c97df44	1574	*/
lypinator	0:bb348c97df44	1575	__STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef* DMAx, uint32_t Stream)
lypinator	0:bb348c97df44	1576	{
lypinator	0:bb348c97df44	1577	return (READ_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR));
lypinator	0:bb348c97df44	1578	}
lypinator	0:bb348c97df44	1579
lypinator	0:bb348c97df44	1580	/**
lypinator	0:bb348c97df44	1581	* @brief Get the Memory to Memory Destination address.
lypinator	0:bb348c97df44	1582	* @rmtoll M0AR M0A LL_DMA_GetM2MDstAddress
lypinator	0:bb348c97df44	1583	* @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
lypinator	0:bb348c97df44	1584	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	1585	* @param Stream This parameter can be one of the following values:
lypinator	0:bb348c97df44	1586	* @arg @ref LL_DMA_STREAM_0
lypinator	0:bb348c97df44	1587	* @arg @ref LL_DMA_STREAM_1
lypinator	0:bb348c97df44	1588	* @arg @ref LL_DMA_STREAM_2
lypinator	0:bb348c97df44	1589	* @arg @ref LL_DMA_STREAM_3
lypinator	0:bb348c97df44	1590	* @arg @ref LL_DMA_STREAM_4
lypinator	0:bb348c97df44	1591	* @arg @ref LL_DMA_STREAM_5
lypinator	0:bb348c97df44	1592	* @arg @ref LL_DMA_STREAM_6
lypinator	0:bb348c97df44	1593	* @arg @ref LL_DMA_STREAM_7
lypinator	0:bb348c97df44	1594	* @retval Between 0 to 0xFFFFFFFF
lypinator	0:bb348c97df44	1595	*/
lypinator	0:bb348c97df44	1596	__STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef* DMAx, uint32_t Stream)
lypinator	0:bb348c97df44	1597	{
lypinator	0:bb348c97df44	1598	return (READ_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR));
lypinator	0:bb348c97df44	1599	}
lypinator	0:bb348c97df44	1600
lypinator	0:bb348c97df44	1601	/**
lypinator	0:bb348c97df44	1602	* @brief Set Memory 1 address (used in case of Double buffer mode).
lypinator	0:bb348c97df44	1603	* @rmtoll M1AR M1A LL_DMA_SetMemory1Address
lypinator	0:bb348c97df44	1604	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	1605	* @param Stream This parameter can be one of the following values:
lypinator	0:bb348c97df44	1606	* @arg @ref LL_DMA_STREAM_0
lypinator	0:bb348c97df44	1607	* @arg @ref LL_DMA_STREAM_1
lypinator	0:bb348c97df44	1608	* @arg @ref LL_DMA_STREAM_2
lypinator	0:bb348c97df44	1609	* @arg @ref LL_DMA_STREAM_3
lypinator	0:bb348c97df44	1610	* @arg @ref LL_DMA_STREAM_4
lypinator	0:bb348c97df44	1611	* @arg @ref LL_DMA_STREAM_5
lypinator	0:bb348c97df44	1612	* @arg @ref LL_DMA_STREAM_6
lypinator	0:bb348c97df44	1613	* @arg @ref LL_DMA_STREAM_7
lypinator	0:bb348c97df44	1614	* @param Address Between 0 to 0xFFFFFFFF
lypinator	0:bb348c97df44	1615	* @retval None
lypinator	0:bb348c97df44	1616	*/
lypinator	0:bb348c97df44	1617	__STATIC_INLINE void LL_DMA_SetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Address)
lypinator	0:bb348c97df44	1618	{
lypinator	0:bb348c97df44	1619	MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M1AR, DMA_SxM1AR_M1A, Address);
lypinator	0:bb348c97df44	1620	}
lypinator	0:bb348c97df44	1621
lypinator	0:bb348c97df44	1622	/**
lypinator	0:bb348c97df44	1623	* @brief Get Memory 1 address (used in case of Double buffer mode).
lypinator	0:bb348c97df44	1624	* @rmtoll M1AR M1A LL_DMA_GetMemory1Address
lypinator	0:bb348c97df44	1625	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	1626	* @param Stream This parameter can be one of the following values:
lypinator	0:bb348c97df44	1627	* @arg @ref LL_DMA_STREAM_0
lypinator	0:bb348c97df44	1628	* @arg @ref LL_DMA_STREAM_1
lypinator	0:bb348c97df44	1629	* @arg @ref LL_DMA_STREAM_2
lypinator	0:bb348c97df44	1630	* @arg @ref LL_DMA_STREAM_3
lypinator	0:bb348c97df44	1631	* @arg @ref LL_DMA_STREAM_4
lypinator	0:bb348c97df44	1632	* @arg @ref LL_DMA_STREAM_5
lypinator	0:bb348c97df44	1633	* @arg @ref LL_DMA_STREAM_6
lypinator	0:bb348c97df44	1634	* @arg @ref LL_DMA_STREAM_7
lypinator	0:bb348c97df44	1635	* @retval Between 0 to 0xFFFFFFFF
lypinator	0:bb348c97df44	1636	*/
lypinator	0:bb348c97df44	1637	__STATIC_INLINE uint32_t LL_DMA_GetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream)
lypinator	0:bb348c97df44	1638	{
lypinator	0:bb348c97df44	1639	return (((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M1AR);
lypinator	0:bb348c97df44	1640	}
lypinator	0:bb348c97df44	1641
lypinator	0:bb348c97df44	1642	/**
lypinator	0:bb348c97df44	1643	* @}
lypinator	0:bb348c97df44	1644	*/
lypinator	0:bb348c97df44	1645
lypinator	0:bb348c97df44	1646	/** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management
lypinator	0:bb348c97df44	1647	* @{
lypinator	0:bb348c97df44	1648	*/
lypinator	0:bb348c97df44	1649
lypinator	0:bb348c97df44	1650	/**
lypinator	0:bb348c97df44	1651	* @brief Get Stream 0 half transfer flag.
lypinator	0:bb348c97df44	1652	* @rmtoll LISR HTIF0 LL_DMA_IsActiveFlag_HT0
lypinator	0:bb348c97df44	1653	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	1654	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	1655	*/
lypinator	0:bb348c97df44	1656	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT0(DMA_TypeDef *DMAx)
lypinator	0:bb348c97df44	1657	{
lypinator	0:bb348c97df44	1658	return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF0)==(DMA_LISR_HTIF0));
lypinator	0:bb348c97df44	1659	}
lypinator	0:bb348c97df44	1660
lypinator	0:bb348c97df44	1661	/**
lypinator	0:bb348c97df44	1662	* @brief Get Stream 1 half transfer flag.
lypinator	0:bb348c97df44	1663	* @rmtoll LISR HTIF1 LL_DMA_IsActiveFlag_HT1
lypinator	0:bb348c97df44	1664	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	1665	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	1666	*/
lypinator	0:bb348c97df44	1667	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx)
lypinator	0:bb348c97df44	1668	{
lypinator	0:bb348c97df44	1669	return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF1)==(DMA_LISR_HTIF1));
lypinator	0:bb348c97df44	1670	}
lypinator	0:bb348c97df44	1671
lypinator	0:bb348c97df44	1672	/**
lypinator	0:bb348c97df44	1673	* @brief Get Stream 2 half transfer flag.
lypinator	0:bb348c97df44	1674	* @rmtoll LISR HTIF2 LL_DMA_IsActiveFlag_HT2
lypinator	0:bb348c97df44	1675	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	1676	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	1677	*/
lypinator	0:bb348c97df44	1678	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx)
lypinator	0:bb348c97df44	1679	{
lypinator	0:bb348c97df44	1680	return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF2)==(DMA_LISR_HTIF2));
lypinator	0:bb348c97df44	1681	}
lypinator	0:bb348c97df44	1682
lypinator	0:bb348c97df44	1683	/**
lypinator	0:bb348c97df44	1684	* @brief Get Stream 3 half transfer flag.
lypinator	0:bb348c97df44	1685	* @rmtoll LISR HTIF3 LL_DMA_IsActiveFlag_HT3
lypinator	0:bb348c97df44	1686	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	1687	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	1688	*/
lypinator	0:bb348c97df44	1689	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx)
lypinator	0:bb348c97df44	1690	{
lypinator	0:bb348c97df44	1691	return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF3)==(DMA_LISR_HTIF3));
lypinator	0:bb348c97df44	1692	}
lypinator	0:bb348c97df44	1693
lypinator	0:bb348c97df44	1694	/**
lypinator	0:bb348c97df44	1695	* @brief Get Stream 4 half transfer flag.
lypinator	0:bb348c97df44	1696	* @rmtoll HISR HTIF4 LL_DMA_IsActiveFlag_HT4
lypinator	0:bb348c97df44	1697	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	1698	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	1699	*/
lypinator	0:bb348c97df44	1700	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx)
lypinator	0:bb348c97df44	1701	{
lypinator	0:bb348c97df44	1702	return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF4)==(DMA_HISR_HTIF4));
lypinator	0:bb348c97df44	1703	}
lypinator	0:bb348c97df44	1704
lypinator	0:bb348c97df44	1705	/**
lypinator	0:bb348c97df44	1706	* @brief Get Stream 5 half transfer flag.
lypinator	0:bb348c97df44	1707	* @rmtoll HISR HTIF0 LL_DMA_IsActiveFlag_HT5
lypinator	0:bb348c97df44	1708	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	1709	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	1710	*/
lypinator	0:bb348c97df44	1711	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx)
lypinator	0:bb348c97df44	1712	{
lypinator	0:bb348c97df44	1713	return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF5)==(DMA_HISR_HTIF5));
lypinator	0:bb348c97df44	1714	}
lypinator	0:bb348c97df44	1715
lypinator	0:bb348c97df44	1716	/**
lypinator	0:bb348c97df44	1717	* @brief Get Stream 6 half transfer flag.
lypinator	0:bb348c97df44	1718	* @rmtoll HISR HTIF6 LL_DMA_IsActiveFlag_HT6
lypinator	0:bb348c97df44	1719	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	1720	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	1721	*/
lypinator	0:bb348c97df44	1722	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx)
lypinator	0:bb348c97df44	1723	{
lypinator	0:bb348c97df44	1724	return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF6)==(DMA_HISR_HTIF6));
lypinator	0:bb348c97df44	1725	}
lypinator	0:bb348c97df44	1726
lypinator	0:bb348c97df44	1727	/**
lypinator	0:bb348c97df44	1728	* @brief Get Stream 7 half transfer flag.
lypinator	0:bb348c97df44	1729	* @rmtoll HISR HTIF7 LL_DMA_IsActiveFlag_HT7
lypinator	0:bb348c97df44	1730	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	1731	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	1732	*/
lypinator	0:bb348c97df44	1733	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx)
lypinator	0:bb348c97df44	1734	{
lypinator	0:bb348c97df44	1735	return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF7)==(DMA_HISR_HTIF7));
lypinator	0:bb348c97df44	1736	}
lypinator	0:bb348c97df44	1737
lypinator	0:bb348c97df44	1738	/**
lypinator	0:bb348c97df44	1739	* @brief Get Stream 0 transfer complete flag.
lypinator	0:bb348c97df44	1740	* @rmtoll LISR TCIF0 LL_DMA_IsActiveFlag_TC0
lypinator	0:bb348c97df44	1741	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	1742	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	1743	*/
lypinator	0:bb348c97df44	1744	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC0(DMA_TypeDef *DMAx)
lypinator	0:bb348c97df44	1745	{
lypinator	0:bb348c97df44	1746	return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF0)==(DMA_LISR_TCIF0));
lypinator	0:bb348c97df44	1747	}
lypinator	0:bb348c97df44	1748
lypinator	0:bb348c97df44	1749	/**
lypinator	0:bb348c97df44	1750	* @brief Get Stream 1 transfer complete flag.
lypinator	0:bb348c97df44	1751	* @rmtoll LISR TCIF1 LL_DMA_IsActiveFlag_TC1
lypinator	0:bb348c97df44	1752	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	1753	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	1754	*/
lypinator	0:bb348c97df44	1755	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx)
lypinator	0:bb348c97df44	1756	{
lypinator	0:bb348c97df44	1757	return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF1)==(DMA_LISR_TCIF1));
lypinator	0:bb348c97df44	1758	}
lypinator	0:bb348c97df44	1759
lypinator	0:bb348c97df44	1760	/**
lypinator	0:bb348c97df44	1761	* @brief Get Stream 2 transfer complete flag.
lypinator	0:bb348c97df44	1762	* @rmtoll LISR TCIF2 LL_DMA_IsActiveFlag_TC2
lypinator	0:bb348c97df44	1763	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	1764	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	1765	*/
lypinator	0:bb348c97df44	1766	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx)
lypinator	0:bb348c97df44	1767	{
lypinator	0:bb348c97df44	1768	return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF2)==(DMA_LISR_TCIF2));
lypinator	0:bb348c97df44	1769	}
lypinator	0:bb348c97df44	1770
lypinator	0:bb348c97df44	1771	/**
lypinator	0:bb348c97df44	1772	* @brief Get Stream 3 transfer complete flag.
lypinator	0:bb348c97df44	1773	* @rmtoll LISR TCIF3 LL_DMA_IsActiveFlag_TC3
lypinator	0:bb348c97df44	1774	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	1775	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	1776	*/
lypinator	0:bb348c97df44	1777	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx)
lypinator	0:bb348c97df44	1778	{
lypinator	0:bb348c97df44	1779	return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF3)==(DMA_LISR_TCIF3));
lypinator	0:bb348c97df44	1780	}
lypinator	0:bb348c97df44	1781
lypinator	0:bb348c97df44	1782	/**
lypinator	0:bb348c97df44	1783	* @brief Get Stream 4 transfer complete flag.
lypinator	0:bb348c97df44	1784	* @rmtoll HISR TCIF4 LL_DMA_IsActiveFlag_TC4
lypinator	0:bb348c97df44	1785	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	1786	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	1787	*/
lypinator	0:bb348c97df44	1788	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx)
lypinator	0:bb348c97df44	1789	{
lypinator	0:bb348c97df44	1790	return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF4)==(DMA_HISR_TCIF4));
lypinator	0:bb348c97df44	1791	}
lypinator	0:bb348c97df44	1792
lypinator	0:bb348c97df44	1793	/**
lypinator	0:bb348c97df44	1794	* @brief Get Stream 5 transfer complete flag.
lypinator	0:bb348c97df44	1795	* @rmtoll HISR TCIF0 LL_DMA_IsActiveFlag_TC5
lypinator	0:bb348c97df44	1796	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	1797	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	1798	*/
lypinator	0:bb348c97df44	1799	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx)
lypinator	0:bb348c97df44	1800	{
lypinator	0:bb348c97df44	1801	return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF5)==(DMA_HISR_TCIF5));
lypinator	0:bb348c97df44	1802	}
lypinator	0:bb348c97df44	1803
lypinator	0:bb348c97df44	1804	/**
lypinator	0:bb348c97df44	1805	* @brief Get Stream 6 transfer complete flag.
lypinator	0:bb348c97df44	1806	* @rmtoll HISR TCIF6 LL_DMA_IsActiveFlag_TC6
lypinator	0:bb348c97df44	1807	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	1808	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	1809	*/
lypinator	0:bb348c97df44	1810	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx)
lypinator	0:bb348c97df44	1811	{
lypinator	0:bb348c97df44	1812	return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF6)==(DMA_HISR_TCIF6));
lypinator	0:bb348c97df44	1813	}
lypinator	0:bb348c97df44	1814
lypinator	0:bb348c97df44	1815	/**
lypinator	0:bb348c97df44	1816	* @brief Get Stream 7 transfer complete flag.
lypinator	0:bb348c97df44	1817	* @rmtoll HISR TCIF7 LL_DMA_IsActiveFlag_TC7
lypinator	0:bb348c97df44	1818	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	1819	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	1820	*/
lypinator	0:bb348c97df44	1821	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx)
lypinator	0:bb348c97df44	1822	{
lypinator	0:bb348c97df44	1823	return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF7)==(DMA_HISR_TCIF7));
lypinator	0:bb348c97df44	1824	}
lypinator	0:bb348c97df44	1825
lypinator	0:bb348c97df44	1826	/**
lypinator	0:bb348c97df44	1827	* @brief Get Stream 0 transfer error flag.
lypinator	0:bb348c97df44	1828	* @rmtoll LISR TEIF0 LL_DMA_IsActiveFlag_TE0
lypinator	0:bb348c97df44	1829	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	1830	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	1831	*/
lypinator	0:bb348c97df44	1832	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE0(DMA_TypeDef *DMAx)
lypinator	0:bb348c97df44	1833	{
lypinator	0:bb348c97df44	1834	return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF0)==(DMA_LISR_TEIF0));
lypinator	0:bb348c97df44	1835	}
lypinator	0:bb348c97df44	1836
lypinator	0:bb348c97df44	1837	/**
lypinator	0:bb348c97df44	1838	* @brief Get Stream 1 transfer error flag.
lypinator	0:bb348c97df44	1839	* @rmtoll LISR TEIF1 LL_DMA_IsActiveFlag_TE1
lypinator	0:bb348c97df44	1840	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	1841	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	1842	*/
lypinator	0:bb348c97df44	1843	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx)
lypinator	0:bb348c97df44	1844	{
lypinator	0:bb348c97df44	1845	return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF1)==(DMA_LISR_TEIF1));
lypinator	0:bb348c97df44	1846	}
lypinator	0:bb348c97df44	1847
lypinator	0:bb348c97df44	1848	/**
lypinator	0:bb348c97df44	1849	* @brief Get Stream 2 transfer error flag.
lypinator	0:bb348c97df44	1850	* @rmtoll LISR TEIF2 LL_DMA_IsActiveFlag_TE2
lypinator	0:bb348c97df44	1851	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	1852	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	1853	*/
lypinator	0:bb348c97df44	1854	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx)
lypinator	0:bb348c97df44	1855	{
lypinator	0:bb348c97df44	1856	return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF2)==(DMA_LISR_TEIF2));
lypinator	0:bb348c97df44	1857	}
lypinator	0:bb348c97df44	1858
lypinator	0:bb348c97df44	1859	/**
lypinator	0:bb348c97df44	1860	* @brief Get Stream 3 transfer error flag.
lypinator	0:bb348c97df44	1861	* @rmtoll LISR TEIF3 LL_DMA_IsActiveFlag_TE3
lypinator	0:bb348c97df44	1862	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	1863	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	1864	*/
lypinator	0:bb348c97df44	1865	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx)
lypinator	0:bb348c97df44	1866	{
lypinator	0:bb348c97df44	1867	return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF3)==(DMA_LISR_TEIF3));
lypinator	0:bb348c97df44	1868	}
lypinator	0:bb348c97df44	1869
lypinator	0:bb348c97df44	1870	/**
lypinator	0:bb348c97df44	1871	* @brief Get Stream 4 transfer error flag.
lypinator	0:bb348c97df44	1872	* @rmtoll HISR TEIF4 LL_DMA_IsActiveFlag_TE4
lypinator	0:bb348c97df44	1873	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	1874	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	1875	*/
lypinator	0:bb348c97df44	1876	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx)
lypinator	0:bb348c97df44	1877	{
lypinator	0:bb348c97df44	1878	return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF4)==(DMA_HISR_TEIF4));
lypinator	0:bb348c97df44	1879	}
lypinator	0:bb348c97df44	1880
lypinator	0:bb348c97df44	1881	/**
lypinator	0:bb348c97df44	1882	* @brief Get Stream 5 transfer error flag.
lypinator	0:bb348c97df44	1883	* @rmtoll HISR TEIF0 LL_DMA_IsActiveFlag_TE5
lypinator	0:bb348c97df44	1884	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	1885	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	1886	*/
lypinator	0:bb348c97df44	1887	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx)
lypinator	0:bb348c97df44	1888	{
lypinator	0:bb348c97df44	1889	return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF5)==(DMA_HISR_TEIF5));
lypinator	0:bb348c97df44	1890	}
lypinator	0:bb348c97df44	1891
lypinator	0:bb348c97df44	1892	/**
lypinator	0:bb348c97df44	1893	* @brief Get Stream 6 transfer error flag.
lypinator	0:bb348c97df44	1894	* @rmtoll HISR TEIF6 LL_DMA_IsActiveFlag_TE6
lypinator	0:bb348c97df44	1895	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	1896	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	1897	*/
lypinator	0:bb348c97df44	1898	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx)
lypinator	0:bb348c97df44	1899	{
lypinator	0:bb348c97df44	1900	return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF6)==(DMA_HISR_TEIF6));
lypinator	0:bb348c97df44	1901	}
lypinator	0:bb348c97df44	1902
lypinator	0:bb348c97df44	1903	/**
lypinator	0:bb348c97df44	1904	* @brief Get Stream 7 transfer error flag.
lypinator	0:bb348c97df44	1905	* @rmtoll HISR TEIF7 LL_DMA_IsActiveFlag_TE7
lypinator	0:bb348c97df44	1906	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	1907	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	1908	*/
lypinator	0:bb348c97df44	1909	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx)
lypinator	0:bb348c97df44	1910	{
lypinator	0:bb348c97df44	1911	return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF7)==(DMA_HISR_TEIF7));
lypinator	0:bb348c97df44	1912	}
lypinator	0:bb348c97df44	1913
lypinator	0:bb348c97df44	1914	/**
lypinator	0:bb348c97df44	1915	* @brief Get Stream 0 direct mode error flag.
lypinator	0:bb348c97df44	1916	* @rmtoll LISR DMEIF0 LL_DMA_IsActiveFlag_DME0
lypinator	0:bb348c97df44	1917	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	1918	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	1919	*/
lypinator	0:bb348c97df44	1920	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME0(DMA_TypeDef *DMAx)
lypinator	0:bb348c97df44	1921	{
lypinator	0:bb348c97df44	1922	return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF0)==(DMA_LISR_DMEIF0));
lypinator	0:bb348c97df44	1923	}
lypinator	0:bb348c97df44	1924
lypinator	0:bb348c97df44	1925	/**
lypinator	0:bb348c97df44	1926	* @brief Get Stream 1 direct mode error flag.
lypinator	0:bb348c97df44	1927	* @rmtoll LISR DMEIF1 LL_DMA_IsActiveFlag_DME1
lypinator	0:bb348c97df44	1928	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	1929	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	1930	*/
lypinator	0:bb348c97df44	1931	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME1(DMA_TypeDef *DMAx)
lypinator	0:bb348c97df44	1932	{
lypinator	0:bb348c97df44	1933	return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF1)==(DMA_LISR_DMEIF1));
lypinator	0:bb348c97df44	1934	}
lypinator	0:bb348c97df44	1935
lypinator	0:bb348c97df44	1936	/**
lypinator	0:bb348c97df44	1937	* @brief Get Stream 2 direct mode error flag.
lypinator	0:bb348c97df44	1938	* @rmtoll LISR DMEIF2 LL_DMA_IsActiveFlag_DME2
lypinator	0:bb348c97df44	1939	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	1940	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	1941	*/
lypinator	0:bb348c97df44	1942	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME2(DMA_TypeDef *DMAx)
lypinator	0:bb348c97df44	1943	{
lypinator	0:bb348c97df44	1944	return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF2)==(DMA_LISR_DMEIF2));
lypinator	0:bb348c97df44	1945	}
lypinator	0:bb348c97df44	1946
lypinator	0:bb348c97df44	1947	/**
lypinator	0:bb348c97df44	1948	* @brief Get Stream 3 direct mode error flag.
lypinator	0:bb348c97df44	1949	* @rmtoll LISR DMEIF3 LL_DMA_IsActiveFlag_DME3
lypinator	0:bb348c97df44	1950	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	1951	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	1952	*/
lypinator	0:bb348c97df44	1953	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME3(DMA_TypeDef *DMAx)
lypinator	0:bb348c97df44	1954	{
lypinator	0:bb348c97df44	1955	return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF3)==(DMA_LISR_DMEIF3));
lypinator	0:bb348c97df44	1956	}
lypinator	0:bb348c97df44	1957
lypinator	0:bb348c97df44	1958	/**
lypinator	0:bb348c97df44	1959	* @brief Get Stream 4 direct mode error flag.
lypinator	0:bb348c97df44	1960	* @rmtoll HISR DMEIF4 LL_DMA_IsActiveFlag_DME4
lypinator	0:bb348c97df44	1961	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	1962	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	1963	*/
lypinator	0:bb348c97df44	1964	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME4(DMA_TypeDef *DMAx)
lypinator	0:bb348c97df44	1965	{
lypinator	0:bb348c97df44	1966	return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF4)==(DMA_HISR_DMEIF4));
lypinator	0:bb348c97df44	1967	}
lypinator	0:bb348c97df44	1968
lypinator	0:bb348c97df44	1969	/**
lypinator	0:bb348c97df44	1970	* @brief Get Stream 5 direct mode error flag.
lypinator	0:bb348c97df44	1971	* @rmtoll HISR DMEIF0 LL_DMA_IsActiveFlag_DME5
lypinator	0:bb348c97df44	1972	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	1973	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	1974	*/
lypinator	0:bb348c97df44	1975	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME5(DMA_TypeDef *DMAx)
lypinator	0:bb348c97df44	1976	{
lypinator	0:bb348c97df44	1977	return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF5)==(DMA_HISR_DMEIF5));
lypinator	0:bb348c97df44	1978	}
lypinator	0:bb348c97df44	1979
lypinator	0:bb348c97df44	1980	/**
lypinator	0:bb348c97df44	1981	* @brief Get Stream 6 direct mode error flag.
lypinator	0:bb348c97df44	1982	* @rmtoll HISR DMEIF6 LL_DMA_IsActiveFlag_DME6
lypinator	0:bb348c97df44	1983	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	1984	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	1985	*/
lypinator	0:bb348c97df44	1986	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME6(DMA_TypeDef *DMAx)
lypinator	0:bb348c97df44	1987	{
lypinator	0:bb348c97df44	1988	return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF6)==(DMA_HISR_DMEIF6));
lypinator	0:bb348c97df44	1989	}
lypinator	0:bb348c97df44	1990
lypinator	0:bb348c97df44	1991	/**
lypinator	0:bb348c97df44	1992	* @brief Get Stream 7 direct mode error flag.
lypinator	0:bb348c97df44	1993	* @rmtoll HISR DMEIF7 LL_DMA_IsActiveFlag_DME7
lypinator	0:bb348c97df44	1994	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	1995	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	1996	*/
lypinator	0:bb348c97df44	1997	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME7(DMA_TypeDef *DMAx)
lypinator	0:bb348c97df44	1998	{
lypinator	0:bb348c97df44	1999	return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF7)==(DMA_HISR_DMEIF7));
lypinator	0:bb348c97df44	2000	}
lypinator	0:bb348c97df44	2001
lypinator	0:bb348c97df44	2002	/**
lypinator	0:bb348c97df44	2003	* @brief Get Stream 0 FIFO error flag.
lypinator	0:bb348c97df44	2004	* @rmtoll LISR FEIF0 LL_DMA_IsActiveFlag_FE0
lypinator	0:bb348c97df44	2005	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	2006	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	2007	*/
lypinator	0:bb348c97df44	2008	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE0(DMA_TypeDef *DMAx)
lypinator	0:bb348c97df44	2009	{
lypinator	0:bb348c97df44	2010	return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF0)==(DMA_LISR_FEIF0));
lypinator	0:bb348c97df44	2011	}
lypinator	0:bb348c97df44	2012
lypinator	0:bb348c97df44	2013	/**
lypinator	0:bb348c97df44	2014	* @brief Get Stream 1 FIFO error flag.
lypinator	0:bb348c97df44	2015	* @rmtoll LISR FEIF1 LL_DMA_IsActiveFlag_FE1
lypinator	0:bb348c97df44	2016	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	2017	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	2018	*/
lypinator	0:bb348c97df44	2019	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE1(DMA_TypeDef *DMAx)
lypinator	0:bb348c97df44	2020	{
lypinator	0:bb348c97df44	2021	return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF1)==(DMA_LISR_FEIF1));
lypinator	0:bb348c97df44	2022	}
lypinator	0:bb348c97df44	2023
lypinator	0:bb348c97df44	2024	/**
lypinator	0:bb348c97df44	2025	* @brief Get Stream 2 FIFO error flag.
lypinator	0:bb348c97df44	2026	* @rmtoll LISR FEIF2 LL_DMA_IsActiveFlag_FE2
lypinator	0:bb348c97df44	2027	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	2028	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	2029	*/
lypinator	0:bb348c97df44	2030	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE2(DMA_TypeDef *DMAx)
lypinator	0:bb348c97df44	2031	{
lypinator	0:bb348c97df44	2032	return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF2)==(DMA_LISR_FEIF2));
lypinator	0:bb348c97df44	2033	}
lypinator	0:bb348c97df44	2034
lypinator	0:bb348c97df44	2035	/**
lypinator	0:bb348c97df44	2036	* @brief Get Stream 3 FIFO error flag.
lypinator	0:bb348c97df44	2037	* @rmtoll LISR FEIF3 LL_DMA_IsActiveFlag_FE3
lypinator	0:bb348c97df44	2038	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	2039	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	2040	*/
lypinator	0:bb348c97df44	2041	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE3(DMA_TypeDef *DMAx)
lypinator	0:bb348c97df44	2042	{
lypinator	0:bb348c97df44	2043	return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF3)==(DMA_LISR_FEIF3));
lypinator	0:bb348c97df44	2044	}
lypinator	0:bb348c97df44	2045
lypinator	0:bb348c97df44	2046	/**
lypinator	0:bb348c97df44	2047	* @brief Get Stream 4 FIFO error flag.
lypinator	0:bb348c97df44	2048	* @rmtoll HISR FEIF4 LL_DMA_IsActiveFlag_FE4
lypinator	0:bb348c97df44	2049	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	2050	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	2051	*/
lypinator	0:bb348c97df44	2052	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE4(DMA_TypeDef *DMAx)
lypinator	0:bb348c97df44	2053	{
lypinator	0:bb348c97df44	2054	return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF4)==(DMA_HISR_FEIF4));
lypinator	0:bb348c97df44	2055	}
lypinator	0:bb348c97df44	2056
lypinator	0:bb348c97df44	2057	/**
lypinator	0:bb348c97df44	2058	* @brief Get Stream 5 FIFO error flag.
lypinator	0:bb348c97df44	2059	* @rmtoll HISR FEIF0 LL_DMA_IsActiveFlag_FE5
lypinator	0:bb348c97df44	2060	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	2061	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	2062	*/
lypinator	0:bb348c97df44	2063	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE5(DMA_TypeDef *DMAx)
lypinator	0:bb348c97df44	2064	{
lypinator	0:bb348c97df44	2065	return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF5)==(DMA_HISR_FEIF5));
lypinator	0:bb348c97df44	2066	}
lypinator	0:bb348c97df44	2067
lypinator	0:bb348c97df44	2068	/**
lypinator	0:bb348c97df44	2069	* @brief Get Stream 6 FIFO error flag.
lypinator	0:bb348c97df44	2070	* @rmtoll HISR FEIF6 LL_DMA_IsActiveFlag_FE6
lypinator	0:bb348c97df44	2071	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	2072	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	2073	*/
lypinator	0:bb348c97df44	2074	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE6(DMA_TypeDef *DMAx)
lypinator	0:bb348c97df44	2075	{
lypinator	0:bb348c97df44	2076	return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF6)==(DMA_HISR_FEIF6));
lypinator	0:bb348c97df44	2077	}
lypinator	0:bb348c97df44	2078
lypinator	0:bb348c97df44	2079	/**
lypinator	0:bb348c97df44	2080	* @brief Get Stream 7 FIFO error flag.
lypinator	0:bb348c97df44	2081	* @rmtoll HISR FEIF7 LL_DMA_IsActiveFlag_FE7
lypinator	0:bb348c97df44	2082	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	2083	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	2084	*/
lypinator	0:bb348c97df44	2085	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE7(DMA_TypeDef *DMAx)
lypinator	0:bb348c97df44	2086	{
lypinator	0:bb348c97df44	2087	return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF7)==(DMA_HISR_FEIF7));
lypinator	0:bb348c97df44	2088	}
lypinator	0:bb348c97df44	2089
lypinator	0:bb348c97df44	2090	/**
lypinator	0:bb348c97df44	2091	* @brief Clear Stream 0 half transfer flag.
lypinator	0:bb348c97df44	2092	* @rmtoll LIFCR CHTIF0 LL_DMA_ClearFlag_HT0
lypinator	0:bb348c97df44	2093	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	2094	* @retval None
lypinator	0:bb348c97df44	2095	*/
lypinator	0:bb348c97df44	2096	__STATIC_INLINE void LL_DMA_ClearFlag_HT0(DMA_TypeDef *DMAx)
lypinator	0:bb348c97df44	2097	{
lypinator	0:bb348c97df44	2098	WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF0);
lypinator	0:bb348c97df44	2099	}
lypinator	0:bb348c97df44	2100
lypinator	0:bb348c97df44	2101	/**
lypinator	0:bb348c97df44	2102	* @brief Clear Stream 1 half transfer flag.
lypinator	0:bb348c97df44	2103	* @rmtoll LIFCR CHTIF1 LL_DMA_ClearFlag_HT1
lypinator	0:bb348c97df44	2104	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	2105	* @retval None
lypinator	0:bb348c97df44	2106	*/
lypinator	0:bb348c97df44	2107	__STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx)
lypinator	0:bb348c97df44	2108	{
lypinator	0:bb348c97df44	2109	WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF1);
lypinator	0:bb348c97df44	2110	}
lypinator	0:bb348c97df44	2111
lypinator	0:bb348c97df44	2112	/**
lypinator	0:bb348c97df44	2113	* @brief Clear Stream 2 half transfer flag.
lypinator	0:bb348c97df44	2114	* @rmtoll LIFCR CHTIF2 LL_DMA_ClearFlag_HT2
lypinator	0:bb348c97df44	2115	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	2116	* @retval None
lypinator	0:bb348c97df44	2117	*/
lypinator	0:bb348c97df44	2118	__STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx)
lypinator	0:bb348c97df44	2119	{
lypinator	0:bb348c97df44	2120	WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF2);
lypinator	0:bb348c97df44	2121	}
lypinator	0:bb348c97df44	2122
lypinator	0:bb348c97df44	2123	/**
lypinator	0:bb348c97df44	2124	* @brief Clear Stream 3 half transfer flag.
lypinator	0:bb348c97df44	2125	* @rmtoll LIFCR CHTIF3 LL_DMA_ClearFlag_HT3
lypinator	0:bb348c97df44	2126	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	2127	* @retval None
lypinator	0:bb348c97df44	2128	*/
lypinator	0:bb348c97df44	2129	__STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx)
lypinator	0:bb348c97df44	2130	{
lypinator	0:bb348c97df44	2131	WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF3);
lypinator	0:bb348c97df44	2132	}
lypinator	0:bb348c97df44	2133
lypinator	0:bb348c97df44	2134	/**
lypinator	0:bb348c97df44	2135	* @brief Clear Stream 4 half transfer flag.
lypinator	0:bb348c97df44	2136	* @rmtoll HIFCR CHTIF4 LL_DMA_ClearFlag_HT4
lypinator	0:bb348c97df44	2137	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	2138	* @retval None
lypinator	0:bb348c97df44	2139	*/
lypinator	0:bb348c97df44	2140	__STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx)
lypinator	0:bb348c97df44	2141	{
lypinator	0:bb348c97df44	2142	WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF4);
lypinator	0:bb348c97df44	2143	}
lypinator	0:bb348c97df44	2144
lypinator	0:bb348c97df44	2145	/**
lypinator	0:bb348c97df44	2146	* @brief Clear Stream 5 half transfer flag.
lypinator	0:bb348c97df44	2147	* @rmtoll HIFCR CHTIF5 LL_DMA_ClearFlag_HT5
lypinator	0:bb348c97df44	2148	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	2149	* @retval None
lypinator	0:bb348c97df44	2150	*/
lypinator	0:bb348c97df44	2151	__STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx)
lypinator	0:bb348c97df44	2152	{
lypinator	0:bb348c97df44	2153	WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF5);
lypinator	0:bb348c97df44	2154	}
lypinator	0:bb348c97df44	2155
lypinator	0:bb348c97df44	2156	/**
lypinator	0:bb348c97df44	2157	* @brief Clear Stream 6 half transfer flag.
lypinator	0:bb348c97df44	2158	* @rmtoll HIFCR CHTIF6 LL_DMA_ClearFlag_HT6
lypinator	0:bb348c97df44	2159	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	2160	* @retval None
lypinator	0:bb348c97df44	2161	*/
lypinator	0:bb348c97df44	2162	__STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx)
lypinator	0:bb348c97df44	2163	{
lypinator	0:bb348c97df44	2164	WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF6);
lypinator	0:bb348c97df44	2165	}
lypinator	0:bb348c97df44	2166
lypinator	0:bb348c97df44	2167	/**
lypinator	0:bb348c97df44	2168	* @brief Clear Stream 7 half transfer flag.
lypinator	0:bb348c97df44	2169	* @rmtoll HIFCR CHTIF7 LL_DMA_ClearFlag_HT7
lypinator	0:bb348c97df44	2170	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	2171	* @retval None
lypinator	0:bb348c97df44	2172	*/
lypinator	0:bb348c97df44	2173	__STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx)
lypinator	0:bb348c97df44	2174	{
lypinator	0:bb348c97df44	2175	WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF7);
lypinator	0:bb348c97df44	2176	}
lypinator	0:bb348c97df44	2177
lypinator	0:bb348c97df44	2178	/**
lypinator	0:bb348c97df44	2179	* @brief Clear Stream 0 transfer complete flag.
lypinator	0:bb348c97df44	2180	* @rmtoll LIFCR CTCIF0 LL_DMA_ClearFlag_TC0
lypinator	0:bb348c97df44	2181	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	2182	* @retval None
lypinator	0:bb348c97df44	2183	*/
lypinator	0:bb348c97df44	2184	__STATIC_INLINE void LL_DMA_ClearFlag_TC0(DMA_TypeDef *DMAx)
lypinator	0:bb348c97df44	2185	{
lypinator	0:bb348c97df44	2186	WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF0);
lypinator	0:bb348c97df44	2187	}
lypinator	0:bb348c97df44	2188
lypinator	0:bb348c97df44	2189	/**
lypinator	0:bb348c97df44	2190	* @brief Clear Stream 1 transfer complete flag.
lypinator	0:bb348c97df44	2191	* @rmtoll LIFCR CTCIF1 LL_DMA_ClearFlag_TC1
lypinator	0:bb348c97df44	2192	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	2193	* @retval None
lypinator	0:bb348c97df44	2194	*/
lypinator	0:bb348c97df44	2195	__STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx)
lypinator	0:bb348c97df44	2196	{
lypinator	0:bb348c97df44	2197	WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF1);
lypinator	0:bb348c97df44	2198	}
lypinator	0:bb348c97df44	2199
lypinator	0:bb348c97df44	2200	/**
lypinator	0:bb348c97df44	2201	* @brief Clear Stream 2 transfer complete flag.
lypinator	0:bb348c97df44	2202	* @rmtoll LIFCR CTCIF2 LL_DMA_ClearFlag_TC2
lypinator	0:bb348c97df44	2203	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	2204	* @retval None
lypinator	0:bb348c97df44	2205	*/
lypinator	0:bb348c97df44	2206	__STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx)
lypinator	0:bb348c97df44	2207	{
lypinator	0:bb348c97df44	2208	WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF2);
lypinator	0:bb348c97df44	2209	}
lypinator	0:bb348c97df44	2210
lypinator	0:bb348c97df44	2211	/**
lypinator	0:bb348c97df44	2212	* @brief Clear Stream 3 transfer complete flag.
lypinator	0:bb348c97df44	2213	* @rmtoll LIFCR CTCIF3 LL_DMA_ClearFlag_TC3
lypinator	0:bb348c97df44	2214	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	2215	* @retval None
lypinator	0:bb348c97df44	2216	*/
lypinator	0:bb348c97df44	2217	__STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx)
lypinator	0:bb348c97df44	2218	{
lypinator	0:bb348c97df44	2219	WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF3);
lypinator	0:bb348c97df44	2220	}
lypinator	0:bb348c97df44	2221
lypinator	0:bb348c97df44	2222	/**
lypinator	0:bb348c97df44	2223	* @brief Clear Stream 4 transfer complete flag.
lypinator	0:bb348c97df44	2224	* @rmtoll HIFCR CTCIF4 LL_DMA_ClearFlag_TC4
lypinator	0:bb348c97df44	2225	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	2226	* @retval None
lypinator	0:bb348c97df44	2227	*/
lypinator	0:bb348c97df44	2228	__STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx)
lypinator	0:bb348c97df44	2229	{
lypinator	0:bb348c97df44	2230	WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF4);
lypinator	0:bb348c97df44	2231	}
lypinator	0:bb348c97df44	2232
lypinator	0:bb348c97df44	2233	/**
lypinator	0:bb348c97df44	2234	* @brief Clear Stream 5 transfer complete flag.
lypinator	0:bb348c97df44	2235	* @rmtoll HIFCR CTCIF5 LL_DMA_ClearFlag_TC5
lypinator	0:bb348c97df44	2236	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	2237	* @retval None
lypinator	0:bb348c97df44	2238	*/
lypinator	0:bb348c97df44	2239	__STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx)
lypinator	0:bb348c97df44	2240	{
lypinator	0:bb348c97df44	2241	WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF5);
lypinator	0:bb348c97df44	2242	}
lypinator	0:bb348c97df44	2243
lypinator	0:bb348c97df44	2244	/**
lypinator	0:bb348c97df44	2245	* @brief Clear Stream 6 transfer complete flag.
lypinator	0:bb348c97df44	2246	* @rmtoll HIFCR CTCIF6 LL_DMA_ClearFlag_TC6
lypinator	0:bb348c97df44	2247	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	2248	* @retval None
lypinator	0:bb348c97df44	2249	*/
lypinator	0:bb348c97df44	2250	__STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx)
lypinator	0:bb348c97df44	2251	{
lypinator	0:bb348c97df44	2252	WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF6);
lypinator	0:bb348c97df44	2253	}
lypinator	0:bb348c97df44	2254
lypinator	0:bb348c97df44	2255	/**
lypinator	0:bb348c97df44	2256	* @brief Clear Stream 7 transfer complete flag.
lypinator	0:bb348c97df44	2257	* @rmtoll HIFCR CTCIF7 LL_DMA_ClearFlag_TC7
lypinator	0:bb348c97df44	2258	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	2259	* @retval None
lypinator	0:bb348c97df44	2260	*/
lypinator	0:bb348c97df44	2261	__STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx)
lypinator	0:bb348c97df44	2262	{
lypinator	0:bb348c97df44	2263	WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF7);
lypinator	0:bb348c97df44	2264	}
lypinator	0:bb348c97df44	2265
lypinator	0:bb348c97df44	2266	/**
lypinator	0:bb348c97df44	2267	* @brief Clear Stream 0 transfer error flag.
lypinator	0:bb348c97df44	2268	* @rmtoll LIFCR CTEIF0 LL_DMA_ClearFlag_TE0
lypinator	0:bb348c97df44	2269	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	2270	* @retval None
lypinator	0:bb348c97df44	2271	*/
lypinator	0:bb348c97df44	2272	__STATIC_INLINE void LL_DMA_ClearFlag_TE0(DMA_TypeDef *DMAx)
lypinator	0:bb348c97df44	2273	{
lypinator	0:bb348c97df44	2274	WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF0);
lypinator	0:bb348c97df44	2275	}
lypinator	0:bb348c97df44	2276
lypinator	0:bb348c97df44	2277	/**
lypinator	0:bb348c97df44	2278	* @brief Clear Stream 1 transfer error flag.
lypinator	0:bb348c97df44	2279	* @rmtoll LIFCR CTEIF1 LL_DMA_ClearFlag_TE1
lypinator	0:bb348c97df44	2280	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	2281	* @retval None
lypinator	0:bb348c97df44	2282	*/
lypinator	0:bb348c97df44	2283	__STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx)
lypinator	0:bb348c97df44	2284	{
lypinator	0:bb348c97df44	2285	WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF1);
lypinator	0:bb348c97df44	2286	}
lypinator	0:bb348c97df44	2287
lypinator	0:bb348c97df44	2288	/**
lypinator	0:bb348c97df44	2289	* @brief Clear Stream 2 transfer error flag.
lypinator	0:bb348c97df44	2290	* @rmtoll LIFCR CTEIF2 LL_DMA_ClearFlag_TE2
lypinator	0:bb348c97df44	2291	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	2292	* @retval None
lypinator	0:bb348c97df44	2293	*/
lypinator	0:bb348c97df44	2294	__STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx)
lypinator	0:bb348c97df44	2295	{
lypinator	0:bb348c97df44	2296	WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF2);
lypinator	0:bb348c97df44	2297	}
lypinator	0:bb348c97df44	2298
lypinator	0:bb348c97df44	2299	/**
lypinator	0:bb348c97df44	2300	* @brief Clear Stream 3 transfer error flag.
lypinator	0:bb348c97df44	2301	* @rmtoll LIFCR CTEIF3 LL_DMA_ClearFlag_TE3
lypinator	0:bb348c97df44	2302	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	2303	* @retval None
lypinator	0:bb348c97df44	2304	*/
lypinator	0:bb348c97df44	2305	__STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx)
lypinator	0:bb348c97df44	2306	{
lypinator	0:bb348c97df44	2307	WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF3);
lypinator	0:bb348c97df44	2308	}
lypinator	0:bb348c97df44	2309
lypinator	0:bb348c97df44	2310	/**
lypinator	0:bb348c97df44	2311	* @brief Clear Stream 4 transfer error flag.
lypinator	0:bb348c97df44	2312	* @rmtoll HIFCR CTEIF4 LL_DMA_ClearFlag_TE4
lypinator	0:bb348c97df44	2313	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	2314	* @retval None
lypinator	0:bb348c97df44	2315	*/
lypinator	0:bb348c97df44	2316	__STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx)
lypinator	0:bb348c97df44	2317	{
lypinator	0:bb348c97df44	2318	WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF4);
lypinator	0:bb348c97df44	2319	}
lypinator	0:bb348c97df44	2320
lypinator	0:bb348c97df44	2321	/**
lypinator	0:bb348c97df44	2322	* @brief Clear Stream 5 transfer error flag.
lypinator	0:bb348c97df44	2323	* @rmtoll HIFCR CTEIF5 LL_DMA_ClearFlag_TE5
lypinator	0:bb348c97df44	2324	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	2325	* @retval None
lypinator	0:bb348c97df44	2326	*/
lypinator	0:bb348c97df44	2327	__STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx)
lypinator	0:bb348c97df44	2328	{
lypinator	0:bb348c97df44	2329	WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF5);
lypinator	0:bb348c97df44	2330	}
lypinator	0:bb348c97df44	2331
lypinator	0:bb348c97df44	2332	/**
lypinator	0:bb348c97df44	2333	* @brief Clear Stream 6 transfer error flag.
lypinator	0:bb348c97df44	2334	* @rmtoll HIFCR CTEIF6 LL_DMA_ClearFlag_TE6
lypinator	0:bb348c97df44	2335	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	2336	* @retval None
lypinator	0:bb348c97df44	2337	*/
lypinator	0:bb348c97df44	2338	__STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx)
lypinator	0:bb348c97df44	2339	{
lypinator	0:bb348c97df44	2340	WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF6);
lypinator	0:bb348c97df44	2341	}
lypinator	0:bb348c97df44	2342
lypinator	0:bb348c97df44	2343	/**
lypinator	0:bb348c97df44	2344	* @brief Clear Stream 7 transfer error flag.
lypinator	0:bb348c97df44	2345	* @rmtoll HIFCR CTEIF7 LL_DMA_ClearFlag_TE7
lypinator	0:bb348c97df44	2346	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	2347	* @retval None
lypinator	0:bb348c97df44	2348	*/
lypinator	0:bb348c97df44	2349	__STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx)
lypinator	0:bb348c97df44	2350	{
lypinator	0:bb348c97df44	2351	WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF7);
lypinator	0:bb348c97df44	2352	}
lypinator	0:bb348c97df44	2353
lypinator	0:bb348c97df44	2354	/**
lypinator	0:bb348c97df44	2355	* @brief Clear Stream 0 direct mode error flag.
lypinator	0:bb348c97df44	2356	* @rmtoll LIFCR CDMEIF0 LL_DMA_ClearFlag_DME0
lypinator	0:bb348c97df44	2357	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	2358	* @retval None
lypinator	0:bb348c97df44	2359	*/
lypinator	0:bb348c97df44	2360	__STATIC_INLINE void LL_DMA_ClearFlag_DME0(DMA_TypeDef *DMAx)
lypinator	0:bb348c97df44	2361	{
lypinator	0:bb348c97df44	2362	WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF0);
lypinator	0:bb348c97df44	2363	}
lypinator	0:bb348c97df44	2364
lypinator	0:bb348c97df44	2365	/**
lypinator	0:bb348c97df44	2366	* @brief Clear Stream 1 direct mode error flag.
lypinator	0:bb348c97df44	2367	* @rmtoll LIFCR CDMEIF1 LL_DMA_ClearFlag_DME1
lypinator	0:bb348c97df44	2368	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	2369	* @retval None
lypinator	0:bb348c97df44	2370	*/
lypinator	0:bb348c97df44	2371	__STATIC_INLINE void LL_DMA_ClearFlag_DME1(DMA_TypeDef *DMAx)
lypinator	0:bb348c97df44	2372	{
lypinator	0:bb348c97df44	2373	WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF1);
lypinator	0:bb348c97df44	2374	}
lypinator	0:bb348c97df44	2375
lypinator	0:bb348c97df44	2376	/**
lypinator	0:bb348c97df44	2377	* @brief Clear Stream 2 direct mode error flag.
lypinator	0:bb348c97df44	2378	* @rmtoll LIFCR CDMEIF2 LL_DMA_ClearFlag_DME2
lypinator	0:bb348c97df44	2379	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	2380	* @retval None
lypinator	0:bb348c97df44	2381	*/
lypinator	0:bb348c97df44	2382	__STATIC_INLINE void LL_DMA_ClearFlag_DME2(DMA_TypeDef *DMAx)
lypinator	0:bb348c97df44	2383	{
lypinator	0:bb348c97df44	2384	WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF2);
lypinator	0:bb348c97df44	2385	}
lypinator	0:bb348c97df44	2386
lypinator	0:bb348c97df44	2387	/**
lypinator	0:bb348c97df44	2388	* @brief Clear Stream 3 direct mode error flag.
lypinator	0:bb348c97df44	2389	* @rmtoll LIFCR CDMEIF3 LL_DMA_ClearFlag_DME3
lypinator	0:bb348c97df44	2390	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	2391	* @retval None
lypinator	0:bb348c97df44	2392	*/
lypinator	0:bb348c97df44	2393	__STATIC_INLINE void LL_DMA_ClearFlag_DME3(DMA_TypeDef *DMAx)
lypinator	0:bb348c97df44	2394	{
lypinator	0:bb348c97df44	2395	WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF3);
lypinator	0:bb348c97df44	2396	}
lypinator	0:bb348c97df44	2397
lypinator	0:bb348c97df44	2398	/**
lypinator	0:bb348c97df44	2399	* @brief Clear Stream 4 direct mode error flag.
lypinator	0:bb348c97df44	2400	* @rmtoll HIFCR CDMEIF4 LL_DMA_ClearFlag_DME4
lypinator	0:bb348c97df44	2401	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	2402	* @retval None
lypinator	0:bb348c97df44	2403	*/
lypinator	0:bb348c97df44	2404	__STATIC_INLINE void LL_DMA_ClearFlag_DME4(DMA_TypeDef *DMAx)
lypinator	0:bb348c97df44	2405	{
lypinator	0:bb348c97df44	2406	WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF4);
lypinator	0:bb348c97df44	2407	}
lypinator	0:bb348c97df44	2408
lypinator	0:bb348c97df44	2409	/**
lypinator	0:bb348c97df44	2410	* @brief Clear Stream 5 direct mode error flag.
lypinator	0:bb348c97df44	2411	* @rmtoll HIFCR CDMEIF5 LL_DMA_ClearFlag_DME5
lypinator	0:bb348c97df44	2412	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	2413	* @retval None
lypinator	0:bb348c97df44	2414	*/
lypinator	0:bb348c97df44	2415	__STATIC_INLINE void LL_DMA_ClearFlag_DME5(DMA_TypeDef *DMAx)
lypinator	0:bb348c97df44	2416	{
lypinator	0:bb348c97df44	2417	WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF5);
lypinator	0:bb348c97df44	2418	}
lypinator	0:bb348c97df44	2419
lypinator	0:bb348c97df44	2420	/**
lypinator	0:bb348c97df44	2421	* @brief Clear Stream 6 direct mode error flag.
lypinator	0:bb348c97df44	2422	* @rmtoll HIFCR CDMEIF6 LL_DMA_ClearFlag_DME6
lypinator	0:bb348c97df44	2423	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	2424	* @retval None
lypinator	0:bb348c97df44	2425	*/
lypinator	0:bb348c97df44	2426	__STATIC_INLINE void LL_DMA_ClearFlag_DME6(DMA_TypeDef *DMAx)
lypinator	0:bb348c97df44	2427	{
lypinator	0:bb348c97df44	2428	WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF6);
lypinator	0:bb348c97df44	2429	}
lypinator	0:bb348c97df44	2430
lypinator	0:bb348c97df44	2431	/**
lypinator	0:bb348c97df44	2432	* @brief Clear Stream 7 direct mode error flag.
lypinator	0:bb348c97df44	2433	* @rmtoll HIFCR CDMEIF7 LL_DMA_ClearFlag_DME7
lypinator	0:bb348c97df44	2434	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	2435	* @retval None
lypinator	0:bb348c97df44	2436	*/
lypinator	0:bb348c97df44	2437	__STATIC_INLINE void LL_DMA_ClearFlag_DME7(DMA_TypeDef *DMAx)
lypinator	0:bb348c97df44	2438	{
lypinator	0:bb348c97df44	2439	WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF7);
lypinator	0:bb348c97df44	2440	}
lypinator	0:bb348c97df44	2441
lypinator	0:bb348c97df44	2442	/**
lypinator	0:bb348c97df44	2443	* @brief Clear Stream 0 FIFO error flag.
lypinator	0:bb348c97df44	2444	* @rmtoll LIFCR CFEIF0 LL_DMA_ClearFlag_FE0
lypinator	0:bb348c97df44	2445	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	2446	* @retval None
lypinator	0:bb348c97df44	2447	*/
lypinator	0:bb348c97df44	2448	__STATIC_INLINE void LL_DMA_ClearFlag_FE0(DMA_TypeDef *DMAx)
lypinator	0:bb348c97df44	2449	{
lypinator	0:bb348c97df44	2450	WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF0);
lypinator	0:bb348c97df44	2451	}
lypinator	0:bb348c97df44	2452
lypinator	0:bb348c97df44	2453	/**
lypinator	0:bb348c97df44	2454	* @brief Clear Stream 1 FIFO error flag.
lypinator	0:bb348c97df44	2455	* @rmtoll LIFCR CFEIF1 LL_DMA_ClearFlag_FE1
lypinator	0:bb348c97df44	2456	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	2457	* @retval None
lypinator	0:bb348c97df44	2458	*/
lypinator	0:bb348c97df44	2459	__STATIC_INLINE void LL_DMA_ClearFlag_FE1(DMA_TypeDef *DMAx)
lypinator	0:bb348c97df44	2460	{
lypinator	0:bb348c97df44	2461	WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF1);
lypinator	0:bb348c97df44	2462	}
lypinator	0:bb348c97df44	2463
lypinator	0:bb348c97df44	2464	/**
lypinator	0:bb348c97df44	2465	* @brief Clear Stream 2 FIFO error flag.
lypinator	0:bb348c97df44	2466	* @rmtoll LIFCR CFEIF2 LL_DMA_ClearFlag_FE2
lypinator	0:bb348c97df44	2467	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	2468	* @retval None
lypinator	0:bb348c97df44	2469	*/
lypinator	0:bb348c97df44	2470	__STATIC_INLINE void LL_DMA_ClearFlag_FE2(DMA_TypeDef *DMAx)
lypinator	0:bb348c97df44	2471	{
lypinator	0:bb348c97df44	2472	WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF2);
lypinator	0:bb348c97df44	2473	}
lypinator	0:bb348c97df44	2474
lypinator	0:bb348c97df44	2475	/**
lypinator	0:bb348c97df44	2476	* @brief Clear Stream 3 FIFO error flag.
lypinator	0:bb348c97df44	2477	* @rmtoll LIFCR CFEIF3 LL_DMA_ClearFlag_FE3
lypinator	0:bb348c97df44	2478	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	2479	* @retval None
lypinator	0:bb348c97df44	2480	*/
lypinator	0:bb348c97df44	2481	__STATIC_INLINE void LL_DMA_ClearFlag_FE3(DMA_TypeDef *DMAx)
lypinator	0:bb348c97df44	2482	{
lypinator	0:bb348c97df44	2483	WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF3);
lypinator	0:bb348c97df44	2484	}
lypinator	0:bb348c97df44	2485
lypinator	0:bb348c97df44	2486	/**
lypinator	0:bb348c97df44	2487	* @brief Clear Stream 4 FIFO error flag.
lypinator	0:bb348c97df44	2488	* @rmtoll HIFCR CFEIF4 LL_DMA_ClearFlag_FE4
lypinator	0:bb348c97df44	2489	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	2490	* @retval None
lypinator	0:bb348c97df44	2491	*/
lypinator	0:bb348c97df44	2492	__STATIC_INLINE void LL_DMA_ClearFlag_FE4(DMA_TypeDef *DMAx)
lypinator	0:bb348c97df44	2493	{
lypinator	0:bb348c97df44	2494	WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF4);
lypinator	0:bb348c97df44	2495	}
lypinator	0:bb348c97df44	2496
lypinator	0:bb348c97df44	2497	/**
lypinator	0:bb348c97df44	2498	* @brief Clear Stream 5 FIFO error flag.
lypinator	0:bb348c97df44	2499	* @rmtoll HIFCR CFEIF5 LL_DMA_ClearFlag_FE5
lypinator	0:bb348c97df44	2500	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	2501	* @retval None
lypinator	0:bb348c97df44	2502	*/
lypinator	0:bb348c97df44	2503	__STATIC_INLINE void LL_DMA_ClearFlag_FE5(DMA_TypeDef *DMAx)
lypinator	0:bb348c97df44	2504	{
lypinator	0:bb348c97df44	2505	WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF5);
lypinator	0:bb348c97df44	2506	}
lypinator	0:bb348c97df44	2507
lypinator	0:bb348c97df44	2508	/**
lypinator	0:bb348c97df44	2509	* @brief Clear Stream 6 FIFO error flag.
lypinator	0:bb348c97df44	2510	* @rmtoll HIFCR CFEIF6 LL_DMA_ClearFlag_FE6
lypinator	0:bb348c97df44	2511	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	2512	* @retval None
lypinator	0:bb348c97df44	2513	*/
lypinator	0:bb348c97df44	2514	__STATIC_INLINE void LL_DMA_ClearFlag_FE6(DMA_TypeDef *DMAx)
lypinator	0:bb348c97df44	2515	{
lypinator	0:bb348c97df44	2516	WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF6);
lypinator	0:bb348c97df44	2517	}
lypinator	0:bb348c97df44	2518
lypinator	0:bb348c97df44	2519	/**
lypinator	0:bb348c97df44	2520	* @brief Clear Stream 7 FIFO error flag.
lypinator	0:bb348c97df44	2521	* @rmtoll HIFCR CFEIF7 LL_DMA_ClearFlag_FE7
lypinator	0:bb348c97df44	2522	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	2523	* @retval None
lypinator	0:bb348c97df44	2524	*/
lypinator	0:bb348c97df44	2525	__STATIC_INLINE void LL_DMA_ClearFlag_FE7(DMA_TypeDef *DMAx)
lypinator	0:bb348c97df44	2526	{
lypinator	0:bb348c97df44	2527	WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF7);
lypinator	0:bb348c97df44	2528	}
lypinator	0:bb348c97df44	2529
lypinator	0:bb348c97df44	2530	/**
lypinator	0:bb348c97df44	2531	* @}
lypinator	0:bb348c97df44	2532	*/
lypinator	0:bb348c97df44	2533
lypinator	0:bb348c97df44	2534	/** @defgroup DMA_LL_EF_IT_Management IT_Management
lypinator	0:bb348c97df44	2535	* @{
lypinator	0:bb348c97df44	2536	*/
lypinator	0:bb348c97df44	2537
lypinator	0:bb348c97df44	2538	/**
lypinator	0:bb348c97df44	2539	* @brief Enable Half transfer interrupt.
lypinator	0:bb348c97df44	2540	* @rmtoll CR HTIE LL_DMA_EnableIT_HT
lypinator	0:bb348c97df44	2541	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	2542	* @param Stream This parameter can be one of the following values:
lypinator	0:bb348c97df44	2543	* @arg @ref LL_DMA_STREAM_0
lypinator	0:bb348c97df44	2544	* @arg @ref LL_DMA_STREAM_1
lypinator	0:bb348c97df44	2545	* @arg @ref LL_DMA_STREAM_2
lypinator	0:bb348c97df44	2546	* @arg @ref LL_DMA_STREAM_3
lypinator	0:bb348c97df44	2547	* @arg @ref LL_DMA_STREAM_4
lypinator	0:bb348c97df44	2548	* @arg @ref LL_DMA_STREAM_5
lypinator	0:bb348c97df44	2549	* @arg @ref LL_DMA_STREAM_6
lypinator	0:bb348c97df44	2550	* @arg @ref LL_DMA_STREAM_7
lypinator	0:bb348c97df44	2551	* @retval None
lypinator	0:bb348c97df44	2552	*/
lypinator	0:bb348c97df44	2553	__STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream)
lypinator	0:bb348c97df44	2554	{
lypinator	0:bb348c97df44	2555	SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_HTIE);
lypinator	0:bb348c97df44	2556	}
lypinator	0:bb348c97df44	2557
lypinator	0:bb348c97df44	2558	/**
lypinator	0:bb348c97df44	2559	* @brief Enable Transfer error interrupt.
lypinator	0:bb348c97df44	2560	* @rmtoll CR TEIE LL_DMA_EnableIT_TE
lypinator	0:bb348c97df44	2561	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	2562	* @param Stream This parameter can be one of the following values:
lypinator	0:bb348c97df44	2563	* @arg @ref LL_DMA_STREAM_0
lypinator	0:bb348c97df44	2564	* @arg @ref LL_DMA_STREAM_1
lypinator	0:bb348c97df44	2565	* @arg @ref LL_DMA_STREAM_2
lypinator	0:bb348c97df44	2566	* @arg @ref LL_DMA_STREAM_3
lypinator	0:bb348c97df44	2567	* @arg @ref LL_DMA_STREAM_4
lypinator	0:bb348c97df44	2568	* @arg @ref LL_DMA_STREAM_5
lypinator	0:bb348c97df44	2569	* @arg @ref LL_DMA_STREAM_6
lypinator	0:bb348c97df44	2570	* @arg @ref LL_DMA_STREAM_7
lypinator	0:bb348c97df44	2571	* @retval None
lypinator	0:bb348c97df44	2572	*/
lypinator	0:bb348c97df44	2573	__STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream)
lypinator	0:bb348c97df44	2574	{
lypinator	0:bb348c97df44	2575	SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TEIE);
lypinator	0:bb348c97df44	2576	}
lypinator	0:bb348c97df44	2577
lypinator	0:bb348c97df44	2578	/**
lypinator	0:bb348c97df44	2579	* @brief Enable Transfer complete interrupt.
lypinator	0:bb348c97df44	2580	* @rmtoll CR TCIE LL_DMA_EnableIT_TC
lypinator	0:bb348c97df44	2581	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	2582	* @param Stream This parameter can be one of the following values:
lypinator	0:bb348c97df44	2583	* @arg @ref LL_DMA_STREAM_0
lypinator	0:bb348c97df44	2584	* @arg @ref LL_DMA_STREAM_1
lypinator	0:bb348c97df44	2585	* @arg @ref LL_DMA_STREAM_2
lypinator	0:bb348c97df44	2586	* @arg @ref LL_DMA_STREAM_3
lypinator	0:bb348c97df44	2587	* @arg @ref LL_DMA_STREAM_4
lypinator	0:bb348c97df44	2588	* @arg @ref LL_DMA_STREAM_5
lypinator	0:bb348c97df44	2589	* @arg @ref LL_DMA_STREAM_6
lypinator	0:bb348c97df44	2590	* @arg @ref LL_DMA_STREAM_7
lypinator	0:bb348c97df44	2591	* @retval None
lypinator	0:bb348c97df44	2592	*/
lypinator	0:bb348c97df44	2593	__STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream)
lypinator	0:bb348c97df44	2594	{
lypinator	0:bb348c97df44	2595	SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TCIE);
lypinator	0:bb348c97df44	2596	}
lypinator	0:bb348c97df44	2597
lypinator	0:bb348c97df44	2598	/**
lypinator	0:bb348c97df44	2599	* @brief Enable Direct mode error interrupt.
lypinator	0:bb348c97df44	2600	* @rmtoll CR DMEIE LL_DMA_EnableIT_DME
lypinator	0:bb348c97df44	2601	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	2602	* @param Stream This parameter can be one of the following values:
lypinator	0:bb348c97df44	2603	* @arg @ref LL_DMA_STREAM_0
lypinator	0:bb348c97df44	2604	* @arg @ref LL_DMA_STREAM_1
lypinator	0:bb348c97df44	2605	* @arg @ref LL_DMA_STREAM_2
lypinator	0:bb348c97df44	2606	* @arg @ref LL_DMA_STREAM_3
lypinator	0:bb348c97df44	2607	* @arg @ref LL_DMA_STREAM_4
lypinator	0:bb348c97df44	2608	* @arg @ref LL_DMA_STREAM_5
lypinator	0:bb348c97df44	2609	* @arg @ref LL_DMA_STREAM_6
lypinator	0:bb348c97df44	2610	* @arg @ref LL_DMA_STREAM_7
lypinator	0:bb348c97df44	2611	* @retval None
lypinator	0:bb348c97df44	2612	*/
lypinator	0:bb348c97df44	2613	__STATIC_INLINE void LL_DMA_EnableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream)
lypinator	0:bb348c97df44	2614	{
lypinator	0:bb348c97df44	2615	SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DMEIE);
lypinator	0:bb348c97df44	2616	}
lypinator	0:bb348c97df44	2617
lypinator	0:bb348c97df44	2618	/**
lypinator	0:bb348c97df44	2619	* @brief Enable FIFO error interrupt.
lypinator	0:bb348c97df44	2620	* @rmtoll FCR FEIE LL_DMA_EnableIT_FE
lypinator	0:bb348c97df44	2621	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	2622	* @param Stream This parameter can be one of the following values:
lypinator	0:bb348c97df44	2623	* @arg @ref LL_DMA_STREAM_0
lypinator	0:bb348c97df44	2624	* @arg @ref LL_DMA_STREAM_1
lypinator	0:bb348c97df44	2625	* @arg @ref LL_DMA_STREAM_2
lypinator	0:bb348c97df44	2626	* @arg @ref LL_DMA_STREAM_3
lypinator	0:bb348c97df44	2627	* @arg @ref LL_DMA_STREAM_4
lypinator	0:bb348c97df44	2628	* @arg @ref LL_DMA_STREAM_5
lypinator	0:bb348c97df44	2629	* @arg @ref LL_DMA_STREAM_6
lypinator	0:bb348c97df44	2630	* @arg @ref LL_DMA_STREAM_7
lypinator	0:bb348c97df44	2631	* @retval None
lypinator	0:bb348c97df44	2632	*/
lypinator	0:bb348c97df44	2633	__STATIC_INLINE void LL_DMA_EnableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream)
lypinator	0:bb348c97df44	2634	{
lypinator	0:bb348c97df44	2635	SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FEIE);
lypinator	0:bb348c97df44	2636	}
lypinator	0:bb348c97df44	2637
lypinator	0:bb348c97df44	2638	/**
lypinator	0:bb348c97df44	2639	* @brief Disable Half transfer interrupt.
lypinator	0:bb348c97df44	2640	* @rmtoll CR HTIE LL_DMA_DisableIT_HT
lypinator	0:bb348c97df44	2641	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	2642	* @param Stream This parameter can be one of the following values:
lypinator	0:bb348c97df44	2643	* @arg @ref LL_DMA_STREAM_0
lypinator	0:bb348c97df44	2644	* @arg @ref LL_DMA_STREAM_1
lypinator	0:bb348c97df44	2645	* @arg @ref LL_DMA_STREAM_2
lypinator	0:bb348c97df44	2646	* @arg @ref LL_DMA_STREAM_3
lypinator	0:bb348c97df44	2647	* @arg @ref LL_DMA_STREAM_4
lypinator	0:bb348c97df44	2648	* @arg @ref LL_DMA_STREAM_5
lypinator	0:bb348c97df44	2649	* @arg @ref LL_DMA_STREAM_6
lypinator	0:bb348c97df44	2650	* @arg @ref LL_DMA_STREAM_7
lypinator	0:bb348c97df44	2651	* @retval None
lypinator	0:bb348c97df44	2652	*/
lypinator	0:bb348c97df44	2653	__STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream)
lypinator	0:bb348c97df44	2654	{
lypinator	0:bb348c97df44	2655	CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_HTIE);
lypinator	0:bb348c97df44	2656	}
lypinator	0:bb348c97df44	2657
lypinator	0:bb348c97df44	2658	/**
lypinator	0:bb348c97df44	2659	* @brief Disable Transfer error interrupt.
lypinator	0:bb348c97df44	2660	* @rmtoll CR TEIE LL_DMA_DisableIT_TE
lypinator	0:bb348c97df44	2661	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	2662	* @param Stream This parameter can be one of the following values:
lypinator	0:bb348c97df44	2663	* @arg @ref LL_DMA_STREAM_0
lypinator	0:bb348c97df44	2664	* @arg @ref LL_DMA_STREAM_1
lypinator	0:bb348c97df44	2665	* @arg @ref LL_DMA_STREAM_2
lypinator	0:bb348c97df44	2666	* @arg @ref LL_DMA_STREAM_3
lypinator	0:bb348c97df44	2667	* @arg @ref LL_DMA_STREAM_4
lypinator	0:bb348c97df44	2668	* @arg @ref LL_DMA_STREAM_5
lypinator	0:bb348c97df44	2669	* @arg @ref LL_DMA_STREAM_6
lypinator	0:bb348c97df44	2670	* @arg @ref LL_DMA_STREAM_7
lypinator	0:bb348c97df44	2671	* @retval None
lypinator	0:bb348c97df44	2672	*/
lypinator	0:bb348c97df44	2673	__STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream)
lypinator	0:bb348c97df44	2674	{
lypinator	0:bb348c97df44	2675	CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TEIE);
lypinator	0:bb348c97df44	2676	}
lypinator	0:bb348c97df44	2677
lypinator	0:bb348c97df44	2678	/**
lypinator	0:bb348c97df44	2679	* @brief Disable Transfer complete interrupt.
lypinator	0:bb348c97df44	2680	* @rmtoll CR TCIE LL_DMA_DisableIT_TC
lypinator	0:bb348c97df44	2681	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	2682	* @param Stream This parameter can be one of the following values:
lypinator	0:bb348c97df44	2683	* @arg @ref LL_DMA_STREAM_0
lypinator	0:bb348c97df44	2684	* @arg @ref LL_DMA_STREAM_1
lypinator	0:bb348c97df44	2685	* @arg @ref LL_DMA_STREAM_2
lypinator	0:bb348c97df44	2686	* @arg @ref LL_DMA_STREAM_3
lypinator	0:bb348c97df44	2687	* @arg @ref LL_DMA_STREAM_4
lypinator	0:bb348c97df44	2688	* @arg @ref LL_DMA_STREAM_5
lypinator	0:bb348c97df44	2689	* @arg @ref LL_DMA_STREAM_6
lypinator	0:bb348c97df44	2690	* @arg @ref LL_DMA_STREAM_7
lypinator	0:bb348c97df44	2691	* @retval None
lypinator	0:bb348c97df44	2692	*/
lypinator	0:bb348c97df44	2693	__STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream)
lypinator	0:bb348c97df44	2694	{
lypinator	0:bb348c97df44	2695	CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TCIE);
lypinator	0:bb348c97df44	2696	}
lypinator	0:bb348c97df44	2697
lypinator	0:bb348c97df44	2698	/**
lypinator	0:bb348c97df44	2699	* @brief Disable Direct mode error interrupt.
lypinator	0:bb348c97df44	2700	* @rmtoll CR DMEIE LL_DMA_DisableIT_DME
lypinator	0:bb348c97df44	2701	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	2702	* @param Stream This parameter can be one of the following values:
lypinator	0:bb348c97df44	2703	* @arg @ref LL_DMA_STREAM_0
lypinator	0:bb348c97df44	2704	* @arg @ref LL_DMA_STREAM_1
lypinator	0:bb348c97df44	2705	* @arg @ref LL_DMA_STREAM_2
lypinator	0:bb348c97df44	2706	* @arg @ref LL_DMA_STREAM_3
lypinator	0:bb348c97df44	2707	* @arg @ref LL_DMA_STREAM_4
lypinator	0:bb348c97df44	2708	* @arg @ref LL_DMA_STREAM_5
lypinator	0:bb348c97df44	2709	* @arg @ref LL_DMA_STREAM_6
lypinator	0:bb348c97df44	2710	* @arg @ref LL_DMA_STREAM_7
lypinator	0:bb348c97df44	2711	* @retval None
lypinator	0:bb348c97df44	2712	*/
lypinator	0:bb348c97df44	2713	__STATIC_INLINE void LL_DMA_DisableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream)
lypinator	0:bb348c97df44	2714	{
lypinator	0:bb348c97df44	2715	CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DMEIE);
lypinator	0:bb348c97df44	2716	}
lypinator	0:bb348c97df44	2717
lypinator	0:bb348c97df44	2718	/**
lypinator	0:bb348c97df44	2719	* @brief Disable FIFO error interrupt.
lypinator	0:bb348c97df44	2720	* @rmtoll FCR FEIE LL_DMA_DisableIT_FE
lypinator	0:bb348c97df44	2721	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	2722	* @param Stream This parameter can be one of the following values:
lypinator	0:bb348c97df44	2723	* @arg @ref LL_DMA_STREAM_0
lypinator	0:bb348c97df44	2724	* @arg @ref LL_DMA_STREAM_1
lypinator	0:bb348c97df44	2725	* @arg @ref LL_DMA_STREAM_2
lypinator	0:bb348c97df44	2726	* @arg @ref LL_DMA_STREAM_3
lypinator	0:bb348c97df44	2727	* @arg @ref LL_DMA_STREAM_4
lypinator	0:bb348c97df44	2728	* @arg @ref LL_DMA_STREAM_5
lypinator	0:bb348c97df44	2729	* @arg @ref LL_DMA_STREAM_6
lypinator	0:bb348c97df44	2730	* @arg @ref LL_DMA_STREAM_7
lypinator	0:bb348c97df44	2731	* @retval None
lypinator	0:bb348c97df44	2732	*/
lypinator	0:bb348c97df44	2733	__STATIC_INLINE void LL_DMA_DisableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream)
lypinator	0:bb348c97df44	2734	{
lypinator	0:bb348c97df44	2735	CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FEIE);
lypinator	0:bb348c97df44	2736	}
lypinator	0:bb348c97df44	2737
lypinator	0:bb348c97df44	2738	/**
lypinator	0:bb348c97df44	2739	* @brief Check if Half transfer interrup is enabled.
lypinator	0:bb348c97df44	2740	* @rmtoll CR HTIE LL_DMA_IsEnabledIT_HT
lypinator	0:bb348c97df44	2741	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	2742	* @param Stream This parameter can be one of the following values:
lypinator	0:bb348c97df44	2743	* @arg @ref LL_DMA_STREAM_0
lypinator	0:bb348c97df44	2744	* @arg @ref LL_DMA_STREAM_1
lypinator	0:bb348c97df44	2745	* @arg @ref LL_DMA_STREAM_2
lypinator	0:bb348c97df44	2746	* @arg @ref LL_DMA_STREAM_3
lypinator	0:bb348c97df44	2747	* @arg @ref LL_DMA_STREAM_4
lypinator	0:bb348c97df44	2748	* @arg @ref LL_DMA_STREAM_5
lypinator	0:bb348c97df44	2749	* @arg @ref LL_DMA_STREAM_6
lypinator	0:bb348c97df44	2750	* @arg @ref LL_DMA_STREAM_7
lypinator	0:bb348c97df44	2751	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	2752	*/
lypinator	0:bb348c97df44	2753	__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Stream)
lypinator	0:bb348c97df44	2754	{
lypinator	0:bb348c97df44	2755	return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_HTIE) == DMA_SxCR_HTIE);
lypinator	0:bb348c97df44	2756	}
lypinator	0:bb348c97df44	2757
lypinator	0:bb348c97df44	2758	/**
lypinator	0:bb348c97df44	2759	* @brief Check if Transfer error nterrup is enabled.
lypinator	0:bb348c97df44	2760	* @rmtoll CR TEIE LL_DMA_IsEnabledIT_TE
lypinator	0:bb348c97df44	2761	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	2762	* @param Stream This parameter can be one of the following values:
lypinator	0:bb348c97df44	2763	* @arg @ref LL_DMA_STREAM_0
lypinator	0:bb348c97df44	2764	* @arg @ref LL_DMA_STREAM_1
lypinator	0:bb348c97df44	2765	* @arg @ref LL_DMA_STREAM_2
lypinator	0:bb348c97df44	2766	* @arg @ref LL_DMA_STREAM_3
lypinator	0:bb348c97df44	2767	* @arg @ref LL_DMA_STREAM_4
lypinator	0:bb348c97df44	2768	* @arg @ref LL_DMA_STREAM_5
lypinator	0:bb348c97df44	2769	* @arg @ref LL_DMA_STREAM_6
lypinator	0:bb348c97df44	2770	* @arg @ref LL_DMA_STREAM_7
lypinator	0:bb348c97df44	2771	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	2772	*/
lypinator	0:bb348c97df44	2773	__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Stream)
lypinator	0:bb348c97df44	2774	{
lypinator	0:bb348c97df44	2775	return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TEIE) == DMA_SxCR_TEIE);
lypinator	0:bb348c97df44	2776	}
lypinator	0:bb348c97df44	2777
lypinator	0:bb348c97df44	2778	/**
lypinator	0:bb348c97df44	2779	* @brief Check if Transfer complete interrup is enabled.
lypinator	0:bb348c97df44	2780	* @rmtoll CR TCIE LL_DMA_IsEnabledIT_TC
lypinator	0:bb348c97df44	2781	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	2782	* @param Stream This parameter can be one of the following values:
lypinator	0:bb348c97df44	2783	* @arg @ref LL_DMA_STREAM_0
lypinator	0:bb348c97df44	2784	* @arg @ref LL_DMA_STREAM_1
lypinator	0:bb348c97df44	2785	* @arg @ref LL_DMA_STREAM_2
lypinator	0:bb348c97df44	2786	* @arg @ref LL_DMA_STREAM_3
lypinator	0:bb348c97df44	2787	* @arg @ref LL_DMA_STREAM_4
lypinator	0:bb348c97df44	2788	* @arg @ref LL_DMA_STREAM_5
lypinator	0:bb348c97df44	2789	* @arg @ref LL_DMA_STREAM_6
lypinator	0:bb348c97df44	2790	* @arg @ref LL_DMA_STREAM_7
lypinator	0:bb348c97df44	2791	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	2792	*/
lypinator	0:bb348c97df44	2793	__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Stream)
lypinator	0:bb348c97df44	2794	{
lypinator	0:bb348c97df44	2795	return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TCIE) == DMA_SxCR_TCIE);
lypinator	0:bb348c97df44	2796	}
lypinator	0:bb348c97df44	2797
lypinator	0:bb348c97df44	2798	/**
lypinator	0:bb348c97df44	2799	* @brief Check if Direct mode error interrupt is enabled.
lypinator	0:bb348c97df44	2800	* @rmtoll CR DMEIE LL_DMA_IsEnabledIT_DME
lypinator	0:bb348c97df44	2801	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	2802	* @param Stream This parameter can be one of the following values:
lypinator	0:bb348c97df44	2803	* @arg @ref LL_DMA_STREAM_0
lypinator	0:bb348c97df44	2804	* @arg @ref LL_DMA_STREAM_1
lypinator	0:bb348c97df44	2805	* @arg @ref LL_DMA_STREAM_2
lypinator	0:bb348c97df44	2806	* @arg @ref LL_DMA_STREAM_3
lypinator	0:bb348c97df44	2807	* @arg @ref LL_DMA_STREAM_4
lypinator	0:bb348c97df44	2808	* @arg @ref LL_DMA_STREAM_5
lypinator	0:bb348c97df44	2809	* @arg @ref LL_DMA_STREAM_6
lypinator	0:bb348c97df44	2810	* @arg @ref LL_DMA_STREAM_7
lypinator	0:bb348c97df44	2811	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	2812	*/
lypinator	0:bb348c97df44	2813	__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_DME(DMA_TypeDef *DMAx, uint32_t Stream)
lypinator	0:bb348c97df44	2814	{
lypinator	0:bb348c97df44	2815	return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DMEIE) == DMA_SxCR_DMEIE);
lypinator	0:bb348c97df44	2816	}
lypinator	0:bb348c97df44	2817
lypinator	0:bb348c97df44	2818	/**
lypinator	0:bb348c97df44	2819	* @brief Check if FIFO error interrup is enabled.
lypinator	0:bb348c97df44	2820	* @rmtoll FCR FEIE LL_DMA_IsEnabledIT_FE
lypinator	0:bb348c97df44	2821	* @param DMAx DMAx Instance
lypinator	0:bb348c97df44	2822	* @param Stream This parameter can be one of the following values:
lypinator	0:bb348c97df44	2823	* @arg @ref LL_DMA_STREAM_0
lypinator	0:bb348c97df44	2824	* @arg @ref LL_DMA_STREAM_1
lypinator	0:bb348c97df44	2825	* @arg @ref LL_DMA_STREAM_2
lypinator	0:bb348c97df44	2826	* @arg @ref LL_DMA_STREAM_3
lypinator	0:bb348c97df44	2827	* @arg @ref LL_DMA_STREAM_4
lypinator	0:bb348c97df44	2828	* @arg @ref LL_DMA_STREAM_5
lypinator	0:bb348c97df44	2829	* @arg @ref LL_DMA_STREAM_6
lypinator	0:bb348c97df44	2830	* @arg @ref LL_DMA_STREAM_7
lypinator	0:bb348c97df44	2831	* @retval State of bit (1 or 0).
lypinator	0:bb348c97df44	2832	*/
lypinator	0:bb348c97df44	2833	__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_FE(DMA_TypeDef *DMAx, uint32_t Stream)
lypinator	0:bb348c97df44	2834	{
lypinator	0:bb348c97df44	2835	return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FEIE) == DMA_SxFCR_FEIE);
lypinator	0:bb348c97df44	2836	}
lypinator	0:bb348c97df44	2837
lypinator	0:bb348c97df44	2838	/**
lypinator	0:bb348c97df44	2839	* @}
lypinator	0:bb348c97df44	2840	*/
lypinator	0:bb348c97df44	2841
lypinator	0:bb348c97df44	2842	#if defined(USE_FULL_LL_DRIVER)
lypinator	0:bb348c97df44	2843	/** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
lypinator	0:bb348c97df44	2844	* @{
lypinator	0:bb348c97df44	2845	*/
lypinator	0:bb348c97df44	2846
lypinator	0:bb348c97df44	2847	uint32_t LL_DMA_Init(DMA_TypeDef DMAx, uint32_t Stream, LL_DMA_InitTypeDef DMA_InitStruct);
lypinator	0:bb348c97df44	2848	uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Stream);
lypinator	0:bb348c97df44	2849	void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);
lypinator	0:bb348c97df44	2850
lypinator	0:bb348c97df44	2851	/**
lypinator	0:bb348c97df44	2852	* @}
lypinator	0:bb348c97df44	2853	*/
lypinator	0:bb348c97df44	2854	#endif /* USE_FULL_LL_DRIVER */
lypinator	0:bb348c97df44	2855
lypinator	0:bb348c97df44	2856	/**
lypinator	0:bb348c97df44	2857	* @}
lypinator	0:bb348c97df44	2858	*/
lypinator	0:bb348c97df44	2859
lypinator	0:bb348c97df44	2860	/**
lypinator	0:bb348c97df44	2861	* @}
lypinator	0:bb348c97df44	2862	*/
lypinator	0:bb348c97df44	2863
lypinator	0:bb348c97df44	2864	#endif /* DMA1 \|\| DMA2 */
lypinator	0:bb348c97df44	2865
lypinator	0:bb348c97df44	2866	/**
lypinator	0:bb348c97df44	2867	* @}
lypinator	0:bb348c97df44	2868	*/
lypinator	0:bb348c97df44	2869
lypinator	0:bb348c97df44	2870	#ifdef __cplusplus
lypinator	0:bb348c97df44	2871	}
lypinator	0:bb348c97df44	2872	#endif
lypinator	0:bb348c97df44	2873
lypinator	0:bb348c97df44	2874	#endif /* __STM32F4xx_LL_DMA_H */
lypinator	0:bb348c97df44	2875
lypinator	0:bb348c97df44	2876	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Program
Created:	16 Sep 2020
Imports:	1
Forks:	0
Commits:	1
Dependents:	0
Dependencies:	1
Followers:	1

mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_dma.h@0:bb348c97df44, 2020-09-16 (annotated)

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