Thomas Lyp / DevLibMemoryController

Initial commit

Dependencies:   FastPWM

mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_cortex.h@0:bb348c97df44, 2020-09-16 (annotated)

Committer:
lypinator
Date:
Wed Sep 16 01:11:49 2020 +0000
Revision:
0:bb348c97df44
Added PWM

Who changed what in which revision?

UserRevisionLine numberNew contents of line
lypinator 0:bb348c97df44 1 /**
lypinator 0:bb348c97df44 2 ******************************************************************************
lypinator 0:bb348c97df44 3 * @file stm32f4xx_ll_cortex.h
lypinator 0:bb348c97df44 4 * @author MCD Application Team
lypinator 0:bb348c97df44 5 * @brief Header file of CORTEX LL module.
lypinator 0:bb348c97df44 6 @verbatim
lypinator 0:bb348c97df44 7 ==============================================================================
lypinator 0:bb348c97df44 8 ##### How to use this driver #####
lypinator 0:bb348c97df44 9 ==============================================================================
lypinator 0:bb348c97df44 10 [..]
lypinator 0:bb348c97df44 11 The LL CORTEX driver contains a set of generic APIs that can be
lypinator 0:bb348c97df44 12 used by user:
lypinator 0:bb348c97df44 13 (+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick
lypinator 0:bb348c97df44 14 functions
lypinator 0:bb348c97df44 15 (+) Low power mode configuration (SCB register of Cortex-MCU)
lypinator 0:bb348c97df44 16 (+) MPU API to configure and enable regions
lypinator 0:bb348c97df44 17 (MPU services provided only on some devices)
lypinator 0:bb348c97df44 18 (+) API to access to MCU info (CPUID register)
lypinator 0:bb348c97df44 19 (+) API to enable fault handler (SHCSR accesses)
lypinator 0:bb348c97df44 20
lypinator 0:bb348c97df44 21 @endverbatim
lypinator 0:bb348c97df44 22 ******************************************************************************
lypinator 0:bb348c97df44 23 * @attention
lypinator 0:bb348c97df44 24 *
lypinator 0:bb348c97df44 25 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
lypinator 0:bb348c97df44 26 *
lypinator 0:bb348c97df44 27 * Redistribution and use in source and binary forms, with or without modification,
lypinator 0:bb348c97df44 28 * are permitted provided that the following conditions are met:
lypinator 0:bb348c97df44 29 * 1. Redistributions of source code must retain the above copyright notice,
lypinator 0:bb348c97df44 30 * this list of conditions and the following disclaimer.
lypinator 0:bb348c97df44 31 * 2. Redistributions in binary form must reproduce the above copyright notice,
lypinator 0:bb348c97df44 32 * this list of conditions and the following disclaimer in the documentation
lypinator 0:bb348c97df44 33 * and/or other materials provided with the distribution.
lypinator 0:bb348c97df44 34 * 3. Neither the name of STMicroelectronics nor the names of its contributors
lypinator 0:bb348c97df44 35 * may be used to endorse or promote products derived from this software
lypinator 0:bb348c97df44 36 * without specific prior written permission.
lypinator 0:bb348c97df44 37 *
lypinator 0:bb348c97df44 38 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
lypinator 0:bb348c97df44 39 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
lypinator 0:bb348c97df44 40 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
lypinator 0:bb348c97df44 41 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
lypinator 0:bb348c97df44 42 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
lypinator 0:bb348c97df44 43 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
lypinator 0:bb348c97df44 44 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
lypinator 0:bb348c97df44 45 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
lypinator 0:bb348c97df44 46 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
lypinator 0:bb348c97df44 47 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
lypinator 0:bb348c97df44 48 *
lypinator 0:bb348c97df44 49 ******************************************************************************
lypinator 0:bb348c97df44 50 */
lypinator 0:bb348c97df44 51
lypinator 0:bb348c97df44 52 /* Define to prevent recursive inclusion -------------------------------------*/
lypinator 0:bb348c97df44 53 #ifndef __STM32F4xx_LL_CORTEX_H
lypinator 0:bb348c97df44 54 #define __STM32F4xx_LL_CORTEX_H
lypinator 0:bb348c97df44 55
lypinator 0:bb348c97df44 56 #ifdef __cplusplus
lypinator 0:bb348c97df44 57 extern "C" {
lypinator 0:bb348c97df44 58 #endif
lypinator 0:bb348c97df44 59
lypinator 0:bb348c97df44 60 /* Includes ------------------------------------------------------------------*/
lypinator 0:bb348c97df44 61 #include "stm32f4xx.h"
lypinator 0:bb348c97df44 62
lypinator 0:bb348c97df44 63 /** @addtogroup STM32F4xx_LL_Driver
lypinator 0:bb348c97df44 64 * @{
lypinator 0:bb348c97df44 65 */
lypinator 0:bb348c97df44 66
lypinator 0:bb348c97df44 67 /** @defgroup CORTEX_LL CORTEX
lypinator 0:bb348c97df44 68 * @{
lypinator 0:bb348c97df44 69 */
lypinator 0:bb348c97df44 70
lypinator 0:bb348c97df44 71 /* Private types -------------------------------------------------------------*/
lypinator 0:bb348c97df44 72 /* Private variables ---------------------------------------------------------*/
lypinator 0:bb348c97df44 73
lypinator 0:bb348c97df44 74 /* Private constants ---------------------------------------------------------*/
lypinator 0:bb348c97df44 75
lypinator 0:bb348c97df44 76 /* Private macros ------------------------------------------------------------*/
lypinator 0:bb348c97df44 77
lypinator 0:bb348c97df44 78 /* Exported types ------------------------------------------------------------*/
lypinator 0:bb348c97df44 79 /* Exported constants --------------------------------------------------------*/
lypinator 0:bb348c97df44 80 /** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants
lypinator 0:bb348c97df44 81 * @{
lypinator 0:bb348c97df44 82 */
lypinator 0:bb348c97df44 83
lypinator 0:bb348c97df44 84 /** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source
lypinator 0:bb348c97df44 85 * @{
lypinator 0:bb348c97df44 86 */
lypinator 0:bb348c97df44 87 #define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U /*!< AHB clock divided by 8 selected as SysTick clock source.*/
lypinator 0:bb348c97df44 88 #define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick clock source. */
lypinator 0:bb348c97df44 89 /**
lypinator 0:bb348c97df44 90 * @}
lypinator 0:bb348c97df44 91 */
lypinator 0:bb348c97df44 92
lypinator 0:bb348c97df44 93 /** @defgroup CORTEX_LL_EC_FAULT Handler Fault type
lypinator 0:bb348c97df44 94 * @{
lypinator 0:bb348c97df44 95 */
lypinator 0:bb348c97df44 96 #define LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk /*!< Usage fault */
lypinator 0:bb348c97df44 97 #define LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk /*!< Bus fault */
lypinator 0:bb348c97df44 98 #define LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk /*!< Memory management fault */
lypinator 0:bb348c97df44 99 /**
lypinator 0:bb348c97df44 100 * @}
lypinator 0:bb348c97df44 101 */
lypinator 0:bb348c97df44 102
lypinator 0:bb348c97df44 103 #if __MPU_PRESENT
lypinator 0:bb348c97df44 104
lypinator 0:bb348c97df44 105 /** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control
lypinator 0:bb348c97df44 106 * @{
lypinator 0:bb348c97df44 107 */
lypinator 0:bb348c97df44 108 #define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0x00000000U /*!< Disable NMI and privileged SW access */
lypinator 0:bb348c97df44 109 #define LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */
lypinator 0:bb348c97df44 110 #define LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk /*!< Enable privileged software access to default memory map */
lypinator 0:bb348c97df44 111 #define LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */
lypinator 0:bb348c97df44 112 /**
lypinator 0:bb348c97df44 113 * @}
lypinator 0:bb348c97df44 114 */
lypinator 0:bb348c97df44 115
lypinator 0:bb348c97df44 116 /** @defgroup CORTEX_LL_EC_REGION MPU Region Number
lypinator 0:bb348c97df44 117 * @{
lypinator 0:bb348c97df44 118 */
lypinator 0:bb348c97df44 119 #define LL_MPU_REGION_NUMBER0 0x00U /*!< REGION Number 0 */
lypinator 0:bb348c97df44 120 #define LL_MPU_REGION_NUMBER1 0x01U /*!< REGION Number 1 */
lypinator 0:bb348c97df44 121 #define LL_MPU_REGION_NUMBER2 0x02U /*!< REGION Number 2 */
lypinator 0:bb348c97df44 122 #define LL_MPU_REGION_NUMBER3 0x03U /*!< REGION Number 3 */
lypinator 0:bb348c97df44 123 #define LL_MPU_REGION_NUMBER4 0x04U /*!< REGION Number 4 */
lypinator 0:bb348c97df44 124 #define LL_MPU_REGION_NUMBER5 0x05U /*!< REGION Number 5 */
lypinator 0:bb348c97df44 125 #define LL_MPU_REGION_NUMBER6 0x06U /*!< REGION Number 6 */
lypinator 0:bb348c97df44 126 #define LL_MPU_REGION_NUMBER7 0x07U /*!< REGION Number 7 */
lypinator 0:bb348c97df44 127 /**
lypinator 0:bb348c97df44 128 * @}
lypinator 0:bb348c97df44 129 */
lypinator 0:bb348c97df44 130
lypinator 0:bb348c97df44 131 /** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size
lypinator 0:bb348c97df44 132 * @{
lypinator 0:bb348c97df44 133 */
lypinator 0:bb348c97df44 134 #define LL_MPU_REGION_SIZE_32B (0x04U << MPU_RASR_SIZE_Pos) /*!< 32B Size of the MPU protection region */
lypinator 0:bb348c97df44 135 #define LL_MPU_REGION_SIZE_64B (0x05U << MPU_RASR_SIZE_Pos) /*!< 64B Size of the MPU protection region */
lypinator 0:bb348c97df44 136 #define LL_MPU_REGION_SIZE_128B (0x06U << MPU_RASR_SIZE_Pos) /*!< 128B Size of the MPU protection region */
lypinator 0:bb348c97df44 137 #define LL_MPU_REGION_SIZE_256B (0x07U << MPU_RASR_SIZE_Pos) /*!< 256B Size of the MPU protection region */
lypinator 0:bb348c97df44 138 #define LL_MPU_REGION_SIZE_512B (0x08U << MPU_RASR_SIZE_Pos) /*!< 512B Size of the MPU protection region */
lypinator 0:bb348c97df44 139 #define LL_MPU_REGION_SIZE_1KB (0x09U << MPU_RASR_SIZE_Pos) /*!< 1KB Size of the MPU protection region */
lypinator 0:bb348c97df44 140 #define LL_MPU_REGION_SIZE_2KB (0x0AU << MPU_RASR_SIZE_Pos) /*!< 2KB Size of the MPU protection region */
lypinator 0:bb348c97df44 141 #define LL_MPU_REGION_SIZE_4KB (0x0BU << MPU_RASR_SIZE_Pos) /*!< 4KB Size of the MPU protection region */
lypinator 0:bb348c97df44 142 #define LL_MPU_REGION_SIZE_8KB (0x0CU << MPU_RASR_SIZE_Pos) /*!< 8KB Size of the MPU protection region */
lypinator 0:bb348c97df44 143 #define LL_MPU_REGION_SIZE_16KB (0x0DU << MPU_RASR_SIZE_Pos) /*!< 16KB Size of the MPU protection region */
lypinator 0:bb348c97df44 144 #define LL_MPU_REGION_SIZE_32KB (0x0EU << MPU_RASR_SIZE_Pos) /*!< 32KB Size of the MPU protection region */
lypinator 0:bb348c97df44 145 #define LL_MPU_REGION_SIZE_64KB (0x0FU << MPU_RASR_SIZE_Pos) /*!< 64KB Size of the MPU protection region */
lypinator 0:bb348c97df44 146 #define LL_MPU_REGION_SIZE_128KB (0x10U << MPU_RASR_SIZE_Pos) /*!< 128KB Size of the MPU protection region */
lypinator 0:bb348c97df44 147 #define LL_MPU_REGION_SIZE_256KB (0x11U << MPU_RASR_SIZE_Pos) /*!< 256KB Size of the MPU protection region */
lypinator 0:bb348c97df44 148 #define LL_MPU_REGION_SIZE_512KB (0x12U << MPU_RASR_SIZE_Pos) /*!< 512KB Size of the MPU protection region */
lypinator 0:bb348c97df44 149 #define LL_MPU_REGION_SIZE_1MB (0x13U << MPU_RASR_SIZE_Pos) /*!< 1MB Size of the MPU protection region */
lypinator 0:bb348c97df44 150 #define LL_MPU_REGION_SIZE_2MB (0x14U << MPU_RASR_SIZE_Pos) /*!< 2MB Size of the MPU protection region */
lypinator 0:bb348c97df44 151 #define LL_MPU_REGION_SIZE_4MB (0x15U << MPU_RASR_SIZE_Pos) /*!< 4MB Size of the MPU protection region */
lypinator 0:bb348c97df44 152 #define LL_MPU_REGION_SIZE_8MB (0x16U << MPU_RASR_SIZE_Pos) /*!< 8MB Size of the MPU protection region */
lypinator 0:bb348c97df44 153 #define LL_MPU_REGION_SIZE_16MB (0x17U << MPU_RASR_SIZE_Pos) /*!< 16MB Size of the MPU protection region */
lypinator 0:bb348c97df44 154 #define LL_MPU_REGION_SIZE_32MB (0x18U << MPU_RASR_SIZE_Pos) /*!< 32MB Size of the MPU protection region */
lypinator 0:bb348c97df44 155 #define LL_MPU_REGION_SIZE_64MB (0x19U << MPU_RASR_SIZE_Pos) /*!< 64MB Size of the MPU protection region */
lypinator 0:bb348c97df44 156 #define LL_MPU_REGION_SIZE_128MB (0x1AU << MPU_RASR_SIZE_Pos) /*!< 128MB Size of the MPU protection region */
lypinator 0:bb348c97df44 157 #define LL_MPU_REGION_SIZE_256MB (0x1BU << MPU_RASR_SIZE_Pos) /*!< 256MB Size of the MPU protection region */
lypinator 0:bb348c97df44 158 #define LL_MPU_REGION_SIZE_512MB (0x1CU << MPU_RASR_SIZE_Pos) /*!< 512MB Size of the MPU protection region */
lypinator 0:bb348c97df44 159 #define LL_MPU_REGION_SIZE_1GB (0x1DU << MPU_RASR_SIZE_Pos) /*!< 1GB Size of the MPU protection region */
lypinator 0:bb348c97df44 160 #define LL_MPU_REGION_SIZE_2GB (0x1EU << MPU_RASR_SIZE_Pos) /*!< 2GB Size of the MPU protection region */
lypinator 0:bb348c97df44 161 #define LL_MPU_REGION_SIZE_4GB (0x1FU << MPU_RASR_SIZE_Pos) /*!< 4GB Size of the MPU protection region */
lypinator 0:bb348c97df44 162 /**
lypinator 0:bb348c97df44 163 * @}
lypinator 0:bb348c97df44 164 */
lypinator 0:bb348c97df44 165
lypinator 0:bb348c97df44 166 /** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges
lypinator 0:bb348c97df44 167 * @{
lypinator 0:bb348c97df44 168 */
lypinator 0:bb348c97df44 169 #define LL_MPU_REGION_NO_ACCESS (0x00U << MPU_RASR_AP_Pos) /*!< No access*/
lypinator 0:bb348c97df44 170 #define LL_MPU_REGION_PRIV_RW (0x01U << MPU_RASR_AP_Pos) /*!< RW privileged (privileged access only)*/
lypinator 0:bb348c97df44 171 #define LL_MPU_REGION_PRIV_RW_URO (0x02U << MPU_RASR_AP_Pos) /*!< RW privileged - RO user (Write in a user program generates a fault) */
lypinator 0:bb348c97df44 172 #define LL_MPU_REGION_FULL_ACCESS (0x03U << MPU_RASR_AP_Pos) /*!< RW privileged & user (Full access) */
lypinator 0:bb348c97df44 173 #define LL_MPU_REGION_PRIV_RO (0x05U << MPU_RASR_AP_Pos) /*!< RO privileged (privileged read only)*/
lypinator 0:bb348c97df44 174 #define LL_MPU_REGION_PRIV_RO_URO (0x06U << MPU_RASR_AP_Pos) /*!< RO privileged & user (read only) */
lypinator 0:bb348c97df44 175 /**
lypinator 0:bb348c97df44 176 * @}
lypinator 0:bb348c97df44 177 */
lypinator 0:bb348c97df44 178
lypinator 0:bb348c97df44 179 /** @defgroup CORTEX_LL_EC_TEX MPU TEX Level
lypinator 0:bb348c97df44 180 * @{
lypinator 0:bb348c97df44 181 */
lypinator 0:bb348c97df44 182 #define LL_MPU_TEX_LEVEL0 (0x00U << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */
lypinator 0:bb348c97df44 183 #define LL_MPU_TEX_LEVEL1 (0x01U << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */
lypinator 0:bb348c97df44 184 #define LL_MPU_TEX_LEVEL2 (0x02U << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */
lypinator 0:bb348c97df44 185 #define LL_MPU_TEX_LEVEL4 (0x04U << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits */
lypinator 0:bb348c97df44 186 /**
lypinator 0:bb348c97df44 187 * @}
lypinator 0:bb348c97df44 188 */
lypinator 0:bb348c97df44 189
lypinator 0:bb348c97df44 190 /** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access
lypinator 0:bb348c97df44 191 * @{
lypinator 0:bb348c97df44 192 */
lypinator 0:bb348c97df44 193 #define LL_MPU_INSTRUCTION_ACCESS_ENABLE 0x00U /*!< Instruction fetches enabled */
lypinator 0:bb348c97df44 194 #define LL_MPU_INSTRUCTION_ACCESS_DISABLE MPU_RASR_XN_Msk /*!< Instruction fetches disabled*/
lypinator 0:bb348c97df44 195 /**
lypinator 0:bb348c97df44 196 * @}
lypinator 0:bb348c97df44 197 */
lypinator 0:bb348c97df44 198
lypinator 0:bb348c97df44 199 /** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access
lypinator 0:bb348c97df44 200 * @{
lypinator 0:bb348c97df44 201 */
lypinator 0:bb348c97df44 202 #define LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_Msk /*!< Shareable memory attribute */
lypinator 0:bb348c97df44 203 #define LL_MPU_ACCESS_NOT_SHAREABLE 0x00U /*!< Not Shareable memory attribute */
lypinator 0:bb348c97df44 204 /**
lypinator 0:bb348c97df44 205 * @}
lypinator 0:bb348c97df44 206 */
lypinator 0:bb348c97df44 207
lypinator 0:bb348c97df44 208 /** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access
lypinator 0:bb348c97df44 209 * @{
lypinator 0:bb348c97df44 210 */
lypinator 0:bb348c97df44 211 #define LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_Msk /*!< Cacheable memory attribute */
lypinator 0:bb348c97df44 212 #define LL_MPU_ACCESS_NOT_CACHEABLE 0x00U /*!< Not Cacheable memory attribute */
lypinator 0:bb348c97df44 213 /**
lypinator 0:bb348c97df44 214 * @}
lypinator 0:bb348c97df44 215 */
lypinator 0:bb348c97df44 216
lypinator 0:bb348c97df44 217 /** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access
lypinator 0:bb348c97df44 218 * @{
lypinator 0:bb348c97df44 219 */
lypinator 0:bb348c97df44 220 #define LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_Msk /*!< Bufferable memory attribute */
lypinator 0:bb348c97df44 221 #define LL_MPU_ACCESS_NOT_BUFFERABLE 0x00U /*!< Not Bufferable memory attribute */
lypinator 0:bb348c97df44 222 /**
lypinator 0:bb348c97df44 223 * @}
lypinator 0:bb348c97df44 224 */
lypinator 0:bb348c97df44 225 #endif /* __MPU_PRESENT */
lypinator 0:bb348c97df44 226 /**
lypinator 0:bb348c97df44 227 * @}
lypinator 0:bb348c97df44 228 */
lypinator 0:bb348c97df44 229
lypinator 0:bb348c97df44 230 /* Exported macro ------------------------------------------------------------*/
lypinator 0:bb348c97df44 231
lypinator 0:bb348c97df44 232 /* Exported functions --------------------------------------------------------*/
lypinator 0:bb348c97df44 233 /** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions
lypinator 0:bb348c97df44 234 * @{
lypinator 0:bb348c97df44 235 */
lypinator 0:bb348c97df44 236
lypinator 0:bb348c97df44 237 /** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK
lypinator 0:bb348c97df44 238 * @{
lypinator 0:bb348c97df44 239 */
lypinator 0:bb348c97df44 240
lypinator 0:bb348c97df44 241 /**
lypinator 0:bb348c97df44 242 * @brief This function checks if the Systick counter flag is active or not.
lypinator 0:bb348c97df44 243 * @note It can be used in timeout function on application side.
lypinator 0:bb348c97df44 244 * @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag
lypinator 0:bb348c97df44 245 * @retval State of bit (1 or 0).
lypinator 0:bb348c97df44 246 */
lypinator 0:bb348c97df44 247 __STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void)
lypinator 0:bb348c97df44 248 {
lypinator 0:bb348c97df44 249 return ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk));
lypinator 0:bb348c97df44 250 }
lypinator 0:bb348c97df44 251
lypinator 0:bb348c97df44 252 /**
lypinator 0:bb348c97df44 253 * @brief Configures the SysTick clock source
lypinator 0:bb348c97df44 254 * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource
lypinator 0:bb348c97df44 255 * @param Source This parameter can be one of the following values:
lypinator 0:bb348c97df44 256 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
lypinator 0:bb348c97df44 257 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
lypinator 0:bb348c97df44 258 * @retval None
lypinator 0:bb348c97df44 259 */
lypinator 0:bb348c97df44 260 __STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source)
lypinator 0:bb348c97df44 261 {
lypinator 0:bb348c97df44 262 if (Source == LL_SYSTICK_CLKSOURCE_HCLK)
lypinator 0:bb348c97df44 263 {
lypinator 0:bb348c97df44 264 SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
lypinator 0:bb348c97df44 265 }
lypinator 0:bb348c97df44 266 else
lypinator 0:bb348c97df44 267 {
lypinator 0:bb348c97df44 268 CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
lypinator 0:bb348c97df44 269 }
lypinator 0:bb348c97df44 270 }
lypinator 0:bb348c97df44 271
lypinator 0:bb348c97df44 272 /**
lypinator 0:bb348c97df44 273 * @brief Get the SysTick clock source
lypinator 0:bb348c97df44 274 * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource
lypinator 0:bb348c97df44 275 * @retval Returned value can be one of the following values:
lypinator 0:bb348c97df44 276 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
lypinator 0:bb348c97df44 277 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
lypinator 0:bb348c97df44 278 */
lypinator 0:bb348c97df44 279 __STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void)
lypinator 0:bb348c97df44 280 {
lypinator 0:bb348c97df44 281 return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
lypinator 0:bb348c97df44 282 }
lypinator 0:bb348c97df44 283
lypinator 0:bb348c97df44 284 /**
lypinator 0:bb348c97df44 285 * @brief Enable SysTick exception request
lypinator 0:bb348c97df44 286 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT
lypinator 0:bb348c97df44 287 * @retval None
lypinator 0:bb348c97df44 288 */
lypinator 0:bb348c97df44 289 __STATIC_INLINE void LL_SYSTICK_EnableIT(void)
lypinator 0:bb348c97df44 290 {
lypinator 0:bb348c97df44 291 SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
lypinator 0:bb348c97df44 292 }
lypinator 0:bb348c97df44 293
lypinator 0:bb348c97df44 294 /**
lypinator 0:bb348c97df44 295 * @brief Disable SysTick exception request
lypinator 0:bb348c97df44 296 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT
lypinator 0:bb348c97df44 297 * @retval None
lypinator 0:bb348c97df44 298 */
lypinator 0:bb348c97df44 299 __STATIC_INLINE void LL_SYSTICK_DisableIT(void)
lypinator 0:bb348c97df44 300 {
lypinator 0:bb348c97df44 301 CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
lypinator 0:bb348c97df44 302 }
lypinator 0:bb348c97df44 303
lypinator 0:bb348c97df44 304 /**
lypinator 0:bb348c97df44 305 * @brief Checks if the SYSTICK interrupt is enabled or disabled.
lypinator 0:bb348c97df44 306 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT
lypinator 0:bb348c97df44 307 * @retval State of bit (1 or 0).
lypinator 0:bb348c97df44 308 */
lypinator 0:bb348c97df44 309 __STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void)
lypinator 0:bb348c97df44 310 {
lypinator 0:bb348c97df44 311 return (READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk));
lypinator 0:bb348c97df44 312 }
lypinator 0:bb348c97df44 313
lypinator 0:bb348c97df44 314 /**
lypinator 0:bb348c97df44 315 * @}
lypinator 0:bb348c97df44 316 */
lypinator 0:bb348c97df44 317
lypinator 0:bb348c97df44 318 /** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE
lypinator 0:bb348c97df44 319 * @{
lypinator 0:bb348c97df44 320 */
lypinator 0:bb348c97df44 321
lypinator 0:bb348c97df44 322 /**
lypinator 0:bb348c97df44 323 * @brief Processor uses sleep as its low power mode
lypinator 0:bb348c97df44 324 * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep
lypinator 0:bb348c97df44 325 * @retval None
lypinator 0:bb348c97df44 326 */
lypinator 0:bb348c97df44 327 __STATIC_INLINE void LL_LPM_EnableSleep(void)
lypinator 0:bb348c97df44 328 {
lypinator 0:bb348c97df44 329 /* Clear SLEEPDEEP bit of Cortex System Control Register */
lypinator 0:bb348c97df44 330 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
lypinator 0:bb348c97df44 331 }
lypinator 0:bb348c97df44 332
lypinator 0:bb348c97df44 333 /**
lypinator 0:bb348c97df44 334 * @brief Processor uses deep sleep as its low power mode
lypinator 0:bb348c97df44 335 * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep
lypinator 0:bb348c97df44 336 * @retval None
lypinator 0:bb348c97df44 337 */
lypinator 0:bb348c97df44 338 __STATIC_INLINE void LL_LPM_EnableDeepSleep(void)
lypinator 0:bb348c97df44 339 {
lypinator 0:bb348c97df44 340 /* Set SLEEPDEEP bit of Cortex System Control Register */
lypinator 0:bb348c97df44 341 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
lypinator 0:bb348c97df44 342 }
lypinator 0:bb348c97df44 343
lypinator 0:bb348c97df44 344 /**
lypinator 0:bb348c97df44 345 * @brief Configures sleep-on-exit when returning from Handler mode to Thread mode.
lypinator 0:bb348c97df44 346 * @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an
lypinator 0:bb348c97df44 347 * empty main application.
lypinator 0:bb348c97df44 348 * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit
lypinator 0:bb348c97df44 349 * @retval None
lypinator 0:bb348c97df44 350 */
lypinator 0:bb348c97df44 351 __STATIC_INLINE void LL_LPM_EnableSleepOnExit(void)
lypinator 0:bb348c97df44 352 {
lypinator 0:bb348c97df44 353 /* Set SLEEPONEXIT bit of Cortex System Control Register */
lypinator 0:bb348c97df44 354 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
lypinator 0:bb348c97df44 355 }
lypinator 0:bb348c97df44 356
lypinator 0:bb348c97df44 357 /**
lypinator 0:bb348c97df44 358 * @brief Do not sleep when returning to Thread mode.
lypinator 0:bb348c97df44 359 * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit
lypinator 0:bb348c97df44 360 * @retval None
lypinator 0:bb348c97df44 361 */
lypinator 0:bb348c97df44 362 __STATIC_INLINE void LL_LPM_DisableSleepOnExit(void)
lypinator 0:bb348c97df44 363 {
lypinator 0:bb348c97df44 364 /* Clear SLEEPONEXIT bit of Cortex System Control Register */
lypinator 0:bb348c97df44 365 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
lypinator 0:bb348c97df44 366 }
lypinator 0:bb348c97df44 367
lypinator 0:bb348c97df44 368 /**
lypinator 0:bb348c97df44 369 * @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the
lypinator 0:bb348c97df44 370 * processor.
lypinator 0:bb348c97df44 371 * @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend
lypinator 0:bb348c97df44 372 * @retval None
lypinator 0:bb348c97df44 373 */
lypinator 0:bb348c97df44 374 __STATIC_INLINE void LL_LPM_EnableEventOnPend(void)
lypinator 0:bb348c97df44 375 {
lypinator 0:bb348c97df44 376 /* Set SEVEONPEND bit of Cortex System Control Register */
lypinator 0:bb348c97df44 377 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
lypinator 0:bb348c97df44 378 }
lypinator 0:bb348c97df44 379
lypinator 0:bb348c97df44 380 /**
lypinator 0:bb348c97df44 381 * @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are
lypinator 0:bb348c97df44 382 * excluded
lypinator 0:bb348c97df44 383 * @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend
lypinator 0:bb348c97df44 384 * @retval None
lypinator 0:bb348c97df44 385 */
lypinator 0:bb348c97df44 386 __STATIC_INLINE void LL_LPM_DisableEventOnPend(void)
lypinator 0:bb348c97df44 387 {
lypinator 0:bb348c97df44 388 /* Clear SEVEONPEND bit of Cortex System Control Register */
lypinator 0:bb348c97df44 389 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
lypinator 0:bb348c97df44 390 }
lypinator 0:bb348c97df44 391
lypinator 0:bb348c97df44 392 /**
lypinator 0:bb348c97df44 393 * @}
lypinator 0:bb348c97df44 394 */
lypinator 0:bb348c97df44 395
lypinator 0:bb348c97df44 396 /** @defgroup CORTEX_LL_EF_HANDLER HANDLER
lypinator 0:bb348c97df44 397 * @{
lypinator 0:bb348c97df44 398 */
lypinator 0:bb348c97df44 399
lypinator 0:bb348c97df44 400 /**
lypinator 0:bb348c97df44 401 * @brief Enable a fault in System handler control register (SHCSR)
lypinator 0:bb348c97df44 402 * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_EnableFault
lypinator 0:bb348c97df44 403 * @param Fault This parameter can be a combination of the following values:
lypinator 0:bb348c97df44 404 * @arg @ref LL_HANDLER_FAULT_USG
lypinator 0:bb348c97df44 405 * @arg @ref LL_HANDLER_FAULT_BUS
lypinator 0:bb348c97df44 406 * @arg @ref LL_HANDLER_FAULT_MEM
lypinator 0:bb348c97df44 407 * @retval None
lypinator 0:bb348c97df44 408 */
lypinator 0:bb348c97df44 409 __STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault)
lypinator 0:bb348c97df44 410 {
lypinator 0:bb348c97df44 411 /* Enable the system handler fault */
lypinator 0:bb348c97df44 412 SET_BIT(SCB->SHCSR, Fault);
lypinator 0:bb348c97df44 413 }
lypinator 0:bb348c97df44 414
lypinator 0:bb348c97df44 415 /**
lypinator 0:bb348c97df44 416 * @brief Disable a fault in System handler control register (SHCSR)
lypinator 0:bb348c97df44 417 * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_DisableFault
lypinator 0:bb348c97df44 418 * @param Fault This parameter can be a combination of the following values:
lypinator 0:bb348c97df44 419 * @arg @ref LL_HANDLER_FAULT_USG
lypinator 0:bb348c97df44 420 * @arg @ref LL_HANDLER_FAULT_BUS
lypinator 0:bb348c97df44 421 * @arg @ref LL_HANDLER_FAULT_MEM
lypinator 0:bb348c97df44 422 * @retval None
lypinator 0:bb348c97df44 423 */
lypinator 0:bb348c97df44 424 __STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault)
lypinator 0:bb348c97df44 425 {
lypinator 0:bb348c97df44 426 /* Disable the system handler fault */
lypinator 0:bb348c97df44 427 CLEAR_BIT(SCB->SHCSR, Fault);
lypinator 0:bb348c97df44 428 }
lypinator 0:bb348c97df44 429
lypinator 0:bb348c97df44 430 /**
lypinator 0:bb348c97df44 431 * @}
lypinator 0:bb348c97df44 432 */
lypinator 0:bb348c97df44 433
lypinator 0:bb348c97df44 434 /** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO
lypinator 0:bb348c97df44 435 * @{
lypinator 0:bb348c97df44 436 */
lypinator 0:bb348c97df44 437
lypinator 0:bb348c97df44 438 /**
lypinator 0:bb348c97df44 439 * @brief Get Implementer code
lypinator 0:bb348c97df44 440 * @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer
lypinator 0:bb348c97df44 441 * @retval Value should be equal to 0x41 for ARM
lypinator 0:bb348c97df44 442 */
lypinator 0:bb348c97df44 443 __STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void)
lypinator 0:bb348c97df44 444 {
lypinator 0:bb348c97df44 445 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos);
lypinator 0:bb348c97df44 446 }
lypinator 0:bb348c97df44 447
lypinator 0:bb348c97df44 448 /**
lypinator 0:bb348c97df44 449 * @brief Get Variant number (The r value in the rnpn product revision identifier)
lypinator 0:bb348c97df44 450 * @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant
lypinator 0:bb348c97df44 451 * @retval Value between 0 and 255 (0x0: revision 0)
lypinator 0:bb348c97df44 452 */
lypinator 0:bb348c97df44 453 __STATIC_INLINE uint32_t LL_CPUID_GetVariant(void)
lypinator 0:bb348c97df44 454 {
lypinator 0:bb348c97df44 455 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos);
lypinator 0:bb348c97df44 456 }
lypinator 0:bb348c97df44 457
lypinator 0:bb348c97df44 458 /**
lypinator 0:bb348c97df44 459 * @brief Get Constant number
lypinator 0:bb348c97df44 460 * @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetConstant
lypinator 0:bb348c97df44 461 * @retval Value should be equal to 0xF for Cortex-M4 devices
lypinator 0:bb348c97df44 462 */
lypinator 0:bb348c97df44 463 __STATIC_INLINE uint32_t LL_CPUID_GetConstant(void)
lypinator 0:bb348c97df44 464 {
lypinator 0:bb348c97df44 465 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos);
lypinator 0:bb348c97df44 466 }
lypinator 0:bb348c97df44 467
lypinator 0:bb348c97df44 468 /**
lypinator 0:bb348c97df44 469 * @brief Get Part number
lypinator 0:bb348c97df44 470 * @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo
lypinator 0:bb348c97df44 471 * @retval Value should be equal to 0xC24 for Cortex-M4
lypinator 0:bb348c97df44 472 */
lypinator 0:bb348c97df44 473 __STATIC_INLINE uint32_t LL_CPUID_GetParNo(void)
lypinator 0:bb348c97df44 474 {
lypinator 0:bb348c97df44 475 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos);
lypinator 0:bb348c97df44 476 }
lypinator 0:bb348c97df44 477
lypinator 0:bb348c97df44 478 /**
lypinator 0:bb348c97df44 479 * @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)
lypinator 0:bb348c97df44 480 * @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision
lypinator 0:bb348c97df44 481 * @retval Value between 0 and 255 (0x1: patch 1)
lypinator 0:bb348c97df44 482 */
lypinator 0:bb348c97df44 483 __STATIC_INLINE uint32_t LL_CPUID_GetRevision(void)
lypinator 0:bb348c97df44 484 {
lypinator 0:bb348c97df44 485 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos);
lypinator 0:bb348c97df44 486 }
lypinator 0:bb348c97df44 487
lypinator 0:bb348c97df44 488 /**
lypinator 0:bb348c97df44 489 * @}
lypinator 0:bb348c97df44 490 */
lypinator 0:bb348c97df44 491
lypinator 0:bb348c97df44 492 #if __MPU_PRESENT
lypinator 0:bb348c97df44 493 /** @defgroup CORTEX_LL_EF_MPU MPU
lypinator 0:bb348c97df44 494 * @{
lypinator 0:bb348c97df44 495 */
lypinator 0:bb348c97df44 496
lypinator 0:bb348c97df44 497 /**
lypinator 0:bb348c97df44 498 * @brief Enable MPU with input options
lypinator 0:bb348c97df44 499 * @rmtoll MPU_CTRL ENABLE LL_MPU_Enable
lypinator 0:bb348c97df44 500 * @param Options This parameter can be one of the following values:
lypinator 0:bb348c97df44 501 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
lypinator 0:bb348c97df44 502 * @arg @ref LL_MPU_CTRL_HARDFAULT_NMI
lypinator 0:bb348c97df44 503 * @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT
lypinator 0:bb348c97df44 504 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF
lypinator 0:bb348c97df44 505 * @retval None
lypinator 0:bb348c97df44 506 */
lypinator 0:bb348c97df44 507 __STATIC_INLINE void LL_MPU_Enable(uint32_t Options)
lypinator 0:bb348c97df44 508 {
lypinator 0:bb348c97df44 509 /* Enable the MPU*/
lypinator 0:bb348c97df44 510 WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options));
lypinator 0:bb348c97df44 511 /* Ensure MPU settings take effects */
lypinator 0:bb348c97df44 512 __DSB();
lypinator 0:bb348c97df44 513 /* Sequence instruction fetches using update settings */
lypinator 0:bb348c97df44 514 __ISB();
lypinator 0:bb348c97df44 515 }
lypinator 0:bb348c97df44 516
lypinator 0:bb348c97df44 517 /**
lypinator 0:bb348c97df44 518 * @brief Disable MPU
lypinator 0:bb348c97df44 519 * @rmtoll MPU_CTRL ENABLE LL_MPU_Disable
lypinator 0:bb348c97df44 520 * @retval None
lypinator 0:bb348c97df44 521 */
lypinator 0:bb348c97df44 522 __STATIC_INLINE void LL_MPU_Disable(void)
lypinator 0:bb348c97df44 523 {
lypinator 0:bb348c97df44 524 /* Make sure outstanding transfers are done */
lypinator 0:bb348c97df44 525 __DMB();
lypinator 0:bb348c97df44 526 /* Disable MPU*/
lypinator 0:bb348c97df44 527 WRITE_REG(MPU->CTRL, 0U);
lypinator 0:bb348c97df44 528 }
lypinator 0:bb348c97df44 529
lypinator 0:bb348c97df44 530 /**
lypinator 0:bb348c97df44 531 * @brief Check if MPU is enabled or not
lypinator 0:bb348c97df44 532 * @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled
lypinator 0:bb348c97df44 533 * @retval State of bit (1 or 0).
lypinator 0:bb348c97df44 534 */
lypinator 0:bb348c97df44 535 __STATIC_INLINE uint32_t LL_MPU_IsEnabled(void)
lypinator 0:bb348c97df44 536 {
lypinator 0:bb348c97df44 537 return (READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk));
lypinator 0:bb348c97df44 538 }
lypinator 0:bb348c97df44 539
lypinator 0:bb348c97df44 540 /**
lypinator 0:bb348c97df44 541 * @brief Enable a MPU region
lypinator 0:bb348c97df44 542 * @rmtoll MPU_RASR ENABLE LL_MPU_EnableRegion
lypinator 0:bb348c97df44 543 * @param Region This parameter can be one of the following values:
lypinator 0:bb348c97df44 544 * @arg @ref LL_MPU_REGION_NUMBER0
lypinator 0:bb348c97df44 545 * @arg @ref LL_MPU_REGION_NUMBER1
lypinator 0:bb348c97df44 546 * @arg @ref LL_MPU_REGION_NUMBER2
lypinator 0:bb348c97df44 547 * @arg @ref LL_MPU_REGION_NUMBER3
lypinator 0:bb348c97df44 548 * @arg @ref LL_MPU_REGION_NUMBER4
lypinator 0:bb348c97df44 549 * @arg @ref LL_MPU_REGION_NUMBER5
lypinator 0:bb348c97df44 550 * @arg @ref LL_MPU_REGION_NUMBER6
lypinator 0:bb348c97df44 551 * @arg @ref LL_MPU_REGION_NUMBER7
lypinator 0:bb348c97df44 552 * @retval None
lypinator 0:bb348c97df44 553 */
lypinator 0:bb348c97df44 554 __STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region)
lypinator 0:bb348c97df44 555 {
lypinator 0:bb348c97df44 556 /* Set Region number */
lypinator 0:bb348c97df44 557 WRITE_REG(MPU->RNR, Region);
lypinator 0:bb348c97df44 558 /* Enable the MPU region */
lypinator 0:bb348c97df44 559 SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
lypinator 0:bb348c97df44 560 }
lypinator 0:bb348c97df44 561
lypinator 0:bb348c97df44 562 /**
lypinator 0:bb348c97df44 563 * @brief Configure and enable a region
lypinator 0:bb348c97df44 564 * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion\n
lypinator 0:bb348c97df44 565 * MPU_RBAR REGION LL_MPU_ConfigRegion\n
lypinator 0:bb348c97df44 566 * MPU_RBAR ADDR LL_MPU_ConfigRegion\n
lypinator 0:bb348c97df44 567 * MPU_RASR XN LL_MPU_ConfigRegion\n
lypinator 0:bb348c97df44 568 * MPU_RASR AP LL_MPU_ConfigRegion\n
lypinator 0:bb348c97df44 569 * MPU_RASR S LL_MPU_ConfigRegion\n
lypinator 0:bb348c97df44 570 * MPU_RASR C LL_MPU_ConfigRegion\n
lypinator 0:bb348c97df44 571 * MPU_RASR B LL_MPU_ConfigRegion\n
lypinator 0:bb348c97df44 572 * MPU_RASR SIZE LL_MPU_ConfigRegion
lypinator 0:bb348c97df44 573 * @param Region This parameter can be one of the following values:
lypinator 0:bb348c97df44 574 * @arg @ref LL_MPU_REGION_NUMBER0
lypinator 0:bb348c97df44 575 * @arg @ref LL_MPU_REGION_NUMBER1
lypinator 0:bb348c97df44 576 * @arg @ref LL_MPU_REGION_NUMBER2
lypinator 0:bb348c97df44 577 * @arg @ref LL_MPU_REGION_NUMBER3
lypinator 0:bb348c97df44 578 * @arg @ref LL_MPU_REGION_NUMBER4
lypinator 0:bb348c97df44 579 * @arg @ref LL_MPU_REGION_NUMBER5
lypinator 0:bb348c97df44 580 * @arg @ref LL_MPU_REGION_NUMBER6
lypinator 0:bb348c97df44 581 * @arg @ref LL_MPU_REGION_NUMBER7
lypinator 0:bb348c97df44 582 * @param Address Value of region base address
lypinator 0:bb348c97df44 583 * @param SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF
lypinator 0:bb348c97df44 584 * @param Attributes This parameter can be a combination of the following values:
lypinator 0:bb348c97df44 585 * @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or @ref LL_MPU_REGION_SIZE_128B or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B
lypinator 0:bb348c97df44 586 * or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB
lypinator 0:bb348c97df44 587 * or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB
lypinator 0:bb348c97df44 588 * or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB
lypinator 0:bb348c97df44 589 * or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB
lypinator 0:bb348c97df44 590 * or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB
lypinator 0:bb348c97df44 591 * @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS
lypinator 0:bb348c97df44 592 * or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO
lypinator 0:bb348c97df44 593 * @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4
lypinator 0:bb348c97df44 594 * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
lypinator 0:bb348c97df44 595 * @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE
lypinator 0:bb348c97df44 596 * @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE
lypinator 0:bb348c97df44 597 * @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE
lypinator 0:bb348c97df44 598 * @retval None
lypinator 0:bb348c97df44 599 */
lypinator 0:bb348c97df44 600 __STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes)
lypinator 0:bb348c97df44 601 {
lypinator 0:bb348c97df44 602 /* Set Region number */
lypinator 0:bb348c97df44 603 WRITE_REG(MPU->RNR, Region);
lypinator 0:bb348c97df44 604 /* Set base address */
lypinator 0:bb348c97df44 605 WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U));
lypinator 0:bb348c97df44 606 /* Configure MPU */
lypinator 0:bb348c97df44 607 WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | SubRegionDisable << MPU_RASR_SRD_Pos));
lypinator 0:bb348c97df44 608 }
lypinator 0:bb348c97df44 609
lypinator 0:bb348c97df44 610 /**
lypinator 0:bb348c97df44 611 * @brief Disable a region
lypinator 0:bb348c97df44 612 * @rmtoll MPU_RNR REGION LL_MPU_DisableRegion\n
lypinator 0:bb348c97df44 613 * MPU_RASR ENABLE LL_MPU_DisableRegion
lypinator 0:bb348c97df44 614 * @param Region This parameter can be one of the following values:
lypinator 0:bb348c97df44 615 * @arg @ref LL_MPU_REGION_NUMBER0
lypinator 0:bb348c97df44 616 * @arg @ref LL_MPU_REGION_NUMBER1
lypinator 0:bb348c97df44 617 * @arg @ref LL_MPU_REGION_NUMBER2
lypinator 0:bb348c97df44 618 * @arg @ref LL_MPU_REGION_NUMBER3
lypinator 0:bb348c97df44 619 * @arg @ref LL_MPU_REGION_NUMBER4
lypinator 0:bb348c97df44 620 * @arg @ref LL_MPU_REGION_NUMBER5
lypinator 0:bb348c97df44 621 * @arg @ref LL_MPU_REGION_NUMBER6
lypinator 0:bb348c97df44 622 * @arg @ref LL_MPU_REGION_NUMBER7
lypinator 0:bb348c97df44 623 * @retval None
lypinator 0:bb348c97df44 624 */
lypinator 0:bb348c97df44 625 __STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region)
lypinator 0:bb348c97df44 626 {
lypinator 0:bb348c97df44 627 /* Set Region number */
lypinator 0:bb348c97df44 628 WRITE_REG(MPU->RNR, Region);
lypinator 0:bb348c97df44 629 /* Disable the MPU region */
lypinator 0:bb348c97df44 630 CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
lypinator 0:bb348c97df44 631 }
lypinator 0:bb348c97df44 632
lypinator 0:bb348c97df44 633 /**
lypinator 0:bb348c97df44 634 * @}
lypinator 0:bb348c97df44 635 */
lypinator 0:bb348c97df44 636
lypinator 0:bb348c97df44 637 #endif /* __MPU_PRESENT */
lypinator 0:bb348c97df44 638 /**
lypinator 0:bb348c97df44 639 * @}
lypinator 0:bb348c97df44 640 */
lypinator 0:bb348c97df44 641
lypinator 0:bb348c97df44 642 /**
lypinator 0:bb348c97df44 643 * @}
lypinator 0:bb348c97df44 644 */
lypinator 0:bb348c97df44 645
lypinator 0:bb348c97df44 646 /**
lypinator 0:bb348c97df44 647 * @}
lypinator 0:bb348c97df44 648 */
lypinator 0:bb348c97df44 649
lypinator 0:bb348c97df44 650 #ifdef __cplusplus
lypinator 0:bb348c97df44 651 }
lypinator 0:bb348c97df44 652 #endif
lypinator 0:bb348c97df44 653
lypinator 0:bb348c97df44 654 #endif /* __STM32F4xx_LL_CORTEX_H */
lypinator 0:bb348c97df44 655
lypinator 0:bb348c97df44 656 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/