Thomas Lyp / DevLibMemoryController

Initial commit

Dependencies:   FastPWM

mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_tim.h@0:bb348c97df44, 2020-09-16 (annotated)

Committer:
lypinator
Date:
Wed Sep 16 01:11:49 2020 +0000
Revision:
0:bb348c97df44
Added PWM

Who changed what in which revision?

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lypinator 0:bb348c97df44 1 /**
lypinator 0:bb348c97df44 2 ******************************************************************************
lypinator 0:bb348c97df44 3 * @file stm32f4xx_hal_tim.h
lypinator 0:bb348c97df44 4 * @author MCD Application Team
lypinator 0:bb348c97df44 5 * @brief Header file of TIM HAL module.
lypinator 0:bb348c97df44 6 ******************************************************************************
lypinator 0:bb348c97df44 7 * @attention
lypinator 0:bb348c97df44 8 *
lypinator 0:bb348c97df44 9 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
lypinator 0:bb348c97df44 10 *
lypinator 0:bb348c97df44 11 * Redistribution and use in source and binary forms, with or without modification,
lypinator 0:bb348c97df44 12 * are permitted provided that the following conditions are met:
lypinator 0:bb348c97df44 13 * 1. Redistributions of source code must retain the above copyright notice,
lypinator 0:bb348c97df44 14 * this list of conditions and the following disclaimer.
lypinator 0:bb348c97df44 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
lypinator 0:bb348c97df44 16 * this list of conditions and the following disclaimer in the documentation
lypinator 0:bb348c97df44 17 * and/or other materials provided with the distribution.
lypinator 0:bb348c97df44 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
lypinator 0:bb348c97df44 19 * may be used to endorse or promote products derived from this software
lypinator 0:bb348c97df44 20 * without specific prior written permission.
lypinator 0:bb348c97df44 21 *
lypinator 0:bb348c97df44 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
lypinator 0:bb348c97df44 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
lypinator 0:bb348c97df44 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
lypinator 0:bb348c97df44 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
lypinator 0:bb348c97df44 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
lypinator 0:bb348c97df44 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
lypinator 0:bb348c97df44 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
lypinator 0:bb348c97df44 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
lypinator 0:bb348c97df44 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
lypinator 0:bb348c97df44 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
lypinator 0:bb348c97df44 32 *
lypinator 0:bb348c97df44 33 ******************************************************************************
lypinator 0:bb348c97df44 34 */
lypinator 0:bb348c97df44 35
lypinator 0:bb348c97df44 36 /* Define to prevent recursive inclusion -------------------------------------*/
lypinator 0:bb348c97df44 37 #ifndef __STM32F4xx_HAL_TIM_H
lypinator 0:bb348c97df44 38 #define __STM32F4xx_HAL_TIM_H
lypinator 0:bb348c97df44 39
lypinator 0:bb348c97df44 40 #ifdef __cplusplus
lypinator 0:bb348c97df44 41 extern "C" {
lypinator 0:bb348c97df44 42 #endif
lypinator 0:bb348c97df44 43
lypinator 0:bb348c97df44 44 /* Includes ------------------------------------------------------------------*/
lypinator 0:bb348c97df44 45 #include "stm32f4xx_hal_def.h"
lypinator 0:bb348c97df44 46
lypinator 0:bb348c97df44 47 /** @addtogroup STM32F4xx_HAL_Driver
lypinator 0:bb348c97df44 48 * @{
lypinator 0:bb348c97df44 49 */
lypinator 0:bb348c97df44 50
lypinator 0:bb348c97df44 51 /** @addtogroup TIM
lypinator 0:bb348c97df44 52 * @{
lypinator 0:bb348c97df44 53 */
lypinator 0:bb348c97df44 54
lypinator 0:bb348c97df44 55 /* Exported types ------------------------------------------------------------*/
lypinator 0:bb348c97df44 56 /** @defgroup TIM_Exported_Types TIM Exported Types
lypinator 0:bb348c97df44 57 * @{
lypinator 0:bb348c97df44 58 */
lypinator 0:bb348c97df44 59
lypinator 0:bb348c97df44 60 /**
lypinator 0:bb348c97df44 61 * @brief TIM Time base Configuration Structure definition
lypinator 0:bb348c97df44 62 */
lypinator 0:bb348c97df44 63 typedef struct
lypinator 0:bb348c97df44 64 {
lypinator 0:bb348c97df44 65 uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
lypinator 0:bb348c97df44 66 This parameter can be a number between Min_Data = 0x0000U and Max_Data = 0xFFFFU */
lypinator 0:bb348c97df44 67
lypinator 0:bb348c97df44 68 uint32_t CounterMode; /*!< Specifies the counter mode.
lypinator 0:bb348c97df44 69 This parameter can be a value of @ref TIM_Counter_Mode */
lypinator 0:bb348c97df44 70
lypinator 0:bb348c97df44 71 uint32_t Period; /*!< Specifies the period value to be loaded into the active
lypinator 0:bb348c97df44 72 Auto-Reload Register at the next update event.
lypinator 0:bb348c97df44 73 This parameter can be a number between Min_Data = 0x0000U and Max_Data = 0xFFFF. */
lypinator 0:bb348c97df44 74
lypinator 0:bb348c97df44 75 uint32_t ClockDivision; /*!< Specifies the clock division.
lypinator 0:bb348c97df44 76 This parameter can be a value of @ref TIM_ClockDivision */
lypinator 0:bb348c97df44 77
lypinator 0:bb348c97df44 78 uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
lypinator 0:bb348c97df44 79 reaches zero, an update event is generated and counting restarts
lypinator 0:bb348c97df44 80 from the RCR value (N).
lypinator 0:bb348c97df44 81 This means in PWM mode that (N+1) corresponds to:
lypinator 0:bb348c97df44 82 - the number of PWM periods in edge-aligned mode
lypinator 0:bb348c97df44 83 - the number of half PWM period in center-aligned mode
lypinator 0:bb348c97df44 84 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
lypinator 0:bb348c97df44 85 @note This parameter is valid only for TIM1 and TIM8. */
lypinator 0:bb348c97df44 86 } TIM_Base_InitTypeDef;
lypinator 0:bb348c97df44 87
lypinator 0:bb348c97df44 88 /**
lypinator 0:bb348c97df44 89 * @brief TIM Output Compare Configuration Structure definition
lypinator 0:bb348c97df44 90 */
lypinator 0:bb348c97df44 91
lypinator 0:bb348c97df44 92 typedef struct
lypinator 0:bb348c97df44 93 {
lypinator 0:bb348c97df44 94 uint32_t OCMode; /*!< Specifies the TIM mode.
lypinator 0:bb348c97df44 95 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
lypinator 0:bb348c97df44 96
lypinator 0:bb348c97df44 97 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
lypinator 0:bb348c97df44 98 This parameter can be a number between Min_Data = 0x0000U and Max_Data = 0xFFFFU */
lypinator 0:bb348c97df44 99
lypinator 0:bb348c97df44 100 uint32_t OCPolarity; /*!< Specifies the output polarity.
lypinator 0:bb348c97df44 101 This parameter can be a value of @ref TIM_Output_Compare_Polarity */
lypinator 0:bb348c97df44 102
lypinator 0:bb348c97df44 103 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
lypinator 0:bb348c97df44 104 This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
lypinator 0:bb348c97df44 105 @note This parameter is valid only for TIM1 and TIM8. */
lypinator 0:bb348c97df44 106
lypinator 0:bb348c97df44 107 uint32_t OCFastMode; /*!< Specifies the Fast mode state.
lypinator 0:bb348c97df44 108 This parameter can be a value of @ref TIM_Output_Fast_State
lypinator 0:bb348c97df44 109 @note This parameter is valid only in PWM1 and PWM2 mode. */
lypinator 0:bb348c97df44 110
lypinator 0:bb348c97df44 111
lypinator 0:bb348c97df44 112 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
lypinator 0:bb348c97df44 113 This parameter can be a value of @ref TIM_Output_Compare_Idle_State
lypinator 0:bb348c97df44 114 @note This parameter is valid only for TIM1 and TIM8. */
lypinator 0:bb348c97df44 115
lypinator 0:bb348c97df44 116 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
lypinator 0:bb348c97df44 117 This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
lypinator 0:bb348c97df44 118 @note This parameter is valid only for TIM1 and TIM8. */
lypinator 0:bb348c97df44 119 } TIM_OC_InitTypeDef;
lypinator 0:bb348c97df44 120
lypinator 0:bb348c97df44 121 /**
lypinator 0:bb348c97df44 122 * @brief TIM One Pulse Mode Configuration Structure definition
lypinator 0:bb348c97df44 123 */
lypinator 0:bb348c97df44 124 typedef struct
lypinator 0:bb348c97df44 125 {
lypinator 0:bb348c97df44 126 uint32_t OCMode; /*!< Specifies the TIM mode.
lypinator 0:bb348c97df44 127 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
lypinator 0:bb348c97df44 128
lypinator 0:bb348c97df44 129 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
lypinator 0:bb348c97df44 130 This parameter can be a number between Min_Data = 0x0000U and Max_Data = 0xFFFFU */
lypinator 0:bb348c97df44 131
lypinator 0:bb348c97df44 132 uint32_t OCPolarity; /*!< Specifies the output polarity.
lypinator 0:bb348c97df44 133 This parameter can be a value of @ref TIM_Output_Compare_Polarity */
lypinator 0:bb348c97df44 134
lypinator 0:bb348c97df44 135 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
lypinator 0:bb348c97df44 136 This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
lypinator 0:bb348c97df44 137 @note This parameter is valid only for TIM1 and TIM8. */
lypinator 0:bb348c97df44 138
lypinator 0:bb348c97df44 139 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
lypinator 0:bb348c97df44 140 This parameter can be a value of @ref TIM_Output_Compare_Idle_State
lypinator 0:bb348c97df44 141 @note This parameter is valid only for TIM1 and TIM8. */
lypinator 0:bb348c97df44 142
lypinator 0:bb348c97df44 143 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
lypinator 0:bb348c97df44 144 This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
lypinator 0:bb348c97df44 145 @note This parameter is valid only for TIM1 and TIM8. */
lypinator 0:bb348c97df44 146
lypinator 0:bb348c97df44 147 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
lypinator 0:bb348c97df44 148 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
lypinator 0:bb348c97df44 149
lypinator 0:bb348c97df44 150 uint32_t ICSelection; /*!< Specifies the input.
lypinator 0:bb348c97df44 151 This parameter can be a value of @ref TIM_Input_Capture_Selection */
lypinator 0:bb348c97df44 152
lypinator 0:bb348c97df44 153 uint32_t ICFilter; /*!< Specifies the input capture filter.
lypinator 0:bb348c97df44 154 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
lypinator 0:bb348c97df44 155 } TIM_OnePulse_InitTypeDef;
lypinator 0:bb348c97df44 156
lypinator 0:bb348c97df44 157
lypinator 0:bb348c97df44 158 /**
lypinator 0:bb348c97df44 159 * @brief TIM Input Capture Configuration Structure definition
lypinator 0:bb348c97df44 160 */
lypinator 0:bb348c97df44 161
lypinator 0:bb348c97df44 162 typedef struct
lypinator 0:bb348c97df44 163 {
lypinator 0:bb348c97df44 164 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
lypinator 0:bb348c97df44 165 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
lypinator 0:bb348c97df44 166
lypinator 0:bb348c97df44 167 uint32_t ICSelection; /*!< Specifies the input.
lypinator 0:bb348c97df44 168 This parameter can be a value of @ref TIM_Input_Capture_Selection */
lypinator 0:bb348c97df44 169
lypinator 0:bb348c97df44 170 uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
lypinator 0:bb348c97df44 171 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
lypinator 0:bb348c97df44 172
lypinator 0:bb348c97df44 173 uint32_t ICFilter; /*!< Specifies the input capture filter.
lypinator 0:bb348c97df44 174 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
lypinator 0:bb348c97df44 175 } TIM_IC_InitTypeDef;
lypinator 0:bb348c97df44 176
lypinator 0:bb348c97df44 177 /**
lypinator 0:bb348c97df44 178 * @brief TIM Encoder Configuration Structure definition
lypinator 0:bb348c97df44 179 */
lypinator 0:bb348c97df44 180
lypinator 0:bb348c97df44 181 typedef struct
lypinator 0:bb348c97df44 182 {
lypinator 0:bb348c97df44 183 uint32_t EncoderMode; /*!< Specifies the active edge of the input signal.
lypinator 0:bb348c97df44 184 This parameter can be a value of @ref TIM_Encoder_Mode */
lypinator 0:bb348c97df44 185
lypinator 0:bb348c97df44 186 uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
lypinator 0:bb348c97df44 187 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
lypinator 0:bb348c97df44 188
lypinator 0:bb348c97df44 189 uint32_t IC1Selection; /*!< Specifies the input.
lypinator 0:bb348c97df44 190 This parameter can be a value of @ref TIM_Input_Capture_Selection */
lypinator 0:bb348c97df44 191
lypinator 0:bb348c97df44 192 uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
lypinator 0:bb348c97df44 193 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
lypinator 0:bb348c97df44 194
lypinator 0:bb348c97df44 195 uint32_t IC1Filter; /*!< Specifies the input capture filter.
lypinator 0:bb348c97df44 196 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
lypinator 0:bb348c97df44 197
lypinator 0:bb348c97df44 198 uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
lypinator 0:bb348c97df44 199 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
lypinator 0:bb348c97df44 200
lypinator 0:bb348c97df44 201 uint32_t IC2Selection; /*!< Specifies the input.
lypinator 0:bb348c97df44 202 This parameter can be a value of @ref TIM_Input_Capture_Selection */
lypinator 0:bb348c97df44 203
lypinator 0:bb348c97df44 204 uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler.
lypinator 0:bb348c97df44 205 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
lypinator 0:bb348c97df44 206
lypinator 0:bb348c97df44 207 uint32_t IC2Filter; /*!< Specifies the input capture filter.
lypinator 0:bb348c97df44 208 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
lypinator 0:bb348c97df44 209 } TIM_Encoder_InitTypeDef;
lypinator 0:bb348c97df44 210
lypinator 0:bb348c97df44 211 /**
lypinator 0:bb348c97df44 212 * @brief Clock Configuration Handle Structure definition
lypinator 0:bb348c97df44 213 */
lypinator 0:bb348c97df44 214 typedef struct
lypinator 0:bb348c97df44 215 {
lypinator 0:bb348c97df44 216 uint32_t ClockSource; /*!< TIM clock sources.
lypinator 0:bb348c97df44 217 This parameter can be a value of @ref TIM_Clock_Source */
lypinator 0:bb348c97df44 218 uint32_t ClockPolarity; /*!< TIM clock polarity.
lypinator 0:bb348c97df44 219 This parameter can be a value of @ref TIM_Clock_Polarity */
lypinator 0:bb348c97df44 220 uint32_t ClockPrescaler; /*!< TIM clock prescaler.
lypinator 0:bb348c97df44 221 This parameter can be a value of @ref TIM_Clock_Prescaler */
lypinator 0:bb348c97df44 222 uint32_t ClockFilter; /*!< TIM clock filter.
lypinator 0:bb348c97df44 223 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
lypinator 0:bb348c97df44 224 }TIM_ClockConfigTypeDef;
lypinator 0:bb348c97df44 225
lypinator 0:bb348c97df44 226 /**
lypinator 0:bb348c97df44 227 * @brief Clear Input Configuration Handle Structure definition
lypinator 0:bb348c97df44 228 */
lypinator 0:bb348c97df44 229 typedef struct
lypinator 0:bb348c97df44 230 {
lypinator 0:bb348c97df44 231 uint32_t ClearInputState; /*!< TIM clear Input state.
lypinator 0:bb348c97df44 232 This parameter can be ENABLE or DISABLE */
lypinator 0:bb348c97df44 233 uint32_t ClearInputSource; /*!< TIM clear Input sources.
lypinator 0:bb348c97df44 234 This parameter can be a value of @ref TIM_ClearInput_Source */
lypinator 0:bb348c97df44 235 uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity.
lypinator 0:bb348c97df44 236 This parameter can be a value of @ref TIM_ClearInput_Polarity */
lypinator 0:bb348c97df44 237 uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler.
lypinator 0:bb348c97df44 238 This parameter can be a value of @ref TIM_ClearInput_Prescaler */
lypinator 0:bb348c97df44 239 uint32_t ClearInputFilter; /*!< TIM Clear Input filter.
lypinator 0:bb348c97df44 240 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
lypinator 0:bb348c97df44 241 }TIM_ClearInputConfigTypeDef;
lypinator 0:bb348c97df44 242
lypinator 0:bb348c97df44 243 /**
lypinator 0:bb348c97df44 244 * @brief TIM Slave configuration Structure definition
lypinator 0:bb348c97df44 245 */
lypinator 0:bb348c97df44 246 typedef struct {
lypinator 0:bb348c97df44 247 uint32_t SlaveMode; /*!< Slave mode selection
lypinator 0:bb348c97df44 248 This parameter can be a value of @ref TIM_Slave_Mode */
lypinator 0:bb348c97df44 249 uint32_t InputTrigger; /*!< Input Trigger source
lypinator 0:bb348c97df44 250 This parameter can be a value of @ref TIM_Trigger_Selection */
lypinator 0:bb348c97df44 251 uint32_t TriggerPolarity; /*!< Input Trigger polarity
lypinator 0:bb348c97df44 252 This parameter can be a value of @ref TIM_Trigger_Polarity */
lypinator 0:bb348c97df44 253 uint32_t TriggerPrescaler; /*!< Input trigger prescaler
lypinator 0:bb348c97df44 254 This parameter can be a value of @ref TIM_Trigger_Prescaler */
lypinator 0:bb348c97df44 255 uint32_t TriggerFilter; /*!< Input trigger filter
lypinator 0:bb348c97df44 256 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
lypinator 0:bb348c97df44 257
lypinator 0:bb348c97df44 258 }TIM_SlaveConfigTypeDef;
lypinator 0:bb348c97df44 259
lypinator 0:bb348c97df44 260 /**
lypinator 0:bb348c97df44 261 * @brief HAL State structures definition
lypinator 0:bb348c97df44 262 */
lypinator 0:bb348c97df44 263 typedef enum
lypinator 0:bb348c97df44 264 {
lypinator 0:bb348c97df44 265 HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */
lypinator 0:bb348c97df44 266 HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
lypinator 0:bb348c97df44 267 HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */
lypinator 0:bb348c97df44 268 HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
lypinator 0:bb348c97df44 269 HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */
lypinator 0:bb348c97df44 270 }HAL_TIM_StateTypeDef;
lypinator 0:bb348c97df44 271
lypinator 0:bb348c97df44 272 /**
lypinator 0:bb348c97df44 273 * @brief HAL Active channel structures definition
lypinator 0:bb348c97df44 274 */
lypinator 0:bb348c97df44 275 typedef enum
lypinator 0:bb348c97df44 276 {
lypinator 0:bb348c97df44 277 HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */
lypinator 0:bb348c97df44 278 HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */
lypinator 0:bb348c97df44 279 HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */
lypinator 0:bb348c97df44 280 HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */
lypinator 0:bb348c97df44 281 HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */
lypinator 0:bb348c97df44 282 }HAL_TIM_ActiveChannel;
lypinator 0:bb348c97df44 283
lypinator 0:bb348c97df44 284 /**
lypinator 0:bb348c97df44 285 * @brief TIM Time Base Handle Structure definition
lypinator 0:bb348c97df44 286 */
lypinator 0:bb348c97df44 287 typedef struct
lypinator 0:bb348c97df44 288 {
lypinator 0:bb348c97df44 289 TIM_TypeDef *Instance; /*!< Register base address */
lypinator 0:bb348c97df44 290 TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */
lypinator 0:bb348c97df44 291 HAL_TIM_ActiveChannel Channel; /*!< Active channel */
lypinator 0:bb348c97df44 292 DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array
lypinator 0:bb348c97df44 293 This array is accessed by a @ref DMA_Handle_index */
lypinator 0:bb348c97df44 294 HAL_LockTypeDef Lock; /*!< Locking object */
lypinator 0:bb348c97df44 295 __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */
lypinator 0:bb348c97df44 296 }TIM_HandleTypeDef;
lypinator 0:bb348c97df44 297 /**
lypinator 0:bb348c97df44 298 * @}
lypinator 0:bb348c97df44 299 */
lypinator 0:bb348c97df44 300
lypinator 0:bb348c97df44 301 /* Exported constants --------------------------------------------------------*/
lypinator 0:bb348c97df44 302 /** @defgroup TIM_Exported_Constants TIM Exported Constants
lypinator 0:bb348c97df44 303 * @{
lypinator 0:bb348c97df44 304 */
lypinator 0:bb348c97df44 305
lypinator 0:bb348c97df44 306 /** @defgroup TIM_Input_Channel_Polarity TIM Input Channel Polarity
lypinator 0:bb348c97df44 307 * @{
lypinator 0:bb348c97df44 308 */
lypinator 0:bb348c97df44 309 #define TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U /*!< Polarity for TIx source */
lypinator 0:bb348c97df44 310 #define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /*!< Polarity for TIx source */
lypinator 0:bb348c97df44 311 #define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */
lypinator 0:bb348c97df44 312 /**
lypinator 0:bb348c97df44 313 * @}
lypinator 0:bb348c97df44 314 */
lypinator 0:bb348c97df44 315
lypinator 0:bb348c97df44 316 /** @defgroup TIM_ETR_Polarity TIM ETR Polarity
lypinator 0:bb348c97df44 317 * @{
lypinator 0:bb348c97df44 318 */
lypinator 0:bb348c97df44 319 #define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /*!< Polarity for ETR source */
lypinator 0:bb348c97df44 320 #define TIM_ETRPOLARITY_NONINVERTED 0x00000000U /*!< Polarity for ETR source */
lypinator 0:bb348c97df44 321 /**
lypinator 0:bb348c97df44 322 * @}
lypinator 0:bb348c97df44 323 */
lypinator 0:bb348c97df44 324
lypinator 0:bb348c97df44 325 /** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
lypinator 0:bb348c97df44 326 * @{
lypinator 0:bb348c97df44 327 */
lypinator 0:bb348c97df44 328 #define TIM_ETRPRESCALER_DIV1 0x00000000U /*!< No prescaler is used */
lypinator 0:bb348c97df44 329 #define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /*!< ETR input source is divided by 2 */
lypinator 0:bb348c97df44 330 #define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /*!< ETR input source is divided by 4 */
lypinator 0:bb348c97df44 331 #define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /*!< ETR input source is divided by 8 */
lypinator 0:bb348c97df44 332 /**
lypinator 0:bb348c97df44 333 * @}
lypinator 0:bb348c97df44 334 */
lypinator 0:bb348c97df44 335
lypinator 0:bb348c97df44 336 /** @defgroup TIM_Counter_Mode TIM Counter Mode
lypinator 0:bb348c97df44 337 * @{
lypinator 0:bb348c97df44 338 */
lypinator 0:bb348c97df44 339 #define TIM_COUNTERMODE_UP 0x00000000U
lypinator 0:bb348c97df44 340 #define TIM_COUNTERMODE_DOWN TIM_CR1_DIR
lypinator 0:bb348c97df44 341 #define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0
lypinator 0:bb348c97df44 342 #define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1
lypinator 0:bb348c97df44 343 #define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS
lypinator 0:bb348c97df44 344 /**
lypinator 0:bb348c97df44 345 * @}
lypinator 0:bb348c97df44 346 */
lypinator 0:bb348c97df44 347
lypinator 0:bb348c97df44 348 /** @defgroup TIM_ClockDivision TIM Clock Division
lypinator 0:bb348c97df44 349 * @{
lypinator 0:bb348c97df44 350 */
lypinator 0:bb348c97df44 351 #define TIM_CLOCKDIVISION_DIV1 0x00000000U
lypinator 0:bb348c97df44 352 #define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0)
lypinator 0:bb348c97df44 353 #define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1)
lypinator 0:bb348c97df44 354 /**
lypinator 0:bb348c97df44 355 * @}
lypinator 0:bb348c97df44 356 */
lypinator 0:bb348c97df44 357
lypinator 0:bb348c97df44 358 /** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM modes
lypinator 0:bb348c97df44 359 * @{
lypinator 0:bb348c97df44 360 */
lypinator 0:bb348c97df44 361 #define TIM_OCMODE_TIMING 0x00000000U
lypinator 0:bb348c97df44 362 #define TIM_OCMODE_ACTIVE (TIM_CCMR1_OC1M_0)
lypinator 0:bb348c97df44 363 #define TIM_OCMODE_INACTIVE (TIM_CCMR1_OC1M_1)
lypinator 0:bb348c97df44 364 #define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_1)
lypinator 0:bb348c97df44 365 #define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)
lypinator 0:bb348c97df44 366 #define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M)
lypinator 0:bb348c97df44 367 #define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)
lypinator 0:bb348c97df44 368 #define TIM_OCMODE_FORCED_INACTIVE (TIM_CCMR1_OC1M_2)
lypinator 0:bb348c97df44 369
lypinator 0:bb348c97df44 370 /**
lypinator 0:bb348c97df44 371 * @}
lypinator 0:bb348c97df44 372 */
lypinator 0:bb348c97df44 373
lypinator 0:bb348c97df44 374 /** @defgroup TIM_Output_Fast_State TIM Output Fast State
lypinator 0:bb348c97df44 375 * @{
lypinator 0:bb348c97df44 376 */
lypinator 0:bb348c97df44 377 #define TIM_OCFAST_DISABLE 0x00000000U
lypinator 0:bb348c97df44 378 #define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE)
lypinator 0:bb348c97df44 379 /**
lypinator 0:bb348c97df44 380 * @}
lypinator 0:bb348c97df44 381 */
lypinator 0:bb348c97df44 382
lypinator 0:bb348c97df44 383 /** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
lypinator 0:bb348c97df44 384 * @{
lypinator 0:bb348c97df44 385 */
lypinator 0:bb348c97df44 386 #define TIM_OCPOLARITY_HIGH 0x00000000U
lypinator 0:bb348c97df44 387 #define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P)
lypinator 0:bb348c97df44 388 /**
lypinator 0:bb348c97df44 389 * @}
lypinator 0:bb348c97df44 390 */
lypinator 0:bb348c97df44 391
lypinator 0:bb348c97df44 392 /** @defgroup TIM_Output_Compare_N_Polarity TIM Output CompareN Polarity
lypinator 0:bb348c97df44 393 * @{
lypinator 0:bb348c97df44 394 */
lypinator 0:bb348c97df44 395 #define TIM_OCNPOLARITY_HIGH 0x00000000U
lypinator 0:bb348c97df44 396 #define TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP)
lypinator 0:bb348c97df44 397 /**
lypinator 0:bb348c97df44 398 * @}
lypinator 0:bb348c97df44 399 */
lypinator 0:bb348c97df44 400
lypinator 0:bb348c97df44 401 /** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State
lypinator 0:bb348c97df44 402 * @{
lypinator 0:bb348c97df44 403 */
lypinator 0:bb348c97df44 404 #define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1)
lypinator 0:bb348c97df44 405 #define TIM_OCIDLESTATE_RESET 0x00000000U
lypinator 0:bb348c97df44 406 /**
lypinator 0:bb348c97df44 407 * @}
lypinator 0:bb348c97df44 408 */
lypinator 0:bb348c97df44 409
lypinator 0:bb348c97df44 410 /** @defgroup TIM_Output_Compare_N_Idle_State TIM Output Compare N Idle State
lypinator 0:bb348c97df44 411 * @{
lypinator 0:bb348c97df44 412 */
lypinator 0:bb348c97df44 413 #define TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N)
lypinator 0:bb348c97df44 414 #define TIM_OCNIDLESTATE_RESET 0x00000000U
lypinator 0:bb348c97df44 415 /**
lypinator 0:bb348c97df44 416 * @}
lypinator 0:bb348c97df44 417 */
lypinator 0:bb348c97df44 418
lypinator 0:bb348c97df44 419 /** @defgroup TIM_Channel TIM Channel
lypinator 0:bb348c97df44 420 * @{
lypinator 0:bb348c97df44 421 */
lypinator 0:bb348c97df44 422 #define TIM_CHANNEL_1 0x00000000U
lypinator 0:bb348c97df44 423 #define TIM_CHANNEL_2 0x00000004U
lypinator 0:bb348c97df44 424 #define TIM_CHANNEL_3 0x00000008U
lypinator 0:bb348c97df44 425 #define TIM_CHANNEL_4 0x0000000CU
lypinator 0:bb348c97df44 426 #define TIM_CHANNEL_ALL 0x00000018U
lypinator 0:bb348c97df44 427
lypinator 0:bb348c97df44 428 /**
lypinator 0:bb348c97df44 429 * @}
lypinator 0:bb348c97df44 430 */
lypinator 0:bb348c97df44 431
lypinator 0:bb348c97df44 432 /** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
lypinator 0:bb348c97df44 433 * @{
lypinator 0:bb348c97df44 434 */
lypinator 0:bb348c97df44 435 #define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
lypinator 0:bb348c97df44 436 #define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
lypinator 0:bb348c97df44 437 #define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
lypinator 0:bb348c97df44 438 /**
lypinator 0:bb348c97df44 439 * @}
lypinator 0:bb348c97df44 440 */
lypinator 0:bb348c97df44 441
lypinator 0:bb348c97df44 442 /** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
lypinator 0:bb348c97df44 443 * @{
lypinator 0:bb348c97df44 444 */
lypinator 0:bb348c97df44 445 #define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be
lypinator 0:bb348c97df44 446 connected to IC1, IC2, IC3 or IC4, respectively */
lypinator 0:bb348c97df44 447 #define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be
lypinator 0:bb348c97df44 448 connected to IC2, IC1, IC4 or IC3, respectively */
lypinator 0:bb348c97df44 449 #define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */
lypinator 0:bb348c97df44 450
lypinator 0:bb348c97df44 451 /**
lypinator 0:bb348c97df44 452 * @}
lypinator 0:bb348c97df44 453 */
lypinator 0:bb348c97df44 454
lypinator 0:bb348c97df44 455 /** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
lypinator 0:bb348c97df44 456 * @{
lypinator 0:bb348c97df44 457 */
lypinator 0:bb348c97df44 458 #define TIM_ICPSC_DIV1 0x00000000U /*!< Capture performed each time an edge is detected on the capture input */
lypinator 0:bb348c97df44 459 #define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /*!< Capture performed once every 2 events */
lypinator 0:bb348c97df44 460 #define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /*!< Capture performed once every 4 events */
lypinator 0:bb348c97df44 461 #define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /*!< Capture performed once every 8 events */
lypinator 0:bb348c97df44 462 /**
lypinator 0:bb348c97df44 463 * @}
lypinator 0:bb348c97df44 464 */
lypinator 0:bb348c97df44 465
lypinator 0:bb348c97df44 466 /** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
lypinator 0:bb348c97df44 467 * @{
lypinator 0:bb348c97df44 468 */
lypinator 0:bb348c97df44 469 #define TIM_OPMODE_SINGLE (TIM_CR1_OPM)
lypinator 0:bb348c97df44 470 #define TIM_OPMODE_REPETITIVE 0x00000000U
lypinator 0:bb348c97df44 471 /**
lypinator 0:bb348c97df44 472 * @}
lypinator 0:bb348c97df44 473 */
lypinator 0:bb348c97df44 474
lypinator 0:bb348c97df44 475 /** @defgroup TIM_Encoder_Mode TIM Encoder Mode
lypinator 0:bb348c97df44 476 * @{
lypinator 0:bb348c97df44 477 */
lypinator 0:bb348c97df44 478 #define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0)
lypinator 0:bb348c97df44 479 #define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1)
lypinator 0:bb348c97df44 480 #define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
lypinator 0:bb348c97df44 481
lypinator 0:bb348c97df44 482 /**
lypinator 0:bb348c97df44 483 * @}
lypinator 0:bb348c97df44 484 */
lypinator 0:bb348c97df44 485
lypinator 0:bb348c97df44 486 /** @defgroup TIM_Interrupt_definition TIM Interrupt definition
lypinator 0:bb348c97df44 487 * @{
lypinator 0:bb348c97df44 488 */
lypinator 0:bb348c97df44 489 #define TIM_IT_UPDATE (TIM_DIER_UIE)
lypinator 0:bb348c97df44 490 #define TIM_IT_CC1 (TIM_DIER_CC1IE)
lypinator 0:bb348c97df44 491 #define TIM_IT_CC2 (TIM_DIER_CC2IE)
lypinator 0:bb348c97df44 492 #define TIM_IT_CC3 (TIM_DIER_CC3IE)
lypinator 0:bb348c97df44 493 #define TIM_IT_CC4 (TIM_DIER_CC4IE)
lypinator 0:bb348c97df44 494 #define TIM_IT_COM (TIM_DIER_COMIE)
lypinator 0:bb348c97df44 495 #define TIM_IT_TRIGGER (TIM_DIER_TIE)
lypinator 0:bb348c97df44 496 #define TIM_IT_BREAK (TIM_DIER_BIE)
lypinator 0:bb348c97df44 497 /**
lypinator 0:bb348c97df44 498 * @}
lypinator 0:bb348c97df44 499 */
lypinator 0:bb348c97df44 500
lypinator 0:bb348c97df44 501 /** @defgroup TIM_Commutation_Source TIM Commutation Source
lypinator 0:bb348c97df44 502 * @{
lypinator 0:bb348c97df44 503 */
lypinator 0:bb348c97df44 504 #define TIM_COMMUTATION_TRGI (TIM_CR2_CCUS)
lypinator 0:bb348c97df44 505 #define TIM_COMMUTATION_SOFTWARE 0x00000000U
lypinator 0:bb348c97df44 506 /**
lypinator 0:bb348c97df44 507 * @}
lypinator 0:bb348c97df44 508 */
lypinator 0:bb348c97df44 509
lypinator 0:bb348c97df44 510 /** @defgroup TIM_DMA_sources TIM DMA sources
lypinator 0:bb348c97df44 511 * @{
lypinator 0:bb348c97df44 512 */
lypinator 0:bb348c97df44 513 #define TIM_DMA_UPDATE (TIM_DIER_UDE)
lypinator 0:bb348c97df44 514 #define TIM_DMA_CC1 (TIM_DIER_CC1DE)
lypinator 0:bb348c97df44 515 #define TIM_DMA_CC2 (TIM_DIER_CC2DE)
lypinator 0:bb348c97df44 516 #define TIM_DMA_CC3 (TIM_DIER_CC3DE)
lypinator 0:bb348c97df44 517 #define TIM_DMA_CC4 (TIM_DIER_CC4DE)
lypinator 0:bb348c97df44 518 #define TIM_DMA_COM (TIM_DIER_COMDE)
lypinator 0:bb348c97df44 519 #define TIM_DMA_TRIGGER (TIM_DIER_TDE)
lypinator 0:bb348c97df44 520 /**
lypinator 0:bb348c97df44 521 * @}
lypinator 0:bb348c97df44 522 */
lypinator 0:bb348c97df44 523
lypinator 0:bb348c97df44 524 /** @defgroup TIM_Event_Source TIM Event Source
lypinator 0:bb348c97df44 525 * @{
lypinator 0:bb348c97df44 526 */
lypinator 0:bb348c97df44 527 #define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG
lypinator 0:bb348c97df44 528 #define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G
lypinator 0:bb348c97df44 529 #define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G
lypinator 0:bb348c97df44 530 #define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G
lypinator 0:bb348c97df44 531 #define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G
lypinator 0:bb348c97df44 532 #define TIM_EVENTSOURCE_COM TIM_EGR_COMG
lypinator 0:bb348c97df44 533 #define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG
lypinator 0:bb348c97df44 534 #define TIM_EVENTSOURCE_BREAK TIM_EGR_BG
lypinator 0:bb348c97df44 535
lypinator 0:bb348c97df44 536 /**
lypinator 0:bb348c97df44 537 * @}
lypinator 0:bb348c97df44 538 */
lypinator 0:bb348c97df44 539
lypinator 0:bb348c97df44 540 /** @defgroup TIM_Flag_definition TIM Flag definition
lypinator 0:bb348c97df44 541 * @{
lypinator 0:bb348c97df44 542 */
lypinator 0:bb348c97df44 543 #define TIM_FLAG_UPDATE (TIM_SR_UIF)
lypinator 0:bb348c97df44 544 #define TIM_FLAG_CC1 (TIM_SR_CC1IF)
lypinator 0:bb348c97df44 545 #define TIM_FLAG_CC2 (TIM_SR_CC2IF)
lypinator 0:bb348c97df44 546 #define TIM_FLAG_CC3 (TIM_SR_CC3IF)
lypinator 0:bb348c97df44 547 #define TIM_FLAG_CC4 (TIM_SR_CC4IF)
lypinator 0:bb348c97df44 548 #define TIM_FLAG_COM (TIM_SR_COMIF)
lypinator 0:bb348c97df44 549 #define TIM_FLAG_TRIGGER (TIM_SR_TIF)
lypinator 0:bb348c97df44 550 #define TIM_FLAG_BREAK (TIM_SR_BIF)
lypinator 0:bb348c97df44 551 #define TIM_FLAG_CC1OF (TIM_SR_CC1OF)
lypinator 0:bb348c97df44 552 #define TIM_FLAG_CC2OF (TIM_SR_CC2OF)
lypinator 0:bb348c97df44 553 #define TIM_FLAG_CC3OF (TIM_SR_CC3OF)
lypinator 0:bb348c97df44 554 #define TIM_FLAG_CC4OF (TIM_SR_CC4OF)
lypinator 0:bb348c97df44 555 /**
lypinator 0:bb348c97df44 556 * @}
lypinator 0:bb348c97df44 557 */
lypinator 0:bb348c97df44 558
lypinator 0:bb348c97df44 559 /** @defgroup TIM_Clock_Source TIM Clock Source
lypinator 0:bb348c97df44 560 * @{
lypinator 0:bb348c97df44 561 */
lypinator 0:bb348c97df44 562 #define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1)
lypinator 0:bb348c97df44 563 #define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0)
lypinator 0:bb348c97df44 564 #define TIM_CLOCKSOURCE_ITR0 0x00000000U
lypinator 0:bb348c97df44 565 #define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0)
lypinator 0:bb348c97df44 566 #define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1)
lypinator 0:bb348c97df44 567 #define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)
lypinator 0:bb348c97df44 568 #define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2)
lypinator 0:bb348c97df44 569 #define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)
lypinator 0:bb348c97df44 570 #define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)
lypinator 0:bb348c97df44 571 #define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS)
lypinator 0:bb348c97df44 572 /**
lypinator 0:bb348c97df44 573 * @}
lypinator 0:bb348c97df44 574 */
lypinator 0:bb348c97df44 575
lypinator 0:bb348c97df44 576 /** @defgroup TIM_Clock_Polarity TIM Clock Polarity
lypinator 0:bb348c97df44 577 * @{
lypinator 0:bb348c97df44 578 */
lypinator 0:bb348c97df44 579 #define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */
lypinator 0:bb348c97df44 580 #define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */
lypinator 0:bb348c97df44 581 #define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */
lypinator 0:bb348c97df44 582 #define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */
lypinator 0:bb348c97df44 583 #define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */
lypinator 0:bb348c97df44 584 /**
lypinator 0:bb348c97df44 585 * @}
lypinator 0:bb348c97df44 586 */
lypinator 0:bb348c97df44 587
lypinator 0:bb348c97df44 588 /** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
lypinator 0:bb348c97df44 589 * @{
lypinator 0:bb348c97df44 590 */
lypinator 0:bb348c97df44 591 #define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
lypinator 0:bb348c97df44 592 #define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */
lypinator 0:bb348c97df44 593 #define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */
lypinator 0:bb348c97df44 594 #define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */
lypinator 0:bb348c97df44 595 /**
lypinator 0:bb348c97df44 596 * @}
lypinator 0:bb348c97df44 597 */
lypinator 0:bb348c97df44 598
lypinator 0:bb348c97df44 599 /** @defgroup TIM_ClearInput_Source TIM Clear Input Source
lypinator 0:bb348c97df44 600 * @{
lypinator 0:bb348c97df44 601 */
lypinator 0:bb348c97df44 602 #define TIM_CLEARINPUTSOURCE_ETR 0x00000001U
lypinator 0:bb348c97df44 603 #define TIM_CLEARINPUTSOURCE_NONE 0x00000000U
lypinator 0:bb348c97df44 604 /**
lypinator 0:bb348c97df44 605 * @}
lypinator 0:bb348c97df44 606 */
lypinator 0:bb348c97df44 607
lypinator 0:bb348c97df44 608 /** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
lypinator 0:bb348c97df44 609 * @{
lypinator 0:bb348c97df44 610 */
lypinator 0:bb348c97df44 611 #define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */
lypinator 0:bb348c97df44 612 #define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */
lypinator 0:bb348c97df44 613 /**
lypinator 0:bb348c97df44 614 * @}
lypinator 0:bb348c97df44 615 */
lypinator 0:bb348c97df44 616
lypinator 0:bb348c97df44 617 /** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
lypinator 0:bb348c97df44 618 * @{
lypinator 0:bb348c97df44 619 */
lypinator 0:bb348c97df44 620 #define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
lypinator 0:bb348c97df44 621 #define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */
lypinator 0:bb348c97df44 622 #define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */
lypinator 0:bb348c97df44 623 #define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */
lypinator 0:bb348c97df44 624 /**
lypinator 0:bb348c97df44 625 * @}
lypinator 0:bb348c97df44 626 */
lypinator 0:bb348c97df44 627
lypinator 0:bb348c97df44 628 /** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state
lypinator 0:bb348c97df44 629 * @{
lypinator 0:bb348c97df44 630 */
lypinator 0:bb348c97df44 631 #define TIM_OSSR_ENABLE (TIM_BDTR_OSSR)
lypinator 0:bb348c97df44 632 #define TIM_OSSR_DISABLE 0x00000000U
lypinator 0:bb348c97df44 633 /**
lypinator 0:bb348c97df44 634 * @}
lypinator 0:bb348c97df44 635 */
lypinator 0:bb348c97df44 636
lypinator 0:bb348c97df44 637 /** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state
lypinator 0:bb348c97df44 638 * @{
lypinator 0:bb348c97df44 639 */
lypinator 0:bb348c97df44 640 #define TIM_OSSI_ENABLE (TIM_BDTR_OSSI)
lypinator 0:bb348c97df44 641 #define TIM_OSSI_DISABLE 0x00000000U
lypinator 0:bb348c97df44 642 /**
lypinator 0:bb348c97df44 643 * @}
lypinator 0:bb348c97df44 644 */
lypinator 0:bb348c97df44 645
lypinator 0:bb348c97df44 646 /** @defgroup TIM_Lock_level TIM Lock level
lypinator 0:bb348c97df44 647 * @{
lypinator 0:bb348c97df44 648 */
lypinator 0:bb348c97df44 649 #define TIM_LOCKLEVEL_OFF 0x00000000U
lypinator 0:bb348c97df44 650 #define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0)
lypinator 0:bb348c97df44 651 #define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1)
lypinator 0:bb348c97df44 652 #define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK)
lypinator 0:bb348c97df44 653 /**
lypinator 0:bb348c97df44 654 * @}
lypinator 0:bb348c97df44 655 */
lypinator 0:bb348c97df44 656 /** @defgroup TIM_Break_Input_enable_disable TIM Break Input State
lypinator 0:bb348c97df44 657 * @{
lypinator 0:bb348c97df44 658 */
lypinator 0:bb348c97df44 659 #define TIM_BREAK_ENABLE (TIM_BDTR_BKE)
lypinator 0:bb348c97df44 660 #define TIM_BREAK_DISABLE 0x00000000U
lypinator 0:bb348c97df44 661 /**
lypinator 0:bb348c97df44 662 * @}
lypinator 0:bb348c97df44 663 */
lypinator 0:bb348c97df44 664
lypinator 0:bb348c97df44 665 /** @defgroup TIM_Break_Polarity TIM Break Polarity
lypinator 0:bb348c97df44 666 * @{
lypinator 0:bb348c97df44 667 */
lypinator 0:bb348c97df44 668 #define TIM_BREAKPOLARITY_LOW 0x00000000U
lypinator 0:bb348c97df44 669 #define TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP)
lypinator 0:bb348c97df44 670 /**
lypinator 0:bb348c97df44 671 * @}
lypinator 0:bb348c97df44 672 */
lypinator 0:bb348c97df44 673
lypinator 0:bb348c97df44 674 /** @defgroup TIM_AOE_Bit_Set_Reset TIM AOE Bit State
lypinator 0:bb348c97df44 675 * @{
lypinator 0:bb348c97df44 676 */
lypinator 0:bb348c97df44 677 #define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE)
lypinator 0:bb348c97df44 678 #define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U
lypinator 0:bb348c97df44 679 /**
lypinator 0:bb348c97df44 680 * @}
lypinator 0:bb348c97df44 681 */
lypinator 0:bb348c97df44 682
lypinator 0:bb348c97df44 683 /** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
lypinator 0:bb348c97df44 684 * @{
lypinator 0:bb348c97df44 685 */
lypinator 0:bb348c97df44 686 #define TIM_TRGO_RESET 0x00000000U
lypinator 0:bb348c97df44 687 #define TIM_TRGO_ENABLE (TIM_CR2_MMS_0)
lypinator 0:bb348c97df44 688 #define TIM_TRGO_UPDATE (TIM_CR2_MMS_1)
lypinator 0:bb348c97df44 689 #define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
lypinator 0:bb348c97df44 690 #define TIM_TRGO_OC1REF (TIM_CR2_MMS_2)
lypinator 0:bb348c97df44 691 #define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0))
lypinator 0:bb348c97df44 692 #define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1))
lypinator 0:bb348c97df44 693 #define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
lypinator 0:bb348c97df44 694 /**
lypinator 0:bb348c97df44 695 * @}
lypinator 0:bb348c97df44 696 */
lypinator 0:bb348c97df44 697
lypinator 0:bb348c97df44 698 /** @defgroup TIM_Slave_Mode TIM Slave Mode
lypinator 0:bb348c97df44 699 * @{
lypinator 0:bb348c97df44 700 */
lypinator 0:bb348c97df44 701 #define TIM_SLAVEMODE_DISABLE 0x00000000U
lypinator 0:bb348c97df44 702 #define TIM_SLAVEMODE_RESET 0x00000004U
lypinator 0:bb348c97df44 703 #define TIM_SLAVEMODE_GATED 0x00000005U
lypinator 0:bb348c97df44 704 #define TIM_SLAVEMODE_TRIGGER 0x00000006U
lypinator 0:bb348c97df44 705 #define TIM_SLAVEMODE_EXTERNAL1 0x00000007U
lypinator 0:bb348c97df44 706 /**
lypinator 0:bb348c97df44 707 * @}
lypinator 0:bb348c97df44 708 */
lypinator 0:bb348c97df44 709
lypinator 0:bb348c97df44 710 /** @defgroup TIM_Master_Slave_Mode TIM Master Slave Mode
lypinator 0:bb348c97df44 711 * @{
lypinator 0:bb348c97df44 712 */
lypinator 0:bb348c97df44 713 #define TIM_MASTERSLAVEMODE_ENABLE 0x00000080U
lypinator 0:bb348c97df44 714 #define TIM_MASTERSLAVEMODE_DISABLE 0x00000000U
lypinator 0:bb348c97df44 715 /**
lypinator 0:bb348c97df44 716 * @}
lypinator 0:bb348c97df44 717 */
lypinator 0:bb348c97df44 718
lypinator 0:bb348c97df44 719 /** @defgroup TIM_Trigger_Selection TIM Trigger Selection
lypinator 0:bb348c97df44 720 * @{
lypinator 0:bb348c97df44 721 */
lypinator 0:bb348c97df44 722 #define TIM_TS_ITR0 0x00000000U
lypinator 0:bb348c97df44 723 #define TIM_TS_ITR1 0x00000010U
lypinator 0:bb348c97df44 724 #define TIM_TS_ITR2 0x00000020U
lypinator 0:bb348c97df44 725 #define TIM_TS_ITR3 0x00000030U
lypinator 0:bb348c97df44 726 #define TIM_TS_TI1F_ED 0x00000040U
lypinator 0:bb348c97df44 727 #define TIM_TS_TI1FP1 0x00000050U
lypinator 0:bb348c97df44 728 #define TIM_TS_TI2FP2 0x00000060U
lypinator 0:bb348c97df44 729 #define TIM_TS_ETRF 0x00000070U
lypinator 0:bb348c97df44 730 #define TIM_TS_NONE 0x0000FFFFU
lypinator 0:bb348c97df44 731 /**
lypinator 0:bb348c97df44 732 * @}
lypinator 0:bb348c97df44 733 */
lypinator 0:bb348c97df44 734
lypinator 0:bb348c97df44 735 /** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
lypinator 0:bb348c97df44 736 * @{
lypinator 0:bb348c97df44 737 */
lypinator 0:bb348c97df44 738 #define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */
lypinator 0:bb348c97df44 739 #define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */
lypinator 0:bb348c97df44 740 #define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
lypinator 0:bb348c97df44 741 #define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
lypinator 0:bb348c97df44 742 #define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */
lypinator 0:bb348c97df44 743 /**
lypinator 0:bb348c97df44 744 * @}
lypinator 0:bb348c97df44 745 */
lypinator 0:bb348c97df44 746
lypinator 0:bb348c97df44 747 /** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
lypinator 0:bb348c97df44 748 * @{
lypinator 0:bb348c97df44 749 */
lypinator 0:bb348c97df44 750 #define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
lypinator 0:bb348c97df44 751 #define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */
lypinator 0:bb348c97df44 752 #define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */
lypinator 0:bb348c97df44 753 #define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */
lypinator 0:bb348c97df44 754 /**
lypinator 0:bb348c97df44 755 * @}
lypinator 0:bb348c97df44 756 */
lypinator 0:bb348c97df44 757
lypinator 0:bb348c97df44 758
lypinator 0:bb348c97df44 759 /** @defgroup TIM_TI1_Selection TIM TI1 Selection
lypinator 0:bb348c97df44 760 * @{
lypinator 0:bb348c97df44 761 */
lypinator 0:bb348c97df44 762 #define TIM_TI1SELECTION_CH1 0x00000000U
lypinator 0:bb348c97df44 763 #define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S)
lypinator 0:bb348c97df44 764 /**
lypinator 0:bb348c97df44 765 * @}
lypinator 0:bb348c97df44 766 */
lypinator 0:bb348c97df44 767
lypinator 0:bb348c97df44 768 /** @defgroup TIM_DMA_Base_address TIM DMA Base address
lypinator 0:bb348c97df44 769 * @{
lypinator 0:bb348c97df44 770 */
lypinator 0:bb348c97df44 771 #define TIM_DMABASE_CR1 0x00000000U
lypinator 0:bb348c97df44 772 #define TIM_DMABASE_CR2 0x00000001U
lypinator 0:bb348c97df44 773 #define TIM_DMABASE_SMCR 0x00000002U
lypinator 0:bb348c97df44 774 #define TIM_DMABASE_DIER 0x00000003U
lypinator 0:bb348c97df44 775 #define TIM_DMABASE_SR 0x00000004U
lypinator 0:bb348c97df44 776 #define TIM_DMABASE_EGR 0x00000005U
lypinator 0:bb348c97df44 777 #define TIM_DMABASE_CCMR1 0x00000006U
lypinator 0:bb348c97df44 778 #define TIM_DMABASE_CCMR2 0x00000007U
lypinator 0:bb348c97df44 779 #define TIM_DMABASE_CCER 0x00000008U
lypinator 0:bb348c97df44 780 #define TIM_DMABASE_CNT 0x00000009U
lypinator 0:bb348c97df44 781 #define TIM_DMABASE_PSC 0x0000000AU
lypinator 0:bb348c97df44 782 #define TIM_DMABASE_ARR 0x0000000BU
lypinator 0:bb348c97df44 783 #define TIM_DMABASE_RCR 0x0000000CU
lypinator 0:bb348c97df44 784 #define TIM_DMABASE_CCR1 0x0000000DU
lypinator 0:bb348c97df44 785 #define TIM_DMABASE_CCR2 0x0000000EU
lypinator 0:bb348c97df44 786 #define TIM_DMABASE_CCR3 0x0000000FU
lypinator 0:bb348c97df44 787 #define TIM_DMABASE_CCR4 0x00000010U
lypinator 0:bb348c97df44 788 #define TIM_DMABASE_BDTR 0x00000011U
lypinator 0:bb348c97df44 789 #define TIM_DMABASE_DCR 0x00000012U
lypinator 0:bb348c97df44 790 #define TIM_DMABASE_OR 0x00000013U
lypinator 0:bb348c97df44 791 /**
lypinator 0:bb348c97df44 792 * @}
lypinator 0:bb348c97df44 793 */
lypinator 0:bb348c97df44 794
lypinator 0:bb348c97df44 795 /** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
lypinator 0:bb348c97df44 796 * @{
lypinator 0:bb348c97df44 797 */
lypinator 0:bb348c97df44 798 #define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U
lypinator 0:bb348c97df44 799 #define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U
lypinator 0:bb348c97df44 800 #define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U
lypinator 0:bb348c97df44 801 #define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U
lypinator 0:bb348c97df44 802 #define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U
lypinator 0:bb348c97df44 803 #define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U
lypinator 0:bb348c97df44 804 #define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U
lypinator 0:bb348c97df44 805 #define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U
lypinator 0:bb348c97df44 806 #define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U
lypinator 0:bb348c97df44 807 #define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U
lypinator 0:bb348c97df44 808 #define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U
lypinator 0:bb348c97df44 809 #define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U
lypinator 0:bb348c97df44 810 #define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U
lypinator 0:bb348c97df44 811 #define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U
lypinator 0:bb348c97df44 812 #define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U
lypinator 0:bb348c97df44 813 #define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U
lypinator 0:bb348c97df44 814 #define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U
lypinator 0:bb348c97df44 815 #define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U
lypinator 0:bb348c97df44 816 /**
lypinator 0:bb348c97df44 817 * @}
lypinator 0:bb348c97df44 818 */
lypinator 0:bb348c97df44 819
lypinator 0:bb348c97df44 820 /** @defgroup DMA_Handle_index DMA Handle index
lypinator 0:bb348c97df44 821 * @{
lypinator 0:bb348c97df44 822 */
lypinator 0:bb348c97df44 823 #define TIM_DMA_ID_UPDATE ((uint16_t)0x0000) /*!< Index of the DMA handle used for Update DMA requests */
lypinator 0:bb348c97df44 824 #define TIM_DMA_ID_CC1 ((uint16_t)0x0001) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */
lypinator 0:bb348c97df44 825 #define TIM_DMA_ID_CC2 ((uint16_t)0x0002) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */
lypinator 0:bb348c97df44 826 #define TIM_DMA_ID_CC3 ((uint16_t)0x0003) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */
lypinator 0:bb348c97df44 827 #define TIM_DMA_ID_CC4 ((uint16_t)0x0004) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */
lypinator 0:bb348c97df44 828 #define TIM_DMA_ID_COMMUTATION ((uint16_t)0x0005) /*!< Index of the DMA handle used for Commutation DMA requests */
lypinator 0:bb348c97df44 829 #define TIM_DMA_ID_TRIGGER ((uint16_t)0x0006) /*!< Index of the DMA handle used for Trigger DMA requests */
lypinator 0:bb348c97df44 830 /**
lypinator 0:bb348c97df44 831 * @}
lypinator 0:bb348c97df44 832 */
lypinator 0:bb348c97df44 833
lypinator 0:bb348c97df44 834 /** @defgroup Channel_CC_State Channel CC State
lypinator 0:bb348c97df44 835 * @{
lypinator 0:bb348c97df44 836 */
lypinator 0:bb348c97df44 837 #define TIM_CCx_ENABLE 0x00000001U
lypinator 0:bb348c97df44 838 #define TIM_CCx_DISABLE 0x00000000U
lypinator 0:bb348c97df44 839 #define TIM_CCxN_ENABLE 0x00000004U
lypinator 0:bb348c97df44 840 #define TIM_CCxN_DISABLE 0x00000000U
lypinator 0:bb348c97df44 841 /**
lypinator 0:bb348c97df44 842 * @}
lypinator 0:bb348c97df44 843 */
lypinator 0:bb348c97df44 844
lypinator 0:bb348c97df44 845 /**
lypinator 0:bb348c97df44 846 * @}
lypinator 0:bb348c97df44 847 */
lypinator 0:bb348c97df44 848
lypinator 0:bb348c97df44 849 /* Exported macro ------------------------------------------------------------*/
lypinator 0:bb348c97df44 850 /** @defgroup TIM_Exported_Macros TIM Exported Macros
lypinator 0:bb348c97df44 851 * @{
lypinator 0:bb348c97df44 852 */
lypinator 0:bb348c97df44 853 /** @brief Reset TIM handle state
lypinator 0:bb348c97df44 854 * @param __HANDLE__ TIM handle
lypinator 0:bb348c97df44 855 * @retval None
lypinator 0:bb348c97df44 856 */
lypinator 0:bb348c97df44 857 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
lypinator 0:bb348c97df44 858
lypinator 0:bb348c97df44 859 /**
lypinator 0:bb348c97df44 860 * @brief Enable the TIM peripheral.
lypinator 0:bb348c97df44 861 * @param __HANDLE__ TIM handle
lypinator 0:bb348c97df44 862 * @retval None
lypinator 0:bb348c97df44 863 */
lypinator 0:bb348c97df44 864 #define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
lypinator 0:bb348c97df44 865
lypinator 0:bb348c97df44 866 /**
lypinator 0:bb348c97df44 867 * @brief Enable the TIM main Output.
lypinator 0:bb348c97df44 868 * @param __HANDLE__ TIM handle
lypinator 0:bb348c97df44 869 * @retval None
lypinator 0:bb348c97df44 870 */
lypinator 0:bb348c97df44 871 #define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))
lypinator 0:bb348c97df44 872
lypinator 0:bb348c97df44 873
lypinator 0:bb348c97df44 874 /**
lypinator 0:bb348c97df44 875 * @brief Disable the TIM peripheral.
lypinator 0:bb348c97df44 876 * @param __HANDLE__ TIM handle
lypinator 0:bb348c97df44 877 * @retval None
lypinator 0:bb348c97df44 878 */
lypinator 0:bb348c97df44 879 #define __HAL_TIM_DISABLE(__HANDLE__) \
lypinator 0:bb348c97df44 880 do { \
lypinator 0:bb348c97df44 881 if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0U) \
lypinator 0:bb348c97df44 882 { \
lypinator 0:bb348c97df44 883 if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0U) \
lypinator 0:bb348c97df44 884 { \
lypinator 0:bb348c97df44 885 (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
lypinator 0:bb348c97df44 886 } \
lypinator 0:bb348c97df44 887 } \
lypinator 0:bb348c97df44 888 } while(0U)
lypinator 0:bb348c97df44 889
lypinator 0:bb348c97df44 890 /* The Main Output of a timer instance is disabled only if all the CCx and CCxN
lypinator 0:bb348c97df44 891 channels have been disabled */
lypinator 0:bb348c97df44 892 /**
lypinator 0:bb348c97df44 893 * @brief Disable the TIM main Output.
lypinator 0:bb348c97df44 894 * @param __HANDLE__ TIM handle
lypinator 0:bb348c97df44 895 * @retval None
lypinator 0:bb348c97df44 896 */
lypinator 0:bb348c97df44 897 #define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
lypinator 0:bb348c97df44 898 do { \
lypinator 0:bb348c97df44 899 if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0U) \
lypinator 0:bb348c97df44 900 { \
lypinator 0:bb348c97df44 901 if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0U) \
lypinator 0:bb348c97df44 902 { \
lypinator 0:bb348c97df44 903 (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
lypinator 0:bb348c97df44 904 } \
lypinator 0:bb348c97df44 905 } \
lypinator 0:bb348c97df44 906 } while(0U)
lypinator 0:bb348c97df44 907
lypinator 0:bb348c97df44 908 /**
lypinator 0:bb348c97df44 909 * @brief Disable the TIM main Output.
lypinator 0:bb348c97df44 910 * @param __HANDLE__ TIM handle
lypinator 0:bb348c97df44 911 * @retval None
lypinator 0:bb348c97df44 912 * @note The Main Output Enable of a timer instance is disabled unconditionally
lypinator 0:bb348c97df44 913 */
lypinator 0:bb348c97df44 914 #define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE)
lypinator 0:bb348c97df44 915
lypinator 0:bb348c97df44 916 /** @brief Enable the specified TIM interrupt.
lypinator 0:bb348c97df44 917 * @param __HANDLE__ specifies the TIM Handle.
lypinator 0:bb348c97df44 918 * @param __INTERRUPT__ specifies the TIM interrupt source to enable.
lypinator 0:bb348c97df44 919 * This parameter can be one of the following values:
lypinator 0:bb348c97df44 920 * @arg TIM_IT_UPDATE: Update interrupt
lypinator 0:bb348c97df44 921 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
lypinator 0:bb348c97df44 922 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
lypinator 0:bb348c97df44 923 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
lypinator 0:bb348c97df44 924 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
lypinator 0:bb348c97df44 925 * @arg TIM_IT_COM: Commutation interrupt
lypinator 0:bb348c97df44 926 * @arg TIM_IT_TRIGGER: Trigger interrupt
lypinator 0:bb348c97df44 927 * @arg TIM_IT_BREAK: Break interrupt
lypinator 0:bb348c97df44 928 * @retval None
lypinator 0:bb348c97df44 929 */
lypinator 0:bb348c97df44 930 #define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
lypinator 0:bb348c97df44 931
lypinator 0:bb348c97df44 932
lypinator 0:bb348c97df44 933 /** @brief Disable the specified TIM interrupt.
lypinator 0:bb348c97df44 934 * @param __HANDLE__ specifies the TIM Handle.
lypinator 0:bb348c97df44 935 * @param __INTERRUPT__ specifies the TIM interrupt source to disable.
lypinator 0:bb348c97df44 936 * This parameter can be one of the following values:
lypinator 0:bb348c97df44 937 * @arg TIM_IT_UPDATE: Update interrupt
lypinator 0:bb348c97df44 938 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
lypinator 0:bb348c97df44 939 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
lypinator 0:bb348c97df44 940 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
lypinator 0:bb348c97df44 941 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
lypinator 0:bb348c97df44 942 * @arg TIM_IT_COM: Commutation interrupt
lypinator 0:bb348c97df44 943 * @arg TIM_IT_TRIGGER: Trigger interrupt
lypinator 0:bb348c97df44 944 * @arg TIM_IT_BREAK: Break interrupt
lypinator 0:bb348c97df44 945 * @retval None
lypinator 0:bb348c97df44 946 */
lypinator 0:bb348c97df44 947 #define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
lypinator 0:bb348c97df44 948
lypinator 0:bb348c97df44 949 /** @brief Enable the specified DMA request.
lypinator 0:bb348c97df44 950 * @param __HANDLE__ specifies the TIM Handle.
lypinator 0:bb348c97df44 951 * @param __DMA__ specifies the TIM DMA request to enable.
lypinator 0:bb348c97df44 952 * This parameter can be one of the following values:
lypinator 0:bb348c97df44 953 * @arg TIM_DMA_UPDATE: Update DMA request
lypinator 0:bb348c97df44 954 * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
lypinator 0:bb348c97df44 955 * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
lypinator 0:bb348c97df44 956 * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
lypinator 0:bb348c97df44 957 * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
lypinator 0:bb348c97df44 958 * @arg TIM_DMA_COM: Commutation DMA request
lypinator 0:bb348c97df44 959 * @arg TIM_DMA_TRIGGER: Trigger DMA request
lypinator 0:bb348c97df44 960 * @retval None
lypinator 0:bb348c97df44 961 */
lypinator 0:bb348c97df44 962 #define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__))
lypinator 0:bb348c97df44 963
lypinator 0:bb348c97df44 964 /** @brief Disable the specified DMA request.
lypinator 0:bb348c97df44 965 * @param __HANDLE__ specifies the TIM Handle.
lypinator 0:bb348c97df44 966 * @param __DMA__ specifies the TIM DMA request to disable.
lypinator 0:bb348c97df44 967 * This parameter can be one of the following values:
lypinator 0:bb348c97df44 968 * @arg TIM_DMA_UPDATE: Update DMA request
lypinator 0:bb348c97df44 969 * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
lypinator 0:bb348c97df44 970 * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
lypinator 0:bb348c97df44 971 * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
lypinator 0:bb348c97df44 972 * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
lypinator 0:bb348c97df44 973 * @arg TIM_DMA_COM: Commutation DMA request
lypinator 0:bb348c97df44 974 * @arg TIM_DMA_TRIGGER: Trigger DMA request
lypinator 0:bb348c97df44 975 * @retval None
lypinator 0:bb348c97df44 976 */
lypinator 0:bb348c97df44 977 #define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
lypinator 0:bb348c97df44 978
lypinator 0:bb348c97df44 979 /** @brief Check whether the specified TIM interrupt flag is set or not.
lypinator 0:bb348c97df44 980 * @param __HANDLE__ specifies the TIM Handle.
lypinator 0:bb348c97df44 981 * @param __FLAG__ specifies the TIM interrupt flag to check.
lypinator 0:bb348c97df44 982 * This parameter can be one of the following values:
lypinator 0:bb348c97df44 983 * @arg TIM_FLAG_UPDATE: Update interrupt flag
lypinator 0:bb348c97df44 984 * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
lypinator 0:bb348c97df44 985 * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
lypinator 0:bb348c97df44 986 * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
lypinator 0:bb348c97df44 987 * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
lypinator 0:bb348c97df44 988 * @arg TIM_FLAG_CC5: Compare 5 interrupt flag
lypinator 0:bb348c97df44 989 * @arg TIM_FLAG_CC6: Compare 6 interrupt flag
lypinator 0:bb348c97df44 990 * @arg TIM_FLAG_COM: Commutation interrupt flag
lypinator 0:bb348c97df44 991 * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
lypinator 0:bb348c97df44 992 * @arg TIM_FLAG_BREAK: Break interrupt flag
lypinator 0:bb348c97df44 993 * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag
lypinator 0:bb348c97df44 994 * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag
lypinator 0:bb348c97df44 995 * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
lypinator 0:bb348c97df44 996 * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
lypinator 0:bb348c97df44 997 * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
lypinator 0:bb348c97df44 998 * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
lypinator 0:bb348c97df44 999 * @retval The new state of __FLAG__ (TRUE or FALSE).
lypinator 0:bb348c97df44 1000 */
lypinator 0:bb348c97df44 1001 #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
lypinator 0:bb348c97df44 1002
lypinator 0:bb348c97df44 1003 /** @brief Clear the specified TIM interrupt flag.
lypinator 0:bb348c97df44 1004 * @param __HANDLE__ specifies the TIM Handle.
lypinator 0:bb348c97df44 1005 * @param __FLAG__ specifies the TIM interrupt flag to clear.
lypinator 0:bb348c97df44 1006 * This parameter can be one of the following values:
lypinator 0:bb348c97df44 1007 * @arg TIM_FLAG_UPDATE: Update interrupt flag
lypinator 0:bb348c97df44 1008 * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
lypinator 0:bb348c97df44 1009 * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
lypinator 0:bb348c97df44 1010 * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
lypinator 0:bb348c97df44 1011 * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
lypinator 0:bb348c97df44 1012 * @arg TIM_FLAG_CC5: Compare 5 interrupt flag
lypinator 0:bb348c97df44 1013 * @arg TIM_FLAG_CC6: Compare 6 interrupt flag
lypinator 0:bb348c97df44 1014 * @arg TIM_FLAG_COM: Commutation interrupt flag
lypinator 0:bb348c97df44 1015 * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
lypinator 0:bb348c97df44 1016 * @arg TIM_FLAG_BREAK: Break interrupt flag
lypinator 0:bb348c97df44 1017 * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag
lypinator 0:bb348c97df44 1018 * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag
lypinator 0:bb348c97df44 1019 * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
lypinator 0:bb348c97df44 1020 * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
lypinator 0:bb348c97df44 1021 * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
lypinator 0:bb348c97df44 1022 * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
lypinator 0:bb348c97df44 1023 * @retval The new state of __FLAG__ (TRUE or FALSE).
lypinator 0:bb348c97df44 1024 */
lypinator 0:bb348c97df44 1025 #define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
lypinator 0:bb348c97df44 1026
lypinator 0:bb348c97df44 1027 /**
lypinator 0:bb348c97df44 1028 * @brief Check whether the specified TIM interrupt source is enabled or not.
lypinator 0:bb348c97df44 1029 * @param __HANDLE__ TIM handle
lypinator 0:bb348c97df44 1030 * @param __INTERRUPT__ specifies the TIM interrupt source to check.
lypinator 0:bb348c97df44 1031 * This parameter can be one of the following values:
lypinator 0:bb348c97df44 1032 * @arg TIM_IT_UPDATE: Update interrupt
lypinator 0:bb348c97df44 1033 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
lypinator 0:bb348c97df44 1034 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
lypinator 0:bb348c97df44 1035 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
lypinator 0:bb348c97df44 1036 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
lypinator 0:bb348c97df44 1037 * @arg TIM_IT_COM: Commutation interrupt
lypinator 0:bb348c97df44 1038 * @arg TIM_IT_TRIGGER: Trigger interrupt
lypinator 0:bb348c97df44 1039 * @arg TIM_IT_BREAK: Break interrupt
lypinator 0:bb348c97df44 1040 * @retval The state of TIM_IT (SET or RESET).
lypinator 0:bb348c97df44 1041 */
lypinator 0:bb348c97df44 1042 #define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
lypinator 0:bb348c97df44 1043
lypinator 0:bb348c97df44 1044 /** @brief Clear the TIM interrupt pending bits.
lypinator 0:bb348c97df44 1045 * @param __HANDLE__ TIM handle
lypinator 0:bb348c97df44 1046 * @param __INTERRUPT__ specifies the interrupt pending bit to clear.
lypinator 0:bb348c97df44 1047 * This parameter can be one of the following values:
lypinator 0:bb348c97df44 1048 * @arg TIM_IT_UPDATE: Update interrupt
lypinator 0:bb348c97df44 1049 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
lypinator 0:bb348c97df44 1050 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
lypinator 0:bb348c97df44 1051 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
lypinator 0:bb348c97df44 1052 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
lypinator 0:bb348c97df44 1053 * @arg TIM_IT_COM: Commutation interrupt
lypinator 0:bb348c97df44 1054 * @arg TIM_IT_TRIGGER: Trigger interrupt
lypinator 0:bb348c97df44 1055 * @arg TIM_IT_BREAK: Break interrupt
lypinator 0:bb348c97df44 1056 * @retval None
lypinator 0:bb348c97df44 1057 */
lypinator 0:bb348c97df44 1058 #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
lypinator 0:bb348c97df44 1059
lypinator 0:bb348c97df44 1060 /**
lypinator 0:bb348c97df44 1061 * @brief Indicates whether or not the TIM Counter is used as downcounter.
lypinator 0:bb348c97df44 1062 * @param __HANDLE__ TIM handle.
lypinator 0:bb348c97df44 1063 * @retval False (Counter used as upcounter) or True (Counter used as downcounter)
lypinator 0:bb348c97df44 1064 * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode or Encoder
lypinator 0:bb348c97df44 1065 mode.
lypinator 0:bb348c97df44 1066 */
lypinator 0:bb348c97df44 1067 #define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
lypinator 0:bb348c97df44 1068
lypinator 0:bb348c97df44 1069 /**
lypinator 0:bb348c97df44 1070 * @brief Set the TIM Prescaler on runtime.
lypinator 0:bb348c97df44 1071 * @param __HANDLE__ TIM handle.
lypinator 0:bb348c97df44 1072 * @param __PRESC__ specifies the Prescaler new value.
lypinator 0:bb348c97df44 1073 * @retval None
lypinator 0:bb348c97df44 1074 */
lypinator 0:bb348c97df44 1075 #define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
lypinator 0:bb348c97df44 1076
lypinator 0:bb348c97df44 1077 #define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
lypinator 0:bb348c97df44 1078 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
lypinator 0:bb348c97df44 1079 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\
lypinator 0:bb348c97df44 1080 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
lypinator 0:bb348c97df44 1081 ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))
lypinator 0:bb348c97df44 1082
lypinator 0:bb348c97df44 1083 #define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
lypinator 0:bb348c97df44 1084 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\
lypinator 0:bb348c97df44 1085 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\
lypinator 0:bb348c97df44 1086 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\
lypinator 0:bb348c97df44 1087 ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC))
lypinator 0:bb348c97df44 1088
lypinator 0:bb348c97df44 1089 #define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
lypinator 0:bb348c97df44 1090 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
lypinator 0:bb348c97df44 1091 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\
lypinator 0:bb348c97df44 1092 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\
lypinator 0:bb348c97df44 1093 ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U) & TIM_CCER_CC4P)))
lypinator 0:bb348c97df44 1094
lypinator 0:bb348c97df44 1095 #define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
lypinator 0:bb348c97df44 1096 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
lypinator 0:bb348c97df44 1097 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
lypinator 0:bb348c97df44 1098 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
lypinator 0:bb348c97df44 1099 ((__HANDLE__)->Instance->CCER &= (uint16_t)~TIM_CCER_CC4P))
lypinator 0:bb348c97df44 1100
lypinator 0:bb348c97df44 1101 /**
lypinator 0:bb348c97df44 1102 * @brief Sets the TIM Capture Compare Register value on runtime without
lypinator 0:bb348c97df44 1103 * calling another time ConfigChannel function.
lypinator 0:bb348c97df44 1104 * @param __HANDLE__ TIM handle.
lypinator 0:bb348c97df44 1105 * @param __CHANNEL__ TIM Channels to be configured.
lypinator 0:bb348c97df44 1106 * This parameter can be one of the following values:
lypinator 0:bb348c97df44 1107 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
lypinator 0:bb348c97df44 1108 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
lypinator 0:bb348c97df44 1109 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
lypinator 0:bb348c97df44 1110 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
lypinator 0:bb348c97df44 1111 * @param __COMPARE__ specifies the Capture Compare register new value.
lypinator 0:bb348c97df44 1112 * @retval None
lypinator 0:bb348c97df44 1113 */
lypinator 0:bb348c97df44 1114 #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
lypinator 0:bb348c97df44 1115 (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)) = (__COMPARE__))
lypinator 0:bb348c97df44 1116
lypinator 0:bb348c97df44 1117 /**
lypinator 0:bb348c97df44 1118 * @brief Gets the TIM Capture Compare Register value on runtime.
lypinator 0:bb348c97df44 1119 * @param __HANDLE__ TIM handle.
lypinator 0:bb348c97df44 1120 * @param __CHANNEL__ TIM Channel associated with the capture compare register
lypinator 0:bb348c97df44 1121 * This parameter can be one of the following values:
lypinator 0:bb348c97df44 1122 * @arg TIM_CHANNEL_1: get capture/compare 1 register value
lypinator 0:bb348c97df44 1123 * @arg TIM_CHANNEL_2: get capture/compare 2 register value
lypinator 0:bb348c97df44 1124 * @arg TIM_CHANNEL_3: get capture/compare 3 register value
lypinator 0:bb348c97df44 1125 * @arg TIM_CHANNEL_4: get capture/compare 4 register value
lypinator 0:bb348c97df44 1126 * @arg TIM_CHANNEL_5: get capture/compare 5 register value
lypinator 0:bb348c97df44 1127 * @arg TIM_CHANNEL_6: get capture/compare 6 register value
lypinator 0:bb348c97df44 1128 * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy)
lypinator 0:bb348c97df44 1129 */
lypinator 0:bb348c97df44 1130 #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
lypinator 0:bb348c97df44 1131 (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)))
lypinator 0:bb348c97df44 1132
lypinator 0:bb348c97df44 1133 /**
lypinator 0:bb348c97df44 1134 * @brief Sets the TIM Counter Register value on runtime.
lypinator 0:bb348c97df44 1135 * @param __HANDLE__ TIM handle.
lypinator 0:bb348c97df44 1136 * @param __COUNTER__ specifies the Counter register new value.
lypinator 0:bb348c97df44 1137 * @retval None
lypinator 0:bb348c97df44 1138 */
lypinator 0:bb348c97df44 1139 #define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
lypinator 0:bb348c97df44 1140
lypinator 0:bb348c97df44 1141 /**
lypinator 0:bb348c97df44 1142 * @brief Gets the TIM Counter Register value on runtime.
lypinator 0:bb348c97df44 1143 * @param __HANDLE__ TIM handle.
lypinator 0:bb348c97df44 1144 * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT)
lypinator 0:bb348c97df44 1145 */
lypinator 0:bb348c97df44 1146 #define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT)
lypinator 0:bb348c97df44 1147
lypinator 0:bb348c97df44 1148 /**
lypinator 0:bb348c97df44 1149 * @brief Sets the TIM Autoreload Register value on runtime without calling
lypinator 0:bb348c97df44 1150 * another time any Init function.
lypinator 0:bb348c97df44 1151 * @param __HANDLE__ TIM handle.
lypinator 0:bb348c97df44 1152 * @param __AUTORELOAD__ specifies the Counter register new value.
lypinator 0:bb348c97df44 1153 * @retval None
lypinator 0:bb348c97df44 1154 */
lypinator 0:bb348c97df44 1155 #define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
lypinator 0:bb348c97df44 1156 do{ \
lypinator 0:bb348c97df44 1157 (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
lypinator 0:bb348c97df44 1158 (__HANDLE__)->Init.Period = (__AUTORELOAD__); \
lypinator 0:bb348c97df44 1159 } while(0U)
lypinator 0:bb348c97df44 1160 /**
lypinator 0:bb348c97df44 1161 * @brief Gets the TIM Autoreload Register value on runtime.
lypinator 0:bb348c97df44 1162 * @param __HANDLE__ TIM handle.
lypinator 0:bb348c97df44 1163 * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR)
lypinator 0:bb348c97df44 1164 */
lypinator 0:bb348c97df44 1165 #define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR)
lypinator 0:bb348c97df44 1166
lypinator 0:bb348c97df44 1167 /**
lypinator 0:bb348c97df44 1168 * @brief Sets the TIM Clock Division value on runtime without calling another time any Init function.
lypinator 0:bb348c97df44 1169 * @param __HANDLE__ TIM handle.
lypinator 0:bb348c97df44 1170 * @param __CKD__ specifies the clock division value.
lypinator 0:bb348c97df44 1171 * This parameter can be one of the following value:
lypinator 0:bb348c97df44 1172 * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
lypinator 0:bb348c97df44 1173 * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
lypinator 0:bb348c97df44 1174 * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
lypinator 0:bb348c97df44 1175 * @retval None
lypinator 0:bb348c97df44 1176 */
lypinator 0:bb348c97df44 1177 #define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
lypinator 0:bb348c97df44 1178 do{ \
lypinator 0:bb348c97df44 1179 (__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD); \
lypinator 0:bb348c97df44 1180 (__HANDLE__)->Instance->CR1 |= (__CKD__); \
lypinator 0:bb348c97df44 1181 (__HANDLE__)->Init.ClockDivision = (__CKD__); \
lypinator 0:bb348c97df44 1182 } while(0U)
lypinator 0:bb348c97df44 1183 /**
lypinator 0:bb348c97df44 1184 * @brief Gets the TIM Clock Division value on runtime.
lypinator 0:bb348c97df44 1185 * @param __HANDLE__ TIM handle.
lypinator 0:bb348c97df44 1186 * @retval The clock division can be one of the following values:
lypinator 0:bb348c97df44 1187 * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
lypinator 0:bb348c97df44 1188 * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
lypinator 0:bb348c97df44 1189 * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
lypinator 0:bb348c97df44 1190 */
lypinator 0:bb348c97df44 1191 #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
lypinator 0:bb348c97df44 1192
lypinator 0:bb348c97df44 1193 /**
lypinator 0:bb348c97df44 1194 * @brief Sets the TIM Input Capture prescaler on runtime without calling
lypinator 0:bb348c97df44 1195 * another time HAL_TIM_IC_ConfigChannel() function.
lypinator 0:bb348c97df44 1196 * @param __HANDLE__ TIM handle.
lypinator 0:bb348c97df44 1197 * @param __CHANNEL__ TIM Channels to be configured.
lypinator 0:bb348c97df44 1198 * This parameter can be one of the following values:
lypinator 0:bb348c97df44 1199 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
lypinator 0:bb348c97df44 1200 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
lypinator 0:bb348c97df44 1201 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
lypinator 0:bb348c97df44 1202 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
lypinator 0:bb348c97df44 1203 * @param __ICPSC__ specifies the Input Capture4 prescaler new value.
lypinator 0:bb348c97df44 1204 * This parameter can be one of the following values:
lypinator 0:bb348c97df44 1205 * @arg TIM_ICPSC_DIV1: no prescaler
lypinator 0:bb348c97df44 1206 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
lypinator 0:bb348c97df44 1207 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
lypinator 0:bb348c97df44 1208 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
lypinator 0:bb348c97df44 1209 * @retval None
lypinator 0:bb348c97df44 1210 */
lypinator 0:bb348c97df44 1211 #define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
lypinator 0:bb348c97df44 1212 do{ \
lypinator 0:bb348c97df44 1213 TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \
lypinator 0:bb348c97df44 1214 TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
lypinator 0:bb348c97df44 1215 } while(0U)
lypinator 0:bb348c97df44 1216
lypinator 0:bb348c97df44 1217 /**
lypinator 0:bb348c97df44 1218 * @brief Get the TIM Input Capture prescaler on runtime.
lypinator 0:bb348c97df44 1219 * @param __HANDLE__ TIM handle.
lypinator 0:bb348c97df44 1220 * @param __CHANNEL__ TIM Channels to be configured.
lypinator 0:bb348c97df44 1221 * This parameter can be one of the following values:
lypinator 0:bb348c97df44 1222 * @arg TIM_CHANNEL_1: get input capture 1 prescaler value
lypinator 0:bb348c97df44 1223 * @arg TIM_CHANNEL_2: get input capture 2 prescaler value
lypinator 0:bb348c97df44 1224 * @arg TIM_CHANNEL_3: get input capture 3 prescaler value
lypinator 0:bb348c97df44 1225 * @arg TIM_CHANNEL_4: get input capture 4 prescaler value
lypinator 0:bb348c97df44 1226 * @retval The input capture prescaler can be one of the following values:
lypinator 0:bb348c97df44 1227 * @arg TIM_ICPSC_DIV1: no prescaler
lypinator 0:bb348c97df44 1228 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
lypinator 0:bb348c97df44 1229 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
lypinator 0:bb348c97df44 1230 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
lypinator 0:bb348c97df44 1231 */
lypinator 0:bb348c97df44 1232 #define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \
lypinator 0:bb348c97df44 1233 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
lypinator 0:bb348c97df44 1234 ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\
lypinator 0:bb348c97df44 1235 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
lypinator 0:bb348c97df44 1236 (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)
lypinator 0:bb348c97df44 1237
lypinator 0:bb348c97df44 1238 /**
lypinator 0:bb348c97df44 1239 * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register
lypinator 0:bb348c97df44 1240 * @param __HANDLE__ TIM handle.
lypinator 0:bb348c97df44 1241 * @note When the USR bit of the TIMx_CR1 register is set, only counter
lypinator 0:bb348c97df44 1242 * overflow/underflow generates an update interrupt or DMA request (if
lypinator 0:bb348c97df44 1243 * enabled)
lypinator 0:bb348c97df44 1244 * @retval None
lypinator 0:bb348c97df44 1245 */
lypinator 0:bb348c97df44 1246 #define __HAL_TIM_URS_ENABLE(__HANDLE__) \
lypinator 0:bb348c97df44 1247 ((__HANDLE__)->Instance->CR1|= (TIM_CR1_URS))
lypinator 0:bb348c97df44 1248
lypinator 0:bb348c97df44 1249 /**
lypinator 0:bb348c97df44 1250 * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register
lypinator 0:bb348c97df44 1251 * @param __HANDLE__ TIM handle.
lypinator 0:bb348c97df44 1252 * @note When the USR bit of the TIMx_CR1 register is reset, any of the
lypinator 0:bb348c97df44 1253 * following events generate an update interrupt or DMA request (if
lypinator 0:bb348c97df44 1254 * enabled):
lypinator 0:bb348c97df44 1255 * _ Counter overflow/underflow
lypinator 0:bb348c97df44 1256 * _ Setting the UG bit
lypinator 0:bb348c97df44 1257 * _ Update generation through the slave mode controller
lypinator 0:bb348c97df44 1258 * @retval None
lypinator 0:bb348c97df44 1259 */
lypinator 0:bb348c97df44 1260 #define __HAL_TIM_URS_DISABLE(__HANDLE__) \
lypinator 0:bb348c97df44 1261 ((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS))
lypinator 0:bb348c97df44 1262
lypinator 0:bb348c97df44 1263 /**
lypinator 0:bb348c97df44 1264 * @brief Sets the TIM Capture x input polarity on runtime.
lypinator 0:bb348c97df44 1265 * @param __HANDLE__ TIM handle.
lypinator 0:bb348c97df44 1266 * @param __CHANNEL__ TIM Channels to be configured.
lypinator 0:bb348c97df44 1267 * This parameter can be one of the following values:
lypinator 0:bb348c97df44 1268 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
lypinator 0:bb348c97df44 1269 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
lypinator 0:bb348c97df44 1270 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
lypinator 0:bb348c97df44 1271 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
lypinator 0:bb348c97df44 1272 * @param __POLARITY__ Polarity for TIx source
lypinator 0:bb348c97df44 1273 * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
lypinator 0:bb348c97df44 1274 * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
lypinator 0:bb348c97df44 1275 * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
lypinator 0:bb348c97df44 1276 * @note The polarity TIM_INPUTCHANNELPOLARITY_BOTHEDGE is not authorized for TIM Channel 4.
lypinator 0:bb348c97df44 1277 * @retval None
lypinator 0:bb348c97df44 1278 */
lypinator 0:bb348c97df44 1279 #define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
lypinator 0:bb348c97df44 1280 do{ \
lypinator 0:bb348c97df44 1281 TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \
lypinator 0:bb348c97df44 1282 TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
lypinator 0:bb348c97df44 1283 }while(0U)
lypinator 0:bb348c97df44 1284 /**
lypinator 0:bb348c97df44 1285 * @}
lypinator 0:bb348c97df44 1286 */
lypinator 0:bb348c97df44 1287
lypinator 0:bb348c97df44 1288 /* Include TIM HAL Extension module */
lypinator 0:bb348c97df44 1289 #include "stm32f4xx_hal_tim_ex.h"
lypinator 0:bb348c97df44 1290
lypinator 0:bb348c97df44 1291 /* Exported functions --------------------------------------------------------*/
lypinator 0:bb348c97df44 1292 /** @addtogroup TIM_Exported_Functions
lypinator 0:bb348c97df44 1293 * @{
lypinator 0:bb348c97df44 1294 */
lypinator 0:bb348c97df44 1295
lypinator 0:bb348c97df44 1296 /** @addtogroup TIM_Exported_Functions_Group1
lypinator 0:bb348c97df44 1297 * @{
lypinator 0:bb348c97df44 1298 */
lypinator 0:bb348c97df44 1299
lypinator 0:bb348c97df44 1300 /* Time Base functions ********************************************************/
lypinator 0:bb348c97df44 1301 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
lypinator 0:bb348c97df44 1302 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
lypinator 0:bb348c97df44 1303 void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
lypinator 0:bb348c97df44 1304 void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
lypinator 0:bb348c97df44 1305 /* Blocking mode: Polling */
lypinator 0:bb348c97df44 1306 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
lypinator 0:bb348c97df44 1307 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
lypinator 0:bb348c97df44 1308 /* Non-Blocking mode: Interrupt */
lypinator 0:bb348c97df44 1309 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
lypinator 0:bb348c97df44 1310 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
lypinator 0:bb348c97df44 1311 /* Non-Blocking mode: DMA */
lypinator 0:bb348c97df44 1312 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
lypinator 0:bb348c97df44 1313 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
lypinator 0:bb348c97df44 1314 /**
lypinator 0:bb348c97df44 1315 * @}
lypinator 0:bb348c97df44 1316 */
lypinator 0:bb348c97df44 1317
lypinator 0:bb348c97df44 1318 /** @addtogroup TIM_Exported_Functions_Group2
lypinator 0:bb348c97df44 1319 * @{
lypinator 0:bb348c97df44 1320 */
lypinator 0:bb348c97df44 1321 /* Timer Output Compare functions **********************************************/
lypinator 0:bb348c97df44 1322 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
lypinator 0:bb348c97df44 1323 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
lypinator 0:bb348c97df44 1324 void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
lypinator 0:bb348c97df44 1325 void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
lypinator 0:bb348c97df44 1326 /* Blocking mode: Polling */
lypinator 0:bb348c97df44 1327 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
lypinator 0:bb348c97df44 1328 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
lypinator 0:bb348c97df44 1329 /* Non-Blocking mode: Interrupt */
lypinator 0:bb348c97df44 1330 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
lypinator 0:bb348c97df44 1331 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
lypinator 0:bb348c97df44 1332 /* Non-Blocking mode: DMA */
lypinator 0:bb348c97df44 1333 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
lypinator 0:bb348c97df44 1334 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
lypinator 0:bb348c97df44 1335
lypinator 0:bb348c97df44 1336 /**
lypinator 0:bb348c97df44 1337 * @}
lypinator 0:bb348c97df44 1338 */
lypinator 0:bb348c97df44 1339
lypinator 0:bb348c97df44 1340 /** @addtogroup TIM_Exported_Functions_Group3
lypinator 0:bb348c97df44 1341 * @{
lypinator 0:bb348c97df44 1342 */
lypinator 0:bb348c97df44 1343 /* Timer PWM functions *********************************************************/
lypinator 0:bb348c97df44 1344 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
lypinator 0:bb348c97df44 1345 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
lypinator 0:bb348c97df44 1346 void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
lypinator 0:bb348c97df44 1347 void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
lypinator 0:bb348c97df44 1348 /* Blocking mode: Polling */
lypinator 0:bb348c97df44 1349 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
lypinator 0:bb348c97df44 1350 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
lypinator 0:bb348c97df44 1351 /* Non-Blocking mode: Interrupt */
lypinator 0:bb348c97df44 1352 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
lypinator 0:bb348c97df44 1353 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
lypinator 0:bb348c97df44 1354 /* Non-Blocking mode: DMA */
lypinator 0:bb348c97df44 1355 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
lypinator 0:bb348c97df44 1356 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
lypinator 0:bb348c97df44 1357
lypinator 0:bb348c97df44 1358 /**
lypinator 0:bb348c97df44 1359 * @}
lypinator 0:bb348c97df44 1360 */
lypinator 0:bb348c97df44 1361
lypinator 0:bb348c97df44 1362 /** @addtogroup TIM_Exported_Functions_Group4
lypinator 0:bb348c97df44 1363 * @{
lypinator 0:bb348c97df44 1364 */
lypinator 0:bb348c97df44 1365 /* Timer Input Capture functions ***********************************************/
lypinator 0:bb348c97df44 1366 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
lypinator 0:bb348c97df44 1367 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
lypinator 0:bb348c97df44 1368 void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
lypinator 0:bb348c97df44 1369 void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
lypinator 0:bb348c97df44 1370 /* Blocking mode: Polling */
lypinator 0:bb348c97df44 1371 HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
lypinator 0:bb348c97df44 1372 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
lypinator 0:bb348c97df44 1373 /* Non-Blocking mode: Interrupt */
lypinator 0:bb348c97df44 1374 HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
lypinator 0:bb348c97df44 1375 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
lypinator 0:bb348c97df44 1376 /* Non-Blocking mode: DMA */
lypinator 0:bb348c97df44 1377 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
lypinator 0:bb348c97df44 1378 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
lypinator 0:bb348c97df44 1379
lypinator 0:bb348c97df44 1380 /**
lypinator 0:bb348c97df44 1381 * @}
lypinator 0:bb348c97df44 1382 */
lypinator 0:bb348c97df44 1383
lypinator 0:bb348c97df44 1384 /** @addtogroup TIM_Exported_Functions_Group5
lypinator 0:bb348c97df44 1385 * @{
lypinator 0:bb348c97df44 1386 */
lypinator 0:bb348c97df44 1387 /* Timer One Pulse functions ***************************************************/
lypinator 0:bb348c97df44 1388 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
lypinator 0:bb348c97df44 1389 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
lypinator 0:bb348c97df44 1390 void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
lypinator 0:bb348c97df44 1391 void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
lypinator 0:bb348c97df44 1392 /* Blocking mode: Polling */
lypinator 0:bb348c97df44 1393 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
lypinator 0:bb348c97df44 1394 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
lypinator 0:bb348c97df44 1395
lypinator 0:bb348c97df44 1396 /* Non-Blocking mode: Interrupt */
lypinator 0:bb348c97df44 1397 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
lypinator 0:bb348c97df44 1398 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
lypinator 0:bb348c97df44 1399
lypinator 0:bb348c97df44 1400 /**
lypinator 0:bb348c97df44 1401 * @}
lypinator 0:bb348c97df44 1402 */
lypinator 0:bb348c97df44 1403
lypinator 0:bb348c97df44 1404 /** @addtogroup TIM_Exported_Functions_Group6
lypinator 0:bb348c97df44 1405 * @{
lypinator 0:bb348c97df44 1406 */
lypinator 0:bb348c97df44 1407 /* Timer Encoder functions *****************************************************/
lypinator 0:bb348c97df44 1408 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig);
lypinator 0:bb348c97df44 1409 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
lypinator 0:bb348c97df44 1410 void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
lypinator 0:bb348c97df44 1411 void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
lypinator 0:bb348c97df44 1412 /* Blocking mode: Polling */
lypinator 0:bb348c97df44 1413 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
lypinator 0:bb348c97df44 1414 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
lypinator 0:bb348c97df44 1415 /* Non-Blocking mode: Interrupt */
lypinator 0:bb348c97df44 1416 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
lypinator 0:bb348c97df44 1417 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
lypinator 0:bb348c97df44 1418 /* Non-Blocking mode: DMA */
lypinator 0:bb348c97df44 1419 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length);
lypinator 0:bb348c97df44 1420 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
lypinator 0:bb348c97df44 1421
lypinator 0:bb348c97df44 1422 /**
lypinator 0:bb348c97df44 1423 * @}
lypinator 0:bb348c97df44 1424 */
lypinator 0:bb348c97df44 1425
lypinator 0:bb348c97df44 1426 /** @addtogroup TIM_Exported_Functions_Group7
lypinator 0:bb348c97df44 1427 * @{
lypinator 0:bb348c97df44 1428 */
lypinator 0:bb348c97df44 1429 /* Interrupt Handler functions **********************************************/
lypinator 0:bb348c97df44 1430 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
lypinator 0:bb348c97df44 1431
lypinator 0:bb348c97df44 1432 /**
lypinator 0:bb348c97df44 1433 * @}
lypinator 0:bb348c97df44 1434 */
lypinator 0:bb348c97df44 1435
lypinator 0:bb348c97df44 1436 /** @addtogroup TIM_Exported_Functions_Group8
lypinator 0:bb348c97df44 1437 * @{
lypinator 0:bb348c97df44 1438 */
lypinator 0:bb348c97df44 1439 /* Control functions *********************************************************/
lypinator 0:bb348c97df44 1440 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
lypinator 0:bb348c97df44 1441 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
lypinator 0:bb348c97df44 1442 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel);
lypinator 0:bb348c97df44 1443 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel);
lypinator 0:bb348c97df44 1444 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel);
lypinator 0:bb348c97df44 1445 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig);
lypinator 0:bb348c97df44 1446 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
lypinator 0:bb348c97df44 1447 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);
lypinator 0:bb348c97df44 1448 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);
lypinator 0:bb348c97df44 1449 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
lypinator 0:bb348c97df44 1450 uint32_t *BurstBuffer, uint32_t BurstLength);
lypinator 0:bb348c97df44 1451 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
lypinator 0:bb348c97df44 1452 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
lypinator 0:bb348c97df44 1453 uint32_t *BurstBuffer, uint32_t BurstLength);
lypinator 0:bb348c97df44 1454 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
lypinator 0:bb348c97df44 1455 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
lypinator 0:bb348c97df44 1456 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
lypinator 0:bb348c97df44 1457
lypinator 0:bb348c97df44 1458 /**
lypinator 0:bb348c97df44 1459 * @}
lypinator 0:bb348c97df44 1460 */
lypinator 0:bb348c97df44 1461
lypinator 0:bb348c97df44 1462 /** @addtogroup TIM_Exported_Functions_Group9
lypinator 0:bb348c97df44 1463 * @{
lypinator 0:bb348c97df44 1464 */
lypinator 0:bb348c97df44 1465 /* Callback in non blocking modes (Interrupt and DMA) *************************/
lypinator 0:bb348c97df44 1466 void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
lypinator 0:bb348c97df44 1467 void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
lypinator 0:bb348c97df44 1468 void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
lypinator 0:bb348c97df44 1469 void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
lypinator 0:bb348c97df44 1470 void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
lypinator 0:bb348c97df44 1471 void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
lypinator 0:bb348c97df44 1472
lypinator 0:bb348c97df44 1473 /**
lypinator 0:bb348c97df44 1474 * @}
lypinator 0:bb348c97df44 1475 */
lypinator 0:bb348c97df44 1476
lypinator 0:bb348c97df44 1477 /** @addtogroup TIM_Exported_Functions_Group10
lypinator 0:bb348c97df44 1478 * @{
lypinator 0:bb348c97df44 1479 */
lypinator 0:bb348c97df44 1480 /* Peripheral State functions **************************************************/
lypinator 0:bb348c97df44 1481 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
lypinator 0:bb348c97df44 1482 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
lypinator 0:bb348c97df44 1483 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
lypinator 0:bb348c97df44 1484 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
lypinator 0:bb348c97df44 1485 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
lypinator 0:bb348c97df44 1486 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
lypinator 0:bb348c97df44 1487
lypinator 0:bb348c97df44 1488 /**
lypinator 0:bb348c97df44 1489 * @}
lypinator 0:bb348c97df44 1490 */
lypinator 0:bb348c97df44 1491
lypinator 0:bb348c97df44 1492 /**
lypinator 0:bb348c97df44 1493 * @}
lypinator 0:bb348c97df44 1494 */
lypinator 0:bb348c97df44 1495
lypinator 0:bb348c97df44 1496 /* Private macros ------------------------------------------------------------*/
lypinator 0:bb348c97df44 1497 /** @defgroup TIM_Private_Macros TIM Private Macros
lypinator 0:bb348c97df44 1498 * @{
lypinator 0:bb348c97df44 1499 */
lypinator 0:bb348c97df44 1500
lypinator 0:bb348c97df44 1501 /** @defgroup TIM_IS_TIM_Definitions TIM Private macros to check input parameters
lypinator 0:bb348c97df44 1502 * @{
lypinator 0:bb348c97df44 1503 */
lypinator 0:bb348c97df44 1504 #define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_COUNTERMODE_UP) || \
lypinator 0:bb348c97df44 1505 ((MODE) == TIM_COUNTERMODE_DOWN) || \
lypinator 0:bb348c97df44 1506 ((MODE) == TIM_COUNTERMODE_CENTERALIGNED1) || \
lypinator 0:bb348c97df44 1507 ((MODE) == TIM_COUNTERMODE_CENTERALIGNED2) || \
lypinator 0:bb348c97df44 1508 ((MODE) == TIM_COUNTERMODE_CENTERALIGNED3))
lypinator 0:bb348c97df44 1509
lypinator 0:bb348c97df44 1510 #define IS_TIM_CLOCKDIVISION_DIV(DIV) (((DIV) == TIM_CLOCKDIVISION_DIV1) || \
lypinator 0:bb348c97df44 1511 ((DIV) == TIM_CLOCKDIVISION_DIV2) || \
lypinator 0:bb348c97df44 1512 ((DIV) == TIM_CLOCKDIVISION_DIV4))
lypinator 0:bb348c97df44 1513
lypinator 0:bb348c97df44 1514 #define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) || \
lypinator 0:bb348c97df44 1515 ((MODE) == TIM_OCMODE_PWM2))
lypinator 0:bb348c97df44 1516
lypinator 0:bb348c97df44 1517 #define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) || \
lypinator 0:bb348c97df44 1518 ((MODE) == TIM_OCMODE_ACTIVE) || \
lypinator 0:bb348c97df44 1519 ((MODE) == TIM_OCMODE_INACTIVE) || \
lypinator 0:bb348c97df44 1520 ((MODE) == TIM_OCMODE_TOGGLE) || \
lypinator 0:bb348c97df44 1521 ((MODE) == TIM_OCMODE_FORCED_ACTIVE) || \
lypinator 0:bb348c97df44 1522 ((MODE) == TIM_OCMODE_FORCED_INACTIVE))
lypinator 0:bb348c97df44 1523
lypinator 0:bb348c97df44 1524 #define IS_TIM_FAST_STATE(STATE) (((STATE) == TIM_OCFAST_DISABLE) || \
lypinator 0:bb348c97df44 1525 ((STATE) == TIM_OCFAST_ENABLE))
lypinator 0:bb348c97df44 1526
lypinator 0:bb348c97df44 1527 #define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPOLARITY_HIGH) || \
lypinator 0:bb348c97df44 1528 ((POLARITY) == TIM_OCPOLARITY_LOW))
lypinator 0:bb348c97df44 1529
lypinator 0:bb348c97df44 1530 #define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPOLARITY_HIGH) || \
lypinator 0:bb348c97df44 1531 ((POLARITY) == TIM_OCNPOLARITY_LOW))
lypinator 0:bb348c97df44 1532
lypinator 0:bb348c97df44 1533 #define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIDLESTATE_SET) || \
lypinator 0:bb348c97df44 1534 ((STATE) == TIM_OCIDLESTATE_RESET))
lypinator 0:bb348c97df44 1535
lypinator 0:bb348c97df44 1536 #define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIDLESTATE_SET) || \
lypinator 0:bb348c97df44 1537 ((STATE) == TIM_OCNIDLESTATE_RESET))
lypinator 0:bb348c97df44 1538
lypinator 0:bb348c97df44 1539 #define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
lypinator 0:bb348c97df44 1540 ((CHANNEL) == TIM_CHANNEL_2) || \
lypinator 0:bb348c97df44 1541 ((CHANNEL) == TIM_CHANNEL_3) || \
lypinator 0:bb348c97df44 1542 ((CHANNEL) == TIM_CHANNEL_4) || \
lypinator 0:bb348c97df44 1543 ((CHANNEL) == TIM_CHANNEL_ALL))
lypinator 0:bb348c97df44 1544
lypinator 0:bb348c97df44 1545 #define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
lypinator 0:bb348c97df44 1546 ((CHANNEL) == TIM_CHANNEL_2))
lypinator 0:bb348c97df44 1547
lypinator 0:bb348c97df44 1548 #define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
lypinator 0:bb348c97df44 1549 ((CHANNEL) == TIM_CHANNEL_2) || \
lypinator 0:bb348c97df44 1550 ((CHANNEL) == TIM_CHANNEL_3))
lypinator 0:bb348c97df44 1551
lypinator 0:bb348c97df44 1552 #define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPOLARITY_RISING) || \
lypinator 0:bb348c97df44 1553 ((POLARITY) == TIM_ICPOLARITY_FALLING) || \
lypinator 0:bb348c97df44 1554 ((POLARITY) == TIM_ICPOLARITY_BOTHEDGE))
lypinator 0:bb348c97df44 1555
lypinator 0:bb348c97df44 1556 #define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSELECTION_DIRECTTI) || \
lypinator 0:bb348c97df44 1557 ((SELECTION) == TIM_ICSELECTION_INDIRECTTI) || \
lypinator 0:bb348c97df44 1558 ((SELECTION) == TIM_ICSELECTION_TRC))
lypinator 0:bb348c97df44 1559
lypinator 0:bb348c97df44 1560 #define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \
lypinator 0:bb348c97df44 1561 ((PRESCALER) == TIM_ICPSC_DIV2) || \
lypinator 0:bb348c97df44 1562 ((PRESCALER) == TIM_ICPSC_DIV4) || \
lypinator 0:bb348c97df44 1563 ((PRESCALER) == TIM_ICPSC_DIV8))
lypinator 0:bb348c97df44 1564
lypinator 0:bb348c97df44 1565 #define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMODE_SINGLE) || \
lypinator 0:bb348c97df44 1566 ((MODE) == TIM_OPMODE_REPETITIVE))
lypinator 0:bb348c97df44 1567
lypinator 0:bb348c97df44 1568 #define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FFU) == 0x00000000U) && ((SOURCE) != 0x00000000U))
lypinator 0:bb348c97df44 1569
lypinator 0:bb348c97df44 1570 #define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_ENCODERMODE_TI1) || \
lypinator 0:bb348c97df44 1571 ((MODE) == TIM_ENCODERMODE_TI2) || \
lypinator 0:bb348c97df44 1572 ((MODE) == TIM_ENCODERMODE_TI12))
lypinator 0:bb348c97df44 1573
lypinator 0:bb348c97df44 1574 #define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00U) == 0x00000000U) && ((SOURCE) != 0x00000000U))
lypinator 0:bb348c97df44 1575
lypinator 0:bb348c97df44 1576 #define IS_TIM_CLOCKSOURCE(CLOCK) (((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) || \
lypinator 0:bb348c97df44 1577 ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) || \
lypinator 0:bb348c97df44 1578 ((CLOCK) == TIM_CLOCKSOURCE_ITR0) || \
lypinator 0:bb348c97df44 1579 ((CLOCK) == TIM_CLOCKSOURCE_ITR1) || \
lypinator 0:bb348c97df44 1580 ((CLOCK) == TIM_CLOCKSOURCE_ITR2) || \
lypinator 0:bb348c97df44 1581 ((CLOCK) == TIM_CLOCKSOURCE_ITR3) || \
lypinator 0:bb348c97df44 1582 ((CLOCK) == TIM_CLOCKSOURCE_TI1ED) || \
lypinator 0:bb348c97df44 1583 ((CLOCK) == TIM_CLOCKSOURCE_TI1) || \
lypinator 0:bb348c97df44 1584 ((CLOCK) == TIM_CLOCKSOURCE_TI2) || \
lypinator 0:bb348c97df44 1585 ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1))
lypinator 0:bb348c97df44 1586
lypinator 0:bb348c97df44 1587 #define IS_TIM_CLOCKPOLARITY(POLARITY) (((POLARITY) == TIM_CLOCKPOLARITY_INVERTED) || \
lypinator 0:bb348c97df44 1588 ((POLARITY) == TIM_CLOCKPOLARITY_NONINVERTED) || \
lypinator 0:bb348c97df44 1589 ((POLARITY) == TIM_CLOCKPOLARITY_RISING) || \
lypinator 0:bb348c97df44 1590 ((POLARITY) == TIM_CLOCKPOLARITY_FALLING) || \
lypinator 0:bb348c97df44 1591 ((POLARITY) == TIM_CLOCKPOLARITY_BOTHEDGE))
lypinator 0:bb348c97df44 1592
lypinator 0:bb348c97df44 1593 #define IS_TIM_CLOCKPRESCALER(PRESCALER) (((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) || \
lypinator 0:bb348c97df44 1594 ((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) || \
lypinator 0:bb348c97df44 1595 ((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) || \
lypinator 0:bb348c97df44 1596 ((PRESCALER) == TIM_CLOCKPRESCALER_DIV8))
lypinator 0:bb348c97df44 1597
lypinator 0:bb348c97df44 1598 #define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0x0FU)
lypinator 0:bb348c97df44 1599
lypinator 0:bb348c97df44 1600 #define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_NONE) || \
lypinator 0:bb348c97df44 1601 ((SOURCE) == TIM_CLEARINPUTSOURCE_ETR))
lypinator 0:bb348c97df44 1602
lypinator 0:bb348c97df44 1603 #define IS_TIM_CLEARINPUT_POLARITY(POLARITY) (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
lypinator 0:bb348c97df44 1604 ((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
lypinator 0:bb348c97df44 1605
lypinator 0:bb348c97df44 1606 #define IS_TIM_CLEARINPUT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV1) || \
lypinator 0:bb348c97df44 1607 ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV2) || \
lypinator 0:bb348c97df44 1608 ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) || \
lypinator 0:bb348c97df44 1609 ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8))
lypinator 0:bb348c97df44 1610
lypinator 0:bb348c97df44 1611 #define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0x0FU)
lypinator 0:bb348c97df44 1612
lypinator 0:bb348c97df44 1613 #define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) || \
lypinator 0:bb348c97df44 1614 ((STATE) == TIM_OSSR_DISABLE))
lypinator 0:bb348c97df44 1615
lypinator 0:bb348c97df44 1616 #define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSI_ENABLE) || \
lypinator 0:bb348c97df44 1617 ((STATE) == TIM_OSSI_DISABLE))
lypinator 0:bb348c97df44 1618
lypinator 0:bb348c97df44 1619 #define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLEVEL_OFF) || \
lypinator 0:bb348c97df44 1620 ((LEVEL) == TIM_LOCKLEVEL_1) || \
lypinator 0:bb348c97df44 1621 ((LEVEL) == TIM_LOCKLEVEL_2) || \
lypinator 0:bb348c97df44 1622 ((LEVEL) == TIM_LOCKLEVEL_3))
lypinator 0:bb348c97df44 1623
lypinator 0:bb348c97df44 1624 #define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_BREAK_ENABLE) || \
lypinator 0:bb348c97df44 1625 ((STATE) == TIM_BREAK_DISABLE))
lypinator 0:bb348c97df44 1626
lypinator 0:bb348c97df44 1627 #define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BREAKPOLARITY_LOW) || \
lypinator 0:bb348c97df44 1628 ((POLARITY) == TIM_BREAKPOLARITY_HIGH))
lypinator 0:bb348c97df44 1629
lypinator 0:bb348c97df44 1630 #define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AUTOMATICOUTPUT_ENABLE) || \
lypinator 0:bb348c97df44 1631 ((STATE) == TIM_AUTOMATICOUTPUT_DISABLE))
lypinator 0:bb348c97df44 1632
lypinator 0:bb348c97df44 1633 #define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO_RESET) || \
lypinator 0:bb348c97df44 1634 ((SOURCE) == TIM_TRGO_ENABLE) || \
lypinator 0:bb348c97df44 1635 ((SOURCE) == TIM_TRGO_UPDATE) || \
lypinator 0:bb348c97df44 1636 ((SOURCE) == TIM_TRGO_OC1) || \
lypinator 0:bb348c97df44 1637 ((SOURCE) == TIM_TRGO_OC1REF) || \
lypinator 0:bb348c97df44 1638 ((SOURCE) == TIM_TRGO_OC2REF) || \
lypinator 0:bb348c97df44 1639 ((SOURCE) == TIM_TRGO_OC3REF) || \
lypinator 0:bb348c97df44 1640 ((SOURCE) == TIM_TRGO_OC4REF))
lypinator 0:bb348c97df44 1641
lypinator 0:bb348c97df44 1642 #define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) || \
lypinator 0:bb348c97df44 1643 ((MODE) == TIM_SLAVEMODE_GATED) || \
lypinator 0:bb348c97df44 1644 ((MODE) == TIM_SLAVEMODE_RESET) || \
lypinator 0:bb348c97df44 1645 ((MODE) == TIM_SLAVEMODE_TRIGGER) || \
lypinator 0:bb348c97df44 1646 ((MODE) == TIM_SLAVEMODE_EXTERNAL1))
lypinator 0:bb348c97df44 1647
lypinator 0:bb348c97df44 1648 #define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MASTERSLAVEMODE_ENABLE) || \
lypinator 0:bb348c97df44 1649 ((STATE) == TIM_MASTERSLAVEMODE_DISABLE))
lypinator 0:bb348c97df44 1650
lypinator 0:bb348c97df44 1651 #define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
lypinator 0:bb348c97df44 1652 ((SELECTION) == TIM_TS_ITR1) || \
lypinator 0:bb348c97df44 1653 ((SELECTION) == TIM_TS_ITR2) || \
lypinator 0:bb348c97df44 1654 ((SELECTION) == TIM_TS_ITR3) || \
lypinator 0:bb348c97df44 1655 ((SELECTION) == TIM_TS_TI1F_ED) || \
lypinator 0:bb348c97df44 1656 ((SELECTION) == TIM_TS_TI1FP1) || \
lypinator 0:bb348c97df44 1657 ((SELECTION) == TIM_TS_TI2FP2) || \
lypinator 0:bb348c97df44 1658 ((SELECTION) == TIM_TS_ETRF))
lypinator 0:bb348c97df44 1659
lypinator 0:bb348c97df44 1660 #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
lypinator 0:bb348c97df44 1661 ((SELECTION) == TIM_TS_ITR1) || \
lypinator 0:bb348c97df44 1662 ((SELECTION) == TIM_TS_ITR2) || \
lypinator 0:bb348c97df44 1663 ((SELECTION) == TIM_TS_ITR3) || \
lypinator 0:bb348c97df44 1664 ((SELECTION) == TIM_TS_NONE))
lypinator 0:bb348c97df44 1665
lypinator 0:bb348c97df44 1666 #define IS_TIM_TRIGGERPOLARITY(POLARITY) (((POLARITY) == TIM_TRIGGERPOLARITY_INVERTED ) || \
lypinator 0:bb348c97df44 1667 ((POLARITY) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
lypinator 0:bb348c97df44 1668 ((POLARITY) == TIM_TRIGGERPOLARITY_RISING ) || \
lypinator 0:bb348c97df44 1669 ((POLARITY) == TIM_TRIGGERPOLARITY_FALLING ) || \
lypinator 0:bb348c97df44 1670 ((POLARITY) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
lypinator 0:bb348c97df44 1671
lypinator 0:bb348c97df44 1672 #define IS_TIM_TRIGGERPRESCALER(PRESCALER) (((PRESCALER) == TIM_TRIGGERPRESCALER_DIV1) || \
lypinator 0:bb348c97df44 1673 ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV2) || \
lypinator 0:bb348c97df44 1674 ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) || \
lypinator 0:bb348c97df44 1675 ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8))
lypinator 0:bb348c97df44 1676
lypinator 0:bb348c97df44 1677 #define IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0x0FU)
lypinator 0:bb348c97df44 1678
lypinator 0:bb348c97df44 1679 #define IS_TIM_TI1SELECTION(TI1SELECTION) (((TI1SELECTION) == TIM_TI1SELECTION_CH1) || \
lypinator 0:bb348c97df44 1680 ((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION))
lypinator 0:bb348c97df44 1681
lypinator 0:bb348c97df44 1682 #define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABASE_CR1) || \
lypinator 0:bb348c97df44 1683 ((BASE) == TIM_DMABASE_CR2) || \
lypinator 0:bb348c97df44 1684 ((BASE) == TIM_DMABASE_SMCR) || \
lypinator 0:bb348c97df44 1685 ((BASE) == TIM_DMABASE_DIER) || \
lypinator 0:bb348c97df44 1686 ((BASE) == TIM_DMABASE_SR) || \
lypinator 0:bb348c97df44 1687 ((BASE) == TIM_DMABASE_EGR) || \
lypinator 0:bb348c97df44 1688 ((BASE) == TIM_DMABASE_CCMR1) || \
lypinator 0:bb348c97df44 1689 ((BASE) == TIM_DMABASE_CCMR2) || \
lypinator 0:bb348c97df44 1690 ((BASE) == TIM_DMABASE_CCER) || \
lypinator 0:bb348c97df44 1691 ((BASE) == TIM_DMABASE_CNT) || \
lypinator 0:bb348c97df44 1692 ((BASE) == TIM_DMABASE_PSC) || \
lypinator 0:bb348c97df44 1693 ((BASE) == TIM_DMABASE_ARR) || \
lypinator 0:bb348c97df44 1694 ((BASE) == TIM_DMABASE_RCR) || \
lypinator 0:bb348c97df44 1695 ((BASE) == TIM_DMABASE_CCR1) || \
lypinator 0:bb348c97df44 1696 ((BASE) == TIM_DMABASE_CCR2) || \
lypinator 0:bb348c97df44 1697 ((BASE) == TIM_DMABASE_CCR3) || \
lypinator 0:bb348c97df44 1698 ((BASE) == TIM_DMABASE_CCR4) || \
lypinator 0:bb348c97df44 1699 ((BASE) == TIM_DMABASE_BDTR) || \
lypinator 0:bb348c97df44 1700 ((BASE) == TIM_DMABASE_DCR) || \
lypinator 0:bb348c97df44 1701 ((BASE) == TIM_DMABASE_OR))
lypinator 0:bb348c97df44 1702
lypinator 0:bb348c97df44 1703 #define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABURSTLENGTH_1TRANSFER) || \
lypinator 0:bb348c97df44 1704 ((LENGTH) == TIM_DMABURSTLENGTH_2TRANSFERS) || \
lypinator 0:bb348c97df44 1705 ((LENGTH) == TIM_DMABURSTLENGTH_3TRANSFERS) || \
lypinator 0:bb348c97df44 1706 ((LENGTH) == TIM_DMABURSTLENGTH_4TRANSFERS) || \
lypinator 0:bb348c97df44 1707 ((LENGTH) == TIM_DMABURSTLENGTH_5TRANSFERS) || \
lypinator 0:bb348c97df44 1708 ((LENGTH) == TIM_DMABURSTLENGTH_6TRANSFERS) || \
lypinator 0:bb348c97df44 1709 ((LENGTH) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
lypinator 0:bb348c97df44 1710 ((LENGTH) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
lypinator 0:bb348c97df44 1711 ((LENGTH) == TIM_DMABURSTLENGTH_9TRANSFERS) || \
lypinator 0:bb348c97df44 1712 ((LENGTH) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
lypinator 0:bb348c97df44 1713 ((LENGTH) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
lypinator 0:bb348c97df44 1714 ((LENGTH) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
lypinator 0:bb348c97df44 1715 ((LENGTH) == TIM_DMABURSTLENGTH_13TRANSFERS) || \
lypinator 0:bb348c97df44 1716 ((LENGTH) == TIM_DMABURSTLENGTH_14TRANSFERS) || \
lypinator 0:bb348c97df44 1717 ((LENGTH) == TIM_DMABURSTLENGTH_15TRANSFERS) || \
lypinator 0:bb348c97df44 1718 ((LENGTH) == TIM_DMABURSTLENGTH_16TRANSFERS) || \
lypinator 0:bb348c97df44 1719 ((LENGTH) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
lypinator 0:bb348c97df44 1720 ((LENGTH) == TIM_DMABURSTLENGTH_18TRANSFERS))
lypinator 0:bb348c97df44 1721
lypinator 0:bb348c97df44 1722 #define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0x0FU)
lypinator 0:bb348c97df44 1723 /**
lypinator 0:bb348c97df44 1724 * @}
lypinator 0:bb348c97df44 1725 */
lypinator 0:bb348c97df44 1726
lypinator 0:bb348c97df44 1727 /** @defgroup TIM_Mask_Definitions TIM Mask Definition
lypinator 0:bb348c97df44 1728 * @{
lypinator 0:bb348c97df44 1729 */
lypinator 0:bb348c97df44 1730 /* The counter of a timer instance is disabled only if all the CCx and CCxN
lypinator 0:bb348c97df44 1731 channels have been disabled */
lypinator 0:bb348c97df44 1732 #define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
lypinator 0:bb348c97df44 1733 #define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))
lypinator 0:bb348c97df44 1734 /**
lypinator 0:bb348c97df44 1735 * @}
lypinator 0:bb348c97df44 1736 */
lypinator 0:bb348c97df44 1737
lypinator 0:bb348c97df44 1738 /**
lypinator 0:bb348c97df44 1739 * @}
lypinator 0:bb348c97df44 1740 */
lypinator 0:bb348c97df44 1741
lypinator 0:bb348c97df44 1742 /* Private functions ---------------------------------------------------------*/
lypinator 0:bb348c97df44 1743 /** @defgroup TIM_Private_Functions TIM Private Functions
lypinator 0:bb348c97df44 1744 * @{
lypinator 0:bb348c97df44 1745 */
lypinator 0:bb348c97df44 1746 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);
lypinator 0:bb348c97df44 1747 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
lypinator 0:bb348c97df44 1748 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
lypinator 0:bb348c97df44 1749 void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
lypinator 0:bb348c97df44 1750 void TIM_DMAError(DMA_HandleTypeDef *hdma);
lypinator 0:bb348c97df44 1751 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
lypinator 0:bb348c97df44 1752 void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState);
lypinator 0:bb348c97df44 1753 /**
lypinator 0:bb348c97df44 1754 * @}
lypinator 0:bb348c97df44 1755 */
lypinator 0:bb348c97df44 1756
lypinator 0:bb348c97df44 1757 /**
lypinator 0:bb348c97df44 1758 * @}
lypinator 0:bb348c97df44 1759 */
lypinator 0:bb348c97df44 1760
lypinator 0:bb348c97df44 1761 /**
lypinator 0:bb348c97df44 1762 * @}
lypinator 0:bb348c97df44 1763 */
lypinator 0:bb348c97df44 1764
lypinator 0:bb348c97df44 1765 #ifdef __cplusplus
lypinator 0:bb348c97df44 1766 }
lypinator 0:bb348c97df44 1767 #endif
lypinator 0:bb348c97df44 1768
lypinator 0:bb348c97df44 1769 #endif /* __STM32F4xx_HAL_TIM_H */
lypinator 0:bb348c97df44 1770
lypinator 0:bb348c97df44 1771 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/