Thomas Lyp / DevLibMemoryController

Initial commit

Dependencies:   FastPWM

mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_tim.c@0:bb348c97df44, 2020-09-16 (annotated)

Committer:
lypinator
Date:
Wed Sep 16 01:11:49 2020 +0000
Revision:
0:bb348c97df44
Added PWM

Who changed what in which revision?

UserRevisionLine numberNew contents of line
lypinator 0:bb348c97df44 1 /**
lypinator 0:bb348c97df44 2 ******************************************************************************
lypinator 0:bb348c97df44 3 * @file stm32f4xx_hal_tim.c
lypinator 0:bb348c97df44 4 * @author MCD Application Team
lypinator 0:bb348c97df44 5 * @brief TIM HAL module driver.
lypinator 0:bb348c97df44 6 * This file provides firmware functions to manage the following
lypinator 0:bb348c97df44 7 * functionalities of the Timer (TIM) peripheral:
lypinator 0:bb348c97df44 8 * + Time Base Initialization
lypinator 0:bb348c97df44 9 * + Time Base Start
lypinator 0:bb348c97df44 10 * + Time Base Start Interruption
lypinator 0:bb348c97df44 11 * + Time Base Start DMA
lypinator 0:bb348c97df44 12 * + Time Output Compare/PWM Initialization
lypinator 0:bb348c97df44 13 * + Time Output Compare/PWM Channel Configuration
lypinator 0:bb348c97df44 14 * + Time Output Compare/PWM Start
lypinator 0:bb348c97df44 15 * + Time Output Compare/PWM Start Interruption
lypinator 0:bb348c97df44 16 * + Time Output Compare/PWM Start DMA
lypinator 0:bb348c97df44 17 * + Time Input Capture Initialization
lypinator 0:bb348c97df44 18 * + Time Input Capture Channel Configuration
lypinator 0:bb348c97df44 19 * + Time Input Capture Start
lypinator 0:bb348c97df44 20 * + Time Input Capture Start Interruption
lypinator 0:bb348c97df44 21 * + Time Input Capture Start DMA
lypinator 0:bb348c97df44 22 * + Time One Pulse Initialization
lypinator 0:bb348c97df44 23 * + Time One Pulse Channel Configuration
lypinator 0:bb348c97df44 24 * + Time One Pulse Start
lypinator 0:bb348c97df44 25 * + Time Encoder Interface Initialization
lypinator 0:bb348c97df44 26 * + Time Encoder Interface Start
lypinator 0:bb348c97df44 27 * + Time Encoder Interface Start Interruption
lypinator 0:bb348c97df44 28 * + Time Encoder Interface Start DMA
lypinator 0:bb348c97df44 29 * + Commutation Event configuration with Interruption and DMA
lypinator 0:bb348c97df44 30 * + Time OCRef clear configuration
lypinator 0:bb348c97df44 31 * + Time External Clock configuration
lypinator 0:bb348c97df44 32 @verbatim
lypinator 0:bb348c97df44 33 ==============================================================================
lypinator 0:bb348c97df44 34 ##### TIMER Generic features #####
lypinator 0:bb348c97df44 35 ==============================================================================
lypinator 0:bb348c97df44 36 [..] The Timer features include:
lypinator 0:bb348c97df44 37 (#) 16-bit up, down, up/down auto-reload counter.
lypinator 0:bb348c97df44 38 (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
lypinator 0:bb348c97df44 39 counter clock frequency either by any factor between 1 and 65536.
lypinator 0:bb348c97df44 40 (#) Up to 4 independent channels for:
lypinator 0:bb348c97df44 41 (++) Input Capture
lypinator 0:bb348c97df44 42 (++) Output Compare
lypinator 0:bb348c97df44 43 (++) PWM generation (Edge and Center-aligned Mode)
lypinator 0:bb348c97df44 44 (++) One-pulse mode output
lypinator 0:bb348c97df44 45
lypinator 0:bb348c97df44 46 ##### How to use this driver #####
lypinator 0:bb348c97df44 47 ==============================================================================
lypinator 0:bb348c97df44 48 [..]
lypinator 0:bb348c97df44 49 (#) Initialize the TIM low level resources by implementing the following functions
lypinator 0:bb348c97df44 50 depending from feature used :
lypinator 0:bb348c97df44 51 (++) Time Base : HAL_TIM_Base_MspInit()
lypinator 0:bb348c97df44 52 (++) Input Capture : HAL_TIM_IC_MspInit()
lypinator 0:bb348c97df44 53 (++) Output Compare : HAL_TIM_OC_MspInit()
lypinator 0:bb348c97df44 54 (++) PWM generation : HAL_TIM_PWM_MspInit()
lypinator 0:bb348c97df44 55 (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
lypinator 0:bb348c97df44 56 (++) Encoder mode output : HAL_TIM_Encoder_MspInit()
lypinator 0:bb348c97df44 57
lypinator 0:bb348c97df44 58 (#) Initialize the TIM low level resources :
lypinator 0:bb348c97df44 59 (##) Enable the TIM interface clock using __TIMx_CLK_ENABLE();
lypinator 0:bb348c97df44 60 (##) TIM pins configuration
lypinator 0:bb348c97df44 61 (+++) Enable the clock for the TIM GPIOs using the following function:
lypinator 0:bb348c97df44 62 __GPIOx_CLK_ENABLE();
lypinator 0:bb348c97df44 63 (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
lypinator 0:bb348c97df44 64
lypinator 0:bb348c97df44 65 (#) The external Clock can be configured, if needed (the default clock is the
lypinator 0:bb348c97df44 66 internal clock from the APBx), using the following function:
lypinator 0:bb348c97df44 67 HAL_TIM_ConfigClockSource, the clock configuration should be done before
lypinator 0:bb348c97df44 68 any start function.
lypinator 0:bb348c97df44 69
lypinator 0:bb348c97df44 70 (#) Configure the TIM in the desired functioning mode using one of the
lypinator 0:bb348c97df44 71 initialization function of this driver:
lypinator 0:bb348c97df44 72 (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
lypinator 0:bb348c97df44 73 (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
lypinator 0:bb348c97df44 74 Output Compare signal.
lypinator 0:bb348c97df44 75 (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
lypinator 0:bb348c97df44 76 PWM signal.
lypinator 0:bb348c97df44 77 (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
lypinator 0:bb348c97df44 78 external signal.
lypinator 0:bb348c97df44 79 (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
lypinator 0:bb348c97df44 80 in One Pulse Mode.
lypinator 0:bb348c97df44 81 (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
lypinator 0:bb348c97df44 82
lypinator 0:bb348c97df44 83 (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
lypinator 0:bb348c97df44 84 (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
lypinator 0:bb348c97df44 85 (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
lypinator 0:bb348c97df44 86 (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
lypinator 0:bb348c97df44 87 (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
lypinator 0:bb348c97df44 88 (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
lypinator 0:bb348c97df44 89 (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
lypinator 0:bb348c97df44 90
lypinator 0:bb348c97df44 91 (#) The DMA Burst is managed with the two following functions:
lypinator 0:bb348c97df44 92 HAL_TIM_DMABurst_WriteStart()
lypinator 0:bb348c97df44 93 HAL_TIM_DMABurst_ReadStart()
lypinator 0:bb348c97df44 94
lypinator 0:bb348c97df44 95 @endverbatim
lypinator 0:bb348c97df44 96 ******************************************************************************
lypinator 0:bb348c97df44 97 * @attention
lypinator 0:bb348c97df44 98 *
lypinator 0:bb348c97df44 99 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
lypinator 0:bb348c97df44 100 *
lypinator 0:bb348c97df44 101 * Redistribution and use in source and binary forms, with or without modification,
lypinator 0:bb348c97df44 102 * are permitted provided that the following conditions are met:
lypinator 0:bb348c97df44 103 * 1. Redistributions of source code must retain the above copyright notice,
lypinator 0:bb348c97df44 104 * this list of conditions and the following disclaimer.
lypinator 0:bb348c97df44 105 * 2. Redistributions in binary form must reproduce the above copyright notice,
lypinator 0:bb348c97df44 106 * this list of conditions and the following disclaimer in the documentation
lypinator 0:bb348c97df44 107 * and/or other materials provided with the distribution.
lypinator 0:bb348c97df44 108 * 3. Neither the name of STMicroelectronics nor the names of its contributors
lypinator 0:bb348c97df44 109 * may be used to endorse or promote products derived from this software
lypinator 0:bb348c97df44 110 * without specific prior written permission.
lypinator 0:bb348c97df44 111 *
lypinator 0:bb348c97df44 112 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
lypinator 0:bb348c97df44 113 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
lypinator 0:bb348c97df44 114 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
lypinator 0:bb348c97df44 115 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
lypinator 0:bb348c97df44 116 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
lypinator 0:bb348c97df44 117 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
lypinator 0:bb348c97df44 118 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
lypinator 0:bb348c97df44 119 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
lypinator 0:bb348c97df44 120 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
lypinator 0:bb348c97df44 121 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
lypinator 0:bb348c97df44 122 *
lypinator 0:bb348c97df44 123 ******************************************************************************
lypinator 0:bb348c97df44 124 */
lypinator 0:bb348c97df44 125
lypinator 0:bb348c97df44 126 /* Includes ------------------------------------------------------------------*/
lypinator 0:bb348c97df44 127 #include "stm32f4xx_hal.h"
lypinator 0:bb348c97df44 128
lypinator 0:bb348c97df44 129 /** @addtogroup STM32F4xx_HAL_Driver
lypinator 0:bb348c97df44 130 * @{
lypinator 0:bb348c97df44 131 */
lypinator 0:bb348c97df44 132
lypinator 0:bb348c97df44 133 /** @defgroup TIM TIM
lypinator 0:bb348c97df44 134 * @brief TIM HAL module driver
lypinator 0:bb348c97df44 135 * @{
lypinator 0:bb348c97df44 136 */
lypinator 0:bb348c97df44 137
lypinator 0:bb348c97df44 138 #ifdef HAL_TIM_MODULE_ENABLED
lypinator 0:bb348c97df44 139
lypinator 0:bb348c97df44 140 /* Private typedef -----------------------------------------------------------*/
lypinator 0:bb348c97df44 141 /* Private define ------------------------------------------------------------*/
lypinator 0:bb348c97df44 142 /* Private macro -------------------------------------------------------------*/
lypinator 0:bb348c97df44 143 /* Private variables ---------------------------------------------------------*/
lypinator 0:bb348c97df44 144 /** @addtogroup TIM_Private_Functions
lypinator 0:bb348c97df44 145 * @{
lypinator 0:bb348c97df44 146 */
lypinator 0:bb348c97df44 147 /* Private function prototypes -----------------------------------------------*/
lypinator 0:bb348c97df44 148 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
lypinator 0:bb348c97df44 149 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
lypinator 0:bb348c97df44 150 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
lypinator 0:bb348c97df44 151
lypinator 0:bb348c97df44 152 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
lypinator 0:bb348c97df44 153 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
lypinator 0:bb348c97df44 154 uint32_t TIM_ICFilter);
lypinator 0:bb348c97df44 155 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
lypinator 0:bb348c97df44 156 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
lypinator 0:bb348c97df44 157 uint32_t TIM_ICFilter);
lypinator 0:bb348c97df44 158 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
lypinator 0:bb348c97df44 159 uint32_t TIM_ICFilter);
lypinator 0:bb348c97df44 160
lypinator 0:bb348c97df44 161 static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
lypinator 0:bb348c97df44 162 uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
lypinator 0:bb348c97df44 163
lypinator 0:bb348c97df44 164 static void TIM_ITRx_SetConfig(TIM_TypeDef* TIMx, uint16_t TIM_ITRx);
lypinator 0:bb348c97df44 165 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
lypinator 0:bb348c97df44 166 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
lypinator 0:bb348c97df44 167 static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
lypinator 0:bb348c97df44 168 TIM_SlaveConfigTypeDef * sSlaveConfig);
lypinator 0:bb348c97df44 169 /**
lypinator 0:bb348c97df44 170 * @}
lypinator 0:bb348c97df44 171 */
lypinator 0:bb348c97df44 172
lypinator 0:bb348c97df44 173 /* Exported functions --------------------------------------------------------*/
lypinator 0:bb348c97df44 174 /** @defgroup TIM_Exported_Functions TIM Exported Functions
lypinator 0:bb348c97df44 175 * @{
lypinator 0:bb348c97df44 176 */
lypinator 0:bb348c97df44 177
lypinator 0:bb348c97df44 178 /** @defgroup TIM_Exported_Functions_Group1 Time Base functions
lypinator 0:bb348c97df44 179 * @brief Time Base functions
lypinator 0:bb348c97df44 180 *
lypinator 0:bb348c97df44 181 @verbatim
lypinator 0:bb348c97df44 182 ==============================================================================
lypinator 0:bb348c97df44 183 ##### Time Base functions #####
lypinator 0:bb348c97df44 184 ==============================================================================
lypinator 0:bb348c97df44 185 [..]
lypinator 0:bb348c97df44 186 This section provides functions allowing to:
lypinator 0:bb348c97df44 187 (+) Initialize and configure the TIM base.
lypinator 0:bb348c97df44 188 (+) De-initialize the TIM base.
lypinator 0:bb348c97df44 189 (+) Start the Time Base.
lypinator 0:bb348c97df44 190 (+) Stop the Time Base.
lypinator 0:bb348c97df44 191 (+) Start the Time Base and enable interrupt.
lypinator 0:bb348c97df44 192 (+) Stop the Time Base and disable interrupt.
lypinator 0:bb348c97df44 193 (+) Start the Time Base and enable DMA transfer.
lypinator 0:bb348c97df44 194 (+) Stop the Time Base and disable DMA transfer.
lypinator 0:bb348c97df44 195
lypinator 0:bb348c97df44 196 @endverbatim
lypinator 0:bb348c97df44 197 * @{
lypinator 0:bb348c97df44 198 */
lypinator 0:bb348c97df44 199 /**
lypinator 0:bb348c97df44 200 * @brief Initializes the TIM Time base Unit according to the specified
lypinator 0:bb348c97df44 201 * parameters in the TIM_HandleTypeDef and create the associated handle.
lypinator 0:bb348c97df44 202 * @param htim pointer to a TIM_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 203 * the configuration information for TIM module.
lypinator 0:bb348c97df44 204 * @retval HAL status
lypinator 0:bb348c97df44 205 */
lypinator 0:bb348c97df44 206 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
lypinator 0:bb348c97df44 207 {
lypinator 0:bb348c97df44 208 /* Check the TIM handle allocation */
lypinator 0:bb348c97df44 209 if(htim == NULL)
lypinator 0:bb348c97df44 210 {
lypinator 0:bb348c97df44 211 return HAL_ERROR;
lypinator 0:bb348c97df44 212 }
lypinator 0:bb348c97df44 213
lypinator 0:bb348c97df44 214 /* Check the parameters */
lypinator 0:bb348c97df44 215 assert_param(IS_TIM_INSTANCE(htim->Instance));
lypinator 0:bb348c97df44 216 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
lypinator 0:bb348c97df44 217 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
lypinator 0:bb348c97df44 218
lypinator 0:bb348c97df44 219 if(htim->State == HAL_TIM_STATE_RESET)
lypinator 0:bb348c97df44 220 {
lypinator 0:bb348c97df44 221 /* Allocate lock resource and initialize it */
lypinator 0:bb348c97df44 222 htim->Lock = HAL_UNLOCKED;
lypinator 0:bb348c97df44 223 /* Init the low level hardware : GPIO, CLOCK, NVIC */
lypinator 0:bb348c97df44 224 HAL_TIM_Base_MspInit(htim);
lypinator 0:bb348c97df44 225 }
lypinator 0:bb348c97df44 226
lypinator 0:bb348c97df44 227 /* Set the TIM state */
lypinator 0:bb348c97df44 228 htim->State= HAL_TIM_STATE_BUSY;
lypinator 0:bb348c97df44 229
lypinator 0:bb348c97df44 230 /* Set the Time Base configuration */
lypinator 0:bb348c97df44 231 TIM_Base_SetConfig(htim->Instance, &htim->Init);
lypinator 0:bb348c97df44 232
lypinator 0:bb348c97df44 233 /* Initialize the TIM state*/
lypinator 0:bb348c97df44 234 htim->State= HAL_TIM_STATE_READY;
lypinator 0:bb348c97df44 235
lypinator 0:bb348c97df44 236 return HAL_OK;
lypinator 0:bb348c97df44 237 }
lypinator 0:bb348c97df44 238
lypinator 0:bb348c97df44 239 /**
lypinator 0:bb348c97df44 240 * @brief DeInitializes the TIM Base peripheral
lypinator 0:bb348c97df44 241 * @param htim pointer to a TIM_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 242 * the configuration information for TIM module.
lypinator 0:bb348c97df44 243 * @retval HAL status
lypinator 0:bb348c97df44 244 */
lypinator 0:bb348c97df44 245 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
lypinator 0:bb348c97df44 246 {
lypinator 0:bb348c97df44 247 /* Check the parameters */
lypinator 0:bb348c97df44 248 assert_param(IS_TIM_INSTANCE(htim->Instance));
lypinator 0:bb348c97df44 249
lypinator 0:bb348c97df44 250 htim->State = HAL_TIM_STATE_BUSY;
lypinator 0:bb348c97df44 251
lypinator 0:bb348c97df44 252 /* Disable the TIM Peripheral Clock */
lypinator 0:bb348c97df44 253 __HAL_TIM_DISABLE(htim);
lypinator 0:bb348c97df44 254
lypinator 0:bb348c97df44 255 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
lypinator 0:bb348c97df44 256 HAL_TIM_Base_MspDeInit(htim);
lypinator 0:bb348c97df44 257
lypinator 0:bb348c97df44 258 /* Change TIM state */
lypinator 0:bb348c97df44 259 htim->State = HAL_TIM_STATE_RESET;
lypinator 0:bb348c97df44 260
lypinator 0:bb348c97df44 261 /* Release Lock */
lypinator 0:bb348c97df44 262 __HAL_UNLOCK(htim);
lypinator 0:bb348c97df44 263
lypinator 0:bb348c97df44 264 return HAL_OK;
lypinator 0:bb348c97df44 265 }
lypinator 0:bb348c97df44 266
lypinator 0:bb348c97df44 267 /**
lypinator 0:bb348c97df44 268 * @brief Initializes the TIM Base MSP.
lypinator 0:bb348c97df44 269 * @param htim pointer to a TIM_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 270 * the configuration information for TIM module.
lypinator 0:bb348c97df44 271 * @retval None
lypinator 0:bb348c97df44 272 */
lypinator 0:bb348c97df44 273 __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
lypinator 0:bb348c97df44 274 {
lypinator 0:bb348c97df44 275 /* Prevent unused argument(s) compilation warning */
lypinator 0:bb348c97df44 276 UNUSED(htim);
lypinator 0:bb348c97df44 277 /* NOTE : This function Should not be modified, when the callback is needed,
lypinator 0:bb348c97df44 278 the HAL_TIM_Base_MspInit could be implemented in the user file
lypinator 0:bb348c97df44 279 */
lypinator 0:bb348c97df44 280 }
lypinator 0:bb348c97df44 281
lypinator 0:bb348c97df44 282 /**
lypinator 0:bb348c97df44 283 * @brief DeInitializes TIM Base MSP.
lypinator 0:bb348c97df44 284 * @param htim pointer to a TIM_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 285 * the configuration information for TIM module.
lypinator 0:bb348c97df44 286 * @retval None
lypinator 0:bb348c97df44 287 */
lypinator 0:bb348c97df44 288 __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
lypinator 0:bb348c97df44 289 {
lypinator 0:bb348c97df44 290 /* Prevent unused argument(s) compilation warning */
lypinator 0:bb348c97df44 291 UNUSED(htim);
lypinator 0:bb348c97df44 292 /* NOTE : This function Should not be modified, when the callback is needed,
lypinator 0:bb348c97df44 293 the HAL_TIM_Base_MspDeInit could be implemented in the user file
lypinator 0:bb348c97df44 294 */
lypinator 0:bb348c97df44 295 }
lypinator 0:bb348c97df44 296
lypinator 0:bb348c97df44 297 /**
lypinator 0:bb348c97df44 298 * @brief Starts the TIM Base generation.
lypinator 0:bb348c97df44 299 * @param htim pointer to a TIM_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 300 * the configuration information for TIM module.
lypinator 0:bb348c97df44 301 * @retval HAL status
lypinator 0:bb348c97df44 302 */
lypinator 0:bb348c97df44 303 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
lypinator 0:bb348c97df44 304 {
lypinator 0:bb348c97df44 305 /* Check the parameters */
lypinator 0:bb348c97df44 306 assert_param(IS_TIM_INSTANCE(htim->Instance));
lypinator 0:bb348c97df44 307
lypinator 0:bb348c97df44 308 /* Set the TIM state */
lypinator 0:bb348c97df44 309 htim->State= HAL_TIM_STATE_BUSY;
lypinator 0:bb348c97df44 310
lypinator 0:bb348c97df44 311 /* Enable the Peripheral */
lypinator 0:bb348c97df44 312 __HAL_TIM_ENABLE(htim);
lypinator 0:bb348c97df44 313
lypinator 0:bb348c97df44 314 /* Change the TIM state*/
lypinator 0:bb348c97df44 315 htim->State= HAL_TIM_STATE_READY;
lypinator 0:bb348c97df44 316
lypinator 0:bb348c97df44 317 /* Return function status */
lypinator 0:bb348c97df44 318 return HAL_OK;
lypinator 0:bb348c97df44 319 }
lypinator 0:bb348c97df44 320
lypinator 0:bb348c97df44 321 /**
lypinator 0:bb348c97df44 322 * @brief Stops the TIM Base generation.
lypinator 0:bb348c97df44 323 * @param htim pointer to a TIM_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 324 * the configuration information for TIM module.
lypinator 0:bb348c97df44 325 * @retval HAL status
lypinator 0:bb348c97df44 326 */
lypinator 0:bb348c97df44 327 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
lypinator 0:bb348c97df44 328 {
lypinator 0:bb348c97df44 329 /* Check the parameters */
lypinator 0:bb348c97df44 330 assert_param(IS_TIM_INSTANCE(htim->Instance));
lypinator 0:bb348c97df44 331
lypinator 0:bb348c97df44 332 /* Set the TIM state */
lypinator 0:bb348c97df44 333 htim->State= HAL_TIM_STATE_BUSY;
lypinator 0:bb348c97df44 334
lypinator 0:bb348c97df44 335 /* Disable the Peripheral */
lypinator 0:bb348c97df44 336 __HAL_TIM_DISABLE(htim);
lypinator 0:bb348c97df44 337
lypinator 0:bb348c97df44 338 /* Change the TIM state*/
lypinator 0:bb348c97df44 339 htim->State= HAL_TIM_STATE_READY;
lypinator 0:bb348c97df44 340
lypinator 0:bb348c97df44 341 /* Return function status */
lypinator 0:bb348c97df44 342 return HAL_OK;
lypinator 0:bb348c97df44 343 }
lypinator 0:bb348c97df44 344
lypinator 0:bb348c97df44 345 /**
lypinator 0:bb348c97df44 346 * @brief Starts the TIM Base generation in interrupt mode.
lypinator 0:bb348c97df44 347 * @param htim pointer to a TIM_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 348 * the configuration information for TIM module.
lypinator 0:bb348c97df44 349 * @retval HAL status
lypinator 0:bb348c97df44 350 */
lypinator 0:bb348c97df44 351 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
lypinator 0:bb348c97df44 352 {
lypinator 0:bb348c97df44 353 /* Check the parameters */
lypinator 0:bb348c97df44 354 assert_param(IS_TIM_INSTANCE(htim->Instance));
lypinator 0:bb348c97df44 355
lypinator 0:bb348c97df44 356 /* Enable the TIM Update interrupt */
lypinator 0:bb348c97df44 357 __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
lypinator 0:bb348c97df44 358
lypinator 0:bb348c97df44 359 /* Enable the Peripheral */
lypinator 0:bb348c97df44 360 __HAL_TIM_ENABLE(htim);
lypinator 0:bb348c97df44 361
lypinator 0:bb348c97df44 362 /* Return function status */
lypinator 0:bb348c97df44 363 return HAL_OK;
lypinator 0:bb348c97df44 364 }
lypinator 0:bb348c97df44 365
lypinator 0:bb348c97df44 366 /**
lypinator 0:bb348c97df44 367 * @brief Stops the TIM Base generation in interrupt mode.
lypinator 0:bb348c97df44 368 * @param htim pointer to a TIM_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 369 * the configuration information for TIM module.
lypinator 0:bb348c97df44 370 * @retval HAL status
lypinator 0:bb348c97df44 371 */
lypinator 0:bb348c97df44 372 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
lypinator 0:bb348c97df44 373 {
lypinator 0:bb348c97df44 374 /* Check the parameters */
lypinator 0:bb348c97df44 375 assert_param(IS_TIM_INSTANCE(htim->Instance));
lypinator 0:bb348c97df44 376 /* Disable the TIM Update interrupt */
lypinator 0:bb348c97df44 377 __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
lypinator 0:bb348c97df44 378
lypinator 0:bb348c97df44 379 /* Disable the Peripheral */
lypinator 0:bb348c97df44 380 __HAL_TIM_DISABLE(htim);
lypinator 0:bb348c97df44 381
lypinator 0:bb348c97df44 382 /* Return function status */
lypinator 0:bb348c97df44 383 return HAL_OK;
lypinator 0:bb348c97df44 384 }
lypinator 0:bb348c97df44 385
lypinator 0:bb348c97df44 386 /**
lypinator 0:bb348c97df44 387 * @brief Starts the TIM Base generation in DMA mode.
lypinator 0:bb348c97df44 388 * @param htim pointer to a TIM_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 389 * the configuration information for TIM module.
lypinator 0:bb348c97df44 390 * @param pData The source Buffer address.
lypinator 0:bb348c97df44 391 * @param Length The length of data to be transferred from memory to peripheral.
lypinator 0:bb348c97df44 392 * @retval HAL status
lypinator 0:bb348c97df44 393 */
lypinator 0:bb348c97df44 394 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
lypinator 0:bb348c97df44 395 {
lypinator 0:bb348c97df44 396 /* Check the parameters */
lypinator 0:bb348c97df44 397 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
lypinator 0:bb348c97df44 398
lypinator 0:bb348c97df44 399 if((htim->State == HAL_TIM_STATE_BUSY))
lypinator 0:bb348c97df44 400 {
lypinator 0:bb348c97df44 401 return HAL_BUSY;
lypinator 0:bb348c97df44 402 }
lypinator 0:bb348c97df44 403 else if((htim->State == HAL_TIM_STATE_READY))
lypinator 0:bb348c97df44 404 {
lypinator 0:bb348c97df44 405 if((pData == 0U) && (Length > 0))
lypinator 0:bb348c97df44 406 {
lypinator 0:bb348c97df44 407 return HAL_ERROR;
lypinator 0:bb348c97df44 408 }
lypinator 0:bb348c97df44 409 else
lypinator 0:bb348c97df44 410 {
lypinator 0:bb348c97df44 411 htim->State = HAL_TIM_STATE_BUSY;
lypinator 0:bb348c97df44 412 }
lypinator 0:bb348c97df44 413 }
lypinator 0:bb348c97df44 414 /* Set the DMA Period elapsed callback */
lypinator 0:bb348c97df44 415 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
lypinator 0:bb348c97df44 416
lypinator 0:bb348c97df44 417 /* Set the DMA error callback */
lypinator 0:bb348c97df44 418 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
lypinator 0:bb348c97df44 419
lypinator 0:bb348c97df44 420 /* Enable the DMA Stream */
lypinator 0:bb348c97df44 421 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length);
lypinator 0:bb348c97df44 422
lypinator 0:bb348c97df44 423 /* Enable the TIM Update DMA request */
lypinator 0:bb348c97df44 424 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
lypinator 0:bb348c97df44 425
lypinator 0:bb348c97df44 426 /* Enable the Peripheral */
lypinator 0:bb348c97df44 427 __HAL_TIM_ENABLE(htim);
lypinator 0:bb348c97df44 428
lypinator 0:bb348c97df44 429 /* Return function status */
lypinator 0:bb348c97df44 430 return HAL_OK;
lypinator 0:bb348c97df44 431 }
lypinator 0:bb348c97df44 432
lypinator 0:bb348c97df44 433 /**
lypinator 0:bb348c97df44 434 * @brief Stops the TIM Base generation in DMA mode.
lypinator 0:bb348c97df44 435 * @param htim pointer to a TIM_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 436 * the configuration information for TIM module.
lypinator 0:bb348c97df44 437 * @retval HAL status
lypinator 0:bb348c97df44 438 */
lypinator 0:bb348c97df44 439 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
lypinator 0:bb348c97df44 440 {
lypinator 0:bb348c97df44 441 /* Check the parameters */
lypinator 0:bb348c97df44 442 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
lypinator 0:bb348c97df44 443
lypinator 0:bb348c97df44 444 /* Disable the TIM Update DMA request */
lypinator 0:bb348c97df44 445 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
lypinator 0:bb348c97df44 446
lypinator 0:bb348c97df44 447 /* Disable the Peripheral */
lypinator 0:bb348c97df44 448 __HAL_TIM_DISABLE(htim);
lypinator 0:bb348c97df44 449
lypinator 0:bb348c97df44 450 /* Change the htim state */
lypinator 0:bb348c97df44 451 htim->State = HAL_TIM_STATE_READY;
lypinator 0:bb348c97df44 452
lypinator 0:bb348c97df44 453 /* Return function status */
lypinator 0:bb348c97df44 454 return HAL_OK;
lypinator 0:bb348c97df44 455 }
lypinator 0:bb348c97df44 456 /**
lypinator 0:bb348c97df44 457 * @}
lypinator 0:bb348c97df44 458 */
lypinator 0:bb348c97df44 459
lypinator 0:bb348c97df44 460 /** @defgroup TIM_Exported_Functions_Group2 Time Output Compare functions
lypinator 0:bb348c97df44 461 * @brief Time Output Compare functions
lypinator 0:bb348c97df44 462 *
lypinator 0:bb348c97df44 463 @verbatim
lypinator 0:bb348c97df44 464 ==============================================================================
lypinator 0:bb348c97df44 465 ##### Time Output Compare functions #####
lypinator 0:bb348c97df44 466 ==============================================================================
lypinator 0:bb348c97df44 467 [..]
lypinator 0:bb348c97df44 468 This section provides functions allowing to:
lypinator 0:bb348c97df44 469 (+) Initialize and configure the TIM Output Compare.
lypinator 0:bb348c97df44 470 (+) De-initialize the TIM Output Compare.
lypinator 0:bb348c97df44 471 (+) Start the Time Output Compare.
lypinator 0:bb348c97df44 472 (+) Stop the Time Output Compare.
lypinator 0:bb348c97df44 473 (+) Start the Time Output Compare and enable interrupt.
lypinator 0:bb348c97df44 474 (+) Stop the Time Output Compare and disable interrupt.
lypinator 0:bb348c97df44 475 (+) Start the Time Output Compare and enable DMA transfer.
lypinator 0:bb348c97df44 476 (+) Stop the Time Output Compare and disable DMA transfer.
lypinator 0:bb348c97df44 477
lypinator 0:bb348c97df44 478 @endverbatim
lypinator 0:bb348c97df44 479 * @{
lypinator 0:bb348c97df44 480 */
lypinator 0:bb348c97df44 481 /**
lypinator 0:bb348c97df44 482 * @brief Initializes the TIM Output Compare according to the specified
lypinator 0:bb348c97df44 483 * parameters in the TIM_HandleTypeDef and create the associated handle.
lypinator 0:bb348c97df44 484 * @param htim pointer to a TIM_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 485 * the configuration information for TIM module.
lypinator 0:bb348c97df44 486 * @retval HAL status
lypinator 0:bb348c97df44 487 */
lypinator 0:bb348c97df44 488 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim)
lypinator 0:bb348c97df44 489 {
lypinator 0:bb348c97df44 490 /* Check the TIM handle allocation */
lypinator 0:bb348c97df44 491 if(htim == NULL)
lypinator 0:bb348c97df44 492 {
lypinator 0:bb348c97df44 493 return HAL_ERROR;
lypinator 0:bb348c97df44 494 }
lypinator 0:bb348c97df44 495
lypinator 0:bb348c97df44 496 /* Check the parameters */
lypinator 0:bb348c97df44 497 assert_param(IS_TIM_INSTANCE(htim->Instance));
lypinator 0:bb348c97df44 498 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
lypinator 0:bb348c97df44 499 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
lypinator 0:bb348c97df44 500
lypinator 0:bb348c97df44 501 if(htim->State == HAL_TIM_STATE_RESET)
lypinator 0:bb348c97df44 502 {
lypinator 0:bb348c97df44 503 /* Allocate lock resource and initialize it */
lypinator 0:bb348c97df44 504 htim->Lock = HAL_UNLOCKED;
lypinator 0:bb348c97df44 505 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
lypinator 0:bb348c97df44 506 HAL_TIM_OC_MspInit(htim);
lypinator 0:bb348c97df44 507 }
lypinator 0:bb348c97df44 508
lypinator 0:bb348c97df44 509 /* Set the TIM state */
lypinator 0:bb348c97df44 510 htim->State= HAL_TIM_STATE_BUSY;
lypinator 0:bb348c97df44 511
lypinator 0:bb348c97df44 512 /* Init the base time for the Output Compare */
lypinator 0:bb348c97df44 513 TIM_Base_SetConfig(htim->Instance, &htim->Init);
lypinator 0:bb348c97df44 514
lypinator 0:bb348c97df44 515 /* Initialize the TIM state*/
lypinator 0:bb348c97df44 516 htim->State= HAL_TIM_STATE_READY;
lypinator 0:bb348c97df44 517
lypinator 0:bb348c97df44 518 return HAL_OK;
lypinator 0:bb348c97df44 519 }
lypinator 0:bb348c97df44 520
lypinator 0:bb348c97df44 521 /**
lypinator 0:bb348c97df44 522 * @brief DeInitializes the TIM peripheral
lypinator 0:bb348c97df44 523 * @param htim pointer to a TIM_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 524 * the configuration information for TIM module.
lypinator 0:bb348c97df44 525 * @retval HAL status
lypinator 0:bb348c97df44 526 */
lypinator 0:bb348c97df44 527 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
lypinator 0:bb348c97df44 528 {
lypinator 0:bb348c97df44 529 /* Check the parameters */
lypinator 0:bb348c97df44 530 assert_param(IS_TIM_INSTANCE(htim->Instance));
lypinator 0:bb348c97df44 531
lypinator 0:bb348c97df44 532 htim->State = HAL_TIM_STATE_BUSY;
lypinator 0:bb348c97df44 533
lypinator 0:bb348c97df44 534 /* Disable the TIM Peripheral Clock */
lypinator 0:bb348c97df44 535 __HAL_TIM_DISABLE(htim);
lypinator 0:bb348c97df44 536
lypinator 0:bb348c97df44 537 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
lypinator 0:bb348c97df44 538 HAL_TIM_OC_MspDeInit(htim);
lypinator 0:bb348c97df44 539
lypinator 0:bb348c97df44 540 /* Change TIM state */
lypinator 0:bb348c97df44 541 htim->State = HAL_TIM_STATE_RESET;
lypinator 0:bb348c97df44 542
lypinator 0:bb348c97df44 543 /* Release Lock */
lypinator 0:bb348c97df44 544 __HAL_UNLOCK(htim);
lypinator 0:bb348c97df44 545
lypinator 0:bb348c97df44 546 return HAL_OK;
lypinator 0:bb348c97df44 547 }
lypinator 0:bb348c97df44 548
lypinator 0:bb348c97df44 549 /**
lypinator 0:bb348c97df44 550 * @brief Initializes the TIM Output Compare MSP.
lypinator 0:bb348c97df44 551 * @param htim pointer to a TIM_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 552 * the configuration information for TIM module.
lypinator 0:bb348c97df44 553 * @retval None
lypinator 0:bb348c97df44 554 */
lypinator 0:bb348c97df44 555 __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
lypinator 0:bb348c97df44 556 {
lypinator 0:bb348c97df44 557 /* Prevent unused argument(s) compilation warning */
lypinator 0:bb348c97df44 558 UNUSED(htim);
lypinator 0:bb348c97df44 559 /* NOTE : This function Should not be modified, when the callback is needed,
lypinator 0:bb348c97df44 560 the HAL_TIM_OC_MspInit could be implemented in the user file
lypinator 0:bb348c97df44 561 */
lypinator 0:bb348c97df44 562 }
lypinator 0:bb348c97df44 563
lypinator 0:bb348c97df44 564 /**
lypinator 0:bb348c97df44 565 * @brief DeInitializes TIM Output Compare MSP.
lypinator 0:bb348c97df44 566 * @param htim pointer to a TIM_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 567 * the configuration information for TIM module.
lypinator 0:bb348c97df44 568 * @retval None
lypinator 0:bb348c97df44 569 */
lypinator 0:bb348c97df44 570 __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
lypinator 0:bb348c97df44 571 {
lypinator 0:bb348c97df44 572 /* Prevent unused argument(s) compilation warning */
lypinator 0:bb348c97df44 573 UNUSED(htim);
lypinator 0:bb348c97df44 574 /* NOTE : This function Should not be modified, when the callback is needed,
lypinator 0:bb348c97df44 575 the HAL_TIM_OC_MspDeInit could be implemented in the user file
lypinator 0:bb348c97df44 576 */
lypinator 0:bb348c97df44 577 }
lypinator 0:bb348c97df44 578
lypinator 0:bb348c97df44 579 /**
lypinator 0:bb348c97df44 580 * @brief Starts the TIM Output Compare signal generation.
lypinator 0:bb348c97df44 581 * @param htim pointer to a TIM_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 582 * the configuration information for TIM module.
lypinator 0:bb348c97df44 583 * @param Channel TIM Channel to be enabled.
lypinator 0:bb348c97df44 584 * This parameter can be one of the following values:
lypinator 0:bb348c97df44 585 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
lypinator 0:bb348c97df44 586 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
lypinator 0:bb348c97df44 587 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
lypinator 0:bb348c97df44 588 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
lypinator 0:bb348c97df44 589 * @retval HAL status
lypinator 0:bb348c97df44 590 */
lypinator 0:bb348c97df44 591 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
lypinator 0:bb348c97df44 592 {
lypinator 0:bb348c97df44 593 /* Check the parameters */
lypinator 0:bb348c97df44 594 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
lypinator 0:bb348c97df44 595
lypinator 0:bb348c97df44 596 /* Enable the Output compare channel */
lypinator 0:bb348c97df44 597 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
lypinator 0:bb348c97df44 598
lypinator 0:bb348c97df44 599 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
lypinator 0:bb348c97df44 600 {
lypinator 0:bb348c97df44 601 /* Enable the main output */
lypinator 0:bb348c97df44 602 __HAL_TIM_MOE_ENABLE(htim);
lypinator 0:bb348c97df44 603 }
lypinator 0:bb348c97df44 604
lypinator 0:bb348c97df44 605 /* Enable the Peripheral */
lypinator 0:bb348c97df44 606 __HAL_TIM_ENABLE(htim);
lypinator 0:bb348c97df44 607
lypinator 0:bb348c97df44 608 /* Return function status */
lypinator 0:bb348c97df44 609 return HAL_OK;
lypinator 0:bb348c97df44 610 }
lypinator 0:bb348c97df44 611
lypinator 0:bb348c97df44 612 /**
lypinator 0:bb348c97df44 613 * @brief Stops the TIM Output Compare signal generation.
lypinator 0:bb348c97df44 614 * @param htim pointer to a TIM_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 615 * the configuration information for TIM module.
lypinator 0:bb348c97df44 616 * @param Channel TIM Channel to be disabled.
lypinator 0:bb348c97df44 617 * This parameter can be one of the following values:
lypinator 0:bb348c97df44 618 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
lypinator 0:bb348c97df44 619 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
lypinator 0:bb348c97df44 620 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
lypinator 0:bb348c97df44 621 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
lypinator 0:bb348c97df44 622 * @retval HAL status
lypinator 0:bb348c97df44 623 */
lypinator 0:bb348c97df44 624 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
lypinator 0:bb348c97df44 625 {
lypinator 0:bb348c97df44 626 /* Check the parameters */
lypinator 0:bb348c97df44 627 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
lypinator 0:bb348c97df44 628
lypinator 0:bb348c97df44 629 /* Disable the Output compare channel */
lypinator 0:bb348c97df44 630 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
lypinator 0:bb348c97df44 631
lypinator 0:bb348c97df44 632 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
lypinator 0:bb348c97df44 633 {
lypinator 0:bb348c97df44 634 /* Disable the Main Output */
lypinator 0:bb348c97df44 635 __HAL_TIM_MOE_DISABLE(htim);
lypinator 0:bb348c97df44 636 }
lypinator 0:bb348c97df44 637
lypinator 0:bb348c97df44 638 /* Disable the Peripheral */
lypinator 0:bb348c97df44 639 __HAL_TIM_DISABLE(htim);
lypinator 0:bb348c97df44 640
lypinator 0:bb348c97df44 641 /* Return function status */
lypinator 0:bb348c97df44 642 return HAL_OK;
lypinator 0:bb348c97df44 643 }
lypinator 0:bb348c97df44 644
lypinator 0:bb348c97df44 645 /**
lypinator 0:bb348c97df44 646 * @brief Starts the TIM Output Compare signal generation in interrupt mode.
lypinator 0:bb348c97df44 647 * @param htim pointer to a TIM_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 648 * the configuration information for TIM module.
lypinator 0:bb348c97df44 649 * @param Channel TIM Channel to be enabled.
lypinator 0:bb348c97df44 650 * This parameter can be one of the following values:
lypinator 0:bb348c97df44 651 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
lypinator 0:bb348c97df44 652 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
lypinator 0:bb348c97df44 653 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
lypinator 0:bb348c97df44 654 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
lypinator 0:bb348c97df44 655 * @retval HAL status
lypinator 0:bb348c97df44 656 */
lypinator 0:bb348c97df44 657 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
lypinator 0:bb348c97df44 658 {
lypinator 0:bb348c97df44 659 /* Check the parameters */
lypinator 0:bb348c97df44 660 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
lypinator 0:bb348c97df44 661
lypinator 0:bb348c97df44 662 switch (Channel)
lypinator 0:bb348c97df44 663 {
lypinator 0:bb348c97df44 664 case TIM_CHANNEL_1:
lypinator 0:bb348c97df44 665 {
lypinator 0:bb348c97df44 666 /* Enable the TIM Capture/Compare 1 interrupt */
lypinator 0:bb348c97df44 667 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
lypinator 0:bb348c97df44 668 }
lypinator 0:bb348c97df44 669 break;
lypinator 0:bb348c97df44 670
lypinator 0:bb348c97df44 671 case TIM_CHANNEL_2:
lypinator 0:bb348c97df44 672 {
lypinator 0:bb348c97df44 673 /* Enable the TIM Capture/Compare 2 interrupt */
lypinator 0:bb348c97df44 674 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
lypinator 0:bb348c97df44 675 }
lypinator 0:bb348c97df44 676 break;
lypinator 0:bb348c97df44 677
lypinator 0:bb348c97df44 678 case TIM_CHANNEL_3:
lypinator 0:bb348c97df44 679 {
lypinator 0:bb348c97df44 680 /* Enable the TIM Capture/Compare 3 interrupt */
lypinator 0:bb348c97df44 681 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
lypinator 0:bb348c97df44 682 }
lypinator 0:bb348c97df44 683 break;
lypinator 0:bb348c97df44 684
lypinator 0:bb348c97df44 685 case TIM_CHANNEL_4:
lypinator 0:bb348c97df44 686 {
lypinator 0:bb348c97df44 687 /* Enable the TIM Capture/Compare 4 interrupt */
lypinator 0:bb348c97df44 688 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
lypinator 0:bb348c97df44 689 }
lypinator 0:bb348c97df44 690 break;
lypinator 0:bb348c97df44 691
lypinator 0:bb348c97df44 692 default:
lypinator 0:bb348c97df44 693 break;
lypinator 0:bb348c97df44 694 }
lypinator 0:bb348c97df44 695
lypinator 0:bb348c97df44 696 /* Enable the Output compare channel */
lypinator 0:bb348c97df44 697 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
lypinator 0:bb348c97df44 698
lypinator 0:bb348c97df44 699 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
lypinator 0:bb348c97df44 700 {
lypinator 0:bb348c97df44 701 /* Enable the main output */
lypinator 0:bb348c97df44 702 __HAL_TIM_MOE_ENABLE(htim);
lypinator 0:bb348c97df44 703 }
lypinator 0:bb348c97df44 704
lypinator 0:bb348c97df44 705 /* Enable the Peripheral */
lypinator 0:bb348c97df44 706 __HAL_TIM_ENABLE(htim);
lypinator 0:bb348c97df44 707
lypinator 0:bb348c97df44 708 /* Return function status */
lypinator 0:bb348c97df44 709 return HAL_OK;
lypinator 0:bb348c97df44 710 }
lypinator 0:bb348c97df44 711
lypinator 0:bb348c97df44 712 /**
lypinator 0:bb348c97df44 713 * @brief Stops the TIM Output Compare signal generation in interrupt mode.
lypinator 0:bb348c97df44 714 * @param htim pointer to a TIM_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 715 * the configuration information for TIM module.
lypinator 0:bb348c97df44 716 * @param Channel TIM Channel to be disabled.
lypinator 0:bb348c97df44 717 * This parameter can be one of the following values:
lypinator 0:bb348c97df44 718 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
lypinator 0:bb348c97df44 719 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
lypinator 0:bb348c97df44 720 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
lypinator 0:bb348c97df44 721 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
lypinator 0:bb348c97df44 722 * @retval HAL status
lypinator 0:bb348c97df44 723 */
lypinator 0:bb348c97df44 724 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
lypinator 0:bb348c97df44 725 {
lypinator 0:bb348c97df44 726 /* Check the parameters */
lypinator 0:bb348c97df44 727 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
lypinator 0:bb348c97df44 728
lypinator 0:bb348c97df44 729 switch (Channel)
lypinator 0:bb348c97df44 730 {
lypinator 0:bb348c97df44 731 case TIM_CHANNEL_1:
lypinator 0:bb348c97df44 732 {
lypinator 0:bb348c97df44 733 /* Disable the TIM Capture/Compare 1 interrupt */
lypinator 0:bb348c97df44 734 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
lypinator 0:bb348c97df44 735 }
lypinator 0:bb348c97df44 736 break;
lypinator 0:bb348c97df44 737
lypinator 0:bb348c97df44 738 case TIM_CHANNEL_2:
lypinator 0:bb348c97df44 739 {
lypinator 0:bb348c97df44 740 /* Disable the TIM Capture/Compare 2 interrupt */
lypinator 0:bb348c97df44 741 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
lypinator 0:bb348c97df44 742 }
lypinator 0:bb348c97df44 743 break;
lypinator 0:bb348c97df44 744
lypinator 0:bb348c97df44 745 case TIM_CHANNEL_3:
lypinator 0:bb348c97df44 746 {
lypinator 0:bb348c97df44 747 /* Disable the TIM Capture/Compare 3 interrupt */
lypinator 0:bb348c97df44 748 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
lypinator 0:bb348c97df44 749 }
lypinator 0:bb348c97df44 750 break;
lypinator 0:bb348c97df44 751
lypinator 0:bb348c97df44 752 case TIM_CHANNEL_4:
lypinator 0:bb348c97df44 753 {
lypinator 0:bb348c97df44 754 /* Disable the TIM Capture/Compare 4 interrupt */
lypinator 0:bb348c97df44 755 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
lypinator 0:bb348c97df44 756 }
lypinator 0:bb348c97df44 757 break;
lypinator 0:bb348c97df44 758
lypinator 0:bb348c97df44 759 default:
lypinator 0:bb348c97df44 760 break;
lypinator 0:bb348c97df44 761 }
lypinator 0:bb348c97df44 762
lypinator 0:bb348c97df44 763 /* Disable the Output compare channel */
lypinator 0:bb348c97df44 764 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
lypinator 0:bb348c97df44 765
lypinator 0:bb348c97df44 766 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
lypinator 0:bb348c97df44 767 {
lypinator 0:bb348c97df44 768 /* Disable the Main Output */
lypinator 0:bb348c97df44 769 __HAL_TIM_MOE_DISABLE(htim);
lypinator 0:bb348c97df44 770 }
lypinator 0:bb348c97df44 771
lypinator 0:bb348c97df44 772 /* Disable the Peripheral */
lypinator 0:bb348c97df44 773 __HAL_TIM_DISABLE(htim);
lypinator 0:bb348c97df44 774
lypinator 0:bb348c97df44 775 /* Return function status */
lypinator 0:bb348c97df44 776 return HAL_OK;
lypinator 0:bb348c97df44 777 }
lypinator 0:bb348c97df44 778
lypinator 0:bb348c97df44 779 /**
lypinator 0:bb348c97df44 780 * @brief Starts the TIM Output Compare signal generation in DMA mode.
lypinator 0:bb348c97df44 781 * @param htim pointer to a TIM_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 782 * the configuration information for TIM module.
lypinator 0:bb348c97df44 783 * @param Channel TIM Channel to be enabled.
lypinator 0:bb348c97df44 784 * This parameter can be one of the following values:
lypinator 0:bb348c97df44 785 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
lypinator 0:bb348c97df44 786 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
lypinator 0:bb348c97df44 787 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
lypinator 0:bb348c97df44 788 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
lypinator 0:bb348c97df44 789 * @param pData The source Buffer address.
lypinator 0:bb348c97df44 790 * @param Length The length of data to be transferred from memory to TIM peripheral
lypinator 0:bb348c97df44 791 * @retval HAL status
lypinator 0:bb348c97df44 792 */
lypinator 0:bb348c97df44 793 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
lypinator 0:bb348c97df44 794 {
lypinator 0:bb348c97df44 795 /* Check the parameters */
lypinator 0:bb348c97df44 796 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
lypinator 0:bb348c97df44 797
lypinator 0:bb348c97df44 798 if((htim->State == HAL_TIM_STATE_BUSY))
lypinator 0:bb348c97df44 799 {
lypinator 0:bb348c97df44 800 return HAL_BUSY;
lypinator 0:bb348c97df44 801 }
lypinator 0:bb348c97df44 802 else if((htim->State == HAL_TIM_STATE_READY))
lypinator 0:bb348c97df44 803 {
lypinator 0:bb348c97df44 804 if(((uint32_t)pData == 0U) && (Length > 0))
lypinator 0:bb348c97df44 805 {
lypinator 0:bb348c97df44 806 return HAL_ERROR;
lypinator 0:bb348c97df44 807 }
lypinator 0:bb348c97df44 808 else
lypinator 0:bb348c97df44 809 {
lypinator 0:bb348c97df44 810 htim->State = HAL_TIM_STATE_BUSY;
lypinator 0:bb348c97df44 811 }
lypinator 0:bb348c97df44 812 }
lypinator 0:bb348c97df44 813 switch (Channel)
lypinator 0:bb348c97df44 814 {
lypinator 0:bb348c97df44 815 case TIM_CHANNEL_1:
lypinator 0:bb348c97df44 816 {
lypinator 0:bb348c97df44 817 /* Set the DMA Period elapsed callback */
lypinator 0:bb348c97df44 818 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
lypinator 0:bb348c97df44 819
lypinator 0:bb348c97df44 820 /* Set the DMA error callback */
lypinator 0:bb348c97df44 821 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
lypinator 0:bb348c97df44 822
lypinator 0:bb348c97df44 823 /* Enable the DMA Stream */
lypinator 0:bb348c97df44 824 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
lypinator 0:bb348c97df44 825
lypinator 0:bb348c97df44 826 /* Enable the TIM Capture/Compare 1 DMA request */
lypinator 0:bb348c97df44 827 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
lypinator 0:bb348c97df44 828 }
lypinator 0:bb348c97df44 829 break;
lypinator 0:bb348c97df44 830
lypinator 0:bb348c97df44 831 case TIM_CHANNEL_2:
lypinator 0:bb348c97df44 832 {
lypinator 0:bb348c97df44 833 /* Set the DMA Period elapsed callback */
lypinator 0:bb348c97df44 834 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
lypinator 0:bb348c97df44 835
lypinator 0:bb348c97df44 836 /* Set the DMA error callback */
lypinator 0:bb348c97df44 837 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
lypinator 0:bb348c97df44 838
lypinator 0:bb348c97df44 839 /* Enable the DMA Stream */
lypinator 0:bb348c97df44 840 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
lypinator 0:bb348c97df44 841
lypinator 0:bb348c97df44 842 /* Enable the TIM Capture/Compare 2 DMA request */
lypinator 0:bb348c97df44 843 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
lypinator 0:bb348c97df44 844 }
lypinator 0:bb348c97df44 845 break;
lypinator 0:bb348c97df44 846
lypinator 0:bb348c97df44 847 case TIM_CHANNEL_3:
lypinator 0:bb348c97df44 848 {
lypinator 0:bb348c97df44 849 /* Set the DMA Period elapsed callback */
lypinator 0:bb348c97df44 850 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
lypinator 0:bb348c97df44 851
lypinator 0:bb348c97df44 852 /* Set the DMA error callback */
lypinator 0:bb348c97df44 853 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
lypinator 0:bb348c97df44 854
lypinator 0:bb348c97df44 855 /* Enable the DMA Stream */
lypinator 0:bb348c97df44 856 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
lypinator 0:bb348c97df44 857
lypinator 0:bb348c97df44 858 /* Enable the TIM Capture/Compare 3 DMA request */
lypinator 0:bb348c97df44 859 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
lypinator 0:bb348c97df44 860 }
lypinator 0:bb348c97df44 861 break;
lypinator 0:bb348c97df44 862
lypinator 0:bb348c97df44 863 case TIM_CHANNEL_4:
lypinator 0:bb348c97df44 864 {
lypinator 0:bb348c97df44 865 /* Set the DMA Period elapsed callback */
lypinator 0:bb348c97df44 866 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
lypinator 0:bb348c97df44 867
lypinator 0:bb348c97df44 868 /* Set the DMA error callback */
lypinator 0:bb348c97df44 869 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
lypinator 0:bb348c97df44 870
lypinator 0:bb348c97df44 871 /* Enable the DMA Stream */
lypinator 0:bb348c97df44 872 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
lypinator 0:bb348c97df44 873
lypinator 0:bb348c97df44 874 /* Enable the TIM Capture/Compare 4 DMA request */
lypinator 0:bb348c97df44 875 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
lypinator 0:bb348c97df44 876 }
lypinator 0:bb348c97df44 877 break;
lypinator 0:bb348c97df44 878
lypinator 0:bb348c97df44 879 default:
lypinator 0:bb348c97df44 880 break;
lypinator 0:bb348c97df44 881 }
lypinator 0:bb348c97df44 882
lypinator 0:bb348c97df44 883 /* Enable the Output compare channel */
lypinator 0:bb348c97df44 884 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
lypinator 0:bb348c97df44 885
lypinator 0:bb348c97df44 886 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
lypinator 0:bb348c97df44 887 {
lypinator 0:bb348c97df44 888 /* Enable the main output */
lypinator 0:bb348c97df44 889 __HAL_TIM_MOE_ENABLE(htim);
lypinator 0:bb348c97df44 890 }
lypinator 0:bb348c97df44 891
lypinator 0:bb348c97df44 892 /* Enable the Peripheral */
lypinator 0:bb348c97df44 893 __HAL_TIM_ENABLE(htim);
lypinator 0:bb348c97df44 894
lypinator 0:bb348c97df44 895 /* Return function status */
lypinator 0:bb348c97df44 896 return HAL_OK;
lypinator 0:bb348c97df44 897 }
lypinator 0:bb348c97df44 898
lypinator 0:bb348c97df44 899 /**
lypinator 0:bb348c97df44 900 * @brief Stops the TIM Output Compare signal generation in DMA mode.
lypinator 0:bb348c97df44 901 * @param htim pointer to a TIM_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 902 * the configuration information for TIM module.
lypinator 0:bb348c97df44 903 * @param Channel TIM Channel to be disabled.
lypinator 0:bb348c97df44 904 * This parameter can be one of the following values:
lypinator 0:bb348c97df44 905 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
lypinator 0:bb348c97df44 906 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
lypinator 0:bb348c97df44 907 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
lypinator 0:bb348c97df44 908 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
lypinator 0:bb348c97df44 909 * @retval HAL status
lypinator 0:bb348c97df44 910 */
lypinator 0:bb348c97df44 911 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
lypinator 0:bb348c97df44 912 {
lypinator 0:bb348c97df44 913 /* Check the parameters */
lypinator 0:bb348c97df44 914 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
lypinator 0:bb348c97df44 915
lypinator 0:bb348c97df44 916 switch (Channel)
lypinator 0:bb348c97df44 917 {
lypinator 0:bb348c97df44 918 case TIM_CHANNEL_1:
lypinator 0:bb348c97df44 919 {
lypinator 0:bb348c97df44 920 /* Disable the TIM Capture/Compare 1 DMA request */
lypinator 0:bb348c97df44 921 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
lypinator 0:bb348c97df44 922 }
lypinator 0:bb348c97df44 923 break;
lypinator 0:bb348c97df44 924
lypinator 0:bb348c97df44 925 case TIM_CHANNEL_2:
lypinator 0:bb348c97df44 926 {
lypinator 0:bb348c97df44 927 /* Disable the TIM Capture/Compare 2 DMA request */
lypinator 0:bb348c97df44 928 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
lypinator 0:bb348c97df44 929 }
lypinator 0:bb348c97df44 930 break;
lypinator 0:bb348c97df44 931
lypinator 0:bb348c97df44 932 case TIM_CHANNEL_3:
lypinator 0:bb348c97df44 933 {
lypinator 0:bb348c97df44 934 /* Disable the TIM Capture/Compare 3 DMA request */
lypinator 0:bb348c97df44 935 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
lypinator 0:bb348c97df44 936 }
lypinator 0:bb348c97df44 937 break;
lypinator 0:bb348c97df44 938
lypinator 0:bb348c97df44 939 case TIM_CHANNEL_4:
lypinator 0:bb348c97df44 940 {
lypinator 0:bb348c97df44 941 /* Disable the TIM Capture/Compare 4 interrupt */
lypinator 0:bb348c97df44 942 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
lypinator 0:bb348c97df44 943 }
lypinator 0:bb348c97df44 944 break;
lypinator 0:bb348c97df44 945
lypinator 0:bb348c97df44 946 default:
lypinator 0:bb348c97df44 947 break;
lypinator 0:bb348c97df44 948 }
lypinator 0:bb348c97df44 949
lypinator 0:bb348c97df44 950 /* Disable the Output compare channel */
lypinator 0:bb348c97df44 951 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
lypinator 0:bb348c97df44 952
lypinator 0:bb348c97df44 953 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
lypinator 0:bb348c97df44 954 {
lypinator 0:bb348c97df44 955 /* Disable the Main Output */
lypinator 0:bb348c97df44 956 __HAL_TIM_MOE_DISABLE(htim);
lypinator 0:bb348c97df44 957 }
lypinator 0:bb348c97df44 958
lypinator 0:bb348c97df44 959 /* Disable the Peripheral */
lypinator 0:bb348c97df44 960 __HAL_TIM_DISABLE(htim);
lypinator 0:bb348c97df44 961
lypinator 0:bb348c97df44 962 /* Change the htim state */
lypinator 0:bb348c97df44 963 htim->State = HAL_TIM_STATE_READY;
lypinator 0:bb348c97df44 964
lypinator 0:bb348c97df44 965 /* Return function status */
lypinator 0:bb348c97df44 966 return HAL_OK;
lypinator 0:bb348c97df44 967 }
lypinator 0:bb348c97df44 968 /**
lypinator 0:bb348c97df44 969 * @}
lypinator 0:bb348c97df44 970 */
lypinator 0:bb348c97df44 971
lypinator 0:bb348c97df44 972 /** @defgroup TIM_Exported_Functions_Group3 Time PWM functions
lypinator 0:bb348c97df44 973 * @brief Time PWM functions
lypinator 0:bb348c97df44 974 *
lypinator 0:bb348c97df44 975 @verbatim
lypinator 0:bb348c97df44 976 ==============================================================================
lypinator 0:bb348c97df44 977 ##### Time PWM functions #####
lypinator 0:bb348c97df44 978 ==============================================================================
lypinator 0:bb348c97df44 979 [..]
lypinator 0:bb348c97df44 980 This section provides functions allowing to:
lypinator 0:bb348c97df44 981 (+) Initialize and configure the TIM OPWM.
lypinator 0:bb348c97df44 982 (+) De-initialize the TIM PWM.
lypinator 0:bb348c97df44 983 (+) Start the Time PWM.
lypinator 0:bb348c97df44 984 (+) Stop the Time PWM.
lypinator 0:bb348c97df44 985 (+) Start the Time PWM and enable interrupt.
lypinator 0:bb348c97df44 986 (+) Stop the Time PWM and disable interrupt.
lypinator 0:bb348c97df44 987 (+) Start the Time PWM and enable DMA transfer.
lypinator 0:bb348c97df44 988 (+) Stop the Time PWM and disable DMA transfer.
lypinator 0:bb348c97df44 989
lypinator 0:bb348c97df44 990 @endverbatim
lypinator 0:bb348c97df44 991 * @{
lypinator 0:bb348c97df44 992 */
lypinator 0:bb348c97df44 993 /**
lypinator 0:bb348c97df44 994 * @brief Initializes the TIM PWM Time Base according to the specified
lypinator 0:bb348c97df44 995 * parameters in the TIM_HandleTypeDef and create the associated handle.
lypinator 0:bb348c97df44 996 * @param htim pointer to a TIM_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 997 * the configuration information for TIM module.
lypinator 0:bb348c97df44 998 * @retval HAL status
lypinator 0:bb348c97df44 999 */
lypinator 0:bb348c97df44 1000 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
lypinator 0:bb348c97df44 1001 {
lypinator 0:bb348c97df44 1002 /* Check the TIM handle allocation */
lypinator 0:bb348c97df44 1003 if(htim == NULL)
lypinator 0:bb348c97df44 1004 {
lypinator 0:bb348c97df44 1005 return HAL_ERROR;
lypinator 0:bb348c97df44 1006 }
lypinator 0:bb348c97df44 1007
lypinator 0:bb348c97df44 1008 /* Check the parameters */
lypinator 0:bb348c97df44 1009 assert_param(IS_TIM_INSTANCE(htim->Instance));
lypinator 0:bb348c97df44 1010 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
lypinator 0:bb348c97df44 1011 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
lypinator 0:bb348c97df44 1012
lypinator 0:bb348c97df44 1013 if(htim->State == HAL_TIM_STATE_RESET)
lypinator 0:bb348c97df44 1014 {
lypinator 0:bb348c97df44 1015 /* Allocate lock resource and initialize it */
lypinator 0:bb348c97df44 1016 htim->Lock = HAL_UNLOCKED;
lypinator 0:bb348c97df44 1017 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
lypinator 0:bb348c97df44 1018 HAL_TIM_PWM_MspInit(htim);
lypinator 0:bb348c97df44 1019 }
lypinator 0:bb348c97df44 1020
lypinator 0:bb348c97df44 1021 /* Set the TIM state */
lypinator 0:bb348c97df44 1022 htim->State= HAL_TIM_STATE_BUSY;
lypinator 0:bb348c97df44 1023
lypinator 0:bb348c97df44 1024 /* Init the base time for the PWM */
lypinator 0:bb348c97df44 1025 TIM_Base_SetConfig(htim->Instance, &htim->Init);
lypinator 0:bb348c97df44 1026
lypinator 0:bb348c97df44 1027 /* Initialize the TIM state*/
lypinator 0:bb348c97df44 1028 htim->State= HAL_TIM_STATE_READY;
lypinator 0:bb348c97df44 1029
lypinator 0:bb348c97df44 1030 return HAL_OK;
lypinator 0:bb348c97df44 1031 }
lypinator 0:bb348c97df44 1032
lypinator 0:bb348c97df44 1033 /**
lypinator 0:bb348c97df44 1034 * @brief DeInitializes the TIM peripheral
lypinator 0:bb348c97df44 1035 * @param htim pointer to a TIM_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 1036 * the configuration information for TIM module.
lypinator 0:bb348c97df44 1037 * @retval HAL status
lypinator 0:bb348c97df44 1038 */
lypinator 0:bb348c97df44 1039 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
lypinator 0:bb348c97df44 1040 {
lypinator 0:bb348c97df44 1041 /* Check the parameters */
lypinator 0:bb348c97df44 1042 assert_param(IS_TIM_INSTANCE(htim->Instance));
lypinator 0:bb348c97df44 1043
lypinator 0:bb348c97df44 1044 htim->State = HAL_TIM_STATE_BUSY;
lypinator 0:bb348c97df44 1045
lypinator 0:bb348c97df44 1046 /* Disable the TIM Peripheral Clock */
lypinator 0:bb348c97df44 1047 __HAL_TIM_DISABLE(htim);
lypinator 0:bb348c97df44 1048
lypinator 0:bb348c97df44 1049 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
lypinator 0:bb348c97df44 1050 HAL_TIM_PWM_MspDeInit(htim);
lypinator 0:bb348c97df44 1051
lypinator 0:bb348c97df44 1052 /* Change TIM state */
lypinator 0:bb348c97df44 1053 htim->State = HAL_TIM_STATE_RESET;
lypinator 0:bb348c97df44 1054
lypinator 0:bb348c97df44 1055 /* Release Lock */
lypinator 0:bb348c97df44 1056 __HAL_UNLOCK(htim);
lypinator 0:bb348c97df44 1057
lypinator 0:bb348c97df44 1058 return HAL_OK;
lypinator 0:bb348c97df44 1059 }
lypinator 0:bb348c97df44 1060
lypinator 0:bb348c97df44 1061 /**
lypinator 0:bb348c97df44 1062 * @brief Initializes the TIM PWM MSP.
lypinator 0:bb348c97df44 1063 * @param htim pointer to a TIM_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 1064 * the configuration information for TIM module.
lypinator 0:bb348c97df44 1065 * @retval None
lypinator 0:bb348c97df44 1066 */
lypinator 0:bb348c97df44 1067 __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
lypinator 0:bb348c97df44 1068 {
lypinator 0:bb348c97df44 1069 /* Prevent unused argument(s) compilation warning */
lypinator 0:bb348c97df44 1070 UNUSED(htim);
lypinator 0:bb348c97df44 1071 /* NOTE : This function Should not be modified, when the callback is needed,
lypinator 0:bb348c97df44 1072 the HAL_TIM_PWM_MspInit could be implemented in the user file
lypinator 0:bb348c97df44 1073 */
lypinator 0:bb348c97df44 1074 }
lypinator 0:bb348c97df44 1075
lypinator 0:bb348c97df44 1076 /**
lypinator 0:bb348c97df44 1077 * @brief DeInitializes TIM PWM MSP.
lypinator 0:bb348c97df44 1078 * @param htim pointer to a TIM_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 1079 * the configuration information for TIM module.
lypinator 0:bb348c97df44 1080 * @retval None
lypinator 0:bb348c97df44 1081 */
lypinator 0:bb348c97df44 1082 __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
lypinator 0:bb348c97df44 1083 {
lypinator 0:bb348c97df44 1084 /* Prevent unused argument(s) compilation warning */
lypinator 0:bb348c97df44 1085 UNUSED(htim);
lypinator 0:bb348c97df44 1086 /* NOTE : This function Should not be modified, when the callback is needed,
lypinator 0:bb348c97df44 1087 the HAL_TIM_PWM_MspDeInit could be implemented in the user file
lypinator 0:bb348c97df44 1088 */
lypinator 0:bb348c97df44 1089 }
lypinator 0:bb348c97df44 1090
lypinator 0:bb348c97df44 1091 /**
lypinator 0:bb348c97df44 1092 * @brief Starts the PWM signal generation.
lypinator 0:bb348c97df44 1093 * @param htim pointer to a TIM_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 1094 * the configuration information for TIM module.
lypinator 0:bb348c97df44 1095 * @param Channel TIM Channels to be enabled.
lypinator 0:bb348c97df44 1096 * This parameter can be one of the following values:
lypinator 0:bb348c97df44 1097 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
lypinator 0:bb348c97df44 1098 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
lypinator 0:bb348c97df44 1099 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
lypinator 0:bb348c97df44 1100 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
lypinator 0:bb348c97df44 1101 * @retval HAL status
lypinator 0:bb348c97df44 1102 */
lypinator 0:bb348c97df44 1103 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
lypinator 0:bb348c97df44 1104 {
lypinator 0:bb348c97df44 1105 /* Check the parameters */
lypinator 0:bb348c97df44 1106 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
lypinator 0:bb348c97df44 1107
lypinator 0:bb348c97df44 1108 /* Enable the Capture compare channel */
lypinator 0:bb348c97df44 1109 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
lypinator 0:bb348c97df44 1110
lypinator 0:bb348c97df44 1111 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
lypinator 0:bb348c97df44 1112 {
lypinator 0:bb348c97df44 1113 /* Enable the main output */
lypinator 0:bb348c97df44 1114 __HAL_TIM_MOE_ENABLE(htim);
lypinator 0:bb348c97df44 1115 }
lypinator 0:bb348c97df44 1116
lypinator 0:bb348c97df44 1117 /* Enable the Peripheral */
lypinator 0:bb348c97df44 1118 __HAL_TIM_ENABLE(htim);
lypinator 0:bb348c97df44 1119
lypinator 0:bb348c97df44 1120 /* Return function status */
lypinator 0:bb348c97df44 1121 return HAL_OK;
lypinator 0:bb348c97df44 1122 }
lypinator 0:bb348c97df44 1123
lypinator 0:bb348c97df44 1124 /**
lypinator 0:bb348c97df44 1125 * @brief Stops the PWM signal generation.
lypinator 0:bb348c97df44 1126 * @param htim pointer to a TIM_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 1127 * the configuration information for TIM module.
lypinator 0:bb348c97df44 1128 * @param Channel TIM Channels to be disabled.
lypinator 0:bb348c97df44 1129 * This parameter can be one of the following values:
lypinator 0:bb348c97df44 1130 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
lypinator 0:bb348c97df44 1131 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
lypinator 0:bb348c97df44 1132 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
lypinator 0:bb348c97df44 1133 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
lypinator 0:bb348c97df44 1134 * @retval HAL status
lypinator 0:bb348c97df44 1135 */
lypinator 0:bb348c97df44 1136 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
lypinator 0:bb348c97df44 1137 {
lypinator 0:bb348c97df44 1138 /* Check the parameters */
lypinator 0:bb348c97df44 1139 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
lypinator 0:bb348c97df44 1140
lypinator 0:bb348c97df44 1141 /* Disable the Capture compare channel */
lypinator 0:bb348c97df44 1142 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
lypinator 0:bb348c97df44 1143
lypinator 0:bb348c97df44 1144 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
lypinator 0:bb348c97df44 1145 {
lypinator 0:bb348c97df44 1146 /* Disable the Main Output */
lypinator 0:bb348c97df44 1147 __HAL_TIM_MOE_DISABLE(htim);
lypinator 0:bb348c97df44 1148 }
lypinator 0:bb348c97df44 1149
lypinator 0:bb348c97df44 1150 /* Disable the Peripheral */
lypinator 0:bb348c97df44 1151 __HAL_TIM_DISABLE(htim);
lypinator 0:bb348c97df44 1152
lypinator 0:bb348c97df44 1153 /* Change the htim state */
lypinator 0:bb348c97df44 1154 htim->State = HAL_TIM_STATE_READY;
lypinator 0:bb348c97df44 1155
lypinator 0:bb348c97df44 1156 /* Return function status */
lypinator 0:bb348c97df44 1157 return HAL_OK;
lypinator 0:bb348c97df44 1158 }
lypinator 0:bb348c97df44 1159
lypinator 0:bb348c97df44 1160 /**
lypinator 0:bb348c97df44 1161 * @brief Starts the PWM signal generation in interrupt mode.
lypinator 0:bb348c97df44 1162 * @param htim pointer to a TIM_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 1163 * the configuration information for TIM module.
lypinator 0:bb348c97df44 1164 * @param Channel TIM Channel to be enabled.
lypinator 0:bb348c97df44 1165 * This parameter can be one of the following values:
lypinator 0:bb348c97df44 1166 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
lypinator 0:bb348c97df44 1167 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
lypinator 0:bb348c97df44 1168 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
lypinator 0:bb348c97df44 1169 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
lypinator 0:bb348c97df44 1170 * @retval HAL status
lypinator 0:bb348c97df44 1171 */
lypinator 0:bb348c97df44 1172 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
lypinator 0:bb348c97df44 1173 {
lypinator 0:bb348c97df44 1174 /* Check the parameters */
lypinator 0:bb348c97df44 1175 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
lypinator 0:bb348c97df44 1176
lypinator 0:bb348c97df44 1177 switch (Channel)
lypinator 0:bb348c97df44 1178 {
lypinator 0:bb348c97df44 1179 case TIM_CHANNEL_1:
lypinator 0:bb348c97df44 1180 {
lypinator 0:bb348c97df44 1181 /* Enable the TIM Capture/Compare 1 interrupt */
lypinator 0:bb348c97df44 1182 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
lypinator 0:bb348c97df44 1183 }
lypinator 0:bb348c97df44 1184 break;
lypinator 0:bb348c97df44 1185
lypinator 0:bb348c97df44 1186 case TIM_CHANNEL_2:
lypinator 0:bb348c97df44 1187 {
lypinator 0:bb348c97df44 1188 /* Enable the TIM Capture/Compare 2 interrupt */
lypinator 0:bb348c97df44 1189 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
lypinator 0:bb348c97df44 1190 }
lypinator 0:bb348c97df44 1191 break;
lypinator 0:bb348c97df44 1192
lypinator 0:bb348c97df44 1193 case TIM_CHANNEL_3:
lypinator 0:bb348c97df44 1194 {
lypinator 0:bb348c97df44 1195 /* Enable the TIM Capture/Compare 3 interrupt */
lypinator 0:bb348c97df44 1196 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
lypinator 0:bb348c97df44 1197 }
lypinator 0:bb348c97df44 1198 break;
lypinator 0:bb348c97df44 1199
lypinator 0:bb348c97df44 1200 case TIM_CHANNEL_4:
lypinator 0:bb348c97df44 1201 {
lypinator 0:bb348c97df44 1202 /* Enable the TIM Capture/Compare 4 interrupt */
lypinator 0:bb348c97df44 1203 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
lypinator 0:bb348c97df44 1204 }
lypinator 0:bb348c97df44 1205 break;
lypinator 0:bb348c97df44 1206
lypinator 0:bb348c97df44 1207 default:
lypinator 0:bb348c97df44 1208 break;
lypinator 0:bb348c97df44 1209 }
lypinator 0:bb348c97df44 1210
lypinator 0:bb348c97df44 1211 /* Enable the Capture compare channel */
lypinator 0:bb348c97df44 1212 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
lypinator 0:bb348c97df44 1213
lypinator 0:bb348c97df44 1214 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
lypinator 0:bb348c97df44 1215 {
lypinator 0:bb348c97df44 1216 /* Enable the main output */
lypinator 0:bb348c97df44 1217 __HAL_TIM_MOE_ENABLE(htim);
lypinator 0:bb348c97df44 1218 }
lypinator 0:bb348c97df44 1219
lypinator 0:bb348c97df44 1220 /* Enable the Peripheral */
lypinator 0:bb348c97df44 1221 __HAL_TIM_ENABLE(htim);
lypinator 0:bb348c97df44 1222
lypinator 0:bb348c97df44 1223 /* Return function status */
lypinator 0:bb348c97df44 1224 return HAL_OK;
lypinator 0:bb348c97df44 1225 }
lypinator 0:bb348c97df44 1226
lypinator 0:bb348c97df44 1227 /**
lypinator 0:bb348c97df44 1228 * @brief Stops the PWM signal generation in interrupt mode.
lypinator 0:bb348c97df44 1229 * @param htim pointer to a TIM_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 1230 * the configuration information for TIM module.
lypinator 0:bb348c97df44 1231 * @param Channel TIM Channels to be disabled.
lypinator 0:bb348c97df44 1232 * This parameter can be one of the following values:
lypinator 0:bb348c97df44 1233 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
lypinator 0:bb348c97df44 1234 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
lypinator 0:bb348c97df44 1235 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
lypinator 0:bb348c97df44 1236 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
lypinator 0:bb348c97df44 1237 * @retval HAL status
lypinator 0:bb348c97df44 1238 */
lypinator 0:bb348c97df44 1239 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
lypinator 0:bb348c97df44 1240 {
lypinator 0:bb348c97df44 1241 /* Check the parameters */
lypinator 0:bb348c97df44 1242 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
lypinator 0:bb348c97df44 1243
lypinator 0:bb348c97df44 1244 switch (Channel)
lypinator 0:bb348c97df44 1245 {
lypinator 0:bb348c97df44 1246 case TIM_CHANNEL_1:
lypinator 0:bb348c97df44 1247 {
lypinator 0:bb348c97df44 1248 /* Disable the TIM Capture/Compare 1 interrupt */
lypinator 0:bb348c97df44 1249 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
lypinator 0:bb348c97df44 1250 }
lypinator 0:bb348c97df44 1251 break;
lypinator 0:bb348c97df44 1252
lypinator 0:bb348c97df44 1253 case TIM_CHANNEL_2:
lypinator 0:bb348c97df44 1254 {
lypinator 0:bb348c97df44 1255 /* Disable the TIM Capture/Compare 2 interrupt */
lypinator 0:bb348c97df44 1256 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
lypinator 0:bb348c97df44 1257 }
lypinator 0:bb348c97df44 1258 break;
lypinator 0:bb348c97df44 1259
lypinator 0:bb348c97df44 1260 case TIM_CHANNEL_3:
lypinator 0:bb348c97df44 1261 {
lypinator 0:bb348c97df44 1262 /* Disable the TIM Capture/Compare 3 interrupt */
lypinator 0:bb348c97df44 1263 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
lypinator 0:bb348c97df44 1264 }
lypinator 0:bb348c97df44 1265 break;
lypinator 0:bb348c97df44 1266
lypinator 0:bb348c97df44 1267 case TIM_CHANNEL_4:
lypinator 0:bb348c97df44 1268 {
lypinator 0:bb348c97df44 1269 /* Disable the TIM Capture/Compare 4 interrupt */
lypinator 0:bb348c97df44 1270 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
lypinator 0:bb348c97df44 1271 }
lypinator 0:bb348c97df44 1272 break;
lypinator 0:bb348c97df44 1273
lypinator 0:bb348c97df44 1274 default:
lypinator 0:bb348c97df44 1275 break;
lypinator 0:bb348c97df44 1276 }
lypinator 0:bb348c97df44 1277
lypinator 0:bb348c97df44 1278 /* Disable the Capture compare channel */
lypinator 0:bb348c97df44 1279 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
lypinator 0:bb348c97df44 1280
lypinator 0:bb348c97df44 1281 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
lypinator 0:bb348c97df44 1282 {
lypinator 0:bb348c97df44 1283 /* Disable the Main Output */
lypinator 0:bb348c97df44 1284 __HAL_TIM_MOE_DISABLE(htim);
lypinator 0:bb348c97df44 1285 }
lypinator 0:bb348c97df44 1286
lypinator 0:bb348c97df44 1287 /* Disable the Peripheral */
lypinator 0:bb348c97df44 1288 __HAL_TIM_DISABLE(htim);
lypinator 0:bb348c97df44 1289
lypinator 0:bb348c97df44 1290 /* Return function status */
lypinator 0:bb348c97df44 1291 return HAL_OK;
lypinator 0:bb348c97df44 1292 }
lypinator 0:bb348c97df44 1293
lypinator 0:bb348c97df44 1294 /**
lypinator 0:bb348c97df44 1295 * @brief Starts the TIM PWM signal generation in DMA mode.
lypinator 0:bb348c97df44 1296 * @param htim pointer to a TIM_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 1297 * the configuration information for TIM module.
lypinator 0:bb348c97df44 1298 * @param Channel TIM Channels to be enabled.
lypinator 0:bb348c97df44 1299 * This parameter can be one of the following values:
lypinator 0:bb348c97df44 1300 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
lypinator 0:bb348c97df44 1301 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
lypinator 0:bb348c97df44 1302 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
lypinator 0:bb348c97df44 1303 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
lypinator 0:bb348c97df44 1304 * @param pData The source Buffer address.
lypinator 0:bb348c97df44 1305 * @param Length The length of data to be transferred from memory to TIM peripheral
lypinator 0:bb348c97df44 1306 * @retval HAL status
lypinator 0:bb348c97df44 1307 */
lypinator 0:bb348c97df44 1308 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
lypinator 0:bb348c97df44 1309 {
lypinator 0:bb348c97df44 1310 /* Check the parameters */
lypinator 0:bb348c97df44 1311 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
lypinator 0:bb348c97df44 1312
lypinator 0:bb348c97df44 1313 if((htim->State == HAL_TIM_STATE_BUSY))
lypinator 0:bb348c97df44 1314 {
lypinator 0:bb348c97df44 1315 return HAL_BUSY;
lypinator 0:bb348c97df44 1316 }
lypinator 0:bb348c97df44 1317 else if((htim->State == HAL_TIM_STATE_READY))
lypinator 0:bb348c97df44 1318 {
lypinator 0:bb348c97df44 1319 if(((uint32_t)pData == 0U) && (Length > 0))
lypinator 0:bb348c97df44 1320 {
lypinator 0:bb348c97df44 1321 return HAL_ERROR;
lypinator 0:bb348c97df44 1322 }
lypinator 0:bb348c97df44 1323 else
lypinator 0:bb348c97df44 1324 {
lypinator 0:bb348c97df44 1325 htim->State = HAL_TIM_STATE_BUSY;
lypinator 0:bb348c97df44 1326 }
lypinator 0:bb348c97df44 1327 }
lypinator 0:bb348c97df44 1328 switch (Channel)
lypinator 0:bb348c97df44 1329 {
lypinator 0:bb348c97df44 1330 case TIM_CHANNEL_1:
lypinator 0:bb348c97df44 1331 {
lypinator 0:bb348c97df44 1332 /* Set the DMA Period elapsed callback */
lypinator 0:bb348c97df44 1333 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
lypinator 0:bb348c97df44 1334
lypinator 0:bb348c97df44 1335 /* Set the DMA error callback */
lypinator 0:bb348c97df44 1336 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
lypinator 0:bb348c97df44 1337
lypinator 0:bb348c97df44 1338 /* Enable the DMA Stream */
lypinator 0:bb348c97df44 1339 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
lypinator 0:bb348c97df44 1340
lypinator 0:bb348c97df44 1341 /* Enable the TIM Capture/Compare 1 DMA request */
lypinator 0:bb348c97df44 1342 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
lypinator 0:bb348c97df44 1343 }
lypinator 0:bb348c97df44 1344 break;
lypinator 0:bb348c97df44 1345
lypinator 0:bb348c97df44 1346 case TIM_CHANNEL_2:
lypinator 0:bb348c97df44 1347 {
lypinator 0:bb348c97df44 1348 /* Set the DMA Period elapsed callback */
lypinator 0:bb348c97df44 1349 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
lypinator 0:bb348c97df44 1350
lypinator 0:bb348c97df44 1351 /* Set the DMA error callback */
lypinator 0:bb348c97df44 1352 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
lypinator 0:bb348c97df44 1353
lypinator 0:bb348c97df44 1354 /* Enable the DMA Stream */
lypinator 0:bb348c97df44 1355 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
lypinator 0:bb348c97df44 1356
lypinator 0:bb348c97df44 1357 /* Enable the TIM Capture/Compare 2 DMA request */
lypinator 0:bb348c97df44 1358 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
lypinator 0:bb348c97df44 1359 }
lypinator 0:bb348c97df44 1360 break;
lypinator 0:bb348c97df44 1361
lypinator 0:bb348c97df44 1362 case TIM_CHANNEL_3:
lypinator 0:bb348c97df44 1363 {
lypinator 0:bb348c97df44 1364 /* Set the DMA Period elapsed callback */
lypinator 0:bb348c97df44 1365 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
lypinator 0:bb348c97df44 1366
lypinator 0:bb348c97df44 1367 /* Set the DMA error callback */
lypinator 0:bb348c97df44 1368 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
lypinator 0:bb348c97df44 1369
lypinator 0:bb348c97df44 1370 /* Enable the DMA Stream */
lypinator 0:bb348c97df44 1371 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
lypinator 0:bb348c97df44 1372
lypinator 0:bb348c97df44 1373 /* Enable the TIM Output Capture/Compare 3 request */
lypinator 0:bb348c97df44 1374 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
lypinator 0:bb348c97df44 1375 }
lypinator 0:bb348c97df44 1376 break;
lypinator 0:bb348c97df44 1377
lypinator 0:bb348c97df44 1378 case TIM_CHANNEL_4:
lypinator 0:bb348c97df44 1379 {
lypinator 0:bb348c97df44 1380 /* Set the DMA Period elapsed callback */
lypinator 0:bb348c97df44 1381 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
lypinator 0:bb348c97df44 1382
lypinator 0:bb348c97df44 1383 /* Set the DMA error callback */
lypinator 0:bb348c97df44 1384 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
lypinator 0:bb348c97df44 1385
lypinator 0:bb348c97df44 1386 /* Enable the DMA Stream */
lypinator 0:bb348c97df44 1387 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
lypinator 0:bb348c97df44 1388
lypinator 0:bb348c97df44 1389 /* Enable the TIM Capture/Compare 4 DMA request */
lypinator 0:bb348c97df44 1390 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
lypinator 0:bb348c97df44 1391 }
lypinator 0:bb348c97df44 1392 break;
lypinator 0:bb348c97df44 1393
lypinator 0:bb348c97df44 1394 default:
lypinator 0:bb348c97df44 1395 break;
lypinator 0:bb348c97df44 1396 }
lypinator 0:bb348c97df44 1397
lypinator 0:bb348c97df44 1398 /* Enable the Capture compare channel */
lypinator 0:bb348c97df44 1399 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
lypinator 0:bb348c97df44 1400
lypinator 0:bb348c97df44 1401 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
lypinator 0:bb348c97df44 1402 {
lypinator 0:bb348c97df44 1403 /* Enable the main output */
lypinator 0:bb348c97df44 1404 __HAL_TIM_MOE_ENABLE(htim);
lypinator 0:bb348c97df44 1405 }
lypinator 0:bb348c97df44 1406
lypinator 0:bb348c97df44 1407 /* Enable the Peripheral */
lypinator 0:bb348c97df44 1408 __HAL_TIM_ENABLE(htim);
lypinator 0:bb348c97df44 1409
lypinator 0:bb348c97df44 1410 /* Return function status */
lypinator 0:bb348c97df44 1411 return HAL_OK;
lypinator 0:bb348c97df44 1412 }
lypinator 0:bb348c97df44 1413
lypinator 0:bb348c97df44 1414 /**
lypinator 0:bb348c97df44 1415 * @brief Stops the TIM PWM signal generation in DMA mode.
lypinator 0:bb348c97df44 1416 * @param htim pointer to a TIM_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 1417 * the configuration information for TIM module.
lypinator 0:bb348c97df44 1418 * @param Channel TIM Channels to be disabled.
lypinator 0:bb348c97df44 1419 * This parameter can be one of the following values:
lypinator 0:bb348c97df44 1420 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
lypinator 0:bb348c97df44 1421 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
lypinator 0:bb348c97df44 1422 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
lypinator 0:bb348c97df44 1423 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
lypinator 0:bb348c97df44 1424 * @retval HAL status
lypinator 0:bb348c97df44 1425 */
lypinator 0:bb348c97df44 1426 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
lypinator 0:bb348c97df44 1427 {
lypinator 0:bb348c97df44 1428 /* Check the parameters */
lypinator 0:bb348c97df44 1429 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
lypinator 0:bb348c97df44 1430
lypinator 0:bb348c97df44 1431 switch (Channel)
lypinator 0:bb348c97df44 1432 {
lypinator 0:bb348c97df44 1433 case TIM_CHANNEL_1:
lypinator 0:bb348c97df44 1434 {
lypinator 0:bb348c97df44 1435 /* Disable the TIM Capture/Compare 1 DMA request */
lypinator 0:bb348c97df44 1436 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
lypinator 0:bb348c97df44 1437 }
lypinator 0:bb348c97df44 1438 break;
lypinator 0:bb348c97df44 1439
lypinator 0:bb348c97df44 1440 case TIM_CHANNEL_2:
lypinator 0:bb348c97df44 1441 {
lypinator 0:bb348c97df44 1442 /* Disable the TIM Capture/Compare 2 DMA request */
lypinator 0:bb348c97df44 1443 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
lypinator 0:bb348c97df44 1444 }
lypinator 0:bb348c97df44 1445 break;
lypinator 0:bb348c97df44 1446
lypinator 0:bb348c97df44 1447 case TIM_CHANNEL_3:
lypinator 0:bb348c97df44 1448 {
lypinator 0:bb348c97df44 1449 /* Disable the TIM Capture/Compare 3 DMA request */
lypinator 0:bb348c97df44 1450 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
lypinator 0:bb348c97df44 1451 }
lypinator 0:bb348c97df44 1452 break;
lypinator 0:bb348c97df44 1453
lypinator 0:bb348c97df44 1454 case TIM_CHANNEL_4:
lypinator 0:bb348c97df44 1455 {
lypinator 0:bb348c97df44 1456 /* Disable the TIM Capture/Compare 4 interrupt */
lypinator 0:bb348c97df44 1457 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
lypinator 0:bb348c97df44 1458 }
lypinator 0:bb348c97df44 1459 break;
lypinator 0:bb348c97df44 1460
lypinator 0:bb348c97df44 1461 default:
lypinator 0:bb348c97df44 1462 break;
lypinator 0:bb348c97df44 1463 }
lypinator 0:bb348c97df44 1464
lypinator 0:bb348c97df44 1465 /* Disable the Capture compare channel */
lypinator 0:bb348c97df44 1466 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
lypinator 0:bb348c97df44 1467
lypinator 0:bb348c97df44 1468 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
lypinator 0:bb348c97df44 1469 {
lypinator 0:bb348c97df44 1470 /* Disable the Main Output */
lypinator 0:bb348c97df44 1471 __HAL_TIM_MOE_DISABLE(htim);
lypinator 0:bb348c97df44 1472 }
lypinator 0:bb348c97df44 1473
lypinator 0:bb348c97df44 1474 /* Disable the Peripheral */
lypinator 0:bb348c97df44 1475 __HAL_TIM_DISABLE(htim);
lypinator 0:bb348c97df44 1476
lypinator 0:bb348c97df44 1477 /* Change the htim state */
lypinator 0:bb348c97df44 1478 htim->State = HAL_TIM_STATE_READY;
lypinator 0:bb348c97df44 1479
lypinator 0:bb348c97df44 1480 /* Return function status */
lypinator 0:bb348c97df44 1481 return HAL_OK;
lypinator 0:bb348c97df44 1482 }
lypinator 0:bb348c97df44 1483 /**
lypinator 0:bb348c97df44 1484 * @}
lypinator 0:bb348c97df44 1485 */
lypinator 0:bb348c97df44 1486
lypinator 0:bb348c97df44 1487 /** @defgroup TIM_Exported_Functions_Group4 Time Input Capture functions
lypinator 0:bb348c97df44 1488 * @brief Time Input Capture functions
lypinator 0:bb348c97df44 1489 *
lypinator 0:bb348c97df44 1490 @verbatim
lypinator 0:bb348c97df44 1491 ==============================================================================
lypinator 0:bb348c97df44 1492 ##### Time Input Capture functions #####
lypinator 0:bb348c97df44 1493 ==============================================================================
lypinator 0:bb348c97df44 1494 [..]
lypinator 0:bb348c97df44 1495 This section provides functions allowing to:
lypinator 0:bb348c97df44 1496 (+) Initialize and configure the TIM Input Capture.
lypinator 0:bb348c97df44 1497 (+) De-initialize the TIM Input Capture.
lypinator 0:bb348c97df44 1498 (+) Start the Time Input Capture.
lypinator 0:bb348c97df44 1499 (+) Stop the Time Input Capture.
lypinator 0:bb348c97df44 1500 (+) Start the Time Input Capture and enable interrupt.
lypinator 0:bb348c97df44 1501 (+) Stop the Time Input Capture and disable interrupt.
lypinator 0:bb348c97df44 1502 (+) Start the Time Input Capture and enable DMA transfer.
lypinator 0:bb348c97df44 1503 (+) Stop the Time Input Capture and disable DMA transfer.
lypinator 0:bb348c97df44 1504
lypinator 0:bb348c97df44 1505 @endverbatim
lypinator 0:bb348c97df44 1506 * @{
lypinator 0:bb348c97df44 1507 */
lypinator 0:bb348c97df44 1508 /**
lypinator 0:bb348c97df44 1509 * @brief Initializes the TIM Input Capture Time base according to the specified
lypinator 0:bb348c97df44 1510 * parameters in the TIM_HandleTypeDef and create the associated handle.
lypinator 0:bb348c97df44 1511 * @param htim pointer to a TIM_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 1512 * the configuration information for TIM module.
lypinator 0:bb348c97df44 1513 * @retval HAL status
lypinator 0:bb348c97df44 1514 */
lypinator 0:bb348c97df44 1515 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
lypinator 0:bb348c97df44 1516 {
lypinator 0:bb348c97df44 1517 /* Check the TIM handle allocation */
lypinator 0:bb348c97df44 1518 if(htim == NULL)
lypinator 0:bb348c97df44 1519 {
lypinator 0:bb348c97df44 1520 return HAL_ERROR;
lypinator 0:bb348c97df44 1521 }
lypinator 0:bb348c97df44 1522
lypinator 0:bb348c97df44 1523 /* Check the parameters */
lypinator 0:bb348c97df44 1524 assert_param(IS_TIM_INSTANCE(htim->Instance));
lypinator 0:bb348c97df44 1525 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
lypinator 0:bb348c97df44 1526 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
lypinator 0:bb348c97df44 1527
lypinator 0:bb348c97df44 1528 if(htim->State == HAL_TIM_STATE_RESET)
lypinator 0:bb348c97df44 1529 {
lypinator 0:bb348c97df44 1530 /* Allocate lock resource and initialize it */
lypinator 0:bb348c97df44 1531 htim->Lock = HAL_UNLOCKED;
lypinator 0:bb348c97df44 1532 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
lypinator 0:bb348c97df44 1533 HAL_TIM_IC_MspInit(htim);
lypinator 0:bb348c97df44 1534 }
lypinator 0:bb348c97df44 1535
lypinator 0:bb348c97df44 1536 /* Set the TIM state */
lypinator 0:bb348c97df44 1537 htim->State= HAL_TIM_STATE_BUSY;
lypinator 0:bb348c97df44 1538
lypinator 0:bb348c97df44 1539 /* Init the base time for the input capture */
lypinator 0:bb348c97df44 1540 TIM_Base_SetConfig(htim->Instance, &htim->Init);
lypinator 0:bb348c97df44 1541
lypinator 0:bb348c97df44 1542 /* Initialize the TIM state*/
lypinator 0:bb348c97df44 1543 htim->State= HAL_TIM_STATE_READY;
lypinator 0:bb348c97df44 1544
lypinator 0:bb348c97df44 1545 return HAL_OK;
lypinator 0:bb348c97df44 1546 }
lypinator 0:bb348c97df44 1547
lypinator 0:bb348c97df44 1548 /**
lypinator 0:bb348c97df44 1549 * @brief DeInitializes the TIM peripheral
lypinator 0:bb348c97df44 1550 * @param htim pointer to a TIM_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 1551 * the configuration information for TIM module.
lypinator 0:bb348c97df44 1552 * @retval HAL status
lypinator 0:bb348c97df44 1553 */
lypinator 0:bb348c97df44 1554 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
lypinator 0:bb348c97df44 1555 {
lypinator 0:bb348c97df44 1556 /* Check the parameters */
lypinator 0:bb348c97df44 1557 assert_param(IS_TIM_INSTANCE(htim->Instance));
lypinator 0:bb348c97df44 1558
lypinator 0:bb348c97df44 1559 htim->State = HAL_TIM_STATE_BUSY;
lypinator 0:bb348c97df44 1560
lypinator 0:bb348c97df44 1561 /* Disable the TIM Peripheral Clock */
lypinator 0:bb348c97df44 1562 __HAL_TIM_DISABLE(htim);
lypinator 0:bb348c97df44 1563
lypinator 0:bb348c97df44 1564 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
lypinator 0:bb348c97df44 1565 HAL_TIM_IC_MspDeInit(htim);
lypinator 0:bb348c97df44 1566
lypinator 0:bb348c97df44 1567 /* Change TIM state */
lypinator 0:bb348c97df44 1568 htim->State = HAL_TIM_STATE_RESET;
lypinator 0:bb348c97df44 1569
lypinator 0:bb348c97df44 1570 /* Release Lock */
lypinator 0:bb348c97df44 1571 __HAL_UNLOCK(htim);
lypinator 0:bb348c97df44 1572
lypinator 0:bb348c97df44 1573 return HAL_OK;
lypinator 0:bb348c97df44 1574 }
lypinator 0:bb348c97df44 1575
lypinator 0:bb348c97df44 1576 /**
lypinator 0:bb348c97df44 1577 * @brief Initializes the TIM INput Capture MSP.
lypinator 0:bb348c97df44 1578 * @param htim pointer to a TIM_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 1579 * the configuration information for TIM module.
lypinator 0:bb348c97df44 1580 * @retval None
lypinator 0:bb348c97df44 1581 */
lypinator 0:bb348c97df44 1582 __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
lypinator 0:bb348c97df44 1583 {
lypinator 0:bb348c97df44 1584 /* Prevent unused argument(s) compilation warning */
lypinator 0:bb348c97df44 1585 UNUSED(htim);
lypinator 0:bb348c97df44 1586 /* NOTE : This function Should not be modified, when the callback is needed,
lypinator 0:bb348c97df44 1587 the HAL_TIM_IC_MspInit could be implemented in the user file
lypinator 0:bb348c97df44 1588 */
lypinator 0:bb348c97df44 1589 }
lypinator 0:bb348c97df44 1590
lypinator 0:bb348c97df44 1591 /**
lypinator 0:bb348c97df44 1592 * @brief DeInitializes TIM Input Capture MSP.
lypinator 0:bb348c97df44 1593 * @param htim pointer to a TIM_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 1594 * the configuration information for TIM module.
lypinator 0:bb348c97df44 1595 * @retval None
lypinator 0:bb348c97df44 1596 */
lypinator 0:bb348c97df44 1597 __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
lypinator 0:bb348c97df44 1598 {
lypinator 0:bb348c97df44 1599 /* Prevent unused argument(s) compilation warning */
lypinator 0:bb348c97df44 1600 UNUSED(htim);
lypinator 0:bb348c97df44 1601 /* NOTE : This function Should not be modified, when the callback is needed,
lypinator 0:bb348c97df44 1602 the HAL_TIM_IC_MspDeInit could be implemented in the user file
lypinator 0:bb348c97df44 1603 */
lypinator 0:bb348c97df44 1604 }
lypinator 0:bb348c97df44 1605
lypinator 0:bb348c97df44 1606 /**
lypinator 0:bb348c97df44 1607 * @brief Starts the TIM Input Capture measurement.
lypinator 0:bb348c97df44 1608 * @param htim pointer to a TIM_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 1609 * the configuration information for TIM module.
lypinator 0:bb348c97df44 1610 * @param Channel TIM Channels to be enabled.
lypinator 0:bb348c97df44 1611 * This parameter can be one of the following values:
lypinator 0:bb348c97df44 1612 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
lypinator 0:bb348c97df44 1613 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
lypinator 0:bb348c97df44 1614 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
lypinator 0:bb348c97df44 1615 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
lypinator 0:bb348c97df44 1616 * @retval HAL status
lypinator 0:bb348c97df44 1617 */
lypinator 0:bb348c97df44 1618 HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
lypinator 0:bb348c97df44 1619 {
lypinator 0:bb348c97df44 1620 /* Check the parameters */
lypinator 0:bb348c97df44 1621 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
lypinator 0:bb348c97df44 1622
lypinator 0:bb348c97df44 1623 /* Enable the Input Capture channel */
lypinator 0:bb348c97df44 1624 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
lypinator 0:bb348c97df44 1625
lypinator 0:bb348c97df44 1626 /* Enable the Peripheral */
lypinator 0:bb348c97df44 1627 __HAL_TIM_ENABLE(htim);
lypinator 0:bb348c97df44 1628
lypinator 0:bb348c97df44 1629 /* Return function status */
lypinator 0:bb348c97df44 1630 return HAL_OK;
lypinator 0:bb348c97df44 1631 }
lypinator 0:bb348c97df44 1632
lypinator 0:bb348c97df44 1633 /**
lypinator 0:bb348c97df44 1634 * @brief Stops the TIM Input Capture measurement.
lypinator 0:bb348c97df44 1635 * @param htim pointer to a TIM_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 1636 * the configuration information for TIM module.
lypinator 0:bb348c97df44 1637 * @param Channel TIM Channels to be disabled.
lypinator 0:bb348c97df44 1638 * This parameter can be one of the following values:
lypinator 0:bb348c97df44 1639 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
lypinator 0:bb348c97df44 1640 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
lypinator 0:bb348c97df44 1641 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
lypinator 0:bb348c97df44 1642 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
lypinator 0:bb348c97df44 1643 * @retval HAL status
lypinator 0:bb348c97df44 1644 */
lypinator 0:bb348c97df44 1645 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
lypinator 0:bb348c97df44 1646 {
lypinator 0:bb348c97df44 1647 /* Check the parameters */
lypinator 0:bb348c97df44 1648 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
lypinator 0:bb348c97df44 1649
lypinator 0:bb348c97df44 1650 /* Disable the Input Capture channel */
lypinator 0:bb348c97df44 1651 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
lypinator 0:bb348c97df44 1652
lypinator 0:bb348c97df44 1653 /* Disable the Peripheral */
lypinator 0:bb348c97df44 1654 __HAL_TIM_DISABLE(htim);
lypinator 0:bb348c97df44 1655
lypinator 0:bb348c97df44 1656 /* Return function status */
lypinator 0:bb348c97df44 1657 return HAL_OK;
lypinator 0:bb348c97df44 1658 }
lypinator 0:bb348c97df44 1659
lypinator 0:bb348c97df44 1660 /**
lypinator 0:bb348c97df44 1661 * @brief Starts the TIM Input Capture measurement in interrupt mode.
lypinator 0:bb348c97df44 1662 * @param htim pointer to a TIM_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 1663 * the configuration information for TIM module.
lypinator 0:bb348c97df44 1664 * @param Channel TIM Channels to be enabled.
lypinator 0:bb348c97df44 1665 * This parameter can be one of the following values:
lypinator 0:bb348c97df44 1666 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
lypinator 0:bb348c97df44 1667 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
lypinator 0:bb348c97df44 1668 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
lypinator 0:bb348c97df44 1669 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
lypinator 0:bb348c97df44 1670 * @retval HAL status
lypinator 0:bb348c97df44 1671 */
lypinator 0:bb348c97df44 1672 HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
lypinator 0:bb348c97df44 1673 {
lypinator 0:bb348c97df44 1674 /* Check the parameters */
lypinator 0:bb348c97df44 1675 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
lypinator 0:bb348c97df44 1676
lypinator 0:bb348c97df44 1677 switch (Channel)
lypinator 0:bb348c97df44 1678 {
lypinator 0:bb348c97df44 1679 case TIM_CHANNEL_1:
lypinator 0:bb348c97df44 1680 {
lypinator 0:bb348c97df44 1681 /* Enable the TIM Capture/Compare 1 interrupt */
lypinator 0:bb348c97df44 1682 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
lypinator 0:bb348c97df44 1683 }
lypinator 0:bb348c97df44 1684 break;
lypinator 0:bb348c97df44 1685
lypinator 0:bb348c97df44 1686 case TIM_CHANNEL_2:
lypinator 0:bb348c97df44 1687 {
lypinator 0:bb348c97df44 1688 /* Enable the TIM Capture/Compare 2 interrupt */
lypinator 0:bb348c97df44 1689 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
lypinator 0:bb348c97df44 1690 }
lypinator 0:bb348c97df44 1691 break;
lypinator 0:bb348c97df44 1692
lypinator 0:bb348c97df44 1693 case TIM_CHANNEL_3:
lypinator 0:bb348c97df44 1694 {
lypinator 0:bb348c97df44 1695 /* Enable the TIM Capture/Compare 3 interrupt */
lypinator 0:bb348c97df44 1696 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
lypinator 0:bb348c97df44 1697 }
lypinator 0:bb348c97df44 1698 break;
lypinator 0:bb348c97df44 1699
lypinator 0:bb348c97df44 1700 case TIM_CHANNEL_4:
lypinator 0:bb348c97df44 1701 {
lypinator 0:bb348c97df44 1702 /* Enable the TIM Capture/Compare 4 interrupt */
lypinator 0:bb348c97df44 1703 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
lypinator 0:bb348c97df44 1704 }
lypinator 0:bb348c97df44 1705 break;
lypinator 0:bb348c97df44 1706
lypinator 0:bb348c97df44 1707 default:
lypinator 0:bb348c97df44 1708 break;
lypinator 0:bb348c97df44 1709 }
lypinator 0:bb348c97df44 1710 /* Enable the Input Capture channel */
lypinator 0:bb348c97df44 1711 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
lypinator 0:bb348c97df44 1712
lypinator 0:bb348c97df44 1713 /* Enable the Peripheral */
lypinator 0:bb348c97df44 1714 __HAL_TIM_ENABLE(htim);
lypinator 0:bb348c97df44 1715
lypinator 0:bb348c97df44 1716 /* Return function status */
lypinator 0:bb348c97df44 1717 return HAL_OK;
lypinator 0:bb348c97df44 1718 }
lypinator 0:bb348c97df44 1719
lypinator 0:bb348c97df44 1720 /**
lypinator 0:bb348c97df44 1721 * @brief Stops the TIM Input Capture measurement in interrupt mode.
lypinator 0:bb348c97df44 1722 * @param htim pointer to a TIM_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 1723 * the configuration information for TIM module.
lypinator 0:bb348c97df44 1724 * @param Channel TIM Channels to be disabled.
lypinator 0:bb348c97df44 1725 * This parameter can be one of the following values:
lypinator 0:bb348c97df44 1726 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
lypinator 0:bb348c97df44 1727 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
lypinator 0:bb348c97df44 1728 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
lypinator 0:bb348c97df44 1729 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
lypinator 0:bb348c97df44 1730 * @retval HAL status
lypinator 0:bb348c97df44 1731 */
lypinator 0:bb348c97df44 1732 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
lypinator 0:bb348c97df44 1733 {
lypinator 0:bb348c97df44 1734 /* Check the parameters */
lypinator 0:bb348c97df44 1735 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
lypinator 0:bb348c97df44 1736
lypinator 0:bb348c97df44 1737 switch (Channel)
lypinator 0:bb348c97df44 1738 {
lypinator 0:bb348c97df44 1739 case TIM_CHANNEL_1:
lypinator 0:bb348c97df44 1740 {
lypinator 0:bb348c97df44 1741 /* Disable the TIM Capture/Compare 1 interrupt */
lypinator 0:bb348c97df44 1742 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
lypinator 0:bb348c97df44 1743 }
lypinator 0:bb348c97df44 1744 break;
lypinator 0:bb348c97df44 1745
lypinator 0:bb348c97df44 1746 case TIM_CHANNEL_2:
lypinator 0:bb348c97df44 1747 {
lypinator 0:bb348c97df44 1748 /* Disable the TIM Capture/Compare 2 interrupt */
lypinator 0:bb348c97df44 1749 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
lypinator 0:bb348c97df44 1750 }
lypinator 0:bb348c97df44 1751 break;
lypinator 0:bb348c97df44 1752
lypinator 0:bb348c97df44 1753 case TIM_CHANNEL_3:
lypinator 0:bb348c97df44 1754 {
lypinator 0:bb348c97df44 1755 /* Disable the TIM Capture/Compare 3 interrupt */
lypinator 0:bb348c97df44 1756 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
lypinator 0:bb348c97df44 1757 }
lypinator 0:bb348c97df44 1758 break;
lypinator 0:bb348c97df44 1759
lypinator 0:bb348c97df44 1760 case TIM_CHANNEL_4:
lypinator 0:bb348c97df44 1761 {
lypinator 0:bb348c97df44 1762 /* Disable the TIM Capture/Compare 4 interrupt */
lypinator 0:bb348c97df44 1763 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
lypinator 0:bb348c97df44 1764 }
lypinator 0:bb348c97df44 1765 break;
lypinator 0:bb348c97df44 1766
lypinator 0:bb348c97df44 1767 default:
lypinator 0:bb348c97df44 1768 break;
lypinator 0:bb348c97df44 1769 }
lypinator 0:bb348c97df44 1770
lypinator 0:bb348c97df44 1771 /* Disable the Input Capture channel */
lypinator 0:bb348c97df44 1772 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
lypinator 0:bb348c97df44 1773
lypinator 0:bb348c97df44 1774 /* Disable the Peripheral */
lypinator 0:bb348c97df44 1775 __HAL_TIM_DISABLE(htim);
lypinator 0:bb348c97df44 1776
lypinator 0:bb348c97df44 1777 /* Return function status */
lypinator 0:bb348c97df44 1778 return HAL_OK;
lypinator 0:bb348c97df44 1779 }
lypinator 0:bb348c97df44 1780
lypinator 0:bb348c97df44 1781 /**
lypinator 0:bb348c97df44 1782 * @brief Starts the TIM Input Capture measurement on in DMA mode.
lypinator 0:bb348c97df44 1783 * @param htim pointer to a TIM_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 1784 * the configuration information for TIM module.
lypinator 0:bb348c97df44 1785 * @param Channel TIM Channels to be enabled.
lypinator 0:bb348c97df44 1786 * This parameter can be one of the following values:
lypinator 0:bb348c97df44 1787 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
lypinator 0:bb348c97df44 1788 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
lypinator 0:bb348c97df44 1789 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
lypinator 0:bb348c97df44 1790 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
lypinator 0:bb348c97df44 1791 * @param pData The destination Buffer address.
lypinator 0:bb348c97df44 1792 * @param Length The length of data to be transferred from TIM peripheral to memory.
lypinator 0:bb348c97df44 1793 * @retval HAL status
lypinator 0:bb348c97df44 1794 */
lypinator 0:bb348c97df44 1795 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
lypinator 0:bb348c97df44 1796 {
lypinator 0:bb348c97df44 1797 /* Check the parameters */
lypinator 0:bb348c97df44 1798 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
lypinator 0:bb348c97df44 1799 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
lypinator 0:bb348c97df44 1800
lypinator 0:bb348c97df44 1801 if((htim->State == HAL_TIM_STATE_BUSY))
lypinator 0:bb348c97df44 1802 {
lypinator 0:bb348c97df44 1803 return HAL_BUSY;
lypinator 0:bb348c97df44 1804 }
lypinator 0:bb348c97df44 1805 else if((htim->State == HAL_TIM_STATE_READY))
lypinator 0:bb348c97df44 1806 {
lypinator 0:bb348c97df44 1807 if((pData == 0U) && (Length > 0))
lypinator 0:bb348c97df44 1808 {
lypinator 0:bb348c97df44 1809 return HAL_ERROR;
lypinator 0:bb348c97df44 1810 }
lypinator 0:bb348c97df44 1811 else
lypinator 0:bb348c97df44 1812 {
lypinator 0:bb348c97df44 1813 htim->State = HAL_TIM_STATE_BUSY;
lypinator 0:bb348c97df44 1814 }
lypinator 0:bb348c97df44 1815 }
lypinator 0:bb348c97df44 1816
lypinator 0:bb348c97df44 1817 switch (Channel)
lypinator 0:bb348c97df44 1818 {
lypinator 0:bb348c97df44 1819 case TIM_CHANNEL_1:
lypinator 0:bb348c97df44 1820 {
lypinator 0:bb348c97df44 1821 /* Set the DMA Period elapsed callback */
lypinator 0:bb348c97df44 1822 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
lypinator 0:bb348c97df44 1823
lypinator 0:bb348c97df44 1824 /* Set the DMA error callback */
lypinator 0:bb348c97df44 1825 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
lypinator 0:bb348c97df44 1826
lypinator 0:bb348c97df44 1827 /* Enable the DMA Stream */
lypinator 0:bb348c97df44 1828 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
lypinator 0:bb348c97df44 1829
lypinator 0:bb348c97df44 1830 /* Enable the TIM Capture/Compare 1 DMA request */
lypinator 0:bb348c97df44 1831 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
lypinator 0:bb348c97df44 1832 }
lypinator 0:bb348c97df44 1833 break;
lypinator 0:bb348c97df44 1834
lypinator 0:bb348c97df44 1835 case TIM_CHANNEL_2:
lypinator 0:bb348c97df44 1836 {
lypinator 0:bb348c97df44 1837 /* Set the DMA Period elapsed callback */
lypinator 0:bb348c97df44 1838 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
lypinator 0:bb348c97df44 1839
lypinator 0:bb348c97df44 1840 /* Set the DMA error callback */
lypinator 0:bb348c97df44 1841 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
lypinator 0:bb348c97df44 1842
lypinator 0:bb348c97df44 1843 /* Enable the DMA Stream */
lypinator 0:bb348c97df44 1844 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length);
lypinator 0:bb348c97df44 1845
lypinator 0:bb348c97df44 1846 /* Enable the TIM Capture/Compare 2 DMA request */
lypinator 0:bb348c97df44 1847 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
lypinator 0:bb348c97df44 1848 }
lypinator 0:bb348c97df44 1849 break;
lypinator 0:bb348c97df44 1850
lypinator 0:bb348c97df44 1851 case TIM_CHANNEL_3:
lypinator 0:bb348c97df44 1852 {
lypinator 0:bb348c97df44 1853 /* Set the DMA Period elapsed callback */
lypinator 0:bb348c97df44 1854 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
lypinator 0:bb348c97df44 1855
lypinator 0:bb348c97df44 1856 /* Set the DMA error callback */
lypinator 0:bb348c97df44 1857 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
lypinator 0:bb348c97df44 1858
lypinator 0:bb348c97df44 1859 /* Enable the DMA Stream */
lypinator 0:bb348c97df44 1860 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length);
lypinator 0:bb348c97df44 1861
lypinator 0:bb348c97df44 1862 /* Enable the TIM Capture/Compare 3 DMA request */
lypinator 0:bb348c97df44 1863 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
lypinator 0:bb348c97df44 1864 }
lypinator 0:bb348c97df44 1865 break;
lypinator 0:bb348c97df44 1866
lypinator 0:bb348c97df44 1867 case TIM_CHANNEL_4:
lypinator 0:bb348c97df44 1868 {
lypinator 0:bb348c97df44 1869 /* Set the DMA Period elapsed callback */
lypinator 0:bb348c97df44 1870 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
lypinator 0:bb348c97df44 1871
lypinator 0:bb348c97df44 1872 /* Set the DMA error callback */
lypinator 0:bb348c97df44 1873 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
lypinator 0:bb348c97df44 1874
lypinator 0:bb348c97df44 1875 /* Enable the DMA Stream */
lypinator 0:bb348c97df44 1876 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length);
lypinator 0:bb348c97df44 1877
lypinator 0:bb348c97df44 1878 /* Enable the TIM Capture/Compare 4 DMA request */
lypinator 0:bb348c97df44 1879 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
lypinator 0:bb348c97df44 1880 }
lypinator 0:bb348c97df44 1881 break;
lypinator 0:bb348c97df44 1882
lypinator 0:bb348c97df44 1883 default:
lypinator 0:bb348c97df44 1884 break;
lypinator 0:bb348c97df44 1885 }
lypinator 0:bb348c97df44 1886
lypinator 0:bb348c97df44 1887 /* Enable the Input Capture channel */
lypinator 0:bb348c97df44 1888 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
lypinator 0:bb348c97df44 1889
lypinator 0:bb348c97df44 1890 /* Enable the Peripheral */
lypinator 0:bb348c97df44 1891 __HAL_TIM_ENABLE(htim);
lypinator 0:bb348c97df44 1892
lypinator 0:bb348c97df44 1893 /* Return function status */
lypinator 0:bb348c97df44 1894 return HAL_OK;
lypinator 0:bb348c97df44 1895 }
lypinator 0:bb348c97df44 1896
lypinator 0:bb348c97df44 1897 /**
lypinator 0:bb348c97df44 1898 * @brief Stops the TIM Input Capture measurement on in DMA mode.
lypinator 0:bb348c97df44 1899 * @param htim pointer to a TIM_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 1900 * the configuration information for TIM module.
lypinator 0:bb348c97df44 1901 * @param Channel TIM Channels to be disabled.
lypinator 0:bb348c97df44 1902 * This parameter can be one of the following values:
lypinator 0:bb348c97df44 1903 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
lypinator 0:bb348c97df44 1904 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
lypinator 0:bb348c97df44 1905 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
lypinator 0:bb348c97df44 1906 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
lypinator 0:bb348c97df44 1907 * @retval HAL status
lypinator 0:bb348c97df44 1908 */
lypinator 0:bb348c97df44 1909 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
lypinator 0:bb348c97df44 1910 {
lypinator 0:bb348c97df44 1911 /* Check the parameters */
lypinator 0:bb348c97df44 1912 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
lypinator 0:bb348c97df44 1913 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
lypinator 0:bb348c97df44 1914
lypinator 0:bb348c97df44 1915 switch (Channel)
lypinator 0:bb348c97df44 1916 {
lypinator 0:bb348c97df44 1917 case TIM_CHANNEL_1:
lypinator 0:bb348c97df44 1918 {
lypinator 0:bb348c97df44 1919 /* Disable the TIM Capture/Compare 1 DMA request */
lypinator 0:bb348c97df44 1920 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
lypinator 0:bb348c97df44 1921 }
lypinator 0:bb348c97df44 1922 break;
lypinator 0:bb348c97df44 1923
lypinator 0:bb348c97df44 1924 case TIM_CHANNEL_2:
lypinator 0:bb348c97df44 1925 {
lypinator 0:bb348c97df44 1926 /* Disable the TIM Capture/Compare 2 DMA request */
lypinator 0:bb348c97df44 1927 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
lypinator 0:bb348c97df44 1928 }
lypinator 0:bb348c97df44 1929 break;
lypinator 0:bb348c97df44 1930
lypinator 0:bb348c97df44 1931 case TIM_CHANNEL_3:
lypinator 0:bb348c97df44 1932 {
lypinator 0:bb348c97df44 1933 /* Disable the TIM Capture/Compare 3 DMA request */
lypinator 0:bb348c97df44 1934 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
lypinator 0:bb348c97df44 1935 }
lypinator 0:bb348c97df44 1936 break;
lypinator 0:bb348c97df44 1937
lypinator 0:bb348c97df44 1938 case TIM_CHANNEL_4:
lypinator 0:bb348c97df44 1939 {
lypinator 0:bb348c97df44 1940 /* Disable the TIM Capture/Compare 4 DMA request */
lypinator 0:bb348c97df44 1941 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
lypinator 0:bb348c97df44 1942 }
lypinator 0:bb348c97df44 1943 break;
lypinator 0:bb348c97df44 1944
lypinator 0:bb348c97df44 1945 default:
lypinator 0:bb348c97df44 1946 break;
lypinator 0:bb348c97df44 1947 }
lypinator 0:bb348c97df44 1948
lypinator 0:bb348c97df44 1949 /* Disable the Input Capture channel */
lypinator 0:bb348c97df44 1950 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
lypinator 0:bb348c97df44 1951
lypinator 0:bb348c97df44 1952 /* Disable the Peripheral */
lypinator 0:bb348c97df44 1953 __HAL_TIM_DISABLE(htim);
lypinator 0:bb348c97df44 1954
lypinator 0:bb348c97df44 1955 /* Change the htim state */
lypinator 0:bb348c97df44 1956 htim->State = HAL_TIM_STATE_READY;
lypinator 0:bb348c97df44 1957
lypinator 0:bb348c97df44 1958 /* Return function status */
lypinator 0:bb348c97df44 1959 return HAL_OK;
lypinator 0:bb348c97df44 1960 }
lypinator 0:bb348c97df44 1961 /**
lypinator 0:bb348c97df44 1962 * @}
lypinator 0:bb348c97df44 1963 */
lypinator 0:bb348c97df44 1964
lypinator 0:bb348c97df44 1965 /** @defgroup TIM_Exported_Functions_Group5 Time One Pulse functions
lypinator 0:bb348c97df44 1966 * @brief Time One Pulse functions
lypinator 0:bb348c97df44 1967 *
lypinator 0:bb348c97df44 1968 @verbatim
lypinator 0:bb348c97df44 1969 ==============================================================================
lypinator 0:bb348c97df44 1970 ##### Time One Pulse functions #####
lypinator 0:bb348c97df44 1971 ==============================================================================
lypinator 0:bb348c97df44 1972 [..]
lypinator 0:bb348c97df44 1973 This section provides functions allowing to:
lypinator 0:bb348c97df44 1974 (+) Initialize and configure the TIM One Pulse.
lypinator 0:bb348c97df44 1975 (+) De-initialize the TIM One Pulse.
lypinator 0:bb348c97df44 1976 (+) Start the Time One Pulse.
lypinator 0:bb348c97df44 1977 (+) Stop the Time One Pulse.
lypinator 0:bb348c97df44 1978 (+) Start the Time One Pulse and enable interrupt.
lypinator 0:bb348c97df44 1979 (+) Stop the Time One Pulse and disable interrupt.
lypinator 0:bb348c97df44 1980 (+) Start the Time One Pulse and enable DMA transfer.
lypinator 0:bb348c97df44 1981 (+) Stop the Time One Pulse and disable DMA transfer.
lypinator 0:bb348c97df44 1982
lypinator 0:bb348c97df44 1983 @endverbatim
lypinator 0:bb348c97df44 1984 * @{
lypinator 0:bb348c97df44 1985 */
lypinator 0:bb348c97df44 1986 /**
lypinator 0:bb348c97df44 1987 * @brief Initializes the TIM One Pulse Time Base according to the specified
lypinator 0:bb348c97df44 1988 * parameters in the TIM_HandleTypeDef and create the associated handle.
lypinator 0:bb348c97df44 1989 * @param htim pointer to a TIM_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 1990 * the configuration information for TIM module.
lypinator 0:bb348c97df44 1991 * @param OnePulseMode Select the One pulse mode.
lypinator 0:bb348c97df44 1992 * This parameter can be one of the following values:
lypinator 0:bb348c97df44 1993 * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
lypinator 0:bb348c97df44 1994 * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.
lypinator 0:bb348c97df44 1995 * @retval HAL status
lypinator 0:bb348c97df44 1996 */
lypinator 0:bb348c97df44 1997 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
lypinator 0:bb348c97df44 1998 {
lypinator 0:bb348c97df44 1999 /* Check the TIM handle allocation */
lypinator 0:bb348c97df44 2000 if(htim == NULL)
lypinator 0:bb348c97df44 2001 {
lypinator 0:bb348c97df44 2002 return HAL_ERROR;
lypinator 0:bb348c97df44 2003 }
lypinator 0:bb348c97df44 2004
lypinator 0:bb348c97df44 2005 /* Check the parameters */
lypinator 0:bb348c97df44 2006 assert_param(IS_TIM_INSTANCE(htim->Instance));
lypinator 0:bb348c97df44 2007 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
lypinator 0:bb348c97df44 2008 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
lypinator 0:bb348c97df44 2009 assert_param(IS_TIM_OPM_MODE(OnePulseMode));
lypinator 0:bb348c97df44 2010
lypinator 0:bb348c97df44 2011 if(htim->State == HAL_TIM_STATE_RESET)
lypinator 0:bb348c97df44 2012 {
lypinator 0:bb348c97df44 2013 /* Allocate lock resource and initialize it */
lypinator 0:bb348c97df44 2014 htim->Lock = HAL_UNLOCKED;
lypinator 0:bb348c97df44 2015 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
lypinator 0:bb348c97df44 2016 HAL_TIM_OnePulse_MspInit(htim);
lypinator 0:bb348c97df44 2017 }
lypinator 0:bb348c97df44 2018
lypinator 0:bb348c97df44 2019 /* Set the TIM state */
lypinator 0:bb348c97df44 2020 htim->State= HAL_TIM_STATE_BUSY;
lypinator 0:bb348c97df44 2021
lypinator 0:bb348c97df44 2022 /* Configure the Time base in the One Pulse Mode */
lypinator 0:bb348c97df44 2023 TIM_Base_SetConfig(htim->Instance, &htim->Init);
lypinator 0:bb348c97df44 2024
lypinator 0:bb348c97df44 2025 /* Reset the OPM Bit */
lypinator 0:bb348c97df44 2026 htim->Instance->CR1 &= ~TIM_CR1_OPM;
lypinator 0:bb348c97df44 2027
lypinator 0:bb348c97df44 2028 /* Configure the OPM Mode */
lypinator 0:bb348c97df44 2029 htim->Instance->CR1 |= OnePulseMode;
lypinator 0:bb348c97df44 2030
lypinator 0:bb348c97df44 2031 /* Initialize the TIM state*/
lypinator 0:bb348c97df44 2032 htim->State= HAL_TIM_STATE_READY;
lypinator 0:bb348c97df44 2033
lypinator 0:bb348c97df44 2034 return HAL_OK;
lypinator 0:bb348c97df44 2035 }
lypinator 0:bb348c97df44 2036
lypinator 0:bb348c97df44 2037 /**
lypinator 0:bb348c97df44 2038 * @brief DeInitializes the TIM One Pulse
lypinator 0:bb348c97df44 2039 * @param htim pointer to a TIM_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 2040 * the configuration information for TIM module.
lypinator 0:bb348c97df44 2041 * @retval HAL status
lypinator 0:bb348c97df44 2042 */
lypinator 0:bb348c97df44 2043 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
lypinator 0:bb348c97df44 2044 {
lypinator 0:bb348c97df44 2045 /* Check the parameters */
lypinator 0:bb348c97df44 2046 assert_param(IS_TIM_INSTANCE(htim->Instance));
lypinator 0:bb348c97df44 2047
lypinator 0:bb348c97df44 2048 htim->State = HAL_TIM_STATE_BUSY;
lypinator 0:bb348c97df44 2049
lypinator 0:bb348c97df44 2050 /* Disable the TIM Peripheral Clock */
lypinator 0:bb348c97df44 2051 __HAL_TIM_DISABLE(htim);
lypinator 0:bb348c97df44 2052
lypinator 0:bb348c97df44 2053 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
lypinator 0:bb348c97df44 2054 HAL_TIM_OnePulse_MspDeInit(htim);
lypinator 0:bb348c97df44 2055
lypinator 0:bb348c97df44 2056 /* Change TIM state */
lypinator 0:bb348c97df44 2057 htim->State = HAL_TIM_STATE_RESET;
lypinator 0:bb348c97df44 2058
lypinator 0:bb348c97df44 2059 /* Release Lock */
lypinator 0:bb348c97df44 2060 __HAL_UNLOCK(htim);
lypinator 0:bb348c97df44 2061
lypinator 0:bb348c97df44 2062 return HAL_OK;
lypinator 0:bb348c97df44 2063 }
lypinator 0:bb348c97df44 2064
lypinator 0:bb348c97df44 2065 /**
lypinator 0:bb348c97df44 2066 * @brief Initializes the TIM One Pulse MSP.
lypinator 0:bb348c97df44 2067 * @param htim pointer to a TIM_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 2068 * the configuration information for TIM module.
lypinator 0:bb348c97df44 2069 * @retval None
lypinator 0:bb348c97df44 2070 */
lypinator 0:bb348c97df44 2071 __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
lypinator 0:bb348c97df44 2072 {
lypinator 0:bb348c97df44 2073 /* Prevent unused argument(s) compilation warning */
lypinator 0:bb348c97df44 2074 UNUSED(htim);
lypinator 0:bb348c97df44 2075 /* NOTE : This function Should not be modified, when the callback is needed,
lypinator 0:bb348c97df44 2076 the HAL_TIM_OnePulse_MspInit could be implemented in the user file
lypinator 0:bb348c97df44 2077 */
lypinator 0:bb348c97df44 2078 }
lypinator 0:bb348c97df44 2079
lypinator 0:bb348c97df44 2080 /**
lypinator 0:bb348c97df44 2081 * @brief DeInitializes TIM One Pulse MSP.
lypinator 0:bb348c97df44 2082 * @param htim pointer to a TIM_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 2083 * the configuration information for TIM module.
lypinator 0:bb348c97df44 2084 * @retval None
lypinator 0:bb348c97df44 2085 */
lypinator 0:bb348c97df44 2086 __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
lypinator 0:bb348c97df44 2087 {
lypinator 0:bb348c97df44 2088 /* Prevent unused argument(s) compilation warning */
lypinator 0:bb348c97df44 2089 UNUSED(htim);
lypinator 0:bb348c97df44 2090 /* NOTE : This function Should not be modified, when the callback is needed,
lypinator 0:bb348c97df44 2091 the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
lypinator 0:bb348c97df44 2092 */
lypinator 0:bb348c97df44 2093 }
lypinator 0:bb348c97df44 2094
lypinator 0:bb348c97df44 2095 /**
lypinator 0:bb348c97df44 2096 * @brief Starts the TIM One Pulse signal generation.
lypinator 0:bb348c97df44 2097 * @param htim pointer to a TIM_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 2098 * the configuration information for TIM module.
lypinator 0:bb348c97df44 2099 * @param OutputChannel TIM Channels to be enabled.
lypinator 0:bb348c97df44 2100 * This parameter can be one of the following values:
lypinator 0:bb348c97df44 2101 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
lypinator 0:bb348c97df44 2102 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
lypinator 0:bb348c97df44 2103 * @retval HAL status
lypinator 0:bb348c97df44 2104 */
lypinator 0:bb348c97df44 2105 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
lypinator 0:bb348c97df44 2106 {
lypinator 0:bb348c97df44 2107 /* Prevent unused argument(s) compilation warning */
lypinator 0:bb348c97df44 2108 UNUSED(OutputChannel);
lypinator 0:bb348c97df44 2109
lypinator 0:bb348c97df44 2110 /* Enable the Capture compare and the Input Capture channels
lypinator 0:bb348c97df44 2111 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
lypinator 0:bb348c97df44 2112 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
lypinator 0:bb348c97df44 2113 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
lypinator 0:bb348c97df44 2114 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
lypinator 0:bb348c97df44 2115
lypinator 0:bb348c97df44 2116 No need to enable the counter, it's enabled automatically by hardware
lypinator 0:bb348c97df44 2117 (the counter starts in response to a stimulus and generate a pulse */
lypinator 0:bb348c97df44 2118
lypinator 0:bb348c97df44 2119 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
lypinator 0:bb348c97df44 2120 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
lypinator 0:bb348c97df44 2121
lypinator 0:bb348c97df44 2122 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
lypinator 0:bb348c97df44 2123 {
lypinator 0:bb348c97df44 2124 /* Enable the main output */
lypinator 0:bb348c97df44 2125 __HAL_TIM_MOE_ENABLE(htim);
lypinator 0:bb348c97df44 2126 }
lypinator 0:bb348c97df44 2127
lypinator 0:bb348c97df44 2128 /* Return function status */
lypinator 0:bb348c97df44 2129 return HAL_OK;
lypinator 0:bb348c97df44 2130 }
lypinator 0:bb348c97df44 2131
lypinator 0:bb348c97df44 2132 /**
lypinator 0:bb348c97df44 2133 * @brief Stops the TIM One Pulse signal generation.
lypinator 0:bb348c97df44 2134 * @param htim pointer to a TIM_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 2135 * the configuration information for TIM module.
lypinator 0:bb348c97df44 2136 * @param OutputChannel TIM Channels to be disable.
lypinator 0:bb348c97df44 2137 * This parameter can be one of the following values:
lypinator 0:bb348c97df44 2138 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
lypinator 0:bb348c97df44 2139 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
lypinator 0:bb348c97df44 2140 * @retval HAL status
lypinator 0:bb348c97df44 2141 */
lypinator 0:bb348c97df44 2142 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
lypinator 0:bb348c97df44 2143 {
lypinator 0:bb348c97df44 2144 /* Prevent unused argument(s) compilation warning */
lypinator 0:bb348c97df44 2145 UNUSED(OutputChannel);
lypinator 0:bb348c97df44 2146
lypinator 0:bb348c97df44 2147 /* Disable the Capture compare and the Input Capture channels
lypinator 0:bb348c97df44 2148 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
lypinator 0:bb348c97df44 2149 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
lypinator 0:bb348c97df44 2150 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
lypinator 0:bb348c97df44 2151 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
lypinator 0:bb348c97df44 2152
lypinator 0:bb348c97df44 2153 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
lypinator 0:bb348c97df44 2154 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
lypinator 0:bb348c97df44 2155
lypinator 0:bb348c97df44 2156 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
lypinator 0:bb348c97df44 2157 {
lypinator 0:bb348c97df44 2158 /* Disable the Main Output */
lypinator 0:bb348c97df44 2159 __HAL_TIM_MOE_DISABLE(htim);
lypinator 0:bb348c97df44 2160 }
lypinator 0:bb348c97df44 2161
lypinator 0:bb348c97df44 2162 /* Disable the Peripheral */
lypinator 0:bb348c97df44 2163 __HAL_TIM_DISABLE(htim);
lypinator 0:bb348c97df44 2164
lypinator 0:bb348c97df44 2165 /* Return function status */
lypinator 0:bb348c97df44 2166 return HAL_OK;
lypinator 0:bb348c97df44 2167 }
lypinator 0:bb348c97df44 2168
lypinator 0:bb348c97df44 2169 /**
lypinator 0:bb348c97df44 2170 * @brief Starts the TIM One Pulse signal generation in interrupt mode.
lypinator 0:bb348c97df44 2171 * @param htim pointer to a TIM_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 2172 * the configuration information for TIM module.
lypinator 0:bb348c97df44 2173 * @param OutputChannel TIM Channels to be enabled.
lypinator 0:bb348c97df44 2174 * This parameter can be one of the following values:
lypinator 0:bb348c97df44 2175 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
lypinator 0:bb348c97df44 2176 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
lypinator 0:bb348c97df44 2177 * @retval HAL status
lypinator 0:bb348c97df44 2178 */
lypinator 0:bb348c97df44 2179 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
lypinator 0:bb348c97df44 2180 {
lypinator 0:bb348c97df44 2181 /* Enable the Capture compare and the Input Capture channels
lypinator 0:bb348c97df44 2182 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
lypinator 0:bb348c97df44 2183 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
lypinator 0:bb348c97df44 2184 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
lypinator 0:bb348c97df44 2185 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
lypinator 0:bb348c97df44 2186
lypinator 0:bb348c97df44 2187 No need to enable the counter, it's enabled automatically by hardware
lypinator 0:bb348c97df44 2188 (the counter starts in response to a stimulus and generate a pulse */
lypinator 0:bb348c97df44 2189
lypinator 0:bb348c97df44 2190 /* Prevent unused argument(s) compilation warning */
lypinator 0:bb348c97df44 2191 UNUSED(OutputChannel);
lypinator 0:bb348c97df44 2192
lypinator 0:bb348c97df44 2193 /* Enable the TIM Capture/Compare 1 interrupt */
lypinator 0:bb348c97df44 2194 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
lypinator 0:bb348c97df44 2195
lypinator 0:bb348c97df44 2196 /* Enable the TIM Capture/Compare 2 interrupt */
lypinator 0:bb348c97df44 2197 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
lypinator 0:bb348c97df44 2198
lypinator 0:bb348c97df44 2199 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
lypinator 0:bb348c97df44 2200 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
lypinator 0:bb348c97df44 2201
lypinator 0:bb348c97df44 2202 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
lypinator 0:bb348c97df44 2203 {
lypinator 0:bb348c97df44 2204 /* Enable the main output */
lypinator 0:bb348c97df44 2205 __HAL_TIM_MOE_ENABLE(htim);
lypinator 0:bb348c97df44 2206 }
lypinator 0:bb348c97df44 2207
lypinator 0:bb348c97df44 2208 /* Return function status */
lypinator 0:bb348c97df44 2209 return HAL_OK;
lypinator 0:bb348c97df44 2210 }
lypinator 0:bb348c97df44 2211
lypinator 0:bb348c97df44 2212 /**
lypinator 0:bb348c97df44 2213 * @brief Stops the TIM One Pulse signal generation in interrupt mode.
lypinator 0:bb348c97df44 2214 * @param htim pointer to a TIM_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 2215 * the configuration information for TIM module.
lypinator 0:bb348c97df44 2216 * @param OutputChannel TIM Channels to be enabled.
lypinator 0:bb348c97df44 2217 * This parameter can be one of the following values:
lypinator 0:bb348c97df44 2218 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
lypinator 0:bb348c97df44 2219 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
lypinator 0:bb348c97df44 2220 * @retval HAL status
lypinator 0:bb348c97df44 2221 */
lypinator 0:bb348c97df44 2222 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
lypinator 0:bb348c97df44 2223 {
lypinator 0:bb348c97df44 2224 /* Prevent unused argument(s) compilation warning */
lypinator 0:bb348c97df44 2225 UNUSED(OutputChannel);
lypinator 0:bb348c97df44 2226
lypinator 0:bb348c97df44 2227 /* Disable the TIM Capture/Compare 1 interrupt */
lypinator 0:bb348c97df44 2228 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
lypinator 0:bb348c97df44 2229
lypinator 0:bb348c97df44 2230 /* Disable the TIM Capture/Compare 2 interrupt */
lypinator 0:bb348c97df44 2231 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
lypinator 0:bb348c97df44 2232
lypinator 0:bb348c97df44 2233 /* Disable the Capture compare and the Input Capture channels
lypinator 0:bb348c97df44 2234 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
lypinator 0:bb348c97df44 2235 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
lypinator 0:bb348c97df44 2236 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
lypinator 0:bb348c97df44 2237 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
lypinator 0:bb348c97df44 2238 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
lypinator 0:bb348c97df44 2239 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
lypinator 0:bb348c97df44 2240
lypinator 0:bb348c97df44 2241 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
lypinator 0:bb348c97df44 2242 {
lypinator 0:bb348c97df44 2243 /* Disable the Main Output */
lypinator 0:bb348c97df44 2244 __HAL_TIM_MOE_DISABLE(htim);
lypinator 0:bb348c97df44 2245 }
lypinator 0:bb348c97df44 2246
lypinator 0:bb348c97df44 2247 /* Disable the Peripheral */
lypinator 0:bb348c97df44 2248 __HAL_TIM_DISABLE(htim);
lypinator 0:bb348c97df44 2249
lypinator 0:bb348c97df44 2250 /* Return function status */
lypinator 0:bb348c97df44 2251 return HAL_OK;
lypinator 0:bb348c97df44 2252 }
lypinator 0:bb348c97df44 2253 /**
lypinator 0:bb348c97df44 2254 * @}
lypinator 0:bb348c97df44 2255 */
lypinator 0:bb348c97df44 2256
lypinator 0:bb348c97df44 2257 /** @defgroup TIM_Exported_Functions_Group6 Time Encoder functions
lypinator 0:bb348c97df44 2258 * @brief Time Encoder functions
lypinator 0:bb348c97df44 2259 *
lypinator 0:bb348c97df44 2260 @verbatim
lypinator 0:bb348c97df44 2261 ==============================================================================
lypinator 0:bb348c97df44 2262 ##### Time Encoder functions #####
lypinator 0:bb348c97df44 2263 ==============================================================================
lypinator 0:bb348c97df44 2264 [..]
lypinator 0:bb348c97df44 2265 This section provides functions allowing to:
lypinator 0:bb348c97df44 2266 (+) Initialize and configure the TIM Encoder.
lypinator 0:bb348c97df44 2267 (+) De-initialize the TIM Encoder.
lypinator 0:bb348c97df44 2268 (+) Start the Time Encoder.
lypinator 0:bb348c97df44 2269 (+) Stop the Time Encoder.
lypinator 0:bb348c97df44 2270 (+) Start the Time Encoder and enable interrupt.
lypinator 0:bb348c97df44 2271 (+) Stop the Time Encoder and disable interrupt.
lypinator 0:bb348c97df44 2272 (+) Start the Time Encoder and enable DMA transfer.
lypinator 0:bb348c97df44 2273 (+) Stop the Time Encoder and disable DMA transfer.
lypinator 0:bb348c97df44 2274
lypinator 0:bb348c97df44 2275 @endverbatim
lypinator 0:bb348c97df44 2276 * @{
lypinator 0:bb348c97df44 2277 */
lypinator 0:bb348c97df44 2278 /**
lypinator 0:bb348c97df44 2279 * @brief Initializes the TIM Encoder Interface and create the associated handle.
lypinator 0:bb348c97df44 2280 * @param htim pointer to a TIM_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 2281 * the configuration information for TIM module.
lypinator 0:bb348c97df44 2282 * @param sConfig TIM Encoder Interface configuration structure
lypinator 0:bb348c97df44 2283 * @retval HAL status
lypinator 0:bb348c97df44 2284 */
lypinator 0:bb348c97df44 2285 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig)
lypinator 0:bb348c97df44 2286 {
lypinator 0:bb348c97df44 2287 uint32_t tmpsmcr = 0U;
lypinator 0:bb348c97df44 2288 uint32_t tmpccmr1 = 0U;
lypinator 0:bb348c97df44 2289 uint32_t tmpccer = 0U;
lypinator 0:bb348c97df44 2290
lypinator 0:bb348c97df44 2291 /* Check the TIM handle allocation */
lypinator 0:bb348c97df44 2292 if(htim == NULL)
lypinator 0:bb348c97df44 2293 {
lypinator 0:bb348c97df44 2294 return HAL_ERROR;
lypinator 0:bb348c97df44 2295 }
lypinator 0:bb348c97df44 2296
lypinator 0:bb348c97df44 2297 /* Check the parameters */
lypinator 0:bb348c97df44 2298 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
lypinator 0:bb348c97df44 2299 assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
lypinator 0:bb348c97df44 2300 assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
lypinator 0:bb348c97df44 2301 assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
lypinator 0:bb348c97df44 2302 assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
lypinator 0:bb348c97df44 2303 assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity));
lypinator 0:bb348c97df44 2304 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
lypinator 0:bb348c97df44 2305 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
lypinator 0:bb348c97df44 2306 assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
lypinator 0:bb348c97df44 2307 assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
lypinator 0:bb348c97df44 2308
lypinator 0:bb348c97df44 2309 if(htim->State == HAL_TIM_STATE_RESET)
lypinator 0:bb348c97df44 2310 {
lypinator 0:bb348c97df44 2311 /* Allocate lock resource and initialize it */
lypinator 0:bb348c97df44 2312 htim->Lock = HAL_UNLOCKED;
lypinator 0:bb348c97df44 2313 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
lypinator 0:bb348c97df44 2314 HAL_TIM_Encoder_MspInit(htim);
lypinator 0:bb348c97df44 2315 }
lypinator 0:bb348c97df44 2316
lypinator 0:bb348c97df44 2317 /* Set the TIM state */
lypinator 0:bb348c97df44 2318 htim->State= HAL_TIM_STATE_BUSY;
lypinator 0:bb348c97df44 2319
lypinator 0:bb348c97df44 2320 /* Reset the SMS bits */
lypinator 0:bb348c97df44 2321 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
lypinator 0:bb348c97df44 2322
lypinator 0:bb348c97df44 2323 /* Configure the Time base in the Encoder Mode */
lypinator 0:bb348c97df44 2324 TIM_Base_SetConfig(htim->Instance, &htim->Init);
lypinator 0:bb348c97df44 2325
lypinator 0:bb348c97df44 2326 /* Get the TIMx SMCR register value */
lypinator 0:bb348c97df44 2327 tmpsmcr = htim->Instance->SMCR;
lypinator 0:bb348c97df44 2328
lypinator 0:bb348c97df44 2329 /* Get the TIMx CCMR1 register value */
lypinator 0:bb348c97df44 2330 tmpccmr1 = htim->Instance->CCMR1;
lypinator 0:bb348c97df44 2331
lypinator 0:bb348c97df44 2332 /* Get the TIMx CCER register value */
lypinator 0:bb348c97df44 2333 tmpccer = htim->Instance->CCER;
lypinator 0:bb348c97df44 2334
lypinator 0:bb348c97df44 2335 /* Set the encoder Mode */
lypinator 0:bb348c97df44 2336 tmpsmcr |= sConfig->EncoderMode;
lypinator 0:bb348c97df44 2337
lypinator 0:bb348c97df44 2338 /* Select the Capture Compare 1 and the Capture Compare 2 as input */
lypinator 0:bb348c97df44 2339 tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
lypinator 0:bb348c97df44 2340 tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U));
lypinator 0:bb348c97df44 2341
lypinator 0:bb348c97df44 2342 /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
lypinator 0:bb348c97df44 2343 tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
lypinator 0:bb348c97df44 2344 tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
lypinator 0:bb348c97df44 2345 tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);
lypinator 0:bb348c97df44 2346 tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
lypinator 0:bb348c97df44 2347
lypinator 0:bb348c97df44 2348 /* Set the TI1 and the TI2 Polarities */
lypinator 0:bb348c97df44 2349 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
lypinator 0:bb348c97df44 2350 tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
lypinator 0:bb348c97df44 2351 tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);
lypinator 0:bb348c97df44 2352
lypinator 0:bb348c97df44 2353 /* Write to TIMx SMCR */
lypinator 0:bb348c97df44 2354 htim->Instance->SMCR = tmpsmcr;
lypinator 0:bb348c97df44 2355
lypinator 0:bb348c97df44 2356 /* Write to TIMx CCMR1 */
lypinator 0:bb348c97df44 2357 htim->Instance->CCMR1 = tmpccmr1;
lypinator 0:bb348c97df44 2358
lypinator 0:bb348c97df44 2359 /* Write to TIMx CCER */
lypinator 0:bb348c97df44 2360 htim->Instance->CCER = tmpccer;
lypinator 0:bb348c97df44 2361
lypinator 0:bb348c97df44 2362 /* Initialize the TIM state*/
lypinator 0:bb348c97df44 2363 htim->State= HAL_TIM_STATE_READY;
lypinator 0:bb348c97df44 2364
lypinator 0:bb348c97df44 2365 return HAL_OK;
lypinator 0:bb348c97df44 2366 }
lypinator 0:bb348c97df44 2367
lypinator 0:bb348c97df44 2368 /**
lypinator 0:bb348c97df44 2369 * @brief DeInitializes the TIM Encoder interface
lypinator 0:bb348c97df44 2370 * @param htim pointer to a TIM_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 2371 * the configuration information for TIM module.
lypinator 0:bb348c97df44 2372 * @retval HAL status
lypinator 0:bb348c97df44 2373 */
lypinator 0:bb348c97df44 2374 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
lypinator 0:bb348c97df44 2375 {
lypinator 0:bb348c97df44 2376 /* Check the parameters */
lypinator 0:bb348c97df44 2377 assert_param(IS_TIM_INSTANCE(htim->Instance));
lypinator 0:bb348c97df44 2378
lypinator 0:bb348c97df44 2379 htim->State = HAL_TIM_STATE_BUSY;
lypinator 0:bb348c97df44 2380
lypinator 0:bb348c97df44 2381 /* Disable the TIM Peripheral Clock */
lypinator 0:bb348c97df44 2382 __HAL_TIM_DISABLE(htim);
lypinator 0:bb348c97df44 2383
lypinator 0:bb348c97df44 2384 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
lypinator 0:bb348c97df44 2385 HAL_TIM_Encoder_MspDeInit(htim);
lypinator 0:bb348c97df44 2386
lypinator 0:bb348c97df44 2387 /* Change TIM state */
lypinator 0:bb348c97df44 2388 htim->State = HAL_TIM_STATE_RESET;
lypinator 0:bb348c97df44 2389
lypinator 0:bb348c97df44 2390 /* Release Lock */
lypinator 0:bb348c97df44 2391 __HAL_UNLOCK(htim);
lypinator 0:bb348c97df44 2392
lypinator 0:bb348c97df44 2393 return HAL_OK;
lypinator 0:bb348c97df44 2394 }
lypinator 0:bb348c97df44 2395
lypinator 0:bb348c97df44 2396 /**
lypinator 0:bb348c97df44 2397 * @brief Initializes the TIM Encoder Interface MSP.
lypinator 0:bb348c97df44 2398 * @param htim pointer to a TIM_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 2399 * the configuration information for TIM module.
lypinator 0:bb348c97df44 2400 * @retval None
lypinator 0:bb348c97df44 2401 */
lypinator 0:bb348c97df44 2402 __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
lypinator 0:bb348c97df44 2403 {
lypinator 0:bb348c97df44 2404 /* Prevent unused argument(s) compilation warning */
lypinator 0:bb348c97df44 2405 UNUSED(htim);
lypinator 0:bb348c97df44 2406 /* NOTE : This function Should not be modified, when the callback is needed,
lypinator 0:bb348c97df44 2407 the HAL_TIM_Encoder_MspInit could be implemented in the user file
lypinator 0:bb348c97df44 2408 */
lypinator 0:bb348c97df44 2409 }
lypinator 0:bb348c97df44 2410
lypinator 0:bb348c97df44 2411 /**
lypinator 0:bb348c97df44 2412 * @brief DeInitializes TIM Encoder Interface MSP.
lypinator 0:bb348c97df44 2413 * @param htim pointer to a TIM_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 2414 * the configuration information for TIM module.
lypinator 0:bb348c97df44 2415 * @retval None
lypinator 0:bb348c97df44 2416 */
lypinator 0:bb348c97df44 2417 __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
lypinator 0:bb348c97df44 2418 {
lypinator 0:bb348c97df44 2419 /* Prevent unused argument(s) compilation warning */
lypinator 0:bb348c97df44 2420 UNUSED(htim);
lypinator 0:bb348c97df44 2421 /* NOTE : This function Should not be modified, when the callback is needed,
lypinator 0:bb348c97df44 2422 the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
lypinator 0:bb348c97df44 2423 */
lypinator 0:bb348c97df44 2424 }
lypinator 0:bb348c97df44 2425
lypinator 0:bb348c97df44 2426 /**
lypinator 0:bb348c97df44 2427 * @brief Starts the TIM Encoder Interface.
lypinator 0:bb348c97df44 2428 * @param htim pointer to a TIM_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 2429 * the configuration information for TIM module.
lypinator 0:bb348c97df44 2430 * @param Channel TIM Channels to be enabled.
lypinator 0:bb348c97df44 2431 * This parameter can be one of the following values:
lypinator 0:bb348c97df44 2432 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
lypinator 0:bb348c97df44 2433 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
lypinator 0:bb348c97df44 2434 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
lypinator 0:bb348c97df44 2435 * @retval HAL status
lypinator 0:bb348c97df44 2436 */
lypinator 0:bb348c97df44 2437 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
lypinator 0:bb348c97df44 2438 {
lypinator 0:bb348c97df44 2439 /* Check the parameters */
lypinator 0:bb348c97df44 2440 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
lypinator 0:bb348c97df44 2441
lypinator 0:bb348c97df44 2442 /* Enable the encoder interface channels */
lypinator 0:bb348c97df44 2443 switch (Channel)
lypinator 0:bb348c97df44 2444 {
lypinator 0:bb348c97df44 2445 case TIM_CHANNEL_1:
lypinator 0:bb348c97df44 2446 {
lypinator 0:bb348c97df44 2447 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
lypinator 0:bb348c97df44 2448 break;
lypinator 0:bb348c97df44 2449 }
lypinator 0:bb348c97df44 2450 case TIM_CHANNEL_2:
lypinator 0:bb348c97df44 2451 {
lypinator 0:bb348c97df44 2452 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
lypinator 0:bb348c97df44 2453 break;
lypinator 0:bb348c97df44 2454 }
lypinator 0:bb348c97df44 2455 default :
lypinator 0:bb348c97df44 2456 {
lypinator 0:bb348c97df44 2457 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
lypinator 0:bb348c97df44 2458 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
lypinator 0:bb348c97df44 2459 break;
lypinator 0:bb348c97df44 2460 }
lypinator 0:bb348c97df44 2461 }
lypinator 0:bb348c97df44 2462 /* Enable the Peripheral */
lypinator 0:bb348c97df44 2463 __HAL_TIM_ENABLE(htim);
lypinator 0:bb348c97df44 2464
lypinator 0:bb348c97df44 2465 /* Return function status */
lypinator 0:bb348c97df44 2466 return HAL_OK;
lypinator 0:bb348c97df44 2467 }
lypinator 0:bb348c97df44 2468
lypinator 0:bb348c97df44 2469 /**
lypinator 0:bb348c97df44 2470 * @brief Stops the TIM Encoder Interface.
lypinator 0:bb348c97df44 2471 * @param htim pointer to a TIM_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 2472 * the configuration information for TIM module.
lypinator 0:bb348c97df44 2473 * @param Channel TIM Channels to be disabled.
lypinator 0:bb348c97df44 2474 * This parameter can be one of the following values:
lypinator 0:bb348c97df44 2475 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
lypinator 0:bb348c97df44 2476 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
lypinator 0:bb348c97df44 2477 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
lypinator 0:bb348c97df44 2478 * @retval HAL status
lypinator 0:bb348c97df44 2479 */
lypinator 0:bb348c97df44 2480 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
lypinator 0:bb348c97df44 2481 {
lypinator 0:bb348c97df44 2482 /* Check the parameters */
lypinator 0:bb348c97df44 2483 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
lypinator 0:bb348c97df44 2484
lypinator 0:bb348c97df44 2485 /* Disable the Input Capture channels 1 and 2
lypinator 0:bb348c97df44 2486 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
lypinator 0:bb348c97df44 2487 switch (Channel)
lypinator 0:bb348c97df44 2488 {
lypinator 0:bb348c97df44 2489 case TIM_CHANNEL_1:
lypinator 0:bb348c97df44 2490 {
lypinator 0:bb348c97df44 2491 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
lypinator 0:bb348c97df44 2492 break;
lypinator 0:bb348c97df44 2493 }
lypinator 0:bb348c97df44 2494 case TIM_CHANNEL_2:
lypinator 0:bb348c97df44 2495 {
lypinator 0:bb348c97df44 2496 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
lypinator 0:bb348c97df44 2497 break;
lypinator 0:bb348c97df44 2498 }
lypinator 0:bb348c97df44 2499 default :
lypinator 0:bb348c97df44 2500 {
lypinator 0:bb348c97df44 2501 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
lypinator 0:bb348c97df44 2502 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
lypinator 0:bb348c97df44 2503 break;
lypinator 0:bb348c97df44 2504 }
lypinator 0:bb348c97df44 2505 }
lypinator 0:bb348c97df44 2506 /* Disable the Peripheral */
lypinator 0:bb348c97df44 2507 __HAL_TIM_DISABLE(htim);
lypinator 0:bb348c97df44 2508
lypinator 0:bb348c97df44 2509 /* Return function status */
lypinator 0:bb348c97df44 2510 return HAL_OK;
lypinator 0:bb348c97df44 2511 }
lypinator 0:bb348c97df44 2512
lypinator 0:bb348c97df44 2513 /**
lypinator 0:bb348c97df44 2514 * @brief Starts the TIM Encoder Interface in interrupt mode.
lypinator 0:bb348c97df44 2515 * @param htim pointer to a TIM_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 2516 * the configuration information for TIM module.
lypinator 0:bb348c97df44 2517 * @param Channel TIM Channels to be enabled.
lypinator 0:bb348c97df44 2518 * This parameter can be one of the following values:
lypinator 0:bb348c97df44 2519 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
lypinator 0:bb348c97df44 2520 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
lypinator 0:bb348c97df44 2521 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
lypinator 0:bb348c97df44 2522 * @retval HAL status
lypinator 0:bb348c97df44 2523 */
lypinator 0:bb348c97df44 2524 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
lypinator 0:bb348c97df44 2525 {
lypinator 0:bb348c97df44 2526 /* Check the parameters */
lypinator 0:bb348c97df44 2527 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
lypinator 0:bb348c97df44 2528
lypinator 0:bb348c97df44 2529 /* Enable the encoder interface channels */
lypinator 0:bb348c97df44 2530 /* Enable the capture compare Interrupts 1 and/or 2 */
lypinator 0:bb348c97df44 2531 switch (Channel)
lypinator 0:bb348c97df44 2532 {
lypinator 0:bb348c97df44 2533 case TIM_CHANNEL_1:
lypinator 0:bb348c97df44 2534 {
lypinator 0:bb348c97df44 2535 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
lypinator 0:bb348c97df44 2536 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
lypinator 0:bb348c97df44 2537 break;
lypinator 0:bb348c97df44 2538 }
lypinator 0:bb348c97df44 2539 case TIM_CHANNEL_2:
lypinator 0:bb348c97df44 2540 {
lypinator 0:bb348c97df44 2541 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
lypinator 0:bb348c97df44 2542 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
lypinator 0:bb348c97df44 2543 break;
lypinator 0:bb348c97df44 2544 }
lypinator 0:bb348c97df44 2545 default :
lypinator 0:bb348c97df44 2546 {
lypinator 0:bb348c97df44 2547 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
lypinator 0:bb348c97df44 2548 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
lypinator 0:bb348c97df44 2549 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
lypinator 0:bb348c97df44 2550 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
lypinator 0:bb348c97df44 2551 break;
lypinator 0:bb348c97df44 2552 }
lypinator 0:bb348c97df44 2553 }
lypinator 0:bb348c97df44 2554
lypinator 0:bb348c97df44 2555 /* Enable the Peripheral */
lypinator 0:bb348c97df44 2556 __HAL_TIM_ENABLE(htim);
lypinator 0:bb348c97df44 2557
lypinator 0:bb348c97df44 2558 /* Return function status */
lypinator 0:bb348c97df44 2559 return HAL_OK;
lypinator 0:bb348c97df44 2560 }
lypinator 0:bb348c97df44 2561
lypinator 0:bb348c97df44 2562 /**
lypinator 0:bb348c97df44 2563 * @brief Stops the TIM Encoder Interface in interrupt mode.
lypinator 0:bb348c97df44 2564 * @param htim pointer to a TIM_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 2565 * the configuration information for TIM module.
lypinator 0:bb348c97df44 2566 * @param Channel TIM Channels to be disabled.
lypinator 0:bb348c97df44 2567 * This parameter can be one of the following values:
lypinator 0:bb348c97df44 2568 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
lypinator 0:bb348c97df44 2569 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
lypinator 0:bb348c97df44 2570 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
lypinator 0:bb348c97df44 2571 * @retval HAL status
lypinator 0:bb348c97df44 2572 */
lypinator 0:bb348c97df44 2573 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
lypinator 0:bb348c97df44 2574 {
lypinator 0:bb348c97df44 2575 /* Check the parameters */
lypinator 0:bb348c97df44 2576 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
lypinator 0:bb348c97df44 2577
lypinator 0:bb348c97df44 2578 /* Disable the Input Capture channels 1 and 2
lypinator 0:bb348c97df44 2579 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
lypinator 0:bb348c97df44 2580 if(Channel == TIM_CHANNEL_1)
lypinator 0:bb348c97df44 2581 {
lypinator 0:bb348c97df44 2582 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
lypinator 0:bb348c97df44 2583
lypinator 0:bb348c97df44 2584 /* Disable the capture compare Interrupts 1 */
lypinator 0:bb348c97df44 2585 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
lypinator 0:bb348c97df44 2586 }
lypinator 0:bb348c97df44 2587 else if(Channel == TIM_CHANNEL_2)
lypinator 0:bb348c97df44 2588 {
lypinator 0:bb348c97df44 2589 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
lypinator 0:bb348c97df44 2590
lypinator 0:bb348c97df44 2591 /* Disable the capture compare Interrupts 2 */
lypinator 0:bb348c97df44 2592 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
lypinator 0:bb348c97df44 2593 }
lypinator 0:bb348c97df44 2594 else
lypinator 0:bb348c97df44 2595 {
lypinator 0:bb348c97df44 2596 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
lypinator 0:bb348c97df44 2597 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
lypinator 0:bb348c97df44 2598
lypinator 0:bb348c97df44 2599 /* Disable the capture compare Interrupts 1 and 2 */
lypinator 0:bb348c97df44 2600 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
lypinator 0:bb348c97df44 2601 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
lypinator 0:bb348c97df44 2602 }
lypinator 0:bb348c97df44 2603
lypinator 0:bb348c97df44 2604 /* Disable the Peripheral */
lypinator 0:bb348c97df44 2605 __HAL_TIM_DISABLE(htim);
lypinator 0:bb348c97df44 2606
lypinator 0:bb348c97df44 2607 /* Change the htim state */
lypinator 0:bb348c97df44 2608 htim->State = HAL_TIM_STATE_READY;
lypinator 0:bb348c97df44 2609
lypinator 0:bb348c97df44 2610 /* Return function status */
lypinator 0:bb348c97df44 2611 return HAL_OK;
lypinator 0:bb348c97df44 2612 }
lypinator 0:bb348c97df44 2613
lypinator 0:bb348c97df44 2614 /**
lypinator 0:bb348c97df44 2615 * @brief Starts the TIM Encoder Interface in DMA mode.
lypinator 0:bb348c97df44 2616 * @param htim pointer to a TIM_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 2617 * the configuration information for TIM module.
lypinator 0:bb348c97df44 2618 * @param Channel TIM Channels to be enabled.
lypinator 0:bb348c97df44 2619 * This parameter can be one of the following values:
lypinator 0:bb348c97df44 2620 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
lypinator 0:bb348c97df44 2621 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
lypinator 0:bb348c97df44 2622 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
lypinator 0:bb348c97df44 2623 * @param pData1 The destination Buffer address for IC1.
lypinator 0:bb348c97df44 2624 * @param pData2 The destination Buffer address for IC2.
lypinator 0:bb348c97df44 2625 * @param Length The length of data to be transferred from TIM peripheral to memory.
lypinator 0:bb348c97df44 2626 * @retval HAL status
lypinator 0:bb348c97df44 2627 */
lypinator 0:bb348c97df44 2628 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length)
lypinator 0:bb348c97df44 2629 {
lypinator 0:bb348c97df44 2630 /* Check the parameters */
lypinator 0:bb348c97df44 2631 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
lypinator 0:bb348c97df44 2632
lypinator 0:bb348c97df44 2633 if((htim->State == HAL_TIM_STATE_BUSY))
lypinator 0:bb348c97df44 2634 {
lypinator 0:bb348c97df44 2635 return HAL_BUSY;
lypinator 0:bb348c97df44 2636 }
lypinator 0:bb348c97df44 2637 else if((htim->State == HAL_TIM_STATE_READY))
lypinator 0:bb348c97df44 2638 {
lypinator 0:bb348c97df44 2639 if((((pData1 == 0U) || (pData2 == 0U) )) && (Length > 0))
lypinator 0:bb348c97df44 2640 {
lypinator 0:bb348c97df44 2641 return HAL_ERROR;
lypinator 0:bb348c97df44 2642 }
lypinator 0:bb348c97df44 2643 else
lypinator 0:bb348c97df44 2644 {
lypinator 0:bb348c97df44 2645 htim->State = HAL_TIM_STATE_BUSY;
lypinator 0:bb348c97df44 2646 }
lypinator 0:bb348c97df44 2647 }
lypinator 0:bb348c97df44 2648
lypinator 0:bb348c97df44 2649 switch (Channel)
lypinator 0:bb348c97df44 2650 {
lypinator 0:bb348c97df44 2651 case TIM_CHANNEL_1:
lypinator 0:bb348c97df44 2652 {
lypinator 0:bb348c97df44 2653 /* Set the DMA Period elapsed callback */
lypinator 0:bb348c97df44 2654 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
lypinator 0:bb348c97df44 2655
lypinator 0:bb348c97df44 2656 /* Set the DMA error callback */
lypinator 0:bb348c97df44 2657 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
lypinator 0:bb348c97df44 2658
lypinator 0:bb348c97df44 2659 /* Enable the DMA Stream */
lypinator 0:bb348c97df44 2660 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t )pData1, Length);
lypinator 0:bb348c97df44 2661
lypinator 0:bb348c97df44 2662 /* Enable the TIM Input Capture DMA request */
lypinator 0:bb348c97df44 2663 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
lypinator 0:bb348c97df44 2664
lypinator 0:bb348c97df44 2665 /* Enable the Peripheral */
lypinator 0:bb348c97df44 2666 __HAL_TIM_ENABLE(htim);
lypinator 0:bb348c97df44 2667
lypinator 0:bb348c97df44 2668 /* Enable the Capture compare channel */
lypinator 0:bb348c97df44 2669 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
lypinator 0:bb348c97df44 2670 }
lypinator 0:bb348c97df44 2671 break;
lypinator 0:bb348c97df44 2672
lypinator 0:bb348c97df44 2673 case TIM_CHANNEL_2:
lypinator 0:bb348c97df44 2674 {
lypinator 0:bb348c97df44 2675 /* Set the DMA Period elapsed callback */
lypinator 0:bb348c97df44 2676 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
lypinator 0:bb348c97df44 2677
lypinator 0:bb348c97df44 2678 /* Set the DMA error callback */
lypinator 0:bb348c97df44 2679 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
lypinator 0:bb348c97df44 2680 /* Enable the DMA Stream */
lypinator 0:bb348c97df44 2681 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
lypinator 0:bb348c97df44 2682
lypinator 0:bb348c97df44 2683 /* Enable the TIM Input Capture DMA request */
lypinator 0:bb348c97df44 2684 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
lypinator 0:bb348c97df44 2685
lypinator 0:bb348c97df44 2686 /* Enable the Peripheral */
lypinator 0:bb348c97df44 2687 __HAL_TIM_ENABLE(htim);
lypinator 0:bb348c97df44 2688
lypinator 0:bb348c97df44 2689 /* Enable the Capture compare channel */
lypinator 0:bb348c97df44 2690 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
lypinator 0:bb348c97df44 2691 }
lypinator 0:bb348c97df44 2692 break;
lypinator 0:bb348c97df44 2693
lypinator 0:bb348c97df44 2694 case TIM_CHANNEL_ALL:
lypinator 0:bb348c97df44 2695 {
lypinator 0:bb348c97df44 2696 /* Set the DMA Period elapsed callback */
lypinator 0:bb348c97df44 2697 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
lypinator 0:bb348c97df44 2698
lypinator 0:bb348c97df44 2699 /* Set the DMA error callback */
lypinator 0:bb348c97df44 2700 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
lypinator 0:bb348c97df44 2701
lypinator 0:bb348c97df44 2702 /* Enable the DMA Stream */
lypinator 0:bb348c97df44 2703 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length);
lypinator 0:bb348c97df44 2704
lypinator 0:bb348c97df44 2705 /* Set the DMA Period elapsed callback */
lypinator 0:bb348c97df44 2706 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
lypinator 0:bb348c97df44 2707
lypinator 0:bb348c97df44 2708 /* Set the DMA error callback */
lypinator 0:bb348c97df44 2709 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
lypinator 0:bb348c97df44 2710
lypinator 0:bb348c97df44 2711 /* Enable the DMA Stream */
lypinator 0:bb348c97df44 2712 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
lypinator 0:bb348c97df44 2713
lypinator 0:bb348c97df44 2714 /* Enable the Peripheral */
lypinator 0:bb348c97df44 2715 __HAL_TIM_ENABLE(htim);
lypinator 0:bb348c97df44 2716
lypinator 0:bb348c97df44 2717 /* Enable the Capture compare channel */
lypinator 0:bb348c97df44 2718 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
lypinator 0:bb348c97df44 2719 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
lypinator 0:bb348c97df44 2720
lypinator 0:bb348c97df44 2721 /* Enable the TIM Input Capture DMA request */
lypinator 0:bb348c97df44 2722 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
lypinator 0:bb348c97df44 2723 /* Enable the TIM Input Capture DMA request */
lypinator 0:bb348c97df44 2724 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
lypinator 0:bb348c97df44 2725 }
lypinator 0:bb348c97df44 2726 break;
lypinator 0:bb348c97df44 2727
lypinator 0:bb348c97df44 2728 default:
lypinator 0:bb348c97df44 2729 break;
lypinator 0:bb348c97df44 2730 }
lypinator 0:bb348c97df44 2731 /* Return function status */
lypinator 0:bb348c97df44 2732 return HAL_OK;
lypinator 0:bb348c97df44 2733 }
lypinator 0:bb348c97df44 2734
lypinator 0:bb348c97df44 2735 /**
lypinator 0:bb348c97df44 2736 * @brief Stops the TIM Encoder Interface in DMA mode.
lypinator 0:bb348c97df44 2737 * @param htim pointer to a TIM_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 2738 * the configuration information for TIM module.
lypinator 0:bb348c97df44 2739 * @param Channel TIM Channels to be enabled.
lypinator 0:bb348c97df44 2740 * This parameter can be one of the following values:
lypinator 0:bb348c97df44 2741 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
lypinator 0:bb348c97df44 2742 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
lypinator 0:bb348c97df44 2743 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
lypinator 0:bb348c97df44 2744 * @retval HAL status
lypinator 0:bb348c97df44 2745 */
lypinator 0:bb348c97df44 2746 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
lypinator 0:bb348c97df44 2747 {
lypinator 0:bb348c97df44 2748 /* Check the parameters */
lypinator 0:bb348c97df44 2749 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
lypinator 0:bb348c97df44 2750
lypinator 0:bb348c97df44 2751 /* Disable the Input Capture channels 1 and 2
lypinator 0:bb348c97df44 2752 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
lypinator 0:bb348c97df44 2753 if(Channel == TIM_CHANNEL_1)
lypinator 0:bb348c97df44 2754 {
lypinator 0:bb348c97df44 2755 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
lypinator 0:bb348c97df44 2756
lypinator 0:bb348c97df44 2757 /* Disable the capture compare DMA Request 1 */
lypinator 0:bb348c97df44 2758 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
lypinator 0:bb348c97df44 2759 }
lypinator 0:bb348c97df44 2760 else if(Channel == TIM_CHANNEL_2)
lypinator 0:bb348c97df44 2761 {
lypinator 0:bb348c97df44 2762 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
lypinator 0:bb348c97df44 2763
lypinator 0:bb348c97df44 2764 /* Disable the capture compare DMA Request 2 */
lypinator 0:bb348c97df44 2765 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
lypinator 0:bb348c97df44 2766 }
lypinator 0:bb348c97df44 2767 else
lypinator 0:bb348c97df44 2768 {
lypinator 0:bb348c97df44 2769 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
lypinator 0:bb348c97df44 2770 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
lypinator 0:bb348c97df44 2771
lypinator 0:bb348c97df44 2772 /* Disable the capture compare DMA Request 1 and 2 */
lypinator 0:bb348c97df44 2773 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
lypinator 0:bb348c97df44 2774 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
lypinator 0:bb348c97df44 2775 }
lypinator 0:bb348c97df44 2776
lypinator 0:bb348c97df44 2777 /* Disable the Peripheral */
lypinator 0:bb348c97df44 2778 __HAL_TIM_DISABLE(htim);
lypinator 0:bb348c97df44 2779
lypinator 0:bb348c97df44 2780 /* Change the htim state */
lypinator 0:bb348c97df44 2781 htim->State = HAL_TIM_STATE_READY;
lypinator 0:bb348c97df44 2782
lypinator 0:bb348c97df44 2783 /* Return function status */
lypinator 0:bb348c97df44 2784 return HAL_OK;
lypinator 0:bb348c97df44 2785 }
lypinator 0:bb348c97df44 2786 /**
lypinator 0:bb348c97df44 2787 * @}
lypinator 0:bb348c97df44 2788 */
lypinator 0:bb348c97df44 2789
lypinator 0:bb348c97df44 2790 /** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
lypinator 0:bb348c97df44 2791 * @brief IRQ handler management
lypinator 0:bb348c97df44 2792 *
lypinator 0:bb348c97df44 2793 @verbatim
lypinator 0:bb348c97df44 2794 ==============================================================================
lypinator 0:bb348c97df44 2795 ##### IRQ handler management #####
lypinator 0:bb348c97df44 2796 ==============================================================================
lypinator 0:bb348c97df44 2797 [..]
lypinator 0:bb348c97df44 2798 This section provides Timer IRQ handler function.
lypinator 0:bb348c97df44 2799
lypinator 0:bb348c97df44 2800 @endverbatim
lypinator 0:bb348c97df44 2801 * @{
lypinator 0:bb348c97df44 2802 */
lypinator 0:bb348c97df44 2803 /**
lypinator 0:bb348c97df44 2804 * @brief This function handles TIM interrupts requests.
lypinator 0:bb348c97df44 2805 * @param htim pointer to a TIM_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 2806 * the configuration information for TIM module.
lypinator 0:bb348c97df44 2807 * @retval None
lypinator 0:bb348c97df44 2808 */
lypinator 0:bb348c97df44 2809 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
lypinator 0:bb348c97df44 2810 {
lypinator 0:bb348c97df44 2811 /* Capture compare 1 event */
lypinator 0:bb348c97df44 2812 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
lypinator 0:bb348c97df44 2813 {
lypinator 0:bb348c97df44 2814 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) !=RESET)
lypinator 0:bb348c97df44 2815 {
lypinator 0:bb348c97df44 2816 {
lypinator 0:bb348c97df44 2817 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
lypinator 0:bb348c97df44 2818 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
lypinator 0:bb348c97df44 2819
lypinator 0:bb348c97df44 2820 /* Input capture event */
lypinator 0:bb348c97df44 2821 if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
lypinator 0:bb348c97df44 2822 {
lypinator 0:bb348c97df44 2823 HAL_TIM_IC_CaptureCallback(htim);
lypinator 0:bb348c97df44 2824 }
lypinator 0:bb348c97df44 2825 /* Output compare event */
lypinator 0:bb348c97df44 2826 else
lypinator 0:bb348c97df44 2827 {
lypinator 0:bb348c97df44 2828 HAL_TIM_OC_DelayElapsedCallback(htim);
lypinator 0:bb348c97df44 2829 HAL_TIM_PWM_PulseFinishedCallback(htim);
lypinator 0:bb348c97df44 2830 }
lypinator 0:bb348c97df44 2831 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
lypinator 0:bb348c97df44 2832 }
lypinator 0:bb348c97df44 2833 }
lypinator 0:bb348c97df44 2834 }
lypinator 0:bb348c97df44 2835 /* Capture compare 2 event */
lypinator 0:bb348c97df44 2836 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
lypinator 0:bb348c97df44 2837 {
lypinator 0:bb348c97df44 2838 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) !=RESET)
lypinator 0:bb348c97df44 2839 {
lypinator 0:bb348c97df44 2840 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
lypinator 0:bb348c97df44 2841 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
lypinator 0:bb348c97df44 2842 /* Input capture event */
lypinator 0:bb348c97df44 2843 if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
lypinator 0:bb348c97df44 2844 {
lypinator 0:bb348c97df44 2845 HAL_TIM_IC_CaptureCallback(htim);
lypinator 0:bb348c97df44 2846 }
lypinator 0:bb348c97df44 2847 /* Output compare event */
lypinator 0:bb348c97df44 2848 else
lypinator 0:bb348c97df44 2849 {
lypinator 0:bb348c97df44 2850 HAL_TIM_OC_DelayElapsedCallback(htim);
lypinator 0:bb348c97df44 2851 HAL_TIM_PWM_PulseFinishedCallback(htim);
lypinator 0:bb348c97df44 2852 }
lypinator 0:bb348c97df44 2853 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
lypinator 0:bb348c97df44 2854 }
lypinator 0:bb348c97df44 2855 }
lypinator 0:bb348c97df44 2856 /* Capture compare 3 event */
lypinator 0:bb348c97df44 2857 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
lypinator 0:bb348c97df44 2858 {
lypinator 0:bb348c97df44 2859 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) !=RESET)
lypinator 0:bb348c97df44 2860 {
lypinator 0:bb348c97df44 2861 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
lypinator 0:bb348c97df44 2862 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
lypinator 0:bb348c97df44 2863 /* Input capture event */
lypinator 0:bb348c97df44 2864 if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
lypinator 0:bb348c97df44 2865 {
lypinator 0:bb348c97df44 2866 HAL_TIM_IC_CaptureCallback(htim);
lypinator 0:bb348c97df44 2867 }
lypinator 0:bb348c97df44 2868 /* Output compare event */
lypinator 0:bb348c97df44 2869 else
lypinator 0:bb348c97df44 2870 {
lypinator 0:bb348c97df44 2871 HAL_TIM_OC_DelayElapsedCallback(htim);
lypinator 0:bb348c97df44 2872 HAL_TIM_PWM_PulseFinishedCallback(htim);
lypinator 0:bb348c97df44 2873 }
lypinator 0:bb348c97df44 2874 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
lypinator 0:bb348c97df44 2875 }
lypinator 0:bb348c97df44 2876 }
lypinator 0:bb348c97df44 2877 /* Capture compare 4 event */
lypinator 0:bb348c97df44 2878 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
lypinator 0:bb348c97df44 2879 {
lypinator 0:bb348c97df44 2880 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) !=RESET)
lypinator 0:bb348c97df44 2881 {
lypinator 0:bb348c97df44 2882 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
lypinator 0:bb348c97df44 2883 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
lypinator 0:bb348c97df44 2884 /* Input capture event */
lypinator 0:bb348c97df44 2885 if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
lypinator 0:bb348c97df44 2886 {
lypinator 0:bb348c97df44 2887 HAL_TIM_IC_CaptureCallback(htim);
lypinator 0:bb348c97df44 2888 }
lypinator 0:bb348c97df44 2889 /* Output compare event */
lypinator 0:bb348c97df44 2890 else
lypinator 0:bb348c97df44 2891 {
lypinator 0:bb348c97df44 2892 HAL_TIM_OC_DelayElapsedCallback(htim);
lypinator 0:bb348c97df44 2893 HAL_TIM_PWM_PulseFinishedCallback(htim);
lypinator 0:bb348c97df44 2894 }
lypinator 0:bb348c97df44 2895 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
lypinator 0:bb348c97df44 2896 }
lypinator 0:bb348c97df44 2897 }
lypinator 0:bb348c97df44 2898 /* TIM Update event */
lypinator 0:bb348c97df44 2899 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
lypinator 0:bb348c97df44 2900 {
lypinator 0:bb348c97df44 2901 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) !=RESET)
lypinator 0:bb348c97df44 2902 {
lypinator 0:bb348c97df44 2903 __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
lypinator 0:bb348c97df44 2904 HAL_TIM_PeriodElapsedCallback(htim);
lypinator 0:bb348c97df44 2905 }
lypinator 0:bb348c97df44 2906 }
lypinator 0:bb348c97df44 2907 /* TIM Break input event */
lypinator 0:bb348c97df44 2908 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
lypinator 0:bb348c97df44 2909 {
lypinator 0:bb348c97df44 2910 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) !=RESET)
lypinator 0:bb348c97df44 2911 {
lypinator 0:bb348c97df44 2912 __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
lypinator 0:bb348c97df44 2913 HAL_TIMEx_BreakCallback(htim);
lypinator 0:bb348c97df44 2914 }
lypinator 0:bb348c97df44 2915 }
lypinator 0:bb348c97df44 2916 /* TIM Trigger detection event */
lypinator 0:bb348c97df44 2917 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
lypinator 0:bb348c97df44 2918 {
lypinator 0:bb348c97df44 2919 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) !=RESET)
lypinator 0:bb348c97df44 2920 {
lypinator 0:bb348c97df44 2921 __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
lypinator 0:bb348c97df44 2922 HAL_TIM_TriggerCallback(htim);
lypinator 0:bb348c97df44 2923 }
lypinator 0:bb348c97df44 2924 }
lypinator 0:bb348c97df44 2925 /* TIM commutation event */
lypinator 0:bb348c97df44 2926 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
lypinator 0:bb348c97df44 2927 {
lypinator 0:bb348c97df44 2928 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) !=RESET)
lypinator 0:bb348c97df44 2929 {
lypinator 0:bb348c97df44 2930 __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
lypinator 0:bb348c97df44 2931 HAL_TIMEx_CommutationCallback(htim);
lypinator 0:bb348c97df44 2932 }
lypinator 0:bb348c97df44 2933 }
lypinator 0:bb348c97df44 2934 }
lypinator 0:bb348c97df44 2935 /**
lypinator 0:bb348c97df44 2936 * @}
lypinator 0:bb348c97df44 2937 */
lypinator 0:bb348c97df44 2938
lypinator 0:bb348c97df44 2939 /** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions
lypinator 0:bb348c97df44 2940 * @brief Peripheral Control functions
lypinator 0:bb348c97df44 2941 *
lypinator 0:bb348c97df44 2942 @verbatim
lypinator 0:bb348c97df44 2943 ==============================================================================
lypinator 0:bb348c97df44 2944 ##### Peripheral Control functions #####
lypinator 0:bb348c97df44 2945 ==============================================================================
lypinator 0:bb348c97df44 2946 [..]
lypinator 0:bb348c97df44 2947 This section provides functions allowing to:
lypinator 0:bb348c97df44 2948 (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
lypinator 0:bb348c97df44 2949 (+) Configure External Clock source.
lypinator 0:bb348c97df44 2950 (+) Configure Complementary channels, break features and dead time.
lypinator 0:bb348c97df44 2951 (+) Configure Master and the Slave synchronization.
lypinator 0:bb348c97df44 2952 (+) Configure the DMA Burst Mode.
lypinator 0:bb348c97df44 2953
lypinator 0:bb348c97df44 2954 @endverbatim
lypinator 0:bb348c97df44 2955 * @{
lypinator 0:bb348c97df44 2956 */
lypinator 0:bb348c97df44 2957
lypinator 0:bb348c97df44 2958 /**
lypinator 0:bb348c97df44 2959 * @brief Initializes the TIM Output Compare Channels according to the specified
lypinator 0:bb348c97df44 2960 * parameters in the TIM_OC_InitTypeDef.
lypinator 0:bb348c97df44 2961 * @param htim pointer to a TIM_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 2962 * the configuration information for TIM module.
lypinator 0:bb348c97df44 2963 * @param sConfig TIM Output Compare configuration structure
lypinator 0:bb348c97df44 2964 * @param Channel TIM Channels to be enabled.
lypinator 0:bb348c97df44 2965 * This parameter can be one of the following values:
lypinator 0:bb348c97df44 2966 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
lypinator 0:bb348c97df44 2967 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
lypinator 0:bb348c97df44 2968 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
lypinator 0:bb348c97df44 2969 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
lypinator 0:bb348c97df44 2970 * @retval HAL status
lypinator 0:bb348c97df44 2971 */
lypinator 0:bb348c97df44 2972 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
lypinator 0:bb348c97df44 2973 {
lypinator 0:bb348c97df44 2974 /* Check the parameters */
lypinator 0:bb348c97df44 2975 assert_param(IS_TIM_CHANNELS(Channel));
lypinator 0:bb348c97df44 2976 assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
lypinator 0:bb348c97df44 2977 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
lypinator 0:bb348c97df44 2978
lypinator 0:bb348c97df44 2979 /* Check input state */
lypinator 0:bb348c97df44 2980 __HAL_LOCK(htim);
lypinator 0:bb348c97df44 2981
lypinator 0:bb348c97df44 2982 htim->State = HAL_TIM_STATE_BUSY;
lypinator 0:bb348c97df44 2983
lypinator 0:bb348c97df44 2984 switch (Channel)
lypinator 0:bb348c97df44 2985 {
lypinator 0:bb348c97df44 2986 case TIM_CHANNEL_1:
lypinator 0:bb348c97df44 2987 {
lypinator 0:bb348c97df44 2988 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
lypinator 0:bb348c97df44 2989 /* Configure the TIM Channel 1 in Output Compare */
lypinator 0:bb348c97df44 2990 TIM_OC1_SetConfig(htim->Instance, sConfig);
lypinator 0:bb348c97df44 2991 }
lypinator 0:bb348c97df44 2992 break;
lypinator 0:bb348c97df44 2993
lypinator 0:bb348c97df44 2994 case TIM_CHANNEL_2:
lypinator 0:bb348c97df44 2995 {
lypinator 0:bb348c97df44 2996 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
lypinator 0:bb348c97df44 2997 /* Configure the TIM Channel 2 in Output Compare */
lypinator 0:bb348c97df44 2998 TIM_OC2_SetConfig(htim->Instance, sConfig);
lypinator 0:bb348c97df44 2999 }
lypinator 0:bb348c97df44 3000 break;
lypinator 0:bb348c97df44 3001
lypinator 0:bb348c97df44 3002 case TIM_CHANNEL_3:
lypinator 0:bb348c97df44 3003 {
lypinator 0:bb348c97df44 3004 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
lypinator 0:bb348c97df44 3005 /* Configure the TIM Channel 3 in Output Compare */
lypinator 0:bb348c97df44 3006 TIM_OC3_SetConfig(htim->Instance, sConfig);
lypinator 0:bb348c97df44 3007 }
lypinator 0:bb348c97df44 3008 break;
lypinator 0:bb348c97df44 3009
lypinator 0:bb348c97df44 3010 case TIM_CHANNEL_4:
lypinator 0:bb348c97df44 3011 {
lypinator 0:bb348c97df44 3012 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
lypinator 0:bb348c97df44 3013 /* Configure the TIM Channel 4 in Output Compare */
lypinator 0:bb348c97df44 3014 TIM_OC4_SetConfig(htim->Instance, sConfig);
lypinator 0:bb348c97df44 3015 }
lypinator 0:bb348c97df44 3016 break;
lypinator 0:bb348c97df44 3017
lypinator 0:bb348c97df44 3018 default:
lypinator 0:bb348c97df44 3019 break;
lypinator 0:bb348c97df44 3020 }
lypinator 0:bb348c97df44 3021 htim->State = HAL_TIM_STATE_READY;
lypinator 0:bb348c97df44 3022
lypinator 0:bb348c97df44 3023 __HAL_UNLOCK(htim);
lypinator 0:bb348c97df44 3024
lypinator 0:bb348c97df44 3025 return HAL_OK;
lypinator 0:bb348c97df44 3026 }
lypinator 0:bb348c97df44 3027
lypinator 0:bb348c97df44 3028 /**
lypinator 0:bb348c97df44 3029 * @brief Initializes the TIM Input Capture Channels according to the specified
lypinator 0:bb348c97df44 3030 * parameters in the TIM_IC_InitTypeDef.
lypinator 0:bb348c97df44 3031 * @param htim pointer to a TIM_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 3032 * the configuration information for TIM module.
lypinator 0:bb348c97df44 3033 * @param sConfig TIM Input Capture configuration structure
lypinator 0:bb348c97df44 3034 * @param Channel TIM Channels to be enabled.
lypinator 0:bb348c97df44 3035 * This parameter can be one of the following values:
lypinator 0:bb348c97df44 3036 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
lypinator 0:bb348c97df44 3037 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
lypinator 0:bb348c97df44 3038 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
lypinator 0:bb348c97df44 3039 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
lypinator 0:bb348c97df44 3040 * @retval HAL status
lypinator 0:bb348c97df44 3041 */
lypinator 0:bb348c97df44 3042 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel)
lypinator 0:bb348c97df44 3043 {
lypinator 0:bb348c97df44 3044 /* Check the parameters */
lypinator 0:bb348c97df44 3045 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
lypinator 0:bb348c97df44 3046 assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
lypinator 0:bb348c97df44 3047 assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
lypinator 0:bb348c97df44 3048 assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
lypinator 0:bb348c97df44 3049 assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
lypinator 0:bb348c97df44 3050
lypinator 0:bb348c97df44 3051 __HAL_LOCK(htim);
lypinator 0:bb348c97df44 3052
lypinator 0:bb348c97df44 3053 htim->State = HAL_TIM_STATE_BUSY;
lypinator 0:bb348c97df44 3054
lypinator 0:bb348c97df44 3055 if (Channel == TIM_CHANNEL_1)
lypinator 0:bb348c97df44 3056 {
lypinator 0:bb348c97df44 3057 /* TI1 Configuration */
lypinator 0:bb348c97df44 3058 TIM_TI1_SetConfig(htim->Instance,
lypinator 0:bb348c97df44 3059 sConfig->ICPolarity,
lypinator 0:bb348c97df44 3060 sConfig->ICSelection,
lypinator 0:bb348c97df44 3061 sConfig->ICFilter);
lypinator 0:bb348c97df44 3062
lypinator 0:bb348c97df44 3063 /* Reset the IC1PSC Bits */
lypinator 0:bb348c97df44 3064 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
lypinator 0:bb348c97df44 3065
lypinator 0:bb348c97df44 3066 /* Set the IC1PSC value */
lypinator 0:bb348c97df44 3067 htim->Instance->CCMR1 |= sConfig->ICPrescaler;
lypinator 0:bb348c97df44 3068 }
lypinator 0:bb348c97df44 3069 else if (Channel == TIM_CHANNEL_2)
lypinator 0:bb348c97df44 3070 {
lypinator 0:bb348c97df44 3071 /* TI2 Configuration */
lypinator 0:bb348c97df44 3072 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
lypinator 0:bb348c97df44 3073
lypinator 0:bb348c97df44 3074 TIM_TI2_SetConfig(htim->Instance,
lypinator 0:bb348c97df44 3075 sConfig->ICPolarity,
lypinator 0:bb348c97df44 3076 sConfig->ICSelection,
lypinator 0:bb348c97df44 3077 sConfig->ICFilter);
lypinator 0:bb348c97df44 3078
lypinator 0:bb348c97df44 3079 /* Reset the IC2PSC Bits */
lypinator 0:bb348c97df44 3080 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
lypinator 0:bb348c97df44 3081
lypinator 0:bb348c97df44 3082 /* Set the IC2PSC value */
lypinator 0:bb348c97df44 3083 htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U);
lypinator 0:bb348c97df44 3084 }
lypinator 0:bb348c97df44 3085 else if (Channel == TIM_CHANNEL_3)
lypinator 0:bb348c97df44 3086 {
lypinator 0:bb348c97df44 3087 /* TI3 Configuration */
lypinator 0:bb348c97df44 3088 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
lypinator 0:bb348c97df44 3089
lypinator 0:bb348c97df44 3090 TIM_TI3_SetConfig(htim->Instance,
lypinator 0:bb348c97df44 3091 sConfig->ICPolarity,
lypinator 0:bb348c97df44 3092 sConfig->ICSelection,
lypinator 0:bb348c97df44 3093 sConfig->ICFilter);
lypinator 0:bb348c97df44 3094
lypinator 0:bb348c97df44 3095 /* Reset the IC3PSC Bits */
lypinator 0:bb348c97df44 3096 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
lypinator 0:bb348c97df44 3097
lypinator 0:bb348c97df44 3098 /* Set the IC3PSC value */
lypinator 0:bb348c97df44 3099 htim->Instance->CCMR2 |= sConfig->ICPrescaler;
lypinator 0:bb348c97df44 3100 }
lypinator 0:bb348c97df44 3101 else
lypinator 0:bb348c97df44 3102 {
lypinator 0:bb348c97df44 3103 /* TI4 Configuration */
lypinator 0:bb348c97df44 3104 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
lypinator 0:bb348c97df44 3105
lypinator 0:bb348c97df44 3106 TIM_TI4_SetConfig(htim->Instance,
lypinator 0:bb348c97df44 3107 sConfig->ICPolarity,
lypinator 0:bb348c97df44 3108 sConfig->ICSelection,
lypinator 0:bb348c97df44 3109 sConfig->ICFilter);
lypinator 0:bb348c97df44 3110
lypinator 0:bb348c97df44 3111 /* Reset the IC4PSC Bits */
lypinator 0:bb348c97df44 3112 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
lypinator 0:bb348c97df44 3113
lypinator 0:bb348c97df44 3114 /* Set the IC4PSC value */
lypinator 0:bb348c97df44 3115 htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U);
lypinator 0:bb348c97df44 3116 }
lypinator 0:bb348c97df44 3117
lypinator 0:bb348c97df44 3118 htim->State = HAL_TIM_STATE_READY;
lypinator 0:bb348c97df44 3119
lypinator 0:bb348c97df44 3120 __HAL_UNLOCK(htim);
lypinator 0:bb348c97df44 3121
lypinator 0:bb348c97df44 3122 return HAL_OK;
lypinator 0:bb348c97df44 3123 }
lypinator 0:bb348c97df44 3124
lypinator 0:bb348c97df44 3125 /**
lypinator 0:bb348c97df44 3126 * @brief Initializes the TIM PWM channels according to the specified
lypinator 0:bb348c97df44 3127 * parameters in the TIM_OC_InitTypeDef.
lypinator 0:bb348c97df44 3128 * @param htim pointer to a TIM_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 3129 * the configuration information for TIM module.
lypinator 0:bb348c97df44 3130 * @param sConfig TIM PWM configuration structure
lypinator 0:bb348c97df44 3131 * @param Channel TIM Channels to be enabled.
lypinator 0:bb348c97df44 3132 * This parameter can be one of the following values:
lypinator 0:bb348c97df44 3133 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
lypinator 0:bb348c97df44 3134 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
lypinator 0:bb348c97df44 3135 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
lypinator 0:bb348c97df44 3136 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
lypinator 0:bb348c97df44 3137 * @retval HAL status
lypinator 0:bb348c97df44 3138 */
lypinator 0:bb348c97df44 3139 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
lypinator 0:bb348c97df44 3140 {
lypinator 0:bb348c97df44 3141 __HAL_LOCK(htim);
lypinator 0:bb348c97df44 3142
lypinator 0:bb348c97df44 3143 /* Check the parameters */
lypinator 0:bb348c97df44 3144 assert_param(IS_TIM_CHANNELS(Channel));
lypinator 0:bb348c97df44 3145 assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
lypinator 0:bb348c97df44 3146 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
lypinator 0:bb348c97df44 3147 assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
lypinator 0:bb348c97df44 3148
lypinator 0:bb348c97df44 3149 htim->State = HAL_TIM_STATE_BUSY;
lypinator 0:bb348c97df44 3150
lypinator 0:bb348c97df44 3151 switch (Channel)
lypinator 0:bb348c97df44 3152 {
lypinator 0:bb348c97df44 3153 case TIM_CHANNEL_1:
lypinator 0:bb348c97df44 3154 {
lypinator 0:bb348c97df44 3155 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
lypinator 0:bb348c97df44 3156 /* Configure the Channel 1 in PWM mode */
lypinator 0:bb348c97df44 3157 TIM_OC1_SetConfig(htim->Instance, sConfig);
lypinator 0:bb348c97df44 3158
lypinator 0:bb348c97df44 3159 /* Set the Preload enable bit for channel1 */
lypinator 0:bb348c97df44 3160 htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
lypinator 0:bb348c97df44 3161
lypinator 0:bb348c97df44 3162 /* Configure the Output Fast mode */
lypinator 0:bb348c97df44 3163 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
lypinator 0:bb348c97df44 3164 htim->Instance->CCMR1 |= sConfig->OCFastMode;
lypinator 0:bb348c97df44 3165 }
lypinator 0:bb348c97df44 3166 break;
lypinator 0:bb348c97df44 3167
lypinator 0:bb348c97df44 3168 case TIM_CHANNEL_2:
lypinator 0:bb348c97df44 3169 {
lypinator 0:bb348c97df44 3170 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
lypinator 0:bb348c97df44 3171 /* Configure the Channel 2 in PWM mode */
lypinator 0:bb348c97df44 3172 TIM_OC2_SetConfig(htim->Instance, sConfig);
lypinator 0:bb348c97df44 3173
lypinator 0:bb348c97df44 3174 /* Set the Preload enable bit for channel2 */
lypinator 0:bb348c97df44 3175 htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
lypinator 0:bb348c97df44 3176
lypinator 0:bb348c97df44 3177 /* Configure the Output Fast mode */
lypinator 0:bb348c97df44 3178 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
lypinator 0:bb348c97df44 3179 htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
lypinator 0:bb348c97df44 3180 }
lypinator 0:bb348c97df44 3181 break;
lypinator 0:bb348c97df44 3182
lypinator 0:bb348c97df44 3183 case TIM_CHANNEL_3:
lypinator 0:bb348c97df44 3184 {
lypinator 0:bb348c97df44 3185 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
lypinator 0:bb348c97df44 3186 /* Configure the Channel 3 in PWM mode */
lypinator 0:bb348c97df44 3187 TIM_OC3_SetConfig(htim->Instance, sConfig);
lypinator 0:bb348c97df44 3188
lypinator 0:bb348c97df44 3189 /* Set the Preload enable bit for channel3 */
lypinator 0:bb348c97df44 3190 htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
lypinator 0:bb348c97df44 3191
lypinator 0:bb348c97df44 3192 /* Configure the Output Fast mode */
lypinator 0:bb348c97df44 3193 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
lypinator 0:bb348c97df44 3194 htim->Instance->CCMR2 |= sConfig->OCFastMode;
lypinator 0:bb348c97df44 3195 }
lypinator 0:bb348c97df44 3196 break;
lypinator 0:bb348c97df44 3197
lypinator 0:bb348c97df44 3198 case TIM_CHANNEL_4:
lypinator 0:bb348c97df44 3199 {
lypinator 0:bb348c97df44 3200 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
lypinator 0:bb348c97df44 3201 /* Configure the Channel 4 in PWM mode */
lypinator 0:bb348c97df44 3202 TIM_OC4_SetConfig(htim->Instance, sConfig);
lypinator 0:bb348c97df44 3203
lypinator 0:bb348c97df44 3204 /* Set the Preload enable bit for channel4 */
lypinator 0:bb348c97df44 3205 htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
lypinator 0:bb348c97df44 3206
lypinator 0:bb348c97df44 3207 /* Configure the Output Fast mode */
lypinator 0:bb348c97df44 3208 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
lypinator 0:bb348c97df44 3209 htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
lypinator 0:bb348c97df44 3210 }
lypinator 0:bb348c97df44 3211 break;
lypinator 0:bb348c97df44 3212
lypinator 0:bb348c97df44 3213 default:
lypinator 0:bb348c97df44 3214 break;
lypinator 0:bb348c97df44 3215 }
lypinator 0:bb348c97df44 3216
lypinator 0:bb348c97df44 3217 htim->State = HAL_TIM_STATE_READY;
lypinator 0:bb348c97df44 3218
lypinator 0:bb348c97df44 3219 __HAL_UNLOCK(htim);
lypinator 0:bb348c97df44 3220
lypinator 0:bb348c97df44 3221 return HAL_OK;
lypinator 0:bb348c97df44 3222 }
lypinator 0:bb348c97df44 3223
lypinator 0:bb348c97df44 3224 /**
lypinator 0:bb348c97df44 3225 * @brief Initializes the TIM One Pulse Channels according to the specified
lypinator 0:bb348c97df44 3226 * parameters in the TIM_OnePulse_InitTypeDef.
lypinator 0:bb348c97df44 3227 * @param htim pointer to a TIM_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 3228 * the configuration information for TIM module.
lypinator 0:bb348c97df44 3229 * @param sConfig TIM One Pulse configuration structure
lypinator 0:bb348c97df44 3230 * @param OutputChannel TIM Channels to be enabled.
lypinator 0:bb348c97df44 3231 * This parameter can be one of the following values:
lypinator 0:bb348c97df44 3232 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
lypinator 0:bb348c97df44 3233 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
lypinator 0:bb348c97df44 3234 * @param InputChannel TIM Channels to be enabled.
lypinator 0:bb348c97df44 3235 * This parameter can be one of the following values:
lypinator 0:bb348c97df44 3236 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
lypinator 0:bb348c97df44 3237 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
lypinator 0:bb348c97df44 3238 * @retval HAL status
lypinator 0:bb348c97df44 3239 */
lypinator 0:bb348c97df44 3240 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel)
lypinator 0:bb348c97df44 3241 {
lypinator 0:bb348c97df44 3242 TIM_OC_InitTypeDef temp1;
lypinator 0:bb348c97df44 3243
lypinator 0:bb348c97df44 3244 /* Check the parameters */
lypinator 0:bb348c97df44 3245 assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
lypinator 0:bb348c97df44 3246 assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
lypinator 0:bb348c97df44 3247
lypinator 0:bb348c97df44 3248 if(OutputChannel != InputChannel)
lypinator 0:bb348c97df44 3249 {
lypinator 0:bb348c97df44 3250 __HAL_LOCK(htim);
lypinator 0:bb348c97df44 3251
lypinator 0:bb348c97df44 3252 htim->State = HAL_TIM_STATE_BUSY;
lypinator 0:bb348c97df44 3253
lypinator 0:bb348c97df44 3254 /* Extract the Output compare configuration from sConfig structure */
lypinator 0:bb348c97df44 3255 temp1.OCMode = sConfig->OCMode;
lypinator 0:bb348c97df44 3256 temp1.Pulse = sConfig->Pulse;
lypinator 0:bb348c97df44 3257 temp1.OCPolarity = sConfig->OCPolarity;
lypinator 0:bb348c97df44 3258 temp1.OCNPolarity = sConfig->OCNPolarity;
lypinator 0:bb348c97df44 3259 temp1.OCIdleState = sConfig->OCIdleState;
lypinator 0:bb348c97df44 3260 temp1.OCNIdleState = sConfig->OCNIdleState;
lypinator 0:bb348c97df44 3261
lypinator 0:bb348c97df44 3262 switch (OutputChannel)
lypinator 0:bb348c97df44 3263 {
lypinator 0:bb348c97df44 3264 case TIM_CHANNEL_1:
lypinator 0:bb348c97df44 3265 {
lypinator 0:bb348c97df44 3266 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
lypinator 0:bb348c97df44 3267
lypinator 0:bb348c97df44 3268 TIM_OC1_SetConfig(htim->Instance, &temp1);
lypinator 0:bb348c97df44 3269 }
lypinator 0:bb348c97df44 3270 break;
lypinator 0:bb348c97df44 3271 case TIM_CHANNEL_2:
lypinator 0:bb348c97df44 3272 {
lypinator 0:bb348c97df44 3273 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
lypinator 0:bb348c97df44 3274
lypinator 0:bb348c97df44 3275 TIM_OC2_SetConfig(htim->Instance, &temp1);
lypinator 0:bb348c97df44 3276 }
lypinator 0:bb348c97df44 3277 break;
lypinator 0:bb348c97df44 3278 default:
lypinator 0:bb348c97df44 3279 break;
lypinator 0:bb348c97df44 3280 }
lypinator 0:bb348c97df44 3281 switch (InputChannel)
lypinator 0:bb348c97df44 3282 {
lypinator 0:bb348c97df44 3283 case TIM_CHANNEL_1:
lypinator 0:bb348c97df44 3284 {
lypinator 0:bb348c97df44 3285 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
lypinator 0:bb348c97df44 3286
lypinator 0:bb348c97df44 3287 TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
lypinator 0:bb348c97df44 3288 sConfig->ICSelection, sConfig->ICFilter);
lypinator 0:bb348c97df44 3289
lypinator 0:bb348c97df44 3290 /* Reset the IC1PSC Bits */
lypinator 0:bb348c97df44 3291 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
lypinator 0:bb348c97df44 3292
lypinator 0:bb348c97df44 3293 /* Select the Trigger source */
lypinator 0:bb348c97df44 3294 htim->Instance->SMCR &= ~TIM_SMCR_TS;
lypinator 0:bb348c97df44 3295 htim->Instance->SMCR |= TIM_TS_TI1FP1;
lypinator 0:bb348c97df44 3296
lypinator 0:bb348c97df44 3297 /* Select the Slave Mode */
lypinator 0:bb348c97df44 3298 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
lypinator 0:bb348c97df44 3299 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
lypinator 0:bb348c97df44 3300 }
lypinator 0:bb348c97df44 3301 break;
lypinator 0:bb348c97df44 3302 case TIM_CHANNEL_2:
lypinator 0:bb348c97df44 3303 {
lypinator 0:bb348c97df44 3304 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
lypinator 0:bb348c97df44 3305
lypinator 0:bb348c97df44 3306 TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
lypinator 0:bb348c97df44 3307 sConfig->ICSelection, sConfig->ICFilter);
lypinator 0:bb348c97df44 3308
lypinator 0:bb348c97df44 3309 /* Reset the IC2PSC Bits */
lypinator 0:bb348c97df44 3310 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
lypinator 0:bb348c97df44 3311
lypinator 0:bb348c97df44 3312 /* Select the Trigger source */
lypinator 0:bb348c97df44 3313 htim->Instance->SMCR &= ~TIM_SMCR_TS;
lypinator 0:bb348c97df44 3314 htim->Instance->SMCR |= TIM_TS_TI2FP2;
lypinator 0:bb348c97df44 3315
lypinator 0:bb348c97df44 3316 /* Select the Slave Mode */
lypinator 0:bb348c97df44 3317 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
lypinator 0:bb348c97df44 3318 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
lypinator 0:bb348c97df44 3319 }
lypinator 0:bb348c97df44 3320 break;
lypinator 0:bb348c97df44 3321
lypinator 0:bb348c97df44 3322 default:
lypinator 0:bb348c97df44 3323 break;
lypinator 0:bb348c97df44 3324 }
lypinator 0:bb348c97df44 3325
lypinator 0:bb348c97df44 3326 htim->State = HAL_TIM_STATE_READY;
lypinator 0:bb348c97df44 3327
lypinator 0:bb348c97df44 3328 __HAL_UNLOCK(htim);
lypinator 0:bb348c97df44 3329
lypinator 0:bb348c97df44 3330 return HAL_OK;
lypinator 0:bb348c97df44 3331 }
lypinator 0:bb348c97df44 3332 else
lypinator 0:bb348c97df44 3333 {
lypinator 0:bb348c97df44 3334 return HAL_ERROR;
lypinator 0:bb348c97df44 3335 }
lypinator 0:bb348c97df44 3336 }
lypinator 0:bb348c97df44 3337
lypinator 0:bb348c97df44 3338 /**
lypinator 0:bb348c97df44 3339 * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
lypinator 0:bb348c97df44 3340 * @param htim pointer to a TIM_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 3341 * the configuration information for TIM module.
lypinator 0:bb348c97df44 3342 * @param BurstBaseAddress TIM Base address from when the DMA will starts the Data write.
lypinator 0:bb348c97df44 3343 * This parameters can be on of the following values:
lypinator 0:bb348c97df44 3344 * @arg TIM_DMABASE_CR1
lypinator 0:bb348c97df44 3345 * @arg TIM_DMABASE_CR2
lypinator 0:bb348c97df44 3346 * @arg TIM_DMABASE_SMCR
lypinator 0:bb348c97df44 3347 * @arg TIM_DMABASE_DIER
lypinator 0:bb348c97df44 3348 * @arg TIM_DMABASE_SR
lypinator 0:bb348c97df44 3349 * @arg TIM_DMABASE_EGR
lypinator 0:bb348c97df44 3350 * @arg TIM_DMABASE_CCMR1
lypinator 0:bb348c97df44 3351 * @arg TIM_DMABASE_CCMR2
lypinator 0:bb348c97df44 3352 * @arg TIM_DMABASE_CCER
lypinator 0:bb348c97df44 3353 * @arg TIM_DMABASE_CNT
lypinator 0:bb348c97df44 3354 * @arg TIM_DMABASE_PSC
lypinator 0:bb348c97df44 3355 * @arg TIM_DMABASE_ARR
lypinator 0:bb348c97df44 3356 * @arg TIM_DMABASE_RCR
lypinator 0:bb348c97df44 3357 * @arg TIM_DMABASE_CCR1
lypinator 0:bb348c97df44 3358 * @arg TIM_DMABASE_CCR2
lypinator 0:bb348c97df44 3359 * @arg TIM_DMABASE_CCR3
lypinator 0:bb348c97df44 3360 * @arg TIM_DMABASE_CCR4
lypinator 0:bb348c97df44 3361 * @arg TIM_DMABASE_BDTR
lypinator 0:bb348c97df44 3362 * @arg TIM_DMABASE_DCR
lypinator 0:bb348c97df44 3363 * @param BurstRequestSrc TIM DMA Request sources.
lypinator 0:bb348c97df44 3364 * This parameters can be on of the following values:
lypinator 0:bb348c97df44 3365 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
lypinator 0:bb348c97df44 3366 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
lypinator 0:bb348c97df44 3367 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
lypinator 0:bb348c97df44 3368 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
lypinator 0:bb348c97df44 3369 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
lypinator 0:bb348c97df44 3370 * @arg TIM_DMA_COM: TIM Commutation DMA source
lypinator 0:bb348c97df44 3371 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
lypinator 0:bb348c97df44 3372 * @param BurstBuffer The Buffer address.
lypinator 0:bb348c97df44 3373 * @param BurstLength DMA Burst length. This parameter can be one value
lypinator 0:bb348c97df44 3374 * between TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
lypinator 0:bb348c97df44 3375 * @retval HAL status
lypinator 0:bb348c97df44 3376 */
lypinator 0:bb348c97df44 3377 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
lypinator 0:bb348c97df44 3378 uint32_t* BurstBuffer, uint32_t BurstLength)
lypinator 0:bb348c97df44 3379 {
lypinator 0:bb348c97df44 3380 /* Check the parameters */
lypinator 0:bb348c97df44 3381 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
lypinator 0:bb348c97df44 3382 assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
lypinator 0:bb348c97df44 3383 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
lypinator 0:bb348c97df44 3384 assert_param(IS_TIM_DMA_LENGTH(BurstLength));
lypinator 0:bb348c97df44 3385
lypinator 0:bb348c97df44 3386 if((htim->State == HAL_TIM_STATE_BUSY))
lypinator 0:bb348c97df44 3387 {
lypinator 0:bb348c97df44 3388 return HAL_BUSY;
lypinator 0:bb348c97df44 3389 }
lypinator 0:bb348c97df44 3390 else if((htim->State == HAL_TIM_STATE_READY))
lypinator 0:bb348c97df44 3391 {
lypinator 0:bb348c97df44 3392 if((BurstBuffer == 0U) && (BurstLength > 0U))
lypinator 0:bb348c97df44 3393 {
lypinator 0:bb348c97df44 3394 return HAL_ERROR;
lypinator 0:bb348c97df44 3395 }
lypinator 0:bb348c97df44 3396 else
lypinator 0:bb348c97df44 3397 {
lypinator 0:bb348c97df44 3398 htim->State = HAL_TIM_STATE_BUSY;
lypinator 0:bb348c97df44 3399 }
lypinator 0:bb348c97df44 3400 }
lypinator 0:bb348c97df44 3401 switch(BurstRequestSrc)
lypinator 0:bb348c97df44 3402 {
lypinator 0:bb348c97df44 3403 case TIM_DMA_UPDATE:
lypinator 0:bb348c97df44 3404 {
lypinator 0:bb348c97df44 3405 /* Set the DMA Period elapsed callback */
lypinator 0:bb348c97df44 3406 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
lypinator 0:bb348c97df44 3407
lypinator 0:bb348c97df44 3408 /* Set the DMA error callback */
lypinator 0:bb348c97df44 3409 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
lypinator 0:bb348c97df44 3410
lypinator 0:bb348c97df44 3411 /* Enable the DMA Stream */
lypinator 0:bb348c97df44 3412 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
lypinator 0:bb348c97df44 3413 }
lypinator 0:bb348c97df44 3414 break;
lypinator 0:bb348c97df44 3415 case TIM_DMA_CC1:
lypinator 0:bb348c97df44 3416 {
lypinator 0:bb348c97df44 3417 /* Set the DMA Period elapsed callback */
lypinator 0:bb348c97df44 3418 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
lypinator 0:bb348c97df44 3419
lypinator 0:bb348c97df44 3420 /* Set the DMA error callback */
lypinator 0:bb348c97df44 3421 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
lypinator 0:bb348c97df44 3422
lypinator 0:bb348c97df44 3423 /* Enable the DMA Stream */
lypinator 0:bb348c97df44 3424 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
lypinator 0:bb348c97df44 3425 }
lypinator 0:bb348c97df44 3426 break;
lypinator 0:bb348c97df44 3427 case TIM_DMA_CC2:
lypinator 0:bb348c97df44 3428 {
lypinator 0:bb348c97df44 3429 /* Set the DMA Period elapsed callback */
lypinator 0:bb348c97df44 3430 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
lypinator 0:bb348c97df44 3431
lypinator 0:bb348c97df44 3432 /* Set the DMA error callback */
lypinator 0:bb348c97df44 3433 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
lypinator 0:bb348c97df44 3434
lypinator 0:bb348c97df44 3435 /* Enable the DMA Stream */
lypinator 0:bb348c97df44 3436 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
lypinator 0:bb348c97df44 3437 }
lypinator 0:bb348c97df44 3438 break;
lypinator 0:bb348c97df44 3439 case TIM_DMA_CC3:
lypinator 0:bb348c97df44 3440 {
lypinator 0:bb348c97df44 3441 /* Set the DMA Period elapsed callback */
lypinator 0:bb348c97df44 3442 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
lypinator 0:bb348c97df44 3443
lypinator 0:bb348c97df44 3444 /* Set the DMA error callback */
lypinator 0:bb348c97df44 3445 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
lypinator 0:bb348c97df44 3446
lypinator 0:bb348c97df44 3447 /* Enable the DMA Stream */
lypinator 0:bb348c97df44 3448 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
lypinator 0:bb348c97df44 3449 }
lypinator 0:bb348c97df44 3450 break;
lypinator 0:bb348c97df44 3451 case TIM_DMA_CC4:
lypinator 0:bb348c97df44 3452 {
lypinator 0:bb348c97df44 3453 /* Set the DMA Period elapsed callback */
lypinator 0:bb348c97df44 3454 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
lypinator 0:bb348c97df44 3455
lypinator 0:bb348c97df44 3456 /* Set the DMA error callback */
lypinator 0:bb348c97df44 3457 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
lypinator 0:bb348c97df44 3458
lypinator 0:bb348c97df44 3459 /* Enable the DMA Stream */
lypinator 0:bb348c97df44 3460 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
lypinator 0:bb348c97df44 3461 }
lypinator 0:bb348c97df44 3462 break;
lypinator 0:bb348c97df44 3463 case TIM_DMA_COM:
lypinator 0:bb348c97df44 3464 {
lypinator 0:bb348c97df44 3465 /* Set the DMA Period elapsed callback */
lypinator 0:bb348c97df44 3466 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
lypinator 0:bb348c97df44 3467
lypinator 0:bb348c97df44 3468 /* Set the DMA error callback */
lypinator 0:bb348c97df44 3469 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
lypinator 0:bb348c97df44 3470
lypinator 0:bb348c97df44 3471 /* Enable the DMA Stream */
lypinator 0:bb348c97df44 3472 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
lypinator 0:bb348c97df44 3473 }
lypinator 0:bb348c97df44 3474 break;
lypinator 0:bb348c97df44 3475 case TIM_DMA_TRIGGER:
lypinator 0:bb348c97df44 3476 {
lypinator 0:bb348c97df44 3477 /* Set the DMA Period elapsed callback */
lypinator 0:bb348c97df44 3478 htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
lypinator 0:bb348c97df44 3479
lypinator 0:bb348c97df44 3480 /* Set the DMA error callback */
lypinator 0:bb348c97df44 3481 htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
lypinator 0:bb348c97df44 3482
lypinator 0:bb348c97df44 3483 /* Enable the DMA Stream */
lypinator 0:bb348c97df44 3484 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
lypinator 0:bb348c97df44 3485 }
lypinator 0:bb348c97df44 3486 break;
lypinator 0:bb348c97df44 3487 default:
lypinator 0:bb348c97df44 3488 break;
lypinator 0:bb348c97df44 3489 }
lypinator 0:bb348c97df44 3490 /* configure the DMA Burst Mode */
lypinator 0:bb348c97df44 3491 htim->Instance->DCR = BurstBaseAddress | BurstLength;
lypinator 0:bb348c97df44 3492
lypinator 0:bb348c97df44 3493 /* Enable the TIM DMA Request */
lypinator 0:bb348c97df44 3494 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
lypinator 0:bb348c97df44 3495
lypinator 0:bb348c97df44 3496 htim->State = HAL_TIM_STATE_READY;
lypinator 0:bb348c97df44 3497
lypinator 0:bb348c97df44 3498 /* Return function status */
lypinator 0:bb348c97df44 3499 return HAL_OK;
lypinator 0:bb348c97df44 3500 }
lypinator 0:bb348c97df44 3501
lypinator 0:bb348c97df44 3502 /**
lypinator 0:bb348c97df44 3503 * @brief Stops the TIM DMA Burst mode
lypinator 0:bb348c97df44 3504 * @param htim pointer to a TIM_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 3505 * the configuration information for TIM module.
lypinator 0:bb348c97df44 3506 * @param BurstRequestSrc TIM DMA Request sources to disable
lypinator 0:bb348c97df44 3507 * @retval HAL status
lypinator 0:bb348c97df44 3508 */
lypinator 0:bb348c97df44 3509 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
lypinator 0:bb348c97df44 3510 {
lypinator 0:bb348c97df44 3511 /* Check the parameters */
lypinator 0:bb348c97df44 3512 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
lypinator 0:bb348c97df44 3513
lypinator 0:bb348c97df44 3514 /* Abort the DMA transfer (at least disable the DMA channel) */
lypinator 0:bb348c97df44 3515 switch(BurstRequestSrc)
lypinator 0:bb348c97df44 3516 {
lypinator 0:bb348c97df44 3517 case TIM_DMA_UPDATE:
lypinator 0:bb348c97df44 3518 {
lypinator 0:bb348c97df44 3519 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
lypinator 0:bb348c97df44 3520 }
lypinator 0:bb348c97df44 3521 break;
lypinator 0:bb348c97df44 3522 case TIM_DMA_CC1:
lypinator 0:bb348c97df44 3523 {
lypinator 0:bb348c97df44 3524 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
lypinator 0:bb348c97df44 3525 }
lypinator 0:bb348c97df44 3526 break;
lypinator 0:bb348c97df44 3527 case TIM_DMA_CC2:
lypinator 0:bb348c97df44 3528 {
lypinator 0:bb348c97df44 3529 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
lypinator 0:bb348c97df44 3530 }
lypinator 0:bb348c97df44 3531 break;
lypinator 0:bb348c97df44 3532 case TIM_DMA_CC3:
lypinator 0:bb348c97df44 3533 {
lypinator 0:bb348c97df44 3534 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
lypinator 0:bb348c97df44 3535 }
lypinator 0:bb348c97df44 3536 break;
lypinator 0:bb348c97df44 3537 case TIM_DMA_CC4:
lypinator 0:bb348c97df44 3538 {
lypinator 0:bb348c97df44 3539 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
lypinator 0:bb348c97df44 3540 }
lypinator 0:bb348c97df44 3541 break;
lypinator 0:bb348c97df44 3542 case TIM_DMA_COM:
lypinator 0:bb348c97df44 3543 {
lypinator 0:bb348c97df44 3544 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
lypinator 0:bb348c97df44 3545 }
lypinator 0:bb348c97df44 3546 break;
lypinator 0:bb348c97df44 3547 case TIM_DMA_TRIGGER:
lypinator 0:bb348c97df44 3548 {
lypinator 0:bb348c97df44 3549 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
lypinator 0:bb348c97df44 3550 }
lypinator 0:bb348c97df44 3551 break;
lypinator 0:bb348c97df44 3552 default:
lypinator 0:bb348c97df44 3553 break;
lypinator 0:bb348c97df44 3554 }
lypinator 0:bb348c97df44 3555
lypinator 0:bb348c97df44 3556 /* Disable the TIM Update DMA request */
lypinator 0:bb348c97df44 3557 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
lypinator 0:bb348c97df44 3558
lypinator 0:bb348c97df44 3559 /* Return function status */
lypinator 0:bb348c97df44 3560 return HAL_OK;
lypinator 0:bb348c97df44 3561 }
lypinator 0:bb348c97df44 3562
lypinator 0:bb348c97df44 3563 /**
lypinator 0:bb348c97df44 3564 * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
lypinator 0:bb348c97df44 3565 * @param htim pointer to a TIM_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 3566 * the configuration information for TIM module.
lypinator 0:bb348c97df44 3567 * @param BurstBaseAddress TIM Base address from when the DMA will starts the Data read.
lypinator 0:bb348c97df44 3568 * This parameters can be on of the following values:
lypinator 0:bb348c97df44 3569 * @arg TIM_DMABASE_CR1
lypinator 0:bb348c97df44 3570 * @arg TIM_DMABASE_CR2
lypinator 0:bb348c97df44 3571 * @arg TIM_DMABASE_SMCR
lypinator 0:bb348c97df44 3572 * @arg TIM_DMABASE_DIER
lypinator 0:bb348c97df44 3573 * @arg TIM_DMABASE_SR
lypinator 0:bb348c97df44 3574 * @arg TIM_DMABASE_EGR
lypinator 0:bb348c97df44 3575 * @arg TIM_DMABASE_CCMR1
lypinator 0:bb348c97df44 3576 * @arg TIM_DMABASE_CCMR2
lypinator 0:bb348c97df44 3577 * @arg TIM_DMABASE_CCER
lypinator 0:bb348c97df44 3578 * @arg TIM_DMABASE_CNT
lypinator 0:bb348c97df44 3579 * @arg TIM_DMABASE_PSC
lypinator 0:bb348c97df44 3580 * @arg TIM_DMABASE_ARR
lypinator 0:bb348c97df44 3581 * @arg TIM_DMABASE_RCR
lypinator 0:bb348c97df44 3582 * @arg TIM_DMABASE_CCR1
lypinator 0:bb348c97df44 3583 * @arg TIM_DMABASE_CCR2
lypinator 0:bb348c97df44 3584 * @arg TIM_DMABASE_CCR3
lypinator 0:bb348c97df44 3585 * @arg TIM_DMABASE_CCR4
lypinator 0:bb348c97df44 3586 * @arg TIM_DMABASE_BDTR
lypinator 0:bb348c97df44 3587 * @arg TIM_DMABASE_DCR
lypinator 0:bb348c97df44 3588 * @param BurstRequestSrc TIM DMA Request sources.
lypinator 0:bb348c97df44 3589 * This parameters can be on of the following values:
lypinator 0:bb348c97df44 3590 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
lypinator 0:bb348c97df44 3591 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
lypinator 0:bb348c97df44 3592 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
lypinator 0:bb348c97df44 3593 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
lypinator 0:bb348c97df44 3594 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
lypinator 0:bb348c97df44 3595 * @arg TIM_DMA_COM: TIM Commutation DMA source
lypinator 0:bb348c97df44 3596 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
lypinator 0:bb348c97df44 3597 * @param BurstBuffer The Buffer address.
lypinator 0:bb348c97df44 3598 * @param BurstLength DMA Burst length. This parameter can be one value
lypinator 0:bb348c97df44 3599 * between TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
lypinator 0:bb348c97df44 3600 * @retval HAL status
lypinator 0:bb348c97df44 3601 */
lypinator 0:bb348c97df44 3602 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
lypinator 0:bb348c97df44 3603 uint32_t *BurstBuffer, uint32_t BurstLength)
lypinator 0:bb348c97df44 3604 {
lypinator 0:bb348c97df44 3605 /* Check the parameters */
lypinator 0:bb348c97df44 3606 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
lypinator 0:bb348c97df44 3607 assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
lypinator 0:bb348c97df44 3608 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
lypinator 0:bb348c97df44 3609 assert_param(IS_TIM_DMA_LENGTH(BurstLength));
lypinator 0:bb348c97df44 3610
lypinator 0:bb348c97df44 3611 if((htim->State == HAL_TIM_STATE_BUSY))
lypinator 0:bb348c97df44 3612 {
lypinator 0:bb348c97df44 3613 return HAL_BUSY;
lypinator 0:bb348c97df44 3614 }
lypinator 0:bb348c97df44 3615 else if((htim->State == HAL_TIM_STATE_READY))
lypinator 0:bb348c97df44 3616 {
lypinator 0:bb348c97df44 3617 if((BurstBuffer == 0U) && (BurstLength > 0U))
lypinator 0:bb348c97df44 3618 {
lypinator 0:bb348c97df44 3619 return HAL_ERROR;
lypinator 0:bb348c97df44 3620 }
lypinator 0:bb348c97df44 3621 else
lypinator 0:bb348c97df44 3622 {
lypinator 0:bb348c97df44 3623 htim->State = HAL_TIM_STATE_BUSY;
lypinator 0:bb348c97df44 3624 }
lypinator 0:bb348c97df44 3625 }
lypinator 0:bb348c97df44 3626 switch(BurstRequestSrc)
lypinator 0:bb348c97df44 3627 {
lypinator 0:bb348c97df44 3628 case TIM_DMA_UPDATE:
lypinator 0:bb348c97df44 3629 {
lypinator 0:bb348c97df44 3630 /* Set the DMA Period elapsed callback */
lypinator 0:bb348c97df44 3631 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
lypinator 0:bb348c97df44 3632
lypinator 0:bb348c97df44 3633 /* Set the DMA error callback */
lypinator 0:bb348c97df44 3634 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
lypinator 0:bb348c97df44 3635
lypinator 0:bb348c97df44 3636 /* Enable the DMA Stream */
lypinator 0:bb348c97df44 3637 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
lypinator 0:bb348c97df44 3638 }
lypinator 0:bb348c97df44 3639 break;
lypinator 0:bb348c97df44 3640 case TIM_DMA_CC1:
lypinator 0:bb348c97df44 3641 {
lypinator 0:bb348c97df44 3642 /* Set the DMA Period elapsed callback */
lypinator 0:bb348c97df44 3643 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
lypinator 0:bb348c97df44 3644
lypinator 0:bb348c97df44 3645 /* Set the DMA error callback */
lypinator 0:bb348c97df44 3646 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
lypinator 0:bb348c97df44 3647
lypinator 0:bb348c97df44 3648 /* Enable the DMA Stream */
lypinator 0:bb348c97df44 3649 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
lypinator 0:bb348c97df44 3650 }
lypinator 0:bb348c97df44 3651 break;
lypinator 0:bb348c97df44 3652 case TIM_DMA_CC2:
lypinator 0:bb348c97df44 3653 {
lypinator 0:bb348c97df44 3654 /* Set the DMA Period elapsed callback */
lypinator 0:bb348c97df44 3655 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
lypinator 0:bb348c97df44 3656
lypinator 0:bb348c97df44 3657 /* Set the DMA error callback */
lypinator 0:bb348c97df44 3658 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
lypinator 0:bb348c97df44 3659
lypinator 0:bb348c97df44 3660 /* Enable the DMA Stream */
lypinator 0:bb348c97df44 3661 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
lypinator 0:bb348c97df44 3662 }
lypinator 0:bb348c97df44 3663 break;
lypinator 0:bb348c97df44 3664 case TIM_DMA_CC3:
lypinator 0:bb348c97df44 3665 {
lypinator 0:bb348c97df44 3666 /* Set the DMA Period elapsed callback */
lypinator 0:bb348c97df44 3667 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
lypinator 0:bb348c97df44 3668
lypinator 0:bb348c97df44 3669 /* Set the DMA error callback */
lypinator 0:bb348c97df44 3670 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
lypinator 0:bb348c97df44 3671
lypinator 0:bb348c97df44 3672 /* Enable the DMA Stream */
lypinator 0:bb348c97df44 3673 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
lypinator 0:bb348c97df44 3674 }
lypinator 0:bb348c97df44 3675 break;
lypinator 0:bb348c97df44 3676 case TIM_DMA_CC4:
lypinator 0:bb348c97df44 3677 {
lypinator 0:bb348c97df44 3678 /* Set the DMA Period elapsed callback */
lypinator 0:bb348c97df44 3679 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
lypinator 0:bb348c97df44 3680
lypinator 0:bb348c97df44 3681 /* Set the DMA error callback */
lypinator 0:bb348c97df44 3682 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
lypinator 0:bb348c97df44 3683
lypinator 0:bb348c97df44 3684 /* Enable the DMA Stream */
lypinator 0:bb348c97df44 3685 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
lypinator 0:bb348c97df44 3686 }
lypinator 0:bb348c97df44 3687 break;
lypinator 0:bb348c97df44 3688 case TIM_DMA_COM:
lypinator 0:bb348c97df44 3689 {
lypinator 0:bb348c97df44 3690 /* Set the DMA Period elapsed callback */
lypinator 0:bb348c97df44 3691 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
lypinator 0:bb348c97df44 3692
lypinator 0:bb348c97df44 3693 /* Set the DMA error callback */
lypinator 0:bb348c97df44 3694 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
lypinator 0:bb348c97df44 3695
lypinator 0:bb348c97df44 3696 /* Enable the DMA Stream */
lypinator 0:bb348c97df44 3697 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
lypinator 0:bb348c97df44 3698 }
lypinator 0:bb348c97df44 3699 break;
lypinator 0:bb348c97df44 3700 case TIM_DMA_TRIGGER:
lypinator 0:bb348c97df44 3701 {
lypinator 0:bb348c97df44 3702 /* Set the DMA Period elapsed callback */
lypinator 0:bb348c97df44 3703 htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
lypinator 0:bb348c97df44 3704
lypinator 0:bb348c97df44 3705 /* Set the DMA error callback */
lypinator 0:bb348c97df44 3706 htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
lypinator 0:bb348c97df44 3707
lypinator 0:bb348c97df44 3708 /* Enable the DMA Stream */
lypinator 0:bb348c97df44 3709 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1);
lypinator 0:bb348c97df44 3710 }
lypinator 0:bb348c97df44 3711 break;
lypinator 0:bb348c97df44 3712 default:
lypinator 0:bb348c97df44 3713 break;
lypinator 0:bb348c97df44 3714 }
lypinator 0:bb348c97df44 3715
lypinator 0:bb348c97df44 3716 /* configure the DMA Burst Mode */
lypinator 0:bb348c97df44 3717 htim->Instance->DCR = BurstBaseAddress | BurstLength;
lypinator 0:bb348c97df44 3718
lypinator 0:bb348c97df44 3719 /* Enable the TIM DMA Request */
lypinator 0:bb348c97df44 3720 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
lypinator 0:bb348c97df44 3721
lypinator 0:bb348c97df44 3722 htim->State = HAL_TIM_STATE_READY;
lypinator 0:bb348c97df44 3723
lypinator 0:bb348c97df44 3724 /* Return function status */
lypinator 0:bb348c97df44 3725 return HAL_OK;
lypinator 0:bb348c97df44 3726 }
lypinator 0:bb348c97df44 3727
lypinator 0:bb348c97df44 3728 /**
lypinator 0:bb348c97df44 3729 * @brief Stop the DMA burst reading
lypinator 0:bb348c97df44 3730 * @param htim pointer to a TIM_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 3731 * the configuration information for TIM module.
lypinator 0:bb348c97df44 3732 * @param BurstRequestSrc TIM DMA Request sources to disable.
lypinator 0:bb348c97df44 3733 * @retval HAL status
lypinator 0:bb348c97df44 3734 */
lypinator 0:bb348c97df44 3735 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
lypinator 0:bb348c97df44 3736 {
lypinator 0:bb348c97df44 3737 /* Check the parameters */
lypinator 0:bb348c97df44 3738 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
lypinator 0:bb348c97df44 3739
lypinator 0:bb348c97df44 3740 /* Abort the DMA transfer (at least disable the DMA channel) */
lypinator 0:bb348c97df44 3741 switch(BurstRequestSrc)
lypinator 0:bb348c97df44 3742 {
lypinator 0:bb348c97df44 3743 case TIM_DMA_UPDATE:
lypinator 0:bb348c97df44 3744 {
lypinator 0:bb348c97df44 3745 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
lypinator 0:bb348c97df44 3746 }
lypinator 0:bb348c97df44 3747 break;
lypinator 0:bb348c97df44 3748 case TIM_DMA_CC1:
lypinator 0:bb348c97df44 3749 {
lypinator 0:bb348c97df44 3750 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
lypinator 0:bb348c97df44 3751 }
lypinator 0:bb348c97df44 3752 break;
lypinator 0:bb348c97df44 3753 case TIM_DMA_CC2:
lypinator 0:bb348c97df44 3754 {
lypinator 0:bb348c97df44 3755 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
lypinator 0:bb348c97df44 3756 }
lypinator 0:bb348c97df44 3757 break;
lypinator 0:bb348c97df44 3758 case TIM_DMA_CC3:
lypinator 0:bb348c97df44 3759 {
lypinator 0:bb348c97df44 3760 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
lypinator 0:bb348c97df44 3761 }
lypinator 0:bb348c97df44 3762 break;
lypinator 0:bb348c97df44 3763 case TIM_DMA_CC4:
lypinator 0:bb348c97df44 3764 {
lypinator 0:bb348c97df44 3765 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
lypinator 0:bb348c97df44 3766 }
lypinator 0:bb348c97df44 3767 break;
lypinator 0:bb348c97df44 3768 case TIM_DMA_COM:
lypinator 0:bb348c97df44 3769 {
lypinator 0:bb348c97df44 3770 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
lypinator 0:bb348c97df44 3771 }
lypinator 0:bb348c97df44 3772 break;
lypinator 0:bb348c97df44 3773 case TIM_DMA_TRIGGER:
lypinator 0:bb348c97df44 3774 {
lypinator 0:bb348c97df44 3775 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
lypinator 0:bb348c97df44 3776 }
lypinator 0:bb348c97df44 3777 break;
lypinator 0:bb348c97df44 3778 default:
lypinator 0:bb348c97df44 3779 break;
lypinator 0:bb348c97df44 3780 }
lypinator 0:bb348c97df44 3781
lypinator 0:bb348c97df44 3782 /* Disable the TIM Update DMA request */
lypinator 0:bb348c97df44 3783 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
lypinator 0:bb348c97df44 3784
lypinator 0:bb348c97df44 3785 /* Return function status */
lypinator 0:bb348c97df44 3786 return HAL_OK;
lypinator 0:bb348c97df44 3787 }
lypinator 0:bb348c97df44 3788
lypinator 0:bb348c97df44 3789 /**
lypinator 0:bb348c97df44 3790 * @brief Generate a software event
lypinator 0:bb348c97df44 3791 * @param htim pointer to a TIM_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 3792 * the configuration information for TIM module.
lypinator 0:bb348c97df44 3793 * @param EventSource specifies the event source.
lypinator 0:bb348c97df44 3794 * This parameter can be one of the following values:
lypinator 0:bb348c97df44 3795 * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
lypinator 0:bb348c97df44 3796 * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
lypinator 0:bb348c97df44 3797 * @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
lypinator 0:bb348c97df44 3798 * @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
lypinator 0:bb348c97df44 3799 * @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
lypinator 0:bb348c97df44 3800 * @arg TIM_EVENTSOURCE_COM: Timer COM event source
lypinator 0:bb348c97df44 3801 * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
lypinator 0:bb348c97df44 3802 * @arg TIM_EVENTSOURCE_BREAK: Timer Break event source
lypinator 0:bb348c97df44 3803 * @note TIM6 and TIM7 can only generate an update event.
lypinator 0:bb348c97df44 3804 * @note TIM_EVENTSOURCE_COM and TIM_EVENTSOURCE_BREAK are used only with TIM1 and TIM8.
lypinator 0:bb348c97df44 3805 * @retval HAL status
lypinator 0:bb348c97df44 3806 */
lypinator 0:bb348c97df44 3807
lypinator 0:bb348c97df44 3808 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
lypinator 0:bb348c97df44 3809 {
lypinator 0:bb348c97df44 3810 /* Check the parameters */
lypinator 0:bb348c97df44 3811 assert_param(IS_TIM_INSTANCE(htim->Instance));
lypinator 0:bb348c97df44 3812 assert_param(IS_TIM_EVENT_SOURCE(EventSource));
lypinator 0:bb348c97df44 3813
lypinator 0:bb348c97df44 3814 /* Process Locked */
lypinator 0:bb348c97df44 3815 __HAL_LOCK(htim);
lypinator 0:bb348c97df44 3816
lypinator 0:bb348c97df44 3817 /* Change the TIM state */
lypinator 0:bb348c97df44 3818 htim->State = HAL_TIM_STATE_BUSY;
lypinator 0:bb348c97df44 3819
lypinator 0:bb348c97df44 3820 /* Set the event sources */
lypinator 0:bb348c97df44 3821 htim->Instance->EGR = EventSource;
lypinator 0:bb348c97df44 3822
lypinator 0:bb348c97df44 3823 /* Change the TIM state */
lypinator 0:bb348c97df44 3824 htim->State = HAL_TIM_STATE_READY;
lypinator 0:bb348c97df44 3825
lypinator 0:bb348c97df44 3826 __HAL_UNLOCK(htim);
lypinator 0:bb348c97df44 3827
lypinator 0:bb348c97df44 3828 /* Return function status */
lypinator 0:bb348c97df44 3829 return HAL_OK;
lypinator 0:bb348c97df44 3830 }
lypinator 0:bb348c97df44 3831
lypinator 0:bb348c97df44 3832 /**
lypinator 0:bb348c97df44 3833 * @brief Configures the OCRef clear feature
lypinator 0:bb348c97df44 3834 * @param htim pointer to a TIM_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 3835 * the configuration information for TIM module.
lypinator 0:bb348c97df44 3836 * @param sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that
lypinator 0:bb348c97df44 3837 * contains the OCREF clear feature and parameters for the TIM peripheral.
lypinator 0:bb348c97df44 3838 * @param Channel specifies the TIM Channel.
lypinator 0:bb348c97df44 3839 * This parameter can be one of the following values:
lypinator 0:bb348c97df44 3840 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
lypinator 0:bb348c97df44 3841 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
lypinator 0:bb348c97df44 3842 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
lypinator 0:bb348c97df44 3843 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
lypinator 0:bb348c97df44 3844 * @retval HAL status
lypinator 0:bb348c97df44 3845 */
lypinator 0:bb348c97df44 3846 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel)
lypinator 0:bb348c97df44 3847 {
lypinator 0:bb348c97df44 3848 /* Check the parameters */
lypinator 0:bb348c97df44 3849 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
lypinator 0:bb348c97df44 3850 assert_param(IS_TIM_CHANNELS(Channel));
lypinator 0:bb348c97df44 3851 assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
lypinator 0:bb348c97df44 3852 assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
lypinator 0:bb348c97df44 3853 assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
lypinator 0:bb348c97df44 3854 assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
lypinator 0:bb348c97df44 3855
lypinator 0:bb348c97df44 3856 /* Process Locked */
lypinator 0:bb348c97df44 3857 __HAL_LOCK(htim);
lypinator 0:bb348c97df44 3858
lypinator 0:bb348c97df44 3859 htim->State = HAL_TIM_STATE_BUSY;
lypinator 0:bb348c97df44 3860
lypinator 0:bb348c97df44 3861 if(sClearInputConfig->ClearInputSource == TIM_CLEARINPUTSOURCE_ETR)
lypinator 0:bb348c97df44 3862 {
lypinator 0:bb348c97df44 3863 TIM_ETR_SetConfig(htim->Instance,
lypinator 0:bb348c97df44 3864 sClearInputConfig->ClearInputPrescaler,
lypinator 0:bb348c97df44 3865 sClearInputConfig->ClearInputPolarity,
lypinator 0:bb348c97df44 3866 sClearInputConfig->ClearInputFilter);
lypinator 0:bb348c97df44 3867 }
lypinator 0:bb348c97df44 3868
lypinator 0:bb348c97df44 3869 switch (Channel)
lypinator 0:bb348c97df44 3870 {
lypinator 0:bb348c97df44 3871 case TIM_CHANNEL_1:
lypinator 0:bb348c97df44 3872 {
lypinator 0:bb348c97df44 3873 if(sClearInputConfig->ClearInputState != RESET)
lypinator 0:bb348c97df44 3874 {
lypinator 0:bb348c97df44 3875 /* Enable the Ocref clear feature for Channel 1 */
lypinator 0:bb348c97df44 3876 htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE;
lypinator 0:bb348c97df44 3877 }
lypinator 0:bb348c97df44 3878 else
lypinator 0:bb348c97df44 3879 {
lypinator 0:bb348c97df44 3880 /* Disable the Ocref clear feature for Channel 1 */
lypinator 0:bb348c97df44 3881 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE;
lypinator 0:bb348c97df44 3882 }
lypinator 0:bb348c97df44 3883 }
lypinator 0:bb348c97df44 3884 break;
lypinator 0:bb348c97df44 3885 case TIM_CHANNEL_2:
lypinator 0:bb348c97df44 3886 {
lypinator 0:bb348c97df44 3887 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
lypinator 0:bb348c97df44 3888 if(sClearInputConfig->ClearInputState != RESET)
lypinator 0:bb348c97df44 3889 {
lypinator 0:bb348c97df44 3890 /* Enable the Ocref clear feature for Channel 2 */
lypinator 0:bb348c97df44 3891 htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE;
lypinator 0:bb348c97df44 3892 }
lypinator 0:bb348c97df44 3893 else
lypinator 0:bb348c97df44 3894 {
lypinator 0:bb348c97df44 3895 /* Disable the Ocref clear feature for Channel 2 */
lypinator 0:bb348c97df44 3896 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE;
lypinator 0:bb348c97df44 3897 }
lypinator 0:bb348c97df44 3898 }
lypinator 0:bb348c97df44 3899 break;
lypinator 0:bb348c97df44 3900 case TIM_CHANNEL_3:
lypinator 0:bb348c97df44 3901 {
lypinator 0:bb348c97df44 3902 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
lypinator 0:bb348c97df44 3903 if(sClearInputConfig->ClearInputState != RESET)
lypinator 0:bb348c97df44 3904 {
lypinator 0:bb348c97df44 3905 /* Enable the Ocref clear feature for Channel 3 */
lypinator 0:bb348c97df44 3906 htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE;
lypinator 0:bb348c97df44 3907 }
lypinator 0:bb348c97df44 3908 else
lypinator 0:bb348c97df44 3909 {
lypinator 0:bb348c97df44 3910 /* Disable the Ocref clear feature for Channel 3 */
lypinator 0:bb348c97df44 3911 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE;
lypinator 0:bb348c97df44 3912 }
lypinator 0:bb348c97df44 3913 }
lypinator 0:bb348c97df44 3914 break;
lypinator 0:bb348c97df44 3915 case TIM_CHANNEL_4:
lypinator 0:bb348c97df44 3916 {
lypinator 0:bb348c97df44 3917 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
lypinator 0:bb348c97df44 3918 if(sClearInputConfig->ClearInputState != RESET)
lypinator 0:bb348c97df44 3919 {
lypinator 0:bb348c97df44 3920 /* Enable the Ocref clear feature for Channel 4 */
lypinator 0:bb348c97df44 3921 htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE;
lypinator 0:bb348c97df44 3922 }
lypinator 0:bb348c97df44 3923 else
lypinator 0:bb348c97df44 3924 {
lypinator 0:bb348c97df44 3925 /* Disable the Ocref clear feature for Channel 4 */
lypinator 0:bb348c97df44 3926 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE;
lypinator 0:bb348c97df44 3927 }
lypinator 0:bb348c97df44 3928 }
lypinator 0:bb348c97df44 3929 break;
lypinator 0:bb348c97df44 3930 default:
lypinator 0:bb348c97df44 3931 break;
lypinator 0:bb348c97df44 3932 }
lypinator 0:bb348c97df44 3933
lypinator 0:bb348c97df44 3934 htim->State = HAL_TIM_STATE_READY;
lypinator 0:bb348c97df44 3935
lypinator 0:bb348c97df44 3936 __HAL_UNLOCK(htim);
lypinator 0:bb348c97df44 3937
lypinator 0:bb348c97df44 3938 return HAL_OK;
lypinator 0:bb348c97df44 3939 }
lypinator 0:bb348c97df44 3940
lypinator 0:bb348c97df44 3941 /**
lypinator 0:bb348c97df44 3942 * @brief Configures the clock source to be used
lypinator 0:bb348c97df44 3943 * @param htim pointer to a TIM_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 3944 * the configuration information for TIM module.
lypinator 0:bb348c97df44 3945 * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
lypinator 0:bb348c97df44 3946 * contains the clock source information for the TIM peripheral.
lypinator 0:bb348c97df44 3947 * @retval HAL status
lypinator 0:bb348c97df44 3948 */
lypinator 0:bb348c97df44 3949 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig)
lypinator 0:bb348c97df44 3950 {
lypinator 0:bb348c97df44 3951 uint32_t tmpsmcr = 0U;
lypinator 0:bb348c97df44 3952
lypinator 0:bb348c97df44 3953 /* Process Locked */
lypinator 0:bb348c97df44 3954 __HAL_LOCK(htim);
lypinator 0:bb348c97df44 3955
lypinator 0:bb348c97df44 3956 htim->State = HAL_TIM_STATE_BUSY;
lypinator 0:bb348c97df44 3957
lypinator 0:bb348c97df44 3958 /* Check the parameters */
lypinator 0:bb348c97df44 3959 assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
lypinator 0:bb348c97df44 3960
lypinator 0:bb348c97df44 3961 /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
lypinator 0:bb348c97df44 3962 tmpsmcr = htim->Instance->SMCR;
lypinator 0:bb348c97df44 3963 tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
lypinator 0:bb348c97df44 3964 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
lypinator 0:bb348c97df44 3965 htim->Instance->SMCR = tmpsmcr;
lypinator 0:bb348c97df44 3966
lypinator 0:bb348c97df44 3967 switch (sClockSourceConfig->ClockSource)
lypinator 0:bb348c97df44 3968 {
lypinator 0:bb348c97df44 3969 case TIM_CLOCKSOURCE_INTERNAL:
lypinator 0:bb348c97df44 3970 {
lypinator 0:bb348c97df44 3971 assert_param(IS_TIM_INSTANCE(htim->Instance));
lypinator 0:bb348c97df44 3972
lypinator 0:bb348c97df44 3973 /* Disable slave mode to clock the prescaler directly with the internal clock */
lypinator 0:bb348c97df44 3974 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
lypinator 0:bb348c97df44 3975 }
lypinator 0:bb348c97df44 3976 break;
lypinator 0:bb348c97df44 3977
lypinator 0:bb348c97df44 3978 case TIM_CLOCKSOURCE_ETRMODE1:
lypinator 0:bb348c97df44 3979 {
lypinator 0:bb348c97df44 3980 assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
lypinator 0:bb348c97df44 3981
lypinator 0:bb348c97df44 3982 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
lypinator 0:bb348c97df44 3983 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
lypinator 0:bb348c97df44 3984 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
lypinator 0:bb348c97df44 3985
lypinator 0:bb348c97df44 3986 /* Configure the ETR Clock source */
lypinator 0:bb348c97df44 3987 TIM_ETR_SetConfig(htim->Instance,
lypinator 0:bb348c97df44 3988 sClockSourceConfig->ClockPrescaler,
lypinator 0:bb348c97df44 3989 sClockSourceConfig->ClockPolarity,
lypinator 0:bb348c97df44 3990 sClockSourceConfig->ClockFilter);
lypinator 0:bb348c97df44 3991 /* Get the TIMx SMCR register value */
lypinator 0:bb348c97df44 3992 tmpsmcr = htim->Instance->SMCR;
lypinator 0:bb348c97df44 3993 /* Reset the SMS and TS Bits */
lypinator 0:bb348c97df44 3994 tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
lypinator 0:bb348c97df44 3995 /* Select the External clock mode1 and the ETRF trigger */
lypinator 0:bb348c97df44 3996 tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
lypinator 0:bb348c97df44 3997 /* Write to TIMx SMCR */
lypinator 0:bb348c97df44 3998 htim->Instance->SMCR = tmpsmcr;
lypinator 0:bb348c97df44 3999 }
lypinator 0:bb348c97df44 4000 break;
lypinator 0:bb348c97df44 4001
lypinator 0:bb348c97df44 4002 case TIM_CLOCKSOURCE_ETRMODE2:
lypinator 0:bb348c97df44 4003 {
lypinator 0:bb348c97df44 4004 assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
lypinator 0:bb348c97df44 4005
lypinator 0:bb348c97df44 4006 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
lypinator 0:bb348c97df44 4007 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
lypinator 0:bb348c97df44 4008 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
lypinator 0:bb348c97df44 4009
lypinator 0:bb348c97df44 4010 /* Configure the ETR Clock source */
lypinator 0:bb348c97df44 4011 TIM_ETR_SetConfig(htim->Instance,
lypinator 0:bb348c97df44 4012 sClockSourceConfig->ClockPrescaler,
lypinator 0:bb348c97df44 4013 sClockSourceConfig->ClockPolarity,
lypinator 0:bb348c97df44 4014 sClockSourceConfig->ClockFilter);
lypinator 0:bb348c97df44 4015 /* Enable the External clock mode2 */
lypinator 0:bb348c97df44 4016 htim->Instance->SMCR |= TIM_SMCR_ECE;
lypinator 0:bb348c97df44 4017 }
lypinator 0:bb348c97df44 4018 break;
lypinator 0:bb348c97df44 4019
lypinator 0:bb348c97df44 4020 case TIM_CLOCKSOURCE_TI1:
lypinator 0:bb348c97df44 4021 {
lypinator 0:bb348c97df44 4022 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
lypinator 0:bb348c97df44 4023
lypinator 0:bb348c97df44 4024 /* Check TI1 input conditioning related parameters */
lypinator 0:bb348c97df44 4025 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
lypinator 0:bb348c97df44 4026 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
lypinator 0:bb348c97df44 4027
lypinator 0:bb348c97df44 4028 TIM_TI1_ConfigInputStage(htim->Instance,
lypinator 0:bb348c97df44 4029 sClockSourceConfig->ClockPolarity,
lypinator 0:bb348c97df44 4030 sClockSourceConfig->ClockFilter);
lypinator 0:bb348c97df44 4031 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
lypinator 0:bb348c97df44 4032 }
lypinator 0:bb348c97df44 4033 break;
lypinator 0:bb348c97df44 4034 case TIM_CLOCKSOURCE_TI2:
lypinator 0:bb348c97df44 4035 {
lypinator 0:bb348c97df44 4036 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
lypinator 0:bb348c97df44 4037
lypinator 0:bb348c97df44 4038 /* Check TI1 input conditioning related parameters */
lypinator 0:bb348c97df44 4039 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
lypinator 0:bb348c97df44 4040 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
lypinator 0:bb348c97df44 4041
lypinator 0:bb348c97df44 4042 TIM_TI2_ConfigInputStage(htim->Instance,
lypinator 0:bb348c97df44 4043 sClockSourceConfig->ClockPolarity,
lypinator 0:bb348c97df44 4044 sClockSourceConfig->ClockFilter);
lypinator 0:bb348c97df44 4045 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
lypinator 0:bb348c97df44 4046 }
lypinator 0:bb348c97df44 4047 break;
lypinator 0:bb348c97df44 4048 case TIM_CLOCKSOURCE_TI1ED:
lypinator 0:bb348c97df44 4049 {
lypinator 0:bb348c97df44 4050 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
lypinator 0:bb348c97df44 4051
lypinator 0:bb348c97df44 4052 /* Check TI1 input conditioning related parameters */
lypinator 0:bb348c97df44 4053 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
lypinator 0:bb348c97df44 4054 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
lypinator 0:bb348c97df44 4055
lypinator 0:bb348c97df44 4056 TIM_TI1_ConfigInputStage(htim->Instance,
lypinator 0:bb348c97df44 4057 sClockSourceConfig->ClockPolarity,
lypinator 0:bb348c97df44 4058 sClockSourceConfig->ClockFilter);
lypinator 0:bb348c97df44 4059 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
lypinator 0:bb348c97df44 4060 }
lypinator 0:bb348c97df44 4061 break;
lypinator 0:bb348c97df44 4062 case TIM_CLOCKSOURCE_ITR0:
lypinator 0:bb348c97df44 4063 {
lypinator 0:bb348c97df44 4064 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
lypinator 0:bb348c97df44 4065 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR0);
lypinator 0:bb348c97df44 4066 }
lypinator 0:bb348c97df44 4067 break;
lypinator 0:bb348c97df44 4068 case TIM_CLOCKSOURCE_ITR1:
lypinator 0:bb348c97df44 4069 {
lypinator 0:bb348c97df44 4070 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
lypinator 0:bb348c97df44 4071 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR1);
lypinator 0:bb348c97df44 4072 }
lypinator 0:bb348c97df44 4073 break;
lypinator 0:bb348c97df44 4074 case TIM_CLOCKSOURCE_ITR2:
lypinator 0:bb348c97df44 4075 {
lypinator 0:bb348c97df44 4076 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
lypinator 0:bb348c97df44 4077 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR2);
lypinator 0:bb348c97df44 4078 }
lypinator 0:bb348c97df44 4079 break;
lypinator 0:bb348c97df44 4080 case TIM_CLOCKSOURCE_ITR3:
lypinator 0:bb348c97df44 4081 {
lypinator 0:bb348c97df44 4082 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
lypinator 0:bb348c97df44 4083 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR3);
lypinator 0:bb348c97df44 4084 }
lypinator 0:bb348c97df44 4085 break;
lypinator 0:bb348c97df44 4086
lypinator 0:bb348c97df44 4087 default:
lypinator 0:bb348c97df44 4088 break;
lypinator 0:bb348c97df44 4089 }
lypinator 0:bb348c97df44 4090 htim->State = HAL_TIM_STATE_READY;
lypinator 0:bb348c97df44 4091
lypinator 0:bb348c97df44 4092 __HAL_UNLOCK(htim);
lypinator 0:bb348c97df44 4093
lypinator 0:bb348c97df44 4094 return HAL_OK;
lypinator 0:bb348c97df44 4095 }
lypinator 0:bb348c97df44 4096
lypinator 0:bb348c97df44 4097 /**
lypinator 0:bb348c97df44 4098 * @brief Selects the signal connected to the TI1 input: direct from CH1_input
lypinator 0:bb348c97df44 4099 * or a XOR combination between CH1_input, CH2_input & CH3_input
lypinator 0:bb348c97df44 4100 * @param htim pointer to a TIM_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 4101 * the configuration information for TIM module.
lypinator 0:bb348c97df44 4102 * @param TI1_Selection Indicate whether or not channel 1 is connected to the
lypinator 0:bb348c97df44 4103 * output of a XOR gate.
lypinator 0:bb348c97df44 4104 * This parameter can be one of the following values:
lypinator 0:bb348c97df44 4105 * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
lypinator 0:bb348c97df44 4106 * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
lypinator 0:bb348c97df44 4107 * pins are connected to the TI1 input (XOR combination)
lypinator 0:bb348c97df44 4108 * @retval HAL status
lypinator 0:bb348c97df44 4109 */
lypinator 0:bb348c97df44 4110 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
lypinator 0:bb348c97df44 4111 {
lypinator 0:bb348c97df44 4112 uint32_t tmpcr2 = 0U;
lypinator 0:bb348c97df44 4113
lypinator 0:bb348c97df44 4114 /* Check the parameters */
lypinator 0:bb348c97df44 4115 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
lypinator 0:bb348c97df44 4116 assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
lypinator 0:bb348c97df44 4117
lypinator 0:bb348c97df44 4118 /* Get the TIMx CR2 register value */
lypinator 0:bb348c97df44 4119 tmpcr2 = htim->Instance->CR2;
lypinator 0:bb348c97df44 4120
lypinator 0:bb348c97df44 4121 /* Reset the TI1 selection */
lypinator 0:bb348c97df44 4122 tmpcr2 &= ~TIM_CR2_TI1S;
lypinator 0:bb348c97df44 4123
lypinator 0:bb348c97df44 4124 /* Set the TI1 selection */
lypinator 0:bb348c97df44 4125 tmpcr2 |= TI1_Selection;
lypinator 0:bb348c97df44 4126
lypinator 0:bb348c97df44 4127 /* Write to TIMxCR2 */
lypinator 0:bb348c97df44 4128 htim->Instance->CR2 = tmpcr2;
lypinator 0:bb348c97df44 4129
lypinator 0:bb348c97df44 4130 return HAL_OK;
lypinator 0:bb348c97df44 4131 }
lypinator 0:bb348c97df44 4132
lypinator 0:bb348c97df44 4133 /**
lypinator 0:bb348c97df44 4134 * @brief Configures the TIM in Slave mode
lypinator 0:bb348c97df44 4135 * @param htim pointer to a TIM_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 4136 * the configuration information for TIM module.
lypinator 0:bb348c97df44 4137 * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
lypinator 0:bb348c97df44 4138 * contains the selected trigger (internal trigger input, filtered
lypinator 0:bb348c97df44 4139 * timer input or external trigger input) and the ) and the Slave
lypinator 0:bb348c97df44 4140 * mode (Disable, Reset, Gated, Trigger, External clock mode 1).
lypinator 0:bb348c97df44 4141 * @retval HAL status
lypinator 0:bb348c97df44 4142 */
lypinator 0:bb348c97df44 4143 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig)
lypinator 0:bb348c97df44 4144 {
lypinator 0:bb348c97df44 4145 /* Check the parameters */
lypinator 0:bb348c97df44 4146 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
lypinator 0:bb348c97df44 4147 assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
lypinator 0:bb348c97df44 4148 assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
lypinator 0:bb348c97df44 4149
lypinator 0:bb348c97df44 4150 __HAL_LOCK(htim);
lypinator 0:bb348c97df44 4151
lypinator 0:bb348c97df44 4152 htim->State = HAL_TIM_STATE_BUSY;
lypinator 0:bb348c97df44 4153
lypinator 0:bb348c97df44 4154 TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
lypinator 0:bb348c97df44 4155
lypinator 0:bb348c97df44 4156 /* Disable Trigger Interrupt */
lypinator 0:bb348c97df44 4157 __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
lypinator 0:bb348c97df44 4158
lypinator 0:bb348c97df44 4159 /* Disable Trigger DMA request */
lypinator 0:bb348c97df44 4160 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
lypinator 0:bb348c97df44 4161
lypinator 0:bb348c97df44 4162 htim->State = HAL_TIM_STATE_READY;
lypinator 0:bb348c97df44 4163
lypinator 0:bb348c97df44 4164 __HAL_UNLOCK(htim);
lypinator 0:bb348c97df44 4165
lypinator 0:bb348c97df44 4166 return HAL_OK;
lypinator 0:bb348c97df44 4167 }
lypinator 0:bb348c97df44 4168
lypinator 0:bb348c97df44 4169 /**
lypinator 0:bb348c97df44 4170 * @brief Configures the TIM in Slave mode in interrupt mode
lypinator 0:bb348c97df44 4171 * @param htim TIM handle.
lypinator 0:bb348c97df44 4172 * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
lypinator 0:bb348c97df44 4173 * contains the selected trigger (internal trigger input, filtered
lypinator 0:bb348c97df44 4174 * timer input or external trigger input) and the ) and the Slave
lypinator 0:bb348c97df44 4175 * mode (Disable, Reset, Gated, Trigger, External clock mode 1).
lypinator 0:bb348c97df44 4176 * @retval HAL status
lypinator 0:bb348c97df44 4177 */
lypinator 0:bb348c97df44 4178 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim,
lypinator 0:bb348c97df44 4179 TIM_SlaveConfigTypeDef * sSlaveConfig)
lypinator 0:bb348c97df44 4180 {
lypinator 0:bb348c97df44 4181 /* Check the parameters */
lypinator 0:bb348c97df44 4182 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
lypinator 0:bb348c97df44 4183 assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
lypinator 0:bb348c97df44 4184 assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
lypinator 0:bb348c97df44 4185
lypinator 0:bb348c97df44 4186 __HAL_LOCK(htim);
lypinator 0:bb348c97df44 4187
lypinator 0:bb348c97df44 4188 htim->State = HAL_TIM_STATE_BUSY;
lypinator 0:bb348c97df44 4189
lypinator 0:bb348c97df44 4190 TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
lypinator 0:bb348c97df44 4191
lypinator 0:bb348c97df44 4192 /* Enable Trigger Interrupt */
lypinator 0:bb348c97df44 4193 __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
lypinator 0:bb348c97df44 4194
lypinator 0:bb348c97df44 4195 /* Disable Trigger DMA request */
lypinator 0:bb348c97df44 4196 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
lypinator 0:bb348c97df44 4197
lypinator 0:bb348c97df44 4198 htim->State = HAL_TIM_STATE_READY;
lypinator 0:bb348c97df44 4199
lypinator 0:bb348c97df44 4200 __HAL_UNLOCK(htim);
lypinator 0:bb348c97df44 4201
lypinator 0:bb348c97df44 4202 return HAL_OK;
lypinator 0:bb348c97df44 4203 }
lypinator 0:bb348c97df44 4204
lypinator 0:bb348c97df44 4205 /**
lypinator 0:bb348c97df44 4206 * @brief Read the captured value from Capture Compare unit
lypinator 0:bb348c97df44 4207 * @param htim pointer to a TIM_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 4208 * the configuration information for TIM module.
lypinator 0:bb348c97df44 4209 * @param Channel TIM Channels to be enabled.
lypinator 0:bb348c97df44 4210 * This parameter can be one of the following values:
lypinator 0:bb348c97df44 4211 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
lypinator 0:bb348c97df44 4212 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
lypinator 0:bb348c97df44 4213 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
lypinator 0:bb348c97df44 4214 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
lypinator 0:bb348c97df44 4215 * @retval Captured value
lypinator 0:bb348c97df44 4216 */
lypinator 0:bb348c97df44 4217 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
lypinator 0:bb348c97df44 4218 {
lypinator 0:bb348c97df44 4219 uint32_t tmpreg = 0U;
lypinator 0:bb348c97df44 4220
lypinator 0:bb348c97df44 4221 __HAL_LOCK(htim);
lypinator 0:bb348c97df44 4222
lypinator 0:bb348c97df44 4223 switch (Channel)
lypinator 0:bb348c97df44 4224 {
lypinator 0:bb348c97df44 4225 case TIM_CHANNEL_1:
lypinator 0:bb348c97df44 4226 {
lypinator 0:bb348c97df44 4227 /* Check the parameters */
lypinator 0:bb348c97df44 4228 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
lypinator 0:bb348c97df44 4229
lypinator 0:bb348c97df44 4230 /* Return the capture 1 value */
lypinator 0:bb348c97df44 4231 tmpreg = htim->Instance->CCR1;
lypinator 0:bb348c97df44 4232
lypinator 0:bb348c97df44 4233 break;
lypinator 0:bb348c97df44 4234 }
lypinator 0:bb348c97df44 4235 case TIM_CHANNEL_2:
lypinator 0:bb348c97df44 4236 {
lypinator 0:bb348c97df44 4237 /* Check the parameters */
lypinator 0:bb348c97df44 4238 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
lypinator 0:bb348c97df44 4239
lypinator 0:bb348c97df44 4240 /* Return the capture 2 value */
lypinator 0:bb348c97df44 4241 tmpreg = htim->Instance->CCR2;
lypinator 0:bb348c97df44 4242
lypinator 0:bb348c97df44 4243 break;
lypinator 0:bb348c97df44 4244 }
lypinator 0:bb348c97df44 4245
lypinator 0:bb348c97df44 4246 case TIM_CHANNEL_3:
lypinator 0:bb348c97df44 4247 {
lypinator 0:bb348c97df44 4248 /* Check the parameters */
lypinator 0:bb348c97df44 4249 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
lypinator 0:bb348c97df44 4250
lypinator 0:bb348c97df44 4251 /* Return the capture 3 value */
lypinator 0:bb348c97df44 4252 tmpreg = htim->Instance->CCR3;
lypinator 0:bb348c97df44 4253
lypinator 0:bb348c97df44 4254 break;
lypinator 0:bb348c97df44 4255 }
lypinator 0:bb348c97df44 4256
lypinator 0:bb348c97df44 4257 case TIM_CHANNEL_4:
lypinator 0:bb348c97df44 4258 {
lypinator 0:bb348c97df44 4259 /* Check the parameters */
lypinator 0:bb348c97df44 4260 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
lypinator 0:bb348c97df44 4261
lypinator 0:bb348c97df44 4262 /* Return the capture 4 value */
lypinator 0:bb348c97df44 4263 tmpreg = htim->Instance->CCR4;
lypinator 0:bb348c97df44 4264
lypinator 0:bb348c97df44 4265 break;
lypinator 0:bb348c97df44 4266 }
lypinator 0:bb348c97df44 4267
lypinator 0:bb348c97df44 4268 default:
lypinator 0:bb348c97df44 4269 break;
lypinator 0:bb348c97df44 4270 }
lypinator 0:bb348c97df44 4271
lypinator 0:bb348c97df44 4272 __HAL_UNLOCK(htim);
lypinator 0:bb348c97df44 4273 return tmpreg;
lypinator 0:bb348c97df44 4274 }
lypinator 0:bb348c97df44 4275 /**
lypinator 0:bb348c97df44 4276 * @}
lypinator 0:bb348c97df44 4277 */
lypinator 0:bb348c97df44 4278
lypinator 0:bb348c97df44 4279 /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
lypinator 0:bb348c97df44 4280 * @brief TIM Callbacks functions
lypinator 0:bb348c97df44 4281 *
lypinator 0:bb348c97df44 4282 @verbatim
lypinator 0:bb348c97df44 4283 ==============================================================================
lypinator 0:bb348c97df44 4284 ##### TIM Callbacks functions #####
lypinator 0:bb348c97df44 4285 ==============================================================================
lypinator 0:bb348c97df44 4286 [..]
lypinator 0:bb348c97df44 4287 This section provides TIM callback functions:
lypinator 0:bb348c97df44 4288 (+) Timer Period elapsed callback
lypinator 0:bb348c97df44 4289 (+) Timer Output Compare callback
lypinator 0:bb348c97df44 4290 (+) Timer Input capture callback
lypinator 0:bb348c97df44 4291 (+) Timer Trigger callback
lypinator 0:bb348c97df44 4292 (+) Timer Error callback
lypinator 0:bb348c97df44 4293
lypinator 0:bb348c97df44 4294 @endverbatim
lypinator 0:bb348c97df44 4295 * @{
lypinator 0:bb348c97df44 4296 */
lypinator 0:bb348c97df44 4297
lypinator 0:bb348c97df44 4298 /**
lypinator 0:bb348c97df44 4299 * @brief Period elapsed callback in non blocking mode
lypinator 0:bb348c97df44 4300 * @param htim pointer to a TIM_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 4301 * the configuration information for TIM module.
lypinator 0:bb348c97df44 4302 * @retval None
lypinator 0:bb348c97df44 4303 */
lypinator 0:bb348c97df44 4304 __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
lypinator 0:bb348c97df44 4305 {
lypinator 0:bb348c97df44 4306 /* Prevent unused argument(s) compilation warning */
lypinator 0:bb348c97df44 4307 UNUSED(htim);
lypinator 0:bb348c97df44 4308 /* NOTE : This function Should not be modified, when the callback is needed,
lypinator 0:bb348c97df44 4309 the __HAL_TIM_PeriodElapsedCallback could be implemented in the user file
lypinator 0:bb348c97df44 4310 */
lypinator 0:bb348c97df44 4311 }
lypinator 0:bb348c97df44 4312
lypinator 0:bb348c97df44 4313 /**
lypinator 0:bb348c97df44 4314 * @brief Output Compare callback in non blocking mode
lypinator 0:bb348c97df44 4315 * @param htim pointer to a TIM_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 4316 * the configuration information for TIM module.
lypinator 0:bb348c97df44 4317 * @retval None
lypinator 0:bb348c97df44 4318 */
lypinator 0:bb348c97df44 4319 __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
lypinator 0:bb348c97df44 4320 {
lypinator 0:bb348c97df44 4321 /* Prevent unused argument(s) compilation warning */
lypinator 0:bb348c97df44 4322 UNUSED(htim);
lypinator 0:bb348c97df44 4323 /* NOTE : This function Should not be modified, when the callback is needed,
lypinator 0:bb348c97df44 4324 the __HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
lypinator 0:bb348c97df44 4325 */
lypinator 0:bb348c97df44 4326 }
lypinator 0:bb348c97df44 4327
lypinator 0:bb348c97df44 4328 /**
lypinator 0:bb348c97df44 4329 * @brief Input Capture callback in non blocking mode
lypinator 0:bb348c97df44 4330 * @param htim pointer to a TIM_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 4331 * the configuration information for TIM module.
lypinator 0:bb348c97df44 4332 * @retval None
lypinator 0:bb348c97df44 4333 */
lypinator 0:bb348c97df44 4334 __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
lypinator 0:bb348c97df44 4335 {
lypinator 0:bb348c97df44 4336 /* Prevent unused argument(s) compilation warning */
lypinator 0:bb348c97df44 4337 UNUSED(htim);
lypinator 0:bb348c97df44 4338 /* NOTE : This function Should not be modified, when the callback is needed,
lypinator 0:bb348c97df44 4339 the __HAL_TIM_IC_CaptureCallback could be implemented in the user file
lypinator 0:bb348c97df44 4340 */
lypinator 0:bb348c97df44 4341 }
lypinator 0:bb348c97df44 4342
lypinator 0:bb348c97df44 4343 /**
lypinator 0:bb348c97df44 4344 * @brief PWM Pulse finished callback in non blocking mode
lypinator 0:bb348c97df44 4345 * @param htim pointer to a TIM_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 4346 * the configuration information for TIM module.
lypinator 0:bb348c97df44 4347 * @retval None
lypinator 0:bb348c97df44 4348 */
lypinator 0:bb348c97df44 4349 __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
lypinator 0:bb348c97df44 4350 {
lypinator 0:bb348c97df44 4351 /* Prevent unused argument(s) compilation warning */
lypinator 0:bb348c97df44 4352 UNUSED(htim);
lypinator 0:bb348c97df44 4353 /* NOTE : This function Should not be modified, when the callback is needed,
lypinator 0:bb348c97df44 4354 the __HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
lypinator 0:bb348c97df44 4355 */
lypinator 0:bb348c97df44 4356 }
lypinator 0:bb348c97df44 4357
lypinator 0:bb348c97df44 4358 /**
lypinator 0:bb348c97df44 4359 * @brief Hall Trigger detection callback in non blocking mode
lypinator 0:bb348c97df44 4360 * @param htim pointer to a TIM_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 4361 * the configuration information for TIM module.
lypinator 0:bb348c97df44 4362 * @retval None
lypinator 0:bb348c97df44 4363 */
lypinator 0:bb348c97df44 4364 __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
lypinator 0:bb348c97df44 4365 {
lypinator 0:bb348c97df44 4366 /* Prevent unused argument(s) compilation warning */
lypinator 0:bb348c97df44 4367 UNUSED(htim);
lypinator 0:bb348c97df44 4368 /* NOTE : This function Should not be modified, when the callback is needed,
lypinator 0:bb348c97df44 4369 the HAL_TIM_TriggerCallback could be implemented in the user file
lypinator 0:bb348c97df44 4370 */
lypinator 0:bb348c97df44 4371 }
lypinator 0:bb348c97df44 4372
lypinator 0:bb348c97df44 4373 /**
lypinator 0:bb348c97df44 4374 * @brief Timer error callback in non blocking mode
lypinator 0:bb348c97df44 4375 * @param htim pointer to a TIM_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 4376 * the configuration information for TIM module.
lypinator 0:bb348c97df44 4377 * @retval None
lypinator 0:bb348c97df44 4378 */
lypinator 0:bb348c97df44 4379 __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
lypinator 0:bb348c97df44 4380 {
lypinator 0:bb348c97df44 4381 /* Prevent unused argument(s) compilation warning */
lypinator 0:bb348c97df44 4382 UNUSED(htim);
lypinator 0:bb348c97df44 4383 /* NOTE : This function Should not be modified, when the callback is needed,
lypinator 0:bb348c97df44 4384 the HAL_TIM_ErrorCallback could be implemented in the user file
lypinator 0:bb348c97df44 4385 */
lypinator 0:bb348c97df44 4386 }
lypinator 0:bb348c97df44 4387 /**
lypinator 0:bb348c97df44 4388 * @}
lypinator 0:bb348c97df44 4389 */
lypinator 0:bb348c97df44 4390
lypinator 0:bb348c97df44 4391 /** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions
lypinator 0:bb348c97df44 4392 * @brief Peripheral State functions
lypinator 0:bb348c97df44 4393 *
lypinator 0:bb348c97df44 4394 @verbatim
lypinator 0:bb348c97df44 4395 ==============================================================================
lypinator 0:bb348c97df44 4396 ##### Peripheral State functions #####
lypinator 0:bb348c97df44 4397 ==============================================================================
lypinator 0:bb348c97df44 4398 [..]
lypinator 0:bb348c97df44 4399 This subsection permits to get in run-time the status of the peripheral
lypinator 0:bb348c97df44 4400 and the data flow.
lypinator 0:bb348c97df44 4401
lypinator 0:bb348c97df44 4402 @endverbatim
lypinator 0:bb348c97df44 4403 * @{
lypinator 0:bb348c97df44 4404 */
lypinator 0:bb348c97df44 4405
lypinator 0:bb348c97df44 4406 /**
lypinator 0:bb348c97df44 4407 * @brief Return the TIM Base state
lypinator 0:bb348c97df44 4408 * @param htim pointer to a TIM_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 4409 * the configuration information for TIM module.
lypinator 0:bb348c97df44 4410 * @retval HAL state
lypinator 0:bb348c97df44 4411 */
lypinator 0:bb348c97df44 4412 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
lypinator 0:bb348c97df44 4413 {
lypinator 0:bb348c97df44 4414 return htim->State;
lypinator 0:bb348c97df44 4415 }
lypinator 0:bb348c97df44 4416
lypinator 0:bb348c97df44 4417 /**
lypinator 0:bb348c97df44 4418 * @brief Return the TIM OC state
lypinator 0:bb348c97df44 4419 * @param htim pointer to a TIM_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 4420 * the configuration information for TIM module.
lypinator 0:bb348c97df44 4421 * @retval HAL state
lypinator 0:bb348c97df44 4422 */
lypinator 0:bb348c97df44 4423 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
lypinator 0:bb348c97df44 4424 {
lypinator 0:bb348c97df44 4425 return htim->State;
lypinator 0:bb348c97df44 4426 }
lypinator 0:bb348c97df44 4427
lypinator 0:bb348c97df44 4428 /**
lypinator 0:bb348c97df44 4429 * @brief Return the TIM PWM state
lypinator 0:bb348c97df44 4430 * @param htim pointer to a TIM_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 4431 * the configuration information for TIM module.
lypinator 0:bb348c97df44 4432 * @retval HAL state
lypinator 0:bb348c97df44 4433 */
lypinator 0:bb348c97df44 4434 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
lypinator 0:bb348c97df44 4435 {
lypinator 0:bb348c97df44 4436 return htim->State;
lypinator 0:bb348c97df44 4437 }
lypinator 0:bb348c97df44 4438
lypinator 0:bb348c97df44 4439 /**
lypinator 0:bb348c97df44 4440 * @brief Return the TIM Input Capture state
lypinator 0:bb348c97df44 4441 * @param htim pointer to a TIM_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 4442 * the configuration information for TIM module.
lypinator 0:bb348c97df44 4443 * @retval HAL state
lypinator 0:bb348c97df44 4444 */
lypinator 0:bb348c97df44 4445 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
lypinator 0:bb348c97df44 4446 {
lypinator 0:bb348c97df44 4447 return htim->State;
lypinator 0:bb348c97df44 4448 }
lypinator 0:bb348c97df44 4449
lypinator 0:bb348c97df44 4450 /**
lypinator 0:bb348c97df44 4451 * @brief Return the TIM One Pulse Mode state
lypinator 0:bb348c97df44 4452 * @param htim pointer to a TIM_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 4453 * the configuration information for TIM module.
lypinator 0:bb348c97df44 4454 * @retval HAL state
lypinator 0:bb348c97df44 4455 */
lypinator 0:bb348c97df44 4456 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
lypinator 0:bb348c97df44 4457 {
lypinator 0:bb348c97df44 4458 return htim->State;
lypinator 0:bb348c97df44 4459 }
lypinator 0:bb348c97df44 4460
lypinator 0:bb348c97df44 4461 /**
lypinator 0:bb348c97df44 4462 * @brief Return the TIM Encoder Mode state
lypinator 0:bb348c97df44 4463 * @param htim pointer to a TIM_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 4464 * the configuration information for TIM module.
lypinator 0:bb348c97df44 4465 * @retval HAL state
lypinator 0:bb348c97df44 4466 */
lypinator 0:bb348c97df44 4467 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
lypinator 0:bb348c97df44 4468 {
lypinator 0:bb348c97df44 4469 return htim->State;
lypinator 0:bb348c97df44 4470 }
lypinator 0:bb348c97df44 4471 /**
lypinator 0:bb348c97df44 4472 * @}
lypinator 0:bb348c97df44 4473 */
lypinator 0:bb348c97df44 4474
lypinator 0:bb348c97df44 4475 /**
lypinator 0:bb348c97df44 4476 * @brief Time Base configuration
lypinator 0:bb348c97df44 4477 * @param TIMx TIM peripheral
lypinator 0:bb348c97df44 4478 * @param Structure pointer on TIM Time Base required parameters
lypinator 0:bb348c97df44 4479 * @retval None
lypinator 0:bb348c97df44 4480 */
lypinator 0:bb348c97df44 4481 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
lypinator 0:bb348c97df44 4482 {
lypinator 0:bb348c97df44 4483 uint32_t tmpcr1 = 0U;
lypinator 0:bb348c97df44 4484 tmpcr1 = TIMx->CR1;
lypinator 0:bb348c97df44 4485
lypinator 0:bb348c97df44 4486 /* Set TIM Time Base Unit parameters ---------------------------------------*/
lypinator 0:bb348c97df44 4487 if(IS_TIM_CC3_INSTANCE(TIMx) != RESET)
lypinator 0:bb348c97df44 4488 {
lypinator 0:bb348c97df44 4489 /* Select the Counter Mode */
lypinator 0:bb348c97df44 4490 tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
lypinator 0:bb348c97df44 4491 tmpcr1 |= Structure->CounterMode;
lypinator 0:bb348c97df44 4492 }
lypinator 0:bb348c97df44 4493
lypinator 0:bb348c97df44 4494 if(IS_TIM_CC1_INSTANCE(TIMx) != RESET)
lypinator 0:bb348c97df44 4495 {
lypinator 0:bb348c97df44 4496 /* Set the clock division */
lypinator 0:bb348c97df44 4497 tmpcr1 &= ~TIM_CR1_CKD;
lypinator 0:bb348c97df44 4498 tmpcr1 |= (uint32_t)Structure->ClockDivision;
lypinator 0:bb348c97df44 4499 }
lypinator 0:bb348c97df44 4500
lypinator 0:bb348c97df44 4501 TIMx->CR1 = tmpcr1;
lypinator 0:bb348c97df44 4502
lypinator 0:bb348c97df44 4503 /* Set the Auto-reload value */
lypinator 0:bb348c97df44 4504 TIMx->ARR = (uint32_t)Structure->Period ;
lypinator 0:bb348c97df44 4505
lypinator 0:bb348c97df44 4506 /* Set the Prescaler value */
lypinator 0:bb348c97df44 4507 TIMx->PSC = (uint32_t)Structure->Prescaler;
lypinator 0:bb348c97df44 4508
lypinator 0:bb348c97df44 4509 if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
lypinator 0:bb348c97df44 4510 {
lypinator 0:bb348c97df44 4511 /* Set the Repetition Counter value */
lypinator 0:bb348c97df44 4512 TIMx->RCR = Structure->RepetitionCounter;
lypinator 0:bb348c97df44 4513 }
lypinator 0:bb348c97df44 4514
lypinator 0:bb348c97df44 4515 /* Generate an update event to reload the Prescaler
lypinator 0:bb348c97df44 4516 and the repetition counter(only for TIM1 and TIM8) value immediately */
lypinator 0:bb348c97df44 4517 TIMx->EGR = TIM_EGR_UG;
lypinator 0:bb348c97df44 4518 }
lypinator 0:bb348c97df44 4519
lypinator 0:bb348c97df44 4520 /**
lypinator 0:bb348c97df44 4521 * @brief Configure the TI1 as Input.
lypinator 0:bb348c97df44 4522 * @param TIMx to select the TIM peripheral.
lypinator 0:bb348c97df44 4523 * @param TIM_ICPolarity The Input Polarity.
lypinator 0:bb348c97df44 4524 * This parameter can be one of the following values:
lypinator 0:bb348c97df44 4525 * @arg TIM_ICPolarity_Rising
lypinator 0:bb348c97df44 4526 * @arg TIM_ICPolarity_Falling
lypinator 0:bb348c97df44 4527 * @arg TIM_ICPolarity_BothEdge
lypinator 0:bb348c97df44 4528 * @param TIM_ICSelection specifies the input to be used.
lypinator 0:bb348c97df44 4529 * This parameter can be one of the following values:
lypinator 0:bb348c97df44 4530 * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.
lypinator 0:bb348c97df44 4531 * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.
lypinator 0:bb348c97df44 4532 * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.
lypinator 0:bb348c97df44 4533 * @param TIM_ICFilter Specifies the Input Capture Filter.
lypinator 0:bb348c97df44 4534 * This parameter must be a value between 0x00 and 0x0F.
lypinator 0:bb348c97df44 4535 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
lypinator 0:bb348c97df44 4536 * (on channel2 path) is used as the input signal. Therefore CCMR1 must be
lypinator 0:bb348c97df44 4537 * protected against un-initialized filter and polarity values.
lypinator 0:bb348c97df44 4538 * @retval None
lypinator 0:bb348c97df44 4539 */
lypinator 0:bb348c97df44 4540 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
lypinator 0:bb348c97df44 4541 uint32_t TIM_ICFilter)
lypinator 0:bb348c97df44 4542 {
lypinator 0:bb348c97df44 4543 uint32_t tmpccmr1 = 0U;
lypinator 0:bb348c97df44 4544 uint32_t tmpccer = 0U;
lypinator 0:bb348c97df44 4545
lypinator 0:bb348c97df44 4546 /* Disable the Channel 1: Reset the CC1E Bit */
lypinator 0:bb348c97df44 4547 TIMx->CCER &= ~TIM_CCER_CC1E;
lypinator 0:bb348c97df44 4548 tmpccmr1 = TIMx->CCMR1;
lypinator 0:bb348c97df44 4549 tmpccer = TIMx->CCER;
lypinator 0:bb348c97df44 4550
lypinator 0:bb348c97df44 4551 /* Select the Input */
lypinator 0:bb348c97df44 4552 if(IS_TIM_CC2_INSTANCE(TIMx) != RESET)
lypinator 0:bb348c97df44 4553 {
lypinator 0:bb348c97df44 4554 tmpccmr1 &= ~TIM_CCMR1_CC1S;
lypinator 0:bb348c97df44 4555 tmpccmr1 |= TIM_ICSelection;
lypinator 0:bb348c97df44 4556 }
lypinator 0:bb348c97df44 4557 else
lypinator 0:bb348c97df44 4558 {
lypinator 0:bb348c97df44 4559 tmpccmr1 &= ~TIM_CCMR1_CC1S;
lypinator 0:bb348c97df44 4560 tmpccmr1 |= TIM_CCMR1_CC1S_0;
lypinator 0:bb348c97df44 4561 }
lypinator 0:bb348c97df44 4562
lypinator 0:bb348c97df44 4563 /* Set the filter */
lypinator 0:bb348c97df44 4564 tmpccmr1 &= ~TIM_CCMR1_IC1F;
lypinator 0:bb348c97df44 4565 tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F);
lypinator 0:bb348c97df44 4566
lypinator 0:bb348c97df44 4567 /* Select the Polarity and set the CC1E Bit */
lypinator 0:bb348c97df44 4568 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
lypinator 0:bb348c97df44 4569 tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
lypinator 0:bb348c97df44 4570
lypinator 0:bb348c97df44 4571 /* Write to TIMx CCMR1 and CCER registers */
lypinator 0:bb348c97df44 4572 TIMx->CCMR1 = tmpccmr1;
lypinator 0:bb348c97df44 4573 TIMx->CCER = tmpccer;
lypinator 0:bb348c97df44 4574 }
lypinator 0:bb348c97df44 4575
lypinator 0:bb348c97df44 4576 /**
lypinator 0:bb348c97df44 4577 * @brief Time Output Compare 2 configuration
lypinator 0:bb348c97df44 4578 * @param TIMx to select the TIM peripheral
lypinator 0:bb348c97df44 4579 * @param OC_Config The output configuration structure
lypinator 0:bb348c97df44 4580 * @retval None
lypinator 0:bb348c97df44 4581 */
lypinator 0:bb348c97df44 4582 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
lypinator 0:bb348c97df44 4583 {
lypinator 0:bb348c97df44 4584 uint32_t tmpccmrx = 0U;
lypinator 0:bb348c97df44 4585 uint32_t tmpccer = 0U;
lypinator 0:bb348c97df44 4586 uint32_t tmpcr2 = 0U;
lypinator 0:bb348c97df44 4587
lypinator 0:bb348c97df44 4588 /* Disable the Channel 2: Reset the CC2E Bit */
lypinator 0:bb348c97df44 4589 TIMx->CCER &= ~TIM_CCER_CC2E;
lypinator 0:bb348c97df44 4590
lypinator 0:bb348c97df44 4591 /* Get the TIMx CCER register value */
lypinator 0:bb348c97df44 4592 tmpccer = TIMx->CCER;
lypinator 0:bb348c97df44 4593 /* Get the TIMx CR2 register value */
lypinator 0:bb348c97df44 4594 tmpcr2 = TIMx->CR2;
lypinator 0:bb348c97df44 4595
lypinator 0:bb348c97df44 4596 /* Get the TIMx CCMR1 register value */
lypinator 0:bb348c97df44 4597 tmpccmrx = TIMx->CCMR1;
lypinator 0:bb348c97df44 4598
lypinator 0:bb348c97df44 4599 /* Reset the Output Compare mode and Capture/Compare selection Bits */
lypinator 0:bb348c97df44 4600 tmpccmrx &= ~TIM_CCMR1_OC2M;
lypinator 0:bb348c97df44 4601 tmpccmrx &= ~TIM_CCMR1_CC2S;
lypinator 0:bb348c97df44 4602
lypinator 0:bb348c97df44 4603 /* Select the Output Compare Mode */
lypinator 0:bb348c97df44 4604 tmpccmrx |= (OC_Config->OCMode << 8U);
lypinator 0:bb348c97df44 4605
lypinator 0:bb348c97df44 4606 /* Reset the Output Polarity level */
lypinator 0:bb348c97df44 4607 tmpccer &= ~TIM_CCER_CC2P;
lypinator 0:bb348c97df44 4608 /* Set the Output Compare Polarity */
lypinator 0:bb348c97df44 4609 tmpccer |= (OC_Config->OCPolarity << 4U);
lypinator 0:bb348c97df44 4610
lypinator 0:bb348c97df44 4611 if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
lypinator 0:bb348c97df44 4612 {
lypinator 0:bb348c97df44 4613 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
lypinator 0:bb348c97df44 4614
lypinator 0:bb348c97df44 4615 /* Reset the Output N Polarity level */
lypinator 0:bb348c97df44 4616 tmpccer &= ~TIM_CCER_CC2NP;
lypinator 0:bb348c97df44 4617 /* Set the Output N Polarity */
lypinator 0:bb348c97df44 4618 tmpccer |= (OC_Config->OCNPolarity << 4U);
lypinator 0:bb348c97df44 4619 /* Reset the Output N State */
lypinator 0:bb348c97df44 4620 tmpccer &= ~TIM_CCER_CC2NE;
lypinator 0:bb348c97df44 4621
lypinator 0:bb348c97df44 4622 /* Reset the Output Compare and Output Compare N IDLE State */
lypinator 0:bb348c97df44 4623 tmpcr2 &= ~TIM_CR2_OIS2;
lypinator 0:bb348c97df44 4624 tmpcr2 &= ~TIM_CR2_OIS2N;
lypinator 0:bb348c97df44 4625 /* Set the Output Idle state */
lypinator 0:bb348c97df44 4626 tmpcr2 |= (OC_Config->OCIdleState << 2U);
lypinator 0:bb348c97df44 4627 /* Set the Output N Idle state */
lypinator 0:bb348c97df44 4628 tmpcr2 |= (OC_Config->OCNIdleState << 2U);
lypinator 0:bb348c97df44 4629 }
lypinator 0:bb348c97df44 4630 /* Write to TIMx CR2 */
lypinator 0:bb348c97df44 4631 TIMx->CR2 = tmpcr2;
lypinator 0:bb348c97df44 4632
lypinator 0:bb348c97df44 4633 /* Write to TIMx CCMR1 */
lypinator 0:bb348c97df44 4634 TIMx->CCMR1 = tmpccmrx;
lypinator 0:bb348c97df44 4635
lypinator 0:bb348c97df44 4636 /* Set the Capture Compare Register value */
lypinator 0:bb348c97df44 4637 TIMx->CCR2 = OC_Config->Pulse;
lypinator 0:bb348c97df44 4638
lypinator 0:bb348c97df44 4639 /* Write to TIMx CCER */
lypinator 0:bb348c97df44 4640 TIMx->CCER = tmpccer;
lypinator 0:bb348c97df44 4641 }
lypinator 0:bb348c97df44 4642
lypinator 0:bb348c97df44 4643 /**
lypinator 0:bb348c97df44 4644 * @brief TIM DMA Delay Pulse complete callback.
lypinator 0:bb348c97df44 4645 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 4646 * the configuration information for the specified DMA module.
lypinator 0:bb348c97df44 4647 * @retval None
lypinator 0:bb348c97df44 4648 */
lypinator 0:bb348c97df44 4649 void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
lypinator 0:bb348c97df44 4650 {
lypinator 0:bb348c97df44 4651 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
lypinator 0:bb348c97df44 4652
lypinator 0:bb348c97df44 4653 htim->State= HAL_TIM_STATE_READY;
lypinator 0:bb348c97df44 4654
lypinator 0:bb348c97df44 4655 if(hdma == htim->hdma[TIM_DMA_ID_CC1])
lypinator 0:bb348c97df44 4656 {
lypinator 0:bb348c97df44 4657 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
lypinator 0:bb348c97df44 4658 }
lypinator 0:bb348c97df44 4659 else if(hdma == htim->hdma[TIM_DMA_ID_CC2])
lypinator 0:bb348c97df44 4660 {
lypinator 0:bb348c97df44 4661 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
lypinator 0:bb348c97df44 4662 }
lypinator 0:bb348c97df44 4663 else if(hdma == htim->hdma[TIM_DMA_ID_CC3])
lypinator 0:bb348c97df44 4664 {
lypinator 0:bb348c97df44 4665 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
lypinator 0:bb348c97df44 4666 }
lypinator 0:bb348c97df44 4667 else if(hdma == htim->hdma[TIM_DMA_ID_CC4])
lypinator 0:bb348c97df44 4668 {
lypinator 0:bb348c97df44 4669 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
lypinator 0:bb348c97df44 4670 }
lypinator 0:bb348c97df44 4671
lypinator 0:bb348c97df44 4672 HAL_TIM_PWM_PulseFinishedCallback(htim);
lypinator 0:bb348c97df44 4673
lypinator 0:bb348c97df44 4674 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
lypinator 0:bb348c97df44 4675 }
lypinator 0:bb348c97df44 4676
lypinator 0:bb348c97df44 4677 /**
lypinator 0:bb348c97df44 4678 * @brief TIM DMA error callback
lypinator 0:bb348c97df44 4679 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 4680 * the configuration information for the specified DMA module.
lypinator 0:bb348c97df44 4681 * @retval None
lypinator 0:bb348c97df44 4682 */
lypinator 0:bb348c97df44 4683 void TIM_DMAError(DMA_HandleTypeDef *hdma)
lypinator 0:bb348c97df44 4684 {
lypinator 0:bb348c97df44 4685 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
lypinator 0:bb348c97df44 4686
lypinator 0:bb348c97df44 4687 htim->State= HAL_TIM_STATE_READY;
lypinator 0:bb348c97df44 4688
lypinator 0:bb348c97df44 4689 HAL_TIM_ErrorCallback(htim);
lypinator 0:bb348c97df44 4690 }
lypinator 0:bb348c97df44 4691
lypinator 0:bb348c97df44 4692 /**
lypinator 0:bb348c97df44 4693 * @brief TIM DMA Capture complete callback.
lypinator 0:bb348c97df44 4694 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 4695 * the configuration information for the specified DMA module.
lypinator 0:bb348c97df44 4696 * @retval None
lypinator 0:bb348c97df44 4697 */
lypinator 0:bb348c97df44 4698 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
lypinator 0:bb348c97df44 4699 {
lypinator 0:bb348c97df44 4700 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
lypinator 0:bb348c97df44 4701
lypinator 0:bb348c97df44 4702 htim->State= HAL_TIM_STATE_READY;
lypinator 0:bb348c97df44 4703
lypinator 0:bb348c97df44 4704 if(hdma == htim->hdma[TIM_DMA_ID_CC1])
lypinator 0:bb348c97df44 4705 {
lypinator 0:bb348c97df44 4706 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
lypinator 0:bb348c97df44 4707 }
lypinator 0:bb348c97df44 4708 else if(hdma == htim->hdma[TIM_DMA_ID_CC2])
lypinator 0:bb348c97df44 4709 {
lypinator 0:bb348c97df44 4710 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
lypinator 0:bb348c97df44 4711 }
lypinator 0:bb348c97df44 4712 else if(hdma == htim->hdma[TIM_DMA_ID_CC3])
lypinator 0:bb348c97df44 4713 {
lypinator 0:bb348c97df44 4714 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
lypinator 0:bb348c97df44 4715 }
lypinator 0:bb348c97df44 4716 else if(hdma == htim->hdma[TIM_DMA_ID_CC4])
lypinator 0:bb348c97df44 4717 {
lypinator 0:bb348c97df44 4718 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
lypinator 0:bb348c97df44 4719 }
lypinator 0:bb348c97df44 4720
lypinator 0:bb348c97df44 4721 HAL_TIM_IC_CaptureCallback(htim);
lypinator 0:bb348c97df44 4722
lypinator 0:bb348c97df44 4723 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
lypinator 0:bb348c97df44 4724 }
lypinator 0:bb348c97df44 4725
lypinator 0:bb348c97df44 4726 /**
lypinator 0:bb348c97df44 4727 * @brief Enables or disables the TIM Capture Compare Channel x.
lypinator 0:bb348c97df44 4728 * @param TIMx to select the TIM peripheral
lypinator 0:bb348c97df44 4729 * @param Channel specifies the TIM Channel
lypinator 0:bb348c97df44 4730 * This parameter can be one of the following values:
lypinator 0:bb348c97df44 4731 * @arg TIM_Channel_1: TIM Channel 1
lypinator 0:bb348c97df44 4732 * @arg TIM_Channel_2: TIM Channel 2
lypinator 0:bb348c97df44 4733 * @arg TIM_Channel_3: TIM Channel 3
lypinator 0:bb348c97df44 4734 * @arg TIM_Channel_4: TIM Channel 4
lypinator 0:bb348c97df44 4735 * @param ChannelState specifies the TIM Channel CCxE bit new state.
lypinator 0:bb348c97df44 4736 * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable.
lypinator 0:bb348c97df44 4737 * @retval None
lypinator 0:bb348c97df44 4738 */
lypinator 0:bb348c97df44 4739 void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState)
lypinator 0:bb348c97df44 4740 {
lypinator 0:bb348c97df44 4741 uint32_t tmp = 0U;
lypinator 0:bb348c97df44 4742
lypinator 0:bb348c97df44 4743 /* Check the parameters */
lypinator 0:bb348c97df44 4744 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
lypinator 0:bb348c97df44 4745 assert_param(IS_TIM_CHANNELS(Channel));
lypinator 0:bb348c97df44 4746
lypinator 0:bb348c97df44 4747 tmp = TIM_CCER_CC1E << Channel;
lypinator 0:bb348c97df44 4748
lypinator 0:bb348c97df44 4749 /* Reset the CCxE Bit */
lypinator 0:bb348c97df44 4750 TIMx->CCER &= ~tmp;
lypinator 0:bb348c97df44 4751
lypinator 0:bb348c97df44 4752 /* Set or reset the CCxE Bit */
lypinator 0:bb348c97df44 4753 TIMx->CCER |= (uint32_t)(ChannelState << Channel);
lypinator 0:bb348c97df44 4754 }
lypinator 0:bb348c97df44 4755
lypinator 0:bb348c97df44 4756 /**
lypinator 0:bb348c97df44 4757 * @brief TIM DMA Period Elapse complete callback.
lypinator 0:bb348c97df44 4758 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 4759 * the configuration information for the specified DMA module.
lypinator 0:bb348c97df44 4760 * @retval None
lypinator 0:bb348c97df44 4761 */
lypinator 0:bb348c97df44 4762 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
lypinator 0:bb348c97df44 4763 {
lypinator 0:bb348c97df44 4764 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
lypinator 0:bb348c97df44 4765
lypinator 0:bb348c97df44 4766 htim->State= HAL_TIM_STATE_READY;
lypinator 0:bb348c97df44 4767
lypinator 0:bb348c97df44 4768 HAL_TIM_PeriodElapsedCallback(htim);
lypinator 0:bb348c97df44 4769 }
lypinator 0:bb348c97df44 4770
lypinator 0:bb348c97df44 4771 /**
lypinator 0:bb348c97df44 4772 * @brief TIM DMA Trigger callback.
lypinator 0:bb348c97df44 4773 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 4774 * the configuration information for the specified DMA module.
lypinator 0:bb348c97df44 4775 * @retval None
lypinator 0:bb348c97df44 4776 */
lypinator 0:bb348c97df44 4777 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
lypinator 0:bb348c97df44 4778 {
lypinator 0:bb348c97df44 4779 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
lypinator 0:bb348c97df44 4780
lypinator 0:bb348c97df44 4781 htim->State= HAL_TIM_STATE_READY;
lypinator 0:bb348c97df44 4782
lypinator 0:bb348c97df44 4783 HAL_TIM_TriggerCallback(htim);
lypinator 0:bb348c97df44 4784 }
lypinator 0:bb348c97df44 4785
lypinator 0:bb348c97df44 4786 /**
lypinator 0:bb348c97df44 4787 * @brief Time Output Compare 1 configuration
lypinator 0:bb348c97df44 4788 * @param TIMx to select the TIM peripheral
lypinator 0:bb348c97df44 4789 * @param OC_Config The output configuration structure
lypinator 0:bb348c97df44 4790 * @retval None
lypinator 0:bb348c97df44 4791 */
lypinator 0:bb348c97df44 4792 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
lypinator 0:bb348c97df44 4793 {
lypinator 0:bb348c97df44 4794 uint32_t tmpccmrx = 0U;
lypinator 0:bb348c97df44 4795 uint32_t tmpccer = 0U;
lypinator 0:bb348c97df44 4796 uint32_t tmpcr2 = 0U;
lypinator 0:bb348c97df44 4797
lypinator 0:bb348c97df44 4798 /* Disable the Channel 1: Reset the CC1E Bit */
lypinator 0:bb348c97df44 4799 TIMx->CCER &= ~TIM_CCER_CC1E;
lypinator 0:bb348c97df44 4800
lypinator 0:bb348c97df44 4801 /* Get the TIMx CCER register value */
lypinator 0:bb348c97df44 4802 tmpccer = TIMx->CCER;
lypinator 0:bb348c97df44 4803 /* Get the TIMx CR2 register value */
lypinator 0:bb348c97df44 4804 tmpcr2 = TIMx->CR2;
lypinator 0:bb348c97df44 4805
lypinator 0:bb348c97df44 4806 /* Get the TIMx CCMR1 register value */
lypinator 0:bb348c97df44 4807 tmpccmrx = TIMx->CCMR1;
lypinator 0:bb348c97df44 4808
lypinator 0:bb348c97df44 4809 /* Reset the Output Compare Mode Bits */
lypinator 0:bb348c97df44 4810 tmpccmrx &= ~TIM_CCMR1_OC1M;
lypinator 0:bb348c97df44 4811 tmpccmrx &= ~TIM_CCMR1_CC1S;
lypinator 0:bb348c97df44 4812 /* Select the Output Compare Mode */
lypinator 0:bb348c97df44 4813 tmpccmrx |= OC_Config->OCMode;
lypinator 0:bb348c97df44 4814
lypinator 0:bb348c97df44 4815 /* Reset the Output Polarity level */
lypinator 0:bb348c97df44 4816 tmpccer &= ~TIM_CCER_CC1P;
lypinator 0:bb348c97df44 4817 /* Set the Output Compare Polarity */
lypinator 0:bb348c97df44 4818 tmpccer |= OC_Config->OCPolarity;
lypinator 0:bb348c97df44 4819
lypinator 0:bb348c97df44 4820
lypinator 0:bb348c97df44 4821 if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
lypinator 0:bb348c97df44 4822 {
lypinator 0:bb348c97df44 4823 /* Reset the Output N Polarity level */
lypinator 0:bb348c97df44 4824 tmpccer &= ~TIM_CCER_CC1NP;
lypinator 0:bb348c97df44 4825 /* Set the Output N Polarity */
lypinator 0:bb348c97df44 4826 tmpccer |= OC_Config->OCNPolarity;
lypinator 0:bb348c97df44 4827 /* Reset the Output N State */
lypinator 0:bb348c97df44 4828 tmpccer &= ~TIM_CCER_CC1NE;
lypinator 0:bb348c97df44 4829
lypinator 0:bb348c97df44 4830 /* Reset the Output Compare and Output Compare N IDLE State */
lypinator 0:bb348c97df44 4831 tmpcr2 &= ~TIM_CR2_OIS1;
lypinator 0:bb348c97df44 4832 tmpcr2 &= ~TIM_CR2_OIS1N;
lypinator 0:bb348c97df44 4833 /* Set the Output Idle state */
lypinator 0:bb348c97df44 4834 tmpcr2 |= OC_Config->OCIdleState;
lypinator 0:bb348c97df44 4835 /* Set the Output N Idle state */
lypinator 0:bb348c97df44 4836 tmpcr2 |= OC_Config->OCNIdleState;
lypinator 0:bb348c97df44 4837 }
lypinator 0:bb348c97df44 4838 /* Write to TIMx CR2 */
lypinator 0:bb348c97df44 4839 TIMx->CR2 = tmpcr2;
lypinator 0:bb348c97df44 4840
lypinator 0:bb348c97df44 4841 /* Write to TIMx CCMR1 */
lypinator 0:bb348c97df44 4842 TIMx->CCMR1 = tmpccmrx;
lypinator 0:bb348c97df44 4843
lypinator 0:bb348c97df44 4844 /* Set the Capture Compare Register value */
lypinator 0:bb348c97df44 4845 TIMx->CCR1 = OC_Config->Pulse;
lypinator 0:bb348c97df44 4846
lypinator 0:bb348c97df44 4847 /* Write to TIMx CCER */
lypinator 0:bb348c97df44 4848 TIMx->CCER = tmpccer;
lypinator 0:bb348c97df44 4849 }
lypinator 0:bb348c97df44 4850
lypinator 0:bb348c97df44 4851 /**
lypinator 0:bb348c97df44 4852 * @brief Time Output Compare 3 configuration
lypinator 0:bb348c97df44 4853 * @param TIMx to select the TIM peripheral
lypinator 0:bb348c97df44 4854 * @param OC_Config The output configuration structure
lypinator 0:bb348c97df44 4855 * @retval None
lypinator 0:bb348c97df44 4856 */
lypinator 0:bb348c97df44 4857 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
lypinator 0:bb348c97df44 4858 {
lypinator 0:bb348c97df44 4859 uint32_t tmpccmrx = 0U;
lypinator 0:bb348c97df44 4860 uint32_t tmpccer = 0U;
lypinator 0:bb348c97df44 4861 uint32_t tmpcr2 = 0U;
lypinator 0:bb348c97df44 4862
lypinator 0:bb348c97df44 4863 /* Disable the Channel 3: Reset the CC2E Bit */
lypinator 0:bb348c97df44 4864 TIMx->CCER &= ~TIM_CCER_CC3E;
lypinator 0:bb348c97df44 4865
lypinator 0:bb348c97df44 4866 /* Get the TIMx CCER register value */
lypinator 0:bb348c97df44 4867 tmpccer = TIMx->CCER;
lypinator 0:bb348c97df44 4868 /* Get the TIMx CR2 register value */
lypinator 0:bb348c97df44 4869 tmpcr2 = TIMx->CR2;
lypinator 0:bb348c97df44 4870
lypinator 0:bb348c97df44 4871 /* Get the TIMx CCMR2 register value */
lypinator 0:bb348c97df44 4872 tmpccmrx = TIMx->CCMR2;
lypinator 0:bb348c97df44 4873
lypinator 0:bb348c97df44 4874 /* Reset the Output Compare mode and Capture/Compare selection Bits */
lypinator 0:bb348c97df44 4875 tmpccmrx &= ~TIM_CCMR2_OC3M;
lypinator 0:bb348c97df44 4876 tmpccmrx &= ~TIM_CCMR2_CC3S;
lypinator 0:bb348c97df44 4877 /* Select the Output Compare Mode */
lypinator 0:bb348c97df44 4878 tmpccmrx |= OC_Config->OCMode;
lypinator 0:bb348c97df44 4879
lypinator 0:bb348c97df44 4880 /* Reset the Output Polarity level */
lypinator 0:bb348c97df44 4881 tmpccer &= ~TIM_CCER_CC3P;
lypinator 0:bb348c97df44 4882 /* Set the Output Compare Polarity */
lypinator 0:bb348c97df44 4883 tmpccer |= (OC_Config->OCPolarity << 8U);
lypinator 0:bb348c97df44 4884
lypinator 0:bb348c97df44 4885 if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
lypinator 0:bb348c97df44 4886 {
lypinator 0:bb348c97df44 4887 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
lypinator 0:bb348c97df44 4888 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
lypinator 0:bb348c97df44 4889 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
lypinator 0:bb348c97df44 4890
lypinator 0:bb348c97df44 4891 /* Reset the Output N Polarity level */
lypinator 0:bb348c97df44 4892 tmpccer &= ~TIM_CCER_CC3NP;
lypinator 0:bb348c97df44 4893 /* Set the Output N Polarity */
lypinator 0:bb348c97df44 4894 tmpccer |= (OC_Config->OCNPolarity << 8U);
lypinator 0:bb348c97df44 4895 /* Reset the Output N State */
lypinator 0:bb348c97df44 4896 tmpccer &= ~TIM_CCER_CC3NE;
lypinator 0:bb348c97df44 4897
lypinator 0:bb348c97df44 4898 /* Reset the Output Compare and Output Compare N IDLE State */
lypinator 0:bb348c97df44 4899 tmpcr2 &= ~TIM_CR2_OIS3;
lypinator 0:bb348c97df44 4900 tmpcr2 &= ~TIM_CR2_OIS3N;
lypinator 0:bb348c97df44 4901 /* Set the Output Idle state */
lypinator 0:bb348c97df44 4902 tmpcr2 |= (OC_Config->OCIdleState << 4U);
lypinator 0:bb348c97df44 4903 /* Set the Output N Idle state */
lypinator 0:bb348c97df44 4904 tmpcr2 |= (OC_Config->OCNIdleState << 4U);
lypinator 0:bb348c97df44 4905 }
lypinator 0:bb348c97df44 4906 /* Write to TIMx CR2 */
lypinator 0:bb348c97df44 4907 TIMx->CR2 = tmpcr2;
lypinator 0:bb348c97df44 4908
lypinator 0:bb348c97df44 4909 /* Write to TIMx CCMR2 */
lypinator 0:bb348c97df44 4910 TIMx->CCMR2 = tmpccmrx;
lypinator 0:bb348c97df44 4911
lypinator 0:bb348c97df44 4912 /* Set the Capture Compare Register value */
lypinator 0:bb348c97df44 4913 TIMx->CCR3 = OC_Config->Pulse;
lypinator 0:bb348c97df44 4914
lypinator 0:bb348c97df44 4915 /* Write to TIMx CCER */
lypinator 0:bb348c97df44 4916 TIMx->CCER = tmpccer;
lypinator 0:bb348c97df44 4917 }
lypinator 0:bb348c97df44 4918
lypinator 0:bb348c97df44 4919 /**
lypinator 0:bb348c97df44 4920 * @brief Time Output Compare 4 configuration
lypinator 0:bb348c97df44 4921 * @param TIMx to select the TIM peripheral
lypinator 0:bb348c97df44 4922 * @param OC_Config The output configuration structure
lypinator 0:bb348c97df44 4923 * @retval None
lypinator 0:bb348c97df44 4924 */
lypinator 0:bb348c97df44 4925 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
lypinator 0:bb348c97df44 4926 {
lypinator 0:bb348c97df44 4927 uint32_t tmpccmrx = 0U;
lypinator 0:bb348c97df44 4928 uint32_t tmpccer = 0U;
lypinator 0:bb348c97df44 4929 uint32_t tmpcr2 = 0U;
lypinator 0:bb348c97df44 4930
lypinator 0:bb348c97df44 4931 /* Disable the Channel 4: Reset the CC4E Bit */
lypinator 0:bb348c97df44 4932 TIMx->CCER &= ~TIM_CCER_CC4E;
lypinator 0:bb348c97df44 4933
lypinator 0:bb348c97df44 4934 /* Get the TIMx CCER register value */
lypinator 0:bb348c97df44 4935 tmpccer = TIMx->CCER;
lypinator 0:bb348c97df44 4936 /* Get the TIMx CR2 register value */
lypinator 0:bb348c97df44 4937 tmpcr2 = TIMx->CR2;
lypinator 0:bb348c97df44 4938
lypinator 0:bb348c97df44 4939 /* Get the TIMx CCMR2 register value */
lypinator 0:bb348c97df44 4940 tmpccmrx = TIMx->CCMR2;
lypinator 0:bb348c97df44 4941
lypinator 0:bb348c97df44 4942 /* Reset the Output Compare mode and Capture/Compare selection Bits */
lypinator 0:bb348c97df44 4943 tmpccmrx &= ~TIM_CCMR2_OC4M;
lypinator 0:bb348c97df44 4944 tmpccmrx &= ~TIM_CCMR2_CC4S;
lypinator 0:bb348c97df44 4945
lypinator 0:bb348c97df44 4946 /* Select the Output Compare Mode */
lypinator 0:bb348c97df44 4947 tmpccmrx |= (OC_Config->OCMode << 8U);
lypinator 0:bb348c97df44 4948
lypinator 0:bb348c97df44 4949 /* Reset the Output Polarity level */
lypinator 0:bb348c97df44 4950 tmpccer &= ~TIM_CCER_CC4P;
lypinator 0:bb348c97df44 4951 /* Set the Output Compare Polarity */
lypinator 0:bb348c97df44 4952 tmpccer |= (OC_Config->OCPolarity << 12U);
lypinator 0:bb348c97df44 4953
lypinator 0:bb348c97df44 4954 /*if((TIMx == TIM1) || (TIMx == TIM8))*/
lypinator 0:bb348c97df44 4955 if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
lypinator 0:bb348c97df44 4956 {
lypinator 0:bb348c97df44 4957 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
lypinator 0:bb348c97df44 4958 /* Reset the Output Compare IDLE State */
lypinator 0:bb348c97df44 4959 tmpcr2 &= ~TIM_CR2_OIS4;
lypinator 0:bb348c97df44 4960 /* Set the Output Idle state */
lypinator 0:bb348c97df44 4961 tmpcr2 |= (OC_Config->OCIdleState << 6U);
lypinator 0:bb348c97df44 4962 }
lypinator 0:bb348c97df44 4963 /* Write to TIMx CR2 */
lypinator 0:bb348c97df44 4964 TIMx->CR2 = tmpcr2;
lypinator 0:bb348c97df44 4965
lypinator 0:bb348c97df44 4966 /* Write to TIMx CCMR2 */
lypinator 0:bb348c97df44 4967 TIMx->CCMR2 = tmpccmrx;
lypinator 0:bb348c97df44 4968
lypinator 0:bb348c97df44 4969 /* Set the Capture Compare Register value */
lypinator 0:bb348c97df44 4970 TIMx->CCR4 = OC_Config->Pulse;
lypinator 0:bb348c97df44 4971
lypinator 0:bb348c97df44 4972 /* Write to TIMx CCER */
lypinator 0:bb348c97df44 4973 TIMx->CCER = tmpccer;
lypinator 0:bb348c97df44 4974 }
lypinator 0:bb348c97df44 4975
lypinator 0:bb348c97df44 4976 /**
lypinator 0:bb348c97df44 4977 * @brief Time Output Compare 4 configuration
lypinator 0:bb348c97df44 4978 * @param htim pointer to a TIM_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 4979 * the configuration information for TIM module.
lypinator 0:bb348c97df44 4980 * @param sSlaveConfig The slave configuration structure
lypinator 0:bb348c97df44 4981 * @retval None
lypinator 0:bb348c97df44 4982 */
lypinator 0:bb348c97df44 4983 static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
lypinator 0:bb348c97df44 4984 TIM_SlaveConfigTypeDef * sSlaveConfig)
lypinator 0:bb348c97df44 4985 {
lypinator 0:bb348c97df44 4986 uint32_t tmpsmcr = 0U;
lypinator 0:bb348c97df44 4987 uint32_t tmpccmr1 = 0U;
lypinator 0:bb348c97df44 4988 uint32_t tmpccer = 0U;
lypinator 0:bb348c97df44 4989
lypinator 0:bb348c97df44 4990 /* Get the TIMx SMCR register value */
lypinator 0:bb348c97df44 4991 tmpsmcr = htim->Instance->SMCR;
lypinator 0:bb348c97df44 4992
lypinator 0:bb348c97df44 4993 /* Reset the Trigger Selection Bits */
lypinator 0:bb348c97df44 4994 tmpsmcr &= ~TIM_SMCR_TS;
lypinator 0:bb348c97df44 4995 /* Set the Input Trigger source */
lypinator 0:bb348c97df44 4996 tmpsmcr |= sSlaveConfig->InputTrigger;
lypinator 0:bb348c97df44 4997
lypinator 0:bb348c97df44 4998 /* Reset the slave mode Bits */
lypinator 0:bb348c97df44 4999 tmpsmcr &= ~TIM_SMCR_SMS;
lypinator 0:bb348c97df44 5000 /* Set the slave mode */
lypinator 0:bb348c97df44 5001 tmpsmcr |= sSlaveConfig->SlaveMode;
lypinator 0:bb348c97df44 5002
lypinator 0:bb348c97df44 5003 /* Write to TIMx SMCR */
lypinator 0:bb348c97df44 5004 htim->Instance->SMCR = tmpsmcr;
lypinator 0:bb348c97df44 5005
lypinator 0:bb348c97df44 5006 /* Configure the trigger prescaler, filter, and polarity */
lypinator 0:bb348c97df44 5007 switch (sSlaveConfig->InputTrigger)
lypinator 0:bb348c97df44 5008 {
lypinator 0:bb348c97df44 5009 case TIM_TS_ETRF:
lypinator 0:bb348c97df44 5010 {
lypinator 0:bb348c97df44 5011 /* Check the parameters */
lypinator 0:bb348c97df44 5012 assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
lypinator 0:bb348c97df44 5013 assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
lypinator 0:bb348c97df44 5014 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
lypinator 0:bb348c97df44 5015 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
lypinator 0:bb348c97df44 5016 /* Configure the ETR Trigger source */
lypinator 0:bb348c97df44 5017 TIM_ETR_SetConfig(htim->Instance,
lypinator 0:bb348c97df44 5018 sSlaveConfig->TriggerPrescaler,
lypinator 0:bb348c97df44 5019 sSlaveConfig->TriggerPolarity,
lypinator 0:bb348c97df44 5020 sSlaveConfig->TriggerFilter);
lypinator 0:bb348c97df44 5021 }
lypinator 0:bb348c97df44 5022 break;
lypinator 0:bb348c97df44 5023
lypinator 0:bb348c97df44 5024 case TIM_TS_TI1F_ED:
lypinator 0:bb348c97df44 5025 {
lypinator 0:bb348c97df44 5026 /* Check the parameters */
lypinator 0:bb348c97df44 5027 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
lypinator 0:bb348c97df44 5028 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
lypinator 0:bb348c97df44 5029
lypinator 0:bb348c97df44 5030 /* Disable the Channel 1: Reset the CC1E Bit */
lypinator 0:bb348c97df44 5031 tmpccer = htim->Instance->CCER;
lypinator 0:bb348c97df44 5032 htim->Instance->CCER &= ~TIM_CCER_CC1E;
lypinator 0:bb348c97df44 5033 tmpccmr1 = htim->Instance->CCMR1;
lypinator 0:bb348c97df44 5034
lypinator 0:bb348c97df44 5035 /* Set the filter */
lypinator 0:bb348c97df44 5036 tmpccmr1 &= ~TIM_CCMR1_IC1F;
lypinator 0:bb348c97df44 5037 tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U);
lypinator 0:bb348c97df44 5038
lypinator 0:bb348c97df44 5039 /* Write to TIMx CCMR1 and CCER registers */
lypinator 0:bb348c97df44 5040 htim->Instance->CCMR1 = tmpccmr1;
lypinator 0:bb348c97df44 5041 htim->Instance->CCER = tmpccer;
lypinator 0:bb348c97df44 5042
lypinator 0:bb348c97df44 5043 }
lypinator 0:bb348c97df44 5044 break;
lypinator 0:bb348c97df44 5045
lypinator 0:bb348c97df44 5046 case TIM_TS_TI1FP1:
lypinator 0:bb348c97df44 5047 {
lypinator 0:bb348c97df44 5048 /* Check the parameters */
lypinator 0:bb348c97df44 5049 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
lypinator 0:bb348c97df44 5050 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
lypinator 0:bb348c97df44 5051 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
lypinator 0:bb348c97df44 5052
lypinator 0:bb348c97df44 5053 /* Configure TI1 Filter and Polarity */
lypinator 0:bb348c97df44 5054 TIM_TI1_ConfigInputStage(htim->Instance,
lypinator 0:bb348c97df44 5055 sSlaveConfig->TriggerPolarity,
lypinator 0:bb348c97df44 5056 sSlaveConfig->TriggerFilter);
lypinator 0:bb348c97df44 5057 }
lypinator 0:bb348c97df44 5058 break;
lypinator 0:bb348c97df44 5059
lypinator 0:bb348c97df44 5060 case TIM_TS_TI2FP2:
lypinator 0:bb348c97df44 5061 {
lypinator 0:bb348c97df44 5062 /* Check the parameters */
lypinator 0:bb348c97df44 5063 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
lypinator 0:bb348c97df44 5064 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
lypinator 0:bb348c97df44 5065 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
lypinator 0:bb348c97df44 5066
lypinator 0:bb348c97df44 5067 /* Configure TI2 Filter and Polarity */
lypinator 0:bb348c97df44 5068 TIM_TI2_ConfigInputStage(htim->Instance,
lypinator 0:bb348c97df44 5069 sSlaveConfig->TriggerPolarity,
lypinator 0:bb348c97df44 5070 sSlaveConfig->TriggerFilter);
lypinator 0:bb348c97df44 5071 }
lypinator 0:bb348c97df44 5072 break;
lypinator 0:bb348c97df44 5073
lypinator 0:bb348c97df44 5074 case TIM_TS_ITR0:
lypinator 0:bb348c97df44 5075 {
lypinator 0:bb348c97df44 5076 /* Check the parameter */
lypinator 0:bb348c97df44 5077 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
lypinator 0:bb348c97df44 5078 }
lypinator 0:bb348c97df44 5079 break;
lypinator 0:bb348c97df44 5080
lypinator 0:bb348c97df44 5081 case TIM_TS_ITR1:
lypinator 0:bb348c97df44 5082 {
lypinator 0:bb348c97df44 5083 /* Check the parameter */
lypinator 0:bb348c97df44 5084 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
lypinator 0:bb348c97df44 5085 }
lypinator 0:bb348c97df44 5086 break;
lypinator 0:bb348c97df44 5087
lypinator 0:bb348c97df44 5088 case TIM_TS_ITR2:
lypinator 0:bb348c97df44 5089 {
lypinator 0:bb348c97df44 5090 /* Check the parameter */
lypinator 0:bb348c97df44 5091 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
lypinator 0:bb348c97df44 5092 }
lypinator 0:bb348c97df44 5093 break;
lypinator 0:bb348c97df44 5094
lypinator 0:bb348c97df44 5095 case TIM_TS_ITR3:
lypinator 0:bb348c97df44 5096 {
lypinator 0:bb348c97df44 5097 /* Check the parameter */
lypinator 0:bb348c97df44 5098 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
lypinator 0:bb348c97df44 5099 }
lypinator 0:bb348c97df44 5100 break;
lypinator 0:bb348c97df44 5101
lypinator 0:bb348c97df44 5102 default:
lypinator 0:bb348c97df44 5103 break;
lypinator 0:bb348c97df44 5104 }
lypinator 0:bb348c97df44 5105 }
lypinator 0:bb348c97df44 5106
lypinator 0:bb348c97df44 5107
lypinator 0:bb348c97df44 5108 /**
lypinator 0:bb348c97df44 5109 * @brief Configure the Polarity and Filter for TI1.
lypinator 0:bb348c97df44 5110 * @param TIMx to select the TIM peripheral.
lypinator 0:bb348c97df44 5111 * @param TIM_ICPolarity The Input Polarity.
lypinator 0:bb348c97df44 5112 * This parameter can be one of the following values:
lypinator 0:bb348c97df44 5113 * @arg TIM_ICPolarity_Rising
lypinator 0:bb348c97df44 5114 * @arg TIM_ICPolarity_Falling
lypinator 0:bb348c97df44 5115 * @arg TIM_ICPolarity_BothEdge
lypinator 0:bb348c97df44 5116 * @param TIM_ICFilter Specifies the Input Capture Filter.
lypinator 0:bb348c97df44 5117 * This parameter must be a value between 0x00 and 0x0F.
lypinator 0:bb348c97df44 5118 * @retval None
lypinator 0:bb348c97df44 5119 */
lypinator 0:bb348c97df44 5120 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
lypinator 0:bb348c97df44 5121 {
lypinator 0:bb348c97df44 5122 uint32_t tmpccmr1 = 0U;
lypinator 0:bb348c97df44 5123 uint32_t tmpccer = 0U;
lypinator 0:bb348c97df44 5124
lypinator 0:bb348c97df44 5125 /* Disable the Channel 1: Reset the CC1E Bit */
lypinator 0:bb348c97df44 5126 tmpccer = TIMx->CCER;
lypinator 0:bb348c97df44 5127 TIMx->CCER &= ~TIM_CCER_CC1E;
lypinator 0:bb348c97df44 5128 tmpccmr1 = TIMx->CCMR1;
lypinator 0:bb348c97df44 5129
lypinator 0:bb348c97df44 5130 /* Set the filter */
lypinator 0:bb348c97df44 5131 tmpccmr1 &= ~TIM_CCMR1_IC1F;
lypinator 0:bb348c97df44 5132 tmpccmr1 |= (TIM_ICFilter << 4U);
lypinator 0:bb348c97df44 5133
lypinator 0:bb348c97df44 5134 /* Select the Polarity and set the CC1E Bit */
lypinator 0:bb348c97df44 5135 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
lypinator 0:bb348c97df44 5136 tmpccer |= TIM_ICPolarity;
lypinator 0:bb348c97df44 5137
lypinator 0:bb348c97df44 5138 /* Write to TIMx CCMR1 and CCER registers */
lypinator 0:bb348c97df44 5139 TIMx->CCMR1 = tmpccmr1;
lypinator 0:bb348c97df44 5140 TIMx->CCER = tmpccer;
lypinator 0:bb348c97df44 5141 }
lypinator 0:bb348c97df44 5142
lypinator 0:bb348c97df44 5143 /**
lypinator 0:bb348c97df44 5144 * @brief Configure the TI2 as Input.
lypinator 0:bb348c97df44 5145 * @param TIMx to select the TIM peripheral
lypinator 0:bb348c97df44 5146 * @param TIM_ICPolarity The Input Polarity.
lypinator 0:bb348c97df44 5147 * This parameter can be one of the following values:
lypinator 0:bb348c97df44 5148 * @arg TIM_ICPolarity_Rising
lypinator 0:bb348c97df44 5149 * @arg TIM_ICPolarity_Falling
lypinator 0:bb348c97df44 5150 * @arg TIM_ICPolarity_BothEdge
lypinator 0:bb348c97df44 5151 * @param TIM_ICSelection specifies the input to be used.
lypinator 0:bb348c97df44 5152 * This parameter can be one of the following values:
lypinator 0:bb348c97df44 5153 * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.
lypinator 0:bb348c97df44 5154 * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.
lypinator 0:bb348c97df44 5155 * @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.
lypinator 0:bb348c97df44 5156 * @param TIM_ICFilter Specifies the Input Capture Filter.
lypinator 0:bb348c97df44 5157 * This parameter must be a value between 0x00 and 0x0F.
lypinator 0:bb348c97df44 5158 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
lypinator 0:bb348c97df44 5159 * (on channel1 path) is used as the input signal. Therefore CCMR1 must be
lypinator 0:bb348c97df44 5160 * protected against un-initialized filter and polarity values.
lypinator 0:bb348c97df44 5161 * @retval None
lypinator 0:bb348c97df44 5162 */
lypinator 0:bb348c97df44 5163 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
lypinator 0:bb348c97df44 5164 uint32_t TIM_ICFilter)
lypinator 0:bb348c97df44 5165 {
lypinator 0:bb348c97df44 5166 uint32_t tmpccmr1 = 0U;
lypinator 0:bb348c97df44 5167 uint32_t tmpccer = 0U;
lypinator 0:bb348c97df44 5168
lypinator 0:bb348c97df44 5169 /* Disable the Channel 2: Reset the CC2E Bit */
lypinator 0:bb348c97df44 5170 TIMx->CCER &= ~TIM_CCER_CC2E;
lypinator 0:bb348c97df44 5171 tmpccmr1 = TIMx->CCMR1;
lypinator 0:bb348c97df44 5172 tmpccer = TIMx->CCER;
lypinator 0:bb348c97df44 5173
lypinator 0:bb348c97df44 5174 /* Select the Input */
lypinator 0:bb348c97df44 5175 tmpccmr1 &= ~TIM_CCMR1_CC2S;
lypinator 0:bb348c97df44 5176 tmpccmr1 |= (TIM_ICSelection << 8U);
lypinator 0:bb348c97df44 5177
lypinator 0:bb348c97df44 5178 /* Set the filter */
lypinator 0:bb348c97df44 5179 tmpccmr1 &= ~TIM_CCMR1_IC2F;
lypinator 0:bb348c97df44 5180 tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F);
lypinator 0:bb348c97df44 5181
lypinator 0:bb348c97df44 5182 /* Select the Polarity and set the CC2E Bit */
lypinator 0:bb348c97df44 5183 tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
lypinator 0:bb348c97df44 5184 tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));
lypinator 0:bb348c97df44 5185
lypinator 0:bb348c97df44 5186 /* Write to TIMx CCMR1 and CCER registers */
lypinator 0:bb348c97df44 5187 TIMx->CCMR1 = tmpccmr1 ;
lypinator 0:bb348c97df44 5188 TIMx->CCER = tmpccer;
lypinator 0:bb348c97df44 5189 }
lypinator 0:bb348c97df44 5190
lypinator 0:bb348c97df44 5191 /**
lypinator 0:bb348c97df44 5192 * @brief Configure the Polarity and Filter for TI2.
lypinator 0:bb348c97df44 5193 * @param TIMx to select the TIM peripheral.
lypinator 0:bb348c97df44 5194 * @param TIM_ICPolarity The Input Polarity.
lypinator 0:bb348c97df44 5195 * This parameter can be one of the following values:
lypinator 0:bb348c97df44 5196 * @arg TIM_ICPolarity_Rising
lypinator 0:bb348c97df44 5197 * @arg TIM_ICPolarity_Falling
lypinator 0:bb348c97df44 5198 * @arg TIM_ICPolarity_BothEdge
lypinator 0:bb348c97df44 5199 * @param TIM_ICFilter Specifies the Input Capture Filter.
lypinator 0:bb348c97df44 5200 * This parameter must be a value between 0x00 and 0x0F.
lypinator 0:bb348c97df44 5201 * @retval None
lypinator 0:bb348c97df44 5202 */
lypinator 0:bb348c97df44 5203 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
lypinator 0:bb348c97df44 5204 {
lypinator 0:bb348c97df44 5205 uint32_t tmpccmr1 = 0U;
lypinator 0:bb348c97df44 5206 uint32_t tmpccer = 0U;
lypinator 0:bb348c97df44 5207
lypinator 0:bb348c97df44 5208 /* Disable the Channel 2: Reset the CC2E Bit */
lypinator 0:bb348c97df44 5209 TIMx->CCER &= ~TIM_CCER_CC2E;
lypinator 0:bb348c97df44 5210 tmpccmr1 = TIMx->CCMR1;
lypinator 0:bb348c97df44 5211 tmpccer = TIMx->CCER;
lypinator 0:bb348c97df44 5212
lypinator 0:bb348c97df44 5213 /* Set the filter */
lypinator 0:bb348c97df44 5214 tmpccmr1 &= ~TIM_CCMR1_IC2F;
lypinator 0:bb348c97df44 5215 tmpccmr1 |= (TIM_ICFilter << 12U);
lypinator 0:bb348c97df44 5216
lypinator 0:bb348c97df44 5217 /* Select the Polarity and set the CC2E Bit */
lypinator 0:bb348c97df44 5218 tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
lypinator 0:bb348c97df44 5219 tmpccer |= (TIM_ICPolarity << 4U);
lypinator 0:bb348c97df44 5220
lypinator 0:bb348c97df44 5221 /* Write to TIMx CCMR1 and CCER registers */
lypinator 0:bb348c97df44 5222 TIMx->CCMR1 = tmpccmr1 ;
lypinator 0:bb348c97df44 5223 TIMx->CCER = tmpccer;
lypinator 0:bb348c97df44 5224 }
lypinator 0:bb348c97df44 5225
lypinator 0:bb348c97df44 5226 /**
lypinator 0:bb348c97df44 5227 * @brief Configure the TI3 as Input.
lypinator 0:bb348c97df44 5228 * @param TIMx to select the TIM peripheral
lypinator 0:bb348c97df44 5229 * @param TIM_ICPolarity The Input Polarity.
lypinator 0:bb348c97df44 5230 * This parameter can be one of the following values:
lypinator 0:bb348c97df44 5231 * @arg TIM_ICPolarity_Rising
lypinator 0:bb348c97df44 5232 * @arg TIM_ICPolarity_Falling
lypinator 0:bb348c97df44 5233 * @arg TIM_ICPolarity_BothEdge
lypinator 0:bb348c97df44 5234 * @param TIM_ICSelection specifies the input to be used.
lypinator 0:bb348c97df44 5235 * This parameter can be one of the following values:
lypinator 0:bb348c97df44 5236 * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.
lypinator 0:bb348c97df44 5237 * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.
lypinator 0:bb348c97df44 5238 * @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.
lypinator 0:bb348c97df44 5239 * @param TIM_ICFilter Specifies the Input Capture Filter.
lypinator 0:bb348c97df44 5240 * This parameter must be a value between 0x00 and 0x0F.
lypinator 0:bb348c97df44 5241 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
lypinator 0:bb348c97df44 5242 * (on channel4 path) is used as the input signal. Therefore CCMR2 must be
lypinator 0:bb348c97df44 5243 * protected against un-initialized filter and polarity values.
lypinator 0:bb348c97df44 5244 * @retval None
lypinator 0:bb348c97df44 5245 */
lypinator 0:bb348c97df44 5246 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
lypinator 0:bb348c97df44 5247 uint32_t TIM_ICFilter)
lypinator 0:bb348c97df44 5248 {
lypinator 0:bb348c97df44 5249 uint32_t tmpccmr2 = 0U;
lypinator 0:bb348c97df44 5250 uint32_t tmpccer = 0U;
lypinator 0:bb348c97df44 5251
lypinator 0:bb348c97df44 5252 /* Disable the Channel 3: Reset the CC3E Bit */
lypinator 0:bb348c97df44 5253 TIMx->CCER &= ~TIM_CCER_CC3E;
lypinator 0:bb348c97df44 5254 tmpccmr2 = TIMx->CCMR2;
lypinator 0:bb348c97df44 5255 tmpccer = TIMx->CCER;
lypinator 0:bb348c97df44 5256
lypinator 0:bb348c97df44 5257 /* Select the Input */
lypinator 0:bb348c97df44 5258 tmpccmr2 &= ~TIM_CCMR2_CC3S;
lypinator 0:bb348c97df44 5259 tmpccmr2 |= TIM_ICSelection;
lypinator 0:bb348c97df44 5260
lypinator 0:bb348c97df44 5261 /* Set the filter */
lypinator 0:bb348c97df44 5262 tmpccmr2 &= ~TIM_CCMR2_IC3F;
lypinator 0:bb348c97df44 5263 tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F);
lypinator 0:bb348c97df44 5264
lypinator 0:bb348c97df44 5265 /* Select the Polarity and set the CC3E Bit */
lypinator 0:bb348c97df44 5266 tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
lypinator 0:bb348c97df44 5267 tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));
lypinator 0:bb348c97df44 5268
lypinator 0:bb348c97df44 5269 /* Write to TIMx CCMR2 and CCER registers */
lypinator 0:bb348c97df44 5270 TIMx->CCMR2 = tmpccmr2;
lypinator 0:bb348c97df44 5271 TIMx->CCER = tmpccer;
lypinator 0:bb348c97df44 5272 }
lypinator 0:bb348c97df44 5273
lypinator 0:bb348c97df44 5274 /**
lypinator 0:bb348c97df44 5275 * @brief Configure the TI4 as Input.
lypinator 0:bb348c97df44 5276 * @param TIMx to select the TIM peripheral
lypinator 0:bb348c97df44 5277 * @param TIM_ICPolarity The Input Polarity.
lypinator 0:bb348c97df44 5278 * This parameter can be one of the following values:
lypinator 0:bb348c97df44 5279 * @arg TIM_ICPolarity_Rising
lypinator 0:bb348c97df44 5280 * @arg TIM_ICPolarity_Falling
lypinator 0:bb348c97df44 5281 * @arg TIM_ICPolarity_BothEdge
lypinator 0:bb348c97df44 5282 * @param TIM_ICSelection specifies the input to be used.
lypinator 0:bb348c97df44 5283 * This parameter can be one of the following values:
lypinator 0:bb348c97df44 5284 * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.
lypinator 0:bb348c97df44 5285 * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.
lypinator 0:bb348c97df44 5286 * @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.
lypinator 0:bb348c97df44 5287 * @param TIM_ICFilter Specifies the Input Capture Filter.
lypinator 0:bb348c97df44 5288 * This parameter must be a value between 0x00 and 0x0F.
lypinator 0:bb348c97df44 5289 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
lypinator 0:bb348c97df44 5290 * (on channel3 path) is used as the input signal. Therefore CCMR2 must be
lypinator 0:bb348c97df44 5291 * protected against un-initialized filter and polarity values.
lypinator 0:bb348c97df44 5292 * @retval None
lypinator 0:bb348c97df44 5293 */
lypinator 0:bb348c97df44 5294 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
lypinator 0:bb348c97df44 5295 uint32_t TIM_ICFilter)
lypinator 0:bb348c97df44 5296 {
lypinator 0:bb348c97df44 5297 uint32_t tmpccmr2 = 0U;
lypinator 0:bb348c97df44 5298 uint32_t tmpccer = 0U;
lypinator 0:bb348c97df44 5299
lypinator 0:bb348c97df44 5300 /* Disable the Channel 4: Reset the CC4E Bit */
lypinator 0:bb348c97df44 5301 TIMx->CCER &= ~TIM_CCER_CC4E;
lypinator 0:bb348c97df44 5302 tmpccmr2 = TIMx->CCMR2;
lypinator 0:bb348c97df44 5303 tmpccer = TIMx->CCER;
lypinator 0:bb348c97df44 5304
lypinator 0:bb348c97df44 5305 /* Select the Input */
lypinator 0:bb348c97df44 5306 tmpccmr2 &= ~TIM_CCMR2_CC4S;
lypinator 0:bb348c97df44 5307 tmpccmr2 |= (TIM_ICSelection << 8U);
lypinator 0:bb348c97df44 5308
lypinator 0:bb348c97df44 5309 /* Set the filter */
lypinator 0:bb348c97df44 5310 tmpccmr2 &= ~TIM_CCMR2_IC4F;
lypinator 0:bb348c97df44 5311 tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F);
lypinator 0:bb348c97df44 5312
lypinator 0:bb348c97df44 5313 /* Select the Polarity and set the CC4E Bit */
lypinator 0:bb348c97df44 5314 tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
lypinator 0:bb348c97df44 5315 tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));
lypinator 0:bb348c97df44 5316
lypinator 0:bb348c97df44 5317 /* Write to TIMx CCMR2 and CCER registers */
lypinator 0:bb348c97df44 5318 TIMx->CCMR2 = tmpccmr2;
lypinator 0:bb348c97df44 5319 TIMx->CCER = tmpccer ;
lypinator 0:bb348c97df44 5320 }
lypinator 0:bb348c97df44 5321
lypinator 0:bb348c97df44 5322 /**
lypinator 0:bb348c97df44 5323 * @brief Selects the Input Trigger source
lypinator 0:bb348c97df44 5324 * @param TIMx to select the TIM peripheral
lypinator 0:bb348c97df44 5325 * @param TIM_ITRx The Input Trigger source.
lypinator 0:bb348c97df44 5326 * This parameter can be one of the following values:
lypinator 0:bb348c97df44 5327 * @arg TIM_TS_ITR0: Internal Trigger 0
lypinator 0:bb348c97df44 5328 * @arg TIM_TS_ITR1: Internal Trigger 1
lypinator 0:bb348c97df44 5329 * @arg TIM_TS_ITR2: Internal Trigger 2
lypinator 0:bb348c97df44 5330 * @arg TIM_TS_ITR3: Internal Trigger 3
lypinator 0:bb348c97df44 5331 * @arg TIM_TS_TI1F_ED: TI1 Edge Detector
lypinator 0:bb348c97df44 5332 * @arg TIM_TS_TI1FP1: Filtered Timer Input 1
lypinator 0:bb348c97df44 5333 * @arg TIM_TS_TI2FP2: Filtered Timer Input 2
lypinator 0:bb348c97df44 5334 * @arg TIM_TS_ETRF: External Trigger input
lypinator 0:bb348c97df44 5335 * @retval None
lypinator 0:bb348c97df44 5336 */
lypinator 0:bb348c97df44 5337 static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t TIM_ITRx)
lypinator 0:bb348c97df44 5338 {
lypinator 0:bb348c97df44 5339 uint32_t tmpsmcr = 0U;
lypinator 0:bb348c97df44 5340
lypinator 0:bb348c97df44 5341 /* Get the TIMx SMCR register value */
lypinator 0:bb348c97df44 5342 tmpsmcr = TIMx->SMCR;
lypinator 0:bb348c97df44 5343 /* Reset the TS Bits */
lypinator 0:bb348c97df44 5344 tmpsmcr &= ~TIM_SMCR_TS;
lypinator 0:bb348c97df44 5345 /* Set the Input Trigger source and the slave mode*/
lypinator 0:bb348c97df44 5346 tmpsmcr |= TIM_ITRx | TIM_SLAVEMODE_EXTERNAL1;
lypinator 0:bb348c97df44 5347 /* Write to TIMx SMCR */
lypinator 0:bb348c97df44 5348 TIMx->SMCR = tmpsmcr;
lypinator 0:bb348c97df44 5349 }
lypinator 0:bb348c97df44 5350
lypinator 0:bb348c97df44 5351 /**
lypinator 0:bb348c97df44 5352 * @brief Configures the TIMx External Trigger (ETR).
lypinator 0:bb348c97df44 5353 * @param TIMx to select the TIM peripheral
lypinator 0:bb348c97df44 5354 * @param TIM_ExtTRGPrescaler The external Trigger Prescaler.
lypinator 0:bb348c97df44 5355 * This parameter can be one of the following values:
lypinator 0:bb348c97df44 5356 * @arg TIM_ETRPRESCALER_DIV1 : ETRP Prescaler OFF.
lypinator 0:bb348c97df44 5357 * @arg TIM_ETRPRESCALER_DIV2 : ETRP frequency divided by 2.
lypinator 0:bb348c97df44 5358 * @arg TIM_ETRPRESCALER_DIV4 : ETRP frequency divided by 4.
lypinator 0:bb348c97df44 5359 * @arg TIM_ETRPRESCALER_DIV8 : ETRP frequency divided by 8.
lypinator 0:bb348c97df44 5360 * @param TIM_ExtTRGPolarity The external Trigger Polarity.
lypinator 0:bb348c97df44 5361 * This parameter can be one of the following values:
lypinator 0:bb348c97df44 5362 * @arg TIM_ETRPOLARITY_INVERTED : active low or falling edge active.
lypinator 0:bb348c97df44 5363 * @arg TIM_ETRPOLARITY_NONINVERTED : active high or rising edge active.
lypinator 0:bb348c97df44 5364 * @param ExtTRGFilter External Trigger Filter.
lypinator 0:bb348c97df44 5365 * This parameter must be a value between 0x00 and 0x0F
lypinator 0:bb348c97df44 5366 * @retval None
lypinator 0:bb348c97df44 5367 */
lypinator 0:bb348c97df44 5368 static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
lypinator 0:bb348c97df44 5369 uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
lypinator 0:bb348c97df44 5370 {
lypinator 0:bb348c97df44 5371 uint32_t tmpsmcr = 0U;
lypinator 0:bb348c97df44 5372
lypinator 0:bb348c97df44 5373 tmpsmcr = TIMx->SMCR;
lypinator 0:bb348c97df44 5374
lypinator 0:bb348c97df44 5375 /* Reset the ETR Bits */
lypinator 0:bb348c97df44 5376 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
lypinator 0:bb348c97df44 5377
lypinator 0:bb348c97df44 5378 /* Set the Prescaler, the Filter value and the Polarity */
lypinator 0:bb348c97df44 5379 tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8)));
lypinator 0:bb348c97df44 5380
lypinator 0:bb348c97df44 5381 /* Write to TIMx SMCR */
lypinator 0:bb348c97df44 5382 TIMx->SMCR = tmpsmcr;
lypinator 0:bb348c97df44 5383 }
lypinator 0:bb348c97df44 5384
lypinator 0:bb348c97df44 5385 /**
lypinator 0:bb348c97df44 5386 * @}
lypinator 0:bb348c97df44 5387 */
lypinator 0:bb348c97df44 5388
lypinator 0:bb348c97df44 5389 #endif /* HAL_TIM_MODULE_ENABLED */
lypinator 0:bb348c97df44 5390 /**
lypinator 0:bb348c97df44 5391 * @}
lypinator 0:bb348c97df44 5392 */
lypinator 0:bb348c97df44 5393
lypinator 0:bb348c97df44 5394 /**
lypinator 0:bb348c97df44 5395 * @}
lypinator 0:bb348c97df44 5396 */
lypinator 0:bb348c97df44 5397 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/