Thomas Lyp / DevLibMemoryController

Initial commit

Dependencies:   FastPWM

mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_spi.h@0:bb348c97df44, 2020-09-16 (annotated)

Committer:
lypinator
Date:
Wed Sep 16 01:11:49 2020 +0000
Revision:
0:bb348c97df44
Added PWM

Who changed what in which revision?

UserRevisionLine numberNew contents of line
lypinator 0:bb348c97df44 1 /**
lypinator 0:bb348c97df44 2 ******************************************************************************
lypinator 0:bb348c97df44 3 * @file stm32f4xx_hal_spi.h
lypinator 0:bb348c97df44 4 * @author MCD Application Team
lypinator 0:bb348c97df44 5 * @brief Header file of SPI HAL module.
lypinator 0:bb348c97df44 6 ******************************************************************************
lypinator 0:bb348c97df44 7 * @attention
lypinator 0:bb348c97df44 8 *
lypinator 0:bb348c97df44 9 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
lypinator 0:bb348c97df44 10 *
lypinator 0:bb348c97df44 11 * Redistribution and use in source and binary forms, with or without modification,
lypinator 0:bb348c97df44 12 * are permitted provided that the following conditions are met:
lypinator 0:bb348c97df44 13 * 1. Redistributions of source code must retain the above copyright notice,
lypinator 0:bb348c97df44 14 * this list of conditions and the following disclaimer.
lypinator 0:bb348c97df44 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
lypinator 0:bb348c97df44 16 * this list of conditions and the following disclaimer in the documentation
lypinator 0:bb348c97df44 17 * and/or other materials provided with the distribution.
lypinator 0:bb348c97df44 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
lypinator 0:bb348c97df44 19 * may be used to endorse or promote products derived from this software
lypinator 0:bb348c97df44 20 * without specific prior written permission.
lypinator 0:bb348c97df44 21 *
lypinator 0:bb348c97df44 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
lypinator 0:bb348c97df44 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
lypinator 0:bb348c97df44 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
lypinator 0:bb348c97df44 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
lypinator 0:bb348c97df44 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
lypinator 0:bb348c97df44 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
lypinator 0:bb348c97df44 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
lypinator 0:bb348c97df44 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
lypinator 0:bb348c97df44 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
lypinator 0:bb348c97df44 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
lypinator 0:bb348c97df44 32 *
lypinator 0:bb348c97df44 33 ******************************************************************************
lypinator 0:bb348c97df44 34 */
lypinator 0:bb348c97df44 35
lypinator 0:bb348c97df44 36 /* Define to prevent recursive inclusion -------------------------------------*/
lypinator 0:bb348c97df44 37 #ifndef __STM32F4xx_HAL_SPI_H
lypinator 0:bb348c97df44 38 #define __STM32F4xx_HAL_SPI_H
lypinator 0:bb348c97df44 39
lypinator 0:bb348c97df44 40 #ifdef __cplusplus
lypinator 0:bb348c97df44 41 extern "C" {
lypinator 0:bb348c97df44 42 #endif
lypinator 0:bb348c97df44 43
lypinator 0:bb348c97df44 44 /* Includes ------------------------------------------------------------------*/
lypinator 0:bb348c97df44 45 #include "stm32f4xx_hal_def.h"
lypinator 0:bb348c97df44 46
lypinator 0:bb348c97df44 47 /** @addtogroup STM32F4xx_HAL_Driver
lypinator 0:bb348c97df44 48 * @{
lypinator 0:bb348c97df44 49 */
lypinator 0:bb348c97df44 50
lypinator 0:bb348c97df44 51 /** @addtogroup SPI
lypinator 0:bb348c97df44 52 * @{
lypinator 0:bb348c97df44 53 */
lypinator 0:bb348c97df44 54
lypinator 0:bb348c97df44 55 /* Exported types ------------------------------------------------------------*/
lypinator 0:bb348c97df44 56 /** @defgroup SPI_Exported_Types SPI Exported Types
lypinator 0:bb348c97df44 57 * @{
lypinator 0:bb348c97df44 58 */
lypinator 0:bb348c97df44 59
lypinator 0:bb348c97df44 60 /**
lypinator 0:bb348c97df44 61 * @brief SPI Configuration Structure definition
lypinator 0:bb348c97df44 62 */
lypinator 0:bb348c97df44 63 typedef struct
lypinator 0:bb348c97df44 64 {
lypinator 0:bb348c97df44 65 uint32_t Mode; /*!< Specifies the SPI operating mode.
lypinator 0:bb348c97df44 66 This parameter can be a value of @ref SPI_Mode */
lypinator 0:bb348c97df44 67
lypinator 0:bb348c97df44 68 uint32_t Direction; /*!< Specifies the SPI bidirectional mode state.
lypinator 0:bb348c97df44 69 This parameter can be a value of @ref SPI_Direction */
lypinator 0:bb348c97df44 70
lypinator 0:bb348c97df44 71 uint32_t DataSize; /*!< Specifies the SPI data size.
lypinator 0:bb348c97df44 72 This parameter can be a value of @ref SPI_Data_Size */
lypinator 0:bb348c97df44 73
lypinator 0:bb348c97df44 74 uint32_t CLKPolarity; /*!< Specifies the serial clock steady state.
lypinator 0:bb348c97df44 75 This parameter can be a value of @ref SPI_Clock_Polarity */
lypinator 0:bb348c97df44 76
lypinator 0:bb348c97df44 77 uint32_t CLKPhase; /*!< Specifies the clock active edge for the bit capture.
lypinator 0:bb348c97df44 78 This parameter can be a value of @ref SPI_Clock_Phase */
lypinator 0:bb348c97df44 79
lypinator 0:bb348c97df44 80 uint32_t NSS; /*!< Specifies whether the NSS signal is managed by
lypinator 0:bb348c97df44 81 hardware (NSS pin) or by software using the SSI bit.
lypinator 0:bb348c97df44 82 This parameter can be a value of @ref SPI_Slave_Select_management */
lypinator 0:bb348c97df44 83
lypinator 0:bb348c97df44 84 uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be
lypinator 0:bb348c97df44 85 used to configure the transmit and receive SCK clock.
lypinator 0:bb348c97df44 86 This parameter can be a value of @ref SPI_BaudRate_Prescaler
lypinator 0:bb348c97df44 87 @note The communication clock is derived from the master
lypinator 0:bb348c97df44 88 clock. The slave clock does not need to be set. */
lypinator 0:bb348c97df44 89
lypinator 0:bb348c97df44 90 uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
lypinator 0:bb348c97df44 91 This parameter can be a value of @ref SPI_MSB_LSB_transmission */
lypinator 0:bb348c97df44 92
lypinator 0:bb348c97df44 93 uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not.
lypinator 0:bb348c97df44 94 This parameter can be a value of @ref SPI_TI_mode */
lypinator 0:bb348c97df44 95
lypinator 0:bb348c97df44 96 uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
lypinator 0:bb348c97df44 97 This parameter can be a value of @ref SPI_CRC_Calculation */
lypinator 0:bb348c97df44 98
lypinator 0:bb348c97df44 99 uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation.
lypinator 0:bb348c97df44 100 This parameter must be a number between Min_Data = 0 and Max_Data = 65535 */
lypinator 0:bb348c97df44 101 }SPI_InitTypeDef;
lypinator 0:bb348c97df44 102
lypinator 0:bb348c97df44 103 /**
lypinator 0:bb348c97df44 104 * @brief HAL SPI State structure definition
lypinator 0:bb348c97df44 105 */
lypinator 0:bb348c97df44 106 typedef enum
lypinator 0:bb348c97df44 107 {
lypinator 0:bb348c97df44 108 HAL_SPI_STATE_RESET = 0x00U, /*!< Peripheral not Initialized */
lypinator 0:bb348c97df44 109 HAL_SPI_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
lypinator 0:bb348c97df44 110 HAL_SPI_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */
lypinator 0:bb348c97df44 111 HAL_SPI_STATE_BUSY_TX = 0x03U, /*!< Data Transmission process is ongoing */
lypinator 0:bb348c97df44 112 HAL_SPI_STATE_BUSY_RX = 0x04U, /*!< Data Reception process is ongoing */
lypinator 0:bb348c97df44 113 HAL_SPI_STATE_BUSY_TX_RX = 0x05U, /*!< Data Transmission and Reception process is ongoing */
lypinator 0:bb348c97df44 114 HAL_SPI_STATE_ERROR = 0x06U /*!< SPI error state */
lypinator 0:bb348c97df44 115 }HAL_SPI_StateTypeDef;
lypinator 0:bb348c97df44 116
lypinator 0:bb348c97df44 117 /**
lypinator 0:bb348c97df44 118 * @brief SPI handle Structure definition
lypinator 0:bb348c97df44 119 */
lypinator 0:bb348c97df44 120 typedef struct __SPI_HandleTypeDef
lypinator 0:bb348c97df44 121 {
lypinator 0:bb348c97df44 122 SPI_TypeDef *Instance; /* SPI registers base address */
lypinator 0:bb348c97df44 123
lypinator 0:bb348c97df44 124 SPI_InitTypeDef Init; /* SPI communication parameters */
lypinator 0:bb348c97df44 125
lypinator 0:bb348c97df44 126 uint8_t *pTxBuffPtr; /* Pointer to SPI Tx transfer Buffer */
lypinator 0:bb348c97df44 127
lypinator 0:bb348c97df44 128 uint16_t TxXferSize; /* SPI Tx Transfer size */
lypinator 0:bb348c97df44 129
lypinator 0:bb348c97df44 130 __IO uint16_t TxXferCount; /* SPI Tx Transfer Counter */
lypinator 0:bb348c97df44 131
lypinator 0:bb348c97df44 132 uint8_t *pRxBuffPtr; /* Pointer to SPI Rx transfer Buffer */
lypinator 0:bb348c97df44 133
lypinator 0:bb348c97df44 134 uint16_t RxXferSize; /* SPI Rx Transfer size */
lypinator 0:bb348c97df44 135
lypinator 0:bb348c97df44 136 __IO uint16_t RxXferCount; /* SPI Rx Transfer Counter */
lypinator 0:bb348c97df44 137
lypinator 0:bb348c97df44 138 void (*RxISR)(struct __SPI_HandleTypeDef * hspi); /* function pointer on Rx ISR */
lypinator 0:bb348c97df44 139
lypinator 0:bb348c97df44 140 void (*TxISR)(struct __SPI_HandleTypeDef * hspi); /* function pointer on Tx ISR */
lypinator 0:bb348c97df44 141
lypinator 0:bb348c97df44 142 DMA_HandleTypeDef *hdmatx; /* SPI Tx DMA Handle parameters */
lypinator 0:bb348c97df44 143
lypinator 0:bb348c97df44 144 DMA_HandleTypeDef *hdmarx; /* SPI Rx DMA Handle parameters */
lypinator 0:bb348c97df44 145
lypinator 0:bb348c97df44 146 HAL_LockTypeDef Lock; /* Locking object */
lypinator 0:bb348c97df44 147
lypinator 0:bb348c97df44 148 __IO HAL_SPI_StateTypeDef State; /* SPI communication state */
lypinator 0:bb348c97df44 149
lypinator 0:bb348c97df44 150 __IO uint32_t ErrorCode; /* SPI Error code */
lypinator 0:bb348c97df44 151
lypinator 0:bb348c97df44 152 }SPI_HandleTypeDef;
lypinator 0:bb348c97df44 153
lypinator 0:bb348c97df44 154 /**
lypinator 0:bb348c97df44 155 * @}
lypinator 0:bb348c97df44 156 */
lypinator 0:bb348c97df44 157
lypinator 0:bb348c97df44 158 /* Exported constants --------------------------------------------------------*/
lypinator 0:bb348c97df44 159 /** @defgroup SPI_Exported_Constants SPI Exported Constants
lypinator 0:bb348c97df44 160 * @{
lypinator 0:bb348c97df44 161 */
lypinator 0:bb348c97df44 162
lypinator 0:bb348c97df44 163 /** @defgroup SPI_Error_Code SPI Error Code
lypinator 0:bb348c97df44 164 * @{
lypinator 0:bb348c97df44 165 */
lypinator 0:bb348c97df44 166 #define HAL_SPI_ERROR_NONE 0x00000000U /*!< No error */
lypinator 0:bb348c97df44 167 #define HAL_SPI_ERROR_MODF 0x00000001U /*!< MODF error */
lypinator 0:bb348c97df44 168 #define HAL_SPI_ERROR_CRC 0x00000002U /*!< CRC error */
lypinator 0:bb348c97df44 169 #define HAL_SPI_ERROR_OVR 0x00000004U /*!< OVR error */
lypinator 0:bb348c97df44 170 #define HAL_SPI_ERROR_FRE 0x00000008U /*!< FRE error */
lypinator 0:bb348c97df44 171 #define HAL_SPI_ERROR_DMA 0x00000010U /*!< DMA transfer error */
lypinator 0:bb348c97df44 172 #define HAL_SPI_ERROR_FLAG 0x00000020U /*!< Flag: RXNE,TXE, BSY */
lypinator 0:bb348c97df44 173 /**
lypinator 0:bb348c97df44 174 * @}
lypinator 0:bb348c97df44 175 */
lypinator 0:bb348c97df44 176
lypinator 0:bb348c97df44 177 /** @defgroup SPI_Mode SPI Mode
lypinator 0:bb348c97df44 178 * @{
lypinator 0:bb348c97df44 179 */
lypinator 0:bb348c97df44 180 #define SPI_MODE_SLAVE 0x00000000U
lypinator 0:bb348c97df44 181 #define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI)
lypinator 0:bb348c97df44 182 /**
lypinator 0:bb348c97df44 183 * @}
lypinator 0:bb348c97df44 184 */
lypinator 0:bb348c97df44 185
lypinator 0:bb348c97df44 186 /** @defgroup SPI_Direction SPI Direction Mode
lypinator 0:bb348c97df44 187 * @{
lypinator 0:bb348c97df44 188 */
lypinator 0:bb348c97df44 189 #define SPI_DIRECTION_2LINES 0x00000000U
lypinator 0:bb348c97df44 190 #define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY
lypinator 0:bb348c97df44 191 #define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE
lypinator 0:bb348c97df44 192 /**
lypinator 0:bb348c97df44 193 * @}
lypinator 0:bb348c97df44 194 */
lypinator 0:bb348c97df44 195
lypinator 0:bb348c97df44 196 /** @defgroup SPI_Data_Size SPI Data Size
lypinator 0:bb348c97df44 197 * @{
lypinator 0:bb348c97df44 198 */
lypinator 0:bb348c97df44 199 #define SPI_DATASIZE_8BIT 0x00000000U
lypinator 0:bb348c97df44 200 #define SPI_DATASIZE_16BIT SPI_CR1_DFF
lypinator 0:bb348c97df44 201 /**
lypinator 0:bb348c97df44 202 * @}
lypinator 0:bb348c97df44 203 */
lypinator 0:bb348c97df44 204
lypinator 0:bb348c97df44 205 /** @defgroup SPI_Clock_Polarity SPI Clock Polarity
lypinator 0:bb348c97df44 206 * @{
lypinator 0:bb348c97df44 207 */
lypinator 0:bb348c97df44 208 #define SPI_POLARITY_LOW 0x00000000U
lypinator 0:bb348c97df44 209 #define SPI_POLARITY_HIGH SPI_CR1_CPOL
lypinator 0:bb348c97df44 210 /**
lypinator 0:bb348c97df44 211 * @}
lypinator 0:bb348c97df44 212 */
lypinator 0:bb348c97df44 213
lypinator 0:bb348c97df44 214 /** @defgroup SPI_Clock_Phase SPI Clock Phase
lypinator 0:bb348c97df44 215 * @{
lypinator 0:bb348c97df44 216 */
lypinator 0:bb348c97df44 217 #define SPI_PHASE_1EDGE 0x00000000U
lypinator 0:bb348c97df44 218 #define SPI_PHASE_2EDGE SPI_CR1_CPHA
lypinator 0:bb348c97df44 219 /**
lypinator 0:bb348c97df44 220 * @}
lypinator 0:bb348c97df44 221 */
lypinator 0:bb348c97df44 222
lypinator 0:bb348c97df44 223 /** @defgroup SPI_Slave_Select_management SPI Slave Select Management
lypinator 0:bb348c97df44 224 * @{
lypinator 0:bb348c97df44 225 */
lypinator 0:bb348c97df44 226 #define SPI_NSS_SOFT SPI_CR1_SSM
lypinator 0:bb348c97df44 227 #define SPI_NSS_HARD_INPUT 0x00000000U
lypinator 0:bb348c97df44 228 #define SPI_NSS_HARD_OUTPUT 0x00040000U
lypinator 0:bb348c97df44 229 /**
lypinator 0:bb348c97df44 230 * @}
lypinator 0:bb348c97df44 231 */
lypinator 0:bb348c97df44 232
lypinator 0:bb348c97df44 233 /** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler
lypinator 0:bb348c97df44 234 * @{
lypinator 0:bb348c97df44 235 */
lypinator 0:bb348c97df44 236 #define SPI_BAUDRATEPRESCALER_2 0x00000000U
lypinator 0:bb348c97df44 237 #define SPI_BAUDRATEPRESCALER_4 0x00000008U
lypinator 0:bb348c97df44 238 #define SPI_BAUDRATEPRESCALER_8 0x00000010U
lypinator 0:bb348c97df44 239 #define SPI_BAUDRATEPRESCALER_16 0x00000018U
lypinator 0:bb348c97df44 240 #define SPI_BAUDRATEPRESCALER_32 0x00000020U
lypinator 0:bb348c97df44 241 #define SPI_BAUDRATEPRESCALER_64 0x00000028U
lypinator 0:bb348c97df44 242 #define SPI_BAUDRATEPRESCALER_128 0x00000030U
lypinator 0:bb348c97df44 243 #define SPI_BAUDRATEPRESCALER_256 0x00000038U
lypinator 0:bb348c97df44 244 /**
lypinator 0:bb348c97df44 245 * @}
lypinator 0:bb348c97df44 246 */
lypinator 0:bb348c97df44 247
lypinator 0:bb348c97df44 248 /** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB Transmission
lypinator 0:bb348c97df44 249 * @{
lypinator 0:bb348c97df44 250 */
lypinator 0:bb348c97df44 251 #define SPI_FIRSTBIT_MSB 0x00000000U
lypinator 0:bb348c97df44 252 #define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST
lypinator 0:bb348c97df44 253 /**
lypinator 0:bb348c97df44 254 * @}
lypinator 0:bb348c97df44 255 */
lypinator 0:bb348c97df44 256
lypinator 0:bb348c97df44 257 /** @defgroup SPI_TI_mode SPI TI Mode
lypinator 0:bb348c97df44 258 * @{
lypinator 0:bb348c97df44 259 */
lypinator 0:bb348c97df44 260 #define SPI_TIMODE_DISABLE 0x00000000U
lypinator 0:bb348c97df44 261 #define SPI_TIMODE_ENABLE SPI_CR2_FRF
lypinator 0:bb348c97df44 262 /**
lypinator 0:bb348c97df44 263 * @}
lypinator 0:bb348c97df44 264 */
lypinator 0:bb348c97df44 265
lypinator 0:bb348c97df44 266 /** @defgroup SPI_CRC_Calculation SPI CRC Calculation
lypinator 0:bb348c97df44 267 * @{
lypinator 0:bb348c97df44 268 */
lypinator 0:bb348c97df44 269 #define SPI_CRCCALCULATION_DISABLE 0x00000000U
lypinator 0:bb348c97df44 270 #define SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN
lypinator 0:bb348c97df44 271 /**
lypinator 0:bb348c97df44 272 * @}
lypinator 0:bb348c97df44 273 */
lypinator 0:bb348c97df44 274
lypinator 0:bb348c97df44 275 /** @defgroup SPI_Interrupt_definition SPI Interrupt Definition
lypinator 0:bb348c97df44 276 * @{
lypinator 0:bb348c97df44 277 */
lypinator 0:bb348c97df44 278 #define SPI_IT_TXE SPI_CR2_TXEIE
lypinator 0:bb348c97df44 279 #define SPI_IT_RXNE SPI_CR2_RXNEIE
lypinator 0:bb348c97df44 280 #define SPI_IT_ERR SPI_CR2_ERRIE
lypinator 0:bb348c97df44 281 /**
lypinator 0:bb348c97df44 282 * @}
lypinator 0:bb348c97df44 283 */
lypinator 0:bb348c97df44 284
lypinator 0:bb348c97df44 285 /** @defgroup SPI_Flags_definition SPI Flags Definition
lypinator 0:bb348c97df44 286 * @{
lypinator 0:bb348c97df44 287 */
lypinator 0:bb348c97df44 288 #define SPI_FLAG_RXNE SPI_SR_RXNE /* SPI status flag: Rx buffer not empty flag */
lypinator 0:bb348c97df44 289 #define SPI_FLAG_TXE SPI_SR_TXE /* SPI status flag: Tx buffer empty flag */
lypinator 0:bb348c97df44 290 #define SPI_FLAG_BSY SPI_SR_BSY /* SPI status flag: Busy flag */
lypinator 0:bb348c97df44 291 #define SPI_FLAG_CRCERR SPI_SR_CRCERR /* SPI Error flag: CRC error flag */
lypinator 0:bb348c97df44 292 #define SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag: Mode fault flag */
lypinator 0:bb348c97df44 293 #define SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag: Overrun flag */
lypinator 0:bb348c97df44 294 #define SPI_FLAG_FRE SPI_SR_FRE /* SPI Error flag: TI mode frame format error flag */
lypinator 0:bb348c97df44 295 /**
lypinator 0:bb348c97df44 296 * @}
lypinator 0:bb348c97df44 297 */
lypinator 0:bb348c97df44 298
lypinator 0:bb348c97df44 299 /**
lypinator 0:bb348c97df44 300 * @}
lypinator 0:bb348c97df44 301 */
lypinator 0:bb348c97df44 302
lypinator 0:bb348c97df44 303 /* Exported macro ------------------------------------------------------------*/
lypinator 0:bb348c97df44 304 /** @defgroup SPI_Exported_Macros SPI Exported Macros
lypinator 0:bb348c97df44 305 * @{
lypinator 0:bb348c97df44 306 */
lypinator 0:bb348c97df44 307
lypinator 0:bb348c97df44 308 /** @brief Reset SPI handle state.
lypinator 0:bb348c97df44 309 * @param __HANDLE__ specifies the SPI Handle.
lypinator 0:bb348c97df44 310 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
lypinator 0:bb348c97df44 311 * @retval None
lypinator 0:bb348c97df44 312 */
lypinator 0:bb348c97df44 313 #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
lypinator 0:bb348c97df44 314
lypinator 0:bb348c97df44 315 /** @brief Enable or disable the specified SPI interrupts.
lypinator 0:bb348c97df44 316 * @param __HANDLE__ specifies the SPI Handle.
lypinator 0:bb348c97df44 317 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
lypinator 0:bb348c97df44 318 * @param __INTERRUPT__ specifies the interrupt source to enable or disable.
lypinator 0:bb348c97df44 319 * This parameter can be one of the following values:
lypinator 0:bb348c97df44 320 * @arg SPI_IT_TXE: Tx buffer empty interrupt enable
lypinator 0:bb348c97df44 321 * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
lypinator 0:bb348c97df44 322 * @arg SPI_IT_ERR: Error interrupt enable
lypinator 0:bb348c97df44 323 * @retval None
lypinator 0:bb348c97df44 324 */
lypinator 0:bb348c97df44 325 #define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
lypinator 0:bb348c97df44 326 #define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__)))
lypinator 0:bb348c97df44 327
lypinator 0:bb348c97df44 328 /** @brief Check whether the specified SPI interrupt source is enabled or not.
lypinator 0:bb348c97df44 329 * @param __HANDLE__ specifies the SPI Handle.
lypinator 0:bb348c97df44 330 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
lypinator 0:bb348c97df44 331 * @param __INTERRUPT__ specifies the SPI interrupt source to check.
lypinator 0:bb348c97df44 332 * This parameter can be one of the following values:
lypinator 0:bb348c97df44 333 * @arg SPI_IT_TXE: Tx buffer empty interrupt enable
lypinator 0:bb348c97df44 334 * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
lypinator 0:bb348c97df44 335 * @arg SPI_IT_ERR: Error interrupt enable
lypinator 0:bb348c97df44 336 * @retval The new state of __IT__ (TRUE or FALSE).
lypinator 0:bb348c97df44 337 */
lypinator 0:bb348c97df44 338 #define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
lypinator 0:bb348c97df44 339
lypinator 0:bb348c97df44 340 /** @brief Check whether the specified SPI flag is set or not.
lypinator 0:bb348c97df44 341 * @param __HANDLE__ specifies the SPI Handle.
lypinator 0:bb348c97df44 342 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
lypinator 0:bb348c97df44 343 * @param __FLAG__ specifies the flag to check.
lypinator 0:bb348c97df44 344 * This parameter can be one of the following values:
lypinator 0:bb348c97df44 345 * @arg SPI_FLAG_RXNE: Receive buffer not empty flag
lypinator 0:bb348c97df44 346 * @arg SPI_FLAG_TXE: Transmit buffer empty flag
lypinator 0:bb348c97df44 347 * @arg SPI_FLAG_CRCERR: CRC error flag
lypinator 0:bb348c97df44 348 * @arg SPI_FLAG_MODF: Mode fault flag
lypinator 0:bb348c97df44 349 * @arg SPI_FLAG_OVR: Overrun flag
lypinator 0:bb348c97df44 350 * @arg SPI_FLAG_BSY: Busy flag
lypinator 0:bb348c97df44 351 * @arg SPI_FLAG_FRE: Frame format error flag
lypinator 0:bb348c97df44 352 * @retval The new state of __FLAG__ (TRUE or FALSE).
lypinator 0:bb348c97df44 353 */
lypinator 0:bb348c97df44 354 #define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
lypinator 0:bb348c97df44 355
lypinator 0:bb348c97df44 356 /** @brief Clear the SPI CRCERR pending flag.
lypinator 0:bb348c97df44 357 * @param __HANDLE__ specifies the SPI Handle.
lypinator 0:bb348c97df44 358 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
lypinator 0:bb348c97df44 359 * @retval None
lypinator 0:bb348c97df44 360 */
lypinator 0:bb348c97df44 361 #define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR))
lypinator 0:bb348c97df44 362
lypinator 0:bb348c97df44 363 /** @brief Clear the SPI MODF pending flag.
lypinator 0:bb348c97df44 364 * @param __HANDLE__ specifies the SPI Handle.
lypinator 0:bb348c97df44 365 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
lypinator 0:bb348c97df44 366 * @retval None
lypinator 0:bb348c97df44 367 */
lypinator 0:bb348c97df44 368 #define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) \
lypinator 0:bb348c97df44 369 do{ \
lypinator 0:bb348c97df44 370 __IO uint32_t tmpreg_modf = 0x00U; \
lypinator 0:bb348c97df44 371 tmpreg_modf = (__HANDLE__)->Instance->SR; \
lypinator 0:bb348c97df44 372 (__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE); \
lypinator 0:bb348c97df44 373 UNUSED(tmpreg_modf); \
lypinator 0:bb348c97df44 374 } while(0U)
lypinator 0:bb348c97df44 375
lypinator 0:bb348c97df44 376 /** @brief Clear the SPI OVR pending flag.
lypinator 0:bb348c97df44 377 * @param __HANDLE__ specifies the SPI Handle.
lypinator 0:bb348c97df44 378 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
lypinator 0:bb348c97df44 379 * @retval None
lypinator 0:bb348c97df44 380 */
lypinator 0:bb348c97df44 381 #define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) \
lypinator 0:bb348c97df44 382 do{ \
lypinator 0:bb348c97df44 383 __IO uint32_t tmpreg_ovr = 0x00U; \
lypinator 0:bb348c97df44 384 tmpreg_ovr = (__HANDLE__)->Instance->DR; \
lypinator 0:bb348c97df44 385 tmpreg_ovr = (__HANDLE__)->Instance->SR; \
lypinator 0:bb348c97df44 386 UNUSED(tmpreg_ovr); \
lypinator 0:bb348c97df44 387 } while(0U)
lypinator 0:bb348c97df44 388
lypinator 0:bb348c97df44 389 /** @brief Clear the SPI FRE pending flag.
lypinator 0:bb348c97df44 390 * @param __HANDLE__ specifies the SPI Handle.
lypinator 0:bb348c97df44 391 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
lypinator 0:bb348c97df44 392 * @retval None
lypinator 0:bb348c97df44 393 */
lypinator 0:bb348c97df44 394 #define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) \
lypinator 0:bb348c97df44 395 do{ \
lypinator 0:bb348c97df44 396 __IO uint32_t tmpreg_fre = 0x00U; \
lypinator 0:bb348c97df44 397 tmpreg_fre = (__HANDLE__)->Instance->SR; \
lypinator 0:bb348c97df44 398 UNUSED(tmpreg_fre); \
lypinator 0:bb348c97df44 399 }while(0U)
lypinator 0:bb348c97df44 400
lypinator 0:bb348c97df44 401 /** @brief Enable the SPI peripheral.
lypinator 0:bb348c97df44 402 * @param __HANDLE__ specifies the SPI Handle.
lypinator 0:bb348c97df44 403 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
lypinator 0:bb348c97df44 404 * @retval None
lypinator 0:bb348c97df44 405 */
lypinator 0:bb348c97df44 406 #define __HAL_SPI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_SPE)
lypinator 0:bb348c97df44 407
lypinator 0:bb348c97df44 408 /** @brief Disable the SPI peripheral.
lypinator 0:bb348c97df44 409 * @param __HANDLE__ specifies the SPI Handle.
lypinator 0:bb348c97df44 410 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
lypinator 0:bb348c97df44 411 * @retval None
lypinator 0:bb348c97df44 412 */
lypinator 0:bb348c97df44 413 #define __HAL_SPI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE))
lypinator 0:bb348c97df44 414 /**
lypinator 0:bb348c97df44 415 * @}
lypinator 0:bb348c97df44 416 */
lypinator 0:bb348c97df44 417
lypinator 0:bb348c97df44 418 /* Exported functions --------------------------------------------------------*/
lypinator 0:bb348c97df44 419 /** @addtogroup SPI_Exported_Functions
lypinator 0:bb348c97df44 420 * @{
lypinator 0:bb348c97df44 421 */
lypinator 0:bb348c97df44 422
lypinator 0:bb348c97df44 423 /** @addtogroup SPI_Exported_Functions_Group1
lypinator 0:bb348c97df44 424 * @{
lypinator 0:bb348c97df44 425 */
lypinator 0:bb348c97df44 426 /* Initialization/de-initialization functions **********************************/
lypinator 0:bb348c97df44 427 HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);
lypinator 0:bb348c97df44 428 HAL_StatusTypeDef HAL_SPI_DeInit (SPI_HandleTypeDef *hspi);
lypinator 0:bb348c97df44 429 void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);
lypinator 0:bb348c97df44 430 void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);
lypinator 0:bb348c97df44 431 /**
lypinator 0:bb348c97df44 432 * @}
lypinator 0:bb348c97df44 433 */
lypinator 0:bb348c97df44 434
lypinator 0:bb348c97df44 435 /** @addtogroup SPI_Exported_Functions_Group2
lypinator 0:bb348c97df44 436 * @{
lypinator 0:bb348c97df44 437 */
lypinator 0:bb348c97df44 438 /* I/O operation functions *****************************************************/
lypinator 0:bb348c97df44 439 HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
lypinator 0:bb348c97df44 440 HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
lypinator 0:bb348c97df44 441 HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
lypinator 0:bb348c97df44 442 HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
lypinator 0:bb348c97df44 443 HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
lypinator 0:bb348c97df44 444 HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
lypinator 0:bb348c97df44 445 HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
lypinator 0:bb348c97df44 446 HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
lypinator 0:bb348c97df44 447 HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
lypinator 0:bb348c97df44 448 HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);
lypinator 0:bb348c97df44 449 HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);
lypinator 0:bb348c97df44 450 HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi);
lypinator 0:bb348c97df44 451 /* Transfer Abort functions */
lypinator 0:bb348c97df44 452 HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi);
lypinator 0:bb348c97df44 453 HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi);
lypinator 0:bb348c97df44 454
lypinator 0:bb348c97df44 455 void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi);
lypinator 0:bb348c97df44 456 void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi);
lypinator 0:bb348c97df44 457 void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi);
lypinator 0:bb348c97df44 458 void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi);
lypinator 0:bb348c97df44 459 void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi);
lypinator 0:bb348c97df44 460 void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi);
lypinator 0:bb348c97df44 461 void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi);
lypinator 0:bb348c97df44 462 void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);
lypinator 0:bb348c97df44 463 void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi);
lypinator 0:bb348c97df44 464 /**
lypinator 0:bb348c97df44 465 * @}
lypinator 0:bb348c97df44 466 */
lypinator 0:bb348c97df44 467
lypinator 0:bb348c97df44 468 /** @addtogroup SPI_Exported_Functions_Group3
lypinator 0:bb348c97df44 469 * @{
lypinator 0:bb348c97df44 470 */
lypinator 0:bb348c97df44 471 /* Peripheral State and Error functions ***************************************/
lypinator 0:bb348c97df44 472 HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi);
lypinator 0:bb348c97df44 473 uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
lypinator 0:bb348c97df44 474 /**
lypinator 0:bb348c97df44 475 * @}
lypinator 0:bb348c97df44 476 */
lypinator 0:bb348c97df44 477
lypinator 0:bb348c97df44 478 /**
lypinator 0:bb348c97df44 479 * @}
lypinator 0:bb348c97df44 480 */
lypinator 0:bb348c97df44 481
lypinator 0:bb348c97df44 482 /* Private types -------------------------------------------------------------*/
lypinator 0:bb348c97df44 483 /* Private variables ---------------------------------------------------------*/
lypinator 0:bb348c97df44 484 /* Private constants ---------------------------------------------------------*/
lypinator 0:bb348c97df44 485
lypinator 0:bb348c97df44 486 /* Private macros ------------------------------------------------------------*/
lypinator 0:bb348c97df44 487 /** @defgroup SPI_Private_Macros SPI Private Macros
lypinator 0:bb348c97df44 488 * @{
lypinator 0:bb348c97df44 489 */
lypinator 0:bb348c97df44 490
lypinator 0:bb348c97df44 491 /** @brief Set the SPI transmit-only mode.
lypinator 0:bb348c97df44 492 * @param __HANDLE__ specifies the SPI Handle.
lypinator 0:bb348c97df44 493 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
lypinator 0:bb348c97df44 494 * @retval None
lypinator 0:bb348c97df44 495 */
lypinator 0:bb348c97df44 496 #define SPI_1LINE_TX(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_BIDIOE)
lypinator 0:bb348c97df44 497
lypinator 0:bb348c97df44 498 /** @brief Set the SPI receive-only mode.
lypinator 0:bb348c97df44 499 * @param __HANDLE__ specifies the SPI Handle.
lypinator 0:bb348c97df44 500 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
lypinator 0:bb348c97df44 501 * @retval None
lypinator 0:bb348c97df44 502 */
lypinator 0:bb348c97df44 503 #define SPI_1LINE_RX(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_BIDIOE))
lypinator 0:bb348c97df44 504
lypinator 0:bb348c97df44 505 /** @brief Reset the CRC calculation of the SPI.
lypinator 0:bb348c97df44 506 * @param __HANDLE__ specifies the SPI Handle.
lypinator 0:bb348c97df44 507 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
lypinator 0:bb348c97df44 508 * @retval None
lypinator 0:bb348c97df44 509 */
lypinator 0:bb348c97df44 510 #define SPI_RESET_CRC(__HANDLE__) do{(__HANDLE__)->Instance->CR1 &= (uint16_t)(~SPI_CR1_CRCEN);\
lypinator 0:bb348c97df44 511 (__HANDLE__)->Instance->CR1 |= SPI_CR1_CRCEN;}while(0U)
lypinator 0:bb348c97df44 512
lypinator 0:bb348c97df44 513 #define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \
lypinator 0:bb348c97df44 514 ((MODE) == SPI_MODE_MASTER))
lypinator 0:bb348c97df44 515
lypinator 0:bb348c97df44 516 #define IS_SPI_DIRECTION(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \
lypinator 0:bb348c97df44 517 ((MODE) == SPI_DIRECTION_2LINES_RXONLY) || \
lypinator 0:bb348c97df44 518 ((MODE) == SPI_DIRECTION_1LINE))
lypinator 0:bb348c97df44 519
lypinator 0:bb348c97df44 520 #define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES)
lypinator 0:bb348c97df44 521
lypinator 0:bb348c97df44 522 #define IS_SPI_DIRECTION_2LINES_OR_1LINE(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \
lypinator 0:bb348c97df44 523 ((MODE) == SPI_DIRECTION_1LINE))
lypinator 0:bb348c97df44 524
lypinator 0:bb348c97df44 525 #define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_16BIT) || \
lypinator 0:bb348c97df44 526 ((DATASIZE) == SPI_DATASIZE_8BIT))
lypinator 0:bb348c97df44 527
lypinator 0:bb348c97df44 528 #define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_POLARITY_LOW) || \
lypinator 0:bb348c97df44 529 ((CPOL) == SPI_POLARITY_HIGH))
lypinator 0:bb348c97df44 530
lypinator 0:bb348c97df44 531 #define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) || \
lypinator 0:bb348c97df44 532 ((CPHA) == SPI_PHASE_2EDGE))
lypinator 0:bb348c97df44 533
lypinator 0:bb348c97df44 534 #define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) || \
lypinator 0:bb348c97df44 535 ((NSS) == SPI_NSS_HARD_INPUT) || \
lypinator 0:bb348c97df44 536 ((NSS) == SPI_NSS_HARD_OUTPUT))
lypinator 0:bb348c97df44 537
lypinator 0:bb348c97df44 538 #define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2) || \
lypinator 0:bb348c97df44 539 ((PRESCALER) == SPI_BAUDRATEPRESCALER_4) || \
lypinator 0:bb348c97df44 540 ((PRESCALER) == SPI_BAUDRATEPRESCALER_8) || \
lypinator 0:bb348c97df44 541 ((PRESCALER) == SPI_BAUDRATEPRESCALER_16) || \
lypinator 0:bb348c97df44 542 ((PRESCALER) == SPI_BAUDRATEPRESCALER_32) || \
lypinator 0:bb348c97df44 543 ((PRESCALER) == SPI_BAUDRATEPRESCALER_64) || \
lypinator 0:bb348c97df44 544 ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \
lypinator 0:bb348c97df44 545 ((PRESCALER) == SPI_BAUDRATEPRESCALER_256))
lypinator 0:bb348c97df44 546
lypinator 0:bb348c97df44 547 #define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || \
lypinator 0:bb348c97df44 548 ((BIT) == SPI_FIRSTBIT_LSB))
lypinator 0:bb348c97df44 549
lypinator 0:bb348c97df44 550 #define IS_SPI_TIMODE(MODE) (((MODE) == SPI_TIMODE_DISABLE) || \
lypinator 0:bb348c97df44 551 ((MODE) == SPI_TIMODE_ENABLE))
lypinator 0:bb348c97df44 552
lypinator 0:bb348c97df44 553 #define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLE) || \
lypinator 0:bb348c97df44 554 ((CALCULATION) == SPI_CRCCALCULATION_ENABLE))
lypinator 0:bb348c97df44 555
lypinator 0:bb348c97df44 556 #define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x01U) && ((POLYNOMIAL) <= 0xFFFFU))
lypinator 0:bb348c97df44 557
lypinator 0:bb348c97df44 558 /**
lypinator 0:bb348c97df44 559 * @}
lypinator 0:bb348c97df44 560 */
lypinator 0:bb348c97df44 561
lypinator 0:bb348c97df44 562 /* Private functions ---------------------------------------------------------*/
lypinator 0:bb348c97df44 563 /** @defgroup SPI_Private_Functions SPI Private Functions
lypinator 0:bb348c97df44 564 * @{
lypinator 0:bb348c97df44 565 */
lypinator 0:bb348c97df44 566
lypinator 0:bb348c97df44 567 /**
lypinator 0:bb348c97df44 568 * @}
lypinator 0:bb348c97df44 569 */
lypinator 0:bb348c97df44 570
lypinator 0:bb348c97df44 571 /**
lypinator 0:bb348c97df44 572 * @}
lypinator 0:bb348c97df44 573 */
lypinator 0:bb348c97df44 574
lypinator 0:bb348c97df44 575 /**
lypinator 0:bb348c97df44 576 * @}
lypinator 0:bb348c97df44 577 */
lypinator 0:bb348c97df44 578
lypinator 0:bb348c97df44 579 #ifdef __cplusplus
lypinator 0:bb348c97df44 580 }
lypinator 0:bb348c97df44 581 #endif
lypinator 0:bb348c97df44 582
lypinator 0:bb348c97df44 583 #endif /* __STM32F4xx_HAL_SPI_H */
lypinator 0:bb348c97df44 584
lypinator 0:bb348c97df44 585 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/