DevLibMemoryController - Initial commit

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Initial commit

mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rcc_ex.h@0:bb348c97df44, 2020-09-16 (annotated)

Committer:: lypinator
Date:: Wed Sep 16 01:11:49 2020 +0000
Revision:: 0:bb348c97df44

Added PWM

Who changed what in which revision?

User	Revision	Line number	New contents of line
lypinator	0:bb348c97df44	1	/**
lypinator	0:bb348c97df44	2	******************************************************************************
lypinator	0:bb348c97df44	3	* @file stm32f4xx_hal_rcc_ex.h
lypinator	0:bb348c97df44	4	* @author MCD Application Team
lypinator	0:bb348c97df44	5	* @brief Header file of RCC HAL Extension module.
lypinator	0:bb348c97df44	6	******************************************************************************
lypinator	0:bb348c97df44	7	* @attention
lypinator	0:bb348c97df44	8	*
lypinator	0:bb348c97df44	9	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
lypinator	0:bb348c97df44	10	*
lypinator	0:bb348c97df44	11	* Redistribution and use in source and binary forms, with or without modification,
lypinator	0:bb348c97df44	12	* are permitted provided that the following conditions are met:
lypinator	0:bb348c97df44	13	* 1. Redistributions of source code must retain the above copyright notice,
lypinator	0:bb348c97df44	14	* this list of conditions and the following disclaimer.
lypinator	0:bb348c97df44	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
lypinator	0:bb348c97df44	16	* this list of conditions and the following disclaimer in the documentation
lypinator	0:bb348c97df44	17	* and/or other materials provided with the distribution.
lypinator	0:bb348c97df44	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
lypinator	0:bb348c97df44	19	* may be used to endorse or promote products derived from this software
lypinator	0:bb348c97df44	20	* without specific prior written permission.
lypinator	0:bb348c97df44	21	*
lypinator	0:bb348c97df44	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
lypinator	0:bb348c97df44	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
lypinator	0:bb348c97df44	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
lypinator	0:bb348c97df44	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
lypinator	0:bb348c97df44	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
lypinator	0:bb348c97df44	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
lypinator	0:bb348c97df44	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
lypinator	0:bb348c97df44	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
lypinator	0:bb348c97df44	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
lypinator	0:bb348c97df44	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
lypinator	0:bb348c97df44	32	*
lypinator	0:bb348c97df44	33	******************************************************************************
lypinator	0:bb348c97df44	34	*/
lypinator	0:bb348c97df44	35
lypinator	0:bb348c97df44	36	/* Define to prevent recursive inclusion -------------------------------------*/
lypinator	0:bb348c97df44	37	#ifndef __STM32F4xx_HAL_RCC_EX_H
lypinator	0:bb348c97df44	38	#define __STM32F4xx_HAL_RCC_EX_H
lypinator	0:bb348c97df44	39
lypinator	0:bb348c97df44	40	#ifdef __cplusplus
lypinator	0:bb348c97df44	41	extern "C" {
lypinator	0:bb348c97df44	42	#endif
lypinator	0:bb348c97df44	43
lypinator	0:bb348c97df44	44	/* Includes ------------------------------------------------------------------*/
lypinator	0:bb348c97df44	45	#include "stm32f4xx_hal_def.h"
lypinator	0:bb348c97df44	46
lypinator	0:bb348c97df44	47	/** @addtogroup STM32F4xx_HAL_Driver
lypinator	0:bb348c97df44	48	* @{
lypinator	0:bb348c97df44	49	*/
lypinator	0:bb348c97df44	50
lypinator	0:bb348c97df44	51	/** @addtogroup RCCEx
lypinator	0:bb348c97df44	52	* @{
lypinator	0:bb348c97df44	53	*/
lypinator	0:bb348c97df44	54
lypinator	0:bb348c97df44	55	/* Exported types ------------------------------------------------------------*/
lypinator	0:bb348c97df44	56	/** @defgroup RCCEx_Exported_Types RCCEx Exported Types
lypinator	0:bb348c97df44	57	* @{
lypinator	0:bb348c97df44	58	*/
lypinator	0:bb348c97df44	59
lypinator	0:bb348c97df44	60	/**
lypinator	0:bb348c97df44	61	* @brief RCC PLL configuration structure definition
lypinator	0:bb348c97df44	62	*/
lypinator	0:bb348c97df44	63	typedef struct
lypinator	0:bb348c97df44	64	{
lypinator	0:bb348c97df44	65	uint32_t PLLState; /*!< The new state of the PLL.
lypinator	0:bb348c97df44	66	This parameter can be a value of @ref RCC_PLL_Config */
lypinator	0:bb348c97df44	67
lypinator	0:bb348c97df44	68	uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source.
lypinator	0:bb348c97df44	69	This parameter must be a value of @ref RCC_PLL_Clock_Source */
lypinator	0:bb348c97df44	70
lypinator	0:bb348c97df44	71	uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock.
lypinator	0:bb348c97df44	72	This parameter must be a number between Min_Data = 0 and Max_Data = 63 */
lypinator	0:bb348c97df44	73
lypinator	0:bb348c97df44	74	uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock.
lypinator	0:bb348c97df44	75	This parameter must be a number between Min_Data = 50 and Max_Data = 432
lypinator	0:bb348c97df44	76	except for STM32F411xE devices where the Min_Data = 192 */
lypinator	0:bb348c97df44	77
lypinator	0:bb348c97df44	78	uint32_t PLLP; /*!< PLLP: Division factor for main system clock (SYSCLK).
lypinator	0:bb348c97df44	79	This parameter must be a value of @ref RCC_PLLP_Clock_Divider */
lypinator	0:bb348c97df44	80
lypinator	0:bb348c97df44	81	uint32_t PLLQ; /*!< PLLQ: Division factor for OTG FS, SDIO and RNG clocks.
lypinator	0:bb348c97df44	82	This parameter must be a number between Min_Data = 2 and Max_Data = 15 */
lypinator	0:bb348c97df44	83	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx) \|\| defined(STM32F446xx) \|\| defined(STM32F469xx) \|\|\
lypinator	0:bb348c97df44	84	defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx) \|\|\
lypinator	0:bb348c97df44	85	defined(STM32F413xx) \|\| defined(STM32F423xx)
lypinator	0:bb348c97df44	86	uint32_t PLLR; /*!< PLLR: PLL division factor for I2S, SAI, SYSTEM, SPDIFRX clocks.
lypinator	0:bb348c97df44	87	This parameter is only available in STM32F410xx/STM32F446xx/STM32F469xx/STM32F479xx
lypinator	0:bb348c97df44	88	and STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx/STM32F413xx/STM32F423xx devices.
lypinator	0:bb348c97df44	89	This parameter must be a number between Min_Data = 2 and Max_Data = 7 */
lypinator	0:bb348c97df44	90	#endif /* STM32F410xx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx \|\| STM32F413xx \|\| STM32F423xx */
lypinator	0:bb348c97df44	91	}RCC_PLLInitTypeDef;
lypinator	0:bb348c97df44	92
lypinator	0:bb348c97df44	93	#if defined(STM32F446xx)
lypinator	0:bb348c97df44	94	/**
lypinator	0:bb348c97df44	95	* @brief PLLI2S Clock structure definition
lypinator	0:bb348c97df44	96	*/
lypinator	0:bb348c97df44	97	typedef struct
lypinator	0:bb348c97df44	98	{
lypinator	0:bb348c97df44	99	uint32_t PLLI2SM; /*!< Specifies division factor for PLL VCO input clock.
lypinator	0:bb348c97df44	100	This parameter must be a number between Min_Data = 2 and Max_Data = 63 */
lypinator	0:bb348c97df44	101
lypinator	0:bb348c97df44	102	uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
lypinator	0:bb348c97df44	103	This parameter must be a number between Min_Data = 50 and Max_Data = 432 */
lypinator	0:bb348c97df44	104
lypinator	0:bb348c97df44	105	uint32_t PLLI2SP; /*!< Specifies division factor for SPDIFRX Clock.
lypinator	0:bb348c97df44	106	This parameter must be a value of @ref RCCEx_PLLI2SP_Clock_Divider */
lypinator	0:bb348c97df44	107
lypinator	0:bb348c97df44	108	uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI clock.
lypinator	0:bb348c97df44	109	This parameter must be a number between Min_Data = 2 and Max_Data = 15.
lypinator	0:bb348c97df44	110	This parameter will be used only when PLLI2S is selected as Clock Source SAI */
lypinator	0:bb348c97df44	111
lypinator	0:bb348c97df44	112	uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock.
lypinator	0:bb348c97df44	113	This parameter must be a number between Min_Data = 2 and Max_Data = 7.
lypinator	0:bb348c97df44	114	This parameter will be used only when PLLI2S is selected as Clock Source I2S */
lypinator	0:bb348c97df44	115	}RCC_PLLI2SInitTypeDef;
lypinator	0:bb348c97df44	116
lypinator	0:bb348c97df44	117	/**
lypinator	0:bb348c97df44	118	* @brief PLLSAI Clock structure definition
lypinator	0:bb348c97df44	119	*/
lypinator	0:bb348c97df44	120	typedef struct
lypinator	0:bb348c97df44	121	{
lypinator	0:bb348c97df44	122	uint32_t PLLSAIM; /*!< Spcifies division factor for PLL VCO input clock.
lypinator	0:bb348c97df44	123	This parameter must be a number between Min_Data = 2 and Max_Data = 63 */
lypinator	0:bb348c97df44	124
lypinator	0:bb348c97df44	125	uint32_t PLLSAIN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
lypinator	0:bb348c97df44	126	This parameter must be a number between Min_Data = 50 and Max_Data = 432 */
lypinator	0:bb348c97df44	127
lypinator	0:bb348c97df44	128	uint32_t PLLSAIP; /*!< Specifies division factor for OTG FS, SDIO and RNG clocks.
lypinator	0:bb348c97df44	129	This parameter must be a value of @ref RCCEx_PLLSAIP_Clock_Divider */
lypinator	0:bb348c97df44	130
lypinator	0:bb348c97df44	131	uint32_t PLLSAIQ; /*!< Specifies the division factor for SAI clock.
lypinator	0:bb348c97df44	132	This parameter must be a number between Min_Data = 2 and Max_Data = 15.
lypinator	0:bb348c97df44	133	This parameter will be used only when PLLSAI is selected as Clock Source SAI */
lypinator	0:bb348c97df44	134	}RCC_PLLSAIInitTypeDef;
lypinator	0:bb348c97df44	135
lypinator	0:bb348c97df44	136	/**
lypinator	0:bb348c97df44	137	* @brief RCC extended clocks structure definition
lypinator	0:bb348c97df44	138	*/
lypinator	0:bb348c97df44	139	typedef struct
lypinator	0:bb348c97df44	140	{
lypinator	0:bb348c97df44	141	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
lypinator	0:bb348c97df44	142	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
lypinator	0:bb348c97df44	143
lypinator	0:bb348c97df44	144	RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters.
lypinator	0:bb348c97df44	145	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
lypinator	0:bb348c97df44	146
lypinator	0:bb348c97df44	147	RCC_PLLSAIInitTypeDef PLLSAI; /*!< PLL SAI structure parameters.
lypinator	0:bb348c97df44	148	This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */
lypinator	0:bb348c97df44	149
lypinator	0:bb348c97df44	150	uint32_t PLLI2SDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
lypinator	0:bb348c97df44	151	This parameter must be a number between Min_Data = 1 and Max_Data = 32
lypinator	0:bb348c97df44	152	This parameter will be used only when PLLI2S is selected as Clock Source SAI */
lypinator	0:bb348c97df44	153
lypinator	0:bb348c97df44	154	uint32_t PLLSAIDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
lypinator	0:bb348c97df44	155	This parameter must be a number between Min_Data = 1 and Max_Data = 32
lypinator	0:bb348c97df44	156	This parameter will be used only when PLLSAI is selected as Clock Source SAI */
lypinator	0:bb348c97df44	157
lypinator	0:bb348c97df44	158	uint32_t Sai1ClockSelection; /*!< Specifies SAI1 Clock Source Selection.
lypinator	0:bb348c97df44	159	This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */
lypinator	0:bb348c97df44	160
lypinator	0:bb348c97df44	161	uint32_t Sai2ClockSelection; /*!< Specifies SAI2 Clock Source Selection.
lypinator	0:bb348c97df44	162	This parameter can be a value of @ref RCCEx_SAI2_Clock_Source */
lypinator	0:bb348c97df44	163
lypinator	0:bb348c97df44	164	uint32_t I2sApb1ClockSelection; /*!< Specifies I2S APB1 Clock Source Selection.
lypinator	0:bb348c97df44	165	This parameter can be a value of @ref RCCEx_I2SAPB1_Clock_Source */
lypinator	0:bb348c97df44	166
lypinator	0:bb348c97df44	167	uint32_t I2sApb2ClockSelection; /*!< Specifies I2S APB2 Clock Source Selection.
lypinator	0:bb348c97df44	168	This parameter can be a value of @ref RCCEx_I2SAPB2_Clock_Source */
lypinator	0:bb348c97df44	169
lypinator	0:bb348c97df44	170	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Source Selection.
lypinator	0:bb348c97df44	171	This parameter can be a value of @ref RCC_RTC_Clock_Source */
lypinator	0:bb348c97df44	172
lypinator	0:bb348c97df44	173	uint32_t SdioClockSelection; /*!< Specifies SDIO Clock Source Selection.
lypinator	0:bb348c97df44	174	This parameter can be a value of @ref RCCEx_SDIO_Clock_Source */
lypinator	0:bb348c97df44	175
lypinator	0:bb348c97df44	176	uint32_t CecClockSelection; /*!< Specifies CEC Clock Source Selection.
lypinator	0:bb348c97df44	177	This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
lypinator	0:bb348c97df44	178
lypinator	0:bb348c97df44	179	uint32_t Fmpi2c1ClockSelection; /*!< Specifies FMPI2C1 Clock Source Selection.
lypinator	0:bb348c97df44	180	This parameter can be a value of @ref RCCEx_FMPI2C1_Clock_Source */
lypinator	0:bb348c97df44	181
lypinator	0:bb348c97df44	182	uint32_t SpdifClockSelection; /*!< Specifies SPDIFRX Clock Source Selection.
lypinator	0:bb348c97df44	183	This parameter can be a value of @ref RCCEx_SPDIFRX_Clock_Source */
lypinator	0:bb348c97df44	184
lypinator	0:bb348c97df44	185	uint32_t Clk48ClockSelection; /*!< Specifies CLK48 Clock Selection this clock used OTG FS, SDIO and RNG clocks.
lypinator	0:bb348c97df44	186	This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */
lypinator	0:bb348c97df44	187
lypinator	0:bb348c97df44	188	uint8_t TIMPresSelection; /*!< Specifies TIM Clock Source Selection.
lypinator	0:bb348c97df44	189	This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
lypinator	0:bb348c97df44	190	}RCC_PeriphCLKInitTypeDef;
lypinator	0:bb348c97df44	191	#endif /* STM32F446xx */
lypinator	0:bb348c97df44	192
lypinator	0:bb348c97df44	193	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
lypinator	0:bb348c97df44	194	/**
lypinator	0:bb348c97df44	195	* @brief RCC extended clocks structure definition
lypinator	0:bb348c97df44	196	*/
lypinator	0:bb348c97df44	197	typedef struct
lypinator	0:bb348c97df44	198	{
lypinator	0:bb348c97df44	199	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
lypinator	0:bb348c97df44	200	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
lypinator	0:bb348c97df44	201
lypinator	0:bb348c97df44	202	uint32_t I2SClockSelection; /*!< Specifies RTC Clock Source Selection.
lypinator	0:bb348c97df44	203	This parameter can be a value of @ref RCCEx_I2S_APB_Clock_Source */
lypinator	0:bb348c97df44	204
lypinator	0:bb348c97df44	205	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Source Selection.
lypinator	0:bb348c97df44	206	This parameter can be a value of @ref RCC_RTC_Clock_Source */
lypinator	0:bb348c97df44	207
lypinator	0:bb348c97df44	208	uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 Clock Source Selection.
lypinator	0:bb348c97df44	209	This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */
lypinator	0:bb348c97df44	210
lypinator	0:bb348c97df44	211	uint32_t Fmpi2c1ClockSelection; /*!< Specifies FMPI2C1 Clock Source Selection.
lypinator	0:bb348c97df44	212	This parameter can be a value of @ref RCCEx_FMPI2C1_Clock_Source */
lypinator	0:bb348c97df44	213
lypinator	0:bb348c97df44	214	uint8_t TIMPresSelection; /*!< Specifies TIM Clock Source Selection.
lypinator	0:bb348c97df44	215	This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
lypinator	0:bb348c97df44	216	}RCC_PeriphCLKInitTypeDef;
lypinator	0:bb348c97df44	217	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
lypinator	0:bb348c97df44	218
lypinator	0:bb348c97df44	219	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
lypinator	0:bb348c97df44	220	/**
lypinator	0:bb348c97df44	221	* @brief PLLI2S Clock structure definition
lypinator	0:bb348c97df44	222	*/
lypinator	0:bb348c97df44	223	typedef struct
lypinator	0:bb348c97df44	224	{
lypinator	0:bb348c97df44	225	uint32_t PLLI2SM; /*!< Specifies division factor for PLL VCO input clock.
lypinator	0:bb348c97df44	226	This parameter must be a number between Min_Data = 2 and Max_Data = 63 */
lypinator	0:bb348c97df44	227
lypinator	0:bb348c97df44	228	uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
lypinator	0:bb348c97df44	229	This parameter must be a number between Min_Data = 50 and Max_Data = 432 */
lypinator	0:bb348c97df44	230
lypinator	0:bb348c97df44	231	uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI clock.
lypinator	0:bb348c97df44	232	This parameter must be a number between Min_Data = 2 and Max_Data = 15.
lypinator	0:bb348c97df44	233	This parameter will be used only when PLLI2S is selected as Clock Source SAI */
lypinator	0:bb348c97df44	234
lypinator	0:bb348c97df44	235	uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock.
lypinator	0:bb348c97df44	236	This parameter must be a number between Min_Data = 2 and Max_Data = 7.
lypinator	0:bb348c97df44	237	This parameter will be used only when PLLI2S is selected as Clock Source I2S */
lypinator	0:bb348c97df44	238	}RCC_PLLI2SInitTypeDef;
lypinator	0:bb348c97df44	239
lypinator	0:bb348c97df44	240	/**
lypinator	0:bb348c97df44	241	* @brief RCC extended clocks structure definition
lypinator	0:bb348c97df44	242	*/
lypinator	0:bb348c97df44	243	typedef struct
lypinator	0:bb348c97df44	244	{
lypinator	0:bb348c97df44	245	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
lypinator	0:bb348c97df44	246	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
lypinator	0:bb348c97df44	247
lypinator	0:bb348c97df44	248	RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters.
lypinator	0:bb348c97df44	249	This parameter will be used only when PLLI2S is selected as Clock Source I2S */
lypinator	0:bb348c97df44	250
lypinator	0:bb348c97df44	251	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
lypinator	0:bb348c97df44	252	uint32_t PLLDivR; /*!< Specifies the PLL division factor for SAI1 clock.
lypinator	0:bb348c97df44	253	This parameter must be a number between Min_Data = 1 and Max_Data = 32
lypinator	0:bb348c97df44	254	This parameter will be used only when PLL is selected as Clock Source SAI */
lypinator	0:bb348c97df44	255
lypinator	0:bb348c97df44	256	uint32_t PLLI2SDivR; /*!< Specifies the PLLI2S division factor for SAI1 clock.
lypinator	0:bb348c97df44	257	This parameter must be a number between Min_Data = 1 and Max_Data = 32
lypinator	0:bb348c97df44	258	This parameter will be used only when PLLI2S is selected as Clock Source SAI */
lypinator	0:bb348c97df44	259	#endif /* STM32F413xx \|\| STM32F423xx */
lypinator	0:bb348c97df44	260
lypinator	0:bb348c97df44	261	uint32_t I2sApb1ClockSelection; /*!< Specifies I2S APB1 Clock Source Selection.
lypinator	0:bb348c97df44	262	This parameter can be a value of @ref RCCEx_I2SAPB1_Clock_Source */
lypinator	0:bb348c97df44	263
lypinator	0:bb348c97df44	264	uint32_t I2sApb2ClockSelection; /*!< Specifies I2S APB2 Clock Source Selection.
lypinator	0:bb348c97df44	265	This parameter can be a value of @ref RCCEx_I2SAPB2_Clock_Source */
lypinator	0:bb348c97df44	266
lypinator	0:bb348c97df44	267	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Source Selection.
lypinator	0:bb348c97df44	268	This parameter can be a value of @ref RCC_RTC_Clock_Source */
lypinator	0:bb348c97df44	269
lypinator	0:bb348c97df44	270	uint32_t SdioClockSelection; /*!< Specifies SDIO Clock Source Selection.
lypinator	0:bb348c97df44	271	This parameter can be a value of @ref RCCEx_SDIO_Clock_Source */
lypinator	0:bb348c97df44	272
lypinator	0:bb348c97df44	273	uint32_t Fmpi2c1ClockSelection; /*!< Specifies FMPI2C1 Clock Source Selection.
lypinator	0:bb348c97df44	274	This parameter can be a value of @ref RCCEx_FMPI2C1_Clock_Source */
lypinator	0:bb348c97df44	275
lypinator	0:bb348c97df44	276	uint32_t Clk48ClockSelection; /*!< Specifies CLK48 Clock Selection this clock used OTG FS, SDIO and RNG clocks.
lypinator	0:bb348c97df44	277	This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */
lypinator	0:bb348c97df44	278
lypinator	0:bb348c97df44	279	uint32_t Dfsdm1ClockSelection; /*!< Specifies DFSDM1 Clock Selection.
lypinator	0:bb348c97df44	280	This parameter can be a value of @ref RCCEx_DFSDM1_Kernel_Clock_Source */
lypinator	0:bb348c97df44	281
lypinator	0:bb348c97df44	282	uint32_t Dfsdm1AudioClockSelection;/*!< Specifies DFSDM1 Audio Clock Selection.
lypinator	0:bb348c97df44	283	This parameter can be a value of @ref RCCEx_DFSDM1_Audio_Clock_Source */
lypinator	0:bb348c97df44	284
lypinator	0:bb348c97df44	285	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
lypinator	0:bb348c97df44	286	uint32_t Dfsdm2ClockSelection; /*!< Specifies DFSDM2 Clock Selection.
lypinator	0:bb348c97df44	287	This parameter can be a value of @ref RCCEx_DFSDM2_Kernel_Clock_Source */
lypinator	0:bb348c97df44	288
lypinator	0:bb348c97df44	289	uint32_t Dfsdm2AudioClockSelection;/*!< Specifies DFSDM2 Audio Clock Selection.
lypinator	0:bb348c97df44	290	This parameter can be a value of @ref RCCEx_DFSDM2_Audio_Clock_Source */
lypinator	0:bb348c97df44	291
lypinator	0:bb348c97df44	292	uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 Clock Source Selection.
lypinator	0:bb348c97df44	293	This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */
lypinator	0:bb348c97df44	294
lypinator	0:bb348c97df44	295	uint32_t SaiAClockSelection; /*!< Specifies SAI1_A Clock Prescalers Selection
lypinator	0:bb348c97df44	296	This parameter can be a value of @ref RCCEx_SAI1_BlockA_Clock_Source */
lypinator	0:bb348c97df44	297
lypinator	0:bb348c97df44	298	uint32_t SaiBClockSelection; /*!< Specifies SAI1_B Clock Prescalers Selection
lypinator	0:bb348c97df44	299	This parameter can be a value of @ref RCCEx_SAI1_BlockB_Clock_Source */
lypinator	0:bb348c97df44	300	#endif /* STM32F413xx \|\| STM32F423xx */
lypinator	0:bb348c97df44	301
lypinator	0:bb348c97df44	302	uint32_t PLLI2SSelection; /*!< Specifies PLL I2S Clock Source Selection.
lypinator	0:bb348c97df44	303	This parameter can be a value of @ref RCCEx_PLL_I2S_Clock_Source */
lypinator	0:bb348c97df44	304
lypinator	0:bb348c97df44	305	uint8_t TIMPresSelection; /*!< Specifies TIM Clock Source Selection.
lypinator	0:bb348c97df44	306	This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
lypinator	0:bb348c97df44	307	}RCC_PeriphCLKInitTypeDef;
lypinator	0:bb348c97df44	308	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx \|\| STM32F413xx \|\| STM32F423xx */
lypinator	0:bb348c97df44	309
lypinator	0:bb348c97df44	310	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
lypinator	0:bb348c97df44	311
lypinator	0:bb348c97df44	312	/**
lypinator	0:bb348c97df44	313	* @brief PLLI2S Clock structure definition
lypinator	0:bb348c97df44	314	*/
lypinator	0:bb348c97df44	315	typedef struct
lypinator	0:bb348c97df44	316	{
lypinator	0:bb348c97df44	317	uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
lypinator	0:bb348c97df44	318	This parameter must be a number between Min_Data = 50 and Max_Data = 432.
lypinator	0:bb348c97df44	319	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
lypinator	0:bb348c97df44	320
lypinator	0:bb348c97df44	321	uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock.
lypinator	0:bb348c97df44	322	This parameter must be a number between Min_Data = 2 and Max_Data = 7.
lypinator	0:bb348c97df44	323	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
lypinator	0:bb348c97df44	324
lypinator	0:bb348c97df44	325	uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI1 clock.
lypinator	0:bb348c97df44	326	This parameter must be a number between Min_Data = 2 and Max_Data = 15.
lypinator	0:bb348c97df44	327	This parameter will be used only when PLLI2S is selected as Clock Source SAI */
lypinator	0:bb348c97df44	328	}RCC_PLLI2SInitTypeDef;
lypinator	0:bb348c97df44	329
lypinator	0:bb348c97df44	330	/**
lypinator	0:bb348c97df44	331	* @brief PLLSAI Clock structure definition
lypinator	0:bb348c97df44	332	*/
lypinator	0:bb348c97df44	333	typedef struct
lypinator	0:bb348c97df44	334	{
lypinator	0:bb348c97df44	335	uint32_t PLLSAIN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
lypinator	0:bb348c97df44	336	This parameter must be a number between Min_Data = 50 and Max_Data = 432.
lypinator	0:bb348c97df44	337	This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */
lypinator	0:bb348c97df44	338	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
lypinator	0:bb348c97df44	339	uint32_t PLLSAIP; /*!< Specifies division factor for OTG FS and SDIO clocks.
lypinator	0:bb348c97df44	340	This parameter is only available in STM32F469xx/STM32F479xx devices.
lypinator	0:bb348c97df44	341	This parameter must be a value of @ref RCCEx_PLLSAIP_Clock_Divider */
lypinator	0:bb348c97df44	342	#endif /* STM32F469xx \|\| STM32F479xx */
lypinator	0:bb348c97df44	343
lypinator	0:bb348c97df44	344	uint32_t PLLSAIQ; /*!< Specifies the division factor for SAI1 clock.
lypinator	0:bb348c97df44	345	This parameter must be a number between Min_Data = 2 and Max_Data = 15.
lypinator	0:bb348c97df44	346	This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */
lypinator	0:bb348c97df44	347
lypinator	0:bb348c97df44	348	uint32_t PLLSAIR; /*!< specifies the division factor for LTDC clock
lypinator	0:bb348c97df44	349	This parameter must be a number between Min_Data = 2 and Max_Data = 7.
lypinator	0:bb348c97df44	350	This parameter will be used only when PLLSAI is selected as Clock Source LTDC */
lypinator	0:bb348c97df44	351
lypinator	0:bb348c97df44	352	}RCC_PLLSAIInitTypeDef;
lypinator	0:bb348c97df44	353
lypinator	0:bb348c97df44	354	/**
lypinator	0:bb348c97df44	355	* @brief RCC extended clocks structure definition
lypinator	0:bb348c97df44	356	*/
lypinator	0:bb348c97df44	357	typedef struct
lypinator	0:bb348c97df44	358	{
lypinator	0:bb348c97df44	359	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
lypinator	0:bb348c97df44	360	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
lypinator	0:bb348c97df44	361
lypinator	0:bb348c97df44	362	RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters.
lypinator	0:bb348c97df44	363	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
lypinator	0:bb348c97df44	364
lypinator	0:bb348c97df44	365	RCC_PLLSAIInitTypeDef PLLSAI; /*!< PLL SAI structure parameters.
lypinator	0:bb348c97df44	366	This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */
lypinator	0:bb348c97df44	367
lypinator	0:bb348c97df44	368	uint32_t PLLI2SDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
lypinator	0:bb348c97df44	369	This parameter must be a number between Min_Data = 1 and Max_Data = 32
lypinator	0:bb348c97df44	370	This parameter will be used only when PLLI2S is selected as Clock Source SAI */
lypinator	0:bb348c97df44	371
lypinator	0:bb348c97df44	372	uint32_t PLLSAIDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
lypinator	0:bb348c97df44	373	This parameter must be a number between Min_Data = 1 and Max_Data = 32
lypinator	0:bb348c97df44	374	This parameter will be used only when PLLSAI is selected as Clock Source SAI */
lypinator	0:bb348c97df44	375
lypinator	0:bb348c97df44	376	uint32_t PLLSAIDivR; /*!< Specifies the PLLSAI division factor for LTDC clock.
lypinator	0:bb348c97df44	377	This parameter must be one value of @ref RCCEx_PLLSAI_DIVR */
lypinator	0:bb348c97df44	378
lypinator	0:bb348c97df44	379	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection.
lypinator	0:bb348c97df44	380	This parameter can be a value of @ref RCC_RTC_Clock_Source */
lypinator	0:bb348c97df44	381
lypinator	0:bb348c97df44	382	uint8_t TIMPresSelection; /*!< Specifies TIM Clock Prescalers Selection.
lypinator	0:bb348c97df44	383	This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
lypinator	0:bb348c97df44	384	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
lypinator	0:bb348c97df44	385	uint32_t Clk48ClockSelection; /*!< Specifies CLK48 Clock Selection this clock used OTG FS, SDIO and RNG clocks.
lypinator	0:bb348c97df44	386	This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */
lypinator	0:bb348c97df44	387
lypinator	0:bb348c97df44	388	uint32_t SdioClockSelection; /*!< Specifies SDIO Clock Source Selection.
lypinator	0:bb348c97df44	389	This parameter can be a value of @ref RCCEx_SDIO_Clock_Source */
lypinator	0:bb348c97df44	390	#endif /* STM32F469xx \|\| STM32F479xx */
lypinator	0:bb348c97df44	391	}RCC_PeriphCLKInitTypeDef;
lypinator	0:bb348c97df44	392
lypinator	0:bb348c97df44	393	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
lypinator	0:bb348c97df44	394
lypinator	0:bb348c97df44	395	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\|\
lypinator	0:bb348c97df44	396	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE)
lypinator	0:bb348c97df44	397	/**
lypinator	0:bb348c97df44	398	* @brief PLLI2S Clock structure definition
lypinator	0:bb348c97df44	399	*/
lypinator	0:bb348c97df44	400	typedef struct
lypinator	0:bb348c97df44	401	{
lypinator	0:bb348c97df44	402	#if defined(STM32F411xE)
lypinator	0:bb348c97df44	403	uint32_t PLLI2SM; /*!< PLLM: Division factor for PLLI2S VCO input clock.
lypinator	0:bb348c97df44	404	This parameter must be a number between Min_Data = 2 and Max_Data = 62 */
lypinator	0:bb348c97df44	405	#endif /* STM32F411xE */
lypinator	0:bb348c97df44	406
lypinator	0:bb348c97df44	407	uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
lypinator	0:bb348c97df44	408	This parameter must be a number between Min_Data = 50 and Max_Data = 432
lypinator	0:bb348c97df44	409	Except for STM32F411xE devices where the Min_Data = 192.
lypinator	0:bb348c97df44	410	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
lypinator	0:bb348c97df44	411
lypinator	0:bb348c97df44	412	uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock.
lypinator	0:bb348c97df44	413	This parameter must be a number between Min_Data = 2 and Max_Data = 7.
lypinator	0:bb348c97df44	414	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
lypinator	0:bb348c97df44	415
lypinator	0:bb348c97df44	416	}RCC_PLLI2SInitTypeDef;
lypinator	0:bb348c97df44	417
lypinator	0:bb348c97df44	418	/**
lypinator	0:bb348c97df44	419	* @brief RCC extended clocks structure definition
lypinator	0:bb348c97df44	420	*/
lypinator	0:bb348c97df44	421	typedef struct
lypinator	0:bb348c97df44	422	{
lypinator	0:bb348c97df44	423	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
lypinator	0:bb348c97df44	424	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
lypinator	0:bb348c97df44	425
lypinator	0:bb348c97df44	426	RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters.
lypinator	0:bb348c97df44	427	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
lypinator	0:bb348c97df44	428
lypinator	0:bb348c97df44	429	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection.
lypinator	0:bb348c97df44	430	This parameter can be a value of @ref RCC_RTC_Clock_Source */
lypinator	0:bb348c97df44	431	#if defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE)
lypinator	0:bb348c97df44	432	uint8_t TIMPresSelection; /*!< Specifies TIM Clock Source Selection.
lypinator	0:bb348c97df44	433	This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
lypinator	0:bb348c97df44	434	#endif /* STM32F401xC \|\| STM32F401xE \|\| STM32F411xE */
lypinator	0:bb348c97df44	435	}RCC_PeriphCLKInitTypeDef;
lypinator	0:bb348c97df44	436	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F401xC \|\| STM32F401xE \|\| STM32F411xE */
lypinator	0:bb348c97df44	437	/**
lypinator	0:bb348c97df44	438	* @}
lypinator	0:bb348c97df44	439	*/
lypinator	0:bb348c97df44	440
lypinator	0:bb348c97df44	441	/* Exported constants --------------------------------------------------------*/
lypinator	0:bb348c97df44	442	/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
lypinator	0:bb348c97df44	443	* @{
lypinator	0:bb348c97df44	444	*/
lypinator	0:bb348c97df44	445
lypinator	0:bb348c97df44	446	/** @defgroup RCCEx_Periph_Clock_Selection RCC Periph Clock Selection
lypinator	0:bb348c97df44	447	* @{
lypinator	0:bb348c97df44	448	*/
lypinator	0:bb348c97df44	449	/* Peripheral Clock source for STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx */
lypinator	0:bb348c97df44	450	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx) \|\|\
lypinator	0:bb348c97df44	451	defined(STM32F413xx) \|\| defined(STM32F423xx)
lypinator	0:bb348c97df44	452	#define RCC_PERIPHCLK_I2S_APB1 0x00000001U
lypinator	0:bb348c97df44	453	#define RCC_PERIPHCLK_I2S_APB2 0x00000002U
lypinator	0:bb348c97df44	454	#define RCC_PERIPHCLK_TIM 0x00000004U
lypinator	0:bb348c97df44	455	#define RCC_PERIPHCLK_RTC 0x00000008U
lypinator	0:bb348c97df44	456	#define RCC_PERIPHCLK_FMPI2C1 0x00000010U
lypinator	0:bb348c97df44	457	#define RCC_PERIPHCLK_CLK48 0x00000020U
lypinator	0:bb348c97df44	458	#define RCC_PERIPHCLK_SDIO 0x00000040U
lypinator	0:bb348c97df44	459	#define RCC_PERIPHCLK_PLLI2S 0x00000080U
lypinator	0:bb348c97df44	460	#define RCC_PERIPHCLK_DFSDM1 0x00000100U
lypinator	0:bb348c97df44	461	#define RCC_PERIPHCLK_DFSDM1_AUDIO 0x00000200U
lypinator	0:bb348c97df44	462	#endif /* STM32F412Zx \|\| STM32F412Vx) \|\| STM32F412Rx \|\| STM32F412Cx */
lypinator	0:bb348c97df44	463	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
lypinator	0:bb348c97df44	464	#define RCC_PERIPHCLK_DFSDM2 0x00000400U
lypinator	0:bb348c97df44	465	#define RCC_PERIPHCLK_DFSDM2_AUDIO 0x00000800U
lypinator	0:bb348c97df44	466	#define RCC_PERIPHCLK_LPTIM1 0x00001000U
lypinator	0:bb348c97df44	467	#define RCC_PERIPHCLK_SAIA 0x00002000U
lypinator	0:bb348c97df44	468	#define RCC_PERIPHCLK_SAIB 0x00004000U
lypinator	0:bb348c97df44	469	#endif /* STM32F413xx \|\| STM32F423xx */
lypinator	0:bb348c97df44	470	/----------------------------------------------------------------------------/
lypinator	0:bb348c97df44	471
lypinator	0:bb348c97df44	472	/------------------- Peripheral Clock source for STM32F410xx ----------------/
lypinator	0:bb348c97df44	473	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
lypinator	0:bb348c97df44	474	#define RCC_PERIPHCLK_I2S 0x00000001U
lypinator	0:bb348c97df44	475	#define RCC_PERIPHCLK_TIM 0x00000002U
lypinator	0:bb348c97df44	476	#define RCC_PERIPHCLK_RTC 0x00000004U
lypinator	0:bb348c97df44	477	#define RCC_PERIPHCLK_FMPI2C1 0x00000008U
lypinator	0:bb348c97df44	478	#define RCC_PERIPHCLK_LPTIM1 0x00000010U
lypinator	0:bb348c97df44	479	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
lypinator	0:bb348c97df44	480	/----------------------------------------------------------------------------/
lypinator	0:bb348c97df44	481
lypinator	0:bb348c97df44	482	/------------------- Peripheral Clock source for STM32F446xx ----------------/
lypinator	0:bb348c97df44	483	#if defined(STM32F446xx)
lypinator	0:bb348c97df44	484	#define RCC_PERIPHCLK_I2S_APB1 0x00000001U
lypinator	0:bb348c97df44	485	#define RCC_PERIPHCLK_I2S_APB2 0x00000002U
lypinator	0:bb348c97df44	486	#define RCC_PERIPHCLK_SAI1 0x00000004U
lypinator	0:bb348c97df44	487	#define RCC_PERIPHCLK_SAI2 0x00000008U
lypinator	0:bb348c97df44	488	#define RCC_PERIPHCLK_TIM 0x00000010U
lypinator	0:bb348c97df44	489	#define RCC_PERIPHCLK_RTC 0x00000020U
lypinator	0:bb348c97df44	490	#define RCC_PERIPHCLK_CEC 0x00000040U
lypinator	0:bb348c97df44	491	#define RCC_PERIPHCLK_FMPI2C1 0x00000080U
lypinator	0:bb348c97df44	492	#define RCC_PERIPHCLK_CLK48 0x00000100U
lypinator	0:bb348c97df44	493	#define RCC_PERIPHCLK_SDIO 0x00000200U
lypinator	0:bb348c97df44	494	#define RCC_PERIPHCLK_SPDIFRX 0x00000400U
lypinator	0:bb348c97df44	495	#define RCC_PERIPHCLK_PLLI2S 0x00000800U
lypinator	0:bb348c97df44	496	#endif /* STM32F446xx */
lypinator	0:bb348c97df44	497	/-----------------------------------------------------------------------------/
lypinator	0:bb348c97df44	498
lypinator	0:bb348c97df44	499	/----------- Peripheral Clock source for STM32F469xx/STM32F479xx -------------/
lypinator	0:bb348c97df44	500	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
lypinator	0:bb348c97df44	501	#define RCC_PERIPHCLK_I2S 0x00000001U
lypinator	0:bb348c97df44	502	#define RCC_PERIPHCLK_SAI_PLLI2S 0x00000002U
lypinator	0:bb348c97df44	503	#define RCC_PERIPHCLK_SAI_PLLSAI 0x00000004U
lypinator	0:bb348c97df44	504	#define RCC_PERIPHCLK_LTDC 0x00000008U
lypinator	0:bb348c97df44	505	#define RCC_PERIPHCLK_TIM 0x00000010U
lypinator	0:bb348c97df44	506	#define RCC_PERIPHCLK_RTC 0x00000020U
lypinator	0:bb348c97df44	507	#define RCC_PERIPHCLK_PLLI2S 0x00000040U
lypinator	0:bb348c97df44	508	#define RCC_PERIPHCLK_CLK48 0x00000080U
lypinator	0:bb348c97df44	509	#define RCC_PERIPHCLK_SDIO 0x00000100U
lypinator	0:bb348c97df44	510	#endif /* STM32F469xx \|\| STM32F479xx */
lypinator	0:bb348c97df44	511	/----------------------------------------------------------------------------/
lypinator	0:bb348c97df44	512
lypinator	0:bb348c97df44	513	/-------- Peripheral Clock source for STM32F42xxx/STM32F43xxx ---------------/
lypinator	0:bb348c97df44	514	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
lypinator	0:bb348c97df44	515	#define RCC_PERIPHCLK_I2S 0x00000001U
lypinator	0:bb348c97df44	516	#define RCC_PERIPHCLK_SAI_PLLI2S 0x00000002U
lypinator	0:bb348c97df44	517	#define RCC_PERIPHCLK_SAI_PLLSAI 0x00000004U
lypinator	0:bb348c97df44	518	#define RCC_PERIPHCLK_LTDC 0x00000008U
lypinator	0:bb348c97df44	519	#define RCC_PERIPHCLK_TIM 0x00000010U
lypinator	0:bb348c97df44	520	#define RCC_PERIPHCLK_RTC 0x00000020U
lypinator	0:bb348c97df44	521	#define RCC_PERIPHCLK_PLLI2S 0x00000040U
lypinator	0:bb348c97df44	522	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
lypinator	0:bb348c97df44	523	/----------------------------------------------------------------------------/
lypinator	0:bb348c97df44	524
lypinator	0:bb348c97df44	525	/-------- Peripheral Clock source for STM32F40xxx/STM32F41xxx ---------------/
lypinator	0:bb348c97df44	526	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx)\|\| defined(STM32F417xx) \|\|\
lypinator	0:bb348c97df44	527	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE)
lypinator	0:bb348c97df44	528	#define RCC_PERIPHCLK_I2S 0x00000001U
lypinator	0:bb348c97df44	529	#define RCC_PERIPHCLK_RTC 0x00000002U
lypinator	0:bb348c97df44	530	#define RCC_PERIPHCLK_PLLI2S 0x00000004U
lypinator	0:bb348c97df44	531	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F401xC \|\| STM32F401xE \|\| STM32F411xE */
lypinator	0:bb348c97df44	532	#if defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE)
lypinator	0:bb348c97df44	533	#define RCC_PERIPHCLK_TIM 0x00000008U
lypinator	0:bb348c97df44	534	#endif /* STM32F401xC \|\| STM32F401xE \|\| STM32F411xE */
lypinator	0:bb348c97df44	535	/----------------------------------------------------------------------------/
lypinator	0:bb348c97df44	536	/**
lypinator	0:bb348c97df44	537	* @}
lypinator	0:bb348c97df44	538	*/
lypinator	0:bb348c97df44	539	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\| \
lypinator	0:bb348c97df44	540	defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| \
lypinator	0:bb348c97df44	541	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE) \|\| defined(STM32F469xx) \|\| \
lypinator	0:bb348c97df44	542	defined(STM32F479xx)
lypinator	0:bb348c97df44	543	/** @defgroup RCCEx_I2S_Clock_Source I2S Clock Source
lypinator	0:bb348c97df44	544	* @{
lypinator	0:bb348c97df44	545	*/
lypinator	0:bb348c97df44	546	#define RCC_I2SCLKSOURCE_PLLI2S 0x00000000U
lypinator	0:bb348c97df44	547	#define RCC_I2SCLKSOURCE_EXT 0x00000001U
lypinator	0:bb348c97df44	548	/**
lypinator	0:bb348c97df44	549	* @}
lypinator	0:bb348c97df44	550	*/
lypinator	0:bb348c97df44	551	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\|
lypinator	0:bb348c97df44	552	STM32F401xC \|\| STM32F401xE \|\| STM32F411xE \|\| STM32F469xx \|\| STM32F479xx */
lypinator	0:bb348c97df44	553
lypinator	0:bb348c97df44	554	/** @defgroup RCCEx_PLLSAI_DIVR RCC PLLSAI DIVR
lypinator	0:bb348c97df44	555	* @{
lypinator	0:bb348c97df44	556	*/
lypinator	0:bb348c97df44	557	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F446xx) \|\|\
lypinator	0:bb348c97df44	558	defined(STM32F469xx) \|\| defined(STM32F479xx)
lypinator	0:bb348c97df44	559	#define RCC_PLLSAIDIVR_2 0x00000000U
lypinator	0:bb348c97df44	560	#define RCC_PLLSAIDIVR_4 0x00010000U
lypinator	0:bb348c97df44	561	#define RCC_PLLSAIDIVR_8 0x00020000U
lypinator	0:bb348c97df44	562	#define RCC_PLLSAIDIVR_16 0x00030000U
lypinator	0:bb348c97df44	563	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
lypinator	0:bb348c97df44	564	/**
lypinator	0:bb348c97df44	565	* @}
lypinator	0:bb348c97df44	566	*/
lypinator	0:bb348c97df44	567
lypinator	0:bb348c97df44	568	/** @defgroup RCCEx_PLLI2SP_Clock_Divider RCC PLLI2SP Clock Divider
lypinator	0:bb348c97df44	569	* @{
lypinator	0:bb348c97df44	570	*/
lypinator	0:bb348c97df44	571	#if defined(STM32F446xx) \|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| \
lypinator	0:bb348c97df44	572	defined(STM32F412Rx) \|\| defined(STM32F412Cx)
lypinator	0:bb348c97df44	573	#define RCC_PLLI2SP_DIV2 0x00000002U
lypinator	0:bb348c97df44	574	#define RCC_PLLI2SP_DIV4 0x00000004U
lypinator	0:bb348c97df44	575	#define RCC_PLLI2SP_DIV6 0x00000006U
lypinator	0:bb348c97df44	576	#define RCC_PLLI2SP_DIV8 0x00000008U
lypinator	0:bb348c97df44	577	#endif /* STM32F446xx \|\| STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx */
lypinator	0:bb348c97df44	578	/**
lypinator	0:bb348c97df44	579	* @}
lypinator	0:bb348c97df44	580	*/
lypinator	0:bb348c97df44	581
lypinator	0:bb348c97df44	582	/** @defgroup RCCEx_PLLSAIP_Clock_Divider RCC PLLSAIP Clock Divider
lypinator	0:bb348c97df44	583	* @{
lypinator	0:bb348c97df44	584	*/
lypinator	0:bb348c97df44	585	#if defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
lypinator	0:bb348c97df44	586	#define RCC_PLLSAIP_DIV2 0x00000002U
lypinator	0:bb348c97df44	587	#define RCC_PLLSAIP_DIV4 0x00000004U
lypinator	0:bb348c97df44	588	#define RCC_PLLSAIP_DIV6 0x00000006U
lypinator	0:bb348c97df44	589	#define RCC_PLLSAIP_DIV8 0x00000008U
lypinator	0:bb348c97df44	590	#endif /* STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
lypinator	0:bb348c97df44	591	/**
lypinator	0:bb348c97df44	592	* @}
lypinator	0:bb348c97df44	593	*/
lypinator	0:bb348c97df44	594
lypinator	0:bb348c97df44	595	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
lypinator	0:bb348c97df44	596	/** @defgroup RCCEx_SAI_BlockA_Clock_Source RCC SAI BlockA Clock Source
lypinator	0:bb348c97df44	597	* @{
lypinator	0:bb348c97df44	598	*/
lypinator	0:bb348c97df44	599	#define RCC_SAIACLKSOURCE_PLLSAI 0x00000000U
lypinator	0:bb348c97df44	600	#define RCC_SAIACLKSOURCE_PLLI2S 0x00100000U
lypinator	0:bb348c97df44	601	#define RCC_SAIACLKSOURCE_EXT 0x00200000U
lypinator	0:bb348c97df44	602	/**
lypinator	0:bb348c97df44	603	* @}
lypinator	0:bb348c97df44	604	*/
lypinator	0:bb348c97df44	605
lypinator	0:bb348c97df44	606	/** @defgroup RCCEx_SAI_BlockB_Clock_Source RCC SAI BlockB Clock Source
lypinator	0:bb348c97df44	607	* @{
lypinator	0:bb348c97df44	608	*/
lypinator	0:bb348c97df44	609	#define RCC_SAIBCLKSOURCE_PLLSAI 0x00000000U
lypinator	0:bb348c97df44	610	#define RCC_SAIBCLKSOURCE_PLLI2S 0x00400000U
lypinator	0:bb348c97df44	611	#define RCC_SAIBCLKSOURCE_EXT 0x00800000U
lypinator	0:bb348c97df44	612	/**
lypinator	0:bb348c97df44	613	* @}
lypinator	0:bb348c97df44	614	*/
lypinator	0:bb348c97df44	615	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
lypinator	0:bb348c97df44	616
lypinator	0:bb348c97df44	617	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
lypinator	0:bb348c97df44	618	/** @defgroup RCCEx_CLK48_Clock_Source RCC CLK48 Clock Source
lypinator	0:bb348c97df44	619	* @{
lypinator	0:bb348c97df44	620	*/
lypinator	0:bb348c97df44	621	#define RCC_CLK48CLKSOURCE_PLLQ 0x00000000U
lypinator	0:bb348c97df44	622	#define RCC_CLK48CLKSOURCE_PLLSAIP ((uint32_t)RCC_DCKCFGR_CK48MSEL)
lypinator	0:bb348c97df44	623	/**
lypinator	0:bb348c97df44	624	* @}
lypinator	0:bb348c97df44	625	*/
lypinator	0:bb348c97df44	626
lypinator	0:bb348c97df44	627	/** @defgroup RCCEx_SDIO_Clock_Source RCC SDIO Clock Source
lypinator	0:bb348c97df44	628	* @{
lypinator	0:bb348c97df44	629	*/
lypinator	0:bb348c97df44	630	#define RCC_SDIOCLKSOURCE_CLK48 0x00000000U
lypinator	0:bb348c97df44	631	#define RCC_SDIOCLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR_SDIOSEL)
lypinator	0:bb348c97df44	632	/**
lypinator	0:bb348c97df44	633	* @}
lypinator	0:bb348c97df44	634	*/
lypinator	0:bb348c97df44	635
lypinator	0:bb348c97df44	636	/** @defgroup RCCEx_DSI_Clock_Source RCC DSI Clock Source
lypinator	0:bb348c97df44	637	* @{
lypinator	0:bb348c97df44	638	*/
lypinator	0:bb348c97df44	639	#define RCC_DSICLKSOURCE_DSIPHY 0x00000000U
lypinator	0:bb348c97df44	640	#define RCC_DSICLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_DSISEL)
lypinator	0:bb348c97df44	641	/**
lypinator	0:bb348c97df44	642	* @}
lypinator	0:bb348c97df44	643	*/
lypinator	0:bb348c97df44	644	#endif /* STM32F469xx \|\| STM32F479xx */
lypinator	0:bb348c97df44	645
lypinator	0:bb348c97df44	646	#if defined(STM32F446xx)
lypinator	0:bb348c97df44	647	/** @defgroup RCCEx_SAI1_Clock_Source RCC SAI1 Clock Source
lypinator	0:bb348c97df44	648	* @{
lypinator	0:bb348c97df44	649	*/
lypinator	0:bb348c97df44	650	#define RCC_SAI1CLKSOURCE_PLLSAI 0x00000000U
lypinator	0:bb348c97df44	651	#define RCC_SAI1CLKSOURCE_PLLI2S ((uint32_t)RCC_DCKCFGR_SAI1SRC_0)
lypinator	0:bb348c97df44	652	#define RCC_SAI1CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_SAI1SRC_1)
lypinator	0:bb348c97df44	653	#define RCC_SAI1CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_SAI1SRC)
lypinator	0:bb348c97df44	654	/**
lypinator	0:bb348c97df44	655	* @}
lypinator	0:bb348c97df44	656	*/
lypinator	0:bb348c97df44	657
lypinator	0:bb348c97df44	658	/** @defgroup RCCEx_SAI2_Clock_Source RCC SAI2 Clock Source
lypinator	0:bb348c97df44	659	* @{
lypinator	0:bb348c97df44	660	*/
lypinator	0:bb348c97df44	661	#define RCC_SAI2CLKSOURCE_PLLSAI 0x00000000U
lypinator	0:bb348c97df44	662	#define RCC_SAI2CLKSOURCE_PLLI2S ((uint32_t)RCC_DCKCFGR_SAI2SRC_0)
lypinator	0:bb348c97df44	663	#define RCC_SAI2CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_SAI2SRC_1)
lypinator	0:bb348c97df44	664	#define RCC_SAI2CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_SAI2SRC)
lypinator	0:bb348c97df44	665	/**
lypinator	0:bb348c97df44	666	* @}
lypinator	0:bb348c97df44	667	*/
lypinator	0:bb348c97df44	668
lypinator	0:bb348c97df44	669	/** @defgroup RCCEx_I2SAPB1_Clock_Source RCC I2S APB1 Clock Source
lypinator	0:bb348c97df44	670	* @{
lypinator	0:bb348c97df44	671	*/
lypinator	0:bb348c97df44	672	#define RCC_I2SAPB1CLKSOURCE_PLLI2S 0x00000000U
lypinator	0:bb348c97df44	673	#define RCC_I2SAPB1CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2S1SRC_0)
lypinator	0:bb348c97df44	674	#define RCC_I2SAPB1CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_I2S1SRC_1)
lypinator	0:bb348c97df44	675	#define RCC_I2SAPB1CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2S1SRC)
lypinator	0:bb348c97df44	676	/**
lypinator	0:bb348c97df44	677	* @}
lypinator	0:bb348c97df44	678	*/
lypinator	0:bb348c97df44	679
lypinator	0:bb348c97df44	680	/** @defgroup RCCEx_I2SAPB2_Clock_Source RCC I2S APB2 Clock Source
lypinator	0:bb348c97df44	681	* @{
lypinator	0:bb348c97df44	682	*/
lypinator	0:bb348c97df44	683	#define RCC_I2SAPB2CLKSOURCE_PLLI2S 0x00000000U
lypinator	0:bb348c97df44	684	#define RCC_I2SAPB2CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2S2SRC_0)
lypinator	0:bb348c97df44	685	#define RCC_I2SAPB2CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_I2S2SRC_1)
lypinator	0:bb348c97df44	686	#define RCC_I2SAPB2CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2S2SRC)
lypinator	0:bb348c97df44	687	/**
lypinator	0:bb348c97df44	688	* @}
lypinator	0:bb348c97df44	689	*/
lypinator	0:bb348c97df44	690
lypinator	0:bb348c97df44	691	/** @defgroup RCCEx_FMPI2C1_Clock_Source RCC FMPI2C1 Clock Source
lypinator	0:bb348c97df44	692	* @{
lypinator	0:bb348c97df44	693	*/
lypinator	0:bb348c97df44	694	#define RCC_FMPI2C1CLKSOURCE_PCLK1 0x00000000U
lypinator	0:bb348c97df44	695	#define RCC_FMPI2C1CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0)
lypinator	0:bb348c97df44	696	#define RCC_FMPI2C1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1)
lypinator	0:bb348c97df44	697	/**
lypinator	0:bb348c97df44	698	* @}
lypinator	0:bb348c97df44	699	*/
lypinator	0:bb348c97df44	700
lypinator	0:bb348c97df44	701	/** @defgroup RCCEx_CEC_Clock_Source RCC CEC Clock Source
lypinator	0:bb348c97df44	702	* @{
lypinator	0:bb348c97df44	703	*/
lypinator	0:bb348c97df44	704	#define RCC_CECCLKSOURCE_HSI 0x00000000U
lypinator	0:bb348c97df44	705	#define RCC_CECCLKSOURCE_LSE ((uint32_t)RCC_DCKCFGR2_CECSEL)
lypinator	0:bb348c97df44	706	/**
lypinator	0:bb348c97df44	707	* @}
lypinator	0:bb348c97df44	708	*/
lypinator	0:bb348c97df44	709
lypinator	0:bb348c97df44	710	/** @defgroup RCCEx_CLK48_Clock_Source RCC CLK48 Clock Source
lypinator	0:bb348c97df44	711	* @{
lypinator	0:bb348c97df44	712	*/
lypinator	0:bb348c97df44	713	#define RCC_CLK48CLKSOURCE_PLLQ 0x00000000U
lypinator	0:bb348c97df44	714	#define RCC_CLK48CLKSOURCE_PLLSAIP ((uint32_t)RCC_DCKCFGR2_CK48MSEL)
lypinator	0:bb348c97df44	715	/**
lypinator	0:bb348c97df44	716	* @}
lypinator	0:bb348c97df44	717	*/
lypinator	0:bb348c97df44	718
lypinator	0:bb348c97df44	719	/** @defgroup RCCEx_SDIO_Clock_Source RCC SDIO Clock Source
lypinator	0:bb348c97df44	720	* @{
lypinator	0:bb348c97df44	721	*/
lypinator	0:bb348c97df44	722	#define RCC_SDIOCLKSOURCE_CLK48 0x00000000U
lypinator	0:bb348c97df44	723	#define RCC_SDIOCLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_SDIOSEL)
lypinator	0:bb348c97df44	724	/**
lypinator	0:bb348c97df44	725	* @}
lypinator	0:bb348c97df44	726	*/
lypinator	0:bb348c97df44	727
lypinator	0:bb348c97df44	728	/** @defgroup RCCEx_SPDIFRX_Clock_Source RCC SPDIFRX Clock Source
lypinator	0:bb348c97df44	729	* @{
lypinator	0:bb348c97df44	730	*/
lypinator	0:bb348c97df44	731	#define RCC_SPDIFRXCLKSOURCE_PLLR 0x00000000U
lypinator	0:bb348c97df44	732	#define RCC_SPDIFRXCLKSOURCE_PLLI2SP ((uint32_t)RCC_DCKCFGR2_SPDIFRXSEL)
lypinator	0:bb348c97df44	733	/**
lypinator	0:bb348c97df44	734	* @}
lypinator	0:bb348c97df44	735	*/
lypinator	0:bb348c97df44	736
lypinator	0:bb348c97df44	737	#endif /* STM32F446xx */
lypinator	0:bb348c97df44	738
lypinator	0:bb348c97df44	739	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
lypinator	0:bb348c97df44	740	/** @defgroup RCCEx_SAI1_BlockA_Clock_Source RCC SAI BlockA Clock Source
lypinator	0:bb348c97df44	741	* @{
lypinator	0:bb348c97df44	742	*/
lypinator	0:bb348c97df44	743	#define RCC_SAIACLKSOURCE_PLLI2SR 0x00000000U
lypinator	0:bb348c97df44	744	#define RCC_SAIACLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_SAI1ASRC_0)
lypinator	0:bb348c97df44	745	#define RCC_SAIACLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_SAI1ASRC_1)
lypinator	0:bb348c97df44	746	#define RCC_SAIACLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_SAI1ASRC_0 \| RCC_DCKCFGR_SAI1ASRC_1)
lypinator	0:bb348c97df44	747	/**
lypinator	0:bb348c97df44	748	* @}
lypinator	0:bb348c97df44	749	*/
lypinator	0:bb348c97df44	750
lypinator	0:bb348c97df44	751	/** @defgroup RCCEx_SAI1_BlockB_Clock_Source RCC SAI BlockB Clock Source
lypinator	0:bb348c97df44	752	* @{
lypinator	0:bb348c97df44	753	*/
lypinator	0:bb348c97df44	754	#define RCC_SAIBCLKSOURCE_PLLI2SR 0x00000000U
lypinator	0:bb348c97df44	755	#define RCC_SAIBCLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_SAI1BSRC_0)
lypinator	0:bb348c97df44	756	#define RCC_SAIBCLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_SAI1BSRC_1)
lypinator	0:bb348c97df44	757	#define RCC_SAIBCLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_SAI1BSRC_0 \| RCC_DCKCFGR_SAI1BSRC_1)
lypinator	0:bb348c97df44	758	/**
lypinator	0:bb348c97df44	759	* @}
lypinator	0:bb348c97df44	760	*/
lypinator	0:bb348c97df44	761
lypinator	0:bb348c97df44	762	/** @defgroup RCCEx_LPTIM1_Clock_Source RCC LPTIM1 Clock Source
lypinator	0:bb348c97df44	763	* @{
lypinator	0:bb348c97df44	764	*/
lypinator	0:bb348c97df44	765	#define RCC_LPTIM1CLKSOURCE_PCLK1 0x00000000U
lypinator	0:bb348c97df44	766	#define RCC_LPTIM1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0)
lypinator	0:bb348c97df44	767	#define RCC_LPTIM1CLKSOURCE_LSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_1)
lypinator	0:bb348c97df44	768	#define RCC_LPTIM1CLKSOURCE_LSE ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0 \| RCC_DCKCFGR2_LPTIM1SEL_1)
lypinator	0:bb348c97df44	769	/**
lypinator	0:bb348c97df44	770	* @}
lypinator	0:bb348c97df44	771	*/
lypinator	0:bb348c97df44	772
lypinator	0:bb348c97df44	773
lypinator	0:bb348c97df44	774	/** @defgroup RCCEx_DFSDM2_Audio_Clock_Source RCC DFSDM2 Audio Clock Source
lypinator	0:bb348c97df44	775	* @{
lypinator	0:bb348c97df44	776	*/
lypinator	0:bb348c97df44	777	#define RCC_DFSDM2AUDIOCLKSOURCE_I2S1 0x00000000U
lypinator	0:bb348c97df44	778	#define RCC_DFSDM2AUDIOCLKSOURCE_I2S2 ((uint32_t)RCC_DCKCFGR_CKDFSDM2ASEL)
lypinator	0:bb348c97df44	779	/**
lypinator	0:bb348c97df44	780	* @}
lypinator	0:bb348c97df44	781	*/
lypinator	0:bb348c97df44	782
lypinator	0:bb348c97df44	783	/** @defgroup RCCEx_DFSDM2_Kernel_Clock_Source RCC DFSDM2 Kernel Clock Source
lypinator	0:bb348c97df44	784	* @{
lypinator	0:bb348c97df44	785	*/
lypinator	0:bb348c97df44	786	#define RCC_DFSDM2CLKSOURCE_PCLK2 0x00000000U
lypinator	0:bb348c97df44	787	#define RCC_DFSDM2CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR_CKDFSDM1SEL)
lypinator	0:bb348c97df44	788	/**
lypinator	0:bb348c97df44	789	* @}
lypinator	0:bb348c97df44	790	*/
lypinator	0:bb348c97df44	791
lypinator	0:bb348c97df44	792	#endif /* STM32F413xx \|\| STM32F423xx */
lypinator	0:bb348c97df44	793
lypinator	0:bb348c97df44	794	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
lypinator	0:bb348c97df44	795	/** @defgroup RCCEx_PLL_I2S_Clock_Source PLL I2S Clock Source
lypinator	0:bb348c97df44	796	* @{
lypinator	0:bb348c97df44	797	*/
lypinator	0:bb348c97df44	798	#define RCC_PLLI2SCLKSOURCE_PLLSRC 0x00000000U
lypinator	0:bb348c97df44	799	#define RCC_PLLI2SCLKSOURCE_EXT ((uint32_t)RCC_PLLI2SCFGR_PLLI2SSRC)
lypinator	0:bb348c97df44	800	/**
lypinator	0:bb348c97df44	801	* @}
lypinator	0:bb348c97df44	802	*/
lypinator	0:bb348c97df44	803
lypinator	0:bb348c97df44	804	/** @defgroup RCCEx_DFSDM1_Audio_Clock_Source RCC DFSDM1 Audio Clock Source
lypinator	0:bb348c97df44	805	* @{
lypinator	0:bb348c97df44	806	*/
lypinator	0:bb348c97df44	807	#define RCC_DFSDM1AUDIOCLKSOURCE_I2S1 0x00000000U
lypinator	0:bb348c97df44	808	#define RCC_DFSDM1AUDIOCLKSOURCE_I2S2 ((uint32_t)RCC_DCKCFGR_CKDFSDM1ASEL)
lypinator	0:bb348c97df44	809	/**
lypinator	0:bb348c97df44	810	* @}
lypinator	0:bb348c97df44	811	*/
lypinator	0:bb348c97df44	812
lypinator	0:bb348c97df44	813	/** @defgroup RCCEx_DFSDM1_Kernel_Clock_Source RCC DFSDM1 Kernel Clock Source
lypinator	0:bb348c97df44	814	* @{
lypinator	0:bb348c97df44	815	*/
lypinator	0:bb348c97df44	816	#define RCC_DFSDM1CLKSOURCE_PCLK2 0x00000000U
lypinator	0:bb348c97df44	817	#define RCC_DFSDM1CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR_CKDFSDM1SEL)
lypinator	0:bb348c97df44	818	/**
lypinator	0:bb348c97df44	819	* @}
lypinator	0:bb348c97df44	820	*/
lypinator	0:bb348c97df44	821
lypinator	0:bb348c97df44	822	/** @defgroup RCCEx_I2SAPB1_Clock_Source RCC I2S APB1 Clock Source
lypinator	0:bb348c97df44	823	* @{
lypinator	0:bb348c97df44	824	*/
lypinator	0:bb348c97df44	825	#define RCC_I2SAPB1CLKSOURCE_PLLI2S 0x00000000U
lypinator	0:bb348c97df44	826	#define RCC_I2SAPB1CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2S1SRC_0)
lypinator	0:bb348c97df44	827	#define RCC_I2SAPB1CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_I2S1SRC_1)
lypinator	0:bb348c97df44	828	#define RCC_I2SAPB1CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2S1SRC)
lypinator	0:bb348c97df44	829	/**
lypinator	0:bb348c97df44	830	* @}
lypinator	0:bb348c97df44	831	*/
lypinator	0:bb348c97df44	832
lypinator	0:bb348c97df44	833	/** @defgroup RCCEx_I2SAPB2_Clock_Source RCC I2S APB2 Clock Source
lypinator	0:bb348c97df44	834	* @{
lypinator	0:bb348c97df44	835	*/
lypinator	0:bb348c97df44	836	#define RCC_I2SAPB2CLKSOURCE_PLLI2S 0x00000000U
lypinator	0:bb348c97df44	837	#define RCC_I2SAPB2CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2S2SRC_0)
lypinator	0:bb348c97df44	838	#define RCC_I2SAPB2CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_I2S2SRC_1)
lypinator	0:bb348c97df44	839	#define RCC_I2SAPB2CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2S2SRC)
lypinator	0:bb348c97df44	840	/**
lypinator	0:bb348c97df44	841	* @}
lypinator	0:bb348c97df44	842	*/
lypinator	0:bb348c97df44	843
lypinator	0:bb348c97df44	844	/** @defgroup RCCEx_FMPI2C1_Clock_Source RCC FMPI2C1 Clock Source
lypinator	0:bb348c97df44	845	* @{
lypinator	0:bb348c97df44	846	*/
lypinator	0:bb348c97df44	847	#define RCC_FMPI2C1CLKSOURCE_PCLK1 0x00000000U
lypinator	0:bb348c97df44	848	#define RCC_FMPI2C1CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0)
lypinator	0:bb348c97df44	849	#define RCC_FMPI2C1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1)
lypinator	0:bb348c97df44	850	/**
lypinator	0:bb348c97df44	851	* @}
lypinator	0:bb348c97df44	852	*/
lypinator	0:bb348c97df44	853
lypinator	0:bb348c97df44	854	/** @defgroup RCCEx_CLK48_Clock_Source RCC CLK48 Clock Source
lypinator	0:bb348c97df44	855	* @{
lypinator	0:bb348c97df44	856	*/
lypinator	0:bb348c97df44	857	#define RCC_CLK48CLKSOURCE_PLLQ 0x00000000U
lypinator	0:bb348c97df44	858	#define RCC_CLK48CLKSOURCE_PLLI2SQ ((uint32_t)RCC_DCKCFGR2_CK48MSEL)
lypinator	0:bb348c97df44	859	/**
lypinator	0:bb348c97df44	860	* @}
lypinator	0:bb348c97df44	861	*/
lypinator	0:bb348c97df44	862
lypinator	0:bb348c97df44	863	/** @defgroup RCCEx_SDIO_Clock_Source RCC SDIO Clock Source
lypinator	0:bb348c97df44	864	* @{
lypinator	0:bb348c97df44	865	*/
lypinator	0:bb348c97df44	866	#define RCC_SDIOCLKSOURCE_CLK48 0x00000000U
lypinator	0:bb348c97df44	867	#define RCC_SDIOCLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_SDIOSEL)
lypinator	0:bb348c97df44	868	/**
lypinator	0:bb348c97df44	869	* @}
lypinator	0:bb348c97df44	870	*/
lypinator	0:bb348c97df44	871	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx \|\| STM32F413xx \|\| STM32F423xx */
lypinator	0:bb348c97df44	872
lypinator	0:bb348c97df44	873	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
lypinator	0:bb348c97df44	874
lypinator	0:bb348c97df44	875	/** @defgroup RCCEx_I2S_APB_Clock_Source RCC I2S APB Clock Source
lypinator	0:bb348c97df44	876	* @{
lypinator	0:bb348c97df44	877	*/
lypinator	0:bb348c97df44	878	#define RCC_I2SAPBCLKSOURCE_PLLR 0x00000000U
lypinator	0:bb348c97df44	879	#define RCC_I2SAPBCLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2SSRC_0)
lypinator	0:bb348c97df44	880	#define RCC_I2SAPBCLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2SSRC_1)
lypinator	0:bb348c97df44	881	/**
lypinator	0:bb348c97df44	882	* @}
lypinator	0:bb348c97df44	883	*/
lypinator	0:bb348c97df44	884
lypinator	0:bb348c97df44	885	/** @defgroup RCCEx_FMPI2C1_Clock_Source RCC FMPI2C1 Clock Source
lypinator	0:bb348c97df44	886	* @{
lypinator	0:bb348c97df44	887	*/
lypinator	0:bb348c97df44	888	#define RCC_FMPI2C1CLKSOURCE_PCLK1 0x00000000U
lypinator	0:bb348c97df44	889	#define RCC_FMPI2C1CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0)
lypinator	0:bb348c97df44	890	#define RCC_FMPI2C1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1)
lypinator	0:bb348c97df44	891	/**
lypinator	0:bb348c97df44	892	* @}
lypinator	0:bb348c97df44	893	*/
lypinator	0:bb348c97df44	894
lypinator	0:bb348c97df44	895	/** @defgroup RCCEx_LPTIM1_Clock_Source RCC LPTIM1 Clock Source
lypinator	0:bb348c97df44	896	* @{
lypinator	0:bb348c97df44	897	*/
lypinator	0:bb348c97df44	898	#define RCC_LPTIM1CLKSOURCE_PCLK1 0x00000000U
lypinator	0:bb348c97df44	899	#define RCC_LPTIM1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0)
lypinator	0:bb348c97df44	900	#define RCC_LPTIM1CLKSOURCE_LSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_1)
lypinator	0:bb348c97df44	901	#define RCC_LPTIM1CLKSOURCE_LSE ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0 \| RCC_DCKCFGR2_LPTIM1SEL_1)
lypinator	0:bb348c97df44	902	/**
lypinator	0:bb348c97df44	903	* @}
lypinator	0:bb348c97df44	904	*/
lypinator	0:bb348c97df44	905	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
lypinator	0:bb348c97df44	906
lypinator	0:bb348c97df44	907	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\|\
lypinator	0:bb348c97df44	908	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\|\
lypinator	0:bb348c97df44	909	defined(STM32F410Rx) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| defined(STM32F469xx) \|\|\
lypinator	0:bb348c97df44	910	defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\|\
lypinator	0:bb348c97df44	911	defined(STM32F412Cx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
lypinator	0:bb348c97df44	912	/** @defgroup RCCEx_TIM_PRescaler_Selection RCC TIM PRescaler Selection
lypinator	0:bb348c97df44	913	* @{
lypinator	0:bb348c97df44	914	*/
lypinator	0:bb348c97df44	915	#define RCC_TIMPRES_DESACTIVATED ((uint8_t)0x00)
lypinator	0:bb348c97df44	916	#define RCC_TIMPRES_ACTIVATED ((uint8_t)0x01)
lypinator	0:bb348c97df44	917	/**
lypinator	0:bb348c97df44	918	* @}
lypinator	0:bb348c97df44	919	*/
lypinator	0:bb348c97df44	920	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F401xC \|\| STM32F401xE \|\|\
lypinator	0:bb348c97df44	921	STM32F410xx \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\|\
lypinator	0:bb348c97df44	922	STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx \|\| STM32F413xx \|\| STM32F423xx */
lypinator	0:bb348c97df44	923
lypinator	0:bb348c97df44	924	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx) \|\| defined(STM32F411xE) \|\|\
lypinator	0:bb348c97df44	925	defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\|\
lypinator	0:bb348c97df44	926	defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx) \|\| defined(STM32F413xx) \|\|\
lypinator	0:bb348c97df44	927	defined(STM32F423xx)
lypinator	0:bb348c97df44	928	/** @defgroup RCCEx_LSE_Dual_Mode_Selection RCC LSE Dual Mode Selection
lypinator	0:bb348c97df44	929	* @{
lypinator	0:bb348c97df44	930	*/
lypinator	0:bb348c97df44	931	#define RCC_LSE_LOWPOWER_MODE ((uint8_t)0x00)
lypinator	0:bb348c97df44	932	#define RCC_LSE_HIGHDRIVE_MODE ((uint8_t)0x01)
lypinator	0:bb348c97df44	933	/**
lypinator	0:bb348c97df44	934	* @}
lypinator	0:bb348c97df44	935	*/
lypinator	0:bb348c97df44	936	#endif /* STM32F410xx \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\| STM32F412Vx \|\|\
lypinator	0:bb348c97df44	937	STM32F412Rx \|\| STM32F412Cx */
lypinator	0:bb348c97df44	938
lypinator	0:bb348c97df44	939	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\| \
lypinator	0:bb348c97df44	940	defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| \
lypinator	0:bb348c97df44	941	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| \
lypinator	0:bb348c97df44	942	defined(STM32F469xx) \|\| defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| \
lypinator	0:bb348c97df44	943	defined(STM32F412Rx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
lypinator	0:bb348c97df44	944	/** @defgroup RCC_MCO2_Clock_Source MCO2 Clock Source
lypinator	0:bb348c97df44	945	* @{
lypinator	0:bb348c97df44	946	*/
lypinator	0:bb348c97df44	947	#define RCC_MCO2SOURCE_SYSCLK 0x00000000U
lypinator	0:bb348c97df44	948	#define RCC_MCO2SOURCE_PLLI2SCLK RCC_CFGR_MCO2_0
lypinator	0:bb348c97df44	949	#define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1
lypinator	0:bb348c97df44	950	#define RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2
lypinator	0:bb348c97df44	951	/**
lypinator	0:bb348c97df44	952	* @}
lypinator	0:bb348c97df44	953	*/
lypinator	0:bb348c97df44	954	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\|
lypinator	0:bb348c97df44	955	STM32F401xC \|\| STM32F401xE \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\| STM32F412Vx \|\|
lypinator	0:bb348c97df44	956	STM32F412Rx \|\| STM32F413xx \| STM32F423xx */
lypinator	0:bb348c97df44	957
lypinator	0:bb348c97df44	958	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
lypinator	0:bb348c97df44	959	/** @defgroup RCC_MCO2_Clock_Source MCO2 Clock Source
lypinator	0:bb348c97df44	960	* @{
lypinator	0:bb348c97df44	961	*/
lypinator	0:bb348c97df44	962	#define RCC_MCO2SOURCE_SYSCLK 0x00000000U
lypinator	0:bb348c97df44	963	#define RCC_MCO2SOURCE_I2SCLK RCC_CFGR_MCO2_0
lypinator	0:bb348c97df44	964	#define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1
lypinator	0:bb348c97df44	965	#define RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2
lypinator	0:bb348c97df44	966	/**
lypinator	0:bb348c97df44	967	* @}
lypinator	0:bb348c97df44	968	*/
lypinator	0:bb348c97df44	969	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
lypinator	0:bb348c97df44	970
lypinator	0:bb348c97df44	971	/**
lypinator	0:bb348c97df44	972	* @}
lypinator	0:bb348c97df44	973	*/
lypinator	0:bb348c97df44	974
lypinator	0:bb348c97df44	975	/* Exported macro ------------------------------------------------------------*/
lypinator	0:bb348c97df44	976	/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
lypinator	0:bb348c97df44	977	* @{
lypinator	0:bb348c97df44	978	*/
lypinator	0:bb348c97df44	979	/------------------- STM32F42xxx/STM32F43xxx/STM32F469xx/STM32F479xx --------/
lypinator	0:bb348c97df44	980	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx)\|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
lypinator	0:bb348c97df44	981	/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
lypinator	0:bb348c97df44	982	* @brief Enables or disables the AHB1 peripheral clock.
lypinator	0:bb348c97df44	983	* @note After reset, the peripheral clock (used for registers read/write access)
lypinator	0:bb348c97df44	984	* is disabled and the application software has to enable this clock before
lypinator	0:bb348c97df44	985	* using it.
lypinator	0:bb348c97df44	986	* @{
lypinator	0:bb348c97df44	987	*/
lypinator	0:bb348c97df44	988	#define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	989	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	990	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
lypinator	0:bb348c97df44	991	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	992	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
lypinator	0:bb348c97df44	993	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	994	} while(0U)
lypinator	0:bb348c97df44	995	#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	996	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	997	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
lypinator	0:bb348c97df44	998	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	999	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
lypinator	0:bb348c97df44	1000	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	1001	} while(0U)
lypinator	0:bb348c97df44	1002	#define __HAL_RCC_CRC_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	1003	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	1004	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
lypinator	0:bb348c97df44	1005	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	1006	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
lypinator	0:bb348c97df44	1007	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	1008	} while(0U)
lypinator	0:bb348c97df44	1009	#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	1010	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	1011	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
lypinator	0:bb348c97df44	1012	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	1013	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
lypinator	0:bb348c97df44	1014	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	1015	} while(0U)
lypinator	0:bb348c97df44	1016	#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	1017	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	1018	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
lypinator	0:bb348c97df44	1019	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	1020	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
lypinator	0:bb348c97df44	1021	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	1022	} while(0U)
lypinator	0:bb348c97df44	1023	#define __HAL_RCC_GPIOI_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	1024	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	1025	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
lypinator	0:bb348c97df44	1026	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	1027	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
lypinator	0:bb348c97df44	1028	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	1029	} while(0U)
lypinator	0:bb348c97df44	1030	#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	1031	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	1032	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
lypinator	0:bb348c97df44	1033	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	1034	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
lypinator	0:bb348c97df44	1035	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	1036	} while(0U)
lypinator	0:bb348c97df44	1037	#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	1038	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	1039	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
lypinator	0:bb348c97df44	1040	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	1041	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
lypinator	0:bb348c97df44	1042	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	1043	} while(0U)
lypinator	0:bb348c97df44	1044	#define __HAL_RCC_GPIOJ_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	1045	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	1046	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\
lypinator	0:bb348c97df44	1047	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	1048	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\
lypinator	0:bb348c97df44	1049	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	1050	} while(0U)
lypinator	0:bb348c97df44	1051	#define __HAL_RCC_GPIOK_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	1052	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	1053	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\
lypinator	0:bb348c97df44	1054	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	1055	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\
lypinator	0:bb348c97df44	1056	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	1057	} while(0U)
lypinator	0:bb348c97df44	1058	#define __HAL_RCC_DMA2D_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	1059	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	1060	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\
lypinator	0:bb348c97df44	1061	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	1062	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\
lypinator	0:bb348c97df44	1063	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	1064	} while(0U)
lypinator	0:bb348c97df44	1065	#define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	1066	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	1067	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
lypinator	0:bb348c97df44	1068	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	1069	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
lypinator	0:bb348c97df44	1070	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	1071	} while(0U)
lypinator	0:bb348c97df44	1072	#define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	1073	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	1074	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
lypinator	0:bb348c97df44	1075	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	1076	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
lypinator	0:bb348c97df44	1077	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	1078	} while(0U)
lypinator	0:bb348c97df44	1079	#define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	1080	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	1081	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
lypinator	0:bb348c97df44	1082	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	1083	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
lypinator	0:bb348c97df44	1084	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	1085	} while(0U)
lypinator	0:bb348c97df44	1086	#define __HAL_RCC_ETHMACPTP_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	1087	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	1088	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
lypinator	0:bb348c97df44	1089	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	1090	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
lypinator	0:bb348c97df44	1091	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	1092	} while(0U)
lypinator	0:bb348c97df44	1093	#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	1094	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	1095	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
lypinator	0:bb348c97df44	1096	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	1097	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
lypinator	0:bb348c97df44	1098	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	1099	} while(0U)
lypinator	0:bb348c97df44	1100	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	1101	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	1102	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
lypinator	0:bb348c97df44	1103	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	1104	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
lypinator	0:bb348c97df44	1105	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	1106	} while(0U)
lypinator	0:bb348c97df44	1107	#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
lypinator	0:bb348c97df44	1108	#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
lypinator	0:bb348c97df44	1109	#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
lypinator	0:bb348c97df44	1110	#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
lypinator	0:bb348c97df44	1111	#define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))
lypinator	0:bb348c97df44	1112	#define __HAL_RCC_GPIOJ_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOJEN))
lypinator	0:bb348c97df44	1113	#define __HAL_RCC_GPIOK_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOKEN))
lypinator	0:bb348c97df44	1114	#define __HAL_RCC_DMA2D_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2DEN))
lypinator	0:bb348c97df44	1115	#define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))
lypinator	0:bb348c97df44	1116	#define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))
lypinator	0:bb348c97df44	1117	#define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))
lypinator	0:bb348c97df44	1118	#define __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))
lypinator	0:bb348c97df44	1119	#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
lypinator	0:bb348c97df44	1120	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
lypinator	0:bb348c97df44	1121	#define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
lypinator	0:bb348c97df44	1122	#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
lypinator	0:bb348c97df44	1123	#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
lypinator	0:bb348c97df44	1124
lypinator	0:bb348c97df44	1125	/**
lypinator	0:bb348c97df44	1126	* @brief Enable ETHERNET clock.
lypinator	0:bb348c97df44	1127	*/
lypinator	0:bb348c97df44	1128	#define __HAL_RCC_ETH_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	1129	__HAL_RCC_ETHMAC_CLK_ENABLE(); \
lypinator	0:bb348c97df44	1130	__HAL_RCC_ETHMACTX_CLK_ENABLE(); \
lypinator	0:bb348c97df44	1131	__HAL_RCC_ETHMACRX_CLK_ENABLE(); \
lypinator	0:bb348c97df44	1132	} while(0U)
lypinator	0:bb348c97df44	1133	/**
lypinator	0:bb348c97df44	1134	* @brief Disable ETHERNET clock.
lypinator	0:bb348c97df44	1135	*/
lypinator	0:bb348c97df44	1136	#define __HAL_RCC_ETH_CLK_DISABLE() do { \
lypinator	0:bb348c97df44	1137	__HAL_RCC_ETHMACTX_CLK_DISABLE(); \
lypinator	0:bb348c97df44	1138	__HAL_RCC_ETHMACRX_CLK_DISABLE(); \
lypinator	0:bb348c97df44	1139	__HAL_RCC_ETHMAC_CLK_DISABLE(); \
lypinator	0:bb348c97df44	1140	} while(0U)
lypinator	0:bb348c97df44	1141	/**
lypinator	0:bb348c97df44	1142	* @}
lypinator	0:bb348c97df44	1143	*/
lypinator	0:bb348c97df44	1144
lypinator	0:bb348c97df44	1145	/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
lypinator	0:bb348c97df44	1146	* @brief Get the enable or disable status of the AHB1 peripheral clock.
lypinator	0:bb348c97df44	1147	* @note After reset, the peripheral clock (used for registers read/write access)
lypinator	0:bb348c97df44	1148	* is disabled and the application software has to enable this clock before
lypinator	0:bb348c97df44	1149	* using it.
lypinator	0:bb348c97df44	1150	* @{
lypinator	0:bb348c97df44	1151	*/
lypinator	0:bb348c97df44	1152	#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)
lypinator	0:bb348c97df44	1153	#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)
lypinator	0:bb348c97df44	1154	#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET)
lypinator	0:bb348c97df44	1155	#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET)
lypinator	0:bb348c97df44	1156	#define __HAL_RCC_GPIOI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) != RESET)
lypinator	0:bb348c97df44	1157	#define __HAL_RCC_GPIOJ_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) != RESET)
lypinator	0:bb348c97df44	1158	#define __HAL_RCC_GPIOK_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) != RESET)
lypinator	0:bb348c97df44	1159	#define __HAL_RCC_DMA2D_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) != RESET)
lypinator	0:bb348c97df44	1160	#define __HAL_RCC_ETHMAC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) != RESET)
lypinator	0:bb348c97df44	1161	#define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) != RESET)
lypinator	0:bb348c97df44	1162	#define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) != RESET)
lypinator	0:bb348c97df44	1163	#define __HAL_RCC_ETHMACPTP_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) != RESET)
lypinator	0:bb348c97df44	1164	#define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET)
lypinator	0:bb348c97df44	1165	#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET)
lypinator	0:bb348c97df44	1166	#define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET)
lypinator	0:bb348c97df44	1167	#define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) != RESET)
lypinator	0:bb348c97df44	1168	#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
lypinator	0:bb348c97df44	1169	#define __HAL_RCC_ETH_IS_CLK_ENABLED() (__HAL_RCC_ETHMAC_IS_CLK_ENABLED() && \
lypinator	0:bb348c97df44	1170	__HAL_RCC_ETHMACTX_IS_CLK_ENABLED() && \
lypinator	0:bb348c97df44	1171	__HAL_RCC_ETHMACRX_IS_CLK_ENABLED())
lypinator	0:bb348c97df44	1172
lypinator	0:bb348c97df44	1173	#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)
lypinator	0:bb348c97df44	1174	#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)
lypinator	0:bb348c97df44	1175	#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET)
lypinator	0:bb348c97df44	1176	#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET)
lypinator	0:bb348c97df44	1177	#define __HAL_RCC_GPIOI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) == RESET)
lypinator	0:bb348c97df44	1178	#define __HAL_RCC_GPIOJ_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) == RESET)
lypinator	0:bb348c97df44	1179	#define __HAL_RCC_GPIOK_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) == RESET)
lypinator	0:bb348c97df44	1180	#define __HAL_RCC_DMA2D_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) == RESET)
lypinator	0:bb348c97df44	1181	#define __HAL_RCC_ETHMAC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) == RESET)
lypinator	0:bb348c97df44	1182	#define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) == RESET)
lypinator	0:bb348c97df44	1183	#define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) == RESET)
lypinator	0:bb348c97df44	1184	#define __HAL_RCC_ETHMACPTP_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) == RESET)
lypinator	0:bb348c97df44	1185	#define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET)
lypinator	0:bb348c97df44	1186	#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) == RESET)
lypinator	0:bb348c97df44	1187	#define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET)
lypinator	0:bb348c97df44	1188	#define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET)
lypinator	0:bb348c97df44	1189	#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
lypinator	0:bb348c97df44	1190	#define __HAL_RCC_ETH_IS_CLK_DISABLED() (__HAL_RCC_ETHMAC_IS_CLK_DISABLED() && \
lypinator	0:bb348c97df44	1191	__HAL_RCC_ETHMACTX_IS_CLK_DISABLED() && \
lypinator	0:bb348c97df44	1192	__HAL_RCC_ETHMACRX_IS_CLK_DISABLED())
lypinator	0:bb348c97df44	1193	/**
lypinator	0:bb348c97df44	1194	* @}
lypinator	0:bb348c97df44	1195	*/
lypinator	0:bb348c97df44	1196
lypinator	0:bb348c97df44	1197	/** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
lypinator	0:bb348c97df44	1198	* @brief Enable or disable the AHB2 peripheral clock.
lypinator	0:bb348c97df44	1199	* @note After reset, the peripheral clock (used for registers read/write access)
lypinator	0:bb348c97df44	1200	* is disabled and the application software has to enable this clock before
lypinator	0:bb348c97df44	1201	* using it.
lypinator	0:bb348c97df44	1202	* @{
lypinator	0:bb348c97df44	1203	*/
lypinator	0:bb348c97df44	1204	#define __HAL_RCC_DCMI_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	1205	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	1206	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
lypinator	0:bb348c97df44	1207	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	1208	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
lypinator	0:bb348c97df44	1209	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	1210	} while(0U)
lypinator	0:bb348c97df44	1211	#define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
lypinator	0:bb348c97df44	1212
lypinator	0:bb348c97df44	1213	#if defined(STM32F437xx)\|\| defined(STM32F439xx) \|\| defined(STM32F479xx)
lypinator	0:bb348c97df44	1214	#define __HAL_RCC_CRYP_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	1215	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	1216	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
lypinator	0:bb348c97df44	1217	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	1218	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
lypinator	0:bb348c97df44	1219	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	1220	} while(0U)
lypinator	0:bb348c97df44	1221	#define __HAL_RCC_HASH_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	1222	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	1223	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
lypinator	0:bb348c97df44	1224	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	1225	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
lypinator	0:bb348c97df44	1226	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	1227	} while(0U)
lypinator	0:bb348c97df44	1228
lypinator	0:bb348c97df44	1229	#define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))
lypinator	0:bb348c97df44	1230	#define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN))
lypinator	0:bb348c97df44	1231	#endif /* STM32F437xx \|\| STM32F439xx \|\| STM32F479xx */
lypinator	0:bb348c97df44	1232
lypinator	0:bb348c97df44	1233	#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR \|= (RCC_AHB2ENR_OTGFSEN));\
lypinator	0:bb348c97df44	1234	__HAL_RCC_SYSCFG_CLK_ENABLE();\
lypinator	0:bb348c97df44	1235	}while(0U)
lypinator	0:bb348c97df44	1236
lypinator	0:bb348c97df44	1237	#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
lypinator	0:bb348c97df44	1238
lypinator	0:bb348c97df44	1239	#define __HAL_RCC_RNG_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	1240	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	1241	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
lypinator	0:bb348c97df44	1242	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	1243	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
lypinator	0:bb348c97df44	1244	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	1245	} while(0U)
lypinator	0:bb348c97df44	1246	#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
lypinator	0:bb348c97df44	1247	/**
lypinator	0:bb348c97df44	1248	* @}
lypinator	0:bb348c97df44	1249	*/
lypinator	0:bb348c97df44	1250
lypinator	0:bb348c97df44	1251	/** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status
lypinator	0:bb348c97df44	1252	* @brief Get the enable or disable status of the AHB1 peripheral clock.
lypinator	0:bb348c97df44	1253	* @note After reset, the peripheral clock (used for registers read/write access)
lypinator	0:bb348c97df44	1254	* is disabled and the application software has to enable this clock before
lypinator	0:bb348c97df44	1255	* using it.
lypinator	0:bb348c97df44	1256	* @{
lypinator	0:bb348c97df44	1257	*/
lypinator	0:bb348c97df44	1258	#define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET)
lypinator	0:bb348c97df44	1259	#define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET)
lypinator	0:bb348c97df44	1260
lypinator	0:bb348c97df44	1261	#if defined(STM32F437xx)\|\| defined(STM32F439xx) \|\| defined(STM32F479xx)
lypinator	0:bb348c97df44	1262	#define __HAL_RCC_CRYP_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) != RESET)
lypinator	0:bb348c97df44	1263	#define __HAL_RCC_CRYP_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) == RESET)
lypinator	0:bb348c97df44	1264
lypinator	0:bb348c97df44	1265	#define __HAL_RCC_HASH_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) != RESET)
lypinator	0:bb348c97df44	1266	#define __HAL_RCC_HASH_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) == RESET)
lypinator	0:bb348c97df44	1267	#endif /* STM32F437xx \|\| STM32F439xx \|\| STM32F479xx */
lypinator	0:bb348c97df44	1268
lypinator	0:bb348c97df44	1269	#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
lypinator	0:bb348c97df44	1270	#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
lypinator	0:bb348c97df44	1271
lypinator	0:bb348c97df44	1272	#define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET)
lypinator	0:bb348c97df44	1273	#define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET)
lypinator	0:bb348c97df44	1274	/**
lypinator	0:bb348c97df44	1275	* @}
lypinator	0:bb348c97df44	1276	*/
lypinator	0:bb348c97df44	1277
lypinator	0:bb348c97df44	1278	/** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable
lypinator	0:bb348c97df44	1279	* @brief Enables or disables the AHB3 peripheral clock.
lypinator	0:bb348c97df44	1280	* @note After reset, the peripheral clock (used for registers read/write access)
lypinator	0:bb348c97df44	1281	* is disabled and the application software has to enable this clock before
lypinator	0:bb348c97df44	1282	* using it.
lypinator	0:bb348c97df44	1283	* @{
lypinator	0:bb348c97df44	1284	*/
lypinator	0:bb348c97df44	1285	#define __HAL_RCC_FMC_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	1286	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	1287	SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
lypinator	0:bb348c97df44	1288	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	1289	tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
lypinator	0:bb348c97df44	1290	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	1291	} while(0U)
lypinator	0:bb348c97df44	1292	#define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN))
lypinator	0:bb348c97df44	1293	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
lypinator	0:bb348c97df44	1294	#define __HAL_RCC_QSPI_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	1295	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	1296	SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
lypinator	0:bb348c97df44	1297	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	1298	tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
lypinator	0:bb348c97df44	1299	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	1300	} while(0U)
lypinator	0:bb348c97df44	1301	#define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN))
lypinator	0:bb348c97df44	1302	#endif /* STM32F469xx \|\| STM32F479xx */
lypinator	0:bb348c97df44	1303	/**
lypinator	0:bb348c97df44	1304	* @}
lypinator	0:bb348c97df44	1305	*/
lypinator	0:bb348c97df44	1306
lypinator	0:bb348c97df44	1307
lypinator	0:bb348c97df44	1308	/** @defgroup RCCEx_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enable Disable Status
lypinator	0:bb348c97df44	1309	* @brief Get the enable or disable status of the AHB3 peripheral clock.
lypinator	0:bb348c97df44	1310	* @note After reset, the peripheral clock (used for registers read/write access)
lypinator	0:bb348c97df44	1311	* is disabled and the application software has to enable this clock before
lypinator	0:bb348c97df44	1312	* using it.
lypinator	0:bb348c97df44	1313	* @{
lypinator	0:bb348c97df44	1314	*/
lypinator	0:bb348c97df44	1315	#define __HAL_RCC_FMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) != RESET)
lypinator	0:bb348c97df44	1316	#define __HAL_RCC_FMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) == RESET)
lypinator	0:bb348c97df44	1317	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
lypinator	0:bb348c97df44	1318	#define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET)
lypinator	0:bb348c97df44	1319	#define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET)
lypinator	0:bb348c97df44	1320	#endif /* STM32F469xx \|\| STM32F479xx */
lypinator	0:bb348c97df44	1321	/**
lypinator	0:bb348c97df44	1322	* @}
lypinator	0:bb348c97df44	1323	*/
lypinator	0:bb348c97df44	1324
lypinator	0:bb348c97df44	1325	/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
lypinator	0:bb348c97df44	1326	* @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
lypinator	0:bb348c97df44	1327	* @note After reset, the peripheral clock (used for registers read/write access)
lypinator	0:bb348c97df44	1328	* is disabled and the application software has to enable this clock before
lypinator	0:bb348c97df44	1329	* using it.
lypinator	0:bb348c97df44	1330	* @{
lypinator	0:bb348c97df44	1331	*/
lypinator	0:bb348c97df44	1332	#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	1333	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	1334	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
lypinator	0:bb348c97df44	1335	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	1336	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
lypinator	0:bb348c97df44	1337	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	1338	} while(0U)
lypinator	0:bb348c97df44	1339	#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	1340	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	1341	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
lypinator	0:bb348c97df44	1342	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	1343	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
lypinator	0:bb348c97df44	1344	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	1345	} while(0U)
lypinator	0:bb348c97df44	1346	#define __HAL_RCC_TIM12_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	1347	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	1348	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
lypinator	0:bb348c97df44	1349	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	1350	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
lypinator	0:bb348c97df44	1351	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	1352	} while(0U)
lypinator	0:bb348c97df44	1353	#define __HAL_RCC_TIM13_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	1354	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	1355	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
lypinator	0:bb348c97df44	1356	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	1357	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
lypinator	0:bb348c97df44	1358	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	1359	} while(0U)
lypinator	0:bb348c97df44	1360	#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	1361	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	1362	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
lypinator	0:bb348c97df44	1363	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	1364	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
lypinator	0:bb348c97df44	1365	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	1366	} while(0U)
lypinator	0:bb348c97df44	1367	#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	1368	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	1369	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
lypinator	0:bb348c97df44	1370	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	1371	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
lypinator	0:bb348c97df44	1372	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	1373	} while(0U)
lypinator	0:bb348c97df44	1374	#define __HAL_RCC_USART3_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	1375	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	1376	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
lypinator	0:bb348c97df44	1377	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	1378	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
lypinator	0:bb348c97df44	1379	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	1380	} while(0U)
lypinator	0:bb348c97df44	1381	#define __HAL_RCC_UART4_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	1382	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	1383	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
lypinator	0:bb348c97df44	1384	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	1385	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
lypinator	0:bb348c97df44	1386	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	1387	} while(0U)
lypinator	0:bb348c97df44	1388	#define __HAL_RCC_UART5_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	1389	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	1390	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
lypinator	0:bb348c97df44	1391	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	1392	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
lypinator	0:bb348c97df44	1393	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	1394	} while(0U)
lypinator	0:bb348c97df44	1395	#define __HAL_RCC_CAN1_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	1396	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	1397	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
lypinator	0:bb348c97df44	1398	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	1399	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
lypinator	0:bb348c97df44	1400	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	1401	} while(0U)
lypinator	0:bb348c97df44	1402	#define __HAL_RCC_CAN2_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	1403	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	1404	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
lypinator	0:bb348c97df44	1405	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	1406	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
lypinator	0:bb348c97df44	1407	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	1408	} while(0U)
lypinator	0:bb348c97df44	1409	#define __HAL_RCC_DAC_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	1410	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	1411	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
lypinator	0:bb348c97df44	1412	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	1413	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
lypinator	0:bb348c97df44	1414	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	1415	} while(0U)
lypinator	0:bb348c97df44	1416	#define __HAL_RCC_UART7_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	1417	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	1418	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
lypinator	0:bb348c97df44	1419	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	1420	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
lypinator	0:bb348c97df44	1421	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	1422	} while(0U)
lypinator	0:bb348c97df44	1423	#define __HAL_RCC_UART8_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	1424	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	1425	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
lypinator	0:bb348c97df44	1426	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	1427	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
lypinator	0:bb348c97df44	1428	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	1429	} while(0U)
lypinator	0:bb348c97df44	1430	#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	1431	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	1432	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
lypinator	0:bb348c97df44	1433	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	1434	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
lypinator	0:bb348c97df44	1435	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	1436	} while(0U)
lypinator	0:bb348c97df44	1437	#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	1438	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	1439	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
lypinator	0:bb348c97df44	1440	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	1441	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
lypinator	0:bb348c97df44	1442	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	1443	} while(0U)
lypinator	0:bb348c97df44	1444	#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	1445	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	1446	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
lypinator	0:bb348c97df44	1447	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	1448	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
lypinator	0:bb348c97df44	1449	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	1450	} while(0U)
lypinator	0:bb348c97df44	1451	#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	1452	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	1453	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
lypinator	0:bb348c97df44	1454	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	1455	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
lypinator	0:bb348c97df44	1456	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	1457	} while(0U)
lypinator	0:bb348c97df44	1458	#define __HAL_RCC_I2C3_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	1459	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	1460	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
lypinator	0:bb348c97df44	1461	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	1462	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
lypinator	0:bb348c97df44	1463	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	1464	} while(0U)
lypinator	0:bb348c97df44	1465	#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
lypinator	0:bb348c97df44	1466	#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
lypinator	0:bb348c97df44	1467	#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
lypinator	0:bb348c97df44	1468	#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
lypinator	0:bb348c97df44	1469	#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
lypinator	0:bb348c97df44	1470	#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
lypinator	0:bb348c97df44	1471	#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
lypinator	0:bb348c97df44	1472	#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
lypinator	0:bb348c97df44	1473	#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
lypinator	0:bb348c97df44	1474	#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
lypinator	0:bb348c97df44	1475	#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
lypinator	0:bb348c97df44	1476	#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
lypinator	0:bb348c97df44	1477	#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
lypinator	0:bb348c97df44	1478	#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
lypinator	0:bb348c97df44	1479	#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
lypinator	0:bb348c97df44	1480	#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
lypinator	0:bb348c97df44	1481	#define __HAL_RCC_UART7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN))
lypinator	0:bb348c97df44	1482	#define __HAL_RCC_UART8_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN))
lypinator	0:bb348c97df44	1483	/**
lypinator	0:bb348c97df44	1484	* @}
lypinator	0:bb348c97df44	1485	*/
lypinator	0:bb348c97df44	1486
lypinator	0:bb348c97df44	1487	/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
lypinator	0:bb348c97df44	1488	* @brief Get the enable or disable status of the APB1 peripheral clock.
lypinator	0:bb348c97df44	1489	* @note After reset, the peripheral clock (used for registers read/write access)
lypinator	0:bb348c97df44	1490	* is disabled and the application software has to enable this clock before
lypinator	0:bb348c97df44	1491	* using it.
lypinator	0:bb348c97df44	1492	* @{
lypinator	0:bb348c97df44	1493	*/
lypinator	0:bb348c97df44	1494	#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
lypinator	0:bb348c97df44	1495	#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
lypinator	0:bb348c97df44	1496	#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
lypinator	0:bb348c97df44	1497	#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
lypinator	0:bb348c97df44	1498	#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
lypinator	0:bb348c97df44	1499	#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
lypinator	0:bb348c97df44	1500	#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
lypinator	0:bb348c97df44	1501	#define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
lypinator	0:bb348c97df44	1502	#define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
lypinator	0:bb348c97df44	1503	#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
lypinator	0:bb348c97df44	1504	#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
lypinator	0:bb348c97df44	1505	#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
lypinator	0:bb348c97df44	1506	#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
lypinator	0:bb348c97df44	1507	#define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET)
lypinator	0:bb348c97df44	1508	#define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)
lypinator	0:bb348c97df44	1509	#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
lypinator	0:bb348c97df44	1510	#define __HAL_RCC_UART7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) != RESET)
lypinator	0:bb348c97df44	1511	#define __HAL_RCC_UART8_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) != RESET)
lypinator	0:bb348c97df44	1512
lypinator	0:bb348c97df44	1513	#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
lypinator	0:bb348c97df44	1514	#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
lypinator	0:bb348c97df44	1515	#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
lypinator	0:bb348c97df44	1516	#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
lypinator	0:bb348c97df44	1517	#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
lypinator	0:bb348c97df44	1518	#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
lypinator	0:bb348c97df44	1519	#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
lypinator	0:bb348c97df44	1520	#define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
lypinator	0:bb348c97df44	1521	#define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
lypinator	0:bb348c97df44	1522	#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
lypinator	0:bb348c97df44	1523	#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
lypinator	0:bb348c97df44	1524	#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
lypinator	0:bb348c97df44	1525	#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
lypinator	0:bb348c97df44	1526	#define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
lypinator	0:bb348c97df44	1527	#define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)
lypinator	0:bb348c97df44	1528	#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
lypinator	0:bb348c97df44	1529	#define __HAL_RCC_UART7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) == RESET)
lypinator	0:bb348c97df44	1530	#define __HAL_RCC_UART8_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) == RESET)
lypinator	0:bb348c97df44	1531	/**
lypinator	0:bb348c97df44	1532	* @}
lypinator	0:bb348c97df44	1533	*/
lypinator	0:bb348c97df44	1534
lypinator	0:bb348c97df44	1535	/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
lypinator	0:bb348c97df44	1536	* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
lypinator	0:bb348c97df44	1537	* @note After reset, the peripheral clock (used for registers read/write access)
lypinator	0:bb348c97df44	1538	* is disabled and the application software has to enable this clock before
lypinator	0:bb348c97df44	1539	* using it.
lypinator	0:bb348c97df44	1540	* @{
lypinator	0:bb348c97df44	1541	*/
lypinator	0:bb348c97df44	1542	#define __HAL_RCC_TIM8_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	1543	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	1544	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
lypinator	0:bb348c97df44	1545	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	1546	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
lypinator	0:bb348c97df44	1547	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	1548	} while(0U)
lypinator	0:bb348c97df44	1549	#define __HAL_RCC_ADC2_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	1550	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	1551	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
lypinator	0:bb348c97df44	1552	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	1553	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
lypinator	0:bb348c97df44	1554	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	1555	} while(0U)
lypinator	0:bb348c97df44	1556	#define __HAL_RCC_ADC3_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	1557	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	1558	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
lypinator	0:bb348c97df44	1559	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	1560	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
lypinator	0:bb348c97df44	1561	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	1562	} while(0U)
lypinator	0:bb348c97df44	1563	#define __HAL_RCC_SPI5_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	1564	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	1565	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
lypinator	0:bb348c97df44	1566	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	1567	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
lypinator	0:bb348c97df44	1568	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	1569	} while(0U)
lypinator	0:bb348c97df44	1570	#define __HAL_RCC_SPI6_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	1571	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	1572	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\
lypinator	0:bb348c97df44	1573	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	1574	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\
lypinator	0:bb348c97df44	1575	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	1576	} while(0U)
lypinator	0:bb348c97df44	1577	#define __HAL_RCC_SAI1_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	1578	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	1579	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
lypinator	0:bb348c97df44	1580	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	1581	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
lypinator	0:bb348c97df44	1582	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	1583	} while(0U)
lypinator	0:bb348c97df44	1584	#define __HAL_RCC_SDIO_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	1585	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	1586	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
lypinator	0:bb348c97df44	1587	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	1588	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
lypinator	0:bb348c97df44	1589	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	1590	} while(0U)
lypinator	0:bb348c97df44	1591	#define __HAL_RCC_SPI4_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	1592	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	1593	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
lypinator	0:bb348c97df44	1594	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	1595	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
lypinator	0:bb348c97df44	1596	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	1597	} while(0U)
lypinator	0:bb348c97df44	1598	#define __HAL_RCC_TIM10_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	1599	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	1600	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
lypinator	0:bb348c97df44	1601	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	1602	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
lypinator	0:bb348c97df44	1603	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	1604	} while(0U)
lypinator	0:bb348c97df44	1605	#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
lypinator	0:bb348c97df44	1606	#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
lypinator	0:bb348c97df44	1607	#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
lypinator	0:bb348c97df44	1608	#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
lypinator	0:bb348c97df44	1609	#define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
lypinator	0:bb348c97df44	1610	#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
lypinator	0:bb348c97df44	1611	#define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
lypinator	0:bb348c97df44	1612	#define __HAL_RCC_SPI6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN))
lypinator	0:bb348c97df44	1613	#define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))
lypinator	0:bb348c97df44	1614
lypinator	0:bb348c97df44	1615	#if defined(STM32F429xx)\|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
lypinator	0:bb348c97df44	1616	#define __HAL_RCC_LTDC_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	1617	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	1618	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\
lypinator	0:bb348c97df44	1619	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	1620	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\
lypinator	0:bb348c97df44	1621	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	1622	} while(0U)
lypinator	0:bb348c97df44	1623
lypinator	0:bb348c97df44	1624	#define __HAL_RCC_LTDC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_LTDCEN))
lypinator	0:bb348c97df44	1625	#endif /* STM32F429xx \|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
lypinator	0:bb348c97df44	1626
lypinator	0:bb348c97df44	1627	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
lypinator	0:bb348c97df44	1628	#define __HAL_RCC_DSI_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	1629	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	1630	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\
lypinator	0:bb348c97df44	1631	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	1632	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\
lypinator	0:bb348c97df44	1633	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	1634	} while(0U)
lypinator	0:bb348c97df44	1635
lypinator	0:bb348c97df44	1636	#define __HAL_RCC_DSI_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DSIEN))
lypinator	0:bb348c97df44	1637	#endif /* STM32F469xx \|\| STM32F479xx */
lypinator	0:bb348c97df44	1638	/**
lypinator	0:bb348c97df44	1639	* @}
lypinator	0:bb348c97df44	1640	*/
lypinator	0:bb348c97df44	1641
lypinator	0:bb348c97df44	1642	/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
lypinator	0:bb348c97df44	1643	* @brief Get the enable or disable status of the APB2 peripheral clock.
lypinator	0:bb348c97df44	1644	* @note After reset, the peripheral clock (used for registers read/write access)
lypinator	0:bb348c97df44	1645	* is disabled and the application software has to enable this clock before
lypinator	0:bb348c97df44	1646	* using it.
lypinator	0:bb348c97df44	1647	* @{
lypinator	0:bb348c97df44	1648	*/
lypinator	0:bb348c97df44	1649	#define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)
lypinator	0:bb348c97df44	1650	#define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET)
lypinator	0:bb348c97df44	1651	#define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET)
lypinator	0:bb348c97df44	1652	#define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET)
lypinator	0:bb348c97df44	1653	#define __HAL_RCC_SPI6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) != RESET)
lypinator	0:bb348c97df44	1654	#define __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET)
lypinator	0:bb348c97df44	1655	#define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET)
lypinator	0:bb348c97df44	1656	#define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)
lypinator	0:bb348c97df44	1657	#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN))!= RESET)
lypinator	0:bb348c97df44	1658
lypinator	0:bb348c97df44	1659	#define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET)
lypinator	0:bb348c97df44	1660	#define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
lypinator	0:bb348c97df44	1661	#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN))== RESET)
lypinator	0:bb348c97df44	1662	#define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)
lypinator	0:bb348c97df44	1663	#define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET)
lypinator	0:bb348c97df44	1664	#define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET)
lypinator	0:bb348c97df44	1665	#define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET)
lypinator	0:bb348c97df44	1666	#define __HAL_RCC_SPI6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) == RESET)
lypinator	0:bb348c97df44	1667	#define __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET)
lypinator	0:bb348c97df44	1668
lypinator	0:bb348c97df44	1669	#if defined(STM32F429xx)\|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
lypinator	0:bb348c97df44	1670	#define __HAL_RCC_LTDC_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) != RESET)
lypinator	0:bb348c97df44	1671	#define __HAL_RCC_LTDC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) == RESET)
lypinator	0:bb348c97df44	1672	#endif /* STM32F429xx \|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
lypinator	0:bb348c97df44	1673
lypinator	0:bb348c97df44	1674	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
lypinator	0:bb348c97df44	1675	#define __HAL_RCC_DSI_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) != RESET)
lypinator	0:bb348c97df44	1676	#define __HAL_RCC_DSI_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) == RESET)
lypinator	0:bb348c97df44	1677	#endif /* STM32F469xx \|\| STM32F479xx */
lypinator	0:bb348c97df44	1678	/**
lypinator	0:bb348c97df44	1679	* @}
lypinator	0:bb348c97df44	1680	*/
lypinator	0:bb348c97df44	1681
lypinator	0:bb348c97df44	1682	/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset
lypinator	0:bb348c97df44	1683	* @brief Force or release AHB1 peripheral reset.
lypinator	0:bb348c97df44	1684	* @{
lypinator	0:bb348c97df44	1685	*/
lypinator	0:bb348c97df44	1686	#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIODRST))
lypinator	0:bb348c97df44	1687	#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOERST))
lypinator	0:bb348c97df44	1688	#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOFRST))
lypinator	0:bb348c97df44	1689	#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOGRST))
lypinator	0:bb348c97df44	1690	#define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOIRST))
lypinator	0:bb348c97df44	1691	#define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_ETHMACRST))
lypinator	0:bb348c97df44	1692	#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_OTGHRST))
lypinator	0:bb348c97df44	1693	#define __HAL_RCC_GPIOJ_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOJRST))
lypinator	0:bb348c97df44	1694	#define __HAL_RCC_GPIOK_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOKRST))
lypinator	0:bb348c97df44	1695	#define __HAL_RCC_DMA2D_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_DMA2DRST))
lypinator	0:bb348c97df44	1696	#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_CRCRST))
lypinator	0:bb348c97df44	1697
lypinator	0:bb348c97df44	1698	#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
lypinator	0:bb348c97df44	1699	#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
lypinator	0:bb348c97df44	1700	#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
lypinator	0:bb348c97df44	1701	#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
lypinator	0:bb348c97df44	1702	#define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
lypinator	0:bb348c97df44	1703	#define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))
lypinator	0:bb348c97df44	1704	#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
lypinator	0:bb348c97df44	1705	#define __HAL_RCC_GPIOJ_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOJRST))
lypinator	0:bb348c97df44	1706	#define __HAL_RCC_GPIOK_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOKRST))
lypinator	0:bb348c97df44	1707	#define __HAL_RCC_DMA2D_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2DRST))
lypinator	0:bb348c97df44	1708	#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
lypinator	0:bb348c97df44	1709	/**
lypinator	0:bb348c97df44	1710	* @}
lypinator	0:bb348c97df44	1711	*/
lypinator	0:bb348c97df44	1712
lypinator	0:bb348c97df44	1713	/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset
lypinator	0:bb348c97df44	1714	* @brief Force or release AHB2 peripheral reset.
lypinator	0:bb348c97df44	1715	* @{
lypinator	0:bb348c97df44	1716	*/
lypinator	0:bb348c97df44	1717	#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU)
lypinator	0:bb348c97df44	1718	#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_OTGFSRST))
lypinator	0:bb348c97df44	1719	#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_RNGRST))
lypinator	0:bb348c97df44	1720	#define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_DCMIRST))
lypinator	0:bb348c97df44	1721
lypinator	0:bb348c97df44	1722	#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U)
lypinator	0:bb348c97df44	1723	#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
lypinator	0:bb348c97df44	1724	#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
lypinator	0:bb348c97df44	1725	#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
lypinator	0:bb348c97df44	1726
lypinator	0:bb348c97df44	1727	#if defined(STM32F437xx)\|\| defined(STM32F439xx) \|\| defined(STM32F479xx)
lypinator	0:bb348c97df44	1728	#define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_CRYPRST))
lypinator	0:bb348c97df44	1729	#define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_HASHRST))
lypinator	0:bb348c97df44	1730
lypinator	0:bb348c97df44	1731	#define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST))
lypinator	0:bb348c97df44	1732	#define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST))
lypinator	0:bb348c97df44	1733	#endif /* STM32F437xx \|\| STM32F439xx \|\| STM32F479xx */
lypinator	0:bb348c97df44	1734	/**
lypinator	0:bb348c97df44	1735	* @}
lypinator	0:bb348c97df44	1736	*/
lypinator	0:bb348c97df44	1737
lypinator	0:bb348c97df44	1738	/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset
lypinator	0:bb348c97df44	1739	* @brief Force or release AHB3 peripheral reset.
lypinator	0:bb348c97df44	1740	* @{
lypinator	0:bb348c97df44	1741	*/
lypinator	0:bb348c97df44	1742	#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
lypinator	0:bb348c97df44	1743	#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U)
lypinator	0:bb348c97df44	1744	#define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR \|= (RCC_AHB3RSTR_FMCRST))
lypinator	0:bb348c97df44	1745	#define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST))
lypinator	0:bb348c97df44	1746
lypinator	0:bb348c97df44	1747	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
lypinator	0:bb348c97df44	1748	#define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR \|= (RCC_AHB3RSTR_QSPIRST))
lypinator	0:bb348c97df44	1749	#define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST))
lypinator	0:bb348c97df44	1750	#endif /* STM32F469xx \|\| STM32F479xx */
lypinator	0:bb348c97df44	1751	/**
lypinator	0:bb348c97df44	1752	* @}
lypinator	0:bb348c97df44	1753	*/
lypinator	0:bb348c97df44	1754
lypinator	0:bb348c97df44	1755	/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset
lypinator	0:bb348c97df44	1756	* @brief Force or release APB1 peripheral reset.
lypinator	0:bb348c97df44	1757	* @{
lypinator	0:bb348c97df44	1758	*/
lypinator	0:bb348c97df44	1759	#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM6RST))
lypinator	0:bb348c97df44	1760	#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM7RST))
lypinator	0:bb348c97df44	1761	#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM12RST))
lypinator	0:bb348c97df44	1762	#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM13RST))
lypinator	0:bb348c97df44	1763	#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM14RST))
lypinator	0:bb348c97df44	1764	#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART3RST))
lypinator	0:bb348c97df44	1765	#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART4RST))
lypinator	0:bb348c97df44	1766	#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART5RST))
lypinator	0:bb348c97df44	1767	#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN1RST))
lypinator	0:bb348c97df44	1768	#define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN2RST))
lypinator	0:bb348c97df44	1769	#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DACRST))
lypinator	0:bb348c97df44	1770	#define __HAL_RCC_UART7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART7RST))
lypinator	0:bb348c97df44	1771	#define __HAL_RCC_UART8_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART8RST))
lypinator	0:bb348c97df44	1772	#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM2RST))
lypinator	0:bb348c97df44	1773	#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM3RST))
lypinator	0:bb348c97df44	1774	#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM4RST))
lypinator	0:bb348c97df44	1775	#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI3RST))
lypinator	0:bb348c97df44	1776	#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C3RST))
lypinator	0:bb348c97df44	1777
lypinator	0:bb348c97df44	1778	#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
lypinator	0:bb348c97df44	1779	#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
lypinator	0:bb348c97df44	1780	#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
lypinator	0:bb348c97df44	1781	#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
lypinator	0:bb348c97df44	1782	#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
lypinator	0:bb348c97df44	1783	#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
lypinator	0:bb348c97df44	1784	#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
lypinator	0:bb348c97df44	1785	#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
lypinator	0:bb348c97df44	1786	#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
lypinator	0:bb348c97df44	1787	#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
lypinator	0:bb348c97df44	1788	#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
lypinator	0:bb348c97df44	1789	#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
lypinator	0:bb348c97df44	1790	#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
lypinator	0:bb348c97df44	1791	#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
lypinator	0:bb348c97df44	1792	#define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
lypinator	0:bb348c97df44	1793	#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
lypinator	0:bb348c97df44	1794	#define __HAL_RCC_UART7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST))
lypinator	0:bb348c97df44	1795	#define __HAL_RCC_UART8_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST))
lypinator	0:bb348c97df44	1796	/**
lypinator	0:bb348c97df44	1797	* @}
lypinator	0:bb348c97df44	1798	*/
lypinator	0:bb348c97df44	1799
lypinator	0:bb348c97df44	1800	/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
lypinator	0:bb348c97df44	1801	* @brief Force or release APB2 peripheral reset.
lypinator	0:bb348c97df44	1802	* @{
lypinator	0:bb348c97df44	1803	*/
lypinator	0:bb348c97df44	1804	#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM8RST))
lypinator	0:bb348c97df44	1805	#define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI5RST))
lypinator	0:bb348c97df44	1806	#define __HAL_RCC_SPI6_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI6RST))
lypinator	0:bb348c97df44	1807	#define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SAI1RST))
lypinator	0:bb348c97df44	1808	#define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SDIORST))
lypinator	0:bb348c97df44	1809	#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI4RST))
lypinator	0:bb348c97df44	1810	#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM10RST))
lypinator	0:bb348c97df44	1811
lypinator	0:bb348c97df44	1812	#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
lypinator	0:bb348c97df44	1813	#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
lypinator	0:bb348c97df44	1814	#define __HAL_RCC_TIM10_RELEASE_RESET()(RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
lypinator	0:bb348c97df44	1815	#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
lypinator	0:bb348c97df44	1816	#define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
lypinator	0:bb348c97df44	1817	#define __HAL_RCC_SPI6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI6RST))
lypinator	0:bb348c97df44	1818	#define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))
lypinator	0:bb348c97df44	1819
lypinator	0:bb348c97df44	1820	#if defined(STM32F429xx)\|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
lypinator	0:bb348c97df44	1821	#define __HAL_RCC_LTDC_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_LTDCRST))
lypinator	0:bb348c97df44	1822	#define __HAL_RCC_LTDC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_LTDCRST))
lypinator	0:bb348c97df44	1823	#endif /* STM32F429xx\|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
lypinator	0:bb348c97df44	1824
lypinator	0:bb348c97df44	1825	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
lypinator	0:bb348c97df44	1826	#define __HAL_RCC_DSI_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_DSIRST))
lypinator	0:bb348c97df44	1827	#define __HAL_RCC_DSI_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DSIRST))
lypinator	0:bb348c97df44	1828	#endif /* STM32F469xx \|\| STM32F479xx */
lypinator	0:bb348c97df44	1829	/**
lypinator	0:bb348c97df44	1830	* @}
lypinator	0:bb348c97df44	1831	*/
lypinator	0:bb348c97df44	1832
lypinator	0:bb348c97df44	1833	/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
lypinator	0:bb348c97df44	1834	* @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
lypinator	0:bb348c97df44	1835	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
lypinator	0:bb348c97df44	1836	* power consumption.
lypinator	0:bb348c97df44	1837	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
lypinator	0:bb348c97df44	1838	* @note By default, all peripheral clocks are enabled during SLEEP mode.
lypinator	0:bb348c97df44	1839	* @{
lypinator	0:bb348c97df44	1840	*/
lypinator	0:bb348c97df44	1841	#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIODLPEN))
lypinator	0:bb348c97df44	1842	#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOELPEN))
lypinator	0:bb348c97df44	1843	#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOFLPEN))
lypinator	0:bb348c97df44	1844	#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOGLPEN))
lypinator	0:bb348c97df44	1845	#define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOILPEN))
lypinator	0:bb348c97df44	1846	#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM2LPEN))
lypinator	0:bb348c97df44	1847	#define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACLPEN))
lypinator	0:bb348c97df44	1848	#define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACTXLPEN))
lypinator	0:bb348c97df44	1849	#define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACRXLPEN))
lypinator	0:bb348c97df44	1850	#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACPTPLPEN))
lypinator	0:bb348c97df44	1851	#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_OTGHSLPEN))
lypinator	0:bb348c97df44	1852	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_OTGHSULPILPEN))
lypinator	0:bb348c97df44	1853	#define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOJLPEN))
lypinator	0:bb348c97df44	1854	#define __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOKLPEN))
lypinator	0:bb348c97df44	1855	#define __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM3LPEN))
lypinator	0:bb348c97df44	1856	#define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_DMA2DLPEN))
lypinator	0:bb348c97df44	1857	#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_CRCLPEN))
lypinator	0:bb348c97df44	1858	#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_FLITFLPEN))
lypinator	0:bb348c97df44	1859	#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM1LPEN))
lypinator	0:bb348c97df44	1860	#define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_BKPSRAMLPEN))
lypinator	0:bb348c97df44	1861
lypinator	0:bb348c97df44	1862	#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
lypinator	0:bb348c97df44	1863	#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
lypinator	0:bb348c97df44	1864	#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
lypinator	0:bb348c97df44	1865	#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
lypinator	0:bb348c97df44	1866	#define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN))
lypinator	0:bb348c97df44	1867	#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
lypinator	0:bb348c97df44	1868	#define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN))
lypinator	0:bb348c97df44	1869	#define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))
lypinator	0:bb348c97df44	1870	#define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))
lypinator	0:bb348c97df44	1871	#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))
lypinator	0:bb348c97df44	1872	#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
lypinator	0:bb348c97df44	1873	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
lypinator	0:bb348c97df44	1874	#define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOJLPEN))
lypinator	0:bb348c97df44	1875	#define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOKLPEN))
lypinator	0:bb348c97df44	1876	#define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2DLPEN))
lypinator	0:bb348c97df44	1877	#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
lypinator	0:bb348c97df44	1878	#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
lypinator	0:bb348c97df44	1879	#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
lypinator	0:bb348c97df44	1880	#define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))
lypinator	0:bb348c97df44	1881	/**
lypinator	0:bb348c97df44	1882	* @}
lypinator	0:bb348c97df44	1883	*/
lypinator	0:bb348c97df44	1884
lypinator	0:bb348c97df44	1885	/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
lypinator	0:bb348c97df44	1886	* @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
lypinator	0:bb348c97df44	1887	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
lypinator	0:bb348c97df44	1888	* power consumption.
lypinator	0:bb348c97df44	1889	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
lypinator	0:bb348c97df44	1890	* @note By default, all peripheral clocks are enabled during SLEEP mode.
lypinator	0:bb348c97df44	1891	* @{
lypinator	0:bb348c97df44	1892	*/
lypinator	0:bb348c97df44	1893	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_OTGFSLPEN))
lypinator	0:bb348c97df44	1894	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
lypinator	0:bb348c97df44	1895
lypinator	0:bb348c97df44	1896	#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_RNGLPEN))
lypinator	0:bb348c97df44	1897	#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
lypinator	0:bb348c97df44	1898
lypinator	0:bb348c97df44	1899	#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_DCMILPEN))
lypinator	0:bb348c97df44	1900	#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
lypinator	0:bb348c97df44	1901
lypinator	0:bb348c97df44	1902	#if defined(STM32F437xx)\|\| defined(STM32F439xx) \|\| defined(STM32F479xx)
lypinator	0:bb348c97df44	1903	#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_CRYPLPEN))
lypinator	0:bb348c97df44	1904	#define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_HASHLPEN))
lypinator	0:bb348c97df44	1905
lypinator	0:bb348c97df44	1906	#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN))
lypinator	0:bb348c97df44	1907	#define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN))
lypinator	0:bb348c97df44	1908	#endif /* STM32F437xx \|\| STM32F439xx \|\| STM32F479xx */
lypinator	0:bb348c97df44	1909	/**
lypinator	0:bb348c97df44	1910	* @}
lypinator	0:bb348c97df44	1911	*/
lypinator	0:bb348c97df44	1912
lypinator	0:bb348c97df44	1913	/** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable
lypinator	0:bb348c97df44	1914	* @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
lypinator	0:bb348c97df44	1915	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
lypinator	0:bb348c97df44	1916	* power consumption.
lypinator	0:bb348c97df44	1917	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
lypinator	0:bb348c97df44	1918	* @note By default, all peripheral clocks are enabled during SLEEP mode.
lypinator	0:bb348c97df44	1919	* @{
lypinator	0:bb348c97df44	1920	*/
lypinator	0:bb348c97df44	1921	#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_FMCLPEN))
lypinator	0:bb348c97df44	1922	#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN))
lypinator	0:bb348c97df44	1923
lypinator	0:bb348c97df44	1924	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
lypinator	0:bb348c97df44	1925	#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_QSPILPEN))
lypinator	0:bb348c97df44	1926	#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN))
lypinator	0:bb348c97df44	1927	#endif /* STM32F469xx \|\| STM32F479xx */
lypinator	0:bb348c97df44	1928	/**
lypinator	0:bb348c97df44	1929	* @}
lypinator	0:bb348c97df44	1930	*/
lypinator	0:bb348c97df44	1931
lypinator	0:bb348c97df44	1932	/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
lypinator	0:bb348c97df44	1933	* @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
lypinator	0:bb348c97df44	1934	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
lypinator	0:bb348c97df44	1935	* power consumption.
lypinator	0:bb348c97df44	1936	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
lypinator	0:bb348c97df44	1937	* @note By default, all peripheral clocks are enabled during SLEEP mode.
lypinator	0:bb348c97df44	1938	* @{
lypinator	0:bb348c97df44	1939	*/
lypinator	0:bb348c97df44	1940	#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM6LPEN))
lypinator	0:bb348c97df44	1941	#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM7LPEN))
lypinator	0:bb348c97df44	1942	#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM12LPEN))
lypinator	0:bb348c97df44	1943	#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM13LPEN))
lypinator	0:bb348c97df44	1944	#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM14LPEN))
lypinator	0:bb348c97df44	1945	#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_USART3LPEN))
lypinator	0:bb348c97df44	1946	#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART4LPEN))
lypinator	0:bb348c97df44	1947	#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART5LPEN))
lypinator	0:bb348c97df44	1948	#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN1LPEN))
lypinator	0:bb348c97df44	1949	#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN2LPEN))
lypinator	0:bb348c97df44	1950	#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_DACLPEN))
lypinator	0:bb348c97df44	1951	#define __HAL_RCC_UART7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART7LPEN))
lypinator	0:bb348c97df44	1952	#define __HAL_RCC_UART8_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART8LPEN))
lypinator	0:bb348c97df44	1953	#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM2LPEN))
lypinator	0:bb348c97df44	1954	#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM3LPEN))
lypinator	0:bb348c97df44	1955	#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM4LPEN))
lypinator	0:bb348c97df44	1956	#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_SPI3LPEN))
lypinator	0:bb348c97df44	1957	#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C3LPEN))
lypinator	0:bb348c97df44	1958
lypinator	0:bb348c97df44	1959	#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
lypinator	0:bb348c97df44	1960	#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
lypinator	0:bb348c97df44	1961	#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
lypinator	0:bb348c97df44	1962	#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
lypinator	0:bb348c97df44	1963	#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
lypinator	0:bb348c97df44	1964	#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
lypinator	0:bb348c97df44	1965	#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
lypinator	0:bb348c97df44	1966	#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
lypinator	0:bb348c97df44	1967	#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
lypinator	0:bb348c97df44	1968	#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
lypinator	0:bb348c97df44	1969	#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
lypinator	0:bb348c97df44	1970	#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
lypinator	0:bb348c97df44	1971	#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
lypinator	0:bb348c97df44	1972	#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
lypinator	0:bb348c97df44	1973	#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
lypinator	0:bb348c97df44	1974	#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
lypinator	0:bb348c97df44	1975	#define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN))
lypinator	0:bb348c97df44	1976	#define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN))
lypinator	0:bb348c97df44	1977	/**
lypinator	0:bb348c97df44	1978	* @}
lypinator	0:bb348c97df44	1979	*/
lypinator	0:bb348c97df44	1980
lypinator	0:bb348c97df44	1981	/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
lypinator	0:bb348c97df44	1982	* @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
lypinator	0:bb348c97df44	1983	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
lypinator	0:bb348c97df44	1984	* power consumption.
lypinator	0:bb348c97df44	1985	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
lypinator	0:bb348c97df44	1986	* @note By default, all peripheral clocks are enabled during SLEEP mode.
lypinator	0:bb348c97df44	1987	* @{
lypinator	0:bb348c97df44	1988	*/
lypinator	0:bb348c97df44	1989	#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM8LPEN))
lypinator	0:bb348c97df44	1990	#define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC2LPEN))
lypinator	0:bb348c97df44	1991	#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC3LPEN))
lypinator	0:bb348c97df44	1992	#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI5LPEN))
lypinator	0:bb348c97df44	1993	#define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI6LPEN))
lypinator	0:bb348c97df44	1994	#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SAI1LPEN))
lypinator	0:bb348c97df44	1995	#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SDIOLPEN))
lypinator	0:bb348c97df44	1996	#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI4LPEN))
lypinator	0:bb348c97df44	1997	#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()(RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM10LPEN))
lypinator	0:bb348c97df44	1998
lypinator	0:bb348c97df44	1999	#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
lypinator	0:bb348c97df44	2000	#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
lypinator	0:bb348c97df44	2001	#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()(RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
lypinator	0:bb348c97df44	2002	#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
lypinator	0:bb348c97df44	2003	#define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
lypinator	0:bb348c97df44	2004	#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
lypinator	0:bb348c97df44	2005	#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
lypinator	0:bb348c97df44	2006	#define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI6LPEN))
lypinator	0:bb348c97df44	2007	#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN))
lypinator	0:bb348c97df44	2008
lypinator	0:bb348c97df44	2009	#if defined(STM32F429xx)\|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
lypinator	0:bb348c97df44	2010	#define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_LTDCLPEN))
lypinator	0:bb348c97df44	2011
lypinator	0:bb348c97df44	2012	#define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_LTDCLPEN))
lypinator	0:bb348c97df44	2013	#endif /* STM32F429xx \|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
lypinator	0:bb348c97df44	2014
lypinator	0:bb348c97df44	2015	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
lypinator	0:bb348c97df44	2016	#define __HAL_RCC_DSI_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_DSILPEN))
lypinator	0:bb348c97df44	2017	#define __HAL_RCC_DSI_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DSILPEN))
lypinator	0:bb348c97df44	2018	#endif /* STM32F469xx \|\| STM32F479xx */
lypinator	0:bb348c97df44	2019	/**
lypinator	0:bb348c97df44	2020	* @}
lypinator	0:bb348c97df44	2021	*/
lypinator	0:bb348c97df44	2022	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx\|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
lypinator	0:bb348c97df44	2023	/----------------------------------------------------------------------------/
lypinator	0:bb348c97df44	2024
lypinator	0:bb348c97df44	2025	/----------------------------------- STM32F40xxx/STM32F41xxx-----------------/
lypinator	0:bb348c97df44	2026	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx)\|\| defined(STM32F417xx)
lypinator	0:bb348c97df44	2027	/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
lypinator	0:bb348c97df44	2028	* @brief Enables or disables the AHB1 peripheral clock.
lypinator	0:bb348c97df44	2029	* @note After reset, the peripheral clock (used for registers read/write access)
lypinator	0:bb348c97df44	2030	* is disabled and the application software has to enable this clock before
lypinator	0:bb348c97df44	2031	* using it.
lypinator	0:bb348c97df44	2032	* @{
lypinator	0:bb348c97df44	2033	*/
lypinator	0:bb348c97df44	2034	#define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	2035	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	2036	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
lypinator	0:bb348c97df44	2037	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	2038	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
lypinator	0:bb348c97df44	2039	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	2040	} while(0U)
lypinator	0:bb348c97df44	2041	#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	2042	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	2043	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
lypinator	0:bb348c97df44	2044	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	2045	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
lypinator	0:bb348c97df44	2046	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	2047	} while(0U)
lypinator	0:bb348c97df44	2048	#define __HAL_RCC_CRC_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	2049	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	2050	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
lypinator	0:bb348c97df44	2051	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	2052	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
lypinator	0:bb348c97df44	2053	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	2054	} while(0U)
lypinator	0:bb348c97df44	2055	#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	2056	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	2057	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
lypinator	0:bb348c97df44	2058	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	2059	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
lypinator	0:bb348c97df44	2060	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	2061	} while(0U)
lypinator	0:bb348c97df44	2062	#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	2063	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	2064	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
lypinator	0:bb348c97df44	2065	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	2066	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
lypinator	0:bb348c97df44	2067	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	2068	} while(0U)
lypinator	0:bb348c97df44	2069	#define __HAL_RCC_GPIOI_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	2070	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	2071	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
lypinator	0:bb348c97df44	2072	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	2073	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
lypinator	0:bb348c97df44	2074	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	2075	} while(0U)
lypinator	0:bb348c97df44	2076	#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	2077	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	2078	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
lypinator	0:bb348c97df44	2079	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	2080	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
lypinator	0:bb348c97df44	2081	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	2082	} while(0U)
lypinator	0:bb348c97df44	2083	#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	2084	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	2085	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
lypinator	0:bb348c97df44	2086	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	2087	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
lypinator	0:bb348c97df44	2088	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	2089	} while(0U)
lypinator	0:bb348c97df44	2090	#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	2091	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	2092	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
lypinator	0:bb348c97df44	2093	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	2094	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
lypinator	0:bb348c97df44	2095	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	2096	} while(0U)
lypinator	0:bb348c97df44	2097	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	2098	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	2099	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
lypinator	0:bb348c97df44	2100	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	2101	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
lypinator	0:bb348c97df44	2102	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	2103	} while(0U)
lypinator	0:bb348c97df44	2104	#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
lypinator	0:bb348c97df44	2105	#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
lypinator	0:bb348c97df44	2106	#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
lypinator	0:bb348c97df44	2107	#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
lypinator	0:bb348c97df44	2108	#define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))
lypinator	0:bb348c97df44	2109	#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
lypinator	0:bb348c97df44	2110	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
lypinator	0:bb348c97df44	2111	#define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
lypinator	0:bb348c97df44	2112	#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
lypinator	0:bb348c97df44	2113	#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
lypinator	0:bb348c97df44	2114	#if defined(STM32F407xx)\|\| defined(STM32F417xx)
lypinator	0:bb348c97df44	2115	/**
lypinator	0:bb348c97df44	2116	* @brief Enable ETHERNET clock.
lypinator	0:bb348c97df44	2117	*/
lypinator	0:bb348c97df44	2118	#define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	2119	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	2120	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
lypinator	0:bb348c97df44	2121	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	2122	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
lypinator	0:bb348c97df44	2123	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	2124	} while(0U)
lypinator	0:bb348c97df44	2125	#define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	2126	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	2127	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
lypinator	0:bb348c97df44	2128	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	2129	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
lypinator	0:bb348c97df44	2130	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	2131	} while(0U)
lypinator	0:bb348c97df44	2132	#define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	2133	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	2134	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
lypinator	0:bb348c97df44	2135	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	2136	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
lypinator	0:bb348c97df44	2137	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	2138	} while(0U)
lypinator	0:bb348c97df44	2139	#define __HAL_RCC_ETHMACPTP_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	2140	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	2141	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
lypinator	0:bb348c97df44	2142	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	2143	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
lypinator	0:bb348c97df44	2144	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	2145	} while(0U)
lypinator	0:bb348c97df44	2146	#define __HAL_RCC_ETH_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	2147	__HAL_RCC_ETHMAC_CLK_ENABLE(); \
lypinator	0:bb348c97df44	2148	__HAL_RCC_ETHMACTX_CLK_ENABLE(); \
lypinator	0:bb348c97df44	2149	__HAL_RCC_ETHMACRX_CLK_ENABLE(); \
lypinator	0:bb348c97df44	2150	} while(0U)
lypinator	0:bb348c97df44	2151
lypinator	0:bb348c97df44	2152	/**
lypinator	0:bb348c97df44	2153	* @brief Disable ETHERNET clock.
lypinator	0:bb348c97df44	2154	*/
lypinator	0:bb348c97df44	2155	#define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))
lypinator	0:bb348c97df44	2156	#define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))
lypinator	0:bb348c97df44	2157	#define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))
lypinator	0:bb348c97df44	2158	#define __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))
lypinator	0:bb348c97df44	2159	#define __HAL_RCC_ETH_CLK_DISABLE() do { \
lypinator	0:bb348c97df44	2160	__HAL_RCC_ETHMACTX_CLK_DISABLE(); \
lypinator	0:bb348c97df44	2161	__HAL_RCC_ETHMACRX_CLK_DISABLE(); \
lypinator	0:bb348c97df44	2162	__HAL_RCC_ETHMAC_CLK_DISABLE(); \
lypinator	0:bb348c97df44	2163	} while(0U)
lypinator	0:bb348c97df44	2164	#endif /* STM32F407xx \|\| STM32F417xx */
lypinator	0:bb348c97df44	2165	/**
lypinator	0:bb348c97df44	2166	* @}
lypinator	0:bb348c97df44	2167	*/
lypinator	0:bb348c97df44	2168
lypinator	0:bb348c97df44	2169	/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
lypinator	0:bb348c97df44	2170	* @brief Get the enable or disable status of the AHB1 peripheral clock.
lypinator	0:bb348c97df44	2171	* @note After reset, the peripheral clock (used for registers read/write access)
lypinator	0:bb348c97df44	2172	* is disabled and the application software has to enable this clock before
lypinator	0:bb348c97df44	2173	* using it.
lypinator	0:bb348c97df44	2174	* @{
lypinator	0:bb348c97df44	2175	*/
lypinator	0:bb348c97df44	2176	#define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET)
lypinator	0:bb348c97df44	2177	#define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) != RESET)
lypinator	0:bb348c97df44	2178	#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
lypinator	0:bb348c97df44	2179	#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)
lypinator	0:bb348c97df44	2180	#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)
lypinator	0:bb348c97df44	2181	#define __HAL_RCC_GPIOI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) != RESET)
lypinator	0:bb348c97df44	2182	#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET)
lypinator	0:bb348c97df44	2183	#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET)
lypinator	0:bb348c97df44	2184	#define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET)
lypinator	0:bb348c97df44	2185	#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET)
lypinator	0:bb348c97df44	2186
lypinator	0:bb348c97df44	2187	#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)
lypinator	0:bb348c97df44	2188	#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)
lypinator	0:bb348c97df44	2189	#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET)
lypinator	0:bb348c97df44	2190	#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET)
lypinator	0:bb348c97df44	2191	#define __HAL_RCC_GPIOI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) == RESET)
lypinator	0:bb348c97df44	2192	#define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET)
lypinator	0:bb348c97df44	2193	#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN))== RESET)
lypinator	0:bb348c97df44	2194	#define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET)
lypinator	0:bb348c97df44	2195	#define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET)
lypinator	0:bb348c97df44	2196	#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
lypinator	0:bb348c97df44	2197	#if defined(STM32F407xx)\|\| defined(STM32F417xx)
lypinator	0:bb348c97df44	2198	/**
lypinator	0:bb348c97df44	2199	* @brief Enable ETHERNET clock.
lypinator	0:bb348c97df44	2200	*/
lypinator	0:bb348c97df44	2201	#define __HAL_RCC_ETHMAC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) != RESET)
lypinator	0:bb348c97df44	2202	#define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) != RESET)
lypinator	0:bb348c97df44	2203	#define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) != RESET)
lypinator	0:bb348c97df44	2204	#define __HAL_RCC_ETHMACPTP_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) != RESET)
lypinator	0:bb348c97df44	2205	#define __HAL_RCC_ETH_IS_CLK_ENABLED() (__HAL_RCC_ETHMAC_IS_CLK_ENABLED() && \
lypinator	0:bb348c97df44	2206	__HAL_RCC_ETHMACTX_IS_CLK_ENABLED() && \
lypinator	0:bb348c97df44	2207	__HAL_RCC_ETHMACRX_IS_CLK_ENABLED())
lypinator	0:bb348c97df44	2208	/**
lypinator	0:bb348c97df44	2209	* @brief Disable ETHERNET clock.
lypinator	0:bb348c97df44	2210	*/
lypinator	0:bb348c97df44	2211	#define __HAL_RCC_ETHMAC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) == RESET)
lypinator	0:bb348c97df44	2212	#define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) == RESET)
lypinator	0:bb348c97df44	2213	#define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) == RESET)
lypinator	0:bb348c97df44	2214	#define __HAL_RCC_ETHMACPTP_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) == RESET)
lypinator	0:bb348c97df44	2215	#define __HAL_RCC_ETH_IS_CLK_DISABLED() (__HAL_RCC_ETHMAC_IS_CLK_DISABLED() && \
lypinator	0:bb348c97df44	2216	__HAL_RCC_ETHMACTX_IS_CLK_DISABLED() && \
lypinator	0:bb348c97df44	2217	__HAL_RCC_ETHMACRX_IS_CLK_DISABLED())
lypinator	0:bb348c97df44	2218	#endif /* STM32F407xx \|\| STM32F417xx */
lypinator	0:bb348c97df44	2219	/**
lypinator	0:bb348c97df44	2220	* @}
lypinator	0:bb348c97df44	2221	*/
lypinator	0:bb348c97df44	2222
lypinator	0:bb348c97df44	2223	/** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
lypinator	0:bb348c97df44	2224	* @brief Enable or disable the AHB2 peripheral clock.
lypinator	0:bb348c97df44	2225	* @note After reset, the peripheral clock (used for registers read/write access)
lypinator	0:bb348c97df44	2226	* is disabled and the application software has to enable this clock before
lypinator	0:bb348c97df44	2227	* using it.
lypinator	0:bb348c97df44	2228	* @{
lypinator	0:bb348c97df44	2229	*/
lypinator	0:bb348c97df44	2230	#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR \|= (RCC_AHB2ENR_OTGFSEN));\
lypinator	0:bb348c97df44	2231	__HAL_RCC_SYSCFG_CLK_ENABLE();\
lypinator	0:bb348c97df44	2232	}while(0U)
lypinator	0:bb348c97df44	2233
lypinator	0:bb348c97df44	2234	#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
lypinator	0:bb348c97df44	2235
lypinator	0:bb348c97df44	2236	#define __HAL_RCC_RNG_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	2237	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	2238	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
lypinator	0:bb348c97df44	2239	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	2240	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
lypinator	0:bb348c97df44	2241	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	2242	} while(0U)
lypinator	0:bb348c97df44	2243	#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
lypinator	0:bb348c97df44	2244
lypinator	0:bb348c97df44	2245	#if defined(STM32F407xx)\|\| defined(STM32F417xx)
lypinator	0:bb348c97df44	2246	#define __HAL_RCC_DCMI_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	2247	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	2248	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
lypinator	0:bb348c97df44	2249	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	2250	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
lypinator	0:bb348c97df44	2251	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	2252	} while(0U)
lypinator	0:bb348c97df44	2253	#define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
lypinator	0:bb348c97df44	2254	#endif /* STM32F407xx \|\| STM32F417xx */
lypinator	0:bb348c97df44	2255
lypinator	0:bb348c97df44	2256	#if defined(STM32F415xx) \|\| defined(STM32F417xx)
lypinator	0:bb348c97df44	2257	#define __HAL_RCC_CRYP_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	2258	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	2259	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
lypinator	0:bb348c97df44	2260	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	2261	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
lypinator	0:bb348c97df44	2262	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	2263	} while(0U)
lypinator	0:bb348c97df44	2264	#define __HAL_RCC_HASH_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	2265	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	2266	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
lypinator	0:bb348c97df44	2267	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	2268	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
lypinator	0:bb348c97df44	2269	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	2270	} while(0U)
lypinator	0:bb348c97df44	2271	#define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))
lypinator	0:bb348c97df44	2272	#define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN))
lypinator	0:bb348c97df44	2273	#endif /* STM32F415xx \|\| STM32F417xx */
lypinator	0:bb348c97df44	2274	/**
lypinator	0:bb348c97df44	2275	* @}
lypinator	0:bb348c97df44	2276	*/
lypinator	0:bb348c97df44	2277
lypinator	0:bb348c97df44	2278
lypinator	0:bb348c97df44	2279	/** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status
lypinator	0:bb348c97df44	2280	* @brief Get the enable or disable status of the AHB2 peripheral clock.
lypinator	0:bb348c97df44	2281	* @note After reset, the peripheral clock (used for registers read/write access)
lypinator	0:bb348c97df44	2282	* is disabled and the application software has to enable this clock before
lypinator	0:bb348c97df44	2283	* using it.
lypinator	0:bb348c97df44	2284	* @{
lypinator	0:bb348c97df44	2285	*/
lypinator	0:bb348c97df44	2286	#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
lypinator	0:bb348c97df44	2287	#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
lypinator	0:bb348c97df44	2288
lypinator	0:bb348c97df44	2289	#define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET)
lypinator	0:bb348c97df44	2290	#define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET)
lypinator	0:bb348c97df44	2291
lypinator	0:bb348c97df44	2292	#if defined(STM32F407xx)\|\| defined(STM32F417xx)
lypinator	0:bb348c97df44	2293	#define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET)
lypinator	0:bb348c97df44	2294	#define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET)
lypinator	0:bb348c97df44	2295	#endif /* STM32F407xx \|\| STM32F417xx */
lypinator	0:bb348c97df44	2296
lypinator	0:bb348c97df44	2297	#if defined(STM32F415xx) \|\| defined(STM32F417xx)
lypinator	0:bb348c97df44	2298	#define __HAL_RCC_CRYP_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) != RESET)
lypinator	0:bb348c97df44	2299	#define __HAL_RCC_HASH_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) != RESET)
lypinator	0:bb348c97df44	2300
lypinator	0:bb348c97df44	2301	#define __HAL_RCC_CRYP_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) == RESET)
lypinator	0:bb348c97df44	2302	#define __HAL_RCC_HASH_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) == RESET)
lypinator	0:bb348c97df44	2303	#endif /* STM32F415xx \|\| STM32F417xx */
lypinator	0:bb348c97df44	2304	/**
lypinator	0:bb348c97df44	2305	* @}
lypinator	0:bb348c97df44	2306	*/
lypinator	0:bb348c97df44	2307
lypinator	0:bb348c97df44	2308	/** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable
lypinator	0:bb348c97df44	2309	* @brief Enables or disables the AHB3 peripheral clock.
lypinator	0:bb348c97df44	2310	* @note After reset, the peripheral clock (used for registers read/write access)
lypinator	0:bb348c97df44	2311	* is disabled and the application software has to enable this clock before
lypinator	0:bb348c97df44	2312	* using it.
lypinator	0:bb348c97df44	2313	* @{
lypinator	0:bb348c97df44	2314	*/
lypinator	0:bb348c97df44	2315	#define __HAL_RCC_FSMC_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	2316	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	2317	SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\
lypinator	0:bb348c97df44	2318	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	2319	tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\
lypinator	0:bb348c97df44	2320	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	2321	} while(0U)
lypinator	0:bb348c97df44	2322	#define __HAL_RCC_FSMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FSMCEN))
lypinator	0:bb348c97df44	2323	/**
lypinator	0:bb348c97df44	2324	* @}
lypinator	0:bb348c97df44	2325	*/
lypinator	0:bb348c97df44	2326
lypinator	0:bb348c97df44	2327	/** @defgroup RCCEx_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enable Disable Status
lypinator	0:bb348c97df44	2328	* @brief Get the enable or disable status of the AHB3 peripheral clock.
lypinator	0:bb348c97df44	2329	* @note After reset, the peripheral clock (used for registers read/write access)
lypinator	0:bb348c97df44	2330	* is disabled and the application software has to enable this clock before
lypinator	0:bb348c97df44	2331	* using it.
lypinator	0:bb348c97df44	2332	* @{
lypinator	0:bb348c97df44	2333	*/
lypinator	0:bb348c97df44	2334	#define __HAL_RCC_FSMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FSMCEN)) != RESET)
lypinator	0:bb348c97df44	2335	#define __HAL_RCC_FSMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FSMCEN)) == RESET)
lypinator	0:bb348c97df44	2336	/**
lypinator	0:bb348c97df44	2337	* @}
lypinator	0:bb348c97df44	2338	*/
lypinator	0:bb348c97df44	2339
lypinator	0:bb348c97df44	2340	/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
lypinator	0:bb348c97df44	2341	* @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
lypinator	0:bb348c97df44	2342	* @note After reset, the peripheral clock (used for registers read/write access)
lypinator	0:bb348c97df44	2343	* is disabled and the application software has to enable this clock before
lypinator	0:bb348c97df44	2344	* using it.
lypinator	0:bb348c97df44	2345	* @{
lypinator	0:bb348c97df44	2346	*/
lypinator	0:bb348c97df44	2347	#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	2348	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	2349	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
lypinator	0:bb348c97df44	2350	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	2351	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
lypinator	0:bb348c97df44	2352	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	2353	} while(0U)
lypinator	0:bb348c97df44	2354	#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	2355	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	2356	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
lypinator	0:bb348c97df44	2357	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	2358	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
lypinator	0:bb348c97df44	2359	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	2360	} while(0U)
lypinator	0:bb348c97df44	2361	#define __HAL_RCC_TIM12_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	2362	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	2363	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
lypinator	0:bb348c97df44	2364	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	2365	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
lypinator	0:bb348c97df44	2366	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	2367	} while(0U)
lypinator	0:bb348c97df44	2368	#define __HAL_RCC_TIM13_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	2369	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	2370	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
lypinator	0:bb348c97df44	2371	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	2372	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
lypinator	0:bb348c97df44	2373	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	2374	} while(0U)
lypinator	0:bb348c97df44	2375	#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	2376	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	2377	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
lypinator	0:bb348c97df44	2378	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	2379	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
lypinator	0:bb348c97df44	2380	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	2381	} while(0U)
lypinator	0:bb348c97df44	2382	#define __HAL_RCC_USART3_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	2383	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	2384	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
lypinator	0:bb348c97df44	2385	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	2386	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
lypinator	0:bb348c97df44	2387	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	2388	} while(0U)
lypinator	0:bb348c97df44	2389	#define __HAL_RCC_UART4_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	2390	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	2391	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
lypinator	0:bb348c97df44	2392	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	2393	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
lypinator	0:bb348c97df44	2394	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	2395	} while(0U)
lypinator	0:bb348c97df44	2396	#define __HAL_RCC_UART5_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	2397	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	2398	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
lypinator	0:bb348c97df44	2399	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	2400	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
lypinator	0:bb348c97df44	2401	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	2402	} while(0U)
lypinator	0:bb348c97df44	2403	#define __HAL_RCC_CAN1_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	2404	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	2405	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
lypinator	0:bb348c97df44	2406	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	2407	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
lypinator	0:bb348c97df44	2408	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	2409	} while(0U)
lypinator	0:bb348c97df44	2410	#define __HAL_RCC_CAN2_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	2411	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	2412	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
lypinator	0:bb348c97df44	2413	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	2414	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
lypinator	0:bb348c97df44	2415	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	2416	} while(0U)
lypinator	0:bb348c97df44	2417	#define __HAL_RCC_DAC_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	2418	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	2419	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
lypinator	0:bb348c97df44	2420	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	2421	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
lypinator	0:bb348c97df44	2422	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	2423	} while(0U)
lypinator	0:bb348c97df44	2424	#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	2425	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	2426	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
lypinator	0:bb348c97df44	2427	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	2428	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
lypinator	0:bb348c97df44	2429	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	2430	} while(0U)
lypinator	0:bb348c97df44	2431	#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	2432	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	2433	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
lypinator	0:bb348c97df44	2434	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	2435	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
lypinator	0:bb348c97df44	2436	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	2437	} while(0U)
lypinator	0:bb348c97df44	2438	#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	2439	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	2440	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
lypinator	0:bb348c97df44	2441	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	2442	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
lypinator	0:bb348c97df44	2443	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	2444	} while(0U)
lypinator	0:bb348c97df44	2445	#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	2446	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	2447	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
lypinator	0:bb348c97df44	2448	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	2449	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
lypinator	0:bb348c97df44	2450	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	2451	} while(0U)
lypinator	0:bb348c97df44	2452	#define __HAL_RCC_I2C3_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	2453	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	2454	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
lypinator	0:bb348c97df44	2455	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	2456	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
lypinator	0:bb348c97df44	2457	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	2458	} while(0U)
lypinator	0:bb348c97df44	2459	#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
lypinator	0:bb348c97df44	2460	#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
lypinator	0:bb348c97df44	2461	#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
lypinator	0:bb348c97df44	2462	#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
lypinator	0:bb348c97df44	2463	#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
lypinator	0:bb348c97df44	2464	#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
lypinator	0:bb348c97df44	2465	#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
lypinator	0:bb348c97df44	2466	#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
lypinator	0:bb348c97df44	2467	#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
lypinator	0:bb348c97df44	2468	#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
lypinator	0:bb348c97df44	2469	#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
lypinator	0:bb348c97df44	2470	#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
lypinator	0:bb348c97df44	2471	#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
lypinator	0:bb348c97df44	2472	#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
lypinator	0:bb348c97df44	2473	#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
lypinator	0:bb348c97df44	2474	#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
lypinator	0:bb348c97df44	2475	/**
lypinator	0:bb348c97df44	2476	* @}
lypinator	0:bb348c97df44	2477	*/
lypinator	0:bb348c97df44	2478
lypinator	0:bb348c97df44	2479	/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
lypinator	0:bb348c97df44	2480	* @brief Get the enable or disable status of the APB1 peripheral clock.
lypinator	0:bb348c97df44	2481	* @note After reset, the peripheral clock (used for registers read/write access)
lypinator	0:bb348c97df44	2482	* is disabled and the application software has to enable this clock before
lypinator	0:bb348c97df44	2483	* using it.
lypinator	0:bb348c97df44	2484	* @{
lypinator	0:bb348c97df44	2485	*/
lypinator	0:bb348c97df44	2486	#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
lypinator	0:bb348c97df44	2487	#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
lypinator	0:bb348c97df44	2488	#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
lypinator	0:bb348c97df44	2489	#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
lypinator	0:bb348c97df44	2490	#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
lypinator	0:bb348c97df44	2491	#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
lypinator	0:bb348c97df44	2492	#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
lypinator	0:bb348c97df44	2493	#define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
lypinator	0:bb348c97df44	2494	#define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
lypinator	0:bb348c97df44	2495	#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
lypinator	0:bb348c97df44	2496	#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
lypinator	0:bb348c97df44	2497	#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
lypinator	0:bb348c97df44	2498	#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
lypinator	0:bb348c97df44	2499	#define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET)
lypinator	0:bb348c97df44	2500	#define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)
lypinator	0:bb348c97df44	2501	#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
lypinator	0:bb348c97df44	2502
lypinator	0:bb348c97df44	2503	#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
lypinator	0:bb348c97df44	2504	#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
lypinator	0:bb348c97df44	2505	#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
lypinator	0:bb348c97df44	2506	#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
lypinator	0:bb348c97df44	2507	#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
lypinator	0:bb348c97df44	2508	#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
lypinator	0:bb348c97df44	2509	#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
lypinator	0:bb348c97df44	2510	#define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
lypinator	0:bb348c97df44	2511	#define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
lypinator	0:bb348c97df44	2512	#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
lypinator	0:bb348c97df44	2513	#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
lypinator	0:bb348c97df44	2514	#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
lypinator	0:bb348c97df44	2515	#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
lypinator	0:bb348c97df44	2516	#define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
lypinator	0:bb348c97df44	2517	#define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)
lypinator	0:bb348c97df44	2518	#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
lypinator	0:bb348c97df44	2519	/**
lypinator	0:bb348c97df44	2520	* @}
lypinator	0:bb348c97df44	2521	*/
lypinator	0:bb348c97df44	2522
lypinator	0:bb348c97df44	2523	/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
lypinator	0:bb348c97df44	2524	* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
lypinator	0:bb348c97df44	2525	* @note After reset, the peripheral clock (used for registers read/write access)
lypinator	0:bb348c97df44	2526	* is disabled and the application software has to enable this clock before
lypinator	0:bb348c97df44	2527	* using it.
lypinator	0:bb348c97df44	2528	* @{
lypinator	0:bb348c97df44	2529	*/
lypinator	0:bb348c97df44	2530	#define __HAL_RCC_TIM8_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	2531	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	2532	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
lypinator	0:bb348c97df44	2533	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	2534	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
lypinator	0:bb348c97df44	2535	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	2536	} while(0U)
lypinator	0:bb348c97df44	2537	#define __HAL_RCC_ADC2_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	2538	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	2539	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
lypinator	0:bb348c97df44	2540	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	2541	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
lypinator	0:bb348c97df44	2542	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	2543	} while(0U)
lypinator	0:bb348c97df44	2544	#define __HAL_RCC_ADC3_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	2545	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	2546	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
lypinator	0:bb348c97df44	2547	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	2548	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
lypinator	0:bb348c97df44	2549	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	2550	} while(0U)
lypinator	0:bb348c97df44	2551	#define __HAL_RCC_SDIO_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	2552	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	2553	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
lypinator	0:bb348c97df44	2554	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	2555	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
lypinator	0:bb348c97df44	2556	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	2557	} while(0U)
lypinator	0:bb348c97df44	2558	#define __HAL_RCC_SPI4_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	2559	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	2560	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
lypinator	0:bb348c97df44	2561	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	2562	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
lypinator	0:bb348c97df44	2563	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	2564	} while(0U)
lypinator	0:bb348c97df44	2565	#define __HAL_RCC_TIM10_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	2566	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	2567	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
lypinator	0:bb348c97df44	2568	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	2569	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
lypinator	0:bb348c97df44	2570	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	2571	} while(0U)
lypinator	0:bb348c97df44	2572
lypinator	0:bb348c97df44	2573	#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
lypinator	0:bb348c97df44	2574	#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
lypinator	0:bb348c97df44	2575	#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
lypinator	0:bb348c97df44	2576	#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
lypinator	0:bb348c97df44	2577	#define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
lypinator	0:bb348c97df44	2578	#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
lypinator	0:bb348c97df44	2579	/**
lypinator	0:bb348c97df44	2580	* @}
lypinator	0:bb348c97df44	2581	*/
lypinator	0:bb348c97df44	2582
lypinator	0:bb348c97df44	2583	/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
lypinator	0:bb348c97df44	2584	* @brief Get the enable or disable status of the APB2 peripheral clock.
lypinator	0:bb348c97df44	2585	* @note After reset, the peripheral clock (used for registers read/write access)
lypinator	0:bb348c97df44	2586	* is disabled and the application software has to enable this clock before
lypinator	0:bb348c97df44	2587	* using it.
lypinator	0:bb348c97df44	2588	* @{
lypinator	0:bb348c97df44	2589	*/
lypinator	0:bb348c97df44	2590	#define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET)
lypinator	0:bb348c97df44	2591	#define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)
lypinator	0:bb348c97df44	2592	#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)
lypinator	0:bb348c97df44	2593	#define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)
lypinator	0:bb348c97df44	2594	#define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET)
lypinator	0:bb348c97df44	2595	#define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET)
lypinator	0:bb348c97df44	2596
lypinator	0:bb348c97df44	2597	#define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET)
lypinator	0:bb348c97df44	2598	#define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
lypinator	0:bb348c97df44	2599	#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)
lypinator	0:bb348c97df44	2600	#define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)
lypinator	0:bb348c97df44	2601	#define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET)
lypinator	0:bb348c97df44	2602	#define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET)
lypinator	0:bb348c97df44	2603	/**
lypinator	0:bb348c97df44	2604	* @}
lypinator	0:bb348c97df44	2605	*/
lypinator	0:bb348c97df44	2606
lypinator	0:bb348c97df44	2607	/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset
lypinator	0:bb348c97df44	2608	* @brief Force or release AHB1 peripheral reset.
lypinator	0:bb348c97df44	2609	* @{
lypinator	0:bb348c97df44	2610	*/
lypinator	0:bb348c97df44	2611	#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIODRST))
lypinator	0:bb348c97df44	2612	#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOERST))
lypinator	0:bb348c97df44	2613	#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOFRST))
lypinator	0:bb348c97df44	2614	#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOGRST))
lypinator	0:bb348c97df44	2615	#define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOIRST))
lypinator	0:bb348c97df44	2616	#define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_ETHMACRST))
lypinator	0:bb348c97df44	2617	#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_OTGHRST))
lypinator	0:bb348c97df44	2618	#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_CRCRST))
lypinator	0:bb348c97df44	2619
lypinator	0:bb348c97df44	2620	#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
lypinator	0:bb348c97df44	2621	#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
lypinator	0:bb348c97df44	2622	#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
lypinator	0:bb348c97df44	2623	#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
lypinator	0:bb348c97df44	2624	#define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
lypinator	0:bb348c97df44	2625	#define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))
lypinator	0:bb348c97df44	2626	#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
lypinator	0:bb348c97df44	2627	#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
lypinator	0:bb348c97df44	2628	/**
lypinator	0:bb348c97df44	2629	* @}
lypinator	0:bb348c97df44	2630	*/
lypinator	0:bb348c97df44	2631
lypinator	0:bb348c97df44	2632	/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset
lypinator	0:bb348c97df44	2633	* @brief Force or release AHB2 peripheral reset.
lypinator	0:bb348c97df44	2634	* @{
lypinator	0:bb348c97df44	2635	*/
lypinator	0:bb348c97df44	2636	#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU)
lypinator	0:bb348c97df44	2637	#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U)
lypinator	0:bb348c97df44	2638
lypinator	0:bb348c97df44	2639	#if defined(STM32F407xx)\|\| defined(STM32F417xx)
lypinator	0:bb348c97df44	2640	#define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_DCMIRST))
lypinator	0:bb348c97df44	2641	#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
lypinator	0:bb348c97df44	2642	#endif /* STM32F407xx \|\| STM32F417xx */
lypinator	0:bb348c97df44	2643
lypinator	0:bb348c97df44	2644	#if defined(STM32F415xx) \|\| defined(STM32F417xx)
lypinator	0:bb348c97df44	2645	#define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_CRYPRST))
lypinator	0:bb348c97df44	2646	#define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_HASHRST))
lypinator	0:bb348c97df44	2647
lypinator	0:bb348c97df44	2648	#define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST))
lypinator	0:bb348c97df44	2649	#define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST))
lypinator	0:bb348c97df44	2650	#endif /* STM32F415xx \|\| STM32F417xx */
lypinator	0:bb348c97df44	2651
lypinator	0:bb348c97df44	2652	#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_OTGFSRST))
lypinator	0:bb348c97df44	2653	#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
lypinator	0:bb348c97df44	2654
lypinator	0:bb348c97df44	2655	#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_RNGRST))
lypinator	0:bb348c97df44	2656	#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
lypinator	0:bb348c97df44	2657	/**
lypinator	0:bb348c97df44	2658	* @}
lypinator	0:bb348c97df44	2659	*/
lypinator	0:bb348c97df44	2660
lypinator	0:bb348c97df44	2661	/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset
lypinator	0:bb348c97df44	2662	* @brief Force or release AHB3 peripheral reset.
lypinator	0:bb348c97df44	2663	* @{
lypinator	0:bb348c97df44	2664	*/
lypinator	0:bb348c97df44	2665	#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
lypinator	0:bb348c97df44	2666	#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U)
lypinator	0:bb348c97df44	2667
lypinator	0:bb348c97df44	2668	#define __HAL_RCC_FSMC_FORCE_RESET() (RCC->AHB3RSTR \|= (RCC_AHB3RSTR_FSMCRST))
lypinator	0:bb348c97df44	2669	#define __HAL_RCC_FSMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FSMCRST))
lypinator	0:bb348c97df44	2670	/**
lypinator	0:bb348c97df44	2671	* @}
lypinator	0:bb348c97df44	2672	*/
lypinator	0:bb348c97df44	2673
lypinator	0:bb348c97df44	2674	/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset
lypinator	0:bb348c97df44	2675	* @brief Force or release APB1 peripheral reset.
lypinator	0:bb348c97df44	2676	* @{
lypinator	0:bb348c97df44	2677	*/
lypinator	0:bb348c97df44	2678	#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM6RST))
lypinator	0:bb348c97df44	2679	#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM7RST))
lypinator	0:bb348c97df44	2680	#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM12RST))
lypinator	0:bb348c97df44	2681	#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM13RST))
lypinator	0:bb348c97df44	2682	#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM14RST))
lypinator	0:bb348c97df44	2683	#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART3RST))
lypinator	0:bb348c97df44	2684	#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART4RST))
lypinator	0:bb348c97df44	2685	#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART5RST))
lypinator	0:bb348c97df44	2686	#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN1RST))
lypinator	0:bb348c97df44	2687	#define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN2RST))
lypinator	0:bb348c97df44	2688	#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DACRST))
lypinator	0:bb348c97df44	2689	#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM2RST))
lypinator	0:bb348c97df44	2690	#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM3RST))
lypinator	0:bb348c97df44	2691	#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM4RST))
lypinator	0:bb348c97df44	2692	#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI3RST))
lypinator	0:bb348c97df44	2693	#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C3RST))
lypinator	0:bb348c97df44	2694
lypinator	0:bb348c97df44	2695	#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
lypinator	0:bb348c97df44	2696	#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
lypinator	0:bb348c97df44	2697	#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
lypinator	0:bb348c97df44	2698	#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
lypinator	0:bb348c97df44	2699	#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
lypinator	0:bb348c97df44	2700	#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
lypinator	0:bb348c97df44	2701	#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
lypinator	0:bb348c97df44	2702	#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
lypinator	0:bb348c97df44	2703	#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
lypinator	0:bb348c97df44	2704	#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
lypinator	0:bb348c97df44	2705	#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
lypinator	0:bb348c97df44	2706	#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
lypinator	0:bb348c97df44	2707	#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
lypinator	0:bb348c97df44	2708	#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
lypinator	0:bb348c97df44	2709	#define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
lypinator	0:bb348c97df44	2710	#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
lypinator	0:bb348c97df44	2711	/**
lypinator	0:bb348c97df44	2712	* @}
lypinator	0:bb348c97df44	2713	*/
lypinator	0:bb348c97df44	2714
lypinator	0:bb348c97df44	2715	/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
lypinator	0:bb348c97df44	2716	* @brief Force or release APB2 peripheral reset.
lypinator	0:bb348c97df44	2717	* @{
lypinator	0:bb348c97df44	2718	*/
lypinator	0:bb348c97df44	2719	#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM8RST))
lypinator	0:bb348c97df44	2720	#define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SDIORST))
lypinator	0:bb348c97df44	2721	#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI4RST))
lypinator	0:bb348c97df44	2722	#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM10RST))
lypinator	0:bb348c97df44	2723
lypinator	0:bb348c97df44	2724	#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
lypinator	0:bb348c97df44	2725	#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
lypinator	0:bb348c97df44	2726	#define __HAL_RCC_TIM10_RELEASE_RESET()(RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
lypinator	0:bb348c97df44	2727	#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
lypinator	0:bb348c97df44	2728	/**
lypinator	0:bb348c97df44	2729	* @}
lypinator	0:bb348c97df44	2730	*/
lypinator	0:bb348c97df44	2731
lypinator	0:bb348c97df44	2732	/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
lypinator	0:bb348c97df44	2733	* @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
lypinator	0:bb348c97df44	2734	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
lypinator	0:bb348c97df44	2735	* power consumption.
lypinator	0:bb348c97df44	2736	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
lypinator	0:bb348c97df44	2737	* @note By default, all peripheral clocks are enabled during SLEEP mode.
lypinator	0:bb348c97df44	2738	* @{
lypinator	0:bb348c97df44	2739	*/
lypinator	0:bb348c97df44	2740	#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIODLPEN))
lypinator	0:bb348c97df44	2741	#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOELPEN))
lypinator	0:bb348c97df44	2742	#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOFLPEN))
lypinator	0:bb348c97df44	2743	#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOGLPEN))
lypinator	0:bb348c97df44	2744	#define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOILPEN))
lypinator	0:bb348c97df44	2745	#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM2LPEN))
lypinator	0:bb348c97df44	2746	#define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACLPEN))
lypinator	0:bb348c97df44	2747	#define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACTXLPEN))
lypinator	0:bb348c97df44	2748	#define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACRXLPEN))
lypinator	0:bb348c97df44	2749	#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACPTPLPEN))
lypinator	0:bb348c97df44	2750	#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_OTGHSLPEN))
lypinator	0:bb348c97df44	2751	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_OTGHSULPILPEN))
lypinator	0:bb348c97df44	2752	#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_CRCLPEN))
lypinator	0:bb348c97df44	2753	#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_FLITFLPEN))
lypinator	0:bb348c97df44	2754	#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM1LPEN))
lypinator	0:bb348c97df44	2755	#define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_BKPSRAMLPEN))
lypinator	0:bb348c97df44	2756
lypinator	0:bb348c97df44	2757	#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
lypinator	0:bb348c97df44	2758	#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
lypinator	0:bb348c97df44	2759	#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
lypinator	0:bb348c97df44	2760	#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
lypinator	0:bb348c97df44	2761	#define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN))
lypinator	0:bb348c97df44	2762	#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
lypinator	0:bb348c97df44	2763	#define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN))
lypinator	0:bb348c97df44	2764	#define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))
lypinator	0:bb348c97df44	2765	#define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))
lypinator	0:bb348c97df44	2766	#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))
lypinator	0:bb348c97df44	2767	#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
lypinator	0:bb348c97df44	2768	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
lypinator	0:bb348c97df44	2769	#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
lypinator	0:bb348c97df44	2770	#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
lypinator	0:bb348c97df44	2771	#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
lypinator	0:bb348c97df44	2772	#define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))
lypinator	0:bb348c97df44	2773	/**
lypinator	0:bb348c97df44	2774	* @}
lypinator	0:bb348c97df44	2775	*/
lypinator	0:bb348c97df44	2776
lypinator	0:bb348c97df44	2777	/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
lypinator	0:bb348c97df44	2778	* @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
lypinator	0:bb348c97df44	2779	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
lypinator	0:bb348c97df44	2780	* power consumption.
lypinator	0:bb348c97df44	2781	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
lypinator	0:bb348c97df44	2782	* @note By default, all peripheral clocks are enabled during SLEEP mode.
lypinator	0:bb348c97df44	2783	* @{
lypinator	0:bb348c97df44	2784	*/
lypinator	0:bb348c97df44	2785	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_OTGFSLPEN))
lypinator	0:bb348c97df44	2786	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
lypinator	0:bb348c97df44	2787
lypinator	0:bb348c97df44	2788	#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_RNGLPEN))
lypinator	0:bb348c97df44	2789	#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
lypinator	0:bb348c97df44	2790
lypinator	0:bb348c97df44	2791	#if defined(STM32F407xx)\|\| defined(STM32F417xx)
lypinator	0:bb348c97df44	2792	#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_DCMILPEN))
lypinator	0:bb348c97df44	2793	#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
lypinator	0:bb348c97df44	2794	#endif /* STM32F407xx \|\| STM32F417xx */
lypinator	0:bb348c97df44	2795
lypinator	0:bb348c97df44	2796	#if defined(STM32F415xx) \|\| defined(STM32F417xx)
lypinator	0:bb348c97df44	2797	#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_CRYPLPEN))
lypinator	0:bb348c97df44	2798	#define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_HASHLPEN))
lypinator	0:bb348c97df44	2799
lypinator	0:bb348c97df44	2800	#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN))
lypinator	0:bb348c97df44	2801	#define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN))
lypinator	0:bb348c97df44	2802	#endif /* STM32F415xx \|\| STM32F417xx */
lypinator	0:bb348c97df44	2803	/**
lypinator	0:bb348c97df44	2804	* @}
lypinator	0:bb348c97df44	2805	*/
lypinator	0:bb348c97df44	2806
lypinator	0:bb348c97df44	2807	/** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable
lypinator	0:bb348c97df44	2808	* @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
lypinator	0:bb348c97df44	2809	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
lypinator	0:bb348c97df44	2810	* power consumption.
lypinator	0:bb348c97df44	2811	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
lypinator	0:bb348c97df44	2812	* @note By default, all peripheral clocks are enabled during SLEEP mode.
lypinator	0:bb348c97df44	2813	* @{
lypinator	0:bb348c97df44	2814	*/
lypinator	0:bb348c97df44	2815	#define __HAL_RCC_FSMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_FSMCLPEN))
lypinator	0:bb348c97df44	2816	#define __HAL_RCC_FSMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FSMCLPEN))
lypinator	0:bb348c97df44	2817	/**
lypinator	0:bb348c97df44	2818	* @}
lypinator	0:bb348c97df44	2819	*/
lypinator	0:bb348c97df44	2820
lypinator	0:bb348c97df44	2821	/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
lypinator	0:bb348c97df44	2822	* @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
lypinator	0:bb348c97df44	2823	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
lypinator	0:bb348c97df44	2824	* power consumption.
lypinator	0:bb348c97df44	2825	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
lypinator	0:bb348c97df44	2826	* @note By default, all peripheral clocks are enabled during SLEEP mode.
lypinator	0:bb348c97df44	2827	* @{
lypinator	0:bb348c97df44	2828	*/
lypinator	0:bb348c97df44	2829	#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM6LPEN))
lypinator	0:bb348c97df44	2830	#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM7LPEN))
lypinator	0:bb348c97df44	2831	#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM12LPEN))
lypinator	0:bb348c97df44	2832	#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM13LPEN))
lypinator	0:bb348c97df44	2833	#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM14LPEN))
lypinator	0:bb348c97df44	2834	#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_USART3LPEN))
lypinator	0:bb348c97df44	2835	#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART4LPEN))
lypinator	0:bb348c97df44	2836	#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART5LPEN))
lypinator	0:bb348c97df44	2837	#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN1LPEN))
lypinator	0:bb348c97df44	2838	#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN2LPEN))
lypinator	0:bb348c97df44	2839	#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_DACLPEN))
lypinator	0:bb348c97df44	2840	#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM2LPEN))
lypinator	0:bb348c97df44	2841	#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM3LPEN))
lypinator	0:bb348c97df44	2842	#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM4LPEN))
lypinator	0:bb348c97df44	2843	#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_SPI3LPEN))
lypinator	0:bb348c97df44	2844	#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C3LPEN))
lypinator	0:bb348c97df44	2845
lypinator	0:bb348c97df44	2846	#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
lypinator	0:bb348c97df44	2847	#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
lypinator	0:bb348c97df44	2848	#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
lypinator	0:bb348c97df44	2849	#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
lypinator	0:bb348c97df44	2850	#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
lypinator	0:bb348c97df44	2851	#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
lypinator	0:bb348c97df44	2852	#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
lypinator	0:bb348c97df44	2853	#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
lypinator	0:bb348c97df44	2854	#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
lypinator	0:bb348c97df44	2855	#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
lypinator	0:bb348c97df44	2856	#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
lypinator	0:bb348c97df44	2857	#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
lypinator	0:bb348c97df44	2858	#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
lypinator	0:bb348c97df44	2859	#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
lypinator	0:bb348c97df44	2860	#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
lypinator	0:bb348c97df44	2861	#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
lypinator	0:bb348c97df44	2862	/**
lypinator	0:bb348c97df44	2863	* @}
lypinator	0:bb348c97df44	2864	*/
lypinator	0:bb348c97df44	2865
lypinator	0:bb348c97df44	2866	/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
lypinator	0:bb348c97df44	2867	* @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
lypinator	0:bb348c97df44	2868	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
lypinator	0:bb348c97df44	2869	* power consumption.
lypinator	0:bb348c97df44	2870	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
lypinator	0:bb348c97df44	2871	* @note By default, all peripheral clocks are enabled during SLEEP mode.
lypinator	0:bb348c97df44	2872	* @{
lypinator	0:bb348c97df44	2873	*/
lypinator	0:bb348c97df44	2874	#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM8LPEN))
lypinator	0:bb348c97df44	2875	#define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC2LPEN))
lypinator	0:bb348c97df44	2876	#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC3LPEN))
lypinator	0:bb348c97df44	2877	#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SDIOLPEN))
lypinator	0:bb348c97df44	2878	#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI4LPEN))
lypinator	0:bb348c97df44	2879	#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()(RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM10LPEN))
lypinator	0:bb348c97df44	2880
lypinator	0:bb348c97df44	2881	#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
lypinator	0:bb348c97df44	2882	#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
lypinator	0:bb348c97df44	2883	#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()(RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
lypinator	0:bb348c97df44	2884	#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
lypinator	0:bb348c97df44	2885	#define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
lypinator	0:bb348c97df44	2886	#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
lypinator	0:bb348c97df44	2887	/**
lypinator	0:bb348c97df44	2888	* @}
lypinator	0:bb348c97df44	2889	*/
lypinator	0:bb348c97df44	2890	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx */
lypinator	0:bb348c97df44	2891	/----------------------------------------------------------------------------/
lypinator	0:bb348c97df44	2892
lypinator	0:bb348c97df44	2893	/------------------------- STM32F401xE/STM32F401xC --------------------------/
lypinator	0:bb348c97df44	2894	#if defined(STM32F401xC) \|\| defined(STM32F401xE)
lypinator	0:bb348c97df44	2895	/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
lypinator	0:bb348c97df44	2896	* @brief Enable or disable the AHB1 peripheral clock.
lypinator	0:bb348c97df44	2897	* @note After reset, the peripheral clock (used for registers read/write access)
lypinator	0:bb348c97df44	2898	* is disabled and the application software has to enable this clock before
lypinator	0:bb348c97df44	2899	* using it.
lypinator	0:bb348c97df44	2900	* @{
lypinator	0:bb348c97df44	2901	*/
lypinator	0:bb348c97df44	2902	#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	2903	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	2904	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
lypinator	0:bb348c97df44	2905	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	2906	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
lypinator	0:bb348c97df44	2907	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	2908	} while(0U)
lypinator	0:bb348c97df44	2909	#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	2910	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	2911	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
lypinator	0:bb348c97df44	2912	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	2913	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
lypinator	0:bb348c97df44	2914	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	2915	} while(0U)
lypinator	0:bb348c97df44	2916	#define __HAL_RCC_CRC_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	2917	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	2918	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
lypinator	0:bb348c97df44	2919	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	2920	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
lypinator	0:bb348c97df44	2921	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	2922	} while(0U)
lypinator	0:bb348c97df44	2923	#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	2924	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	2925	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
lypinator	0:bb348c97df44	2926	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	2927	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
lypinator	0:bb348c97df44	2928	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	2929	} while(0U)
lypinator	0:bb348c97df44	2930
lypinator	0:bb348c97df44	2931	#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
lypinator	0:bb348c97df44	2932	#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
lypinator	0:bb348c97df44	2933	#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
lypinator	0:bb348c97df44	2934	#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
lypinator	0:bb348c97df44	2935	/**
lypinator	0:bb348c97df44	2936	* @}
lypinator	0:bb348c97df44	2937	*/
lypinator	0:bb348c97df44	2938
lypinator	0:bb348c97df44	2939	/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
lypinator	0:bb348c97df44	2940	* @brief Get the enable or disable status of the AHB1 peripheral clock.
lypinator	0:bb348c97df44	2941	* @note After reset, the peripheral clock (used for registers read/write access)
lypinator	0:bb348c97df44	2942	* is disabled and the application software has to enable this clock before
lypinator	0:bb348c97df44	2943	* using it.
lypinator	0:bb348c97df44	2944	* @{
lypinator	0:bb348c97df44	2945	*/
lypinator	0:bb348c97df44	2946	#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)
lypinator	0:bb348c97df44	2947	#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)
lypinator	0:bb348c97df44	2948	#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
lypinator	0:bb348c97df44	2949	#define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) != RESET)
lypinator	0:bb348c97df44	2950
lypinator	0:bb348c97df44	2951	#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)
lypinator	0:bb348c97df44	2952	#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)
lypinator	0:bb348c97df44	2953	#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
lypinator	0:bb348c97df44	2954	#define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET)
lypinator	0:bb348c97df44	2955	/**
lypinator	0:bb348c97df44	2956	* @}
lypinator	0:bb348c97df44	2957	*/
lypinator	0:bb348c97df44	2958
lypinator	0:bb348c97df44	2959	/** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
lypinator	0:bb348c97df44	2960	* @brief Enable or disable the AHB2 peripheral clock.
lypinator	0:bb348c97df44	2961	* @note After reset, the peripheral clock (used for registers read/write access)
lypinator	0:bb348c97df44	2962	* is disabled and the application software has to enable this clock before
lypinator	0:bb348c97df44	2963	* using it.
lypinator	0:bb348c97df44	2964	* @{
lypinator	0:bb348c97df44	2965	*/
lypinator	0:bb348c97df44	2966	#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR \|= (RCC_AHB2ENR_OTGFSEN));\
lypinator	0:bb348c97df44	2967	__HAL_RCC_SYSCFG_CLK_ENABLE();\
lypinator	0:bb348c97df44	2968	}while(0U)
lypinator	0:bb348c97df44	2969
lypinator	0:bb348c97df44	2970	#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
lypinator	0:bb348c97df44	2971	/**
lypinator	0:bb348c97df44	2972	* @}
lypinator	0:bb348c97df44	2973	*/
lypinator	0:bb348c97df44	2974
lypinator	0:bb348c97df44	2975	/** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status
lypinator	0:bb348c97df44	2976	* @brief Get the enable or disable status of the AHB2 peripheral clock.
lypinator	0:bb348c97df44	2977	* @note After reset, the peripheral clock (used for registers read/write access)
lypinator	0:bb348c97df44	2978	* is disabled and the application software has to enable this clock before
lypinator	0:bb348c97df44	2979	* using it.
lypinator	0:bb348c97df44	2980	* @{
lypinator	0:bb348c97df44	2981	*/
lypinator	0:bb348c97df44	2982	#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
lypinator	0:bb348c97df44	2983	#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
lypinator	0:bb348c97df44	2984	/**
lypinator	0:bb348c97df44	2985	* @}
lypinator	0:bb348c97df44	2986	*/
lypinator	0:bb348c97df44	2987
lypinator	0:bb348c97df44	2988	/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
lypinator	0:bb348c97df44	2989	* @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
lypinator	0:bb348c97df44	2990	* @note After reset, the peripheral clock (used for registers read/write access)
lypinator	0:bb348c97df44	2991	* is disabled and the application software has to enable this clock before
lypinator	0:bb348c97df44	2992	* using it.
lypinator	0:bb348c97df44	2993	* @{
lypinator	0:bb348c97df44	2994	*/
lypinator	0:bb348c97df44	2995	#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	2996	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	2997	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
lypinator	0:bb348c97df44	2998	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	2999	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
lypinator	0:bb348c97df44	3000	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	3001	} while(0U)
lypinator	0:bb348c97df44	3002	#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	3003	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	3004	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
lypinator	0:bb348c97df44	3005	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	3006	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
lypinator	0:bb348c97df44	3007	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	3008	} while(0U)
lypinator	0:bb348c97df44	3009	#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	3010	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	3011	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
lypinator	0:bb348c97df44	3012	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	3013	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
lypinator	0:bb348c97df44	3014	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	3015	} while(0U)
lypinator	0:bb348c97df44	3016	#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	3017	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	3018	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
lypinator	0:bb348c97df44	3019	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	3020	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
lypinator	0:bb348c97df44	3021	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	3022	} while(0U)
lypinator	0:bb348c97df44	3023	#define __HAL_RCC_I2C3_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	3024	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	3025	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
lypinator	0:bb348c97df44	3026	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	3027	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
lypinator	0:bb348c97df44	3028	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	3029	} while(0U)
lypinator	0:bb348c97df44	3030	#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
lypinator	0:bb348c97df44	3031	#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
lypinator	0:bb348c97df44	3032	#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
lypinator	0:bb348c97df44	3033	#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
lypinator	0:bb348c97df44	3034	#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
lypinator	0:bb348c97df44	3035	/**
lypinator	0:bb348c97df44	3036	* @}
lypinator	0:bb348c97df44	3037	*/
lypinator	0:bb348c97df44	3038
lypinator	0:bb348c97df44	3039	/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
lypinator	0:bb348c97df44	3040	* @brief Get the enable or disable status of the APB1 peripheral clock.
lypinator	0:bb348c97df44	3041	* @note After reset, the peripheral clock (used for registers read/write access)
lypinator	0:bb348c97df44	3042	* is disabled and the application software has to enable this clock before
lypinator	0:bb348c97df44	3043	* using it.
lypinator	0:bb348c97df44	3044	* @{
lypinator	0:bb348c97df44	3045	*/
lypinator	0:bb348c97df44	3046	#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
lypinator	0:bb348c97df44	3047	#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
lypinator	0:bb348c97df44	3048	#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
lypinator	0:bb348c97df44	3049	#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
lypinator	0:bb348c97df44	3050	#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
lypinator	0:bb348c97df44	3051
lypinator	0:bb348c97df44	3052	#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
lypinator	0:bb348c97df44	3053	#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
lypinator	0:bb348c97df44	3054	#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
lypinator	0:bb348c97df44	3055	#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
lypinator	0:bb348c97df44	3056	#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
lypinator	0:bb348c97df44	3057	/**
lypinator	0:bb348c97df44	3058	* @}
lypinator	0:bb348c97df44	3059	*/
lypinator	0:bb348c97df44	3060
lypinator	0:bb348c97df44	3061	/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
lypinator	0:bb348c97df44	3062	* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
lypinator	0:bb348c97df44	3063	* @note After reset, the peripheral clock (used for registers read/write access)
lypinator	0:bb348c97df44	3064	* is disabled and the application software has to enable this clock before
lypinator	0:bb348c97df44	3065	* using it.
lypinator	0:bb348c97df44	3066	* @{
lypinator	0:bb348c97df44	3067	*/
lypinator	0:bb348c97df44	3068	#define __HAL_RCC_SDIO_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	3069	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	3070	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
lypinator	0:bb348c97df44	3071	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	3072	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
lypinator	0:bb348c97df44	3073	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	3074	} while(0U)
lypinator	0:bb348c97df44	3075	#define __HAL_RCC_SPI4_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	3076	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	3077	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
lypinator	0:bb348c97df44	3078	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	3079	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
lypinator	0:bb348c97df44	3080	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	3081	} while(0U)
lypinator	0:bb348c97df44	3082	#define __HAL_RCC_TIM10_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	3083	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	3084	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
lypinator	0:bb348c97df44	3085	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	3086	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
lypinator	0:bb348c97df44	3087	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	3088	} while(0U)
lypinator	0:bb348c97df44	3089
lypinator	0:bb348c97df44	3090	#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
lypinator	0:bb348c97df44	3091	#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
lypinator	0:bb348c97df44	3092	#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
lypinator	0:bb348c97df44	3093	/**
lypinator	0:bb348c97df44	3094	* @}
lypinator	0:bb348c97df44	3095	*/
lypinator	0:bb348c97df44	3096
lypinator	0:bb348c97df44	3097	/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
lypinator	0:bb348c97df44	3098	* @brief Get the enable or disable status of the APB2 peripheral clock.
lypinator	0:bb348c97df44	3099	* @note After reset, the peripheral clock (used for registers read/write access)
lypinator	0:bb348c97df44	3100	* is disabled and the application software has to enable this clock before
lypinator	0:bb348c97df44	3101	* using it.
lypinator	0:bb348c97df44	3102	* @{
lypinator	0:bb348c97df44	3103	*/
lypinator	0:bb348c97df44	3104	#define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET)
lypinator	0:bb348c97df44	3105	#define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)
lypinator	0:bb348c97df44	3106	#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)
lypinator	0:bb348c97df44	3107
lypinator	0:bb348c97df44	3108	#define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET)
lypinator	0:bb348c97df44	3109	#define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
lypinator	0:bb348c97df44	3110	#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)
lypinator	0:bb348c97df44	3111	/**
lypinator	0:bb348c97df44	3112	* @}
lypinator	0:bb348c97df44	3113	*/
lypinator	0:bb348c97df44	3114	/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset
lypinator	0:bb348c97df44	3115	* @brief Force or release AHB1 peripheral reset.
lypinator	0:bb348c97df44	3116	* @{
lypinator	0:bb348c97df44	3117	*/
lypinator	0:bb348c97df44	3118	#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFFU)
lypinator	0:bb348c97df44	3119	#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIODRST))
lypinator	0:bb348c97df44	3120	#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOERST))
lypinator	0:bb348c97df44	3121	#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_CRCRST))
lypinator	0:bb348c97df44	3122
lypinator	0:bb348c97df44	3123	#define __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00U)
lypinator	0:bb348c97df44	3124	#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
lypinator	0:bb348c97df44	3125	#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
lypinator	0:bb348c97df44	3126	#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
lypinator	0:bb348c97df44	3127	/**
lypinator	0:bb348c97df44	3128	* @}
lypinator	0:bb348c97df44	3129	*/
lypinator	0:bb348c97df44	3130
lypinator	0:bb348c97df44	3131	/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset
lypinator	0:bb348c97df44	3132	* @brief Force or release AHB2 peripheral reset.
lypinator	0:bb348c97df44	3133	* @{
lypinator	0:bb348c97df44	3134	*/
lypinator	0:bb348c97df44	3135	#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU)
lypinator	0:bb348c97df44	3136	#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_OTGFSRST))
lypinator	0:bb348c97df44	3137
lypinator	0:bb348c97df44	3138	#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U)
lypinator	0:bb348c97df44	3139	#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
lypinator	0:bb348c97df44	3140	/**
lypinator	0:bb348c97df44	3141	* @}
lypinator	0:bb348c97df44	3142	*/
lypinator	0:bb348c97df44	3143
lypinator	0:bb348c97df44	3144	/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset
lypinator	0:bb348c97df44	3145	* @brief Force or release APB1 peripheral reset.
lypinator	0:bb348c97df44	3146	* @{
lypinator	0:bb348c97df44	3147	*/
lypinator	0:bb348c97df44	3148	#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU)
lypinator	0:bb348c97df44	3149	#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM2RST))
lypinator	0:bb348c97df44	3150	#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM3RST))
lypinator	0:bb348c97df44	3151	#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM4RST))
lypinator	0:bb348c97df44	3152	#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI3RST))
lypinator	0:bb348c97df44	3153	#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C3RST))
lypinator	0:bb348c97df44	3154
lypinator	0:bb348c97df44	3155	#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00U)
lypinator	0:bb348c97df44	3156	#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
lypinator	0:bb348c97df44	3157	#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
lypinator	0:bb348c97df44	3158	#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
lypinator	0:bb348c97df44	3159	#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
lypinator	0:bb348c97df44	3160	#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
lypinator	0:bb348c97df44	3161	/**
lypinator	0:bb348c97df44	3162	* @}
lypinator	0:bb348c97df44	3163	*/
lypinator	0:bb348c97df44	3164
lypinator	0:bb348c97df44	3165	/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
lypinator	0:bb348c97df44	3166	* @brief Force or release APB2 peripheral reset.
lypinator	0:bb348c97df44	3167	* @{
lypinator	0:bb348c97df44	3168	*/
lypinator	0:bb348c97df44	3169	#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU)
lypinator	0:bb348c97df44	3170	#define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SDIORST))
lypinator	0:bb348c97df44	3171	#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI4RST))
lypinator	0:bb348c97df44	3172	#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM10RST))
lypinator	0:bb348c97df44	3173
lypinator	0:bb348c97df44	3174	#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00U)
lypinator	0:bb348c97df44	3175	#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
lypinator	0:bb348c97df44	3176	#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
lypinator	0:bb348c97df44	3177	#define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
lypinator	0:bb348c97df44	3178	/**
lypinator	0:bb348c97df44	3179	* @}
lypinator	0:bb348c97df44	3180	*/
lypinator	0:bb348c97df44	3181
lypinator	0:bb348c97df44	3182	/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset
lypinator	0:bb348c97df44	3183	* @brief Force or release AHB3 peripheral reset.
lypinator	0:bb348c97df44	3184	* @{
lypinator	0:bb348c97df44	3185	*/
lypinator	0:bb348c97df44	3186	#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
lypinator	0:bb348c97df44	3187	#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U)
lypinator	0:bb348c97df44	3188	/**
lypinator	0:bb348c97df44	3189	* @}
lypinator	0:bb348c97df44	3190	*/
lypinator	0:bb348c97df44	3191
lypinator	0:bb348c97df44	3192	/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
lypinator	0:bb348c97df44	3193	* @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
lypinator	0:bb348c97df44	3194	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
lypinator	0:bb348c97df44	3195	* power consumption.
lypinator	0:bb348c97df44	3196	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
lypinator	0:bb348c97df44	3197	* @note By default, all peripheral clocks are enabled during SLEEP mode.
lypinator	0:bb348c97df44	3198	* @{
lypinator	0:bb348c97df44	3199	*/
lypinator	0:bb348c97df44	3200	#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIODLPEN))
lypinator	0:bb348c97df44	3201	#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOELPEN))
lypinator	0:bb348c97df44	3202	#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_CRCLPEN))
lypinator	0:bb348c97df44	3203	#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_FLITFLPEN))
lypinator	0:bb348c97df44	3204	#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM1LPEN))
lypinator	0:bb348c97df44	3205
lypinator	0:bb348c97df44	3206	#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
lypinator	0:bb348c97df44	3207	#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
lypinator	0:bb348c97df44	3208	#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
lypinator	0:bb348c97df44	3209	#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
lypinator	0:bb348c97df44	3210	#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
lypinator	0:bb348c97df44	3211	/**
lypinator	0:bb348c97df44	3212	* @}
lypinator	0:bb348c97df44	3213	*/
lypinator	0:bb348c97df44	3214
lypinator	0:bb348c97df44	3215	/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
lypinator	0:bb348c97df44	3216	* @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
lypinator	0:bb348c97df44	3217	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
lypinator	0:bb348c97df44	3218	* power consumption.
lypinator	0:bb348c97df44	3219	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
lypinator	0:bb348c97df44	3220	* @note By default, all peripheral clocks are enabled during SLEEP mode.
lypinator	0:bb348c97df44	3221	* @{
lypinator	0:bb348c97df44	3222	*/
lypinator	0:bb348c97df44	3223	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_OTGFSLPEN))
lypinator	0:bb348c97df44	3224
lypinator	0:bb348c97df44	3225	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
lypinator	0:bb348c97df44	3226	/**
lypinator	0:bb348c97df44	3227	* @}
lypinator	0:bb348c97df44	3228	*/
lypinator	0:bb348c97df44	3229
lypinator	0:bb348c97df44	3230	/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
lypinator	0:bb348c97df44	3231	* @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
lypinator	0:bb348c97df44	3232	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
lypinator	0:bb348c97df44	3233	* power consumption.
lypinator	0:bb348c97df44	3234	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
lypinator	0:bb348c97df44	3235	* @note By default, all peripheral clocks are enabled during SLEEP mode.
lypinator	0:bb348c97df44	3236	* @{
lypinator	0:bb348c97df44	3237	*/
lypinator	0:bb348c97df44	3238	#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM2LPEN))
lypinator	0:bb348c97df44	3239	#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM3LPEN))
lypinator	0:bb348c97df44	3240	#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM4LPEN))
lypinator	0:bb348c97df44	3241	#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_SPI3LPEN))
lypinator	0:bb348c97df44	3242	#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C3LPEN))
lypinator	0:bb348c97df44	3243
lypinator	0:bb348c97df44	3244	#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
lypinator	0:bb348c97df44	3245	#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
lypinator	0:bb348c97df44	3246	#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
lypinator	0:bb348c97df44	3247	#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
lypinator	0:bb348c97df44	3248	#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
lypinator	0:bb348c97df44	3249	/**
lypinator	0:bb348c97df44	3250	* @}
lypinator	0:bb348c97df44	3251	*/
lypinator	0:bb348c97df44	3252
lypinator	0:bb348c97df44	3253	/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
lypinator	0:bb348c97df44	3254	* @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
lypinator	0:bb348c97df44	3255	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
lypinator	0:bb348c97df44	3256	* power consumption.
lypinator	0:bb348c97df44	3257	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
lypinator	0:bb348c97df44	3258	* @note By default, all peripheral clocks are enabled during SLEEP mode.
lypinator	0:bb348c97df44	3259	* @{
lypinator	0:bb348c97df44	3260	*/
lypinator	0:bb348c97df44	3261	#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SDIOLPEN))
lypinator	0:bb348c97df44	3262	#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI4LPEN))
lypinator	0:bb348c97df44	3263	#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM10LPEN))
lypinator	0:bb348c97df44	3264
lypinator	0:bb348c97df44	3265	#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
lypinator	0:bb348c97df44	3266	#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
lypinator	0:bb348c97df44	3267	#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
lypinator	0:bb348c97df44	3268	/**
lypinator	0:bb348c97df44	3269	* @}
lypinator	0:bb348c97df44	3270	*/
lypinator	0:bb348c97df44	3271	#endif /* STM32F401xC \|\| STM32F401xE*/
lypinator	0:bb348c97df44	3272	/----------------------------------------------------------------------------/
lypinator	0:bb348c97df44	3273
lypinator	0:bb348c97df44	3274	/-------------------------------- STM32F410xx -------------------------------/
lypinator	0:bb348c97df44	3275	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
lypinator	0:bb348c97df44	3276	/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
lypinator	0:bb348c97df44	3277	* @brief Enables or disables the AHB1 peripheral clock.
lypinator	0:bb348c97df44	3278	* @note After reset, the peripheral clock (used for registers read/write access)
lypinator	0:bb348c97df44	3279	* is disabled and the application software has to enable this clock before
lypinator	0:bb348c97df44	3280	* using it.
lypinator	0:bb348c97df44	3281	* @{
lypinator	0:bb348c97df44	3282	*/
lypinator	0:bb348c97df44	3283	#define __HAL_RCC_CRC_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	3284	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	3285	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
lypinator	0:bb348c97df44	3286	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	3287	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
lypinator	0:bb348c97df44	3288	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	3289	} while(0U)
lypinator	0:bb348c97df44	3290	#define __HAL_RCC_RNG_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	3291	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	3292	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RNGEN);\
lypinator	0:bb348c97df44	3293	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	3294	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RNGEN);\
lypinator	0:bb348c97df44	3295	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	3296	} while(0U)
lypinator	0:bb348c97df44	3297	#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
lypinator	0:bb348c97df44	3298	#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_RNGEN))
lypinator	0:bb348c97df44	3299	/**
lypinator	0:bb348c97df44	3300	* @}
lypinator	0:bb348c97df44	3301	*/
lypinator	0:bb348c97df44	3302
lypinator	0:bb348c97df44	3303	/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
lypinator	0:bb348c97df44	3304	* @brief Get the enable or disable status of the AHB1 peripheral clock.
lypinator	0:bb348c97df44	3305	* @note After reset, the peripheral clock (used for registers read/write access)
lypinator	0:bb348c97df44	3306	* is disabled and the application software has to enable this clock before
lypinator	0:bb348c97df44	3307	* using it.
lypinator	0:bb348c97df44	3308	* @{
lypinator	0:bb348c97df44	3309	*/
lypinator	0:bb348c97df44	3310	#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
lypinator	0:bb348c97df44	3311	#define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_RNGEN)) != RESET)
lypinator	0:bb348c97df44	3312
lypinator	0:bb348c97df44	3313	#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
lypinator	0:bb348c97df44	3314	#define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_RNGEN)) == RESET)
lypinator	0:bb348c97df44	3315	/**
lypinator	0:bb348c97df44	3316	* @}
lypinator	0:bb348c97df44	3317	*/
lypinator	0:bb348c97df44	3318
lypinator	0:bb348c97df44	3319	/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
lypinator	0:bb348c97df44	3320	* @brief Enable or disable the High Speed APB (APB1) peripheral clock.
lypinator	0:bb348c97df44	3321	* @{
lypinator	0:bb348c97df44	3322	*/
lypinator	0:bb348c97df44	3323	#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	3324	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	3325	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
lypinator	0:bb348c97df44	3326	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	3327	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
lypinator	0:bb348c97df44	3328	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	3329	} while(0U)
lypinator	0:bb348c97df44	3330	#define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	3331	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	3332	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\
lypinator	0:bb348c97df44	3333	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	3334	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\
lypinator	0:bb348c97df44	3335	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	3336	} while(0U)
lypinator	0:bb348c97df44	3337	#define __HAL_RCC_RTCAPB_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	3338	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	3339	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\
lypinator	0:bb348c97df44	3340	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	3341	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\
lypinator	0:bb348c97df44	3342	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	3343	} while(0U)
lypinator	0:bb348c97df44	3344	#define __HAL_RCC_FMPI2C1_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	3345	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	3346	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
lypinator	0:bb348c97df44	3347	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	3348	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
lypinator	0:bb348c97df44	3349	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	3350	} while(0U)
lypinator	0:bb348c97df44	3351	#define __HAL_RCC_DAC_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	3352	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	3353	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
lypinator	0:bb348c97df44	3354	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	3355	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
lypinator	0:bb348c97df44	3356	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	3357	} while(0U)
lypinator	0:bb348c97df44	3358
lypinator	0:bb348c97df44	3359	#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
lypinator	0:bb348c97df44	3360	#define __HAL_RCC_RTCAPB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_RTCAPBEN))
lypinator	0:bb348c97df44	3361	#define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_LPTIM1EN))
lypinator	0:bb348c97df44	3362	#define __HAL_RCC_FMPI2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_FMPI2C1EN))
lypinator	0:bb348c97df44	3363	#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
lypinator	0:bb348c97df44	3364	/**
lypinator	0:bb348c97df44	3365	* @}
lypinator	0:bb348c97df44	3366	*/
lypinator	0:bb348c97df44	3367
lypinator	0:bb348c97df44	3368	/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
lypinator	0:bb348c97df44	3369	* @brief Get the enable or disable status of the APB1 peripheral clock.
lypinator	0:bb348c97df44	3370	* @note After reset, the peripheral clock (used for registers read/write access)
lypinator	0:bb348c97df44	3371	* is disabled and the application software has to enable this clock before
lypinator	0:bb348c97df44	3372	* using it.
lypinator	0:bb348c97df44	3373	* @{
lypinator	0:bb348c97df44	3374	*/
lypinator	0:bb348c97df44	3375	#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
lypinator	0:bb348c97df44	3376	#define __HAL_RCC_RTCAPB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) != RESET)
lypinator	0:bb348c97df44	3377	#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) != RESET)
lypinator	0:bb348c97df44	3378	#define __HAL_RCC_FMPI2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) != RESET)
lypinator	0:bb348c97df44	3379	#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
lypinator	0:bb348c97df44	3380
lypinator	0:bb348c97df44	3381	#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
lypinator	0:bb348c97df44	3382	#define __HAL_RCC_RTCAPB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) == RESET)
lypinator	0:bb348c97df44	3383	#define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) == RESET)
lypinator	0:bb348c97df44	3384	#define __HAL_RCC_FMPI2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) == RESET)
lypinator	0:bb348c97df44	3385	#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
lypinator	0:bb348c97df44	3386	/**
lypinator	0:bb348c97df44	3387	* @}
lypinator	0:bb348c97df44	3388	*/
lypinator	0:bb348c97df44	3389
lypinator	0:bb348c97df44	3390	/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
lypinator	0:bb348c97df44	3391	* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
lypinator	0:bb348c97df44	3392	* @{
lypinator	0:bb348c97df44	3393	*/
lypinator	0:bb348c97df44	3394	#define __HAL_RCC_SPI5_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	3395	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	3396	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
lypinator	0:bb348c97df44	3397	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	3398	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
lypinator	0:bb348c97df44	3399	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	3400	} while(0U)
lypinator	0:bb348c97df44	3401	#define __HAL_RCC_EXTIT_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	3402	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	3403	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\
lypinator	0:bb348c97df44	3404	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	3405	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\
lypinator	0:bb348c97df44	3406	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	3407	} while(0U)
lypinator	0:bb348c97df44	3408	#define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
lypinator	0:bb348c97df44	3409	#define __HAL_RCC_EXTIT_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_EXTITEN))
lypinator	0:bb348c97df44	3410	/**
lypinator	0:bb348c97df44	3411	* @}
lypinator	0:bb348c97df44	3412	*/
lypinator	0:bb348c97df44	3413
lypinator	0:bb348c97df44	3414	/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
lypinator	0:bb348c97df44	3415	* @brief Get the enable or disable status of the APB2 peripheral clock.
lypinator	0:bb348c97df44	3416	* @note After reset, the peripheral clock (used for registers read/write access)
lypinator	0:bb348c97df44	3417	* is disabled and the application software has to enable this clock before
lypinator	0:bb348c97df44	3418	* using it.
lypinator	0:bb348c97df44	3419	* @{
lypinator	0:bb348c97df44	3420	*/
lypinator	0:bb348c97df44	3421	#define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET)
lypinator	0:bb348c97df44	3422	#define __HAL_RCC_EXTIT_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) != RESET)
lypinator	0:bb348c97df44	3423
lypinator	0:bb348c97df44	3424	#define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET)
lypinator	0:bb348c97df44	3425	#define __HAL_RCC_EXTIT_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) == RESET)
lypinator	0:bb348c97df44	3426	/**
lypinator	0:bb348c97df44	3427	* @}
lypinator	0:bb348c97df44	3428	*/
lypinator	0:bb348c97df44	3429
lypinator	0:bb348c97df44	3430	/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset
lypinator	0:bb348c97df44	3431	* @brief Force or release AHB1 peripheral reset.
lypinator	0:bb348c97df44	3432	* @{
lypinator	0:bb348c97df44	3433	*/
lypinator	0:bb348c97df44	3434	#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_CRCRST))
lypinator	0:bb348c97df44	3435	#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_RNGRST))
lypinator	0:bb348c97df44	3436	#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
lypinator	0:bb348c97df44	3437	#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_RNGRST))
lypinator	0:bb348c97df44	3438	/**
lypinator	0:bb348c97df44	3439	* @}
lypinator	0:bb348c97df44	3440	*/
lypinator	0:bb348c97df44	3441
lypinator	0:bb348c97df44	3442	/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset
lypinator	0:bb348c97df44	3443	* @brief Force or release AHB2 peripheral reset.
lypinator	0:bb348c97df44	3444	* @{
lypinator	0:bb348c97df44	3445	*/
lypinator	0:bb348c97df44	3446	#define __HAL_RCC_AHB2_FORCE_RESET()
lypinator	0:bb348c97df44	3447	#define __HAL_RCC_AHB2_RELEASE_RESET()
lypinator	0:bb348c97df44	3448	/**
lypinator	0:bb348c97df44	3449	* @}
lypinator	0:bb348c97df44	3450	*/
lypinator	0:bb348c97df44	3451
lypinator	0:bb348c97df44	3452	/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset
lypinator	0:bb348c97df44	3453	* @brief Force or release AHB3 peripheral reset.
lypinator	0:bb348c97df44	3454	* @{
lypinator	0:bb348c97df44	3455	*/
lypinator	0:bb348c97df44	3456	#define __HAL_RCC_AHB3_FORCE_RESET()
lypinator	0:bb348c97df44	3457	#define __HAL_RCC_AHB3_RELEASE_RESET()
lypinator	0:bb348c97df44	3458	/**
lypinator	0:bb348c97df44	3459	* @}
lypinator	0:bb348c97df44	3460	*/
lypinator	0:bb348c97df44	3461
lypinator	0:bb348c97df44	3462	/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset
lypinator	0:bb348c97df44	3463	* @brief Force or release APB1 peripheral reset.
lypinator	0:bb348c97df44	3464	* @{
lypinator	0:bb348c97df44	3465	*/
lypinator	0:bb348c97df44	3466	#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM6RST))
lypinator	0:bb348c97df44	3467	#define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_LPTIM1RST))
lypinator	0:bb348c97df44	3468	#define __HAL_RCC_FMPI2C1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_FMPI2C1RST))
lypinator	0:bb348c97df44	3469	#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DACRST))
lypinator	0:bb348c97df44	3470
lypinator	0:bb348c97df44	3471	#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
lypinator	0:bb348c97df44	3472	#define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LPTIM1RST))
lypinator	0:bb348c97df44	3473	#define __HAL_RCC_FMPI2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_FMPI2C1RST))
lypinator	0:bb348c97df44	3474	#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
lypinator	0:bb348c97df44	3475	/**
lypinator	0:bb348c97df44	3476	* @}
lypinator	0:bb348c97df44	3477	*/
lypinator	0:bb348c97df44	3478
lypinator	0:bb348c97df44	3479	/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
lypinator	0:bb348c97df44	3480	* @brief Force or release APB2 peripheral reset.
lypinator	0:bb348c97df44	3481	* @{
lypinator	0:bb348c97df44	3482	*/
lypinator	0:bb348c97df44	3483	#define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI5RST))
lypinator	0:bb348c97df44	3484	#define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
lypinator	0:bb348c97df44	3485	/**
lypinator	0:bb348c97df44	3486	* @}
lypinator	0:bb348c97df44	3487	*/
lypinator	0:bb348c97df44	3488
lypinator	0:bb348c97df44	3489	/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
lypinator	0:bb348c97df44	3490	* @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
lypinator	0:bb348c97df44	3491	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
lypinator	0:bb348c97df44	3492	* power consumption.
lypinator	0:bb348c97df44	3493	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
lypinator	0:bb348c97df44	3494	* @note By default, all peripheral clocks are enabled during SLEEP mode.
lypinator	0:bb348c97df44	3495	* @{
lypinator	0:bb348c97df44	3496	*/
lypinator	0:bb348c97df44	3497	#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_RNGLPEN))
lypinator	0:bb348c97df44	3498	#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_CRCLPEN))
lypinator	0:bb348c97df44	3499	#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_FLITFLPEN))
lypinator	0:bb348c97df44	3500	#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM1LPEN))
lypinator	0:bb348c97df44	3501
lypinator	0:bb348c97df44	3502	#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_RNGLPEN))
lypinator	0:bb348c97df44	3503	#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
lypinator	0:bb348c97df44	3504	#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
lypinator	0:bb348c97df44	3505	#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
lypinator	0:bb348c97df44	3506	/**
lypinator	0:bb348c97df44	3507	* @}
lypinator	0:bb348c97df44	3508	*/
lypinator	0:bb348c97df44	3509
lypinator	0:bb348c97df44	3510	/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
lypinator	0:bb348c97df44	3511	* @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
lypinator	0:bb348c97df44	3512	* @{
lypinator	0:bb348c97df44	3513	*/
lypinator	0:bb348c97df44	3514	#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM6LPEN))
lypinator	0:bb348c97df44	3515	#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_LPTIM1LPEN))
lypinator	0:bb348c97df44	3516	#define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_RTCAPBLPEN))
lypinator	0:bb348c97df44	3517	#define __HAL_RCC_FMPI2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_FMPI2C1LPEN))
lypinator	0:bb348c97df44	3518	#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_DACLPEN))
lypinator	0:bb348c97df44	3519
lypinator	0:bb348c97df44	3520	#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
lypinator	0:bb348c97df44	3521	#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LPTIM1LPEN))
lypinator	0:bb348c97df44	3522	#define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_RTCAPBLPEN))
lypinator	0:bb348c97df44	3523	#define __HAL_RCC_FMPI2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_FMPI2C1LPEN))
lypinator	0:bb348c97df44	3524	#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
lypinator	0:bb348c97df44	3525	/**
lypinator	0:bb348c97df44	3526	* @}
lypinator	0:bb348c97df44	3527	*/
lypinator	0:bb348c97df44	3528
lypinator	0:bb348c97df44	3529	/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
lypinator	0:bb348c97df44	3530	* @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
lypinator	0:bb348c97df44	3531	* @{
lypinator	0:bb348c97df44	3532	*/
lypinator	0:bb348c97df44	3533	#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI5LPEN))
lypinator	0:bb348c97df44	3534	#define __HAL_RCC_EXTIT_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_EXTITLPEN))
lypinator	0:bb348c97df44	3535	#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
lypinator	0:bb348c97df44	3536	#define __HAL_RCC_EXTIT_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_EXTITLPEN))
lypinator	0:bb348c97df44	3537	/**
lypinator	0:bb348c97df44	3538	* @}
lypinator	0:bb348c97df44	3539	*/
lypinator	0:bb348c97df44	3540
lypinator	0:bb348c97df44	3541	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
lypinator	0:bb348c97df44	3542	/----------------------------------------------------------------------------/
lypinator	0:bb348c97df44	3543
lypinator	0:bb348c97df44	3544	/-------------------------------- STM32F411xx -------------------------------/
lypinator	0:bb348c97df44	3545	#if defined(STM32F411xE)
lypinator	0:bb348c97df44	3546	/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
lypinator	0:bb348c97df44	3547	* @brief Enables or disables the AHB1 peripheral clock.
lypinator	0:bb348c97df44	3548	* @note After reset, the peripheral clock (used for registers read/write access)
lypinator	0:bb348c97df44	3549	* is disabled and the application software has to enable this clock before
lypinator	0:bb348c97df44	3550	* using it.
lypinator	0:bb348c97df44	3551	* @{
lypinator	0:bb348c97df44	3552	*/
lypinator	0:bb348c97df44	3553	#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	3554	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	3555	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
lypinator	0:bb348c97df44	3556	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	3557	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
lypinator	0:bb348c97df44	3558	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	3559	} while(0U)
lypinator	0:bb348c97df44	3560	#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	3561	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	3562	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
lypinator	0:bb348c97df44	3563	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	3564	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
lypinator	0:bb348c97df44	3565	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	3566	} while(0U)
lypinator	0:bb348c97df44	3567	#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	3568	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	3569	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
lypinator	0:bb348c97df44	3570	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	3571	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
lypinator	0:bb348c97df44	3572	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	3573	} while(0U)
lypinator	0:bb348c97df44	3574	#define __HAL_RCC_CRC_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	3575	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	3576	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
lypinator	0:bb348c97df44	3577	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	3578	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
lypinator	0:bb348c97df44	3579	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	3580	} while(0U)
lypinator	0:bb348c97df44	3581	#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
lypinator	0:bb348c97df44	3582	#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
lypinator	0:bb348c97df44	3583	#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
lypinator	0:bb348c97df44	3584	#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
lypinator	0:bb348c97df44	3585	/**
lypinator	0:bb348c97df44	3586	* @}
lypinator	0:bb348c97df44	3587	*/
lypinator	0:bb348c97df44	3588
lypinator	0:bb348c97df44	3589	/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
lypinator	0:bb348c97df44	3590	* @brief Get the enable or disable status of the AHB1 peripheral clock.
lypinator	0:bb348c97df44	3591	* @note After reset, the peripheral clock (used for registers read/write access)
lypinator	0:bb348c97df44	3592	* is disabled and the application software has to enable this clock before
lypinator	0:bb348c97df44	3593	* using it.
lypinator	0:bb348c97df44	3594	* @{
lypinator	0:bb348c97df44	3595	*/
lypinator	0:bb348c97df44	3596	#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)
lypinator	0:bb348c97df44	3597	#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)
lypinator	0:bb348c97df44	3598	#define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) != RESET)
lypinator	0:bb348c97df44	3599	#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
lypinator	0:bb348c97df44	3600
lypinator	0:bb348c97df44	3601	#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)
lypinator	0:bb348c97df44	3602	#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)
lypinator	0:bb348c97df44	3603	#define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET)
lypinator	0:bb348c97df44	3604	#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
lypinator	0:bb348c97df44	3605	/**
lypinator	0:bb348c97df44	3606	* @}
lypinator	0:bb348c97df44	3607	*/
lypinator	0:bb348c97df44	3608
lypinator	0:bb348c97df44	3609	/** @defgroup RCCEX_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
lypinator	0:bb348c97df44	3610	* @brief Enable or disable the AHB2 peripheral clock.
lypinator	0:bb348c97df44	3611	* @note After reset, the peripheral clock (used for registers read/write access)
lypinator	0:bb348c97df44	3612	* is disabled and the application software has to enable this clock before
lypinator	0:bb348c97df44	3613	* using it.
lypinator	0:bb348c97df44	3614	* @{
lypinator	0:bb348c97df44	3615	*/
lypinator	0:bb348c97df44	3616	#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR \|= (RCC_AHB2ENR_OTGFSEN));\
lypinator	0:bb348c97df44	3617	__HAL_RCC_SYSCFG_CLK_ENABLE();\
lypinator	0:bb348c97df44	3618	}while(0U)
lypinator	0:bb348c97df44	3619
lypinator	0:bb348c97df44	3620	#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
lypinator	0:bb348c97df44	3621	/**
lypinator	0:bb348c97df44	3622	* @}
lypinator	0:bb348c97df44	3623	*/
lypinator	0:bb348c97df44	3624
lypinator	0:bb348c97df44	3625	/** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status
lypinator	0:bb348c97df44	3626	* @brief Get the enable or disable status of the AHB2 peripheral clock.
lypinator	0:bb348c97df44	3627	* @note After reset, the peripheral clock (used for registers read/write access)
lypinator	0:bb348c97df44	3628	* is disabled and the application software has to enable this clock before
lypinator	0:bb348c97df44	3629	* using it.
lypinator	0:bb348c97df44	3630	* @{
lypinator	0:bb348c97df44	3631	*/
lypinator	0:bb348c97df44	3632	#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
lypinator	0:bb348c97df44	3633	#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
lypinator	0:bb348c97df44	3634	/**
lypinator	0:bb348c97df44	3635	* @}
lypinator	0:bb348c97df44	3636	*/
lypinator	0:bb348c97df44	3637
lypinator	0:bb348c97df44	3638	/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
lypinator	0:bb348c97df44	3639	* @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
lypinator	0:bb348c97df44	3640	* @note After reset, the peripheral clock (used for registers read/write access)
lypinator	0:bb348c97df44	3641	* is disabled and the application software has to enable this clock before
lypinator	0:bb348c97df44	3642	* using it.
lypinator	0:bb348c97df44	3643	* @{
lypinator	0:bb348c97df44	3644	*/
lypinator	0:bb348c97df44	3645	#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	3646	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	3647	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
lypinator	0:bb348c97df44	3648	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	3649	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
lypinator	0:bb348c97df44	3650	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	3651	} while(0U)
lypinator	0:bb348c97df44	3652	#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	3653	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	3654	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
lypinator	0:bb348c97df44	3655	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	3656	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
lypinator	0:bb348c97df44	3657	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	3658	} while(0U)
lypinator	0:bb348c97df44	3659	#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	3660	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	3661	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
lypinator	0:bb348c97df44	3662	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	3663	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
lypinator	0:bb348c97df44	3664	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	3665	} while(0U)
lypinator	0:bb348c97df44	3666	#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	3667	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	3668	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
lypinator	0:bb348c97df44	3669	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	3670	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
lypinator	0:bb348c97df44	3671	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	3672	} while(0U)
lypinator	0:bb348c97df44	3673	#define __HAL_RCC_I2C3_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	3674	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	3675	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
lypinator	0:bb348c97df44	3676	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	3677	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
lypinator	0:bb348c97df44	3678	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	3679	} while(0U)
lypinator	0:bb348c97df44	3680	#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
lypinator	0:bb348c97df44	3681	#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
lypinator	0:bb348c97df44	3682	#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
lypinator	0:bb348c97df44	3683	#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
lypinator	0:bb348c97df44	3684	#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
lypinator	0:bb348c97df44	3685	/**
lypinator	0:bb348c97df44	3686	* @}
lypinator	0:bb348c97df44	3687	*/
lypinator	0:bb348c97df44	3688
lypinator	0:bb348c97df44	3689	/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
lypinator	0:bb348c97df44	3690	* @brief Get the enable or disable status of the APB1 peripheral clock.
lypinator	0:bb348c97df44	3691	* @note After reset, the peripheral clock (used for registers read/write access)
lypinator	0:bb348c97df44	3692	* is disabled and the application software has to enable this clock before
lypinator	0:bb348c97df44	3693	* using it.
lypinator	0:bb348c97df44	3694	* @{
lypinator	0:bb348c97df44	3695	*/
lypinator	0:bb348c97df44	3696	#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
lypinator	0:bb348c97df44	3697	#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
lypinator	0:bb348c97df44	3698	#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
lypinator	0:bb348c97df44	3699	#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
lypinator	0:bb348c97df44	3700	#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
lypinator	0:bb348c97df44	3701
lypinator	0:bb348c97df44	3702	#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
lypinator	0:bb348c97df44	3703	#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
lypinator	0:bb348c97df44	3704	#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
lypinator	0:bb348c97df44	3705	#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
lypinator	0:bb348c97df44	3706	#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
lypinator	0:bb348c97df44	3707	/**
lypinator	0:bb348c97df44	3708	* @}
lypinator	0:bb348c97df44	3709	*/
lypinator	0:bb348c97df44	3710
lypinator	0:bb348c97df44	3711	/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
lypinator	0:bb348c97df44	3712	* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
lypinator	0:bb348c97df44	3713	* @{
lypinator	0:bb348c97df44	3714	*/
lypinator	0:bb348c97df44	3715	#define __HAL_RCC_SPI5_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	3716	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	3717	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
lypinator	0:bb348c97df44	3718	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	3719	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
lypinator	0:bb348c97df44	3720	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	3721	} while(0U)
lypinator	0:bb348c97df44	3722	#define __HAL_RCC_SDIO_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	3723	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	3724	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
lypinator	0:bb348c97df44	3725	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	3726	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
lypinator	0:bb348c97df44	3727	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	3728	} while(0U)
lypinator	0:bb348c97df44	3729	#define __HAL_RCC_SPI4_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	3730	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	3731	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
lypinator	0:bb348c97df44	3732	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	3733	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
lypinator	0:bb348c97df44	3734	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	3735	} while(0U)
lypinator	0:bb348c97df44	3736	#define __HAL_RCC_TIM10_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	3737	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	3738	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
lypinator	0:bb348c97df44	3739	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	3740	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
lypinator	0:bb348c97df44	3741	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	3742	} while(0U)
lypinator	0:bb348c97df44	3743	#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
lypinator	0:bb348c97df44	3744	#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
lypinator	0:bb348c97df44	3745	#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
lypinator	0:bb348c97df44	3746	#define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
lypinator	0:bb348c97df44	3747	/**
lypinator	0:bb348c97df44	3748	* @}
lypinator	0:bb348c97df44	3749	*/
lypinator	0:bb348c97df44	3750
lypinator	0:bb348c97df44	3751	/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
lypinator	0:bb348c97df44	3752	* @brief Get the enable or disable status of the APB2 peripheral clock.
lypinator	0:bb348c97df44	3753	* @note After reset, the peripheral clock (used for registers read/write access)
lypinator	0:bb348c97df44	3754	* is disabled and the application software has to enable this clock before
lypinator	0:bb348c97df44	3755	* using it.
lypinator	0:bb348c97df44	3756	* @{
lypinator	0:bb348c97df44	3757	*/
lypinator	0:bb348c97df44	3758	#define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET)
lypinator	0:bb348c97df44	3759	#define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)
lypinator	0:bb348c97df44	3760	#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)
lypinator	0:bb348c97df44	3761	#define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET)
lypinator	0:bb348c97df44	3762
lypinator	0:bb348c97df44	3763	#define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET)
lypinator	0:bb348c97df44	3764	#define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
lypinator	0:bb348c97df44	3765	#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)
lypinator	0:bb348c97df44	3766	#define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET)
lypinator	0:bb348c97df44	3767	/**
lypinator	0:bb348c97df44	3768	* @}
lypinator	0:bb348c97df44	3769	*/
lypinator	0:bb348c97df44	3770
lypinator	0:bb348c97df44	3771	/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset
lypinator	0:bb348c97df44	3772	* @brief Force or release AHB1 peripheral reset.
lypinator	0:bb348c97df44	3773	* @{
lypinator	0:bb348c97df44	3774	*/
lypinator	0:bb348c97df44	3775	#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIODRST))
lypinator	0:bb348c97df44	3776	#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOERST))
lypinator	0:bb348c97df44	3777	#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_CRCRST))
lypinator	0:bb348c97df44	3778
lypinator	0:bb348c97df44	3779	#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
lypinator	0:bb348c97df44	3780	#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
lypinator	0:bb348c97df44	3781	#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
lypinator	0:bb348c97df44	3782	/**
lypinator	0:bb348c97df44	3783	* @}
lypinator	0:bb348c97df44	3784	*/
lypinator	0:bb348c97df44	3785
lypinator	0:bb348c97df44	3786	/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset
lypinator	0:bb348c97df44	3787	* @brief Force or release AHB2 peripheral reset.
lypinator	0:bb348c97df44	3788	* @{
lypinator	0:bb348c97df44	3789	*/
lypinator	0:bb348c97df44	3790	#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU)
lypinator	0:bb348c97df44	3791	#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_OTGFSRST))
lypinator	0:bb348c97df44	3792
lypinator	0:bb348c97df44	3793	#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U)
lypinator	0:bb348c97df44	3794	#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
lypinator	0:bb348c97df44	3795	/**
lypinator	0:bb348c97df44	3796	* @}
lypinator	0:bb348c97df44	3797	*/
lypinator	0:bb348c97df44	3798
lypinator	0:bb348c97df44	3799	/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset
lypinator	0:bb348c97df44	3800	* @brief Force or release AHB3 peripheral reset.
lypinator	0:bb348c97df44	3801	* @{
lypinator	0:bb348c97df44	3802	*/
lypinator	0:bb348c97df44	3803	#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
lypinator	0:bb348c97df44	3804	#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U)
lypinator	0:bb348c97df44	3805	/**
lypinator	0:bb348c97df44	3806	* @}
lypinator	0:bb348c97df44	3807	*/
lypinator	0:bb348c97df44	3808
lypinator	0:bb348c97df44	3809	/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset
lypinator	0:bb348c97df44	3810	* @brief Force or release APB1 peripheral reset.
lypinator	0:bb348c97df44	3811	* @{
lypinator	0:bb348c97df44	3812	*/
lypinator	0:bb348c97df44	3813	#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM2RST))
lypinator	0:bb348c97df44	3814	#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM3RST))
lypinator	0:bb348c97df44	3815	#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM4RST))
lypinator	0:bb348c97df44	3816	#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI3RST))
lypinator	0:bb348c97df44	3817	#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C3RST))
lypinator	0:bb348c97df44	3818
lypinator	0:bb348c97df44	3819	#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
lypinator	0:bb348c97df44	3820	#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
lypinator	0:bb348c97df44	3821	#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
lypinator	0:bb348c97df44	3822	#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
lypinator	0:bb348c97df44	3823	#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
lypinator	0:bb348c97df44	3824	/**
lypinator	0:bb348c97df44	3825	* @}
lypinator	0:bb348c97df44	3826	*/
lypinator	0:bb348c97df44	3827
lypinator	0:bb348c97df44	3828	/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
lypinator	0:bb348c97df44	3829	* @brief Force or release APB2 peripheral reset.
lypinator	0:bb348c97df44	3830	* @{
lypinator	0:bb348c97df44	3831	*/
lypinator	0:bb348c97df44	3832	#define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI5RST))
lypinator	0:bb348c97df44	3833	#define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SDIORST))
lypinator	0:bb348c97df44	3834	#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI4RST))
lypinator	0:bb348c97df44	3835	#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM10RST))
lypinator	0:bb348c97df44	3836
lypinator	0:bb348c97df44	3837	#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
lypinator	0:bb348c97df44	3838	#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
lypinator	0:bb348c97df44	3839	#define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
lypinator	0:bb348c97df44	3840	#define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
lypinator	0:bb348c97df44	3841	/**
lypinator	0:bb348c97df44	3842	* @}
lypinator	0:bb348c97df44	3843	*/
lypinator	0:bb348c97df44	3844
lypinator	0:bb348c97df44	3845	/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
lypinator	0:bb348c97df44	3846	* @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
lypinator	0:bb348c97df44	3847	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
lypinator	0:bb348c97df44	3848	* power consumption.
lypinator	0:bb348c97df44	3849	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
lypinator	0:bb348c97df44	3850	* @note By default, all peripheral clocks are enabled during SLEEP mode.
lypinator	0:bb348c97df44	3851	* @{
lypinator	0:bb348c97df44	3852	*/
lypinator	0:bb348c97df44	3853	#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIODLPEN))
lypinator	0:bb348c97df44	3854	#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOELPEN))
lypinator	0:bb348c97df44	3855	#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_CRCLPEN))
lypinator	0:bb348c97df44	3856	#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_FLITFLPEN))
lypinator	0:bb348c97df44	3857	#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM1LPEN))
lypinator	0:bb348c97df44	3858
lypinator	0:bb348c97df44	3859	#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
lypinator	0:bb348c97df44	3860	#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
lypinator	0:bb348c97df44	3861	#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
lypinator	0:bb348c97df44	3862	#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
lypinator	0:bb348c97df44	3863	#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
lypinator	0:bb348c97df44	3864	/**
lypinator	0:bb348c97df44	3865	* @}
lypinator	0:bb348c97df44	3866	*/
lypinator	0:bb348c97df44	3867
lypinator	0:bb348c97df44	3868	/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
lypinator	0:bb348c97df44	3869	* @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
lypinator	0:bb348c97df44	3870	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
lypinator	0:bb348c97df44	3871	* power consumption.
lypinator	0:bb348c97df44	3872	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
lypinator	0:bb348c97df44	3873	* @note By default, all peripheral clocks are enabled during SLEEP mode.
lypinator	0:bb348c97df44	3874	* @{
lypinator	0:bb348c97df44	3875	*/
lypinator	0:bb348c97df44	3876	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_OTGFSLPEN))
lypinator	0:bb348c97df44	3877	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
lypinator	0:bb348c97df44	3878	/**
lypinator	0:bb348c97df44	3879	* @}
lypinator	0:bb348c97df44	3880	*/
lypinator	0:bb348c97df44	3881
lypinator	0:bb348c97df44	3882	/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
lypinator	0:bb348c97df44	3883	* @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
lypinator	0:bb348c97df44	3884	* @{
lypinator	0:bb348c97df44	3885	*/
lypinator	0:bb348c97df44	3886	#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM2LPEN))
lypinator	0:bb348c97df44	3887	#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM3LPEN))
lypinator	0:bb348c97df44	3888	#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM4LPEN))
lypinator	0:bb348c97df44	3889	#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_SPI3LPEN))
lypinator	0:bb348c97df44	3890	#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C3LPEN))
lypinator	0:bb348c97df44	3891
lypinator	0:bb348c97df44	3892	#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
lypinator	0:bb348c97df44	3893	#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
lypinator	0:bb348c97df44	3894	#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
lypinator	0:bb348c97df44	3895	#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
lypinator	0:bb348c97df44	3896	#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
lypinator	0:bb348c97df44	3897	/**
lypinator	0:bb348c97df44	3898	* @}
lypinator	0:bb348c97df44	3899	*/
lypinator	0:bb348c97df44	3900
lypinator	0:bb348c97df44	3901	/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
lypinator	0:bb348c97df44	3902	* @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
lypinator	0:bb348c97df44	3903	* @{
lypinator	0:bb348c97df44	3904	*/
lypinator	0:bb348c97df44	3905	#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI5LPEN))
lypinator	0:bb348c97df44	3906	#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SDIOLPEN))
lypinator	0:bb348c97df44	3907	#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI4LPEN))
lypinator	0:bb348c97df44	3908	#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM10LPEN))
lypinator	0:bb348c97df44	3909
lypinator	0:bb348c97df44	3910	#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
lypinator	0:bb348c97df44	3911	#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
lypinator	0:bb348c97df44	3912	#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
lypinator	0:bb348c97df44	3913	#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
lypinator	0:bb348c97df44	3914	/**
lypinator	0:bb348c97df44	3915	* @}
lypinator	0:bb348c97df44	3916	*/
lypinator	0:bb348c97df44	3917	#endif /* STM32F411xE */
lypinator	0:bb348c97df44	3918	/----------------------------------------------------------------------------/
lypinator	0:bb348c97df44	3919
lypinator	0:bb348c97df44	3920	/---------------------------------- STM32F446xx -----------------------------/
lypinator	0:bb348c97df44	3921	#if defined(STM32F446xx)
lypinator	0:bb348c97df44	3922	/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
lypinator	0:bb348c97df44	3923	* @brief Enables or disables the AHB1 peripheral clock.
lypinator	0:bb348c97df44	3924	* @note After reset, the peripheral clock (used for registers read/write access)
lypinator	0:bb348c97df44	3925	* is disabled and the application software has to enable this clock before
lypinator	0:bb348c97df44	3926	* using it.
lypinator	0:bb348c97df44	3927	* @{
lypinator	0:bb348c97df44	3928	*/
lypinator	0:bb348c97df44	3929	#define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	3930	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	3931	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
lypinator	0:bb348c97df44	3932	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	3933	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
lypinator	0:bb348c97df44	3934	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	3935	} while(0U)
lypinator	0:bb348c97df44	3936	#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	3937	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	3938	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
lypinator	0:bb348c97df44	3939	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	3940	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
lypinator	0:bb348c97df44	3941	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	3942	} while(0U)
lypinator	0:bb348c97df44	3943	#define __HAL_RCC_CRC_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	3944	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	3945	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
lypinator	0:bb348c97df44	3946	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	3947	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
lypinator	0:bb348c97df44	3948	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	3949	} while(0U)
lypinator	0:bb348c97df44	3950	#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	3951	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	3952	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
lypinator	0:bb348c97df44	3953	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	3954	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
lypinator	0:bb348c97df44	3955	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	3956	} while(0U)
lypinator	0:bb348c97df44	3957	#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	3958	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	3959	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
lypinator	0:bb348c97df44	3960	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	3961	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
lypinator	0:bb348c97df44	3962	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	3963	} while(0U)
lypinator	0:bb348c97df44	3964	#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	3965	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	3966	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
lypinator	0:bb348c97df44	3967	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	3968	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
lypinator	0:bb348c97df44	3969	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	3970	} while(0U)
lypinator	0:bb348c97df44	3971	#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	3972	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	3973	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
lypinator	0:bb348c97df44	3974	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	3975	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
lypinator	0:bb348c97df44	3976	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	3977	} while(0U)
lypinator	0:bb348c97df44	3978	#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	3979	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	3980	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
lypinator	0:bb348c97df44	3981	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	3982	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
lypinator	0:bb348c97df44	3983	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	3984	} while(0U)
lypinator	0:bb348c97df44	3985	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	3986	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	3987	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
lypinator	0:bb348c97df44	3988	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	3989	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
lypinator	0:bb348c97df44	3990	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	3991	} while(0U)
lypinator	0:bb348c97df44	3992	#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
lypinator	0:bb348c97df44	3993	#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
lypinator	0:bb348c97df44	3994	#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
lypinator	0:bb348c97df44	3995	#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
lypinator	0:bb348c97df44	3996	#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
lypinator	0:bb348c97df44	3997	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
lypinator	0:bb348c97df44	3998	#define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
lypinator	0:bb348c97df44	3999	#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
lypinator	0:bb348c97df44	4000	#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
lypinator	0:bb348c97df44	4001	/**
lypinator	0:bb348c97df44	4002	* @}
lypinator	0:bb348c97df44	4003	*/
lypinator	0:bb348c97df44	4004
lypinator	0:bb348c97df44	4005	/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
lypinator	0:bb348c97df44	4006	* @brief Get the enable or disable status of the AHB1 peripheral clock.
lypinator	0:bb348c97df44	4007	* @note After reset, the peripheral clock (used for registers read/write access)
lypinator	0:bb348c97df44	4008	* is disabled and the application software has to enable this clock before
lypinator	0:bb348c97df44	4009	* using it.
lypinator	0:bb348c97df44	4010	* @{
lypinator	0:bb348c97df44	4011	*/
lypinator	0:bb348c97df44	4012	#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)
lypinator	0:bb348c97df44	4013	#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)
lypinator	0:bb348c97df44	4014	#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET)
lypinator	0:bb348c97df44	4015	#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET)
lypinator	0:bb348c97df44	4016	#define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET)
lypinator	0:bb348c97df44	4017	#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET)
lypinator	0:bb348c97df44	4018	#define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET)
lypinator	0:bb348c97df44	4019	#define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN))!= RESET)
lypinator	0:bb348c97df44	4020	#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
lypinator	0:bb348c97df44	4021
lypinator	0:bb348c97df44	4022	#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)
lypinator	0:bb348c97df44	4023	#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)
lypinator	0:bb348c97df44	4024	#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET)
lypinator	0:bb348c97df44	4025	#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET)
lypinator	0:bb348c97df44	4026	#define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET)
lypinator	0:bb348c97df44	4027	#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) == RESET)
lypinator	0:bb348c97df44	4028	#define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET)
lypinator	0:bb348c97df44	4029	#define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET)
lypinator	0:bb348c97df44	4030	#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
lypinator	0:bb348c97df44	4031	/**
lypinator	0:bb348c97df44	4032	* @}
lypinator	0:bb348c97df44	4033	*/
lypinator	0:bb348c97df44	4034
lypinator	0:bb348c97df44	4035	/** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
lypinator	0:bb348c97df44	4036	* @brief Enable or disable the AHB2 peripheral clock.
lypinator	0:bb348c97df44	4037	* @note After reset, the peripheral clock (used for registers read/write access)
lypinator	0:bb348c97df44	4038	* is disabled and the application software has to enable this clock before
lypinator	0:bb348c97df44	4039	* using it.
lypinator	0:bb348c97df44	4040	* @{
lypinator	0:bb348c97df44	4041	*/
lypinator	0:bb348c97df44	4042	#define __HAL_RCC_DCMI_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	4043	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	4044	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
lypinator	0:bb348c97df44	4045	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	4046	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
lypinator	0:bb348c97df44	4047	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	4048	} while(0U)
lypinator	0:bb348c97df44	4049	#define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
lypinator	0:bb348c97df44	4050	#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR \|= (RCC_AHB2ENR_OTGFSEN));\
lypinator	0:bb348c97df44	4051	__HAL_RCC_SYSCFG_CLK_ENABLE();\
lypinator	0:bb348c97df44	4052	}while(0U)
lypinator	0:bb348c97df44	4053
lypinator	0:bb348c97df44	4054	#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
lypinator	0:bb348c97df44	4055
lypinator	0:bb348c97df44	4056	#define __HAL_RCC_RNG_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	4057	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	4058	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
lypinator	0:bb348c97df44	4059	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	4060	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
lypinator	0:bb348c97df44	4061	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	4062	} while(0U)
lypinator	0:bb348c97df44	4063	#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
lypinator	0:bb348c97df44	4064	/**
lypinator	0:bb348c97df44	4065	* @}
lypinator	0:bb348c97df44	4066	*/
lypinator	0:bb348c97df44	4067
lypinator	0:bb348c97df44	4068	/** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status
lypinator	0:bb348c97df44	4069	* @brief Get the enable or disable status of the AHB2 peripheral clock.
lypinator	0:bb348c97df44	4070	* @note After reset, the peripheral clock (used for registers read/write access)
lypinator	0:bb348c97df44	4071	* is disabled and the application software has to enable this clock before
lypinator	0:bb348c97df44	4072	* using it.
lypinator	0:bb348c97df44	4073	* @{
lypinator	0:bb348c97df44	4074	*/
lypinator	0:bb348c97df44	4075	#define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET)
lypinator	0:bb348c97df44	4076	#define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET)
lypinator	0:bb348c97df44	4077
lypinator	0:bb348c97df44	4078	#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
lypinator	0:bb348c97df44	4079	#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
lypinator	0:bb348c97df44	4080
lypinator	0:bb348c97df44	4081	#define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET)
lypinator	0:bb348c97df44	4082	#define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET)
lypinator	0:bb348c97df44	4083	/**
lypinator	0:bb348c97df44	4084	* @}
lypinator	0:bb348c97df44	4085	*/
lypinator	0:bb348c97df44	4086
lypinator	0:bb348c97df44	4087	/** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable
lypinator	0:bb348c97df44	4088	* @brief Enables or disables the AHB3 peripheral clock.
lypinator	0:bb348c97df44	4089	* @note After reset, the peripheral clock (used for registers read/write access)
lypinator	0:bb348c97df44	4090	* is disabled and the application software has to enable this clock before
lypinator	0:bb348c97df44	4091	* using it.
lypinator	0:bb348c97df44	4092	* @{
lypinator	0:bb348c97df44	4093	*/
lypinator	0:bb348c97df44	4094	#define __HAL_RCC_FMC_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	4095	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	4096	SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
lypinator	0:bb348c97df44	4097	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	4098	tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
lypinator	0:bb348c97df44	4099	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	4100	} while(0U)
lypinator	0:bb348c97df44	4101	#define __HAL_RCC_QSPI_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	4102	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	4103	SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
lypinator	0:bb348c97df44	4104	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	4105	tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
lypinator	0:bb348c97df44	4106	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	4107	} while(0U)
lypinator	0:bb348c97df44	4108
lypinator	0:bb348c97df44	4109	#define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN))
lypinator	0:bb348c97df44	4110	#define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN))
lypinator	0:bb348c97df44	4111	/**
lypinator	0:bb348c97df44	4112	* @}
lypinator	0:bb348c97df44	4113	*/
lypinator	0:bb348c97df44	4114
lypinator	0:bb348c97df44	4115	/** @defgroup RCCEx_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enable Disable Status
lypinator	0:bb348c97df44	4116	* @brief Get the enable or disable status of the AHB3 peripheral clock.
lypinator	0:bb348c97df44	4117	* @note After reset, the peripheral clock (used for registers read/write access)
lypinator	0:bb348c97df44	4118	* is disabled and the application software has to enable this clock before
lypinator	0:bb348c97df44	4119	* using it.
lypinator	0:bb348c97df44	4120	* @{
lypinator	0:bb348c97df44	4121	*/
lypinator	0:bb348c97df44	4122	#define __HAL_RCC_FMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) != RESET)
lypinator	0:bb348c97df44	4123	#define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET)
lypinator	0:bb348c97df44	4124
lypinator	0:bb348c97df44	4125	#define __HAL_RCC_FMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) == RESET)
lypinator	0:bb348c97df44	4126	#define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET)
lypinator	0:bb348c97df44	4127	/**
lypinator	0:bb348c97df44	4128	* @}
lypinator	0:bb348c97df44	4129	*/
lypinator	0:bb348c97df44	4130
lypinator	0:bb348c97df44	4131	/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
lypinator	0:bb348c97df44	4132	* @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
lypinator	0:bb348c97df44	4133	* @note After reset, the peripheral clock (used for registers read/write access)
lypinator	0:bb348c97df44	4134	* is disabled and the application software has to enable this clock before
lypinator	0:bb348c97df44	4135	* using it.
lypinator	0:bb348c97df44	4136	* @{
lypinator	0:bb348c97df44	4137	*/
lypinator	0:bb348c97df44	4138	#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	4139	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	4140	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
lypinator	0:bb348c97df44	4141	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	4142	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
lypinator	0:bb348c97df44	4143	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	4144	} while(0U)
lypinator	0:bb348c97df44	4145	#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	4146	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	4147	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
lypinator	0:bb348c97df44	4148	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	4149	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
lypinator	0:bb348c97df44	4150	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	4151	} while(0U)
lypinator	0:bb348c97df44	4152	#define __HAL_RCC_TIM12_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	4153	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	4154	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
lypinator	0:bb348c97df44	4155	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	4156	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
lypinator	0:bb348c97df44	4157	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	4158	} while(0U)
lypinator	0:bb348c97df44	4159	#define __HAL_RCC_TIM13_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	4160	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	4161	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
lypinator	0:bb348c97df44	4162	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	4163	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
lypinator	0:bb348c97df44	4164	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	4165	} while(0U)
lypinator	0:bb348c97df44	4166	#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	4167	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	4168	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
lypinator	0:bb348c97df44	4169	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	4170	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
lypinator	0:bb348c97df44	4171	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	4172	} while(0U)
lypinator	0:bb348c97df44	4173	#define __HAL_RCC_SPDIFRX_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	4174	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	4175	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\
lypinator	0:bb348c97df44	4176	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	4177	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\
lypinator	0:bb348c97df44	4178	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	4179	} while(0U)
lypinator	0:bb348c97df44	4180	#define __HAL_RCC_USART3_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	4181	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	4182	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
lypinator	0:bb348c97df44	4183	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	4184	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
lypinator	0:bb348c97df44	4185	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	4186	} while(0U)
lypinator	0:bb348c97df44	4187	#define __HAL_RCC_UART4_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	4188	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	4189	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
lypinator	0:bb348c97df44	4190	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	4191	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
lypinator	0:bb348c97df44	4192	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	4193	} while(0U)
lypinator	0:bb348c97df44	4194	#define __HAL_RCC_UART5_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	4195	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	4196	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
lypinator	0:bb348c97df44	4197	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	4198	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
lypinator	0:bb348c97df44	4199	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	4200	} while(0U)
lypinator	0:bb348c97df44	4201	#define __HAL_RCC_FMPI2C1_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	4202	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	4203	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
lypinator	0:bb348c97df44	4204	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	4205	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
lypinator	0:bb348c97df44	4206	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	4207	} while(0U)
lypinator	0:bb348c97df44	4208	#define __HAL_RCC_CAN1_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	4209	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	4210	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
lypinator	0:bb348c97df44	4211	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	4212	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
lypinator	0:bb348c97df44	4213	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	4214	} while(0U)
lypinator	0:bb348c97df44	4215	#define __HAL_RCC_CAN2_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	4216	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	4217	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
lypinator	0:bb348c97df44	4218	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	4219	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
lypinator	0:bb348c97df44	4220	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	4221	} while(0U)
lypinator	0:bb348c97df44	4222	#define __HAL_RCC_CEC_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	4223	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	4224	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
lypinator	0:bb348c97df44	4225	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	4226	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
lypinator	0:bb348c97df44	4227	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	4228	} while(0U)
lypinator	0:bb348c97df44	4229	#define __HAL_RCC_DAC_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	4230	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	4231	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
lypinator	0:bb348c97df44	4232	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	4233	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
lypinator	0:bb348c97df44	4234	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	4235	} while(0U)
lypinator	0:bb348c97df44	4236	#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	4237	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	4238	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
lypinator	0:bb348c97df44	4239	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	4240	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
lypinator	0:bb348c97df44	4241	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	4242	} while(0U)
lypinator	0:bb348c97df44	4243	#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	4244	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	4245	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
lypinator	0:bb348c97df44	4246	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	4247	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
lypinator	0:bb348c97df44	4248	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	4249	} while(0U)
lypinator	0:bb348c97df44	4250	#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	4251	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	4252	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
lypinator	0:bb348c97df44	4253	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	4254	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
lypinator	0:bb348c97df44	4255	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	4256	} while(0U)
lypinator	0:bb348c97df44	4257	#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	4258	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	4259	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
lypinator	0:bb348c97df44	4260	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	4261	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
lypinator	0:bb348c97df44	4262	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	4263	} while(0U)
lypinator	0:bb348c97df44	4264	#define __HAL_RCC_I2C3_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	4265	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	4266	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
lypinator	0:bb348c97df44	4267	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	4268	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
lypinator	0:bb348c97df44	4269	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	4270	} while(0U)
lypinator	0:bb348c97df44	4271	#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
lypinator	0:bb348c97df44	4272	#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
lypinator	0:bb348c97df44	4273	#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
lypinator	0:bb348c97df44	4274	#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
lypinator	0:bb348c97df44	4275	#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
lypinator	0:bb348c97df44	4276	#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
lypinator	0:bb348c97df44	4277	#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
lypinator	0:bb348c97df44	4278	#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
lypinator	0:bb348c97df44	4279	#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
lypinator	0:bb348c97df44	4280	#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
lypinator	0:bb348c97df44	4281	#define __HAL_RCC_SPDIFRX_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPDIFRXEN))
lypinator	0:bb348c97df44	4282	#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
lypinator	0:bb348c97df44	4283	#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
lypinator	0:bb348c97df44	4284	#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
lypinator	0:bb348c97df44	4285	#define __HAL_RCC_FMPI2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_FMPI2C1EN))
lypinator	0:bb348c97df44	4286	#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
lypinator	0:bb348c97df44	4287	#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
lypinator	0:bb348c97df44	4288	#define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
lypinator	0:bb348c97df44	4289	#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
lypinator	0:bb348c97df44	4290	/**
lypinator	0:bb348c97df44	4291	* @}
lypinator	0:bb348c97df44	4292	*/
lypinator	0:bb348c97df44	4293
lypinator	0:bb348c97df44	4294	/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
lypinator	0:bb348c97df44	4295	* @brief Get the enable or disable status of the APB1 peripheral clock.
lypinator	0:bb348c97df44	4296	* @note After reset, the peripheral clock (used for registers read/write access)
lypinator	0:bb348c97df44	4297	* is disabled and the application software has to enable this clock before
lypinator	0:bb348c97df44	4298	* using it.
lypinator	0:bb348c97df44	4299	* @{
lypinator	0:bb348c97df44	4300	*/
lypinator	0:bb348c97df44	4301	#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
lypinator	0:bb348c97df44	4302	#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
lypinator	0:bb348c97df44	4303	#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
lypinator	0:bb348c97df44	4304	#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
lypinator	0:bb348c97df44	4305	#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
lypinator	0:bb348c97df44	4306	#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
lypinator	0:bb348c97df44	4307	#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
lypinator	0:bb348c97df44	4308	#define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
lypinator	0:bb348c97df44	4309	#define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
lypinator	0:bb348c97df44	4310	#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
lypinator	0:bb348c97df44	4311	#define __HAL_RCC_SPDIFRX_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) != RESET)
lypinator	0:bb348c97df44	4312	#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
lypinator	0:bb348c97df44	4313	#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
lypinator	0:bb348c97df44	4314	#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
lypinator	0:bb348c97df44	4315	#define __HAL_RCC_FMPI2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) != RESET)
lypinator	0:bb348c97df44	4316	#define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET)
lypinator	0:bb348c97df44	4317	#define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)
lypinator	0:bb348c97df44	4318	#define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET)
lypinator	0:bb348c97df44	4319	#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
lypinator	0:bb348c97df44	4320
lypinator	0:bb348c97df44	4321	#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
lypinator	0:bb348c97df44	4322	#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
lypinator	0:bb348c97df44	4323	#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
lypinator	0:bb348c97df44	4324	#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
lypinator	0:bb348c97df44	4325	#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
lypinator	0:bb348c97df44	4326	#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
lypinator	0:bb348c97df44	4327	#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
lypinator	0:bb348c97df44	4328	#define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
lypinator	0:bb348c97df44	4329	#define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
lypinator	0:bb348c97df44	4330	#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
lypinator	0:bb348c97df44	4331	#define __HAL_RCC_SPDIFRX_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) == RESET)
lypinator	0:bb348c97df44	4332	#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
lypinator	0:bb348c97df44	4333	#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
lypinator	0:bb348c97df44	4334	#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
lypinator	0:bb348c97df44	4335	#define __HAL_RCC_FMPI2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) == RESET)
lypinator	0:bb348c97df44	4336	#define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
lypinator	0:bb348c97df44	4337	#define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)
lypinator	0:bb348c97df44	4338	#define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET)
lypinator	0:bb348c97df44	4339	#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
lypinator	0:bb348c97df44	4340	/**
lypinator	0:bb348c97df44	4341	* @}
lypinator	0:bb348c97df44	4342	*/
lypinator	0:bb348c97df44	4343
lypinator	0:bb348c97df44	4344	/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
lypinator	0:bb348c97df44	4345	* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
lypinator	0:bb348c97df44	4346	* @note After reset, the peripheral clock (used for registers read/write access)
lypinator	0:bb348c97df44	4347	* is disabled and the application software has to enable this clock before
lypinator	0:bb348c97df44	4348	* using it.
lypinator	0:bb348c97df44	4349	* @{
lypinator	0:bb348c97df44	4350	*/
lypinator	0:bb348c97df44	4351	#define __HAL_RCC_TIM8_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	4352	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	4353	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
lypinator	0:bb348c97df44	4354	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	4355	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
lypinator	0:bb348c97df44	4356	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	4357	} while(0U)
lypinator	0:bb348c97df44	4358	#define __HAL_RCC_ADC2_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	4359	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	4360	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
lypinator	0:bb348c97df44	4361	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	4362	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
lypinator	0:bb348c97df44	4363	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	4364	} while(0U)
lypinator	0:bb348c97df44	4365	#define __HAL_RCC_ADC3_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	4366	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	4367	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
lypinator	0:bb348c97df44	4368	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	4369	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
lypinator	0:bb348c97df44	4370	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	4371	} while(0U)
lypinator	0:bb348c97df44	4372	#define __HAL_RCC_SAI1_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	4373	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	4374	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
lypinator	0:bb348c97df44	4375	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	4376	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
lypinator	0:bb348c97df44	4377	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	4378	} while(0U)
lypinator	0:bb348c97df44	4379	#define __HAL_RCC_SAI2_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	4380	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	4381	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
lypinator	0:bb348c97df44	4382	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	4383	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
lypinator	0:bb348c97df44	4384	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	4385	} while(0U)
lypinator	0:bb348c97df44	4386	#define __HAL_RCC_SDIO_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	4387	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	4388	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
lypinator	0:bb348c97df44	4389	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	4390	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
lypinator	0:bb348c97df44	4391	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	4392	} while(0U)
lypinator	0:bb348c97df44	4393	#define __HAL_RCC_SPI4_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	4394	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	4395	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
lypinator	0:bb348c97df44	4396	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	4397	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
lypinator	0:bb348c97df44	4398	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	4399	} while(0U)
lypinator	0:bb348c97df44	4400	#define __HAL_RCC_TIM10_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	4401	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	4402	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
lypinator	0:bb348c97df44	4403	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	4404	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
lypinator	0:bb348c97df44	4405	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	4406	} while(0U)
lypinator	0:bb348c97df44	4407	#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
lypinator	0:bb348c97df44	4408	#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
lypinator	0:bb348c97df44	4409	#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
lypinator	0:bb348c97df44	4410	#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
lypinator	0:bb348c97df44	4411	#define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
lypinator	0:bb348c97df44	4412	#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
lypinator	0:bb348c97df44	4413	#define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))
lypinator	0:bb348c97df44	4414	#define __HAL_RCC_SAI2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI2EN))
lypinator	0:bb348c97df44	4415	/**
lypinator	0:bb348c97df44	4416	* @}
lypinator	0:bb348c97df44	4417	*/
lypinator	0:bb348c97df44	4418
lypinator	0:bb348c97df44	4419	/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
lypinator	0:bb348c97df44	4420	* @brief Get the enable or disable status of the APB2 peripheral clock.
lypinator	0:bb348c97df44	4421	* @note After reset, the peripheral clock (used for registers read/write access)
lypinator	0:bb348c97df44	4422	* is disabled and the application software has to enable this clock before
lypinator	0:bb348c97df44	4423	* using it.
lypinator	0:bb348c97df44	4424	* @{
lypinator	0:bb348c97df44	4425	*/
lypinator	0:bb348c97df44	4426	#define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET)
lypinator	0:bb348c97df44	4427	#define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)
lypinator	0:bb348c97df44	4428	#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)
lypinator	0:bb348c97df44	4429	#define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)
lypinator	0:bb348c97df44	4430	#define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET)
lypinator	0:bb348c97df44	4431	#define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET)
lypinator	0:bb348c97df44	4432	#define __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET)
lypinator	0:bb348c97df44	4433	#define __HAL_RCC_SAI2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) != RESET)
lypinator	0:bb348c97df44	4434
lypinator	0:bb348c97df44	4435	#define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET)
lypinator	0:bb348c97df44	4436	#define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
lypinator	0:bb348c97df44	4437	#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)
lypinator	0:bb348c97df44	4438	#define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)
lypinator	0:bb348c97df44	4439	#define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET)
lypinator	0:bb348c97df44	4440	#define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET)
lypinator	0:bb348c97df44	4441	#define __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET)
lypinator	0:bb348c97df44	4442	#define __HAL_RCC_SAI2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) == RESET)
lypinator	0:bb348c97df44	4443	/**
lypinator	0:bb348c97df44	4444	* @}
lypinator	0:bb348c97df44	4445	*/
lypinator	0:bb348c97df44	4446
lypinator	0:bb348c97df44	4447	/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset
lypinator	0:bb348c97df44	4448	* @brief Force or release AHB1 peripheral reset.
lypinator	0:bb348c97df44	4449	* @{
lypinator	0:bb348c97df44	4450	*/
lypinator	0:bb348c97df44	4451	#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIODRST))
lypinator	0:bb348c97df44	4452	#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOERST))
lypinator	0:bb348c97df44	4453	#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOFRST))
lypinator	0:bb348c97df44	4454	#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOGRST))
lypinator	0:bb348c97df44	4455	#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_OTGHRST))
lypinator	0:bb348c97df44	4456	#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_CRCRST))
lypinator	0:bb348c97df44	4457
lypinator	0:bb348c97df44	4458	#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
lypinator	0:bb348c97df44	4459	#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
lypinator	0:bb348c97df44	4460	#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
lypinator	0:bb348c97df44	4461	#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
lypinator	0:bb348c97df44	4462	#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
lypinator	0:bb348c97df44	4463	#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
lypinator	0:bb348c97df44	4464	/**
lypinator	0:bb348c97df44	4465	* @}
lypinator	0:bb348c97df44	4466	*/
lypinator	0:bb348c97df44	4467
lypinator	0:bb348c97df44	4468	/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset
lypinator	0:bb348c97df44	4469	* @brief Force or release AHB2 peripheral reset.
lypinator	0:bb348c97df44	4470	* @{
lypinator	0:bb348c97df44	4471	*/
lypinator	0:bb348c97df44	4472	#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU)
lypinator	0:bb348c97df44	4473	#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_OTGFSRST))
lypinator	0:bb348c97df44	4474	#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_RNGRST))
lypinator	0:bb348c97df44	4475	#define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_DCMIRST))
lypinator	0:bb348c97df44	4476
lypinator	0:bb348c97df44	4477	#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U)
lypinator	0:bb348c97df44	4478	#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
lypinator	0:bb348c97df44	4479	#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
lypinator	0:bb348c97df44	4480	#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
lypinator	0:bb348c97df44	4481	/**
lypinator	0:bb348c97df44	4482	* @}
lypinator	0:bb348c97df44	4483	*/
lypinator	0:bb348c97df44	4484
lypinator	0:bb348c97df44	4485	/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset
lypinator	0:bb348c97df44	4486	* @brief Force or release AHB3 peripheral reset.
lypinator	0:bb348c97df44	4487	* @{
lypinator	0:bb348c97df44	4488	*/
lypinator	0:bb348c97df44	4489	#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
lypinator	0:bb348c97df44	4490	#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U)
lypinator	0:bb348c97df44	4491
lypinator	0:bb348c97df44	4492	#define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR \|= (RCC_AHB3RSTR_FMCRST))
lypinator	0:bb348c97df44	4493	#define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR \|= (RCC_AHB3RSTR_QSPIRST))
lypinator	0:bb348c97df44	4494
lypinator	0:bb348c97df44	4495	#define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST))
lypinator	0:bb348c97df44	4496	#define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST))
lypinator	0:bb348c97df44	4497	/**
lypinator	0:bb348c97df44	4498	* @}
lypinator	0:bb348c97df44	4499	*/
lypinator	0:bb348c97df44	4500
lypinator	0:bb348c97df44	4501	/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset
lypinator	0:bb348c97df44	4502	* @brief Force or release APB1 peripheral reset.
lypinator	0:bb348c97df44	4503	* @{
lypinator	0:bb348c97df44	4504	*/
lypinator	0:bb348c97df44	4505	#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM6RST))
lypinator	0:bb348c97df44	4506	#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM7RST))
lypinator	0:bb348c97df44	4507	#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM12RST))
lypinator	0:bb348c97df44	4508	#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM13RST))
lypinator	0:bb348c97df44	4509	#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM14RST))
lypinator	0:bb348c97df44	4510	#define __HAL_RCC_SPDIFRX_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPDIFRXRST))
lypinator	0:bb348c97df44	4511	#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART3RST))
lypinator	0:bb348c97df44	4512	#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART4RST))
lypinator	0:bb348c97df44	4513	#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART5RST))
lypinator	0:bb348c97df44	4514	#define __HAL_RCC_FMPI2C1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_FMPI2C1RST))
lypinator	0:bb348c97df44	4515	#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN1RST))
lypinator	0:bb348c97df44	4516	#define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN2RST))
lypinator	0:bb348c97df44	4517	#define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CECRST))
lypinator	0:bb348c97df44	4518	#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DACRST))
lypinator	0:bb348c97df44	4519	#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM2RST))
lypinator	0:bb348c97df44	4520	#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM3RST))
lypinator	0:bb348c97df44	4521	#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM4RST))
lypinator	0:bb348c97df44	4522	#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI3RST))
lypinator	0:bb348c97df44	4523	#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C3RST))
lypinator	0:bb348c97df44	4524
lypinator	0:bb348c97df44	4525	#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
lypinator	0:bb348c97df44	4526	#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
lypinator	0:bb348c97df44	4527	#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
lypinator	0:bb348c97df44	4528	#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
lypinator	0:bb348c97df44	4529	#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
lypinator	0:bb348c97df44	4530	#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
lypinator	0:bb348c97df44	4531	#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
lypinator	0:bb348c97df44	4532	#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
lypinator	0:bb348c97df44	4533	#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
lypinator	0:bb348c97df44	4534	#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
lypinator	0:bb348c97df44	4535	#define __HAL_RCC_SPDIFRX_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPDIFRXRST))
lypinator	0:bb348c97df44	4536	#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
lypinator	0:bb348c97df44	4537	#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
lypinator	0:bb348c97df44	4538	#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
lypinator	0:bb348c97df44	4539	#define __HAL_RCC_FMPI2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_FMPI2C1RST))
lypinator	0:bb348c97df44	4540	#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
lypinator	0:bb348c97df44	4541	#define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
lypinator	0:bb348c97df44	4542	#define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))
lypinator	0:bb348c97df44	4543	#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
lypinator	0:bb348c97df44	4544	/**
lypinator	0:bb348c97df44	4545	* @}
lypinator	0:bb348c97df44	4546	*/
lypinator	0:bb348c97df44	4547
lypinator	0:bb348c97df44	4548	/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
lypinator	0:bb348c97df44	4549	* @brief Force or release APB2 peripheral reset.
lypinator	0:bb348c97df44	4550	* @{
lypinator	0:bb348c97df44	4551	*/
lypinator	0:bb348c97df44	4552	#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM8RST))
lypinator	0:bb348c97df44	4553	#define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SAI1RST))
lypinator	0:bb348c97df44	4554	#define __HAL_RCC_SAI2_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SAI2RST))
lypinator	0:bb348c97df44	4555	#define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SDIORST))
lypinator	0:bb348c97df44	4556	#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI4RST))
lypinator	0:bb348c97df44	4557	#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM10RST))
lypinator	0:bb348c97df44	4558
lypinator	0:bb348c97df44	4559	#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
lypinator	0:bb348c97df44	4560	#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
lypinator	0:bb348c97df44	4561	#define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
lypinator	0:bb348c97df44	4562	#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
lypinator	0:bb348c97df44	4563	#define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))
lypinator	0:bb348c97df44	4564	#define __HAL_RCC_SAI2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI2RST))
lypinator	0:bb348c97df44	4565	/**
lypinator	0:bb348c97df44	4566	* @}
lypinator	0:bb348c97df44	4567	*/
lypinator	0:bb348c97df44	4568
lypinator	0:bb348c97df44	4569	/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
lypinator	0:bb348c97df44	4570	* @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
lypinator	0:bb348c97df44	4571	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
lypinator	0:bb348c97df44	4572	* power consumption.
lypinator	0:bb348c97df44	4573	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
lypinator	0:bb348c97df44	4574	* @note By default, all peripheral clocks are enabled during SLEEP mode.
lypinator	0:bb348c97df44	4575	* @{
lypinator	0:bb348c97df44	4576	*/
lypinator	0:bb348c97df44	4577	#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIODLPEN))
lypinator	0:bb348c97df44	4578	#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOELPEN))
lypinator	0:bb348c97df44	4579	#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOFLPEN))
lypinator	0:bb348c97df44	4580	#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOGLPEN))
lypinator	0:bb348c97df44	4581	#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM2LPEN))
lypinator	0:bb348c97df44	4582	#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_OTGHSLPEN))
lypinator	0:bb348c97df44	4583	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_OTGHSULPILPEN))
lypinator	0:bb348c97df44	4584	#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_CRCLPEN))
lypinator	0:bb348c97df44	4585	#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_FLITFLPEN))
lypinator	0:bb348c97df44	4586	#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM1LPEN))
lypinator	0:bb348c97df44	4587	#define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_BKPSRAMLPEN))
lypinator	0:bb348c97df44	4588
lypinator	0:bb348c97df44	4589	#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
lypinator	0:bb348c97df44	4590	#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
lypinator	0:bb348c97df44	4591	#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
lypinator	0:bb348c97df44	4592	#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
lypinator	0:bb348c97df44	4593	#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
lypinator	0:bb348c97df44	4594	#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
lypinator	0:bb348c97df44	4595	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
lypinator	0:bb348c97df44	4596	#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
lypinator	0:bb348c97df44	4597	#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
lypinator	0:bb348c97df44	4598	#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
lypinator	0:bb348c97df44	4599	#define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))
lypinator	0:bb348c97df44	4600	/**
lypinator	0:bb348c97df44	4601	* @}
lypinator	0:bb348c97df44	4602	*/
lypinator	0:bb348c97df44	4603
lypinator	0:bb348c97df44	4604	/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
lypinator	0:bb348c97df44	4605	* @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
lypinator	0:bb348c97df44	4606	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
lypinator	0:bb348c97df44	4607	* power consumption.
lypinator	0:bb348c97df44	4608	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
lypinator	0:bb348c97df44	4609	* @note By default, all peripheral clocks are enabled during SLEEP mode.
lypinator	0:bb348c97df44	4610	* @{
lypinator	0:bb348c97df44	4611	*/
lypinator	0:bb348c97df44	4612	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_OTGFSLPEN))
lypinator	0:bb348c97df44	4613	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
lypinator	0:bb348c97df44	4614
lypinator	0:bb348c97df44	4615	#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_RNGLPEN))
lypinator	0:bb348c97df44	4616	#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
lypinator	0:bb348c97df44	4617
lypinator	0:bb348c97df44	4618	#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_DCMILPEN))
lypinator	0:bb348c97df44	4619	#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
lypinator	0:bb348c97df44	4620	/**
lypinator	0:bb348c97df44	4621	* @}
lypinator	0:bb348c97df44	4622	*/
lypinator	0:bb348c97df44	4623
lypinator	0:bb348c97df44	4624	/** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable
lypinator	0:bb348c97df44	4625	* @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
lypinator	0:bb348c97df44	4626	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
lypinator	0:bb348c97df44	4627	* power consumption.
lypinator	0:bb348c97df44	4628	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
lypinator	0:bb348c97df44	4629	* @note By default, all peripheral clocks are enabled during SLEEP mode.
lypinator	0:bb348c97df44	4630	* @{
lypinator	0:bb348c97df44	4631	*/
lypinator	0:bb348c97df44	4632	#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_FMCLPEN))
lypinator	0:bb348c97df44	4633	#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_QSPILPEN))
lypinator	0:bb348c97df44	4634
lypinator	0:bb348c97df44	4635	#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN))
lypinator	0:bb348c97df44	4636	#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN))
lypinator	0:bb348c97df44	4637	/**
lypinator	0:bb348c97df44	4638	* @}
lypinator	0:bb348c97df44	4639	*/
lypinator	0:bb348c97df44	4640
lypinator	0:bb348c97df44	4641	/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
lypinator	0:bb348c97df44	4642	* @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
lypinator	0:bb348c97df44	4643	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
lypinator	0:bb348c97df44	4644	* power consumption.
lypinator	0:bb348c97df44	4645	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
lypinator	0:bb348c97df44	4646	* @note By default, all peripheral clocks are enabled during SLEEP mode.
lypinator	0:bb348c97df44	4647	* @{
lypinator	0:bb348c97df44	4648	*/
lypinator	0:bb348c97df44	4649	#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM6LPEN))
lypinator	0:bb348c97df44	4650	#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM7LPEN))
lypinator	0:bb348c97df44	4651	#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM12LPEN))
lypinator	0:bb348c97df44	4652	#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM13LPEN))
lypinator	0:bb348c97df44	4653	#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM14LPEN))
lypinator	0:bb348c97df44	4654	#define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_SPDIFRXLPEN))
lypinator	0:bb348c97df44	4655	#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_USART3LPEN))
lypinator	0:bb348c97df44	4656	#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART4LPEN))
lypinator	0:bb348c97df44	4657	#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART5LPEN))
lypinator	0:bb348c97df44	4658	#define __HAL_RCC_FMPI2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_FMPI2C1LPEN))
lypinator	0:bb348c97df44	4659	#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN1LPEN))
lypinator	0:bb348c97df44	4660	#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN2LPEN))
lypinator	0:bb348c97df44	4661	#define __HAL_RCC_CEC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CECLPEN))
lypinator	0:bb348c97df44	4662	#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_DACLPEN))
lypinator	0:bb348c97df44	4663	#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM2LPEN))
lypinator	0:bb348c97df44	4664	#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM3LPEN))
lypinator	0:bb348c97df44	4665	#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM4LPEN))
lypinator	0:bb348c97df44	4666	#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_SPI3LPEN))
lypinator	0:bb348c97df44	4667	#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C3LPEN))
lypinator	0:bb348c97df44	4668
lypinator	0:bb348c97df44	4669	#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
lypinator	0:bb348c97df44	4670	#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
lypinator	0:bb348c97df44	4671	#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
lypinator	0:bb348c97df44	4672	#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
lypinator	0:bb348c97df44	4673	#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
lypinator	0:bb348c97df44	4674	#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
lypinator	0:bb348c97df44	4675	#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
lypinator	0:bb348c97df44	4676	#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
lypinator	0:bb348c97df44	4677	#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
lypinator	0:bb348c97df44	4678	#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
lypinator	0:bb348c97df44	4679	#define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPDIFRXLPEN))
lypinator	0:bb348c97df44	4680	#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
lypinator	0:bb348c97df44	4681	#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
lypinator	0:bb348c97df44	4682	#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
lypinator	0:bb348c97df44	4683	#define __HAL_RCC_FMPI2C1_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_FMPI2C1LPEN))
lypinator	0:bb348c97df44	4684	#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
lypinator	0:bb348c97df44	4685	#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
lypinator	0:bb348c97df44	4686	#define __HAL_RCC_CEC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CECLPEN))
lypinator	0:bb348c97df44	4687	#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
lypinator	0:bb348c97df44	4688	/**
lypinator	0:bb348c97df44	4689	* @}
lypinator	0:bb348c97df44	4690	*/
lypinator	0:bb348c97df44	4691
lypinator	0:bb348c97df44	4692	/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
lypinator	0:bb348c97df44	4693	* @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
lypinator	0:bb348c97df44	4694	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
lypinator	0:bb348c97df44	4695	* power consumption.
lypinator	0:bb348c97df44	4696	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
lypinator	0:bb348c97df44	4697	* @note By default, all peripheral clocks are enabled during SLEEP mode.
lypinator	0:bb348c97df44	4698	* @{
lypinator	0:bb348c97df44	4699	*/
lypinator	0:bb348c97df44	4700	#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM8LPEN))
lypinator	0:bb348c97df44	4701	#define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC2LPEN))
lypinator	0:bb348c97df44	4702	#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC3LPEN))
lypinator	0:bb348c97df44	4703	#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SAI1LPEN))
lypinator	0:bb348c97df44	4704	#define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SAI2LPEN))
lypinator	0:bb348c97df44	4705	#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SDIOLPEN))
lypinator	0:bb348c97df44	4706	#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI4LPEN))
lypinator	0:bb348c97df44	4707	#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()(RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM10LPEN))
lypinator	0:bb348c97df44	4708
lypinator	0:bb348c97df44	4709	#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
lypinator	0:bb348c97df44	4710	#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
lypinator	0:bb348c97df44	4711	#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()(RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
lypinator	0:bb348c97df44	4712	#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
lypinator	0:bb348c97df44	4713	#define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
lypinator	0:bb348c97df44	4714	#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
lypinator	0:bb348c97df44	4715	#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN))
lypinator	0:bb348c97df44	4716	#define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI2LPEN))
lypinator	0:bb348c97df44	4717	/**
lypinator	0:bb348c97df44	4718	* @}
lypinator	0:bb348c97df44	4719	*/
lypinator	0:bb348c97df44	4720
lypinator	0:bb348c97df44	4721	#endif /* STM32F446xx */
lypinator	0:bb348c97df44	4722	/----------------------------------------------------------------------------/
lypinator	0:bb348c97df44	4723
lypinator	0:bb348c97df44	4724	/-------STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx \|\| STM32F413xx \|\| STM32F423xx-------/
lypinator	0:bb348c97df44	4725	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
lypinator	0:bb348c97df44	4726	/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
lypinator	0:bb348c97df44	4727	* @brief Enables or disables the AHB1 peripheral clock.
lypinator	0:bb348c97df44	4728	* @note After reset, the peripheral clock (used for registers read/write access)
lypinator	0:bb348c97df44	4729	* is disabled and the application software has to enable this clock before
lypinator	0:bb348c97df44	4730	* using it.
lypinator	0:bb348c97df44	4731	* @{
lypinator	0:bb348c97df44	4732	*/
lypinator	0:bb348c97df44	4733	#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	4734	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	4735	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
lypinator	0:bb348c97df44	4736	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	4737	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
lypinator	0:bb348c97df44	4738	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	4739	} while(0U)
lypinator	0:bb348c97df44	4740	#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	4741	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	4742	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
lypinator	0:bb348c97df44	4743	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	4744	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
lypinator	0:bb348c97df44	4745	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	4746	} while(0U)
lypinator	0:bb348c97df44	4747	#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	4748	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	4749	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
lypinator	0:bb348c97df44	4750	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	4751	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
lypinator	0:bb348c97df44	4752	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	4753	} while(0U)
lypinator	0:bb348c97df44	4754	#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	4755	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	4756	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
lypinator	0:bb348c97df44	4757	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	4758	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
lypinator	0:bb348c97df44	4759	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	4760	} while(0U)
lypinator	0:bb348c97df44	4761	#define __HAL_RCC_CRC_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	4762	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	4763	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
lypinator	0:bb348c97df44	4764	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	4765	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
lypinator	0:bb348c97df44	4766	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	4767	} while(0U)
lypinator	0:bb348c97df44	4768
lypinator	0:bb348c97df44	4769	#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
lypinator	0:bb348c97df44	4770	#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
lypinator	0:bb348c97df44	4771	#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
lypinator	0:bb348c97df44	4772	#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
lypinator	0:bb348c97df44	4773	#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
lypinator	0:bb348c97df44	4774	/**
lypinator	0:bb348c97df44	4775	* @}
lypinator	0:bb348c97df44	4776	*/
lypinator	0:bb348c97df44	4777
lypinator	0:bb348c97df44	4778	/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
lypinator	0:bb348c97df44	4779	* @brief Get the enable or disable status of the AHB1 peripheral clock.
lypinator	0:bb348c97df44	4780	* @note After reset, the peripheral clock (used for registers read/write access)
lypinator	0:bb348c97df44	4781	* is disabled and the application software has to enable this clock before
lypinator	0:bb348c97df44	4782	* using it.
lypinator	0:bb348c97df44	4783	* @{
lypinator	0:bb348c97df44	4784	*/
lypinator	0:bb348c97df44	4785	#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)
lypinator	0:bb348c97df44	4786	#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)
lypinator	0:bb348c97df44	4787	#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET)
lypinator	0:bb348c97df44	4788	#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET)
lypinator	0:bb348c97df44	4789	#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
lypinator	0:bb348c97df44	4790
lypinator	0:bb348c97df44	4791	#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)
lypinator	0:bb348c97df44	4792	#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)
lypinator	0:bb348c97df44	4793	#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET)
lypinator	0:bb348c97df44	4794	#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET)
lypinator	0:bb348c97df44	4795	#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
lypinator	0:bb348c97df44	4796	/**
lypinator	0:bb348c97df44	4797	* @}
lypinator	0:bb348c97df44	4798	*/
lypinator	0:bb348c97df44	4799
lypinator	0:bb348c97df44	4800	/** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
lypinator	0:bb348c97df44	4801	* @brief Enable or disable the AHB2 peripheral clock.
lypinator	0:bb348c97df44	4802	* @note After reset, the peripheral clock (used for registers read/write access)
lypinator	0:bb348c97df44	4803	* is disabled and the application software has to enable this clock before
lypinator	0:bb348c97df44	4804	* using it.
lypinator	0:bb348c97df44	4805	* @{
lypinator	0:bb348c97df44	4806	*/
lypinator	0:bb348c97df44	4807	#if defined(STM32F423xx)
lypinator	0:bb348c97df44	4808	#define __HAL_RCC_AES_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	4809	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	4810	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);\
lypinator	0:bb348c97df44	4811	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	4812	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);\
lypinator	0:bb348c97df44	4813	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	4814	} while(0U)
lypinator	0:bb348c97df44	4815
lypinator	0:bb348c97df44	4816	#define __HAL_RCC_AES_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_AESEN))
lypinator	0:bb348c97df44	4817	#endif /* STM32F423xx */
lypinator	0:bb348c97df44	4818
lypinator	0:bb348c97df44	4819	#define __HAL_RCC_RNG_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	4820	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	4821	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
lypinator	0:bb348c97df44	4822	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	4823	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
lypinator	0:bb348c97df44	4824	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	4825	} while(0U)
lypinator	0:bb348c97df44	4826	#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
lypinator	0:bb348c97df44	4827
lypinator	0:bb348c97df44	4828	#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR \|= (RCC_AHB2ENR_OTGFSEN));\
lypinator	0:bb348c97df44	4829	__HAL_RCC_SYSCFG_CLK_ENABLE();\
lypinator	0:bb348c97df44	4830	}while(0U)
lypinator	0:bb348c97df44	4831
lypinator	0:bb348c97df44	4832	#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
lypinator	0:bb348c97df44	4833	/**
lypinator	0:bb348c97df44	4834	* @}
lypinator	0:bb348c97df44	4835	*/
lypinator	0:bb348c97df44	4836
lypinator	0:bb348c97df44	4837	/** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status
lypinator	0:bb348c97df44	4838	* @brief Get the enable or disable status of the AHB2 peripheral clock.
lypinator	0:bb348c97df44	4839	* @note After reset, the peripheral clock (used for registers read/write access)
lypinator	0:bb348c97df44	4840	* is disabled and the application software has to enable this clock before
lypinator	0:bb348c97df44	4841	* using it.
lypinator	0:bb348c97df44	4842	* @{
lypinator	0:bb348c97df44	4843	*/
lypinator	0:bb348c97df44	4844	#if defined(STM32F423xx)
lypinator	0:bb348c97df44	4845	#define __HAL_RCC_AES_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_AESEN)) != RESET)
lypinator	0:bb348c97df44	4846	#define __HAL_RCC_AES_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_AESEN)) == RESET)
lypinator	0:bb348c97df44	4847	#endif /* STM32F423xx */
lypinator	0:bb348c97df44	4848
lypinator	0:bb348c97df44	4849	#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
lypinator	0:bb348c97df44	4850	#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
lypinator	0:bb348c97df44	4851
lypinator	0:bb348c97df44	4852	#define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET)
lypinator	0:bb348c97df44	4853	#define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET)
lypinator	0:bb348c97df44	4854	/**
lypinator	0:bb348c97df44	4855	* @}
lypinator	0:bb348c97df44	4856	*/
lypinator	0:bb348c97df44	4857
lypinator	0:bb348c97df44	4858	/** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable
lypinator	0:bb348c97df44	4859	* @brief Enables or disables the AHB3 peripheral clock.
lypinator	0:bb348c97df44	4860	* @note After reset, the peripheral clock (used for registers read/write access)
lypinator	0:bb348c97df44	4861	* is disabled and the application software has to enable this clock before
lypinator	0:bb348c97df44	4862	* using it.
lypinator	0:bb348c97df44	4863	* @{
lypinator	0:bb348c97df44	4864	*/
lypinator	0:bb348c97df44	4865	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
lypinator	0:bb348c97df44	4866	#define __HAL_RCC_FSMC_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	4867	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	4868	SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\
lypinator	0:bb348c97df44	4869	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	4870	tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\
lypinator	0:bb348c97df44	4871	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	4872	} while(0U)
lypinator	0:bb348c97df44	4873	#define __HAL_RCC_QSPI_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	4874	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	4875	SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
lypinator	0:bb348c97df44	4876	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	4877	tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
lypinator	0:bb348c97df44	4878	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	4879	} while(0U)
lypinator	0:bb348c97df44	4880
lypinator	0:bb348c97df44	4881	#define __HAL_RCC_FSMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FSMCEN))
lypinator	0:bb348c97df44	4882	#define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN))
lypinator	0:bb348c97df44	4883	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F413xx \|\| STM32F423xx */
lypinator	0:bb348c97df44	4884	/**
lypinator	0:bb348c97df44	4885	* @}
lypinator	0:bb348c97df44	4886	*/
lypinator	0:bb348c97df44	4887
lypinator	0:bb348c97df44	4888	/** @defgroup RCCEx_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enable Disable Status
lypinator	0:bb348c97df44	4889	* @brief Get the enable or disable status of the AHB3 peripheral clock.
lypinator	0:bb348c97df44	4890	* @note After reset, the peripheral clock (used for registers read/write access)
lypinator	0:bb348c97df44	4891	* is disabled and the application software has to enable this clock before
lypinator	0:bb348c97df44	4892	* using it.
lypinator	0:bb348c97df44	4893	* @{
lypinator	0:bb348c97df44	4894	*/
lypinator	0:bb348c97df44	4895	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
lypinator	0:bb348c97df44	4896	#define __HAL_RCC_FSMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FSMCEN)) != RESET)
lypinator	0:bb348c97df44	4897	#define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET)
lypinator	0:bb348c97df44	4898
lypinator	0:bb348c97df44	4899	#define __HAL_RCC_FSMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FSMCEN)) == RESET)
lypinator	0:bb348c97df44	4900	#define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET)
lypinator	0:bb348c97df44	4901	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F413xx \|\| STM32F423xx */
lypinator	0:bb348c97df44	4902
lypinator	0:bb348c97df44	4903	/**
lypinator	0:bb348c97df44	4904	* @}
lypinator	0:bb348c97df44	4905	*/
lypinator	0:bb348c97df44	4906
lypinator	0:bb348c97df44	4907	/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
lypinator	0:bb348c97df44	4908	* @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
lypinator	0:bb348c97df44	4909	* @note After reset, the peripheral clock (used for registers read/write access)
lypinator	0:bb348c97df44	4910	* is disabled and the application software has to enable this clock before
lypinator	0:bb348c97df44	4911	* using it.
lypinator	0:bb348c97df44	4912	* @{
lypinator	0:bb348c97df44	4913	*/
lypinator	0:bb348c97df44	4914	#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	4915	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	4916	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
lypinator	0:bb348c97df44	4917	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	4918	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
lypinator	0:bb348c97df44	4919	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	4920	} while(0U)
lypinator	0:bb348c97df44	4921	#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	4922	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	4923	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
lypinator	0:bb348c97df44	4924	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	4925	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
lypinator	0:bb348c97df44	4926	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	4927	} while(0U)
lypinator	0:bb348c97df44	4928	#define __HAL_RCC_TIM12_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	4929	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	4930	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
lypinator	0:bb348c97df44	4931	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	4932	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
lypinator	0:bb348c97df44	4933	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	4934	} while(0U)
lypinator	0:bb348c97df44	4935	#define __HAL_RCC_TIM13_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	4936	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	4937	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
lypinator	0:bb348c97df44	4938	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	4939	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
lypinator	0:bb348c97df44	4940	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	4941	} while(0U)
lypinator	0:bb348c97df44	4942	#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	4943	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	4944	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
lypinator	0:bb348c97df44	4945	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	4946	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
lypinator	0:bb348c97df44	4947	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	4948	} while(0U)
lypinator	0:bb348c97df44	4949	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
lypinator	0:bb348c97df44	4950	#define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	4951	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	4952	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\
lypinator	0:bb348c97df44	4953	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	4954	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\
lypinator	0:bb348c97df44	4955	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	4956	} while(0U)
lypinator	0:bb348c97df44	4957	#endif /* STM32F413xx \|\| STM32F423xx */
lypinator	0:bb348c97df44	4958	#define __HAL_RCC_RTCAPB_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	4959	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	4960	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\
lypinator	0:bb348c97df44	4961	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	4962	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\
lypinator	0:bb348c97df44	4963	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	4964	} while(0U)
lypinator	0:bb348c97df44	4965	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
lypinator	0:bb348c97df44	4966	#define __HAL_RCC_USART3_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	4967	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	4968	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
lypinator	0:bb348c97df44	4969	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	4970	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
lypinator	0:bb348c97df44	4971	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	4972	} while(0U)
lypinator	0:bb348c97df44	4973	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F413xx \|\| STM32F423xx */
lypinator	0:bb348c97df44	4974
lypinator	0:bb348c97df44	4975	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
lypinator	0:bb348c97df44	4976	#define __HAL_RCC_UART4_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	4977	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	4978	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
lypinator	0:bb348c97df44	4979	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	4980	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
lypinator	0:bb348c97df44	4981	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	4982	} while(0U)
lypinator	0:bb348c97df44	4983	#define __HAL_RCC_UART5_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	4984	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	4985	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
lypinator	0:bb348c97df44	4986	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	4987	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
lypinator	0:bb348c97df44	4988	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	4989	} while(0U)
lypinator	0:bb348c97df44	4990	#endif /* STM32F413xx \|\| STM32F423xx */
lypinator	0:bb348c97df44	4991
lypinator	0:bb348c97df44	4992	#define __HAL_RCC_FMPI2C1_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	4993	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	4994	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
lypinator	0:bb348c97df44	4995	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	4996	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
lypinator	0:bb348c97df44	4997	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	4998	} while(0U)
lypinator	0:bb348c97df44	4999	#define __HAL_RCC_CAN1_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	5000	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	5001	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
lypinator	0:bb348c97df44	5002	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	5003	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
lypinator	0:bb348c97df44	5004	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	5005	} while(0U)
lypinator	0:bb348c97df44	5006	#define __HAL_RCC_CAN2_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	5007	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	5008	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
lypinator	0:bb348c97df44	5009	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	5010	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
lypinator	0:bb348c97df44	5011	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	5012	} while(0U)
lypinator	0:bb348c97df44	5013	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
lypinator	0:bb348c97df44	5014	#define __HAL_RCC_CAN3_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	5015	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	5016	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN3EN);\
lypinator	0:bb348c97df44	5017	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	5018	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN3EN);\
lypinator	0:bb348c97df44	5019	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	5020	} while(0U)
lypinator	0:bb348c97df44	5021	#endif /* STM32F413xx \|\| STM32F423xx */
lypinator	0:bb348c97df44	5022	#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	5023	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	5024	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
lypinator	0:bb348c97df44	5025	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	5026	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
lypinator	0:bb348c97df44	5027	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	5028	} while(0U)
lypinator	0:bb348c97df44	5029	#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	5030	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	5031	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
lypinator	0:bb348c97df44	5032	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	5033	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
lypinator	0:bb348c97df44	5034	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	5035	} while(0U)
lypinator	0:bb348c97df44	5036	#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	5037	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	5038	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
lypinator	0:bb348c97df44	5039	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	5040	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
lypinator	0:bb348c97df44	5041	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	5042	} while(0U)
lypinator	0:bb348c97df44	5043	#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	5044	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	5045	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
lypinator	0:bb348c97df44	5046	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	5047	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
lypinator	0:bb348c97df44	5048	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	5049	} while(0U)
lypinator	0:bb348c97df44	5050	#define __HAL_RCC_I2C3_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	5051	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	5052	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
lypinator	0:bb348c97df44	5053	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	5054	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
lypinator	0:bb348c97df44	5055	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	5056	} while(0U)
lypinator	0:bb348c97df44	5057	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
lypinator	0:bb348c97df44	5058	#define __HAL_RCC_DAC_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	5059	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	5060	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
lypinator	0:bb348c97df44	5061	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	5062	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
lypinator	0:bb348c97df44	5063	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	5064	} while(0U)
lypinator	0:bb348c97df44	5065	#define __HAL_RCC_UART7_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	5066	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	5067	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
lypinator	0:bb348c97df44	5068	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	5069	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
lypinator	0:bb348c97df44	5070	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	5071	} while(0U)
lypinator	0:bb348c97df44	5072	#define __HAL_RCC_UART8_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	5073	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	5074	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
lypinator	0:bb348c97df44	5075	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	5076	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
lypinator	0:bb348c97df44	5077	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	5078	} while(0U)
lypinator	0:bb348c97df44	5079	#endif /* STM32F413xx \|\| STM32F423xx */
lypinator	0:bb348c97df44	5080
lypinator	0:bb348c97df44	5081	#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
lypinator	0:bb348c97df44	5082	#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
lypinator	0:bb348c97df44	5083	#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
lypinator	0:bb348c97df44	5084	#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
lypinator	0:bb348c97df44	5085	#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
lypinator	0:bb348c97df44	5086	#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
lypinator	0:bb348c97df44	5087	#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
lypinator	0:bb348c97df44	5088	#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
lypinator	0:bb348c97df44	5089	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
lypinator	0:bb348c97df44	5090	#define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_LPTIM1EN))
lypinator	0:bb348c97df44	5091	#endif /* STM32F413xx \|\| STM32F423xx */
lypinator	0:bb348c97df44	5092	#define __HAL_RCC_RTCAPB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_RTCAPBEN))
lypinator	0:bb348c97df44	5093	#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
lypinator	0:bb348c97df44	5094	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
lypinator	0:bb348c97df44	5095	#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
lypinator	0:bb348c97df44	5096	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F413xx \|\| STM32F423xx */
lypinator	0:bb348c97df44	5097	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
lypinator	0:bb348c97df44	5098	#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
lypinator	0:bb348c97df44	5099	#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
lypinator	0:bb348c97df44	5100	#endif /* STM32F413xx \|\| STM32F423xx */
lypinator	0:bb348c97df44	5101	#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
lypinator	0:bb348c97df44	5102	#define __HAL_RCC_FMPI2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_FMPI2C1EN))
lypinator	0:bb348c97df44	5103	#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
lypinator	0:bb348c97df44	5104	#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
lypinator	0:bb348c97df44	5105	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
lypinator	0:bb348c97df44	5106	#define __HAL_RCC_CAN3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN3EN))
lypinator	0:bb348c97df44	5107	#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
lypinator	0:bb348c97df44	5108	#define __HAL_RCC_UART7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN))
lypinator	0:bb348c97df44	5109	#define __HAL_RCC_UART8_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN))
lypinator	0:bb348c97df44	5110	#endif /* STM32F413xx \|\| STM32F423xx */
lypinator	0:bb348c97df44	5111
lypinator	0:bb348c97df44	5112	/**
lypinator	0:bb348c97df44	5113	* @}
lypinator	0:bb348c97df44	5114	*/
lypinator	0:bb348c97df44	5115
lypinator	0:bb348c97df44	5116	/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
lypinator	0:bb348c97df44	5117	* @brief Get the enable or disable status of the APB1 peripheral clock.
lypinator	0:bb348c97df44	5118	* @note After reset, the peripheral clock (used for registers read/write access)
lypinator	0:bb348c97df44	5119	* is disabled and the application software has to enable this clock before
lypinator	0:bb348c97df44	5120	* using it.
lypinator	0:bb348c97df44	5121	* @{
lypinator	0:bb348c97df44	5122	*/
lypinator	0:bb348c97df44	5123	#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
lypinator	0:bb348c97df44	5124	#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
lypinator	0:bb348c97df44	5125	#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
lypinator	0:bb348c97df44	5126	#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
lypinator	0:bb348c97df44	5127	#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
lypinator	0:bb348c97df44	5128	#define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
lypinator	0:bb348c97df44	5129	#define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
lypinator	0:bb348c97df44	5130	#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
lypinator	0:bb348c97df44	5131	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
lypinator	0:bb348c97df44	5132	#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) != RESET)
lypinator	0:bb348c97df44	5133	#endif /* STM32F413xx \|\| STM32F423xx */
lypinator	0:bb348c97df44	5134	#define __HAL_RCC_RTCAPB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) != RESET)
lypinator	0:bb348c97df44	5135	#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
lypinator	0:bb348c97df44	5136	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
lypinator	0:bb348c97df44	5137	#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
lypinator	0:bb348c97df44	5138	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F413xx \| STM32F423xx */
lypinator	0:bb348c97df44	5139	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
lypinator	0:bb348c97df44	5140	#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
lypinator	0:bb348c97df44	5141	#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
lypinator	0:bb348c97df44	5142	#endif /* STM32F413xx \|\| STM32F423xx */
lypinator	0:bb348c97df44	5143	#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
lypinator	0:bb348c97df44	5144	#define __HAL_RCC_FMPI2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) != RESET)
lypinator	0:bb348c97df44	5145	#define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN))!= RESET)
lypinator	0:bb348c97df44	5146	#define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)
lypinator	0:bb348c97df44	5147	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
lypinator	0:bb348c97df44	5148	#define __HAL_RCC_CAN3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN3EN)) != RESET)
lypinator	0:bb348c97df44	5149	#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
lypinator	0:bb348c97df44	5150	#define __HAL_RCC_UART7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) != RESET)
lypinator	0:bb348c97df44	5151	#define __HAL_RCC_UART8_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) != RESET)
lypinator	0:bb348c97df44	5152	#endif /* STM32F413xx \|\| STM32F423xx */
lypinator	0:bb348c97df44	5153
lypinator	0:bb348c97df44	5154	#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
lypinator	0:bb348c97df44	5155	#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
lypinator	0:bb348c97df44	5156	#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
lypinator	0:bb348c97df44	5157	#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
lypinator	0:bb348c97df44	5158	#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
lypinator	0:bb348c97df44	5159	#define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
lypinator	0:bb348c97df44	5160	#define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
lypinator	0:bb348c97df44	5161	#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
lypinator	0:bb348c97df44	5162	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
lypinator	0:bb348c97df44	5163	#define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) == RESET)
lypinator	0:bb348c97df44	5164	#endif /* STM32F413xx \|\| STM32F423xx */
lypinator	0:bb348c97df44	5165	#define __HAL_RCC_RTCAPB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) == RESET)
lypinator	0:bb348c97df44	5166	#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
lypinator	0:bb348c97df44	5167	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
lypinator	0:bb348c97df44	5168	#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
lypinator	0:bb348c97df44	5169	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F413xx \| STM32F423xx */
lypinator	0:bb348c97df44	5170	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
lypinator	0:bb348c97df44	5171	#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
lypinator	0:bb348c97df44	5172	#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
lypinator	0:bb348c97df44	5173	#endif /* STM32F413xx \|\| STM32F423xx */
lypinator	0:bb348c97df44	5174	#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
lypinator	0:bb348c97df44	5175	#define __HAL_RCC_FMPI2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) == RESET)
lypinator	0:bb348c97df44	5176	#define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
lypinator	0:bb348c97df44	5177	#define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)
lypinator	0:bb348c97df44	5178	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
lypinator	0:bb348c97df44	5179	#define __HAL_RCC_CAN3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN3EN)) == RESET)
lypinator	0:bb348c97df44	5180	#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
lypinator	0:bb348c97df44	5181	#define __HAL_RCC_UART7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) == RESET)
lypinator	0:bb348c97df44	5182	#define __HAL_RCC_UART8_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) == RESET)
lypinator	0:bb348c97df44	5183	#endif /* STM32F413xx \|\| STM32F423xx */
lypinator	0:bb348c97df44	5184	/**
lypinator	0:bb348c97df44	5185	* @}
lypinator	0:bb348c97df44	5186	*/
lypinator	0:bb348c97df44	5187	/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
lypinator	0:bb348c97df44	5188	* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
lypinator	0:bb348c97df44	5189	* @note After reset, the peripheral clock (used for registers read/write access)
lypinator	0:bb348c97df44	5190	* is disabled and the application software has to enable this clock before
lypinator	0:bb348c97df44	5191	* using it.
lypinator	0:bb348c97df44	5192	* @{
lypinator	0:bb348c97df44	5193	*/
lypinator	0:bb348c97df44	5194	#define __HAL_RCC_TIM8_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	5195	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	5196	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
lypinator	0:bb348c97df44	5197	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	5198	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
lypinator	0:bb348c97df44	5199	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	5200	} while(0U)
lypinator	0:bb348c97df44	5201	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
lypinator	0:bb348c97df44	5202	#define __HAL_RCC_UART9_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	5203	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	5204	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_UART9EN);\
lypinator	0:bb348c97df44	5205	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	5206	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_UART9EN);\
lypinator	0:bb348c97df44	5207	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	5208	} while(0U)
lypinator	0:bb348c97df44	5209	#define __HAL_RCC_UART10_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	5210	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	5211	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_UART10EN);\
lypinator	0:bb348c97df44	5212	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	5213	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_UART10EN);\
lypinator	0:bb348c97df44	5214	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	5215	} while(0U)
lypinator	0:bb348c97df44	5216	#endif /* STM32F413xx \|\| STM32F423xx */
lypinator	0:bb348c97df44	5217	#define __HAL_RCC_SDIO_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	5218	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	5219	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
lypinator	0:bb348c97df44	5220	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	5221	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
lypinator	0:bb348c97df44	5222	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	5223	} while(0U)
lypinator	0:bb348c97df44	5224	#define __HAL_RCC_SPI4_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	5225	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	5226	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
lypinator	0:bb348c97df44	5227	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	5228	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
lypinator	0:bb348c97df44	5229	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	5230	} while(0U)
lypinator	0:bb348c97df44	5231	#define __HAL_RCC_EXTIT_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	5232	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	5233	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\
lypinator	0:bb348c97df44	5234	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	5235	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\
lypinator	0:bb348c97df44	5236	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	5237	} while(0U)
lypinator	0:bb348c97df44	5238	#define __HAL_RCC_TIM10_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	5239	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	5240	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
lypinator	0:bb348c97df44	5241	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	5242	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
lypinator	0:bb348c97df44	5243	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	5244	} while(0U)
lypinator	0:bb348c97df44	5245	#define __HAL_RCC_SPI5_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	5246	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	5247	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
lypinator	0:bb348c97df44	5248	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	5249	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
lypinator	0:bb348c97df44	5250	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	5251	} while(0U)
lypinator	0:bb348c97df44	5252	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
lypinator	0:bb348c97df44	5253	#define __HAL_RCC_SAI1_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	5254	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	5255	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
lypinator	0:bb348c97df44	5256	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	5257	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
lypinator	0:bb348c97df44	5258	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	5259	} while(0U)
lypinator	0:bb348c97df44	5260	#endif /* STM32F413xx \|\| STM32F423xx */
lypinator	0:bb348c97df44	5261	#define __HAL_RCC_DFSDM1_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	5262	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	5263	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
lypinator	0:bb348c97df44	5264	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	5265	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
lypinator	0:bb348c97df44	5266	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	5267	} while(0U)
lypinator	0:bb348c97df44	5268	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
lypinator	0:bb348c97df44	5269	#define __HAL_RCC_DFSDM2_CLK_ENABLE() do { \
lypinator	0:bb348c97df44	5270	__IO uint32_t tmpreg = 0x00U; \
lypinator	0:bb348c97df44	5271	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM2EN);\
lypinator	0:bb348c97df44	5272	/* Delay after an RCC peripheral clock enabling */ \
lypinator	0:bb348c97df44	5273	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM2EN);\
lypinator	0:bb348c97df44	5274	UNUSED(tmpreg); \
lypinator	0:bb348c97df44	5275	} while(0U)
lypinator	0:bb348c97df44	5276	#endif /* STM32F413xx \|\| STM32F423xx */
lypinator	0:bb348c97df44	5277
lypinator	0:bb348c97df44	5278	#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
lypinator	0:bb348c97df44	5279	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
lypinator	0:bb348c97df44	5280	#define __HAL_RCC_UART9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_UART9EN))
lypinator	0:bb348c97df44	5281	#define __HAL_RCC_UART10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_UART10EN))
lypinator	0:bb348c97df44	5282	#endif /* STM32F413xx \|\| STM32F423xx */
lypinator	0:bb348c97df44	5283	#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
lypinator	0:bb348c97df44	5284	#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
lypinator	0:bb348c97df44	5285	#define __HAL_RCC_EXTIT_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_EXTITEN))
lypinator	0:bb348c97df44	5286	#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
lypinator	0:bb348c97df44	5287	#define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
lypinator	0:bb348c97df44	5288	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
lypinator	0:bb348c97df44	5289	#define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))
lypinator	0:bb348c97df44	5290	#endif /* STM32F413xx \|\| STM32F423xx */
lypinator	0:bb348c97df44	5291	#define __HAL_RCC_DFSDM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DFSDM1EN))
lypinator	0:bb348c97df44	5292	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
lypinator	0:bb348c97df44	5293	#define __HAL_RCC_DFSDM2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DFSDM2EN))
lypinator	0:bb348c97df44	5294	#endif /* STM32F413xx \|\| STM32F423xx */
lypinator	0:bb348c97df44	5295	/**
lypinator	0:bb348c97df44	5296	* @}
lypinator	0:bb348c97df44	5297	*/
lypinator	0:bb348c97df44	5298
lypinator	0:bb348c97df44	5299	/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
lypinator	0:bb348c97df44	5300	* @brief Get the enable or disable status of the APB2 peripheral clock.
lypinator	0:bb348c97df44	5301	* @note After reset, the peripheral clock (used for registers read/write access)
lypinator	0:bb348c97df44	5302	* is disabled and the application software has to enable this clock before
lypinator	0:bb348c97df44	5303	* using it.
lypinator	0:bb348c97df44	5304	* @{
lypinator	0:bb348c97df44	5305	*/
lypinator	0:bb348c97df44	5306	#define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)
lypinator	0:bb348c97df44	5307	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
lypinator	0:bb348c97df44	5308	#define __HAL_RCC_UART9_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_UART9EN)) != RESET)
lypinator	0:bb348c97df44	5309	#define __HAL_RCC_UART10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_UART10EN)) != RESET)
lypinator	0:bb348c97df44	5310	#endif /* STM32F413xx \|\| STM32F423xx */
lypinator	0:bb348c97df44	5311	#define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET)
lypinator	0:bb348c97df44	5312	#define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)
lypinator	0:bb348c97df44	5313	#define __HAL_RCC_EXTIT_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) != RESET)
lypinator	0:bb348c97df44	5314	#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)
lypinator	0:bb348c97df44	5315	#define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET)
lypinator	0:bb348c97df44	5316	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
lypinator	0:bb348c97df44	5317	#define __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET)
lypinator	0:bb348c97df44	5318	#endif /* STM32F413xx \|\| STM32F423xx */
lypinator	0:bb348c97df44	5319	#define __HAL_RCC_DFSDM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) != RESET)
lypinator	0:bb348c97df44	5320	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
lypinator	0:bb348c97df44	5321	#define __HAL_RCC_DFSDM2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM2EN)) != RESET)
lypinator	0:bb348c97df44	5322	#endif /* STM32F413xx \|\| STM32F423xx */
lypinator	0:bb348c97df44	5323
lypinator	0:bb348c97df44	5324	#define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)
lypinator	0:bb348c97df44	5325	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
lypinator	0:bb348c97df44	5326	#define __HAL_RCC_UART9_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_UART9EN)) == RESET)
lypinator	0:bb348c97df44	5327	#define __HAL_RCC_UART10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_UART10EN)) == RESET)
lypinator	0:bb348c97df44	5328	#endif /* STM32F413xx \|\| STM32F423xx */
lypinator	0:bb348c97df44	5329	#define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET)
lypinator	0:bb348c97df44	5330	#define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
lypinator	0:bb348c97df44	5331	#define __HAL_RCC_EXTIT_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) == RESET)
lypinator	0:bb348c97df44	5332	#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)
lypinator	0:bb348c97df44	5333	#define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET)
lypinator	0:bb348c97df44	5334	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
lypinator	0:bb348c97df44	5335	#define __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET)
lypinator	0:bb348c97df44	5336	#endif /* STM32F413xx \|\| STM32F423xx */
lypinator	0:bb348c97df44	5337	#define __HAL_RCC_DFSDM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) == RESET)
lypinator	0:bb348c97df44	5338	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
lypinator	0:bb348c97df44	5339	#define __HAL_RCC_DFSDM2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM2EN)) == RESET)
lypinator	0:bb348c97df44	5340	#endif /* STM32F413xx \|\| STM32F423xx */
lypinator	0:bb348c97df44	5341	/**
lypinator	0:bb348c97df44	5342	* @}
lypinator	0:bb348c97df44	5343	*/
lypinator	0:bb348c97df44	5344
lypinator	0:bb348c97df44	5345	/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset
lypinator	0:bb348c97df44	5346	* @brief Force or release AHB1 peripheral reset.
lypinator	0:bb348c97df44	5347	* @{
lypinator	0:bb348c97df44	5348	*/
lypinator	0:bb348c97df44	5349	#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIODRST))
lypinator	0:bb348c97df44	5350	#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOERST))
lypinator	0:bb348c97df44	5351	#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOFRST))
lypinator	0:bb348c97df44	5352	#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOGRST))
lypinator	0:bb348c97df44	5353	#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_CRCRST))
lypinator	0:bb348c97df44	5354
lypinator	0:bb348c97df44	5355	#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
lypinator	0:bb348c97df44	5356	#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
lypinator	0:bb348c97df44	5357	#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
lypinator	0:bb348c97df44	5358	#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
lypinator	0:bb348c97df44	5359	#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
lypinator	0:bb348c97df44	5360	/**
lypinator	0:bb348c97df44	5361	* @}
lypinator	0:bb348c97df44	5362	*/
lypinator	0:bb348c97df44	5363
lypinator	0:bb348c97df44	5364	/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset
lypinator	0:bb348c97df44	5365	* @brief Force or release AHB2 peripheral reset.
lypinator	0:bb348c97df44	5366	* @{
lypinator	0:bb348c97df44	5367	*/
lypinator	0:bb348c97df44	5368	#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU)
lypinator	0:bb348c97df44	5369	#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U)
lypinator	0:bb348c97df44	5370
lypinator	0:bb348c97df44	5371	#if defined(STM32F423xx)
lypinator	0:bb348c97df44	5372	#define __HAL_RCC_AES_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_AESRST))
lypinator	0:bb348c97df44	5373	#define __HAL_RCC_AES_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_AESRST))
lypinator	0:bb348c97df44	5374	#endif /* STM32F423xx */
lypinator	0:bb348c97df44	5375
lypinator	0:bb348c97df44	5376	#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_OTGFSRST))
lypinator	0:bb348c97df44	5377	#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
lypinator	0:bb348c97df44	5378
lypinator	0:bb348c97df44	5379	#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_RNGRST))
lypinator	0:bb348c97df44	5380	#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
lypinator	0:bb348c97df44	5381	/**
lypinator	0:bb348c97df44	5382	* @}
lypinator	0:bb348c97df44	5383	*/
lypinator	0:bb348c97df44	5384
lypinator	0:bb348c97df44	5385	/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset
lypinator	0:bb348c97df44	5386	* @brief Force or release AHB3 peripheral reset.
lypinator	0:bb348c97df44	5387	* @{
lypinator	0:bb348c97df44	5388	*/
lypinator	0:bb348c97df44	5389	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
lypinator	0:bb348c97df44	5390	#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
lypinator	0:bb348c97df44	5391	#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U)
lypinator	0:bb348c97df44	5392
lypinator	0:bb348c97df44	5393	#define __HAL_RCC_FSMC_FORCE_RESET() (RCC->AHB3RSTR \|= (RCC_AHB3RSTR_FSMCRST))
lypinator	0:bb348c97df44	5394	#define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR \|= (RCC_AHB3RSTR_QSPIRST))
lypinator	0:bb348c97df44	5395
lypinator	0:bb348c97df44	5396	#define __HAL_RCC_FSMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FSMCRST))
lypinator	0:bb348c97df44	5397	#define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST))
lypinator	0:bb348c97df44	5398	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F413xx \|\| STM32F423xx */
lypinator	0:bb348c97df44	5399	#if defined(STM32F412Cx)
lypinator	0:bb348c97df44	5400	#define __HAL_RCC_AHB3_FORCE_RESET()
lypinator	0:bb348c97df44	5401	#define __HAL_RCC_AHB3_RELEASE_RESET()
lypinator	0:bb348c97df44	5402
lypinator	0:bb348c97df44	5403	#define __HAL_RCC_FSMC_FORCE_RESET()
lypinator	0:bb348c97df44	5404	#define __HAL_RCC_QSPI_FORCE_RESET()
lypinator	0:bb348c97df44	5405
lypinator	0:bb348c97df44	5406	#define __HAL_RCC_FSMC_RELEASE_RESET()
lypinator	0:bb348c97df44	5407	#define __HAL_RCC_QSPI_RELEASE_RESET()
lypinator	0:bb348c97df44	5408	#endif /* STM32F412Cx */
lypinator	0:bb348c97df44	5409	/**
lypinator	0:bb348c97df44	5410	* @}
lypinator	0:bb348c97df44	5411	*/
lypinator	0:bb348c97df44	5412
lypinator	0:bb348c97df44	5413	/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset
lypinator	0:bb348c97df44	5414	* @brief Force or release APB1 peripheral reset.
lypinator	0:bb348c97df44	5415	* @{
lypinator	0:bb348c97df44	5416	*/
lypinator	0:bb348c97df44	5417	#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM2RST))
lypinator	0:bb348c97df44	5418	#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM3RST))
lypinator	0:bb348c97df44	5419	#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM4RST))
lypinator	0:bb348c97df44	5420	#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM6RST))
lypinator	0:bb348c97df44	5421	#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM7RST))
lypinator	0:bb348c97df44	5422	#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM12RST))
lypinator	0:bb348c97df44	5423	#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM13RST))
lypinator	0:bb348c97df44	5424	#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM14RST))
lypinator	0:bb348c97df44	5425	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
lypinator	0:bb348c97df44	5426	#define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_LPTIM1RST))
lypinator	0:bb348c97df44	5427	#endif /* STM32F413xx \|\| STM32F423xx */
lypinator	0:bb348c97df44	5428	#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI3RST))
lypinator	0:bb348c97df44	5429	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
lypinator	0:bb348c97df44	5430	#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART3RST))
lypinator	0:bb348c97df44	5431	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F413xx \|\| STM32F423xx */
lypinator	0:bb348c97df44	5432	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
lypinator	0:bb348c97df44	5433	#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART4RST))
lypinator	0:bb348c97df44	5434	#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART5RST))
lypinator	0:bb348c97df44	5435	#endif /* STM32F413xx \|\| STM32F423xx */
lypinator	0:bb348c97df44	5436	#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C3RST))
lypinator	0:bb348c97df44	5437	#define __HAL_RCC_FMPI2C1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_FMPI2C1RST))
lypinator	0:bb348c97df44	5438	#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN1RST))
lypinator	0:bb348c97df44	5439	#define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN2RST))
lypinator	0:bb348c97df44	5440	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
lypinator	0:bb348c97df44	5441	#define __HAL_RCC_CAN3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN3RST))
lypinator	0:bb348c97df44	5442	#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DACRST))
lypinator	0:bb348c97df44	5443	#define __HAL_RCC_UART7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART7RST))
lypinator	0:bb348c97df44	5444	#define __HAL_RCC_UART8_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART8RST))
lypinator	0:bb348c97df44	5445	#endif /* STM32F413xx \|\| STM32F423xx */
lypinator	0:bb348c97df44	5446
lypinator	0:bb348c97df44	5447	#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
lypinator	0:bb348c97df44	5448	#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
lypinator	0:bb348c97df44	5449	#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
lypinator	0:bb348c97df44	5450	#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
lypinator	0:bb348c97df44	5451	#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
lypinator	0:bb348c97df44	5452	#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
lypinator	0:bb348c97df44	5453	#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
lypinator	0:bb348c97df44	5454	#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
lypinator	0:bb348c97df44	5455	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
lypinator	0:bb348c97df44	5456	#define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LPTIM1RST))
lypinator	0:bb348c97df44	5457	#endif /* STM32F413xx \|\| STM32F423xx */
lypinator	0:bb348c97df44	5458	#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
lypinator	0:bb348c97df44	5459	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
lypinator	0:bb348c97df44	5460	#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
lypinator	0:bb348c97df44	5461	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F413xx \|\| STM32F423xx */
lypinator	0:bb348c97df44	5462	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
lypinator	0:bb348c97df44	5463	#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
lypinator	0:bb348c97df44	5464	#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
lypinator	0:bb348c97df44	5465	#endif /* STM32F413xx \|\| STM32F423xx */
lypinator	0:bb348c97df44	5466	#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
lypinator	0:bb348c97df44	5467	#define __HAL_RCC_FMPI2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_FMPI2C1RST))
lypinator	0:bb348c97df44	5468	#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
lypinator	0:bb348c97df44	5469	#define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
lypinator	0:bb348c97df44	5470	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
lypinator	0:bb348c97df44	5471	#define __HAL_RCC_CAN3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN3RST))
lypinator	0:bb348c97df44	5472	#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
lypinator	0:bb348c97df44	5473	#define __HAL_RCC_UART7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST))
lypinator	0:bb348c97df44	5474	#define __HAL_RCC_UART8_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST))
lypinator	0:bb348c97df44	5475	#endif /* STM32F413xx \|\| STM32F423xx */
lypinator	0:bb348c97df44	5476	/**
lypinator	0:bb348c97df44	5477	* @}
lypinator	0:bb348c97df44	5478	*/
lypinator	0:bb348c97df44	5479
lypinator	0:bb348c97df44	5480	/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
lypinator	0:bb348c97df44	5481	* @brief Force or release APB2 peripheral reset.
lypinator	0:bb348c97df44	5482	* @{
lypinator	0:bb348c97df44	5483	*/
lypinator	0:bb348c97df44	5484	#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM8RST))
lypinator	0:bb348c97df44	5485	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
lypinator	0:bb348c97df44	5486	#define __HAL_RCC_UART9_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_UART9RST))
lypinator	0:bb348c97df44	5487	#define __HAL_RCC_UART10_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_UART10RST))
lypinator	0:bb348c97df44	5488	#endif /* STM32F413xx \|\| STM32F423xx */
lypinator	0:bb348c97df44	5489	#define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SDIORST))
lypinator	0:bb348c97df44	5490	#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI4RST))
lypinator	0:bb348c97df44	5491	#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM10RST))
lypinator	0:bb348c97df44	5492	#define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI5RST))
lypinator	0:bb348c97df44	5493	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
lypinator	0:bb348c97df44	5494	#define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SAI1RST))
lypinator	0:bb348c97df44	5495	#endif /* STM32F413xx \|\| STM32F423xx */
lypinator	0:bb348c97df44	5496	#define __HAL_RCC_DFSDM1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_DFSDM1RST))
lypinator	0:bb348c97df44	5497	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
lypinator	0:bb348c97df44	5498	#define __HAL_RCC_DFSDM2_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_DFSDM2RST))
lypinator	0:bb348c97df44	5499	#endif /* STM32F413xx \|\| STM32F423xx */
lypinator	0:bb348c97df44	5500
lypinator	0:bb348c97df44	5501	#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
lypinator	0:bb348c97df44	5502	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
lypinator	0:bb348c97df44	5503	#define __HAL_RCC_UART9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_UART9RST))
lypinator	0:bb348c97df44	5504	#define __HAL_RCC_UART10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_UART10RST))
lypinator	0:bb348c97df44	5505	#endif /* STM32F413xx \|\| STM32F423xx */
lypinator	0:bb348c97df44	5506	#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
lypinator	0:bb348c97df44	5507	#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
lypinator	0:bb348c97df44	5508	#define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
lypinator	0:bb348c97df44	5509	#define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
lypinator	0:bb348c97df44	5510	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
lypinator	0:bb348c97df44	5511	#define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))
lypinator	0:bb348c97df44	5512	#endif /* STM32F413xx \|\| STM32F423xx */
lypinator	0:bb348c97df44	5513	#define __HAL_RCC_DFSDM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DFSDM1RST))
lypinator	0:bb348c97df44	5514	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
lypinator	0:bb348c97df44	5515	#define __HAL_RCC_DFSDM2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DFSDM2RST))
lypinator	0:bb348c97df44	5516	#endif /* STM32F413xx \|\| STM32F423xx */
lypinator	0:bb348c97df44	5517	/**
lypinator	0:bb348c97df44	5518	* @}
lypinator	0:bb348c97df44	5519	*/
lypinator	0:bb348c97df44	5520
lypinator	0:bb348c97df44	5521	/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
lypinator	0:bb348c97df44	5522	* @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
lypinator	0:bb348c97df44	5523	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
lypinator	0:bb348c97df44	5524	* power consumption.
lypinator	0:bb348c97df44	5525	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
lypinator	0:bb348c97df44	5526	* @note By default, all peripheral clocks are enabled during SLEEP mode.
lypinator	0:bb348c97df44	5527	* @{
lypinator	0:bb348c97df44	5528	*/
lypinator	0:bb348c97df44	5529	#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIODLPEN))
lypinator	0:bb348c97df44	5530	#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOELPEN))
lypinator	0:bb348c97df44	5531	#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOFLPEN))
lypinator	0:bb348c97df44	5532	#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOGLPEN))
lypinator	0:bb348c97df44	5533	#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_CRCLPEN))
lypinator	0:bb348c97df44	5534	#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_FLITFLPEN))
lypinator	0:bb348c97df44	5535	#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM1LPEN))
lypinator	0:bb348c97df44	5536	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
lypinator	0:bb348c97df44	5537	#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM2LPEN))
lypinator	0:bb348c97df44	5538	#endif /* STM32F413xx \|\| STM32F423xx */
lypinator	0:bb348c97df44	5539
lypinator	0:bb348c97df44	5540	#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
lypinator	0:bb348c97df44	5541	#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
lypinator	0:bb348c97df44	5542	#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
lypinator	0:bb348c97df44	5543	#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
lypinator	0:bb348c97df44	5544	#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
lypinator	0:bb348c97df44	5545	#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
lypinator	0:bb348c97df44	5546	#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
lypinator	0:bb348c97df44	5547	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
lypinator	0:bb348c97df44	5548	#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
lypinator	0:bb348c97df44	5549	#endif /* STM32F413xx \|\| STM32F423xx */
lypinator	0:bb348c97df44	5550	/**
lypinator	0:bb348c97df44	5551	* @}
lypinator	0:bb348c97df44	5552	*/
lypinator	0:bb348c97df44	5553
lypinator	0:bb348c97df44	5554	/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
lypinator	0:bb348c97df44	5555	* @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
lypinator	0:bb348c97df44	5556	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
lypinator	0:bb348c97df44	5557	* power consumption.
lypinator	0:bb348c97df44	5558	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
lypinator	0:bb348c97df44	5559	* @note By default, all peripheral clocks are enabled during SLEEP mode.
lypinator	0:bb348c97df44	5560	* @{
lypinator	0:bb348c97df44	5561	*/
lypinator	0:bb348c97df44	5562	#if defined(STM32F423xx)
lypinator	0:bb348c97df44	5563	#define __HAL_RCC_AES_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_AESLPEN))
lypinator	0:bb348c97df44	5564	#define __HAL_RCC_AES_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_AESLPEN))
lypinator	0:bb348c97df44	5565	#endif /* STM32F423xx */
lypinator	0:bb348c97df44	5566
lypinator	0:bb348c97df44	5567	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_OTGFSLPEN))
lypinator	0:bb348c97df44	5568	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
lypinator	0:bb348c97df44	5569
lypinator	0:bb348c97df44	5570	#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_RNGLPEN))
lypinator	0:bb348c97df44	5571	#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
lypinator	0:bb348c97df44	5572	/**
lypinator	0:bb348c97df44	5573	* @}
lypinator	0:bb348c97df44	5574	*/
lypinator	0:bb348c97df44	5575
lypinator	0:bb348c97df44	5576	/** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable
lypinator	0:bb348c97df44	5577	* @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
lypinator	0:bb348c97df44	5578	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
lypinator	0:bb348c97df44	5579	* power consumption.
lypinator	0:bb348c97df44	5580	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
lypinator	0:bb348c97df44	5581	* @note By default, all peripheral clocks are enabled during SLEEP mode.
lypinator	0:bb348c97df44	5582	* @{
lypinator	0:bb348c97df44	5583	*/
lypinator	0:bb348c97df44	5584	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
lypinator	0:bb348c97df44	5585	#define __HAL_RCC_FSMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_FSMCLPEN))
lypinator	0:bb348c97df44	5586	#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_QSPILPEN))
lypinator	0:bb348c97df44	5587
lypinator	0:bb348c97df44	5588	#define __HAL_RCC_FSMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FSMCLPEN))
lypinator	0:bb348c97df44	5589	#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN))
lypinator	0:bb348c97df44	5590	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F413xx \|\| STM32F423xx */
lypinator	0:bb348c97df44	5591
lypinator	0:bb348c97df44	5592	/**
lypinator	0:bb348c97df44	5593	* @}
lypinator	0:bb348c97df44	5594	*/
lypinator	0:bb348c97df44	5595
lypinator	0:bb348c97df44	5596	/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
lypinator	0:bb348c97df44	5597	* @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
lypinator	0:bb348c97df44	5598	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
lypinator	0:bb348c97df44	5599	* power consumption.
lypinator	0:bb348c97df44	5600	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
lypinator	0:bb348c97df44	5601	* @note By default, all peripheral clocks are enabled during SLEEP mode.
lypinator	0:bb348c97df44	5602	* @{
lypinator	0:bb348c97df44	5603	*/
lypinator	0:bb348c97df44	5604	#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM2LPEN))
lypinator	0:bb348c97df44	5605	#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM3LPEN))
lypinator	0:bb348c97df44	5606	#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM4LPEN))
lypinator	0:bb348c97df44	5607	#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM6LPEN))
lypinator	0:bb348c97df44	5608	#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM7LPEN))
lypinator	0:bb348c97df44	5609	#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM12LPEN))
lypinator	0:bb348c97df44	5610	#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM13LPEN))
lypinator	0:bb348c97df44	5611	#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM14LPEN))
lypinator	0:bb348c97df44	5612	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
lypinator	0:bb348c97df44	5613	#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_LPTIM1LPEN))
lypinator	0:bb348c97df44	5614	#endif /* STM32F413xx \|\| STM32F423xx */
lypinator	0:bb348c97df44	5615	#define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_RTCAPBLPEN))
lypinator	0:bb348c97df44	5616	#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_SPI3LPEN))
lypinator	0:bb348c97df44	5617	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
lypinator	0:bb348c97df44	5618	#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_USART3LPEN))
lypinator	0:bb348c97df44	5619	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F413xx \|\| STM32F423xx */
lypinator	0:bb348c97df44	5620	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
lypinator	0:bb348c97df44	5621	#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART4LPEN))
lypinator	0:bb348c97df44	5622	#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART5LPEN))
lypinator	0:bb348c97df44	5623	#endif /* STM32F413xx \|\| STM32F423xx */
lypinator	0:bb348c97df44	5624	#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C3LPEN))
lypinator	0:bb348c97df44	5625	#define __HAL_RCC_FMPI2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_FMPI2C1LPEN))
lypinator	0:bb348c97df44	5626	#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN1LPEN))
lypinator	0:bb348c97df44	5627	#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN2LPEN))
lypinator	0:bb348c97df44	5628	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
lypinator	0:bb348c97df44	5629	#define __HAL_RCC_CAN3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN3LPEN))
lypinator	0:bb348c97df44	5630	#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_DACLPEN))
lypinator	0:bb348c97df44	5631	#define __HAL_RCC_UART7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART7LPEN))
lypinator	0:bb348c97df44	5632	#define __HAL_RCC_UART8_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART8LPEN))
lypinator	0:bb348c97df44	5633	#endif /* STM32F413xx \|\| STM32F423xx */
lypinator	0:bb348c97df44	5634
lypinator	0:bb348c97df44	5635	#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
lypinator	0:bb348c97df44	5636	#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
lypinator	0:bb348c97df44	5637	#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
lypinator	0:bb348c97df44	5638	#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
lypinator	0:bb348c97df44	5639	#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
lypinator	0:bb348c97df44	5640	#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
lypinator	0:bb348c97df44	5641	#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
lypinator	0:bb348c97df44	5642	#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
lypinator	0:bb348c97df44	5643	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
lypinator	0:bb348c97df44	5644	#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LPTIM1LPEN))
lypinator	0:bb348c97df44	5645	#endif /* STM32F413xx \|\| STM32F423xx */
lypinator	0:bb348c97df44	5646	#define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_RTCAPBLPEN))
lypinator	0:bb348c97df44	5647	#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
lypinator	0:bb348c97df44	5648	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
lypinator	0:bb348c97df44	5649	#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
lypinator	0:bb348c97df44	5650	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F413xx \|\| STM32F423xx */
lypinator	0:bb348c97df44	5651	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
lypinator	0:bb348c97df44	5652	#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
lypinator	0:bb348c97df44	5653	#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
lypinator	0:bb348c97df44	5654	#endif /* STM32F413xx \|\| STM32F423xx */
lypinator	0:bb348c97df44	5655	#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
lypinator	0:bb348c97df44	5656	#define __HAL_RCC_FMPI2C1_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_FMPI2C1LPEN))
lypinator	0:bb348c97df44	5657	#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
lypinator	0:bb348c97df44	5658	#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
lypinator	0:bb348c97df44	5659	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
lypinator	0:bb348c97df44	5660	#define __HAL_RCC_CAN3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN3LPEN))
lypinator	0:bb348c97df44	5661	#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
lypinator	0:bb348c97df44	5662	#define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN))
lypinator	0:bb348c97df44	5663	#define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN))
lypinator	0:bb348c97df44	5664	#endif /* STM32F413xx \|\| STM32F423xx */
lypinator	0:bb348c97df44	5665	/**
lypinator	0:bb348c97df44	5666	* @}
lypinator	0:bb348c97df44	5667	*/
lypinator	0:bb348c97df44	5668
lypinator	0:bb348c97df44	5669	/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
lypinator	0:bb348c97df44	5670	* @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
lypinator	0:bb348c97df44	5671	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
lypinator	0:bb348c97df44	5672	* power consumption.
lypinator	0:bb348c97df44	5673	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
lypinator	0:bb348c97df44	5674	* @note By default, all peripheral clocks are enabled during SLEEP mode.
lypinator	0:bb348c97df44	5675	* @{
lypinator	0:bb348c97df44	5676	*/
lypinator	0:bb348c97df44	5677	#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM8LPEN))
lypinator	0:bb348c97df44	5678	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
lypinator	0:bb348c97df44	5679	#define __HAL_RCC_UART9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_UART9LPEN))
lypinator	0:bb348c97df44	5680	#define __HAL_RCC_UART10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_UART10LPEN))
lypinator	0:bb348c97df44	5681	#endif /* STM32F413xx \|\| STM32F423xx */
lypinator	0:bb348c97df44	5682	#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SDIOLPEN))
lypinator	0:bb348c97df44	5683	#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI4LPEN))
lypinator	0:bb348c97df44	5684	#define __HAL_RCC_EXTIT_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_EXTITLPEN))
lypinator	0:bb348c97df44	5685	#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM10LPEN))
lypinator	0:bb348c97df44	5686	#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI5LPEN))
lypinator	0:bb348c97df44	5687	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
lypinator	0:bb348c97df44	5688	#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SAI1LPEN))
lypinator	0:bb348c97df44	5689	#endif /* STM32F413xx \|\| STM32F423xx */
lypinator	0:bb348c97df44	5690	#define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_DFSDM1LPEN))
lypinator	0:bb348c97df44	5691	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
lypinator	0:bb348c97df44	5692	#define __HAL_RCC_DFSDM2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_DFSDM2LPEN))
lypinator	0:bb348c97df44	5693	#endif /* STM32F413xx \|\| STM32F423xx */
lypinator	0:bb348c97df44	5694
lypinator	0:bb348c97df44	5695	#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
lypinator	0:bb348c97df44	5696	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
lypinator	0:bb348c97df44	5697	#define __HAL_RCC_UART9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_UART9LPEN))
lypinator	0:bb348c97df44	5698	#define __HAL_RCC_UART10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_UART10LPEN))
lypinator	0:bb348c97df44	5699	#endif /* STM32F413xx \|\| STM32F423xx */
lypinator	0:bb348c97df44	5700	#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
lypinator	0:bb348c97df44	5701	#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
lypinator	0:bb348c97df44	5702	#define __HAL_RCC_EXTIT_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_EXTITLPEN))
lypinator	0:bb348c97df44	5703	#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
lypinator	0:bb348c97df44	5704	#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
lypinator	0:bb348c97df44	5705	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
lypinator	0:bb348c97df44	5706	#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN))
lypinator	0:bb348c97df44	5707	#endif /* STM32F413xx \|\| STM32F423xx */
lypinator	0:bb348c97df44	5708	#define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DFSDM1LPEN))
lypinator	0:bb348c97df44	5709	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
lypinator	0:bb348c97df44	5710	#define __HAL_RCC_DFSDM2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DFSDM2LPEN))
lypinator	0:bb348c97df44	5711	#endif /* STM32F413xx \|\| STM32F423xx */
lypinator	0:bb348c97df44	5712	/**
lypinator	0:bb348c97df44	5713	* @}
lypinator	0:bb348c97df44	5714	*/
lypinator	0:bb348c97df44	5715	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx \|\| STM32F413xx \|\| STM32F423xx */
lypinator	0:bb348c97df44	5716	/----------------------------------------------------------------------------/
lypinator	0:bb348c97df44	5717
lypinator	0:bb348c97df44	5718	/------------------------------- PLL Configuration --------------------------/
lypinator	0:bb348c97df44	5719	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx) \|\| defined(STM32F446xx) \|\|\
lypinator	0:bb348c97df44	5720	defined(STM32F469xx) \|\| defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| \
lypinator	0:bb348c97df44	5721	defined(STM32F412Rx) \|\| defined(STM32F412Cx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
lypinator	0:bb348c97df44	5722	/** @brief Macro to configure the main PLL clock source, multiplication and division factors.
lypinator	0:bb348c97df44	5723	* @note This function must be used only when the main PLL is disabled.
lypinator	0:bb348c97df44	5724	* @param __RCC_PLLSource__ specifies the PLL entry clock source.
lypinator	0:bb348c97df44	5725	* This parameter can be one of the following values:
lypinator	0:bb348c97df44	5726	* @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
lypinator	0:bb348c97df44	5727	* @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
lypinator	0:bb348c97df44	5728	* @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.
lypinator	0:bb348c97df44	5729	* @param __PLLM__ specifies the division factor for PLL VCO input clock
lypinator	0:bb348c97df44	5730	* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
lypinator	0:bb348c97df44	5731	* @note You have to set the PLLM parameter correctly to ensure that the VCO input
lypinator	0:bb348c97df44	5732	* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
lypinator	0:bb348c97df44	5733	* of 2 MHz to limit PLL jitter.
lypinator	0:bb348c97df44	5734	* @param __PLLN__ specifies the multiplication factor for PLL VCO output clock
lypinator	0:bb348c97df44	5735	* This parameter must be a number between Min_Data = 50 and Max_Data = 432.
lypinator	0:bb348c97df44	5736	* @note You have to set the PLLN parameter correctly to ensure that the VCO
lypinator	0:bb348c97df44	5737	* output frequency is between 100 and 432 MHz.
lypinator	0:bb348c97df44	5738	*
lypinator	0:bb348c97df44	5739	* @param __PLLP__ specifies the division factor for main system clock (SYSCLK)
lypinator	0:bb348c97df44	5740	* This parameter must be a number in the range {2, 4, 6, or 8}.
lypinator	0:bb348c97df44	5741	*
lypinator	0:bb348c97df44	5742	* @param __PLLQ__ specifies the division factor for OTG FS, SDIO and RNG clocks
lypinator	0:bb348c97df44	5743	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
lypinator	0:bb348c97df44	5744	* @note If the USB OTG FS is used in your application, you have to set the
lypinator	0:bb348c97df44	5745	* PLLQ parameter correctly to have 48 MHz clock for the USB. However,
lypinator	0:bb348c97df44	5746	* the SDIO and RNG need a frequency lower than or equal to 48 MHz to work
lypinator	0:bb348c97df44	5747	* correctly.
lypinator	0:bb348c97df44	5748	*
lypinator	0:bb348c97df44	5749	* @param __PLLR__ PLL division factor for I2S, SAI, SYSTEM, SPDIFRX clocks.
lypinator	0:bb348c97df44	5750	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
lypinator	0:bb348c97df44	5751	* @note This parameter is only available in STM32F446xx/STM32F469xx/STM32F479xx/
lypinator	0:bb348c97df44	5752	STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx/STM32F413xx/STM32F423xx devices.
lypinator	0:bb348c97df44	5753	*
lypinator	0:bb348c97df44	5754	*/
lypinator	0:bb348c97df44	5755	#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__) \
lypinator	0:bb348c97df44	5756	(RCC->PLLCFGR = ((__RCC_PLLSource__) \| (__PLLM__) \| \
lypinator	0:bb348c97df44	5757	((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) \| \
lypinator	0:bb348c97df44	5758	((((__PLLP__) >> 1U) -1U) << RCC_PLLCFGR_PLLP_Pos) \| \
lypinator	0:bb348c97df44	5759	((__PLLQ__) << RCC_PLLCFGR_PLLQ_Pos) \| \
lypinator	0:bb348c97df44	5760	((__PLLR__) << RCC_PLLCFGR_PLLR_Pos)))
lypinator	0:bb348c97df44	5761	#else
lypinator	0:bb348c97df44	5762	/** @brief Macro to configure the main PLL clock source, multiplication and division factors.
lypinator	0:bb348c97df44	5763	* @note This function must be used only when the main PLL is disabled.
lypinator	0:bb348c97df44	5764	* @param __RCC_PLLSource__ specifies the PLL entry clock source.
lypinator	0:bb348c97df44	5765	* This parameter can be one of the following values:
lypinator	0:bb348c97df44	5766	* @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
lypinator	0:bb348c97df44	5767	* @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
lypinator	0:bb348c97df44	5768	* @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.
lypinator	0:bb348c97df44	5769	* @param __PLLM__ specifies the division factor for PLL VCO input clock
lypinator	0:bb348c97df44	5770	* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
lypinator	0:bb348c97df44	5771	* @note You have to set the PLLM parameter correctly to ensure that the VCO input
lypinator	0:bb348c97df44	5772	* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
lypinator	0:bb348c97df44	5773	* of 2 MHz to limit PLL jitter.
lypinator	0:bb348c97df44	5774	* @param __PLLN__ specifies the multiplication factor for PLL VCO output clock
lypinator	0:bb348c97df44	5775	* This parameter must be a number between Min_Data = 50 and Max_Data = 432
lypinator	0:bb348c97df44	5776	* Except for STM32F411xE devices where Min_Data = 192.
lypinator	0:bb348c97df44	5777	* @note You have to set the PLLN parameter correctly to ensure that the VCO
lypinator	0:bb348c97df44	5778	* output frequency is between 100 and 432 MHz, Except for STM32F411xE devices
lypinator	0:bb348c97df44	5779	* where frequency is between 192 and 432 MHz.
lypinator	0:bb348c97df44	5780	* @param __PLLP__ specifies the division factor for main system clock (SYSCLK)
lypinator	0:bb348c97df44	5781	* This parameter must be a number in the range {2, 4, 6, or 8}.
lypinator	0:bb348c97df44	5782	*
lypinator	0:bb348c97df44	5783	* @param __PLLQ__ specifies the division factor for OTG FS, SDIO and RNG clocks
lypinator	0:bb348c97df44	5784	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
lypinator	0:bb348c97df44	5785	* @note If the USB OTG FS is used in your application, you have to set the
lypinator	0:bb348c97df44	5786	* PLLQ parameter correctly to have 48 MHz clock for the USB. However,
lypinator	0:bb348c97df44	5787	* the SDIO and RNG need a frequency lower than or equal to 48 MHz to work
lypinator	0:bb348c97df44	5788	* correctly.
lypinator	0:bb348c97df44	5789	*
lypinator	0:bb348c97df44	5790	*/
lypinator	0:bb348c97df44	5791	#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__) \
lypinator	0:bb348c97df44	5792	(RCC->PLLCFGR = (0x20000000U \| (__RCC_PLLSource__) \| (__PLLM__)\| \
lypinator	0:bb348c97df44	5793	((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) \| \
lypinator	0:bb348c97df44	5794	((((__PLLP__) >> 1U) -1U) << RCC_PLLCFGR_PLLP_Pos) \| \
lypinator	0:bb348c97df44	5795	((__PLLQ__) << RCC_PLLCFGR_PLLQ_Pos)))
lypinator	0:bb348c97df44	5796	#endif /* STM32F410xx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx */
lypinator	0:bb348c97df44	5797	/----------------------------------------------------------------------------/
lypinator	0:bb348c97df44	5798
lypinator	0:bb348c97df44	5799	/----------------------------PLLI2S Configuration ---------------------------/
lypinator	0:bb348c97df44	5800	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\| \
lypinator	0:bb348c97df44	5801	defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| \
lypinator	0:bb348c97df44	5802	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| \
lypinator	0:bb348c97df44	5803	defined(STM32F469xx) \|\| defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| \
lypinator	0:bb348c97df44	5804	defined(STM32F412Rx) \|\| defined(STM32F412Cx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
lypinator	0:bb348c97df44	5805
lypinator	0:bb348c97df44	5806	/** @brief Macros to enable or disable the PLLI2S.
lypinator	0:bb348c97df44	5807	* @note The PLLI2S is disabled by hardware when entering STOP and STANDBY modes.
lypinator	0:bb348c97df44	5808	*/
lypinator	0:bb348c97df44	5809	#define __HAL_RCC_PLLI2S_ENABLE() ((__IO uint32_t ) RCC_CR_PLLI2SON_BB = ENABLE)
lypinator	0:bb348c97df44	5810	#define __HAL_RCC_PLLI2S_DISABLE() ((__IO uint32_t ) RCC_CR_PLLI2SON_BB = DISABLE)
lypinator	0:bb348c97df44	5811
lypinator	0:bb348c97df44	5812	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\|
lypinator	0:bb348c97df44	5813	STM32F401xC \|\| STM32F401xE \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\| STM32F412Vx \|\|
lypinator	0:bb348c97df44	5814	STM32F412Rx \|\| STM32F412Cx */
lypinator	0:bb348c97df44	5815	#if defined(STM32F446xx)
lypinator	0:bb348c97df44	5816	/** @brief Macro to configure the PLLI2S clock multiplication and division factors .
lypinator	0:bb348c97df44	5817	* @note This macro must be used only when the PLLI2S is disabled.
lypinator	0:bb348c97df44	5818	* @note PLLI2S clock source is common with the main PLL (configured in
lypinator	0:bb348c97df44	5819	* HAL_RCC_ClockConfig() API).
lypinator	0:bb348c97df44	5820	* @param __PLLI2SM__ specifies the division factor for PLLI2S VCO input clock
lypinator	0:bb348c97df44	5821	* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
lypinator	0:bb348c97df44	5822	* @note You have to set the PLLI2SM parameter correctly to ensure that the VCO input
lypinator	0:bb348c97df44	5823	* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
lypinator	0:bb348c97df44	5824	* of 1 MHz to limit PLLI2S jitter.
lypinator	0:bb348c97df44	5825	*
lypinator	0:bb348c97df44	5826	* @param __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock
lypinator	0:bb348c97df44	5827	* This parameter must be a number between Min_Data = 50 and Max_Data = 432.
lypinator	0:bb348c97df44	5828	* @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
lypinator	0:bb348c97df44	5829	* output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
lypinator	0:bb348c97df44	5830	*
lypinator	0:bb348c97df44	5831	* @param __PLLI2SP__ specifies division factor for SPDIFRX Clock.
lypinator	0:bb348c97df44	5832	* This parameter must be a number in the range {2, 4, 6, or 8}.
lypinator	0:bb348c97df44	5833	* @note the PLLI2SP parameter is only available with STM32F446xx Devices
lypinator	0:bb348c97df44	5834	*
lypinator	0:bb348c97df44	5835	* @param __PLLI2SR__ specifies the division factor for I2S clock
lypinator	0:bb348c97df44	5836	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
lypinator	0:bb348c97df44	5837	* @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
lypinator	0:bb348c97df44	5838	* on the I2S clock frequency.
lypinator	0:bb348c97df44	5839	*
lypinator	0:bb348c97df44	5840	* @param __PLLI2SQ__ specifies the division factor for SAI clock
lypinator	0:bb348c97df44	5841	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
lypinator	0:bb348c97df44	5842	*/
lypinator	0:bb348c97df44	5843	#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SP__, __PLLI2SQ__, __PLLI2SR__) \
lypinator	0:bb348c97df44	5844	(RCC->PLLI2SCFGR = ((__PLLI2SM__) \|\
lypinator	0:bb348c97df44	5845	((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos) \|\
lypinator	0:bb348c97df44	5846	((((__PLLI2SP__) >> 1U) -1U) << RCC_PLLI2SCFGR_PLLI2SP_Pos) \|\
lypinator	0:bb348c97df44	5847	((__PLLI2SQ__) << RCC_PLLI2SCFGR_PLLI2SQ_Pos) \|\
lypinator	0:bb348c97df44	5848	((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos)))
lypinator	0:bb348c97df44	5849	#elif defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx) \|\|\
lypinator	0:bb348c97df44	5850	defined(STM32F413xx) \|\| defined(STM32F423xx)
lypinator	0:bb348c97df44	5851	/** @brief Macro to configure the PLLI2S clock multiplication and division factors .
lypinator	0:bb348c97df44	5852	* @note This macro must be used only when the PLLI2S is disabled.
lypinator	0:bb348c97df44	5853	* @note PLLI2S clock source is common with the main PLL (configured in
lypinator	0:bb348c97df44	5854	* HAL_RCC_ClockConfig() API).
lypinator	0:bb348c97df44	5855	* @param __PLLI2SM__ specifies the division factor for PLLI2S VCO input clock
lypinator	0:bb348c97df44	5856	* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
lypinator	0:bb348c97df44	5857	* @note You have to set the PLLI2SM parameter correctly to ensure that the VCO input
lypinator	0:bb348c97df44	5858	* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
lypinator	0:bb348c97df44	5859	* of 1 MHz to limit PLLI2S jitter.
lypinator	0:bb348c97df44	5860	*
lypinator	0:bb348c97df44	5861	* @param __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock
lypinator	0:bb348c97df44	5862	* This parameter must be a number between Min_Data = 50 and Max_Data = 432.
lypinator	0:bb348c97df44	5863	* @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
lypinator	0:bb348c97df44	5864	* output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
lypinator	0:bb348c97df44	5865	*
lypinator	0:bb348c97df44	5866	* @param __PLLI2SR__ specifies the division factor for I2S clock
lypinator	0:bb348c97df44	5867	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
lypinator	0:bb348c97df44	5868	* @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
lypinator	0:bb348c97df44	5869	* on the I2S clock frequency.
lypinator	0:bb348c97df44	5870	*
lypinator	0:bb348c97df44	5871	* @param __PLLI2SQ__ specifies the division factor for SAI clock
lypinator	0:bb348c97df44	5872	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
lypinator	0:bb348c97df44	5873	*/
lypinator	0:bb348c97df44	5874	#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SQ__, __PLLI2SR__) \
lypinator	0:bb348c97df44	5875	(RCC->PLLI2SCFGR = ((__PLLI2SM__) \|\
lypinator	0:bb348c97df44	5876	((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos) \|\
lypinator	0:bb348c97df44	5877	((__PLLI2SQ__) << RCC_PLLI2SCFGR_PLLI2SQ_Pos) \|\
lypinator	0:bb348c97df44	5878	((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos)))
lypinator	0:bb348c97df44	5879	#else
lypinator	0:bb348c97df44	5880	/** @brief Macro to configure the PLLI2S clock multiplication and division factors .
lypinator	0:bb348c97df44	5881	* @note This macro must be used only when the PLLI2S is disabled.
lypinator	0:bb348c97df44	5882	* @note PLLI2S clock source is common with the main PLL (configured in
lypinator	0:bb348c97df44	5883	* HAL_RCC_ClockConfig() API).
lypinator	0:bb348c97df44	5884	* @param __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock
lypinator	0:bb348c97df44	5885	* This parameter must be a number between Min_Data = 50 and Max_Data = 432.
lypinator	0:bb348c97df44	5886	* @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
lypinator	0:bb348c97df44	5887	* output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
lypinator	0:bb348c97df44	5888	*
lypinator	0:bb348c97df44	5889	* @param __PLLI2SR__ specifies the division factor for I2S clock
lypinator	0:bb348c97df44	5890	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
lypinator	0:bb348c97df44	5891	* @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
lypinator	0:bb348c97df44	5892	* on the I2S clock frequency.
lypinator	0:bb348c97df44	5893	*
lypinator	0:bb348c97df44	5894	*/
lypinator	0:bb348c97df44	5895	#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SR__) \
lypinator	0:bb348c97df44	5896	(RCC->PLLI2SCFGR = (((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos) \|\
lypinator	0:bb348c97df44	5897	((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos)))
lypinator	0:bb348c97df44	5898	#endif /* STM32F446xx */
lypinator	0:bb348c97df44	5899
lypinator	0:bb348c97df44	5900	#if defined(STM32F411xE)
lypinator	0:bb348c97df44	5901	/** @brief Macro to configure the PLLI2S clock multiplication and division factors .
lypinator	0:bb348c97df44	5902	* @note This macro must be used only when the PLLI2S is disabled.
lypinator	0:bb348c97df44	5903	* @note This macro must be used only when the PLLI2S is disabled.
lypinator	0:bb348c97df44	5904	* @note PLLI2S clock source is common with the main PLL (configured in
lypinator	0:bb348c97df44	5905	* HAL_RCC_ClockConfig() API).
lypinator	0:bb348c97df44	5906	* @param __PLLI2SM__ specifies the division factor for PLLI2S VCO input clock
lypinator	0:bb348c97df44	5907	* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
lypinator	0:bb348c97df44	5908	* @note The PLLI2SM parameter is only used with STM32F411xE/STM32F410xx Devices
lypinator	0:bb348c97df44	5909	* @note You have to set the PLLI2SM parameter correctly to ensure that the VCO input
lypinator	0:bb348c97df44	5910	* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
lypinator	0:bb348c97df44	5911	* of 2 MHz to limit PLLI2S jitter.
lypinator	0:bb348c97df44	5912	* @param __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock
lypinator	0:bb348c97df44	5913	* This parameter must be a number between Min_Data = 192 and Max_Data = 432.
lypinator	0:bb348c97df44	5914	* @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
lypinator	0:bb348c97df44	5915	* output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
lypinator	0:bb348c97df44	5916	* @param __PLLI2SR__ specifies the division factor for I2S clock
lypinator	0:bb348c97df44	5917	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
lypinator	0:bb348c97df44	5918	* @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
lypinator	0:bb348c97df44	5919	* on the I2S clock frequency.
lypinator	0:bb348c97df44	5920	*/
lypinator	0:bb348c97df44	5921	#define __HAL_RCC_PLLI2S_I2SCLK_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SM__) \|\
lypinator	0:bb348c97df44	5922	((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos) \|\
lypinator	0:bb348c97df44	5923	((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos)))
lypinator	0:bb348c97df44	5924	#endif /* STM32F411xE */
lypinator	0:bb348c97df44	5925
lypinator	0:bb348c97df44	5926	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
lypinator	0:bb348c97df44	5927	/** @brief Macro used by the SAI HAL driver to configure the PLLI2S clock multiplication and division factors.
lypinator	0:bb348c97df44	5928	* @note This macro must be used only when the PLLI2S is disabled.
lypinator	0:bb348c97df44	5929	* @note PLLI2S clock source is common with the main PLL (configured in
lypinator	0:bb348c97df44	5930	* HAL_RCC_ClockConfig() API)
lypinator	0:bb348c97df44	5931	* @param __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock.
lypinator	0:bb348c97df44	5932	* This parameter must be a number between Min_Data = 50 and Max_Data = 432.
lypinator	0:bb348c97df44	5933	* @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
lypinator	0:bb348c97df44	5934	* output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
lypinator	0:bb348c97df44	5935	* @param __PLLI2SQ__ specifies the division factor for SAI1 clock.
lypinator	0:bb348c97df44	5936	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
lypinator	0:bb348c97df44	5937	* @note the PLLI2SQ parameter is only available with STM32F427xx/437xx/429xx/439xx/469xx/479xx
lypinator	0:bb348c97df44	5938	* Devices and can be configured using the __HAL_RCC_PLLI2S_PLLSAICLK_CONFIG() macro
lypinator	0:bb348c97df44	5939	* @param __PLLI2SR__ specifies the division factor for I2S clock
lypinator	0:bb348c97df44	5940	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
lypinator	0:bb348c97df44	5941	* @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
lypinator	0:bb348c97df44	5942	* on the I2S clock frequency.
lypinator	0:bb348c97df44	5943	*/
lypinator	0:bb348c97df44	5944	#define __HAL_RCC_PLLI2S_SAICLK_CONFIG(__PLLI2SN__, __PLLI2SQ__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SN__) << 6U) \|\
lypinator	0:bb348c97df44	5945	((__PLLI2SQ__) << 24U) \|\
lypinator	0:bb348c97df44	5946	((__PLLI2SR__) << 28U))
lypinator	0:bb348c97df44	5947	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
lypinator	0:bb348c97df44	5948	/----------------------------------------------------------------------------/
lypinator	0:bb348c97df44	5949
lypinator	0:bb348c97df44	5950	/------------------------------ PLLSAI Configuration ------------------------/
lypinator	0:bb348c97df44	5951	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
lypinator	0:bb348c97df44	5952	/** @brief Macros to Enable or Disable the PLLISAI.
lypinator	0:bb348c97df44	5953	* @note The PLLSAI is only available with STM32F429x/439x Devices.
lypinator	0:bb348c97df44	5954	* @note The PLLSAI is disabled by hardware when entering STOP and STANDBY modes.
lypinator	0:bb348c97df44	5955	*/
lypinator	0:bb348c97df44	5956	#define __HAL_RCC_PLLSAI_ENABLE() ((__IO uint32_t ) RCC_CR_PLLSAION_BB = ENABLE)
lypinator	0:bb348c97df44	5957	#define __HAL_RCC_PLLSAI_DISABLE() ((__IO uint32_t ) RCC_CR_PLLSAION_BB = DISABLE)
lypinator	0:bb348c97df44	5958
lypinator	0:bb348c97df44	5959	#if defined(STM32F446xx)
lypinator	0:bb348c97df44	5960	/** @brief Macro to configure the PLLSAI clock multiplication and division factors.
lypinator	0:bb348c97df44	5961	*
lypinator	0:bb348c97df44	5962	* @param __PLLSAIM__ specifies the division factor for PLLSAI VCO input clock
lypinator	0:bb348c97df44	5963	* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
lypinator	0:bb348c97df44	5964	* @note You have to set the PLLSAIM parameter correctly to ensure that the VCO input
lypinator	0:bb348c97df44	5965	* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
lypinator	0:bb348c97df44	5966	* of 1 MHz to limit PLLI2S jitter.
lypinator	0:bb348c97df44	5967	* @note The PLLSAIM parameter is only used with STM32F446xx Devices
lypinator	0:bb348c97df44	5968	*
lypinator	0:bb348c97df44	5969	* @param __PLLSAIN__ specifies the multiplication factor for PLLSAI VCO output clock.
lypinator	0:bb348c97df44	5970	* This parameter must be a number between Min_Data = 50 and Max_Data = 432.
lypinator	0:bb348c97df44	5971	* @note You have to set the PLLSAIN parameter correctly to ensure that the VCO
lypinator	0:bb348c97df44	5972	* output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
lypinator	0:bb348c97df44	5973	*
lypinator	0:bb348c97df44	5974	* @param __PLLSAIP__ specifies division factor for OTG FS, SDIO and RNG clocks.
lypinator	0:bb348c97df44	5975	* This parameter must be a number in the range {2, 4, 6, or 8}.
lypinator	0:bb348c97df44	5976	* @note the PLLSAIP parameter is only available with STM32F446xx Devices
lypinator	0:bb348c97df44	5977	*
lypinator	0:bb348c97df44	5978	* @param __PLLSAIQ__ specifies the division factor for SAI clock
lypinator	0:bb348c97df44	5979	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
lypinator	0:bb348c97df44	5980	*
lypinator	0:bb348c97df44	5981	* @param __PLLSAIR__ specifies the division factor for LTDC clock
lypinator	0:bb348c97df44	5982	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
lypinator	0:bb348c97df44	5983	* @note the PLLI2SR parameter is only available with STM32F427/437/429/439xx Devices
lypinator	0:bb348c97df44	5984	*/
lypinator	0:bb348c97df44	5985	#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIM__, __PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__) \
lypinator	0:bb348c97df44	5986	(RCC->PLLSAICFGR = ((__PLLSAIM__) \| \
lypinator	0:bb348c97df44	5987	((__PLLSAIN__) << RCC_PLLSAICFGR_PLLSAIN_Pos) \| \
lypinator	0:bb348c97df44	5988	((((__PLLSAIP__) >> 1U) -1U) << RCC_PLLSAICFGR_PLLSAIP_Pos) \| \
lypinator	0:bb348c97df44	5989	((__PLLSAIQ__) << RCC_PLLSAICFGR_PLLSAIQ_Pos)))
lypinator	0:bb348c97df44	5990	#endif /* STM32F446xx */
lypinator	0:bb348c97df44	5991
lypinator	0:bb348c97df44	5992	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
lypinator	0:bb348c97df44	5993	/** @brief Macro to configure the PLLSAI clock multiplication and division factors.
lypinator	0:bb348c97df44	5994	*
lypinator	0:bb348c97df44	5995	* @param __PLLSAIN__ specifies the multiplication factor for PLLSAI VCO output clock.
lypinator	0:bb348c97df44	5996	* This parameter must be a number between Min_Data = 50 and Max_Data = 432.
lypinator	0:bb348c97df44	5997	* @note You have to set the PLLSAIN parameter correctly to ensure that the VCO
lypinator	0:bb348c97df44	5998	* output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
lypinator	0:bb348c97df44	5999	*
lypinator	0:bb348c97df44	6000	* @param __PLLSAIP__ specifies division factor for SDIO and CLK48 clocks.
lypinator	0:bb348c97df44	6001	* This parameter must be a number in the range {2, 4, 6, or 8}.
lypinator	0:bb348c97df44	6002	*
lypinator	0:bb348c97df44	6003	* @param __PLLSAIQ__ specifies the division factor for SAI clock
lypinator	0:bb348c97df44	6004	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
lypinator	0:bb348c97df44	6005	*
lypinator	0:bb348c97df44	6006	* @param __PLLSAIR__ specifies the division factor for LTDC clock
lypinator	0:bb348c97df44	6007	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
lypinator	0:bb348c97df44	6008	*/
lypinator	0:bb348c97df44	6009	#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__) \
lypinator	0:bb348c97df44	6010	(RCC->PLLSAICFGR = (((__PLLSAIN__) << RCC_PLLSAICFGR_PLLSAIN_Pos) \|\
lypinator	0:bb348c97df44	6011	((((__PLLSAIP__) >> 1U) -1U) << RCC_PLLSAICFGR_PLLSAIP_Pos) \|\
lypinator	0:bb348c97df44	6012	((__PLLSAIQ__) << RCC_PLLSAICFGR_PLLSAIQ_Pos) \|\
lypinator	0:bb348c97df44	6013	((__PLLSAIR__) << RCC_PLLSAICFGR_PLLSAIR_Pos)))
lypinator	0:bb348c97df44	6014	#endif /* STM32F469xx \|\| STM32F479xx */
lypinator	0:bb348c97df44	6015
lypinator	0:bb348c97df44	6016	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
lypinator	0:bb348c97df44	6017	/** @brief Macro to configure the PLLSAI clock multiplication and division factors.
lypinator	0:bb348c97df44	6018	*
lypinator	0:bb348c97df44	6019	* @param __PLLSAIN__ specifies the multiplication factor for PLLSAI VCO output clock.
lypinator	0:bb348c97df44	6020	* This parameter must be a number between Min_Data = 50 and Max_Data = 432.
lypinator	0:bb348c97df44	6021	* @note You have to set the PLLSAIN parameter correctly to ensure that the VCO
lypinator	0:bb348c97df44	6022	* output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
lypinator	0:bb348c97df44	6023	*
lypinator	0:bb348c97df44	6024	* @param __PLLSAIQ__ specifies the division factor for SAI clock
lypinator	0:bb348c97df44	6025	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
lypinator	0:bb348c97df44	6026	*
lypinator	0:bb348c97df44	6027	* @param __PLLSAIR__ specifies the division factor for LTDC clock
lypinator	0:bb348c97df44	6028	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
lypinator	0:bb348c97df44	6029	* @note the PLLI2SR parameter is only available with STM32F427/437/429/439xx Devices
lypinator	0:bb348c97df44	6030	*/
lypinator	0:bb348c97df44	6031	#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIQ__, __PLLSAIR__) \
lypinator	0:bb348c97df44	6032	(RCC->PLLSAICFGR = (((__PLLSAIN__) << RCC_PLLSAICFGR_PLLSAIN_Pos) \| \
lypinator	0:bb348c97df44	6033	((__PLLSAIQ__) << RCC_PLLSAICFGR_PLLSAIQ_Pos) \| \
lypinator	0:bb348c97df44	6034	((__PLLSAIR__) << RCC_PLLSAICFGR_PLLSAIR_Pos)))
lypinator	0:bb348c97df44	6035	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
lypinator	0:bb348c97df44	6036
lypinator	0:bb348c97df44	6037	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
lypinator	0:bb348c97df44	6038	/----------------------------------------------------------------------------/
lypinator	0:bb348c97df44	6039
lypinator	0:bb348c97df44	6040	/------------------- PLLSAI/PLLI2S Dividers Configuration -------------------/
lypinator	0:bb348c97df44	6041	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
lypinator	0:bb348c97df44	6042	/** @brief Macro to configure the SAI clock Divider coming from PLLI2S.
lypinator	0:bb348c97df44	6043	* @note This function must be called before enabling the PLLI2S.
lypinator	0:bb348c97df44	6044	* @param __PLLI2SDivR__ specifies the PLLI2S division factor for SAI1 clock.
lypinator	0:bb348c97df44	6045	* This parameter must be a number between 1 and 32.
lypinator	0:bb348c97df44	6046	* SAI1 clock frequency = f(PLLI2SR) / __PLLI2SDivR__
lypinator	0:bb348c97df44	6047	*/
lypinator	0:bb348c97df44	6048	#define __HAL_RCC_PLLI2S_PLLSAICLKDIVR_CONFIG(__PLLI2SDivR__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVR, (__PLLI2SDivR__)-1U))
lypinator	0:bb348c97df44	6049
lypinator	0:bb348c97df44	6050	/** @brief Macro to configure the SAI clock Divider coming from PLL.
lypinator	0:bb348c97df44	6051	* @param __PLLDivR__ specifies the PLL division factor for SAI1 clock.
lypinator	0:bb348c97df44	6052	* This parameter must be a number between 1 and 32.
lypinator	0:bb348c97df44	6053	* SAI1 clock frequency = f(PLLR) / __PLLDivR__
lypinator	0:bb348c97df44	6054	*/
lypinator	0:bb348c97df44	6055	#define __HAL_RCC_PLL_PLLSAICLKDIVR_CONFIG(__PLLDivR__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLDIVR, ((__PLLDivR__)-1U)<<8U))
lypinator	0:bb348c97df44	6056	#endif /* STM32F413xx \|\| STM32F423xx */
lypinator	0:bb348c97df44	6057
lypinator	0:bb348c97df44	6058	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F446xx) \|\|\
lypinator	0:bb348c97df44	6059	defined(STM32F469xx) \|\| defined(STM32F479xx)
lypinator	0:bb348c97df44	6060	/** @brief Macro to configure the SAI clock Divider coming from PLLI2S.
lypinator	0:bb348c97df44	6061	* @note This function must be called before enabling the PLLI2S.
lypinator	0:bb348c97df44	6062	* @param __PLLI2SDivQ__ specifies the PLLI2S division factor for SAI1 clock.
lypinator	0:bb348c97df44	6063	* This parameter must be a number between 1 and 32.
lypinator	0:bb348c97df44	6064	* SAI1 clock frequency = f(PLLI2SQ) / __PLLI2SDivQ__
lypinator	0:bb348c97df44	6065	*/
lypinator	0:bb348c97df44	6066	#define __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(__PLLI2SDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVQ, (__PLLI2SDivQ__)-1U))
lypinator	0:bb348c97df44	6067
lypinator	0:bb348c97df44	6068	/** @brief Macro to configure the SAI clock Divider coming from PLLSAI.
lypinator	0:bb348c97df44	6069	* @note This function must be called before enabling the PLLSAI.
lypinator	0:bb348c97df44	6070	* @param __PLLSAIDivQ__ specifies the PLLSAI division factor for SAI1 clock .
lypinator	0:bb348c97df44	6071	* This parameter must be a number between Min_Data = 1 and Max_Data = 32.
lypinator	0:bb348c97df44	6072	* SAI1 clock frequency = f(PLLSAIQ) / __PLLSAIDivQ__
lypinator	0:bb348c97df44	6073	*/
lypinator	0:bb348c97df44	6074	#define __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(__PLLSAIDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVQ, ((__PLLSAIDivQ__)-1U)<<8U))
lypinator	0:bb348c97df44	6075	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
lypinator	0:bb348c97df44	6076
lypinator	0:bb348c97df44	6077	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
lypinator	0:bb348c97df44	6078	/** @brief Macro to configure the LTDC clock Divider coming from PLLSAI.
lypinator	0:bb348c97df44	6079	*
lypinator	0:bb348c97df44	6080	* @note The LTDC peripheral is only available with STM32F427/437/429/439/469/479xx Devices.
lypinator	0:bb348c97df44	6081	* @note This function must be called before enabling the PLLSAI.
lypinator	0:bb348c97df44	6082	* @param __PLLSAIDivR__ specifies the PLLSAI division factor for LTDC clock .
lypinator	0:bb348c97df44	6083	* This parameter must be a number between Min_Data = 2 and Max_Data = 16.
lypinator	0:bb348c97df44	6084	* LTDC clock frequency = f(PLLSAIR) / __PLLSAIDivR__
lypinator	0:bb348c97df44	6085	*/
lypinator	0:bb348c97df44	6086	#define __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(__PLLSAIDivR__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVR, (__PLLSAIDivR__)))
lypinator	0:bb348c97df44	6087	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
lypinator	0:bb348c97df44	6088	/----------------------------------------------------------------------------/
lypinator	0:bb348c97df44	6089
lypinator	0:bb348c97df44	6090	/------------------------- Peripheral Clock selection -----------------------/
lypinator	0:bb348c97df44	6091	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\|\
lypinator	0:bb348c97df44	6092	defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\|\
lypinator	0:bb348c97df44	6093	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE) \|\| defined(STM32F469xx) \|\|\
lypinator	0:bb348c97df44	6094	defined(STM32F479xx)
lypinator	0:bb348c97df44	6095	/** @brief Macro to configure the I2S clock source (I2SCLK).
lypinator	0:bb348c97df44	6096	* @note This function must be called before enabling the I2S APB clock.
lypinator	0:bb348c97df44	6097	* @param __SOURCE__ specifies the I2S clock source.
lypinator	0:bb348c97df44	6098	* This parameter can be one of the following values:
lypinator	0:bb348c97df44	6099	* @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S clock used as I2S clock source.
lypinator	0:bb348c97df44	6100	* @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin
lypinator	0:bb348c97df44	6101	* used as I2S clock source.
lypinator	0:bb348c97df44	6102	*/
lypinator	0:bb348c97df44	6103	#define __HAL_RCC_I2S_CONFIG(__SOURCE__) ((__IO uint32_t ) RCC_CFGR_I2SSRC_BB = (__SOURCE__))
lypinator	0:bb348c97df44	6104
lypinator	0:bb348c97df44	6105
lypinator	0:bb348c97df44	6106	/** @brief Macro to get the I2S clock source (I2SCLK).
lypinator	0:bb348c97df44	6107	* @retval The clock source can be one of the following values:
lypinator	0:bb348c97df44	6108	* @arg @ref RCC_I2SCLKSOURCE_PLLI2S: PLLI2S clock used as I2S clock source.
lypinator	0:bb348c97df44	6109	* @arg @ref RCC_I2SCLKSOURCE_EXT External clock mapped on the I2S_CKIN pin
lypinator	0:bb348c97df44	6110	* used as I2S clock source
lypinator	0:bb348c97df44	6111	*/
lypinator	0:bb348c97df44	6112	#define __HAL_RCC_GET_I2S_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_I2SSRC)))
lypinator	0:bb348c97df44	6113	#endif /* STM32F40xxx \|\| STM32F41xxx \|\| STM32F42xxx \|\| STM32F43xxx \|\| STM32F469xx \|\| STM32F479xx */
lypinator	0:bb348c97df44	6114
lypinator	0:bb348c97df44	6115	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
lypinator	0:bb348c97df44	6116
lypinator	0:bb348c97df44	6117	/** @brief Macro to configure SAI1BlockA clock source selection.
lypinator	0:bb348c97df44	6118	* @note The SAI peripheral is only available with STM32F427/437/429/439/469/479xx Devices.
lypinator	0:bb348c97df44	6119	* @note This function must be called before enabling PLLSAI, PLLI2S and
lypinator	0:bb348c97df44	6120	* the SAI clock.
lypinator	0:bb348c97df44	6121	* @param __SOURCE__ specifies the SAI Block A clock source.
lypinator	0:bb348c97df44	6122	* This parameter can be one of the following values:
lypinator	0:bb348c97df44	6123	* @arg RCC_SAIACLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
lypinator	0:bb348c97df44	6124	* as SAI1 Block A clock.
lypinator	0:bb348c97df44	6125	* @arg RCC_SAIACLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
lypinator	0:bb348c97df44	6126	* as SAI1 Block A clock.
lypinator	0:bb348c97df44	6127	* @arg RCC_SAIACLKSOURCE_Ext: External clock mapped on the I2S_CKIN pin
lypinator	0:bb348c97df44	6128	* used as SAI1 Block A clock.
lypinator	0:bb348c97df44	6129	*/
lypinator	0:bb348c97df44	6130	#define __HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1ASRC, (__SOURCE__)))
lypinator	0:bb348c97df44	6131
lypinator	0:bb348c97df44	6132	/** @brief Macro to configure SAI1BlockB clock source selection.
lypinator	0:bb348c97df44	6133	* @note The SAI peripheral is only available with STM32F427/437/429/439/469/479xx Devices.
lypinator	0:bb348c97df44	6134	* @note This function must be called before enabling PLLSAI, PLLI2S and
lypinator	0:bb348c97df44	6135	* the SAI clock.
lypinator	0:bb348c97df44	6136	* @param __SOURCE__ specifies the SAI Block B clock source.
lypinator	0:bb348c97df44	6137	* This parameter can be one of the following values:
lypinator	0:bb348c97df44	6138	* @arg RCC_SAIBCLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
lypinator	0:bb348c97df44	6139	* as SAI1 Block B clock.
lypinator	0:bb348c97df44	6140	* @arg RCC_SAIBCLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
lypinator	0:bb348c97df44	6141	* as SAI1 Block B clock.
lypinator	0:bb348c97df44	6142	* @arg RCC_SAIBCLKSOURCE_Ext: External clock mapped on the I2S_CKIN pin
lypinator	0:bb348c97df44	6143	* used as SAI1 Block B clock.
lypinator	0:bb348c97df44	6144	*/
lypinator	0:bb348c97df44	6145	#define __HAL_RCC_SAI_BLOCKBCLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1BSRC, (__SOURCE__)))
lypinator	0:bb348c97df44	6146	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
lypinator	0:bb348c97df44	6147
lypinator	0:bb348c97df44	6148	#if defined(STM32F446xx)
lypinator	0:bb348c97df44	6149	/** @brief Macro to configure SAI1 clock source selection.
lypinator	0:bb348c97df44	6150	* @note This configuration is only available with STM32F446xx Devices.
lypinator	0:bb348c97df44	6151	* @note This function must be called before enabling PLL, PLLSAI, PLLI2S and
lypinator	0:bb348c97df44	6152	* the SAI clock.
lypinator	0:bb348c97df44	6153	* @param __SOURCE__ specifies the SAI1 clock source.
lypinator	0:bb348c97df44	6154	* This parameter can be one of the following values:
lypinator	0:bb348c97df44	6155	* @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI1 clock.
lypinator	0:bb348c97df44	6156	* @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI1 clock.
lypinator	0:bb348c97df44	6157	* @arg RCC_SAI1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock.
lypinator	0:bb348c97df44	6158	* @arg RCC_SAI1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock.
lypinator	0:bb348c97df44	6159	*/
lypinator	0:bb348c97df44	6160	#define __HAL_RCC_SAI1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1SRC, (__SOURCE__)))
lypinator	0:bb348c97df44	6161
lypinator	0:bb348c97df44	6162	/** @brief Macro to Get SAI1 clock source selection.
lypinator	0:bb348c97df44	6163	* @note This configuration is only available with STM32F446xx Devices.
lypinator	0:bb348c97df44	6164	* @retval The clock source can be one of the following values:
lypinator	0:bb348c97df44	6165	* @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI1 clock.
lypinator	0:bb348c97df44	6166	* @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI1 clock.
lypinator	0:bb348c97df44	6167	* @arg RCC_SAI1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock.
lypinator	0:bb348c97df44	6168	* @arg RCC_SAI1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock.
lypinator	0:bb348c97df44	6169	*/
lypinator	0:bb348c97df44	6170	#define __HAL_RCC_GET_SAI1_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI1SRC))
lypinator	0:bb348c97df44	6171
lypinator	0:bb348c97df44	6172	/** @brief Macro to configure SAI2 clock source selection.
lypinator	0:bb348c97df44	6173	* @note This configuration is only available with STM32F446xx Devices.
lypinator	0:bb348c97df44	6174	* @note This function must be called before enabling PLL, PLLSAI, PLLI2S and
lypinator	0:bb348c97df44	6175	* the SAI clock.
lypinator	0:bb348c97df44	6176	* @param __SOURCE__ specifies the SAI2 clock source.
lypinator	0:bb348c97df44	6177	* This parameter can be one of the following values:
lypinator	0:bb348c97df44	6178	* @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI2 clock.
lypinator	0:bb348c97df44	6179	* @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI2 clock.
lypinator	0:bb348c97df44	6180	* @arg RCC_SAI2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI2 clock.
lypinator	0:bb348c97df44	6181	* @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock used as SAI2 clock.
lypinator	0:bb348c97df44	6182	*/
lypinator	0:bb348c97df44	6183	#define __HAL_RCC_SAI2_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI2SRC, (__SOURCE__)))
lypinator	0:bb348c97df44	6184
lypinator	0:bb348c97df44	6185	/** @brief Macro to Get SAI2 clock source selection.
lypinator	0:bb348c97df44	6186	* @note This configuration is only available with STM32F446xx Devices.
lypinator	0:bb348c97df44	6187	* @retval The clock source can be one of the following values:
lypinator	0:bb348c97df44	6188	* @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI2 clock.
lypinator	0:bb348c97df44	6189	* @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI2 clock.
lypinator	0:bb348c97df44	6190	* @arg RCC_SAI2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI2 clock.
lypinator	0:bb348c97df44	6191	* @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock used as SAI2 clock.
lypinator	0:bb348c97df44	6192	*/
lypinator	0:bb348c97df44	6193	#define __HAL_RCC_GET_SAI2_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI2SRC))
lypinator	0:bb348c97df44	6194
lypinator	0:bb348c97df44	6195	/** @brief Macro to configure I2S APB1 clock source selection.
lypinator	0:bb348c97df44	6196	* @note This function must be called before enabling PLL, PLLI2S and the I2S clock.
lypinator	0:bb348c97df44	6197	* @param __SOURCE__ specifies the I2S APB1 clock source.
lypinator	0:bb348c97df44	6198	* This parameter can be one of the following values:
lypinator	0:bb348c97df44	6199	* @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock.
lypinator	0:bb348c97df44	6200	* @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S APB1 clock.
lypinator	0:bb348c97df44	6201	* @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as I2S APB1 clock.
lypinator	0:bb348c97df44	6202	* @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
lypinator	0:bb348c97df44	6203	*/
lypinator	0:bb348c97df44	6204	#define __HAL_RCC_I2S_APB1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC, (__SOURCE__)))
lypinator	0:bb348c97df44	6205
lypinator	0:bb348c97df44	6206	/** @brief Macro to Get I2S APB1 clock source selection.
lypinator	0:bb348c97df44	6207	* @retval The clock source can be one of the following values:
lypinator	0:bb348c97df44	6208	* @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock.
lypinator	0:bb348c97df44	6209	* @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S APB1 clock.
lypinator	0:bb348c97df44	6210	* @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as I2S APB1 clock.
lypinator	0:bb348c97df44	6211	* @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
lypinator	0:bb348c97df44	6212	*/
lypinator	0:bb348c97df44	6213	#define __HAL_RCC_GET_I2S_APB1_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC))
lypinator	0:bb348c97df44	6214
lypinator	0:bb348c97df44	6215	/** @brief Macro to configure I2S APB2 clock source selection.
lypinator	0:bb348c97df44	6216	* @note This function must be called before enabling PLL, PLLI2S and the I2S clock.
lypinator	0:bb348c97df44	6217	* @param __SOURCE__ specifies the SAI Block A clock source.
lypinator	0:bb348c97df44	6218	* This parameter can be one of the following values:
lypinator	0:bb348c97df44	6219	* @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock.
lypinator	0:bb348c97df44	6220	* @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S APB2 clock.
lypinator	0:bb348c97df44	6221	* @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as I2S APB2 clock.
lypinator	0:bb348c97df44	6222	* @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
lypinator	0:bb348c97df44	6223	*/
lypinator	0:bb348c97df44	6224	#define __HAL_RCC_I2S_APB2_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC, (__SOURCE__)))
lypinator	0:bb348c97df44	6225
lypinator	0:bb348c97df44	6226	/** @brief Macro to Get I2S APB2 clock source selection.
lypinator	0:bb348c97df44	6227	* @retval The clock source can be one of the following values:
lypinator	0:bb348c97df44	6228	* @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock.
lypinator	0:bb348c97df44	6229	* @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S APB2 clock.
lypinator	0:bb348c97df44	6230	* @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as I2S APB2 clock.
lypinator	0:bb348c97df44	6231	* @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
lypinator	0:bb348c97df44	6232	*/
lypinator	0:bb348c97df44	6233	#define __HAL_RCC_GET_I2S_APB2_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC))
lypinator	0:bb348c97df44	6234
lypinator	0:bb348c97df44	6235	/** @brief Macro to configure the CEC clock.
lypinator	0:bb348c97df44	6236	* @param __SOURCE__ specifies the CEC clock source.
lypinator	0:bb348c97df44	6237	* This parameter can be one of the following values:
lypinator	0:bb348c97df44	6238	* @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock
lypinator	0:bb348c97df44	6239	* @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
lypinator	0:bb348c97df44	6240	*/
lypinator	0:bb348c97df44	6241	#define __HAL_RCC_CEC_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, (uint32_t)(__SOURCE__)))
lypinator	0:bb348c97df44	6242
lypinator	0:bb348c97df44	6243	/** @brief Macro to Get the CEC clock.
lypinator	0:bb348c97df44	6244	* @retval The clock source can be one of the following values:
lypinator	0:bb348c97df44	6245	* @arg RCC_CECCLKSOURCE_HSI488: HSI selected as CEC clock
lypinator	0:bb348c97df44	6246	* @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
lypinator	0:bb348c97df44	6247	*/
lypinator	0:bb348c97df44	6248	#define __HAL_RCC_GET_CEC_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL))
lypinator	0:bb348c97df44	6249
lypinator	0:bb348c97df44	6250	/** @brief Macro to configure the FMPI2C1 clock.
lypinator	0:bb348c97df44	6251	* @param __SOURCE__ specifies the FMPI2C1 clock source.
lypinator	0:bb348c97df44	6252	* This parameter can be one of the following values:
lypinator	0:bb348c97df44	6253	* @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock
lypinator	0:bb348c97df44	6254	* @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock
lypinator	0:bb348c97df44	6255	* @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock
lypinator	0:bb348c97df44	6256	*/
lypinator	0:bb348c97df44	6257	#define __HAL_RCC_FMPI2C1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, (uint32_t)(__SOURCE__)))
lypinator	0:bb348c97df44	6258
lypinator	0:bb348c97df44	6259	/** @brief Macro to Get the FMPI2C1 clock.
lypinator	0:bb348c97df44	6260	* @retval The clock source can be one of the following values:
lypinator	0:bb348c97df44	6261	* @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock
lypinator	0:bb348c97df44	6262	* @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock
lypinator	0:bb348c97df44	6263	* @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock
lypinator	0:bb348c97df44	6264	*/
lypinator	0:bb348c97df44	6265	#define __HAL_RCC_GET_FMPI2C1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL))
lypinator	0:bb348c97df44	6266
lypinator	0:bb348c97df44	6267	/** @brief Macro to configure the CLK48 clock.
lypinator	0:bb348c97df44	6268	* @param __SOURCE__ specifies the CLK48 clock source.
lypinator	0:bb348c97df44	6269	* This parameter can be one of the following values:
lypinator	0:bb348c97df44	6270	* @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock.
lypinator	0:bb348c97df44	6271	* @arg RCC_CLK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CLK48 clock.
lypinator	0:bb348c97df44	6272	*/
lypinator	0:bb348c97df44	6273	#define __HAL_RCC_CLK48_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, (uint32_t)(__SOURCE__)))
lypinator	0:bb348c97df44	6274
lypinator	0:bb348c97df44	6275	/** @brief Macro to Get the CLK48 clock.
lypinator	0:bb348c97df44	6276	* @retval The clock source can be one of the following values:
lypinator	0:bb348c97df44	6277	* @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock.
lypinator	0:bb348c97df44	6278	* @arg RCC_CLK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CLK48 clock.
lypinator	0:bb348c97df44	6279	*/
lypinator	0:bb348c97df44	6280	#define __HAL_RCC_GET_CLK48_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL))
lypinator	0:bb348c97df44	6281
lypinator	0:bb348c97df44	6282	/** @brief Macro to configure the SDIO clock.
lypinator	0:bb348c97df44	6283	* @param __SOURCE__ specifies the SDIO clock source.
lypinator	0:bb348c97df44	6284	* This parameter can be one of the following values:
lypinator	0:bb348c97df44	6285	* @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock.
lypinator	0:bb348c97df44	6286	* @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock.
lypinator	0:bb348c97df44	6287	*/
lypinator	0:bb348c97df44	6288	#define __HAL_RCC_SDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL, (uint32_t)(__SOURCE__)))
lypinator	0:bb348c97df44	6289
lypinator	0:bb348c97df44	6290	/** @brief Macro to Get the SDIO clock.
lypinator	0:bb348c97df44	6291	* @retval The clock source can be one of the following values:
lypinator	0:bb348c97df44	6292	* @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock.
lypinator	0:bb348c97df44	6293	* @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock.
lypinator	0:bb348c97df44	6294	*/
lypinator	0:bb348c97df44	6295	#define __HAL_RCC_GET_SDIO_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL))
lypinator	0:bb348c97df44	6296
lypinator	0:bb348c97df44	6297	/** @brief Macro to configure the SPDIFRX clock.
lypinator	0:bb348c97df44	6298	* @param __SOURCE__ specifies the SPDIFRX clock source.
lypinator	0:bb348c97df44	6299	* This parameter can be one of the following values:
lypinator	0:bb348c97df44	6300	* @arg RCC_SPDIFRXCLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SPDIFRX clock.
lypinator	0:bb348c97df44	6301	* @arg RCC_SPDIFRXCLKSOURCE_PLLI2SP: PLLI2S VCO Output divided by PLLI2SP used as SPDIFRX clock.
lypinator	0:bb348c97df44	6302	*/
lypinator	0:bb348c97df44	6303	#define __HAL_RCC_SPDIFRX_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL, (uint32_t)(__SOURCE__)))
lypinator	0:bb348c97df44	6304
lypinator	0:bb348c97df44	6305	/** @brief Macro to Get the SPDIFRX clock.
lypinator	0:bb348c97df44	6306	* @retval The clock source can be one of the following values:
lypinator	0:bb348c97df44	6307	* @arg RCC_SPDIFRXCLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SPDIFRX clock.
lypinator	0:bb348c97df44	6308	* @arg RCC_SPDIFRXCLKSOURCE_PLLI2SP: PLLI2S VCO Output divided by PLLI2SP used as SPDIFRX clock.
lypinator	0:bb348c97df44	6309	*/
lypinator	0:bb348c97df44	6310	#define __HAL_RCC_GET_SPDIFRX_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL))
lypinator	0:bb348c97df44	6311	#endif /* STM32F446xx */
lypinator	0:bb348c97df44	6312
lypinator	0:bb348c97df44	6313	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
lypinator	0:bb348c97df44	6314
lypinator	0:bb348c97df44	6315	/** @brief Macro to configure the CLK48 clock.
lypinator	0:bb348c97df44	6316	* @param __SOURCE__ specifies the CLK48 clock source.
lypinator	0:bb348c97df44	6317	* This parameter can be one of the following values:
lypinator	0:bb348c97df44	6318	* @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock.
lypinator	0:bb348c97df44	6319	* @arg RCC_CLK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CLK48 clock.
lypinator	0:bb348c97df44	6320	*/
lypinator	0:bb348c97df44	6321	#define __HAL_RCC_CLK48_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL, (uint32_t)(__SOURCE__)))
lypinator	0:bb348c97df44	6322
lypinator	0:bb348c97df44	6323	/** @brief Macro to Get the CLK48 clock.
lypinator	0:bb348c97df44	6324	* @retval The clock source can be one of the following values:
lypinator	0:bb348c97df44	6325	* @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock.
lypinator	0:bb348c97df44	6326	* @arg RCC_CLK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CLK48 clock.
lypinator	0:bb348c97df44	6327	*/
lypinator	0:bb348c97df44	6328	#define __HAL_RCC_GET_CLK48_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL))
lypinator	0:bb348c97df44	6329
lypinator	0:bb348c97df44	6330	/** @brief Macro to configure the SDIO clock.
lypinator	0:bb348c97df44	6331	* @param __SOURCE__ specifies the SDIO clock source.
lypinator	0:bb348c97df44	6332	* This parameter can be one of the following values:
lypinator	0:bb348c97df44	6333	* @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock.
lypinator	0:bb348c97df44	6334	* @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock.
lypinator	0:bb348c97df44	6335	*/
lypinator	0:bb348c97df44	6336	#define __HAL_RCC_SDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SDIOSEL, (uint32_t)(__SOURCE__)))
lypinator	0:bb348c97df44	6337
lypinator	0:bb348c97df44	6338	/** @brief Macro to Get the SDIO clock.
lypinator	0:bb348c97df44	6339	* @retval The clock source can be one of the following values:
lypinator	0:bb348c97df44	6340	* @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock.
lypinator	0:bb348c97df44	6341	* @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock.
lypinator	0:bb348c97df44	6342	*/
lypinator	0:bb348c97df44	6343	#define __HAL_RCC_GET_SDIO_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SDIOSEL))
lypinator	0:bb348c97df44	6344
lypinator	0:bb348c97df44	6345	/** @brief Macro to configure the DSI clock.
lypinator	0:bb348c97df44	6346	* @param __SOURCE__ specifies the DSI clock source.
lypinator	0:bb348c97df44	6347	* This parameter can be one of the following values:
lypinator	0:bb348c97df44	6348	* @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock.
lypinator	0:bb348c97df44	6349	* @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock.
lypinator	0:bb348c97df44	6350	*/
lypinator	0:bb348c97df44	6351	#define __HAL_RCC_DSI_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_DSISEL, (uint32_t)(__SOURCE__)))
lypinator	0:bb348c97df44	6352
lypinator	0:bb348c97df44	6353	/** @brief Macro to Get the DSI clock.
lypinator	0:bb348c97df44	6354	* @retval The clock source can be one of the following values:
lypinator	0:bb348c97df44	6355	* @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock.
lypinator	0:bb348c97df44	6356	* @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock.
lypinator	0:bb348c97df44	6357	*/
lypinator	0:bb348c97df44	6358	#define __HAL_RCC_GET_DSI_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_DSISEL))
lypinator	0:bb348c97df44	6359
lypinator	0:bb348c97df44	6360	#endif /* STM32F469xx \|\| STM32F479xx */
lypinator	0:bb348c97df44	6361
lypinator	0:bb348c97df44	6362	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx) \|\|\
lypinator	0:bb348c97df44	6363	defined(STM32F413xx) \|\| defined(STM32F423xx)
lypinator	0:bb348c97df44	6364	/** @brief Macro to configure the DFSDM1 clock.
lypinator	0:bb348c97df44	6365	* @param __DFSDM1_CLKSOURCE__ specifies the DFSDM1 clock source.
lypinator	0:bb348c97df44	6366	* This parameter can be one of the following values:
lypinator	0:bb348c97df44	6367	* @arg RCC_DFSDM1CLKSOURCE_PCLK2: PCLK2 clock used as kernel clock.
lypinator	0:bb348c97df44	6368	* @arg RCC_DFSDM1CLKSOURCE_SYSCLK: System clock used as kernal clock.
lypinator	0:bb348c97df44	6369	* @retval None
lypinator	0:bb348c97df44	6370	*/
lypinator	0:bb348c97df44	6371	#define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1_CLKSOURCE__) MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL, (__DFSDM1_CLKSOURCE__))
lypinator	0:bb348c97df44	6372
lypinator	0:bb348c97df44	6373	/** @brief Macro to get the DFSDM1 clock source.
lypinator	0:bb348c97df44	6374	* @retval The clock source can be one of the following values:
lypinator	0:bb348c97df44	6375	* @arg RCC_DFSDM1CLKSOURCE_PCLK2: PCLK2 clock used as kernel clock.
lypinator	0:bb348c97df44	6376	* @arg RCC_DFSDM1CLKSOURCE_SYSCLK: System clock used as kernal clock.
lypinator	0:bb348c97df44	6377	*/
lypinator	0:bb348c97df44	6378	#define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL)))
lypinator	0:bb348c97df44	6379
lypinator	0:bb348c97df44	6380	/** @brief Macro to configure DFSDM1 Audio clock source selection.
lypinator	0:bb348c97df44	6381	* @note This configuration is only available with STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx/
lypinator	0:bb348c97df44	6382	STM32F413xx/STM32F423xx Devices.
lypinator	0:bb348c97df44	6383	* @param __SOURCE__ specifies the DFSDM1 Audio clock source.
lypinator	0:bb348c97df44	6384	* This parameter can be one of the following values:
lypinator	0:bb348c97df44	6385	* @arg RCC_DFSDM1AUDIOCLKSOURCE_I2S1: CK_I2S_PCLK1 selected as audio clock
lypinator	0:bb348c97df44	6386	* @arg RCC_DFSDM1AUDIOCLKSOURCE_I2S2: CK_I2S_PCLK2 selected as audio clock
lypinator	0:bb348c97df44	6387	*/
lypinator	0:bb348c97df44	6388	#define __HAL_RCC_DFSDM1AUDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1ASEL, (__SOURCE__)))
lypinator	0:bb348c97df44	6389
lypinator	0:bb348c97df44	6390	/** @brief Macro to Get DFSDM1 Audio clock source selection.
lypinator	0:bb348c97df44	6391	* @note This configuration is only available with STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx/
lypinator	0:bb348c97df44	6392	STM32F413xx/STM32F423xx Devices.
lypinator	0:bb348c97df44	6393	* @retval The clock source can be one of the following values:
lypinator	0:bb348c97df44	6394	* @arg RCC_DFSDM1AUDIOCLKSOURCE_I2S1: CK_I2S_PCLK1 selected as audio clock
lypinator	0:bb348c97df44	6395	* @arg RCC_DFSDM1AUDIOCLKSOURCE_I2S2: CK_I2S_PCLK2 selected as audio clock
lypinator	0:bb348c97df44	6396	*/
lypinator	0:bb348c97df44	6397	#define __HAL_RCC_GET_DFSDM1AUDIO_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1ASEL))
lypinator	0:bb348c97df44	6398
lypinator	0:bb348c97df44	6399	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
lypinator	0:bb348c97df44	6400	/** @brief Macro to configure the DFSDM2 clock.
lypinator	0:bb348c97df44	6401	* @param __DFSDM2_CLKSOURCE__ specifies the DFSDM1 clock source.
lypinator	0:bb348c97df44	6402	* This parameter can be one of the following values:
lypinator	0:bb348c97df44	6403	* @arg RCC_DFSDM2CLKSOURCE_PCLK2: PCLK2 clock used as kernel clock.
lypinator	0:bb348c97df44	6404	* @arg RCC_DFSDM2CLKSOURCE_SYSCLK: System clock used as kernal clock.
lypinator	0:bb348c97df44	6405	* @retval None
lypinator	0:bb348c97df44	6406	*/
lypinator	0:bb348c97df44	6407	#define __HAL_RCC_DFSDM2_CONFIG(__DFSDM2_CLKSOURCE__) MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL, (__DFSDM2_CLKSOURCE__))
lypinator	0:bb348c97df44	6408
lypinator	0:bb348c97df44	6409	/** @brief Macro to get the DFSDM2 clock source.
lypinator	0:bb348c97df44	6410	* @retval The clock source can be one of the following values:
lypinator	0:bb348c97df44	6411	* @arg RCC_DFSDM2CLKSOURCE_PCLK2: PCLK2 clock used as kernel clock.
lypinator	0:bb348c97df44	6412	* @arg RCC_DFSDM2CLKSOURCE_SYSCLK: System clock used as kernal clock.
lypinator	0:bb348c97df44	6413	*/
lypinator	0:bb348c97df44	6414	#define __HAL_RCC_GET_DFSDM2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL)))
lypinator	0:bb348c97df44	6415
lypinator	0:bb348c97df44	6416	/** @brief Macro to configure DFSDM1 Audio clock source selection.
lypinator	0:bb348c97df44	6417	* @note This configuration is only available with STM32F413xx/STM32F423xx Devices.
lypinator	0:bb348c97df44	6418	* @param __SOURCE__ specifies the DFSDM2 Audio clock source.
lypinator	0:bb348c97df44	6419	* This parameter can be one of the following values:
lypinator	0:bb348c97df44	6420	* @arg RCC_DFSDM2AUDIOCLKSOURCE_I2S1: CK_I2S_PCLK1 selected as audio clock
lypinator	0:bb348c97df44	6421	* @arg RCC_DFSDM2AUDIOCLKSOURCE_I2S2: CK_I2S_PCLK2 selected as audio clock
lypinator	0:bb348c97df44	6422	*/
lypinator	0:bb348c97df44	6423	#define __HAL_RCC_DFSDM2AUDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM2ASEL, (__SOURCE__)))
lypinator	0:bb348c97df44	6424
lypinator	0:bb348c97df44	6425	/** @brief Macro to Get DFSDM2 Audio clock source selection.
lypinator	0:bb348c97df44	6426	* @note This configuration is only available with STM32F413xx/STM32F423xx Devices.
lypinator	0:bb348c97df44	6427	* @retval The clock source can be one of the following values:
lypinator	0:bb348c97df44	6428	* @arg RCC_DFSDM2AUDIOCLKSOURCE_I2S1: CK_I2S_PCLK1 selected as audio clock
lypinator	0:bb348c97df44	6429	* @arg RCC_DFSDM2AUDIOCLKSOURCE_I2S2: CK_I2S_PCLK2 selected as audio clock
lypinator	0:bb348c97df44	6430	*/
lypinator	0:bb348c97df44	6431	#define __HAL_RCC_GET_DFSDM2AUDIO_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM2ASEL))
lypinator	0:bb348c97df44	6432
lypinator	0:bb348c97df44	6433	/** @brief Macro to configure SAI1BlockA clock source selection.
lypinator	0:bb348c97df44	6434	* @note The SAI peripheral is only available with STM32F413xx/STM32F423xx Devices.
lypinator	0:bb348c97df44	6435	* @note This function must be called before enabling PLLSAI, PLLI2S and
lypinator	0:bb348c97df44	6436	* the SAI clock.
lypinator	0:bb348c97df44	6437	* @param __SOURCE__ specifies the SAI Block A clock source.
lypinator	0:bb348c97df44	6438	* This parameter can be one of the following values:
lypinator	0:bb348c97df44	6439	* @arg RCC_SAIACLKSOURCE_PLLI2SR: PLLI2S_R clock divided (R2) used as SAI1 Block A clock.
lypinator	0:bb348c97df44	6440	* @arg RCC_SAIACLKSOURCE_EXT: External clock mapped on the I2S_CKIN pinused as SAI1 Block A clock.
lypinator	0:bb348c97df44	6441	* @arg RCC_SAIACLKSOURCE_PLLR: PLL_R clock divided (R1) used as SAI1 Block A clock.
lypinator	0:bb348c97df44	6442	* @arg RCC_SAIACLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
lypinator	0:bb348c97df44	6443	*/
lypinator	0:bb348c97df44	6444	#define __HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1ASRC, (__SOURCE__)))
lypinator	0:bb348c97df44	6445
lypinator	0:bb348c97df44	6446	/** @brief Macro to Get SAI1 BlockA clock source selection.
lypinator	0:bb348c97df44	6447	* @note This configuration is only available with STM32F413xx/STM32F423xx Devices.
lypinator	0:bb348c97df44	6448	* @retval The clock source can be one of the following values:
lypinator	0:bb348c97df44	6449	* @arg RCC_SAIACLKSOURCE_PLLI2SR: PLLI2S_R clock divided (R2) used as SAI1 Block A clock.
lypinator	0:bb348c97df44	6450	* @arg RCC_SAIACLKSOURCE_EXT: External clock mapped on the I2S_CKIN pinused as SAI1 Block A clock.
lypinator	0:bb348c97df44	6451	* @arg RCC_SAIACLKSOURCE_PLLR: PLL_R clock divided (R1) used as SAI1 Block A clock.
lypinator	0:bb348c97df44	6452	* @arg RCC_SAIACLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
lypinator	0:bb348c97df44	6453	*/
lypinator	0:bb348c97df44	6454	#define __HAL_RCC_GET_SAI_BLOCKA_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI1ASRC))
lypinator	0:bb348c97df44	6455
lypinator	0:bb348c97df44	6456	/** @brief Macro to configure SAI1 BlockB clock source selection.
lypinator	0:bb348c97df44	6457	* @note The SAI peripheral is only available with STM32F413xx/STM32F423xx Devices.
lypinator	0:bb348c97df44	6458	* @note This function must be called before enabling PLLSAI, PLLI2S and
lypinator	0:bb348c97df44	6459	* the SAI clock.
lypinator	0:bb348c97df44	6460	* @param __SOURCE__ specifies the SAI Block B clock source.
lypinator	0:bb348c97df44	6461	* This parameter can be one of the following values:
lypinator	0:bb348c97df44	6462	* @arg RCC_SAIBCLKSOURCE_PLLI2SR: PLLI2S_R clock divided (R2) used as SAI1 Block A clock.
lypinator	0:bb348c97df44	6463	* @arg RCC_SAIBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 Block A clock.
lypinator	0:bb348c97df44	6464	* @arg RCC_SAIBCLKSOURCE_PLLR: PLL_R clock divided (R1) used as SAI1 Block A clock.
lypinator	0:bb348c97df44	6465	* @arg RCC_SAIBCLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
lypinator	0:bb348c97df44	6466	*/
lypinator	0:bb348c97df44	6467	#define __HAL_RCC_SAI_BLOCKBCLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1BSRC, (__SOURCE__)))
lypinator	0:bb348c97df44	6468
lypinator	0:bb348c97df44	6469	/** @brief Macro to Get SAI1 BlockB clock source selection.
lypinator	0:bb348c97df44	6470	* @note This configuration is only available with STM32F413xx/STM32F423xx Devices.
lypinator	0:bb348c97df44	6471	* @retval The clock source can be one of the following values:
lypinator	0:bb348c97df44	6472	* @arg RCC_SAIBCLKSOURCE_PLLI2SR: PLLI2S_R clock divided (R2) used as SAI1 Block A clock.
lypinator	0:bb348c97df44	6473	* @arg RCC_SAIBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 Block A clock.
lypinator	0:bb348c97df44	6474	* @arg RCC_SAIBCLKSOURCE_PLLR: PLL_R clock divided (R1) used as SAI1 Block A clock.
lypinator	0:bb348c97df44	6475	* @arg RCC_SAIBCLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
lypinator	0:bb348c97df44	6476	*/
lypinator	0:bb348c97df44	6477	#define __HAL_RCC_GET_SAI_BLOCKB_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI1BSRC))
lypinator	0:bb348c97df44	6478
lypinator	0:bb348c97df44	6479	/** @brief Macro to configure the LPTIM1 clock.
lypinator	0:bb348c97df44	6480	* @param __SOURCE__ specifies the LPTIM1 clock source.
lypinator	0:bb348c97df44	6481	* This parameter can be one of the following values:
lypinator	0:bb348c97df44	6482	* @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK selected as LPTIM1 clock
lypinator	0:bb348c97df44	6483	* @arg RCC_LPTIM1CLKSOURCE_HSI: HSI clock selected as LPTIM1 clock
lypinator	0:bb348c97df44	6484	* @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock
lypinator	0:bb348c97df44	6485	* @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
lypinator	0:bb348c97df44	6486	*/
lypinator	0:bb348c97df44	6487	#define __HAL_RCC_LPTIM1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, (uint32_t)(__SOURCE__)))
lypinator	0:bb348c97df44	6488
lypinator	0:bb348c97df44	6489	/** @brief Macro to Get the LPTIM1 clock.
lypinator	0:bb348c97df44	6490	* @retval The clock source can be one of the following values:
lypinator	0:bb348c97df44	6491	* @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK selected as LPTIM1 clock
lypinator	0:bb348c97df44	6492	* @arg RCC_LPTIM1CLKSOURCE_HSI: HSI clock selected as LPTIM1 clock
lypinator	0:bb348c97df44	6493	* @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock
lypinator	0:bb348c97df44	6494	* @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
lypinator	0:bb348c97df44	6495	*/
lypinator	0:bb348c97df44	6496	#define __HAL_RCC_GET_LPTIM1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL))
lypinator	0:bb348c97df44	6497	#endif /* STM32F413xx \|\| STM32F423xx */
lypinator	0:bb348c97df44	6498
lypinator	0:bb348c97df44	6499	/** @brief Macro to configure I2S APB1 clock source selection.
lypinator	0:bb348c97df44	6500	* @param __SOURCE__ specifies the I2S APB1 clock source.
lypinator	0:bb348c97df44	6501	* This parameter can be one of the following values:
lypinator	0:bb348c97df44	6502	* @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR.
lypinator	0:bb348c97df44	6503	* @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin.
lypinator	0:bb348c97df44	6504	* @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR.
lypinator	0:bb348c97df44	6505	* @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
lypinator	0:bb348c97df44	6506	*/
lypinator	0:bb348c97df44	6507	#define __HAL_RCC_I2S_APB1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC, (__SOURCE__)))
lypinator	0:bb348c97df44	6508
lypinator	0:bb348c97df44	6509	/** @brief Macro to Get I2S APB1 clock source selection.
lypinator	0:bb348c97df44	6510	* @retval The clock source can be one of the following values:
lypinator	0:bb348c97df44	6511	* @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR.
lypinator	0:bb348c97df44	6512	* @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin.
lypinator	0:bb348c97df44	6513	* @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR.
lypinator	0:bb348c97df44	6514	* @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
lypinator	0:bb348c97df44	6515	*/
lypinator	0:bb348c97df44	6516	#define __HAL_RCC_GET_I2S_APB1_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC))
lypinator	0:bb348c97df44	6517
lypinator	0:bb348c97df44	6518	/** @brief Macro to configure I2S APB2 clock source selection.
lypinator	0:bb348c97df44	6519	* @param __SOURCE__ specifies the I2S APB2 clock source.
lypinator	0:bb348c97df44	6520	* This parameter can be one of the following values:
lypinator	0:bb348c97df44	6521	* @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR.
lypinator	0:bb348c97df44	6522	* @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin.
lypinator	0:bb348c97df44	6523	* @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR.
lypinator	0:bb348c97df44	6524	* @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
lypinator	0:bb348c97df44	6525	*/
lypinator	0:bb348c97df44	6526	#define __HAL_RCC_I2S_APB2_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC, (__SOURCE__)))
lypinator	0:bb348c97df44	6527
lypinator	0:bb348c97df44	6528	/** @brief Macro to Get I2S APB2 clock source selection.
lypinator	0:bb348c97df44	6529	* @retval The clock source can be one of the following values:
lypinator	0:bb348c97df44	6530	* @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR.
lypinator	0:bb348c97df44	6531	* @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin.
lypinator	0:bb348c97df44	6532	* @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR.
lypinator	0:bb348c97df44	6533	* @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
lypinator	0:bb348c97df44	6534	*/
lypinator	0:bb348c97df44	6535	#define __HAL_RCC_GET_I2S_APB2_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC))
lypinator	0:bb348c97df44	6536
lypinator	0:bb348c97df44	6537	/** @brief Macro to configure the PLL I2S clock source (PLLI2SCLK).
lypinator	0:bb348c97df44	6538	* @note This macro must be called before enabling the I2S APB clock.
lypinator	0:bb348c97df44	6539	* @param __SOURCE__ specifies the I2S clock source.
lypinator	0:bb348c97df44	6540	* This parameter can be one of the following values:
lypinator	0:bb348c97df44	6541	* @arg RCC_PLLI2SCLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
lypinator	0:bb348c97df44	6542	* @arg RCC_PLLI2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin
lypinator	0:bb348c97df44	6543	* used as I2S clock source.
lypinator	0:bb348c97df44	6544	*/
lypinator	0:bb348c97df44	6545	#define __HAL_RCC_PLL_I2S_CONFIG(__SOURCE__) ((__IO uint32_t ) RCC_PLLI2SCFGR_PLLI2SSRC_BB = (__SOURCE__))
lypinator	0:bb348c97df44	6546
lypinator	0:bb348c97df44	6547	/** @brief Macro to configure the FMPI2C1 clock.
lypinator	0:bb348c97df44	6548	* @param __SOURCE__ specifies the FMPI2C1 clock source.
lypinator	0:bb348c97df44	6549	* This parameter can be one of the following values:
lypinator	0:bb348c97df44	6550	* @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock
lypinator	0:bb348c97df44	6551	* @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock
lypinator	0:bb348c97df44	6552	* @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock
lypinator	0:bb348c97df44	6553	*/
lypinator	0:bb348c97df44	6554	#define __HAL_RCC_FMPI2C1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, (uint32_t)(__SOURCE__)))
lypinator	0:bb348c97df44	6555
lypinator	0:bb348c97df44	6556	/** @brief Macro to Get the FMPI2C1 clock.
lypinator	0:bb348c97df44	6557	* @retval The clock source can be one of the following values:
lypinator	0:bb348c97df44	6558	* @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock
lypinator	0:bb348c97df44	6559	* @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock
lypinator	0:bb348c97df44	6560	* @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock
lypinator	0:bb348c97df44	6561	*/
lypinator	0:bb348c97df44	6562	#define __HAL_RCC_GET_FMPI2C1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL))
lypinator	0:bb348c97df44	6563
lypinator	0:bb348c97df44	6564	/** @brief Macro to configure the CLK48 clock.
lypinator	0:bb348c97df44	6565	* @param __SOURCE__ specifies the CLK48 clock source.
lypinator	0:bb348c97df44	6566	* This parameter can be one of the following values:
lypinator	0:bb348c97df44	6567	* @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock.
lypinator	0:bb348c97df44	6568	* @arg RCC_CLK48CLKSOURCE_PLLI2SQ: PLLI2S VCO Output divided by PLLI2SQ used as CLK48 clock.
lypinator	0:bb348c97df44	6569	*/
lypinator	0:bb348c97df44	6570	#define __HAL_RCC_CLK48_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, (uint32_t)(__SOURCE__)))
lypinator	0:bb348c97df44	6571
lypinator	0:bb348c97df44	6572	/** @brief Macro to Get the CLK48 clock.
lypinator	0:bb348c97df44	6573	* @retval The clock source can be one of the following values:
lypinator	0:bb348c97df44	6574	* @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock.
lypinator	0:bb348c97df44	6575	* @arg RCC_CLK48CLKSOURCE_PLLI2SQ: PLLI2S VCO Output divided by PLLI2SQ used as CLK48 clock
lypinator	0:bb348c97df44	6576	*/
lypinator	0:bb348c97df44	6577	#define __HAL_RCC_GET_CLK48_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL))
lypinator	0:bb348c97df44	6578
lypinator	0:bb348c97df44	6579	/** @brief Macro to configure the SDIO clock.
lypinator	0:bb348c97df44	6580	* @param __SOURCE__ specifies the SDIO clock source.
lypinator	0:bb348c97df44	6581	* This parameter can be one of the following values:
lypinator	0:bb348c97df44	6582	* @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock.
lypinator	0:bb348c97df44	6583	* @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock.
lypinator	0:bb348c97df44	6584	*/
lypinator	0:bb348c97df44	6585	#define __HAL_RCC_SDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL, (uint32_t)(__SOURCE__)))
lypinator	0:bb348c97df44	6586
lypinator	0:bb348c97df44	6587	/** @brief Macro to Get the SDIO clock.
lypinator	0:bb348c97df44	6588	* @retval The clock source can be one of the following values:
lypinator	0:bb348c97df44	6589	* @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock.
lypinator	0:bb348c97df44	6590	* @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock.
lypinator	0:bb348c97df44	6591	*/
lypinator	0:bb348c97df44	6592	#define __HAL_RCC_GET_SDIO_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL))
lypinator	0:bb348c97df44	6593
lypinator	0:bb348c97df44	6594	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx */
lypinator	0:bb348c97df44	6595
lypinator	0:bb348c97df44	6596	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
lypinator	0:bb348c97df44	6597	/** @brief Macro to configure I2S clock source selection.
lypinator	0:bb348c97df44	6598	* @param __SOURCE__ specifies the I2S clock source.
lypinator	0:bb348c97df44	6599	* This parameter can be one of the following values:
lypinator	0:bb348c97df44	6600	* @arg RCC_I2SAPBCLKSOURCE_PLLR: PLL VCO output clock divided by PLLR.
lypinator	0:bb348c97df44	6601	* @arg RCC_I2SAPBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin.
lypinator	0:bb348c97df44	6602	* @arg RCC_I2SAPBCLKSOURCE_PLLSRC: HSI/HSE depends on PLLSRC.
lypinator	0:bb348c97df44	6603	*/
lypinator	0:bb348c97df44	6604	#define __HAL_RCC_I2S_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2SSRC, (__SOURCE__)))
lypinator	0:bb348c97df44	6605
lypinator	0:bb348c97df44	6606	/** @brief Macro to Get I2S clock source selection.
lypinator	0:bb348c97df44	6607	* @retval The clock source can be one of the following values:
lypinator	0:bb348c97df44	6608	* @arg RCC_I2SAPBCLKSOURCE_PLLR: PLL VCO output clock divided by PLLR.
lypinator	0:bb348c97df44	6609	* @arg RCC_I2SAPBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin.
lypinator	0:bb348c97df44	6610	* @arg RCC_I2SAPBCLKSOURCE_PLLSRC: HSI/HSE depends on PLLSRC.
lypinator	0:bb348c97df44	6611	*/
lypinator	0:bb348c97df44	6612	#define __HAL_RCC_GET_I2S_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2SSRC))
lypinator	0:bb348c97df44	6613
lypinator	0:bb348c97df44	6614	/** @brief Macro to configure the FMPI2C1 clock.
lypinator	0:bb348c97df44	6615	* @param __SOURCE__ specifies the FMPI2C1 clock source.
lypinator	0:bb348c97df44	6616	* This parameter can be one of the following values:
lypinator	0:bb348c97df44	6617	* @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock
lypinator	0:bb348c97df44	6618	* @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock
lypinator	0:bb348c97df44	6619	* @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock
lypinator	0:bb348c97df44	6620	*/
lypinator	0:bb348c97df44	6621	#define __HAL_RCC_FMPI2C1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, (uint32_t)(__SOURCE__)))
lypinator	0:bb348c97df44	6622
lypinator	0:bb348c97df44	6623	/** @brief Macro to Get the FMPI2C1 clock.
lypinator	0:bb348c97df44	6624	* @retval The clock source can be one of the following values:
lypinator	0:bb348c97df44	6625	* @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock
lypinator	0:bb348c97df44	6626	* @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock
lypinator	0:bb348c97df44	6627	* @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock
lypinator	0:bb348c97df44	6628	*/
lypinator	0:bb348c97df44	6629	#define __HAL_RCC_GET_FMPI2C1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL))
lypinator	0:bb348c97df44	6630
lypinator	0:bb348c97df44	6631	/** @brief Macro to configure the LPTIM1 clock.
lypinator	0:bb348c97df44	6632	* @param __SOURCE__ specifies the LPTIM1 clock source.
lypinator	0:bb348c97df44	6633	* This parameter can be one of the following values:
lypinator	0:bb348c97df44	6634	* @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK1 selected as LPTIM1 clock
lypinator	0:bb348c97df44	6635	* @arg RCC_LPTIM1CLKSOURCE_HSI: HSI clock selected as LPTIM1 clock
lypinator	0:bb348c97df44	6636	* @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock
lypinator	0:bb348c97df44	6637	* @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
lypinator	0:bb348c97df44	6638	*/
lypinator	0:bb348c97df44	6639	#define __HAL_RCC_LPTIM1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, (uint32_t)(__SOURCE__)))
lypinator	0:bb348c97df44	6640
lypinator	0:bb348c97df44	6641	/** @brief Macro to Get the LPTIM1 clock.
lypinator	0:bb348c97df44	6642	* @retval The clock source can be one of the following values:
lypinator	0:bb348c97df44	6643	* @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK1 selected as LPTIM1 clock
lypinator	0:bb348c97df44	6644	* @arg RCC_LPTIM1CLKSOURCE_HSI: HSI clock selected as LPTIM1 clock
lypinator	0:bb348c97df44	6645	* @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock
lypinator	0:bb348c97df44	6646	* @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
lypinator	0:bb348c97df44	6647	*/
lypinator	0:bb348c97df44	6648	#define __HAL_RCC_GET_LPTIM1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL))
lypinator	0:bb348c97df44	6649	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
lypinator	0:bb348c97df44	6650
lypinator	0:bb348c97df44	6651	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\|\
lypinator	0:bb348c97df44	6652	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\|\
lypinator	0:bb348c97df44	6653	defined(STM32F410Rx) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| defined(STM32F469xx) \|\|\
lypinator	0:bb348c97df44	6654	defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\|\
lypinator	0:bb348c97df44	6655	defined(STM32F412Cx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
lypinator	0:bb348c97df44	6656	/** @brief Macro to configure the Timers clocks prescalers
lypinator	0:bb348c97df44	6657	* @note This feature is only available with STM32F429x/439x Devices.
lypinator	0:bb348c97df44	6658	* @param __PRESC__ specifies the Timers clocks prescalers selection
lypinator	0:bb348c97df44	6659	* This parameter can be one of the following values:
lypinator	0:bb348c97df44	6660	* @arg RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is
lypinator	0:bb348c97df44	6661	* equal to HPRE if PPREx is corresponding to division by 1 or 2,
lypinator	0:bb348c97df44	6662	* else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to
lypinator	0:bb348c97df44	6663	* division by 4 or more.
lypinator	0:bb348c97df44	6664	* @arg RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is
lypinator	0:bb348c97df44	6665	* equal to HPRE if PPREx is corresponding to division by 1, 2 or 4,
lypinator	0:bb348c97df44	6666	* else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding
lypinator	0:bb348c97df44	6667	* to division by 8 or more.
lypinator	0:bb348c97df44	6668	*/
lypinator	0:bb348c97df44	6669	#define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) ((__IO uint32_t ) RCC_DCKCFGR_TIMPRE_BB = (__PRESC__))
lypinator	0:bb348c97df44	6670
lypinator	0:bb348c97df44	6671	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx) \|\| STM32F401xC \|\| STM32F401xE \|\| STM32F410xx \|\| STM32F411xE \|\|\
lypinator	0:bb348c97df44	6672	STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx \|\| STM32F413xx \|\|\
lypinator	0:bb348c97df44	6673	STM32F423xx */
lypinator	0:bb348c97df44	6674
lypinator	0:bb348c97df44	6675	/----------------------------------------------------------------------------/
lypinator	0:bb348c97df44	6676
lypinator	0:bb348c97df44	6677	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
lypinator	0:bb348c97df44	6678	/** @brief Enable PLLSAI_RDY interrupt.
lypinator	0:bb348c97df44	6679	*/
lypinator	0:bb348c97df44	6680	#define __HAL_RCC_PLLSAI_ENABLE_IT() (RCC->CIR \|= (RCC_CIR_PLLSAIRDYIE))
lypinator	0:bb348c97df44	6681
lypinator	0:bb348c97df44	6682	/** @brief Disable PLLSAI_RDY interrupt.
lypinator	0:bb348c97df44	6683	*/
lypinator	0:bb348c97df44	6684	#define __HAL_RCC_PLLSAI_DISABLE_IT() (RCC->CIR &= ~(RCC_CIR_PLLSAIRDYIE))
lypinator	0:bb348c97df44	6685
lypinator	0:bb348c97df44	6686	/** @brief Clear the PLLSAI RDY interrupt pending bits.
lypinator	0:bb348c97df44	6687	*/
lypinator	0:bb348c97df44	6688	#define __HAL_RCC_PLLSAI_CLEAR_IT() (RCC->CIR \|= (RCC_CIR_PLLSAIRDYF))
lypinator	0:bb348c97df44	6689
lypinator	0:bb348c97df44	6690	/** @brief Check the PLLSAI RDY interrupt has occurred or not.
lypinator	0:bb348c97df44	6691	* @retval The new state (TRUE or FALSE).
lypinator	0:bb348c97df44	6692	*/
lypinator	0:bb348c97df44	6693	#define __HAL_RCC_PLLSAI_GET_IT() ((RCC->CIR & (RCC_CIR_PLLSAIRDYIE)) == (RCC_CIR_PLLSAIRDYIE))
lypinator	0:bb348c97df44	6694
lypinator	0:bb348c97df44	6695	/** @brief Check PLLSAI RDY flag is set or not.
lypinator	0:bb348c97df44	6696	* @retval The new state (TRUE or FALSE).
lypinator	0:bb348c97df44	6697	*/
lypinator	0:bb348c97df44	6698	#define __HAL_RCC_PLLSAI_GET_FLAG() ((RCC->CR & (RCC_CR_PLLSAIRDY)) == (RCC_CR_PLLSAIRDY))
lypinator	0:bb348c97df44	6699
lypinator	0:bb348c97df44	6700	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
lypinator	0:bb348c97df44	6701
lypinator	0:bb348c97df44	6702	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
lypinator	0:bb348c97df44	6703	/** @brief Macros to enable or disable the RCC MCO1 feature.
lypinator	0:bb348c97df44	6704	*/
lypinator	0:bb348c97df44	6705	#define __HAL_RCC_MCO1_ENABLE() ((__IO uint32_t ) RCC_CFGR_MCO1EN_BB = ENABLE)
lypinator	0:bb348c97df44	6706	#define __HAL_RCC_MCO1_DISABLE() ((__IO uint32_t ) RCC_CFGR_MCO1EN_BB = DISABLE)
lypinator	0:bb348c97df44	6707
lypinator	0:bb348c97df44	6708	/** @brief Macros to enable or disable the RCC MCO2 feature.
lypinator	0:bb348c97df44	6709	*/
lypinator	0:bb348c97df44	6710	#define __HAL_RCC_MCO2_ENABLE() ((__IO uint32_t ) RCC_CFGR_MCO2EN_BB = ENABLE)
lypinator	0:bb348c97df44	6711	#define __HAL_RCC_MCO2_DISABLE() ((__IO uint32_t ) RCC_CFGR_MCO2EN_BB = DISABLE)
lypinator	0:bb348c97df44	6712
lypinator	0:bb348c97df44	6713	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
lypinator	0:bb348c97df44	6714
lypinator	0:bb348c97df44	6715	/**
lypinator	0:bb348c97df44	6716	* @}
lypinator	0:bb348c97df44	6717	*/
lypinator	0:bb348c97df44	6718
lypinator	0:bb348c97df44	6719	/* Exported functions --------------------------------------------------------*/
lypinator	0:bb348c97df44	6720	/** @addtogroup RCCEx_Exported_Functions
lypinator	0:bb348c97df44	6721	* @{
lypinator	0:bb348c97df44	6722	*/
lypinator	0:bb348c97df44	6723
lypinator	0:bb348c97df44	6724	/** @addtogroup RCCEx_Exported_Functions_Group1
lypinator	0:bb348c97df44	6725	* @{
lypinator	0:bb348c97df44	6726	*/
lypinator	0:bb348c97df44	6727	HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
lypinator	0:bb348c97df44	6728	void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
lypinator	0:bb348c97df44	6729
lypinator	0:bb348c97df44	6730	uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
lypinator	0:bb348c97df44	6731
lypinator	0:bb348c97df44	6732	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx) \|\| defined(STM32F411xE) \|\|\
lypinator	0:bb348c97df44	6733	defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\|\
lypinator	0:bb348c97df44	6734	defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx) \|\| defined(STM32F413xx) \|\|\
lypinator	0:bb348c97df44	6735	defined(STM32F423xx)
lypinator	0:bb348c97df44	6736	void HAL_RCCEx_SelectLSEMode(uint8_t Mode);
lypinator	0:bb348c97df44	6737	#endif /* STM32F410xx \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx \|\| STM32F413xx \|\| STM32F423xx */
lypinator	0:bb348c97df44	6738	#if defined(RCC_PLLI2S_SUPPORT)
lypinator	0:bb348c97df44	6739	HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit);
lypinator	0:bb348c97df44	6740	HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void);
lypinator	0:bb348c97df44	6741	#endif /* RCC_PLLI2S_SUPPORT */
lypinator	0:bb348c97df44	6742	#if defined(RCC_PLLSAI_SUPPORT)
lypinator	0:bb348c97df44	6743	HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI(RCC_PLLSAIInitTypeDef *PLLSAIInit);
lypinator	0:bb348c97df44	6744	HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI(void);
lypinator	0:bb348c97df44	6745	#endif /* RCC_PLLSAI_SUPPORT */
lypinator	0:bb348c97df44	6746	/**
lypinator	0:bb348c97df44	6747	* @}
lypinator	0:bb348c97df44	6748	*/
lypinator	0:bb348c97df44	6749
lypinator	0:bb348c97df44	6750	/**
lypinator	0:bb348c97df44	6751	* @}
lypinator	0:bb348c97df44	6752	*/
lypinator	0:bb348c97df44	6753	/* Private types -------------------------------------------------------------*/
lypinator	0:bb348c97df44	6754	/* Private variables ---------------------------------------------------------*/
lypinator	0:bb348c97df44	6755	/* Private constants ---------------------------------------------------------*/
lypinator	0:bb348c97df44	6756	/** @defgroup RCCEx_Private_Constants RCCEx Private Constants
lypinator	0:bb348c97df44	6757	* @{
lypinator	0:bb348c97df44	6758	*/
lypinator	0:bb348c97df44	6759
lypinator	0:bb348c97df44	6760	/** @defgroup RCCEx_BitAddress_AliasRegion RCC BitAddress AliasRegion
lypinator	0:bb348c97df44	6761	* @brief RCC registers bit address in the alias region
lypinator	0:bb348c97df44	6762	* @{
lypinator	0:bb348c97df44	6763	*/
lypinator	0:bb348c97df44	6764	/* --- CR Register ---*/
lypinator	0:bb348c97df44	6765	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\|\
lypinator	0:bb348c97df44	6766	defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
lypinator	0:bb348c97df44	6767	/* Alias word address of PLLSAION bit */
lypinator	0:bb348c97df44	6768	#define RCC_PLLSAION_BIT_NUMBER 0x1CU
lypinator	0:bb348c97df44	6769	#define RCC_CR_PLLSAION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_PLLSAION_BIT_NUMBER * 4U))
lypinator	0:bb348c97df44	6770
lypinator	0:bb348c97df44	6771	#define PLLSAI_TIMEOUT_VALUE 2U /* Timeout value fixed to 2 ms */
lypinator	0:bb348c97df44	6772	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
lypinator	0:bb348c97df44	6773
lypinator	0:bb348c97df44	6774	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\| \
lypinator	0:bb348c97df44	6775	defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| \
lypinator	0:bb348c97df44	6776	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| \
lypinator	0:bb348c97df44	6777	defined(STM32F469xx) \|\| defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| \
lypinator	0:bb348c97df44	6778	defined(STM32F412Rx) \|\| defined(STM32F412Cx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
lypinator	0:bb348c97df44	6779	/* Alias word address of PLLI2SON bit */
lypinator	0:bb348c97df44	6780	#define RCC_PLLI2SON_BIT_NUMBER 0x1AU
lypinator	0:bb348c97df44	6781	#define RCC_CR_PLLI2SON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_PLLI2SON_BIT_NUMBER * 4U))
lypinator	0:bb348c97df44	6782	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\|
lypinator	0:bb348c97df44	6783	STM32F401xC \|\| STM32F401xE \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\| STM32F412Vx \|\|
lypinator	0:bb348c97df44	6784	STM32F412Rx \|\| STM32F412Cx \|\| STM32F413xx \|\| STM32F423xx */
lypinator	0:bb348c97df44	6785
lypinator	0:bb348c97df44	6786	/* --- DCKCFGR Register ---*/
lypinator	0:bb348c97df44	6787	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\|\
lypinator	0:bb348c97df44	6788	defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx) \|\| defined(STM32F401xC) \|\|\
lypinator	0:bb348c97df44	6789	defined(STM32F401xE) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| defined(STM32F469xx) \|\|\
lypinator	0:bb348c97df44	6790	defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\|\
lypinator	0:bb348c97df44	6791	defined(STM32F412Cx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
lypinator	0:bb348c97df44	6792	/* Alias word address of TIMPRE bit */
lypinator	0:bb348c97df44	6793	#define RCC_DCKCFGR_OFFSET (RCC_OFFSET + 0x8CU)
lypinator	0:bb348c97df44	6794	#define RCC_TIMPRE_BIT_NUMBER 0x18U
lypinator	0:bb348c97df44	6795	#define RCC_DCKCFGR_TIMPRE_BB (PERIPH_BB_BASE + (RCC_DCKCFGR_OFFSET * 32U) + (RCC_TIMPRE_BIT_NUMBER * 4U))
lypinator	0:bb348c97df44	6796	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F410xx \|\| STM32F401xC \|\|\
lypinator	0:bb348c97df44	6797	STM32F401xE \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\|\
lypinator	0:bb348c97df44	6798	STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx \|\| STM32F413xx \|\| STM32F423xx */
lypinator	0:bb348c97df44	6799
lypinator	0:bb348c97df44	6800	/* --- CFGR Register ---*/
lypinator	0:bb348c97df44	6801	#define RCC_CFGR_OFFSET (RCC_OFFSET + 0x08U)
lypinator	0:bb348c97df44	6802	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\| \
lypinator	0:bb348c97df44	6803	defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| \
lypinator	0:bb348c97df44	6804	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| \
lypinator	0:bb348c97df44	6805	defined(STM32F469xx) \|\| defined(STM32F479xx)
lypinator	0:bb348c97df44	6806	/* Alias word address of I2SSRC bit */
lypinator	0:bb348c97df44	6807	#define RCC_I2SSRC_BIT_NUMBER 0x17U
lypinator	0:bb348c97df44	6808	#define RCC_CFGR_I2SSRC_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32U) + (RCC_I2SSRC_BIT_NUMBER * 4U))
lypinator	0:bb348c97df44	6809
lypinator	0:bb348c97df44	6810	#define PLLI2S_TIMEOUT_VALUE 2U /* Timeout value fixed to 2 ms */
lypinator	0:bb348c97df44	6811	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\|
lypinator	0:bb348c97df44	6812	STM32F401xC \|\| STM32F401xE \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
lypinator	0:bb348c97df44	6813
lypinator	0:bb348c97df44	6814	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx) \|\|\
lypinator	0:bb348c97df44	6815	defined(STM32F413xx) \|\| defined(STM32F423xx)
lypinator	0:bb348c97df44	6816	/* --- PLLI2SCFGR Register ---*/
lypinator	0:bb348c97df44	6817	#define RCC_PLLI2SCFGR_OFFSET (RCC_OFFSET + 0x84U)
lypinator	0:bb348c97df44	6818	/* Alias word address of PLLI2SSRC bit */
lypinator	0:bb348c97df44	6819	#define RCC_PLLI2SSRC_BIT_NUMBER 0x16U
lypinator	0:bb348c97df44	6820	#define RCC_PLLI2SCFGR_PLLI2SSRC_BB (PERIPH_BB_BASE + (RCC_PLLI2SCFGR_OFFSET * 32U) + (RCC_PLLI2SSRC_BIT_NUMBER * 4U))
lypinator	0:bb348c97df44	6821
lypinator	0:bb348c97df44	6822	#define PLLI2S_TIMEOUT_VALUE 2U /* Timeout value fixed to 2 ms */
lypinator	0:bb348c97df44	6823	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx \|\| STM32F413xx \| STM32F423xx */
lypinator	0:bb348c97df44	6824
lypinator	0:bb348c97df44	6825	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
lypinator	0:bb348c97df44	6826	/* Alias word address of MCO1EN bit */
lypinator	0:bb348c97df44	6827	#define RCC_MCO1EN_BIT_NUMBER 0x8U
lypinator	0:bb348c97df44	6828	#define RCC_CFGR_MCO1EN_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32U) + (RCC_MCO1EN_BIT_NUMBER * 4U))
lypinator	0:bb348c97df44	6829
lypinator	0:bb348c97df44	6830	/* Alias word address of MCO2EN bit */
lypinator	0:bb348c97df44	6831	#define RCC_MCO2EN_BIT_NUMBER 0x9U
lypinator	0:bb348c97df44	6832	#define RCC_CFGR_MCO2EN_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32U) + (RCC_MCO2EN_BIT_NUMBER * 4U))
lypinator	0:bb348c97df44	6833	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
lypinator	0:bb348c97df44	6834
lypinator	0:bb348c97df44	6835	#define PLL_TIMEOUT_VALUE 2U /* 2 ms */
lypinator	0:bb348c97df44	6836	/**
lypinator	0:bb348c97df44	6837	* @}
lypinator	0:bb348c97df44	6838	*/
lypinator	0:bb348c97df44	6839
lypinator	0:bb348c97df44	6840	/**
lypinator	0:bb348c97df44	6841	* @}
lypinator	0:bb348c97df44	6842	*/
lypinator	0:bb348c97df44	6843
lypinator	0:bb348c97df44	6844	/* Private macros ------------------------------------------------------------*/
lypinator	0:bb348c97df44	6845	/** @defgroup RCCEx_Private_Macros RCCEx Private Macros
lypinator	0:bb348c97df44	6846	* @{
lypinator	0:bb348c97df44	6847	*/
lypinator	0:bb348c97df44	6848	/** @defgroup RCCEx_IS_RCC_Definitions RCC Private macros to check input parameters
lypinator	0:bb348c97df44	6849	* @{
lypinator	0:bb348c97df44	6850	*/
lypinator	0:bb348c97df44	6851	#if defined(STM32F411xE)
lypinator	0:bb348c97df44	6852	#define IS_RCC_PLLN_VALUE(VALUE) ((192U <= (VALUE)) && ((VALUE) <= 432U))
lypinator	0:bb348c97df44	6853	#define IS_RCC_PLLI2SN_VALUE(VALUE) ((192U <= (VALUE)) && ((VALUE) <= 432U))
lypinator	0:bb348c97df44	6854	#else /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F427xx \|\| STM32F437xx \|\|
lypinator	0:bb348c97df44	6855	STM32F429xx \|\| STM32F439xx \|\| STM32F401xC \|\| STM32F401xE \|\| STM32F410Tx \|\| STM32F410Cx \|\|
lypinator	0:bb348c97df44	6856	STM32F410Rx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Cx \|\| STM32F412Rx \|\|
lypinator	0:bb348c97df44	6857	STM32F412Vx \|\| STM32F412Zx \|\| STM32F413xx \|\| STM32F423xx */
lypinator	0:bb348c97df44	6858	#define IS_RCC_PLLN_VALUE(VALUE) ((50U <= (VALUE)) && ((VALUE) <= 432U))
lypinator	0:bb348c97df44	6859	#define IS_RCC_PLLI2SN_VALUE(VALUE) ((50U <= (VALUE)) && ((VALUE) <= 432U))
lypinator	0:bb348c97df44	6860	#endif /* STM32F411xE */
lypinator	0:bb348c97df44	6861
lypinator	0:bb348c97df44	6862	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx)\|\| defined(STM32F439xx)
lypinator	0:bb348c97df44	6863	#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x0000007FU))
lypinator	0:bb348c97df44	6864	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
lypinator	0:bb348c97df44	6865
lypinator	0:bb348c97df44	6866	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx)\|\| defined(STM32F417xx)
lypinator	0:bb348c97df44	6867	#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x00000007U))
lypinator	0:bb348c97df44	6868	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx */
lypinator	0:bb348c97df44	6869
lypinator	0:bb348c97df44	6870	#if defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE)
lypinator	0:bb348c97df44	6871	#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x0000000FU))
lypinator	0:bb348c97df44	6872	#endif /* STM32F401xC \|\| STM32F401xE \|\| STM32F411xE */
lypinator	0:bb348c97df44	6873
lypinator	0:bb348c97df44	6874	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
lypinator	0:bb348c97df44	6875	#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x0000001FU))
lypinator	0:bb348c97df44	6876	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
lypinator	0:bb348c97df44	6877
lypinator	0:bb348c97df44	6878	#if defined(STM32F446xx)
lypinator	0:bb348c97df44	6879	#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x00000FFFU))
lypinator	0:bb348c97df44	6880	#endif /* STM32F446xx */
lypinator	0:bb348c97df44	6881
lypinator	0:bb348c97df44	6882	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
lypinator	0:bb348c97df44	6883	#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x000001FFU))
lypinator	0:bb348c97df44	6884	#endif /* STM32F469xx \|\| STM32F479xx */
lypinator	0:bb348c97df44	6885
lypinator	0:bb348c97df44	6886	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx)
lypinator	0:bb348c97df44	6887	#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x000003FFU))
lypinator	0:bb348c97df44	6888	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx */
lypinator	0:bb348c97df44	6889
lypinator	0:bb348c97df44	6890	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
lypinator	0:bb348c97df44	6891	#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x00007FFFU))
lypinator	0:bb348c97df44	6892	#endif /* STM32F413xx \|\| STM32F423xx */
lypinator	0:bb348c97df44	6893
lypinator	0:bb348c97df44	6894	#define IS_RCC_PLLI2SR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U))
lypinator	0:bb348c97df44	6895
lypinator	0:bb348c97df44	6896	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx)\|\| defined(STM32F439xx) \|\|\
lypinator	0:bb348c97df44	6897	defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
lypinator	0:bb348c97df44	6898	#define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 15U))
lypinator	0:bb348c97df44	6899
lypinator	0:bb348c97df44	6900	#define IS_RCC_PLLSAIN_VALUE(VALUE) ((50U <= (VALUE)) && ((VALUE) <= 432U))
lypinator	0:bb348c97df44	6901
lypinator	0:bb348c97df44	6902	#define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 15U))
lypinator	0:bb348c97df44	6903
lypinator	0:bb348c97df44	6904	#define IS_RCC_PLLSAIR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U))
lypinator	0:bb348c97df44	6905
lypinator	0:bb348c97df44	6906	#define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 32U))
lypinator	0:bb348c97df44	6907
lypinator	0:bb348c97df44	6908	#define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 32U))
lypinator	0:bb348c97df44	6909
lypinator	0:bb348c97df44	6910	#define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDIVR_2) \|\|\
lypinator	0:bb348c97df44	6911	((VALUE) == RCC_PLLSAIDIVR_4) \|\|\
lypinator	0:bb348c97df44	6912	((VALUE) == RCC_PLLSAIDIVR_8) \|\|\
lypinator	0:bb348c97df44	6913	((VALUE) == RCC_PLLSAIDIVR_16))
lypinator	0:bb348c97df44	6914	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
lypinator	0:bb348c97df44	6915
lypinator	0:bb348c97df44	6916	#if defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| \
lypinator	0:bb348c97df44	6917	defined(STM32F412Rx) \|\| defined(STM32F412Cx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
lypinator	0:bb348c97df44	6918	#define IS_RCC_PLLI2SM_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 63U))
lypinator	0:bb348c97df44	6919
lypinator	0:bb348c97df44	6920	#define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) \|\|\
lypinator	0:bb348c97df44	6921	((MODE) == RCC_LSE_HIGHDRIVE_MODE))
lypinator	0:bb348c97df44	6922	#endif /* STM32F411xE \|\| STM32F446xx \|\| STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx \|\| STM32F413xx \|\| STM32F423xx */
lypinator	0:bb348c97df44	6923
lypinator	0:bb348c97df44	6924	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
lypinator	0:bb348c97df44	6925	#define IS_RCC_PLLR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U))
lypinator	0:bb348c97df44	6926
lypinator	0:bb348c97df44	6927	#define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) \|\|\
lypinator	0:bb348c97df44	6928	((MODE) == RCC_LSE_HIGHDRIVE_MODE))
lypinator	0:bb348c97df44	6929
lypinator	0:bb348c97df44	6930	#define IS_RCC_FMPI2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_FMPI2C1CLKSOURCE_PCLK1) \|\|\
lypinator	0:bb348c97df44	6931	((SOURCE) == RCC_FMPI2C1CLKSOURCE_SYSCLK) \|\|\
lypinator	0:bb348c97df44	6932	((SOURCE) == RCC_FMPI2C1CLKSOURCE_HSI))
lypinator	0:bb348c97df44	6933
lypinator	0:bb348c97df44	6934	#define IS_RCC_LPTIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_LPTIM1CLKSOURCE_PCLK1) \|\|\
lypinator	0:bb348c97df44	6935	((SOURCE) == RCC_LPTIM1CLKSOURCE_HSI) \|\|\
lypinator	0:bb348c97df44	6936	((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) \|\|\
lypinator	0:bb348c97df44	6937	((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE))
lypinator	0:bb348c97df44	6938
lypinator	0:bb348c97df44	6939	#define IS_RCC_I2SAPBCLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPBCLKSOURCE_PLLR) \|\|\
lypinator	0:bb348c97df44	6940	((SOURCE) == RCC_I2SAPBCLKSOURCE_EXT) \|\|\
lypinator	0:bb348c97df44	6941	((SOURCE) == RCC_I2SAPBCLKSOURCE_PLLSRC))
lypinator	0:bb348c97df44	6942	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
lypinator	0:bb348c97df44	6943
lypinator	0:bb348c97df44	6944	#if defined(STM32F446xx)
lypinator	0:bb348c97df44	6945	#define IS_RCC_PLLR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U))
lypinator	0:bb348c97df44	6946
lypinator	0:bb348c97df44	6947	#define IS_RCC_PLLI2SP_VALUE(VALUE) (((VALUE) == RCC_PLLI2SP_DIV2) \|\|\
lypinator	0:bb348c97df44	6948	((VALUE) == RCC_PLLI2SP_DIV4) \|\|\
lypinator	0:bb348c97df44	6949	((VALUE) == RCC_PLLI2SP_DIV6) \|\|\
lypinator	0:bb348c97df44	6950	((VALUE) == RCC_PLLI2SP_DIV8))
lypinator	0:bb348c97df44	6951
lypinator	0:bb348c97df44	6952	#define IS_RCC_PLLSAIM_VALUE(VALUE) ((VALUE) <= 63U)
lypinator	0:bb348c97df44	6953
lypinator	0:bb348c97df44	6954	#define IS_RCC_PLLSAIP_VALUE(VALUE) (((VALUE) == RCC_PLLSAIP_DIV2) \|\|\
lypinator	0:bb348c97df44	6955	((VALUE) == RCC_PLLSAIP_DIV4) \|\|\
lypinator	0:bb348c97df44	6956	((VALUE) == RCC_PLLSAIP_DIV6) \|\|\
lypinator	0:bb348c97df44	6957	((VALUE) == RCC_PLLSAIP_DIV8))
lypinator	0:bb348c97df44	6958
lypinator	0:bb348c97df44	6959	#define IS_RCC_SAI1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI1CLKSOURCE_PLLSAI) \|\|\
lypinator	0:bb348c97df44	6960	((SOURCE) == RCC_SAI1CLKSOURCE_PLLI2S) \|\|\
lypinator	0:bb348c97df44	6961	((SOURCE) == RCC_SAI1CLKSOURCE_PLLR) \|\|\
lypinator	0:bb348c97df44	6962	((SOURCE) == RCC_SAI1CLKSOURCE_EXT))
lypinator	0:bb348c97df44	6963
lypinator	0:bb348c97df44	6964	#define IS_RCC_SAI2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI2CLKSOURCE_PLLSAI) \|\|\
lypinator	0:bb348c97df44	6965	((SOURCE) == RCC_SAI2CLKSOURCE_PLLI2S) \|\|\
lypinator	0:bb348c97df44	6966	((SOURCE) == RCC_SAI2CLKSOURCE_PLLR) \|\|\
lypinator	0:bb348c97df44	6967	((SOURCE) == RCC_SAI2CLKSOURCE_PLLSRC))
lypinator	0:bb348c97df44	6968
lypinator	0:bb348c97df44	6969	#define IS_RCC_I2SAPB1CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLI2S) \|\|\
lypinator	0:bb348c97df44	6970	((SOURCE) == RCC_I2SAPB1CLKSOURCE_EXT) \|\|\
lypinator	0:bb348c97df44	6971	((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLR) \|\|\
lypinator	0:bb348c97df44	6972	((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLSRC))
lypinator	0:bb348c97df44	6973
lypinator	0:bb348c97df44	6974	#define IS_RCC_I2SAPB2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLI2S) \|\|\
lypinator	0:bb348c97df44	6975	((SOURCE) == RCC_I2SAPB2CLKSOURCE_EXT) \|\|\
lypinator	0:bb348c97df44	6976	((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLR) \|\|\
lypinator	0:bb348c97df44	6977	((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLSRC))
lypinator	0:bb348c97df44	6978
lypinator	0:bb348c97df44	6979	#define IS_RCC_FMPI2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_FMPI2C1CLKSOURCE_PCLK1) \|\|\
lypinator	0:bb348c97df44	6980	((SOURCE) == RCC_FMPI2C1CLKSOURCE_SYSCLK) \|\|\
lypinator	0:bb348c97df44	6981	((SOURCE) == RCC_FMPI2C1CLKSOURCE_HSI))
lypinator	0:bb348c97df44	6982
lypinator	0:bb348c97df44	6983	#define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) \|\|\
lypinator	0:bb348c97df44	6984	((SOURCE) == RCC_CECCLKSOURCE_LSE))
lypinator	0:bb348c97df44	6985
lypinator	0:bb348c97df44	6986	#define IS_RCC_CLK48CLKSOURCE(SOURCE) (((SOURCE) == RCC_CLK48CLKSOURCE_PLLQ) \|\|\
lypinator	0:bb348c97df44	6987	((SOURCE) == RCC_CLK48CLKSOURCE_PLLSAIP))
lypinator	0:bb348c97df44	6988
lypinator	0:bb348c97df44	6989	#define IS_RCC_SDIOCLKSOURCE(SOURCE) (((SOURCE) == RCC_SDIOCLKSOURCE_CLK48) \|\|\
lypinator	0:bb348c97df44	6990	((SOURCE) == RCC_SDIOCLKSOURCE_SYSCLK))
lypinator	0:bb348c97df44	6991
lypinator	0:bb348c97df44	6992	#define IS_RCC_SPDIFRXCLKSOURCE(SOURCE) (((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLLR) \|\|\
lypinator	0:bb348c97df44	6993	((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLLI2SP))
lypinator	0:bb348c97df44	6994	#endif /* STM32F446xx */
lypinator	0:bb348c97df44	6995
lypinator	0:bb348c97df44	6996	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
lypinator	0:bb348c97df44	6997	#define IS_RCC_PLLR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U))
lypinator	0:bb348c97df44	6998
lypinator	0:bb348c97df44	6999	#define IS_RCC_PLLSAIP_VALUE(VALUE) (((VALUE) == RCC_PLLSAIP_DIV2) \|\|\
lypinator	0:bb348c97df44	7000	((VALUE) == RCC_PLLSAIP_DIV4) \|\|\
lypinator	0:bb348c97df44	7001	((VALUE) == RCC_PLLSAIP_DIV6) \|\|\
lypinator	0:bb348c97df44	7002	((VALUE) == RCC_PLLSAIP_DIV8))
lypinator	0:bb348c97df44	7003
lypinator	0:bb348c97df44	7004	#define IS_RCC_CLK48CLKSOURCE(SOURCE) (((SOURCE) == RCC_CLK48CLKSOURCE_PLLQ) \|\|\
lypinator	0:bb348c97df44	7005	((SOURCE) == RCC_CLK48CLKSOURCE_PLLSAIP))
lypinator	0:bb348c97df44	7006
lypinator	0:bb348c97df44	7007	#define IS_RCC_SDIOCLKSOURCE(SOURCE) (((SOURCE) == RCC_SDIOCLKSOURCE_CLK48) \|\|\
lypinator	0:bb348c97df44	7008	((SOURCE) == RCC_SDIOCLKSOURCE_SYSCLK))
lypinator	0:bb348c97df44	7009
lypinator	0:bb348c97df44	7010	#define IS_RCC_DSIBYTELANECLKSOURCE(SOURCE) (((SOURCE) == RCC_DSICLKSOURCE_PLLR) \|\|\
lypinator	0:bb348c97df44	7011	((SOURCE) == RCC_DSICLKSOURCE_DSIPHY))
lypinator	0:bb348c97df44	7012
lypinator	0:bb348c97df44	7013	#define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) \|\|\
lypinator	0:bb348c97df44	7014	((MODE) == RCC_LSE_HIGHDRIVE_MODE))
lypinator	0:bb348c97df44	7015	#endif /* STM32F469xx \|\| STM32F479xx */
lypinator	0:bb348c97df44	7016
lypinator	0:bb348c97df44	7017	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx) \|\|\
lypinator	0:bb348c97df44	7018	defined(STM32F413xx) \|\| defined(STM32F423xx)
lypinator	0:bb348c97df44	7019	#define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 15U))
lypinator	0:bb348c97df44	7020
lypinator	0:bb348c97df44	7021	#define IS_RCC_PLLR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U))
lypinator	0:bb348c97df44	7022
lypinator	0:bb348c97df44	7023	#define IS_RCC_PLLI2SCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLI2SCLKSOURCE_PLLSRC) \|\| \
lypinator	0:bb348c97df44	7024	((__SOURCE__) == RCC_PLLI2SCLKSOURCE_EXT))
lypinator	0:bb348c97df44	7025
lypinator	0:bb348c97df44	7026	#define IS_RCC_I2SAPB1CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLI2S) \|\|\
lypinator	0:bb348c97df44	7027	((SOURCE) == RCC_I2SAPB1CLKSOURCE_EXT) \|\|\
lypinator	0:bb348c97df44	7028	((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLR) \|\|\
lypinator	0:bb348c97df44	7029	((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLSRC))
lypinator	0:bb348c97df44	7030
lypinator	0:bb348c97df44	7031	#define IS_RCC_I2SAPB2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLI2S) \|\|\
lypinator	0:bb348c97df44	7032	((SOURCE) == RCC_I2SAPB2CLKSOURCE_EXT) \|\|\
lypinator	0:bb348c97df44	7033	((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLR) \|\|\
lypinator	0:bb348c97df44	7034	((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLSRC))
lypinator	0:bb348c97df44	7035
lypinator	0:bb348c97df44	7036	#define IS_RCC_FMPI2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_FMPI2C1CLKSOURCE_PCLK1) \|\|\
lypinator	0:bb348c97df44	7037	((SOURCE) == RCC_FMPI2C1CLKSOURCE_SYSCLK) \|\|\
lypinator	0:bb348c97df44	7038	((SOURCE) == RCC_FMPI2C1CLKSOURCE_HSI))
lypinator	0:bb348c97df44	7039
lypinator	0:bb348c97df44	7040	#define IS_RCC_CLK48CLKSOURCE(SOURCE) (((SOURCE) == RCC_CLK48CLKSOURCE_PLLQ) \|\|\
lypinator	0:bb348c97df44	7041	((SOURCE) == RCC_CLK48CLKSOURCE_PLLI2SQ))
lypinator	0:bb348c97df44	7042
lypinator	0:bb348c97df44	7043	#define IS_RCC_SDIOCLKSOURCE(SOURCE) (((SOURCE) == RCC_SDIOCLKSOURCE_CLK48) \|\|\
lypinator	0:bb348c97df44	7044	((SOURCE) == RCC_SDIOCLKSOURCE_SYSCLK))
lypinator	0:bb348c97df44	7045
lypinator	0:bb348c97df44	7046	#define IS_RCC_DFSDM1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_DFSDM1CLKSOURCE_PCLK2) \|\| \
lypinator	0:bb348c97df44	7047	((__SOURCE__) == RCC_DFSDM1CLKSOURCE_SYSCLK))
lypinator	0:bb348c97df44	7048
lypinator	0:bb348c97df44	7049	#define IS_RCC_DFSDM1AUDIOCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_I2S1) \|\| \
lypinator	0:bb348c97df44	7050	((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_I2S2))
lypinator	0:bb348c97df44	7051
lypinator	0:bb348c97df44	7052	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
lypinator	0:bb348c97df44	7053	#define IS_RCC_DFSDM2CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_DFSDM2CLKSOURCE_PCLK2) \|\| \
lypinator	0:bb348c97df44	7054	((__SOURCE__) == RCC_DFSDM2CLKSOURCE_SYSCLK))
lypinator	0:bb348c97df44	7055
lypinator	0:bb348c97df44	7056	#define IS_RCC_DFSDM2AUDIOCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_DFSDM2AUDIOCLKSOURCE_I2S1) \|\| \
lypinator	0:bb348c97df44	7057	((__SOURCE__) == RCC_DFSDM2AUDIOCLKSOURCE_I2S2))
lypinator	0:bb348c97df44	7058
lypinator	0:bb348c97df44	7059	#define IS_RCC_LPTIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_LPTIM1CLKSOURCE_PCLK1) \|\|\
lypinator	0:bb348c97df44	7060	((SOURCE) == RCC_LPTIM1CLKSOURCE_HSI) \|\|\
lypinator	0:bb348c97df44	7061	((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) \|\|\
lypinator	0:bb348c97df44	7062	((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE))
lypinator	0:bb348c97df44	7063
lypinator	0:bb348c97df44	7064	#define IS_RCC_SAIACLKSOURCE(SOURCE) (((SOURCE) == RCC_SAIACLKSOURCE_PLLI2SR) \|\|\
lypinator	0:bb348c97df44	7065	((SOURCE) == RCC_SAIACLKSOURCE_EXT) \|\|\
lypinator	0:bb348c97df44	7066	((SOURCE) == RCC_SAIACLKSOURCE_PLLR) \|\|\
lypinator	0:bb348c97df44	7067	((SOURCE) == RCC_SAIACLKSOURCE_PLLSRC))
lypinator	0:bb348c97df44	7068
lypinator	0:bb348c97df44	7069	#define IS_RCC_SAIBCLKSOURCE(SOURCE) (((SOURCE) == RCC_SAIBCLKSOURCE_PLLI2SR) \|\|\
lypinator	0:bb348c97df44	7070	((SOURCE) == RCC_SAIBCLKSOURCE_EXT) \|\|\
lypinator	0:bb348c97df44	7071	((SOURCE) == RCC_SAIBCLKSOURCE_PLLR) \|\|\
lypinator	0:bb348c97df44	7072	((SOURCE) == RCC_SAIBCLKSOURCE_PLLSRC))
lypinator	0:bb348c97df44	7073
lypinator	0:bb348c97df44	7074	#define IS_RCC_PLL_DIVR_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 32U))
lypinator	0:bb348c97df44	7075
lypinator	0:bb348c97df44	7076	#define IS_RCC_PLLI2S_DIVR_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 32U))
lypinator	0:bb348c97df44	7077
lypinator	0:bb348c97df44	7078	#endif /* STM32F413xx \|\| STM32F423xx */
lypinator	0:bb348c97df44	7079	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx \|\| STM32F413xx \|\| STM32F423xx */
lypinator	0:bb348c97df44	7080
lypinator	0:bb348c97df44	7081	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\| \
lypinator	0:bb348c97df44	7082	defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| \
lypinator	0:bb348c97df44	7083	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| \
lypinator	0:bb348c97df44	7084	defined(STM32F469xx) \|\| defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| \
lypinator	0:bb348c97df44	7085	defined(STM32F412Rx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
lypinator	0:bb348c97df44	7086
lypinator	0:bb348c97df44	7087	#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) \|\| ((SOURCE) == RCC_MCO2SOURCE_PLLI2SCLK)\|\| \
lypinator	0:bb348c97df44	7088	((SOURCE) == RCC_MCO2SOURCE_HSE) \|\| ((SOURCE) == RCC_MCO2SOURCE_PLLCLK))
lypinator	0:bb348c97df44	7089
lypinator	0:bb348c97df44	7090	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\|
lypinator	0:bb348c97df44	7091	STM32F401xC \|\| STM32F401xE \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\| STM32F412Vx \|\| \
lypinator	0:bb348c97df44	7092	STM32F412Rx */
lypinator	0:bb348c97df44	7093
lypinator	0:bb348c97df44	7094	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
lypinator	0:bb348c97df44	7095	#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) \|\| ((SOURCE) == RCC_MCO2SOURCE_I2SCLK)\|\| \
lypinator	0:bb348c97df44	7096	((SOURCE) == RCC_MCO2SOURCE_HSE) \|\| ((SOURCE) == RCC_MCO2SOURCE_PLLCLK))
lypinator	0:bb348c97df44	7097	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
lypinator	0:bb348c97df44	7098	/**
lypinator	0:bb348c97df44	7099	* @}
lypinator	0:bb348c97df44	7100	*/
lypinator	0:bb348c97df44	7101
lypinator	0:bb348c97df44	7102	/**
lypinator	0:bb348c97df44	7103	* @}
lypinator	0:bb348c97df44	7104	*/
lypinator	0:bb348c97df44	7105
lypinator	0:bb348c97df44	7106	/**
lypinator	0:bb348c97df44	7107	* @}
lypinator	0:bb348c97df44	7108	*/
lypinator	0:bb348c97df44	7109
lypinator	0:bb348c97df44	7110	/**
lypinator	0:bb348c97df44	7111	* @}
lypinator	0:bb348c97df44	7112	*/
lypinator	0:bb348c97df44	7113	#ifdef __cplusplus
lypinator	0:bb348c97df44	7114	}
lypinator	0:bb348c97df44	7115	#endif
lypinator	0:bb348c97df44	7116
lypinator	0:bb348c97df44	7117	#endif /* __STM32F4xx_HAL_RCC_EX_H */
lypinator	0:bb348c97df44	7118
lypinator	0:bb348c97df44	7119	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Program
Created:	16 Sep 2020
Imports:	1
Forks:	0
Commits:	1
Dependents:	0
Dependencies:	1
Followers:	1

mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rcc_ex.h@0:bb348c97df44, 2020-09-16 (annotated)

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