DevLibMemoryController - Initial commit

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Initial commit

mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rcc_ex.c@0:bb348c97df44, 2020-09-16 (annotated)

Committer:: lypinator
Date:: Wed Sep 16 01:11:49 2020 +0000
Revision:: 0:bb348c97df44

Added PWM

Who changed what in which revision?

User	Revision	Line number	New contents of line
lypinator	0:bb348c97df44	1	/**
lypinator	0:bb348c97df44	2	******************************************************************************
lypinator	0:bb348c97df44	3	* @file stm32f4xx_hal_rcc_ex.c
lypinator	0:bb348c97df44	4	* @author MCD Application Team
lypinator	0:bb348c97df44	5	* @brief Extension RCC HAL module driver.
lypinator	0:bb348c97df44	6	* This file provides firmware functions to manage the following
lypinator	0:bb348c97df44	7	* functionalities RCC extension peripheral:
lypinator	0:bb348c97df44	8	* + Extended Peripheral Control functions
lypinator	0:bb348c97df44	9	*
lypinator	0:bb348c97df44	10	******************************************************************************
lypinator	0:bb348c97df44	11	* @attention
lypinator	0:bb348c97df44	12	*
lypinator	0:bb348c97df44	13	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
lypinator	0:bb348c97df44	14	*
lypinator	0:bb348c97df44	15	* Redistribution and use in source and binary forms, with or without modification,
lypinator	0:bb348c97df44	16	* are permitted provided that the following conditions are met:
lypinator	0:bb348c97df44	17	* 1. Redistributions of source code must retain the above copyright notice,
lypinator	0:bb348c97df44	18	* this list of conditions and the following disclaimer.
lypinator	0:bb348c97df44	19	* 2. Redistributions in binary form must reproduce the above copyright notice,
lypinator	0:bb348c97df44	20	* this list of conditions and the following disclaimer in the documentation
lypinator	0:bb348c97df44	21	* and/or other materials provided with the distribution.
lypinator	0:bb348c97df44	22	* 3. Neither the name of STMicroelectronics nor the names of its contributors
lypinator	0:bb348c97df44	23	* may be used to endorse or promote products derived from this software
lypinator	0:bb348c97df44	24	* without specific prior written permission.
lypinator	0:bb348c97df44	25	*
lypinator	0:bb348c97df44	26	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
lypinator	0:bb348c97df44	27	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
lypinator	0:bb348c97df44	28	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
lypinator	0:bb348c97df44	29	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
lypinator	0:bb348c97df44	30	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
lypinator	0:bb348c97df44	31	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
lypinator	0:bb348c97df44	32	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
lypinator	0:bb348c97df44	33	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
lypinator	0:bb348c97df44	34	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
lypinator	0:bb348c97df44	35	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
lypinator	0:bb348c97df44	36	*
lypinator	0:bb348c97df44	37	******************************************************************************
lypinator	0:bb348c97df44	38	*/
lypinator	0:bb348c97df44	39
lypinator	0:bb348c97df44	40	/* Includes ------------------------------------------------------------------*/
lypinator	0:bb348c97df44	41	#include "stm32f4xx_hal.h"
lypinator	0:bb348c97df44	42
lypinator	0:bb348c97df44	43	/** @addtogroup STM32F4xx_HAL_Driver
lypinator	0:bb348c97df44	44	* @{
lypinator	0:bb348c97df44	45	*/
lypinator	0:bb348c97df44	46
lypinator	0:bb348c97df44	47	/** @defgroup RCCEx RCCEx
lypinator	0:bb348c97df44	48	* @brief RCCEx HAL module driver
lypinator	0:bb348c97df44	49	* @{
lypinator	0:bb348c97df44	50	*/
lypinator	0:bb348c97df44	51
lypinator	0:bb348c97df44	52	#ifdef HAL_RCC_MODULE_ENABLED
lypinator	0:bb348c97df44	53
lypinator	0:bb348c97df44	54	/* Private typedef -----------------------------------------------------------*/
lypinator	0:bb348c97df44	55	/* Private define ------------------------------------------------------------*/
lypinator	0:bb348c97df44	56	/** @addtogroup RCCEx_Private_Constants
lypinator	0:bb348c97df44	57	* @{
lypinator	0:bb348c97df44	58	*/
lypinator	0:bb348c97df44	59	/**
lypinator	0:bb348c97df44	60	* @}
lypinator	0:bb348c97df44	61	*/
lypinator	0:bb348c97df44	62	/* Private macro -------------------------------------------------------------*/
lypinator	0:bb348c97df44	63	/* Private variables ---------------------------------------------------------*/
lypinator	0:bb348c97df44	64	/* Private function prototypes -----------------------------------------------*/
lypinator	0:bb348c97df44	65	/* Private functions ---------------------------------------------------------*/
lypinator	0:bb348c97df44	66	/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions
lypinator	0:bb348c97df44	67	* @{
lypinator	0:bb348c97df44	68	*/
lypinator	0:bb348c97df44	69
lypinator	0:bb348c97df44	70	/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions
lypinator	0:bb348c97df44	71	* @brief Extended Peripheral Control functions
lypinator	0:bb348c97df44	72	*
lypinator	0:bb348c97df44	73	@verbatim
lypinator	0:bb348c97df44	74	===============================================================================
lypinator	0:bb348c97df44	75	##### Extended Peripheral Control functions #####
lypinator	0:bb348c97df44	76	===============================================================================
lypinator	0:bb348c97df44	77	[..]
lypinator	0:bb348c97df44	78	This subsection provides a set of functions allowing to control the RCC Clocks
lypinator	0:bb348c97df44	79	frequencies.
lypinator	0:bb348c97df44	80	[..]
lypinator	0:bb348c97df44	81	(@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
lypinator	0:bb348c97df44	82	select the RTC clock source; in this case the Backup domain will be reset in
lypinator	0:bb348c97df44	83	order to modify the RTC Clock source, as consequence RTC registers (including
lypinator	0:bb348c97df44	84	the backup registers) and RCC_BDCR register are set to their reset values.
lypinator	0:bb348c97df44	85
lypinator	0:bb348c97df44	86	@endverbatim
lypinator	0:bb348c97df44	87	* @{
lypinator	0:bb348c97df44	88	*/
lypinator	0:bb348c97df44	89
lypinator	0:bb348c97df44	90	#if defined(STM32F446xx)
lypinator	0:bb348c97df44	91	/**
lypinator	0:bb348c97df44	92	* @brief Initializes the RCC extended peripherals clocks according to the specified
lypinator	0:bb348c97df44	93	* parameters in the RCC_PeriphCLKInitTypeDef.
lypinator	0:bb348c97df44	94	* @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
lypinator	0:bb348c97df44	95	* contains the configuration information for the Extended Peripherals
lypinator	0:bb348c97df44	96	* clocks(I2S, SAI, LTDC RTC and TIM).
lypinator	0:bb348c97df44	97	*
lypinator	0:bb348c97df44	98	* @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
lypinator	0:bb348c97df44	99	* the RTC clock source; in this case the Backup domain will be reset in
lypinator	0:bb348c97df44	100	* order to modify the RTC Clock source, as consequence RTC registers (including
lypinator	0:bb348c97df44	101	* the backup registers) and RCC_BDCR register are set to their reset values.
lypinator	0:bb348c97df44	102	*
lypinator	0:bb348c97df44	103	* @retval HAL status
lypinator	0:bb348c97df44	104	*/
lypinator	0:bb348c97df44	105	HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
lypinator	0:bb348c97df44	106	{
lypinator	0:bb348c97df44	107	uint32_t tickstart = 0U;
lypinator	0:bb348c97df44	108	uint32_t tmpreg1 = 0U;
lypinator	0:bb348c97df44	109	uint32_t plli2sp = 0U;
lypinator	0:bb348c97df44	110	uint32_t plli2sq = 0U;
lypinator	0:bb348c97df44	111	uint32_t plli2sr = 0U;
lypinator	0:bb348c97df44	112	uint32_t pllsaip = 0U;
lypinator	0:bb348c97df44	113	uint32_t pllsaiq = 0U;
lypinator	0:bb348c97df44	114	uint32_t plli2sused = 0U;
lypinator	0:bb348c97df44	115	uint32_t pllsaiused = 0U;
lypinator	0:bb348c97df44	116
lypinator	0:bb348c97df44	117	/* Check the peripheral clock selection parameters */
lypinator	0:bb348c97df44	118	assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
lypinator	0:bb348c97df44	119
lypinator	0:bb348c97df44	120	/------------------------ I2S APB1 configuration --------------------------/
lypinator	0:bb348c97df44	121	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == (RCC_PERIPHCLK_I2S_APB1))
lypinator	0:bb348c97df44	122	{
lypinator	0:bb348c97df44	123	/* Check the parameters */
lypinator	0:bb348c97df44	124	assert_param(IS_RCC_I2SAPB1CLKSOURCE(PeriphClkInit->I2sApb1ClockSelection));
lypinator	0:bb348c97df44	125
lypinator	0:bb348c97df44	126	/* Configure I2S Clock source */
lypinator	0:bb348c97df44	127	__HAL_RCC_I2S_APB1_CONFIG(PeriphClkInit->I2sApb1ClockSelection);
lypinator	0:bb348c97df44	128	/* Enable the PLLI2S when it's used as clock source for I2S */
lypinator	0:bb348c97df44	129	if(PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S)
lypinator	0:bb348c97df44	130	{
lypinator	0:bb348c97df44	131	plli2sused = 1U;
lypinator	0:bb348c97df44	132	}
lypinator	0:bb348c97df44	133	}
lypinator	0:bb348c97df44	134	/--------------------------------------------------------------------------/
lypinator	0:bb348c97df44	135
lypinator	0:bb348c97df44	136	/---------------------------- I2S APB2 configuration ----------------------/
lypinator	0:bb348c97df44	137	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == (RCC_PERIPHCLK_I2S_APB2))
lypinator	0:bb348c97df44	138	{
lypinator	0:bb348c97df44	139	/* Check the parameters */
lypinator	0:bb348c97df44	140	assert_param(IS_RCC_I2SAPB2CLKSOURCE(PeriphClkInit->I2sApb2ClockSelection));
lypinator	0:bb348c97df44	141
lypinator	0:bb348c97df44	142	/* Configure I2S Clock source */
lypinator	0:bb348c97df44	143	__HAL_RCC_I2S_APB2_CONFIG(PeriphClkInit->I2sApb2ClockSelection);
lypinator	0:bb348c97df44	144	/* Enable the PLLI2S when it's used as clock source for I2S */
lypinator	0:bb348c97df44	145	if(PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S)
lypinator	0:bb348c97df44	146	{
lypinator	0:bb348c97df44	147	plli2sused = 1U;
lypinator	0:bb348c97df44	148	}
lypinator	0:bb348c97df44	149	}
lypinator	0:bb348c97df44	150	/--------------------------------------------------------------------------/
lypinator	0:bb348c97df44	151
lypinator	0:bb348c97df44	152	/--------------------------- SAI1 configuration ---------------------------/
lypinator	0:bb348c97df44	153	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == (RCC_PERIPHCLK_SAI1))
lypinator	0:bb348c97df44	154	{
lypinator	0:bb348c97df44	155	/* Check the parameters */
lypinator	0:bb348c97df44	156	assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection));
lypinator	0:bb348c97df44	157
lypinator	0:bb348c97df44	158	/* Configure SAI1 Clock source */
lypinator	0:bb348c97df44	159	__HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
lypinator	0:bb348c97df44	160	/* Enable the PLLI2S when it's used as clock source for SAI */
lypinator	0:bb348c97df44	161	if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)
lypinator	0:bb348c97df44	162	{
lypinator	0:bb348c97df44	163	plli2sused = 1U;
lypinator	0:bb348c97df44	164	}
lypinator	0:bb348c97df44	165	/* Enable the PLLSAI when it's used as clock source for SAI */
lypinator	0:bb348c97df44	166	if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)
lypinator	0:bb348c97df44	167	{
lypinator	0:bb348c97df44	168	pllsaiused = 1U;
lypinator	0:bb348c97df44	169	}
lypinator	0:bb348c97df44	170	}
lypinator	0:bb348c97df44	171	/--------------------------------------------------------------------------/
lypinator	0:bb348c97df44	172
lypinator	0:bb348c97df44	173	/-------------------------- SAI2 configuration ----------------------------/
lypinator	0:bb348c97df44	174	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == (RCC_PERIPHCLK_SAI2))
lypinator	0:bb348c97df44	175	{
lypinator	0:bb348c97df44	176	/* Check the parameters */
lypinator	0:bb348c97df44	177	assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection));
lypinator	0:bb348c97df44	178
lypinator	0:bb348c97df44	179	/* Configure SAI2 Clock source */
lypinator	0:bb348c97df44	180	__HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection);
lypinator	0:bb348c97df44	181
lypinator	0:bb348c97df44	182	/* Enable the PLLI2S when it's used as clock source for SAI */
lypinator	0:bb348c97df44	183	if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)
lypinator	0:bb348c97df44	184	{
lypinator	0:bb348c97df44	185	plli2sused = 1U;
lypinator	0:bb348c97df44	186	}
lypinator	0:bb348c97df44	187	/* Enable the PLLSAI when it's used as clock source for SAI */
lypinator	0:bb348c97df44	188	if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)
lypinator	0:bb348c97df44	189	{
lypinator	0:bb348c97df44	190	pllsaiused = 1U;
lypinator	0:bb348c97df44	191	}
lypinator	0:bb348c97df44	192	}
lypinator	0:bb348c97df44	193	/--------------------------------------------------------------------------/
lypinator	0:bb348c97df44	194
lypinator	0:bb348c97df44	195	/----------------------------- RTC configuration --------------------------/
lypinator	0:bb348c97df44	196	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
lypinator	0:bb348c97df44	197	{
lypinator	0:bb348c97df44	198	/* Check for RTC Parameters used to output RTCCLK */
lypinator	0:bb348c97df44	199	assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
lypinator	0:bb348c97df44	200
lypinator	0:bb348c97df44	201	/* Enable Power Clock*/
lypinator	0:bb348c97df44	202	__HAL_RCC_PWR_CLK_ENABLE();
lypinator	0:bb348c97df44	203
lypinator	0:bb348c97df44	204	/* Enable write access to Backup domain */
lypinator	0:bb348c97df44	205	PWR->CR \|= PWR_CR_DBP;
lypinator	0:bb348c97df44	206
lypinator	0:bb348c97df44	207	/* Get tick */
lypinator	0:bb348c97df44	208	tickstart = HAL_GetTick();
lypinator	0:bb348c97df44	209
lypinator	0:bb348c97df44	210	while((PWR->CR & PWR_CR_DBP) == RESET)
lypinator	0:bb348c97df44	211	{
lypinator	0:bb348c97df44	212	if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
lypinator	0:bb348c97df44	213	{
lypinator	0:bb348c97df44	214	return HAL_TIMEOUT;
lypinator	0:bb348c97df44	215	}
lypinator	0:bb348c97df44	216	}
lypinator	0:bb348c97df44	217	/* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
lypinator	0:bb348c97df44	218	tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL);
lypinator	0:bb348c97df44	219	if((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
lypinator	0:bb348c97df44	220	{
lypinator	0:bb348c97df44	221	/* Store the content of BDCR register before the reset of Backup Domain */
lypinator	0:bb348c97df44	222	tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
lypinator	0:bb348c97df44	223	/* RTC Clock selection can be changed only if the Backup Domain is reset */
lypinator	0:bb348c97df44	224	__HAL_RCC_BACKUPRESET_FORCE();
lypinator	0:bb348c97df44	225	__HAL_RCC_BACKUPRESET_RELEASE();
lypinator	0:bb348c97df44	226	/* Restore the Content of BDCR register */
lypinator	0:bb348c97df44	227	RCC->BDCR = tmpreg1;
lypinator	0:bb348c97df44	228
lypinator	0:bb348c97df44	229	/* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
lypinator	0:bb348c97df44	230	if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))
lypinator	0:bb348c97df44	231	{
lypinator	0:bb348c97df44	232	/* Get tick */
lypinator	0:bb348c97df44	233	tickstart = HAL_GetTick();
lypinator	0:bb348c97df44	234
lypinator	0:bb348c97df44	235	/* Wait till LSE is ready */
lypinator	0:bb348c97df44	236	while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
lypinator	0:bb348c97df44	237	{
lypinator	0:bb348c97df44	238	if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
lypinator	0:bb348c97df44	239	{
lypinator	0:bb348c97df44	240	return HAL_TIMEOUT;
lypinator	0:bb348c97df44	241	}
lypinator	0:bb348c97df44	242	}
lypinator	0:bb348c97df44	243	}
lypinator	0:bb348c97df44	244	}
lypinator	0:bb348c97df44	245	__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
lypinator	0:bb348c97df44	246	}
lypinator	0:bb348c97df44	247	/--------------------------------------------------------------------------/
lypinator	0:bb348c97df44	248
lypinator	0:bb348c97df44	249	/---------------------------- TIM configuration ---------------------------/
lypinator	0:bb348c97df44	250	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
lypinator	0:bb348c97df44	251	{
lypinator	0:bb348c97df44	252	/* Configure Timer Prescaler */
lypinator	0:bb348c97df44	253	__HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
lypinator	0:bb348c97df44	254	}
lypinator	0:bb348c97df44	255	/--------------------------------------------------------------------------/
lypinator	0:bb348c97df44	256
lypinator	0:bb348c97df44	257	/---------------------------- FMPI2C1 Configuration -----------------------/
lypinator	0:bb348c97df44	258	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMPI2C1) == RCC_PERIPHCLK_FMPI2C1)
lypinator	0:bb348c97df44	259	{
lypinator	0:bb348c97df44	260	/* Check the parameters */
lypinator	0:bb348c97df44	261	assert_param(IS_RCC_FMPI2C1CLKSOURCE(PeriphClkInit->Fmpi2c1ClockSelection));
lypinator	0:bb348c97df44	262
lypinator	0:bb348c97df44	263	/* Configure the FMPI2C1 clock source */
lypinator	0:bb348c97df44	264	__HAL_RCC_FMPI2C1_CONFIG(PeriphClkInit->Fmpi2c1ClockSelection);
lypinator	0:bb348c97df44	265	}
lypinator	0:bb348c97df44	266	/--------------------------------------------------------------------------/
lypinator	0:bb348c97df44	267
lypinator	0:bb348c97df44	268	/------------------------------ CEC Configuration -------------------------/
lypinator	0:bb348c97df44	269	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC)
lypinator	0:bb348c97df44	270	{
lypinator	0:bb348c97df44	271	/* Check the parameters */
lypinator	0:bb348c97df44	272	assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection));
lypinator	0:bb348c97df44	273
lypinator	0:bb348c97df44	274	/* Configure the CEC clock source */
lypinator	0:bb348c97df44	275	__HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection);
lypinator	0:bb348c97df44	276	}
lypinator	0:bb348c97df44	277	/--------------------------------------------------------------------------/
lypinator	0:bb348c97df44	278
lypinator	0:bb348c97df44	279	/----------------------------- CLK48 Configuration ------------------------/
lypinator	0:bb348c97df44	280	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48)
lypinator	0:bb348c97df44	281	{
lypinator	0:bb348c97df44	282	/* Check the parameters */
lypinator	0:bb348c97df44	283	assert_param(IS_RCC_CLK48CLKSOURCE(PeriphClkInit->Clk48ClockSelection));
lypinator	0:bb348c97df44	284
lypinator	0:bb348c97df44	285	/* Configure the CLK48 clock source */
lypinator	0:bb348c97df44	286	__HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection);
lypinator	0:bb348c97df44	287
lypinator	0:bb348c97df44	288	/* Enable the PLLSAI when it's used as clock source for CLK48 */
lypinator	0:bb348c97df44	289	if(PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLSAIP)
lypinator	0:bb348c97df44	290	{
lypinator	0:bb348c97df44	291	pllsaiused = 1U;
lypinator	0:bb348c97df44	292	}
lypinator	0:bb348c97df44	293	}
lypinator	0:bb348c97df44	294	/--------------------------------------------------------------------------/
lypinator	0:bb348c97df44	295
lypinator	0:bb348c97df44	296	/----------------------------- SDIO Configuration -------------------------/
lypinator	0:bb348c97df44	297	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDIO) == RCC_PERIPHCLK_SDIO)
lypinator	0:bb348c97df44	298	{
lypinator	0:bb348c97df44	299	/* Check the parameters */
lypinator	0:bb348c97df44	300	assert_param(IS_RCC_SDIOCLKSOURCE(PeriphClkInit->SdioClockSelection));
lypinator	0:bb348c97df44	301
lypinator	0:bb348c97df44	302	/* Configure the SDIO clock source */
lypinator	0:bb348c97df44	303	__HAL_RCC_SDIO_CONFIG(PeriphClkInit->SdioClockSelection);
lypinator	0:bb348c97df44	304	}
lypinator	0:bb348c97df44	305	/--------------------------------------------------------------------------/
lypinator	0:bb348c97df44	306
lypinator	0:bb348c97df44	307	/------------------------------ SPDIFRX Configuration ---------------------/
lypinator	0:bb348c97df44	308	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)
lypinator	0:bb348c97df44	309	{
lypinator	0:bb348c97df44	310	/* Check the parameters */
lypinator	0:bb348c97df44	311	assert_param(IS_RCC_SPDIFRXCLKSOURCE(PeriphClkInit->SpdifClockSelection));
lypinator	0:bb348c97df44	312
lypinator	0:bb348c97df44	313	/* Configure the SPDIFRX clock source */
lypinator	0:bb348c97df44	314	__HAL_RCC_SPDIFRX_CONFIG(PeriphClkInit->SpdifClockSelection);
lypinator	0:bb348c97df44	315	/* Enable the PLLI2S when it's used as clock source for SPDIFRX */
lypinator	0:bb348c97df44	316	if(PeriphClkInit->SpdifClockSelection == RCC_SPDIFRXCLKSOURCE_PLLI2SP)
lypinator	0:bb348c97df44	317	{
lypinator	0:bb348c97df44	318	plli2sused = 1U;
lypinator	0:bb348c97df44	319	}
lypinator	0:bb348c97df44	320	}
lypinator	0:bb348c97df44	321	/--------------------------------------------------------------------------/
lypinator	0:bb348c97df44	322
lypinator	0:bb348c97df44	323	/---------------------------- PLLI2S Configuration ------------------------/
lypinator	0:bb348c97df44	324	/* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2, I2S on APB1,
lypinator	0:bb348c97df44	325	I2S on APB2 or SPDIFRX */
lypinator	0:bb348c97df44	326	if((plli2sused == 1U) \|\| (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S))
lypinator	0:bb348c97df44	327	{
lypinator	0:bb348c97df44	328	/* Disable the PLLI2S */
lypinator	0:bb348c97df44	329	__HAL_RCC_PLLI2S_DISABLE();
lypinator	0:bb348c97df44	330	/* Get tick */
lypinator	0:bb348c97df44	331	tickstart = HAL_GetTick();
lypinator	0:bb348c97df44	332	/* Wait till PLLI2S is disabled */
lypinator	0:bb348c97df44	333	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
lypinator	0:bb348c97df44	334	{
lypinator	0:bb348c97df44	335	if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
lypinator	0:bb348c97df44	336	{
lypinator	0:bb348c97df44	337	/* return in case of Timeout detected */
lypinator	0:bb348c97df44	338	return HAL_TIMEOUT;
lypinator	0:bb348c97df44	339	}
lypinator	0:bb348c97df44	340	}
lypinator	0:bb348c97df44	341
lypinator	0:bb348c97df44	342	/* check for common PLLI2S Parameters */
lypinator	0:bb348c97df44	343	assert_param(IS_RCC_PLLI2SM_VALUE(PeriphClkInit->PLLI2S.PLLI2SM));
lypinator	0:bb348c97df44	344	assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
lypinator	0:bb348c97df44	345
lypinator	0:bb348c97df44	346	/------ In Case of PLLI2S is selected as source clock for I2S -----------/
lypinator	0:bb348c97df44	347	if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == RCC_PERIPHCLK_I2S_APB1) && (PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S)) \|\|
lypinator	0:bb348c97df44	348	((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == RCC_PERIPHCLK_I2S_APB2) && (PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S)))
lypinator	0:bb348c97df44	349	{
lypinator	0:bb348c97df44	350	/* check for Parameters */
lypinator	0:bb348c97df44	351	assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
lypinator	0:bb348c97df44	352
lypinator	0:bb348c97df44	353	/* Read PLLI2SP/PLLI2SQ value from PLLI2SCFGR register (this value is not needed for I2S configuration) */
lypinator	0:bb348c97df44	354	plli2sp = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) << 1U);
lypinator	0:bb348c97df44	355	plli2sq = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos);
lypinator	0:bb348c97df44	356	/* Configure the PLLI2S division factors */
lypinator	0:bb348c97df44	357	/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */
lypinator	0:bb348c97df44	358	/* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
lypinator	0:bb348c97df44	359	__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , plli2sp, plli2sq, PeriphClkInit->PLLI2S.PLLI2SR);
lypinator	0:bb348c97df44	360	}
lypinator	0:bb348c97df44	361
lypinator	0:bb348c97df44	362	/------- In Case of PLLI2S is selected as source clock for SAI ----------/
lypinator	0:bb348c97df44	363	if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) \|\|
lypinator	0:bb348c97df44	364	((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)))
lypinator	0:bb348c97df44	365	{
lypinator	0:bb348c97df44	366	/* Check for PLLI2S Parameters */
lypinator	0:bb348c97df44	367	assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
lypinator	0:bb348c97df44	368	/* Check for PLLI2S/DIVQ parameters */
lypinator	0:bb348c97df44	369	assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ));
lypinator	0:bb348c97df44	370
lypinator	0:bb348c97df44	371	/* Read PLLI2SP/PLLI2SR value from PLLI2SCFGR register (this value is not needed for SAI configuration) */
lypinator	0:bb348c97df44	372	plli2sp = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) << 1U);
lypinator	0:bb348c97df44	373	plli2sr = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
lypinator	0:bb348c97df44	374	/* Configure the PLLI2S division factors */
lypinator	0:bb348c97df44	375	/* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */
lypinator	0:bb348c97df44	376	/* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
lypinator	0:bb348c97df44	377	/* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
lypinator	0:bb348c97df44	378	__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , plli2sp, PeriphClkInit->PLLI2S.PLLI2SQ, plli2sr);
lypinator	0:bb348c97df44	379
lypinator	0:bb348c97df44	380	/* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
lypinator	0:bb348c97df44	381	__HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ);
lypinator	0:bb348c97df44	382	}
lypinator	0:bb348c97df44	383
lypinator	0:bb348c97df44	384	/------ In Case of PLLI2S is selected as source clock for SPDIFRX -------/
lypinator	0:bb348c97df44	385	if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) && (PeriphClkInit->SpdifClockSelection == RCC_SPDIFRXCLKSOURCE_PLLI2SP))
lypinator	0:bb348c97df44	386	{
lypinator	0:bb348c97df44	387	/* check for Parameters */
lypinator	0:bb348c97df44	388	assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP));
lypinator	0:bb348c97df44	389	/* Read PLLI2SR value from PLLI2SCFGR register (this value is not need for SAI configuration) */
lypinator	0:bb348c97df44	390	plli2sq = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) << 1U);
lypinator	0:bb348c97df44	391	plli2sr = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
lypinator	0:bb348c97df44	392	/* Configure the PLLI2S division factors */
lypinator	0:bb348c97df44	393	/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */
lypinator	0:bb348c97df44	394	/* SPDIFRXCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */
lypinator	0:bb348c97df44	395	__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, plli2sq, plli2sr);
lypinator	0:bb348c97df44	396	}
lypinator	0:bb348c97df44	397
lypinator	0:bb348c97df44	398	/----------------- In Case of PLLI2S is just selected -----------------/
lypinator	0:bb348c97df44	399	if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)
lypinator	0:bb348c97df44	400	{
lypinator	0:bb348c97df44	401	/* Check for Parameters */
lypinator	0:bb348c97df44	402	assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP));
lypinator	0:bb348c97df44	403	assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
lypinator	0:bb348c97df44	404	assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
lypinator	0:bb348c97df44	405
lypinator	0:bb348c97df44	406	/* Configure the PLLI2S division factors */
lypinator	0:bb348c97df44	407	/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */
lypinator	0:bb348c97df44	408	__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR);
lypinator	0:bb348c97df44	409	}
lypinator	0:bb348c97df44	410
lypinator	0:bb348c97df44	411	/* Enable the PLLI2S */
lypinator	0:bb348c97df44	412	__HAL_RCC_PLLI2S_ENABLE();
lypinator	0:bb348c97df44	413	/* Get tick */
lypinator	0:bb348c97df44	414	tickstart = HAL_GetTick();
lypinator	0:bb348c97df44	415	/* Wait till PLLI2S is ready */
lypinator	0:bb348c97df44	416	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
lypinator	0:bb348c97df44	417	{
lypinator	0:bb348c97df44	418	if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
lypinator	0:bb348c97df44	419	{
lypinator	0:bb348c97df44	420	/* return in case of Timeout detected */
lypinator	0:bb348c97df44	421	return HAL_TIMEOUT;
lypinator	0:bb348c97df44	422	}
lypinator	0:bb348c97df44	423	}
lypinator	0:bb348c97df44	424	}
lypinator	0:bb348c97df44	425	/--------------------------------------------------------------------------/
lypinator	0:bb348c97df44	426
lypinator	0:bb348c97df44	427	/----------------------------- PLLSAI Configuration -----------------------/
lypinator	0:bb348c97df44	428	/* PLLSAI is configured when a peripheral will use it as source clock : SAI1, SAI2, CLK48 or SDIO */
lypinator	0:bb348c97df44	429	if(pllsaiused == 1U)
lypinator	0:bb348c97df44	430	{
lypinator	0:bb348c97df44	431	/* Disable PLLSAI Clock */
lypinator	0:bb348c97df44	432	__HAL_RCC_PLLSAI_DISABLE();
lypinator	0:bb348c97df44	433	/* Get tick */
lypinator	0:bb348c97df44	434	tickstart = HAL_GetTick();
lypinator	0:bb348c97df44	435	/* Wait till PLLSAI is disabled */
lypinator	0:bb348c97df44	436	while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
lypinator	0:bb348c97df44	437	{
lypinator	0:bb348c97df44	438	if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
lypinator	0:bb348c97df44	439	{
lypinator	0:bb348c97df44	440	/* return in case of Timeout detected */
lypinator	0:bb348c97df44	441	return HAL_TIMEOUT;
lypinator	0:bb348c97df44	442	}
lypinator	0:bb348c97df44	443	}
lypinator	0:bb348c97df44	444
lypinator	0:bb348c97df44	445	/* Check the PLLSAI division factors */
lypinator	0:bb348c97df44	446	assert_param(IS_RCC_PLLSAIM_VALUE(PeriphClkInit->PLLSAI.PLLSAIM));
lypinator	0:bb348c97df44	447	assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN));
lypinator	0:bb348c97df44	448
lypinator	0:bb348c97df44	449	/------ In Case of PLLSAI is selected as source clock for SAI -----------/
lypinator	0:bb348c97df44	450	if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) \|\|
lypinator	0:bb348c97df44	451	((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)))
lypinator	0:bb348c97df44	452	{
lypinator	0:bb348c97df44	453	/* check for PLLSAIQ Parameter */
lypinator	0:bb348c97df44	454	assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ));
lypinator	0:bb348c97df44	455	/* check for PLLSAI/DIVQ Parameter */
lypinator	0:bb348c97df44	456	assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ));
lypinator	0:bb348c97df44	457
lypinator	0:bb348c97df44	458	/* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */
lypinator	0:bb348c97df44	459	pllsaip = ((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos) + 1U) << 1U);
lypinator	0:bb348c97df44	460	/* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
lypinator	0:bb348c97df44	461	/* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
lypinator	0:bb348c97df44	462	/* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
lypinator	0:bb348c97df44	463	__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIM, PeriphClkInit->PLLSAI.PLLSAIN , pllsaip, PeriphClkInit->PLLSAI.PLLSAIQ, 0U);
lypinator	0:bb348c97df44	464
lypinator	0:bb348c97df44	465	/* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
lypinator	0:bb348c97df44	466	__HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ);
lypinator	0:bb348c97df44	467	}
lypinator	0:bb348c97df44	468
lypinator	0:bb348c97df44	469	/------ In Case of PLLSAI is selected as source clock for CLK48 ---------/
lypinator	0:bb348c97df44	470	/* In Case of PLLI2S is selected as source clock for CLK48 */
lypinator	0:bb348c97df44	471	if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLSAIP))
lypinator	0:bb348c97df44	472	{
lypinator	0:bb348c97df44	473	/* check for Parameters */
lypinator	0:bb348c97df44	474	assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP));
lypinator	0:bb348c97df44	475	/* Read PLLSAIQ value from PLLI2SCFGR register (this value is not need for SAI configuration) */
lypinator	0:bb348c97df44	476	pllsaiq = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);
lypinator	0:bb348c97df44	477	/* Configure the PLLSAI division factors */
lypinator	0:bb348c97df44	478	/* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) * (PLLI2SN/PLLSAIM) */
lypinator	0:bb348c97df44	479	/* 48CLK = f(PLLSAI clock output) = f(VCO clock) / PLLSAIP */
lypinator	0:bb348c97df44	480	__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIM, PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIP, pllsaiq, 0U);
lypinator	0:bb348c97df44	481	}
lypinator	0:bb348c97df44	482
lypinator	0:bb348c97df44	483	/* Enable PLLSAI Clock */
lypinator	0:bb348c97df44	484	__HAL_RCC_PLLSAI_ENABLE();
lypinator	0:bb348c97df44	485	/* Get tick */
lypinator	0:bb348c97df44	486	tickstart = HAL_GetTick();
lypinator	0:bb348c97df44	487	/* Wait till PLLSAI is ready */
lypinator	0:bb348c97df44	488	while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
lypinator	0:bb348c97df44	489	{
lypinator	0:bb348c97df44	490	if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
lypinator	0:bb348c97df44	491	{
lypinator	0:bb348c97df44	492	/* return in case of Timeout detected */
lypinator	0:bb348c97df44	493	return HAL_TIMEOUT;
lypinator	0:bb348c97df44	494	}
lypinator	0:bb348c97df44	495	}
lypinator	0:bb348c97df44	496	}
lypinator	0:bb348c97df44	497	return HAL_OK;
lypinator	0:bb348c97df44	498	}
lypinator	0:bb348c97df44	499
lypinator	0:bb348c97df44	500	/**
lypinator	0:bb348c97df44	501	* @brief Get the RCC_PeriphCLKInitTypeDef according to the internal
lypinator	0:bb348c97df44	502	* RCC configuration registers.
lypinator	0:bb348c97df44	503	* @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
lypinator	0:bb348c97df44	504	* will be configured.
lypinator	0:bb348c97df44	505	* @retval None
lypinator	0:bb348c97df44	506	*/
lypinator	0:bb348c97df44	507	void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
lypinator	0:bb348c97df44	508	{
lypinator	0:bb348c97df44	509	uint32_t tempreg;
lypinator	0:bb348c97df44	510
lypinator	0:bb348c97df44	511	/* Set all possible values for the extended clock type parameter------------*/
lypinator	0:bb348c97df44	512	PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S_APB1 \| RCC_PERIPHCLK_I2S_APB2 \|\
lypinator	0:bb348c97df44	513	RCC_PERIPHCLK_SAI1 \| RCC_PERIPHCLK_SAI2 \|\
lypinator	0:bb348c97df44	514	RCC_PERIPHCLK_TIM \| RCC_PERIPHCLK_RTC \|\
lypinator	0:bb348c97df44	515	RCC_PERIPHCLK_CEC \| RCC_PERIPHCLK_FMPI2C1 \|\
lypinator	0:bb348c97df44	516	RCC_PERIPHCLK_CLK48 \| RCC_PERIPHCLK_SDIO \|\
lypinator	0:bb348c97df44	517	RCC_PERIPHCLK_SPDIFRX;
lypinator	0:bb348c97df44	518
lypinator	0:bb348c97df44	519	/* Get the PLLI2S Clock configuration --------------------------------------*/
lypinator	0:bb348c97df44	520	PeriphClkInit->PLLI2S.PLLI2SM = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM) >> RCC_PLLI2SCFGR_PLLI2SM_Pos);
lypinator	0:bb348c97df44	521	PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos);
lypinator	0:bb348c97df44	522	PeriphClkInit->PLLI2S.PLLI2SP = (uint32_t)((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) << 1U);
lypinator	0:bb348c97df44	523	PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos);
lypinator	0:bb348c97df44	524	PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
lypinator	0:bb348c97df44	525	/* Get the PLLSAI Clock configuration --------------------------------------*/
lypinator	0:bb348c97df44	526	PeriphClkInit->PLLSAI.PLLSAIM = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIM) >> RCC_PLLSAICFGR_PLLSAIM_Pos);
lypinator	0:bb348c97df44	527	PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> RCC_PLLSAICFGR_PLLSAIN_Pos);
lypinator	0:bb348c97df44	528	PeriphClkInit->PLLSAI.PLLSAIP = (uint32_t)((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos) + 1U) << 1U);
lypinator	0:bb348c97df44	529	PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);
lypinator	0:bb348c97df44	530	/* Get the PLLSAI/PLLI2S division factors ----------------------------------*/
lypinator	0:bb348c97df44	531	PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) >> RCC_DCKCFGR_PLLI2SDIVQ_Pos);
lypinator	0:bb348c97df44	532	PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> RCC_DCKCFGR_PLLSAIDIVQ_Pos);
lypinator	0:bb348c97df44	533
lypinator	0:bb348c97df44	534	/* Get the SAI1 clock configuration ----------------------------------------*/
lypinator	0:bb348c97df44	535	PeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE();
lypinator	0:bb348c97df44	536
lypinator	0:bb348c97df44	537	/* Get the SAI2 clock configuration ----------------------------------------*/
lypinator	0:bb348c97df44	538	PeriphClkInit->Sai2ClockSelection = __HAL_RCC_GET_SAI2_SOURCE();
lypinator	0:bb348c97df44	539
lypinator	0:bb348c97df44	540	/* Get the I2S APB1 clock configuration ------------------------------------*/
lypinator	0:bb348c97df44	541	PeriphClkInit->I2sApb1ClockSelection = __HAL_RCC_GET_I2S_APB1_SOURCE();
lypinator	0:bb348c97df44	542
lypinator	0:bb348c97df44	543	/* Get the I2S APB2 clock configuration ------------------------------------*/
lypinator	0:bb348c97df44	544	PeriphClkInit->I2sApb2ClockSelection = __HAL_RCC_GET_I2S_APB2_SOURCE();
lypinator	0:bb348c97df44	545
lypinator	0:bb348c97df44	546	/* Get the RTC Clock configuration -----------------------------------------*/
lypinator	0:bb348c97df44	547	tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
lypinator	0:bb348c97df44	548	PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) \| (RCC->BDCR & RCC_BDCR_RTCSEL));
lypinator	0:bb348c97df44	549
lypinator	0:bb348c97df44	550	/* Get the CEC clock configuration -----------------------------------------*/
lypinator	0:bb348c97df44	551	PeriphClkInit->CecClockSelection = __HAL_RCC_GET_CEC_SOURCE();
lypinator	0:bb348c97df44	552
lypinator	0:bb348c97df44	553	/* Get the FMPI2C1 clock configuration -------------------------------------*/
lypinator	0:bb348c97df44	554	PeriphClkInit->Fmpi2c1ClockSelection = __HAL_RCC_GET_FMPI2C1_SOURCE();
lypinator	0:bb348c97df44	555
lypinator	0:bb348c97df44	556	/* Get the CLK48 clock configuration ----------------------------------------*/
lypinator	0:bb348c97df44	557	PeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE();
lypinator	0:bb348c97df44	558
lypinator	0:bb348c97df44	559	/* Get the SDIO clock configuration ----------------------------------------*/
lypinator	0:bb348c97df44	560	PeriphClkInit->SdioClockSelection = __HAL_RCC_GET_SDIO_SOURCE();
lypinator	0:bb348c97df44	561
lypinator	0:bb348c97df44	562	/* Get the SPDIFRX clock configuration -------------------------------------*/
lypinator	0:bb348c97df44	563	PeriphClkInit->SpdifClockSelection = __HAL_RCC_GET_SPDIFRX_SOURCE();
lypinator	0:bb348c97df44	564
lypinator	0:bb348c97df44	565	/* Get the TIM Prescaler configuration -------------------------------------*/
lypinator	0:bb348c97df44	566	if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET)
lypinator	0:bb348c97df44	567	{
lypinator	0:bb348c97df44	568	PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;
lypinator	0:bb348c97df44	569	}
lypinator	0:bb348c97df44	570	else
lypinator	0:bb348c97df44	571	{
lypinator	0:bb348c97df44	572	PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;
lypinator	0:bb348c97df44	573	}
lypinator	0:bb348c97df44	574	}
lypinator	0:bb348c97df44	575
lypinator	0:bb348c97df44	576	/**
lypinator	0:bb348c97df44	577	* @brief Return the peripheral clock frequency for a given peripheral(SAI..)
lypinator	0:bb348c97df44	578	* @note Return 0 if peripheral clock identifier not managed by this API
lypinator	0:bb348c97df44	579	* @param PeriphClk Peripheral clock identifier
lypinator	0:bb348c97df44	580	* This parameter can be one of the following values:
lypinator	0:bb348c97df44	581	* @arg RCC_PERIPHCLK_SAI1: SAI1 peripheral clock
lypinator	0:bb348c97df44	582	* @arg RCC_PERIPHCLK_SAI2: SAI2 peripheral clock
lypinator	0:bb348c97df44	583	* @arg RCC_PERIPHCLK_I2S_APB1: I2S APB1 peripheral clock
lypinator	0:bb348c97df44	584	* @arg RCC_PERIPHCLK_I2S_APB2: I2S APB2 peripheral clock
lypinator	0:bb348c97df44	585	* @retval Frequency in KHz
lypinator	0:bb348c97df44	586	*/
lypinator	0:bb348c97df44	587	uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
lypinator	0:bb348c97df44	588	{
lypinator	0:bb348c97df44	589	uint32_t tmpreg1 = 0U;
lypinator	0:bb348c97df44	590	/* This variable used to store the SAI clock frequency (value in Hz) */
lypinator	0:bb348c97df44	591	uint32_t frequency = 0U;
lypinator	0:bb348c97df44	592	/* This variable used to store the VCO Input (value in Hz) */
lypinator	0:bb348c97df44	593	uint32_t vcoinput = 0U;
lypinator	0:bb348c97df44	594	/* This variable used to store the SAI clock source */
lypinator	0:bb348c97df44	595	uint32_t saiclocksource = 0U;
lypinator	0:bb348c97df44	596	uint32_t srcclk = 0U;
lypinator	0:bb348c97df44	597	/* This variable used to store the VCO Output (value in Hz) */
lypinator	0:bb348c97df44	598	uint32_t vcooutput = 0U;
lypinator	0:bb348c97df44	599	switch (PeriphClk)
lypinator	0:bb348c97df44	600	{
lypinator	0:bb348c97df44	601	case RCC_PERIPHCLK_SAI1:
lypinator	0:bb348c97df44	602	case RCC_PERIPHCLK_SAI2:
lypinator	0:bb348c97df44	603	{
lypinator	0:bb348c97df44	604	saiclocksource = RCC->DCKCFGR;
lypinator	0:bb348c97df44	605	saiclocksource &= (RCC_DCKCFGR_SAI1SRC \| RCC_DCKCFGR_SAI2SRC);
lypinator	0:bb348c97df44	606	switch (saiclocksource)
lypinator	0:bb348c97df44	607	{
lypinator	0:bb348c97df44	608	case 0U: /* PLLSAI is the clock source for SAI*/
lypinator	0:bb348c97df44	609	{
lypinator	0:bb348c97df44	610	/* Configure the PLLSAI division factor */
lypinator	0:bb348c97df44	611	/* PLLSAI_VCO Input = PLL_SOURCE/PLLSAIM */
lypinator	0:bb348c97df44	612	if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
lypinator	0:bb348c97df44	613	{
lypinator	0:bb348c97df44	614	/* In Case the PLL Source is HSI (Internal Clock) */
lypinator	0:bb348c97df44	615	vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIM));
lypinator	0:bb348c97df44	616	}
lypinator	0:bb348c97df44	617	else
lypinator	0:bb348c97df44	618	{
lypinator	0:bb348c97df44	619	/* In Case the PLL Source is HSE (External Clock) */
lypinator	0:bb348c97df44	620	vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIM)));
lypinator	0:bb348c97df44	621	}
lypinator	0:bb348c97df44	622	/* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
lypinator	0:bb348c97df44	623	/* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
lypinator	0:bb348c97df44	624	tmpreg1 = (RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> 24U;
lypinator	0:bb348c97df44	625	frequency = (vcoinput * ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> 6U))/(tmpreg1);
lypinator	0:bb348c97df44	626
lypinator	0:bb348c97df44	627	/* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
lypinator	0:bb348c97df44	628	tmpreg1 = (((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> 8U) + 1U);
lypinator	0:bb348c97df44	629	frequency = frequency/(tmpreg1);
lypinator	0:bb348c97df44	630	break;
lypinator	0:bb348c97df44	631	}
lypinator	0:bb348c97df44	632	case RCC_DCKCFGR_SAI1SRC_0: /* PLLI2S is the clock source for SAI*/
lypinator	0:bb348c97df44	633	case RCC_DCKCFGR_SAI2SRC_0: /* PLLI2S is the clock source for SAI*/
lypinator	0:bb348c97df44	634	{
lypinator	0:bb348c97df44	635	/* Configure the PLLI2S division factor */
lypinator	0:bb348c97df44	636	/* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */
lypinator	0:bb348c97df44	637	if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
lypinator	0:bb348c97df44	638	{
lypinator	0:bb348c97df44	639	/* In Case the PLL Source is HSI (Internal Clock) */
lypinator	0:bb348c97df44	640	vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
lypinator	0:bb348c97df44	641	}
lypinator	0:bb348c97df44	642	else
lypinator	0:bb348c97df44	643	{
lypinator	0:bb348c97df44	644	/* In Case the PLL Source is HSE (External Clock) */
lypinator	0:bb348c97df44	645	vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM)));
lypinator	0:bb348c97df44	646	}
lypinator	0:bb348c97df44	647
lypinator	0:bb348c97df44	648	/* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
lypinator	0:bb348c97df44	649	/* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
lypinator	0:bb348c97df44	650	tmpreg1 = (RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> 24U;
lypinator	0:bb348c97df44	651	frequency = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U))/(tmpreg1);
lypinator	0:bb348c97df44	652
lypinator	0:bb348c97df44	653	/* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
lypinator	0:bb348c97df44	654	tmpreg1 = ((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) + 1U);
lypinator	0:bb348c97df44	655	frequency = frequency/(tmpreg1);
lypinator	0:bb348c97df44	656	break;
lypinator	0:bb348c97df44	657	}
lypinator	0:bb348c97df44	658	case RCC_DCKCFGR_SAI1SRC_1: /* PLLR is the clock source for SAI*/
lypinator	0:bb348c97df44	659	case RCC_DCKCFGR_SAI2SRC_1: /* PLLR is the clock source for SAI*/
lypinator	0:bb348c97df44	660	{
lypinator	0:bb348c97df44	661	/* Configure the PLLI2S division factor */
lypinator	0:bb348c97df44	662	/* PLL_VCO Input = PLL_SOURCE/PLLM */
lypinator	0:bb348c97df44	663	if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
lypinator	0:bb348c97df44	664	{
lypinator	0:bb348c97df44	665	/* In Case the PLL Source is HSI (Internal Clock) */
lypinator	0:bb348c97df44	666	vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
lypinator	0:bb348c97df44	667	}
lypinator	0:bb348c97df44	668	else
lypinator	0:bb348c97df44	669	{
lypinator	0:bb348c97df44	670	/* In Case the PLL Source is HSE (External Clock) */
lypinator	0:bb348c97df44	671	vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)));
lypinator	0:bb348c97df44	672	}
lypinator	0:bb348c97df44	673
lypinator	0:bb348c97df44	674	/* PLL_VCO Output = PLL_VCO Input * PLLN */
lypinator	0:bb348c97df44	675	/* SAI_CLK_x = PLL_VCO Output/PLLR */
lypinator	0:bb348c97df44	676	tmpreg1 = (RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 28U;
lypinator	0:bb348c97df44	677	frequency = (vcoinput * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6U))/(tmpreg1);
lypinator	0:bb348c97df44	678	break;
lypinator	0:bb348c97df44	679	}
lypinator	0:bb348c97df44	680	case RCC_DCKCFGR_SAI1SRC: /* External clock is the clock source for SAI*/
lypinator	0:bb348c97df44	681	{
lypinator	0:bb348c97df44	682	frequency = EXTERNAL_CLOCK_VALUE;
lypinator	0:bb348c97df44	683	break;
lypinator	0:bb348c97df44	684	}
lypinator	0:bb348c97df44	685	case RCC_DCKCFGR_SAI2SRC: /* PLLSRC(HSE or HSI) is the clock source for SAI*/
lypinator	0:bb348c97df44	686	{
lypinator	0:bb348c97df44	687	if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
lypinator	0:bb348c97df44	688	{
lypinator	0:bb348c97df44	689	/* In Case the PLL Source is HSI (Internal Clock) */
lypinator	0:bb348c97df44	690	frequency = (uint32_t)(HSI_VALUE);
lypinator	0:bb348c97df44	691	}
lypinator	0:bb348c97df44	692	else
lypinator	0:bb348c97df44	693	{
lypinator	0:bb348c97df44	694	/* In Case the PLL Source is HSE (External Clock) */
lypinator	0:bb348c97df44	695	frequency = (uint32_t)(HSE_VALUE);
lypinator	0:bb348c97df44	696	}
lypinator	0:bb348c97df44	697	break;
lypinator	0:bb348c97df44	698	}
lypinator	0:bb348c97df44	699	default :
lypinator	0:bb348c97df44	700	{
lypinator	0:bb348c97df44	701	break;
lypinator	0:bb348c97df44	702	}
lypinator	0:bb348c97df44	703	}
lypinator	0:bb348c97df44	704	break;
lypinator	0:bb348c97df44	705	}
lypinator	0:bb348c97df44	706	case RCC_PERIPHCLK_I2S_APB1:
lypinator	0:bb348c97df44	707	{
lypinator	0:bb348c97df44	708	/* Get the current I2S source */
lypinator	0:bb348c97df44	709	srcclk = __HAL_RCC_GET_I2S_APB1_SOURCE();
lypinator	0:bb348c97df44	710	switch (srcclk)
lypinator	0:bb348c97df44	711	{
lypinator	0:bb348c97df44	712	/* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */
lypinator	0:bb348c97df44	713	case RCC_I2SAPB1CLKSOURCE_EXT:
lypinator	0:bb348c97df44	714	{
lypinator	0:bb348c97df44	715	/* Set the I2S clock to the external clock value */
lypinator	0:bb348c97df44	716	frequency = EXTERNAL_CLOCK_VALUE;
lypinator	0:bb348c97df44	717	break;
lypinator	0:bb348c97df44	718	}
lypinator	0:bb348c97df44	719	/* Check if I2S clock selection is PLLI2S VCO output clock divided by PLLI2SR used as I2S clock */
lypinator	0:bb348c97df44	720	case RCC_I2SAPB1CLKSOURCE_PLLI2S:
lypinator	0:bb348c97df44	721	{
lypinator	0:bb348c97df44	722	/* Configure the PLLI2S division factor */
lypinator	0:bb348c97df44	723	/* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */
lypinator	0:bb348c97df44	724	if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
lypinator	0:bb348c97df44	725	{
lypinator	0:bb348c97df44	726	/* Get the I2S source clock value */
lypinator	0:bb348c97df44	727	vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
lypinator	0:bb348c97df44	728	}
lypinator	0:bb348c97df44	729	else
lypinator	0:bb348c97df44	730	{
lypinator	0:bb348c97df44	731	/* Get the I2S source clock value */
lypinator	0:bb348c97df44	732	vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
lypinator	0:bb348c97df44	733	}
lypinator	0:bb348c97df44	734
lypinator	0:bb348c97df44	735	/* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
lypinator	0:bb348c97df44	736	vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U)));
lypinator	0:bb348c97df44	737	/* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */
lypinator	0:bb348c97df44	738	frequency = (uint32_t)(vcooutput /(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U) & (RCC_PLLI2SCFGR_PLLI2SR >> 28U)));
lypinator	0:bb348c97df44	739	break;
lypinator	0:bb348c97df44	740	}
lypinator	0:bb348c97df44	741	/* Check if I2S clock selection is PLL VCO Output divided by PLLR used as I2S clock */
lypinator	0:bb348c97df44	742	case RCC_I2SAPB1CLKSOURCE_PLLR:
lypinator	0:bb348c97df44	743	{
lypinator	0:bb348c97df44	744	/* Configure the PLL division factor R */
lypinator	0:bb348c97df44	745	/* PLL_VCO Input = PLL_SOURCE/PLLM */
lypinator	0:bb348c97df44	746	if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
lypinator	0:bb348c97df44	747	{
lypinator	0:bb348c97df44	748	/* Get the I2S source clock value */
lypinator	0:bb348c97df44	749	vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
lypinator	0:bb348c97df44	750	}
lypinator	0:bb348c97df44	751	else
lypinator	0:bb348c97df44	752	{
lypinator	0:bb348c97df44	753	/* Get the I2S source clock value */
lypinator	0:bb348c97df44	754	vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
lypinator	0:bb348c97df44	755	}
lypinator	0:bb348c97df44	756
lypinator	0:bb348c97df44	757	/* PLL_VCO Output = PLL_VCO Input * PLLN */
lypinator	0:bb348c97df44	758	vcooutput = (uint32_t)(vcoinput * (((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6U) & (RCC_PLLCFGR_PLLN >> 6U)));
lypinator	0:bb348c97df44	759	/* I2S_CLK = PLL_VCO Output/PLLR */
lypinator	0:bb348c97df44	760	frequency = (uint32_t)(vcooutput /(((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 28U) & (RCC_PLLCFGR_PLLR >> 28U)));
lypinator	0:bb348c97df44	761	break;
lypinator	0:bb348c97df44	762	}
lypinator	0:bb348c97df44	763	/* Check if I2S clock selection is HSI or HSE depending from PLL source Clock */
lypinator	0:bb348c97df44	764	case RCC_I2SAPB1CLKSOURCE_PLLSRC:
lypinator	0:bb348c97df44	765	{
lypinator	0:bb348c97df44	766	if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
lypinator	0:bb348c97df44	767	{
lypinator	0:bb348c97df44	768	frequency = HSE_VALUE;
lypinator	0:bb348c97df44	769	}
lypinator	0:bb348c97df44	770	else
lypinator	0:bb348c97df44	771	{
lypinator	0:bb348c97df44	772	frequency = HSI_VALUE;
lypinator	0:bb348c97df44	773	}
lypinator	0:bb348c97df44	774	break;
lypinator	0:bb348c97df44	775	}
lypinator	0:bb348c97df44	776	/* Clock not enabled for I2S*/
lypinator	0:bb348c97df44	777	default:
lypinator	0:bb348c97df44	778	{
lypinator	0:bb348c97df44	779	frequency = 0U;
lypinator	0:bb348c97df44	780	break;
lypinator	0:bb348c97df44	781	}
lypinator	0:bb348c97df44	782	}
lypinator	0:bb348c97df44	783	break;
lypinator	0:bb348c97df44	784	}
lypinator	0:bb348c97df44	785	case RCC_PERIPHCLK_I2S_APB2:
lypinator	0:bb348c97df44	786	{
lypinator	0:bb348c97df44	787	/* Get the current I2S source */
lypinator	0:bb348c97df44	788	srcclk = __HAL_RCC_GET_I2S_APB2_SOURCE();
lypinator	0:bb348c97df44	789	switch (srcclk)
lypinator	0:bb348c97df44	790	{
lypinator	0:bb348c97df44	791	/* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */
lypinator	0:bb348c97df44	792	case RCC_I2SAPB2CLKSOURCE_EXT:
lypinator	0:bb348c97df44	793	{
lypinator	0:bb348c97df44	794	/* Set the I2S clock to the external clock value */
lypinator	0:bb348c97df44	795	frequency = EXTERNAL_CLOCK_VALUE;
lypinator	0:bb348c97df44	796	break;
lypinator	0:bb348c97df44	797	}
lypinator	0:bb348c97df44	798	/* Check if I2S clock selection is PLLI2S VCO output clock divided by PLLI2SR used as I2S clock */
lypinator	0:bb348c97df44	799	case RCC_I2SAPB2CLKSOURCE_PLLI2S:
lypinator	0:bb348c97df44	800	{
lypinator	0:bb348c97df44	801	/* Configure the PLLI2S division factor */
lypinator	0:bb348c97df44	802	/* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */
lypinator	0:bb348c97df44	803	if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
lypinator	0:bb348c97df44	804	{
lypinator	0:bb348c97df44	805	/* Get the I2S source clock value */
lypinator	0:bb348c97df44	806	vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
lypinator	0:bb348c97df44	807	}
lypinator	0:bb348c97df44	808	else
lypinator	0:bb348c97df44	809	{
lypinator	0:bb348c97df44	810	/* Get the I2S source clock value */
lypinator	0:bb348c97df44	811	vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
lypinator	0:bb348c97df44	812	}
lypinator	0:bb348c97df44	813
lypinator	0:bb348c97df44	814	/* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
lypinator	0:bb348c97df44	815	vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U)));
lypinator	0:bb348c97df44	816	/* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */
lypinator	0:bb348c97df44	817	frequency = (uint32_t)(vcooutput /(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U) & (RCC_PLLI2SCFGR_PLLI2SR >> 28U)));
lypinator	0:bb348c97df44	818	break;
lypinator	0:bb348c97df44	819	}
lypinator	0:bb348c97df44	820	/* Check if I2S clock selection is PLL VCO Output divided by PLLR used as I2S clock */
lypinator	0:bb348c97df44	821	case RCC_I2SAPB2CLKSOURCE_PLLR:
lypinator	0:bb348c97df44	822	{
lypinator	0:bb348c97df44	823	/* Configure the PLL division factor R */
lypinator	0:bb348c97df44	824	/* PLL_VCO Input = PLL_SOURCE/PLLM */
lypinator	0:bb348c97df44	825	if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
lypinator	0:bb348c97df44	826	{
lypinator	0:bb348c97df44	827	/* Get the I2S source clock value */
lypinator	0:bb348c97df44	828	vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
lypinator	0:bb348c97df44	829	}
lypinator	0:bb348c97df44	830	else
lypinator	0:bb348c97df44	831	{
lypinator	0:bb348c97df44	832	/* Get the I2S source clock value */
lypinator	0:bb348c97df44	833	vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
lypinator	0:bb348c97df44	834	}
lypinator	0:bb348c97df44	835
lypinator	0:bb348c97df44	836	/* PLL_VCO Output = PLL_VCO Input * PLLN */
lypinator	0:bb348c97df44	837	vcooutput = (uint32_t)(vcoinput * (((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6U) & (RCC_PLLCFGR_PLLN >> 6U)));
lypinator	0:bb348c97df44	838	/* I2S_CLK = PLL_VCO Output/PLLR */
lypinator	0:bb348c97df44	839	frequency = (uint32_t)(vcooutput /(((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 28U) & (RCC_PLLCFGR_PLLR >> 28U)));
lypinator	0:bb348c97df44	840	break;
lypinator	0:bb348c97df44	841	}
lypinator	0:bb348c97df44	842	/* Check if I2S clock selection is HSI or HSE depending from PLL source Clock */
lypinator	0:bb348c97df44	843	case RCC_I2SAPB2CLKSOURCE_PLLSRC:
lypinator	0:bb348c97df44	844	{
lypinator	0:bb348c97df44	845	if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
lypinator	0:bb348c97df44	846	{
lypinator	0:bb348c97df44	847	frequency = HSE_VALUE;
lypinator	0:bb348c97df44	848	}
lypinator	0:bb348c97df44	849	else
lypinator	0:bb348c97df44	850	{
lypinator	0:bb348c97df44	851	frequency = HSI_VALUE;
lypinator	0:bb348c97df44	852	}
lypinator	0:bb348c97df44	853	break;
lypinator	0:bb348c97df44	854	}
lypinator	0:bb348c97df44	855	/* Clock not enabled for I2S*/
lypinator	0:bb348c97df44	856	default:
lypinator	0:bb348c97df44	857	{
lypinator	0:bb348c97df44	858	frequency = 0U;
lypinator	0:bb348c97df44	859	break;
lypinator	0:bb348c97df44	860	}
lypinator	0:bb348c97df44	861	}
lypinator	0:bb348c97df44	862	break;
lypinator	0:bb348c97df44	863	}
lypinator	0:bb348c97df44	864	}
lypinator	0:bb348c97df44	865	return frequency;
lypinator	0:bb348c97df44	866	}
lypinator	0:bb348c97df44	867	#endif /* STM32F446xx */
lypinator	0:bb348c97df44	868
lypinator	0:bb348c97df44	869	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
lypinator	0:bb348c97df44	870	/**
lypinator	0:bb348c97df44	871	* @brief Initializes the RCC extended peripherals clocks according to the specified
lypinator	0:bb348c97df44	872	* parameters in the RCC_PeriphCLKInitTypeDef.
lypinator	0:bb348c97df44	873	* @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
lypinator	0:bb348c97df44	874	* contains the configuration information for the Extended Peripherals
lypinator	0:bb348c97df44	875	* clocks(I2S, SAI, LTDC, RTC and TIM).
lypinator	0:bb348c97df44	876	*
lypinator	0:bb348c97df44	877	* @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
lypinator	0:bb348c97df44	878	* the RTC clock source; in this case the Backup domain will be reset in
lypinator	0:bb348c97df44	879	* order to modify the RTC Clock source, as consequence RTC registers (including
lypinator	0:bb348c97df44	880	* the backup registers) and RCC_BDCR register are set to their reset values.
lypinator	0:bb348c97df44	881	*
lypinator	0:bb348c97df44	882	* @retval HAL status
lypinator	0:bb348c97df44	883	*/
lypinator	0:bb348c97df44	884	HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
lypinator	0:bb348c97df44	885	{
lypinator	0:bb348c97df44	886	uint32_t tickstart = 0U;
lypinator	0:bb348c97df44	887	uint32_t tmpreg1 = 0U;
lypinator	0:bb348c97df44	888	uint32_t pllsaip = 0U;
lypinator	0:bb348c97df44	889	uint32_t pllsaiq = 0U;
lypinator	0:bb348c97df44	890	uint32_t pllsair = 0U;
lypinator	0:bb348c97df44	891
lypinator	0:bb348c97df44	892	/* Check the parameters */
lypinator	0:bb348c97df44	893	assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
lypinator	0:bb348c97df44	894
lypinator	0:bb348c97df44	895	/--------------------------- CLK48 Configuration --------------------------/
lypinator	0:bb348c97df44	896	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48)
lypinator	0:bb348c97df44	897	{
lypinator	0:bb348c97df44	898	/* Check the parameters */
lypinator	0:bb348c97df44	899	assert_param(IS_RCC_CLK48CLKSOURCE(PeriphClkInit->Clk48ClockSelection));
lypinator	0:bb348c97df44	900
lypinator	0:bb348c97df44	901	/* Configure the CLK48 clock source */
lypinator	0:bb348c97df44	902	__HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection);
lypinator	0:bb348c97df44	903	}
lypinator	0:bb348c97df44	904	/--------------------------------------------------------------------------/
lypinator	0:bb348c97df44	905
lypinator	0:bb348c97df44	906	/------------------------------ SDIO Configuration ------------------------/
lypinator	0:bb348c97df44	907	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDIO) == RCC_PERIPHCLK_SDIO)
lypinator	0:bb348c97df44	908	{
lypinator	0:bb348c97df44	909	/* Check the parameters */
lypinator	0:bb348c97df44	910	assert_param(IS_RCC_SDIOCLKSOURCE(PeriphClkInit->SdioClockSelection));
lypinator	0:bb348c97df44	911
lypinator	0:bb348c97df44	912	/* Configure the SDIO clock source */
lypinator	0:bb348c97df44	913	__HAL_RCC_SDIO_CONFIG(PeriphClkInit->SdioClockSelection);
lypinator	0:bb348c97df44	914	}
lypinator	0:bb348c97df44	915	/--------------------------------------------------------------------------/
lypinator	0:bb348c97df44	916
lypinator	0:bb348c97df44	917	/----------------------- SAI/I2S Configuration (PLLI2S) -------------------/
lypinator	0:bb348c97df44	918	/------------------- Common configuration SAI/I2S -------------------------/
lypinator	0:bb348c97df44	919	/* In Case of SAI or I2S Clock Configuration through PLLI2S, PLLI2SN division
lypinator	0:bb348c97df44	920	factor is common parameters for both peripherals */
lypinator	0:bb348c97df44	921	if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) \|\|
lypinator	0:bb348c97df44	922	(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == RCC_PERIPHCLK_SAI_PLLI2S) \|\|
lypinator	0:bb348c97df44	923	(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S))
lypinator	0:bb348c97df44	924	{
lypinator	0:bb348c97df44	925	/* check for Parameters */
lypinator	0:bb348c97df44	926	assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
lypinator	0:bb348c97df44	927
lypinator	0:bb348c97df44	928	/* Disable the PLLI2S */
lypinator	0:bb348c97df44	929	__HAL_RCC_PLLI2S_DISABLE();
lypinator	0:bb348c97df44	930	/* Get tick */
lypinator	0:bb348c97df44	931	tickstart = HAL_GetTick();
lypinator	0:bb348c97df44	932	/* Wait till PLLI2S is disabled */
lypinator	0:bb348c97df44	933	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
lypinator	0:bb348c97df44	934	{
lypinator	0:bb348c97df44	935	if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
lypinator	0:bb348c97df44	936	{
lypinator	0:bb348c97df44	937	/* return in case of Timeout detected */
lypinator	0:bb348c97df44	938	return HAL_TIMEOUT;
lypinator	0:bb348c97df44	939	}
lypinator	0:bb348c97df44	940	}
lypinator	0:bb348c97df44	941
lypinator	0:bb348c97df44	942	/---------------------- I2S configuration -------------------------------/
lypinator	0:bb348c97df44	943	/* In Case of I2S Clock Configuration through PLLI2S, PLLI2SR must be added
lypinator	0:bb348c97df44	944	only for I2S configuration */
lypinator	0:bb348c97df44	945	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S))
lypinator	0:bb348c97df44	946	{
lypinator	0:bb348c97df44	947	/* check for Parameters */
lypinator	0:bb348c97df44	948	assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
lypinator	0:bb348c97df44	949	/* Configure the PLLI2S division factors */
lypinator	0:bb348c97df44	950	/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */
lypinator	0:bb348c97df44	951	/* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
lypinator	0:bb348c97df44	952	__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SR);
lypinator	0:bb348c97df44	953	}
lypinator	0:bb348c97df44	954
lypinator	0:bb348c97df44	955	/---------------------------- SAI configuration -------------------------/
lypinator	0:bb348c97df44	956	/* In Case of SAI Clock Configuration through PLLI2S, PLLI2SQ and PLLI2S_DIVQ must
lypinator	0:bb348c97df44	957	be added only for SAI configuration */
lypinator	0:bb348c97df44	958	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == (RCC_PERIPHCLK_SAI_PLLI2S))
lypinator	0:bb348c97df44	959	{
lypinator	0:bb348c97df44	960	/* Check the PLLI2S division factors */
lypinator	0:bb348c97df44	961	assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
lypinator	0:bb348c97df44	962	assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ));
lypinator	0:bb348c97df44	963
lypinator	0:bb348c97df44	964	/* Read PLLI2SR value from PLLI2SCFGR register (this value is not need for SAI configuration) */
lypinator	0:bb348c97df44	965	tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
lypinator	0:bb348c97df44	966	/* Configure the PLLI2S division factors */
lypinator	0:bb348c97df44	967	/* PLLI2S_VCO Input = PLL_SOURCE/PLLM */
lypinator	0:bb348c97df44	968	/* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
lypinator	0:bb348c97df44	969	/* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
lypinator	0:bb348c97df44	970	__HAL_RCC_PLLI2S_SAICLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SQ , tmpreg1);
lypinator	0:bb348c97df44	971	/* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
lypinator	0:bb348c97df44	972	__HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ);
lypinator	0:bb348c97df44	973	}
lypinator	0:bb348c97df44	974
lypinator	0:bb348c97df44	975	/----------------- In Case of PLLI2S is just selected -----------------/
lypinator	0:bb348c97df44	976	if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)
lypinator	0:bb348c97df44	977	{
lypinator	0:bb348c97df44	978	/* Check for Parameters */
lypinator	0:bb348c97df44	979	assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
lypinator	0:bb348c97df44	980	assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
lypinator	0:bb348c97df44	981
lypinator	0:bb348c97df44	982	/* Configure the PLLI2S multiplication and division factors */
lypinator	0:bb348c97df44	983	__HAL_RCC_PLLI2S_SAICLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR);
lypinator	0:bb348c97df44	984	}
lypinator	0:bb348c97df44	985
lypinator	0:bb348c97df44	986	/* Enable the PLLI2S */
lypinator	0:bb348c97df44	987	__HAL_RCC_PLLI2S_ENABLE();
lypinator	0:bb348c97df44	988	/* Get tick */
lypinator	0:bb348c97df44	989	tickstart = HAL_GetTick();
lypinator	0:bb348c97df44	990	/* Wait till PLLI2S is ready */
lypinator	0:bb348c97df44	991	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
lypinator	0:bb348c97df44	992	{
lypinator	0:bb348c97df44	993	if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
lypinator	0:bb348c97df44	994	{
lypinator	0:bb348c97df44	995	/* return in case of Timeout detected */
lypinator	0:bb348c97df44	996	return HAL_TIMEOUT;
lypinator	0:bb348c97df44	997	}
lypinator	0:bb348c97df44	998	}
lypinator	0:bb348c97df44	999	}
lypinator	0:bb348c97df44	1000	/--------------------------------------------------------------------------/
lypinator	0:bb348c97df44	1001
lypinator	0:bb348c97df44	1002	/----------------------- SAI/LTDC Configuration (PLLSAI) ------------------/
lypinator	0:bb348c97df44	1003	/----------------------- Common configuration SAI/LTDC --------------------/
lypinator	0:bb348c97df44	1004	/* In Case of SAI, LTDC or CLK48 Clock Configuration through PLLSAI, PLLSAIN division
lypinator	0:bb348c97df44	1005	factor is common parameters for these peripherals */
lypinator	0:bb348c97df44	1006	if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == RCC_PERIPHCLK_SAI_PLLSAI) \|\|
lypinator	0:bb348c97df44	1007	(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) \|\|
lypinator	0:bb348c97df44	1008	((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) &&
lypinator	0:bb348c97df44	1009	(PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLSAIP)))
lypinator	0:bb348c97df44	1010	{
lypinator	0:bb348c97df44	1011	/* Check the PLLSAI division factors */
lypinator	0:bb348c97df44	1012	assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN));
lypinator	0:bb348c97df44	1013
lypinator	0:bb348c97df44	1014	/* Disable PLLSAI Clock */
lypinator	0:bb348c97df44	1015	__HAL_RCC_PLLSAI_DISABLE();
lypinator	0:bb348c97df44	1016	/* Get tick */
lypinator	0:bb348c97df44	1017	tickstart = HAL_GetTick();
lypinator	0:bb348c97df44	1018	/* Wait till PLLSAI is disabled */
lypinator	0:bb348c97df44	1019	while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
lypinator	0:bb348c97df44	1020	{
lypinator	0:bb348c97df44	1021	if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
lypinator	0:bb348c97df44	1022	{
lypinator	0:bb348c97df44	1023	/* return in case of Timeout detected */
lypinator	0:bb348c97df44	1024	return HAL_TIMEOUT;
lypinator	0:bb348c97df44	1025	}
lypinator	0:bb348c97df44	1026	}
lypinator	0:bb348c97df44	1027
lypinator	0:bb348c97df44	1028	/---------------------------- SAI configuration -------------------------/
lypinator	0:bb348c97df44	1029	/* In Case of SAI Clock Configuration through PLLSAI, PLLSAIQ and PLLSAI_DIVQ must
lypinator	0:bb348c97df44	1030	be added only for SAI configuration */
lypinator	0:bb348c97df44	1031	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == (RCC_PERIPHCLK_SAI_PLLSAI))
lypinator	0:bb348c97df44	1032	{
lypinator	0:bb348c97df44	1033	assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ));
lypinator	0:bb348c97df44	1034	assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ));
lypinator	0:bb348c97df44	1035
lypinator	0:bb348c97df44	1036	/* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */
lypinator	0:bb348c97df44	1037	pllsaip = ((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos) + 1U) << 1U);
lypinator	0:bb348c97df44	1038	/* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */
lypinator	0:bb348c97df44	1039	pllsair = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos);
lypinator	0:bb348c97df44	1040	/* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
lypinator	0:bb348c97df44	1041	/* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
lypinator	0:bb348c97df44	1042	/* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
lypinator	0:bb348c97df44	1043	__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN, pllsaip, PeriphClkInit->PLLSAI.PLLSAIQ, pllsair);
lypinator	0:bb348c97df44	1044	/* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
lypinator	0:bb348c97df44	1045	__HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ);
lypinator	0:bb348c97df44	1046	}
lypinator	0:bb348c97df44	1047
lypinator	0:bb348c97df44	1048	/---------------------------- LTDC configuration ------------------------/
lypinator	0:bb348c97df44	1049	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC))
lypinator	0:bb348c97df44	1050	{
lypinator	0:bb348c97df44	1051	assert_param(IS_RCC_PLLSAIR_VALUE(PeriphClkInit->PLLSAI.PLLSAIR));
lypinator	0:bb348c97df44	1052	assert_param(IS_RCC_PLLSAI_DIVR_VALUE(PeriphClkInit->PLLSAIDivR));
lypinator	0:bb348c97df44	1053
lypinator	0:bb348c97df44	1054	/* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */
lypinator	0:bb348c97df44	1055	pllsaip = ((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos) + 1U) << 1U);
lypinator	0:bb348c97df44	1056	/* Read PLLSAIQ value from PLLSAICFGR register (this value is not need for SAI configuration) */
lypinator	0:bb348c97df44	1057	pllsaiq = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);
lypinator	0:bb348c97df44	1058	/* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
lypinator	0:bb348c97df44	1059	/* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
lypinator	0:bb348c97df44	1060	/* LTDC_CLK(first level) = PLLSAI_VCO Output/PLLSAIR */
lypinator	0:bb348c97df44	1061	__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN, pllsaip, pllsaiq, PeriphClkInit->PLLSAI.PLLSAIR);
lypinator	0:bb348c97df44	1062	/* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */
lypinator	0:bb348c97df44	1063	__HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR);
lypinator	0:bb348c97df44	1064	}
lypinator	0:bb348c97df44	1065
lypinator	0:bb348c97df44	1066	/---------------------------- CLK48 configuration ------------------------/
lypinator	0:bb348c97df44	1067	/* Configure the PLLSAI when it is used as clock source for CLK48 */
lypinator	0:bb348c97df44	1068	if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == (RCC_PERIPHCLK_CLK48)) &&
lypinator	0:bb348c97df44	1069	(PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLSAIP))
lypinator	0:bb348c97df44	1070	{
lypinator	0:bb348c97df44	1071	assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP));
lypinator	0:bb348c97df44	1072
lypinator	0:bb348c97df44	1073	/* Read PLLSAIQ value from PLLSAICFGR register (this value is not need for SAI configuration) */
lypinator	0:bb348c97df44	1074	pllsaiq = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);
lypinator	0:bb348c97df44	1075	/* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */
lypinator	0:bb348c97df44	1076	pllsair = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos);
lypinator	0:bb348c97df44	1077	/* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
lypinator	0:bb348c97df44	1078	/* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
lypinator	0:bb348c97df44	1079	/* CLK48_CLK(first level) = PLLSAI_VCO Output/PLLSAIP */
lypinator	0:bb348c97df44	1080	__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN, PeriphClkInit->PLLSAI.PLLSAIP, pllsaiq, pllsair);
lypinator	0:bb348c97df44	1081	}
lypinator	0:bb348c97df44	1082
lypinator	0:bb348c97df44	1083	/* Enable PLLSAI Clock */
lypinator	0:bb348c97df44	1084	__HAL_RCC_PLLSAI_ENABLE();
lypinator	0:bb348c97df44	1085	/* Get tick */
lypinator	0:bb348c97df44	1086	tickstart = HAL_GetTick();
lypinator	0:bb348c97df44	1087	/* Wait till PLLSAI is ready */
lypinator	0:bb348c97df44	1088	while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
lypinator	0:bb348c97df44	1089	{
lypinator	0:bb348c97df44	1090	if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
lypinator	0:bb348c97df44	1091	{
lypinator	0:bb348c97df44	1092	/* return in case of Timeout detected */
lypinator	0:bb348c97df44	1093	return HAL_TIMEOUT;
lypinator	0:bb348c97df44	1094	}
lypinator	0:bb348c97df44	1095	}
lypinator	0:bb348c97df44	1096	}
lypinator	0:bb348c97df44	1097
lypinator	0:bb348c97df44	1098	/--------------------------------------------------------------------------/
lypinator	0:bb348c97df44	1099
lypinator	0:bb348c97df44	1100	/---------------------------- RTC configuration ---------------------------/
lypinator	0:bb348c97df44	1101	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
lypinator	0:bb348c97df44	1102	{
lypinator	0:bb348c97df44	1103	/* Check for RTC Parameters used to output RTCCLK */
lypinator	0:bb348c97df44	1104	assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
lypinator	0:bb348c97df44	1105
lypinator	0:bb348c97df44	1106	/* Enable Power Clock*/
lypinator	0:bb348c97df44	1107	__HAL_RCC_PWR_CLK_ENABLE();
lypinator	0:bb348c97df44	1108
lypinator	0:bb348c97df44	1109	/* Enable write access to Backup domain */
lypinator	0:bb348c97df44	1110	PWR->CR \|= PWR_CR_DBP;
lypinator	0:bb348c97df44	1111
lypinator	0:bb348c97df44	1112	/* Get tick */
lypinator	0:bb348c97df44	1113	tickstart = HAL_GetTick();
lypinator	0:bb348c97df44	1114
lypinator	0:bb348c97df44	1115	while((PWR->CR & PWR_CR_DBP) == RESET)
lypinator	0:bb348c97df44	1116	{
lypinator	0:bb348c97df44	1117	if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
lypinator	0:bb348c97df44	1118	{
lypinator	0:bb348c97df44	1119	return HAL_TIMEOUT;
lypinator	0:bb348c97df44	1120	}
lypinator	0:bb348c97df44	1121	}
lypinator	0:bb348c97df44	1122	/* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
lypinator	0:bb348c97df44	1123	tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL);
lypinator	0:bb348c97df44	1124	if((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
lypinator	0:bb348c97df44	1125	{
lypinator	0:bb348c97df44	1126	/* Store the content of BDCR register before the reset of Backup Domain */
lypinator	0:bb348c97df44	1127	tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
lypinator	0:bb348c97df44	1128	/* RTC Clock selection can be changed only if the Backup Domain is reset */
lypinator	0:bb348c97df44	1129	__HAL_RCC_BACKUPRESET_FORCE();
lypinator	0:bb348c97df44	1130	__HAL_RCC_BACKUPRESET_RELEASE();
lypinator	0:bb348c97df44	1131	/* Restore the Content of BDCR register */
lypinator	0:bb348c97df44	1132	RCC->BDCR = tmpreg1;
lypinator	0:bb348c97df44	1133
lypinator	0:bb348c97df44	1134	/* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
lypinator	0:bb348c97df44	1135	if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))
lypinator	0:bb348c97df44	1136	{
lypinator	0:bb348c97df44	1137	/* Get tick */
lypinator	0:bb348c97df44	1138	tickstart = HAL_GetTick();
lypinator	0:bb348c97df44	1139
lypinator	0:bb348c97df44	1140	/* Wait till LSE is ready */
lypinator	0:bb348c97df44	1141	while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
lypinator	0:bb348c97df44	1142	{
lypinator	0:bb348c97df44	1143	if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
lypinator	0:bb348c97df44	1144	{
lypinator	0:bb348c97df44	1145	return HAL_TIMEOUT;
lypinator	0:bb348c97df44	1146	}
lypinator	0:bb348c97df44	1147	}
lypinator	0:bb348c97df44	1148	}
lypinator	0:bb348c97df44	1149	}
lypinator	0:bb348c97df44	1150	__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
lypinator	0:bb348c97df44	1151	}
lypinator	0:bb348c97df44	1152	/--------------------------------------------------------------------------/
lypinator	0:bb348c97df44	1153
lypinator	0:bb348c97df44	1154	/---------------------------- TIM configuration ---------------------------/
lypinator	0:bb348c97df44	1155	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
lypinator	0:bb348c97df44	1156	{
lypinator	0:bb348c97df44	1157	__HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
lypinator	0:bb348c97df44	1158	}
lypinator	0:bb348c97df44	1159	return HAL_OK;
lypinator	0:bb348c97df44	1160	}
lypinator	0:bb348c97df44	1161
lypinator	0:bb348c97df44	1162	/**
lypinator	0:bb348c97df44	1163	* @brief Configures the RCC_PeriphCLKInitTypeDef according to the internal
lypinator	0:bb348c97df44	1164	* RCC configuration registers.
lypinator	0:bb348c97df44	1165	* @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
lypinator	0:bb348c97df44	1166	* will be configured.
lypinator	0:bb348c97df44	1167	* @retval None
lypinator	0:bb348c97df44	1168	*/
lypinator	0:bb348c97df44	1169	void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
lypinator	0:bb348c97df44	1170	{
lypinator	0:bb348c97df44	1171	uint32_t tempreg;
lypinator	0:bb348c97df44	1172
lypinator	0:bb348c97df44	1173	/* Set all possible values for the extended clock type parameter------------*/
lypinator	0:bb348c97df44	1174	PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S \| RCC_PERIPHCLK_SAI_PLLSAI \|\
lypinator	0:bb348c97df44	1175	RCC_PERIPHCLK_SAI_PLLI2S \| RCC_PERIPHCLK_LTDC \|\
lypinator	0:bb348c97df44	1176	RCC_PERIPHCLK_TIM \| RCC_PERIPHCLK_RTC \|\
lypinator	0:bb348c97df44	1177	RCC_PERIPHCLK_CLK48 \| RCC_PERIPHCLK_SDIO;
lypinator	0:bb348c97df44	1178
lypinator	0:bb348c97df44	1179	/* Get the PLLI2S Clock configuration --------------------------------------*/
lypinator	0:bb348c97df44	1180	PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos);
lypinator	0:bb348c97df44	1181	PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
lypinator	0:bb348c97df44	1182	PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos);
lypinator	0:bb348c97df44	1183	/* Get the PLLSAI Clock configuration --------------------------------------*/
lypinator	0:bb348c97df44	1184	PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> RCC_PLLSAICFGR_PLLSAIN_Pos);
lypinator	0:bb348c97df44	1185	PeriphClkInit->PLLSAI.PLLSAIR = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos);
lypinator	0:bb348c97df44	1186	PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);
lypinator	0:bb348c97df44	1187	/* Get the PLLSAI/PLLI2S division factors ----------------------------------*/
lypinator	0:bb348c97df44	1188	PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) >> RCC_DCKCFGR_PLLI2SDIVQ_Pos);
lypinator	0:bb348c97df44	1189	PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> RCC_DCKCFGR_PLLSAIDIVQ_Pos);
lypinator	0:bb348c97df44	1190	PeriphClkInit->PLLSAIDivR = (uint32_t)(RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVR);
lypinator	0:bb348c97df44	1191	/* Get the RTC Clock configuration -----------------------------------------*/
lypinator	0:bb348c97df44	1192	tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
lypinator	0:bb348c97df44	1193	PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) \| (RCC->BDCR & RCC_BDCR_RTCSEL));
lypinator	0:bb348c97df44	1194
lypinator	0:bb348c97df44	1195	/* Get the CLK48 clock configuration -------------------------------------*/
lypinator	0:bb348c97df44	1196	PeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE();
lypinator	0:bb348c97df44	1197
lypinator	0:bb348c97df44	1198	/* Get the SDIO clock configuration ----------------------------------------*/
lypinator	0:bb348c97df44	1199	PeriphClkInit->SdioClockSelection = __HAL_RCC_GET_SDIO_SOURCE();
lypinator	0:bb348c97df44	1200
lypinator	0:bb348c97df44	1201	if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET)
lypinator	0:bb348c97df44	1202	{
lypinator	0:bb348c97df44	1203	PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;
lypinator	0:bb348c97df44	1204	}
lypinator	0:bb348c97df44	1205	else
lypinator	0:bb348c97df44	1206	{
lypinator	0:bb348c97df44	1207	PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;
lypinator	0:bb348c97df44	1208	}
lypinator	0:bb348c97df44	1209	}
lypinator	0:bb348c97df44	1210
lypinator	0:bb348c97df44	1211	/**
lypinator	0:bb348c97df44	1212	* @brief Return the peripheral clock frequency for a given peripheral(SAI..)
lypinator	0:bb348c97df44	1213	* @note Return 0 if peripheral clock identifier not managed by this API
lypinator	0:bb348c97df44	1214	* @param PeriphClk Peripheral clock identifier
lypinator	0:bb348c97df44	1215	* This parameter can be one of the following values:
lypinator	0:bb348c97df44	1216	* @arg RCC_PERIPHCLK_I2S: I2S peripheral clock
lypinator	0:bb348c97df44	1217	* @retval Frequency in KHz
lypinator	0:bb348c97df44	1218	*/
lypinator	0:bb348c97df44	1219	uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
lypinator	0:bb348c97df44	1220	{
lypinator	0:bb348c97df44	1221	/* This variable used to store the I2S clock frequency (value in Hz) */
lypinator	0:bb348c97df44	1222	uint32_t frequency = 0U;
lypinator	0:bb348c97df44	1223	/* This variable used to store the VCO Input (value in Hz) */
lypinator	0:bb348c97df44	1224	uint32_t vcoinput = 0U;
lypinator	0:bb348c97df44	1225	uint32_t srcclk = 0U;
lypinator	0:bb348c97df44	1226	/* This variable used to store the VCO Output (value in Hz) */
lypinator	0:bb348c97df44	1227	uint32_t vcooutput = 0U;
lypinator	0:bb348c97df44	1228	switch (PeriphClk)
lypinator	0:bb348c97df44	1229	{
lypinator	0:bb348c97df44	1230	case RCC_PERIPHCLK_I2S:
lypinator	0:bb348c97df44	1231	{
lypinator	0:bb348c97df44	1232	/* Get the current I2S source */
lypinator	0:bb348c97df44	1233	srcclk = __HAL_RCC_GET_I2S_SOURCE();
lypinator	0:bb348c97df44	1234	switch (srcclk)
lypinator	0:bb348c97df44	1235	{
lypinator	0:bb348c97df44	1236	/* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */
lypinator	0:bb348c97df44	1237	case RCC_I2SCLKSOURCE_EXT:
lypinator	0:bb348c97df44	1238	{
lypinator	0:bb348c97df44	1239	/* Set the I2S clock to the external clock value */
lypinator	0:bb348c97df44	1240	frequency = EXTERNAL_CLOCK_VALUE;
lypinator	0:bb348c97df44	1241	break;
lypinator	0:bb348c97df44	1242	}
lypinator	0:bb348c97df44	1243	/* Check if I2S clock selection is PLLI2S VCO output clock divided by PLLI2SR used as I2S clock */
lypinator	0:bb348c97df44	1244	case RCC_I2SCLKSOURCE_PLLI2S:
lypinator	0:bb348c97df44	1245	{
lypinator	0:bb348c97df44	1246	/* Configure the PLLI2S division factor */
lypinator	0:bb348c97df44	1247	/* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */
lypinator	0:bb348c97df44	1248	if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
lypinator	0:bb348c97df44	1249	{
lypinator	0:bb348c97df44	1250	/* Get the I2S source clock value */
lypinator	0:bb348c97df44	1251	vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
lypinator	0:bb348c97df44	1252	}
lypinator	0:bb348c97df44	1253	else
lypinator	0:bb348c97df44	1254	{
lypinator	0:bb348c97df44	1255	/* Get the I2S source clock value */
lypinator	0:bb348c97df44	1256	vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
lypinator	0:bb348c97df44	1257	}
lypinator	0:bb348c97df44	1258
lypinator	0:bb348c97df44	1259	/* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
lypinator	0:bb348c97df44	1260	vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U)));
lypinator	0:bb348c97df44	1261	/* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */
lypinator	0:bb348c97df44	1262	frequency = (uint32_t)(vcooutput /(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U) & (RCC_PLLI2SCFGR_PLLI2SR >> 28U)));
lypinator	0:bb348c97df44	1263	break;
lypinator	0:bb348c97df44	1264	}
lypinator	0:bb348c97df44	1265	/* Clock not enabled for I2S*/
lypinator	0:bb348c97df44	1266	default:
lypinator	0:bb348c97df44	1267	{
lypinator	0:bb348c97df44	1268	frequency = 0U;
lypinator	0:bb348c97df44	1269	break;
lypinator	0:bb348c97df44	1270	}
lypinator	0:bb348c97df44	1271	}
lypinator	0:bb348c97df44	1272	break;
lypinator	0:bb348c97df44	1273	}
lypinator	0:bb348c97df44	1274	}
lypinator	0:bb348c97df44	1275	return frequency;
lypinator	0:bb348c97df44	1276	}
lypinator	0:bb348c97df44	1277	#endif /* STM32F469xx \|\| STM32F479xx */
lypinator	0:bb348c97df44	1278
lypinator	0:bb348c97df44	1279	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
lypinator	0:bb348c97df44	1280	/**
lypinator	0:bb348c97df44	1281	* @brief Initializes the RCC extended peripherals clocks according to the specified
lypinator	0:bb348c97df44	1282	* parameters in the RCC_PeriphCLKInitTypeDef.
lypinator	0:bb348c97df44	1283	* @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
lypinator	0:bb348c97df44	1284	* contains the configuration information for the Extended Peripherals
lypinator	0:bb348c97df44	1285	* clocks(I2S, LTDC RTC and TIM).
lypinator	0:bb348c97df44	1286	*
lypinator	0:bb348c97df44	1287	* @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
lypinator	0:bb348c97df44	1288	* the RTC clock source; in this case the Backup domain will be reset in
lypinator	0:bb348c97df44	1289	* order to modify the RTC Clock source, as consequence RTC registers (including
lypinator	0:bb348c97df44	1290	* the backup registers) and RCC_BDCR register are set to their reset values.
lypinator	0:bb348c97df44	1291	*
lypinator	0:bb348c97df44	1292	* @retval HAL status
lypinator	0:bb348c97df44	1293	*/
lypinator	0:bb348c97df44	1294	HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
lypinator	0:bb348c97df44	1295	{
lypinator	0:bb348c97df44	1296	uint32_t tickstart = 0U;
lypinator	0:bb348c97df44	1297	uint32_t tmpreg1 = 0U;
lypinator	0:bb348c97df44	1298	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
lypinator	0:bb348c97df44	1299	uint32_t plli2sq = 0U;
lypinator	0:bb348c97df44	1300	#endif /* STM32F413xx \|\| STM32F423xx */
lypinator	0:bb348c97df44	1301	uint32_t plli2sused = 0U;
lypinator	0:bb348c97df44	1302
lypinator	0:bb348c97df44	1303	/* Check the peripheral clock selection parameters */
lypinator	0:bb348c97df44	1304	assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
lypinator	0:bb348c97df44	1305
lypinator	0:bb348c97df44	1306	/----------------------------------- I2S APB1 configuration ---------------/
lypinator	0:bb348c97df44	1307	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == (RCC_PERIPHCLK_I2S_APB1))
lypinator	0:bb348c97df44	1308	{
lypinator	0:bb348c97df44	1309	/* Check the parameters */
lypinator	0:bb348c97df44	1310	assert_param(IS_RCC_I2SAPB1CLKSOURCE(PeriphClkInit->I2sApb1ClockSelection));
lypinator	0:bb348c97df44	1311
lypinator	0:bb348c97df44	1312	/* Configure I2S Clock source */
lypinator	0:bb348c97df44	1313	__HAL_RCC_I2S_APB1_CONFIG(PeriphClkInit->I2sApb1ClockSelection);
lypinator	0:bb348c97df44	1314	/* Enable the PLLI2S when it's used as clock source for I2S */
lypinator	0:bb348c97df44	1315	if(PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S)
lypinator	0:bb348c97df44	1316	{
lypinator	0:bb348c97df44	1317	plli2sused = 1U;
lypinator	0:bb348c97df44	1318	}
lypinator	0:bb348c97df44	1319	}
lypinator	0:bb348c97df44	1320	/--------------------------------------------------------------------------/
lypinator	0:bb348c97df44	1321
lypinator	0:bb348c97df44	1322	/----------------------------------- I2S APB2 configuration ---------------/
lypinator	0:bb348c97df44	1323	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == (RCC_PERIPHCLK_I2S_APB2))
lypinator	0:bb348c97df44	1324	{
lypinator	0:bb348c97df44	1325	/* Check the parameters */
lypinator	0:bb348c97df44	1326	assert_param(IS_RCC_I2SAPB2CLKSOURCE(PeriphClkInit->I2sApb2ClockSelection));
lypinator	0:bb348c97df44	1327
lypinator	0:bb348c97df44	1328	/* Configure I2S Clock source */
lypinator	0:bb348c97df44	1329	__HAL_RCC_I2S_APB2_CONFIG(PeriphClkInit->I2sApb2ClockSelection);
lypinator	0:bb348c97df44	1330	/* Enable the PLLI2S when it's used as clock source for I2S */
lypinator	0:bb348c97df44	1331	if(PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S)
lypinator	0:bb348c97df44	1332	{
lypinator	0:bb348c97df44	1333	plli2sused = 1U;
lypinator	0:bb348c97df44	1334	}
lypinator	0:bb348c97df44	1335	}
lypinator	0:bb348c97df44	1336	/--------------------------------------------------------------------------/
lypinator	0:bb348c97df44	1337
lypinator	0:bb348c97df44	1338	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
lypinator	0:bb348c97df44	1339	/----------------------- SAI1 Block A configuration -----------------------/
lypinator	0:bb348c97df44	1340	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAIA) == (RCC_PERIPHCLK_SAIA))
lypinator	0:bb348c97df44	1341	{
lypinator	0:bb348c97df44	1342	/* Check the parameters */
lypinator	0:bb348c97df44	1343	assert_param(IS_RCC_SAIACLKSOURCE(PeriphClkInit->SaiAClockSelection));
lypinator	0:bb348c97df44	1344
lypinator	0:bb348c97df44	1345	/* Configure SAI1 Clock source */
lypinator	0:bb348c97df44	1346	__HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(PeriphClkInit->SaiAClockSelection);
lypinator	0:bb348c97df44	1347	/* Enable the PLLI2S when it's used as clock source for SAI */
lypinator	0:bb348c97df44	1348	if(PeriphClkInit->SaiAClockSelection == RCC_SAIACLKSOURCE_PLLI2SR)
lypinator	0:bb348c97df44	1349	{
lypinator	0:bb348c97df44	1350	plli2sused = 1U;
lypinator	0:bb348c97df44	1351	}
lypinator	0:bb348c97df44	1352	/* Enable the PLLSAI when it's used as clock source for SAI */
lypinator	0:bb348c97df44	1353	if(PeriphClkInit->SaiAClockSelection == RCC_SAIACLKSOURCE_PLLR)
lypinator	0:bb348c97df44	1354	{
lypinator	0:bb348c97df44	1355	/* Check for PLL/DIVR parameters */
lypinator	0:bb348c97df44	1356	assert_param(IS_RCC_PLL_DIVR_VALUE(PeriphClkInit->PLLDivR));
lypinator	0:bb348c97df44	1357
lypinator	0:bb348c97df44	1358	/* SAI_CLK_x = SAI_CLK(first level)/PLLDIVR */
lypinator	0:bb348c97df44	1359	__HAL_RCC_PLL_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLDivR);
lypinator	0:bb348c97df44	1360	}
lypinator	0:bb348c97df44	1361	}
lypinator	0:bb348c97df44	1362	/--------------------------------------------------------------------------/
lypinator	0:bb348c97df44	1363
lypinator	0:bb348c97df44	1364	/---------------------- SAI1 Block B configuration ------------------------/
lypinator	0:bb348c97df44	1365	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAIB) == (RCC_PERIPHCLK_SAIB))
lypinator	0:bb348c97df44	1366	{
lypinator	0:bb348c97df44	1367	/* Check the parameters */
lypinator	0:bb348c97df44	1368	assert_param(IS_RCC_SAIBCLKSOURCE(PeriphClkInit->SaiBClockSelection));
lypinator	0:bb348c97df44	1369
lypinator	0:bb348c97df44	1370	/* Configure SAI1 Clock source */
lypinator	0:bb348c97df44	1371	__HAL_RCC_SAI_BLOCKBCLKSOURCE_CONFIG(PeriphClkInit->SaiBClockSelection);
lypinator	0:bb348c97df44	1372	/* Enable the PLLI2S when it's used as clock source for SAI */
lypinator	0:bb348c97df44	1373	if(PeriphClkInit->SaiBClockSelection == RCC_SAIBCLKSOURCE_PLLI2SR)
lypinator	0:bb348c97df44	1374	{
lypinator	0:bb348c97df44	1375	plli2sused = 1U;
lypinator	0:bb348c97df44	1376	}
lypinator	0:bb348c97df44	1377	/* Enable the PLLSAI when it's used as clock source for SAI */
lypinator	0:bb348c97df44	1378	if(PeriphClkInit->SaiBClockSelection == RCC_SAIBCLKSOURCE_PLLR)
lypinator	0:bb348c97df44	1379	{
lypinator	0:bb348c97df44	1380	/* Check for PLL/DIVR parameters */
lypinator	0:bb348c97df44	1381	assert_param(IS_RCC_PLL_DIVR_VALUE(PeriphClkInit->PLLDivR));
lypinator	0:bb348c97df44	1382
lypinator	0:bb348c97df44	1383	/* SAI_CLK_x = SAI_CLK(first level)/PLLDIVR */
lypinator	0:bb348c97df44	1384	__HAL_RCC_PLL_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLDivR);
lypinator	0:bb348c97df44	1385	}
lypinator	0:bb348c97df44	1386	}
lypinator	0:bb348c97df44	1387	/--------------------------------------------------------------------------/
lypinator	0:bb348c97df44	1388	#endif /* STM32F413xx \|\| STM32F423xx */
lypinator	0:bb348c97df44	1389
lypinator	0:bb348c97df44	1390	/------------------------------------ RTC configuration -------------------/
lypinator	0:bb348c97df44	1391	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
lypinator	0:bb348c97df44	1392	{
lypinator	0:bb348c97df44	1393	/* Check for RTC Parameters used to output RTCCLK */
lypinator	0:bb348c97df44	1394	assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
lypinator	0:bb348c97df44	1395
lypinator	0:bb348c97df44	1396	/* Enable Power Clock*/
lypinator	0:bb348c97df44	1397	__HAL_RCC_PWR_CLK_ENABLE();
lypinator	0:bb348c97df44	1398
lypinator	0:bb348c97df44	1399	/* Enable write access to Backup domain */
lypinator	0:bb348c97df44	1400	PWR->CR \|= PWR_CR_DBP;
lypinator	0:bb348c97df44	1401
lypinator	0:bb348c97df44	1402	/* Get tick */
lypinator	0:bb348c97df44	1403	tickstart = HAL_GetTick();
lypinator	0:bb348c97df44	1404
lypinator	0:bb348c97df44	1405	while((PWR->CR & PWR_CR_DBP) == RESET)
lypinator	0:bb348c97df44	1406	{
lypinator	0:bb348c97df44	1407	if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
lypinator	0:bb348c97df44	1408	{
lypinator	0:bb348c97df44	1409	return HAL_TIMEOUT;
lypinator	0:bb348c97df44	1410	}
lypinator	0:bb348c97df44	1411	}
lypinator	0:bb348c97df44	1412	/* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
lypinator	0:bb348c97df44	1413	tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL);
lypinator	0:bb348c97df44	1414	if((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
lypinator	0:bb348c97df44	1415	{
lypinator	0:bb348c97df44	1416	/* Store the content of BDCR register before the reset of Backup Domain */
lypinator	0:bb348c97df44	1417	tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
lypinator	0:bb348c97df44	1418	/* RTC Clock selection can be changed only if the Backup Domain is reset */
lypinator	0:bb348c97df44	1419	__HAL_RCC_BACKUPRESET_FORCE();
lypinator	0:bb348c97df44	1420	__HAL_RCC_BACKUPRESET_RELEASE();
lypinator	0:bb348c97df44	1421	/* Restore the Content of BDCR register */
lypinator	0:bb348c97df44	1422	RCC->BDCR = tmpreg1;
lypinator	0:bb348c97df44	1423
lypinator	0:bb348c97df44	1424	/* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
lypinator	0:bb348c97df44	1425	if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))
lypinator	0:bb348c97df44	1426	{
lypinator	0:bb348c97df44	1427	/* Get tick */
lypinator	0:bb348c97df44	1428	tickstart = HAL_GetTick();
lypinator	0:bb348c97df44	1429
lypinator	0:bb348c97df44	1430	/* Wait till LSE is ready */
lypinator	0:bb348c97df44	1431	while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
lypinator	0:bb348c97df44	1432	{
lypinator	0:bb348c97df44	1433	if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
lypinator	0:bb348c97df44	1434	{
lypinator	0:bb348c97df44	1435	return HAL_TIMEOUT;
lypinator	0:bb348c97df44	1436	}
lypinator	0:bb348c97df44	1437	}
lypinator	0:bb348c97df44	1438	}
lypinator	0:bb348c97df44	1439	}
lypinator	0:bb348c97df44	1440	__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
lypinator	0:bb348c97df44	1441	}
lypinator	0:bb348c97df44	1442	/--------------------------------------------------------------------------/
lypinator	0:bb348c97df44	1443
lypinator	0:bb348c97df44	1444	/------------------------------------ TIM configuration -------------------/
lypinator	0:bb348c97df44	1445	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
lypinator	0:bb348c97df44	1446	{
lypinator	0:bb348c97df44	1447	/* Configure Timer Prescaler */
lypinator	0:bb348c97df44	1448	__HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
lypinator	0:bb348c97df44	1449	}
lypinator	0:bb348c97df44	1450	/--------------------------------------------------------------------------/
lypinator	0:bb348c97df44	1451
lypinator	0:bb348c97df44	1452	/------------------------------------- FMPI2C1 Configuration --------------/
lypinator	0:bb348c97df44	1453	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMPI2C1) == RCC_PERIPHCLK_FMPI2C1)
lypinator	0:bb348c97df44	1454	{
lypinator	0:bb348c97df44	1455	/* Check the parameters */
lypinator	0:bb348c97df44	1456	assert_param(IS_RCC_FMPI2C1CLKSOURCE(PeriphClkInit->Fmpi2c1ClockSelection));
lypinator	0:bb348c97df44	1457
lypinator	0:bb348c97df44	1458	/* Configure the FMPI2C1 clock source */
lypinator	0:bb348c97df44	1459	__HAL_RCC_FMPI2C1_CONFIG(PeriphClkInit->Fmpi2c1ClockSelection);
lypinator	0:bb348c97df44	1460	}
lypinator	0:bb348c97df44	1461	/--------------------------------------------------------------------------/
lypinator	0:bb348c97df44	1462
lypinator	0:bb348c97df44	1463	/------------------------------------- CLK48 Configuration ----------------/
lypinator	0:bb348c97df44	1464	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48)
lypinator	0:bb348c97df44	1465	{
lypinator	0:bb348c97df44	1466	/* Check the parameters */
lypinator	0:bb348c97df44	1467	assert_param(IS_RCC_CLK48CLKSOURCE(PeriphClkInit->Clk48ClockSelection));
lypinator	0:bb348c97df44	1468
lypinator	0:bb348c97df44	1469	/* Configure the SDIO clock source */
lypinator	0:bb348c97df44	1470	__HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection);
lypinator	0:bb348c97df44	1471
lypinator	0:bb348c97df44	1472	/* Enable the PLLI2S when it's used as clock source for CLK48 */
lypinator	0:bb348c97df44	1473	if(PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLI2SQ)
lypinator	0:bb348c97df44	1474	{
lypinator	0:bb348c97df44	1475	plli2sused = 1U;
lypinator	0:bb348c97df44	1476	}
lypinator	0:bb348c97df44	1477	}
lypinator	0:bb348c97df44	1478	/--------------------------------------------------------------------------/
lypinator	0:bb348c97df44	1479
lypinator	0:bb348c97df44	1480	/------------------------------------- SDIO Configuration -----------------/
lypinator	0:bb348c97df44	1481	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDIO) == RCC_PERIPHCLK_SDIO)
lypinator	0:bb348c97df44	1482	{
lypinator	0:bb348c97df44	1483	/* Check the parameters */
lypinator	0:bb348c97df44	1484	assert_param(IS_RCC_SDIOCLKSOURCE(PeriphClkInit->SdioClockSelection));
lypinator	0:bb348c97df44	1485
lypinator	0:bb348c97df44	1486	/* Configure the SDIO clock source */
lypinator	0:bb348c97df44	1487	__HAL_RCC_SDIO_CONFIG(PeriphClkInit->SdioClockSelection);
lypinator	0:bb348c97df44	1488	}
lypinator	0:bb348c97df44	1489	/--------------------------------------------------------------------------/
lypinator	0:bb348c97df44	1490
lypinator	0:bb348c97df44	1491	/-------------------------------------- PLLI2S Configuration --------------/
lypinator	0:bb348c97df44	1492	/* PLLI2S is configured when a peripheral will use it as source clock : I2S on APB1 or
lypinator	0:bb348c97df44	1493	I2S on APB2*/
lypinator	0:bb348c97df44	1494	if((plli2sused == 1U) \|\| (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S))
lypinator	0:bb348c97df44	1495	{
lypinator	0:bb348c97df44	1496	/* Disable the PLLI2S */
lypinator	0:bb348c97df44	1497	__HAL_RCC_PLLI2S_DISABLE();
lypinator	0:bb348c97df44	1498	/* Get tick */
lypinator	0:bb348c97df44	1499	tickstart = HAL_GetTick();
lypinator	0:bb348c97df44	1500	/* Wait till PLLI2S is disabled */
lypinator	0:bb348c97df44	1501	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
lypinator	0:bb348c97df44	1502	{
lypinator	0:bb348c97df44	1503	if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
lypinator	0:bb348c97df44	1504	{
lypinator	0:bb348c97df44	1505	/* return in case of Timeout detected */
lypinator	0:bb348c97df44	1506	return HAL_TIMEOUT;
lypinator	0:bb348c97df44	1507	}
lypinator	0:bb348c97df44	1508	}
lypinator	0:bb348c97df44	1509
lypinator	0:bb348c97df44	1510	/* check for common PLLI2S Parameters */
lypinator	0:bb348c97df44	1511	assert_param(IS_RCC_PLLI2SCLKSOURCE(PeriphClkInit->PLLI2SSelection));
lypinator	0:bb348c97df44	1512	assert_param(IS_RCC_PLLI2SM_VALUE(PeriphClkInit->PLLI2S.PLLI2SM));
lypinator	0:bb348c97df44	1513	assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
lypinator	0:bb348c97df44	1514	/-------------------- Set the PLL I2S clock -----------------------------/
lypinator	0:bb348c97df44	1515	__HAL_RCC_PLL_I2S_CONFIG(PeriphClkInit->PLLI2SSelection);
lypinator	0:bb348c97df44	1516
lypinator	0:bb348c97df44	1517	/------- In Case of PLLI2S is selected as source clock for I2S ----------/
lypinator	0:bb348c97df44	1518	if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == RCC_PERIPHCLK_I2S_APB1) && (PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S)) \|\|
lypinator	0:bb348c97df44	1519	((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == RCC_PERIPHCLK_I2S_APB2) && (PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S)) \|\|
lypinator	0:bb348c97df44	1520	((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLI2SQ)) \|\|
lypinator	0:bb348c97df44	1521	((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDIO) == RCC_PERIPHCLK_SDIO) && (PeriphClkInit->SdioClockSelection == RCC_SDIOCLKSOURCE_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLI2SQ)))
lypinator	0:bb348c97df44	1522	{
lypinator	0:bb348c97df44	1523	/* check for Parameters */
lypinator	0:bb348c97df44	1524	assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
lypinator	0:bb348c97df44	1525	assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
lypinator	0:bb348c97df44	1526
lypinator	0:bb348c97df44	1527	/* Configure the PLLI2S division factors */
lypinator	0:bb348c97df44	1528	/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM)*/
lypinator	0:bb348c97df44	1529	/* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
lypinator	0:bb348c97df44	1530	__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR);
lypinator	0:bb348c97df44	1531	}
lypinator	0:bb348c97df44	1532
lypinator	0:bb348c97df44	1533	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
lypinator	0:bb348c97df44	1534	/------- In Case of PLLI2S is selected as source clock for SAI ----------/
lypinator	0:bb348c97df44	1535	if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAIA) == RCC_PERIPHCLK_SAIA) && (PeriphClkInit->SaiAClockSelection == RCC_SAIACLKSOURCE_PLLI2SR)) \|\|
lypinator	0:bb348c97df44	1536	((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAIB) == RCC_PERIPHCLK_SAIB) && (PeriphClkInit->SaiBClockSelection == RCC_SAIBCLKSOURCE_PLLI2SR)))
lypinator	0:bb348c97df44	1537	{
lypinator	0:bb348c97df44	1538	/* Check for PLLI2S Parameters */
lypinator	0:bb348c97df44	1539	assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
lypinator	0:bb348c97df44	1540	/* Check for PLLI2S/DIVR parameters */
lypinator	0:bb348c97df44	1541	assert_param(IS_RCC_PLLI2S_DIVR_VALUE(PeriphClkInit->PLLI2SDivR));
lypinator	0:bb348c97df44	1542
lypinator	0:bb348c97df44	1543	/* Read PLLI2SQ value from PLLI2SCFGR register (this value is not needed for SAI configuration) */
lypinator	0:bb348c97df44	1544	plli2sq = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos);
lypinator	0:bb348c97df44	1545	/* Configure the PLLI2S division factors */
lypinator	0:bb348c97df44	1546	/* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */
lypinator	0:bb348c97df44	1547	/* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
lypinator	0:bb348c97df44	1548	/* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
lypinator	0:bb348c97df44	1549	__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, plli2sq, PeriphClkInit->PLLI2S.PLLI2SR);
lypinator	0:bb348c97df44	1550
lypinator	0:bb348c97df44	1551	/* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVR */
lypinator	0:bb348c97df44	1552	__HAL_RCC_PLLI2S_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLI2SDivR);
lypinator	0:bb348c97df44	1553	}
lypinator	0:bb348c97df44	1554	#endif /* STM32F413xx \|\| STM32F423xx */
lypinator	0:bb348c97df44	1555
lypinator	0:bb348c97df44	1556	/----------------- In Case of PLLI2S is just selected ------------------/
lypinator	0:bb348c97df44	1557	if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)
lypinator	0:bb348c97df44	1558	{
lypinator	0:bb348c97df44	1559	/* Check for Parameters */
lypinator	0:bb348c97df44	1560	assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
lypinator	0:bb348c97df44	1561	assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
lypinator	0:bb348c97df44	1562
lypinator	0:bb348c97df44	1563	/* Configure the PLLI2S division factors */
lypinator	0:bb348c97df44	1564	/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM)*/
lypinator	0:bb348c97df44	1565	/* SPDIFRXCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */
lypinator	0:bb348c97df44	1566	__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR);
lypinator	0:bb348c97df44	1567	}
lypinator	0:bb348c97df44	1568
lypinator	0:bb348c97df44	1569	/* Enable the PLLI2S */
lypinator	0:bb348c97df44	1570	__HAL_RCC_PLLI2S_ENABLE();
lypinator	0:bb348c97df44	1571	/* Get tick */
lypinator	0:bb348c97df44	1572	tickstart = HAL_GetTick();
lypinator	0:bb348c97df44	1573	/* Wait till PLLI2S is ready */
lypinator	0:bb348c97df44	1574	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
lypinator	0:bb348c97df44	1575	{
lypinator	0:bb348c97df44	1576	if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
lypinator	0:bb348c97df44	1577	{
lypinator	0:bb348c97df44	1578	/* return in case of Timeout detected */
lypinator	0:bb348c97df44	1579	return HAL_TIMEOUT;
lypinator	0:bb348c97df44	1580	}
lypinator	0:bb348c97df44	1581	}
lypinator	0:bb348c97df44	1582	}
lypinator	0:bb348c97df44	1583	/--------------------------------------------------------------------------/
lypinator	0:bb348c97df44	1584
lypinator	0:bb348c97df44	1585	/-------------------- DFSDM1 clock source configuration -------------------/
lypinator	0:bb348c97df44	1586	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1)
lypinator	0:bb348c97df44	1587	{
lypinator	0:bb348c97df44	1588	/* Check the parameters */
lypinator	0:bb348c97df44	1589	assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection));
lypinator	0:bb348c97df44	1590
lypinator	0:bb348c97df44	1591	/* Configure the DFSDM1 interface clock source */
lypinator	0:bb348c97df44	1592	__HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection);
lypinator	0:bb348c97df44	1593	}
lypinator	0:bb348c97df44	1594	/--------------------------------------------------------------------------/
lypinator	0:bb348c97df44	1595
lypinator	0:bb348c97df44	1596	/-------------------- DFSDM1 Audio clock source configuration -------------/
lypinator	0:bb348c97df44	1597	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1_AUDIO) == RCC_PERIPHCLK_DFSDM1_AUDIO)
lypinator	0:bb348c97df44	1598	{
lypinator	0:bb348c97df44	1599	/* Check the parameters */
lypinator	0:bb348c97df44	1600	assert_param(IS_RCC_DFSDM1AUDIOCLKSOURCE(PeriphClkInit->Dfsdm1AudioClockSelection));
lypinator	0:bb348c97df44	1601
lypinator	0:bb348c97df44	1602	/* Configure the DFSDM1 Audio interface clock source */
lypinator	0:bb348c97df44	1603	__HAL_RCC_DFSDM1AUDIO_CONFIG(PeriphClkInit->Dfsdm1AudioClockSelection);
lypinator	0:bb348c97df44	1604	}
lypinator	0:bb348c97df44	1605	/--------------------------------------------------------------------------/
lypinator	0:bb348c97df44	1606
lypinator	0:bb348c97df44	1607	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
lypinator	0:bb348c97df44	1608	/-------------------- DFSDM2 clock source configuration -------------------/
lypinator	0:bb348c97df44	1609	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM2) == RCC_PERIPHCLK_DFSDM2)
lypinator	0:bb348c97df44	1610	{
lypinator	0:bb348c97df44	1611	/* Check the parameters */
lypinator	0:bb348c97df44	1612	assert_param(IS_RCC_DFSDM2CLKSOURCE(PeriphClkInit->Dfsdm2ClockSelection));
lypinator	0:bb348c97df44	1613
lypinator	0:bb348c97df44	1614	/* Configure the DFSDM1 interface clock source */
lypinator	0:bb348c97df44	1615	__HAL_RCC_DFSDM2_CONFIG(PeriphClkInit->Dfsdm2ClockSelection);
lypinator	0:bb348c97df44	1616	}
lypinator	0:bb348c97df44	1617	/--------------------------------------------------------------------------/
lypinator	0:bb348c97df44	1618
lypinator	0:bb348c97df44	1619	/-------------------- DFSDM2 Audio clock source configuration -------------/
lypinator	0:bb348c97df44	1620	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM2_AUDIO) == RCC_PERIPHCLK_DFSDM2_AUDIO)
lypinator	0:bb348c97df44	1621	{
lypinator	0:bb348c97df44	1622	/* Check the parameters */
lypinator	0:bb348c97df44	1623	assert_param(IS_RCC_DFSDM2AUDIOCLKSOURCE(PeriphClkInit->Dfsdm2AudioClockSelection));
lypinator	0:bb348c97df44	1624
lypinator	0:bb348c97df44	1625	/* Configure the DFSDM1 Audio interface clock source */
lypinator	0:bb348c97df44	1626	__HAL_RCC_DFSDM2AUDIO_CONFIG(PeriphClkInit->Dfsdm2AudioClockSelection);
lypinator	0:bb348c97df44	1627	}
lypinator	0:bb348c97df44	1628	/--------------------------------------------------------------------------/
lypinator	0:bb348c97df44	1629
lypinator	0:bb348c97df44	1630	/---------------------------- LPTIM1 Configuration ------------------------/
lypinator	0:bb348c97df44	1631	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)
lypinator	0:bb348c97df44	1632	{
lypinator	0:bb348c97df44	1633	/* Check the parameters */
lypinator	0:bb348c97df44	1634	assert_param(IS_RCC_LPTIM1CLKSOURCE(PeriphClkInit->Lptim1ClockSelection));
lypinator	0:bb348c97df44	1635
lypinator	0:bb348c97df44	1636	/* Configure the LPTIM1 clock source */
lypinator	0:bb348c97df44	1637	__HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
lypinator	0:bb348c97df44	1638	}
lypinator	0:bb348c97df44	1639	/--------------------------------------------------------------------------/
lypinator	0:bb348c97df44	1640	#endif /* STM32F413xx \|\| STM32F423xx */
lypinator	0:bb348c97df44	1641
lypinator	0:bb348c97df44	1642	return HAL_OK;
lypinator	0:bb348c97df44	1643	}
lypinator	0:bb348c97df44	1644
lypinator	0:bb348c97df44	1645	/**
lypinator	0:bb348c97df44	1646	* @brief Get the RCC_PeriphCLKInitTypeDef according to the internal
lypinator	0:bb348c97df44	1647	* RCC configuration registers.
lypinator	0:bb348c97df44	1648	* @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
lypinator	0:bb348c97df44	1649	* will be configured.
lypinator	0:bb348c97df44	1650	* @retval None
lypinator	0:bb348c97df44	1651	*/
lypinator	0:bb348c97df44	1652	void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
lypinator	0:bb348c97df44	1653	{
lypinator	0:bb348c97df44	1654	uint32_t tempreg;
lypinator	0:bb348c97df44	1655
lypinator	0:bb348c97df44	1656	/* Set all possible values for the extended clock type parameter------------*/
lypinator	0:bb348c97df44	1657	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
lypinator	0:bb348c97df44	1658	PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S_APB1 \| RCC_PERIPHCLK_I2S_APB2 \|\
lypinator	0:bb348c97df44	1659	RCC_PERIPHCLK_TIM \| RCC_PERIPHCLK_RTC \|\
lypinator	0:bb348c97df44	1660	RCC_PERIPHCLK_FMPI2C1 \| RCC_PERIPHCLK_CLK48 \|\
lypinator	0:bb348c97df44	1661	RCC_PERIPHCLK_SDIO \| RCC_PERIPHCLK_DFSDM1 \|\
lypinator	0:bb348c97df44	1662	RCC_PERIPHCLK_DFSDM1_AUDIO \| RCC_PERIPHCLK_DFSDM2 \|\
lypinator	0:bb348c97df44	1663	RCC_PERIPHCLK_DFSDM2_AUDIO \| RCC_PERIPHCLK_LPTIM1 \|\
lypinator	0:bb348c97df44	1664	RCC_PERIPHCLK_SAIA \| RCC_PERIPHCLK_SAIB;
lypinator	0:bb348c97df44	1665	#else /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx */
lypinator	0:bb348c97df44	1666	PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S_APB1 \| RCC_PERIPHCLK_I2S_APB2 \|\
lypinator	0:bb348c97df44	1667	RCC_PERIPHCLK_TIM \| RCC_PERIPHCLK_RTC \|\
lypinator	0:bb348c97df44	1668	RCC_PERIPHCLK_FMPI2C1 \| RCC_PERIPHCLK_CLK48 \|\
lypinator	0:bb348c97df44	1669	RCC_PERIPHCLK_SDIO \| RCC_PERIPHCLK_DFSDM1 \|\
lypinator	0:bb348c97df44	1670	RCC_PERIPHCLK_DFSDM1_AUDIO;
lypinator	0:bb348c97df44	1671	#endif /* STM32F413xx \|\| STM32F423xx */
lypinator	0:bb348c97df44	1672
lypinator	0:bb348c97df44	1673
lypinator	0:bb348c97df44	1674
lypinator	0:bb348c97df44	1675	/* Get the PLLI2S Clock configuration --------------------------------------*/
lypinator	0:bb348c97df44	1676	PeriphClkInit->PLLI2S.PLLI2SM = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM) >> RCC_PLLI2SCFGR_PLLI2SM_Pos);
lypinator	0:bb348c97df44	1677	PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos);
lypinator	0:bb348c97df44	1678	PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos);
lypinator	0:bb348c97df44	1679	PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
lypinator	0:bb348c97df44	1680	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
lypinator	0:bb348c97df44	1681	/* Get the PLL/PLLI2S division factors -------------------------------------*/
lypinator	0:bb348c97df44	1682	PeriphClkInit->PLLI2SDivR = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVR) >> RCC_DCKCFGR_PLLI2SDIVR_Pos);
lypinator	0:bb348c97df44	1683	PeriphClkInit->PLLDivR = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLDIVR) >> RCC_DCKCFGR_PLLDIVR_Pos);
lypinator	0:bb348c97df44	1684	#endif /* STM32F413xx \|\| STM32F423xx */
lypinator	0:bb348c97df44	1685
lypinator	0:bb348c97df44	1686	/* Get the I2S APB1 clock configuration ------------------------------------*/
lypinator	0:bb348c97df44	1687	PeriphClkInit->I2sApb1ClockSelection = __HAL_RCC_GET_I2S_APB1_SOURCE();
lypinator	0:bb348c97df44	1688
lypinator	0:bb348c97df44	1689	/* Get the I2S APB2 clock configuration ------------------------------------*/
lypinator	0:bb348c97df44	1690	PeriphClkInit->I2sApb2ClockSelection = __HAL_RCC_GET_I2S_APB2_SOURCE();
lypinator	0:bb348c97df44	1691
lypinator	0:bb348c97df44	1692	/* Get the RTC Clock configuration -----------------------------------------*/
lypinator	0:bb348c97df44	1693	tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
lypinator	0:bb348c97df44	1694	PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) \| (RCC->BDCR & RCC_BDCR_RTCSEL));
lypinator	0:bb348c97df44	1695
lypinator	0:bb348c97df44	1696	/* Get the FMPI2C1 clock configuration -------------------------------------*/
lypinator	0:bb348c97df44	1697	PeriphClkInit->Fmpi2c1ClockSelection = __HAL_RCC_GET_FMPI2C1_SOURCE();
lypinator	0:bb348c97df44	1698
lypinator	0:bb348c97df44	1699	/* Get the CLK48 clock configuration ---------------------------------------*/
lypinator	0:bb348c97df44	1700	PeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE();
lypinator	0:bb348c97df44	1701
lypinator	0:bb348c97df44	1702	/* Get the SDIO clock configuration ----------------------------------------*/
lypinator	0:bb348c97df44	1703	PeriphClkInit->SdioClockSelection = __HAL_RCC_GET_SDIO_SOURCE();
lypinator	0:bb348c97df44	1704
lypinator	0:bb348c97df44	1705	/* Get the DFSDM1 clock configuration --------------------------------------*/
lypinator	0:bb348c97df44	1706	PeriphClkInit->Dfsdm1ClockSelection = __HAL_RCC_GET_DFSDM1_SOURCE();
lypinator	0:bb348c97df44	1707
lypinator	0:bb348c97df44	1708	/* Get the DFSDM1 Audio clock configuration --------------------------------*/
lypinator	0:bb348c97df44	1709	PeriphClkInit->Dfsdm1AudioClockSelection = __HAL_RCC_GET_DFSDM1AUDIO_SOURCE();
lypinator	0:bb348c97df44	1710
lypinator	0:bb348c97df44	1711	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
lypinator	0:bb348c97df44	1712	/* Get the DFSDM2 clock configuration --------------------------------------*/
lypinator	0:bb348c97df44	1713	PeriphClkInit->Dfsdm2ClockSelection = __HAL_RCC_GET_DFSDM2_SOURCE();
lypinator	0:bb348c97df44	1714
lypinator	0:bb348c97df44	1715	/* Get the DFSDM2 Audio clock configuration --------------------------------*/
lypinator	0:bb348c97df44	1716	PeriphClkInit->Dfsdm2AudioClockSelection = __HAL_RCC_GET_DFSDM2AUDIO_SOURCE();
lypinator	0:bb348c97df44	1717
lypinator	0:bb348c97df44	1718	/* Get the LPTIM1 clock configuration --------------------------------------*/
lypinator	0:bb348c97df44	1719	PeriphClkInit->Lptim1ClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE();
lypinator	0:bb348c97df44	1720
lypinator	0:bb348c97df44	1721	/* Get the SAI1 Block Aclock configuration ---------------------------------*/
lypinator	0:bb348c97df44	1722	PeriphClkInit->SaiAClockSelection = __HAL_RCC_GET_SAI_BLOCKA_SOURCE();
lypinator	0:bb348c97df44	1723
lypinator	0:bb348c97df44	1724	/* Get the SAI1 Block B clock configuration --------------------------------*/
lypinator	0:bb348c97df44	1725	PeriphClkInit->SaiBClockSelection = __HAL_RCC_GET_SAI_BLOCKB_SOURCE();
lypinator	0:bb348c97df44	1726	#endif /* STM32F413xx \|\| STM32F423xx */
lypinator	0:bb348c97df44	1727
lypinator	0:bb348c97df44	1728	/* Get the TIM Prescaler configuration -------------------------------------*/
lypinator	0:bb348c97df44	1729	if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET)
lypinator	0:bb348c97df44	1730	{
lypinator	0:bb348c97df44	1731	PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;
lypinator	0:bb348c97df44	1732	}
lypinator	0:bb348c97df44	1733	else
lypinator	0:bb348c97df44	1734	{
lypinator	0:bb348c97df44	1735	PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;
lypinator	0:bb348c97df44	1736	}
lypinator	0:bb348c97df44	1737	}
lypinator	0:bb348c97df44	1738
lypinator	0:bb348c97df44	1739	/**
lypinator	0:bb348c97df44	1740	* @brief Return the peripheral clock frequency for a given peripheral(I2S..)
lypinator	0:bb348c97df44	1741	* @note Return 0 if peripheral clock identifier not managed by this API
lypinator	0:bb348c97df44	1742	* @param PeriphClk Peripheral clock identifier
lypinator	0:bb348c97df44	1743	* This parameter can be one of the following values:
lypinator	0:bb348c97df44	1744	* @arg RCC_PERIPHCLK_I2S_APB1: I2S APB1 peripheral clock
lypinator	0:bb348c97df44	1745	* @arg RCC_PERIPHCLK_I2S_APB2: I2S APB2 peripheral clock
lypinator	0:bb348c97df44	1746	* @retval Frequency in KHz
lypinator	0:bb348c97df44	1747	*/
lypinator	0:bb348c97df44	1748	uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
lypinator	0:bb348c97df44	1749	{
lypinator	0:bb348c97df44	1750	/* This variable used to store the I2S clock frequency (value in Hz) */
lypinator	0:bb348c97df44	1751	uint32_t frequency = 0U;
lypinator	0:bb348c97df44	1752	/* This variable used to store the VCO Input (value in Hz) */
lypinator	0:bb348c97df44	1753	uint32_t vcoinput = 0U;
lypinator	0:bb348c97df44	1754	uint32_t srcclk = 0U;
lypinator	0:bb348c97df44	1755	/* This variable used to store the VCO Output (value in Hz) */
lypinator	0:bb348c97df44	1756	uint32_t vcooutput = 0U;
lypinator	0:bb348c97df44	1757	switch (PeriphClk)
lypinator	0:bb348c97df44	1758	{
lypinator	0:bb348c97df44	1759	case RCC_PERIPHCLK_I2S_APB1:
lypinator	0:bb348c97df44	1760	{
lypinator	0:bb348c97df44	1761	/* Get the current I2S source */
lypinator	0:bb348c97df44	1762	srcclk = __HAL_RCC_GET_I2S_APB1_SOURCE();
lypinator	0:bb348c97df44	1763	switch (srcclk)
lypinator	0:bb348c97df44	1764	{
lypinator	0:bb348c97df44	1765	/* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */
lypinator	0:bb348c97df44	1766	case RCC_I2SAPB1CLKSOURCE_EXT:
lypinator	0:bb348c97df44	1767	{
lypinator	0:bb348c97df44	1768	/* Set the I2S clock to the external clock value */
lypinator	0:bb348c97df44	1769	frequency = EXTERNAL_CLOCK_VALUE;
lypinator	0:bb348c97df44	1770	break;
lypinator	0:bb348c97df44	1771	}
lypinator	0:bb348c97df44	1772	/* Check if I2S clock selection is PLLI2S VCO output clock divided by PLLI2SR used as I2S clock */
lypinator	0:bb348c97df44	1773	case RCC_I2SAPB1CLKSOURCE_PLLI2S:
lypinator	0:bb348c97df44	1774	{
lypinator	0:bb348c97df44	1775	if((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SSRC) == RCC_PLLI2SCFGR_PLLI2SSRC)
lypinator	0:bb348c97df44	1776	{
lypinator	0:bb348c97df44	1777	/* Get the I2S source clock value */
lypinator	0:bb348c97df44	1778	vcoinput = (uint32_t)(EXTERNAL_CLOCK_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
lypinator	0:bb348c97df44	1779	}
lypinator	0:bb348c97df44	1780	else
lypinator	0:bb348c97df44	1781	{
lypinator	0:bb348c97df44	1782	/* Configure the PLLI2S division factor */
lypinator	0:bb348c97df44	1783	/* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */
lypinator	0:bb348c97df44	1784	if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
lypinator	0:bb348c97df44	1785	{
lypinator	0:bb348c97df44	1786	/* Get the I2S source clock value */
lypinator	0:bb348c97df44	1787	vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
lypinator	0:bb348c97df44	1788	}
lypinator	0:bb348c97df44	1789	else
lypinator	0:bb348c97df44	1790	{
lypinator	0:bb348c97df44	1791	/* Get the I2S source clock value */
lypinator	0:bb348c97df44	1792	vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
lypinator	0:bb348c97df44	1793	}
lypinator	0:bb348c97df44	1794	}
lypinator	0:bb348c97df44	1795	/* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
lypinator	0:bb348c97df44	1796	vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U)));
lypinator	0:bb348c97df44	1797	/* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */
lypinator	0:bb348c97df44	1798	frequency = (uint32_t)(vcooutput /(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U) & (RCC_PLLI2SCFGR_PLLI2SR >> 28U)));
lypinator	0:bb348c97df44	1799	break;
lypinator	0:bb348c97df44	1800	}
lypinator	0:bb348c97df44	1801	/* Check if I2S clock selection is PLL VCO Output divided by PLLR used as I2S clock */
lypinator	0:bb348c97df44	1802	case RCC_I2SAPB1CLKSOURCE_PLLR:
lypinator	0:bb348c97df44	1803	{
lypinator	0:bb348c97df44	1804	/* Configure the PLL division factor R */
lypinator	0:bb348c97df44	1805	/* PLL_VCO Input = PLL_SOURCE/PLLM */
lypinator	0:bb348c97df44	1806	if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
lypinator	0:bb348c97df44	1807	{
lypinator	0:bb348c97df44	1808	/* Get the I2S source clock value */
lypinator	0:bb348c97df44	1809	vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
lypinator	0:bb348c97df44	1810	}
lypinator	0:bb348c97df44	1811	else
lypinator	0:bb348c97df44	1812	{
lypinator	0:bb348c97df44	1813	/* Get the I2S source clock value */
lypinator	0:bb348c97df44	1814	vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
lypinator	0:bb348c97df44	1815	}
lypinator	0:bb348c97df44	1816
lypinator	0:bb348c97df44	1817	/* PLL_VCO Output = PLL_VCO Input * PLLN */
lypinator	0:bb348c97df44	1818	vcooutput = (uint32_t)(vcoinput * (((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6U) & (RCC_PLLCFGR_PLLN >> 6U)));
lypinator	0:bb348c97df44	1819	/* I2S_CLK = PLL_VCO Output/PLLR */
lypinator	0:bb348c97df44	1820	frequency = (uint32_t)(vcooutput /(((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 28U) & (RCC_PLLCFGR_PLLR >> 28U)));
lypinator	0:bb348c97df44	1821	break;
lypinator	0:bb348c97df44	1822	}
lypinator	0:bb348c97df44	1823	/* Check if I2S clock selection is HSI or HSE depending from PLL source Clock */
lypinator	0:bb348c97df44	1824	case RCC_I2SAPB1CLKSOURCE_PLLSRC:
lypinator	0:bb348c97df44	1825	{
lypinator	0:bb348c97df44	1826	if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
lypinator	0:bb348c97df44	1827	{
lypinator	0:bb348c97df44	1828	frequency = HSE_VALUE;
lypinator	0:bb348c97df44	1829	}
lypinator	0:bb348c97df44	1830	else
lypinator	0:bb348c97df44	1831	{
lypinator	0:bb348c97df44	1832	frequency = HSI_VALUE;
lypinator	0:bb348c97df44	1833	}
lypinator	0:bb348c97df44	1834	break;
lypinator	0:bb348c97df44	1835	}
lypinator	0:bb348c97df44	1836	/* Clock not enabled for I2S*/
lypinator	0:bb348c97df44	1837	default:
lypinator	0:bb348c97df44	1838	{
lypinator	0:bb348c97df44	1839	frequency = 0U;
lypinator	0:bb348c97df44	1840	break;
lypinator	0:bb348c97df44	1841	}
lypinator	0:bb348c97df44	1842	}
lypinator	0:bb348c97df44	1843	break;
lypinator	0:bb348c97df44	1844	}
lypinator	0:bb348c97df44	1845	case RCC_PERIPHCLK_I2S_APB2:
lypinator	0:bb348c97df44	1846	{
lypinator	0:bb348c97df44	1847	/* Get the current I2S source */
lypinator	0:bb348c97df44	1848	srcclk = __HAL_RCC_GET_I2S_APB2_SOURCE();
lypinator	0:bb348c97df44	1849	switch (srcclk)
lypinator	0:bb348c97df44	1850	{
lypinator	0:bb348c97df44	1851	/* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */
lypinator	0:bb348c97df44	1852	case RCC_I2SAPB2CLKSOURCE_EXT:
lypinator	0:bb348c97df44	1853	{
lypinator	0:bb348c97df44	1854	/* Set the I2S clock to the external clock value */
lypinator	0:bb348c97df44	1855	frequency = EXTERNAL_CLOCK_VALUE;
lypinator	0:bb348c97df44	1856	break;
lypinator	0:bb348c97df44	1857	}
lypinator	0:bb348c97df44	1858	/* Check if I2S clock selection is PLLI2S VCO output clock divided by PLLI2SR used as I2S clock */
lypinator	0:bb348c97df44	1859	case RCC_I2SAPB2CLKSOURCE_PLLI2S:
lypinator	0:bb348c97df44	1860	{
lypinator	0:bb348c97df44	1861	if((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SSRC) == RCC_PLLI2SCFGR_PLLI2SSRC)
lypinator	0:bb348c97df44	1862	{
lypinator	0:bb348c97df44	1863	/* Get the I2S source clock value */
lypinator	0:bb348c97df44	1864	vcoinput = (uint32_t)(EXTERNAL_CLOCK_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
lypinator	0:bb348c97df44	1865	}
lypinator	0:bb348c97df44	1866	else
lypinator	0:bb348c97df44	1867	{
lypinator	0:bb348c97df44	1868	/* Configure the PLLI2S division factor */
lypinator	0:bb348c97df44	1869	/* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */
lypinator	0:bb348c97df44	1870	if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
lypinator	0:bb348c97df44	1871	{
lypinator	0:bb348c97df44	1872	/* Get the I2S source clock value */
lypinator	0:bb348c97df44	1873	vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
lypinator	0:bb348c97df44	1874	}
lypinator	0:bb348c97df44	1875	else
lypinator	0:bb348c97df44	1876	{
lypinator	0:bb348c97df44	1877	/* Get the I2S source clock value */
lypinator	0:bb348c97df44	1878	vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
lypinator	0:bb348c97df44	1879	}
lypinator	0:bb348c97df44	1880	}
lypinator	0:bb348c97df44	1881	/* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
lypinator	0:bb348c97df44	1882	vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U)));
lypinator	0:bb348c97df44	1883	/* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */
lypinator	0:bb348c97df44	1884	frequency = (uint32_t)(vcooutput /(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U) & (RCC_PLLI2SCFGR_PLLI2SR >> 28U)));
lypinator	0:bb348c97df44	1885	break;
lypinator	0:bb348c97df44	1886	}
lypinator	0:bb348c97df44	1887	/* Check if I2S clock selection is PLL VCO Output divided by PLLR used as I2S clock */
lypinator	0:bb348c97df44	1888	case RCC_I2SAPB2CLKSOURCE_PLLR:
lypinator	0:bb348c97df44	1889	{
lypinator	0:bb348c97df44	1890	/* Configure the PLL division factor R */
lypinator	0:bb348c97df44	1891	/* PLL_VCO Input = PLL_SOURCE/PLLM */
lypinator	0:bb348c97df44	1892	if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
lypinator	0:bb348c97df44	1893	{
lypinator	0:bb348c97df44	1894	/* Get the I2S source clock value */
lypinator	0:bb348c97df44	1895	vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
lypinator	0:bb348c97df44	1896	}
lypinator	0:bb348c97df44	1897	else
lypinator	0:bb348c97df44	1898	{
lypinator	0:bb348c97df44	1899	/* Get the I2S source clock value */
lypinator	0:bb348c97df44	1900	vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
lypinator	0:bb348c97df44	1901	}
lypinator	0:bb348c97df44	1902
lypinator	0:bb348c97df44	1903	/* PLL_VCO Output = PLL_VCO Input * PLLN */
lypinator	0:bb348c97df44	1904	vcooutput = (uint32_t)(vcoinput * (((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6U) & (RCC_PLLCFGR_PLLN >> 6U)));
lypinator	0:bb348c97df44	1905	/* I2S_CLK = PLL_VCO Output/PLLR */
lypinator	0:bb348c97df44	1906	frequency = (uint32_t)(vcooutput /(((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 28U) & (RCC_PLLCFGR_PLLR >> 28U)));
lypinator	0:bb348c97df44	1907	break;
lypinator	0:bb348c97df44	1908	}
lypinator	0:bb348c97df44	1909	/* Check if I2S clock selection is HSI or HSE depending from PLL source Clock */
lypinator	0:bb348c97df44	1910	case RCC_I2SAPB2CLKSOURCE_PLLSRC:
lypinator	0:bb348c97df44	1911	{
lypinator	0:bb348c97df44	1912	if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
lypinator	0:bb348c97df44	1913	{
lypinator	0:bb348c97df44	1914	frequency = HSE_VALUE;
lypinator	0:bb348c97df44	1915	}
lypinator	0:bb348c97df44	1916	else
lypinator	0:bb348c97df44	1917	{
lypinator	0:bb348c97df44	1918	frequency = HSI_VALUE;
lypinator	0:bb348c97df44	1919	}
lypinator	0:bb348c97df44	1920	break;
lypinator	0:bb348c97df44	1921	}
lypinator	0:bb348c97df44	1922	/* Clock not enabled for I2S*/
lypinator	0:bb348c97df44	1923	default:
lypinator	0:bb348c97df44	1924	{
lypinator	0:bb348c97df44	1925	frequency = 0U;
lypinator	0:bb348c97df44	1926	break;
lypinator	0:bb348c97df44	1927	}
lypinator	0:bb348c97df44	1928	}
lypinator	0:bb348c97df44	1929	break;
lypinator	0:bb348c97df44	1930	}
lypinator	0:bb348c97df44	1931	}
lypinator	0:bb348c97df44	1932	return frequency;
lypinator	0:bb348c97df44	1933	}
lypinator	0:bb348c97df44	1934	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx \|\| STM32F413xx \|\| STM32F423xx */
lypinator	0:bb348c97df44	1935
lypinator	0:bb348c97df44	1936	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
lypinator	0:bb348c97df44	1937	/**
lypinator	0:bb348c97df44	1938	* @brief Initializes the RCC extended peripherals clocks according to the specified parameters in the
lypinator	0:bb348c97df44	1939	* RCC_PeriphCLKInitTypeDef.
lypinator	0:bb348c97df44	1940	* @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
lypinator	0:bb348c97df44	1941	* contains the configuration information for the Extended Peripherals clocks(I2S and RTC clocks).
lypinator	0:bb348c97df44	1942	*
lypinator	0:bb348c97df44	1943	* @note A caution to be taken when HAL_RCCEx_PeriphCLKConfig() is used to select RTC clock selection, in this case
lypinator	0:bb348c97df44	1944	* the Reset of Backup domain will be applied in order to modify the RTC Clock source as consequence all backup
lypinator	0:bb348c97df44	1945	* domain (RTC and RCC_BDCR register expect BKPSRAM) will be reset
lypinator	0:bb348c97df44	1946	*
lypinator	0:bb348c97df44	1947	* @retval HAL status
lypinator	0:bb348c97df44	1948	*/
lypinator	0:bb348c97df44	1949	HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
lypinator	0:bb348c97df44	1950	{
lypinator	0:bb348c97df44	1951	uint32_t tickstart = 0U;
lypinator	0:bb348c97df44	1952	uint32_t tmpreg1 = 0U;
lypinator	0:bb348c97df44	1953
lypinator	0:bb348c97df44	1954	/* Check the parameters */
lypinator	0:bb348c97df44	1955	assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
lypinator	0:bb348c97df44	1956
lypinator	0:bb348c97df44	1957	/---------------------------- RTC configuration ---------------------------/
lypinator	0:bb348c97df44	1958	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
lypinator	0:bb348c97df44	1959	{
lypinator	0:bb348c97df44	1960	/* Check for RTC Parameters used to output RTCCLK */
lypinator	0:bb348c97df44	1961	assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
lypinator	0:bb348c97df44	1962
lypinator	0:bb348c97df44	1963	/* Enable Power Clock*/
lypinator	0:bb348c97df44	1964	__HAL_RCC_PWR_CLK_ENABLE();
lypinator	0:bb348c97df44	1965
lypinator	0:bb348c97df44	1966	/* Enable write access to Backup domain */
lypinator	0:bb348c97df44	1967	PWR->CR \|= PWR_CR_DBP;
lypinator	0:bb348c97df44	1968
lypinator	0:bb348c97df44	1969	/* Get tick */
lypinator	0:bb348c97df44	1970	tickstart = HAL_GetTick();
lypinator	0:bb348c97df44	1971
lypinator	0:bb348c97df44	1972	while((PWR->CR & PWR_CR_DBP) == RESET)
lypinator	0:bb348c97df44	1973	{
lypinator	0:bb348c97df44	1974	if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
lypinator	0:bb348c97df44	1975	{
lypinator	0:bb348c97df44	1976	return HAL_TIMEOUT;
lypinator	0:bb348c97df44	1977	}
lypinator	0:bb348c97df44	1978	}
lypinator	0:bb348c97df44	1979	/* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
lypinator	0:bb348c97df44	1980	tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL);
lypinator	0:bb348c97df44	1981	if((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
lypinator	0:bb348c97df44	1982	{
lypinator	0:bb348c97df44	1983	/* Store the content of BDCR register before the reset of Backup Domain */
lypinator	0:bb348c97df44	1984	tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
lypinator	0:bb348c97df44	1985	/* RTC Clock selection can be changed only if the Backup Domain is reset */
lypinator	0:bb348c97df44	1986	__HAL_RCC_BACKUPRESET_FORCE();
lypinator	0:bb348c97df44	1987	__HAL_RCC_BACKUPRESET_RELEASE();
lypinator	0:bb348c97df44	1988	/* Restore the Content of BDCR register */
lypinator	0:bb348c97df44	1989	RCC->BDCR = tmpreg1;
lypinator	0:bb348c97df44	1990
lypinator	0:bb348c97df44	1991	/* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
lypinator	0:bb348c97df44	1992	if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))
lypinator	0:bb348c97df44	1993	{
lypinator	0:bb348c97df44	1994	/* Get tick */
lypinator	0:bb348c97df44	1995	tickstart = HAL_GetTick();
lypinator	0:bb348c97df44	1996
lypinator	0:bb348c97df44	1997	/* Wait till LSE is ready */
lypinator	0:bb348c97df44	1998	while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
lypinator	0:bb348c97df44	1999	{
lypinator	0:bb348c97df44	2000	if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
lypinator	0:bb348c97df44	2001	{
lypinator	0:bb348c97df44	2002	return HAL_TIMEOUT;
lypinator	0:bb348c97df44	2003	}
lypinator	0:bb348c97df44	2004	}
lypinator	0:bb348c97df44	2005	}
lypinator	0:bb348c97df44	2006	}
lypinator	0:bb348c97df44	2007	__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
lypinator	0:bb348c97df44	2008	}
lypinator	0:bb348c97df44	2009	/--------------------------------------------------------------------------/
lypinator	0:bb348c97df44	2010
lypinator	0:bb348c97df44	2011	/---------------------------- TIM configuration ---------------------------/
lypinator	0:bb348c97df44	2012	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
lypinator	0:bb348c97df44	2013	{
lypinator	0:bb348c97df44	2014	__HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
lypinator	0:bb348c97df44	2015	}
lypinator	0:bb348c97df44	2016	/--------------------------------------------------------------------------/
lypinator	0:bb348c97df44	2017
lypinator	0:bb348c97df44	2018	/---------------------------- FMPI2C1 Configuration -----------------------/
lypinator	0:bb348c97df44	2019	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMPI2C1) == RCC_PERIPHCLK_FMPI2C1)
lypinator	0:bb348c97df44	2020	{
lypinator	0:bb348c97df44	2021	/* Check the parameters */
lypinator	0:bb348c97df44	2022	assert_param(IS_RCC_FMPI2C1CLKSOURCE(PeriphClkInit->Fmpi2c1ClockSelection));
lypinator	0:bb348c97df44	2023
lypinator	0:bb348c97df44	2024	/* Configure the FMPI2C1 clock source */
lypinator	0:bb348c97df44	2025	__HAL_RCC_FMPI2C1_CONFIG(PeriphClkInit->Fmpi2c1ClockSelection);
lypinator	0:bb348c97df44	2026	}
lypinator	0:bb348c97df44	2027	/--------------------------------------------------------------------------/
lypinator	0:bb348c97df44	2028
lypinator	0:bb348c97df44	2029	/---------------------------- LPTIM1 Configuration ------------------------/
lypinator	0:bb348c97df44	2030	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)
lypinator	0:bb348c97df44	2031	{
lypinator	0:bb348c97df44	2032	/* Check the parameters */
lypinator	0:bb348c97df44	2033	assert_param(IS_RCC_LPTIM1CLKSOURCE(PeriphClkInit->Lptim1ClockSelection));
lypinator	0:bb348c97df44	2034
lypinator	0:bb348c97df44	2035	/* Configure the LPTIM1 clock source */
lypinator	0:bb348c97df44	2036	__HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
lypinator	0:bb348c97df44	2037	}
lypinator	0:bb348c97df44	2038
lypinator	0:bb348c97df44	2039	/---------------------------- I2S Configuration ---------------------------/
lypinator	0:bb348c97df44	2040	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S)
lypinator	0:bb348c97df44	2041	{
lypinator	0:bb348c97df44	2042	/* Check the parameters */
lypinator	0:bb348c97df44	2043	assert_param(IS_RCC_I2SAPBCLKSOURCE(PeriphClkInit->I2SClockSelection));
lypinator	0:bb348c97df44	2044
lypinator	0:bb348c97df44	2045	/* Configure the I2S clock source */
lypinator	0:bb348c97df44	2046	__HAL_RCC_I2S_CONFIG(PeriphClkInit->I2SClockSelection);
lypinator	0:bb348c97df44	2047	}
lypinator	0:bb348c97df44	2048
lypinator	0:bb348c97df44	2049	return HAL_OK;
lypinator	0:bb348c97df44	2050	}
lypinator	0:bb348c97df44	2051
lypinator	0:bb348c97df44	2052	/**
lypinator	0:bb348c97df44	2053	* @brief Configures the RCC_OscInitStruct according to the internal
lypinator	0:bb348c97df44	2054	* RCC configuration registers.
lypinator	0:bb348c97df44	2055	* @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
lypinator	0:bb348c97df44	2056	* will be configured.
lypinator	0:bb348c97df44	2057	* @retval None
lypinator	0:bb348c97df44	2058	*/
lypinator	0:bb348c97df44	2059	void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
lypinator	0:bb348c97df44	2060	{
lypinator	0:bb348c97df44	2061	uint32_t tempreg;
lypinator	0:bb348c97df44	2062
lypinator	0:bb348c97df44	2063	/* Set all possible values for the extended clock type parameter------------*/
lypinator	0:bb348c97df44	2064	PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_FMPI2C1 \| RCC_PERIPHCLK_LPTIM1 \| RCC_PERIPHCLK_TIM \| RCC_PERIPHCLK_RTC;
lypinator	0:bb348c97df44	2065
lypinator	0:bb348c97df44	2066	tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
lypinator	0:bb348c97df44	2067	PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) \| (RCC->BDCR & RCC_BDCR_RTCSEL));
lypinator	0:bb348c97df44	2068
lypinator	0:bb348c97df44	2069	if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET)
lypinator	0:bb348c97df44	2070	{
lypinator	0:bb348c97df44	2071	PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;
lypinator	0:bb348c97df44	2072	}
lypinator	0:bb348c97df44	2073	else
lypinator	0:bb348c97df44	2074	{
lypinator	0:bb348c97df44	2075	PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;
lypinator	0:bb348c97df44	2076	}
lypinator	0:bb348c97df44	2077	/* Get the FMPI2C1 clock configuration -------------------------------------*/
lypinator	0:bb348c97df44	2078	PeriphClkInit->Fmpi2c1ClockSelection = __HAL_RCC_GET_FMPI2C1_SOURCE();
lypinator	0:bb348c97df44	2079
lypinator	0:bb348c97df44	2080	/* Get the I2S clock configuration -----------------------------------------*/
lypinator	0:bb348c97df44	2081	PeriphClkInit->I2SClockSelection = __HAL_RCC_GET_I2S_SOURCE();
lypinator	0:bb348c97df44	2082
lypinator	0:bb348c97df44	2083
lypinator	0:bb348c97df44	2084	}
lypinator	0:bb348c97df44	2085	/**
lypinator	0:bb348c97df44	2086	* @brief Return the peripheral clock frequency for a given peripheral(SAI..)
lypinator	0:bb348c97df44	2087	* @note Return 0 if peripheral clock identifier not managed by this API
lypinator	0:bb348c97df44	2088	* @param PeriphClk Peripheral clock identifier
lypinator	0:bb348c97df44	2089	* This parameter can be one of the following values:
lypinator	0:bb348c97df44	2090	* @arg RCC_PERIPHCLK_I2S: I2S peripheral clock
lypinator	0:bb348c97df44	2091	* @retval Frequency in KHz
lypinator	0:bb348c97df44	2092	*/
lypinator	0:bb348c97df44	2093	uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
lypinator	0:bb348c97df44	2094	{
lypinator	0:bb348c97df44	2095	/* This variable used to store the I2S clock frequency (value in Hz) */
lypinator	0:bb348c97df44	2096	uint32_t frequency = 0U;
lypinator	0:bb348c97df44	2097	/* This variable used to store the VCO Input (value in Hz) */
lypinator	0:bb348c97df44	2098	uint32_t vcoinput = 0U;
lypinator	0:bb348c97df44	2099	uint32_t srcclk = 0U;
lypinator	0:bb348c97df44	2100	/* This variable used to store the VCO Output (value in Hz) */
lypinator	0:bb348c97df44	2101	uint32_t vcooutput = 0U;
lypinator	0:bb348c97df44	2102	switch (PeriphClk)
lypinator	0:bb348c97df44	2103	{
lypinator	0:bb348c97df44	2104	case RCC_PERIPHCLK_I2S:
lypinator	0:bb348c97df44	2105	{
lypinator	0:bb348c97df44	2106	/* Get the current I2S source */
lypinator	0:bb348c97df44	2107	srcclk = __HAL_RCC_GET_I2S_SOURCE();
lypinator	0:bb348c97df44	2108	switch (srcclk)
lypinator	0:bb348c97df44	2109	{
lypinator	0:bb348c97df44	2110	/* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */
lypinator	0:bb348c97df44	2111	case RCC_I2SAPBCLKSOURCE_EXT:
lypinator	0:bb348c97df44	2112	{
lypinator	0:bb348c97df44	2113	/* Set the I2S clock to the external clock value */
lypinator	0:bb348c97df44	2114	frequency = EXTERNAL_CLOCK_VALUE;
lypinator	0:bb348c97df44	2115	break;
lypinator	0:bb348c97df44	2116	}
lypinator	0:bb348c97df44	2117	/* Check if I2S clock selection is PLL VCO Output divided by PLLR used as I2S clock */
lypinator	0:bb348c97df44	2118	case RCC_I2SAPBCLKSOURCE_PLLR:
lypinator	0:bb348c97df44	2119	{
lypinator	0:bb348c97df44	2120	/* Configure the PLL division factor R */
lypinator	0:bb348c97df44	2121	/* PLL_VCO Input = PLL_SOURCE/PLLM */
lypinator	0:bb348c97df44	2122	if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
lypinator	0:bb348c97df44	2123	{
lypinator	0:bb348c97df44	2124	/* Get the I2S source clock value */
lypinator	0:bb348c97df44	2125	vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
lypinator	0:bb348c97df44	2126	}
lypinator	0:bb348c97df44	2127	else
lypinator	0:bb348c97df44	2128	{
lypinator	0:bb348c97df44	2129	/* Get the I2S source clock value */
lypinator	0:bb348c97df44	2130	vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
lypinator	0:bb348c97df44	2131	}
lypinator	0:bb348c97df44	2132
lypinator	0:bb348c97df44	2133	/* PLL_VCO Output = PLL_VCO Input * PLLN */
lypinator	0:bb348c97df44	2134	vcooutput = (uint32_t)(vcoinput * (((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6U) & (RCC_PLLCFGR_PLLN >> 6U)));
lypinator	0:bb348c97df44	2135	/* I2S_CLK = PLL_VCO Output/PLLR */
lypinator	0:bb348c97df44	2136	frequency = (uint32_t)(vcooutput /(((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 28U) & (RCC_PLLCFGR_PLLR >> 28U)));
lypinator	0:bb348c97df44	2137	break;
lypinator	0:bb348c97df44	2138	}
lypinator	0:bb348c97df44	2139	/* Check if I2S clock selection is HSI or HSE depending from PLL source Clock */
lypinator	0:bb348c97df44	2140	case RCC_I2SAPBCLKSOURCE_PLLSRC:
lypinator	0:bb348c97df44	2141	{
lypinator	0:bb348c97df44	2142	if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
lypinator	0:bb348c97df44	2143	{
lypinator	0:bb348c97df44	2144	frequency = HSE_VALUE;
lypinator	0:bb348c97df44	2145	}
lypinator	0:bb348c97df44	2146	else
lypinator	0:bb348c97df44	2147	{
lypinator	0:bb348c97df44	2148	frequency = HSI_VALUE;
lypinator	0:bb348c97df44	2149	}
lypinator	0:bb348c97df44	2150	break;
lypinator	0:bb348c97df44	2151	}
lypinator	0:bb348c97df44	2152	/* Clock not enabled for I2S*/
lypinator	0:bb348c97df44	2153	default:
lypinator	0:bb348c97df44	2154	{
lypinator	0:bb348c97df44	2155	frequency = 0U;
lypinator	0:bb348c97df44	2156	break;
lypinator	0:bb348c97df44	2157	}
lypinator	0:bb348c97df44	2158	}
lypinator	0:bb348c97df44	2159	break;
lypinator	0:bb348c97df44	2160	}
lypinator	0:bb348c97df44	2161	}
lypinator	0:bb348c97df44	2162	return frequency;
lypinator	0:bb348c97df44	2163	}
lypinator	0:bb348c97df44	2164	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
lypinator	0:bb348c97df44	2165
lypinator	0:bb348c97df44	2166	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
lypinator	0:bb348c97df44	2167	/**
lypinator	0:bb348c97df44	2168	* @brief Initializes the RCC extended peripherals clocks according to the specified
lypinator	0:bb348c97df44	2169	* parameters in the RCC_PeriphCLKInitTypeDef.
lypinator	0:bb348c97df44	2170	* @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
lypinator	0:bb348c97df44	2171	* contains the configuration information for the Extended Peripherals
lypinator	0:bb348c97df44	2172	* clocks(I2S, SAI, LTDC RTC and TIM).
lypinator	0:bb348c97df44	2173	*
lypinator	0:bb348c97df44	2174	* @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
lypinator	0:bb348c97df44	2175	* the RTC clock source; in this case the Backup domain will be reset in
lypinator	0:bb348c97df44	2176	* order to modify the RTC Clock source, as consequence RTC registers (including
lypinator	0:bb348c97df44	2177	* the backup registers) and RCC_BDCR register are set to their reset values.
lypinator	0:bb348c97df44	2178	*
lypinator	0:bb348c97df44	2179	* @retval HAL status
lypinator	0:bb348c97df44	2180	*/
lypinator	0:bb348c97df44	2181	HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
lypinator	0:bb348c97df44	2182	{
lypinator	0:bb348c97df44	2183	uint32_t tickstart = 0U;
lypinator	0:bb348c97df44	2184	uint32_t tmpreg1 = 0U;
lypinator	0:bb348c97df44	2185
lypinator	0:bb348c97df44	2186	/* Check the parameters */
lypinator	0:bb348c97df44	2187	assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
lypinator	0:bb348c97df44	2188
lypinator	0:bb348c97df44	2189	/----------------------- SAI/I2S Configuration (PLLI2S) -------------------/
lypinator	0:bb348c97df44	2190	/----------------------- Common configuration SAI/I2S ---------------------/
lypinator	0:bb348c97df44	2191	/* In Case of SAI or I2S Clock Configuration through PLLI2S, PLLI2SN division
lypinator	0:bb348c97df44	2192	factor is common parameters for both peripherals */
lypinator	0:bb348c97df44	2193	if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) \|\|
lypinator	0:bb348c97df44	2194	(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == RCC_PERIPHCLK_SAI_PLLI2S))
lypinator	0:bb348c97df44	2195	{
lypinator	0:bb348c97df44	2196	/* check for Parameters */
lypinator	0:bb348c97df44	2197	assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
lypinator	0:bb348c97df44	2198
lypinator	0:bb348c97df44	2199	/* Disable the PLLI2S */
lypinator	0:bb348c97df44	2200	__HAL_RCC_PLLI2S_DISABLE();
lypinator	0:bb348c97df44	2201	/* Get tick */
lypinator	0:bb348c97df44	2202	tickstart = HAL_GetTick();
lypinator	0:bb348c97df44	2203	/* Wait till PLLI2S is disabled */
lypinator	0:bb348c97df44	2204	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
lypinator	0:bb348c97df44	2205	{
lypinator	0:bb348c97df44	2206	if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
lypinator	0:bb348c97df44	2207	{
lypinator	0:bb348c97df44	2208	/* return in case of Timeout detected */
lypinator	0:bb348c97df44	2209	return HAL_TIMEOUT;
lypinator	0:bb348c97df44	2210	}
lypinator	0:bb348c97df44	2211	}
lypinator	0:bb348c97df44	2212
lypinator	0:bb348c97df44	2213	/---------------------------- I2S configuration -------------------------/
lypinator	0:bb348c97df44	2214	/* In Case of I2S Clock Configuration through PLLI2S, PLLI2SR must be added
lypinator	0:bb348c97df44	2215	only for I2S configuration */
lypinator	0:bb348c97df44	2216	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S))
lypinator	0:bb348c97df44	2217	{
lypinator	0:bb348c97df44	2218	/* check for Parameters */
lypinator	0:bb348c97df44	2219	assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
lypinator	0:bb348c97df44	2220	/* Configure the PLLI2S division factors */
lypinator	0:bb348c97df44	2221	/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLM) */
lypinator	0:bb348c97df44	2222	/* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
lypinator	0:bb348c97df44	2223	__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SR);
lypinator	0:bb348c97df44	2224	}
lypinator	0:bb348c97df44	2225
lypinator	0:bb348c97df44	2226	/---------------------------- SAI configuration -------------------------/
lypinator	0:bb348c97df44	2227	/* In Case of SAI Clock Configuration through PLLI2S, PLLI2SQ and PLLI2S_DIVQ must
lypinator	0:bb348c97df44	2228	be added only for SAI configuration */
lypinator	0:bb348c97df44	2229	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == (RCC_PERIPHCLK_SAI_PLLI2S))
lypinator	0:bb348c97df44	2230	{
lypinator	0:bb348c97df44	2231	/* Check the PLLI2S division factors */
lypinator	0:bb348c97df44	2232	assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
lypinator	0:bb348c97df44	2233	assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ));
lypinator	0:bb348c97df44	2234
lypinator	0:bb348c97df44	2235	/* Read PLLI2SR value from PLLI2SCFGR register (this value is not need for SAI configuration) */
lypinator	0:bb348c97df44	2236	tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
lypinator	0:bb348c97df44	2237	/* Configure the PLLI2S division factors */
lypinator	0:bb348c97df44	2238	/* PLLI2S_VCO Input = PLL_SOURCE/PLLM */
lypinator	0:bb348c97df44	2239	/* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
lypinator	0:bb348c97df44	2240	/* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
lypinator	0:bb348c97df44	2241	__HAL_RCC_PLLI2S_SAICLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SQ , tmpreg1);
lypinator	0:bb348c97df44	2242	/* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
lypinator	0:bb348c97df44	2243	__HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ);
lypinator	0:bb348c97df44	2244	}
lypinator	0:bb348c97df44	2245
lypinator	0:bb348c97df44	2246	/* Enable the PLLI2S */
lypinator	0:bb348c97df44	2247	__HAL_RCC_PLLI2S_ENABLE();
lypinator	0:bb348c97df44	2248	/* Get tick */
lypinator	0:bb348c97df44	2249	tickstart = HAL_GetTick();
lypinator	0:bb348c97df44	2250	/* Wait till PLLI2S is ready */
lypinator	0:bb348c97df44	2251	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
lypinator	0:bb348c97df44	2252	{
lypinator	0:bb348c97df44	2253	if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
lypinator	0:bb348c97df44	2254	{
lypinator	0:bb348c97df44	2255	/* return in case of Timeout detected */
lypinator	0:bb348c97df44	2256	return HAL_TIMEOUT;
lypinator	0:bb348c97df44	2257	}
lypinator	0:bb348c97df44	2258	}
lypinator	0:bb348c97df44	2259	}
lypinator	0:bb348c97df44	2260	/--------------------------------------------------------------------------/
lypinator	0:bb348c97df44	2261
lypinator	0:bb348c97df44	2262	/----------------------- SAI/LTDC Configuration (PLLSAI) ------------------/
lypinator	0:bb348c97df44	2263	/----------------------- Common configuration SAI/LTDC --------------------/
lypinator	0:bb348c97df44	2264	/* In Case of SAI or LTDC Clock Configuration through PLLSAI, PLLSAIN division
lypinator	0:bb348c97df44	2265	factor is common parameters for both peripherals */
lypinator	0:bb348c97df44	2266	if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == RCC_PERIPHCLK_SAI_PLLSAI) \|\|
lypinator	0:bb348c97df44	2267	(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC))
lypinator	0:bb348c97df44	2268	{
lypinator	0:bb348c97df44	2269	/* Check the PLLSAI division factors */
lypinator	0:bb348c97df44	2270	assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN));
lypinator	0:bb348c97df44	2271
lypinator	0:bb348c97df44	2272	/* Disable PLLSAI Clock */
lypinator	0:bb348c97df44	2273	__HAL_RCC_PLLSAI_DISABLE();
lypinator	0:bb348c97df44	2274	/* Get tick */
lypinator	0:bb348c97df44	2275	tickstart = HAL_GetTick();
lypinator	0:bb348c97df44	2276	/* Wait till PLLSAI is disabled */
lypinator	0:bb348c97df44	2277	while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
lypinator	0:bb348c97df44	2278	{
lypinator	0:bb348c97df44	2279	if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
lypinator	0:bb348c97df44	2280	{
lypinator	0:bb348c97df44	2281	/* return in case of Timeout detected */
lypinator	0:bb348c97df44	2282	return HAL_TIMEOUT;
lypinator	0:bb348c97df44	2283	}
lypinator	0:bb348c97df44	2284	}
lypinator	0:bb348c97df44	2285
lypinator	0:bb348c97df44	2286	/---------------------------- SAI configuration -------------------------/
lypinator	0:bb348c97df44	2287	/* In Case of SAI Clock Configuration through PLLSAI, PLLSAIQ and PLLSAI_DIVQ must
lypinator	0:bb348c97df44	2288	be added only for SAI configuration */
lypinator	0:bb348c97df44	2289	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == (RCC_PERIPHCLK_SAI_PLLSAI))
lypinator	0:bb348c97df44	2290	{
lypinator	0:bb348c97df44	2291	assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ));
lypinator	0:bb348c97df44	2292	assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ));
lypinator	0:bb348c97df44	2293
lypinator	0:bb348c97df44	2294	/* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */
lypinator	0:bb348c97df44	2295	tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos);
lypinator	0:bb348c97df44	2296	/* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
lypinator	0:bb348c97df44	2297	/* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
lypinator	0:bb348c97df44	2298	/* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
lypinator	0:bb348c97df44	2299	__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIQ, tmpreg1);
lypinator	0:bb348c97df44	2300	/* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
lypinator	0:bb348c97df44	2301	__HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ);
lypinator	0:bb348c97df44	2302	}
lypinator	0:bb348c97df44	2303
lypinator	0:bb348c97df44	2304	/---------------------------- LTDC configuration ------------------------/
lypinator	0:bb348c97df44	2305	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC))
lypinator	0:bb348c97df44	2306	{
lypinator	0:bb348c97df44	2307	assert_param(IS_RCC_PLLSAIR_VALUE(PeriphClkInit->PLLSAI.PLLSAIR));
lypinator	0:bb348c97df44	2308	assert_param(IS_RCC_PLLSAI_DIVR_VALUE(PeriphClkInit->PLLSAIDivR));
lypinator	0:bb348c97df44	2309
lypinator	0:bb348c97df44	2310	/* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */
lypinator	0:bb348c97df44	2311	tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);
lypinator	0:bb348c97df44	2312	/* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
lypinator	0:bb348c97df44	2313	/* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
lypinator	0:bb348c97df44	2314	/* LTDC_CLK(first level) = PLLSAI_VCO Output/PLLSAIR */
lypinator	0:bb348c97df44	2315	__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg1, PeriphClkInit->PLLSAI.PLLSAIR);
lypinator	0:bb348c97df44	2316	/* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */
lypinator	0:bb348c97df44	2317	__HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR);
lypinator	0:bb348c97df44	2318	}
lypinator	0:bb348c97df44	2319	/* Enable PLLSAI Clock */
lypinator	0:bb348c97df44	2320	__HAL_RCC_PLLSAI_ENABLE();
lypinator	0:bb348c97df44	2321	/* Get tick */
lypinator	0:bb348c97df44	2322	tickstart = HAL_GetTick();
lypinator	0:bb348c97df44	2323	/* Wait till PLLSAI is ready */
lypinator	0:bb348c97df44	2324	while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
lypinator	0:bb348c97df44	2325	{
lypinator	0:bb348c97df44	2326	if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
lypinator	0:bb348c97df44	2327	{
lypinator	0:bb348c97df44	2328	/* return in case of Timeout detected */
lypinator	0:bb348c97df44	2329	return HAL_TIMEOUT;
lypinator	0:bb348c97df44	2330	}
lypinator	0:bb348c97df44	2331	}
lypinator	0:bb348c97df44	2332	}
lypinator	0:bb348c97df44	2333	/--------------------------------------------------------------------------/
lypinator	0:bb348c97df44	2334
lypinator	0:bb348c97df44	2335	/---------------------------- RTC configuration ---------------------------/
lypinator	0:bb348c97df44	2336	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
lypinator	0:bb348c97df44	2337	{
lypinator	0:bb348c97df44	2338	/* Check for RTC Parameters used to output RTCCLK */
lypinator	0:bb348c97df44	2339	assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
lypinator	0:bb348c97df44	2340
lypinator	0:bb348c97df44	2341	/* Enable Power Clock*/
lypinator	0:bb348c97df44	2342	__HAL_RCC_PWR_CLK_ENABLE();
lypinator	0:bb348c97df44	2343
lypinator	0:bb348c97df44	2344	/* Enable write access to Backup domain */
lypinator	0:bb348c97df44	2345	PWR->CR \|= PWR_CR_DBP;
lypinator	0:bb348c97df44	2346
lypinator	0:bb348c97df44	2347	/* Get tick */
lypinator	0:bb348c97df44	2348	tickstart = HAL_GetTick();
lypinator	0:bb348c97df44	2349
lypinator	0:bb348c97df44	2350	while((PWR->CR & PWR_CR_DBP) == RESET)
lypinator	0:bb348c97df44	2351	{
lypinator	0:bb348c97df44	2352	if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
lypinator	0:bb348c97df44	2353	{
lypinator	0:bb348c97df44	2354	return HAL_TIMEOUT;
lypinator	0:bb348c97df44	2355	}
lypinator	0:bb348c97df44	2356	}
lypinator	0:bb348c97df44	2357	/* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
lypinator	0:bb348c97df44	2358	tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL);
lypinator	0:bb348c97df44	2359	if((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
lypinator	0:bb348c97df44	2360	{
lypinator	0:bb348c97df44	2361	/* Store the content of BDCR register before the reset of Backup Domain */
lypinator	0:bb348c97df44	2362	tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
lypinator	0:bb348c97df44	2363	/* RTC Clock selection can be changed only if the Backup Domain is reset */
lypinator	0:bb348c97df44	2364	__HAL_RCC_BACKUPRESET_FORCE();
lypinator	0:bb348c97df44	2365	__HAL_RCC_BACKUPRESET_RELEASE();
lypinator	0:bb348c97df44	2366	/* Restore the Content of BDCR register */
lypinator	0:bb348c97df44	2367	RCC->BDCR = tmpreg1;
lypinator	0:bb348c97df44	2368
lypinator	0:bb348c97df44	2369	/* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
lypinator	0:bb348c97df44	2370	if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))
lypinator	0:bb348c97df44	2371	{
lypinator	0:bb348c97df44	2372	/* Get tick */
lypinator	0:bb348c97df44	2373	tickstart = HAL_GetTick();
lypinator	0:bb348c97df44	2374
lypinator	0:bb348c97df44	2375	/* Wait till LSE is ready */
lypinator	0:bb348c97df44	2376	while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
lypinator	0:bb348c97df44	2377	{
lypinator	0:bb348c97df44	2378	if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
lypinator	0:bb348c97df44	2379	{
lypinator	0:bb348c97df44	2380	return HAL_TIMEOUT;
lypinator	0:bb348c97df44	2381	}
lypinator	0:bb348c97df44	2382	}
lypinator	0:bb348c97df44	2383	}
lypinator	0:bb348c97df44	2384	}
lypinator	0:bb348c97df44	2385	__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
lypinator	0:bb348c97df44	2386	}
lypinator	0:bb348c97df44	2387	/--------------------------------------------------------------------------/
lypinator	0:bb348c97df44	2388
lypinator	0:bb348c97df44	2389	/---------------------------- TIM configuration ---------------------------/
lypinator	0:bb348c97df44	2390	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
lypinator	0:bb348c97df44	2391	{
lypinator	0:bb348c97df44	2392	__HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
lypinator	0:bb348c97df44	2393	}
lypinator	0:bb348c97df44	2394	return HAL_OK;
lypinator	0:bb348c97df44	2395	}
lypinator	0:bb348c97df44	2396
lypinator	0:bb348c97df44	2397	/**
lypinator	0:bb348c97df44	2398	* @brief Configures the PeriphClkInit according to the internal
lypinator	0:bb348c97df44	2399	* RCC configuration registers.
lypinator	0:bb348c97df44	2400	* @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
lypinator	0:bb348c97df44	2401	* will be configured.
lypinator	0:bb348c97df44	2402	* @retval None
lypinator	0:bb348c97df44	2403	*/
lypinator	0:bb348c97df44	2404	void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
lypinator	0:bb348c97df44	2405	{
lypinator	0:bb348c97df44	2406	uint32_t tempreg;
lypinator	0:bb348c97df44	2407
lypinator	0:bb348c97df44	2408	/* Set all possible values for the extended clock type parameter------------*/
lypinator	0:bb348c97df44	2409	PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S \| RCC_PERIPHCLK_SAI_PLLSAI \| RCC_PERIPHCLK_SAI_PLLI2S \| RCC_PERIPHCLK_LTDC \| RCC_PERIPHCLK_TIM \| RCC_PERIPHCLK_RTC;
lypinator	0:bb348c97df44	2410
lypinator	0:bb348c97df44	2411	/* Get the PLLI2S Clock configuration -----------------------------------------------*/
lypinator	0:bb348c97df44	2412	PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos);
lypinator	0:bb348c97df44	2413	PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
lypinator	0:bb348c97df44	2414	PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos);
lypinator	0:bb348c97df44	2415	/* Get the PLLSAI Clock configuration -----------------------------------------------*/
lypinator	0:bb348c97df44	2416	PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> RCC_PLLSAICFGR_PLLSAIN_Pos);
lypinator	0:bb348c97df44	2417	PeriphClkInit->PLLSAI.PLLSAIR = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos);
lypinator	0:bb348c97df44	2418	PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);
lypinator	0:bb348c97df44	2419	/* Get the PLLSAI/PLLI2S division factors -----------------------------------------------*/
lypinator	0:bb348c97df44	2420	PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) >> RCC_DCKCFGR_PLLI2SDIVQ_Pos);
lypinator	0:bb348c97df44	2421	PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> RCC_DCKCFGR_PLLSAIDIVQ_Pos);
lypinator	0:bb348c97df44	2422	PeriphClkInit->PLLSAIDivR = (uint32_t)(RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVR);
lypinator	0:bb348c97df44	2423	/* Get the RTC Clock configuration -----------------------------------------------*/
lypinator	0:bb348c97df44	2424	tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
lypinator	0:bb348c97df44	2425	PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) \| (RCC->BDCR & RCC_BDCR_RTCSEL));
lypinator	0:bb348c97df44	2426
lypinator	0:bb348c97df44	2427	if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET)
lypinator	0:bb348c97df44	2428	{
lypinator	0:bb348c97df44	2429	PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;
lypinator	0:bb348c97df44	2430	}
lypinator	0:bb348c97df44	2431	else
lypinator	0:bb348c97df44	2432	{
lypinator	0:bb348c97df44	2433	PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;
lypinator	0:bb348c97df44	2434	}
lypinator	0:bb348c97df44	2435	}
lypinator	0:bb348c97df44	2436
lypinator	0:bb348c97df44	2437	/**
lypinator	0:bb348c97df44	2438	* @brief Return the peripheral clock frequency for a given peripheral(SAI..)
lypinator	0:bb348c97df44	2439	* @note Return 0 if peripheral clock identifier not managed by this API
lypinator	0:bb348c97df44	2440	* @param PeriphClk Peripheral clock identifier
lypinator	0:bb348c97df44	2441	* This parameter can be one of the following values:
lypinator	0:bb348c97df44	2442	* @arg RCC_PERIPHCLK_I2S: I2S peripheral clock
lypinator	0:bb348c97df44	2443	* @retval Frequency in KHz
lypinator	0:bb348c97df44	2444	*/
lypinator	0:bb348c97df44	2445	uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
lypinator	0:bb348c97df44	2446	{
lypinator	0:bb348c97df44	2447	/* This variable used to store the I2S clock frequency (value in Hz) */
lypinator	0:bb348c97df44	2448	uint32_t frequency = 0U;
lypinator	0:bb348c97df44	2449	/* This variable used to store the VCO Input (value in Hz) */
lypinator	0:bb348c97df44	2450	uint32_t vcoinput = 0U;
lypinator	0:bb348c97df44	2451	uint32_t srcclk = 0U;
lypinator	0:bb348c97df44	2452	/* This variable used to store the VCO Output (value in Hz) */
lypinator	0:bb348c97df44	2453	uint32_t vcooutput = 0U;
lypinator	0:bb348c97df44	2454	switch (PeriphClk)
lypinator	0:bb348c97df44	2455	{
lypinator	0:bb348c97df44	2456	case RCC_PERIPHCLK_I2S:
lypinator	0:bb348c97df44	2457	{
lypinator	0:bb348c97df44	2458	/* Get the current I2S source */
lypinator	0:bb348c97df44	2459	srcclk = __HAL_RCC_GET_I2S_SOURCE();
lypinator	0:bb348c97df44	2460	switch (srcclk)
lypinator	0:bb348c97df44	2461	{
lypinator	0:bb348c97df44	2462	/* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */
lypinator	0:bb348c97df44	2463	case RCC_I2SCLKSOURCE_EXT:
lypinator	0:bb348c97df44	2464	{
lypinator	0:bb348c97df44	2465	/* Set the I2S clock to the external clock value */
lypinator	0:bb348c97df44	2466	frequency = EXTERNAL_CLOCK_VALUE;
lypinator	0:bb348c97df44	2467	break;
lypinator	0:bb348c97df44	2468	}
lypinator	0:bb348c97df44	2469	/* Check if I2S clock selection is PLLI2S VCO output clock divided by PLLI2SR used as I2S clock */
lypinator	0:bb348c97df44	2470	case RCC_I2SCLKSOURCE_PLLI2S:
lypinator	0:bb348c97df44	2471	{
lypinator	0:bb348c97df44	2472	/* Configure the PLLI2S division factor */
lypinator	0:bb348c97df44	2473	/* PLLI2S_VCO Input = PLL_SOURCE/PLLM */
lypinator	0:bb348c97df44	2474	if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
lypinator	0:bb348c97df44	2475	{
lypinator	0:bb348c97df44	2476	/* Get the I2S source clock value */
lypinator	0:bb348c97df44	2477	vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
lypinator	0:bb348c97df44	2478	}
lypinator	0:bb348c97df44	2479	else
lypinator	0:bb348c97df44	2480	{
lypinator	0:bb348c97df44	2481	/* Get the I2S source clock value */
lypinator	0:bb348c97df44	2482	vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
lypinator	0:bb348c97df44	2483	}
lypinator	0:bb348c97df44	2484
lypinator	0:bb348c97df44	2485	/* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
lypinator	0:bb348c97df44	2486	vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U)));
lypinator	0:bb348c97df44	2487	/* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */
lypinator	0:bb348c97df44	2488	frequency = (uint32_t)(vcooutput /(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U) & (RCC_PLLI2SCFGR_PLLI2SR >> 28U)));
lypinator	0:bb348c97df44	2489	break;
lypinator	0:bb348c97df44	2490	}
lypinator	0:bb348c97df44	2491	/* Clock not enabled for I2S */
lypinator	0:bb348c97df44	2492	default:
lypinator	0:bb348c97df44	2493	{
lypinator	0:bb348c97df44	2494	frequency = 0U;
lypinator	0:bb348c97df44	2495	break;
lypinator	0:bb348c97df44	2496	}
lypinator	0:bb348c97df44	2497	}
lypinator	0:bb348c97df44	2498	break;
lypinator	0:bb348c97df44	2499	}
lypinator	0:bb348c97df44	2500	}
lypinator	0:bb348c97df44	2501	return frequency;
lypinator	0:bb348c97df44	2502	}
lypinator	0:bb348c97df44	2503	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
lypinator	0:bb348c97df44	2504
lypinator	0:bb348c97df44	2505	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx)\|\| defined(STM32F417xx) \|\|\
lypinator	0:bb348c97df44	2506	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE)
lypinator	0:bb348c97df44	2507	/**
lypinator	0:bb348c97df44	2508	* @brief Initializes the RCC extended peripherals clocks according to the specified parameters in the
lypinator	0:bb348c97df44	2509	* RCC_PeriphCLKInitTypeDef.
lypinator	0:bb348c97df44	2510	* @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
lypinator	0:bb348c97df44	2511	* contains the configuration information for the Extended Peripherals clocks(I2S and RTC clocks).
lypinator	0:bb348c97df44	2512	*
lypinator	0:bb348c97df44	2513	* @note A caution to be taken when HAL_RCCEx_PeriphCLKConfig() is used to select RTC clock selection, in this case
lypinator	0:bb348c97df44	2514	* the Reset of Backup domain will be applied in order to modify the RTC Clock source as consequence all backup
lypinator	0:bb348c97df44	2515	* domain (RTC and RCC_BDCR register expect BKPSRAM) will be reset
lypinator	0:bb348c97df44	2516	*
lypinator	0:bb348c97df44	2517	* @retval HAL status
lypinator	0:bb348c97df44	2518	*/
lypinator	0:bb348c97df44	2519	HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
lypinator	0:bb348c97df44	2520	{
lypinator	0:bb348c97df44	2521	uint32_t tickstart = 0U;
lypinator	0:bb348c97df44	2522	uint32_t tmpreg1 = 0U;
lypinator	0:bb348c97df44	2523
lypinator	0:bb348c97df44	2524	/* Check the parameters */
lypinator	0:bb348c97df44	2525	assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
lypinator	0:bb348c97df44	2526
lypinator	0:bb348c97df44	2527	/---------------------------- I2S configuration ---------------------------/
lypinator	0:bb348c97df44	2528	if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) \|\|
lypinator	0:bb348c97df44	2529	(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S))
lypinator	0:bb348c97df44	2530	{
lypinator	0:bb348c97df44	2531	/* check for Parameters */
lypinator	0:bb348c97df44	2532	assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
lypinator	0:bb348c97df44	2533	assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
lypinator	0:bb348c97df44	2534	#if defined(STM32F411xE)
lypinator	0:bb348c97df44	2535	assert_param(IS_RCC_PLLI2SM_VALUE(PeriphClkInit->PLLI2S.PLLI2SM));
lypinator	0:bb348c97df44	2536	#endif /* STM32F411xE */
lypinator	0:bb348c97df44	2537	/* Disable the PLLI2S */
lypinator	0:bb348c97df44	2538	__HAL_RCC_PLLI2S_DISABLE();
lypinator	0:bb348c97df44	2539	/* Get tick */
lypinator	0:bb348c97df44	2540	tickstart = HAL_GetTick();
lypinator	0:bb348c97df44	2541	/* Wait till PLLI2S is disabled */
lypinator	0:bb348c97df44	2542	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
lypinator	0:bb348c97df44	2543	{
lypinator	0:bb348c97df44	2544	if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
lypinator	0:bb348c97df44	2545	{
lypinator	0:bb348c97df44	2546	/* return in case of Timeout detected */
lypinator	0:bb348c97df44	2547	return HAL_TIMEOUT;
lypinator	0:bb348c97df44	2548	}
lypinator	0:bb348c97df44	2549	}
lypinator	0:bb348c97df44	2550
lypinator	0:bb348c97df44	2551	#if defined(STM32F411xE)
lypinator	0:bb348c97df44	2552	/* Configure the PLLI2S division factors */
lypinator	0:bb348c97df44	2553	/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */
lypinator	0:bb348c97df44	2554	/* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
lypinator	0:bb348c97df44	2555	__HAL_RCC_PLLI2S_I2SCLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SR);
lypinator	0:bb348c97df44	2556	#else
lypinator	0:bb348c97df44	2557	/* Configure the PLLI2S division factors */
lypinator	0:bb348c97df44	2558	/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLM) */
lypinator	0:bb348c97df44	2559	/* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
lypinator	0:bb348c97df44	2560	__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SR);
lypinator	0:bb348c97df44	2561	#endif /* STM32F411xE */
lypinator	0:bb348c97df44	2562
lypinator	0:bb348c97df44	2563	/* Enable the PLLI2S */
lypinator	0:bb348c97df44	2564	__HAL_RCC_PLLI2S_ENABLE();
lypinator	0:bb348c97df44	2565	/* Get tick */
lypinator	0:bb348c97df44	2566	tickstart = HAL_GetTick();
lypinator	0:bb348c97df44	2567	/* Wait till PLLI2S is ready */
lypinator	0:bb348c97df44	2568	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
lypinator	0:bb348c97df44	2569	{
lypinator	0:bb348c97df44	2570	if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
lypinator	0:bb348c97df44	2571	{
lypinator	0:bb348c97df44	2572	/* return in case of Timeout detected */
lypinator	0:bb348c97df44	2573	return HAL_TIMEOUT;
lypinator	0:bb348c97df44	2574	}
lypinator	0:bb348c97df44	2575	}
lypinator	0:bb348c97df44	2576	}
lypinator	0:bb348c97df44	2577
lypinator	0:bb348c97df44	2578	/---------------------------- RTC configuration ---------------------------/
lypinator	0:bb348c97df44	2579	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
lypinator	0:bb348c97df44	2580	{
lypinator	0:bb348c97df44	2581	/* Check for RTC Parameters used to output RTCCLK */
lypinator	0:bb348c97df44	2582	assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
lypinator	0:bb348c97df44	2583
lypinator	0:bb348c97df44	2584	/* Enable Power Clock*/
lypinator	0:bb348c97df44	2585	__HAL_RCC_PWR_CLK_ENABLE();
lypinator	0:bb348c97df44	2586
lypinator	0:bb348c97df44	2587	/* Enable write access to Backup domain */
lypinator	0:bb348c97df44	2588	PWR->CR \|= PWR_CR_DBP;
lypinator	0:bb348c97df44	2589
lypinator	0:bb348c97df44	2590	/* Get tick */
lypinator	0:bb348c97df44	2591	tickstart = HAL_GetTick();
lypinator	0:bb348c97df44	2592
lypinator	0:bb348c97df44	2593	while((PWR->CR & PWR_CR_DBP) == RESET)
lypinator	0:bb348c97df44	2594	{
lypinator	0:bb348c97df44	2595	if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
lypinator	0:bb348c97df44	2596	{
lypinator	0:bb348c97df44	2597	return HAL_TIMEOUT;
lypinator	0:bb348c97df44	2598	}
lypinator	0:bb348c97df44	2599	}
lypinator	0:bb348c97df44	2600	/* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
lypinator	0:bb348c97df44	2601	tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL);
lypinator	0:bb348c97df44	2602	if((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
lypinator	0:bb348c97df44	2603	{
lypinator	0:bb348c97df44	2604	/* Store the content of BDCR register before the reset of Backup Domain */
lypinator	0:bb348c97df44	2605	tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
lypinator	0:bb348c97df44	2606	/* RTC Clock selection can be changed only if the Backup Domain is reset */
lypinator	0:bb348c97df44	2607	__HAL_RCC_BACKUPRESET_FORCE();
lypinator	0:bb348c97df44	2608	__HAL_RCC_BACKUPRESET_RELEASE();
lypinator	0:bb348c97df44	2609	/* Restore the Content of BDCR register */
lypinator	0:bb348c97df44	2610	RCC->BDCR = tmpreg1;
lypinator	0:bb348c97df44	2611
lypinator	0:bb348c97df44	2612	/* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
lypinator	0:bb348c97df44	2613	if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))
lypinator	0:bb348c97df44	2614	{
lypinator	0:bb348c97df44	2615	/* Get tick */
lypinator	0:bb348c97df44	2616	tickstart = HAL_GetTick();
lypinator	0:bb348c97df44	2617
lypinator	0:bb348c97df44	2618	/* Wait till LSE is ready */
lypinator	0:bb348c97df44	2619	while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
lypinator	0:bb348c97df44	2620	{
lypinator	0:bb348c97df44	2621	if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
lypinator	0:bb348c97df44	2622	{
lypinator	0:bb348c97df44	2623	return HAL_TIMEOUT;
lypinator	0:bb348c97df44	2624	}
lypinator	0:bb348c97df44	2625	}
lypinator	0:bb348c97df44	2626	}
lypinator	0:bb348c97df44	2627	}
lypinator	0:bb348c97df44	2628	__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
lypinator	0:bb348c97df44	2629	}
lypinator	0:bb348c97df44	2630	#if defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE)
lypinator	0:bb348c97df44	2631	/---------------------------- TIM configuration ---------------------------/
lypinator	0:bb348c97df44	2632	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
lypinator	0:bb348c97df44	2633	{
lypinator	0:bb348c97df44	2634	__HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
lypinator	0:bb348c97df44	2635	}
lypinator	0:bb348c97df44	2636	#endif /* STM32F401xC \|\| STM32F401xE \|\| STM32F411xE */
lypinator	0:bb348c97df44	2637	return HAL_OK;
lypinator	0:bb348c97df44	2638	}
lypinator	0:bb348c97df44	2639
lypinator	0:bb348c97df44	2640	/**
lypinator	0:bb348c97df44	2641	* @brief Configures the RCC_OscInitStruct according to the internal
lypinator	0:bb348c97df44	2642	* RCC configuration registers.
lypinator	0:bb348c97df44	2643	* @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
lypinator	0:bb348c97df44	2644	* will be configured.
lypinator	0:bb348c97df44	2645	* @retval None
lypinator	0:bb348c97df44	2646	*/
lypinator	0:bb348c97df44	2647	void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
lypinator	0:bb348c97df44	2648	{
lypinator	0:bb348c97df44	2649	uint32_t tempreg;
lypinator	0:bb348c97df44	2650
lypinator	0:bb348c97df44	2651	/* Set all possible values for the extended clock type parameter------------*/
lypinator	0:bb348c97df44	2652	PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S \| RCC_PERIPHCLK_RTC;
lypinator	0:bb348c97df44	2653
lypinator	0:bb348c97df44	2654	/* Get the PLLI2S Clock configuration --------------------------------------*/
lypinator	0:bb348c97df44	2655	PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos);
lypinator	0:bb348c97df44	2656	PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
lypinator	0:bb348c97df44	2657	#if defined(STM32F411xE)
lypinator	0:bb348c97df44	2658	PeriphClkInit->PLLI2S.PLLI2SM = (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM);
lypinator	0:bb348c97df44	2659	#endif /* STM32F411xE */
lypinator	0:bb348c97df44	2660	/* Get the RTC Clock configuration -----------------------------------------*/
lypinator	0:bb348c97df44	2661	tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
lypinator	0:bb348c97df44	2662	PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) \| (RCC->BDCR & RCC_BDCR_RTCSEL));
lypinator	0:bb348c97df44	2663
lypinator	0:bb348c97df44	2664	#if defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE)
lypinator	0:bb348c97df44	2665	/* Get the TIM Prescaler configuration -------------------------------------*/
lypinator	0:bb348c97df44	2666	if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET)
lypinator	0:bb348c97df44	2667	{
lypinator	0:bb348c97df44	2668	PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;
lypinator	0:bb348c97df44	2669	}
lypinator	0:bb348c97df44	2670	else
lypinator	0:bb348c97df44	2671	{
lypinator	0:bb348c97df44	2672	PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;
lypinator	0:bb348c97df44	2673	}
lypinator	0:bb348c97df44	2674	#endif /* STM32F401xC \|\| STM32F401xE \|\| STM32F411xE */
lypinator	0:bb348c97df44	2675	}
lypinator	0:bb348c97df44	2676
lypinator	0:bb348c97df44	2677	/**
lypinator	0:bb348c97df44	2678	* @brief Return the peripheral clock frequency for a given peripheral(SAI..)
lypinator	0:bb348c97df44	2679	* @note Return 0 if peripheral clock identifier not managed by this API
lypinator	0:bb348c97df44	2680	* @param PeriphClk Peripheral clock identifier
lypinator	0:bb348c97df44	2681	* This parameter can be one of the following values:
lypinator	0:bb348c97df44	2682	* @arg RCC_PERIPHCLK_I2S: I2S peripheral clock
lypinator	0:bb348c97df44	2683	* @retval Frequency in KHz
lypinator	0:bb348c97df44	2684	*/
lypinator	0:bb348c97df44	2685	uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
lypinator	0:bb348c97df44	2686	{
lypinator	0:bb348c97df44	2687	/* This variable used to store the I2S clock frequency (value in Hz) */
lypinator	0:bb348c97df44	2688	uint32_t frequency = 0U;
lypinator	0:bb348c97df44	2689	/* This variable used to store the VCO Input (value in Hz) */
lypinator	0:bb348c97df44	2690	uint32_t vcoinput = 0U;
lypinator	0:bb348c97df44	2691	uint32_t srcclk = 0U;
lypinator	0:bb348c97df44	2692	/* This variable used to store the VCO Output (value in Hz) */
lypinator	0:bb348c97df44	2693	uint32_t vcooutput = 0U;
lypinator	0:bb348c97df44	2694	switch (PeriphClk)
lypinator	0:bb348c97df44	2695	{
lypinator	0:bb348c97df44	2696	case RCC_PERIPHCLK_I2S:
lypinator	0:bb348c97df44	2697	{
lypinator	0:bb348c97df44	2698	/* Get the current I2S source */
lypinator	0:bb348c97df44	2699	srcclk = __HAL_RCC_GET_I2S_SOURCE();
lypinator	0:bb348c97df44	2700	switch (srcclk)
lypinator	0:bb348c97df44	2701	{
lypinator	0:bb348c97df44	2702	/* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */
lypinator	0:bb348c97df44	2703	case RCC_I2SCLKSOURCE_EXT:
lypinator	0:bb348c97df44	2704	{
lypinator	0:bb348c97df44	2705	/* Set the I2S clock to the external clock value */
lypinator	0:bb348c97df44	2706	frequency = EXTERNAL_CLOCK_VALUE;
lypinator	0:bb348c97df44	2707	break;
lypinator	0:bb348c97df44	2708	}
lypinator	0:bb348c97df44	2709	/* Check if I2S clock selection is PLLI2S VCO output clock divided by PLLI2SR used as I2S clock */
lypinator	0:bb348c97df44	2710	case RCC_I2SCLKSOURCE_PLLI2S:
lypinator	0:bb348c97df44	2711	{
lypinator	0:bb348c97df44	2712	#if defined(STM32F411xE)
lypinator	0:bb348c97df44	2713	/* Configure the PLLI2S division factor */
lypinator	0:bb348c97df44	2714	/* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */
lypinator	0:bb348c97df44	2715	if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
lypinator	0:bb348c97df44	2716	{
lypinator	0:bb348c97df44	2717	/* Get the I2S source clock value */
lypinator	0:bb348c97df44	2718	vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
lypinator	0:bb348c97df44	2719	}
lypinator	0:bb348c97df44	2720	else
lypinator	0:bb348c97df44	2721	{
lypinator	0:bb348c97df44	2722	/* Get the I2S source clock value */
lypinator	0:bb348c97df44	2723	vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
lypinator	0:bb348c97df44	2724	}
lypinator	0:bb348c97df44	2725	#else
lypinator	0:bb348c97df44	2726	/* Configure the PLLI2S division factor */
lypinator	0:bb348c97df44	2727	/* PLLI2S_VCO Input = PLL_SOURCE/PLLM */
lypinator	0:bb348c97df44	2728	if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
lypinator	0:bb348c97df44	2729	{
lypinator	0:bb348c97df44	2730	/* Get the I2S source clock value */
lypinator	0:bb348c97df44	2731	vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
lypinator	0:bb348c97df44	2732	}
lypinator	0:bb348c97df44	2733	else
lypinator	0:bb348c97df44	2734	{
lypinator	0:bb348c97df44	2735	/* Get the I2S source clock value */
lypinator	0:bb348c97df44	2736	vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
lypinator	0:bb348c97df44	2737	}
lypinator	0:bb348c97df44	2738	#endif /* STM32F411xE */
lypinator	0:bb348c97df44	2739	/* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
lypinator	0:bb348c97df44	2740	vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U)));
lypinator	0:bb348c97df44	2741	/* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */
lypinator	0:bb348c97df44	2742	frequency = (uint32_t)(vcooutput /(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U) & (RCC_PLLI2SCFGR_PLLI2SR >> 28U)));
lypinator	0:bb348c97df44	2743	break;
lypinator	0:bb348c97df44	2744	}
lypinator	0:bb348c97df44	2745	/* Clock not enabled for I2S*/
lypinator	0:bb348c97df44	2746	default:
lypinator	0:bb348c97df44	2747	{
lypinator	0:bb348c97df44	2748	frequency = 0U;
lypinator	0:bb348c97df44	2749	break;
lypinator	0:bb348c97df44	2750	}
lypinator	0:bb348c97df44	2751	}
lypinator	0:bb348c97df44	2752	break;
lypinator	0:bb348c97df44	2753	}
lypinator	0:bb348c97df44	2754	}
lypinator	0:bb348c97df44	2755	return frequency;
lypinator	0:bb348c97df44	2756	}
lypinator	0:bb348c97df44	2757	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F401xC \|\| STM32F401xE \|\| STM32F411xE */
lypinator	0:bb348c97df44	2758
lypinator	0:bb348c97df44	2759	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\|\
lypinator	0:bb348c97df44	2760	defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
lypinator	0:bb348c97df44	2761	/**
lypinator	0:bb348c97df44	2762	* @brief Select LSE mode
lypinator	0:bb348c97df44	2763	*
lypinator	0:bb348c97df44	2764	* @note This mode is only available for STM32F410xx/STM32F411xx/STM32F446xx/STM32F469xx/STM32F479xx/STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx devices.
lypinator	0:bb348c97df44	2765	*
lypinator	0:bb348c97df44	2766	* @param Mode specifies the LSE mode.
lypinator	0:bb348c97df44	2767	* This parameter can be one of the following values:
lypinator	0:bb348c97df44	2768	* @arg RCC_LSE_LOWPOWER_MODE: LSE oscillator in low power mode selection
lypinator	0:bb348c97df44	2769	* @arg RCC_LSE_HIGHDRIVE_MODE: LSE oscillator in High Drive mode selection
lypinator	0:bb348c97df44	2770	* @retval None
lypinator	0:bb348c97df44	2771	*/
lypinator	0:bb348c97df44	2772	void HAL_RCCEx_SelectLSEMode(uint8_t Mode)
lypinator	0:bb348c97df44	2773	{
lypinator	0:bb348c97df44	2774	/* Check the parameters */
lypinator	0:bb348c97df44	2775	assert_param(IS_RCC_LSE_MODE(Mode));
lypinator	0:bb348c97df44	2776	if(Mode == RCC_LSE_HIGHDRIVE_MODE)
lypinator	0:bb348c97df44	2777	{
lypinator	0:bb348c97df44	2778	SET_BIT(RCC->BDCR, RCC_BDCR_LSEMOD);
lypinator	0:bb348c97df44	2779	}
lypinator	0:bb348c97df44	2780	else
lypinator	0:bb348c97df44	2781	{
lypinator	0:bb348c97df44	2782	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEMOD);
lypinator	0:bb348c97df44	2783	}
lypinator	0:bb348c97df44	2784	}
lypinator	0:bb348c97df44	2785
lypinator	0:bb348c97df44	2786	#endif /* STM32F410xx \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx \|\| STM32F413xx \|\| STM32F423xx */
lypinator	0:bb348c97df44	2787
lypinator	0:bb348c97df44	2788	/** @defgroup RCCEx_Exported_Functions_Group2 Extended Clock management functions
lypinator	0:bb348c97df44	2789	* @brief Extended Clock management functions
lypinator	0:bb348c97df44	2790	*
lypinator	0:bb348c97df44	2791	@verbatim
lypinator	0:bb348c97df44	2792	===============================================================================
lypinator	0:bb348c97df44	2793	##### Extended clock management functions #####
lypinator	0:bb348c97df44	2794	===============================================================================
lypinator	0:bb348c97df44	2795	[..]
lypinator	0:bb348c97df44	2796	This subsection provides a set of functions allowing to control the
lypinator	0:bb348c97df44	2797	activation or deactivation of PLLI2S, PLLSAI.
lypinator	0:bb348c97df44	2798	@endverbatim
lypinator	0:bb348c97df44	2799	* @{
lypinator	0:bb348c97df44	2800	*/
lypinator	0:bb348c97df44	2801
lypinator	0:bb348c97df44	2802	#if defined(RCC_PLLI2S_SUPPORT)
lypinator	0:bb348c97df44	2803	/**
lypinator	0:bb348c97df44	2804	* @brief Enable PLLI2S.
lypinator	0:bb348c97df44	2805	* @param PLLI2SInit pointer to an RCC_PLLI2SInitTypeDef structure that
lypinator	0:bb348c97df44	2806	* contains the configuration information for the PLLI2S
lypinator	0:bb348c97df44	2807	* @retval HAL status
lypinator	0:bb348c97df44	2808	*/
lypinator	0:bb348c97df44	2809	HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit)
lypinator	0:bb348c97df44	2810	{
lypinator	0:bb348c97df44	2811	uint32_t tickstart;
lypinator	0:bb348c97df44	2812
lypinator	0:bb348c97df44	2813	/* Check for parameters */
lypinator	0:bb348c97df44	2814	assert_param(IS_RCC_PLLI2SN_VALUE(PLLI2SInit->PLLI2SN));
lypinator	0:bb348c97df44	2815	assert_param(IS_RCC_PLLI2SR_VALUE(PLLI2SInit->PLLI2SR));
lypinator	0:bb348c97df44	2816	#if defined(RCC_PLLI2SCFGR_PLLI2SM)
lypinator	0:bb348c97df44	2817	assert_param(IS_RCC_PLLI2SM_VALUE(PLLI2SInit->PLLI2SM));
lypinator	0:bb348c97df44	2818	#endif /* RCC_PLLI2SCFGR_PLLI2SM */
lypinator	0:bb348c97df44	2819	#if defined(RCC_PLLI2SCFGR_PLLI2SP)
lypinator	0:bb348c97df44	2820	assert_param(IS_RCC_PLLI2SP_VALUE(PLLI2SInit->PLLI2SP));
lypinator	0:bb348c97df44	2821	#endif /* RCC_PLLI2SCFGR_PLLI2SP */
lypinator	0:bb348c97df44	2822	#if defined(RCC_PLLI2SCFGR_PLLI2SQ)
lypinator	0:bb348c97df44	2823	assert_param(IS_RCC_PLLI2SQ_VALUE(PLLI2SInit->PLLI2SQ));
lypinator	0:bb348c97df44	2824	#endif /* RCC_PLLI2SCFGR_PLLI2SQ */
lypinator	0:bb348c97df44	2825
lypinator	0:bb348c97df44	2826	/* Disable the PLLI2S */
lypinator	0:bb348c97df44	2827	__HAL_RCC_PLLI2S_DISABLE();
lypinator	0:bb348c97df44	2828
lypinator	0:bb348c97df44	2829	/* Wait till PLLI2S is disabled */
lypinator	0:bb348c97df44	2830	tickstart = HAL_GetTick();
lypinator	0:bb348c97df44	2831	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
lypinator	0:bb348c97df44	2832	{
lypinator	0:bb348c97df44	2833	if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
lypinator	0:bb348c97df44	2834	{
lypinator	0:bb348c97df44	2835	/* return in case of Timeout detected */
lypinator	0:bb348c97df44	2836	return HAL_TIMEOUT;
lypinator	0:bb348c97df44	2837	}
lypinator	0:bb348c97df44	2838	}
lypinator	0:bb348c97df44	2839
lypinator	0:bb348c97df44	2840	/* Configure the PLLI2S division factors */
lypinator	0:bb348c97df44	2841	#if defined(STM32F446xx)
lypinator	0:bb348c97df44	2842	/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */
lypinator	0:bb348c97df44	2843	/* I2SPCLK = PLLI2S_VCO / PLLI2SP */
lypinator	0:bb348c97df44	2844	/* I2SQCLK = PLLI2S_VCO / PLLI2SQ */
lypinator	0:bb348c97df44	2845	/* I2SRCLK = PLLI2S_VCO / PLLI2SR */
lypinator	0:bb348c97df44	2846	__HAL_RCC_PLLI2S_CONFIG(PLLI2SInit->PLLI2SM, PLLI2SInit->PLLI2SN, \
lypinator	0:bb348c97df44	2847	PLLI2SInit->PLLI2SP, PLLI2SInit->PLLI2SQ, PLLI2SInit->PLLI2SR);
lypinator	0:bb348c97df44	2848	#elif defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx) \|\|\
lypinator	0:bb348c97df44	2849	defined(STM32F413xx) \|\| defined(STM32F423xx)
lypinator	0:bb348c97df44	2850	/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM)*/
lypinator	0:bb348c97df44	2851	/* I2SQCLK = PLLI2S_VCO / PLLI2SQ */
lypinator	0:bb348c97df44	2852	/* I2SRCLK = PLLI2S_VCO / PLLI2SR */
lypinator	0:bb348c97df44	2853	__HAL_RCC_PLLI2S_CONFIG(PLLI2SInit->PLLI2SM, PLLI2SInit->PLLI2SN, \
lypinator	0:bb348c97df44	2854	PLLI2SInit->PLLI2SQ, PLLI2SInit->PLLI2SR);
lypinator	0:bb348c97df44	2855	#elif defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\|\
lypinator	0:bb348c97df44	2856	defined(STM32F469xx) \|\| defined(STM32F479xx)
lypinator	0:bb348c97df44	2857	/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * PLLI2SN */
lypinator	0:bb348c97df44	2858	/* I2SQCLK = PLLI2S_VCO / PLLI2SQ */
lypinator	0:bb348c97df44	2859	/* I2SRCLK = PLLI2S_VCO / PLLI2SR */
lypinator	0:bb348c97df44	2860	__HAL_RCC_PLLI2S_SAICLK_CONFIG(PLLI2SInit->PLLI2SN, PLLI2SInit->PLLI2SQ, PLLI2SInit->PLLI2SR);
lypinator	0:bb348c97df44	2861	#elif defined(STM32F411xE)
lypinator	0:bb348c97df44	2862	/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */
lypinator	0:bb348c97df44	2863	/* I2SRCLK = PLLI2S_VCO / PLLI2SR */
lypinator	0:bb348c97df44	2864	__HAL_RCC_PLLI2S_I2SCLK_CONFIG(PLLI2SInit->PLLI2SM, PLLI2SInit->PLLI2SN, PLLI2SInit->PLLI2SR);
lypinator	0:bb348c97df44	2865	#else
lypinator	0:bb348c97df44	2866	/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x PLLI2SN */
lypinator	0:bb348c97df44	2867	/* I2SRCLK = PLLI2S_VCO / PLLI2SR */
lypinator	0:bb348c97df44	2868	__HAL_RCC_PLLI2S_CONFIG(PLLI2SInit->PLLI2SN, PLLI2SInit->PLLI2SR);
lypinator	0:bb348c97df44	2869	#endif /* STM32F446xx */
lypinator	0:bb348c97df44	2870
lypinator	0:bb348c97df44	2871	/* Enable the PLLI2S */
lypinator	0:bb348c97df44	2872	__HAL_RCC_PLLI2S_ENABLE();
lypinator	0:bb348c97df44	2873
lypinator	0:bb348c97df44	2874	/* Wait till PLLI2S is ready */
lypinator	0:bb348c97df44	2875	tickstart = HAL_GetTick();
lypinator	0:bb348c97df44	2876	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
lypinator	0:bb348c97df44	2877	{
lypinator	0:bb348c97df44	2878	if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
lypinator	0:bb348c97df44	2879	{
lypinator	0:bb348c97df44	2880	/* return in case of Timeout detected */
lypinator	0:bb348c97df44	2881	return HAL_TIMEOUT;
lypinator	0:bb348c97df44	2882	}
lypinator	0:bb348c97df44	2883	}
lypinator	0:bb348c97df44	2884
lypinator	0:bb348c97df44	2885	return HAL_OK;
lypinator	0:bb348c97df44	2886	}
lypinator	0:bb348c97df44	2887
lypinator	0:bb348c97df44	2888	/**
lypinator	0:bb348c97df44	2889	* @brief Disable PLLI2S.
lypinator	0:bb348c97df44	2890	* @retval HAL status
lypinator	0:bb348c97df44	2891	*/
lypinator	0:bb348c97df44	2892	HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void)
lypinator	0:bb348c97df44	2893	{
lypinator	0:bb348c97df44	2894	uint32_t tickstart;
lypinator	0:bb348c97df44	2895
lypinator	0:bb348c97df44	2896	/* Disable the PLLI2S */
lypinator	0:bb348c97df44	2897	__HAL_RCC_PLLI2S_DISABLE();
lypinator	0:bb348c97df44	2898
lypinator	0:bb348c97df44	2899	/* Wait till PLLI2S is disabled */
lypinator	0:bb348c97df44	2900	tickstart = HAL_GetTick();
lypinator	0:bb348c97df44	2901	while(READ_BIT(RCC->CR, RCC_CR_PLLI2SRDY) != RESET)
lypinator	0:bb348c97df44	2902	{
lypinator	0:bb348c97df44	2903	if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
lypinator	0:bb348c97df44	2904	{
lypinator	0:bb348c97df44	2905	/* return in case of Timeout detected */
lypinator	0:bb348c97df44	2906	return HAL_TIMEOUT;
lypinator	0:bb348c97df44	2907	}
lypinator	0:bb348c97df44	2908	}
lypinator	0:bb348c97df44	2909
lypinator	0:bb348c97df44	2910	return HAL_OK;
lypinator	0:bb348c97df44	2911	}
lypinator	0:bb348c97df44	2912
lypinator	0:bb348c97df44	2913	#endif /* RCC_PLLI2S_SUPPORT */
lypinator	0:bb348c97df44	2914
lypinator	0:bb348c97df44	2915	#if defined(RCC_PLLSAI_SUPPORT)
lypinator	0:bb348c97df44	2916	/**
lypinator	0:bb348c97df44	2917	* @brief Enable PLLSAI.
lypinator	0:bb348c97df44	2918	* @param PLLSAIInit pointer to an RCC_PLLSAIInitTypeDef structure that
lypinator	0:bb348c97df44	2919	* contains the configuration information for the PLLSAI
lypinator	0:bb348c97df44	2920	* @retval HAL status
lypinator	0:bb348c97df44	2921	*/
lypinator	0:bb348c97df44	2922	HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI(RCC_PLLSAIInitTypeDef *PLLSAIInit)
lypinator	0:bb348c97df44	2923	{
lypinator	0:bb348c97df44	2924	uint32_t tickstart;
lypinator	0:bb348c97df44	2925
lypinator	0:bb348c97df44	2926	/* Check for parameters */
lypinator	0:bb348c97df44	2927	assert_param(IS_RCC_PLLSAIN_VALUE(PLLSAIInit->PLLSAIN));
lypinator	0:bb348c97df44	2928	assert_param(IS_RCC_PLLSAIQ_VALUE(PLLSAIInit->PLLSAIQ));
lypinator	0:bb348c97df44	2929	#if defined(RCC_PLLSAICFGR_PLLSAIM)
lypinator	0:bb348c97df44	2930	assert_param(IS_RCC_PLLSAIM_VALUE(PLLSAIInit->PLLSAIM));
lypinator	0:bb348c97df44	2931	#endif /* RCC_PLLSAICFGR_PLLSAIM */
lypinator	0:bb348c97df44	2932	#if defined(RCC_PLLSAICFGR_PLLSAIP)
lypinator	0:bb348c97df44	2933	assert_param(IS_RCC_PLLSAIP_VALUE(PLLSAIInit->PLLSAIP));
lypinator	0:bb348c97df44	2934	#endif /* RCC_PLLSAICFGR_PLLSAIP */
lypinator	0:bb348c97df44	2935	#if defined(RCC_PLLSAICFGR_PLLSAIR)
lypinator	0:bb348c97df44	2936	assert_param(IS_RCC_PLLSAIR_VALUE(PLLSAIInit->PLLSAIR));
lypinator	0:bb348c97df44	2937	#endif /* RCC_PLLSAICFGR_PLLSAIR */
lypinator	0:bb348c97df44	2938
lypinator	0:bb348c97df44	2939	/* Disable the PLLSAI */
lypinator	0:bb348c97df44	2940	__HAL_RCC_PLLSAI_DISABLE();
lypinator	0:bb348c97df44	2941
lypinator	0:bb348c97df44	2942	/* Wait till PLLSAI is disabled */
lypinator	0:bb348c97df44	2943	tickstart = HAL_GetTick();
lypinator	0:bb348c97df44	2944	while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
lypinator	0:bb348c97df44	2945	{
lypinator	0:bb348c97df44	2946	if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
lypinator	0:bb348c97df44	2947	{
lypinator	0:bb348c97df44	2948	/* return in case of Timeout detected */
lypinator	0:bb348c97df44	2949	return HAL_TIMEOUT;
lypinator	0:bb348c97df44	2950	}
lypinator	0:bb348c97df44	2951	}
lypinator	0:bb348c97df44	2952
lypinator	0:bb348c97df44	2953	/* Configure the PLLSAI division factors */
lypinator	0:bb348c97df44	2954	#if defined(STM32F446xx)
lypinator	0:bb348c97df44	2955	/* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) * (PLLSAIN/PLLSAIM) */
lypinator	0:bb348c97df44	2956	/* SAIPCLK = PLLSAI_VCO / PLLSAIP */
lypinator	0:bb348c97df44	2957	/* SAIQCLK = PLLSAI_VCO / PLLSAIQ */
lypinator	0:bb348c97df44	2958	/* SAIRCLK = PLLSAI_VCO / PLLSAIR */
lypinator	0:bb348c97df44	2959	__HAL_RCC_PLLSAI_CONFIG(PLLSAIInit->PLLSAIM, PLLSAIInit->PLLSAIN, \
lypinator	0:bb348c97df44	2960	PLLSAIInit->PLLSAIP, PLLSAIInit->PLLSAIQ, 0U);
lypinator	0:bb348c97df44	2961	#elif defined(STM32F469xx) \|\| defined(STM32F479xx)
lypinator	0:bb348c97df44	2962	/* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) * PLLSAIN */
lypinator	0:bb348c97df44	2963	/* SAIPCLK = PLLSAI_VCO / PLLSAIP */
lypinator	0:bb348c97df44	2964	/* SAIQCLK = PLLSAI_VCO / PLLSAIQ */
lypinator	0:bb348c97df44	2965	/* SAIRCLK = PLLSAI_VCO / PLLSAIR */
lypinator	0:bb348c97df44	2966	__HAL_RCC_PLLSAI_CONFIG(PLLSAIInit->PLLSAIN, PLLSAIInit->PLLSAIP, \
lypinator	0:bb348c97df44	2967	PLLSAIInit->PLLSAIQ, PLLSAIInit->PLLSAIR);
lypinator	0:bb348c97df44	2968	#else
lypinator	0:bb348c97df44	2969	/* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) x PLLSAIN */
lypinator	0:bb348c97df44	2970	/* SAIQCLK = PLLSAI_VCO / PLLSAIQ */
lypinator	0:bb348c97df44	2971	/* SAIRCLK = PLLSAI_VCO / PLLSAIR */
lypinator	0:bb348c97df44	2972	__HAL_RCC_PLLSAI_CONFIG(PLLSAIInit->PLLSAIN, PLLSAIInit->PLLSAIQ, PLLSAIInit->PLLSAIR);
lypinator	0:bb348c97df44	2973	#endif /* STM32F446xx */
lypinator	0:bb348c97df44	2974
lypinator	0:bb348c97df44	2975	/* Enable the PLLSAI */
lypinator	0:bb348c97df44	2976	__HAL_RCC_PLLSAI_ENABLE();
lypinator	0:bb348c97df44	2977
lypinator	0:bb348c97df44	2978	/* Wait till PLLSAI is ready */
lypinator	0:bb348c97df44	2979	tickstart = HAL_GetTick();
lypinator	0:bb348c97df44	2980	while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
lypinator	0:bb348c97df44	2981	{
lypinator	0:bb348c97df44	2982	if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
lypinator	0:bb348c97df44	2983	{
lypinator	0:bb348c97df44	2984	/* return in case of Timeout detected */
lypinator	0:bb348c97df44	2985	return HAL_TIMEOUT;
lypinator	0:bb348c97df44	2986	}
lypinator	0:bb348c97df44	2987	}
lypinator	0:bb348c97df44	2988
lypinator	0:bb348c97df44	2989	return HAL_OK;
lypinator	0:bb348c97df44	2990	}
lypinator	0:bb348c97df44	2991
lypinator	0:bb348c97df44	2992	/**
lypinator	0:bb348c97df44	2993	* @brief Disable PLLSAI.
lypinator	0:bb348c97df44	2994	* @retval HAL status
lypinator	0:bb348c97df44	2995	*/
lypinator	0:bb348c97df44	2996	HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI(void)
lypinator	0:bb348c97df44	2997	{
lypinator	0:bb348c97df44	2998	uint32_t tickstart;
lypinator	0:bb348c97df44	2999
lypinator	0:bb348c97df44	3000	/* Disable the PLLSAI */
lypinator	0:bb348c97df44	3001	__HAL_RCC_PLLSAI_DISABLE();
lypinator	0:bb348c97df44	3002
lypinator	0:bb348c97df44	3003	/* Wait till PLLSAI is disabled */
lypinator	0:bb348c97df44	3004	tickstart = HAL_GetTick();
lypinator	0:bb348c97df44	3005	while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
lypinator	0:bb348c97df44	3006	{
lypinator	0:bb348c97df44	3007	if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)
lypinator	0:bb348c97df44	3008	{
lypinator	0:bb348c97df44	3009	/* return in case of Timeout detected */
lypinator	0:bb348c97df44	3010	return HAL_TIMEOUT;
lypinator	0:bb348c97df44	3011	}
lypinator	0:bb348c97df44	3012	}
lypinator	0:bb348c97df44	3013
lypinator	0:bb348c97df44	3014	return HAL_OK;
lypinator	0:bb348c97df44	3015	}
lypinator	0:bb348c97df44	3016
lypinator	0:bb348c97df44	3017	#endif /* RCC_PLLSAI_SUPPORT */
lypinator	0:bb348c97df44	3018
lypinator	0:bb348c97df44	3019	/**
lypinator	0:bb348c97df44	3020	* @}
lypinator	0:bb348c97df44	3021	*/
lypinator	0:bb348c97df44	3022
lypinator	0:bb348c97df44	3023	#if defined(STM32F446xx)
lypinator	0:bb348c97df44	3024	/**
lypinator	0:bb348c97df44	3025	* @brief Returns the SYSCLK frequency
lypinator	0:bb348c97df44	3026	*
lypinator	0:bb348c97df44	3027	* @note This function implementation is valid only for STM32F446xx devices.
lypinator	0:bb348c97df44	3028	* @note This function add the PLL/PLLR System clock source
lypinator	0:bb348c97df44	3029	*
lypinator	0:bb348c97df44	3030	* @note The system frequency computed by this function is not the real
lypinator	0:bb348c97df44	3031	* frequency in the chip. It is calculated based on the predefined
lypinator	0:bb348c97df44	3032	* constant and the selected clock source:
lypinator	0:bb348c97df44	3033	* @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
lypinator	0:bb348c97df44	3034	* @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
lypinator	0:bb348c97df44	3035	* @note If SYSCLK source is PLL or PLLR, function returns values based on HSE_VALUE(**)
lypinator	0:bb348c97df44	3036	* or HSI_VALUE(*) multiplied/divided by the PLL factors.
lypinator	0:bb348c97df44	3037	* @note (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
lypinator	0:bb348c97df44	3038	* 16 MHz) but the real value may vary depending on the variations
lypinator	0:bb348c97df44	3039	* in voltage and temperature.
lypinator	0:bb348c97df44	3040	* @note (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
lypinator	0:bb348c97df44	3041	* 25 MHz), user has to ensure that HSE_VALUE is same as the real
lypinator	0:bb348c97df44	3042	* frequency of the crystal used. Otherwise, this function may
lypinator	0:bb348c97df44	3043	* have wrong result.
lypinator	0:bb348c97df44	3044	*
lypinator	0:bb348c97df44	3045	* @note The result of this function could be not correct when using fractional
lypinator	0:bb348c97df44	3046	* value for HSE crystal.
lypinator	0:bb348c97df44	3047	*
lypinator	0:bb348c97df44	3048	* @note This function can be used by the user application to compute the
lypinator	0:bb348c97df44	3049	* baudrate for the communication peripherals or configure other parameters.
lypinator	0:bb348c97df44	3050	*
lypinator	0:bb348c97df44	3051	* @note Each time SYSCLK changes, this function must be called to update the
lypinator	0:bb348c97df44	3052	* right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
lypinator	0:bb348c97df44	3053	*
lypinator	0:bb348c97df44	3054	*
lypinator	0:bb348c97df44	3055	* @retval SYSCLK frequency
lypinator	0:bb348c97df44	3056	*/
lypinator	0:bb348c97df44	3057	uint32_t HAL_RCC_GetSysClockFreq(void)
lypinator	0:bb348c97df44	3058	{
lypinator	0:bb348c97df44	3059	uint32_t pllm = 0U;
lypinator	0:bb348c97df44	3060	uint32_t pllvco = 0U;
lypinator	0:bb348c97df44	3061	uint32_t pllp = 0U;
lypinator	0:bb348c97df44	3062	uint32_t pllr = 0U;
lypinator	0:bb348c97df44	3063	uint32_t sysclockfreq = 0U;
lypinator	0:bb348c97df44	3064
lypinator	0:bb348c97df44	3065	/* Get SYSCLK source -------------------------------------------------------*/
lypinator	0:bb348c97df44	3066	switch (RCC->CFGR & RCC_CFGR_SWS)
lypinator	0:bb348c97df44	3067	{
lypinator	0:bb348c97df44	3068	case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */
lypinator	0:bb348c97df44	3069	{
lypinator	0:bb348c97df44	3070	sysclockfreq = HSI_VALUE;
lypinator	0:bb348c97df44	3071	break;
lypinator	0:bb348c97df44	3072	}
lypinator	0:bb348c97df44	3073	case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */
lypinator	0:bb348c97df44	3074	{
lypinator	0:bb348c97df44	3075	sysclockfreq = HSE_VALUE;
lypinator	0:bb348c97df44	3076	break;
lypinator	0:bb348c97df44	3077	}
lypinator	0:bb348c97df44	3078	case RCC_CFGR_SWS_PLL: /* PLL/PLLP used as system clock source */
lypinator	0:bb348c97df44	3079	{
lypinator	0:bb348c97df44	3080	/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
lypinator	0:bb348c97df44	3081	SYSCLK = PLL_VCO / PLLP */
lypinator	0:bb348c97df44	3082	pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
lypinator	0:bb348c97df44	3083	if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
lypinator	0:bb348c97df44	3084	{
lypinator	0:bb348c97df44	3085	/* HSE used as PLL clock source */
lypinator	0:bb348c97df44	3086	pllvco = (uint32_t) ((((uint64_t) HSE_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
lypinator	0:bb348c97df44	3087	}
lypinator	0:bb348c97df44	3088	else
lypinator	0:bb348c97df44	3089	{
lypinator	0:bb348c97df44	3090	/* HSI used as PLL clock source */
lypinator	0:bb348c97df44	3091	pllvco = (uint32_t) ((((uint64_t) HSI_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
lypinator	0:bb348c97df44	3092	}
lypinator	0:bb348c97df44	3093	pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1U) *2U);
lypinator	0:bb348c97df44	3094
lypinator	0:bb348c97df44	3095	sysclockfreq = pllvco/pllp;
lypinator	0:bb348c97df44	3096	break;
lypinator	0:bb348c97df44	3097	}
lypinator	0:bb348c97df44	3098	case RCC_CFGR_SWS_PLLR: /* PLL/PLLR used as system clock source */
lypinator	0:bb348c97df44	3099	{
lypinator	0:bb348c97df44	3100	/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
lypinator	0:bb348c97df44	3101	SYSCLK = PLL_VCO / PLLR */
lypinator	0:bb348c97df44	3102	pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
lypinator	0:bb348c97df44	3103	if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
lypinator	0:bb348c97df44	3104	{
lypinator	0:bb348c97df44	3105	/* HSE used as PLL clock source */
lypinator	0:bb348c97df44	3106	pllvco = (uint32_t) ((((uint64_t) HSE_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
lypinator	0:bb348c97df44	3107	}
lypinator	0:bb348c97df44	3108	else
lypinator	0:bb348c97df44	3109	{
lypinator	0:bb348c97df44	3110	/* HSI used as PLL clock source */
lypinator	0:bb348c97df44	3111	pllvco = (uint32_t) ((((uint64_t) HSI_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
lypinator	0:bb348c97df44	3112	}
lypinator	0:bb348c97df44	3113	pllr = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos);
lypinator	0:bb348c97df44	3114
lypinator	0:bb348c97df44	3115	sysclockfreq = pllvco/pllr;
lypinator	0:bb348c97df44	3116	break;
lypinator	0:bb348c97df44	3117	}
lypinator	0:bb348c97df44	3118	default:
lypinator	0:bb348c97df44	3119	{
lypinator	0:bb348c97df44	3120	sysclockfreq = HSI_VALUE;
lypinator	0:bb348c97df44	3121	break;
lypinator	0:bb348c97df44	3122	}
lypinator	0:bb348c97df44	3123	}
lypinator	0:bb348c97df44	3124	return sysclockfreq;
lypinator	0:bb348c97df44	3125	}
lypinator	0:bb348c97df44	3126	#endif /* STM32F446xx */
lypinator	0:bb348c97df44	3127
lypinator	0:bb348c97df44	3128	/**
lypinator	0:bb348c97df44	3129	* @}
lypinator	0:bb348c97df44	3130	*/
lypinator	0:bb348c97df44	3131
lypinator	0:bb348c97df44	3132	/**
lypinator	0:bb348c97df44	3133	* @}
lypinator	0:bb348c97df44	3134	*/
lypinator	0:bb348c97df44	3135
lypinator	0:bb348c97df44	3136	/**
lypinator	0:bb348c97df44	3137	* @brief Resets the RCC clock configuration to the default reset state.
lypinator	0:bb348c97df44	3138	* @note The default reset state of the clock configuration is given below:
lypinator	0:bb348c97df44	3139	* - HSI ON and used as system clock source
lypinator	0:bb348c97df44	3140	* - HSE, PLL, PLLI2S and PLLSAI OFF
lypinator	0:bb348c97df44	3141	* - AHB, APB1 and APB2 prescaler set to 1.
lypinator	0:bb348c97df44	3142	* - CSS, MCO1 and MCO2 OFF
lypinator	0:bb348c97df44	3143	* - All interrupts disabled
lypinator	0:bb348c97df44	3144	* @note This function doesn't modify the configuration of the
lypinator	0:bb348c97df44	3145	* - Peripheral clocks
lypinator	0:bb348c97df44	3146	* - LSI, LSE and RTC clocks
lypinator	0:bb348c97df44	3147	* @retval HAL status
lypinator	0:bb348c97df44	3148	*/
lypinator	0:bb348c97df44	3149	HAL_StatusTypeDef HAL_RCC_DeInit(void)
lypinator	0:bb348c97df44	3150	{
lypinator	0:bb348c97df44	3151	uint32_t tickstart;
lypinator	0:bb348c97df44	3152
lypinator	0:bb348c97df44	3153	/* Get Start Tick */
lypinator	0:bb348c97df44	3154	tickstart = HAL_GetTick();
lypinator	0:bb348c97df44	3155
lypinator	0:bb348c97df44	3156	/* Set HSION bit to the reset value */
lypinator	0:bb348c97df44	3157	SET_BIT(RCC->CR, RCC_CR_HSION);
lypinator	0:bb348c97df44	3158
lypinator	0:bb348c97df44	3159	/* Wait till HSI is ready */
lypinator	0:bb348c97df44	3160	while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RESET)
lypinator	0:bb348c97df44	3161	{
lypinator	0:bb348c97df44	3162	if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
lypinator	0:bb348c97df44	3163	{
lypinator	0:bb348c97df44	3164	return HAL_TIMEOUT;
lypinator	0:bb348c97df44	3165	}
lypinator	0:bb348c97df44	3166	}
lypinator	0:bb348c97df44	3167
lypinator	0:bb348c97df44	3168	/* Set HSITRIM[4:0] bits to the reset value */
lypinator	0:bb348c97df44	3169	SET_BIT(RCC->CR, RCC_CR_HSITRIM_4);
lypinator	0:bb348c97df44	3170
lypinator	0:bb348c97df44	3171	/* Get Start Tick */
lypinator	0:bb348c97df44	3172	tickstart = HAL_GetTick();
lypinator	0:bb348c97df44	3173
lypinator	0:bb348c97df44	3174	/* Reset CFGR register */
lypinator	0:bb348c97df44	3175	CLEAR_REG(RCC->CFGR);
lypinator	0:bb348c97df44	3176
lypinator	0:bb348c97df44	3177	/* Wait till clock switch is ready */
lypinator	0:bb348c97df44	3178	while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != RESET)
lypinator	0:bb348c97df44	3179	{
lypinator	0:bb348c97df44	3180	if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
lypinator	0:bb348c97df44	3181	{
lypinator	0:bb348c97df44	3182	return HAL_TIMEOUT;
lypinator	0:bb348c97df44	3183	}
lypinator	0:bb348c97df44	3184	}
lypinator	0:bb348c97df44	3185
lypinator	0:bb348c97df44	3186	/* Get Start Tick */
lypinator	0:bb348c97df44	3187	tickstart = HAL_GetTick();
lypinator	0:bb348c97df44	3188
lypinator	0:bb348c97df44	3189	/* Clear HSEON, HSEBYP and CSSON bits */
lypinator	0:bb348c97df44	3190	CLEAR_BIT(RCC->CR, RCC_CR_HSEON \| RCC_CR_HSEBYP \| RCC_CR_CSSON);
lypinator	0:bb348c97df44	3191
lypinator	0:bb348c97df44	3192	/* Wait till HSE is disabled */
lypinator	0:bb348c97df44	3193	while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != RESET)
lypinator	0:bb348c97df44	3194	{
lypinator	0:bb348c97df44	3195	if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
lypinator	0:bb348c97df44	3196	{
lypinator	0:bb348c97df44	3197	return HAL_TIMEOUT;
lypinator	0:bb348c97df44	3198	}
lypinator	0:bb348c97df44	3199	}
lypinator	0:bb348c97df44	3200
lypinator	0:bb348c97df44	3201	/* Get Start Tick */
lypinator	0:bb348c97df44	3202	tickstart = HAL_GetTick();
lypinator	0:bb348c97df44	3203
lypinator	0:bb348c97df44	3204	/* Clear PLLON bit */
lypinator	0:bb348c97df44	3205	CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
lypinator	0:bb348c97df44	3206
lypinator	0:bb348c97df44	3207	/* Wait till PLL is disabled */
lypinator	0:bb348c97df44	3208	while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != RESET)
lypinator	0:bb348c97df44	3209	{
lypinator	0:bb348c97df44	3210	if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
lypinator	0:bb348c97df44	3211	{
lypinator	0:bb348c97df44	3212	return HAL_TIMEOUT;
lypinator	0:bb348c97df44	3213	}
lypinator	0:bb348c97df44	3214	}
lypinator	0:bb348c97df44	3215
lypinator	0:bb348c97df44	3216	#if defined(RCC_PLLI2S_SUPPORT)
lypinator	0:bb348c97df44	3217	/* Get Start Tick */
lypinator	0:bb348c97df44	3218	tickstart = HAL_GetTick();
lypinator	0:bb348c97df44	3219
lypinator	0:bb348c97df44	3220	/* Reset PLLI2SON bit */
lypinator	0:bb348c97df44	3221	CLEAR_BIT(RCC->CR, RCC_CR_PLLI2SON);
lypinator	0:bb348c97df44	3222
lypinator	0:bb348c97df44	3223	/* Wait till PLLI2S is disabled */
lypinator	0:bb348c97df44	3224	while (READ_BIT(RCC->CR, RCC_CR_PLLI2SRDY) != RESET)
lypinator	0:bb348c97df44	3225	{
lypinator	0:bb348c97df44	3226	if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
lypinator	0:bb348c97df44	3227	{
lypinator	0:bb348c97df44	3228	return HAL_TIMEOUT;
lypinator	0:bb348c97df44	3229	}
lypinator	0:bb348c97df44	3230	}
lypinator	0:bb348c97df44	3231	#endif /* RCC_PLLI2S_SUPPORT */
lypinator	0:bb348c97df44	3232
lypinator	0:bb348c97df44	3233	#if defined(RCC_PLLSAI_SUPPORT)
lypinator	0:bb348c97df44	3234	/* Get Start Tick */
lypinator	0:bb348c97df44	3235	tickstart = HAL_GetTick();
lypinator	0:bb348c97df44	3236
lypinator	0:bb348c97df44	3237	/* Reset PLLSAI bit */
lypinator	0:bb348c97df44	3238	CLEAR_BIT(RCC->CR, RCC_CR_PLLSAION);
lypinator	0:bb348c97df44	3239
lypinator	0:bb348c97df44	3240	/* Wait till PLLSAI is disabled */
lypinator	0:bb348c97df44	3241	while (READ_BIT(RCC->CR, RCC_CR_PLLSAIRDY) != RESET)
lypinator	0:bb348c97df44	3242	{
lypinator	0:bb348c97df44	3243	if ((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)
lypinator	0:bb348c97df44	3244	{
lypinator	0:bb348c97df44	3245	return HAL_TIMEOUT;
lypinator	0:bb348c97df44	3246	}
lypinator	0:bb348c97df44	3247	}
lypinator	0:bb348c97df44	3248	#endif /* RCC_PLLSAI_SUPPORT */
lypinator	0:bb348c97df44	3249
lypinator	0:bb348c97df44	3250	/* Once PLL, PLLI2S and PLLSAI are OFF, reset PLLCFGR register to default value */
lypinator	0:bb348c97df44	3251	#if defined(STM32F412Cx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Zx) \|\| defined(STM32F413xx) \|\| \
lypinator	0:bb348c97df44	3252	defined(STM32F423xx) \|\| defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
lypinator	0:bb348c97df44	3253	RCC->PLLCFGR = RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLN_6 \| RCC_PLLCFGR_PLLN_7 \| RCC_PLLCFGR_PLLQ_2 \| RCC_PLLCFGR_PLLR_1;
lypinator	0:bb348c97df44	3254	#elif defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
lypinator	0:bb348c97df44	3255	RCC->PLLCFGR = RCC_PLLCFGR_PLLR_0 \| RCC_PLLCFGR_PLLR_1 \| RCC_PLLCFGR_PLLR_2 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLN_6 \| RCC_PLLCFGR_PLLN_7 \| RCC_PLLCFGR_PLLQ_0 \| RCC_PLLCFGR_PLLQ_1 \| RCC_PLLCFGR_PLLQ_2 \| RCC_PLLCFGR_PLLQ_3;
lypinator	0:bb348c97df44	3256	#else
lypinator	0:bb348c97df44	3257	RCC->PLLCFGR = RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLN_6 \| RCC_PLLCFGR_PLLN_7 \| RCC_PLLCFGR_PLLQ_2;
lypinator	0:bb348c97df44	3258	#endif /* STM32F412Cx \|\| STM32F412Rx \|\| STM32F412Vx \|\| STM32F412Zx \|\| STM32F413xx \|\| STM32F423xx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
lypinator	0:bb348c97df44	3259
lypinator	0:bb348c97df44	3260	/* Reset PLLI2SCFGR register to default value */
lypinator	0:bb348c97df44	3261	#if defined(STM32F412Cx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Zx) \|\| defined(STM32F413xx) \|\| \
lypinator	0:bb348c97df44	3262	defined(STM32F423xx) \|\| defined(STM32F446xx)
lypinator	0:bb348c97df44	3263	RCC->PLLI2SCFGR = RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SN_6 \| RCC_PLLI2SCFGR_PLLI2SN_7 \| RCC_PLLI2SCFGR_PLLI2SQ_2 \| RCC_PLLI2SCFGR_PLLI2SR_1;
lypinator	0:bb348c97df44	3264	#elif defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx)
lypinator	0:bb348c97df44	3265	RCC->PLLI2SCFGR = RCC_PLLI2SCFGR_PLLI2SN_6 \| RCC_PLLI2SCFGR_PLLI2SN_7 \| RCC_PLLI2SCFGR_PLLI2SR_1;
lypinator	0:bb348c97df44	3266	#elif defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
lypinator	0:bb348c97df44	3267	RCC->PLLI2SCFGR = RCC_PLLI2SCFGR_PLLI2SN_6 \| RCC_PLLI2SCFGR_PLLI2SN_7 \| RCC_PLLI2SCFGR_PLLI2SQ_2 \| RCC_PLLI2SCFGR_PLLI2SR_1;
lypinator	0:bb348c97df44	3268	#elif defined(STM32F411xE)
lypinator	0:bb348c97df44	3269	RCC->PLLI2SCFGR = RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SN_6 \| RCC_PLLI2SCFGR_PLLI2SN_7 \| RCC_PLLI2SCFGR_PLLI2SR_1;
lypinator	0:bb348c97df44	3270	#endif /* STM32F412Cx \|\| STM32F412Rx \|\| STM32F412Vx \|\| STM32F412Zx \|\| STM32F413xx \|\| STM32F423xx \|\| STM32F446xx */
lypinator	0:bb348c97df44	3271
lypinator	0:bb348c97df44	3272	/* Reset PLLSAICFGR register */
lypinator	0:bb348c97df44	3273	#if defined(STM32F427xx) \|\| defined(STM32F429xx) \|\| defined(STM32F437xx) \|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
lypinator	0:bb348c97df44	3274	RCC->PLLSAICFGR = RCC_PLLSAICFGR_PLLSAIN_6 \| RCC_PLLSAICFGR_PLLSAIN_7 \| RCC_PLLSAICFGR_PLLSAIQ_2 \| RCC_PLLSAICFGR_PLLSAIR_1;
lypinator	0:bb348c97df44	3275	#elif defined(STM32F446xx)
lypinator	0:bb348c97df44	3276	RCC->PLLSAICFGR = RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIN_6 \| RCC_PLLSAICFGR_PLLSAIN_7 \| RCC_PLLSAICFGR_PLLSAIQ_2;
lypinator	0:bb348c97df44	3277	#endif /* STM32F427xx \|\| STM32F429xx \|\| STM32F437xx \|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
lypinator	0:bb348c97df44	3278
lypinator	0:bb348c97df44	3279	/* Disable all interrupts */
lypinator	0:bb348c97df44	3280	CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE \| RCC_CIR_LSERDYIE \| RCC_CIR_HSIRDYIE \| RCC_CIR_HSERDYIE \| RCC_CIR_PLLRDYIE);
lypinator	0:bb348c97df44	3281
lypinator	0:bb348c97df44	3282	#if defined(RCC_CIR_PLLI2SRDYIE)
lypinator	0:bb348c97df44	3283	CLEAR_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE);
lypinator	0:bb348c97df44	3284	#endif /* RCC_CIR_PLLI2SRDYIE */
lypinator	0:bb348c97df44	3285
lypinator	0:bb348c97df44	3286	#if defined(RCC_CIR_PLLSAIRDYIE)
lypinator	0:bb348c97df44	3287	CLEAR_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE);
lypinator	0:bb348c97df44	3288	#endif /* RCC_CIR_PLLSAIRDYIE */
lypinator	0:bb348c97df44	3289
lypinator	0:bb348c97df44	3290	/* Clear all interrupt flags */
lypinator	0:bb348c97df44	3291	SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC \| RCC_CIR_LSERDYC \| RCC_CIR_HSIRDYC \| RCC_CIR_HSERDYC \| RCC_CIR_PLLRDYC \| RCC_CIR_CSSC);
lypinator	0:bb348c97df44	3292
lypinator	0:bb348c97df44	3293	#if defined(RCC_CIR_PLLI2SRDYC)
lypinator	0:bb348c97df44	3294	SET_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYC);
lypinator	0:bb348c97df44	3295	#endif /* RCC_CIR_PLLI2SRDYC */
lypinator	0:bb348c97df44	3296
lypinator	0:bb348c97df44	3297	#if defined(RCC_CIR_PLLSAIRDYC)
lypinator	0:bb348c97df44	3298	SET_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYC);
lypinator	0:bb348c97df44	3299	#endif /* RCC_CIR_PLLSAIRDYC */
lypinator	0:bb348c97df44	3300
lypinator	0:bb348c97df44	3301	/* Clear LSION bit */
lypinator	0:bb348c97df44	3302	CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
lypinator	0:bb348c97df44	3303
lypinator	0:bb348c97df44	3304	/* Reset all CSR flags */
lypinator	0:bb348c97df44	3305	SET_BIT(RCC->CSR, RCC_CSR_RMVF);
lypinator	0:bb348c97df44	3306
lypinator	0:bb348c97df44	3307	/* Update the SystemCoreClock global variable */
lypinator	0:bb348c97df44	3308	SystemCoreClock = HSI_VALUE;
lypinator	0:bb348c97df44	3309
lypinator	0:bb348c97df44	3310	/* Adapt Systick interrupt period */
lypinator	0:bb348c97df44	3311	if(HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
lypinator	0:bb348c97df44	3312	{
lypinator	0:bb348c97df44	3313	return HAL_ERROR;
lypinator	0:bb348c97df44	3314	}
lypinator	0:bb348c97df44	3315	else
lypinator	0:bb348c97df44	3316	{
lypinator	0:bb348c97df44	3317	return HAL_OK;
lypinator	0:bb348c97df44	3318	}
lypinator	0:bb348c97df44	3319	}
lypinator	0:bb348c97df44	3320
lypinator	0:bb348c97df44	3321	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx) \|\| defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\|\
lypinator	0:bb348c97df44	3322	defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
lypinator	0:bb348c97df44	3323	/**
lypinator	0:bb348c97df44	3324	* @brief Initializes the RCC Oscillators according to the specified parameters in the
lypinator	0:bb348c97df44	3325	* RCC_OscInitTypeDef.
lypinator	0:bb348c97df44	3326	* @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
lypinator	0:bb348c97df44	3327	* contains the configuration information for the RCC Oscillators.
lypinator	0:bb348c97df44	3328	* @note The PLL is not disabled when used as system clock.
lypinator	0:bb348c97df44	3329	* @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
lypinator	0:bb348c97df44	3330	* supported by this API. User should request a transition to LSE Off
lypinator	0:bb348c97df44	3331	* first and then LSE On or LSE Bypass.
lypinator	0:bb348c97df44	3332	* @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
lypinator	0:bb348c97df44	3333	* supported by this API. User should request a transition to HSE Off
lypinator	0:bb348c97df44	3334	* first and then HSE On or HSE Bypass.
lypinator	0:bb348c97df44	3335	* @note This function add the PLL/PLLR factor management during PLL configuration this feature
lypinator	0:bb348c97df44	3336	* is only available in STM32F410xx/STM32F446xx/STM32F469xx/STM32F479xx/STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx devices
lypinator	0:bb348c97df44	3337	* @retval HAL status
lypinator	0:bb348c97df44	3338	*/
lypinator	0:bb348c97df44	3339	HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
lypinator	0:bb348c97df44	3340	{
lypinator	0:bb348c97df44	3341	uint32_t tickstart = 0U;
lypinator	0:bb348c97df44	3342
lypinator	0:bb348c97df44	3343	/* Check the parameters */
lypinator	0:bb348c97df44	3344	assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
lypinator	0:bb348c97df44	3345	/------------------------------- HSE Configuration ------------------------/
lypinator	0:bb348c97df44	3346	if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
lypinator	0:bb348c97df44	3347	{
lypinator	0:bb348c97df44	3348	/* Check the parameters */
lypinator	0:bb348c97df44	3349	assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
lypinator	0:bb348c97df44	3350	/* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */
lypinator	0:bb348c97df44	3351	#if defined(STM32F446xx)
lypinator	0:bb348c97df44	3352	if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) \|\|\
lypinator	0:bb348c97df44	3353	((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)) \|\|\
lypinator	0:bb348c97df44	3354	((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
lypinator	0:bb348c97df44	3355	#else
lypinator	0:bb348c97df44	3356	if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) \|\|\
lypinator	0:bb348c97df44	3357	((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
lypinator	0:bb348c97df44	3358	#endif /* STM32F446xx */
lypinator	0:bb348c97df44	3359	{
lypinator	0:bb348c97df44	3360	if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
lypinator	0:bb348c97df44	3361	{
lypinator	0:bb348c97df44	3362	return HAL_ERROR;
lypinator	0:bb348c97df44	3363	}
lypinator	0:bb348c97df44	3364	}
lypinator	0:bb348c97df44	3365	else
lypinator	0:bb348c97df44	3366	{
lypinator	0:bb348c97df44	3367	/* Set the new HSE configuration ---------------------------------------*/
lypinator	0:bb348c97df44	3368	__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
lypinator	0:bb348c97df44	3369
lypinator	0:bb348c97df44	3370	/* Check the HSE State */
lypinator	0:bb348c97df44	3371	if((RCC_OscInitStruct->HSEState) != RCC_HSE_OFF)
lypinator	0:bb348c97df44	3372	{
lypinator	0:bb348c97df44	3373	/* Get Start Tick*/
lypinator	0:bb348c97df44	3374	tickstart = HAL_GetTick();
lypinator	0:bb348c97df44	3375
lypinator	0:bb348c97df44	3376	/* Wait till HSE is ready */
lypinator	0:bb348c97df44	3377	while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
lypinator	0:bb348c97df44	3378	{
lypinator	0:bb348c97df44	3379	if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
lypinator	0:bb348c97df44	3380	{
lypinator	0:bb348c97df44	3381	return HAL_TIMEOUT;
lypinator	0:bb348c97df44	3382	}
lypinator	0:bb348c97df44	3383	}
lypinator	0:bb348c97df44	3384	}
lypinator	0:bb348c97df44	3385	else
lypinator	0:bb348c97df44	3386	{
lypinator	0:bb348c97df44	3387	/* Get Start Tick*/
lypinator	0:bb348c97df44	3388	tickstart = HAL_GetTick();
lypinator	0:bb348c97df44	3389
lypinator	0:bb348c97df44	3390	/* Wait till HSE is bypassed or disabled */
lypinator	0:bb348c97df44	3391	while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
lypinator	0:bb348c97df44	3392	{
lypinator	0:bb348c97df44	3393	if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
lypinator	0:bb348c97df44	3394	{
lypinator	0:bb348c97df44	3395	return HAL_TIMEOUT;
lypinator	0:bb348c97df44	3396	}
lypinator	0:bb348c97df44	3397	}
lypinator	0:bb348c97df44	3398	}
lypinator	0:bb348c97df44	3399	}
lypinator	0:bb348c97df44	3400	}
lypinator	0:bb348c97df44	3401	/----------------------------- HSI Configuration --------------------------/
lypinator	0:bb348c97df44	3402	if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
lypinator	0:bb348c97df44	3403	{
lypinator	0:bb348c97df44	3404	/* Check the parameters */
lypinator	0:bb348c97df44	3405	assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
lypinator	0:bb348c97df44	3406	assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
lypinator	0:bb348c97df44	3407
lypinator	0:bb348c97df44	3408	/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
lypinator	0:bb348c97df44	3409	#if defined(STM32F446xx)
lypinator	0:bb348c97df44	3410	if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) \|\|\
lypinator	0:bb348c97df44	3411	((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)) \|\|\
lypinator	0:bb348c97df44	3412	((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
lypinator	0:bb348c97df44	3413	#else
lypinator	0:bb348c97df44	3414	if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) \|\|\
lypinator	0:bb348c97df44	3415	((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
lypinator	0:bb348c97df44	3416	#endif /* STM32F446xx */
lypinator	0:bb348c97df44	3417	{
lypinator	0:bb348c97df44	3418	/* When HSI is used as system clock it will not disabled */
lypinator	0:bb348c97df44	3419	if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
lypinator	0:bb348c97df44	3420	{
lypinator	0:bb348c97df44	3421	return HAL_ERROR;
lypinator	0:bb348c97df44	3422	}
lypinator	0:bb348c97df44	3423	/* Otherwise, just the calibration is allowed */
lypinator	0:bb348c97df44	3424	else
lypinator	0:bb348c97df44	3425	{
lypinator	0:bb348c97df44	3426	/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
lypinator	0:bb348c97df44	3427	__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
lypinator	0:bb348c97df44	3428	}
lypinator	0:bb348c97df44	3429	}
lypinator	0:bb348c97df44	3430	else
lypinator	0:bb348c97df44	3431	{
lypinator	0:bb348c97df44	3432	/* Check the HSI State */
lypinator	0:bb348c97df44	3433	if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF)
lypinator	0:bb348c97df44	3434	{
lypinator	0:bb348c97df44	3435	/* Enable the Internal High Speed oscillator (HSI). */
lypinator	0:bb348c97df44	3436	__HAL_RCC_HSI_ENABLE();
lypinator	0:bb348c97df44	3437
lypinator	0:bb348c97df44	3438	/* Get Start Tick*/
lypinator	0:bb348c97df44	3439	tickstart = HAL_GetTick();
lypinator	0:bb348c97df44	3440
lypinator	0:bb348c97df44	3441	/* Wait till HSI is ready */
lypinator	0:bb348c97df44	3442	while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
lypinator	0:bb348c97df44	3443	{
lypinator	0:bb348c97df44	3444	if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
lypinator	0:bb348c97df44	3445	{
lypinator	0:bb348c97df44	3446	return HAL_TIMEOUT;
lypinator	0:bb348c97df44	3447	}
lypinator	0:bb348c97df44	3448	}
lypinator	0:bb348c97df44	3449
lypinator	0:bb348c97df44	3450	/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
lypinator	0:bb348c97df44	3451	__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
lypinator	0:bb348c97df44	3452	}
lypinator	0:bb348c97df44	3453	else
lypinator	0:bb348c97df44	3454	{
lypinator	0:bb348c97df44	3455	/* Disable the Internal High Speed oscillator (HSI). */
lypinator	0:bb348c97df44	3456	__HAL_RCC_HSI_DISABLE();
lypinator	0:bb348c97df44	3457
lypinator	0:bb348c97df44	3458	/* Get Start Tick*/
lypinator	0:bb348c97df44	3459	tickstart = HAL_GetTick();
lypinator	0:bb348c97df44	3460
lypinator	0:bb348c97df44	3461	/* Wait till HSI is ready */
lypinator	0:bb348c97df44	3462	while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
lypinator	0:bb348c97df44	3463	{
lypinator	0:bb348c97df44	3464	if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
lypinator	0:bb348c97df44	3465	{
lypinator	0:bb348c97df44	3466	return HAL_TIMEOUT;
lypinator	0:bb348c97df44	3467	}
lypinator	0:bb348c97df44	3468	}
lypinator	0:bb348c97df44	3469	}
lypinator	0:bb348c97df44	3470	}
lypinator	0:bb348c97df44	3471	}
lypinator	0:bb348c97df44	3472	/------------------------------ LSI Configuration -------------------------/
lypinator	0:bb348c97df44	3473	if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
lypinator	0:bb348c97df44	3474	{
lypinator	0:bb348c97df44	3475	/* Check the parameters */
lypinator	0:bb348c97df44	3476	assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
lypinator	0:bb348c97df44	3477
lypinator	0:bb348c97df44	3478	/* Check the LSI State */
lypinator	0:bb348c97df44	3479	if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF)
lypinator	0:bb348c97df44	3480	{
lypinator	0:bb348c97df44	3481	/* Enable the Internal Low Speed oscillator (LSI). */
lypinator	0:bb348c97df44	3482	__HAL_RCC_LSI_ENABLE();
lypinator	0:bb348c97df44	3483
lypinator	0:bb348c97df44	3484	/* Get Start Tick*/
lypinator	0:bb348c97df44	3485	tickstart = HAL_GetTick();
lypinator	0:bb348c97df44	3486
lypinator	0:bb348c97df44	3487	/* Wait till LSI is ready */
lypinator	0:bb348c97df44	3488	while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
lypinator	0:bb348c97df44	3489	{
lypinator	0:bb348c97df44	3490	if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
lypinator	0:bb348c97df44	3491	{
lypinator	0:bb348c97df44	3492	return HAL_TIMEOUT;
lypinator	0:bb348c97df44	3493	}
lypinator	0:bb348c97df44	3494	}
lypinator	0:bb348c97df44	3495	}
lypinator	0:bb348c97df44	3496	else
lypinator	0:bb348c97df44	3497	{
lypinator	0:bb348c97df44	3498	/* Disable the Internal Low Speed oscillator (LSI). */
lypinator	0:bb348c97df44	3499	__HAL_RCC_LSI_DISABLE();
lypinator	0:bb348c97df44	3500
lypinator	0:bb348c97df44	3501	/* Get Start Tick*/
lypinator	0:bb348c97df44	3502	tickstart = HAL_GetTick();
lypinator	0:bb348c97df44	3503
lypinator	0:bb348c97df44	3504	/* Wait till LSI is ready */
lypinator	0:bb348c97df44	3505	while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
lypinator	0:bb348c97df44	3506	{
lypinator	0:bb348c97df44	3507	if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
lypinator	0:bb348c97df44	3508	{
lypinator	0:bb348c97df44	3509	return HAL_TIMEOUT;
lypinator	0:bb348c97df44	3510	}
lypinator	0:bb348c97df44	3511	}
lypinator	0:bb348c97df44	3512	}
lypinator	0:bb348c97df44	3513	}
lypinator	0:bb348c97df44	3514	/------------------------------ LSE Configuration -------------------------/
lypinator	0:bb348c97df44	3515	if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
lypinator	0:bb348c97df44	3516	{
lypinator	0:bb348c97df44	3517	FlagStatus pwrclkchanged = RESET;
lypinator	0:bb348c97df44	3518
lypinator	0:bb348c97df44	3519	/* Check the parameters */
lypinator	0:bb348c97df44	3520	assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
lypinator	0:bb348c97df44	3521
lypinator	0:bb348c97df44	3522	/* Update LSE configuration in Backup Domain control register */
lypinator	0:bb348c97df44	3523	/* Requires to enable write access to Backup Domain of necessary */
lypinator	0:bb348c97df44	3524	if(__HAL_RCC_PWR_IS_CLK_DISABLED())
lypinator	0:bb348c97df44	3525	{
lypinator	0:bb348c97df44	3526	__HAL_RCC_PWR_CLK_ENABLE();
lypinator	0:bb348c97df44	3527	pwrclkchanged = SET;
lypinator	0:bb348c97df44	3528	}
lypinator	0:bb348c97df44	3529
lypinator	0:bb348c97df44	3530	if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
lypinator	0:bb348c97df44	3531	{
lypinator	0:bb348c97df44	3532	/* Enable write access to Backup domain */
lypinator	0:bb348c97df44	3533	SET_BIT(PWR->CR, PWR_CR_DBP);
lypinator	0:bb348c97df44	3534
lypinator	0:bb348c97df44	3535	/* Wait for Backup domain Write protection disable */
lypinator	0:bb348c97df44	3536	tickstart = HAL_GetTick();
lypinator	0:bb348c97df44	3537
lypinator	0:bb348c97df44	3538	while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
lypinator	0:bb348c97df44	3539	{
lypinator	0:bb348c97df44	3540	if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
lypinator	0:bb348c97df44	3541	{
lypinator	0:bb348c97df44	3542	return HAL_TIMEOUT;
lypinator	0:bb348c97df44	3543	}
lypinator	0:bb348c97df44	3544	}
lypinator	0:bb348c97df44	3545	}
lypinator	0:bb348c97df44	3546
lypinator	0:bb348c97df44	3547	/* Set the new LSE configuration -----------------------------------------*/
lypinator	0:bb348c97df44	3548	__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
lypinator	0:bb348c97df44	3549	/* Check the LSE State */
lypinator	0:bb348c97df44	3550	if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
lypinator	0:bb348c97df44	3551	{
lypinator	0:bb348c97df44	3552	/* Get Start Tick*/
lypinator	0:bb348c97df44	3553	tickstart = HAL_GetTick();
lypinator	0:bb348c97df44	3554
lypinator	0:bb348c97df44	3555	/* Wait till LSE is ready */
lypinator	0:bb348c97df44	3556	while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
lypinator	0:bb348c97df44	3557	{
lypinator	0:bb348c97df44	3558	if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
lypinator	0:bb348c97df44	3559	{
lypinator	0:bb348c97df44	3560	return HAL_TIMEOUT;
lypinator	0:bb348c97df44	3561	}
lypinator	0:bb348c97df44	3562	}
lypinator	0:bb348c97df44	3563	}
lypinator	0:bb348c97df44	3564	else
lypinator	0:bb348c97df44	3565	{
lypinator	0:bb348c97df44	3566	/* Get Start Tick*/
lypinator	0:bb348c97df44	3567	tickstart = HAL_GetTick();
lypinator	0:bb348c97df44	3568
lypinator	0:bb348c97df44	3569	/* Wait till LSE is ready */
lypinator	0:bb348c97df44	3570	while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
lypinator	0:bb348c97df44	3571	{
lypinator	0:bb348c97df44	3572	if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
lypinator	0:bb348c97df44	3573	{
lypinator	0:bb348c97df44	3574	return HAL_TIMEOUT;
lypinator	0:bb348c97df44	3575	}
lypinator	0:bb348c97df44	3576	}
lypinator	0:bb348c97df44	3577	}
lypinator	0:bb348c97df44	3578
lypinator	0:bb348c97df44	3579	/* Restore clock configuration if changed */
lypinator	0:bb348c97df44	3580	if(pwrclkchanged == SET)
lypinator	0:bb348c97df44	3581	{
lypinator	0:bb348c97df44	3582	__HAL_RCC_PWR_CLK_DISABLE();
lypinator	0:bb348c97df44	3583	}
lypinator	0:bb348c97df44	3584	}
lypinator	0:bb348c97df44	3585	/-------------------------------- PLL Configuration -----------------------/
lypinator	0:bb348c97df44	3586	/* Check the parameters */
lypinator	0:bb348c97df44	3587	assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
lypinator	0:bb348c97df44	3588	if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
lypinator	0:bb348c97df44	3589	{
lypinator	0:bb348c97df44	3590	/* Check if the PLL is used as system clock or not */
lypinator	0:bb348c97df44	3591	if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
lypinator	0:bb348c97df44	3592	{
lypinator	0:bb348c97df44	3593	if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
lypinator	0:bb348c97df44	3594	{
lypinator	0:bb348c97df44	3595	/* Check the parameters */
lypinator	0:bb348c97df44	3596	assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
lypinator	0:bb348c97df44	3597	assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM));
lypinator	0:bb348c97df44	3598	assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));
lypinator	0:bb348c97df44	3599	assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
lypinator	0:bb348c97df44	3600	assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
lypinator	0:bb348c97df44	3601	assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
lypinator	0:bb348c97df44	3602
lypinator	0:bb348c97df44	3603	/* Disable the main PLL. */
lypinator	0:bb348c97df44	3604	__HAL_RCC_PLL_DISABLE();
lypinator	0:bb348c97df44	3605
lypinator	0:bb348c97df44	3606	/* Get Start Tick*/
lypinator	0:bb348c97df44	3607	tickstart = HAL_GetTick();
lypinator	0:bb348c97df44	3608
lypinator	0:bb348c97df44	3609	/* Wait till PLL is ready */
lypinator	0:bb348c97df44	3610	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
lypinator	0:bb348c97df44	3611	{
lypinator	0:bb348c97df44	3612	if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
lypinator	0:bb348c97df44	3613	{
lypinator	0:bb348c97df44	3614	return HAL_TIMEOUT;
lypinator	0:bb348c97df44	3615	}
lypinator	0:bb348c97df44	3616	}
lypinator	0:bb348c97df44	3617
lypinator	0:bb348c97df44	3618	/* Configure the main PLL clock source, multiplication and division factors. */
lypinator	0:bb348c97df44	3619	__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
lypinator	0:bb348c97df44	3620	RCC_OscInitStruct->PLL.PLLM,
lypinator	0:bb348c97df44	3621	RCC_OscInitStruct->PLL.PLLN,
lypinator	0:bb348c97df44	3622	RCC_OscInitStruct->PLL.PLLP,
lypinator	0:bb348c97df44	3623	RCC_OscInitStruct->PLL.PLLQ,
lypinator	0:bb348c97df44	3624	RCC_OscInitStruct->PLL.PLLR);
lypinator	0:bb348c97df44	3625
lypinator	0:bb348c97df44	3626	/* Enable the main PLL. */
lypinator	0:bb348c97df44	3627	__HAL_RCC_PLL_ENABLE();
lypinator	0:bb348c97df44	3628
lypinator	0:bb348c97df44	3629	/* Get Start Tick*/
lypinator	0:bb348c97df44	3630	tickstart = HAL_GetTick();
lypinator	0:bb348c97df44	3631
lypinator	0:bb348c97df44	3632	/* Wait till PLL is ready */
lypinator	0:bb348c97df44	3633	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
lypinator	0:bb348c97df44	3634	{
lypinator	0:bb348c97df44	3635	if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
lypinator	0:bb348c97df44	3636	{
lypinator	0:bb348c97df44	3637	return HAL_TIMEOUT;
lypinator	0:bb348c97df44	3638	}
lypinator	0:bb348c97df44	3639	}
lypinator	0:bb348c97df44	3640	}
lypinator	0:bb348c97df44	3641	else
lypinator	0:bb348c97df44	3642	{
lypinator	0:bb348c97df44	3643	/* Disable the main PLL. */
lypinator	0:bb348c97df44	3644	__HAL_RCC_PLL_DISABLE();
lypinator	0:bb348c97df44	3645
lypinator	0:bb348c97df44	3646	/* Get Start Tick*/
lypinator	0:bb348c97df44	3647	tickstart = HAL_GetTick();
lypinator	0:bb348c97df44	3648
lypinator	0:bb348c97df44	3649	/* Wait till PLL is ready */
lypinator	0:bb348c97df44	3650	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
lypinator	0:bb348c97df44	3651	{
lypinator	0:bb348c97df44	3652	if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
lypinator	0:bb348c97df44	3653	{
lypinator	0:bb348c97df44	3654	return HAL_TIMEOUT;
lypinator	0:bb348c97df44	3655	}
lypinator	0:bb348c97df44	3656	}
lypinator	0:bb348c97df44	3657	}
lypinator	0:bb348c97df44	3658	}
lypinator	0:bb348c97df44	3659	else
lypinator	0:bb348c97df44	3660	{
lypinator	0:bb348c97df44	3661	return HAL_ERROR;
lypinator	0:bb348c97df44	3662	}
lypinator	0:bb348c97df44	3663	}
lypinator	0:bb348c97df44	3664	return HAL_OK;
lypinator	0:bb348c97df44	3665	}
lypinator	0:bb348c97df44	3666
lypinator	0:bb348c97df44	3667	/**
lypinator	0:bb348c97df44	3668	* @brief Configures the RCC_OscInitStruct according to the internal
lypinator	0:bb348c97df44	3669	* RCC configuration registers.
lypinator	0:bb348c97df44	3670	* @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that will be configured.
lypinator	0:bb348c97df44	3671	*
lypinator	0:bb348c97df44	3672	* @note This function is only available in case of STM32F410xx/STM32F446xx/STM32F469xx/STM32F479xx/STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx devices.
lypinator	0:bb348c97df44	3673	* @note This function add the PLL/PLLR factor management
lypinator	0:bb348c97df44	3674	* @retval None
lypinator	0:bb348c97df44	3675	*/
lypinator	0:bb348c97df44	3676	void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
lypinator	0:bb348c97df44	3677	{
lypinator	0:bb348c97df44	3678	/* Set all possible values for the Oscillator type parameter ---------------*/
lypinator	0:bb348c97df44	3679	RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE \| RCC_OSCILLATORTYPE_HSI \| RCC_OSCILLATORTYPE_LSE \| RCC_OSCILLATORTYPE_LSI;
lypinator	0:bb348c97df44	3680
lypinator	0:bb348c97df44	3681	/* Get the HSE configuration -----------------------------------------------*/
lypinator	0:bb348c97df44	3682	if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
lypinator	0:bb348c97df44	3683	{
lypinator	0:bb348c97df44	3684	RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
lypinator	0:bb348c97df44	3685	}
lypinator	0:bb348c97df44	3686	else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON)
lypinator	0:bb348c97df44	3687	{
lypinator	0:bb348c97df44	3688	RCC_OscInitStruct->HSEState = RCC_HSE_ON;
lypinator	0:bb348c97df44	3689	}
lypinator	0:bb348c97df44	3690	else
lypinator	0:bb348c97df44	3691	{
lypinator	0:bb348c97df44	3692	RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
lypinator	0:bb348c97df44	3693	}
lypinator	0:bb348c97df44	3694
lypinator	0:bb348c97df44	3695	/* Get the HSI configuration -----------------------------------------------*/
lypinator	0:bb348c97df44	3696	if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION)
lypinator	0:bb348c97df44	3697	{
lypinator	0:bb348c97df44	3698	RCC_OscInitStruct->HSIState = RCC_HSI_ON;
lypinator	0:bb348c97df44	3699	}
lypinator	0:bb348c97df44	3700	else
lypinator	0:bb348c97df44	3701	{
lypinator	0:bb348c97df44	3702	RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
lypinator	0:bb348c97df44	3703	}
lypinator	0:bb348c97df44	3704
lypinator	0:bb348c97df44	3705	RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR &RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos);
lypinator	0:bb348c97df44	3706
lypinator	0:bb348c97df44	3707	/* Get the LSE configuration -----------------------------------------------*/
lypinator	0:bb348c97df44	3708	if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
lypinator	0:bb348c97df44	3709	{
lypinator	0:bb348c97df44	3710	RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
lypinator	0:bb348c97df44	3711	}
lypinator	0:bb348c97df44	3712	else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
lypinator	0:bb348c97df44	3713	{
lypinator	0:bb348c97df44	3714	RCC_OscInitStruct->LSEState = RCC_LSE_ON;
lypinator	0:bb348c97df44	3715	}
lypinator	0:bb348c97df44	3716	else
lypinator	0:bb348c97df44	3717	{
lypinator	0:bb348c97df44	3718	RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
lypinator	0:bb348c97df44	3719	}
lypinator	0:bb348c97df44	3720
lypinator	0:bb348c97df44	3721	/* Get the LSI configuration -----------------------------------------------*/
lypinator	0:bb348c97df44	3722	if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION)
lypinator	0:bb348c97df44	3723	{
lypinator	0:bb348c97df44	3724	RCC_OscInitStruct->LSIState = RCC_LSI_ON;
lypinator	0:bb348c97df44	3725	}
lypinator	0:bb348c97df44	3726	else
lypinator	0:bb348c97df44	3727	{
lypinator	0:bb348c97df44	3728	RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
lypinator	0:bb348c97df44	3729	}
lypinator	0:bb348c97df44	3730
lypinator	0:bb348c97df44	3731	/* Get the PLL configuration -----------------------------------------------*/
lypinator	0:bb348c97df44	3732	if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON)
lypinator	0:bb348c97df44	3733	{
lypinator	0:bb348c97df44	3734	RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
lypinator	0:bb348c97df44	3735	}
lypinator	0:bb348c97df44	3736	else
lypinator	0:bb348c97df44	3737	{
lypinator	0:bb348c97df44	3738	RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
lypinator	0:bb348c97df44	3739	}
lypinator	0:bb348c97df44	3740	RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
lypinator	0:bb348c97df44	3741	RCC_OscInitStruct->PLL.PLLM = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM);
lypinator	0:bb348c97df44	3742	RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
lypinator	0:bb348c97df44	3743	RCC_OscInitStruct->PLL.PLLP = (uint32_t)((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) + RCC_PLLCFGR_PLLP_0) << 1U) >> RCC_PLLCFGR_PLLP_Pos);
lypinator	0:bb348c97df44	3744	RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos);
lypinator	0:bb348c97df44	3745	RCC_OscInitStruct->PLL.PLLR = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos);
lypinator	0:bb348c97df44	3746	}
lypinator	0:bb348c97df44	3747	#endif /* STM32F410xx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx \|\| STM32F413xx \|\| STM32F423xx */
lypinator	0:bb348c97df44	3748
lypinator	0:bb348c97df44	3749	#endif /* HAL_RCC_MODULE_ENABLED */
lypinator	0:bb348c97df44	3750	/**
lypinator	0:bb348c97df44	3751	* @}
lypinator	0:bb348c97df44	3752	*/
lypinator	0:bb348c97df44	3753
lypinator	0:bb348c97df44	3754	/**
lypinator	0:bb348c97df44	3755	* @}
lypinator	0:bb348c97df44	3756	*/
lypinator	0:bb348c97df44	3757
lypinator	0:bb348c97df44	3758	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Program
Created:	16 Sep 2020
Imports:	1
Forks:	0
Commits:	1
Dependents:	0
Dependencies:	1
Followers:	1

mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rcc_ex.c@0:bb348c97df44, 2020-09-16 (annotated)

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