Thomas Lyp / DevLibMemoryController

Initial commit

Dependencies:   FastPWM

mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rcc.h@0:bb348c97df44, 2020-09-16 (annotated)

Committer:
lypinator
Date:
Wed Sep 16 01:11:49 2020 +0000
Revision:
0:bb348c97df44
Added PWM

Who changed what in which revision?

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lypinator 0:bb348c97df44 1 /**
lypinator 0:bb348c97df44 2 ******************************************************************************
lypinator 0:bb348c97df44 3 * @file stm32f4xx_hal_rcc.h
lypinator 0:bb348c97df44 4 * @author MCD Application Team
lypinator 0:bb348c97df44 5 * @brief Header file of RCC HAL module.
lypinator 0:bb348c97df44 6 ******************************************************************************
lypinator 0:bb348c97df44 7 * @attention
lypinator 0:bb348c97df44 8 *
lypinator 0:bb348c97df44 9 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
lypinator 0:bb348c97df44 10 *
lypinator 0:bb348c97df44 11 * Redistribution and use in source and binary forms, with or without modification,
lypinator 0:bb348c97df44 12 * are permitted provided that the following conditions are met:
lypinator 0:bb348c97df44 13 * 1. Redistributions of source code must retain the above copyright notice,
lypinator 0:bb348c97df44 14 * this list of conditions and the following disclaimer.
lypinator 0:bb348c97df44 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
lypinator 0:bb348c97df44 16 * this list of conditions and the following disclaimer in the documentation
lypinator 0:bb348c97df44 17 * and/or other materials provided with the distribution.
lypinator 0:bb348c97df44 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
lypinator 0:bb348c97df44 19 * may be used to endorse or promote products derived from this software
lypinator 0:bb348c97df44 20 * without specific prior written permission.
lypinator 0:bb348c97df44 21 *
lypinator 0:bb348c97df44 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
lypinator 0:bb348c97df44 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
lypinator 0:bb348c97df44 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
lypinator 0:bb348c97df44 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
lypinator 0:bb348c97df44 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
lypinator 0:bb348c97df44 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
lypinator 0:bb348c97df44 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
lypinator 0:bb348c97df44 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
lypinator 0:bb348c97df44 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
lypinator 0:bb348c97df44 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
lypinator 0:bb348c97df44 32 *
lypinator 0:bb348c97df44 33 ******************************************************************************
lypinator 0:bb348c97df44 34 */
lypinator 0:bb348c97df44 35
lypinator 0:bb348c97df44 36 /* Define to prevent recursive inclusion -------------------------------------*/
lypinator 0:bb348c97df44 37 #ifndef __STM32F4xx_HAL_RCC_H
lypinator 0:bb348c97df44 38 #define __STM32F4xx_HAL_RCC_H
lypinator 0:bb348c97df44 39
lypinator 0:bb348c97df44 40 #ifdef __cplusplus
lypinator 0:bb348c97df44 41 extern "C" {
lypinator 0:bb348c97df44 42 #endif
lypinator 0:bb348c97df44 43
lypinator 0:bb348c97df44 44 /* Includes ------------------------------------------------------------------*/
lypinator 0:bb348c97df44 45 #include "stm32f4xx_hal_def.h"
lypinator 0:bb348c97df44 46
lypinator 0:bb348c97df44 47 /* Include RCC HAL Extended module */
lypinator 0:bb348c97df44 48 /* (include on top of file since RCC structures are defined in extended file) */
lypinator 0:bb348c97df44 49 #include "stm32f4xx_hal_rcc_ex.h"
lypinator 0:bb348c97df44 50
lypinator 0:bb348c97df44 51 /** @addtogroup STM32F4xx_HAL_Driver
lypinator 0:bb348c97df44 52 * @{
lypinator 0:bb348c97df44 53 */
lypinator 0:bb348c97df44 54
lypinator 0:bb348c97df44 55 /** @addtogroup RCC
lypinator 0:bb348c97df44 56 * @{
lypinator 0:bb348c97df44 57 */
lypinator 0:bb348c97df44 58
lypinator 0:bb348c97df44 59 /* Exported types ------------------------------------------------------------*/
lypinator 0:bb348c97df44 60 /** @defgroup RCC_Exported_Types RCC Exported Types
lypinator 0:bb348c97df44 61 * @{
lypinator 0:bb348c97df44 62 */
lypinator 0:bb348c97df44 63
lypinator 0:bb348c97df44 64 /**
lypinator 0:bb348c97df44 65 * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
lypinator 0:bb348c97df44 66 */
lypinator 0:bb348c97df44 67 typedef struct
lypinator 0:bb348c97df44 68 {
lypinator 0:bb348c97df44 69 uint32_t OscillatorType; /*!< The oscillators to be configured.
lypinator 0:bb348c97df44 70 This parameter can be a value of @ref RCC_Oscillator_Type */
lypinator 0:bb348c97df44 71
lypinator 0:bb348c97df44 72 uint32_t HSEState; /*!< The new state of the HSE.
lypinator 0:bb348c97df44 73 This parameter can be a value of @ref RCC_HSE_Config */
lypinator 0:bb348c97df44 74
lypinator 0:bb348c97df44 75 uint32_t LSEState; /*!< The new state of the LSE.
lypinator 0:bb348c97df44 76 This parameter can be a value of @ref RCC_LSE_Config */
lypinator 0:bb348c97df44 77
lypinator 0:bb348c97df44 78 uint32_t HSIState; /*!< The new state of the HSI.
lypinator 0:bb348c97df44 79 This parameter can be a value of @ref RCC_HSI_Config */
lypinator 0:bb348c97df44 80
lypinator 0:bb348c97df44 81 uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
lypinator 0:bb348c97df44 82 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
lypinator 0:bb348c97df44 83
lypinator 0:bb348c97df44 84 uint32_t LSIState; /*!< The new state of the LSI.
lypinator 0:bb348c97df44 85 This parameter can be a value of @ref RCC_LSI_Config */
lypinator 0:bb348c97df44 86
lypinator 0:bb348c97df44 87 RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */
lypinator 0:bb348c97df44 88 }RCC_OscInitTypeDef;
lypinator 0:bb348c97df44 89
lypinator 0:bb348c97df44 90 /**
lypinator 0:bb348c97df44 91 * @brief RCC System, AHB and APB busses clock configuration structure definition
lypinator 0:bb348c97df44 92 */
lypinator 0:bb348c97df44 93 typedef struct
lypinator 0:bb348c97df44 94 {
lypinator 0:bb348c97df44 95 uint32_t ClockType; /*!< The clock to be configured.
lypinator 0:bb348c97df44 96 This parameter can be a value of @ref RCC_System_Clock_Type */
lypinator 0:bb348c97df44 97
lypinator 0:bb348c97df44 98 uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
lypinator 0:bb348c97df44 99 This parameter can be a value of @ref RCC_System_Clock_Source */
lypinator 0:bb348c97df44 100
lypinator 0:bb348c97df44 101 uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
lypinator 0:bb348c97df44 102 This parameter can be a value of @ref RCC_AHB_Clock_Source */
lypinator 0:bb348c97df44 103
lypinator 0:bb348c97df44 104 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
lypinator 0:bb348c97df44 105 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
lypinator 0:bb348c97df44 106
lypinator 0:bb348c97df44 107 uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
lypinator 0:bb348c97df44 108 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
lypinator 0:bb348c97df44 109
lypinator 0:bb348c97df44 110 }RCC_ClkInitTypeDef;
lypinator 0:bb348c97df44 111
lypinator 0:bb348c97df44 112 /**
lypinator 0:bb348c97df44 113 * @}
lypinator 0:bb348c97df44 114 */
lypinator 0:bb348c97df44 115
lypinator 0:bb348c97df44 116 /* Exported constants --------------------------------------------------------*/
lypinator 0:bb348c97df44 117 /** @defgroup RCC_Exported_Constants RCC Exported Constants
lypinator 0:bb348c97df44 118 * @{
lypinator 0:bb348c97df44 119 */
lypinator 0:bb348c97df44 120
lypinator 0:bb348c97df44 121 /** @defgroup RCC_Oscillator_Type Oscillator Type
lypinator 0:bb348c97df44 122 * @{
lypinator 0:bb348c97df44 123 */
lypinator 0:bb348c97df44 124 #define RCC_OSCILLATORTYPE_NONE 0x00000000U
lypinator 0:bb348c97df44 125 #define RCC_OSCILLATORTYPE_HSE 0x00000001U
lypinator 0:bb348c97df44 126 #define RCC_OSCILLATORTYPE_HSI 0x00000002U
lypinator 0:bb348c97df44 127 #define RCC_OSCILLATORTYPE_LSE 0x00000004U
lypinator 0:bb348c97df44 128 #define RCC_OSCILLATORTYPE_LSI 0x00000008U
lypinator 0:bb348c97df44 129 /**
lypinator 0:bb348c97df44 130 * @}
lypinator 0:bb348c97df44 131 */
lypinator 0:bb348c97df44 132
lypinator 0:bb348c97df44 133 /** @defgroup RCC_HSE_Config HSE Config
lypinator 0:bb348c97df44 134 * @{
lypinator 0:bb348c97df44 135 */
lypinator 0:bb348c97df44 136 #define RCC_HSE_OFF 0x00000000U
lypinator 0:bb348c97df44 137 #define RCC_HSE_ON RCC_CR_HSEON
lypinator 0:bb348c97df44 138 #define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON))
lypinator 0:bb348c97df44 139 /**
lypinator 0:bb348c97df44 140 * @}
lypinator 0:bb348c97df44 141 */
lypinator 0:bb348c97df44 142
lypinator 0:bb348c97df44 143 /** @defgroup RCC_LSE_Config LSE Config
lypinator 0:bb348c97df44 144 * @{
lypinator 0:bb348c97df44 145 */
lypinator 0:bb348c97df44 146 #define RCC_LSE_OFF 0x00000000U
lypinator 0:bb348c97df44 147 #define RCC_LSE_ON RCC_BDCR_LSEON
lypinator 0:bb348c97df44 148 #define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON))
lypinator 0:bb348c97df44 149 /**
lypinator 0:bb348c97df44 150 * @}
lypinator 0:bb348c97df44 151 */
lypinator 0:bb348c97df44 152
lypinator 0:bb348c97df44 153 /** @defgroup RCC_HSI_Config HSI Config
lypinator 0:bb348c97df44 154 * @{
lypinator 0:bb348c97df44 155 */
lypinator 0:bb348c97df44 156 #define RCC_HSI_OFF ((uint8_t)0x00)
lypinator 0:bb348c97df44 157 #define RCC_HSI_ON ((uint8_t)0x01)
lypinator 0:bb348c97df44 158
lypinator 0:bb348c97df44 159 #define RCC_HSICALIBRATION_DEFAULT 0x10U /* Default HSI calibration trimming value */
lypinator 0:bb348c97df44 160 /**
lypinator 0:bb348c97df44 161 * @}
lypinator 0:bb348c97df44 162 */
lypinator 0:bb348c97df44 163
lypinator 0:bb348c97df44 164 /** @defgroup RCC_LSI_Config LSI Config
lypinator 0:bb348c97df44 165 * @{
lypinator 0:bb348c97df44 166 */
lypinator 0:bb348c97df44 167 #define RCC_LSI_OFF ((uint8_t)0x00)
lypinator 0:bb348c97df44 168 #define RCC_LSI_ON ((uint8_t)0x01)
lypinator 0:bb348c97df44 169 /**
lypinator 0:bb348c97df44 170 * @}
lypinator 0:bb348c97df44 171 */
lypinator 0:bb348c97df44 172
lypinator 0:bb348c97df44 173 /** @defgroup RCC_PLL_Config PLL Config
lypinator 0:bb348c97df44 174 * @{
lypinator 0:bb348c97df44 175 */
lypinator 0:bb348c97df44 176 #define RCC_PLL_NONE ((uint8_t)0x00)
lypinator 0:bb348c97df44 177 #define RCC_PLL_OFF ((uint8_t)0x01)
lypinator 0:bb348c97df44 178 #define RCC_PLL_ON ((uint8_t)0x02)
lypinator 0:bb348c97df44 179 /**
lypinator 0:bb348c97df44 180 * @}
lypinator 0:bb348c97df44 181 */
lypinator 0:bb348c97df44 182
lypinator 0:bb348c97df44 183 /** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider
lypinator 0:bb348c97df44 184 * @{
lypinator 0:bb348c97df44 185 */
lypinator 0:bb348c97df44 186 #define RCC_PLLP_DIV2 0x00000002U
lypinator 0:bb348c97df44 187 #define RCC_PLLP_DIV4 0x00000004U
lypinator 0:bb348c97df44 188 #define RCC_PLLP_DIV6 0x00000006U
lypinator 0:bb348c97df44 189 #define RCC_PLLP_DIV8 0x00000008U
lypinator 0:bb348c97df44 190 /**
lypinator 0:bb348c97df44 191 * @}
lypinator 0:bb348c97df44 192 */
lypinator 0:bb348c97df44 193
lypinator 0:bb348c97df44 194 /** @defgroup RCC_PLL_Clock_Source PLL Clock Source
lypinator 0:bb348c97df44 195 * @{
lypinator 0:bb348c97df44 196 */
lypinator 0:bb348c97df44 197 #define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI
lypinator 0:bb348c97df44 198 #define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE
lypinator 0:bb348c97df44 199 /**
lypinator 0:bb348c97df44 200 * @}
lypinator 0:bb348c97df44 201 */
lypinator 0:bb348c97df44 202
lypinator 0:bb348c97df44 203 /** @defgroup RCC_System_Clock_Type System Clock Type
lypinator 0:bb348c97df44 204 * @{
lypinator 0:bb348c97df44 205 */
lypinator 0:bb348c97df44 206 #define RCC_CLOCKTYPE_SYSCLK 0x00000001U
lypinator 0:bb348c97df44 207 #define RCC_CLOCKTYPE_HCLK 0x00000002U
lypinator 0:bb348c97df44 208 #define RCC_CLOCKTYPE_PCLK1 0x00000004U
lypinator 0:bb348c97df44 209 #define RCC_CLOCKTYPE_PCLK2 0x00000008U
lypinator 0:bb348c97df44 210 /**
lypinator 0:bb348c97df44 211 * @}
lypinator 0:bb348c97df44 212 */
lypinator 0:bb348c97df44 213
lypinator 0:bb348c97df44 214 /** @defgroup RCC_System_Clock_Source System Clock Source
lypinator 0:bb348c97df44 215 * @note The RCC_SYSCLKSOURCE_PLLRCLK parameter is available only for
lypinator 0:bb348c97df44 216 * STM32F446xx devices.
lypinator 0:bb348c97df44 217 * @{
lypinator 0:bb348c97df44 218 */
lypinator 0:bb348c97df44 219 #define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI
lypinator 0:bb348c97df44 220 #define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE
lypinator 0:bb348c97df44 221 #define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL
lypinator 0:bb348c97df44 222 #define RCC_SYSCLKSOURCE_PLLRCLK ((uint32_t)(RCC_CFGR_SW_0 | RCC_CFGR_SW_1))
lypinator 0:bb348c97df44 223 /**
lypinator 0:bb348c97df44 224 * @}
lypinator 0:bb348c97df44 225 */
lypinator 0:bb348c97df44 226
lypinator 0:bb348c97df44 227 /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
lypinator 0:bb348c97df44 228 * @note The RCC_SYSCLKSOURCE_STATUS_PLLRCLK parameter is available only for
lypinator 0:bb348c97df44 229 * STM32F446xx devices.
lypinator 0:bb348c97df44 230 * @{
lypinator 0:bb348c97df44 231 */
lypinator 0:bb348c97df44 232 #define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */
lypinator 0:bb348c97df44 233 #define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */
lypinator 0:bb348c97df44 234 #define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */
lypinator 0:bb348c97df44 235 #define RCC_SYSCLKSOURCE_STATUS_PLLRCLK ((uint32_t)(RCC_CFGR_SWS_0 | RCC_CFGR_SWS_1)) /*!< PLLR used as system clock */
lypinator 0:bb348c97df44 236 /**
lypinator 0:bb348c97df44 237 * @}
lypinator 0:bb348c97df44 238 */
lypinator 0:bb348c97df44 239
lypinator 0:bb348c97df44 240 /** @defgroup RCC_AHB_Clock_Source AHB Clock Source
lypinator 0:bb348c97df44 241 * @{
lypinator 0:bb348c97df44 242 */
lypinator 0:bb348c97df44 243 #define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1
lypinator 0:bb348c97df44 244 #define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2
lypinator 0:bb348c97df44 245 #define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4
lypinator 0:bb348c97df44 246 #define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8
lypinator 0:bb348c97df44 247 #define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16
lypinator 0:bb348c97df44 248 #define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64
lypinator 0:bb348c97df44 249 #define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128
lypinator 0:bb348c97df44 250 #define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256
lypinator 0:bb348c97df44 251 #define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512
lypinator 0:bb348c97df44 252 /**
lypinator 0:bb348c97df44 253 * @}
lypinator 0:bb348c97df44 254 */
lypinator 0:bb348c97df44 255
lypinator 0:bb348c97df44 256 /** @defgroup RCC_APB1_APB2_Clock_Source APB1/APB2 Clock Source
lypinator 0:bb348c97df44 257 * @{
lypinator 0:bb348c97df44 258 */
lypinator 0:bb348c97df44 259 #define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1
lypinator 0:bb348c97df44 260 #define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2
lypinator 0:bb348c97df44 261 #define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4
lypinator 0:bb348c97df44 262 #define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8
lypinator 0:bb348c97df44 263 #define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16
lypinator 0:bb348c97df44 264 /**
lypinator 0:bb348c97df44 265 * @}
lypinator 0:bb348c97df44 266 */
lypinator 0:bb348c97df44 267
lypinator 0:bb348c97df44 268 /** @defgroup RCC_RTC_Clock_Source RTC Clock Source
lypinator 0:bb348c97df44 269 * @{
lypinator 0:bb348c97df44 270 */
lypinator 0:bb348c97df44 271 #define RCC_RTCCLKSOURCE_NO_CLK 0x00000000U
lypinator 0:bb348c97df44 272 #define RCC_RTCCLKSOURCE_LSE 0x00000100U
lypinator 0:bb348c97df44 273 #define RCC_RTCCLKSOURCE_LSI 0x00000200U
lypinator 0:bb348c97df44 274 #define RCC_RTCCLKSOURCE_HSE_DIVX 0x00000300U
lypinator 0:bb348c97df44 275 #define RCC_RTCCLKSOURCE_HSE_DIV2 0x00020300U
lypinator 0:bb348c97df44 276 #define RCC_RTCCLKSOURCE_HSE_DIV3 0x00030300U
lypinator 0:bb348c97df44 277 #define RCC_RTCCLKSOURCE_HSE_DIV4 0x00040300U
lypinator 0:bb348c97df44 278 #define RCC_RTCCLKSOURCE_HSE_DIV5 0x00050300U
lypinator 0:bb348c97df44 279 #define RCC_RTCCLKSOURCE_HSE_DIV6 0x00060300U
lypinator 0:bb348c97df44 280 #define RCC_RTCCLKSOURCE_HSE_DIV7 0x00070300U
lypinator 0:bb348c97df44 281 #define RCC_RTCCLKSOURCE_HSE_DIV8 0x00080300U
lypinator 0:bb348c97df44 282 #define RCC_RTCCLKSOURCE_HSE_DIV9 0x00090300U
lypinator 0:bb348c97df44 283 #define RCC_RTCCLKSOURCE_HSE_DIV10 0x000A0300U
lypinator 0:bb348c97df44 284 #define RCC_RTCCLKSOURCE_HSE_DIV11 0x000B0300U
lypinator 0:bb348c97df44 285 #define RCC_RTCCLKSOURCE_HSE_DIV12 0x000C0300U
lypinator 0:bb348c97df44 286 #define RCC_RTCCLKSOURCE_HSE_DIV13 0x000D0300U
lypinator 0:bb348c97df44 287 #define RCC_RTCCLKSOURCE_HSE_DIV14 0x000E0300U
lypinator 0:bb348c97df44 288 #define RCC_RTCCLKSOURCE_HSE_DIV15 0x000F0300U
lypinator 0:bb348c97df44 289 #define RCC_RTCCLKSOURCE_HSE_DIV16 0x00100300U
lypinator 0:bb348c97df44 290 #define RCC_RTCCLKSOURCE_HSE_DIV17 0x00110300U
lypinator 0:bb348c97df44 291 #define RCC_RTCCLKSOURCE_HSE_DIV18 0x00120300U
lypinator 0:bb348c97df44 292 #define RCC_RTCCLKSOURCE_HSE_DIV19 0x00130300U
lypinator 0:bb348c97df44 293 #define RCC_RTCCLKSOURCE_HSE_DIV20 0x00140300U
lypinator 0:bb348c97df44 294 #define RCC_RTCCLKSOURCE_HSE_DIV21 0x00150300U
lypinator 0:bb348c97df44 295 #define RCC_RTCCLKSOURCE_HSE_DIV22 0x00160300U
lypinator 0:bb348c97df44 296 #define RCC_RTCCLKSOURCE_HSE_DIV23 0x00170300U
lypinator 0:bb348c97df44 297 #define RCC_RTCCLKSOURCE_HSE_DIV24 0x00180300U
lypinator 0:bb348c97df44 298 #define RCC_RTCCLKSOURCE_HSE_DIV25 0x00190300U
lypinator 0:bb348c97df44 299 #define RCC_RTCCLKSOURCE_HSE_DIV26 0x001A0300U
lypinator 0:bb348c97df44 300 #define RCC_RTCCLKSOURCE_HSE_DIV27 0x001B0300U
lypinator 0:bb348c97df44 301 #define RCC_RTCCLKSOURCE_HSE_DIV28 0x001C0300U
lypinator 0:bb348c97df44 302 #define RCC_RTCCLKSOURCE_HSE_DIV29 0x001D0300U
lypinator 0:bb348c97df44 303 #define RCC_RTCCLKSOURCE_HSE_DIV30 0x001E0300U
lypinator 0:bb348c97df44 304 #define RCC_RTCCLKSOURCE_HSE_DIV31 0x001F0300U
lypinator 0:bb348c97df44 305 /**
lypinator 0:bb348c97df44 306 * @}
lypinator 0:bb348c97df44 307 */
lypinator 0:bb348c97df44 308
lypinator 0:bb348c97df44 309 /** @defgroup RCC_MCO_Index MCO Index
lypinator 0:bb348c97df44 310 * @{
lypinator 0:bb348c97df44 311 */
lypinator 0:bb348c97df44 312 #define RCC_MCO1 0x00000000U
lypinator 0:bb348c97df44 313 #define RCC_MCO2 0x00000001U
lypinator 0:bb348c97df44 314 /**
lypinator 0:bb348c97df44 315 * @}
lypinator 0:bb348c97df44 316 */
lypinator 0:bb348c97df44 317
lypinator 0:bb348c97df44 318 /** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source
lypinator 0:bb348c97df44 319 * @{
lypinator 0:bb348c97df44 320 */
lypinator 0:bb348c97df44 321 #define RCC_MCO1SOURCE_HSI 0x00000000U
lypinator 0:bb348c97df44 322 #define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO1_0
lypinator 0:bb348c97df44 323 #define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO1_1
lypinator 0:bb348c97df44 324 #define RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO1
lypinator 0:bb348c97df44 325 /**
lypinator 0:bb348c97df44 326 * @}
lypinator 0:bb348c97df44 327 */
lypinator 0:bb348c97df44 328
lypinator 0:bb348c97df44 329 /** @defgroup RCC_MCOx_Clock_Prescaler MCOx Clock Prescaler
lypinator 0:bb348c97df44 330 * @{
lypinator 0:bb348c97df44 331 */
lypinator 0:bb348c97df44 332 #define RCC_MCODIV_1 0x00000000U
lypinator 0:bb348c97df44 333 #define RCC_MCODIV_2 RCC_CFGR_MCO1PRE_2
lypinator 0:bb348c97df44 334 #define RCC_MCODIV_3 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2)
lypinator 0:bb348c97df44 335 #define RCC_MCODIV_4 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)
lypinator 0:bb348c97df44 336 #define RCC_MCODIV_5 RCC_CFGR_MCO1PRE
lypinator 0:bb348c97df44 337 /**
lypinator 0:bb348c97df44 338 * @}
lypinator 0:bb348c97df44 339 */
lypinator 0:bb348c97df44 340
lypinator 0:bb348c97df44 341 /** @defgroup RCC_Interrupt Interrupts
lypinator 0:bb348c97df44 342 * @{
lypinator 0:bb348c97df44 343 */
lypinator 0:bb348c97df44 344 #define RCC_IT_LSIRDY ((uint8_t)0x01)
lypinator 0:bb348c97df44 345 #define RCC_IT_LSERDY ((uint8_t)0x02)
lypinator 0:bb348c97df44 346 #define RCC_IT_HSIRDY ((uint8_t)0x04)
lypinator 0:bb348c97df44 347 #define RCC_IT_HSERDY ((uint8_t)0x08)
lypinator 0:bb348c97df44 348 #define RCC_IT_PLLRDY ((uint8_t)0x10)
lypinator 0:bb348c97df44 349 #define RCC_IT_PLLI2SRDY ((uint8_t)0x20)
lypinator 0:bb348c97df44 350 #define RCC_IT_CSS ((uint8_t)0x80)
lypinator 0:bb348c97df44 351 /**
lypinator 0:bb348c97df44 352 * @}
lypinator 0:bb348c97df44 353 */
lypinator 0:bb348c97df44 354
lypinator 0:bb348c97df44 355 /** @defgroup RCC_Flag Flags
lypinator 0:bb348c97df44 356 * Elements values convention: 0XXYYYYYb
lypinator 0:bb348c97df44 357 * - YYYYY : Flag position in the register
lypinator 0:bb348c97df44 358 * - 0XX : Register index
lypinator 0:bb348c97df44 359 * - 01: CR register
lypinator 0:bb348c97df44 360 * - 10: BDCR register
lypinator 0:bb348c97df44 361 * - 11: CSR register
lypinator 0:bb348c97df44 362 * @{
lypinator 0:bb348c97df44 363 */
lypinator 0:bb348c97df44 364 /* Flags in the CR register */
lypinator 0:bb348c97df44 365 #define RCC_FLAG_HSIRDY ((uint8_t)0x21)
lypinator 0:bb348c97df44 366 #define RCC_FLAG_HSERDY ((uint8_t)0x31)
lypinator 0:bb348c97df44 367 #define RCC_FLAG_PLLRDY ((uint8_t)0x39)
lypinator 0:bb348c97df44 368 #define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3B)
lypinator 0:bb348c97df44 369
lypinator 0:bb348c97df44 370 /* Flags in the BDCR register */
lypinator 0:bb348c97df44 371 #define RCC_FLAG_LSERDY ((uint8_t)0x41)
lypinator 0:bb348c97df44 372
lypinator 0:bb348c97df44 373 /* Flags in the CSR register */
lypinator 0:bb348c97df44 374 #define RCC_FLAG_LSIRDY ((uint8_t)0x61)
lypinator 0:bb348c97df44 375 #define RCC_FLAG_BORRST ((uint8_t)0x79)
lypinator 0:bb348c97df44 376 #define RCC_FLAG_PINRST ((uint8_t)0x7A)
lypinator 0:bb348c97df44 377 #define RCC_FLAG_PORRST ((uint8_t)0x7B)
lypinator 0:bb348c97df44 378 #define RCC_FLAG_SFTRST ((uint8_t)0x7C)
lypinator 0:bb348c97df44 379 #define RCC_FLAG_IWDGRST ((uint8_t)0x7D)
lypinator 0:bb348c97df44 380 #define RCC_FLAG_WWDGRST ((uint8_t)0x7E)
lypinator 0:bb348c97df44 381 #define RCC_FLAG_LPWRRST ((uint8_t)0x7F)
lypinator 0:bb348c97df44 382 /**
lypinator 0:bb348c97df44 383 * @}
lypinator 0:bb348c97df44 384 */
lypinator 0:bb348c97df44 385
lypinator 0:bb348c97df44 386 /**
lypinator 0:bb348c97df44 387 * @}
lypinator 0:bb348c97df44 388 */
lypinator 0:bb348c97df44 389
lypinator 0:bb348c97df44 390 /* Exported macro ------------------------------------------------------------*/
lypinator 0:bb348c97df44 391 /** @defgroup RCC_Exported_Macros RCC Exported Macros
lypinator 0:bb348c97df44 392 * @{
lypinator 0:bb348c97df44 393 */
lypinator 0:bb348c97df44 394
lypinator 0:bb348c97df44 395 /** @defgroup RCC_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
lypinator 0:bb348c97df44 396 * @brief Enable or disable the AHB1 peripheral clock.
lypinator 0:bb348c97df44 397 * @note After reset, the peripheral clock (used for registers read/write access)
lypinator 0:bb348c97df44 398 * is disabled and the application software has to enable this clock before
lypinator 0:bb348c97df44 399 * using it.
lypinator 0:bb348c97df44 400 * @{
lypinator 0:bb348c97df44 401 */
lypinator 0:bb348c97df44 402 #define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
lypinator 0:bb348c97df44 403 __IO uint32_t tmpreg = 0x00U; \
lypinator 0:bb348c97df44 404 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
lypinator 0:bb348c97df44 405 /* Delay after an RCC peripheral clock enabling */ \
lypinator 0:bb348c97df44 406 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
lypinator 0:bb348c97df44 407 UNUSED(tmpreg); \
lypinator 0:bb348c97df44 408 } while(0U)
lypinator 0:bb348c97df44 409 #define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
lypinator 0:bb348c97df44 410 __IO uint32_t tmpreg = 0x00U; \
lypinator 0:bb348c97df44 411 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
lypinator 0:bb348c97df44 412 /* Delay after an RCC peripheral clock enabling */ \
lypinator 0:bb348c97df44 413 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
lypinator 0:bb348c97df44 414 UNUSED(tmpreg); \
lypinator 0:bb348c97df44 415 } while(0U)
lypinator 0:bb348c97df44 416 #define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
lypinator 0:bb348c97df44 417 __IO uint32_t tmpreg = 0x00U; \
lypinator 0:bb348c97df44 418 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
lypinator 0:bb348c97df44 419 /* Delay after an RCC peripheral clock enabling */ \
lypinator 0:bb348c97df44 420 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
lypinator 0:bb348c97df44 421 UNUSED(tmpreg); \
lypinator 0:bb348c97df44 422 } while(0U)
lypinator 0:bb348c97df44 423 #define __HAL_RCC_GPIOH_CLK_ENABLE() do { \
lypinator 0:bb348c97df44 424 __IO uint32_t tmpreg = 0x00U; \
lypinator 0:bb348c97df44 425 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
lypinator 0:bb348c97df44 426 /* Delay after an RCC peripheral clock enabling */ \
lypinator 0:bb348c97df44 427 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
lypinator 0:bb348c97df44 428 UNUSED(tmpreg); \
lypinator 0:bb348c97df44 429 } while(0U)
lypinator 0:bb348c97df44 430 #define __HAL_RCC_DMA1_CLK_ENABLE() do { \
lypinator 0:bb348c97df44 431 __IO uint32_t tmpreg = 0x00U; \
lypinator 0:bb348c97df44 432 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
lypinator 0:bb348c97df44 433 /* Delay after an RCC peripheral clock enabling */ \
lypinator 0:bb348c97df44 434 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
lypinator 0:bb348c97df44 435 UNUSED(tmpreg); \
lypinator 0:bb348c97df44 436 } while(0U)
lypinator 0:bb348c97df44 437 #define __HAL_RCC_DMA2_CLK_ENABLE() do { \
lypinator 0:bb348c97df44 438 __IO uint32_t tmpreg = 0x00U; \
lypinator 0:bb348c97df44 439 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
lypinator 0:bb348c97df44 440 /* Delay after an RCC peripheral clock enabling */ \
lypinator 0:bb348c97df44 441 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
lypinator 0:bb348c97df44 442 UNUSED(tmpreg); \
lypinator 0:bb348c97df44 443 } while(0U)
lypinator 0:bb348c97df44 444
lypinator 0:bb348c97df44 445 #define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN))
lypinator 0:bb348c97df44 446 #define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN))
lypinator 0:bb348c97df44 447 #define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN))
lypinator 0:bb348c97df44 448 #define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN))
lypinator 0:bb348c97df44 449 #define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA1EN))
lypinator 0:bb348c97df44 450 #define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN))
lypinator 0:bb348c97df44 451 /**
lypinator 0:bb348c97df44 452 * @}
lypinator 0:bb348c97df44 453 */
lypinator 0:bb348c97df44 454
lypinator 0:bb348c97df44 455 /** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
lypinator 0:bb348c97df44 456 * @brief Get the enable or disable status of the AHB1 peripheral clock.
lypinator 0:bb348c97df44 457 * @note After reset, the peripheral clock (used for registers read/write access)
lypinator 0:bb348c97df44 458 * is disabled and the application software has to enable this clock before
lypinator 0:bb348c97df44 459 * using it.
lypinator 0:bb348c97df44 460 * @{
lypinator 0:bb348c97df44 461 */
lypinator 0:bb348c97df44 462 #define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOAEN)) != RESET)
lypinator 0:bb348c97df44 463 #define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOBEN)) != RESET)
lypinator 0:bb348c97df44 464 #define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOCEN)) != RESET)
lypinator 0:bb348c97df44 465 #define __HAL_RCC_GPIOH_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOHEN)) != RESET)
lypinator 0:bb348c97df44 466 #define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA1EN)) != RESET)
lypinator 0:bb348c97df44 467 #define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA2EN)) != RESET)
lypinator 0:bb348c97df44 468
lypinator 0:bb348c97df44 469 #define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOAEN)) == RESET)
lypinator 0:bb348c97df44 470 #define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOBEN)) == RESET)
lypinator 0:bb348c97df44 471 #define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOCEN)) == RESET)
lypinator 0:bb348c97df44 472 #define __HAL_RCC_GPIOH_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOHEN)) == RESET)
lypinator 0:bb348c97df44 473 #define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA1EN)) == RESET)
lypinator 0:bb348c97df44 474 #define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA2EN)) == RESET)
lypinator 0:bb348c97df44 475 /**
lypinator 0:bb348c97df44 476 * @}
lypinator 0:bb348c97df44 477 */
lypinator 0:bb348c97df44 478
lypinator 0:bb348c97df44 479 /** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
lypinator 0:bb348c97df44 480 * @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
lypinator 0:bb348c97df44 481 * @note After reset, the peripheral clock (used for registers read/write access)
lypinator 0:bb348c97df44 482 * is disabled and the application software has to enable this clock before
lypinator 0:bb348c97df44 483 * using it.
lypinator 0:bb348c97df44 484 * @{
lypinator 0:bb348c97df44 485 */
lypinator 0:bb348c97df44 486 #define __HAL_RCC_TIM5_CLK_ENABLE() do { \
lypinator 0:bb348c97df44 487 __IO uint32_t tmpreg = 0x00U; \
lypinator 0:bb348c97df44 488 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
lypinator 0:bb348c97df44 489 /* Delay after an RCC peripheral clock enabling */ \
lypinator 0:bb348c97df44 490 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
lypinator 0:bb348c97df44 491 UNUSED(tmpreg); \
lypinator 0:bb348c97df44 492 } while(0U)
lypinator 0:bb348c97df44 493 #define __HAL_RCC_WWDG_CLK_ENABLE() do { \
lypinator 0:bb348c97df44 494 __IO uint32_t tmpreg = 0x00U; \
lypinator 0:bb348c97df44 495 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
lypinator 0:bb348c97df44 496 /* Delay after an RCC peripheral clock enabling */ \
lypinator 0:bb348c97df44 497 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
lypinator 0:bb348c97df44 498 UNUSED(tmpreg); \
lypinator 0:bb348c97df44 499 } while(0U)
lypinator 0:bb348c97df44 500 #define __HAL_RCC_SPI2_CLK_ENABLE() do { \
lypinator 0:bb348c97df44 501 __IO uint32_t tmpreg = 0x00U; \
lypinator 0:bb348c97df44 502 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
lypinator 0:bb348c97df44 503 /* Delay after an RCC peripheral clock enabling */ \
lypinator 0:bb348c97df44 504 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
lypinator 0:bb348c97df44 505 UNUSED(tmpreg); \
lypinator 0:bb348c97df44 506 } while(0U)
lypinator 0:bb348c97df44 507 #define __HAL_RCC_USART2_CLK_ENABLE() do { \
lypinator 0:bb348c97df44 508 __IO uint32_t tmpreg = 0x00U; \
lypinator 0:bb348c97df44 509 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
lypinator 0:bb348c97df44 510 /* Delay after an RCC peripheral clock enabling */ \
lypinator 0:bb348c97df44 511 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
lypinator 0:bb348c97df44 512 UNUSED(tmpreg); \
lypinator 0:bb348c97df44 513 } while(0U)
lypinator 0:bb348c97df44 514 #define __HAL_RCC_I2C1_CLK_ENABLE() do { \
lypinator 0:bb348c97df44 515 __IO uint32_t tmpreg = 0x00U; \
lypinator 0:bb348c97df44 516 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
lypinator 0:bb348c97df44 517 /* Delay after an RCC peripheral clock enabling */ \
lypinator 0:bb348c97df44 518 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
lypinator 0:bb348c97df44 519 UNUSED(tmpreg); \
lypinator 0:bb348c97df44 520 } while(0U)
lypinator 0:bb348c97df44 521 #define __HAL_RCC_I2C2_CLK_ENABLE() do { \
lypinator 0:bb348c97df44 522 __IO uint32_t tmpreg = 0x00U; \
lypinator 0:bb348c97df44 523 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
lypinator 0:bb348c97df44 524 /* Delay after an RCC peripheral clock enabling */ \
lypinator 0:bb348c97df44 525 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
lypinator 0:bb348c97df44 526 UNUSED(tmpreg); \
lypinator 0:bb348c97df44 527 } while(0U)
lypinator 0:bb348c97df44 528 #define __HAL_RCC_PWR_CLK_ENABLE() do { \
lypinator 0:bb348c97df44 529 __IO uint32_t tmpreg = 0x00U; \
lypinator 0:bb348c97df44 530 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
lypinator 0:bb348c97df44 531 /* Delay after an RCC peripheral clock enabling */ \
lypinator 0:bb348c97df44 532 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
lypinator 0:bb348c97df44 533 UNUSED(tmpreg); \
lypinator 0:bb348c97df44 534 } while(0U)
lypinator 0:bb348c97df44 535
lypinator 0:bb348c97df44 536 #define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
lypinator 0:bb348c97df44 537 #define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
lypinator 0:bb348c97df44 538 #define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
lypinator 0:bb348c97df44 539 #define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
lypinator 0:bb348c97df44 540 #define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
lypinator 0:bb348c97df44 541 #define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
lypinator 0:bb348c97df44 542 #define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
lypinator 0:bb348c97df44 543 /**
lypinator 0:bb348c97df44 544 * @}
lypinator 0:bb348c97df44 545 */
lypinator 0:bb348c97df44 546
lypinator 0:bb348c97df44 547 /** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
lypinator 0:bb348c97df44 548 * @brief Get the enable or disable status of the APB1 peripheral clock.
lypinator 0:bb348c97df44 549 * @note After reset, the peripheral clock (used for registers read/write access)
lypinator 0:bb348c97df44 550 * is disabled and the application software has to enable this clock before
lypinator 0:bb348c97df44 551 * using it.
lypinator 0:bb348c97df44 552 * @{
lypinator 0:bb348c97df44 553 */
lypinator 0:bb348c97df44 554 #define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET)
lypinator 0:bb348c97df44 555 #define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET)
lypinator 0:bb348c97df44 556 #define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)
lypinator 0:bb348c97df44 557 #define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)
lypinator 0:bb348c97df44 558 #define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET)
lypinator 0:bb348c97df44 559 #define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)
lypinator 0:bb348c97df44 560 #define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET)
lypinator 0:bb348c97df44 561
lypinator 0:bb348c97df44 562 #define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET)
lypinator 0:bb348c97df44 563 #define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET)
lypinator 0:bb348c97df44 564 #define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)
lypinator 0:bb348c97df44 565 #define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)
lypinator 0:bb348c97df44 566 #define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET)
lypinator 0:bb348c97df44 567 #define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)
lypinator 0:bb348c97df44 568 #define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET)
lypinator 0:bb348c97df44 569 /**
lypinator 0:bb348c97df44 570 * @}
lypinator 0:bb348c97df44 571 */
lypinator 0:bb348c97df44 572
lypinator 0:bb348c97df44 573 /** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
lypinator 0:bb348c97df44 574 * @brief Enable or disable the High Speed APB (APB2) peripheral clock.
lypinator 0:bb348c97df44 575 * @note After reset, the peripheral clock (used for registers read/write access)
lypinator 0:bb348c97df44 576 * is disabled and the application software has to enable this clock before
lypinator 0:bb348c97df44 577 * using it.
lypinator 0:bb348c97df44 578 * @{
lypinator 0:bb348c97df44 579 */
lypinator 0:bb348c97df44 580 #define __HAL_RCC_TIM1_CLK_ENABLE() do { \
lypinator 0:bb348c97df44 581 __IO uint32_t tmpreg = 0x00U; \
lypinator 0:bb348c97df44 582 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
lypinator 0:bb348c97df44 583 /* Delay after an RCC peripheral clock enabling */ \
lypinator 0:bb348c97df44 584 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
lypinator 0:bb348c97df44 585 UNUSED(tmpreg); \
lypinator 0:bb348c97df44 586 } while(0U)
lypinator 0:bb348c97df44 587 #define __HAL_RCC_USART1_CLK_ENABLE() do { \
lypinator 0:bb348c97df44 588 __IO uint32_t tmpreg = 0x00U; \
lypinator 0:bb348c97df44 589 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
lypinator 0:bb348c97df44 590 /* Delay after an RCC peripheral clock enabling */ \
lypinator 0:bb348c97df44 591 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
lypinator 0:bb348c97df44 592 UNUSED(tmpreg); \
lypinator 0:bb348c97df44 593 } while(0U)
lypinator 0:bb348c97df44 594 #define __HAL_RCC_USART6_CLK_ENABLE() do { \
lypinator 0:bb348c97df44 595 __IO uint32_t tmpreg = 0x00U; \
lypinator 0:bb348c97df44 596 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
lypinator 0:bb348c97df44 597 /* Delay after an RCC peripheral clock enabling */ \
lypinator 0:bb348c97df44 598 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
lypinator 0:bb348c97df44 599 UNUSED(tmpreg); \
lypinator 0:bb348c97df44 600 } while(0U)
lypinator 0:bb348c97df44 601 #define __HAL_RCC_ADC1_CLK_ENABLE() do { \
lypinator 0:bb348c97df44 602 __IO uint32_t tmpreg = 0x00U; \
lypinator 0:bb348c97df44 603 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
lypinator 0:bb348c97df44 604 /* Delay after an RCC peripheral clock enabling */ \
lypinator 0:bb348c97df44 605 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
lypinator 0:bb348c97df44 606 UNUSED(tmpreg); \
lypinator 0:bb348c97df44 607 } while(0U)
lypinator 0:bb348c97df44 608 #define __HAL_RCC_SPI1_CLK_ENABLE() do { \
lypinator 0:bb348c97df44 609 __IO uint32_t tmpreg = 0x00U; \
lypinator 0:bb348c97df44 610 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
lypinator 0:bb348c97df44 611 /* Delay after an RCC peripheral clock enabling */ \
lypinator 0:bb348c97df44 612 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
lypinator 0:bb348c97df44 613 UNUSED(tmpreg); \
lypinator 0:bb348c97df44 614 } while(0U)
lypinator 0:bb348c97df44 615 #define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \
lypinator 0:bb348c97df44 616 __IO uint32_t tmpreg = 0x00U; \
lypinator 0:bb348c97df44 617 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
lypinator 0:bb348c97df44 618 /* Delay after an RCC peripheral clock enabling */ \
lypinator 0:bb348c97df44 619 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
lypinator 0:bb348c97df44 620 UNUSED(tmpreg); \
lypinator 0:bb348c97df44 621 } while(0U)
lypinator 0:bb348c97df44 622 #define __HAL_RCC_TIM9_CLK_ENABLE() do { \
lypinator 0:bb348c97df44 623 __IO uint32_t tmpreg = 0x00U; \
lypinator 0:bb348c97df44 624 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
lypinator 0:bb348c97df44 625 /* Delay after an RCC peripheral clock enabling */ \
lypinator 0:bb348c97df44 626 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
lypinator 0:bb348c97df44 627 UNUSED(tmpreg); \
lypinator 0:bb348c97df44 628 } while(0U)
lypinator 0:bb348c97df44 629 #define __HAL_RCC_TIM11_CLK_ENABLE() do { \
lypinator 0:bb348c97df44 630 __IO uint32_t tmpreg = 0x00U; \
lypinator 0:bb348c97df44 631 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
lypinator 0:bb348c97df44 632 /* Delay after an RCC peripheral clock enabling */ \
lypinator 0:bb348c97df44 633 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
lypinator 0:bb348c97df44 634 UNUSED(tmpreg); \
lypinator 0:bb348c97df44 635 } while(0U)
lypinator 0:bb348c97df44 636
lypinator 0:bb348c97df44 637 #define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
lypinator 0:bb348c97df44 638 #define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
lypinator 0:bb348c97df44 639 #define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))
lypinator 0:bb348c97df44 640 #define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
lypinator 0:bb348c97df44 641 #define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
lypinator 0:bb348c97df44 642 #define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
lypinator 0:bb348c97df44 643 #define __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))
lypinator 0:bb348c97df44 644 #define __HAL_RCC_TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))
lypinator 0:bb348c97df44 645 /**
lypinator 0:bb348c97df44 646 * @}
lypinator 0:bb348c97df44 647 */
lypinator 0:bb348c97df44 648
lypinator 0:bb348c97df44 649 /** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
lypinator 0:bb348c97df44 650 * @brief Get the enable or disable status of the APB2 peripheral clock.
lypinator 0:bb348c97df44 651 * @note After reset, the peripheral clock (used for registers read/write access)
lypinator 0:bb348c97df44 652 * is disabled and the application software has to enable this clock before
lypinator 0:bb348c97df44 653 * using it.
lypinator 0:bb348c97df44 654 * @{
lypinator 0:bb348c97df44 655 */
lypinator 0:bb348c97df44 656 #define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET)
lypinator 0:bb348c97df44 657 #define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET)
lypinator 0:bb348c97df44 658 #define __HAL_RCC_USART6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) != RESET)
lypinator 0:bb348c97df44 659 #define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET)
lypinator 0:bb348c97df44 660 #define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)
lypinator 0:bb348c97df44 661 #define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != RESET)
lypinator 0:bb348c97df44 662 #define __HAL_RCC_TIM9_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != RESET)
lypinator 0:bb348c97df44 663 #define __HAL_RCC_TIM11_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != RESET)
lypinator 0:bb348c97df44 664
lypinator 0:bb348c97df44 665 #define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET)
lypinator 0:bb348c97df44 666 #define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)
lypinator 0:bb348c97df44 667 #define __HAL_RCC_USART6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) == RESET)
lypinator 0:bb348c97df44 668 #define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET)
lypinator 0:bb348c97df44 669 #define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)
lypinator 0:bb348c97df44 670 #define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == RESET)
lypinator 0:bb348c97df44 671 #define __HAL_RCC_TIM9_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == RESET)
lypinator 0:bb348c97df44 672 #define __HAL_RCC_TIM11_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == RESET)
lypinator 0:bb348c97df44 673 /**
lypinator 0:bb348c97df44 674 * @}
lypinator 0:bb348c97df44 675 */
lypinator 0:bb348c97df44 676
lypinator 0:bb348c97df44 677 /** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Force Release Reset
lypinator 0:bb348c97df44 678 * @brief Force or release AHB1 peripheral reset.
lypinator 0:bb348c97df44 679 * @{
lypinator 0:bb348c97df44 680 */
lypinator 0:bb348c97df44 681 #define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFFU)
lypinator 0:bb348c97df44 682 #define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOARST))
lypinator 0:bb348c97df44 683 #define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOBRST))
lypinator 0:bb348c97df44 684 #define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOCRST))
lypinator 0:bb348c97df44 685 #define __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOHRST))
lypinator 0:bb348c97df44 686 #define __HAL_RCC_DMA1_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST))
lypinator 0:bb348c97df44 687 #define __HAL_RCC_DMA2_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST))
lypinator 0:bb348c97df44 688
lypinator 0:bb348c97df44 689 #define __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00U)
lypinator 0:bb348c97df44 690 #define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOARST))
lypinator 0:bb348c97df44 691 #define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOBRST))
lypinator 0:bb348c97df44 692 #define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOCRST))
lypinator 0:bb348c97df44 693 #define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOHRST))
lypinator 0:bb348c97df44 694 #define __HAL_RCC_DMA1_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA1RST))
lypinator 0:bb348c97df44 695 #define __HAL_RCC_DMA2_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2RST))
lypinator 0:bb348c97df44 696 /**
lypinator 0:bb348c97df44 697 * @}
lypinator 0:bb348c97df44 698 */
lypinator 0:bb348c97df44 699
lypinator 0:bb348c97df44 700 /** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset
lypinator 0:bb348c97df44 701 * @brief Force or release APB1 peripheral reset.
lypinator 0:bb348c97df44 702 * @{
lypinator 0:bb348c97df44 703 */
lypinator 0:bb348c97df44 704 #define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU)
lypinator 0:bb348c97df44 705 #define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))
lypinator 0:bb348c97df44 706 #define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
lypinator 0:bb348c97df44 707 #define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
lypinator 0:bb348c97df44 708 #define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
lypinator 0:bb348c97df44 709 #define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
lypinator 0:bb348c97df44 710 #define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
lypinator 0:bb348c97df44 711 #define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))
lypinator 0:bb348c97df44 712
lypinator 0:bb348c97df44 713 #define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00U)
lypinator 0:bb348c97df44 714 #define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
lypinator 0:bb348c97df44 715 #define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
lypinator 0:bb348c97df44 716 #define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
lypinator 0:bb348c97df44 717 #define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
lypinator 0:bb348c97df44 718 #define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
lypinator 0:bb348c97df44 719 #define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
lypinator 0:bb348c97df44 720 #define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
lypinator 0:bb348c97df44 721 /**
lypinator 0:bb348c97df44 722 * @}
lypinator 0:bb348c97df44 723 */
lypinator 0:bb348c97df44 724
lypinator 0:bb348c97df44 725 /** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset
lypinator 0:bb348c97df44 726 * @brief Force or release APB2 peripheral reset.
lypinator 0:bb348c97df44 727 * @{
lypinator 0:bb348c97df44 728 */
lypinator 0:bb348c97df44 729 #define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU)
lypinator 0:bb348c97df44 730 #define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST))
lypinator 0:bb348c97df44 731 #define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
lypinator 0:bb348c97df44 732 #define __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST))
lypinator 0:bb348c97df44 733 #define __HAL_RCC_ADC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADCRST))
lypinator 0:bb348c97df44 734 #define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
lypinator 0:bb348c97df44 735 #define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST))
lypinator 0:bb348c97df44 736 #define __HAL_RCC_TIM9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST))
lypinator 0:bb348c97df44 737 #define __HAL_RCC_TIM11_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST))
lypinator 0:bb348c97df44 738
lypinator 0:bb348c97df44 739 #define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00U)
lypinator 0:bb348c97df44 740 #define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
lypinator 0:bb348c97df44 741 #define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
lypinator 0:bb348c97df44 742 #define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST))
lypinator 0:bb348c97df44 743 #define __HAL_RCC_ADC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADCRST))
lypinator 0:bb348c97df44 744 #define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
lypinator 0:bb348c97df44 745 #define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
lypinator 0:bb348c97df44 746 #define __HAL_RCC_TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST))
lypinator 0:bb348c97df44 747 #define __HAL_RCC_TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST))
lypinator 0:bb348c97df44 748 /**
lypinator 0:bb348c97df44 749 * @}
lypinator 0:bb348c97df44 750 */
lypinator 0:bb348c97df44 751
lypinator 0:bb348c97df44 752 /** @defgroup RCC_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
lypinator 0:bb348c97df44 753 * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
lypinator 0:bb348c97df44 754 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
lypinator 0:bb348c97df44 755 * power consumption.
lypinator 0:bb348c97df44 756 * @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
lypinator 0:bb348c97df44 757 * @note By default, all peripheral clocks are enabled during SLEEP mode.
lypinator 0:bb348c97df44 758 * @{
lypinator 0:bb348c97df44 759 */
lypinator 0:bb348c97df44 760 #define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOALPEN))
lypinator 0:bb348c97df44 761 #define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOBLPEN))
lypinator 0:bb348c97df44 762 #define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOCLPEN))
lypinator 0:bb348c97df44 763 #define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOHLPEN))
lypinator 0:bb348c97df44 764 #define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN))
lypinator 0:bb348c97df44 765 #define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN))
lypinator 0:bb348c97df44 766
lypinator 0:bb348c97df44 767 #define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOALPEN))
lypinator 0:bb348c97df44 768 #define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOBLPEN))
lypinator 0:bb348c97df44 769 #define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOCLPEN))
lypinator 0:bb348c97df44 770 #define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOHLPEN))
lypinator 0:bb348c97df44 771 #define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA1LPEN))
lypinator 0:bb348c97df44 772 #define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2LPEN))
lypinator 0:bb348c97df44 773 /**
lypinator 0:bb348c97df44 774 * @}
lypinator 0:bb348c97df44 775 */
lypinator 0:bb348c97df44 776
lypinator 0:bb348c97df44 777 /** @defgroup RCC_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
lypinator 0:bb348c97df44 778 * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
lypinator 0:bb348c97df44 779 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
lypinator 0:bb348c97df44 780 * power consumption.
lypinator 0:bb348c97df44 781 * @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
lypinator 0:bb348c97df44 782 * @note By default, all peripheral clocks are enabled during SLEEP mode.
lypinator 0:bb348c97df44 783 * @{
lypinator 0:bb348c97df44 784 */
lypinator 0:bb348c97df44 785 #define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM5LPEN))
lypinator 0:bb348c97df44 786 #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_WWDGLPEN))
lypinator 0:bb348c97df44 787 #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI2LPEN))
lypinator 0:bb348c97df44 788 #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART2LPEN))
lypinator 0:bb348c97df44 789 #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C1LPEN))
lypinator 0:bb348c97df44 790 #define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C2LPEN))
lypinator 0:bb348c97df44 791 #define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_PWRLPEN))
lypinator 0:bb348c97df44 792
lypinator 0:bb348c97df44 793 #define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN))
lypinator 0:bb348c97df44 794 #define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN))
lypinator 0:bb348c97df44 795 #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN))
lypinator 0:bb348c97df44 796 #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN))
lypinator 0:bb348c97df44 797 #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN))
lypinator 0:bb348c97df44 798 #define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN))
lypinator 0:bb348c97df44 799 #define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN))
lypinator 0:bb348c97df44 800 /**
lypinator 0:bb348c97df44 801 * @}
lypinator 0:bb348c97df44 802 */
lypinator 0:bb348c97df44 803
lypinator 0:bb348c97df44 804 /** @defgroup RCC_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
lypinator 0:bb348c97df44 805 * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
lypinator 0:bb348c97df44 806 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
lypinator 0:bb348c97df44 807 * power consumption.
lypinator 0:bb348c97df44 808 * @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
lypinator 0:bb348c97df44 809 * @note By default, all peripheral clocks are enabled during SLEEP mode.
lypinator 0:bb348c97df44 810 * @{
lypinator 0:bb348c97df44 811 */
lypinator 0:bb348c97df44 812 #define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM1LPEN))
lypinator 0:bb348c97df44 813 #define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART1LPEN))
lypinator 0:bb348c97df44 814 #define __HAL_RCC_USART6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART6LPEN))
lypinator 0:bb348c97df44 815 #define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC1LPEN))
lypinator 0:bb348c97df44 816 #define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI1LPEN))
lypinator 0:bb348c97df44 817 #define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SYSCFGLPEN))
lypinator 0:bb348c97df44 818 #define __HAL_RCC_TIM9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM9LPEN))
lypinator 0:bb348c97df44 819 #define __HAL_RCC_TIM11_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM11LPEN))
lypinator 0:bb348c97df44 820
lypinator 0:bb348c97df44 821 #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM1LPEN))
lypinator 0:bb348c97df44 822 #define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN))
lypinator 0:bb348c97df44 823 #define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART6LPEN))
lypinator 0:bb348c97df44 824 #define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN))
lypinator 0:bb348c97df44 825 #define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN))
lypinator 0:bb348c97df44 826 #define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN))
lypinator 0:bb348c97df44 827 #define __HAL_RCC_TIM9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN))
lypinator 0:bb348c97df44 828 #define __HAL_RCC_TIM11_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN))
lypinator 0:bb348c97df44 829 /**
lypinator 0:bb348c97df44 830 * @}
lypinator 0:bb348c97df44 831 */
lypinator 0:bb348c97df44 832
lypinator 0:bb348c97df44 833 /** @defgroup RCC_HSI_Configuration HSI Configuration
lypinator 0:bb348c97df44 834 * @{
lypinator 0:bb348c97df44 835 */
lypinator 0:bb348c97df44 836
lypinator 0:bb348c97df44 837 /** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
lypinator 0:bb348c97df44 838 * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
lypinator 0:bb348c97df44 839 * It is used (enabled by hardware) as system clock source after startup
lypinator 0:bb348c97df44 840 * from Reset, wake-up from STOP and STANDBY mode, or in case of failure
lypinator 0:bb348c97df44 841 * of the HSE used directly or indirectly as system clock (if the Clock
lypinator 0:bb348c97df44 842 * Security System CSS is enabled).
lypinator 0:bb348c97df44 843 * @note HSI can not be stopped if it is used as system clock source. In this case,
lypinator 0:bb348c97df44 844 * you have to select another source of the system clock then stop the HSI.
lypinator 0:bb348c97df44 845 * @note After enabling the HSI, the application software should wait on HSIRDY
lypinator 0:bb348c97df44 846 * flag to be set indicating that HSI clock is stable and can be used as
lypinator 0:bb348c97df44 847 * system clock source.
lypinator 0:bb348c97df44 848 * This parameter can be: ENABLE or DISABLE.
lypinator 0:bb348c97df44 849 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
lypinator 0:bb348c97df44 850 * clock cycles.
lypinator 0:bb348c97df44 851 */
lypinator 0:bb348c97df44 852 #define __HAL_RCC_HSI_ENABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = ENABLE)
lypinator 0:bb348c97df44 853 #define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = DISABLE)
lypinator 0:bb348c97df44 854
lypinator 0:bb348c97df44 855 /** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
lypinator 0:bb348c97df44 856 * @note The calibration is used to compensate for the variations in voltage
lypinator 0:bb348c97df44 857 * and temperature that influence the frequency of the internal HSI RC.
lypinator 0:bb348c97df44 858 * @param __HSICalibrationValue__ specifies the calibration trimming value.
lypinator 0:bb348c97df44 859 * (default is RCC_HSICALIBRATION_DEFAULT).
lypinator 0:bb348c97df44 860 * This parameter must be a number between 0 and 0x1F.
lypinator 0:bb348c97df44 861 */
lypinator 0:bb348c97df44 862 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) (MODIFY_REG(RCC->CR,\
lypinator 0:bb348c97df44 863 RCC_CR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << RCC_CR_HSITRIM_Pos))
lypinator 0:bb348c97df44 864 /**
lypinator 0:bb348c97df44 865 * @}
lypinator 0:bb348c97df44 866 */
lypinator 0:bb348c97df44 867
lypinator 0:bb348c97df44 868 /** @defgroup RCC_LSI_Configuration LSI Configuration
lypinator 0:bb348c97df44 869 * @{
lypinator 0:bb348c97df44 870 */
lypinator 0:bb348c97df44 871
lypinator 0:bb348c97df44 872 /** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI).
lypinator 0:bb348c97df44 873 * @note After enabling the LSI, the application software should wait on
lypinator 0:bb348c97df44 874 * LSIRDY flag to be set indicating that LSI clock is stable and can
lypinator 0:bb348c97df44 875 * be used to clock the IWDG and/or the RTC.
lypinator 0:bb348c97df44 876 * @note LSI can not be disabled if the IWDG is running.
lypinator 0:bb348c97df44 877 * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
lypinator 0:bb348c97df44 878 * clock cycles.
lypinator 0:bb348c97df44 879 */
lypinator 0:bb348c97df44 880 #define __HAL_RCC_LSI_ENABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = ENABLE)
lypinator 0:bb348c97df44 881 #define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = DISABLE)
lypinator 0:bb348c97df44 882 /**
lypinator 0:bb348c97df44 883 * @}
lypinator 0:bb348c97df44 884 */
lypinator 0:bb348c97df44 885
lypinator 0:bb348c97df44 886 /** @defgroup RCC_HSE_Configuration HSE Configuration
lypinator 0:bb348c97df44 887 * @{
lypinator 0:bb348c97df44 888 */
lypinator 0:bb348c97df44 889
lypinator 0:bb348c97df44 890 /**
lypinator 0:bb348c97df44 891 * @brief Macro to configure the External High Speed oscillator (HSE).
lypinator 0:bb348c97df44 892 * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not supported by this macro.
lypinator 0:bb348c97df44 893 * User should request a transition to HSE Off first and then HSE On or HSE Bypass.
lypinator 0:bb348c97df44 894 * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
lypinator 0:bb348c97df44 895 * software should wait on HSERDY flag to be set indicating that HSE clock
lypinator 0:bb348c97df44 896 * is stable and can be used to clock the PLL and/or system clock.
lypinator 0:bb348c97df44 897 * @note HSE state can not be changed if it is used directly or through the
lypinator 0:bb348c97df44 898 * PLL as system clock. In this case, you have to select another source
lypinator 0:bb348c97df44 899 * of the system clock then change the HSE state (ex. disable it).
lypinator 0:bb348c97df44 900 * @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
lypinator 0:bb348c97df44 901 * @note This function reset the CSSON bit, so if the clock security system(CSS)
lypinator 0:bb348c97df44 902 * was previously enabled you have to enable it again after calling this
lypinator 0:bb348c97df44 903 * function.
lypinator 0:bb348c97df44 904 * @param __STATE__ specifies the new state of the HSE.
lypinator 0:bb348c97df44 905 * This parameter can be one of the following values:
lypinator 0:bb348c97df44 906 * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
lypinator 0:bb348c97df44 907 * 6 HSE oscillator clock cycles.
lypinator 0:bb348c97df44 908 * @arg RCC_HSE_ON: turn ON the HSE oscillator.
lypinator 0:bb348c97df44 909 * @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock.
lypinator 0:bb348c97df44 910 */
lypinator 0:bb348c97df44 911 #define __HAL_RCC_HSE_CONFIG(__STATE__) \
lypinator 0:bb348c97df44 912 do { \
lypinator 0:bb348c97df44 913 if ((__STATE__) == RCC_HSE_ON) \
lypinator 0:bb348c97df44 914 { \
lypinator 0:bb348c97df44 915 SET_BIT(RCC->CR, RCC_CR_HSEON); \
lypinator 0:bb348c97df44 916 } \
lypinator 0:bb348c97df44 917 else if ((__STATE__) == RCC_HSE_BYPASS) \
lypinator 0:bb348c97df44 918 { \
lypinator 0:bb348c97df44 919 SET_BIT(RCC->CR, RCC_CR_HSEBYP); \
lypinator 0:bb348c97df44 920 SET_BIT(RCC->CR, RCC_CR_HSEON); \
lypinator 0:bb348c97df44 921 } \
lypinator 0:bb348c97df44 922 else \
lypinator 0:bb348c97df44 923 { \
lypinator 0:bb348c97df44 924 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
lypinator 0:bb348c97df44 925 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
lypinator 0:bb348c97df44 926 } \
lypinator 0:bb348c97df44 927 } while(0U)
lypinator 0:bb348c97df44 928 /**
lypinator 0:bb348c97df44 929 * @}
lypinator 0:bb348c97df44 930 */
lypinator 0:bb348c97df44 931
lypinator 0:bb348c97df44 932 /** @defgroup RCC_LSE_Configuration LSE Configuration
lypinator 0:bb348c97df44 933 * @{
lypinator 0:bb348c97df44 934 */
lypinator 0:bb348c97df44 935
lypinator 0:bb348c97df44 936 /**
lypinator 0:bb348c97df44 937 * @brief Macro to configure the External Low Speed oscillator (LSE).
lypinator 0:bb348c97df44 938 * @note Transition LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.
lypinator 0:bb348c97df44 939 * User should request a transition to LSE Off first and then LSE On or LSE Bypass.
lypinator 0:bb348c97df44 940 * @note As the LSE is in the Backup domain and write access is denied to
lypinator 0:bb348c97df44 941 * this domain after reset, you have to enable write access using
lypinator 0:bb348c97df44 942 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE
lypinator 0:bb348c97df44 943 * (to be done once after reset).
lypinator 0:bb348c97df44 944 * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
lypinator 0:bb348c97df44 945 * software should wait on LSERDY flag to be set indicating that LSE clock
lypinator 0:bb348c97df44 946 * is stable and can be used to clock the RTC.
lypinator 0:bb348c97df44 947 * @param __STATE__ specifies the new state of the LSE.
lypinator 0:bb348c97df44 948 * This parameter can be one of the following values:
lypinator 0:bb348c97df44 949 * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
lypinator 0:bb348c97df44 950 * 6 LSE oscillator clock cycles.
lypinator 0:bb348c97df44 951 * @arg RCC_LSE_ON: turn ON the LSE oscillator.
lypinator 0:bb348c97df44 952 * @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock.
lypinator 0:bb348c97df44 953 */
lypinator 0:bb348c97df44 954 #define __HAL_RCC_LSE_CONFIG(__STATE__) \
lypinator 0:bb348c97df44 955 do { \
lypinator 0:bb348c97df44 956 if((__STATE__) == RCC_LSE_ON) \
lypinator 0:bb348c97df44 957 { \
lypinator 0:bb348c97df44 958 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
lypinator 0:bb348c97df44 959 } \
lypinator 0:bb348c97df44 960 else if((__STATE__) == RCC_LSE_BYPASS) \
lypinator 0:bb348c97df44 961 { \
lypinator 0:bb348c97df44 962 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
lypinator 0:bb348c97df44 963 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
lypinator 0:bb348c97df44 964 } \
lypinator 0:bb348c97df44 965 else \
lypinator 0:bb348c97df44 966 { \
lypinator 0:bb348c97df44 967 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
lypinator 0:bb348c97df44 968 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
lypinator 0:bb348c97df44 969 } \
lypinator 0:bb348c97df44 970 } while(0U)
lypinator 0:bb348c97df44 971 /**
lypinator 0:bb348c97df44 972 * @}
lypinator 0:bb348c97df44 973 */
lypinator 0:bb348c97df44 974
lypinator 0:bb348c97df44 975 /** @defgroup RCC_Internal_RTC_Clock_Configuration RTC Clock Configuration
lypinator 0:bb348c97df44 976 * @{
lypinator 0:bb348c97df44 977 */
lypinator 0:bb348c97df44 978
lypinator 0:bb348c97df44 979 /** @brief Macros to enable or disable the RTC clock.
lypinator 0:bb348c97df44 980 * @note These macros must be used only after the RTC clock source was selected.
lypinator 0:bb348c97df44 981 */
lypinator 0:bb348c97df44 982 #define __HAL_RCC_RTC_ENABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = ENABLE)
lypinator 0:bb348c97df44 983 #define __HAL_RCC_RTC_DISABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = DISABLE)
lypinator 0:bb348c97df44 984
lypinator 0:bb348c97df44 985 /** @brief Macros to configure the RTC clock (RTCCLK).
lypinator 0:bb348c97df44 986 * @note As the RTC clock configuration bits are in the Backup domain and write
lypinator 0:bb348c97df44 987 * access is denied to this domain after reset, you have to enable write
lypinator 0:bb348c97df44 988 * access using the Power Backup Access macro before to configure
lypinator 0:bb348c97df44 989 * the RTC clock source (to be done once after reset).
lypinator 0:bb348c97df44 990 * @note Once the RTC clock is configured it can't be changed unless the
lypinator 0:bb348c97df44 991 * Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by
lypinator 0:bb348c97df44 992 * a Power On Reset (POR).
lypinator 0:bb348c97df44 993 * @param __RTCCLKSource__ specifies the RTC clock source.
lypinator 0:bb348c97df44 994 * This parameter can be one of the following values:
lypinator 0:bb348c97df44 995 @arg @ref RCC_RTCCLKSOURCE_NO_CLK: No clock selected as RTC clock.
lypinator 0:bb348c97df44 996 * @arg @ref RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock.
lypinator 0:bb348c97df44 997 * @arg @ref RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock.
lypinator 0:bb348c97df44 998 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX: HSE clock divided by x selected
lypinator 0:bb348c97df44 999 * as RTC clock, where x:[2,31]
lypinator 0:bb348c97df44 1000 * @note If the LSE or LSI is used as RTC clock source, the RTC continues to
lypinator 0:bb348c97df44 1001 * work in STOP and STANDBY modes, and can be used as wake-up source.
lypinator 0:bb348c97df44 1002 * However, when the HSE clock is used as RTC clock source, the RTC
lypinator 0:bb348c97df44 1003 * cannot be used in STOP and STANDBY modes.
lypinator 0:bb348c97df44 1004 * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
lypinator 0:bb348c97df44 1005 * RTC clock source).
lypinator 0:bb348c97df44 1006 */
lypinator 0:bb348c97df44 1007 #define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ? \
lypinator 0:bb348c97df44 1008 MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, ((__RTCCLKSource__) & 0xFFFFCFFU)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE)
lypinator 0:bb348c97df44 1009
lypinator 0:bb348c97df44 1010 #define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__); \
lypinator 0:bb348c97df44 1011 RCC->BDCR |= ((__RTCCLKSource__) & 0x00000FFFU); \
lypinator 0:bb348c97df44 1012 } while(0U)
lypinator 0:bb348c97df44 1013
lypinator 0:bb348c97df44 1014 /** @brief Macro to get the RTC clock source.
lypinator 0:bb348c97df44 1015 * @retval The clock source can be one of the following values:
lypinator 0:bb348c97df44 1016 * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock
lypinator 0:bb348c97df44 1017 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock
lypinator 0:bb348c97df44 1018 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock
lypinator 0:bb348c97df44 1019 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX HSE divided by X selected as RTC clock (X can be retrieved thanks to @ref __HAL_RCC_GET_RTC_HSE_PRESCALER()
lypinator 0:bb348c97df44 1020 */
lypinator 0:bb348c97df44 1021 #define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))
lypinator 0:bb348c97df44 1022
lypinator 0:bb348c97df44 1023 /**
lypinator 0:bb348c97df44 1024 * @brief Get the RTC and HSE clock divider (RTCPRE).
lypinator 0:bb348c97df44 1025 * @retval Returned value can be one of the following values:
lypinator 0:bb348c97df44 1026 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX: HSE clock divided by x selected
lypinator 0:bb348c97df44 1027 * as RTC clock, where x:[2,31]
lypinator 0:bb348c97df44 1028 */
lypinator 0:bb348c97df44 1029 #define __HAL_RCC_GET_RTC_HSE_PRESCALER() (READ_BIT(RCC->CFGR, RCC_CFGR_RTCPRE) | RCC_BDCR_RTCSEL)
lypinator 0:bb348c97df44 1030
lypinator 0:bb348c97df44 1031 /** @brief Macros to force or release the Backup domain reset.
lypinator 0:bb348c97df44 1032 * @note This function resets the RTC peripheral (including the backup registers)
lypinator 0:bb348c97df44 1033 * and the RTC clock source selection in RCC_CSR register.
lypinator 0:bb348c97df44 1034 * @note The BKPSRAM is not affected by this reset.
lypinator 0:bb348c97df44 1035 */
lypinator 0:bb348c97df44 1036 #define __HAL_RCC_BACKUPRESET_FORCE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = ENABLE)
lypinator 0:bb348c97df44 1037 #define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = DISABLE)
lypinator 0:bb348c97df44 1038 /**
lypinator 0:bb348c97df44 1039 * @}
lypinator 0:bb348c97df44 1040 */
lypinator 0:bb348c97df44 1041
lypinator 0:bb348c97df44 1042 /** @defgroup RCC_PLL_Configuration PLL Configuration
lypinator 0:bb348c97df44 1043 * @{
lypinator 0:bb348c97df44 1044 */
lypinator 0:bb348c97df44 1045
lypinator 0:bb348c97df44 1046 /** @brief Macros to enable or disable the main PLL.
lypinator 0:bb348c97df44 1047 * @note After enabling the main PLL, the application software should wait on
lypinator 0:bb348c97df44 1048 * PLLRDY flag to be set indicating that PLL clock is stable and can
lypinator 0:bb348c97df44 1049 * be used as system clock source.
lypinator 0:bb348c97df44 1050 * @note The main PLL can not be disabled if it is used as system clock source
lypinator 0:bb348c97df44 1051 * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
lypinator 0:bb348c97df44 1052 */
lypinator 0:bb348c97df44 1053 #define __HAL_RCC_PLL_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE)
lypinator 0:bb348c97df44 1054 #define __HAL_RCC_PLL_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = DISABLE)
lypinator 0:bb348c97df44 1055
lypinator 0:bb348c97df44 1056 /** @brief Macro to configure the PLL clock source.
lypinator 0:bb348c97df44 1057 * @note This function must be used only when the main PLL is disabled.
lypinator 0:bb348c97df44 1058 * @param __PLLSOURCE__ specifies the PLL entry clock source.
lypinator 0:bb348c97df44 1059 * This parameter can be one of the following values:
lypinator 0:bb348c97df44 1060 * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
lypinator 0:bb348c97df44 1061 * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
lypinator 0:bb348c97df44 1062 *
lypinator 0:bb348c97df44 1063 */
lypinator 0:bb348c97df44 1064 #define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))
lypinator 0:bb348c97df44 1065
lypinator 0:bb348c97df44 1066 /** @brief Macro to configure the PLL multiplication factor.
lypinator 0:bb348c97df44 1067 * @note This function must be used only when the main PLL is disabled.
lypinator 0:bb348c97df44 1068 * @param __PLLM__ specifies the division factor for PLL VCO input clock
lypinator 0:bb348c97df44 1069 * This parameter must be a number between Min_Data = 2 and Max_Data = 63.
lypinator 0:bb348c97df44 1070 * @note You have to set the PLLM parameter correctly to ensure that the VCO input
lypinator 0:bb348c97df44 1071 * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
lypinator 0:bb348c97df44 1072 * of 2 MHz to limit PLL jitter.
lypinator 0:bb348c97df44 1073 *
lypinator 0:bb348c97df44 1074 */
lypinator 0:bb348c97df44 1075 #define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__))
lypinator 0:bb348c97df44 1076 /**
lypinator 0:bb348c97df44 1077 * @}
lypinator 0:bb348c97df44 1078 */
lypinator 0:bb348c97df44 1079
lypinator 0:bb348c97df44 1080 /** @defgroup RCC_Get_Clock_source Get Clock source
lypinator 0:bb348c97df44 1081 * @{
lypinator 0:bb348c97df44 1082 */
lypinator 0:bb348c97df44 1083 /**
lypinator 0:bb348c97df44 1084 * @brief Macro to configure the system clock source.
lypinator 0:bb348c97df44 1085 * @param __RCC_SYSCLKSOURCE__ specifies the system clock source.
lypinator 0:bb348c97df44 1086 * This parameter can be one of the following values:
lypinator 0:bb348c97df44 1087 * - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source.
lypinator 0:bb348c97df44 1088 * - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source.
lypinator 0:bb348c97df44 1089 * - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source.
lypinator 0:bb348c97df44 1090 * - RCC_SYSCLKSOURCE_PLLRCLK: PLLR output is used as system clock source. This
lypinator 0:bb348c97df44 1091 * parameter is available only for STM32F446xx devices.
lypinator 0:bb348c97df44 1092 */
lypinator 0:bb348c97df44 1093 #define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__))
lypinator 0:bb348c97df44 1094
lypinator 0:bb348c97df44 1095 /** @brief Macro to get the clock source used as system clock.
lypinator 0:bb348c97df44 1096 * @retval The clock source used as system clock. The returned value can be one
lypinator 0:bb348c97df44 1097 * of the following:
lypinator 0:bb348c97df44 1098 * - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock.
lypinator 0:bb348c97df44 1099 * - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock.
lypinator 0:bb348c97df44 1100 * - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock.
lypinator 0:bb348c97df44 1101 * - RCC_SYSCLKSOURCE_STATUS_PLLRCLK: PLLR used as system clock. This parameter
lypinator 0:bb348c97df44 1102 * is available only for STM32F446xx devices.
lypinator 0:bb348c97df44 1103 */
lypinator 0:bb348c97df44 1104 #define __HAL_RCC_GET_SYSCLK_SOURCE() (RCC->CFGR & RCC_CFGR_SWS)
lypinator 0:bb348c97df44 1105
lypinator 0:bb348c97df44 1106 /** @brief Macro to get the oscillator used as PLL clock source.
lypinator 0:bb348c97df44 1107 * @retval The oscillator used as PLL clock source. The returned value can be one
lypinator 0:bb348c97df44 1108 * of the following:
lypinator 0:bb348c97df44 1109 * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
lypinator 0:bb348c97df44 1110 * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
lypinator 0:bb348c97df44 1111 */
lypinator 0:bb348c97df44 1112 #define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC))
lypinator 0:bb348c97df44 1113 /**
lypinator 0:bb348c97df44 1114 * @}
lypinator 0:bb348c97df44 1115 */
lypinator 0:bb348c97df44 1116
lypinator 0:bb348c97df44 1117 /** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config
lypinator 0:bb348c97df44 1118 * @{
lypinator 0:bb348c97df44 1119 */
lypinator 0:bb348c97df44 1120
lypinator 0:bb348c97df44 1121 /** @brief Macro to configure the MCO1 clock.
lypinator 0:bb348c97df44 1122 * @param __MCOCLKSOURCE__ specifies the MCO clock source.
lypinator 0:bb348c97df44 1123 * This parameter can be one of the following values:
lypinator 0:bb348c97df44 1124 * @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source
lypinator 0:bb348c97df44 1125 * @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source
lypinator 0:bb348c97df44 1126 * @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source
lypinator 0:bb348c97df44 1127 * @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source
lypinator 0:bb348c97df44 1128 * @param __MCODIV__ specifies the MCO clock prescaler.
lypinator 0:bb348c97df44 1129 * This parameter can be one of the following values:
lypinator 0:bb348c97df44 1130 * @arg RCC_MCODIV_1: no division applied to MCOx clock
lypinator 0:bb348c97df44 1131 * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
lypinator 0:bb348c97df44 1132 * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
lypinator 0:bb348c97df44 1133 * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
lypinator 0:bb348c97df44 1134 * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
lypinator 0:bb348c97df44 1135 */
lypinator 0:bb348c97df44 1136 #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
lypinator 0:bb348c97df44 1137 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))
lypinator 0:bb348c97df44 1138
lypinator 0:bb348c97df44 1139 /** @brief Macro to configure the MCO2 clock.
lypinator 0:bb348c97df44 1140 * @param __MCOCLKSOURCE__ specifies the MCO clock source.
lypinator 0:bb348c97df44 1141 * This parameter can be one of the following values:
lypinator 0:bb348c97df44 1142 * @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source
lypinator 0:bb348c97df44 1143 * @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source, available for all STM32F4 devices except STM32F410xx
lypinator 0:bb348c97df44 1144 * @arg RCC_MCO2SOURCE_I2SCLK: I2SCLK clock selected as MCO2 source, available only for STM32F410Rx devices
lypinator 0:bb348c97df44 1145 * @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source
lypinator 0:bb348c97df44 1146 * @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source
lypinator 0:bb348c97df44 1147 * @param __MCODIV__ specifies the MCO clock prescaler.
lypinator 0:bb348c97df44 1148 * This parameter can be one of the following values:
lypinator 0:bb348c97df44 1149 * @arg RCC_MCODIV_1: no division applied to MCOx clock
lypinator 0:bb348c97df44 1150 * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
lypinator 0:bb348c97df44 1151 * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
lypinator 0:bb348c97df44 1152 * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
lypinator 0:bb348c97df44 1153 * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
lypinator 0:bb348c97df44 1154 * @note For STM32F410Rx devices, to output I2SCLK clock on MCO2, you should have
lypinator 0:bb348c97df44 1155 * at least one of the SPI clocks enabled (SPI1, SPI2 or SPI5).
lypinator 0:bb348c97df44 1156 */
lypinator 0:bb348c97df44 1157 #define __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
lypinator 0:bb348c97df44 1158 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), ((__MCOCLKSOURCE__) | ((__MCODIV__) << 3U)));
lypinator 0:bb348c97df44 1159 /**
lypinator 0:bb348c97df44 1160 * @}
lypinator 0:bb348c97df44 1161 */
lypinator 0:bb348c97df44 1162
lypinator 0:bb348c97df44 1163 /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
lypinator 0:bb348c97df44 1164 * @brief macros to manage the specified RCC Flags and interrupts.
lypinator 0:bb348c97df44 1165 * @{
lypinator 0:bb348c97df44 1166 */
lypinator 0:bb348c97df44 1167
lypinator 0:bb348c97df44 1168 /** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable
lypinator 0:bb348c97df44 1169 * the selected interrupts).
lypinator 0:bb348c97df44 1170 * @param __INTERRUPT__ specifies the RCC interrupt sources to be enabled.
lypinator 0:bb348c97df44 1171 * This parameter can be any combination of the following values:
lypinator 0:bb348c97df44 1172 * @arg RCC_IT_LSIRDY: LSI ready interrupt.
lypinator 0:bb348c97df44 1173 * @arg RCC_IT_LSERDY: LSE ready interrupt.
lypinator 0:bb348c97df44 1174 * @arg RCC_IT_HSIRDY: HSI ready interrupt.
lypinator 0:bb348c97df44 1175 * @arg RCC_IT_HSERDY: HSE ready interrupt.
lypinator 0:bb348c97df44 1176 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
lypinator 0:bb348c97df44 1177 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
lypinator 0:bb348c97df44 1178 */
lypinator 0:bb348c97df44 1179 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__))
lypinator 0:bb348c97df44 1180
lypinator 0:bb348c97df44 1181 /** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable
lypinator 0:bb348c97df44 1182 * the selected interrupts).
lypinator 0:bb348c97df44 1183 * @param __INTERRUPT__ specifies the RCC interrupt sources to be disabled.
lypinator 0:bb348c97df44 1184 * This parameter can be any combination of the following values:
lypinator 0:bb348c97df44 1185 * @arg RCC_IT_LSIRDY: LSI ready interrupt.
lypinator 0:bb348c97df44 1186 * @arg RCC_IT_LSERDY: LSE ready interrupt.
lypinator 0:bb348c97df44 1187 * @arg RCC_IT_HSIRDY: HSI ready interrupt.
lypinator 0:bb348c97df44 1188 * @arg RCC_IT_HSERDY: HSE ready interrupt.
lypinator 0:bb348c97df44 1189 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
lypinator 0:bb348c97df44 1190 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
lypinator 0:bb348c97df44 1191 */
lypinator 0:bb348c97df44 1192 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__)))
lypinator 0:bb348c97df44 1193
lypinator 0:bb348c97df44 1194 /** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16]
lypinator 0:bb348c97df44 1195 * bits to clear the selected interrupt pending bits.
lypinator 0:bb348c97df44 1196 * @param __INTERRUPT__ specifies the interrupt pending bit to clear.
lypinator 0:bb348c97df44 1197 * This parameter can be any combination of the following values:
lypinator 0:bb348c97df44 1198 * @arg RCC_IT_LSIRDY: LSI ready interrupt.
lypinator 0:bb348c97df44 1199 * @arg RCC_IT_LSERDY: LSE ready interrupt.
lypinator 0:bb348c97df44 1200 * @arg RCC_IT_HSIRDY: HSI ready interrupt.
lypinator 0:bb348c97df44 1201 * @arg RCC_IT_HSERDY: HSE ready interrupt.
lypinator 0:bb348c97df44 1202 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
lypinator 0:bb348c97df44 1203 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
lypinator 0:bb348c97df44 1204 * @arg RCC_IT_CSS: Clock Security System interrupt
lypinator 0:bb348c97df44 1205 */
lypinator 0:bb348c97df44 1206 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))
lypinator 0:bb348c97df44 1207
lypinator 0:bb348c97df44 1208 /** @brief Check the RCC's interrupt has occurred or not.
lypinator 0:bb348c97df44 1209 * @param __INTERRUPT__ specifies the RCC interrupt source to check.
lypinator 0:bb348c97df44 1210 * This parameter can be one of the following values:
lypinator 0:bb348c97df44 1211 * @arg RCC_IT_LSIRDY: LSI ready interrupt.
lypinator 0:bb348c97df44 1212 * @arg RCC_IT_LSERDY: LSE ready interrupt.
lypinator 0:bb348c97df44 1213 * @arg RCC_IT_HSIRDY: HSI ready interrupt.
lypinator 0:bb348c97df44 1214 * @arg RCC_IT_HSERDY: HSE ready interrupt.
lypinator 0:bb348c97df44 1215 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
lypinator 0:bb348c97df44 1216 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
lypinator 0:bb348c97df44 1217 * @arg RCC_IT_CSS: Clock Security System interrupt
lypinator 0:bb348c97df44 1218 * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
lypinator 0:bb348c97df44 1219 */
lypinator 0:bb348c97df44 1220 #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
lypinator 0:bb348c97df44 1221
lypinator 0:bb348c97df44 1222 /** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_PINRST, RCC_FLAG_PORRST,
lypinator 0:bb348c97df44 1223 * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST.
lypinator 0:bb348c97df44 1224 */
lypinator 0:bb348c97df44 1225 #define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF)
lypinator 0:bb348c97df44 1226
lypinator 0:bb348c97df44 1227 /** @brief Check RCC flag is set or not.
lypinator 0:bb348c97df44 1228 * @param __FLAG__ specifies the flag to check.
lypinator 0:bb348c97df44 1229 * This parameter can be one of the following values:
lypinator 0:bb348c97df44 1230 * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready.
lypinator 0:bb348c97df44 1231 * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready.
lypinator 0:bb348c97df44 1232 * @arg RCC_FLAG_PLLRDY: Main PLL clock ready.
lypinator 0:bb348c97df44 1233 * @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready.
lypinator 0:bb348c97df44 1234 * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready.
lypinator 0:bb348c97df44 1235 * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready.
lypinator 0:bb348c97df44 1236 * @arg RCC_FLAG_BORRST: POR/PDR or BOR reset.
lypinator 0:bb348c97df44 1237 * @arg RCC_FLAG_PINRST: Pin reset.
lypinator 0:bb348c97df44 1238 * @arg RCC_FLAG_PORRST: POR/PDR reset.
lypinator 0:bb348c97df44 1239 * @arg RCC_FLAG_SFTRST: Software reset.
lypinator 0:bb348c97df44 1240 * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset.
lypinator 0:bb348c97df44 1241 * @arg RCC_FLAG_WWDGRST: Window Watchdog reset.
lypinator 0:bb348c97df44 1242 * @arg RCC_FLAG_LPWRRST: Low Power reset.
lypinator 0:bb348c97df44 1243 * @retval The new state of __FLAG__ (TRUE or FALSE).
lypinator 0:bb348c97df44 1244 */
lypinator 0:bb348c97df44 1245 #define RCC_FLAG_MASK ((uint8_t)0x1FU)
lypinator 0:bb348c97df44 1246 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR :((((__FLAG__) >> 5U) == 3U)? RCC->CSR :RCC->CIR))) & (1U << ((__FLAG__) & RCC_FLAG_MASK)))!= 0U)? 1U : 0U)
lypinator 0:bb348c97df44 1247
lypinator 0:bb348c97df44 1248 /**
lypinator 0:bb348c97df44 1249 * @}
lypinator 0:bb348c97df44 1250 */
lypinator 0:bb348c97df44 1251
lypinator 0:bb348c97df44 1252 /**
lypinator 0:bb348c97df44 1253 * @}
lypinator 0:bb348c97df44 1254 */
lypinator 0:bb348c97df44 1255
lypinator 0:bb348c97df44 1256 /* Exported functions --------------------------------------------------------*/
lypinator 0:bb348c97df44 1257 /** @addtogroup RCC_Exported_Functions
lypinator 0:bb348c97df44 1258 * @{
lypinator 0:bb348c97df44 1259 */
lypinator 0:bb348c97df44 1260
lypinator 0:bb348c97df44 1261 /** @addtogroup RCC_Exported_Functions_Group1
lypinator 0:bb348c97df44 1262 * @{
lypinator 0:bb348c97df44 1263 */
lypinator 0:bb348c97df44 1264 /* Initialization and de-initialization functions ******************************/
lypinator 0:bb348c97df44 1265 HAL_StatusTypeDef HAL_RCC_DeInit(void);
lypinator 0:bb348c97df44 1266 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
lypinator 0:bb348c97df44 1267 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
lypinator 0:bb348c97df44 1268 /**
lypinator 0:bb348c97df44 1269 * @}
lypinator 0:bb348c97df44 1270 */
lypinator 0:bb348c97df44 1271
lypinator 0:bb348c97df44 1272 /** @addtogroup RCC_Exported_Functions_Group2
lypinator 0:bb348c97df44 1273 * @{
lypinator 0:bb348c97df44 1274 */
lypinator 0:bb348c97df44 1275 /* Peripheral Control functions ************************************************/
lypinator 0:bb348c97df44 1276 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
lypinator 0:bb348c97df44 1277 void HAL_RCC_EnableCSS(void);
lypinator 0:bb348c97df44 1278 void HAL_RCC_DisableCSS(void);
lypinator 0:bb348c97df44 1279 uint32_t HAL_RCC_GetSysClockFreq(void);
lypinator 0:bb348c97df44 1280 uint32_t HAL_RCC_GetHCLKFreq(void);
lypinator 0:bb348c97df44 1281 uint32_t HAL_RCC_GetPCLK1Freq(void);
lypinator 0:bb348c97df44 1282 uint32_t HAL_RCC_GetPCLK2Freq(void);
lypinator 0:bb348c97df44 1283 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
lypinator 0:bb348c97df44 1284 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
lypinator 0:bb348c97df44 1285
lypinator 0:bb348c97df44 1286 /* CSS NMI IRQ handler */
lypinator 0:bb348c97df44 1287 void HAL_RCC_NMI_IRQHandler(void);
lypinator 0:bb348c97df44 1288
lypinator 0:bb348c97df44 1289 /* User Callbacks in non blocking mode (IT mode) */
lypinator 0:bb348c97df44 1290 void HAL_RCC_CSSCallback(void);
lypinator 0:bb348c97df44 1291
lypinator 0:bb348c97df44 1292 /**
lypinator 0:bb348c97df44 1293 * @}
lypinator 0:bb348c97df44 1294 */
lypinator 0:bb348c97df44 1295
lypinator 0:bb348c97df44 1296 /**
lypinator 0:bb348c97df44 1297 * @}
lypinator 0:bb348c97df44 1298 */
lypinator 0:bb348c97df44 1299
lypinator 0:bb348c97df44 1300 /* Private types -------------------------------------------------------------*/
lypinator 0:bb348c97df44 1301 /* Private variables ---------------------------------------------------------*/
lypinator 0:bb348c97df44 1302 /* Private constants ---------------------------------------------------------*/
lypinator 0:bb348c97df44 1303 /** @defgroup RCC_Private_Constants RCC Private Constants
lypinator 0:bb348c97df44 1304 * @{
lypinator 0:bb348c97df44 1305 */
lypinator 0:bb348c97df44 1306
lypinator 0:bb348c97df44 1307 /** @defgroup RCC_BitAddress_AliasRegion RCC BitAddress AliasRegion
lypinator 0:bb348c97df44 1308 * @brief RCC registers bit address in the alias region
lypinator 0:bb348c97df44 1309 * @{
lypinator 0:bb348c97df44 1310 */
lypinator 0:bb348c97df44 1311 #define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
lypinator 0:bb348c97df44 1312 /* --- CR Register --- */
lypinator 0:bb348c97df44 1313 /* Alias word address of HSION bit */
lypinator 0:bb348c97df44 1314 #define RCC_CR_OFFSET (RCC_OFFSET + 0x00U)
lypinator 0:bb348c97df44 1315 #define RCC_HSION_BIT_NUMBER 0x00U
lypinator 0:bb348c97df44 1316 #define RCC_CR_HSION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_HSION_BIT_NUMBER * 4U))
lypinator 0:bb348c97df44 1317 /* Alias word address of CSSON bit */
lypinator 0:bb348c97df44 1318 #define RCC_CSSON_BIT_NUMBER 0x13U
lypinator 0:bb348c97df44 1319 #define RCC_CR_CSSON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_CSSON_BIT_NUMBER * 4U))
lypinator 0:bb348c97df44 1320 /* Alias word address of PLLON bit */
lypinator 0:bb348c97df44 1321 #define RCC_PLLON_BIT_NUMBER 0x18U
lypinator 0:bb348c97df44 1322 #define RCC_CR_PLLON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_PLLON_BIT_NUMBER * 4U))
lypinator 0:bb348c97df44 1323
lypinator 0:bb348c97df44 1324 /* --- BDCR Register --- */
lypinator 0:bb348c97df44 1325 /* Alias word address of RTCEN bit */
lypinator 0:bb348c97df44 1326 #define RCC_BDCR_OFFSET (RCC_OFFSET + 0x70U)
lypinator 0:bb348c97df44 1327 #define RCC_RTCEN_BIT_NUMBER 0x0FU
lypinator 0:bb348c97df44 1328 #define RCC_BDCR_RTCEN_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32U) + (RCC_RTCEN_BIT_NUMBER * 4U))
lypinator 0:bb348c97df44 1329 /* Alias word address of BDRST bit */
lypinator 0:bb348c97df44 1330 #define RCC_BDRST_BIT_NUMBER 0x10U
lypinator 0:bb348c97df44 1331 #define RCC_BDCR_BDRST_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32U) + (RCC_BDRST_BIT_NUMBER * 4U))
lypinator 0:bb348c97df44 1332
lypinator 0:bb348c97df44 1333 /* --- CSR Register --- */
lypinator 0:bb348c97df44 1334 /* Alias word address of LSION bit */
lypinator 0:bb348c97df44 1335 #define RCC_CSR_OFFSET (RCC_OFFSET + 0x74U)
lypinator 0:bb348c97df44 1336 #define RCC_LSION_BIT_NUMBER 0x00U
lypinator 0:bb348c97df44 1337 #define RCC_CSR_LSION_BB (PERIPH_BB_BASE + (RCC_CSR_OFFSET * 32U) + (RCC_LSION_BIT_NUMBER * 4U))
lypinator 0:bb348c97df44 1338
lypinator 0:bb348c97df44 1339 /* CR register byte 3 (Bits[23:16]) base address */
lypinator 0:bb348c97df44 1340 #define RCC_CR_BYTE2_ADDRESS 0x40023802U
lypinator 0:bb348c97df44 1341
lypinator 0:bb348c97df44 1342 /* CIR register byte 2 (Bits[15:8]) base address */
lypinator 0:bb348c97df44 1343 #define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + 0x0CU + 0x01U))
lypinator 0:bb348c97df44 1344
lypinator 0:bb348c97df44 1345 /* CIR register byte 3 (Bits[23:16]) base address */
lypinator 0:bb348c97df44 1346 #define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0CU + 0x02U))
lypinator 0:bb348c97df44 1347
lypinator 0:bb348c97df44 1348 /* BDCR register base address */
lypinator 0:bb348c97df44 1349 #define RCC_BDCR_BYTE0_ADDRESS (PERIPH_BASE + RCC_BDCR_OFFSET)
lypinator 0:bb348c97df44 1350
lypinator 0:bb348c97df44 1351 #define RCC_DBP_TIMEOUT_VALUE 2U
lypinator 0:bb348c97df44 1352 #define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
lypinator 0:bb348c97df44 1353
lypinator 0:bb348c97df44 1354 #define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
lypinator 0:bb348c97df44 1355 #define HSI_TIMEOUT_VALUE 2U /* 2 ms */
lypinator 0:bb348c97df44 1356 #define LSI_TIMEOUT_VALUE 2U /* 2 ms */
lypinator 0:bb348c97df44 1357 #define CLOCKSWITCH_TIMEOUT_VALUE 5000U /* 5 s */
lypinator 0:bb348c97df44 1358
lypinator 0:bb348c97df44 1359 /**
lypinator 0:bb348c97df44 1360 * @}
lypinator 0:bb348c97df44 1361 */
lypinator 0:bb348c97df44 1362
lypinator 0:bb348c97df44 1363 /**
lypinator 0:bb348c97df44 1364 * @}
lypinator 0:bb348c97df44 1365 */
lypinator 0:bb348c97df44 1366
lypinator 0:bb348c97df44 1367 /* Private macros ------------------------------------------------------------*/
lypinator 0:bb348c97df44 1368 /** @defgroup RCC_Private_Macros RCC Private Macros
lypinator 0:bb348c97df44 1369 * @{
lypinator 0:bb348c97df44 1370 */
lypinator 0:bb348c97df44 1371
lypinator 0:bb348c97df44 1372 /** @defgroup RCC_IS_RCC_Definitions RCC Private macros to check input parameters
lypinator 0:bb348c97df44 1373 * @{
lypinator 0:bb348c97df44 1374 */
lypinator 0:bb348c97df44 1375 #define IS_RCC_OSCILLATORTYPE(OSCILLATOR) ((OSCILLATOR) <= 15U)
lypinator 0:bb348c97df44 1376
lypinator 0:bb348c97df44 1377 #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
lypinator 0:bb348c97df44 1378 ((HSE) == RCC_HSE_BYPASS))
lypinator 0:bb348c97df44 1379
lypinator 0:bb348c97df44 1380 #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
lypinator 0:bb348c97df44 1381 ((LSE) == RCC_LSE_BYPASS))
lypinator 0:bb348c97df44 1382
lypinator 0:bb348c97df44 1383 #define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON))
lypinator 0:bb348c97df44 1384
lypinator 0:bb348c97df44 1385 #define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON))
lypinator 0:bb348c97df44 1386
lypinator 0:bb348c97df44 1387 #define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || ((PLL) == RCC_PLL_ON))
lypinator 0:bb348c97df44 1388
lypinator 0:bb348c97df44 1389 #define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \
lypinator 0:bb348c97df44 1390 ((SOURCE) == RCC_PLLSOURCE_HSE))
lypinator 0:bb348c97df44 1391
lypinator 0:bb348c97df44 1392 #define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \
lypinator 0:bb348c97df44 1393 ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \
lypinator 0:bb348c97df44 1394 ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK) || \
lypinator 0:bb348c97df44 1395 ((SOURCE) == RCC_SYSCLKSOURCE_PLLRCLK))
lypinator 0:bb348c97df44 1396
lypinator 0:bb348c97df44 1397 #define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \
lypinator 0:bb348c97df44 1398 ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \
lypinator 0:bb348c97df44 1399 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV2) || \
lypinator 0:bb348c97df44 1400 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV3) || \
lypinator 0:bb348c97df44 1401 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV4) || \
lypinator 0:bb348c97df44 1402 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV5) || \
lypinator 0:bb348c97df44 1403 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV6) || \
lypinator 0:bb348c97df44 1404 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV7) || \
lypinator 0:bb348c97df44 1405 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV8) || \
lypinator 0:bb348c97df44 1406 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV9) || \
lypinator 0:bb348c97df44 1407 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV10) || \
lypinator 0:bb348c97df44 1408 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV11) || \
lypinator 0:bb348c97df44 1409 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV12) || \
lypinator 0:bb348c97df44 1410 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV13) || \
lypinator 0:bb348c97df44 1411 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV14) || \
lypinator 0:bb348c97df44 1412 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV15) || \
lypinator 0:bb348c97df44 1413 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV16) || \
lypinator 0:bb348c97df44 1414 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV17) || \
lypinator 0:bb348c97df44 1415 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV18) || \
lypinator 0:bb348c97df44 1416 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV19) || \
lypinator 0:bb348c97df44 1417 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV20) || \
lypinator 0:bb348c97df44 1418 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV21) || \
lypinator 0:bb348c97df44 1419 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV22) || \
lypinator 0:bb348c97df44 1420 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV23) || \
lypinator 0:bb348c97df44 1421 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV24) || \
lypinator 0:bb348c97df44 1422 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV25) || \
lypinator 0:bb348c97df44 1423 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV26) || \
lypinator 0:bb348c97df44 1424 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV27) || \
lypinator 0:bb348c97df44 1425 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV28) || \
lypinator 0:bb348c97df44 1426 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV29) || \
lypinator 0:bb348c97df44 1427 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV30) || \
lypinator 0:bb348c97df44 1428 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV31))
lypinator 0:bb348c97df44 1429
lypinator 0:bb348c97df44 1430 #define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63U)
lypinator 0:bb348c97df44 1431
lypinator 0:bb348c97df44 1432 #define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2U) || ((VALUE) == 4U) || ((VALUE) == 6U) || ((VALUE) == 8U))
lypinator 0:bb348c97df44 1433
lypinator 0:bb348c97df44 1434 #define IS_RCC_PLLQ_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 15U))
lypinator 0:bb348c97df44 1435
lypinator 0:bb348c97df44 1436 #define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_DIV1) || ((HCLK) == RCC_SYSCLK_DIV2) || \
lypinator 0:bb348c97df44 1437 ((HCLK) == RCC_SYSCLK_DIV4) || ((HCLK) == RCC_SYSCLK_DIV8) || \
lypinator 0:bb348c97df44 1438 ((HCLK) == RCC_SYSCLK_DIV16) || ((HCLK) == RCC_SYSCLK_DIV64) || \
lypinator 0:bb348c97df44 1439 ((HCLK) == RCC_SYSCLK_DIV128) || ((HCLK) == RCC_SYSCLK_DIV256) || \
lypinator 0:bb348c97df44 1440 ((HCLK) == RCC_SYSCLK_DIV512))
lypinator 0:bb348c97df44 1441
lypinator 0:bb348c97df44 1442 #define IS_RCC_CLOCKTYPE(CLK) ((1U <= (CLK)) && ((CLK) <= 15U))
lypinator 0:bb348c97df44 1443
lypinator 0:bb348c97df44 1444 #define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_DIV1) || ((PCLK) == RCC_HCLK_DIV2) || \
lypinator 0:bb348c97df44 1445 ((PCLK) == RCC_HCLK_DIV4) || ((PCLK) == RCC_HCLK_DIV8) || \
lypinator 0:bb348c97df44 1446 ((PCLK) == RCC_HCLK_DIV16))
lypinator 0:bb348c97df44 1447
lypinator 0:bb348c97df44 1448 #define IS_RCC_MCO(MCOx) (((MCOx) == RCC_MCO1) || ((MCOx) == RCC_MCO2))
lypinator 0:bb348c97df44 1449
lypinator 0:bb348c97df44 1450 #define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_LSE) || \
lypinator 0:bb348c97df44 1451 ((SOURCE) == RCC_MCO1SOURCE_HSE) || ((SOURCE) == RCC_MCO1SOURCE_PLLCLK))
lypinator 0:bb348c97df44 1452
lypinator 0:bb348c97df44 1453 #define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || \
lypinator 0:bb348c97df44 1454 ((DIV) == RCC_MCODIV_3) || ((DIV) == RCC_MCODIV_4) || \
lypinator 0:bb348c97df44 1455 ((DIV) == RCC_MCODIV_5))
lypinator 0:bb348c97df44 1456 #define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1FU)
lypinator 0:bb348c97df44 1457
lypinator 0:bb348c97df44 1458 /**
lypinator 0:bb348c97df44 1459 * @}
lypinator 0:bb348c97df44 1460 */
lypinator 0:bb348c97df44 1461
lypinator 0:bb348c97df44 1462 /**
lypinator 0:bb348c97df44 1463 * @}
lypinator 0:bb348c97df44 1464 */
lypinator 0:bb348c97df44 1465
lypinator 0:bb348c97df44 1466 /**
lypinator 0:bb348c97df44 1467 * @}
lypinator 0:bb348c97df44 1468 */
lypinator 0:bb348c97df44 1469
lypinator 0:bb348c97df44 1470 /**
lypinator 0:bb348c97df44 1471 * @}
lypinator 0:bb348c97df44 1472 */
lypinator 0:bb348c97df44 1473
lypinator 0:bb348c97df44 1474 #ifdef __cplusplus
lypinator 0:bb348c97df44 1475 }
lypinator 0:bb348c97df44 1476 #endif
lypinator 0:bb348c97df44 1477
lypinator 0:bb348c97df44 1478 #endif /* __STM32F4xx_HAL_RCC_H */
lypinator 0:bb348c97df44 1479
lypinator 0:bb348c97df44 1480 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/