Thomas Lyp / DevLibMemoryController

Initial commit

Dependencies:   FastPWM

mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_pwr_ex.c@0:bb348c97df44, 2020-09-16 (annotated)

Committer:
lypinator
Date:
Wed Sep 16 01:11:49 2020 +0000
Revision:
0:bb348c97df44
Added PWM

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lypinator 0:bb348c97df44 1 /**
lypinator 0:bb348c97df44 2 ******************************************************************************
lypinator 0:bb348c97df44 3 * @file stm32f4xx_hal_pwr_ex.c
lypinator 0:bb348c97df44 4 * @author MCD Application Team
lypinator 0:bb348c97df44 5 * @brief Extended PWR HAL module driver.
lypinator 0:bb348c97df44 6 * This file provides firmware functions to manage the following
lypinator 0:bb348c97df44 7 * functionalities of PWR extension peripheral:
lypinator 0:bb348c97df44 8 * + Peripheral Extended features functions
lypinator 0:bb348c97df44 9 *
lypinator 0:bb348c97df44 10 ******************************************************************************
lypinator 0:bb348c97df44 11 * @attention
lypinator 0:bb348c97df44 12 *
lypinator 0:bb348c97df44 13 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
lypinator 0:bb348c97df44 14 *
lypinator 0:bb348c97df44 15 * Redistribution and use in source and binary forms, with or without modification,
lypinator 0:bb348c97df44 16 * are permitted provided that the following conditions are met:
lypinator 0:bb348c97df44 17 * 1. Redistributions of source code must retain the above copyright notice,
lypinator 0:bb348c97df44 18 * this list of conditions and the following disclaimer.
lypinator 0:bb348c97df44 19 * 2. Redistributions in binary form must reproduce the above copyright notice,
lypinator 0:bb348c97df44 20 * this list of conditions and the following disclaimer in the documentation
lypinator 0:bb348c97df44 21 * and/or other materials provided with the distribution.
lypinator 0:bb348c97df44 22 * 3. Neither the name of STMicroelectronics nor the names of its contributors
lypinator 0:bb348c97df44 23 * may be used to endorse or promote products derived from this software
lypinator 0:bb348c97df44 24 * without specific prior written permission.
lypinator 0:bb348c97df44 25 *
lypinator 0:bb348c97df44 26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
lypinator 0:bb348c97df44 27 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
lypinator 0:bb348c97df44 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
lypinator 0:bb348c97df44 29 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
lypinator 0:bb348c97df44 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
lypinator 0:bb348c97df44 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
lypinator 0:bb348c97df44 32 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
lypinator 0:bb348c97df44 33 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
lypinator 0:bb348c97df44 34 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
lypinator 0:bb348c97df44 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
lypinator 0:bb348c97df44 36 *
lypinator 0:bb348c97df44 37 ******************************************************************************
lypinator 0:bb348c97df44 38 */
lypinator 0:bb348c97df44 39
lypinator 0:bb348c97df44 40 /* Includes ------------------------------------------------------------------*/
lypinator 0:bb348c97df44 41 #include "stm32f4xx_hal.h"
lypinator 0:bb348c97df44 42
lypinator 0:bb348c97df44 43 /** @addtogroup STM32F4xx_HAL_Driver
lypinator 0:bb348c97df44 44 * @{
lypinator 0:bb348c97df44 45 */
lypinator 0:bb348c97df44 46
lypinator 0:bb348c97df44 47 /** @defgroup PWREx PWREx
lypinator 0:bb348c97df44 48 * @brief PWR HAL module driver
lypinator 0:bb348c97df44 49 * @{
lypinator 0:bb348c97df44 50 */
lypinator 0:bb348c97df44 51
lypinator 0:bb348c97df44 52 #ifdef HAL_PWR_MODULE_ENABLED
lypinator 0:bb348c97df44 53
lypinator 0:bb348c97df44 54 /* Private typedef -----------------------------------------------------------*/
lypinator 0:bb348c97df44 55 /* Private define ------------------------------------------------------------*/
lypinator 0:bb348c97df44 56 /** @addtogroup PWREx_Private_Constants
lypinator 0:bb348c97df44 57 * @{
lypinator 0:bb348c97df44 58 */
lypinator 0:bb348c97df44 59 #define PWR_OVERDRIVE_TIMEOUT_VALUE 1000U
lypinator 0:bb348c97df44 60 #define PWR_UDERDRIVE_TIMEOUT_VALUE 1000U
lypinator 0:bb348c97df44 61 #define PWR_BKPREG_TIMEOUT_VALUE 1000U
lypinator 0:bb348c97df44 62 #define PWR_VOSRDY_TIMEOUT_VALUE 1000U
lypinator 0:bb348c97df44 63 /**
lypinator 0:bb348c97df44 64 * @}
lypinator 0:bb348c97df44 65 */
lypinator 0:bb348c97df44 66
lypinator 0:bb348c97df44 67
lypinator 0:bb348c97df44 68 /* Private macro -------------------------------------------------------------*/
lypinator 0:bb348c97df44 69 /* Private variables ---------------------------------------------------------*/
lypinator 0:bb348c97df44 70 /* Private function prototypes -----------------------------------------------*/
lypinator 0:bb348c97df44 71 /* Private functions ---------------------------------------------------------*/
lypinator 0:bb348c97df44 72 /** @defgroup PWREx_Exported_Functions PWREx Exported Functions
lypinator 0:bb348c97df44 73 * @{
lypinator 0:bb348c97df44 74 */
lypinator 0:bb348c97df44 75
lypinator 0:bb348c97df44 76 /** @defgroup PWREx_Exported_Functions_Group1 Peripheral Extended features functions
lypinator 0:bb348c97df44 77 * @brief Peripheral Extended features functions
lypinator 0:bb348c97df44 78 *
lypinator 0:bb348c97df44 79 @verbatim
lypinator 0:bb348c97df44 80
lypinator 0:bb348c97df44 81 ===============================================================================
lypinator 0:bb348c97df44 82 ##### Peripheral extended features functions #####
lypinator 0:bb348c97df44 83 ===============================================================================
lypinator 0:bb348c97df44 84
lypinator 0:bb348c97df44 85 *** Main and Backup Regulators configuration ***
lypinator 0:bb348c97df44 86 ================================================
lypinator 0:bb348c97df44 87 [..]
lypinator 0:bb348c97df44 88 (+) The backup domain includes 4 Kbytes of backup SRAM accessible only from
lypinator 0:bb348c97df44 89 the CPU, and address in 32-bit, 16-bit or 8-bit mode. Its content is
lypinator 0:bb348c97df44 90 retained even in Standby or VBAT mode when the low power backup regulator
lypinator 0:bb348c97df44 91 is enabled. It can be considered as an internal EEPROM when VBAT is
lypinator 0:bb348c97df44 92 always present. You can use the HAL_PWREx_EnableBkUpReg() function to
lypinator 0:bb348c97df44 93 enable the low power backup regulator.
lypinator 0:bb348c97df44 94
lypinator 0:bb348c97df44 95 (+) When the backup domain is supplied by VDD (analog switch connected to VDD)
lypinator 0:bb348c97df44 96 the backup SRAM is powered from VDD which replaces the VBAT power supply to
lypinator 0:bb348c97df44 97 save battery life.
lypinator 0:bb348c97df44 98
lypinator 0:bb348c97df44 99 (+) The backup SRAM is not mass erased by a tamper event. It is read
lypinator 0:bb348c97df44 100 protected to prevent confidential data, such as cryptographic private
lypinator 0:bb348c97df44 101 key, from being accessed. The backup SRAM can be erased only through
lypinator 0:bb348c97df44 102 the Flash interface when a protection level change from level 1 to
lypinator 0:bb348c97df44 103 level 0 is requested.
lypinator 0:bb348c97df44 104 -@- Refer to the description of Read protection (RDP) in the Flash
lypinator 0:bb348c97df44 105 programming manual.
lypinator 0:bb348c97df44 106
lypinator 0:bb348c97df44 107 (+) The main internal regulator can be configured to have a tradeoff between
lypinator 0:bb348c97df44 108 performance and power consumption when the device does not operate at
lypinator 0:bb348c97df44 109 the maximum frequency. This is done through __HAL_PWR_MAINREGULATORMODE_CONFIG()
lypinator 0:bb348c97df44 110 macro which configure VOS bit in PWR_CR register
lypinator 0:bb348c97df44 111
lypinator 0:bb348c97df44 112 Refer to the product datasheets for more details.
lypinator 0:bb348c97df44 113
lypinator 0:bb348c97df44 114 *** FLASH Power Down configuration ****
lypinator 0:bb348c97df44 115 =======================================
lypinator 0:bb348c97df44 116 [..]
lypinator 0:bb348c97df44 117 (+) By setting the FPDS bit in the PWR_CR register by using the
lypinator 0:bb348c97df44 118 HAL_PWREx_EnableFlashPowerDown() function, the Flash memory also enters power
lypinator 0:bb348c97df44 119 down mode when the device enters Stop mode. When the Flash memory
lypinator 0:bb348c97df44 120 is in power down mode, an additional startup delay is incurred when
lypinator 0:bb348c97df44 121 waking up from Stop mode.
lypinator 0:bb348c97df44 122
lypinator 0:bb348c97df44 123 (+) For STM32F42xxx/43xxx/446xx/469xx/479xx Devices, the scale can be modified only when the PLL
lypinator 0:bb348c97df44 124 is OFF and the HSI or HSE clock source is selected as system clock.
lypinator 0:bb348c97df44 125 The new value programmed is active only when the PLL is ON.
lypinator 0:bb348c97df44 126 When the PLL is OFF, the voltage scale 3 is automatically selected.
lypinator 0:bb348c97df44 127 Refer to the datasheets for more details.
lypinator 0:bb348c97df44 128
lypinator 0:bb348c97df44 129 *** Over-Drive and Under-Drive configuration ****
lypinator 0:bb348c97df44 130 =================================================
lypinator 0:bb348c97df44 131 [..]
lypinator 0:bb348c97df44 132 (+) For STM32F42xxx/43xxx/446xx/469xx/479xx Devices, in Run mode: the main regulator has
lypinator 0:bb348c97df44 133 2 operating modes available:
lypinator 0:bb348c97df44 134 (++) Normal mode: The CPU and core logic operate at maximum frequency at a given
lypinator 0:bb348c97df44 135 voltage scaling (scale 1, scale 2 or scale 3)
lypinator 0:bb348c97df44 136 (++) Over-drive mode: This mode allows the CPU and the core logic to operate at a
lypinator 0:bb348c97df44 137 higher frequency than the normal mode for a given voltage scaling (scale 1,
lypinator 0:bb348c97df44 138 scale 2 or scale 3). This mode is enabled through HAL_PWREx_EnableOverDrive() function and
lypinator 0:bb348c97df44 139 disabled by HAL_PWREx_DisableOverDrive() function, to enter or exit from Over-drive mode please follow
lypinator 0:bb348c97df44 140 the sequence described in Reference manual.
lypinator 0:bb348c97df44 141
lypinator 0:bb348c97df44 142 (+) For STM32F42xxx/43xxx/446xx/469xx/479xx Devices, in Stop mode: the main regulator or low power regulator
lypinator 0:bb348c97df44 143 supplies a low power voltage to the 1.2V domain, thus preserving the content of registers
lypinator 0:bb348c97df44 144 and internal SRAM. 2 operating modes are available:
lypinator 0:bb348c97df44 145 (++) Normal mode: the 1.2V domain is preserved in nominal leakage mode. This mode is only
lypinator 0:bb348c97df44 146 available when the main regulator or the low power regulator is used in Scale 3 or
lypinator 0:bb348c97df44 147 low voltage mode.
lypinator 0:bb348c97df44 148 (++) Under-drive mode: the 1.2V domain is preserved in reduced leakage mode. This mode is only
lypinator 0:bb348c97df44 149 available when the main regulator or the low power regulator is in low voltage mode.
lypinator 0:bb348c97df44 150
lypinator 0:bb348c97df44 151 @endverbatim
lypinator 0:bb348c97df44 152 * @{
lypinator 0:bb348c97df44 153 */
lypinator 0:bb348c97df44 154
lypinator 0:bb348c97df44 155 /**
lypinator 0:bb348c97df44 156 * @brief Enables the Backup Regulator.
lypinator 0:bb348c97df44 157 * @retval HAL status
lypinator 0:bb348c97df44 158 */
lypinator 0:bb348c97df44 159 HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void)
lypinator 0:bb348c97df44 160 {
lypinator 0:bb348c97df44 161 uint32_t tickstart = 0U;
lypinator 0:bb348c97df44 162
lypinator 0:bb348c97df44 163 *(__IO uint32_t *) CSR_BRE_BB = (uint32_t)ENABLE;
lypinator 0:bb348c97df44 164
lypinator 0:bb348c97df44 165 /* Get tick */
lypinator 0:bb348c97df44 166 tickstart = HAL_GetTick();
lypinator 0:bb348c97df44 167
lypinator 0:bb348c97df44 168 /* Wait till Backup regulator ready flag is set */
lypinator 0:bb348c97df44 169 while(__HAL_PWR_GET_FLAG(PWR_FLAG_BRR) == RESET)
lypinator 0:bb348c97df44 170 {
lypinator 0:bb348c97df44 171 if((HAL_GetTick() - tickstart ) > PWR_BKPREG_TIMEOUT_VALUE)
lypinator 0:bb348c97df44 172 {
lypinator 0:bb348c97df44 173 return HAL_TIMEOUT;
lypinator 0:bb348c97df44 174 }
lypinator 0:bb348c97df44 175 }
lypinator 0:bb348c97df44 176 return HAL_OK;
lypinator 0:bb348c97df44 177 }
lypinator 0:bb348c97df44 178
lypinator 0:bb348c97df44 179 /**
lypinator 0:bb348c97df44 180 * @brief Disables the Backup Regulator.
lypinator 0:bb348c97df44 181 * @retval HAL status
lypinator 0:bb348c97df44 182 */
lypinator 0:bb348c97df44 183 HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void)
lypinator 0:bb348c97df44 184 {
lypinator 0:bb348c97df44 185 uint32_t tickstart = 0U;
lypinator 0:bb348c97df44 186
lypinator 0:bb348c97df44 187 *(__IO uint32_t *) CSR_BRE_BB = (uint32_t)DISABLE;
lypinator 0:bb348c97df44 188
lypinator 0:bb348c97df44 189 /* Get tick */
lypinator 0:bb348c97df44 190 tickstart = HAL_GetTick();
lypinator 0:bb348c97df44 191
lypinator 0:bb348c97df44 192 /* Wait till Backup regulator ready flag is set */
lypinator 0:bb348c97df44 193 while(__HAL_PWR_GET_FLAG(PWR_FLAG_BRR) != RESET)
lypinator 0:bb348c97df44 194 {
lypinator 0:bb348c97df44 195 if((HAL_GetTick() - tickstart ) > PWR_BKPREG_TIMEOUT_VALUE)
lypinator 0:bb348c97df44 196 {
lypinator 0:bb348c97df44 197 return HAL_TIMEOUT;
lypinator 0:bb348c97df44 198 }
lypinator 0:bb348c97df44 199 }
lypinator 0:bb348c97df44 200 return HAL_OK;
lypinator 0:bb348c97df44 201 }
lypinator 0:bb348c97df44 202
lypinator 0:bb348c97df44 203 /**
lypinator 0:bb348c97df44 204 * @brief Enables the Flash Power Down in Stop mode.
lypinator 0:bb348c97df44 205 * @retval None
lypinator 0:bb348c97df44 206 */
lypinator 0:bb348c97df44 207 void HAL_PWREx_EnableFlashPowerDown(void)
lypinator 0:bb348c97df44 208 {
lypinator 0:bb348c97df44 209 *(__IO uint32_t *) CR_FPDS_BB = (uint32_t)ENABLE;
lypinator 0:bb348c97df44 210 }
lypinator 0:bb348c97df44 211
lypinator 0:bb348c97df44 212 /**
lypinator 0:bb348c97df44 213 * @brief Disables the Flash Power Down in Stop mode.
lypinator 0:bb348c97df44 214 * @retval None
lypinator 0:bb348c97df44 215 */
lypinator 0:bb348c97df44 216 void HAL_PWREx_DisableFlashPowerDown(void)
lypinator 0:bb348c97df44 217 {
lypinator 0:bb348c97df44 218 *(__IO uint32_t *) CR_FPDS_BB = (uint32_t)DISABLE;
lypinator 0:bb348c97df44 219 }
lypinator 0:bb348c97df44 220
lypinator 0:bb348c97df44 221 /**
lypinator 0:bb348c97df44 222 * @brief Return Voltage Scaling Range.
lypinator 0:bb348c97df44 223 * @retval The configured scale for the regulator voltage(VOS bit field).
lypinator 0:bb348c97df44 224 * The returned value can be one of the following:
lypinator 0:bb348c97df44 225 * - @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode
lypinator 0:bb348c97df44 226 * - @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode
lypinator 0:bb348c97df44 227 * - @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode
lypinator 0:bb348c97df44 228 */
lypinator 0:bb348c97df44 229 uint32_t HAL_PWREx_GetVoltageRange(void)
lypinator 0:bb348c97df44 230 {
lypinator 0:bb348c97df44 231 return (PWR->CR & PWR_CR_VOS);
lypinator 0:bb348c97df44 232 }
lypinator 0:bb348c97df44 233
lypinator 0:bb348c97df44 234 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
lypinator 0:bb348c97df44 235 /**
lypinator 0:bb348c97df44 236 * @brief Configures the main internal regulator output voltage.
lypinator 0:bb348c97df44 237 * @param VoltageScaling specifies the regulator output voltage to achieve
lypinator 0:bb348c97df44 238 * a tradeoff between performance and power consumption.
lypinator 0:bb348c97df44 239 * This parameter can be one of the following values:
lypinator 0:bb348c97df44 240 * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output range 1 mode,
lypinator 0:bb348c97df44 241 * the maximum value of fHCLK = 168 MHz.
lypinator 0:bb348c97df44 242 * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output range 2 mode,
lypinator 0:bb348c97df44 243 * the maximum value of fHCLK = 144 MHz.
lypinator 0:bb348c97df44 244 * @note When moving from Range 1 to Range 2, the system frequency must be decreased to
lypinator 0:bb348c97df44 245 * a value below 144 MHz before calling HAL_PWREx_ConfigVoltageScaling() API.
lypinator 0:bb348c97df44 246 * When moving from Range 2 to Range 1, the system frequency can be increased to
lypinator 0:bb348c97df44 247 * a value up to 168 MHz after calling HAL_PWREx_ConfigVoltageScaling() API.
lypinator 0:bb348c97df44 248 * @retval HAL Status
lypinator 0:bb348c97df44 249 */
lypinator 0:bb348c97df44 250 HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
lypinator 0:bb348c97df44 251 {
lypinator 0:bb348c97df44 252 uint32_t tickstart = 0U;
lypinator 0:bb348c97df44 253
lypinator 0:bb348c97df44 254 assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling));
lypinator 0:bb348c97df44 255
lypinator 0:bb348c97df44 256 /* Enable PWR RCC Clock Peripheral */
lypinator 0:bb348c97df44 257 __HAL_RCC_PWR_CLK_ENABLE();
lypinator 0:bb348c97df44 258
lypinator 0:bb348c97df44 259 /* Set Range */
lypinator 0:bb348c97df44 260 __HAL_PWR_VOLTAGESCALING_CONFIG(VoltageScaling);
lypinator 0:bb348c97df44 261
lypinator 0:bb348c97df44 262 /* Get Start Tick*/
lypinator 0:bb348c97df44 263 tickstart = HAL_GetTick();
lypinator 0:bb348c97df44 264 while((__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY) == RESET))
lypinator 0:bb348c97df44 265 {
lypinator 0:bb348c97df44 266 if((HAL_GetTick() - tickstart ) > PWR_VOSRDY_TIMEOUT_VALUE)
lypinator 0:bb348c97df44 267 {
lypinator 0:bb348c97df44 268 return HAL_TIMEOUT;
lypinator 0:bb348c97df44 269 }
lypinator 0:bb348c97df44 270 }
lypinator 0:bb348c97df44 271
lypinator 0:bb348c97df44 272 return HAL_OK;
lypinator 0:bb348c97df44 273 }
lypinator 0:bb348c97df44 274
lypinator 0:bb348c97df44 275 #elif defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
lypinator 0:bb348c97df44 276 defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || \
lypinator 0:bb348c97df44 277 defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) || \
lypinator 0:bb348c97df44 278 defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || \
lypinator 0:bb348c97df44 279 defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
lypinator 0:bb348c97df44 280 /**
lypinator 0:bb348c97df44 281 * @brief Configures the main internal regulator output voltage.
lypinator 0:bb348c97df44 282 * @param VoltageScaling specifies the regulator output voltage to achieve
lypinator 0:bb348c97df44 283 * a tradeoff between performance and power consumption.
lypinator 0:bb348c97df44 284 * This parameter can be one of the following values:
lypinator 0:bb348c97df44 285 * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output range 1 mode,
lypinator 0:bb348c97df44 286 * the maximum value of fHCLK is 168 MHz. It can be extended to
lypinator 0:bb348c97df44 287 * 180 MHz by activating the over-drive mode.
lypinator 0:bb348c97df44 288 * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output range 2 mode,
lypinator 0:bb348c97df44 289 * the maximum value of fHCLK is 144 MHz. It can be extended to,
lypinator 0:bb348c97df44 290 * 168 MHz by activating the over-drive mode.
lypinator 0:bb348c97df44 291 * @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output range 3 mode,
lypinator 0:bb348c97df44 292 * the maximum value of fHCLK is 120 MHz.
lypinator 0:bb348c97df44 293 * @note To update the system clock frequency(SYSCLK):
lypinator 0:bb348c97df44 294 * - Set the HSI or HSE as system clock frequency using the HAL_RCC_ClockConfig().
lypinator 0:bb348c97df44 295 * - Call the HAL_RCC_OscConfig() to configure the PLL.
lypinator 0:bb348c97df44 296 * - Call HAL_PWREx_ConfigVoltageScaling() API to adjust the voltage scale.
lypinator 0:bb348c97df44 297 * - Set the new system clock frequency using the HAL_RCC_ClockConfig().
lypinator 0:bb348c97df44 298 * @note The scale can be modified only when the HSI or HSE clock source is selected
lypinator 0:bb348c97df44 299 * as system clock source, otherwise the API returns HAL_ERROR.
lypinator 0:bb348c97df44 300 * @note When the PLL is OFF, the voltage scale 3 is automatically selected and the VOS bits
lypinator 0:bb348c97df44 301 * value in the PWR_CR1 register are not taken in account.
lypinator 0:bb348c97df44 302 * @note This API forces the PLL state ON to allow the possibility to configure the voltage scale 1 or 2.
lypinator 0:bb348c97df44 303 * @note The new voltage scale is active only when the PLL is ON.
lypinator 0:bb348c97df44 304 * @retval HAL Status
lypinator 0:bb348c97df44 305 */
lypinator 0:bb348c97df44 306 HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
lypinator 0:bb348c97df44 307 {
lypinator 0:bb348c97df44 308 uint32_t tickstart = 0U;
lypinator 0:bb348c97df44 309
lypinator 0:bb348c97df44 310 assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling));
lypinator 0:bb348c97df44 311
lypinator 0:bb348c97df44 312 /* Enable PWR RCC Clock Peripheral */
lypinator 0:bb348c97df44 313 __HAL_RCC_PWR_CLK_ENABLE();
lypinator 0:bb348c97df44 314
lypinator 0:bb348c97df44 315 /* Check if the PLL is used as system clock or not */
lypinator 0:bb348c97df44 316 if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
lypinator 0:bb348c97df44 317 {
lypinator 0:bb348c97df44 318 /* Disable the main PLL */
lypinator 0:bb348c97df44 319 __HAL_RCC_PLL_DISABLE();
lypinator 0:bb348c97df44 320
lypinator 0:bb348c97df44 321 /* Get Start Tick */
lypinator 0:bb348c97df44 322 tickstart = HAL_GetTick();
lypinator 0:bb348c97df44 323 /* Wait till PLL is disabled */
lypinator 0:bb348c97df44 324 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
lypinator 0:bb348c97df44 325 {
lypinator 0:bb348c97df44 326 if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
lypinator 0:bb348c97df44 327 {
lypinator 0:bb348c97df44 328 return HAL_TIMEOUT;
lypinator 0:bb348c97df44 329 }
lypinator 0:bb348c97df44 330 }
lypinator 0:bb348c97df44 331
lypinator 0:bb348c97df44 332 /* Set Range */
lypinator 0:bb348c97df44 333 __HAL_PWR_VOLTAGESCALING_CONFIG(VoltageScaling);
lypinator 0:bb348c97df44 334
lypinator 0:bb348c97df44 335 /* Enable the main PLL */
lypinator 0:bb348c97df44 336 __HAL_RCC_PLL_ENABLE();
lypinator 0:bb348c97df44 337
lypinator 0:bb348c97df44 338 /* Get Start Tick */
lypinator 0:bb348c97df44 339 tickstart = HAL_GetTick();
lypinator 0:bb348c97df44 340 /* Wait till PLL is ready */
lypinator 0:bb348c97df44 341 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
lypinator 0:bb348c97df44 342 {
lypinator 0:bb348c97df44 343 if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
lypinator 0:bb348c97df44 344 {
lypinator 0:bb348c97df44 345 return HAL_TIMEOUT;
lypinator 0:bb348c97df44 346 }
lypinator 0:bb348c97df44 347 }
lypinator 0:bb348c97df44 348
lypinator 0:bb348c97df44 349 /* Get Start Tick */
lypinator 0:bb348c97df44 350 tickstart = HAL_GetTick();
lypinator 0:bb348c97df44 351 while((__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY) == RESET))
lypinator 0:bb348c97df44 352 {
lypinator 0:bb348c97df44 353 if((HAL_GetTick() - tickstart ) > PWR_VOSRDY_TIMEOUT_VALUE)
lypinator 0:bb348c97df44 354 {
lypinator 0:bb348c97df44 355 return HAL_TIMEOUT;
lypinator 0:bb348c97df44 356 }
lypinator 0:bb348c97df44 357 }
lypinator 0:bb348c97df44 358 }
lypinator 0:bb348c97df44 359 else
lypinator 0:bb348c97df44 360 {
lypinator 0:bb348c97df44 361 return HAL_ERROR;
lypinator 0:bb348c97df44 362 }
lypinator 0:bb348c97df44 363
lypinator 0:bb348c97df44 364 return HAL_OK;
lypinator 0:bb348c97df44 365 }
lypinator 0:bb348c97df44 366 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
lypinator 0:bb348c97df44 367
lypinator 0:bb348c97df44 368 #if defined(STM32F469xx) || defined(STM32F479xx)
lypinator 0:bb348c97df44 369 /**
lypinator 0:bb348c97df44 370 * @brief Enables Wakeup Pin Detection on high level (rising edge).
lypinator 0:bb348c97df44 371 * @retval None
lypinator 0:bb348c97df44 372 */
lypinator 0:bb348c97df44 373 void HAL_PWREx_EnableWakeUpPinPolarityRisingEdge(void)
lypinator 0:bb348c97df44 374 {
lypinator 0:bb348c97df44 375 *(__IO uint32_t *) CSR_WUPP_BB = (uint32_t)DISABLE;
lypinator 0:bb348c97df44 376 }
lypinator 0:bb348c97df44 377
lypinator 0:bb348c97df44 378 /**
lypinator 0:bb348c97df44 379 * @brief Enables Wakeup Pin Detection on low level (falling edge).
lypinator 0:bb348c97df44 380 * @retval None
lypinator 0:bb348c97df44 381 */
lypinator 0:bb348c97df44 382 void HAL_PWREx_EnableWakeUpPinPolarityFallingEdge(void)
lypinator 0:bb348c97df44 383 {
lypinator 0:bb348c97df44 384 *(__IO uint32_t *) CSR_WUPP_BB = (uint32_t)ENABLE;
lypinator 0:bb348c97df44 385 }
lypinator 0:bb348c97df44 386 #endif /* STM32F469xx || STM32F479xx */
lypinator 0:bb348c97df44 387
lypinator 0:bb348c97df44 388 #if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) ||\
lypinator 0:bb348c97df44 389 defined(STM32F411xE) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\
lypinator 0:bb348c97df44 390 defined(STM32F413xx) || defined(STM32F423xx)
lypinator 0:bb348c97df44 391 /**
lypinator 0:bb348c97df44 392 * @brief Enables Main Regulator low voltage mode.
lypinator 0:bb348c97df44 393 * @note This mode is only available for STM32F401xx/STM32F410xx/STM32F411xx/STM32F412Zx/STM32F412Rx/STM32F412Vx/STM32F412Cx/
lypinator 0:bb348c97df44 394 * STM32F413xx/STM32F423xx devices.
lypinator 0:bb348c97df44 395 * @retval None
lypinator 0:bb348c97df44 396 */
lypinator 0:bb348c97df44 397 void HAL_PWREx_EnableMainRegulatorLowVoltage(void)
lypinator 0:bb348c97df44 398 {
lypinator 0:bb348c97df44 399 *(__IO uint32_t *) CR_MRLVDS_BB = (uint32_t)ENABLE;
lypinator 0:bb348c97df44 400 }
lypinator 0:bb348c97df44 401
lypinator 0:bb348c97df44 402 /**
lypinator 0:bb348c97df44 403 * @brief Disables Main Regulator low voltage mode.
lypinator 0:bb348c97df44 404 * @note This mode is only available for STM32F401xx/STM32F410xx/STM32F411xx/STM32F412Zx/STM32F412Rx/STM32F412Vx/STM32F412Cx/
lypinator 0:bb348c97df44 405 * STM32F413xx/STM32F423xxdevices.
lypinator 0:bb348c97df44 406 * @retval None
lypinator 0:bb348c97df44 407 */
lypinator 0:bb348c97df44 408 void HAL_PWREx_DisableMainRegulatorLowVoltage(void)
lypinator 0:bb348c97df44 409 {
lypinator 0:bb348c97df44 410 *(__IO uint32_t *) CR_MRLVDS_BB = (uint32_t)DISABLE;
lypinator 0:bb348c97df44 411 }
lypinator 0:bb348c97df44 412
lypinator 0:bb348c97df44 413 /**
lypinator 0:bb348c97df44 414 * @brief Enables Low Power Regulator low voltage mode.
lypinator 0:bb348c97df44 415 * @note This mode is only available for STM32F401xx/STM32F410xx/STM32F411xx/STM32F412Zx/STM32F412Rx/STM32F412Vx/STM32F412Cx/
lypinator 0:bb348c97df44 416 * STM32F413xx/STM32F423xx devices.
lypinator 0:bb348c97df44 417 * @retval None
lypinator 0:bb348c97df44 418 */
lypinator 0:bb348c97df44 419 void HAL_PWREx_EnableLowRegulatorLowVoltage(void)
lypinator 0:bb348c97df44 420 {
lypinator 0:bb348c97df44 421 *(__IO uint32_t *) CR_LPLVDS_BB = (uint32_t)ENABLE;
lypinator 0:bb348c97df44 422 }
lypinator 0:bb348c97df44 423
lypinator 0:bb348c97df44 424 /**
lypinator 0:bb348c97df44 425 * @brief Disables Low Power Regulator low voltage mode.
lypinator 0:bb348c97df44 426 * @note This mode is only available for STM32F401xx/STM32F410xx/STM32F411xx/STM32F412Zx/STM32F412Rx/STM32F412Vx/STM32F412Cx/
lypinator 0:bb348c97df44 427 * STM32F413xx/STM32F423xx devices.
lypinator 0:bb348c97df44 428 * @retval None
lypinator 0:bb348c97df44 429 */
lypinator 0:bb348c97df44 430 void HAL_PWREx_DisableLowRegulatorLowVoltage(void)
lypinator 0:bb348c97df44 431 {
lypinator 0:bb348c97df44 432 *(__IO uint32_t *) CR_LPLVDS_BB = (uint32_t)DISABLE;
lypinator 0:bb348c97df44 433 }
lypinator 0:bb348c97df44 434
lypinator 0:bb348c97df44 435 #endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F412Zx || STM32F412Rx || STM32F412Vx || STM32F412Cx ||
lypinator 0:bb348c97df44 436 STM32F413xx || STM32F423xx */
lypinator 0:bb348c97df44 437
lypinator 0:bb348c97df44 438 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
lypinator 0:bb348c97df44 439 defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
lypinator 0:bb348c97df44 440 /**
lypinator 0:bb348c97df44 441 * @brief Activates the Over-Drive mode.
lypinator 0:bb348c97df44 442 * @note This function can be used only for STM32F42xx/STM32F43xx/STM32F446xx/STM32F469xx/STM32F479xx devices.
lypinator 0:bb348c97df44 443 * This mode allows the CPU and the core logic to operate at a higher frequency
lypinator 0:bb348c97df44 444 * than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3).
lypinator 0:bb348c97df44 445 * @note It is recommended to enter or exit Over-drive mode when the application is not running
lypinator 0:bb348c97df44 446 * critical tasks and when the system clock source is either HSI or HSE.
lypinator 0:bb348c97df44 447 * During the Over-drive switch activation, no peripheral clocks should be enabled.
lypinator 0:bb348c97df44 448 * The peripheral clocks must be enabled once the Over-drive mode is activated.
lypinator 0:bb348c97df44 449 * @retval HAL status
lypinator 0:bb348c97df44 450 */
lypinator 0:bb348c97df44 451 HAL_StatusTypeDef HAL_PWREx_EnableOverDrive(void)
lypinator 0:bb348c97df44 452 {
lypinator 0:bb348c97df44 453 uint32_t tickstart = 0U;
lypinator 0:bb348c97df44 454
lypinator 0:bb348c97df44 455 __HAL_RCC_PWR_CLK_ENABLE();
lypinator 0:bb348c97df44 456
lypinator 0:bb348c97df44 457 /* Enable the Over-drive to extend the clock frequency to 180 Mhz */
lypinator 0:bb348c97df44 458 __HAL_PWR_OVERDRIVE_ENABLE();
lypinator 0:bb348c97df44 459
lypinator 0:bb348c97df44 460 /* Get tick */
lypinator 0:bb348c97df44 461 tickstart = HAL_GetTick();
lypinator 0:bb348c97df44 462
lypinator 0:bb348c97df44 463 while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY))
lypinator 0:bb348c97df44 464 {
lypinator 0:bb348c97df44 465 if((HAL_GetTick() - tickstart) > PWR_OVERDRIVE_TIMEOUT_VALUE)
lypinator 0:bb348c97df44 466 {
lypinator 0:bb348c97df44 467 return HAL_TIMEOUT;
lypinator 0:bb348c97df44 468 }
lypinator 0:bb348c97df44 469 }
lypinator 0:bb348c97df44 470
lypinator 0:bb348c97df44 471 /* Enable the Over-drive switch */
lypinator 0:bb348c97df44 472 __HAL_PWR_OVERDRIVESWITCHING_ENABLE();
lypinator 0:bb348c97df44 473
lypinator 0:bb348c97df44 474 /* Get tick */
lypinator 0:bb348c97df44 475 tickstart = HAL_GetTick();
lypinator 0:bb348c97df44 476
lypinator 0:bb348c97df44 477 while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY))
lypinator 0:bb348c97df44 478 {
lypinator 0:bb348c97df44 479 if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE)
lypinator 0:bb348c97df44 480 {
lypinator 0:bb348c97df44 481 return HAL_TIMEOUT;
lypinator 0:bb348c97df44 482 }
lypinator 0:bb348c97df44 483 }
lypinator 0:bb348c97df44 484 return HAL_OK;
lypinator 0:bb348c97df44 485 }
lypinator 0:bb348c97df44 486
lypinator 0:bb348c97df44 487 /**
lypinator 0:bb348c97df44 488 * @brief Deactivates the Over-Drive mode.
lypinator 0:bb348c97df44 489 * @note This function can be used only for STM32F42xx/STM32F43xx/STM32F446xx/STM32F469xx/STM32F479xx devices.
lypinator 0:bb348c97df44 490 * This mode allows the CPU and the core logic to operate at a higher frequency
lypinator 0:bb348c97df44 491 * than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3).
lypinator 0:bb348c97df44 492 * @note It is recommended to enter or exit Over-drive mode when the application is not running
lypinator 0:bb348c97df44 493 * critical tasks and when the system clock source is either HSI or HSE.
lypinator 0:bb348c97df44 494 * During the Over-drive switch activation, no peripheral clocks should be enabled.
lypinator 0:bb348c97df44 495 * The peripheral clocks must be enabled once the Over-drive mode is activated.
lypinator 0:bb348c97df44 496 * @retval HAL status
lypinator 0:bb348c97df44 497 */
lypinator 0:bb348c97df44 498 HAL_StatusTypeDef HAL_PWREx_DisableOverDrive(void)
lypinator 0:bb348c97df44 499 {
lypinator 0:bb348c97df44 500 uint32_t tickstart = 0U;
lypinator 0:bb348c97df44 501
lypinator 0:bb348c97df44 502 __HAL_RCC_PWR_CLK_ENABLE();
lypinator 0:bb348c97df44 503
lypinator 0:bb348c97df44 504 /* Disable the Over-drive switch */
lypinator 0:bb348c97df44 505 __HAL_PWR_OVERDRIVESWITCHING_DISABLE();
lypinator 0:bb348c97df44 506
lypinator 0:bb348c97df44 507 /* Get tick */
lypinator 0:bb348c97df44 508 tickstart = HAL_GetTick();
lypinator 0:bb348c97df44 509
lypinator 0:bb348c97df44 510 while(__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY))
lypinator 0:bb348c97df44 511 {
lypinator 0:bb348c97df44 512 if((HAL_GetTick() - tickstart) > PWR_OVERDRIVE_TIMEOUT_VALUE)
lypinator 0:bb348c97df44 513 {
lypinator 0:bb348c97df44 514 return HAL_TIMEOUT;
lypinator 0:bb348c97df44 515 }
lypinator 0:bb348c97df44 516 }
lypinator 0:bb348c97df44 517
lypinator 0:bb348c97df44 518 /* Disable the Over-drive */
lypinator 0:bb348c97df44 519 __HAL_PWR_OVERDRIVE_DISABLE();
lypinator 0:bb348c97df44 520
lypinator 0:bb348c97df44 521 /* Get tick */
lypinator 0:bb348c97df44 522 tickstart = HAL_GetTick();
lypinator 0:bb348c97df44 523
lypinator 0:bb348c97df44 524 while(__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY))
lypinator 0:bb348c97df44 525 {
lypinator 0:bb348c97df44 526 if((HAL_GetTick() - tickstart) > PWR_OVERDRIVE_TIMEOUT_VALUE)
lypinator 0:bb348c97df44 527 {
lypinator 0:bb348c97df44 528 return HAL_TIMEOUT;
lypinator 0:bb348c97df44 529 }
lypinator 0:bb348c97df44 530 }
lypinator 0:bb348c97df44 531
lypinator 0:bb348c97df44 532 return HAL_OK;
lypinator 0:bb348c97df44 533 }
lypinator 0:bb348c97df44 534
lypinator 0:bb348c97df44 535 /**
lypinator 0:bb348c97df44 536 * @brief Enters in Under-Drive STOP mode.
lypinator 0:bb348c97df44 537 *
lypinator 0:bb348c97df44 538 * @note This mode is only available for STM32F42xxx/STM32F43xxx/STM32F446xx/STM32F469xx/STM32F479xx devices.
lypinator 0:bb348c97df44 539 *
lypinator 0:bb348c97df44 540 * @note This mode can be selected only when the Under-Drive is already active
lypinator 0:bb348c97df44 541 *
lypinator 0:bb348c97df44 542 * @note This mode is enabled only with STOP low power mode.
lypinator 0:bb348c97df44 543 * In this mode, the 1.2V domain is preserved in reduced leakage mode. This
lypinator 0:bb348c97df44 544 * mode is only available when the main regulator or the low power regulator
lypinator 0:bb348c97df44 545 * is in low voltage mode
lypinator 0:bb348c97df44 546 *
lypinator 0:bb348c97df44 547 * @note If the Under-drive mode was enabled, it is automatically disabled after
lypinator 0:bb348c97df44 548 * exiting Stop mode.
lypinator 0:bb348c97df44 549 * When the voltage regulator operates in Under-drive mode, an additional
lypinator 0:bb348c97df44 550 * startup delay is induced when waking up from Stop mode.
lypinator 0:bb348c97df44 551 *
lypinator 0:bb348c97df44 552 * @note In Stop mode, all I/O pins keep the same state as in Run mode.
lypinator 0:bb348c97df44 553 *
lypinator 0:bb348c97df44 554 * @note When exiting Stop mode by issuing an interrupt or a wake-up event,
lypinator 0:bb348c97df44 555 * the HSI RC oscillator is selected as system clock.
lypinator 0:bb348c97df44 556 *
lypinator 0:bb348c97df44 557 * @note When the voltage regulator operates in low power mode, an additional
lypinator 0:bb348c97df44 558 * startup delay is incurred when waking up from Stop mode.
lypinator 0:bb348c97df44 559 * By keeping the internal regulator ON during Stop mode, the consumption
lypinator 0:bb348c97df44 560 * is higher although the startup time is reduced.
lypinator 0:bb348c97df44 561 *
lypinator 0:bb348c97df44 562 * @param Regulator specifies the regulator state in STOP mode.
lypinator 0:bb348c97df44 563 * This parameter can be one of the following values:
lypinator 0:bb348c97df44 564 * @arg PWR_MAINREGULATOR_UNDERDRIVE_ON: Main Regulator in under-drive mode
lypinator 0:bb348c97df44 565 * and Flash memory in power-down when the device is in Stop under-drive mode
lypinator 0:bb348c97df44 566 * @arg PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON: Low Power Regulator in under-drive mode
lypinator 0:bb348c97df44 567 * and Flash memory in power-down when the device is in Stop under-drive mode
lypinator 0:bb348c97df44 568 * @param STOPEntry specifies if STOP mode in entered with WFI or WFE instruction.
lypinator 0:bb348c97df44 569 * This parameter can be one of the following values:
lypinator 0:bb348c97df44 570 * @arg PWR_SLEEPENTRY_WFI: enter STOP mode with WFI instruction
lypinator 0:bb348c97df44 571 * @arg PWR_SLEEPENTRY_WFE: enter STOP mode with WFE instruction
lypinator 0:bb348c97df44 572 * @retval None
lypinator 0:bb348c97df44 573 */
lypinator 0:bb348c97df44 574 HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
lypinator 0:bb348c97df44 575 {
lypinator 0:bb348c97df44 576 uint32_t tmpreg1 = 0U;
lypinator 0:bb348c97df44 577
lypinator 0:bb348c97df44 578 /* Check the parameters */
lypinator 0:bb348c97df44 579 assert_param(IS_PWR_REGULATOR_UNDERDRIVE(Regulator));
lypinator 0:bb348c97df44 580 assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
lypinator 0:bb348c97df44 581
lypinator 0:bb348c97df44 582 /* Enable Power ctrl clock */
lypinator 0:bb348c97df44 583 __HAL_RCC_PWR_CLK_ENABLE();
lypinator 0:bb348c97df44 584 /* Enable the Under-drive Mode ---------------------------------------------*/
lypinator 0:bb348c97df44 585 /* Clear Under-drive flag */
lypinator 0:bb348c97df44 586 __HAL_PWR_CLEAR_ODRUDR_FLAG();
lypinator 0:bb348c97df44 587
lypinator 0:bb348c97df44 588 /* Enable the Under-drive */
lypinator 0:bb348c97df44 589 __HAL_PWR_UNDERDRIVE_ENABLE();
lypinator 0:bb348c97df44 590
lypinator 0:bb348c97df44 591 /* Select the regulator state in STOP mode ---------------------------------*/
lypinator 0:bb348c97df44 592 tmpreg1 = PWR->CR;
lypinator 0:bb348c97df44 593 /* Clear PDDS, LPDS, MRLUDS and LPLUDS bits */
lypinator 0:bb348c97df44 594 tmpreg1 &= (uint32_t)~(PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_LPUDS | PWR_CR_MRUDS);
lypinator 0:bb348c97df44 595
lypinator 0:bb348c97df44 596 /* Set LPDS, MRLUDS and LPLUDS bits according to PWR_Regulator value */
lypinator 0:bb348c97df44 597 tmpreg1 |= Regulator;
lypinator 0:bb348c97df44 598
lypinator 0:bb348c97df44 599 /* Store the new value */
lypinator 0:bb348c97df44 600 PWR->CR = tmpreg1;
lypinator 0:bb348c97df44 601
lypinator 0:bb348c97df44 602 /* Set SLEEPDEEP bit of Cortex System Control Register */
lypinator 0:bb348c97df44 603 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
lypinator 0:bb348c97df44 604
lypinator 0:bb348c97df44 605 /* Select STOP mode entry --------------------------------------------------*/
lypinator 0:bb348c97df44 606 if(STOPEntry == PWR_SLEEPENTRY_WFI)
lypinator 0:bb348c97df44 607 {
lypinator 0:bb348c97df44 608 /* Request Wait For Interrupt */
lypinator 0:bb348c97df44 609 __WFI();
lypinator 0:bb348c97df44 610 }
lypinator 0:bb348c97df44 611 else
lypinator 0:bb348c97df44 612 {
lypinator 0:bb348c97df44 613 /* Request Wait For Event */
lypinator 0:bb348c97df44 614 __WFE();
lypinator 0:bb348c97df44 615 }
lypinator 0:bb348c97df44 616 /* Reset SLEEPDEEP bit of Cortex System Control Register */
lypinator 0:bb348c97df44 617 SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
lypinator 0:bb348c97df44 618
lypinator 0:bb348c97df44 619 return HAL_OK;
lypinator 0:bb348c97df44 620 }
lypinator 0:bb348c97df44 621
lypinator 0:bb348c97df44 622 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
lypinator 0:bb348c97df44 623 /**
lypinator 0:bb348c97df44 624 * @}
lypinator 0:bb348c97df44 625 */
lypinator 0:bb348c97df44 626
lypinator 0:bb348c97df44 627 /**
lypinator 0:bb348c97df44 628 * @}
lypinator 0:bb348c97df44 629 */
lypinator 0:bb348c97df44 630
lypinator 0:bb348c97df44 631 #endif /* HAL_PWR_MODULE_ENABLED */
lypinator 0:bb348c97df44 632 /**
lypinator 0:bb348c97df44 633 * @}
lypinator 0:bb348c97df44 634 */
lypinator 0:bb348c97df44 635
lypinator 0:bb348c97df44 636 /**
lypinator 0:bb348c97df44 637 * @}
lypinator 0:bb348c97df44 638 */
lypinator 0:bb348c97df44 639
lypinator 0:bb348c97df44 640 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/