Thomas Lyp / DevLibMemoryController

Initial commit

Dependencies:   FastPWM

mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_eth.h@0:bb348c97df44, 2020-09-16 (annotated)

Committer:
lypinator
Date:
Wed Sep 16 01:11:49 2020 +0000
Revision:
0:bb348c97df44
Added PWM

Who changed what in which revision?

UserRevisionLine numberNew contents of line
lypinator 0:bb348c97df44 1 /**
lypinator 0:bb348c97df44 2 ******************************************************************************
lypinator 0:bb348c97df44 3 * @file stm32f4xx_hal_eth.h
lypinator 0:bb348c97df44 4 * @author MCD Application Team
lypinator 0:bb348c97df44 5 * @brief Header file of ETH HAL module.
lypinator 0:bb348c97df44 6 ******************************************************************************
lypinator 0:bb348c97df44 7 * @attention
lypinator 0:bb348c97df44 8 *
lypinator 0:bb348c97df44 9 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
lypinator 0:bb348c97df44 10 *
lypinator 0:bb348c97df44 11 * Redistribution and use in source and binary forms, with or without modification,
lypinator 0:bb348c97df44 12 * are permitted provided that the following conditions are met:
lypinator 0:bb348c97df44 13 * 1. Redistributions of source code must retain the above copyright notice,
lypinator 0:bb348c97df44 14 * this list of conditions and the following disclaimer.
lypinator 0:bb348c97df44 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
lypinator 0:bb348c97df44 16 * this list of conditions and the following disclaimer in the documentation
lypinator 0:bb348c97df44 17 * and/or other materials provided with the distribution.
lypinator 0:bb348c97df44 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
lypinator 0:bb348c97df44 19 * may be used to endorse or promote products derived from this software
lypinator 0:bb348c97df44 20 * without specific prior written permission.
lypinator 0:bb348c97df44 21 *
lypinator 0:bb348c97df44 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
lypinator 0:bb348c97df44 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
lypinator 0:bb348c97df44 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
lypinator 0:bb348c97df44 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
lypinator 0:bb348c97df44 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
lypinator 0:bb348c97df44 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
lypinator 0:bb348c97df44 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
lypinator 0:bb348c97df44 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
lypinator 0:bb348c97df44 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
lypinator 0:bb348c97df44 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
lypinator 0:bb348c97df44 32 *
lypinator 0:bb348c97df44 33 ******************************************************************************
lypinator 0:bb348c97df44 34 */
lypinator 0:bb348c97df44 35
lypinator 0:bb348c97df44 36 /* Define to prevent recursive inclusion -------------------------------------*/
lypinator 0:bb348c97df44 37 #ifndef __STM32F4xx_HAL_ETH_H
lypinator 0:bb348c97df44 38 #define __STM32F4xx_HAL_ETH_H
lypinator 0:bb348c97df44 39
lypinator 0:bb348c97df44 40 #ifdef __cplusplus
lypinator 0:bb348c97df44 41 extern "C" {
lypinator 0:bb348c97df44 42 #endif
lypinator 0:bb348c97df44 43
lypinator 0:bb348c97df44 44 #if defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) ||\
lypinator 0:bb348c97df44 45 defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
lypinator 0:bb348c97df44 46 /* Includes ------------------------------------------------------------------*/
lypinator 0:bb348c97df44 47 #include "stm32f4xx_hal_def.h"
lypinator 0:bb348c97df44 48
lypinator 0:bb348c97df44 49 /** @addtogroup STM32F4xx_HAL_Driver
lypinator 0:bb348c97df44 50 * @{
lypinator 0:bb348c97df44 51 */
lypinator 0:bb348c97df44 52
lypinator 0:bb348c97df44 53 /** @addtogroup ETH
lypinator 0:bb348c97df44 54 * @{
lypinator 0:bb348c97df44 55 */
lypinator 0:bb348c97df44 56
lypinator 0:bb348c97df44 57 /** @addtogroup ETH_Private_Macros
lypinator 0:bb348c97df44 58 * @{
lypinator 0:bb348c97df44 59 */
lypinator 0:bb348c97df44 60 #define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20U)
lypinator 0:bb348c97df44 61 #define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AUTONEGOTIATION_ENABLE) || \
lypinator 0:bb348c97df44 62 ((CMD) == ETH_AUTONEGOTIATION_DISABLE))
lypinator 0:bb348c97df44 63 #define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_SPEED_10M) || \
lypinator 0:bb348c97df44 64 ((SPEED) == ETH_SPEED_100M))
lypinator 0:bb348c97df44 65 #define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_MODE_FULLDUPLEX) || \
lypinator 0:bb348c97df44 66 ((MODE) == ETH_MODE_HALFDUPLEX))
lypinator 0:bb348c97df44 67 #define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) || \
lypinator 0:bb348c97df44 68 ((MODE) == ETH_RXINTERRUPT_MODE))
lypinator 0:bb348c97df44 69 #define IS_ETH_CHECKSUM_MODE(MODE) (((MODE) == ETH_CHECKSUM_BY_HARDWARE) || \
lypinator 0:bb348c97df44 70 ((MODE) == ETH_CHECKSUM_BY_SOFTWARE))
lypinator 0:bb348c97df44 71 #define IS_ETH_MEDIA_INTERFACE(MODE) (((MODE) == ETH_MEDIA_INTERFACE_MII) || \
lypinator 0:bb348c97df44 72 ((MODE) == ETH_MEDIA_INTERFACE_RMII))
lypinator 0:bb348c97df44 73 #define IS_ETH_WATCHDOG(CMD) (((CMD) == ETH_WATCHDOG_ENABLE) || \
lypinator 0:bb348c97df44 74 ((CMD) == ETH_WATCHDOG_DISABLE))
lypinator 0:bb348c97df44 75 #define IS_ETH_JABBER(CMD) (((CMD) == ETH_JABBER_ENABLE) || \
lypinator 0:bb348c97df44 76 ((CMD) == ETH_JABBER_DISABLE))
lypinator 0:bb348c97df44 77 #define IS_ETH_INTER_FRAME_GAP(GAP) (((GAP) == ETH_INTERFRAMEGAP_96BIT) || \
lypinator 0:bb348c97df44 78 ((GAP) == ETH_INTERFRAMEGAP_88BIT) || \
lypinator 0:bb348c97df44 79 ((GAP) == ETH_INTERFRAMEGAP_80BIT) || \
lypinator 0:bb348c97df44 80 ((GAP) == ETH_INTERFRAMEGAP_72BIT) || \
lypinator 0:bb348c97df44 81 ((GAP) == ETH_INTERFRAMEGAP_64BIT) || \
lypinator 0:bb348c97df44 82 ((GAP) == ETH_INTERFRAMEGAP_56BIT) || \
lypinator 0:bb348c97df44 83 ((GAP) == ETH_INTERFRAMEGAP_48BIT) || \
lypinator 0:bb348c97df44 84 ((GAP) == ETH_INTERFRAMEGAP_40BIT))
lypinator 0:bb348c97df44 85 #define IS_ETH_CARRIER_SENSE(CMD) (((CMD) == ETH_CARRIERSENCE_ENABLE) || \
lypinator 0:bb348c97df44 86 ((CMD) == ETH_CARRIERSENCE_DISABLE))
lypinator 0:bb348c97df44 87 #define IS_ETH_RECEIVE_OWN(CMD) (((CMD) == ETH_RECEIVEOWN_ENABLE) || \
lypinator 0:bb348c97df44 88 ((CMD) == ETH_RECEIVEOWN_DISABLE))
lypinator 0:bb348c97df44 89 #define IS_ETH_LOOPBACK_MODE(CMD) (((CMD) == ETH_LOOPBACKMODE_ENABLE) || \
lypinator 0:bb348c97df44 90 ((CMD) == ETH_LOOPBACKMODE_DISABLE))
lypinator 0:bb348c97df44 91 #define IS_ETH_CHECKSUM_OFFLOAD(CMD) (((CMD) == ETH_CHECKSUMOFFLAOD_ENABLE) || \
lypinator 0:bb348c97df44 92 ((CMD) == ETH_CHECKSUMOFFLAOD_DISABLE))
lypinator 0:bb348c97df44 93 #define IS_ETH_RETRY_TRANSMISSION(CMD) (((CMD) == ETH_RETRYTRANSMISSION_ENABLE) || \
lypinator 0:bb348c97df44 94 ((CMD) == ETH_RETRYTRANSMISSION_DISABLE))
lypinator 0:bb348c97df44 95 #define IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD) (((CMD) == ETH_AUTOMATICPADCRCSTRIP_ENABLE) || \
lypinator 0:bb348c97df44 96 ((CMD) == ETH_AUTOMATICPADCRCSTRIP_DISABLE))
lypinator 0:bb348c97df44 97 #define IS_ETH_BACKOFF_LIMIT(LIMIT) (((LIMIT) == ETH_BACKOFFLIMIT_10) || \
lypinator 0:bb348c97df44 98 ((LIMIT) == ETH_BACKOFFLIMIT_8) || \
lypinator 0:bb348c97df44 99 ((LIMIT) == ETH_BACKOFFLIMIT_4) || \
lypinator 0:bb348c97df44 100 ((LIMIT) == ETH_BACKOFFLIMIT_1))
lypinator 0:bb348c97df44 101 #define IS_ETH_DEFERRAL_CHECK(CMD) (((CMD) == ETH_DEFFERRALCHECK_ENABLE) || \
lypinator 0:bb348c97df44 102 ((CMD) == ETH_DEFFERRALCHECK_DISABLE))
lypinator 0:bb348c97df44 103 #define IS_ETH_RECEIVE_ALL(CMD) (((CMD) == ETH_RECEIVEALL_ENABLE) || \
lypinator 0:bb348c97df44 104 ((CMD) == ETH_RECEIVEAll_DISABLE))
lypinator 0:bb348c97df44 105 #define IS_ETH_SOURCE_ADDR_FILTER(CMD) (((CMD) == ETH_SOURCEADDRFILTER_NORMAL_ENABLE) || \
lypinator 0:bb348c97df44 106 ((CMD) == ETH_SOURCEADDRFILTER_INVERSE_ENABLE) || \
lypinator 0:bb348c97df44 107 ((CMD) == ETH_SOURCEADDRFILTER_DISABLE))
lypinator 0:bb348c97df44 108 #define IS_ETH_CONTROL_FRAMES(PASS) (((PASS) == ETH_PASSCONTROLFRAMES_BLOCKALL) || \
lypinator 0:bb348c97df44 109 ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDALL) || \
lypinator 0:bb348c97df44 110 ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER))
lypinator 0:bb348c97df44 111 #define IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD) (((CMD) == ETH_BROADCASTFRAMESRECEPTION_ENABLE) || \
lypinator 0:bb348c97df44 112 ((CMD) == ETH_BROADCASTFRAMESRECEPTION_DISABLE))
lypinator 0:bb348c97df44 113 #define IS_ETH_DESTINATION_ADDR_FILTER(FILTER) (((FILTER) == ETH_DESTINATIONADDRFILTER_NORMAL) || \
lypinator 0:bb348c97df44 114 ((FILTER) == ETH_DESTINATIONADDRFILTER_INVERSE))
lypinator 0:bb348c97df44 115 #define IS_ETH_PROMISCUOUS_MODE(CMD) (((CMD) == ETH_PROMISCUOUS_MODE_ENABLE) || \
lypinator 0:bb348c97df44 116 ((CMD) == ETH_PROMISCUOUS_MODE_DISABLE))
lypinator 0:bb348c97df44 117 #define IS_ETH_MULTICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE) || \
lypinator 0:bb348c97df44 118 ((FILTER) == ETH_MULTICASTFRAMESFILTER_HASHTABLE) || \
lypinator 0:bb348c97df44 119 ((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECT) || \
lypinator 0:bb348c97df44 120 ((FILTER) == ETH_MULTICASTFRAMESFILTER_NONE))
lypinator 0:bb348c97df44 121 #define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE) || \
lypinator 0:bb348c97df44 122 ((FILTER) == ETH_UNICASTFRAMESFILTER_HASHTABLE) || \
lypinator 0:bb348c97df44 123 ((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECT))
lypinator 0:bb348c97df44 124 #define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFFU)
lypinator 0:bb348c97df44 125 #define IS_ETH_ZEROQUANTA_PAUSE(CMD) (((CMD) == ETH_ZEROQUANTAPAUSE_ENABLE) || \
lypinator 0:bb348c97df44 126 ((CMD) == ETH_ZEROQUANTAPAUSE_DISABLE))
lypinator 0:bb348c97df44 127 #define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS4) || \
lypinator 0:bb348c97df44 128 ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS28) || \
lypinator 0:bb348c97df44 129 ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS144) || \
lypinator 0:bb348c97df44 130 ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS256))
lypinator 0:bb348c97df44 131 #define IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD) (((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_ENABLE) || \
lypinator 0:bb348c97df44 132 ((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_DISABLE))
lypinator 0:bb348c97df44 133 #define IS_ETH_RECEIVE_FLOWCONTROL(CMD) (((CMD) == ETH_RECEIVEFLOWCONTROL_ENABLE) || \
lypinator 0:bb348c97df44 134 ((CMD) == ETH_RECEIVEFLOWCONTROL_DISABLE))
lypinator 0:bb348c97df44 135 #define IS_ETH_TRANSMIT_FLOWCONTROL(CMD) (((CMD) == ETH_TRANSMITFLOWCONTROL_ENABLE) || \
lypinator 0:bb348c97df44 136 ((CMD) == ETH_TRANSMITFLOWCONTROL_DISABLE))
lypinator 0:bb348c97df44 137 #define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTAGCOMPARISON_12BIT) || \
lypinator 0:bb348c97df44 138 ((COMPARISON) == ETH_VLANTAGCOMPARISON_16BIT))
lypinator 0:bb348c97df44 139 #define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFFU)
lypinator 0:bb348c97df44 140 #define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS0) || \
lypinator 0:bb348c97df44 141 ((ADDRESS) == ETH_MAC_ADDRESS1) || \
lypinator 0:bb348c97df44 142 ((ADDRESS) == ETH_MAC_ADDRESS2) || \
lypinator 0:bb348c97df44 143 ((ADDRESS) == ETH_MAC_ADDRESS3))
lypinator 0:bb348c97df44 144 #define IS_ETH_MAC_ADDRESS123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS1) || \
lypinator 0:bb348c97df44 145 ((ADDRESS) == ETH_MAC_ADDRESS2) || \
lypinator 0:bb348c97df44 146 ((ADDRESS) == ETH_MAC_ADDRESS3))
lypinator 0:bb348c97df44 147 #define IS_ETH_MAC_ADDRESS_FILTER(FILTER) (((FILTER) == ETH_MAC_ADDRESSFILTER_SA) || \
lypinator 0:bb348c97df44 148 ((FILTER) == ETH_MAC_ADDRESSFILTER_DA))
lypinator 0:bb348c97df44 149 #define IS_ETH_MAC_ADDRESS_MASK(MASK) (((MASK) == ETH_MAC_ADDRESSMASK_BYTE6) || \
lypinator 0:bb348c97df44 150 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE5) || \
lypinator 0:bb348c97df44 151 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE4) || \
lypinator 0:bb348c97df44 152 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE3) || \
lypinator 0:bb348c97df44 153 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE2) || \
lypinator 0:bb348c97df44 154 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE1))
lypinator 0:bb348c97df44 155 #define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD) (((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE) || \
lypinator 0:bb348c97df44 156 ((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE))
lypinator 0:bb348c97df44 157 #define IS_ETH_RECEIVE_STORE_FORWARD(CMD) (((CMD) == ETH_RECEIVESTOREFORWARD_ENABLE) || \
lypinator 0:bb348c97df44 158 ((CMD) == ETH_RECEIVESTOREFORWARD_DISABLE))
lypinator 0:bb348c97df44 159 #define IS_ETH_FLUSH_RECEIVE_FRAME(CMD) (((CMD) == ETH_FLUSHRECEIVEDFRAME_ENABLE) || \
lypinator 0:bb348c97df44 160 ((CMD) == ETH_FLUSHRECEIVEDFRAME_DISABLE))
lypinator 0:bb348c97df44 161 #define IS_ETH_TRANSMIT_STORE_FORWARD(CMD) (((CMD) == ETH_TRANSMITSTOREFORWARD_ENABLE) || \
lypinator 0:bb348c97df44 162 ((CMD) == ETH_TRANSMITSTOREFORWARD_DISABLE))
lypinator 0:bb348c97df44 163 #define IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_64BYTES) || \
lypinator 0:bb348c97df44 164 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_128BYTES) || \
lypinator 0:bb348c97df44 165 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_192BYTES) || \
lypinator 0:bb348c97df44 166 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_256BYTES) || \
lypinator 0:bb348c97df44 167 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_40BYTES) || \
lypinator 0:bb348c97df44 168 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_32BYTES) || \
lypinator 0:bb348c97df44 169 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_24BYTES) || \
lypinator 0:bb348c97df44 170 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_16BYTES))
lypinator 0:bb348c97df44 171 #define IS_ETH_FORWARD_ERROR_FRAMES(CMD) (((CMD) == ETH_FORWARDERRORFRAMES_ENABLE) || \
lypinator 0:bb348c97df44 172 ((CMD) == ETH_FORWARDERRORFRAMES_DISABLE))
lypinator 0:bb348c97df44 173 #define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD) (((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE) || \
lypinator 0:bb348c97df44 174 ((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE))
lypinator 0:bb348c97df44 175 #define IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES) || \
lypinator 0:bb348c97df44 176 ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES) || \
lypinator 0:bb348c97df44 177 ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES) || \
lypinator 0:bb348c97df44 178 ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES))
lypinator 0:bb348c97df44 179 #define IS_ETH_SECOND_FRAME_OPERATE(CMD) (((CMD) == ETH_SECONDFRAMEOPERARTE_ENABLE) || \
lypinator 0:bb348c97df44 180 ((CMD) == ETH_SECONDFRAMEOPERARTE_DISABLE))
lypinator 0:bb348c97df44 181 #define IS_ETH_ADDRESS_ALIGNED_BEATS(CMD) (((CMD) == ETH_ADDRESSALIGNEDBEATS_ENABLE) || \
lypinator 0:bb348c97df44 182 ((CMD) == ETH_ADDRESSALIGNEDBEATS_DISABLE))
lypinator 0:bb348c97df44 183 #define IS_ETH_FIXED_BURST(CMD) (((CMD) == ETH_FIXEDBURST_ENABLE) || \
lypinator 0:bb348c97df44 184 ((CMD) == ETH_FIXEDBURST_DISABLE))
lypinator 0:bb348c97df44 185 #define IS_ETH_RXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_RXDMABURSTLENGTH_1BEAT) || \
lypinator 0:bb348c97df44 186 ((LENGTH) == ETH_RXDMABURSTLENGTH_2BEAT) || \
lypinator 0:bb348c97df44 187 ((LENGTH) == ETH_RXDMABURSTLENGTH_4BEAT) || \
lypinator 0:bb348c97df44 188 ((LENGTH) == ETH_RXDMABURSTLENGTH_8BEAT) || \
lypinator 0:bb348c97df44 189 ((LENGTH) == ETH_RXDMABURSTLENGTH_16BEAT) || \
lypinator 0:bb348c97df44 190 ((LENGTH) == ETH_RXDMABURSTLENGTH_32BEAT) || \
lypinator 0:bb348c97df44 191 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_4BEAT) || \
lypinator 0:bb348c97df44 192 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_8BEAT) || \
lypinator 0:bb348c97df44 193 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_16BEAT) || \
lypinator 0:bb348c97df44 194 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_32BEAT) || \
lypinator 0:bb348c97df44 195 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_64BEAT) || \
lypinator 0:bb348c97df44 196 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_128BEAT))
lypinator 0:bb348c97df44 197 #define IS_ETH_TXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_TXDMABURSTLENGTH_1BEAT) || \
lypinator 0:bb348c97df44 198 ((LENGTH) == ETH_TXDMABURSTLENGTH_2BEAT) || \
lypinator 0:bb348c97df44 199 ((LENGTH) == ETH_TXDMABURSTLENGTH_4BEAT) || \
lypinator 0:bb348c97df44 200 ((LENGTH) == ETH_TXDMABURSTLENGTH_8BEAT) || \
lypinator 0:bb348c97df44 201 ((LENGTH) == ETH_TXDMABURSTLENGTH_16BEAT) || \
lypinator 0:bb348c97df44 202 ((LENGTH) == ETH_TXDMABURSTLENGTH_32BEAT) || \
lypinator 0:bb348c97df44 203 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_4BEAT) || \
lypinator 0:bb348c97df44 204 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_8BEAT) || \
lypinator 0:bb348c97df44 205 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_16BEAT) || \
lypinator 0:bb348c97df44 206 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_32BEAT) || \
lypinator 0:bb348c97df44 207 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_64BEAT) || \
lypinator 0:bb348c97df44 208 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_128BEAT))
lypinator 0:bb348c97df44 209 #define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1FU)
lypinator 0:bb348c97df44 210 #define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO) (((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1) || \
lypinator 0:bb348c97df44 211 ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1) || \
lypinator 0:bb348c97df44 212 ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1) || \
lypinator 0:bb348c97df44 213 ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1) || \
lypinator 0:bb348c97df44 214 ((RATIO) == ETH_DMAARBITRATION_RXPRIORTX))
lypinator 0:bb348c97df44 215 #define IS_ETH_DMATXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMATXDESC_OWN) || \
lypinator 0:bb348c97df44 216 ((FLAG) == ETH_DMATXDESC_IC) || \
lypinator 0:bb348c97df44 217 ((FLAG) == ETH_DMATXDESC_LS) || \
lypinator 0:bb348c97df44 218 ((FLAG) == ETH_DMATXDESC_FS) || \
lypinator 0:bb348c97df44 219 ((FLAG) == ETH_DMATXDESC_DC) || \
lypinator 0:bb348c97df44 220 ((FLAG) == ETH_DMATXDESC_DP) || \
lypinator 0:bb348c97df44 221 ((FLAG) == ETH_DMATXDESC_TTSE) || \
lypinator 0:bb348c97df44 222 ((FLAG) == ETH_DMATXDESC_TER) || \
lypinator 0:bb348c97df44 223 ((FLAG) == ETH_DMATXDESC_TCH) || \
lypinator 0:bb348c97df44 224 ((FLAG) == ETH_DMATXDESC_TTSS) || \
lypinator 0:bb348c97df44 225 ((FLAG) == ETH_DMATXDESC_IHE) || \
lypinator 0:bb348c97df44 226 ((FLAG) == ETH_DMATXDESC_ES) || \
lypinator 0:bb348c97df44 227 ((FLAG) == ETH_DMATXDESC_JT) || \
lypinator 0:bb348c97df44 228 ((FLAG) == ETH_DMATXDESC_FF) || \
lypinator 0:bb348c97df44 229 ((FLAG) == ETH_DMATXDESC_PCE) || \
lypinator 0:bb348c97df44 230 ((FLAG) == ETH_DMATXDESC_LCA) || \
lypinator 0:bb348c97df44 231 ((FLAG) == ETH_DMATXDESC_NC) || \
lypinator 0:bb348c97df44 232 ((FLAG) == ETH_DMATXDESC_LCO) || \
lypinator 0:bb348c97df44 233 ((FLAG) == ETH_DMATXDESC_EC) || \
lypinator 0:bb348c97df44 234 ((FLAG) == ETH_DMATXDESC_VF) || \
lypinator 0:bb348c97df44 235 ((FLAG) == ETH_DMATXDESC_CC) || \
lypinator 0:bb348c97df44 236 ((FLAG) == ETH_DMATXDESC_ED) || \
lypinator 0:bb348c97df44 237 ((FLAG) == ETH_DMATXDESC_UF) || \
lypinator 0:bb348c97df44 238 ((FLAG) == ETH_DMATXDESC_DB))
lypinator 0:bb348c97df44 239 #define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATXDESC_LASTSEGMENTS) || \
lypinator 0:bb348c97df44 240 ((SEGMENT) == ETH_DMATXDESC_FIRSTSEGMENT))
lypinator 0:bb348c97df44 241 #define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM) (((CHECKSUM) == ETH_DMATXDESC_CHECKSUMBYPASS) || \
lypinator 0:bb348c97df44 242 ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMIPV4HEADER) || \
lypinator 0:bb348c97df44 243 ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT) || \
lypinator 0:bb348c97df44 244 ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL))
lypinator 0:bb348c97df44 245 #define IS_ETH_DMATXDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFFU)
lypinator 0:bb348c97df44 246 #define IS_ETH_DMARXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMARXDESC_OWN) || \
lypinator 0:bb348c97df44 247 ((FLAG) == ETH_DMARXDESC_AFM) || \
lypinator 0:bb348c97df44 248 ((FLAG) == ETH_DMARXDESC_ES) || \
lypinator 0:bb348c97df44 249 ((FLAG) == ETH_DMARXDESC_DE) || \
lypinator 0:bb348c97df44 250 ((FLAG) == ETH_DMARXDESC_SAF) || \
lypinator 0:bb348c97df44 251 ((FLAG) == ETH_DMARXDESC_LE) || \
lypinator 0:bb348c97df44 252 ((FLAG) == ETH_DMARXDESC_OE) || \
lypinator 0:bb348c97df44 253 ((FLAG) == ETH_DMARXDESC_VLAN) || \
lypinator 0:bb348c97df44 254 ((FLAG) == ETH_DMARXDESC_FS) || \
lypinator 0:bb348c97df44 255 ((FLAG) == ETH_DMARXDESC_LS) || \
lypinator 0:bb348c97df44 256 ((FLAG) == ETH_DMARXDESC_IPV4HCE) || \
lypinator 0:bb348c97df44 257 ((FLAG) == ETH_DMARXDESC_LC) || \
lypinator 0:bb348c97df44 258 ((FLAG) == ETH_DMARXDESC_FT) || \
lypinator 0:bb348c97df44 259 ((FLAG) == ETH_DMARXDESC_RWT) || \
lypinator 0:bb348c97df44 260 ((FLAG) == ETH_DMARXDESC_RE) || \
lypinator 0:bb348c97df44 261 ((FLAG) == ETH_DMARXDESC_DBE) || \
lypinator 0:bb348c97df44 262 ((FLAG) == ETH_DMARXDESC_CE) || \
lypinator 0:bb348c97df44 263 ((FLAG) == ETH_DMARXDESC_MAMPCE))
lypinator 0:bb348c97df44 264 #define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARXDESC_BUFFER1) || \
lypinator 0:bb348c97df44 265 ((BUFFER) == ETH_DMARXDESC_BUFFER2))
lypinator 0:bb348c97df44 266 #define IS_ETH_PMT_GET_FLAG(FLAG) (((FLAG) == ETH_PMT_FLAG_WUFR) || \
lypinator 0:bb348c97df44 267 ((FLAG) == ETH_PMT_FLAG_MPR))
lypinator 0:bb348c97df44 268 #define IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & 0xC7FE1800U) == 0x00U) && ((FLAG) != 0x00U))
lypinator 0:bb348c97df44 269 #define IS_ETH_DMA_GET_FLAG(FLAG) (((FLAG) == ETH_DMA_FLAG_TST) || ((FLAG) == ETH_DMA_FLAG_PMT) || \
lypinator 0:bb348c97df44 270 ((FLAG) == ETH_DMA_FLAG_MMC) || ((FLAG) == ETH_DMA_FLAG_DATATRANSFERERROR) || \
lypinator 0:bb348c97df44 271 ((FLAG) == ETH_DMA_FLAG_READWRITEERROR) || ((FLAG) == ETH_DMA_FLAG_ACCESSERROR) || \
lypinator 0:bb348c97df44 272 ((FLAG) == ETH_DMA_FLAG_NIS) || ((FLAG) == ETH_DMA_FLAG_AIS) || \
lypinator 0:bb348c97df44 273 ((FLAG) == ETH_DMA_FLAG_ER) || ((FLAG) == ETH_DMA_FLAG_FBE) || \
lypinator 0:bb348c97df44 274 ((FLAG) == ETH_DMA_FLAG_ET) || ((FLAG) == ETH_DMA_FLAG_RWT) || \
lypinator 0:bb348c97df44 275 ((FLAG) == ETH_DMA_FLAG_RPS) || ((FLAG) == ETH_DMA_FLAG_RBU) || \
lypinator 0:bb348c97df44 276 ((FLAG) == ETH_DMA_FLAG_R) || ((FLAG) == ETH_DMA_FLAG_TU) || \
lypinator 0:bb348c97df44 277 ((FLAG) == ETH_DMA_FLAG_RO) || ((FLAG) == ETH_DMA_FLAG_TJT) || \
lypinator 0:bb348c97df44 278 ((FLAG) == ETH_DMA_FLAG_TBU) || ((FLAG) == ETH_DMA_FLAG_TPS) || \
lypinator 0:bb348c97df44 279 ((FLAG) == ETH_DMA_FLAG_T))
lypinator 0:bb348c97df44 280 #define IS_ETH_MAC_IT(IT) ((((IT) & 0xFFFFFDF1U) == 0x00U) && ((IT) != 0x00U))
lypinator 0:bb348c97df44 281 #define IS_ETH_MAC_GET_IT(IT) (((IT) == ETH_MAC_IT_TST) || ((IT) == ETH_MAC_IT_MMCT) || \
lypinator 0:bb348c97df44 282 ((IT) == ETH_MAC_IT_MMCR) || ((IT) == ETH_MAC_IT_MMC) || \
lypinator 0:bb348c97df44 283 ((IT) == ETH_MAC_IT_PMT))
lypinator 0:bb348c97df44 284 #define IS_ETH_MAC_GET_FLAG(FLAG) (((FLAG) == ETH_MAC_FLAG_TST) || ((FLAG) == ETH_MAC_FLAG_MMCT) || \
lypinator 0:bb348c97df44 285 ((FLAG) == ETH_MAC_FLAG_MMCR) || ((FLAG) == ETH_MAC_FLAG_MMC) || \
lypinator 0:bb348c97df44 286 ((FLAG) == ETH_MAC_FLAG_PMT))
lypinator 0:bb348c97df44 287 #define IS_ETH_DMA_IT(IT) ((((IT) & 0xC7FE1800U) == 0x00U) && ((IT) != 0x00U))
lypinator 0:bb348c97df44 288 #define IS_ETH_DMA_GET_IT(IT) (((IT) == ETH_DMA_IT_TST) || ((IT) == ETH_DMA_IT_PMT) || \
lypinator 0:bb348c97df44 289 ((IT) == ETH_DMA_IT_MMC) || ((IT) == ETH_DMA_IT_NIS) || \
lypinator 0:bb348c97df44 290 ((IT) == ETH_DMA_IT_AIS) || ((IT) == ETH_DMA_IT_ER) || \
lypinator 0:bb348c97df44 291 ((IT) == ETH_DMA_IT_FBE) || ((IT) == ETH_DMA_IT_ET) || \
lypinator 0:bb348c97df44 292 ((IT) == ETH_DMA_IT_RWT) || ((IT) == ETH_DMA_IT_RPS) || \
lypinator 0:bb348c97df44 293 ((IT) == ETH_DMA_IT_RBU) || ((IT) == ETH_DMA_IT_R) || \
lypinator 0:bb348c97df44 294 ((IT) == ETH_DMA_IT_TU) || ((IT) == ETH_DMA_IT_RO) || \
lypinator 0:bb348c97df44 295 ((IT) == ETH_DMA_IT_TJT) || ((IT) == ETH_DMA_IT_TBU) || \
lypinator 0:bb348c97df44 296 ((IT) == ETH_DMA_IT_TPS) || ((IT) == ETH_DMA_IT_T))
lypinator 0:bb348c97df44 297 #define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_OVERFLOW_RXFIFOCOUNTER) || \
lypinator 0:bb348c97df44 298 ((OVERFLOW) == ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER))
lypinator 0:bb348c97df44 299 #define IS_ETH_MMC_IT(IT) (((((IT) & 0xFFDF3FFFU) == 0x00U) || (((IT) & 0xEFFDFF9FU) == 0x00U)) && \
lypinator 0:bb348c97df44 300 ((IT) != 0x00U))
lypinator 0:bb348c97df44 301 #define IS_ETH_MMC_GET_IT(IT) (((IT) == ETH_MMC_IT_TGF) || ((IT) == ETH_MMC_IT_TGFMSC) || \
lypinator 0:bb348c97df44 302 ((IT) == ETH_MMC_IT_TGFSC) || ((IT) == ETH_MMC_IT_RGUF) || \
lypinator 0:bb348c97df44 303 ((IT) == ETH_MMC_IT_RFAE) || ((IT) == ETH_MMC_IT_RFCE))
lypinator 0:bb348c97df44 304 #define IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(CMD) (((CMD) == ETH_DMAENHANCEDDESCRIPTOR_ENABLE) || \
lypinator 0:bb348c97df44 305 ((CMD) == ETH_DMAENHANCEDDESCRIPTOR_DISABLE))
lypinator 0:bb348c97df44 306
lypinator 0:bb348c97df44 307 /**
lypinator 0:bb348c97df44 308 * @}
lypinator 0:bb348c97df44 309 */
lypinator 0:bb348c97df44 310
lypinator 0:bb348c97df44 311 /** @addtogroup ETH_Private_Defines
lypinator 0:bb348c97df44 312 * @{
lypinator 0:bb348c97df44 313 */
lypinator 0:bb348c97df44 314 /* Delay to wait when writing to some Ethernet registers */
lypinator 0:bb348c97df44 315 #define ETH_REG_WRITE_DELAY 0x00000001U
lypinator 0:bb348c97df44 316
lypinator 0:bb348c97df44 317 /* ETHERNET Errors */
lypinator 0:bb348c97df44 318 #define ETH_SUCCESS 0U
lypinator 0:bb348c97df44 319 #define ETH_ERROR 1U
lypinator 0:bb348c97df44 320
lypinator 0:bb348c97df44 321 /* ETHERNET DMA Tx descriptors Collision Count Shift */
lypinator 0:bb348c97df44 322 #define ETH_DMATXDESC_COLLISION_COUNTSHIFT 3U
lypinator 0:bb348c97df44 323
lypinator 0:bb348c97df44 324 /* ETHERNET DMA Tx descriptors Buffer2 Size Shift */
lypinator 0:bb348c97df44 325 #define ETH_DMATXDESC_BUFFER2_SIZESHIFT 16U
lypinator 0:bb348c97df44 326
lypinator 0:bb348c97df44 327 /* ETHERNET DMA Rx descriptors Frame Length Shift */
lypinator 0:bb348c97df44 328 #define ETH_DMARXDESC_FRAME_LENGTHSHIFT 16U
lypinator 0:bb348c97df44 329
lypinator 0:bb348c97df44 330 /* ETHERNET DMA Rx descriptors Buffer2 Size Shift */
lypinator 0:bb348c97df44 331 #define ETH_DMARXDESC_BUFFER2_SIZESHIFT 16U
lypinator 0:bb348c97df44 332
lypinator 0:bb348c97df44 333 /* ETHERNET DMA Rx descriptors Frame length Shift */
lypinator 0:bb348c97df44 334 #define ETH_DMARXDESC_FRAMELENGTHSHIFT 16U
lypinator 0:bb348c97df44 335
lypinator 0:bb348c97df44 336 /* ETHERNET MAC address offsets */
lypinator 0:bb348c97df44 337 #define ETH_MAC_ADDR_HBASE (uint32_t)(ETH_MAC_BASE + 0x40U) /* ETHERNET MAC address high offset */
lypinator 0:bb348c97df44 338 #define ETH_MAC_ADDR_LBASE (uint32_t)(ETH_MAC_BASE + 0x44U) /* ETHERNET MAC address low offset */
lypinator 0:bb348c97df44 339
lypinator 0:bb348c97df44 340 /* ETHERNET MACMIIAR register Mask */
lypinator 0:bb348c97df44 341 #define ETH_MACMIIAR_CR_MASK 0xFFFFFFE3U
lypinator 0:bb348c97df44 342
lypinator 0:bb348c97df44 343 /* ETHERNET MACCR register Mask */
lypinator 0:bb348c97df44 344 #define ETH_MACCR_CLEAR_MASK 0xFF20810FU
lypinator 0:bb348c97df44 345
lypinator 0:bb348c97df44 346 /* ETHERNET MACFCR register Mask */
lypinator 0:bb348c97df44 347 #define ETH_MACFCR_CLEAR_MASK 0x0000FF41U
lypinator 0:bb348c97df44 348
lypinator 0:bb348c97df44 349 /* ETHERNET DMAOMR register Mask */
lypinator 0:bb348c97df44 350 #define ETH_DMAOMR_CLEAR_MASK 0xF8DE3F23U
lypinator 0:bb348c97df44 351
lypinator 0:bb348c97df44 352 /* ETHERNET Remote Wake-up frame register length */
lypinator 0:bb348c97df44 353 #define ETH_WAKEUP_REGISTER_LENGTH 8U
lypinator 0:bb348c97df44 354
lypinator 0:bb348c97df44 355 /* ETHERNET Missed frames counter Shift */
lypinator 0:bb348c97df44 356 #define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17U
lypinator 0:bb348c97df44 357 /**
lypinator 0:bb348c97df44 358 * @}
lypinator 0:bb348c97df44 359 */
lypinator 0:bb348c97df44 360
lypinator 0:bb348c97df44 361 /* Exported types ------------------------------------------------------------*/
lypinator 0:bb348c97df44 362 /** @defgroup ETH_Exported_Types ETH Exported Types
lypinator 0:bb348c97df44 363 * @{
lypinator 0:bb348c97df44 364 */
lypinator 0:bb348c97df44 365
lypinator 0:bb348c97df44 366 /**
lypinator 0:bb348c97df44 367 * @brief HAL State structures definition
lypinator 0:bb348c97df44 368 */
lypinator 0:bb348c97df44 369 typedef enum
lypinator 0:bb348c97df44 370 {
lypinator 0:bb348c97df44 371 HAL_ETH_STATE_RESET = 0x00U, /*!< Peripheral not yet Initialized or disabled */
lypinator 0:bb348c97df44 372 HAL_ETH_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
lypinator 0:bb348c97df44 373 HAL_ETH_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */
lypinator 0:bb348c97df44 374 HAL_ETH_STATE_BUSY_TX = 0x12U, /*!< Data Transmission process is ongoing */
lypinator 0:bb348c97df44 375 HAL_ETH_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */
lypinator 0:bb348c97df44 376 HAL_ETH_STATE_BUSY_TX_RX = 0x32U, /*!< Data Transmission and Reception process is ongoing */
lypinator 0:bb348c97df44 377 HAL_ETH_STATE_BUSY_WR = 0x42U, /*!< Write process is ongoing */
lypinator 0:bb348c97df44 378 HAL_ETH_STATE_BUSY_RD = 0x82U, /*!< Read process is ongoing */
lypinator 0:bb348c97df44 379 HAL_ETH_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
lypinator 0:bb348c97df44 380 HAL_ETH_STATE_ERROR = 0x04U /*!< Reception process is ongoing */
lypinator 0:bb348c97df44 381 }HAL_ETH_StateTypeDef;
lypinator 0:bb348c97df44 382
lypinator 0:bb348c97df44 383 /**
lypinator 0:bb348c97df44 384 * @brief ETH Init Structure definition
lypinator 0:bb348c97df44 385 */
lypinator 0:bb348c97df44 386
lypinator 0:bb348c97df44 387 typedef struct
lypinator 0:bb348c97df44 388 {
lypinator 0:bb348c97df44 389 uint32_t AutoNegotiation; /*!< Selects or not the AutoNegotiation mode for the external PHY
lypinator 0:bb348c97df44 390 The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps)
lypinator 0:bb348c97df44 391 and the mode (half/full-duplex).
lypinator 0:bb348c97df44 392 This parameter can be a value of @ref ETH_AutoNegotiation */
lypinator 0:bb348c97df44 393
lypinator 0:bb348c97df44 394 uint32_t Speed; /*!< Sets the Ethernet speed: 10/100 Mbps.
lypinator 0:bb348c97df44 395 This parameter can be a value of @ref ETH_Speed */
lypinator 0:bb348c97df44 396
lypinator 0:bb348c97df44 397 uint32_t DuplexMode; /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode
lypinator 0:bb348c97df44 398 This parameter can be a value of @ref ETH_Duplex_Mode */
lypinator 0:bb348c97df44 399
lypinator 0:bb348c97df44 400 uint16_t PhyAddress; /*!< Ethernet PHY address.
lypinator 0:bb348c97df44 401 This parameter must be a number between Min_Data = 0 and Max_Data = 32 */
lypinator 0:bb348c97df44 402
lypinator 0:bb348c97df44 403 uint8_t *MACAddr; /*!< MAC Address of used Hardware: must be pointer on an array of 6 bytes */
lypinator 0:bb348c97df44 404
lypinator 0:bb348c97df44 405 uint32_t RxMode; /*!< Selects the Ethernet Rx mode: Polling mode, Interrupt mode.
lypinator 0:bb348c97df44 406 This parameter can be a value of @ref ETH_Rx_Mode */
lypinator 0:bb348c97df44 407
lypinator 0:bb348c97df44 408 uint32_t ChecksumMode; /*!< Selects if the checksum is check by hardware or by software.
lypinator 0:bb348c97df44 409 This parameter can be a value of @ref ETH_Checksum_Mode */
lypinator 0:bb348c97df44 410
lypinator 0:bb348c97df44 411 uint32_t MediaInterface; /*!< Selects the media-independent interface or the reduced media-independent interface.
lypinator 0:bb348c97df44 412 This parameter can be a value of @ref ETH_Media_Interface */
lypinator 0:bb348c97df44 413
lypinator 0:bb348c97df44 414 } ETH_InitTypeDef;
lypinator 0:bb348c97df44 415
lypinator 0:bb348c97df44 416
lypinator 0:bb348c97df44 417 /**
lypinator 0:bb348c97df44 418 * @brief ETH MAC Configuration Structure definition
lypinator 0:bb348c97df44 419 */
lypinator 0:bb348c97df44 420
lypinator 0:bb348c97df44 421 typedef struct
lypinator 0:bb348c97df44 422 {
lypinator 0:bb348c97df44 423 uint32_t Watchdog; /*!< Selects or not the Watchdog timer
lypinator 0:bb348c97df44 424 When enabled, the MAC allows no more then 2048 bytes to be received.
lypinator 0:bb348c97df44 425 When disabled, the MAC can receive up to 16384 bytes.
lypinator 0:bb348c97df44 426 This parameter can be a value of @ref ETH_Watchdog */
lypinator 0:bb348c97df44 427
lypinator 0:bb348c97df44 428 uint32_t Jabber; /*!< Selects or not Jabber timer
lypinator 0:bb348c97df44 429 When enabled, the MAC allows no more then 2048 bytes to be sent.
lypinator 0:bb348c97df44 430 When disabled, the MAC can send up to 16384 bytes.
lypinator 0:bb348c97df44 431 This parameter can be a value of @ref ETH_Jabber */
lypinator 0:bb348c97df44 432
lypinator 0:bb348c97df44 433 uint32_t InterFrameGap; /*!< Selects the minimum IFG between frames during transmission.
lypinator 0:bb348c97df44 434 This parameter can be a value of @ref ETH_Inter_Frame_Gap */
lypinator 0:bb348c97df44 435
lypinator 0:bb348c97df44 436 uint32_t CarrierSense; /*!< Selects or not the Carrier Sense.
lypinator 0:bb348c97df44 437 This parameter can be a value of @ref ETH_Carrier_Sense */
lypinator 0:bb348c97df44 438
lypinator 0:bb348c97df44 439 uint32_t ReceiveOwn; /*!< Selects or not the ReceiveOwn,
lypinator 0:bb348c97df44 440 ReceiveOwn allows the reception of frames when the TX_EN signal is asserted
lypinator 0:bb348c97df44 441 in Half-Duplex mode.
lypinator 0:bb348c97df44 442 This parameter can be a value of @ref ETH_Receive_Own */
lypinator 0:bb348c97df44 443
lypinator 0:bb348c97df44 444 uint32_t LoopbackMode; /*!< Selects or not the internal MAC MII Loopback mode.
lypinator 0:bb348c97df44 445 This parameter can be a value of @ref ETH_Loop_Back_Mode */
lypinator 0:bb348c97df44 446
lypinator 0:bb348c97df44 447 uint32_t ChecksumOffload; /*!< Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers.
lypinator 0:bb348c97df44 448 This parameter can be a value of @ref ETH_Checksum_Offload */
lypinator 0:bb348c97df44 449
lypinator 0:bb348c97df44 450 uint32_t RetryTransmission; /*!< Selects or not the MAC attempt retries transmission, based on the settings of BL,
lypinator 0:bb348c97df44 451 when a collision occurs (Half-Duplex mode).
lypinator 0:bb348c97df44 452 This parameter can be a value of @ref ETH_Retry_Transmission */
lypinator 0:bb348c97df44 453
lypinator 0:bb348c97df44 454 uint32_t AutomaticPadCRCStrip; /*!< Selects or not the Automatic MAC Pad/CRC Stripping.
lypinator 0:bb348c97df44 455 This parameter can be a value of @ref ETH_Automatic_Pad_CRC_Strip */
lypinator 0:bb348c97df44 456
lypinator 0:bb348c97df44 457 uint32_t BackOffLimit; /*!< Selects the BackOff limit value.
lypinator 0:bb348c97df44 458 This parameter can be a value of @ref ETH_Back_Off_Limit */
lypinator 0:bb348c97df44 459
lypinator 0:bb348c97df44 460 uint32_t DeferralCheck; /*!< Selects or not the deferral check function (Half-Duplex mode).
lypinator 0:bb348c97df44 461 This parameter can be a value of @ref ETH_Deferral_Check */
lypinator 0:bb348c97df44 462
lypinator 0:bb348c97df44 463 uint32_t ReceiveAll; /*!< Selects or not all frames reception by the MAC (No filtering).
lypinator 0:bb348c97df44 464 This parameter can be a value of @ref ETH_Receive_All */
lypinator 0:bb348c97df44 465
lypinator 0:bb348c97df44 466 uint32_t SourceAddrFilter; /*!< Selects the Source Address Filter mode.
lypinator 0:bb348c97df44 467 This parameter can be a value of @ref ETH_Source_Addr_Filter */
lypinator 0:bb348c97df44 468
lypinator 0:bb348c97df44 469 uint32_t PassControlFrames; /*!< Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames)
lypinator 0:bb348c97df44 470 This parameter can be a value of @ref ETH_Pass_Control_Frames */
lypinator 0:bb348c97df44 471
lypinator 0:bb348c97df44 472 uint32_t BroadcastFramesReception; /*!< Selects or not the reception of Broadcast Frames.
lypinator 0:bb348c97df44 473 This parameter can be a value of @ref ETH_Broadcast_Frames_Reception */
lypinator 0:bb348c97df44 474
lypinator 0:bb348c97df44 475 uint32_t DestinationAddrFilter; /*!< Sets the destination filter mode for both unicast and multicast frames.
lypinator 0:bb348c97df44 476 This parameter can be a value of @ref ETH_Destination_Addr_Filter */
lypinator 0:bb348c97df44 477
lypinator 0:bb348c97df44 478 uint32_t PromiscuousMode; /*!< Selects or not the Promiscuous Mode
lypinator 0:bb348c97df44 479 This parameter can be a value of @ref ETH_Promiscuous_Mode */
lypinator 0:bb348c97df44 480
lypinator 0:bb348c97df44 481 uint32_t MulticastFramesFilter; /*!< Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter.
lypinator 0:bb348c97df44 482 This parameter can be a value of @ref ETH_Multicast_Frames_Filter */
lypinator 0:bb348c97df44 483
lypinator 0:bb348c97df44 484 uint32_t UnicastFramesFilter; /*!< Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter.
lypinator 0:bb348c97df44 485 This parameter can be a value of @ref ETH_Unicast_Frames_Filter */
lypinator 0:bb348c97df44 486
lypinator 0:bb348c97df44 487 uint32_t HashTableHigh; /*!< This field holds the higher 32 bits of Hash table.
lypinator 0:bb348c97df44 488 This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFFU */
lypinator 0:bb348c97df44 489
lypinator 0:bb348c97df44 490 uint32_t HashTableLow; /*!< This field holds the lower 32 bits of Hash table.
lypinator 0:bb348c97df44 491 This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFFU */
lypinator 0:bb348c97df44 492
lypinator 0:bb348c97df44 493 uint32_t PauseTime; /*!< This field holds the value to be used in the Pause Time field in the transmit control frame.
lypinator 0:bb348c97df44 494 This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFU */
lypinator 0:bb348c97df44 495
lypinator 0:bb348c97df44 496 uint32_t ZeroQuantaPause; /*!< Selects or not the automatic generation of Zero-Quanta Pause Control frames.
lypinator 0:bb348c97df44 497 This parameter can be a value of @ref ETH_Zero_Quanta_Pause */
lypinator 0:bb348c97df44 498
lypinator 0:bb348c97df44 499 uint32_t PauseLowThreshold; /*!< This field configures the threshold of the PAUSE to be checked for
lypinator 0:bb348c97df44 500 automatic retransmission of PAUSE Frame.
lypinator 0:bb348c97df44 501 This parameter can be a value of @ref ETH_Pause_Low_Threshold */
lypinator 0:bb348c97df44 502
lypinator 0:bb348c97df44 503 uint32_t UnicastPauseFrameDetect; /*!< Selects or not the MAC detection of the Pause frames (with MAC Address0
lypinator 0:bb348c97df44 504 unicast address and unique multicast address).
lypinator 0:bb348c97df44 505 This parameter can be a value of @ref ETH_Unicast_Pause_Frame_Detect */
lypinator 0:bb348c97df44 506
lypinator 0:bb348c97df44 507 uint32_t ReceiveFlowControl; /*!< Enables or disables the MAC to decode the received Pause frame and
lypinator 0:bb348c97df44 508 disable its transmitter for a specified time (Pause Time)
lypinator 0:bb348c97df44 509 This parameter can be a value of @ref ETH_Receive_Flow_Control */
lypinator 0:bb348c97df44 510
lypinator 0:bb348c97df44 511 uint32_t TransmitFlowControl; /*!< Enables or disables the MAC to transmit Pause frames (Full-Duplex mode)
lypinator 0:bb348c97df44 512 or the MAC back-pressure operation (Half-Duplex mode)
lypinator 0:bb348c97df44 513 This parameter can be a value of @ref ETH_Transmit_Flow_Control */
lypinator 0:bb348c97df44 514
lypinator 0:bb348c97df44 515 uint32_t VLANTagComparison; /*!< Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for
lypinator 0:bb348c97df44 516 comparison and filtering.
lypinator 0:bb348c97df44 517 This parameter can be a value of @ref ETH_VLAN_Tag_Comparison */
lypinator 0:bb348c97df44 518
lypinator 0:bb348c97df44 519 uint32_t VLANTagIdentifier; /*!< Holds the VLAN tag identifier for receive frames */
lypinator 0:bb348c97df44 520
lypinator 0:bb348c97df44 521 } ETH_MACInitTypeDef;
lypinator 0:bb348c97df44 522
lypinator 0:bb348c97df44 523 /**
lypinator 0:bb348c97df44 524 * @brief ETH DMA Configuration Structure definition
lypinator 0:bb348c97df44 525 */
lypinator 0:bb348c97df44 526
lypinator 0:bb348c97df44 527 typedef struct
lypinator 0:bb348c97df44 528 {
lypinator 0:bb348c97df44 529 uint32_t DropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames.
lypinator 0:bb348c97df44 530 This parameter can be a value of @ref ETH_Drop_TCP_IP_Checksum_Error_Frame */
lypinator 0:bb348c97df44 531
lypinator 0:bb348c97df44 532 uint32_t ReceiveStoreForward; /*!< Enables or disables the Receive store and forward mode.
lypinator 0:bb348c97df44 533 This parameter can be a value of @ref ETH_Receive_Store_Forward */
lypinator 0:bb348c97df44 534
lypinator 0:bb348c97df44 535 uint32_t FlushReceivedFrame; /*!< Enables or disables the flushing of received frames.
lypinator 0:bb348c97df44 536 This parameter can be a value of @ref ETH_Flush_Received_Frame */
lypinator 0:bb348c97df44 537
lypinator 0:bb348c97df44 538 uint32_t TransmitStoreForward; /*!< Enables or disables Transmit store and forward mode.
lypinator 0:bb348c97df44 539 This parameter can be a value of @ref ETH_Transmit_Store_Forward */
lypinator 0:bb348c97df44 540
lypinator 0:bb348c97df44 541 uint32_t TransmitThresholdControl; /*!< Selects or not the Transmit Threshold Control.
lypinator 0:bb348c97df44 542 This parameter can be a value of @ref ETH_Transmit_Threshold_Control */
lypinator 0:bb348c97df44 543
lypinator 0:bb348c97df44 544 uint32_t ForwardErrorFrames; /*!< Selects or not the forward to the DMA of erroneous frames.
lypinator 0:bb348c97df44 545 This parameter can be a value of @ref ETH_Forward_Error_Frames */
lypinator 0:bb348c97df44 546
lypinator 0:bb348c97df44 547 uint32_t ForwardUndersizedGoodFrames; /*!< Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error
lypinator 0:bb348c97df44 548 and length less than 64 bytes) including pad-bytes and CRC)
lypinator 0:bb348c97df44 549 This parameter can be a value of @ref ETH_Forward_Undersized_Good_Frames */
lypinator 0:bb348c97df44 550
lypinator 0:bb348c97df44 551 uint32_t ReceiveThresholdControl; /*!< Selects the threshold level of the Receive FIFO.
lypinator 0:bb348c97df44 552 This parameter can be a value of @ref ETH_Receive_Threshold_Control */
lypinator 0:bb348c97df44 553
lypinator 0:bb348c97df44 554 uint32_t SecondFrameOperate; /*!< Selects or not the Operate on second frame mode, which allows the DMA to process a second
lypinator 0:bb348c97df44 555 frame of Transmit data even before obtaining the status for the first frame.
lypinator 0:bb348c97df44 556 This parameter can be a value of @ref ETH_Second_Frame_Operate */
lypinator 0:bb348c97df44 557
lypinator 0:bb348c97df44 558 uint32_t AddressAlignedBeats; /*!< Enables or disables the Address Aligned Beats.
lypinator 0:bb348c97df44 559 This parameter can be a value of @ref ETH_Address_Aligned_Beats */
lypinator 0:bb348c97df44 560
lypinator 0:bb348c97df44 561 uint32_t FixedBurst; /*!< Enables or disables the AHB Master interface fixed burst transfers.
lypinator 0:bb348c97df44 562 This parameter can be a value of @ref ETH_Fixed_Burst */
lypinator 0:bb348c97df44 563
lypinator 0:bb348c97df44 564 uint32_t RxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction.
lypinator 0:bb348c97df44 565 This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */
lypinator 0:bb348c97df44 566
lypinator 0:bb348c97df44 567 uint32_t TxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction.
lypinator 0:bb348c97df44 568 This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */
lypinator 0:bb348c97df44 569
lypinator 0:bb348c97df44 570 uint32_t EnhancedDescriptorFormat; /*!< Enables the enhanced descriptor format.
lypinator 0:bb348c97df44 571 This parameter can be a value of @ref ETH_DMA_Enhanced_descriptor_format */
lypinator 0:bb348c97df44 572
lypinator 0:bb348c97df44 573 uint32_t DescriptorSkipLength; /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode)
lypinator 0:bb348c97df44 574 This parameter must be a number between Min_Data = 0 and Max_Data = 32 */
lypinator 0:bb348c97df44 575
lypinator 0:bb348c97df44 576 uint32_t DMAArbitration; /*!< Selects the DMA Tx/Rx arbitration.
lypinator 0:bb348c97df44 577 This parameter can be a value of @ref ETH_DMA_Arbitration */
lypinator 0:bb348c97df44 578 } ETH_DMAInitTypeDef;
lypinator 0:bb348c97df44 579
lypinator 0:bb348c97df44 580
lypinator 0:bb348c97df44 581 /**
lypinator 0:bb348c97df44 582 * @brief ETH DMA Descriptors data structure definition
lypinator 0:bb348c97df44 583 */
lypinator 0:bb348c97df44 584
lypinator 0:bb348c97df44 585 typedef struct
lypinator 0:bb348c97df44 586 {
lypinator 0:bb348c97df44 587 __IO uint32_t Status; /*!< Status */
lypinator 0:bb348c97df44 588
lypinator 0:bb348c97df44 589 uint32_t ControlBufferSize; /*!< Control and Buffer1, Buffer2 lengths */
lypinator 0:bb348c97df44 590
lypinator 0:bb348c97df44 591 uint32_t Buffer1Addr; /*!< Buffer1 address pointer */
lypinator 0:bb348c97df44 592
lypinator 0:bb348c97df44 593 uint32_t Buffer2NextDescAddr; /*!< Buffer2 or next descriptor address pointer */
lypinator 0:bb348c97df44 594
lypinator 0:bb348c97df44 595 /*!< Enhanced ETHERNET DMA PTP Descriptors */
lypinator 0:bb348c97df44 596 uint32_t ExtendedStatus; /*!< Extended status for PTP receive descriptor */
lypinator 0:bb348c97df44 597
lypinator 0:bb348c97df44 598 uint32_t Reserved1; /*!< Reserved */
lypinator 0:bb348c97df44 599
lypinator 0:bb348c97df44 600 uint32_t TimeStampLow; /*!< Time Stamp Low value for transmit and receive */
lypinator 0:bb348c97df44 601
lypinator 0:bb348c97df44 602 uint32_t TimeStampHigh; /*!< Time Stamp High value for transmit and receive */
lypinator 0:bb348c97df44 603
lypinator 0:bb348c97df44 604 } ETH_DMADescTypeDef;
lypinator 0:bb348c97df44 605
lypinator 0:bb348c97df44 606 /**
lypinator 0:bb348c97df44 607 * @brief Received Frame Informations structure definition
lypinator 0:bb348c97df44 608 */
lypinator 0:bb348c97df44 609 typedef struct
lypinator 0:bb348c97df44 610 {
lypinator 0:bb348c97df44 611 ETH_DMADescTypeDef *FSRxDesc; /*!< First Segment Rx Desc */
lypinator 0:bb348c97df44 612
lypinator 0:bb348c97df44 613 ETH_DMADescTypeDef *LSRxDesc; /*!< Last Segment Rx Desc */
lypinator 0:bb348c97df44 614
lypinator 0:bb348c97df44 615 uint32_t SegCount; /*!< Segment count */
lypinator 0:bb348c97df44 616
lypinator 0:bb348c97df44 617 uint32_t length; /*!< Frame length */
lypinator 0:bb348c97df44 618
lypinator 0:bb348c97df44 619 uint32_t buffer; /*!< Frame buffer */
lypinator 0:bb348c97df44 620
lypinator 0:bb348c97df44 621 } ETH_DMARxFrameInfos;
lypinator 0:bb348c97df44 622
lypinator 0:bb348c97df44 623 /**
lypinator 0:bb348c97df44 624 * @brief ETH Handle Structure definition
lypinator 0:bb348c97df44 625 */
lypinator 0:bb348c97df44 626
lypinator 0:bb348c97df44 627 typedef struct
lypinator 0:bb348c97df44 628 {
lypinator 0:bb348c97df44 629 ETH_TypeDef *Instance; /*!< Register base address */
lypinator 0:bb348c97df44 630
lypinator 0:bb348c97df44 631 ETH_InitTypeDef Init; /*!< Ethernet Init Configuration */
lypinator 0:bb348c97df44 632
lypinator 0:bb348c97df44 633 uint32_t LinkStatus; /*!< Ethernet link status */
lypinator 0:bb348c97df44 634
lypinator 0:bb348c97df44 635 ETH_DMADescTypeDef *RxDesc; /*!< Rx descriptor to Get */
lypinator 0:bb348c97df44 636
lypinator 0:bb348c97df44 637 ETH_DMADescTypeDef *TxDesc; /*!< Tx descriptor to Set */
lypinator 0:bb348c97df44 638
lypinator 0:bb348c97df44 639 ETH_DMARxFrameInfos RxFrameInfos; /*!< last Rx frame infos */
lypinator 0:bb348c97df44 640
lypinator 0:bb348c97df44 641 __IO HAL_ETH_StateTypeDef State; /*!< ETH communication state */
lypinator 0:bb348c97df44 642
lypinator 0:bb348c97df44 643 HAL_LockTypeDef Lock; /*!< ETH Lock */
lypinator 0:bb348c97df44 644
lypinator 0:bb348c97df44 645 } ETH_HandleTypeDef;
lypinator 0:bb348c97df44 646
lypinator 0:bb348c97df44 647 /**
lypinator 0:bb348c97df44 648 * @}
lypinator 0:bb348c97df44 649 */
lypinator 0:bb348c97df44 650
lypinator 0:bb348c97df44 651 /* Exported constants --------------------------------------------------------*/
lypinator 0:bb348c97df44 652 /** @defgroup ETH_Exported_Constants ETH Exported Constants
lypinator 0:bb348c97df44 653 * @{
lypinator 0:bb348c97df44 654 */
lypinator 0:bb348c97df44 655
lypinator 0:bb348c97df44 656 /** @defgroup ETH_Buffers_setting ETH Buffers setting
lypinator 0:bb348c97df44 657 * @{
lypinator 0:bb348c97df44 658 */
lypinator 0:bb348c97df44 659 #define ETH_MAX_PACKET_SIZE 1524U /*!< ETH_HEADER + ETH_EXTRA + ETH_VLAN_TAG + ETH_MAX_ETH_PAYLOAD + ETH_CRC */
lypinator 0:bb348c97df44 660 #define ETH_HEADER 14U /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */
lypinator 0:bb348c97df44 661 #define ETH_CRC 4U /*!< Ethernet CRC */
lypinator 0:bb348c97df44 662 #define ETH_EXTRA 2U /*!< Extra bytes in some cases */
lypinator 0:bb348c97df44 663 #define ETH_VLAN_TAG 4U /*!< optional 802.1q VLAN Tag */
lypinator 0:bb348c97df44 664 #define ETH_MIN_ETH_PAYLOAD 46U /*!< Minimum Ethernet payload size */
lypinator 0:bb348c97df44 665 #define ETH_MAX_ETH_PAYLOAD 1500U /*!< Maximum Ethernet payload size */
lypinator 0:bb348c97df44 666 #define ETH_JUMBO_FRAME_PAYLOAD 9000U /*!< Jumbo frame payload size */
lypinator 0:bb348c97df44 667
lypinator 0:bb348c97df44 668 /* Ethernet driver receive buffers are organized in a chained linked-list, when
lypinator 0:bb348c97df44 669 an ethernet packet is received, the Rx-DMA will transfer the packet from RxFIFO
lypinator 0:bb348c97df44 670 to the driver receive buffers memory.
lypinator 0:bb348c97df44 671
lypinator 0:bb348c97df44 672 Depending on the size of the received ethernet packet and the size of
lypinator 0:bb348c97df44 673 each ethernet driver receive buffer, the received packet can take one or more
lypinator 0:bb348c97df44 674 ethernet driver receive buffer.
lypinator 0:bb348c97df44 675
lypinator 0:bb348c97df44 676 In below are defined the size of one ethernet driver receive buffer ETH_RX_BUF_SIZE
lypinator 0:bb348c97df44 677 and the total count of the driver receive buffers ETH_RXBUFNB.
lypinator 0:bb348c97df44 678
lypinator 0:bb348c97df44 679 The configured value for ETH_RX_BUF_SIZE and ETH_RXBUFNB are only provided as
lypinator 0:bb348c97df44 680 example, they can be reconfigured in the application layer to fit the application
lypinator 0:bb348c97df44 681 needs */
lypinator 0:bb348c97df44 682
lypinator 0:bb348c97df44 683 /* Here we configure each Ethernet driver receive buffer to fit the Max size Ethernet
lypinator 0:bb348c97df44 684 packet */
lypinator 0:bb348c97df44 685 #ifndef ETH_RX_BUF_SIZE
lypinator 0:bb348c97df44 686 #define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE
lypinator 0:bb348c97df44 687 #endif
lypinator 0:bb348c97df44 688
lypinator 0:bb348c97df44 689 /* 5 Ethernet driver receive buffers are used (in a chained linked list)*/
lypinator 0:bb348c97df44 690 #ifndef ETH_RXBUFNB
lypinator 0:bb348c97df44 691 #define ETH_RXBUFNB 5U /* 5 Rx buffers of size ETH_RX_BUF_SIZE */
lypinator 0:bb348c97df44 692 #endif
lypinator 0:bb348c97df44 693
lypinator 0:bb348c97df44 694
lypinator 0:bb348c97df44 695 /* Ethernet driver transmit buffers are organized in a chained linked-list, when
lypinator 0:bb348c97df44 696 an ethernet packet is transmitted, Tx-DMA will transfer the packet from the
lypinator 0:bb348c97df44 697 driver transmit buffers memory to the TxFIFO.
lypinator 0:bb348c97df44 698
lypinator 0:bb348c97df44 699 Depending on the size of the Ethernet packet to be transmitted and the size of
lypinator 0:bb348c97df44 700 each ethernet driver transmit buffer, the packet to be transmitted can take
lypinator 0:bb348c97df44 701 one or more ethernet driver transmit buffer.
lypinator 0:bb348c97df44 702
lypinator 0:bb348c97df44 703 In below are defined the size of one ethernet driver transmit buffer ETH_TX_BUF_SIZE
lypinator 0:bb348c97df44 704 and the total count of the driver transmit buffers ETH_TXBUFNB.
lypinator 0:bb348c97df44 705
lypinator 0:bb348c97df44 706 The configured value for ETH_TX_BUF_SIZE and ETH_TXBUFNB are only provided as
lypinator 0:bb348c97df44 707 example, they can be reconfigured in the application layer to fit the application
lypinator 0:bb348c97df44 708 needs */
lypinator 0:bb348c97df44 709
lypinator 0:bb348c97df44 710 /* Here we configure each Ethernet driver transmit buffer to fit the Max size Ethernet
lypinator 0:bb348c97df44 711 packet */
lypinator 0:bb348c97df44 712 #ifndef ETH_TX_BUF_SIZE
lypinator 0:bb348c97df44 713 #define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE
lypinator 0:bb348c97df44 714 #endif
lypinator 0:bb348c97df44 715
lypinator 0:bb348c97df44 716 /* 5 ethernet driver transmit buffers are used (in a chained linked list)*/
lypinator 0:bb348c97df44 717 #ifndef ETH_TXBUFNB
lypinator 0:bb348c97df44 718 #define ETH_TXBUFNB 5U /* 5 Tx buffers of size ETH_TX_BUF_SIZE */
lypinator 0:bb348c97df44 719 #endif
lypinator 0:bb348c97df44 720
lypinator 0:bb348c97df44 721 /**
lypinator 0:bb348c97df44 722 * @}
lypinator 0:bb348c97df44 723 */
lypinator 0:bb348c97df44 724
lypinator 0:bb348c97df44 725 /** @defgroup ETH_DMA_TX_Descriptor ETH DMA TX Descriptor
lypinator 0:bb348c97df44 726 * @{
lypinator 0:bb348c97df44 727 */
lypinator 0:bb348c97df44 728
lypinator 0:bb348c97df44 729 /*
lypinator 0:bb348c97df44 730 DMA Tx Descriptor
lypinator 0:bb348c97df44 731 -----------------------------------------------------------------------------------------------
lypinator 0:bb348c97df44 732 TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] |
lypinator 0:bb348c97df44 733 -----------------------------------------------------------------------------------------------
lypinator 0:bb348c97df44 734 TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 ByteCount[12:0] |
lypinator 0:bb348c97df44 735 -----------------------------------------------------------------------------------------------
lypinator 0:bb348c97df44 736 TDES2 | Buffer1 Address [31:0] |
lypinator 0:bb348c97df44 737 -----------------------------------------------------------------------------------------------
lypinator 0:bb348c97df44 738 TDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] |
lypinator 0:bb348c97df44 739 -----------------------------------------------------------------------------------------------
lypinator 0:bb348c97df44 740 */
lypinator 0:bb348c97df44 741
lypinator 0:bb348c97df44 742 /**
lypinator 0:bb348c97df44 743 * @brief Bit definition of TDES0 register: DMA Tx descriptor status register
lypinator 0:bb348c97df44 744 */
lypinator 0:bb348c97df44 745 #define ETH_DMATXDESC_OWN 0x80000000U /*!< OWN bit: descriptor is owned by DMA engine */
lypinator 0:bb348c97df44 746 #define ETH_DMATXDESC_IC 0x40000000U /*!< Interrupt on Completion */
lypinator 0:bb348c97df44 747 #define ETH_DMATXDESC_LS 0x20000000U /*!< Last Segment */
lypinator 0:bb348c97df44 748 #define ETH_DMATXDESC_FS 0x10000000U /*!< First Segment */
lypinator 0:bb348c97df44 749 #define ETH_DMATXDESC_DC 0x08000000U /*!< Disable CRC */
lypinator 0:bb348c97df44 750 #define ETH_DMATXDESC_DP 0x04000000U /*!< Disable Padding */
lypinator 0:bb348c97df44 751 #define ETH_DMATXDESC_TTSE 0x02000000U /*!< Transmit Time Stamp Enable */
lypinator 0:bb348c97df44 752 #define ETH_DMATXDESC_CIC 0x00C00000U /*!< Checksum Insertion Control: 4 cases */
lypinator 0:bb348c97df44 753 #define ETH_DMATXDESC_CIC_BYPASS 0x00000000U /*!< Do Nothing: Checksum Engine is bypassed */
lypinator 0:bb348c97df44 754 #define ETH_DMATXDESC_CIC_IPV4HEADER 0x00400000U /*!< IPV4 header Checksum Insertion */
lypinator 0:bb348c97df44 755 #define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT 0x00800000U /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */
lypinator 0:bb348c97df44 756 #define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL 0x00C00000U /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */
lypinator 0:bb348c97df44 757 #define ETH_DMATXDESC_TER 0x00200000U /*!< Transmit End of Ring */
lypinator 0:bb348c97df44 758 #define ETH_DMATXDESC_TCH 0x00100000U /*!< Second Address Chained */
lypinator 0:bb348c97df44 759 #define ETH_DMATXDESC_TTSS 0x00020000U /*!< Tx Time Stamp Status */
lypinator 0:bb348c97df44 760 #define ETH_DMATXDESC_IHE 0x00010000U /*!< IP Header Error */
lypinator 0:bb348c97df44 761 #define ETH_DMATXDESC_ES 0x00008000U /*!< Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */
lypinator 0:bb348c97df44 762 #define ETH_DMATXDESC_JT 0x00004000U /*!< Jabber Timeout */
lypinator 0:bb348c97df44 763 #define ETH_DMATXDESC_FF 0x00002000U /*!< Frame Flushed: DMA/MTL flushed the frame due to SW flush */
lypinator 0:bb348c97df44 764 #define ETH_DMATXDESC_PCE 0x00001000U /*!< Payload Checksum Error */
lypinator 0:bb348c97df44 765 #define ETH_DMATXDESC_LCA 0x00000800U /*!< Loss of Carrier: carrier lost during transmission */
lypinator 0:bb348c97df44 766 #define ETH_DMATXDESC_NC 0x00000400U /*!< No Carrier: no carrier signal from the transceiver */
lypinator 0:bb348c97df44 767 #define ETH_DMATXDESC_LCO 0x00000200U /*!< Late Collision: transmission aborted due to collision */
lypinator 0:bb348c97df44 768 #define ETH_DMATXDESC_EC 0x00000100U /*!< Excessive Collision: transmission aborted after 16 collisions */
lypinator 0:bb348c97df44 769 #define ETH_DMATXDESC_VF 0x00000080U /*!< VLAN Frame */
lypinator 0:bb348c97df44 770 #define ETH_DMATXDESC_CC 0x00000078U /*!< Collision Count */
lypinator 0:bb348c97df44 771 #define ETH_DMATXDESC_ED 0x00000004U /*!< Excessive Deferral */
lypinator 0:bb348c97df44 772 #define ETH_DMATXDESC_UF 0x00000002U /*!< Underflow Error: late data arrival from the memory */
lypinator 0:bb348c97df44 773 #define ETH_DMATXDESC_DB 0x00000001U /*!< Deferred Bit */
lypinator 0:bb348c97df44 774
lypinator 0:bb348c97df44 775 /**
lypinator 0:bb348c97df44 776 * @brief Bit definition of TDES1 register
lypinator 0:bb348c97df44 777 */
lypinator 0:bb348c97df44 778 #define ETH_DMATXDESC_TBS2 0x1FFF0000U /*!< Transmit Buffer2 Size */
lypinator 0:bb348c97df44 779 #define ETH_DMATXDESC_TBS1 0x00001FFFU /*!< Transmit Buffer1 Size */
lypinator 0:bb348c97df44 780
lypinator 0:bb348c97df44 781 /**
lypinator 0:bb348c97df44 782 * @brief Bit definition of TDES2 register
lypinator 0:bb348c97df44 783 */
lypinator 0:bb348c97df44 784 #define ETH_DMATXDESC_B1AP 0xFFFFFFFFU /*!< Buffer1 Address Pointer */
lypinator 0:bb348c97df44 785
lypinator 0:bb348c97df44 786 /**
lypinator 0:bb348c97df44 787 * @brief Bit definition of TDES3 register
lypinator 0:bb348c97df44 788 */
lypinator 0:bb348c97df44 789 #define ETH_DMATXDESC_B2AP 0xFFFFFFFFU /*!< Buffer2 Address Pointer */
lypinator 0:bb348c97df44 790
lypinator 0:bb348c97df44 791 /*---------------------------------------------------------------------------------------------
lypinator 0:bb348c97df44 792 TDES6 | Transmit Time Stamp Low [31:0] |
lypinator 0:bb348c97df44 793 -----------------------------------------------------------------------------------------------
lypinator 0:bb348c97df44 794 TDES7 | Transmit Time Stamp High [31:0] |
lypinator 0:bb348c97df44 795 ----------------------------------------------------------------------------------------------*/
lypinator 0:bb348c97df44 796
lypinator 0:bb348c97df44 797 /* Bit definition of TDES6 register */
lypinator 0:bb348c97df44 798 #define ETH_DMAPTPTXDESC_TTSL 0xFFFFFFFFU /* Transmit Time Stamp Low */
lypinator 0:bb348c97df44 799
lypinator 0:bb348c97df44 800 /* Bit definition of TDES7 register */
lypinator 0:bb348c97df44 801 #define ETH_DMAPTPTXDESC_TTSH 0xFFFFFFFFU /* Transmit Time Stamp High */
lypinator 0:bb348c97df44 802
lypinator 0:bb348c97df44 803 /**
lypinator 0:bb348c97df44 804 * @}
lypinator 0:bb348c97df44 805 */
lypinator 0:bb348c97df44 806 /** @defgroup ETH_DMA_RX_Descriptor ETH DMA RX Descriptor
lypinator 0:bb348c97df44 807 * @{
lypinator 0:bb348c97df44 808 */
lypinator 0:bb348c97df44 809
lypinator 0:bb348c97df44 810 /*
lypinator 0:bb348c97df44 811 DMA Rx Descriptor
lypinator 0:bb348c97df44 812 --------------------------------------------------------------------------------------------------------------------
lypinator 0:bb348c97df44 813 RDES0 | OWN(31) | Status [30:0] |
lypinator 0:bb348c97df44 814 ---------------------------------------------------------------------------------------------------------------------
lypinator 0:bb348c97df44 815 RDES1 | CTRL(31) | Reserved[30:29] | Buffer2 ByteCount[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 ByteCount[12:0] |
lypinator 0:bb348c97df44 816 ---------------------------------------------------------------------------------------------------------------------
lypinator 0:bb348c97df44 817 RDES2 | Buffer1 Address [31:0] |
lypinator 0:bb348c97df44 818 ---------------------------------------------------------------------------------------------------------------------
lypinator 0:bb348c97df44 819 RDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] |
lypinator 0:bb348c97df44 820 ---------------------------------------------------------------------------------------------------------------------
lypinator 0:bb348c97df44 821 */
lypinator 0:bb348c97df44 822
lypinator 0:bb348c97df44 823 /**
lypinator 0:bb348c97df44 824 * @brief Bit definition of RDES0 register: DMA Rx descriptor status register
lypinator 0:bb348c97df44 825 */
lypinator 0:bb348c97df44 826 #define ETH_DMARXDESC_OWN 0x80000000U /*!< OWN bit: descriptor is owned by DMA engine */
lypinator 0:bb348c97df44 827 #define ETH_DMARXDESC_AFM 0x40000000U /*!< DA Filter Fail for the rx frame */
lypinator 0:bb348c97df44 828 #define ETH_DMARXDESC_FL 0x3FFF0000U /*!< Receive descriptor frame length */
lypinator 0:bb348c97df44 829 #define ETH_DMARXDESC_ES 0x00008000U /*!< Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */
lypinator 0:bb348c97df44 830 #define ETH_DMARXDESC_DE 0x00004000U /*!< Descriptor error: no more descriptors for receive frame */
lypinator 0:bb348c97df44 831 #define ETH_DMARXDESC_SAF 0x00002000U /*!< SA Filter Fail for the received frame */
lypinator 0:bb348c97df44 832 #define ETH_DMARXDESC_LE 0x00001000U /*!< Frame size not matching with length field */
lypinator 0:bb348c97df44 833 #define ETH_DMARXDESC_OE 0x00000800U /*!< Overflow Error: Frame was damaged due to buffer overflow */
lypinator 0:bb348c97df44 834 #define ETH_DMARXDESC_VLAN 0x00000400U /*!< VLAN Tag: received frame is a VLAN frame */
lypinator 0:bb348c97df44 835 #define ETH_DMARXDESC_FS 0x00000200U /*!< First descriptor of the frame */
lypinator 0:bb348c97df44 836 #define ETH_DMARXDESC_LS 0x00000100U /*!< Last descriptor of the frame */
lypinator 0:bb348c97df44 837 #define ETH_DMARXDESC_IPV4HCE 0x00000080U /*!< IPC Checksum Error: Rx Ipv4 header checksum error */
lypinator 0:bb348c97df44 838 #define ETH_DMARXDESC_LC 0x00000040U /*!< Late collision occurred during reception */
lypinator 0:bb348c97df44 839 #define ETH_DMARXDESC_FT 0x00000020U /*!< Frame type - Ethernet, otherwise 802.3 */
lypinator 0:bb348c97df44 840 #define ETH_DMARXDESC_RWT 0x00000010U /*!< Receive Watchdog Timeout: watchdog timer expired during reception */
lypinator 0:bb348c97df44 841 #define ETH_DMARXDESC_RE 0x00000008U /*!< Receive error: error reported by MII interface */
lypinator 0:bb348c97df44 842 #define ETH_DMARXDESC_DBE 0x00000004U /*!< Dribble bit error: frame contains non int multiple of 8 bits */
lypinator 0:bb348c97df44 843 #define ETH_DMARXDESC_CE 0x00000002U /*!< CRC error */
lypinator 0:bb348c97df44 844 #define ETH_DMARXDESC_MAMPCE 0x00000001U /*!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */
lypinator 0:bb348c97df44 845
lypinator 0:bb348c97df44 846 /**
lypinator 0:bb348c97df44 847 * @brief Bit definition of RDES1 register
lypinator 0:bb348c97df44 848 */
lypinator 0:bb348c97df44 849 #define ETH_DMARXDESC_DIC 0x80000000U /*!< Disable Interrupt on Completion */
lypinator 0:bb348c97df44 850 #define ETH_DMARXDESC_RBS2 0x1FFF0000U /*!< Receive Buffer2 Size */
lypinator 0:bb348c97df44 851 #define ETH_DMARXDESC_RER 0x00008000U /*!< Receive End of Ring */
lypinator 0:bb348c97df44 852 #define ETH_DMARXDESC_RCH 0x00004000U /*!< Second Address Chained */
lypinator 0:bb348c97df44 853 #define ETH_DMARXDESC_RBS1 0x00001FFFU /*!< Receive Buffer1 Size */
lypinator 0:bb348c97df44 854
lypinator 0:bb348c97df44 855 /**
lypinator 0:bb348c97df44 856 * @brief Bit definition of RDES2 register
lypinator 0:bb348c97df44 857 */
lypinator 0:bb348c97df44 858 #define ETH_DMARXDESC_B1AP 0xFFFFFFFFU /*!< Buffer1 Address Pointer */
lypinator 0:bb348c97df44 859
lypinator 0:bb348c97df44 860 /**
lypinator 0:bb348c97df44 861 * @brief Bit definition of RDES3 register
lypinator 0:bb348c97df44 862 */
lypinator 0:bb348c97df44 863 #define ETH_DMARXDESC_B2AP 0xFFFFFFFFU /*!< Buffer2 Address Pointer */
lypinator 0:bb348c97df44 864
lypinator 0:bb348c97df44 865 /*---------------------------------------------------------------------------------------------------------------------
lypinator 0:bb348c97df44 866 RDES4 | Reserved[31:15] | Extended Status [14:0] |
lypinator 0:bb348c97df44 867 ---------------------------------------------------------------------------------------------------------------------
lypinator 0:bb348c97df44 868 RDES5 | Reserved[31:0] |
lypinator 0:bb348c97df44 869 ---------------------------------------------------------------------------------------------------------------------
lypinator 0:bb348c97df44 870 RDES6 | Receive Time Stamp Low [31:0] |
lypinator 0:bb348c97df44 871 ---------------------------------------------------------------------------------------------------------------------
lypinator 0:bb348c97df44 872 RDES7 | Receive Time Stamp High [31:0] |
lypinator 0:bb348c97df44 873 --------------------------------------------------------------------------------------------------------------------*/
lypinator 0:bb348c97df44 874
lypinator 0:bb348c97df44 875 /* Bit definition of RDES4 register */
lypinator 0:bb348c97df44 876 #define ETH_DMAPTPRXDESC_PTPV 0x00002000U /* PTP Version */
lypinator 0:bb348c97df44 877 #define ETH_DMAPTPRXDESC_PTPFT 0x00001000U /* PTP Frame Type */
lypinator 0:bb348c97df44 878 #define ETH_DMAPTPRXDESC_PTPMT 0x00000F00U /* PTP Message Type */
lypinator 0:bb348c97df44 879 #define ETH_DMAPTPRXDESC_PTPMT_SYNC 0x00000100U /* SYNC message (all clock types) */
lypinator 0:bb348c97df44 880 #define ETH_DMAPTPRXDESC_PTPMT_FOLLOWUP 0x00000200U /* FollowUp message (all clock types) */
lypinator 0:bb348c97df44 881 #define ETH_DMAPTPRXDESC_PTPMT_DELAYREQ 0x00000300U /* DelayReq message (all clock types) */
lypinator 0:bb348c97df44 882 #define ETH_DMAPTPRXDESC_PTPMT_DELAYRESP 0x00000400U /* DelayResp message (all clock types) */
lypinator 0:bb348c97df44 883 #define ETH_DMAPTPRXDESC_PTPMT_PDELAYREQ_ANNOUNCE 0x00000500U /* PdelayReq message (peer-to-peer transparent clock) or Announce message (Ordinary or Boundary clock) */
lypinator 0:bb348c97df44 884 #define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESP_MANAG 0x00000600U /* PdelayResp message (peer-to-peer transparent clock) or Management message (Ordinary or Boundary clock) */
lypinator 0:bb348c97df44 885 #define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESPFOLLOWUP_SIGNAL 0x00000700U /* PdelayRespFollowUp message (peer-to-peer transparent clock) or Signaling message (Ordinary or Boundary clock) */
lypinator 0:bb348c97df44 886 #define ETH_DMAPTPRXDESC_IPV6PR 0x00000080U /* IPv6 Packet Received */
lypinator 0:bb348c97df44 887 #define ETH_DMAPTPRXDESC_IPV4PR 0x00000040U /* IPv4 Packet Received */
lypinator 0:bb348c97df44 888 #define ETH_DMAPTPRXDESC_IPCB 0x00000020U /* IP Checksum Bypassed */
lypinator 0:bb348c97df44 889 #define ETH_DMAPTPRXDESC_IPPE 0x00000010U /* IP Payload Error */
lypinator 0:bb348c97df44 890 #define ETH_DMAPTPRXDESC_IPHE 0x00000008U /* IP Header Error */
lypinator 0:bb348c97df44 891 #define ETH_DMAPTPRXDESC_IPPT 0x00000007U /* IP Payload Type */
lypinator 0:bb348c97df44 892 #define ETH_DMAPTPRXDESC_IPPT_UDP 0x00000001U /* UDP payload encapsulated in the IP datagram */
lypinator 0:bb348c97df44 893 #define ETH_DMAPTPRXDESC_IPPT_TCP 0x00000002U /* TCP payload encapsulated in the IP datagram */
lypinator 0:bb348c97df44 894 #define ETH_DMAPTPRXDESC_IPPT_ICMP 0x00000003U /* ICMP payload encapsulated in the IP datagram */
lypinator 0:bb348c97df44 895
lypinator 0:bb348c97df44 896 /* Bit definition of RDES6 register */
lypinator 0:bb348c97df44 897 #define ETH_DMAPTPRXDESC_RTSL 0xFFFFFFFFU /* Receive Time Stamp Low */
lypinator 0:bb348c97df44 898
lypinator 0:bb348c97df44 899 /* Bit definition of RDES7 register */
lypinator 0:bb348c97df44 900 #define ETH_DMAPTPRXDESC_RTSH 0xFFFFFFFFU /* Receive Time Stamp High */
lypinator 0:bb348c97df44 901 /**
lypinator 0:bb348c97df44 902 * @}
lypinator 0:bb348c97df44 903 */
lypinator 0:bb348c97df44 904 /** @defgroup ETH_AutoNegotiation ETH AutoNegotiation
lypinator 0:bb348c97df44 905 * @{
lypinator 0:bb348c97df44 906 */
lypinator 0:bb348c97df44 907 #define ETH_AUTONEGOTIATION_ENABLE 0x00000001U
lypinator 0:bb348c97df44 908 #define ETH_AUTONEGOTIATION_DISABLE 0x00000000U
lypinator 0:bb348c97df44 909
lypinator 0:bb348c97df44 910 /**
lypinator 0:bb348c97df44 911 * @}
lypinator 0:bb348c97df44 912 */
lypinator 0:bb348c97df44 913 /** @defgroup ETH_Speed ETH Speed
lypinator 0:bb348c97df44 914 * @{
lypinator 0:bb348c97df44 915 */
lypinator 0:bb348c97df44 916 #define ETH_SPEED_10M 0x00000000U
lypinator 0:bb348c97df44 917 #define ETH_SPEED_100M 0x00004000U
lypinator 0:bb348c97df44 918
lypinator 0:bb348c97df44 919 /**
lypinator 0:bb348c97df44 920 * @}
lypinator 0:bb348c97df44 921 */
lypinator 0:bb348c97df44 922 /** @defgroup ETH_Duplex_Mode ETH Duplex Mode
lypinator 0:bb348c97df44 923 * @{
lypinator 0:bb348c97df44 924 */
lypinator 0:bb348c97df44 925 #define ETH_MODE_FULLDUPLEX 0x00000800U
lypinator 0:bb348c97df44 926 #define ETH_MODE_HALFDUPLEX 0x00000000U
lypinator 0:bb348c97df44 927 /**
lypinator 0:bb348c97df44 928 * @}
lypinator 0:bb348c97df44 929 */
lypinator 0:bb348c97df44 930 /** @defgroup ETH_Rx_Mode ETH Rx Mode
lypinator 0:bb348c97df44 931 * @{
lypinator 0:bb348c97df44 932 */
lypinator 0:bb348c97df44 933 #define ETH_RXPOLLING_MODE 0x00000000U
lypinator 0:bb348c97df44 934 #define ETH_RXINTERRUPT_MODE 0x00000001U
lypinator 0:bb348c97df44 935 /**
lypinator 0:bb348c97df44 936 * @}
lypinator 0:bb348c97df44 937 */
lypinator 0:bb348c97df44 938
lypinator 0:bb348c97df44 939 /** @defgroup ETH_Checksum_Mode ETH Checksum Mode
lypinator 0:bb348c97df44 940 * @{
lypinator 0:bb348c97df44 941 */
lypinator 0:bb348c97df44 942 #define ETH_CHECKSUM_BY_HARDWARE 0x00000000U
lypinator 0:bb348c97df44 943 #define ETH_CHECKSUM_BY_SOFTWARE 0x00000001U
lypinator 0:bb348c97df44 944 /**
lypinator 0:bb348c97df44 945 * @}
lypinator 0:bb348c97df44 946 */
lypinator 0:bb348c97df44 947
lypinator 0:bb348c97df44 948 /** @defgroup ETH_Media_Interface ETH Media Interface
lypinator 0:bb348c97df44 949 * @{
lypinator 0:bb348c97df44 950 */
lypinator 0:bb348c97df44 951 #define ETH_MEDIA_INTERFACE_MII 0x00000000U
lypinator 0:bb348c97df44 952 #define ETH_MEDIA_INTERFACE_RMII ((uint32_t)SYSCFG_PMC_MII_RMII_SEL)
lypinator 0:bb348c97df44 953 /**
lypinator 0:bb348c97df44 954 * @}
lypinator 0:bb348c97df44 955 */
lypinator 0:bb348c97df44 956
lypinator 0:bb348c97df44 957 /** @defgroup ETH_Watchdog ETH Watchdog
lypinator 0:bb348c97df44 958 * @{
lypinator 0:bb348c97df44 959 */
lypinator 0:bb348c97df44 960 #define ETH_WATCHDOG_ENABLE 0x00000000U
lypinator 0:bb348c97df44 961 #define ETH_WATCHDOG_DISABLE 0x00800000U
lypinator 0:bb348c97df44 962 /**
lypinator 0:bb348c97df44 963 * @}
lypinator 0:bb348c97df44 964 */
lypinator 0:bb348c97df44 965
lypinator 0:bb348c97df44 966 /** @defgroup ETH_Jabber ETH Jabber
lypinator 0:bb348c97df44 967 * @{
lypinator 0:bb348c97df44 968 */
lypinator 0:bb348c97df44 969 #define ETH_JABBER_ENABLE 0x00000000U
lypinator 0:bb348c97df44 970 #define ETH_JABBER_DISABLE 0x00400000U
lypinator 0:bb348c97df44 971 /**
lypinator 0:bb348c97df44 972 * @}
lypinator 0:bb348c97df44 973 */
lypinator 0:bb348c97df44 974
lypinator 0:bb348c97df44 975 /** @defgroup ETH_Inter_Frame_Gap ETH Inter Frame Gap
lypinator 0:bb348c97df44 976 * @{
lypinator 0:bb348c97df44 977 */
lypinator 0:bb348c97df44 978 #define ETH_INTERFRAMEGAP_96BIT 0x00000000U /*!< minimum IFG between frames during transmission is 96Bit */
lypinator 0:bb348c97df44 979 #define ETH_INTERFRAMEGAP_88BIT 0x00020000U /*!< minimum IFG between frames during transmission is 88Bit */
lypinator 0:bb348c97df44 980 #define ETH_INTERFRAMEGAP_80BIT 0x00040000U /*!< minimum IFG between frames during transmission is 80Bit */
lypinator 0:bb348c97df44 981 #define ETH_INTERFRAMEGAP_72BIT 0x00060000U /*!< minimum IFG between frames during transmission is 72Bit */
lypinator 0:bb348c97df44 982 #define ETH_INTERFRAMEGAP_64BIT 0x00080000U /*!< minimum IFG between frames during transmission is 64Bit */
lypinator 0:bb348c97df44 983 #define ETH_INTERFRAMEGAP_56BIT 0x000A0000U /*!< minimum IFG between frames during transmission is 56Bit */
lypinator 0:bb348c97df44 984 #define ETH_INTERFRAMEGAP_48BIT 0x000C0000U /*!< minimum IFG between frames during transmission is 48Bit */
lypinator 0:bb348c97df44 985 #define ETH_INTERFRAMEGAP_40BIT 0x000E0000U /*!< minimum IFG between frames during transmission is 40Bit */
lypinator 0:bb348c97df44 986 /**
lypinator 0:bb348c97df44 987 * @}
lypinator 0:bb348c97df44 988 */
lypinator 0:bb348c97df44 989
lypinator 0:bb348c97df44 990 /** @defgroup ETH_Carrier_Sense ETH Carrier Sense
lypinator 0:bb348c97df44 991 * @{
lypinator 0:bb348c97df44 992 */
lypinator 0:bb348c97df44 993 #define ETH_CARRIERSENCE_ENABLE 0x00000000U
lypinator 0:bb348c97df44 994 #define ETH_CARRIERSENCE_DISABLE 0x00010000U
lypinator 0:bb348c97df44 995 /**
lypinator 0:bb348c97df44 996 * @}
lypinator 0:bb348c97df44 997 */
lypinator 0:bb348c97df44 998
lypinator 0:bb348c97df44 999 /** @defgroup ETH_Receive_Own ETH Receive Own
lypinator 0:bb348c97df44 1000 * @{
lypinator 0:bb348c97df44 1001 */
lypinator 0:bb348c97df44 1002 #define ETH_RECEIVEOWN_ENABLE 0x00000000U
lypinator 0:bb348c97df44 1003 #define ETH_RECEIVEOWN_DISABLE 0x00002000U
lypinator 0:bb348c97df44 1004 /**
lypinator 0:bb348c97df44 1005 * @}
lypinator 0:bb348c97df44 1006 */
lypinator 0:bb348c97df44 1007
lypinator 0:bb348c97df44 1008 /** @defgroup ETH_Loop_Back_Mode ETH Loop Back Mode
lypinator 0:bb348c97df44 1009 * @{
lypinator 0:bb348c97df44 1010 */
lypinator 0:bb348c97df44 1011 #define ETH_LOOPBACKMODE_ENABLE 0x00001000U
lypinator 0:bb348c97df44 1012 #define ETH_LOOPBACKMODE_DISABLE 0x00000000U
lypinator 0:bb348c97df44 1013 /**
lypinator 0:bb348c97df44 1014 * @}
lypinator 0:bb348c97df44 1015 */
lypinator 0:bb348c97df44 1016
lypinator 0:bb348c97df44 1017 /** @defgroup ETH_Checksum_Offload ETH Checksum Offload
lypinator 0:bb348c97df44 1018 * @{
lypinator 0:bb348c97df44 1019 */
lypinator 0:bb348c97df44 1020 #define ETH_CHECKSUMOFFLAOD_ENABLE 0x00000400U
lypinator 0:bb348c97df44 1021 #define ETH_CHECKSUMOFFLAOD_DISABLE 0x00000000U
lypinator 0:bb348c97df44 1022 /**
lypinator 0:bb348c97df44 1023 * @}
lypinator 0:bb348c97df44 1024 */
lypinator 0:bb348c97df44 1025
lypinator 0:bb348c97df44 1026 /** @defgroup ETH_Retry_Transmission ETH Retry Transmission
lypinator 0:bb348c97df44 1027 * @{
lypinator 0:bb348c97df44 1028 */
lypinator 0:bb348c97df44 1029 #define ETH_RETRYTRANSMISSION_ENABLE 0x00000000U
lypinator 0:bb348c97df44 1030 #define ETH_RETRYTRANSMISSION_DISABLE 0x00000200U
lypinator 0:bb348c97df44 1031 /**
lypinator 0:bb348c97df44 1032 * @}
lypinator 0:bb348c97df44 1033 */
lypinator 0:bb348c97df44 1034
lypinator 0:bb348c97df44 1035 /** @defgroup ETH_Automatic_Pad_CRC_Strip ETH Automatic Pad CRC Strip
lypinator 0:bb348c97df44 1036 * @{
lypinator 0:bb348c97df44 1037 */
lypinator 0:bb348c97df44 1038 #define ETH_AUTOMATICPADCRCSTRIP_ENABLE 0x00000080U
lypinator 0:bb348c97df44 1039 #define ETH_AUTOMATICPADCRCSTRIP_DISABLE 0x00000000U
lypinator 0:bb348c97df44 1040 /**
lypinator 0:bb348c97df44 1041 * @}
lypinator 0:bb348c97df44 1042 */
lypinator 0:bb348c97df44 1043
lypinator 0:bb348c97df44 1044 /** @defgroup ETH_Back_Off_Limit ETH Back Off Limit
lypinator 0:bb348c97df44 1045 * @{
lypinator 0:bb348c97df44 1046 */
lypinator 0:bb348c97df44 1047 #define ETH_BACKOFFLIMIT_10 0x00000000U
lypinator 0:bb348c97df44 1048 #define ETH_BACKOFFLIMIT_8 0x00000020U
lypinator 0:bb348c97df44 1049 #define ETH_BACKOFFLIMIT_4 0x00000040U
lypinator 0:bb348c97df44 1050 #define ETH_BACKOFFLIMIT_1 0x00000060U
lypinator 0:bb348c97df44 1051 /**
lypinator 0:bb348c97df44 1052 * @}
lypinator 0:bb348c97df44 1053 */
lypinator 0:bb348c97df44 1054
lypinator 0:bb348c97df44 1055 /** @defgroup ETH_Deferral_Check ETH Deferral Check
lypinator 0:bb348c97df44 1056 * @{
lypinator 0:bb348c97df44 1057 */
lypinator 0:bb348c97df44 1058 #define ETH_DEFFERRALCHECK_ENABLE 0x00000010U
lypinator 0:bb348c97df44 1059 #define ETH_DEFFERRALCHECK_DISABLE 0x00000000U
lypinator 0:bb348c97df44 1060 /**
lypinator 0:bb348c97df44 1061 * @}
lypinator 0:bb348c97df44 1062 */
lypinator 0:bb348c97df44 1063
lypinator 0:bb348c97df44 1064 /** @defgroup ETH_Receive_All ETH Receive All
lypinator 0:bb348c97df44 1065 * @{
lypinator 0:bb348c97df44 1066 */
lypinator 0:bb348c97df44 1067 #define ETH_RECEIVEALL_ENABLE 0x80000000U
lypinator 0:bb348c97df44 1068 #define ETH_RECEIVEAll_DISABLE 0x00000000U
lypinator 0:bb348c97df44 1069 /**
lypinator 0:bb348c97df44 1070 * @}
lypinator 0:bb348c97df44 1071 */
lypinator 0:bb348c97df44 1072
lypinator 0:bb348c97df44 1073 /** @defgroup ETH_Source_Addr_Filter ETH Source Addr Filter
lypinator 0:bb348c97df44 1074 * @{
lypinator 0:bb348c97df44 1075 */
lypinator 0:bb348c97df44 1076 #define ETH_SOURCEADDRFILTER_NORMAL_ENABLE 0x00000200U
lypinator 0:bb348c97df44 1077 #define ETH_SOURCEADDRFILTER_INVERSE_ENABLE 0x00000300U
lypinator 0:bb348c97df44 1078 #define ETH_SOURCEADDRFILTER_DISABLE 0x00000000U
lypinator 0:bb348c97df44 1079 /**
lypinator 0:bb348c97df44 1080 * @}
lypinator 0:bb348c97df44 1081 */
lypinator 0:bb348c97df44 1082
lypinator 0:bb348c97df44 1083 /** @defgroup ETH_Pass_Control_Frames ETH Pass Control Frames
lypinator 0:bb348c97df44 1084 * @{
lypinator 0:bb348c97df44 1085 */
lypinator 0:bb348c97df44 1086 #define ETH_PASSCONTROLFRAMES_BLOCKALL 0x00000040U /*!< MAC filters all control frames from reaching the application */
lypinator 0:bb348c97df44 1087 #define ETH_PASSCONTROLFRAMES_FORWARDALL 0x00000080U /*!< MAC forwards all control frames to application even if they fail the Address Filter */
lypinator 0:bb348c97df44 1088 #define ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER 0x000000C0U /*!< MAC forwards control frames that pass the Address Filter. */
lypinator 0:bb348c97df44 1089 /**
lypinator 0:bb348c97df44 1090 * @}
lypinator 0:bb348c97df44 1091 */
lypinator 0:bb348c97df44 1092
lypinator 0:bb348c97df44 1093 /** @defgroup ETH_Broadcast_Frames_Reception ETH Broadcast Frames Reception
lypinator 0:bb348c97df44 1094 * @{
lypinator 0:bb348c97df44 1095 */
lypinator 0:bb348c97df44 1096 #define ETH_BROADCASTFRAMESRECEPTION_ENABLE 0x00000000U
lypinator 0:bb348c97df44 1097 #define ETH_BROADCASTFRAMESRECEPTION_DISABLE 0x00000020U
lypinator 0:bb348c97df44 1098 /**
lypinator 0:bb348c97df44 1099 * @}
lypinator 0:bb348c97df44 1100 */
lypinator 0:bb348c97df44 1101
lypinator 0:bb348c97df44 1102 /** @defgroup ETH_Destination_Addr_Filter ETH Destination Addr Filter
lypinator 0:bb348c97df44 1103 * @{
lypinator 0:bb348c97df44 1104 */
lypinator 0:bb348c97df44 1105 #define ETH_DESTINATIONADDRFILTER_NORMAL 0x00000000U
lypinator 0:bb348c97df44 1106 #define ETH_DESTINATIONADDRFILTER_INVERSE 0x00000008U
lypinator 0:bb348c97df44 1107 /**
lypinator 0:bb348c97df44 1108 * @}
lypinator 0:bb348c97df44 1109 */
lypinator 0:bb348c97df44 1110
lypinator 0:bb348c97df44 1111 /** @defgroup ETH_Promiscuous_Mode ETH Promiscuous Mode
lypinator 0:bb348c97df44 1112 * @{
lypinator 0:bb348c97df44 1113 */
lypinator 0:bb348c97df44 1114 #define ETH_PROMISCUOUS_MODE_ENABLE 0x00000001U
lypinator 0:bb348c97df44 1115 #define ETH_PROMISCUOUS_MODE_DISABLE 0x00000000U
lypinator 0:bb348c97df44 1116 /**
lypinator 0:bb348c97df44 1117 * @}
lypinator 0:bb348c97df44 1118 */
lypinator 0:bb348c97df44 1119
lypinator 0:bb348c97df44 1120 /** @defgroup ETH_Multicast_Frames_Filter ETH Multicast Frames Filter
lypinator 0:bb348c97df44 1121 * @{
lypinator 0:bb348c97df44 1122 */
lypinator 0:bb348c97df44 1123 #define ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE 0x00000404U
lypinator 0:bb348c97df44 1124 #define ETH_MULTICASTFRAMESFILTER_HASHTABLE 0x00000004U
lypinator 0:bb348c97df44 1125 #define ETH_MULTICASTFRAMESFILTER_PERFECT 0x00000000U
lypinator 0:bb348c97df44 1126 #define ETH_MULTICASTFRAMESFILTER_NONE 0x00000010U
lypinator 0:bb348c97df44 1127 /**
lypinator 0:bb348c97df44 1128 * @}
lypinator 0:bb348c97df44 1129 */
lypinator 0:bb348c97df44 1130
lypinator 0:bb348c97df44 1131 /** @defgroup ETH_Unicast_Frames_Filter ETH Unicast Frames Filter
lypinator 0:bb348c97df44 1132 * @{
lypinator 0:bb348c97df44 1133 */
lypinator 0:bb348c97df44 1134 #define ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE 0x00000402U
lypinator 0:bb348c97df44 1135 #define ETH_UNICASTFRAMESFILTER_HASHTABLE 0x00000002U
lypinator 0:bb348c97df44 1136 #define ETH_UNICASTFRAMESFILTER_PERFECT 0x00000000U
lypinator 0:bb348c97df44 1137 /**
lypinator 0:bb348c97df44 1138 * @}
lypinator 0:bb348c97df44 1139 */
lypinator 0:bb348c97df44 1140
lypinator 0:bb348c97df44 1141 /** @defgroup ETH_Zero_Quanta_Pause ETH Zero Quanta Pause
lypinator 0:bb348c97df44 1142 * @{
lypinator 0:bb348c97df44 1143 */
lypinator 0:bb348c97df44 1144 #define ETH_ZEROQUANTAPAUSE_ENABLE 0x00000000U
lypinator 0:bb348c97df44 1145 #define ETH_ZEROQUANTAPAUSE_DISABLE 0x00000080U
lypinator 0:bb348c97df44 1146 /**
lypinator 0:bb348c97df44 1147 * @}
lypinator 0:bb348c97df44 1148 */
lypinator 0:bb348c97df44 1149
lypinator 0:bb348c97df44 1150 /** @defgroup ETH_Pause_Low_Threshold ETH Pause Low Threshold
lypinator 0:bb348c97df44 1151 * @{
lypinator 0:bb348c97df44 1152 */
lypinator 0:bb348c97df44 1153 #define ETH_PAUSELOWTHRESHOLD_MINUS4 0x00000000U /*!< Pause time minus 4 slot times */
lypinator 0:bb348c97df44 1154 #define ETH_PAUSELOWTHRESHOLD_MINUS28 0x00000010U /*!< Pause time minus 28 slot times */
lypinator 0:bb348c97df44 1155 #define ETH_PAUSELOWTHRESHOLD_MINUS144 0x00000020U /*!< Pause time minus 144 slot times */
lypinator 0:bb348c97df44 1156 #define ETH_PAUSELOWTHRESHOLD_MINUS256 0x00000030U /*!< Pause time minus 256 slot times */
lypinator 0:bb348c97df44 1157 /**
lypinator 0:bb348c97df44 1158 * @}
lypinator 0:bb348c97df44 1159 */
lypinator 0:bb348c97df44 1160
lypinator 0:bb348c97df44 1161 /** @defgroup ETH_Unicast_Pause_Frame_Detect ETH Unicast Pause Frame Detect
lypinator 0:bb348c97df44 1162 * @{
lypinator 0:bb348c97df44 1163 */
lypinator 0:bb348c97df44 1164 #define ETH_UNICASTPAUSEFRAMEDETECT_ENABLE 0x00000008U
lypinator 0:bb348c97df44 1165 #define ETH_UNICASTPAUSEFRAMEDETECT_DISABLE 0x00000000U
lypinator 0:bb348c97df44 1166 /**
lypinator 0:bb348c97df44 1167 * @}
lypinator 0:bb348c97df44 1168 */
lypinator 0:bb348c97df44 1169
lypinator 0:bb348c97df44 1170 /** @defgroup ETH_Receive_Flow_Control ETH Receive Flow Control
lypinator 0:bb348c97df44 1171 * @{
lypinator 0:bb348c97df44 1172 */
lypinator 0:bb348c97df44 1173 #define ETH_RECEIVEFLOWCONTROL_ENABLE 0x00000004U
lypinator 0:bb348c97df44 1174 #define ETH_RECEIVEFLOWCONTROL_DISABLE 0x00000000U
lypinator 0:bb348c97df44 1175 /**
lypinator 0:bb348c97df44 1176 * @}
lypinator 0:bb348c97df44 1177 */
lypinator 0:bb348c97df44 1178
lypinator 0:bb348c97df44 1179 /** @defgroup ETH_Transmit_Flow_Control ETH Transmit Flow Control
lypinator 0:bb348c97df44 1180 * @{
lypinator 0:bb348c97df44 1181 */
lypinator 0:bb348c97df44 1182 #define ETH_TRANSMITFLOWCONTROL_ENABLE 0x00000002U
lypinator 0:bb348c97df44 1183 #define ETH_TRANSMITFLOWCONTROL_DISABLE 0x00000000U
lypinator 0:bb348c97df44 1184 /**
lypinator 0:bb348c97df44 1185 * @}
lypinator 0:bb348c97df44 1186 */
lypinator 0:bb348c97df44 1187
lypinator 0:bb348c97df44 1188 /** @defgroup ETH_VLAN_Tag_Comparison ETH VLAN Tag Comparison
lypinator 0:bb348c97df44 1189 * @{
lypinator 0:bb348c97df44 1190 */
lypinator 0:bb348c97df44 1191 #define ETH_VLANTAGCOMPARISON_12BIT 0x00010000U
lypinator 0:bb348c97df44 1192 #define ETH_VLANTAGCOMPARISON_16BIT 0x00000000U
lypinator 0:bb348c97df44 1193 /**
lypinator 0:bb348c97df44 1194 * @}
lypinator 0:bb348c97df44 1195 */
lypinator 0:bb348c97df44 1196
lypinator 0:bb348c97df44 1197 /** @defgroup ETH_MAC_addresses ETH MAC addresses
lypinator 0:bb348c97df44 1198 * @{
lypinator 0:bb348c97df44 1199 */
lypinator 0:bb348c97df44 1200 #define ETH_MAC_ADDRESS0 0x00000000U
lypinator 0:bb348c97df44 1201 #define ETH_MAC_ADDRESS1 0x00000008U
lypinator 0:bb348c97df44 1202 #define ETH_MAC_ADDRESS2 0x00000010U
lypinator 0:bb348c97df44 1203 #define ETH_MAC_ADDRESS3 0x00000018U
lypinator 0:bb348c97df44 1204 /**
lypinator 0:bb348c97df44 1205 * @}
lypinator 0:bb348c97df44 1206 */
lypinator 0:bb348c97df44 1207
lypinator 0:bb348c97df44 1208 /** @defgroup ETH_MAC_addresses_filter_SA_DA ETH MAC addresses filter SA DA
lypinator 0:bb348c97df44 1209 * @{
lypinator 0:bb348c97df44 1210 */
lypinator 0:bb348c97df44 1211 #define ETH_MAC_ADDRESSFILTER_SA 0x00000000U
lypinator 0:bb348c97df44 1212 #define ETH_MAC_ADDRESSFILTER_DA 0x00000008U
lypinator 0:bb348c97df44 1213 /**
lypinator 0:bb348c97df44 1214 * @}
lypinator 0:bb348c97df44 1215 */
lypinator 0:bb348c97df44 1216
lypinator 0:bb348c97df44 1217 /** @defgroup ETH_MAC_addresses_filter_Mask_bytes ETH MAC addresses filter Mask bytes
lypinator 0:bb348c97df44 1218 * @{
lypinator 0:bb348c97df44 1219 */
lypinator 0:bb348c97df44 1220 #define ETH_MAC_ADDRESSMASK_BYTE6 0x20000000U /*!< Mask MAC Address high reg bits [15:8] */
lypinator 0:bb348c97df44 1221 #define ETH_MAC_ADDRESSMASK_BYTE5 0x10000000U /*!< Mask MAC Address high reg bits [7:0] */
lypinator 0:bb348c97df44 1222 #define ETH_MAC_ADDRESSMASK_BYTE4 0x08000000U /*!< Mask MAC Address low reg bits [31:24] */
lypinator 0:bb348c97df44 1223 #define ETH_MAC_ADDRESSMASK_BYTE3 0x04000000U /*!< Mask MAC Address low reg bits [23:16] */
lypinator 0:bb348c97df44 1224 #define ETH_MAC_ADDRESSMASK_BYTE2 0x02000000U /*!< Mask MAC Address low reg bits [15:8] */
lypinator 0:bb348c97df44 1225 #define ETH_MAC_ADDRESSMASK_BYTE1 0x01000000U /*!< Mask MAC Address low reg bits [70] */
lypinator 0:bb348c97df44 1226 /**
lypinator 0:bb348c97df44 1227 * @}
lypinator 0:bb348c97df44 1228 */
lypinator 0:bb348c97df44 1229
lypinator 0:bb348c97df44 1230 /** @defgroup ETH_Drop_TCP_IP_Checksum_Error_Frame ETH Drop TCP IP Checksum Error Frame
lypinator 0:bb348c97df44 1231 * @{
lypinator 0:bb348c97df44 1232 */
lypinator 0:bb348c97df44 1233 #define ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE 0x00000000U
lypinator 0:bb348c97df44 1234 #define ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE 0x04000000U
lypinator 0:bb348c97df44 1235 /**
lypinator 0:bb348c97df44 1236 * @}
lypinator 0:bb348c97df44 1237 */
lypinator 0:bb348c97df44 1238
lypinator 0:bb348c97df44 1239 /** @defgroup ETH_Receive_Store_Forward ETH Receive Store Forward
lypinator 0:bb348c97df44 1240 * @{
lypinator 0:bb348c97df44 1241 */
lypinator 0:bb348c97df44 1242 #define ETH_RECEIVESTOREFORWARD_ENABLE 0x02000000U
lypinator 0:bb348c97df44 1243 #define ETH_RECEIVESTOREFORWARD_DISABLE 0x00000000U
lypinator 0:bb348c97df44 1244 /**
lypinator 0:bb348c97df44 1245 * @}
lypinator 0:bb348c97df44 1246 */
lypinator 0:bb348c97df44 1247
lypinator 0:bb348c97df44 1248 /** @defgroup ETH_Flush_Received_Frame ETH Flush Received Frame
lypinator 0:bb348c97df44 1249 * @{
lypinator 0:bb348c97df44 1250 */
lypinator 0:bb348c97df44 1251 #define ETH_FLUSHRECEIVEDFRAME_ENABLE 0x00000000U
lypinator 0:bb348c97df44 1252 #define ETH_FLUSHRECEIVEDFRAME_DISABLE 0x01000000U
lypinator 0:bb348c97df44 1253 /**
lypinator 0:bb348c97df44 1254 * @}
lypinator 0:bb348c97df44 1255 */
lypinator 0:bb348c97df44 1256
lypinator 0:bb348c97df44 1257 /** @defgroup ETH_Transmit_Store_Forward ETH Transmit Store Forward
lypinator 0:bb348c97df44 1258 * @{
lypinator 0:bb348c97df44 1259 */
lypinator 0:bb348c97df44 1260 #define ETH_TRANSMITSTOREFORWARD_ENABLE 0x00200000U
lypinator 0:bb348c97df44 1261 #define ETH_TRANSMITSTOREFORWARD_DISABLE 0x00000000U
lypinator 0:bb348c97df44 1262 /**
lypinator 0:bb348c97df44 1263 * @}
lypinator 0:bb348c97df44 1264 */
lypinator 0:bb348c97df44 1265
lypinator 0:bb348c97df44 1266 /** @defgroup ETH_Transmit_Threshold_Control ETH Transmit Threshold Control
lypinator 0:bb348c97df44 1267 * @{
lypinator 0:bb348c97df44 1268 */
lypinator 0:bb348c97df44 1269 #define ETH_TRANSMITTHRESHOLDCONTROL_64BYTES 0x00000000U /*!< threshold level of the MTL Transmit FIFO is 64 Bytes */
lypinator 0:bb348c97df44 1270 #define ETH_TRANSMITTHRESHOLDCONTROL_128BYTES 0x00004000U /*!< threshold level of the MTL Transmit FIFO is 128 Bytes */
lypinator 0:bb348c97df44 1271 #define ETH_TRANSMITTHRESHOLDCONTROL_192BYTES 0x00008000U /*!< threshold level of the MTL Transmit FIFO is 192 Bytes */
lypinator 0:bb348c97df44 1272 #define ETH_TRANSMITTHRESHOLDCONTROL_256BYTES 0x0000C000U /*!< threshold level of the MTL Transmit FIFO is 256 Bytes */
lypinator 0:bb348c97df44 1273 #define ETH_TRANSMITTHRESHOLDCONTROL_40BYTES 0x00010000U /*!< threshold level of the MTL Transmit FIFO is 40 Bytes */
lypinator 0:bb348c97df44 1274 #define ETH_TRANSMITTHRESHOLDCONTROL_32BYTES 0x00014000U /*!< threshold level of the MTL Transmit FIFO is 32 Bytes */
lypinator 0:bb348c97df44 1275 #define ETH_TRANSMITTHRESHOLDCONTROL_24BYTES 0x00018000U /*!< threshold level of the MTL Transmit FIFO is 24 Bytes */
lypinator 0:bb348c97df44 1276 #define ETH_TRANSMITTHRESHOLDCONTROL_16BYTES 0x0001C000U /*!< threshold level of the MTL Transmit FIFO is 16 Bytes */
lypinator 0:bb348c97df44 1277 /**
lypinator 0:bb348c97df44 1278 * @}
lypinator 0:bb348c97df44 1279 */
lypinator 0:bb348c97df44 1280
lypinator 0:bb348c97df44 1281 /** @defgroup ETH_Forward_Error_Frames ETH Forward Error Frames
lypinator 0:bb348c97df44 1282 * @{
lypinator 0:bb348c97df44 1283 */
lypinator 0:bb348c97df44 1284 #define ETH_FORWARDERRORFRAMES_ENABLE 0x00000080U
lypinator 0:bb348c97df44 1285 #define ETH_FORWARDERRORFRAMES_DISABLE 0x00000000U
lypinator 0:bb348c97df44 1286 /**
lypinator 0:bb348c97df44 1287 * @}
lypinator 0:bb348c97df44 1288 */
lypinator 0:bb348c97df44 1289
lypinator 0:bb348c97df44 1290 /** @defgroup ETH_Forward_Undersized_Good_Frames ETH Forward Undersized Good Frames
lypinator 0:bb348c97df44 1291 * @{
lypinator 0:bb348c97df44 1292 */
lypinator 0:bb348c97df44 1293 #define ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE 0x00000040U
lypinator 0:bb348c97df44 1294 #define ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE 0x00000000U
lypinator 0:bb348c97df44 1295 /**
lypinator 0:bb348c97df44 1296 * @}
lypinator 0:bb348c97df44 1297 */
lypinator 0:bb348c97df44 1298
lypinator 0:bb348c97df44 1299 /** @defgroup ETH_Receive_Threshold_Control ETH Receive Threshold Control
lypinator 0:bb348c97df44 1300 * @{
lypinator 0:bb348c97df44 1301 */
lypinator 0:bb348c97df44 1302 #define ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES 0x00000000U /*!< threshold level of the MTL Receive FIFO is 64 Bytes */
lypinator 0:bb348c97df44 1303 #define ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES 0x00000008U /*!< threshold level of the MTL Receive FIFO is 32 Bytes */
lypinator 0:bb348c97df44 1304 #define ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES 0x00000010U /*!< threshold level of the MTL Receive FIFO is 96 Bytes */
lypinator 0:bb348c97df44 1305 #define ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES 0x00000018U /*!< threshold level of the MTL Receive FIFO is 128 Bytes */
lypinator 0:bb348c97df44 1306 /**
lypinator 0:bb348c97df44 1307 * @}
lypinator 0:bb348c97df44 1308 */
lypinator 0:bb348c97df44 1309
lypinator 0:bb348c97df44 1310 /** @defgroup ETH_Second_Frame_Operate ETH Second Frame Operate
lypinator 0:bb348c97df44 1311 * @{
lypinator 0:bb348c97df44 1312 */
lypinator 0:bb348c97df44 1313 #define ETH_SECONDFRAMEOPERARTE_ENABLE 0x00000004U
lypinator 0:bb348c97df44 1314 #define ETH_SECONDFRAMEOPERARTE_DISABLE 0x00000000U
lypinator 0:bb348c97df44 1315 /**
lypinator 0:bb348c97df44 1316 * @}
lypinator 0:bb348c97df44 1317 */
lypinator 0:bb348c97df44 1318
lypinator 0:bb348c97df44 1319 /** @defgroup ETH_Address_Aligned_Beats ETH Address Aligned Beats
lypinator 0:bb348c97df44 1320 * @{
lypinator 0:bb348c97df44 1321 */
lypinator 0:bb348c97df44 1322 #define ETH_ADDRESSALIGNEDBEATS_ENABLE 0x02000000U
lypinator 0:bb348c97df44 1323 #define ETH_ADDRESSALIGNEDBEATS_DISABLE 0x00000000U
lypinator 0:bb348c97df44 1324 /**
lypinator 0:bb348c97df44 1325 * @}
lypinator 0:bb348c97df44 1326 */
lypinator 0:bb348c97df44 1327
lypinator 0:bb348c97df44 1328 /** @defgroup ETH_Fixed_Burst ETH Fixed Burst
lypinator 0:bb348c97df44 1329 * @{
lypinator 0:bb348c97df44 1330 */
lypinator 0:bb348c97df44 1331 #define ETH_FIXEDBURST_ENABLE 0x00010000U
lypinator 0:bb348c97df44 1332 #define ETH_FIXEDBURST_DISABLE 0x00000000U
lypinator 0:bb348c97df44 1333 /**
lypinator 0:bb348c97df44 1334 * @}
lypinator 0:bb348c97df44 1335 */
lypinator 0:bb348c97df44 1336
lypinator 0:bb348c97df44 1337 /** @defgroup ETH_Rx_DMA_Burst_Length ETH Rx DMA Burst Length
lypinator 0:bb348c97df44 1338 * @{
lypinator 0:bb348c97df44 1339 */
lypinator 0:bb348c97df44 1340 #define ETH_RXDMABURSTLENGTH_1BEAT 0x00020000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 1 */
lypinator 0:bb348c97df44 1341 #define ETH_RXDMABURSTLENGTH_2BEAT 0x00040000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 2 */
lypinator 0:bb348c97df44 1342 #define ETH_RXDMABURSTLENGTH_4BEAT 0x00080000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */
lypinator 0:bb348c97df44 1343 #define ETH_RXDMABURSTLENGTH_8BEAT 0x00100000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */
lypinator 0:bb348c97df44 1344 #define ETH_RXDMABURSTLENGTH_16BEAT 0x00200000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */
lypinator 0:bb348c97df44 1345 #define ETH_RXDMABURSTLENGTH_32BEAT 0x00400000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */
lypinator 0:bb348c97df44 1346 #define ETH_RXDMABURSTLENGTH_4XPBL_4BEAT 0x01020000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */
lypinator 0:bb348c97df44 1347 #define ETH_RXDMABURSTLENGTH_4XPBL_8BEAT 0x01040000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */
lypinator 0:bb348c97df44 1348 #define ETH_RXDMABURSTLENGTH_4XPBL_16BEAT 0x01080000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */
lypinator 0:bb348c97df44 1349 #define ETH_RXDMABURSTLENGTH_4XPBL_32BEAT 0x01100000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */
lypinator 0:bb348c97df44 1350 #define ETH_RXDMABURSTLENGTH_4XPBL_64BEAT 0x01200000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 64 */
lypinator 0:bb348c97df44 1351 #define ETH_RXDMABURSTLENGTH_4XPBL_128BEAT 0x01400000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 128 */
lypinator 0:bb348c97df44 1352 /**
lypinator 0:bb348c97df44 1353 * @}
lypinator 0:bb348c97df44 1354 */
lypinator 0:bb348c97df44 1355
lypinator 0:bb348c97df44 1356 /** @defgroup ETH_Tx_DMA_Burst_Length ETH Tx DMA Burst Length
lypinator 0:bb348c97df44 1357 * @{
lypinator 0:bb348c97df44 1358 */
lypinator 0:bb348c97df44 1359 #define ETH_TXDMABURSTLENGTH_1BEAT 0x00000100U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
lypinator 0:bb348c97df44 1360 #define ETH_TXDMABURSTLENGTH_2BEAT 0x00000200U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
lypinator 0:bb348c97df44 1361 #define ETH_TXDMABURSTLENGTH_4BEAT 0x00000400U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
lypinator 0:bb348c97df44 1362 #define ETH_TXDMABURSTLENGTH_8BEAT 0x00000800U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
lypinator 0:bb348c97df44 1363 #define ETH_TXDMABURSTLENGTH_16BEAT 0x00001000U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
lypinator 0:bb348c97df44 1364 #define ETH_TXDMABURSTLENGTH_32BEAT 0x00002000U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
lypinator 0:bb348c97df44 1365 #define ETH_TXDMABURSTLENGTH_4XPBL_4BEAT 0x01000100U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
lypinator 0:bb348c97df44 1366 #define ETH_TXDMABURSTLENGTH_4XPBL_8BEAT 0x01000200U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
lypinator 0:bb348c97df44 1367 #define ETH_TXDMABURSTLENGTH_4XPBL_16BEAT 0x01000400U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
lypinator 0:bb348c97df44 1368 #define ETH_TXDMABURSTLENGTH_4XPBL_32BEAT 0x01000800U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
lypinator 0:bb348c97df44 1369 #define ETH_TXDMABURSTLENGTH_4XPBL_64BEAT 0x01001000U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
lypinator 0:bb348c97df44 1370 #define ETH_TXDMABURSTLENGTH_4XPBL_128BEAT 0x01002000U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
lypinator 0:bb348c97df44 1371 /**
lypinator 0:bb348c97df44 1372 * @}
lypinator 0:bb348c97df44 1373 */
lypinator 0:bb348c97df44 1374
lypinator 0:bb348c97df44 1375 /** @defgroup ETH_DMA_Enhanced_descriptor_format ETH DMA Enhanced descriptor format
lypinator 0:bb348c97df44 1376 * @{
lypinator 0:bb348c97df44 1377 */
lypinator 0:bb348c97df44 1378 #define ETH_DMAENHANCEDDESCRIPTOR_ENABLE 0x00000080U
lypinator 0:bb348c97df44 1379 #define ETH_DMAENHANCEDDESCRIPTOR_DISABLE 0x00000000U
lypinator 0:bb348c97df44 1380 /**
lypinator 0:bb348c97df44 1381 * @}
lypinator 0:bb348c97df44 1382 */
lypinator 0:bb348c97df44 1383
lypinator 0:bb348c97df44 1384 /** @defgroup ETH_DMA_Arbitration ETH DMA Arbitration
lypinator 0:bb348c97df44 1385 * @{
lypinator 0:bb348c97df44 1386 */
lypinator 0:bb348c97df44 1387 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1 0x00000000U
lypinator 0:bb348c97df44 1388 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1 0x00004000U
lypinator 0:bb348c97df44 1389 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1 0x00008000U
lypinator 0:bb348c97df44 1390 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1 0x0000C000U
lypinator 0:bb348c97df44 1391 #define ETH_DMAARBITRATION_RXPRIORTX 0x00000002U
lypinator 0:bb348c97df44 1392 /**
lypinator 0:bb348c97df44 1393 * @}
lypinator 0:bb348c97df44 1394 */
lypinator 0:bb348c97df44 1395
lypinator 0:bb348c97df44 1396 /** @defgroup ETH_DMA_Tx_descriptor_segment ETH DMA Tx descriptor segment
lypinator 0:bb348c97df44 1397 * @{
lypinator 0:bb348c97df44 1398 */
lypinator 0:bb348c97df44 1399 #define ETH_DMATXDESC_LASTSEGMENTS 0x40000000U /*!< Last Segment */
lypinator 0:bb348c97df44 1400 #define ETH_DMATXDESC_FIRSTSEGMENT 0x20000000U /*!< First Segment */
lypinator 0:bb348c97df44 1401 /**
lypinator 0:bb348c97df44 1402 * @}
lypinator 0:bb348c97df44 1403 */
lypinator 0:bb348c97df44 1404
lypinator 0:bb348c97df44 1405 /** @defgroup ETH_DMA_Tx_descriptor_Checksum_Insertion_Control ETH DMA Tx descriptor Checksum Insertion Control
lypinator 0:bb348c97df44 1406 * @{
lypinator 0:bb348c97df44 1407 */
lypinator 0:bb348c97df44 1408 #define ETH_DMATXDESC_CHECKSUMBYPASS 0x00000000U /*!< Checksum engine bypass */
lypinator 0:bb348c97df44 1409 #define ETH_DMATXDESC_CHECKSUMIPV4HEADER 0x00400000U /*!< IPv4 header checksum insertion */
lypinator 0:bb348c97df44 1410 #define ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT 0x00800000U /*!< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */
lypinator 0:bb348c97df44 1411 #define ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL 0x00C00000U /*!< TCP/UDP/ICMP checksum fully in hardware including pseudo header */
lypinator 0:bb348c97df44 1412 /**
lypinator 0:bb348c97df44 1413 * @}
lypinator 0:bb348c97df44 1414 */
lypinator 0:bb348c97df44 1415
lypinator 0:bb348c97df44 1416 /** @defgroup ETH_DMA_Rx_descriptor_buffers ETH DMA Rx descriptor buffers
lypinator 0:bb348c97df44 1417 * @{
lypinator 0:bb348c97df44 1418 */
lypinator 0:bb348c97df44 1419 #define ETH_DMARXDESC_BUFFER1 0x00000000U /*!< DMA Rx Desc Buffer1 */
lypinator 0:bb348c97df44 1420 #define ETH_DMARXDESC_BUFFER2 0x00000001U /*!< DMA Rx Desc Buffer2 */
lypinator 0:bb348c97df44 1421 /**
lypinator 0:bb348c97df44 1422 * @}
lypinator 0:bb348c97df44 1423 */
lypinator 0:bb348c97df44 1424
lypinator 0:bb348c97df44 1425 /** @defgroup ETH_PMT_Flags ETH PMT Flags
lypinator 0:bb348c97df44 1426 * @{
lypinator 0:bb348c97df44 1427 */
lypinator 0:bb348c97df44 1428 #define ETH_PMT_FLAG_WUFFRPR 0x80000000U /*!< Wake-Up Frame Filter Register Pointer Reset */
lypinator 0:bb348c97df44 1429 #define ETH_PMT_FLAG_WUFR 0x00000040U /*!< Wake-Up Frame Received */
lypinator 0:bb348c97df44 1430 #define ETH_PMT_FLAG_MPR 0x00000020U /*!< Magic Packet Received */
lypinator 0:bb348c97df44 1431 /**
lypinator 0:bb348c97df44 1432 * @}
lypinator 0:bb348c97df44 1433 */
lypinator 0:bb348c97df44 1434
lypinator 0:bb348c97df44 1435 /** @defgroup ETH_MMC_Tx_Interrupts ETH MMC Tx Interrupts
lypinator 0:bb348c97df44 1436 * @{
lypinator 0:bb348c97df44 1437 */
lypinator 0:bb348c97df44 1438 #define ETH_MMC_IT_TGF 0x00200000U /*!< When Tx good frame counter reaches half the maximum value */
lypinator 0:bb348c97df44 1439 #define ETH_MMC_IT_TGFMSC 0x00008000U /*!< When Tx good multi col counter reaches half the maximum value */
lypinator 0:bb348c97df44 1440 #define ETH_MMC_IT_TGFSC 0x00004000U /*!< When Tx good single col counter reaches half the maximum value */
lypinator 0:bb348c97df44 1441 /**
lypinator 0:bb348c97df44 1442 * @}
lypinator 0:bb348c97df44 1443 */
lypinator 0:bb348c97df44 1444
lypinator 0:bb348c97df44 1445 /** @defgroup ETH_MMC_Rx_Interrupts ETH MMC Rx Interrupts
lypinator 0:bb348c97df44 1446 * @{
lypinator 0:bb348c97df44 1447 */
lypinator 0:bb348c97df44 1448 #define ETH_MMC_IT_RGUF 0x10020000U /*!< When Rx good unicast frames counter reaches half the maximum value */
lypinator 0:bb348c97df44 1449 #define ETH_MMC_IT_RFAE 0x10000040U /*!< When Rx alignment error counter reaches half the maximum value */
lypinator 0:bb348c97df44 1450 #define ETH_MMC_IT_RFCE 0x10000020U /*!< When Rx crc error counter reaches half the maximum value */
lypinator 0:bb348c97df44 1451 /**
lypinator 0:bb348c97df44 1452 * @}
lypinator 0:bb348c97df44 1453 */
lypinator 0:bb348c97df44 1454
lypinator 0:bb348c97df44 1455 /** @defgroup ETH_MAC_Flags ETH MAC Flags
lypinator 0:bb348c97df44 1456 * @{
lypinator 0:bb348c97df44 1457 */
lypinator 0:bb348c97df44 1458 #define ETH_MAC_FLAG_TST 0x00000200U /*!< Time stamp trigger flag (on MAC) */
lypinator 0:bb348c97df44 1459 #define ETH_MAC_FLAG_MMCT 0x00000040U /*!< MMC transmit flag */
lypinator 0:bb348c97df44 1460 #define ETH_MAC_FLAG_MMCR 0x00000020U /*!< MMC receive flag */
lypinator 0:bb348c97df44 1461 #define ETH_MAC_FLAG_MMC 0x00000010U /*!< MMC flag (on MAC) */
lypinator 0:bb348c97df44 1462 #define ETH_MAC_FLAG_PMT 0x00000008U /*!< PMT flag (on MAC) */
lypinator 0:bb348c97df44 1463 /**
lypinator 0:bb348c97df44 1464 * @}
lypinator 0:bb348c97df44 1465 */
lypinator 0:bb348c97df44 1466
lypinator 0:bb348c97df44 1467 /** @defgroup ETH_DMA_Flags ETH DMA Flags
lypinator 0:bb348c97df44 1468 * @{
lypinator 0:bb348c97df44 1469 */
lypinator 0:bb348c97df44 1470 #define ETH_DMA_FLAG_TST 0x20000000U /*!< Time-stamp trigger interrupt (on DMA) */
lypinator 0:bb348c97df44 1471 #define ETH_DMA_FLAG_PMT 0x10000000U /*!< PMT interrupt (on DMA) */
lypinator 0:bb348c97df44 1472 #define ETH_DMA_FLAG_MMC 0x08000000U /*!< MMC interrupt (on DMA) */
lypinator 0:bb348c97df44 1473 #define ETH_DMA_FLAG_DATATRANSFERERROR 0x00800000U /*!< Error bits 0-Rx DMA, 1-Tx DMA */
lypinator 0:bb348c97df44 1474 #define ETH_DMA_FLAG_READWRITEERROR 0x01000000U /*!< Error bits 0-write transfer, 1-read transfer */
lypinator 0:bb348c97df44 1475 #define ETH_DMA_FLAG_ACCESSERROR 0x02000000U /*!< Error bits 0-data buffer, 1-desc. access */
lypinator 0:bb348c97df44 1476 #define ETH_DMA_FLAG_NIS 0x00010000U /*!< Normal interrupt summary flag */
lypinator 0:bb348c97df44 1477 #define ETH_DMA_FLAG_AIS 0x00008000U /*!< Abnormal interrupt summary flag */
lypinator 0:bb348c97df44 1478 #define ETH_DMA_FLAG_ER 0x00004000U /*!< Early receive flag */
lypinator 0:bb348c97df44 1479 #define ETH_DMA_FLAG_FBE 0x00002000U /*!< Fatal bus error flag */
lypinator 0:bb348c97df44 1480 #define ETH_DMA_FLAG_ET 0x00000400U /*!< Early transmit flag */
lypinator 0:bb348c97df44 1481 #define ETH_DMA_FLAG_RWT 0x00000200U /*!< Receive watchdog timeout flag */
lypinator 0:bb348c97df44 1482 #define ETH_DMA_FLAG_RPS 0x00000100U /*!< Receive process stopped flag */
lypinator 0:bb348c97df44 1483 #define ETH_DMA_FLAG_RBU 0x00000080U /*!< Receive buffer unavailable flag */
lypinator 0:bb348c97df44 1484 #define ETH_DMA_FLAG_R 0x00000040U /*!< Receive flag */
lypinator 0:bb348c97df44 1485 #define ETH_DMA_FLAG_TU 0x00000020U /*!< Underflow flag */
lypinator 0:bb348c97df44 1486 #define ETH_DMA_FLAG_RO 0x00000010U /*!< Overflow flag */
lypinator 0:bb348c97df44 1487 #define ETH_DMA_FLAG_TJT 0x00000008U /*!< Transmit jabber timeout flag */
lypinator 0:bb348c97df44 1488 #define ETH_DMA_FLAG_TBU 0x00000004U /*!< Transmit buffer unavailable flag */
lypinator 0:bb348c97df44 1489 #define ETH_DMA_FLAG_TPS 0x00000002U /*!< Transmit process stopped flag */
lypinator 0:bb348c97df44 1490 #define ETH_DMA_FLAG_T 0x00000001U /*!< Transmit flag */
lypinator 0:bb348c97df44 1491 /**
lypinator 0:bb348c97df44 1492 * @}
lypinator 0:bb348c97df44 1493 */
lypinator 0:bb348c97df44 1494
lypinator 0:bb348c97df44 1495 /** @defgroup ETH_MAC_Interrupts ETH MAC Interrupts
lypinator 0:bb348c97df44 1496 * @{
lypinator 0:bb348c97df44 1497 */
lypinator 0:bb348c97df44 1498 #define ETH_MAC_IT_TST 0x00000200U /*!< Time stamp trigger interrupt (on MAC) */
lypinator 0:bb348c97df44 1499 #define ETH_MAC_IT_MMCT 0x00000040U /*!< MMC transmit interrupt */
lypinator 0:bb348c97df44 1500 #define ETH_MAC_IT_MMCR 0x00000020U /*!< MMC receive interrupt */
lypinator 0:bb348c97df44 1501 #define ETH_MAC_IT_MMC 0x00000010U /*!< MMC interrupt (on MAC) */
lypinator 0:bb348c97df44 1502 #define ETH_MAC_IT_PMT 0x00000008U /*!< PMT interrupt (on MAC) */
lypinator 0:bb348c97df44 1503 /**
lypinator 0:bb348c97df44 1504 * @}
lypinator 0:bb348c97df44 1505 */
lypinator 0:bb348c97df44 1506
lypinator 0:bb348c97df44 1507 /** @defgroup ETH_DMA_Interrupts ETH DMA Interrupts
lypinator 0:bb348c97df44 1508 * @{
lypinator 0:bb348c97df44 1509 */
lypinator 0:bb348c97df44 1510 #define ETH_DMA_IT_TST 0x20000000U /*!< Time-stamp trigger interrupt (on DMA) */
lypinator 0:bb348c97df44 1511 #define ETH_DMA_IT_PMT 0x10000000U /*!< PMT interrupt (on DMA) */
lypinator 0:bb348c97df44 1512 #define ETH_DMA_IT_MMC 0x08000000U /*!< MMC interrupt (on DMA) */
lypinator 0:bb348c97df44 1513 #define ETH_DMA_IT_NIS 0x00010000U /*!< Normal interrupt summary */
lypinator 0:bb348c97df44 1514 #define ETH_DMA_IT_AIS 0x00008000U /*!< Abnormal interrupt summary */
lypinator 0:bb348c97df44 1515 #define ETH_DMA_IT_ER 0x00004000U /*!< Early receive interrupt */
lypinator 0:bb348c97df44 1516 #define ETH_DMA_IT_FBE 0x00002000U /*!< Fatal bus error interrupt */
lypinator 0:bb348c97df44 1517 #define ETH_DMA_IT_ET 0x00000400U /*!< Early transmit interrupt */
lypinator 0:bb348c97df44 1518 #define ETH_DMA_IT_RWT 0x00000200U /*!< Receive watchdog timeout interrupt */
lypinator 0:bb348c97df44 1519 #define ETH_DMA_IT_RPS 0x00000100U /*!< Receive process stopped interrupt */
lypinator 0:bb348c97df44 1520 #define ETH_DMA_IT_RBU 0x00000080U /*!< Receive buffer unavailable interrupt */
lypinator 0:bb348c97df44 1521 #define ETH_DMA_IT_R 0x00000040U /*!< Receive interrupt */
lypinator 0:bb348c97df44 1522 #define ETH_DMA_IT_TU 0x00000020U /*!< Underflow interrupt */
lypinator 0:bb348c97df44 1523 #define ETH_DMA_IT_RO 0x00000010U /*!< Overflow interrupt */
lypinator 0:bb348c97df44 1524 #define ETH_DMA_IT_TJT 0x00000008U /*!< Transmit jabber timeout interrupt */
lypinator 0:bb348c97df44 1525 #define ETH_DMA_IT_TBU 0x00000004U /*!< Transmit buffer unavailable interrupt */
lypinator 0:bb348c97df44 1526 #define ETH_DMA_IT_TPS 0x00000002U /*!< Transmit process stopped interrupt */
lypinator 0:bb348c97df44 1527 #define ETH_DMA_IT_T 0x00000001U /*!< Transmit interrupt */
lypinator 0:bb348c97df44 1528 /**
lypinator 0:bb348c97df44 1529 * @}
lypinator 0:bb348c97df44 1530 */
lypinator 0:bb348c97df44 1531
lypinator 0:bb348c97df44 1532 /** @defgroup ETH_DMA_transmit_process_state ETH DMA transmit process state
lypinator 0:bb348c97df44 1533 * @{
lypinator 0:bb348c97df44 1534 */
lypinator 0:bb348c97df44 1535 #define ETH_DMA_TRANSMITPROCESS_STOPPED 0x00000000U /*!< Stopped - Reset or Stop Tx Command issued */
lypinator 0:bb348c97df44 1536 #define ETH_DMA_TRANSMITPROCESS_FETCHING 0x00100000U /*!< Running - fetching the Tx descriptor */
lypinator 0:bb348c97df44 1537 #define ETH_DMA_TRANSMITPROCESS_WAITING 0x00200000U /*!< Running - waiting for status */
lypinator 0:bb348c97df44 1538 #define ETH_DMA_TRANSMITPROCESS_READING 0x00300000U /*!< Running - reading the data from host memory */
lypinator 0:bb348c97df44 1539 #define ETH_DMA_TRANSMITPROCESS_SUSPENDED 0x00600000U /*!< Suspended - Tx Descriptor unavailable */
lypinator 0:bb348c97df44 1540 #define ETH_DMA_TRANSMITPROCESS_CLOSING 0x00700000U /*!< Running - closing Rx descriptor */
lypinator 0:bb348c97df44 1541
lypinator 0:bb348c97df44 1542 /**
lypinator 0:bb348c97df44 1543 * @}
lypinator 0:bb348c97df44 1544 */
lypinator 0:bb348c97df44 1545
lypinator 0:bb348c97df44 1546
lypinator 0:bb348c97df44 1547 /** @defgroup ETH_DMA_receive_process_state ETH DMA receive process state
lypinator 0:bb348c97df44 1548 * @{
lypinator 0:bb348c97df44 1549 */
lypinator 0:bb348c97df44 1550 #define ETH_DMA_RECEIVEPROCESS_STOPPED 0x00000000U /*!< Stopped - Reset or Stop Rx Command issued */
lypinator 0:bb348c97df44 1551 #define ETH_DMA_RECEIVEPROCESS_FETCHING 0x00020000U /*!< Running - fetching the Rx descriptor */
lypinator 0:bb348c97df44 1552 #define ETH_DMA_RECEIVEPROCESS_WAITING 0x00060000U /*!< Running - waiting for packet */
lypinator 0:bb348c97df44 1553 #define ETH_DMA_RECEIVEPROCESS_SUSPENDED 0x00080000U /*!< Suspended - Rx Descriptor unavailable */
lypinator 0:bb348c97df44 1554 #define ETH_DMA_RECEIVEPROCESS_CLOSING 0x000A0000U /*!< Running - closing descriptor */
lypinator 0:bb348c97df44 1555 #define ETH_DMA_RECEIVEPROCESS_QUEUING 0x000E0000U /*!< Running - queuing the receive frame into host memory */
lypinator 0:bb348c97df44 1556
lypinator 0:bb348c97df44 1557 /**
lypinator 0:bb348c97df44 1558 * @}
lypinator 0:bb348c97df44 1559 */
lypinator 0:bb348c97df44 1560
lypinator 0:bb348c97df44 1561 /** @defgroup ETH_DMA_overflow ETH DMA overflow
lypinator 0:bb348c97df44 1562 * @{
lypinator 0:bb348c97df44 1563 */
lypinator 0:bb348c97df44 1564 #define ETH_DMA_OVERFLOW_RXFIFOCOUNTER 0x10000000U /*!< Overflow bit for FIFO overflow counter */
lypinator 0:bb348c97df44 1565 #define ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER 0x00010000U /*!< Overflow bit for missed frame counter */
lypinator 0:bb348c97df44 1566 /**
lypinator 0:bb348c97df44 1567 * @}
lypinator 0:bb348c97df44 1568 */
lypinator 0:bb348c97df44 1569
lypinator 0:bb348c97df44 1570 /** @defgroup ETH_EXTI_LINE_WAKEUP ETH EXTI LINE WAKEUP
lypinator 0:bb348c97df44 1571 * @{
lypinator 0:bb348c97df44 1572 */
lypinator 0:bb348c97df44 1573 #define ETH_EXTI_LINE_WAKEUP 0x00080000U /*!< External interrupt line 19 Connected to the ETH EXTI Line */
lypinator 0:bb348c97df44 1574
lypinator 0:bb348c97df44 1575 /**
lypinator 0:bb348c97df44 1576 * @}
lypinator 0:bb348c97df44 1577 */
lypinator 0:bb348c97df44 1578
lypinator 0:bb348c97df44 1579 /**
lypinator 0:bb348c97df44 1580 * @}
lypinator 0:bb348c97df44 1581 */
lypinator 0:bb348c97df44 1582
lypinator 0:bb348c97df44 1583 /* Exported macro ------------------------------------------------------------*/
lypinator 0:bb348c97df44 1584 /** @defgroup ETH_Exported_Macros ETH Exported Macros
lypinator 0:bb348c97df44 1585 * @brief macros to handle interrupts and specific clock configurations
lypinator 0:bb348c97df44 1586 * @{
lypinator 0:bb348c97df44 1587 */
lypinator 0:bb348c97df44 1588
lypinator 0:bb348c97df44 1589 /** @brief Reset ETH handle state
lypinator 0:bb348c97df44 1590 * @param __HANDLE__ specifies the ETH handle.
lypinator 0:bb348c97df44 1591 * @retval None
lypinator 0:bb348c97df44 1592 */
lypinator 0:bb348c97df44 1593 #define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ETH_STATE_RESET)
lypinator 0:bb348c97df44 1594
lypinator 0:bb348c97df44 1595 /**
lypinator 0:bb348c97df44 1596 * @brief Checks whether the specified ETHERNET DMA Tx Desc flag is set or not.
lypinator 0:bb348c97df44 1597 * @param __HANDLE__ ETH Handle
lypinator 0:bb348c97df44 1598 * @param __FLAG__ specifies the flag of TDES0 to check.
lypinator 0:bb348c97df44 1599 * @retval the ETH_DMATxDescFlag (SET or RESET).
lypinator 0:bb348c97df44 1600 */
lypinator 0:bb348c97df44 1601 #define __HAL_ETH_DMATXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->TxDesc->Status & (__FLAG__) == (__FLAG__))
lypinator 0:bb348c97df44 1602
lypinator 0:bb348c97df44 1603 /**
lypinator 0:bb348c97df44 1604 * @brief Checks whether the specified ETHERNET DMA Rx Desc flag is set or not.
lypinator 0:bb348c97df44 1605 * @param __HANDLE__ ETH Handle
lypinator 0:bb348c97df44 1606 * @param __FLAG__ specifies the flag of RDES0 to check.
lypinator 0:bb348c97df44 1607 * @retval the ETH_DMATxDescFlag (SET or RESET).
lypinator 0:bb348c97df44 1608 */
lypinator 0:bb348c97df44 1609 #define __HAL_ETH_DMARXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->RxDesc->Status & (__FLAG__) == (__FLAG__))
lypinator 0:bb348c97df44 1610
lypinator 0:bb348c97df44 1611 /**
lypinator 0:bb348c97df44 1612 * @brief Enables the specified DMA Rx Desc receive interrupt.
lypinator 0:bb348c97df44 1613 * @param __HANDLE__ ETH Handle
lypinator 0:bb348c97df44 1614 * @retval None
lypinator 0:bb348c97df44 1615 */
lypinator 0:bb348c97df44 1616 #define __HAL_ETH_DMARXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARXDESC_DIC))
lypinator 0:bb348c97df44 1617
lypinator 0:bb348c97df44 1618 /**
lypinator 0:bb348c97df44 1619 * @brief Disables the specified DMA Rx Desc receive interrupt.
lypinator 0:bb348c97df44 1620 * @param __HANDLE__ ETH Handle
lypinator 0:bb348c97df44 1621 * @retval None
lypinator 0:bb348c97df44 1622 */
lypinator 0:bb348c97df44 1623 #define __HAL_ETH_DMARXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize |= ETH_DMARXDESC_DIC)
lypinator 0:bb348c97df44 1624
lypinator 0:bb348c97df44 1625 /**
lypinator 0:bb348c97df44 1626 * @brief Set the specified DMA Rx Desc Own bit.
lypinator 0:bb348c97df44 1627 * @param __HANDLE__ ETH Handle
lypinator 0:bb348c97df44 1628 * @retval None
lypinator 0:bb348c97df44 1629 */
lypinator 0:bb348c97df44 1630 #define __HAL_ETH_DMARXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->RxDesc->Status |= ETH_DMARXDESC_OWN)
lypinator 0:bb348c97df44 1631
lypinator 0:bb348c97df44 1632 /**
lypinator 0:bb348c97df44 1633 * @brief Returns the specified ETHERNET DMA Tx Desc collision count.
lypinator 0:bb348c97df44 1634 * @param __HANDLE__ ETH Handle
lypinator 0:bb348c97df44 1635 * @retval The Transmit descriptor collision counter value.
lypinator 0:bb348c97df44 1636 */
lypinator 0:bb348c97df44 1637 #define __HAL_ETH_DMATXDESC_GET_COLLISION_COUNT(__HANDLE__) (((__HANDLE__)->TxDesc->Status & ETH_DMATXDESC_CC) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT)
lypinator 0:bb348c97df44 1638
lypinator 0:bb348c97df44 1639 /**
lypinator 0:bb348c97df44 1640 * @brief Set the specified DMA Tx Desc Own bit.
lypinator 0:bb348c97df44 1641 * @param __HANDLE__ ETH Handle
lypinator 0:bb348c97df44 1642 * @retval None
lypinator 0:bb348c97df44 1643 */
lypinator 0:bb348c97df44 1644 #define __HAL_ETH_DMATXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_OWN)
lypinator 0:bb348c97df44 1645
lypinator 0:bb348c97df44 1646 /**
lypinator 0:bb348c97df44 1647 * @brief Enables the specified DMA Tx Desc Transmit interrupt.
lypinator 0:bb348c97df44 1648 * @param __HANDLE__ ETH Handle
lypinator 0:bb348c97df44 1649 * @retval None
lypinator 0:bb348c97df44 1650 */
lypinator 0:bb348c97df44 1651 #define __HAL_ETH_DMATXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_IC)
lypinator 0:bb348c97df44 1652
lypinator 0:bb348c97df44 1653 /**
lypinator 0:bb348c97df44 1654 * @brief Disables the specified DMA Tx Desc Transmit interrupt.
lypinator 0:bb348c97df44 1655 * @param __HANDLE__ ETH Handle
lypinator 0:bb348c97df44 1656 * @retval None
lypinator 0:bb348c97df44 1657 */
lypinator 0:bb348c97df44 1658 #define __HAL_ETH_DMATXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_IC)
lypinator 0:bb348c97df44 1659
lypinator 0:bb348c97df44 1660 /**
lypinator 0:bb348c97df44 1661 * @brief Selects the specified ETHERNET DMA Tx Desc Checksum Insertion.
lypinator 0:bb348c97df44 1662 * @param __HANDLE__ ETH Handle
lypinator 0:bb348c97df44 1663 * @param __CHECKSUM__ specifies is the DMA Tx desc checksum insertion.
lypinator 0:bb348c97df44 1664 * This parameter can be one of the following values:
lypinator 0:bb348c97df44 1665 * @arg ETH_DMATXDESC_CHECKSUMBYPASS : Checksum bypass
lypinator 0:bb348c97df44 1666 * @arg ETH_DMATXDESC_CHECKSUMIPV4HEADER : IPv4 header checksum
lypinator 0:bb348c97df44 1667 * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT : TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present
lypinator 0:bb348c97df44 1668 * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL : TCP/UDP/ICMP checksum fully in hardware including pseudo header
lypinator 0:bb348c97df44 1669 * @retval None
lypinator 0:bb348c97df44 1670 */
lypinator 0:bb348c97df44 1671 #define __HAL_ETH_DMATXDESC_CHECKSUM_INSERTION(__HANDLE__, __CHECKSUM__) ((__HANDLE__)->TxDesc->Status |= (__CHECKSUM__))
lypinator 0:bb348c97df44 1672
lypinator 0:bb348c97df44 1673 /**
lypinator 0:bb348c97df44 1674 * @brief Enables the DMA Tx Desc CRC.
lypinator 0:bb348c97df44 1675 * @param __HANDLE__ ETH Handle
lypinator 0:bb348c97df44 1676 * @retval None
lypinator 0:bb348c97df44 1677 */
lypinator 0:bb348c97df44 1678 #define __HAL_ETH_DMATXDESC_CRC_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DC)
lypinator 0:bb348c97df44 1679
lypinator 0:bb348c97df44 1680 /**
lypinator 0:bb348c97df44 1681 * @brief Disables the DMA Tx Desc CRC.
lypinator 0:bb348c97df44 1682 * @param __HANDLE__ ETH Handle
lypinator 0:bb348c97df44 1683 * @retval None
lypinator 0:bb348c97df44 1684 */
lypinator 0:bb348c97df44 1685 #define __HAL_ETH_DMATXDESC_CRC_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DC)
lypinator 0:bb348c97df44 1686
lypinator 0:bb348c97df44 1687 /**
lypinator 0:bb348c97df44 1688 * @brief Enables the DMA Tx Desc padding for frame shorter than 64 bytes.
lypinator 0:bb348c97df44 1689 * @param __HANDLE__ ETH Handle
lypinator 0:bb348c97df44 1690 * @retval None
lypinator 0:bb348c97df44 1691 */
lypinator 0:bb348c97df44 1692 #define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DP)
lypinator 0:bb348c97df44 1693
lypinator 0:bb348c97df44 1694 /**
lypinator 0:bb348c97df44 1695 * @brief Disables the DMA Tx Desc padding for frame shorter than 64 bytes.
lypinator 0:bb348c97df44 1696 * @param __HANDLE__ ETH Handle
lypinator 0:bb348c97df44 1697 * @retval None
lypinator 0:bb348c97df44 1698 */
lypinator 0:bb348c97df44 1699 #define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DP)
lypinator 0:bb348c97df44 1700
lypinator 0:bb348c97df44 1701 /**
lypinator 0:bb348c97df44 1702 * @brief Enables the specified ETHERNET MAC interrupts.
lypinator 0:bb348c97df44 1703 * @param __HANDLE__ ETH Handle
lypinator 0:bb348c97df44 1704 * @param __INTERRUPT__ specifies the ETHERNET MAC interrupt sources to be
lypinator 0:bb348c97df44 1705 * enabled or disabled.
lypinator 0:bb348c97df44 1706 * This parameter can be any combination of the following values:
lypinator 0:bb348c97df44 1707 * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt
lypinator 0:bb348c97df44 1708 * @arg ETH_MAC_IT_PMT : PMT interrupt
lypinator 0:bb348c97df44 1709 * @retval None
lypinator 0:bb348c97df44 1710 */
lypinator 0:bb348c97df44 1711 #define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR |= (__INTERRUPT__))
lypinator 0:bb348c97df44 1712
lypinator 0:bb348c97df44 1713 /**
lypinator 0:bb348c97df44 1714 * @brief Disables the specified ETHERNET MAC interrupts.
lypinator 0:bb348c97df44 1715 * @param __HANDLE__ ETH Handle
lypinator 0:bb348c97df44 1716 * @param __INTERRUPT__ specifies the ETHERNET MAC interrupt sources to be
lypinator 0:bb348c97df44 1717 * enabled or disabled.
lypinator 0:bb348c97df44 1718 * This parameter can be any combination of the following values:
lypinator 0:bb348c97df44 1719 * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt
lypinator 0:bb348c97df44 1720 * @arg ETH_MAC_IT_PMT : PMT interrupt
lypinator 0:bb348c97df44 1721 * @retval None
lypinator 0:bb348c97df44 1722 */
lypinator 0:bb348c97df44 1723 #define __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR &= ~(__INTERRUPT__))
lypinator 0:bb348c97df44 1724
lypinator 0:bb348c97df44 1725 /**
lypinator 0:bb348c97df44 1726 * @brief Initiate a Pause Control Frame (Full-duplex only).
lypinator 0:bb348c97df44 1727 * @param __HANDLE__ ETH Handle
lypinator 0:bb348c97df44 1728 * @retval None
lypinator 0:bb348c97df44 1729 */
lypinator 0:bb348c97df44 1730 #define __HAL_ETH_INITIATE_PAUSE_CONTROL_FRAME(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA)
lypinator 0:bb348c97df44 1731
lypinator 0:bb348c97df44 1732 /**
lypinator 0:bb348c97df44 1733 * @brief Checks whether the ETHERNET flow control busy bit is set or not.
lypinator 0:bb348c97df44 1734 * @param __HANDLE__ ETH Handle
lypinator 0:bb348c97df44 1735 * @retval The new state of flow control busy status bit (SET or RESET).
lypinator 0:bb348c97df44 1736 */
lypinator 0:bb348c97df44 1737 #define __HAL_ETH_GET_FLOW_CONTROL_BUSY_STATUS(__HANDLE__) (((__HANDLE__)->Instance->MACFCR & ETH_MACFCR_FCBBPA) == ETH_MACFCR_FCBBPA)
lypinator 0:bb348c97df44 1738
lypinator 0:bb348c97df44 1739 /**
lypinator 0:bb348c97df44 1740 * @brief Enables the MAC Back Pressure operation activation (Half-duplex only).
lypinator 0:bb348c97df44 1741 * @param __HANDLE__ ETH Handle
lypinator 0:bb348c97df44 1742 * @retval None
lypinator 0:bb348c97df44 1743 */
lypinator 0:bb348c97df44 1744 #define __HAL_ETH_BACK_PRESSURE_ACTIVATION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA)
lypinator 0:bb348c97df44 1745
lypinator 0:bb348c97df44 1746 /**
lypinator 0:bb348c97df44 1747 * @brief Disables the MAC BackPressure operation activation (Half-duplex only).
lypinator 0:bb348c97df44 1748 * @param __HANDLE__ ETH Handle
lypinator 0:bb348c97df44 1749 * @retval None
lypinator 0:bb348c97df44 1750 */
lypinator 0:bb348c97df44 1751 #define __HAL_ETH_BACK_PRESSURE_ACTIVATION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR &= ~ETH_MACFCR_FCBBPA)
lypinator 0:bb348c97df44 1752
lypinator 0:bb348c97df44 1753 /**
lypinator 0:bb348c97df44 1754 * @brief Checks whether the specified ETHERNET MAC flag is set or not.
lypinator 0:bb348c97df44 1755 * @param __HANDLE__ ETH Handle
lypinator 0:bb348c97df44 1756 * @param __FLAG__ specifies the flag to check.
lypinator 0:bb348c97df44 1757 * This parameter can be one of the following values:
lypinator 0:bb348c97df44 1758 * @arg ETH_MAC_FLAG_TST : Time stamp trigger flag
lypinator 0:bb348c97df44 1759 * @arg ETH_MAC_FLAG_MMCT : MMC transmit flag
lypinator 0:bb348c97df44 1760 * @arg ETH_MAC_FLAG_MMCR : MMC receive flag
lypinator 0:bb348c97df44 1761 * @arg ETH_MAC_FLAG_MMC : MMC flag
lypinator 0:bb348c97df44 1762 * @arg ETH_MAC_FLAG_PMT : PMT flag
lypinator 0:bb348c97df44 1763 * @retval The state of ETHERNET MAC flag.
lypinator 0:bb348c97df44 1764 */
lypinator 0:bb348c97df44 1765 #define __HAL_ETH_MAC_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACSR &( __FLAG__)) == ( __FLAG__))
lypinator 0:bb348c97df44 1766
lypinator 0:bb348c97df44 1767 /**
lypinator 0:bb348c97df44 1768 * @brief Enables the specified ETHERNET DMA interrupts.
lypinator 0:bb348c97df44 1769 * @param __HANDLE__ ETH Handle
lypinator 0:bb348c97df44 1770 * @param __INTERRUPT__ specifies the ETHERNET DMA interrupt sources to be
lypinator 0:bb348c97df44 1771 * enabled @ref ETH_DMA_Interrupts
lypinator 0:bb348c97df44 1772 * @retval None
lypinator 0:bb348c97df44 1773 */
lypinator 0:bb348c97df44 1774 #define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER |= (__INTERRUPT__))
lypinator 0:bb348c97df44 1775
lypinator 0:bb348c97df44 1776 /**
lypinator 0:bb348c97df44 1777 * @brief Disables the specified ETHERNET DMA interrupts.
lypinator 0:bb348c97df44 1778 * @param __HANDLE__ ETH Handle
lypinator 0:bb348c97df44 1779 * @param __INTERRUPT__ specifies the ETHERNET DMA interrupt sources to be
lypinator 0:bb348c97df44 1780 * disabled. @ref ETH_DMA_Interrupts
lypinator 0:bb348c97df44 1781 * @retval None
lypinator 0:bb348c97df44 1782 */
lypinator 0:bb348c97df44 1783 #define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER &= ~(__INTERRUPT__))
lypinator 0:bb348c97df44 1784
lypinator 0:bb348c97df44 1785 /**
lypinator 0:bb348c97df44 1786 * @brief Clears the ETHERNET DMA IT pending bit.
lypinator 0:bb348c97df44 1787 * @param __HANDLE__ ETH Handle
lypinator 0:bb348c97df44 1788 * @param __INTERRUPT__ specifies the interrupt pending bit to clear. @ref ETH_DMA_Interrupts
lypinator 0:bb348c97df44 1789 * @retval None
lypinator 0:bb348c97df44 1790 */
lypinator 0:bb348c97df44 1791 #define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMASR =(__INTERRUPT__))
lypinator 0:bb348c97df44 1792
lypinator 0:bb348c97df44 1793 /**
lypinator 0:bb348c97df44 1794 * @brief Checks whether the specified ETHERNET DMA flag is set or not.
lypinator 0:bb348c97df44 1795 * @param __HANDLE__ ETH Handle
lypinator 0:bb348c97df44 1796 * @param __FLAG__ specifies the flag to check. @ref ETH_DMA_Flags
lypinator 0:bb348c97df44 1797 * @retval The new state of ETH_DMA_FLAG (SET or RESET).
lypinator 0:bb348c97df44 1798 */
lypinator 0:bb348c97df44 1799 #define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->DMASR &( __FLAG__)) == ( __FLAG__))
lypinator 0:bb348c97df44 1800
lypinator 0:bb348c97df44 1801 /**
lypinator 0:bb348c97df44 1802 * @brief Checks whether the specified ETHERNET DMA flag is set or not.
lypinator 0:bb348c97df44 1803 * @param __HANDLE__ ETH Handle
lypinator 0:bb348c97df44 1804 * @param __FLAG__ specifies the flag to clear. @ref ETH_DMA_Flags
lypinator 0:bb348c97df44 1805 * @retval The new state of ETH_DMA_FLAG (SET or RESET).
lypinator 0:bb348c97df44 1806 */
lypinator 0:bb348c97df44 1807 #define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMASR = (__FLAG__))
lypinator 0:bb348c97df44 1808
lypinator 0:bb348c97df44 1809 /**
lypinator 0:bb348c97df44 1810 * @brief Checks whether the specified ETHERNET DMA overflow flag is set or not.
lypinator 0:bb348c97df44 1811 * @param __HANDLE__ ETH Handle
lypinator 0:bb348c97df44 1812 * @param __OVERFLOW__ specifies the DMA overflow flag to check.
lypinator 0:bb348c97df44 1813 * This parameter can be one of the following values:
lypinator 0:bb348c97df44 1814 * @arg ETH_DMA_OVERFLOW_RXFIFOCOUNTER : Overflow for FIFO Overflows Counter
lypinator 0:bb348c97df44 1815 * @arg ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER : Overflow for Buffer Unavailable Missed Frame Counter
lypinator 0:bb348c97df44 1816 * @retval The state of ETHERNET DMA overflow Flag (SET or RESET).
lypinator 0:bb348c97df44 1817 */
lypinator 0:bb348c97df44 1818 #define __HAL_ETH_GET_DMA_OVERFLOW_STATUS(__HANDLE__, __OVERFLOW__) (((__HANDLE__)->Instance->DMAMFBOCR & (__OVERFLOW__)) == (__OVERFLOW__))
lypinator 0:bb348c97df44 1819
lypinator 0:bb348c97df44 1820 /**
lypinator 0:bb348c97df44 1821 * @brief Set the DMA Receive status watchdog timer register value
lypinator 0:bb348c97df44 1822 * @param __HANDLE__ ETH Handle
lypinator 0:bb348c97df44 1823 * @param __VALUE__ DMA Receive status watchdog timer register value
lypinator 0:bb348c97df44 1824 * @retval None
lypinator 0:bb348c97df44 1825 */
lypinator 0:bb348c97df44 1826 #define __HAL_ETH_SET_RECEIVE_WATCHDOG_TIMER(__HANDLE__, __VALUE__) ((__HANDLE__)->Instance->DMARSWTR = (__VALUE__))
lypinator 0:bb348c97df44 1827
lypinator 0:bb348c97df44 1828 /**
lypinator 0:bb348c97df44 1829 * @brief Enables any unicast packet filtered by the MAC address
lypinator 0:bb348c97df44 1830 * recognition to be a wake-up frame.
lypinator 0:bb348c97df44 1831 * @param __HANDLE__ ETH Handle.
lypinator 0:bb348c97df44 1832 * @retval None
lypinator 0:bb348c97df44 1833 */
lypinator 0:bb348c97df44 1834 #define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_GU)
lypinator 0:bb348c97df44 1835
lypinator 0:bb348c97df44 1836 /**
lypinator 0:bb348c97df44 1837 * @brief Disables any unicast packet filtered by the MAC address
lypinator 0:bb348c97df44 1838 * recognition to be a wake-up frame.
lypinator 0:bb348c97df44 1839 * @param __HANDLE__ ETH Handle.
lypinator 0:bb348c97df44 1840 * @retval None
lypinator 0:bb348c97df44 1841 */
lypinator 0:bb348c97df44 1842 #define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_GU)
lypinator 0:bb348c97df44 1843
lypinator 0:bb348c97df44 1844 /**
lypinator 0:bb348c97df44 1845 * @brief Enables the MAC Wake-Up Frame Detection.
lypinator 0:bb348c97df44 1846 * @param __HANDLE__ ETH Handle.
lypinator 0:bb348c97df44 1847 * @retval None
lypinator 0:bb348c97df44 1848 */
lypinator 0:bb348c97df44 1849 #define __HAL_ETH_WAKEUP_FRAME_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_WFE)
lypinator 0:bb348c97df44 1850
lypinator 0:bb348c97df44 1851 /**
lypinator 0:bb348c97df44 1852 * @brief Disables the MAC Wake-Up Frame Detection.
lypinator 0:bb348c97df44 1853 * @param __HANDLE__ ETH Handle.
lypinator 0:bb348c97df44 1854 * @retval None
lypinator 0:bb348c97df44 1855 */
lypinator 0:bb348c97df44 1856 #define __HAL_ETH_WAKEUP_FRAME_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)
lypinator 0:bb348c97df44 1857
lypinator 0:bb348c97df44 1858 /**
lypinator 0:bb348c97df44 1859 * @brief Enables the MAC Magic Packet Detection.
lypinator 0:bb348c97df44 1860 * @param __HANDLE__ ETH Handle.
lypinator 0:bb348c97df44 1861 * @retval None
lypinator 0:bb348c97df44 1862 */
lypinator 0:bb348c97df44 1863 #define __HAL_ETH_MAGIC_PACKET_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_MPE)
lypinator 0:bb348c97df44 1864
lypinator 0:bb348c97df44 1865 /**
lypinator 0:bb348c97df44 1866 * @brief Disables the MAC Magic Packet Detection.
lypinator 0:bb348c97df44 1867 * @param __HANDLE__ ETH Handle.
lypinator 0:bb348c97df44 1868 * @retval None
lypinator 0:bb348c97df44 1869 */
lypinator 0:bb348c97df44 1870 #define __HAL_ETH_MAGIC_PACKET_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)
lypinator 0:bb348c97df44 1871
lypinator 0:bb348c97df44 1872 /**
lypinator 0:bb348c97df44 1873 * @brief Enables the MAC Power Down.
lypinator 0:bb348c97df44 1874 * @param __HANDLE__ ETH Handle
lypinator 0:bb348c97df44 1875 * @retval None
lypinator 0:bb348c97df44 1876 */
lypinator 0:bb348c97df44 1877 #define __HAL_ETH_POWER_DOWN_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_PD)
lypinator 0:bb348c97df44 1878
lypinator 0:bb348c97df44 1879 /**
lypinator 0:bb348c97df44 1880 * @brief Disables the MAC Power Down.
lypinator 0:bb348c97df44 1881 * @param __HANDLE__ ETH Handle
lypinator 0:bb348c97df44 1882 * @retval None
lypinator 0:bb348c97df44 1883 */
lypinator 0:bb348c97df44 1884 #define __HAL_ETH_POWER_DOWN_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_PD)
lypinator 0:bb348c97df44 1885
lypinator 0:bb348c97df44 1886 /**
lypinator 0:bb348c97df44 1887 * @brief Checks whether the specified ETHERNET PMT flag is set or not.
lypinator 0:bb348c97df44 1888 * @param __HANDLE__ ETH Handle.
lypinator 0:bb348c97df44 1889 * @param __FLAG__ specifies the flag to check.
lypinator 0:bb348c97df44 1890 * This parameter can be one of the following values:
lypinator 0:bb348c97df44 1891 * @arg ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Pointer Reset
lypinator 0:bb348c97df44 1892 * @arg ETH_PMT_FLAG_WUFR : Wake-Up Frame Received
lypinator 0:bb348c97df44 1893 * @arg ETH_PMT_FLAG_MPR : Magic Packet Received
lypinator 0:bb348c97df44 1894 * @retval The new state of ETHERNET PMT Flag (SET or RESET).
lypinator 0:bb348c97df44 1895 */
lypinator 0:bb348c97df44 1896 #define __HAL_ETH_GET_PMT_FLAG_STATUS(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACPMTCSR &( __FLAG__)) == ( __FLAG__))
lypinator 0:bb348c97df44 1897
lypinator 0:bb348c97df44 1898 /**
lypinator 0:bb348c97df44 1899 * @brief Preset and Initialize the MMC counters to almost-full value: 0xFFFF_FFF0 (full - 16)
lypinator 0:bb348c97df44 1900 * @param __HANDLE__ ETH Handle.
lypinator 0:bb348c97df44 1901 * @retval None
lypinator 0:bb348c97df44 1902 */
lypinator 0:bb348c97df44 1903 #define __HAL_ETH_MMC_COUNTER_FULL_PRESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= (ETH_MMCCR_MCFHP | ETH_MMCCR_MCP))
lypinator 0:bb348c97df44 1904
lypinator 0:bb348c97df44 1905 /**
lypinator 0:bb348c97df44 1906 * @brief Preset and Initialize the MMC counters to almost-half value: 0x7FFF_FFF0 (half - 16)
lypinator 0:bb348c97df44 1907 * @param __HANDLE__ ETH Handle.
lypinator 0:bb348c97df44 1908 * @retval None
lypinator 0:bb348c97df44 1909 */
lypinator 0:bb348c97df44 1910 #define __HAL_ETH_MMC_COUNTER_HALF_PRESET(__HANDLE__) do{(__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCFHP;\
lypinator 0:bb348c97df44 1911 (__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCP;} while (0)
lypinator 0:bb348c97df44 1912
lypinator 0:bb348c97df44 1913 /**
lypinator 0:bb348c97df44 1914 * @brief Enables the MMC Counter Freeze.
lypinator 0:bb348c97df44 1915 * @param __HANDLE__ ETH Handle.
lypinator 0:bb348c97df44 1916 * @retval None
lypinator 0:bb348c97df44 1917 */
lypinator 0:bb348c97df44 1918 #define __HAL_ETH_MMC_COUNTER_FREEZE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCF)
lypinator 0:bb348c97df44 1919
lypinator 0:bb348c97df44 1920 /**
lypinator 0:bb348c97df44 1921 * @brief Disables the MMC Counter Freeze.
lypinator 0:bb348c97df44 1922 * @param __HANDLE__ ETH Handle.
lypinator 0:bb348c97df44 1923 * @retval None
lypinator 0:bb348c97df44 1924 */
lypinator 0:bb348c97df44 1925 #define __HAL_ETH_MMC_COUNTER_FREEZE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCF)
lypinator 0:bb348c97df44 1926
lypinator 0:bb348c97df44 1927 /**
lypinator 0:bb348c97df44 1928 * @brief Enables the MMC Reset On Read.
lypinator 0:bb348c97df44 1929 * @param __HANDLE__ ETH Handle.
lypinator 0:bb348c97df44 1930 * @retval None
lypinator 0:bb348c97df44 1931 */
lypinator 0:bb348c97df44 1932 #define __HAL_ETH_ETH_MMC_RESET_ONREAD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_ROR)
lypinator 0:bb348c97df44 1933
lypinator 0:bb348c97df44 1934 /**
lypinator 0:bb348c97df44 1935 * @brief Disables the MMC Reset On Read.
lypinator 0:bb348c97df44 1936 * @param __HANDLE__ ETH Handle.
lypinator 0:bb348c97df44 1937 * @retval None
lypinator 0:bb348c97df44 1938 */
lypinator 0:bb348c97df44 1939 #define __HAL_ETH_ETH_MMC_RESET_ONREAD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_ROR)
lypinator 0:bb348c97df44 1940
lypinator 0:bb348c97df44 1941 /**
lypinator 0:bb348c97df44 1942 * @brief Enables the MMC Counter Stop Rollover.
lypinator 0:bb348c97df44 1943 * @param __HANDLE__ ETH Handle.
lypinator 0:bb348c97df44 1944 * @retval None
lypinator 0:bb348c97df44 1945 */
lypinator 0:bb348c97df44 1946 #define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_CSR)
lypinator 0:bb348c97df44 1947
lypinator 0:bb348c97df44 1948 /**
lypinator 0:bb348c97df44 1949 * @brief Disables the MMC Counter Stop Rollover.
lypinator 0:bb348c97df44 1950 * @param __HANDLE__ ETH Handle.
lypinator 0:bb348c97df44 1951 * @retval None
lypinator 0:bb348c97df44 1952 */
lypinator 0:bb348c97df44 1953 #define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CSR)
lypinator 0:bb348c97df44 1954
lypinator 0:bb348c97df44 1955 /**
lypinator 0:bb348c97df44 1956 * @brief Resets the MMC Counters.
lypinator 0:bb348c97df44 1957 * @param __HANDLE__ ETH Handle.
lypinator 0:bb348c97df44 1958 * @retval None
lypinator 0:bb348c97df44 1959 */
lypinator 0:bb348c97df44 1960 #define __HAL_ETH_MMC_COUNTERS_RESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CR)
lypinator 0:bb348c97df44 1961
lypinator 0:bb348c97df44 1962 /**
lypinator 0:bb348c97df44 1963 * @brief Enables the specified ETHERNET MMC Rx interrupts.
lypinator 0:bb348c97df44 1964 * @param __HANDLE__ ETH Handle.
lypinator 0:bb348c97df44 1965 * @param __INTERRUPT__ specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
lypinator 0:bb348c97df44 1966 * This parameter can be one of the following values:
lypinator 0:bb348c97df44 1967 * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value
lypinator 0:bb348c97df44 1968 * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value
lypinator 0:bb348c97df44 1969 * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value
lypinator 0:bb348c97df44 1970 * @retval None
lypinator 0:bb348c97df44 1971 */
lypinator 0:bb348c97df44 1972 #define __HAL_ETH_MMC_RX_IT_ENABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR &= ~((__INTERRUPT__) & 0xEFFFFFFFU)
lypinator 0:bb348c97df44 1973 /**
lypinator 0:bb348c97df44 1974 * @brief Disables the specified ETHERNET MMC Rx interrupts.
lypinator 0:bb348c97df44 1975 * @param __HANDLE__ ETH Handle.
lypinator 0:bb348c97df44 1976 * @param __INTERRUPT__ specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
lypinator 0:bb348c97df44 1977 * This parameter can be one of the following values:
lypinator 0:bb348c97df44 1978 * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value
lypinator 0:bb348c97df44 1979 * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value
lypinator 0:bb348c97df44 1980 * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value
lypinator 0:bb348c97df44 1981 * @retval None
lypinator 0:bb348c97df44 1982 */
lypinator 0:bb348c97df44 1983 #define __HAL_ETH_MMC_RX_IT_DISABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR |= ((__INTERRUPT__) & 0xEFFFFFFFU)
lypinator 0:bb348c97df44 1984 /**
lypinator 0:bb348c97df44 1985 * @brief Enables the specified ETHERNET MMC Tx interrupts.
lypinator 0:bb348c97df44 1986 * @param __HANDLE__ ETH Handle.
lypinator 0:bb348c97df44 1987 * @param __INTERRUPT__ specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
lypinator 0:bb348c97df44 1988 * This parameter can be one of the following values:
lypinator 0:bb348c97df44 1989 * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value
lypinator 0:bb348c97df44 1990 * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value
lypinator 0:bb348c97df44 1991 * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value
lypinator 0:bb348c97df44 1992 * @retval None
lypinator 0:bb348c97df44 1993 */
lypinator 0:bb348c97df44 1994 #define __HAL_ETH_MMC_TX_IT_ENABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR &= ~ (__INTERRUPT__))
lypinator 0:bb348c97df44 1995
lypinator 0:bb348c97df44 1996 /**
lypinator 0:bb348c97df44 1997 * @brief Disables the specified ETHERNET MMC Tx interrupts.
lypinator 0:bb348c97df44 1998 * @param __HANDLE__ ETH Handle.
lypinator 0:bb348c97df44 1999 * @param __INTERRUPT__ specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
lypinator 0:bb348c97df44 2000 * This parameter can be one of the following values:
lypinator 0:bb348c97df44 2001 * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value
lypinator 0:bb348c97df44 2002 * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value
lypinator 0:bb348c97df44 2003 * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value
lypinator 0:bb348c97df44 2004 * @retval None
lypinator 0:bb348c97df44 2005 */
lypinator 0:bb348c97df44 2006 #define __HAL_ETH_MMC_TX_IT_DISABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR |= (__INTERRUPT__))
lypinator 0:bb348c97df44 2007
lypinator 0:bb348c97df44 2008 /**
lypinator 0:bb348c97df44 2009 * @brief Enables the ETH External interrupt line.
lypinator 0:bb348c97df44 2010 * @retval None
lypinator 0:bb348c97df44 2011 */
lypinator 0:bb348c97df44 2012 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= (ETH_EXTI_LINE_WAKEUP)
lypinator 0:bb348c97df44 2013
lypinator 0:bb348c97df44 2014 /**
lypinator 0:bb348c97df44 2015 * @brief Disables the ETH External interrupt line.
lypinator 0:bb348c97df44 2016 * @retval None
lypinator 0:bb348c97df44 2017 */
lypinator 0:bb348c97df44 2018 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(ETH_EXTI_LINE_WAKEUP)
lypinator 0:bb348c97df44 2019
lypinator 0:bb348c97df44 2020 /**
lypinator 0:bb348c97df44 2021 * @brief Enable event on ETH External event line.
lypinator 0:bb348c97df44 2022 * @retval None.
lypinator 0:bb348c97df44 2023 */
lypinator 0:bb348c97df44 2024 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_EVENT() EXTI->EMR |= (ETH_EXTI_LINE_WAKEUP)
lypinator 0:bb348c97df44 2025
lypinator 0:bb348c97df44 2026 /**
lypinator 0:bb348c97df44 2027 * @brief Disable event on ETH External event line
lypinator 0:bb348c97df44 2028 * @retval None.
lypinator 0:bb348c97df44 2029 */
lypinator 0:bb348c97df44 2030 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_EVENT() EXTI->EMR &= ~(ETH_EXTI_LINE_WAKEUP)
lypinator 0:bb348c97df44 2031
lypinator 0:bb348c97df44 2032 /**
lypinator 0:bb348c97df44 2033 * @brief Get flag of the ETH External interrupt line.
lypinator 0:bb348c97df44 2034 * @retval None
lypinator 0:bb348c97df44 2035 */
lypinator 0:bb348c97df44 2036 #define __HAL_ETH_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (ETH_EXTI_LINE_WAKEUP)
lypinator 0:bb348c97df44 2037
lypinator 0:bb348c97df44 2038 /**
lypinator 0:bb348c97df44 2039 * @brief Clear flag of the ETH External interrupt line.
lypinator 0:bb348c97df44 2040 * @retval None
lypinator 0:bb348c97df44 2041 */
lypinator 0:bb348c97df44 2042 #define __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = (ETH_EXTI_LINE_WAKEUP)
lypinator 0:bb348c97df44 2043
lypinator 0:bb348c97df44 2044 /**
lypinator 0:bb348c97df44 2045 * @brief Enables rising edge trigger to the ETH External interrupt line.
lypinator 0:bb348c97df44 2046 * @retval None
lypinator 0:bb348c97df44 2047 */
lypinator 0:bb348c97df44 2048 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER() EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP
lypinator 0:bb348c97df44 2049
lypinator 0:bb348c97df44 2050 /**
lypinator 0:bb348c97df44 2051 * @brief Disables the rising edge trigger to the ETH External interrupt line.
lypinator 0:bb348c97df44 2052 * @retval None
lypinator 0:bb348c97df44 2053 */
lypinator 0:bb348c97df44 2054 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_RISING_EDGE_TRIGGER() EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP)
lypinator 0:bb348c97df44 2055
lypinator 0:bb348c97df44 2056 /**
lypinator 0:bb348c97df44 2057 * @brief Enables falling edge trigger to the ETH External interrupt line.
lypinator 0:bb348c97df44 2058 * @retval None
lypinator 0:bb348c97df44 2059 */
lypinator 0:bb348c97df44 2060 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR |= (ETH_EXTI_LINE_WAKEUP)
lypinator 0:bb348c97df44 2061
lypinator 0:bb348c97df44 2062 /**
lypinator 0:bb348c97df44 2063 * @brief Disables falling edge trigger to the ETH External interrupt line.
lypinator 0:bb348c97df44 2064 * @retval None
lypinator 0:bb348c97df44 2065 */
lypinator 0:bb348c97df44 2066 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP)
lypinator 0:bb348c97df44 2067
lypinator 0:bb348c97df44 2068 /**
lypinator 0:bb348c97df44 2069 * @brief Enables rising/falling edge trigger to the ETH External interrupt line.
lypinator 0:bb348c97df44 2070 * @retval None
lypinator 0:bb348c97df44 2071 */
lypinator 0:bb348c97df44 2072 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER() do{EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP;\
lypinator 0:bb348c97df44 2073 EXTI->FTSR |= ETH_EXTI_LINE_WAKEUP;\
lypinator 0:bb348c97df44 2074 }while(0U)
lypinator 0:bb348c97df44 2075
lypinator 0:bb348c97df44 2076 /**
lypinator 0:bb348c97df44 2077 * @brief Disables rising/falling edge trigger to the ETH External interrupt line.
lypinator 0:bb348c97df44 2078 * @retval None
lypinator 0:bb348c97df44 2079 */
lypinator 0:bb348c97df44 2080 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLINGRISING_TRIGGER() do{EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP);\
lypinator 0:bb348c97df44 2081 EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP);\
lypinator 0:bb348c97df44 2082 }while(0U)
lypinator 0:bb348c97df44 2083
lypinator 0:bb348c97df44 2084 /**
lypinator 0:bb348c97df44 2085 * @brief Generate a Software interrupt on selected EXTI line.
lypinator 0:bb348c97df44 2086 * @retval None.
lypinator 0:bb348c97df44 2087 */
lypinator 0:bb348c97df44 2088 #define __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT() EXTI->SWIER|= ETH_EXTI_LINE_WAKEUP
lypinator 0:bb348c97df44 2089
lypinator 0:bb348c97df44 2090 /**
lypinator 0:bb348c97df44 2091 * @}
lypinator 0:bb348c97df44 2092 */
lypinator 0:bb348c97df44 2093 /* Exported functions --------------------------------------------------------*/
lypinator 0:bb348c97df44 2094
lypinator 0:bb348c97df44 2095 /** @addtogroup ETH_Exported_Functions
lypinator 0:bb348c97df44 2096 * @{
lypinator 0:bb348c97df44 2097 */
lypinator 0:bb348c97df44 2098
lypinator 0:bb348c97df44 2099 /* Initialization and de-initialization functions ****************************/
lypinator 0:bb348c97df44 2100
lypinator 0:bb348c97df44 2101 /** @addtogroup ETH_Exported_Functions_Group1
lypinator 0:bb348c97df44 2102 * @{
lypinator 0:bb348c97df44 2103 */
lypinator 0:bb348c97df44 2104 HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth);
lypinator 0:bb348c97df44 2105 HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth);
lypinator 0:bb348c97df44 2106 void HAL_ETH_MspInit(ETH_HandleTypeDef *heth);
lypinator 0:bb348c97df44 2107 void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth);
lypinator 0:bb348c97df44 2108 HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount);
lypinator 0:bb348c97df44 2109 HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount);
lypinator 0:bb348c97df44 2110
lypinator 0:bb348c97df44 2111 /**
lypinator 0:bb348c97df44 2112 * @}
lypinator 0:bb348c97df44 2113 */
lypinator 0:bb348c97df44 2114 /* IO operation functions ****************************************************/
lypinator 0:bb348c97df44 2115
lypinator 0:bb348c97df44 2116 /** @addtogroup ETH_Exported_Functions_Group2
lypinator 0:bb348c97df44 2117 * @{
lypinator 0:bb348c97df44 2118 */
lypinator 0:bb348c97df44 2119 HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength);
lypinator 0:bb348c97df44 2120 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth);
lypinator 0:bb348c97df44 2121 /* Communication with PHY functions*/
lypinator 0:bb348c97df44 2122 HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue);
lypinator 0:bb348c97df44 2123 HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue);
lypinator 0:bb348c97df44 2124 /* Non-Blocking mode: Interrupt */
lypinator 0:bb348c97df44 2125 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth);
lypinator 0:bb348c97df44 2126 void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth);
lypinator 0:bb348c97df44 2127 /* Callback in non blocking modes (Interrupt) */
lypinator 0:bb348c97df44 2128 void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth);
lypinator 0:bb348c97df44 2129 void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth);
lypinator 0:bb348c97df44 2130 void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth);
lypinator 0:bb348c97df44 2131 /**
lypinator 0:bb348c97df44 2132 * @}
lypinator 0:bb348c97df44 2133 */
lypinator 0:bb348c97df44 2134
lypinator 0:bb348c97df44 2135 /* Peripheral Control functions **********************************************/
lypinator 0:bb348c97df44 2136
lypinator 0:bb348c97df44 2137 /** @addtogroup ETH_Exported_Functions_Group3
lypinator 0:bb348c97df44 2138 * @{
lypinator 0:bb348c97df44 2139 */
lypinator 0:bb348c97df44 2140
lypinator 0:bb348c97df44 2141 HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth);
lypinator 0:bb348c97df44 2142 HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth);
lypinator 0:bb348c97df44 2143 HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf);
lypinator 0:bb348c97df44 2144 HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf);
lypinator 0:bb348c97df44 2145 /**
lypinator 0:bb348c97df44 2146 * @}
lypinator 0:bb348c97df44 2147 */
lypinator 0:bb348c97df44 2148
lypinator 0:bb348c97df44 2149 /* Peripheral State functions ************************************************/
lypinator 0:bb348c97df44 2150
lypinator 0:bb348c97df44 2151 /** @addtogroup ETH_Exported_Functions_Group4
lypinator 0:bb348c97df44 2152 * @{
lypinator 0:bb348c97df44 2153 */
lypinator 0:bb348c97df44 2154 HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth);
lypinator 0:bb348c97df44 2155 /**
lypinator 0:bb348c97df44 2156 * @}
lypinator 0:bb348c97df44 2157 */
lypinator 0:bb348c97df44 2158
lypinator 0:bb348c97df44 2159 /**
lypinator 0:bb348c97df44 2160 * @}
lypinator 0:bb348c97df44 2161 */
lypinator 0:bb348c97df44 2162
lypinator 0:bb348c97df44 2163 /**
lypinator 0:bb348c97df44 2164 * @}
lypinator 0:bb348c97df44 2165 */
lypinator 0:bb348c97df44 2166
lypinator 0:bb348c97df44 2167 /**
lypinator 0:bb348c97df44 2168 * @}
lypinator 0:bb348c97df44 2169 */
lypinator 0:bb348c97df44 2170
lypinator 0:bb348c97df44 2171 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx ||\
lypinator 0:bb348c97df44 2172 STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
lypinator 0:bb348c97df44 2173
lypinator 0:bb348c97df44 2174 #ifdef __cplusplus
lypinator 0:bb348c97df44 2175 }
lypinator 0:bb348c97df44 2176 #endif
lypinator 0:bb348c97df44 2177
lypinator 0:bb348c97df44 2178 #endif /* __STM32F4xx_HAL_ETH_H */
lypinator 0:bb348c97df44 2179
lypinator 0:bb348c97df44 2180
lypinator 0:bb348c97df44 2181 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/