Thomas Lyp / DevLibMemoryController

Initial commit

Dependencies:   FastPWM

mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_eth.c@0:bb348c97df44, 2020-09-16 (annotated)

Committer:
lypinator
Date:
Wed Sep 16 01:11:49 2020 +0000
Revision:
0:bb348c97df44
Added PWM

Who changed what in which revision?

UserRevisionLine numberNew contents of line
lypinator 0:bb348c97df44 1 /**
lypinator 0:bb348c97df44 2 ******************************************************************************
lypinator 0:bb348c97df44 3 * @file stm32f4xx_hal_eth.c
lypinator 0:bb348c97df44 4 * @author MCD Application Team
lypinator 0:bb348c97df44 5 * @brief ETH HAL module driver.
lypinator 0:bb348c97df44 6 * This file provides firmware functions to manage the following
lypinator 0:bb348c97df44 7 * functionalities of the Ethernet (ETH) peripheral:
lypinator 0:bb348c97df44 8 * + Initialization and de-initialization functions
lypinator 0:bb348c97df44 9 * + IO operation functions
lypinator 0:bb348c97df44 10 * + Peripheral Control functions
lypinator 0:bb348c97df44 11 * + Peripheral State and Errors functions
lypinator 0:bb348c97df44 12 *
lypinator 0:bb348c97df44 13 @verbatim
lypinator 0:bb348c97df44 14 ==============================================================================
lypinator 0:bb348c97df44 15 ##### How to use this driver #####
lypinator 0:bb348c97df44 16 ==============================================================================
lypinator 0:bb348c97df44 17 [..]
lypinator 0:bb348c97df44 18 (#)Declare a ETH_HandleTypeDef handle structure, for example:
lypinator 0:bb348c97df44 19 ETH_HandleTypeDef heth;
lypinator 0:bb348c97df44 20
lypinator 0:bb348c97df44 21 (#)Fill parameters of Init structure in heth handle
lypinator 0:bb348c97df44 22
lypinator 0:bb348c97df44 23 (#)Call HAL_ETH_Init() API to initialize the Ethernet peripheral (MAC, DMA, ...)
lypinator 0:bb348c97df44 24
lypinator 0:bb348c97df44 25 (#)Initialize the ETH low level resources through the HAL_ETH_MspInit() API:
lypinator 0:bb348c97df44 26 (##) Enable the Ethernet interface clock using
lypinator 0:bb348c97df44 27 (+++) __HAL_RCC_ETHMAC_CLK_ENABLE();
lypinator 0:bb348c97df44 28 (+++) __HAL_RCC_ETHMACTX_CLK_ENABLE();
lypinator 0:bb348c97df44 29 (+++) __HAL_RCC_ETHMACRX_CLK_ENABLE();
lypinator 0:bb348c97df44 30
lypinator 0:bb348c97df44 31 (##) Initialize the related GPIO clocks
lypinator 0:bb348c97df44 32 (##) Configure Ethernet pin-out
lypinator 0:bb348c97df44 33 (##) Configure Ethernet NVIC interrupt (IT mode)
lypinator 0:bb348c97df44 34
lypinator 0:bb348c97df44 35 (#)Initialize Ethernet DMA Descriptors in chain mode and point to allocated buffers:
lypinator 0:bb348c97df44 36 (##) HAL_ETH_DMATxDescListInit(); for Transmission process
lypinator 0:bb348c97df44 37 (##) HAL_ETH_DMARxDescListInit(); for Reception process
lypinator 0:bb348c97df44 38
lypinator 0:bb348c97df44 39 (#)Enable MAC and DMA transmission and reception:
lypinator 0:bb348c97df44 40 (##) HAL_ETH_Start();
lypinator 0:bb348c97df44 41
lypinator 0:bb348c97df44 42 (#)Prepare ETH DMA TX Descriptors and give the hand to ETH DMA to transfer
lypinator 0:bb348c97df44 43 the frame to MAC TX FIFO:
lypinator 0:bb348c97df44 44 (##) HAL_ETH_TransmitFrame();
lypinator 0:bb348c97df44 45
lypinator 0:bb348c97df44 46 (#)Poll for a received frame in ETH RX DMA Descriptors and get received
lypinator 0:bb348c97df44 47 frame parameters
lypinator 0:bb348c97df44 48 (##) HAL_ETH_GetReceivedFrame(); (should be called into an infinite loop)
lypinator 0:bb348c97df44 49
lypinator 0:bb348c97df44 50 (#) Get a received frame when an ETH RX interrupt occurs:
lypinator 0:bb348c97df44 51 (##) HAL_ETH_GetReceivedFrame_IT(); (called in IT mode only)
lypinator 0:bb348c97df44 52
lypinator 0:bb348c97df44 53 (#) Communicate with external PHY device:
lypinator 0:bb348c97df44 54 (##) Read a specific register from the PHY
lypinator 0:bb348c97df44 55 HAL_ETH_ReadPHYRegister();
lypinator 0:bb348c97df44 56 (##) Write data to a specific RHY register:
lypinator 0:bb348c97df44 57 HAL_ETH_WritePHYRegister();
lypinator 0:bb348c97df44 58
lypinator 0:bb348c97df44 59 (#) Configure the Ethernet MAC after ETH peripheral initialization
lypinator 0:bb348c97df44 60 HAL_ETH_ConfigMAC(); all MAC parameters should be filled.
lypinator 0:bb348c97df44 61
lypinator 0:bb348c97df44 62 (#) Configure the Ethernet DMA after ETH peripheral initialization
lypinator 0:bb348c97df44 63 HAL_ETH_ConfigDMA(); all DMA parameters should be filled.
lypinator 0:bb348c97df44 64
lypinator 0:bb348c97df44 65 -@- The PTP protocol and the DMA descriptors ring mode are not supported
lypinator 0:bb348c97df44 66 in this driver
lypinator 0:bb348c97df44 67
lypinator 0:bb348c97df44 68 @endverbatim
lypinator 0:bb348c97df44 69 ******************************************************************************
lypinator 0:bb348c97df44 70 * @attention
lypinator 0:bb348c97df44 71 *
lypinator 0:bb348c97df44 72 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
lypinator 0:bb348c97df44 73 *
lypinator 0:bb348c97df44 74 * Redistribution and use in source and binary forms, with or without modification,
lypinator 0:bb348c97df44 75 * are permitted provided that the following conditions are met:
lypinator 0:bb348c97df44 76 * 1. Redistributions of source code must retain the above copyright notice,
lypinator 0:bb348c97df44 77 * this list of conditions and the following disclaimer.
lypinator 0:bb348c97df44 78 * 2. Redistributions in binary form must reproduce the above copyright notice,
lypinator 0:bb348c97df44 79 * this list of conditions and the following disclaimer in the documentation
lypinator 0:bb348c97df44 80 * and/or other materials provided with the distribution.
lypinator 0:bb348c97df44 81 * 3. Neither the name of STMicroelectronics nor the names of its contributors
lypinator 0:bb348c97df44 82 * may be used to endorse or promote products derived from this software
lypinator 0:bb348c97df44 83 * without specific prior written permission.
lypinator 0:bb348c97df44 84 *
lypinator 0:bb348c97df44 85 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
lypinator 0:bb348c97df44 86 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
lypinator 0:bb348c97df44 87 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
lypinator 0:bb348c97df44 88 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
lypinator 0:bb348c97df44 89 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
lypinator 0:bb348c97df44 90 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
lypinator 0:bb348c97df44 91 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
lypinator 0:bb348c97df44 92 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
lypinator 0:bb348c97df44 93 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
lypinator 0:bb348c97df44 94 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
lypinator 0:bb348c97df44 95 *
lypinator 0:bb348c97df44 96 ******************************************************************************
lypinator 0:bb348c97df44 97 */
lypinator 0:bb348c97df44 98
lypinator 0:bb348c97df44 99 /* Includes ------------------------------------------------------------------*/
lypinator 0:bb348c97df44 100 #include "stm32f4xx_hal.h"
lypinator 0:bb348c97df44 101
lypinator 0:bb348c97df44 102 /** @addtogroup STM32F4xx_HAL_Driver
lypinator 0:bb348c97df44 103 * @{
lypinator 0:bb348c97df44 104 */
lypinator 0:bb348c97df44 105
lypinator 0:bb348c97df44 106 /** @defgroup ETH ETH
lypinator 0:bb348c97df44 107 * @brief ETH HAL module driver
lypinator 0:bb348c97df44 108 * @{
lypinator 0:bb348c97df44 109 */
lypinator 0:bb348c97df44 110
lypinator 0:bb348c97df44 111 #ifdef HAL_ETH_MODULE_ENABLED
lypinator 0:bb348c97df44 112
lypinator 0:bb348c97df44 113 #if defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) ||\
lypinator 0:bb348c97df44 114 defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
lypinator 0:bb348c97df44 115
lypinator 0:bb348c97df44 116 /* Private typedef -----------------------------------------------------------*/
lypinator 0:bb348c97df44 117 /* Private define ------------------------------------------------------------*/
lypinator 0:bb348c97df44 118 /** @defgroup ETH_Private_Constants ETH Private Constants
lypinator 0:bb348c97df44 119 * @{
lypinator 0:bb348c97df44 120 */
lypinator 0:bb348c97df44 121 #define ETH_TIMEOUT_SWRESET 500U
lypinator 0:bb348c97df44 122 #define ETH_TIMEOUT_LINKED_STATE 5000U
lypinator 0:bb348c97df44 123 #define ETH_TIMEOUT_AUTONEGO_COMPLETED 5000U
lypinator 0:bb348c97df44 124
lypinator 0:bb348c97df44 125 /**
lypinator 0:bb348c97df44 126 * @}
lypinator 0:bb348c97df44 127 */
lypinator 0:bb348c97df44 128 /* Private macro -------------------------------------------------------------*/
lypinator 0:bb348c97df44 129 /* Private variables ---------------------------------------------------------*/
lypinator 0:bb348c97df44 130 /* Private function prototypes -----------------------------------------------*/
lypinator 0:bb348c97df44 131 /** @defgroup ETH_Private_Functions ETH Private Functions
lypinator 0:bb348c97df44 132 * @{
lypinator 0:bb348c97df44 133 */
lypinator 0:bb348c97df44 134 static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err);
lypinator 0:bb348c97df44 135 static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr);
lypinator 0:bb348c97df44 136 static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth);
lypinator 0:bb348c97df44 137 static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth);
lypinator 0:bb348c97df44 138 static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth);
lypinator 0:bb348c97df44 139 static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth);
lypinator 0:bb348c97df44 140 static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth);
lypinator 0:bb348c97df44 141 static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth);
lypinator 0:bb348c97df44 142 static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth);
lypinator 0:bb348c97df44 143 static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth);
lypinator 0:bb348c97df44 144 static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth);
lypinator 0:bb348c97df44 145 static void ETH_Delay(uint32_t mdelay);
lypinator 0:bb348c97df44 146
lypinator 0:bb348c97df44 147 /**
lypinator 0:bb348c97df44 148 * @}
lypinator 0:bb348c97df44 149 */
lypinator 0:bb348c97df44 150 /* Private functions ---------------------------------------------------------*/
lypinator 0:bb348c97df44 151
lypinator 0:bb348c97df44 152 /** @defgroup ETH_Exported_Functions ETH Exported Functions
lypinator 0:bb348c97df44 153 * @{
lypinator 0:bb348c97df44 154 */
lypinator 0:bb348c97df44 155
lypinator 0:bb348c97df44 156 /** @defgroup ETH_Exported_Functions_Group1 Initialization and de-initialization functions
lypinator 0:bb348c97df44 157 * @brief Initialization and Configuration functions
lypinator 0:bb348c97df44 158 *
lypinator 0:bb348c97df44 159 @verbatim
lypinator 0:bb348c97df44 160 ===============================================================================
lypinator 0:bb348c97df44 161 ##### Initialization and de-initialization functions #####
lypinator 0:bb348c97df44 162 ===============================================================================
lypinator 0:bb348c97df44 163 [..] This section provides functions allowing to:
lypinator 0:bb348c97df44 164 (+) Initialize and configure the Ethernet peripheral
lypinator 0:bb348c97df44 165 (+) De-initialize the Ethernet peripheral
lypinator 0:bb348c97df44 166
lypinator 0:bb348c97df44 167 @endverbatim
lypinator 0:bb348c97df44 168 * @{
lypinator 0:bb348c97df44 169 */
lypinator 0:bb348c97df44 170
lypinator 0:bb348c97df44 171 /**
lypinator 0:bb348c97df44 172 * @brief Initializes the Ethernet MAC and DMA according to default
lypinator 0:bb348c97df44 173 * parameters.
lypinator 0:bb348c97df44 174 * @param heth pointer to a ETH_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 175 * the configuration information for ETHERNET module
lypinator 0:bb348c97df44 176 * @retval HAL status
lypinator 0:bb348c97df44 177 */
lypinator 0:bb348c97df44 178 HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
lypinator 0:bb348c97df44 179 {
lypinator 0:bb348c97df44 180 uint32_t tmpreg1 = 0U, phyreg = 0U;
lypinator 0:bb348c97df44 181 uint32_t hclk = 60000000U;
lypinator 0:bb348c97df44 182 uint32_t tickstart = 0U;
lypinator 0:bb348c97df44 183 uint32_t err = ETH_SUCCESS;
lypinator 0:bb348c97df44 184
lypinator 0:bb348c97df44 185 /* Check the ETH peripheral state */
lypinator 0:bb348c97df44 186 if(heth == NULL)
lypinator 0:bb348c97df44 187 {
lypinator 0:bb348c97df44 188 return HAL_ERROR;
lypinator 0:bb348c97df44 189 }
lypinator 0:bb348c97df44 190
lypinator 0:bb348c97df44 191 /* Check parameters */
lypinator 0:bb348c97df44 192 assert_param(IS_ETH_AUTONEGOTIATION(heth->Init.AutoNegotiation));
lypinator 0:bb348c97df44 193 assert_param(IS_ETH_RX_MODE(heth->Init.RxMode));
lypinator 0:bb348c97df44 194 assert_param(IS_ETH_CHECKSUM_MODE(heth->Init.ChecksumMode));
lypinator 0:bb348c97df44 195 assert_param(IS_ETH_MEDIA_INTERFACE(heth->Init.MediaInterface));
lypinator 0:bb348c97df44 196
lypinator 0:bb348c97df44 197 if(heth->State == HAL_ETH_STATE_RESET)
lypinator 0:bb348c97df44 198 {
lypinator 0:bb348c97df44 199 /* Allocate lock resource and initialize it */
lypinator 0:bb348c97df44 200 heth->Lock = HAL_UNLOCKED;
lypinator 0:bb348c97df44 201 /* Init the low level hardware : GPIO, CLOCK, NVIC. */
lypinator 0:bb348c97df44 202 HAL_ETH_MspInit(heth);
lypinator 0:bb348c97df44 203 }
lypinator 0:bb348c97df44 204
lypinator 0:bb348c97df44 205 /* Enable SYSCFG Clock */
lypinator 0:bb348c97df44 206 __HAL_RCC_SYSCFG_CLK_ENABLE();
lypinator 0:bb348c97df44 207
lypinator 0:bb348c97df44 208 /* Select MII or RMII Mode*/
lypinator 0:bb348c97df44 209 SYSCFG->PMC &= ~(SYSCFG_PMC_MII_RMII_SEL);
lypinator 0:bb348c97df44 210 SYSCFG->PMC |= (uint32_t)heth->Init.MediaInterface;
lypinator 0:bb348c97df44 211
lypinator 0:bb348c97df44 212 /* Ethernet Software reset */
lypinator 0:bb348c97df44 213 /* Set the SWR bit: resets all MAC subsystem internal registers and logic */
lypinator 0:bb348c97df44 214 /* After reset all the registers holds their respective reset values */
lypinator 0:bb348c97df44 215 (heth->Instance)->DMABMR |= ETH_DMABMR_SR;
lypinator 0:bb348c97df44 216
lypinator 0:bb348c97df44 217 /* Get tick */
lypinator 0:bb348c97df44 218 tickstart = HAL_GetTick();
lypinator 0:bb348c97df44 219
lypinator 0:bb348c97df44 220 /* Wait for software reset */
lypinator 0:bb348c97df44 221 while (((heth->Instance)->DMABMR & ETH_DMABMR_SR) != (uint32_t)RESET)
lypinator 0:bb348c97df44 222 {
lypinator 0:bb348c97df44 223 /* Check for the Timeout */
lypinator 0:bb348c97df44 224 if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_SWRESET)
lypinator 0:bb348c97df44 225 {
lypinator 0:bb348c97df44 226 heth->State= HAL_ETH_STATE_TIMEOUT;
lypinator 0:bb348c97df44 227
lypinator 0:bb348c97df44 228 /* Process Unlocked */
lypinator 0:bb348c97df44 229 __HAL_UNLOCK(heth);
lypinator 0:bb348c97df44 230
lypinator 0:bb348c97df44 231 /* Note: The SWR is not performed if the ETH_RX_CLK or the ETH_TX_CLK are
lypinator 0:bb348c97df44 232 not available, please check your external PHY or the IO configuration */
lypinator 0:bb348c97df44 233 return HAL_TIMEOUT;
lypinator 0:bb348c97df44 234 }
lypinator 0:bb348c97df44 235 }
lypinator 0:bb348c97df44 236
lypinator 0:bb348c97df44 237 /*-------------------------------- MAC Initialization ----------------------*/
lypinator 0:bb348c97df44 238 /* Get the ETHERNET MACMIIAR value */
lypinator 0:bb348c97df44 239 tmpreg1 = (heth->Instance)->MACMIIAR;
lypinator 0:bb348c97df44 240 /* Clear CSR Clock Range CR[2:0] bits */
lypinator 0:bb348c97df44 241 tmpreg1 &= ETH_MACMIIAR_CR_MASK;
lypinator 0:bb348c97df44 242
lypinator 0:bb348c97df44 243 /* Get hclk frequency value */
lypinator 0:bb348c97df44 244 hclk = HAL_RCC_GetHCLKFreq();
lypinator 0:bb348c97df44 245
lypinator 0:bb348c97df44 246 /* Set CR bits depending on hclk value */
lypinator 0:bb348c97df44 247 if((hclk >= 20000000U)&&(hclk < 35000000U))
lypinator 0:bb348c97df44 248 {
lypinator 0:bb348c97df44 249 /* CSR Clock Range between 20-35 MHz */
lypinator 0:bb348c97df44 250 tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div16;
lypinator 0:bb348c97df44 251 }
lypinator 0:bb348c97df44 252 else if((hclk >= 35000000U)&&(hclk < 60000000U))
lypinator 0:bb348c97df44 253 {
lypinator 0:bb348c97df44 254 /* CSR Clock Range between 35-60 MHz */
lypinator 0:bb348c97df44 255 tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div26;
lypinator 0:bb348c97df44 256 }
lypinator 0:bb348c97df44 257 else if((hclk >= 60000000U)&&(hclk < 100000000U))
lypinator 0:bb348c97df44 258 {
lypinator 0:bb348c97df44 259 /* CSR Clock Range between 60-100 MHz */
lypinator 0:bb348c97df44 260 tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div42;
lypinator 0:bb348c97df44 261 }
lypinator 0:bb348c97df44 262 else if((hclk >= 100000000U)&&(hclk < 150000000U))
lypinator 0:bb348c97df44 263 {
lypinator 0:bb348c97df44 264 /* CSR Clock Range between 100-150 MHz */
lypinator 0:bb348c97df44 265 tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div62;
lypinator 0:bb348c97df44 266 }
lypinator 0:bb348c97df44 267 else /* ((hclk >= 150000000)&&(hclk <= 183000000)) */
lypinator 0:bb348c97df44 268 {
lypinator 0:bb348c97df44 269 /* CSR Clock Range between 150-183 MHz */
lypinator 0:bb348c97df44 270 tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div102;
lypinator 0:bb348c97df44 271 }
lypinator 0:bb348c97df44 272
lypinator 0:bb348c97df44 273 /* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */
lypinator 0:bb348c97df44 274 (heth->Instance)->MACMIIAR = (uint32_t)tmpreg1;
lypinator 0:bb348c97df44 275
lypinator 0:bb348c97df44 276 /*-------------------- PHY initialization and configuration ----------------*/
lypinator 0:bb348c97df44 277 /* Put the PHY in reset mode */
lypinator 0:bb348c97df44 278 if((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_RESET)) != HAL_OK)
lypinator 0:bb348c97df44 279 {
lypinator 0:bb348c97df44 280 /* In case of write timeout */
lypinator 0:bb348c97df44 281 err = ETH_ERROR;
lypinator 0:bb348c97df44 282
lypinator 0:bb348c97df44 283 /* Config MAC and DMA */
lypinator 0:bb348c97df44 284 ETH_MACDMAConfig(heth, err);
lypinator 0:bb348c97df44 285
lypinator 0:bb348c97df44 286 /* Set the ETH peripheral state to READY */
lypinator 0:bb348c97df44 287 heth->State = HAL_ETH_STATE_READY;
lypinator 0:bb348c97df44 288
lypinator 0:bb348c97df44 289 /* Return HAL_ERROR */
lypinator 0:bb348c97df44 290 return HAL_ERROR;
lypinator 0:bb348c97df44 291 }
lypinator 0:bb348c97df44 292
lypinator 0:bb348c97df44 293 /* Delay to assure PHY reset */
lypinator 0:bb348c97df44 294 HAL_Delay(PHY_RESET_DELAY);
lypinator 0:bb348c97df44 295
lypinator 0:bb348c97df44 296 if((heth->Init).AutoNegotiation != ETH_AUTONEGOTIATION_DISABLE)
lypinator 0:bb348c97df44 297 {
lypinator 0:bb348c97df44 298 /* Get tick */
lypinator 0:bb348c97df44 299 tickstart = HAL_GetTick();
lypinator 0:bb348c97df44 300
lypinator 0:bb348c97df44 301 /* We wait for linked status */
lypinator 0:bb348c97df44 302 do
lypinator 0:bb348c97df44 303 {
lypinator 0:bb348c97df44 304 HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg);
lypinator 0:bb348c97df44 305
lypinator 0:bb348c97df44 306 /* Check for the Timeout */
lypinator 0:bb348c97df44 307 if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_LINKED_STATE)
lypinator 0:bb348c97df44 308 {
lypinator 0:bb348c97df44 309 /* In case of write timeout */
lypinator 0:bb348c97df44 310 err = ETH_ERROR;
lypinator 0:bb348c97df44 311
lypinator 0:bb348c97df44 312 /* Config MAC and DMA */
lypinator 0:bb348c97df44 313 ETH_MACDMAConfig(heth, err);
lypinator 0:bb348c97df44 314
lypinator 0:bb348c97df44 315 heth->State= HAL_ETH_STATE_READY;
lypinator 0:bb348c97df44 316
lypinator 0:bb348c97df44 317 /* Process Unlocked */
lypinator 0:bb348c97df44 318 __HAL_UNLOCK(heth);
lypinator 0:bb348c97df44 319
lypinator 0:bb348c97df44 320 return HAL_TIMEOUT;
lypinator 0:bb348c97df44 321 }
lypinator 0:bb348c97df44 322 } while (((phyreg & PHY_LINKED_STATUS) != PHY_LINKED_STATUS));
lypinator 0:bb348c97df44 323
lypinator 0:bb348c97df44 324
lypinator 0:bb348c97df44 325 /* Enable Auto-Negotiation */
lypinator 0:bb348c97df44 326 if((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_AUTONEGOTIATION)) != HAL_OK)
lypinator 0:bb348c97df44 327 {
lypinator 0:bb348c97df44 328 /* In case of write timeout */
lypinator 0:bb348c97df44 329 err = ETH_ERROR;
lypinator 0:bb348c97df44 330
lypinator 0:bb348c97df44 331 /* Config MAC and DMA */
lypinator 0:bb348c97df44 332 ETH_MACDMAConfig(heth, err);
lypinator 0:bb348c97df44 333
lypinator 0:bb348c97df44 334 /* Set the ETH peripheral state to READY */
lypinator 0:bb348c97df44 335 heth->State = HAL_ETH_STATE_READY;
lypinator 0:bb348c97df44 336
lypinator 0:bb348c97df44 337 /* Return HAL_ERROR */
lypinator 0:bb348c97df44 338 return HAL_ERROR;
lypinator 0:bb348c97df44 339 }
lypinator 0:bb348c97df44 340
lypinator 0:bb348c97df44 341 /* Get tick */
lypinator 0:bb348c97df44 342 tickstart = HAL_GetTick();
lypinator 0:bb348c97df44 343
lypinator 0:bb348c97df44 344 /* Wait until the auto-negotiation will be completed */
lypinator 0:bb348c97df44 345 do
lypinator 0:bb348c97df44 346 {
lypinator 0:bb348c97df44 347 HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg);
lypinator 0:bb348c97df44 348
lypinator 0:bb348c97df44 349 /* Check for the Timeout */
lypinator 0:bb348c97df44 350 if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_AUTONEGO_COMPLETED)
lypinator 0:bb348c97df44 351 {
lypinator 0:bb348c97df44 352 /* In case of write timeout */
lypinator 0:bb348c97df44 353 err = ETH_ERROR;
lypinator 0:bb348c97df44 354
lypinator 0:bb348c97df44 355 /* Config MAC and DMA */
lypinator 0:bb348c97df44 356 ETH_MACDMAConfig(heth, err);
lypinator 0:bb348c97df44 357
lypinator 0:bb348c97df44 358 heth->State= HAL_ETH_STATE_READY;
lypinator 0:bb348c97df44 359
lypinator 0:bb348c97df44 360 /* Process Unlocked */
lypinator 0:bb348c97df44 361 __HAL_UNLOCK(heth);
lypinator 0:bb348c97df44 362
lypinator 0:bb348c97df44 363 return HAL_TIMEOUT;
lypinator 0:bb348c97df44 364 }
lypinator 0:bb348c97df44 365
lypinator 0:bb348c97df44 366 } while (((phyreg & PHY_AUTONEGO_COMPLETE) != PHY_AUTONEGO_COMPLETE));
lypinator 0:bb348c97df44 367
lypinator 0:bb348c97df44 368 /* Read the result of the auto-negotiation */
lypinator 0:bb348c97df44 369 if((HAL_ETH_ReadPHYRegister(heth, PHY_SR, &phyreg)) != HAL_OK)
lypinator 0:bb348c97df44 370 {
lypinator 0:bb348c97df44 371 /* In case of write timeout */
lypinator 0:bb348c97df44 372 err = ETH_ERROR;
lypinator 0:bb348c97df44 373
lypinator 0:bb348c97df44 374 /* Config MAC and DMA */
lypinator 0:bb348c97df44 375 ETH_MACDMAConfig(heth, err);
lypinator 0:bb348c97df44 376
lypinator 0:bb348c97df44 377 /* Set the ETH peripheral state to READY */
lypinator 0:bb348c97df44 378 heth->State = HAL_ETH_STATE_READY;
lypinator 0:bb348c97df44 379
lypinator 0:bb348c97df44 380 /* Return HAL_ERROR */
lypinator 0:bb348c97df44 381 return HAL_ERROR;
lypinator 0:bb348c97df44 382 }
lypinator 0:bb348c97df44 383
lypinator 0:bb348c97df44 384 /* Configure the MAC with the Duplex Mode fixed by the auto-negotiation process */
lypinator 0:bb348c97df44 385 if((phyreg & PHY_DUPLEX_STATUS) != (uint32_t)RESET)
lypinator 0:bb348c97df44 386 {
lypinator 0:bb348c97df44 387 /* Set Ethernet duplex mode to Full-duplex following the auto-negotiation */
lypinator 0:bb348c97df44 388 (heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX;
lypinator 0:bb348c97df44 389 }
lypinator 0:bb348c97df44 390 else
lypinator 0:bb348c97df44 391 {
lypinator 0:bb348c97df44 392 /* Set Ethernet duplex mode to Half-duplex following the auto-negotiation */
lypinator 0:bb348c97df44 393 (heth->Init).DuplexMode = ETH_MODE_HALFDUPLEX;
lypinator 0:bb348c97df44 394 }
lypinator 0:bb348c97df44 395 /* Configure the MAC with the speed fixed by the auto-negotiation process */
lypinator 0:bb348c97df44 396 if((phyreg & PHY_SPEED_STATUS) == PHY_SPEED_STATUS)
lypinator 0:bb348c97df44 397 {
lypinator 0:bb348c97df44 398 /* Set Ethernet speed to 10M following the auto-negotiation */
lypinator 0:bb348c97df44 399 (heth->Init).Speed = ETH_SPEED_10M;
lypinator 0:bb348c97df44 400 }
lypinator 0:bb348c97df44 401 else
lypinator 0:bb348c97df44 402 {
lypinator 0:bb348c97df44 403 /* Set Ethernet speed to 100M following the auto-negotiation */
lypinator 0:bb348c97df44 404 (heth->Init).Speed = ETH_SPEED_100M;
lypinator 0:bb348c97df44 405 }
lypinator 0:bb348c97df44 406 }
lypinator 0:bb348c97df44 407 else /* AutoNegotiation Disable */
lypinator 0:bb348c97df44 408 {
lypinator 0:bb348c97df44 409 /* Check parameters */
lypinator 0:bb348c97df44 410 assert_param(IS_ETH_SPEED(heth->Init.Speed));
lypinator 0:bb348c97df44 411 assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode));
lypinator 0:bb348c97df44 412
lypinator 0:bb348c97df44 413 /* Set MAC Speed and Duplex Mode */
lypinator 0:bb348c97df44 414 if(HAL_ETH_WritePHYRegister(heth, PHY_BCR, ((uint16_t)((heth->Init).DuplexMode >> 3U) |
lypinator 0:bb348c97df44 415 (uint16_t)((heth->Init).Speed >> 1U))) != HAL_OK)
lypinator 0:bb348c97df44 416 {
lypinator 0:bb348c97df44 417 /* In case of write timeout */
lypinator 0:bb348c97df44 418 err = ETH_ERROR;
lypinator 0:bb348c97df44 419
lypinator 0:bb348c97df44 420 /* Config MAC and DMA */
lypinator 0:bb348c97df44 421 ETH_MACDMAConfig(heth, err);
lypinator 0:bb348c97df44 422
lypinator 0:bb348c97df44 423 /* Set the ETH peripheral state to READY */
lypinator 0:bb348c97df44 424 heth->State = HAL_ETH_STATE_READY;
lypinator 0:bb348c97df44 425
lypinator 0:bb348c97df44 426 /* Return HAL_ERROR */
lypinator 0:bb348c97df44 427 return HAL_ERROR;
lypinator 0:bb348c97df44 428 }
lypinator 0:bb348c97df44 429
lypinator 0:bb348c97df44 430 /* Delay to assure PHY configuration */
lypinator 0:bb348c97df44 431 HAL_Delay(PHY_CONFIG_DELAY);
lypinator 0:bb348c97df44 432 }
lypinator 0:bb348c97df44 433
lypinator 0:bb348c97df44 434 /* Config MAC and DMA */
lypinator 0:bb348c97df44 435 ETH_MACDMAConfig(heth, err);
lypinator 0:bb348c97df44 436
lypinator 0:bb348c97df44 437 /* Set ETH HAL State to Ready */
lypinator 0:bb348c97df44 438 heth->State= HAL_ETH_STATE_READY;
lypinator 0:bb348c97df44 439
lypinator 0:bb348c97df44 440 /* Return function status */
lypinator 0:bb348c97df44 441 return HAL_OK;
lypinator 0:bb348c97df44 442 }
lypinator 0:bb348c97df44 443
lypinator 0:bb348c97df44 444 /**
lypinator 0:bb348c97df44 445 * @brief De-Initializes the ETH peripheral.
lypinator 0:bb348c97df44 446 * @param heth pointer to a ETH_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 447 * the configuration information for ETHERNET module
lypinator 0:bb348c97df44 448 * @retval HAL status
lypinator 0:bb348c97df44 449 */
lypinator 0:bb348c97df44 450 HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth)
lypinator 0:bb348c97df44 451 {
lypinator 0:bb348c97df44 452 /* Set the ETH peripheral state to BUSY */
lypinator 0:bb348c97df44 453 heth->State = HAL_ETH_STATE_BUSY;
lypinator 0:bb348c97df44 454
lypinator 0:bb348c97df44 455 /* De-Init the low level hardware : GPIO, CLOCK, NVIC. */
lypinator 0:bb348c97df44 456 HAL_ETH_MspDeInit(heth);
lypinator 0:bb348c97df44 457
lypinator 0:bb348c97df44 458 /* Set ETH HAL state to Disabled */
lypinator 0:bb348c97df44 459 heth->State= HAL_ETH_STATE_RESET;
lypinator 0:bb348c97df44 460
lypinator 0:bb348c97df44 461 /* Release Lock */
lypinator 0:bb348c97df44 462 __HAL_UNLOCK(heth);
lypinator 0:bb348c97df44 463
lypinator 0:bb348c97df44 464 /* Return function status */
lypinator 0:bb348c97df44 465 return HAL_OK;
lypinator 0:bb348c97df44 466 }
lypinator 0:bb348c97df44 467
lypinator 0:bb348c97df44 468 /**
lypinator 0:bb348c97df44 469 * @brief Initializes the DMA Tx descriptors in chain mode.
lypinator 0:bb348c97df44 470 * @param heth pointer to a ETH_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 471 * the configuration information for ETHERNET module
lypinator 0:bb348c97df44 472 * @param DMATxDescTab Pointer to the first Tx desc list
lypinator 0:bb348c97df44 473 * @param TxBuff Pointer to the first TxBuffer list
lypinator 0:bb348c97df44 474 * @param TxBuffCount Number of the used Tx desc in the list
lypinator 0:bb348c97df44 475 * @retval HAL status
lypinator 0:bb348c97df44 476 */
lypinator 0:bb348c97df44 477 HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t *TxBuff, uint32_t TxBuffCount)
lypinator 0:bb348c97df44 478 {
lypinator 0:bb348c97df44 479 uint32_t i = 0U;
lypinator 0:bb348c97df44 480 ETH_DMADescTypeDef *dmatxdesc;
lypinator 0:bb348c97df44 481
lypinator 0:bb348c97df44 482 /* Process Locked */
lypinator 0:bb348c97df44 483 __HAL_LOCK(heth);
lypinator 0:bb348c97df44 484
lypinator 0:bb348c97df44 485 /* Set the ETH peripheral state to BUSY */
lypinator 0:bb348c97df44 486 heth->State = HAL_ETH_STATE_BUSY;
lypinator 0:bb348c97df44 487
lypinator 0:bb348c97df44 488 /* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */
lypinator 0:bb348c97df44 489 heth->TxDesc = DMATxDescTab;
lypinator 0:bb348c97df44 490
lypinator 0:bb348c97df44 491 /* Fill each DMATxDesc descriptor with the right values */
lypinator 0:bb348c97df44 492 for(i=0U; i < TxBuffCount; i++)
lypinator 0:bb348c97df44 493 {
lypinator 0:bb348c97df44 494 /* Get the pointer on the ith member of the Tx Desc list */
lypinator 0:bb348c97df44 495 dmatxdesc = DMATxDescTab + i;
lypinator 0:bb348c97df44 496
lypinator 0:bb348c97df44 497 /* Set Second Address Chained bit */
lypinator 0:bb348c97df44 498 dmatxdesc->Status = ETH_DMATXDESC_TCH;
lypinator 0:bb348c97df44 499
lypinator 0:bb348c97df44 500 /* Set Buffer1 address pointer */
lypinator 0:bb348c97df44 501 dmatxdesc->Buffer1Addr = (uint32_t)(&TxBuff[i*ETH_TX_BUF_SIZE]);
lypinator 0:bb348c97df44 502
lypinator 0:bb348c97df44 503 if ((heth->Init).ChecksumMode == ETH_CHECKSUM_BY_HARDWARE)
lypinator 0:bb348c97df44 504 {
lypinator 0:bb348c97df44 505 /* Set the DMA Tx descriptors checksum insertion */
lypinator 0:bb348c97df44 506 dmatxdesc->Status |= ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL;
lypinator 0:bb348c97df44 507 }
lypinator 0:bb348c97df44 508
lypinator 0:bb348c97df44 509 /* Initialize the next descriptor with the Next Descriptor Polling Enable */
lypinator 0:bb348c97df44 510 if(i < (TxBuffCount-1U))
lypinator 0:bb348c97df44 511 {
lypinator 0:bb348c97df44 512 /* Set next descriptor address register with next descriptor base address */
lypinator 0:bb348c97df44 513 dmatxdesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab+i+1U);
lypinator 0:bb348c97df44 514 }
lypinator 0:bb348c97df44 515 else
lypinator 0:bb348c97df44 516 {
lypinator 0:bb348c97df44 517 /* For last descriptor, set next descriptor address register equal to the first descriptor base address */
lypinator 0:bb348c97df44 518 dmatxdesc->Buffer2NextDescAddr = (uint32_t) DMATxDescTab;
lypinator 0:bb348c97df44 519 }
lypinator 0:bb348c97df44 520 }
lypinator 0:bb348c97df44 521
lypinator 0:bb348c97df44 522 /* Set Transmit Descriptor List Address Register */
lypinator 0:bb348c97df44 523 (heth->Instance)->DMATDLAR = (uint32_t) DMATxDescTab;
lypinator 0:bb348c97df44 524
lypinator 0:bb348c97df44 525 /* Set ETH HAL State to Ready */
lypinator 0:bb348c97df44 526 heth->State= HAL_ETH_STATE_READY;
lypinator 0:bb348c97df44 527
lypinator 0:bb348c97df44 528 /* Process Unlocked */
lypinator 0:bb348c97df44 529 __HAL_UNLOCK(heth);
lypinator 0:bb348c97df44 530
lypinator 0:bb348c97df44 531 /* Return function status */
lypinator 0:bb348c97df44 532 return HAL_OK;
lypinator 0:bb348c97df44 533 }
lypinator 0:bb348c97df44 534
lypinator 0:bb348c97df44 535 /**
lypinator 0:bb348c97df44 536 * @brief Initializes the DMA Rx descriptors in chain mode.
lypinator 0:bb348c97df44 537 * @param heth pointer to a ETH_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 538 * the configuration information for ETHERNET module
lypinator 0:bb348c97df44 539 * @param DMARxDescTab Pointer to the first Rx desc list
lypinator 0:bb348c97df44 540 * @param RxBuff Pointer to the first RxBuffer list
lypinator 0:bb348c97df44 541 * @param RxBuffCount Number of the used Rx desc in the list
lypinator 0:bb348c97df44 542 * @retval HAL status
lypinator 0:bb348c97df44 543 */
lypinator 0:bb348c97df44 544 HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount)
lypinator 0:bb348c97df44 545 {
lypinator 0:bb348c97df44 546 uint32_t i = 0U;
lypinator 0:bb348c97df44 547 ETH_DMADescTypeDef *DMARxDesc;
lypinator 0:bb348c97df44 548
lypinator 0:bb348c97df44 549 /* Process Locked */
lypinator 0:bb348c97df44 550 __HAL_LOCK(heth);
lypinator 0:bb348c97df44 551
lypinator 0:bb348c97df44 552 /* Set the ETH peripheral state to BUSY */
lypinator 0:bb348c97df44 553 heth->State = HAL_ETH_STATE_BUSY;
lypinator 0:bb348c97df44 554
lypinator 0:bb348c97df44 555 /* Set the Ethernet RxDesc pointer with the first one of the DMARxDescTab list */
lypinator 0:bb348c97df44 556 heth->RxDesc = DMARxDescTab;
lypinator 0:bb348c97df44 557
lypinator 0:bb348c97df44 558 /* Fill each DMARxDesc descriptor with the right values */
lypinator 0:bb348c97df44 559 for(i=0U; i < RxBuffCount; i++)
lypinator 0:bb348c97df44 560 {
lypinator 0:bb348c97df44 561 /* Get the pointer on the ith member of the Rx Desc list */
lypinator 0:bb348c97df44 562 DMARxDesc = DMARxDescTab+i;
lypinator 0:bb348c97df44 563
lypinator 0:bb348c97df44 564 /* Set Own bit of the Rx descriptor Status */
lypinator 0:bb348c97df44 565 DMARxDesc->Status = ETH_DMARXDESC_OWN;
lypinator 0:bb348c97df44 566
lypinator 0:bb348c97df44 567 /* Set Buffer1 size and Second Address Chained bit */
lypinator 0:bb348c97df44 568 DMARxDesc->ControlBufferSize = ETH_DMARXDESC_RCH | ETH_RX_BUF_SIZE;
lypinator 0:bb348c97df44 569
lypinator 0:bb348c97df44 570 /* Set Buffer1 address pointer */
lypinator 0:bb348c97df44 571 DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i*ETH_RX_BUF_SIZE]);
lypinator 0:bb348c97df44 572
lypinator 0:bb348c97df44 573 if((heth->Init).RxMode == ETH_RXINTERRUPT_MODE)
lypinator 0:bb348c97df44 574 {
lypinator 0:bb348c97df44 575 /* Enable Ethernet DMA Rx Descriptor interrupt */
lypinator 0:bb348c97df44 576 DMARxDesc->ControlBufferSize &= ~ETH_DMARXDESC_DIC;
lypinator 0:bb348c97df44 577 }
lypinator 0:bb348c97df44 578
lypinator 0:bb348c97df44 579 /* Initialize the next descriptor with the Next Descriptor Polling Enable */
lypinator 0:bb348c97df44 580 if(i < (RxBuffCount-1U))
lypinator 0:bb348c97df44 581 {
lypinator 0:bb348c97df44 582 /* Set next descriptor address register with next descriptor base address */
lypinator 0:bb348c97df44 583 DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab+i+1U);
lypinator 0:bb348c97df44 584 }
lypinator 0:bb348c97df44 585 else
lypinator 0:bb348c97df44 586 {
lypinator 0:bb348c97df44 587 /* For last descriptor, set next descriptor address register equal to the first descriptor base address */
lypinator 0:bb348c97df44 588 DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab);
lypinator 0:bb348c97df44 589 }
lypinator 0:bb348c97df44 590 }
lypinator 0:bb348c97df44 591
lypinator 0:bb348c97df44 592 /* Set Receive Descriptor List Address Register */
lypinator 0:bb348c97df44 593 (heth->Instance)->DMARDLAR = (uint32_t) DMARxDescTab;
lypinator 0:bb348c97df44 594
lypinator 0:bb348c97df44 595 /* Set ETH HAL State to Ready */
lypinator 0:bb348c97df44 596 heth->State= HAL_ETH_STATE_READY;
lypinator 0:bb348c97df44 597
lypinator 0:bb348c97df44 598 /* Process Unlocked */
lypinator 0:bb348c97df44 599 __HAL_UNLOCK(heth);
lypinator 0:bb348c97df44 600
lypinator 0:bb348c97df44 601 /* Return function status */
lypinator 0:bb348c97df44 602 return HAL_OK;
lypinator 0:bb348c97df44 603 }
lypinator 0:bb348c97df44 604
lypinator 0:bb348c97df44 605 /**
lypinator 0:bb348c97df44 606 * @brief Initializes the ETH MSP.
lypinator 0:bb348c97df44 607 * @param heth pointer to a ETH_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 608 * the configuration information for ETHERNET module
lypinator 0:bb348c97df44 609 * @retval None
lypinator 0:bb348c97df44 610 */
lypinator 0:bb348c97df44 611 __weak void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
lypinator 0:bb348c97df44 612 {
lypinator 0:bb348c97df44 613 /* Prevent unused argument(s) compilation warning */
lypinator 0:bb348c97df44 614 UNUSED(heth);
lypinator 0:bb348c97df44 615 /* NOTE : This function Should not be modified, when the callback is needed,
lypinator 0:bb348c97df44 616 the HAL_ETH_MspInit could be implemented in the user file
lypinator 0:bb348c97df44 617 */
lypinator 0:bb348c97df44 618 }
lypinator 0:bb348c97df44 619
lypinator 0:bb348c97df44 620 /**
lypinator 0:bb348c97df44 621 * @brief DeInitializes ETH MSP.
lypinator 0:bb348c97df44 622 * @param heth pointer to a ETH_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 623 * the configuration information for ETHERNET module
lypinator 0:bb348c97df44 624 * @retval None
lypinator 0:bb348c97df44 625 */
lypinator 0:bb348c97df44 626 __weak void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
lypinator 0:bb348c97df44 627 {
lypinator 0:bb348c97df44 628 /* Prevent unused argument(s) compilation warning */
lypinator 0:bb348c97df44 629 UNUSED(heth);
lypinator 0:bb348c97df44 630 /* NOTE : This function Should not be modified, when the callback is needed,
lypinator 0:bb348c97df44 631 the HAL_ETH_MspDeInit could be implemented in the user file
lypinator 0:bb348c97df44 632 */
lypinator 0:bb348c97df44 633 }
lypinator 0:bb348c97df44 634
lypinator 0:bb348c97df44 635 /**
lypinator 0:bb348c97df44 636 * @}
lypinator 0:bb348c97df44 637 */
lypinator 0:bb348c97df44 638
lypinator 0:bb348c97df44 639 /** @defgroup ETH_Exported_Functions_Group2 IO operation functions
lypinator 0:bb348c97df44 640 * @brief Data transfers functions
lypinator 0:bb348c97df44 641 *
lypinator 0:bb348c97df44 642 @verbatim
lypinator 0:bb348c97df44 643 ==============================================================================
lypinator 0:bb348c97df44 644 ##### IO operation functions #####
lypinator 0:bb348c97df44 645 ==============================================================================
lypinator 0:bb348c97df44 646 [..] This section provides functions allowing to:
lypinator 0:bb348c97df44 647 (+) Transmit a frame
lypinator 0:bb348c97df44 648 HAL_ETH_TransmitFrame();
lypinator 0:bb348c97df44 649 (+) Receive a frame
lypinator 0:bb348c97df44 650 HAL_ETH_GetReceivedFrame();
lypinator 0:bb348c97df44 651 HAL_ETH_GetReceivedFrame_IT();
lypinator 0:bb348c97df44 652 (+) Read from an External PHY register
lypinator 0:bb348c97df44 653 HAL_ETH_ReadPHYRegister();
lypinator 0:bb348c97df44 654 (+) Write to an External PHY register
lypinator 0:bb348c97df44 655 HAL_ETH_WritePHYRegister();
lypinator 0:bb348c97df44 656
lypinator 0:bb348c97df44 657 @endverbatim
lypinator 0:bb348c97df44 658
lypinator 0:bb348c97df44 659 * @{
lypinator 0:bb348c97df44 660 */
lypinator 0:bb348c97df44 661
lypinator 0:bb348c97df44 662 /**
lypinator 0:bb348c97df44 663 * @brief Sends an Ethernet frame.
lypinator 0:bb348c97df44 664 * @param heth pointer to a ETH_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 665 * the configuration information for ETHERNET module
lypinator 0:bb348c97df44 666 * @param FrameLength Amount of data to be sent
lypinator 0:bb348c97df44 667 * @retval HAL status
lypinator 0:bb348c97df44 668 */
lypinator 0:bb348c97df44 669 HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength)
lypinator 0:bb348c97df44 670 {
lypinator 0:bb348c97df44 671 uint32_t bufcount = 0U, size = 0U, i = 0U;
lypinator 0:bb348c97df44 672
lypinator 0:bb348c97df44 673 /* Set the ETH peripheral state to BUSY */
lypinator 0:bb348c97df44 674 heth->State = HAL_ETH_STATE_BUSY;
lypinator 0:bb348c97df44 675
lypinator 0:bb348c97df44 676 if (FrameLength == 0U)
lypinator 0:bb348c97df44 677 {
lypinator 0:bb348c97df44 678 /* Set ETH HAL state to READY */
lypinator 0:bb348c97df44 679 heth->State = HAL_ETH_STATE_READY;
lypinator 0:bb348c97df44 680
lypinator 0:bb348c97df44 681 return HAL_ERROR;
lypinator 0:bb348c97df44 682 }
lypinator 0:bb348c97df44 683
lypinator 0:bb348c97df44 684 /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */
lypinator 0:bb348c97df44 685 if(((heth->TxDesc)->Status & ETH_DMATXDESC_OWN) != (uint32_t)RESET)
lypinator 0:bb348c97df44 686 {
lypinator 0:bb348c97df44 687 /* OWN bit set */
lypinator 0:bb348c97df44 688 heth->State = HAL_ETH_STATE_BUSY_TX;
lypinator 0:bb348c97df44 689
lypinator 0:bb348c97df44 690 return HAL_ERROR;
lypinator 0:bb348c97df44 691 }
lypinator 0:bb348c97df44 692
lypinator 0:bb348c97df44 693 /* Get the number of needed Tx buffers for the current frame */
lypinator 0:bb348c97df44 694 if (FrameLength > ETH_TX_BUF_SIZE)
lypinator 0:bb348c97df44 695 {
lypinator 0:bb348c97df44 696 bufcount = FrameLength/ETH_TX_BUF_SIZE;
lypinator 0:bb348c97df44 697 if (FrameLength % ETH_TX_BUF_SIZE)
lypinator 0:bb348c97df44 698 {
lypinator 0:bb348c97df44 699 bufcount++;
lypinator 0:bb348c97df44 700 }
lypinator 0:bb348c97df44 701 }
lypinator 0:bb348c97df44 702 else
lypinator 0:bb348c97df44 703 {
lypinator 0:bb348c97df44 704 bufcount = 1U;
lypinator 0:bb348c97df44 705 }
lypinator 0:bb348c97df44 706 if (bufcount == 1U)
lypinator 0:bb348c97df44 707 {
lypinator 0:bb348c97df44 708 /* Set LAST and FIRST segment */
lypinator 0:bb348c97df44 709 heth->TxDesc->Status |=ETH_DMATXDESC_FS|ETH_DMATXDESC_LS;
lypinator 0:bb348c97df44 710 /* Set frame size */
lypinator 0:bb348c97df44 711 heth->TxDesc->ControlBufferSize = (FrameLength & ETH_DMATXDESC_TBS1);
lypinator 0:bb348c97df44 712 /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
lypinator 0:bb348c97df44 713 heth->TxDesc->Status |= ETH_DMATXDESC_OWN;
lypinator 0:bb348c97df44 714 /* Point to next descriptor */
lypinator 0:bb348c97df44 715 heth->TxDesc= (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr);
lypinator 0:bb348c97df44 716 }
lypinator 0:bb348c97df44 717 else
lypinator 0:bb348c97df44 718 {
lypinator 0:bb348c97df44 719 for (i=0U; i< bufcount; i++)
lypinator 0:bb348c97df44 720 {
lypinator 0:bb348c97df44 721 /* Clear FIRST and LAST segment bits */
lypinator 0:bb348c97df44 722 heth->TxDesc->Status &= ~(ETH_DMATXDESC_FS | ETH_DMATXDESC_LS);
lypinator 0:bb348c97df44 723
lypinator 0:bb348c97df44 724 if (i == 0U)
lypinator 0:bb348c97df44 725 {
lypinator 0:bb348c97df44 726 /* Setting the first segment bit */
lypinator 0:bb348c97df44 727 heth->TxDesc->Status |= ETH_DMATXDESC_FS;
lypinator 0:bb348c97df44 728 }
lypinator 0:bb348c97df44 729
lypinator 0:bb348c97df44 730 /* Program size */
lypinator 0:bb348c97df44 731 heth->TxDesc->ControlBufferSize = (ETH_TX_BUF_SIZE & ETH_DMATXDESC_TBS1);
lypinator 0:bb348c97df44 732
lypinator 0:bb348c97df44 733 if (i == (bufcount-1U))
lypinator 0:bb348c97df44 734 {
lypinator 0:bb348c97df44 735 /* Setting the last segment bit */
lypinator 0:bb348c97df44 736 heth->TxDesc->Status |= ETH_DMATXDESC_LS;
lypinator 0:bb348c97df44 737 size = FrameLength - (bufcount-1U)*ETH_TX_BUF_SIZE;
lypinator 0:bb348c97df44 738 heth->TxDesc->ControlBufferSize = (size & ETH_DMATXDESC_TBS1);
lypinator 0:bb348c97df44 739 }
lypinator 0:bb348c97df44 740
lypinator 0:bb348c97df44 741 /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
lypinator 0:bb348c97df44 742 heth->TxDesc->Status |= ETH_DMATXDESC_OWN;
lypinator 0:bb348c97df44 743 /* point to next descriptor */
lypinator 0:bb348c97df44 744 heth->TxDesc = (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr);
lypinator 0:bb348c97df44 745 }
lypinator 0:bb348c97df44 746 }
lypinator 0:bb348c97df44 747
lypinator 0:bb348c97df44 748 /* When Tx Buffer unavailable flag is set: clear it and resume transmission */
lypinator 0:bb348c97df44 749 if (((heth->Instance)->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET)
lypinator 0:bb348c97df44 750 {
lypinator 0:bb348c97df44 751 /* Clear TBUS ETHERNET DMA flag */
lypinator 0:bb348c97df44 752 (heth->Instance)->DMASR = ETH_DMASR_TBUS;
lypinator 0:bb348c97df44 753 /* Resume DMA transmission*/
lypinator 0:bb348c97df44 754 (heth->Instance)->DMATPDR = 0U;
lypinator 0:bb348c97df44 755 }
lypinator 0:bb348c97df44 756
lypinator 0:bb348c97df44 757 /* Set ETH HAL State to Ready */
lypinator 0:bb348c97df44 758 heth->State = HAL_ETH_STATE_READY;
lypinator 0:bb348c97df44 759
lypinator 0:bb348c97df44 760 /* Return function status */
lypinator 0:bb348c97df44 761 return HAL_OK;
lypinator 0:bb348c97df44 762 }
lypinator 0:bb348c97df44 763
lypinator 0:bb348c97df44 764 /**
lypinator 0:bb348c97df44 765 * @brief Checks for received frames.
lypinator 0:bb348c97df44 766 * @param heth pointer to a ETH_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 767 * the configuration information for ETHERNET module
lypinator 0:bb348c97df44 768 * @retval HAL status
lypinator 0:bb348c97df44 769 */
lypinator 0:bb348c97df44 770 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth)
lypinator 0:bb348c97df44 771 {
lypinator 0:bb348c97df44 772 uint32_t framelength = 0U;
lypinator 0:bb348c97df44 773
lypinator 0:bb348c97df44 774 /* Check the ETH state to BUSY */
lypinator 0:bb348c97df44 775 heth->State = HAL_ETH_STATE_BUSY;
lypinator 0:bb348c97df44 776
lypinator 0:bb348c97df44 777 /* Check if segment is not owned by DMA */
lypinator 0:bb348c97df44 778 /* (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) != (uint32_t)RESET)) */
lypinator 0:bb348c97df44 779 if(((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET))
lypinator 0:bb348c97df44 780 {
lypinator 0:bb348c97df44 781 /* Check if last segment */
lypinator 0:bb348c97df44 782 if(((heth->RxDesc->Status & ETH_DMARXDESC_LS) != (uint32_t)RESET))
lypinator 0:bb348c97df44 783 {
lypinator 0:bb348c97df44 784 /* increment segment count */
lypinator 0:bb348c97df44 785 (heth->RxFrameInfos).SegCount++;
lypinator 0:bb348c97df44 786
lypinator 0:bb348c97df44 787 /* Check if last segment is first segment: one segment contains the frame */
lypinator 0:bb348c97df44 788 if ((heth->RxFrameInfos).SegCount == 1U)
lypinator 0:bb348c97df44 789 {
lypinator 0:bb348c97df44 790 (heth->RxFrameInfos).FSRxDesc =heth->RxDesc;
lypinator 0:bb348c97df44 791 }
lypinator 0:bb348c97df44 792
lypinator 0:bb348c97df44 793 heth->RxFrameInfos.LSRxDesc = heth->RxDesc;
lypinator 0:bb348c97df44 794
lypinator 0:bb348c97df44 795 /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
lypinator 0:bb348c97df44 796 framelength = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4U;
lypinator 0:bb348c97df44 797 heth->RxFrameInfos.length = framelength;
lypinator 0:bb348c97df44 798
lypinator 0:bb348c97df44 799 /* Get the address of the buffer start address */
lypinator 0:bb348c97df44 800 heth->RxFrameInfos.buffer = ((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr;
lypinator 0:bb348c97df44 801 /* point to next descriptor */
lypinator 0:bb348c97df44 802 heth->RxDesc = (ETH_DMADescTypeDef*) ((heth->RxDesc)->Buffer2NextDescAddr);
lypinator 0:bb348c97df44 803
lypinator 0:bb348c97df44 804 /* Set HAL State to Ready */
lypinator 0:bb348c97df44 805 heth->State = HAL_ETH_STATE_READY;
lypinator 0:bb348c97df44 806
lypinator 0:bb348c97df44 807 /* Return function status */
lypinator 0:bb348c97df44 808 return HAL_OK;
lypinator 0:bb348c97df44 809 }
lypinator 0:bb348c97df44 810 /* Check if first segment */
lypinator 0:bb348c97df44 811 else if((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET)
lypinator 0:bb348c97df44 812 {
lypinator 0:bb348c97df44 813 (heth->RxFrameInfos).FSRxDesc = heth->RxDesc;
lypinator 0:bb348c97df44 814 (heth->RxFrameInfos).LSRxDesc = NULL;
lypinator 0:bb348c97df44 815 (heth->RxFrameInfos).SegCount = 1U;
lypinator 0:bb348c97df44 816 /* Point to next descriptor */
lypinator 0:bb348c97df44 817 heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
lypinator 0:bb348c97df44 818 }
lypinator 0:bb348c97df44 819 /* Check if intermediate segment */
lypinator 0:bb348c97df44 820 else
lypinator 0:bb348c97df44 821 {
lypinator 0:bb348c97df44 822 (heth->RxFrameInfos).SegCount++;
lypinator 0:bb348c97df44 823 /* Point to next descriptor */
lypinator 0:bb348c97df44 824 heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
lypinator 0:bb348c97df44 825 }
lypinator 0:bb348c97df44 826 }
lypinator 0:bb348c97df44 827
lypinator 0:bb348c97df44 828 /* Set ETH HAL State to Ready */
lypinator 0:bb348c97df44 829 heth->State = HAL_ETH_STATE_READY;
lypinator 0:bb348c97df44 830
lypinator 0:bb348c97df44 831 /* Return function status */
lypinator 0:bb348c97df44 832 return HAL_ERROR;
lypinator 0:bb348c97df44 833 }
lypinator 0:bb348c97df44 834
lypinator 0:bb348c97df44 835 /**
lypinator 0:bb348c97df44 836 * @brief Gets the Received frame in interrupt mode.
lypinator 0:bb348c97df44 837 * @param heth pointer to a ETH_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 838 * the configuration information for ETHERNET module
lypinator 0:bb348c97df44 839 * @retval HAL status
lypinator 0:bb348c97df44 840 */
lypinator 0:bb348c97df44 841 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth)
lypinator 0:bb348c97df44 842 {
lypinator 0:bb348c97df44 843 uint32_t descriptorscancounter = 0U;
lypinator 0:bb348c97df44 844
lypinator 0:bb348c97df44 845 /* Set ETH HAL State to BUSY */
lypinator 0:bb348c97df44 846 heth->State = HAL_ETH_STATE_BUSY;
lypinator 0:bb348c97df44 847
lypinator 0:bb348c97df44 848 /* Scan descriptors owned by CPU */
lypinator 0:bb348c97df44 849 while (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && (descriptorscancounter < ETH_RXBUFNB))
lypinator 0:bb348c97df44 850 {
lypinator 0:bb348c97df44 851 /* Just for security */
lypinator 0:bb348c97df44 852 descriptorscancounter++;
lypinator 0:bb348c97df44 853
lypinator 0:bb348c97df44 854 /* Check if first segment in frame */
lypinator 0:bb348c97df44 855 /* ((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)) */
lypinator 0:bb348c97df44 856 if((heth->RxDesc->Status & (ETH_DMARXDESC_FS | ETH_DMARXDESC_LS)) == (uint32_t)ETH_DMARXDESC_FS)
lypinator 0:bb348c97df44 857 {
lypinator 0:bb348c97df44 858 heth->RxFrameInfos.FSRxDesc = heth->RxDesc;
lypinator 0:bb348c97df44 859 heth->RxFrameInfos.SegCount = 1U;
lypinator 0:bb348c97df44 860 /* Point to next descriptor */
lypinator 0:bb348c97df44 861 heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
lypinator 0:bb348c97df44 862 }
lypinator 0:bb348c97df44 863 /* Check if intermediate segment */
lypinator 0:bb348c97df44 864 /* ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)&& ((heth->RxDesc->Status & ETH_DMARXDESC_FS) == (uint32_t)RESET)) */
lypinator 0:bb348c97df44 865 else if ((heth->RxDesc->Status & (ETH_DMARXDESC_LS | ETH_DMARXDESC_FS)) == (uint32_t)RESET)
lypinator 0:bb348c97df44 866 {
lypinator 0:bb348c97df44 867 /* Increment segment count */
lypinator 0:bb348c97df44 868 (heth->RxFrameInfos.SegCount)++;
lypinator 0:bb348c97df44 869 /* Point to next descriptor */
lypinator 0:bb348c97df44 870 heth->RxDesc = (ETH_DMADescTypeDef*)(heth->RxDesc->Buffer2NextDescAddr);
lypinator 0:bb348c97df44 871 }
lypinator 0:bb348c97df44 872 /* Should be last segment */
lypinator 0:bb348c97df44 873 else
lypinator 0:bb348c97df44 874 {
lypinator 0:bb348c97df44 875 /* Last segment */
lypinator 0:bb348c97df44 876 heth->RxFrameInfos.LSRxDesc = heth->RxDesc;
lypinator 0:bb348c97df44 877
lypinator 0:bb348c97df44 878 /* Increment segment count */
lypinator 0:bb348c97df44 879 (heth->RxFrameInfos.SegCount)++;
lypinator 0:bb348c97df44 880
lypinator 0:bb348c97df44 881 /* Check if last segment is first segment: one segment contains the frame */
lypinator 0:bb348c97df44 882 if ((heth->RxFrameInfos.SegCount) == 1U)
lypinator 0:bb348c97df44 883 {
lypinator 0:bb348c97df44 884 heth->RxFrameInfos.FSRxDesc = heth->RxDesc;
lypinator 0:bb348c97df44 885 }
lypinator 0:bb348c97df44 886
lypinator 0:bb348c97df44 887 /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
lypinator 0:bb348c97df44 888 heth->RxFrameInfos.length = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4U;
lypinator 0:bb348c97df44 889
lypinator 0:bb348c97df44 890 /* Get the address of the buffer start address */
lypinator 0:bb348c97df44 891 heth->RxFrameInfos.buffer =((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr;
lypinator 0:bb348c97df44 892
lypinator 0:bb348c97df44 893 /* Point to next descriptor */
lypinator 0:bb348c97df44 894 heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
lypinator 0:bb348c97df44 895
lypinator 0:bb348c97df44 896 /* Set HAL State to Ready */
lypinator 0:bb348c97df44 897 heth->State = HAL_ETH_STATE_READY;
lypinator 0:bb348c97df44 898
lypinator 0:bb348c97df44 899 /* Return function status */
lypinator 0:bb348c97df44 900 return HAL_OK;
lypinator 0:bb348c97df44 901 }
lypinator 0:bb348c97df44 902 }
lypinator 0:bb348c97df44 903
lypinator 0:bb348c97df44 904 /* Set HAL State to Ready */
lypinator 0:bb348c97df44 905 heth->State = HAL_ETH_STATE_READY;
lypinator 0:bb348c97df44 906
lypinator 0:bb348c97df44 907 /* Return function status */
lypinator 0:bb348c97df44 908 return HAL_ERROR;
lypinator 0:bb348c97df44 909 }
lypinator 0:bb348c97df44 910
lypinator 0:bb348c97df44 911 /**
lypinator 0:bb348c97df44 912 * @brief This function handles ETH interrupt request.
lypinator 0:bb348c97df44 913 * @param heth pointer to a ETH_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 914 * the configuration information for ETHERNET module
lypinator 0:bb348c97df44 915 * @retval HAL status
lypinator 0:bb348c97df44 916 */
lypinator 0:bb348c97df44 917 void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)
lypinator 0:bb348c97df44 918 {
lypinator 0:bb348c97df44 919 /* Frame received */
lypinator 0:bb348c97df44 920 if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_R))
lypinator 0:bb348c97df44 921 {
lypinator 0:bb348c97df44 922 /* Receive complete callback */
lypinator 0:bb348c97df44 923 HAL_ETH_RxCpltCallback(heth);
lypinator 0:bb348c97df44 924
lypinator 0:bb348c97df44 925 /* Clear the Eth DMA Rx IT pending bits */
lypinator 0:bb348c97df44 926 __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_R);
lypinator 0:bb348c97df44 927
lypinator 0:bb348c97df44 928 /* Set HAL State to Ready */
lypinator 0:bb348c97df44 929 heth->State = HAL_ETH_STATE_READY;
lypinator 0:bb348c97df44 930
lypinator 0:bb348c97df44 931 /* Process Unlocked */
lypinator 0:bb348c97df44 932 __HAL_UNLOCK(heth);
lypinator 0:bb348c97df44 933
lypinator 0:bb348c97df44 934 }
lypinator 0:bb348c97df44 935 /* Frame transmitted */
lypinator 0:bb348c97df44 936 else if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_T))
lypinator 0:bb348c97df44 937 {
lypinator 0:bb348c97df44 938 /* Transfer complete callback */
lypinator 0:bb348c97df44 939 HAL_ETH_TxCpltCallback(heth);
lypinator 0:bb348c97df44 940
lypinator 0:bb348c97df44 941 /* Clear the Eth DMA Tx IT pending bits */
lypinator 0:bb348c97df44 942 __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_T);
lypinator 0:bb348c97df44 943
lypinator 0:bb348c97df44 944 /* Set HAL State to Ready */
lypinator 0:bb348c97df44 945 heth->State = HAL_ETH_STATE_READY;
lypinator 0:bb348c97df44 946
lypinator 0:bb348c97df44 947 /* Process Unlocked */
lypinator 0:bb348c97df44 948 __HAL_UNLOCK(heth);
lypinator 0:bb348c97df44 949 }
lypinator 0:bb348c97df44 950
lypinator 0:bb348c97df44 951 /* Clear the interrupt flags */
lypinator 0:bb348c97df44 952 __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_NIS);
lypinator 0:bb348c97df44 953
lypinator 0:bb348c97df44 954 /* ETH DMA Error */
lypinator 0:bb348c97df44 955 if(__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_AIS))
lypinator 0:bb348c97df44 956 {
lypinator 0:bb348c97df44 957 /* Ethernet Error callback */
lypinator 0:bb348c97df44 958 HAL_ETH_ErrorCallback(heth);
lypinator 0:bb348c97df44 959
lypinator 0:bb348c97df44 960 /* Clear the interrupt flags */
lypinator 0:bb348c97df44 961 __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_FLAG_AIS);
lypinator 0:bb348c97df44 962
lypinator 0:bb348c97df44 963 /* Set HAL State to Ready */
lypinator 0:bb348c97df44 964 heth->State = HAL_ETH_STATE_READY;
lypinator 0:bb348c97df44 965
lypinator 0:bb348c97df44 966 /* Process Unlocked */
lypinator 0:bb348c97df44 967 __HAL_UNLOCK(heth);
lypinator 0:bb348c97df44 968 }
lypinator 0:bb348c97df44 969 }
lypinator 0:bb348c97df44 970
lypinator 0:bb348c97df44 971 /**
lypinator 0:bb348c97df44 972 * @brief Tx Transfer completed callbacks.
lypinator 0:bb348c97df44 973 * @param heth pointer to a ETH_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 974 * the configuration information for ETHERNET module
lypinator 0:bb348c97df44 975 * @retval None
lypinator 0:bb348c97df44 976 */
lypinator 0:bb348c97df44 977 __weak void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth)
lypinator 0:bb348c97df44 978 {
lypinator 0:bb348c97df44 979 /* Prevent unused argument(s) compilation warning */
lypinator 0:bb348c97df44 980 UNUSED(heth);
lypinator 0:bb348c97df44 981 /* NOTE : This function Should not be modified, when the callback is needed,
lypinator 0:bb348c97df44 982 the HAL_ETH_TxCpltCallback could be implemented in the user file
lypinator 0:bb348c97df44 983 */
lypinator 0:bb348c97df44 984 }
lypinator 0:bb348c97df44 985
lypinator 0:bb348c97df44 986 /**
lypinator 0:bb348c97df44 987 * @brief Rx Transfer completed callbacks.
lypinator 0:bb348c97df44 988 * @param heth pointer to a ETH_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 989 * the configuration information for ETHERNET module
lypinator 0:bb348c97df44 990 * @retval None
lypinator 0:bb348c97df44 991 */
lypinator 0:bb348c97df44 992 __weak void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth)
lypinator 0:bb348c97df44 993 {
lypinator 0:bb348c97df44 994 /* Prevent unused argument(s) compilation warning */
lypinator 0:bb348c97df44 995 UNUSED(heth);
lypinator 0:bb348c97df44 996 /* NOTE : This function Should not be modified, when the callback is needed,
lypinator 0:bb348c97df44 997 the HAL_ETH_TxCpltCallback could be implemented in the user file
lypinator 0:bb348c97df44 998 */
lypinator 0:bb348c97df44 999 }
lypinator 0:bb348c97df44 1000
lypinator 0:bb348c97df44 1001 /**
lypinator 0:bb348c97df44 1002 * @brief Ethernet transfer error callbacks
lypinator 0:bb348c97df44 1003 * @param heth pointer to a ETH_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 1004 * the configuration information for ETHERNET module
lypinator 0:bb348c97df44 1005 * @retval None
lypinator 0:bb348c97df44 1006 */
lypinator 0:bb348c97df44 1007 __weak void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth)
lypinator 0:bb348c97df44 1008 {
lypinator 0:bb348c97df44 1009 /* Prevent unused argument(s) compilation warning */
lypinator 0:bb348c97df44 1010 UNUSED(heth);
lypinator 0:bb348c97df44 1011 /* NOTE : This function Should not be modified, when the callback is needed,
lypinator 0:bb348c97df44 1012 the HAL_ETH_TxCpltCallback could be implemented in the user file
lypinator 0:bb348c97df44 1013 */
lypinator 0:bb348c97df44 1014 }
lypinator 0:bb348c97df44 1015
lypinator 0:bb348c97df44 1016 /**
lypinator 0:bb348c97df44 1017 * @brief Reads a PHY register
lypinator 0:bb348c97df44 1018 * @param heth pointer to a ETH_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 1019 * the configuration information for ETHERNET module
lypinator 0:bb348c97df44 1020 * @param PHYReg PHY register address, is the index of one of the 32 PHY register.
lypinator 0:bb348c97df44 1021 * This parameter can be one of the following values:
lypinator 0:bb348c97df44 1022 * PHY_BCR: Transceiver Basic Control Register,
lypinator 0:bb348c97df44 1023 * PHY_BSR: Transceiver Basic Status Register.
lypinator 0:bb348c97df44 1024 * More PHY register could be read depending on the used PHY
lypinator 0:bb348c97df44 1025 * @param RegValue PHY register value
lypinator 0:bb348c97df44 1026 * @retval HAL status
lypinator 0:bb348c97df44 1027 */
lypinator 0:bb348c97df44 1028 HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue)
lypinator 0:bb348c97df44 1029 {
lypinator 0:bb348c97df44 1030 uint32_t tmpreg1 = 0U;
lypinator 0:bb348c97df44 1031 uint32_t tickstart = 0U;
lypinator 0:bb348c97df44 1032
lypinator 0:bb348c97df44 1033 /* Check parameters */
lypinator 0:bb348c97df44 1034 assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress));
lypinator 0:bb348c97df44 1035
lypinator 0:bb348c97df44 1036 /* Check the ETH peripheral state */
lypinator 0:bb348c97df44 1037 if(heth->State == HAL_ETH_STATE_BUSY_RD)
lypinator 0:bb348c97df44 1038 {
lypinator 0:bb348c97df44 1039 return HAL_BUSY;
lypinator 0:bb348c97df44 1040 }
lypinator 0:bb348c97df44 1041 /* Set ETH HAL State to BUSY_RD */
lypinator 0:bb348c97df44 1042 heth->State = HAL_ETH_STATE_BUSY_RD;
lypinator 0:bb348c97df44 1043
lypinator 0:bb348c97df44 1044 /* Get the ETHERNET MACMIIAR value */
lypinator 0:bb348c97df44 1045 tmpreg1 = heth->Instance->MACMIIAR;
lypinator 0:bb348c97df44 1046
lypinator 0:bb348c97df44 1047 /* Keep only the CSR Clock Range CR[2:0] bits value */
lypinator 0:bb348c97df44 1048 tmpreg1 &= ~ETH_MACMIIAR_CR_MASK;
lypinator 0:bb348c97df44 1049
lypinator 0:bb348c97df44 1050 /* Prepare the MII address register value */
lypinator 0:bb348c97df44 1051 tmpreg1 |=(((uint32_t)heth->Init.PhyAddress << 11U) & ETH_MACMIIAR_PA); /* Set the PHY device address */
lypinator 0:bb348c97df44 1052 tmpreg1 |=(((uint32_t)PHYReg<<6U) & ETH_MACMIIAR_MR); /* Set the PHY register address */
lypinator 0:bb348c97df44 1053 tmpreg1 &= ~ETH_MACMIIAR_MW; /* Set the read mode */
lypinator 0:bb348c97df44 1054 tmpreg1 |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
lypinator 0:bb348c97df44 1055
lypinator 0:bb348c97df44 1056 /* Write the result value into the MII Address register */
lypinator 0:bb348c97df44 1057 heth->Instance->MACMIIAR = tmpreg1;
lypinator 0:bb348c97df44 1058
lypinator 0:bb348c97df44 1059 /* Get tick */
lypinator 0:bb348c97df44 1060 tickstart = HAL_GetTick();
lypinator 0:bb348c97df44 1061
lypinator 0:bb348c97df44 1062 /* Check for the Busy flag */
lypinator 0:bb348c97df44 1063 while((tmpreg1 & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB)
lypinator 0:bb348c97df44 1064 {
lypinator 0:bb348c97df44 1065 /* Check for the Timeout */
lypinator 0:bb348c97df44 1066 if((HAL_GetTick() - tickstart ) > PHY_READ_TO)
lypinator 0:bb348c97df44 1067 {
lypinator 0:bb348c97df44 1068 heth->State= HAL_ETH_STATE_READY;
lypinator 0:bb348c97df44 1069
lypinator 0:bb348c97df44 1070 /* Process Unlocked */
lypinator 0:bb348c97df44 1071 __HAL_UNLOCK(heth);
lypinator 0:bb348c97df44 1072
lypinator 0:bb348c97df44 1073 return HAL_TIMEOUT;
lypinator 0:bb348c97df44 1074 }
lypinator 0:bb348c97df44 1075
lypinator 0:bb348c97df44 1076 tmpreg1 = heth->Instance->MACMIIAR;
lypinator 0:bb348c97df44 1077 }
lypinator 0:bb348c97df44 1078
lypinator 0:bb348c97df44 1079 /* Get MACMIIDR value */
lypinator 0:bb348c97df44 1080 *RegValue = (uint16_t)(heth->Instance->MACMIIDR);
lypinator 0:bb348c97df44 1081
lypinator 0:bb348c97df44 1082 /* Set ETH HAL State to READY */
lypinator 0:bb348c97df44 1083 heth->State = HAL_ETH_STATE_READY;
lypinator 0:bb348c97df44 1084
lypinator 0:bb348c97df44 1085 /* Return function status */
lypinator 0:bb348c97df44 1086 return HAL_OK;
lypinator 0:bb348c97df44 1087 }
lypinator 0:bb348c97df44 1088
lypinator 0:bb348c97df44 1089 /**
lypinator 0:bb348c97df44 1090 * @brief Writes to a PHY register.
lypinator 0:bb348c97df44 1091 * @param heth pointer to a ETH_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 1092 * the configuration information for ETHERNET module
lypinator 0:bb348c97df44 1093 * @param PHYReg PHY register address, is the index of one of the 32 PHY register.
lypinator 0:bb348c97df44 1094 * This parameter can be one of the following values:
lypinator 0:bb348c97df44 1095 * PHY_BCR: Transceiver Control Register.
lypinator 0:bb348c97df44 1096 * More PHY register could be written depending on the used PHY
lypinator 0:bb348c97df44 1097 * @param RegValue the value to write
lypinator 0:bb348c97df44 1098 * @retval HAL status
lypinator 0:bb348c97df44 1099 */
lypinator 0:bb348c97df44 1100 HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue)
lypinator 0:bb348c97df44 1101 {
lypinator 0:bb348c97df44 1102 uint32_t tmpreg1 = 0U;
lypinator 0:bb348c97df44 1103 uint32_t tickstart = 0U;
lypinator 0:bb348c97df44 1104
lypinator 0:bb348c97df44 1105 /* Check parameters */
lypinator 0:bb348c97df44 1106 assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress));
lypinator 0:bb348c97df44 1107
lypinator 0:bb348c97df44 1108 /* Check the ETH peripheral state */
lypinator 0:bb348c97df44 1109 if(heth->State == HAL_ETH_STATE_BUSY_WR)
lypinator 0:bb348c97df44 1110 {
lypinator 0:bb348c97df44 1111 return HAL_BUSY;
lypinator 0:bb348c97df44 1112 }
lypinator 0:bb348c97df44 1113 /* Set ETH HAL State to BUSY_WR */
lypinator 0:bb348c97df44 1114 heth->State = HAL_ETH_STATE_BUSY_WR;
lypinator 0:bb348c97df44 1115
lypinator 0:bb348c97df44 1116 /* Get the ETHERNET MACMIIAR value */
lypinator 0:bb348c97df44 1117 tmpreg1 = heth->Instance->MACMIIAR;
lypinator 0:bb348c97df44 1118
lypinator 0:bb348c97df44 1119 /* Keep only the CSR Clock Range CR[2:0] bits value */
lypinator 0:bb348c97df44 1120 tmpreg1 &= ~ETH_MACMIIAR_CR_MASK;
lypinator 0:bb348c97df44 1121
lypinator 0:bb348c97df44 1122 /* Prepare the MII register address value */
lypinator 0:bb348c97df44 1123 tmpreg1 |=(((uint32_t)heth->Init.PhyAddress<<11U) & ETH_MACMIIAR_PA); /* Set the PHY device address */
lypinator 0:bb348c97df44 1124 tmpreg1 |=(((uint32_t)PHYReg<<6U) & ETH_MACMIIAR_MR); /* Set the PHY register address */
lypinator 0:bb348c97df44 1125 tmpreg1 |= ETH_MACMIIAR_MW; /* Set the write mode */
lypinator 0:bb348c97df44 1126 tmpreg1 |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
lypinator 0:bb348c97df44 1127
lypinator 0:bb348c97df44 1128 /* Give the value to the MII data register */
lypinator 0:bb348c97df44 1129 heth->Instance->MACMIIDR = (uint16_t)RegValue;
lypinator 0:bb348c97df44 1130
lypinator 0:bb348c97df44 1131 /* Write the result value into the MII Address register */
lypinator 0:bb348c97df44 1132 heth->Instance->MACMIIAR = tmpreg1;
lypinator 0:bb348c97df44 1133
lypinator 0:bb348c97df44 1134 /* Get tick */
lypinator 0:bb348c97df44 1135 tickstart = HAL_GetTick();
lypinator 0:bb348c97df44 1136
lypinator 0:bb348c97df44 1137 /* Check for the Busy flag */
lypinator 0:bb348c97df44 1138 while((tmpreg1 & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB)
lypinator 0:bb348c97df44 1139 {
lypinator 0:bb348c97df44 1140 /* Check for the Timeout */
lypinator 0:bb348c97df44 1141 if((HAL_GetTick() - tickstart ) > PHY_WRITE_TO)
lypinator 0:bb348c97df44 1142 {
lypinator 0:bb348c97df44 1143 heth->State= HAL_ETH_STATE_READY;
lypinator 0:bb348c97df44 1144
lypinator 0:bb348c97df44 1145 /* Process Unlocked */
lypinator 0:bb348c97df44 1146 __HAL_UNLOCK(heth);
lypinator 0:bb348c97df44 1147
lypinator 0:bb348c97df44 1148 return HAL_TIMEOUT;
lypinator 0:bb348c97df44 1149 }
lypinator 0:bb348c97df44 1150
lypinator 0:bb348c97df44 1151 tmpreg1 = heth->Instance->MACMIIAR;
lypinator 0:bb348c97df44 1152 }
lypinator 0:bb348c97df44 1153
lypinator 0:bb348c97df44 1154 /* Set ETH HAL State to READY */
lypinator 0:bb348c97df44 1155 heth->State = HAL_ETH_STATE_READY;
lypinator 0:bb348c97df44 1156
lypinator 0:bb348c97df44 1157 /* Return function status */
lypinator 0:bb348c97df44 1158 return HAL_OK;
lypinator 0:bb348c97df44 1159 }
lypinator 0:bb348c97df44 1160
lypinator 0:bb348c97df44 1161 /**
lypinator 0:bb348c97df44 1162 * @}
lypinator 0:bb348c97df44 1163 */
lypinator 0:bb348c97df44 1164
lypinator 0:bb348c97df44 1165 /** @defgroup ETH_Exported_Functions_Group3 Peripheral Control functions
lypinator 0:bb348c97df44 1166 * @brief Peripheral Control functions
lypinator 0:bb348c97df44 1167 *
lypinator 0:bb348c97df44 1168 @verbatim
lypinator 0:bb348c97df44 1169 ===============================================================================
lypinator 0:bb348c97df44 1170 ##### Peripheral Control functions #####
lypinator 0:bb348c97df44 1171 ===============================================================================
lypinator 0:bb348c97df44 1172 [..] This section provides functions allowing to:
lypinator 0:bb348c97df44 1173 (+) Enable MAC and DMA transmission and reception.
lypinator 0:bb348c97df44 1174 HAL_ETH_Start();
lypinator 0:bb348c97df44 1175 (+) Disable MAC and DMA transmission and reception.
lypinator 0:bb348c97df44 1176 HAL_ETH_Stop();
lypinator 0:bb348c97df44 1177 (+) Set the MAC configuration in runtime mode
lypinator 0:bb348c97df44 1178 HAL_ETH_ConfigMAC();
lypinator 0:bb348c97df44 1179 (+) Set the DMA configuration in runtime mode
lypinator 0:bb348c97df44 1180 HAL_ETH_ConfigDMA();
lypinator 0:bb348c97df44 1181
lypinator 0:bb348c97df44 1182 @endverbatim
lypinator 0:bb348c97df44 1183 * @{
lypinator 0:bb348c97df44 1184 */
lypinator 0:bb348c97df44 1185
lypinator 0:bb348c97df44 1186 /**
lypinator 0:bb348c97df44 1187 * @brief Enables Ethernet MAC and DMA reception/transmission
lypinator 0:bb348c97df44 1188 * @param heth pointer to a ETH_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 1189 * the configuration information for ETHERNET module
lypinator 0:bb348c97df44 1190 * @retval HAL status
lypinator 0:bb348c97df44 1191 */
lypinator 0:bb348c97df44 1192 HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth)
lypinator 0:bb348c97df44 1193 {
lypinator 0:bb348c97df44 1194 /* Process Locked */
lypinator 0:bb348c97df44 1195 __HAL_LOCK(heth);
lypinator 0:bb348c97df44 1196
lypinator 0:bb348c97df44 1197 /* Set the ETH peripheral state to BUSY */
lypinator 0:bb348c97df44 1198 heth->State = HAL_ETH_STATE_BUSY;
lypinator 0:bb348c97df44 1199
lypinator 0:bb348c97df44 1200 /* Enable transmit state machine of the MAC for transmission on the MII */
lypinator 0:bb348c97df44 1201 ETH_MACTransmissionEnable(heth);
lypinator 0:bb348c97df44 1202
lypinator 0:bb348c97df44 1203 /* Enable receive state machine of the MAC for reception from the MII */
lypinator 0:bb348c97df44 1204 ETH_MACReceptionEnable(heth);
lypinator 0:bb348c97df44 1205
lypinator 0:bb348c97df44 1206 /* Flush Transmit FIFO */
lypinator 0:bb348c97df44 1207 ETH_FlushTransmitFIFO(heth);
lypinator 0:bb348c97df44 1208
lypinator 0:bb348c97df44 1209 /* Start DMA transmission */
lypinator 0:bb348c97df44 1210 ETH_DMATransmissionEnable(heth);
lypinator 0:bb348c97df44 1211
lypinator 0:bb348c97df44 1212 /* Start DMA reception */
lypinator 0:bb348c97df44 1213 ETH_DMAReceptionEnable(heth);
lypinator 0:bb348c97df44 1214
lypinator 0:bb348c97df44 1215 /* Set the ETH state to READY*/
lypinator 0:bb348c97df44 1216 heth->State= HAL_ETH_STATE_READY;
lypinator 0:bb348c97df44 1217
lypinator 0:bb348c97df44 1218 /* Process Unlocked */
lypinator 0:bb348c97df44 1219 __HAL_UNLOCK(heth);
lypinator 0:bb348c97df44 1220
lypinator 0:bb348c97df44 1221 /* Return function status */
lypinator 0:bb348c97df44 1222 return HAL_OK;
lypinator 0:bb348c97df44 1223 }
lypinator 0:bb348c97df44 1224
lypinator 0:bb348c97df44 1225 /**
lypinator 0:bb348c97df44 1226 * @brief Stop Ethernet MAC and DMA reception/transmission
lypinator 0:bb348c97df44 1227 * @param heth pointer to a ETH_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 1228 * the configuration information for ETHERNET module
lypinator 0:bb348c97df44 1229 * @retval HAL status
lypinator 0:bb348c97df44 1230 */
lypinator 0:bb348c97df44 1231 HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth)
lypinator 0:bb348c97df44 1232 {
lypinator 0:bb348c97df44 1233 /* Process Locked */
lypinator 0:bb348c97df44 1234 __HAL_LOCK(heth);
lypinator 0:bb348c97df44 1235
lypinator 0:bb348c97df44 1236 /* Set the ETH peripheral state to BUSY */
lypinator 0:bb348c97df44 1237 heth->State = HAL_ETH_STATE_BUSY;
lypinator 0:bb348c97df44 1238
lypinator 0:bb348c97df44 1239 /* Stop DMA transmission */
lypinator 0:bb348c97df44 1240 ETH_DMATransmissionDisable(heth);
lypinator 0:bb348c97df44 1241
lypinator 0:bb348c97df44 1242 /* Stop DMA reception */
lypinator 0:bb348c97df44 1243 ETH_DMAReceptionDisable(heth);
lypinator 0:bb348c97df44 1244
lypinator 0:bb348c97df44 1245 /* Disable receive state machine of the MAC for reception from the MII */
lypinator 0:bb348c97df44 1246 ETH_MACReceptionDisable(heth);
lypinator 0:bb348c97df44 1247
lypinator 0:bb348c97df44 1248 /* Flush Transmit FIFO */
lypinator 0:bb348c97df44 1249 ETH_FlushTransmitFIFO(heth);
lypinator 0:bb348c97df44 1250
lypinator 0:bb348c97df44 1251 /* Disable transmit state machine of the MAC for transmission on the MII */
lypinator 0:bb348c97df44 1252 ETH_MACTransmissionDisable(heth);
lypinator 0:bb348c97df44 1253
lypinator 0:bb348c97df44 1254 /* Set the ETH state*/
lypinator 0:bb348c97df44 1255 heth->State = HAL_ETH_STATE_READY;
lypinator 0:bb348c97df44 1256
lypinator 0:bb348c97df44 1257 /* Process Unlocked */
lypinator 0:bb348c97df44 1258 __HAL_UNLOCK(heth);
lypinator 0:bb348c97df44 1259
lypinator 0:bb348c97df44 1260 /* Return function status */
lypinator 0:bb348c97df44 1261 return HAL_OK;
lypinator 0:bb348c97df44 1262 }
lypinator 0:bb348c97df44 1263
lypinator 0:bb348c97df44 1264 /**
lypinator 0:bb348c97df44 1265 * @brief Set ETH MAC Configuration.
lypinator 0:bb348c97df44 1266 * @param heth pointer to a ETH_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 1267 * the configuration information for ETHERNET module
lypinator 0:bb348c97df44 1268 * @param macconf MAC Configuration structure
lypinator 0:bb348c97df44 1269 * @retval HAL status
lypinator 0:bb348c97df44 1270 */
lypinator 0:bb348c97df44 1271 HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf)
lypinator 0:bb348c97df44 1272 {
lypinator 0:bb348c97df44 1273 uint32_t tmpreg1 = 0U;
lypinator 0:bb348c97df44 1274
lypinator 0:bb348c97df44 1275 /* Process Locked */
lypinator 0:bb348c97df44 1276 __HAL_LOCK(heth);
lypinator 0:bb348c97df44 1277
lypinator 0:bb348c97df44 1278 /* Set the ETH peripheral state to BUSY */
lypinator 0:bb348c97df44 1279 heth->State= HAL_ETH_STATE_BUSY;
lypinator 0:bb348c97df44 1280
lypinator 0:bb348c97df44 1281 assert_param(IS_ETH_SPEED(heth->Init.Speed));
lypinator 0:bb348c97df44 1282 assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode));
lypinator 0:bb348c97df44 1283
lypinator 0:bb348c97df44 1284 if (macconf != NULL)
lypinator 0:bb348c97df44 1285 {
lypinator 0:bb348c97df44 1286 /* Check the parameters */
lypinator 0:bb348c97df44 1287 assert_param(IS_ETH_WATCHDOG(macconf->Watchdog));
lypinator 0:bb348c97df44 1288 assert_param(IS_ETH_JABBER(macconf->Jabber));
lypinator 0:bb348c97df44 1289 assert_param(IS_ETH_INTER_FRAME_GAP(macconf->InterFrameGap));
lypinator 0:bb348c97df44 1290 assert_param(IS_ETH_CARRIER_SENSE(macconf->CarrierSense));
lypinator 0:bb348c97df44 1291 assert_param(IS_ETH_RECEIVE_OWN(macconf->ReceiveOwn));
lypinator 0:bb348c97df44 1292 assert_param(IS_ETH_LOOPBACK_MODE(macconf->LoopbackMode));
lypinator 0:bb348c97df44 1293 assert_param(IS_ETH_CHECKSUM_OFFLOAD(macconf->ChecksumOffload));
lypinator 0:bb348c97df44 1294 assert_param(IS_ETH_RETRY_TRANSMISSION(macconf->RetryTransmission));
lypinator 0:bb348c97df44 1295 assert_param(IS_ETH_AUTOMATIC_PADCRC_STRIP(macconf->AutomaticPadCRCStrip));
lypinator 0:bb348c97df44 1296 assert_param(IS_ETH_BACKOFF_LIMIT(macconf->BackOffLimit));
lypinator 0:bb348c97df44 1297 assert_param(IS_ETH_DEFERRAL_CHECK(macconf->DeferralCheck));
lypinator 0:bb348c97df44 1298 assert_param(IS_ETH_RECEIVE_ALL(macconf->ReceiveAll));
lypinator 0:bb348c97df44 1299 assert_param(IS_ETH_SOURCE_ADDR_FILTER(macconf->SourceAddrFilter));
lypinator 0:bb348c97df44 1300 assert_param(IS_ETH_CONTROL_FRAMES(macconf->PassControlFrames));
lypinator 0:bb348c97df44 1301 assert_param(IS_ETH_BROADCAST_FRAMES_RECEPTION(macconf->BroadcastFramesReception));
lypinator 0:bb348c97df44 1302 assert_param(IS_ETH_DESTINATION_ADDR_FILTER(macconf->DestinationAddrFilter));
lypinator 0:bb348c97df44 1303 assert_param(IS_ETH_PROMISCUOUS_MODE(macconf->PromiscuousMode));
lypinator 0:bb348c97df44 1304 assert_param(IS_ETH_MULTICAST_FRAMES_FILTER(macconf->MulticastFramesFilter));
lypinator 0:bb348c97df44 1305 assert_param(IS_ETH_UNICAST_FRAMES_FILTER(macconf->UnicastFramesFilter));
lypinator 0:bb348c97df44 1306 assert_param(IS_ETH_PAUSE_TIME(macconf->PauseTime));
lypinator 0:bb348c97df44 1307 assert_param(IS_ETH_ZEROQUANTA_PAUSE(macconf->ZeroQuantaPause));
lypinator 0:bb348c97df44 1308 assert_param(IS_ETH_PAUSE_LOW_THRESHOLD(macconf->PauseLowThreshold));
lypinator 0:bb348c97df44 1309 assert_param(IS_ETH_UNICAST_PAUSE_FRAME_DETECT(macconf->UnicastPauseFrameDetect));
lypinator 0:bb348c97df44 1310 assert_param(IS_ETH_RECEIVE_FLOWCONTROL(macconf->ReceiveFlowControl));
lypinator 0:bb348c97df44 1311 assert_param(IS_ETH_TRANSMIT_FLOWCONTROL(macconf->TransmitFlowControl));
lypinator 0:bb348c97df44 1312 assert_param(IS_ETH_VLAN_TAG_COMPARISON(macconf->VLANTagComparison));
lypinator 0:bb348c97df44 1313 assert_param(IS_ETH_VLAN_TAG_IDENTIFIER(macconf->VLANTagIdentifier));
lypinator 0:bb348c97df44 1314
lypinator 0:bb348c97df44 1315 /*------------------------ ETHERNET MACCR Configuration --------------------*/
lypinator 0:bb348c97df44 1316 /* Get the ETHERNET MACCR value */
lypinator 0:bb348c97df44 1317 tmpreg1 = (heth->Instance)->MACCR;
lypinator 0:bb348c97df44 1318 /* Clear WD, PCE, PS, TE and RE bits */
lypinator 0:bb348c97df44 1319 tmpreg1 &= ETH_MACCR_CLEAR_MASK;
lypinator 0:bb348c97df44 1320
lypinator 0:bb348c97df44 1321 tmpreg1 |= (uint32_t)(macconf->Watchdog |
lypinator 0:bb348c97df44 1322 macconf->Jabber |
lypinator 0:bb348c97df44 1323 macconf->InterFrameGap |
lypinator 0:bb348c97df44 1324 macconf->CarrierSense |
lypinator 0:bb348c97df44 1325 (heth->Init).Speed |
lypinator 0:bb348c97df44 1326 macconf->ReceiveOwn |
lypinator 0:bb348c97df44 1327 macconf->LoopbackMode |
lypinator 0:bb348c97df44 1328 (heth->Init).DuplexMode |
lypinator 0:bb348c97df44 1329 macconf->ChecksumOffload |
lypinator 0:bb348c97df44 1330 macconf->RetryTransmission |
lypinator 0:bb348c97df44 1331 macconf->AutomaticPadCRCStrip |
lypinator 0:bb348c97df44 1332 macconf->BackOffLimit |
lypinator 0:bb348c97df44 1333 macconf->DeferralCheck);
lypinator 0:bb348c97df44 1334
lypinator 0:bb348c97df44 1335 /* Write to ETHERNET MACCR */
lypinator 0:bb348c97df44 1336 (heth->Instance)->MACCR = (uint32_t)tmpreg1;
lypinator 0:bb348c97df44 1337
lypinator 0:bb348c97df44 1338 /* Wait until the write operation will be taken into account :
lypinator 0:bb348c97df44 1339 at least four TX_CLK/RX_CLK clock cycles */
lypinator 0:bb348c97df44 1340 tmpreg1 = (heth->Instance)->MACCR;
lypinator 0:bb348c97df44 1341 HAL_Delay(ETH_REG_WRITE_DELAY);
lypinator 0:bb348c97df44 1342 (heth->Instance)->MACCR = tmpreg1;
lypinator 0:bb348c97df44 1343
lypinator 0:bb348c97df44 1344 /*----------------------- ETHERNET MACFFR Configuration --------------------*/
lypinator 0:bb348c97df44 1345 /* Write to ETHERNET MACFFR */
lypinator 0:bb348c97df44 1346 (heth->Instance)->MACFFR = (uint32_t)(macconf->ReceiveAll |
lypinator 0:bb348c97df44 1347 macconf->SourceAddrFilter |
lypinator 0:bb348c97df44 1348 macconf->PassControlFrames |
lypinator 0:bb348c97df44 1349 macconf->BroadcastFramesReception |
lypinator 0:bb348c97df44 1350 macconf->DestinationAddrFilter |
lypinator 0:bb348c97df44 1351 macconf->PromiscuousMode |
lypinator 0:bb348c97df44 1352 macconf->MulticastFramesFilter |
lypinator 0:bb348c97df44 1353 macconf->UnicastFramesFilter);
lypinator 0:bb348c97df44 1354
lypinator 0:bb348c97df44 1355 /* Wait until the write operation will be taken into account :
lypinator 0:bb348c97df44 1356 at least four TX_CLK/RX_CLK clock cycles */
lypinator 0:bb348c97df44 1357 tmpreg1 = (heth->Instance)->MACFFR;
lypinator 0:bb348c97df44 1358 HAL_Delay(ETH_REG_WRITE_DELAY);
lypinator 0:bb348c97df44 1359 (heth->Instance)->MACFFR = tmpreg1;
lypinator 0:bb348c97df44 1360
lypinator 0:bb348c97df44 1361 /*--------------- ETHERNET MACHTHR and MACHTLR Configuration ---------------*/
lypinator 0:bb348c97df44 1362 /* Write to ETHERNET MACHTHR */
lypinator 0:bb348c97df44 1363 (heth->Instance)->MACHTHR = (uint32_t)macconf->HashTableHigh;
lypinator 0:bb348c97df44 1364
lypinator 0:bb348c97df44 1365 /* Write to ETHERNET MACHTLR */
lypinator 0:bb348c97df44 1366 (heth->Instance)->MACHTLR = (uint32_t)macconf->HashTableLow;
lypinator 0:bb348c97df44 1367 /*----------------------- ETHERNET MACFCR Configuration --------------------*/
lypinator 0:bb348c97df44 1368
lypinator 0:bb348c97df44 1369 /* Get the ETHERNET MACFCR value */
lypinator 0:bb348c97df44 1370 tmpreg1 = (heth->Instance)->MACFCR;
lypinator 0:bb348c97df44 1371 /* Clear xx bits */
lypinator 0:bb348c97df44 1372 tmpreg1 &= ETH_MACFCR_CLEAR_MASK;
lypinator 0:bb348c97df44 1373
lypinator 0:bb348c97df44 1374 tmpreg1 |= (uint32_t)((macconf->PauseTime << 16U) |
lypinator 0:bb348c97df44 1375 macconf->ZeroQuantaPause |
lypinator 0:bb348c97df44 1376 macconf->PauseLowThreshold |
lypinator 0:bb348c97df44 1377 macconf->UnicastPauseFrameDetect |
lypinator 0:bb348c97df44 1378 macconf->ReceiveFlowControl |
lypinator 0:bb348c97df44 1379 macconf->TransmitFlowControl);
lypinator 0:bb348c97df44 1380
lypinator 0:bb348c97df44 1381 /* Write to ETHERNET MACFCR */
lypinator 0:bb348c97df44 1382 (heth->Instance)->MACFCR = (uint32_t)tmpreg1;
lypinator 0:bb348c97df44 1383
lypinator 0:bb348c97df44 1384 /* Wait until the write operation will be taken into account :
lypinator 0:bb348c97df44 1385 at least four TX_CLK/RX_CLK clock cycles */
lypinator 0:bb348c97df44 1386 tmpreg1 = (heth->Instance)->MACFCR;
lypinator 0:bb348c97df44 1387 HAL_Delay(ETH_REG_WRITE_DELAY);
lypinator 0:bb348c97df44 1388 (heth->Instance)->MACFCR = tmpreg1;
lypinator 0:bb348c97df44 1389
lypinator 0:bb348c97df44 1390 /*----------------------- ETHERNET MACVLANTR Configuration -----------------*/
lypinator 0:bb348c97df44 1391 (heth->Instance)->MACVLANTR = (uint32_t)(macconf->VLANTagComparison |
lypinator 0:bb348c97df44 1392 macconf->VLANTagIdentifier);
lypinator 0:bb348c97df44 1393
lypinator 0:bb348c97df44 1394 /* Wait until the write operation will be taken into account :
lypinator 0:bb348c97df44 1395 at least four TX_CLK/RX_CLK clock cycles */
lypinator 0:bb348c97df44 1396 tmpreg1 = (heth->Instance)->MACVLANTR;
lypinator 0:bb348c97df44 1397 HAL_Delay(ETH_REG_WRITE_DELAY);
lypinator 0:bb348c97df44 1398 (heth->Instance)->MACVLANTR = tmpreg1;
lypinator 0:bb348c97df44 1399 }
lypinator 0:bb348c97df44 1400 else /* macconf == NULL : here we just configure Speed and Duplex mode */
lypinator 0:bb348c97df44 1401 {
lypinator 0:bb348c97df44 1402 /*------------------------ ETHERNET MACCR Configuration --------------------*/
lypinator 0:bb348c97df44 1403 /* Get the ETHERNET MACCR value */
lypinator 0:bb348c97df44 1404 tmpreg1 = (heth->Instance)->MACCR;
lypinator 0:bb348c97df44 1405
lypinator 0:bb348c97df44 1406 /* Clear FES and DM bits */
lypinator 0:bb348c97df44 1407 tmpreg1 &= ~(0x00004800U);
lypinator 0:bb348c97df44 1408
lypinator 0:bb348c97df44 1409 tmpreg1 |= (uint32_t)(heth->Init.Speed | heth->Init.DuplexMode);
lypinator 0:bb348c97df44 1410
lypinator 0:bb348c97df44 1411 /* Write to ETHERNET MACCR */
lypinator 0:bb348c97df44 1412 (heth->Instance)->MACCR = (uint32_t)tmpreg1;
lypinator 0:bb348c97df44 1413
lypinator 0:bb348c97df44 1414 /* Wait until the write operation will be taken into account:
lypinator 0:bb348c97df44 1415 at least four TX_CLK/RX_CLK clock cycles */
lypinator 0:bb348c97df44 1416 tmpreg1 = (heth->Instance)->MACCR;
lypinator 0:bb348c97df44 1417 HAL_Delay(ETH_REG_WRITE_DELAY);
lypinator 0:bb348c97df44 1418 (heth->Instance)->MACCR = tmpreg1;
lypinator 0:bb348c97df44 1419 }
lypinator 0:bb348c97df44 1420
lypinator 0:bb348c97df44 1421 /* Set the ETH state to Ready */
lypinator 0:bb348c97df44 1422 heth->State= HAL_ETH_STATE_READY;
lypinator 0:bb348c97df44 1423
lypinator 0:bb348c97df44 1424 /* Process Unlocked */
lypinator 0:bb348c97df44 1425 __HAL_UNLOCK(heth);
lypinator 0:bb348c97df44 1426
lypinator 0:bb348c97df44 1427 /* Return function status */
lypinator 0:bb348c97df44 1428 return HAL_OK;
lypinator 0:bb348c97df44 1429 }
lypinator 0:bb348c97df44 1430
lypinator 0:bb348c97df44 1431 /**
lypinator 0:bb348c97df44 1432 * @brief Sets ETH DMA Configuration.
lypinator 0:bb348c97df44 1433 * @param heth pointer to a ETH_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 1434 * the configuration information for ETHERNET module
lypinator 0:bb348c97df44 1435 * @param dmaconf DMA Configuration structure
lypinator 0:bb348c97df44 1436 * @retval HAL status
lypinator 0:bb348c97df44 1437 */
lypinator 0:bb348c97df44 1438 HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf)
lypinator 0:bb348c97df44 1439 {
lypinator 0:bb348c97df44 1440 uint32_t tmpreg1 = 0U;
lypinator 0:bb348c97df44 1441
lypinator 0:bb348c97df44 1442 /* Process Locked */
lypinator 0:bb348c97df44 1443 __HAL_LOCK(heth);
lypinator 0:bb348c97df44 1444
lypinator 0:bb348c97df44 1445 /* Set the ETH peripheral state to BUSY */
lypinator 0:bb348c97df44 1446 heth->State= HAL_ETH_STATE_BUSY;
lypinator 0:bb348c97df44 1447
lypinator 0:bb348c97df44 1448 /* Check parameters */
lypinator 0:bb348c97df44 1449 assert_param(IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(dmaconf->DropTCPIPChecksumErrorFrame));
lypinator 0:bb348c97df44 1450 assert_param(IS_ETH_RECEIVE_STORE_FORWARD(dmaconf->ReceiveStoreForward));
lypinator 0:bb348c97df44 1451 assert_param(IS_ETH_FLUSH_RECEIVE_FRAME(dmaconf->FlushReceivedFrame));
lypinator 0:bb348c97df44 1452 assert_param(IS_ETH_TRANSMIT_STORE_FORWARD(dmaconf->TransmitStoreForward));
lypinator 0:bb348c97df44 1453 assert_param(IS_ETH_TRANSMIT_THRESHOLD_CONTROL(dmaconf->TransmitThresholdControl));
lypinator 0:bb348c97df44 1454 assert_param(IS_ETH_FORWARD_ERROR_FRAMES(dmaconf->ForwardErrorFrames));
lypinator 0:bb348c97df44 1455 assert_param(IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(dmaconf->ForwardUndersizedGoodFrames));
lypinator 0:bb348c97df44 1456 assert_param(IS_ETH_RECEIVE_THRESHOLD_CONTROL(dmaconf->ReceiveThresholdControl));
lypinator 0:bb348c97df44 1457 assert_param(IS_ETH_SECOND_FRAME_OPERATE(dmaconf->SecondFrameOperate));
lypinator 0:bb348c97df44 1458 assert_param(IS_ETH_ADDRESS_ALIGNED_BEATS(dmaconf->AddressAlignedBeats));
lypinator 0:bb348c97df44 1459 assert_param(IS_ETH_FIXED_BURST(dmaconf->FixedBurst));
lypinator 0:bb348c97df44 1460 assert_param(IS_ETH_RXDMA_BURST_LENGTH(dmaconf->RxDMABurstLength));
lypinator 0:bb348c97df44 1461 assert_param(IS_ETH_TXDMA_BURST_LENGTH(dmaconf->TxDMABurstLength));
lypinator 0:bb348c97df44 1462 assert_param(IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(dmaconf->EnhancedDescriptorFormat));
lypinator 0:bb348c97df44 1463 assert_param(IS_ETH_DMA_DESC_SKIP_LENGTH(dmaconf->DescriptorSkipLength));
lypinator 0:bb348c97df44 1464 assert_param(IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(dmaconf->DMAArbitration));
lypinator 0:bb348c97df44 1465
lypinator 0:bb348c97df44 1466 /*----------------------- ETHERNET DMAOMR Configuration --------------------*/
lypinator 0:bb348c97df44 1467 /* Get the ETHERNET DMAOMR value */
lypinator 0:bb348c97df44 1468 tmpreg1 = (heth->Instance)->DMAOMR;
lypinator 0:bb348c97df44 1469 /* Clear xx bits */
lypinator 0:bb348c97df44 1470 tmpreg1 &= ETH_DMAOMR_CLEAR_MASK;
lypinator 0:bb348c97df44 1471
lypinator 0:bb348c97df44 1472 tmpreg1 |= (uint32_t)(dmaconf->DropTCPIPChecksumErrorFrame |
lypinator 0:bb348c97df44 1473 dmaconf->ReceiveStoreForward |
lypinator 0:bb348c97df44 1474 dmaconf->FlushReceivedFrame |
lypinator 0:bb348c97df44 1475 dmaconf->TransmitStoreForward |
lypinator 0:bb348c97df44 1476 dmaconf->TransmitThresholdControl |
lypinator 0:bb348c97df44 1477 dmaconf->ForwardErrorFrames |
lypinator 0:bb348c97df44 1478 dmaconf->ForwardUndersizedGoodFrames |
lypinator 0:bb348c97df44 1479 dmaconf->ReceiveThresholdControl |
lypinator 0:bb348c97df44 1480 dmaconf->SecondFrameOperate);
lypinator 0:bb348c97df44 1481
lypinator 0:bb348c97df44 1482 /* Write to ETHERNET DMAOMR */
lypinator 0:bb348c97df44 1483 (heth->Instance)->DMAOMR = (uint32_t)tmpreg1;
lypinator 0:bb348c97df44 1484
lypinator 0:bb348c97df44 1485 /* Wait until the write operation will be taken into account:
lypinator 0:bb348c97df44 1486 at least four TX_CLK/RX_CLK clock cycles */
lypinator 0:bb348c97df44 1487 tmpreg1 = (heth->Instance)->DMAOMR;
lypinator 0:bb348c97df44 1488 HAL_Delay(ETH_REG_WRITE_DELAY);
lypinator 0:bb348c97df44 1489 (heth->Instance)->DMAOMR = tmpreg1;
lypinator 0:bb348c97df44 1490
lypinator 0:bb348c97df44 1491 /*----------------------- ETHERNET DMABMR Configuration --------------------*/
lypinator 0:bb348c97df44 1492 (heth->Instance)->DMABMR = (uint32_t)(dmaconf->AddressAlignedBeats |
lypinator 0:bb348c97df44 1493 dmaconf->FixedBurst |
lypinator 0:bb348c97df44 1494 dmaconf->RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
lypinator 0:bb348c97df44 1495 dmaconf->TxDMABurstLength |
lypinator 0:bb348c97df44 1496 dmaconf->EnhancedDescriptorFormat |
lypinator 0:bb348c97df44 1497 (dmaconf->DescriptorSkipLength << 2U) |
lypinator 0:bb348c97df44 1498 dmaconf->DMAArbitration |
lypinator 0:bb348c97df44 1499 ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
lypinator 0:bb348c97df44 1500
lypinator 0:bb348c97df44 1501 /* Wait until the write operation will be taken into account:
lypinator 0:bb348c97df44 1502 at least four TX_CLK/RX_CLK clock cycles */
lypinator 0:bb348c97df44 1503 tmpreg1 = (heth->Instance)->DMABMR;
lypinator 0:bb348c97df44 1504 HAL_Delay(ETH_REG_WRITE_DELAY);
lypinator 0:bb348c97df44 1505 (heth->Instance)->DMABMR = tmpreg1;
lypinator 0:bb348c97df44 1506
lypinator 0:bb348c97df44 1507 /* Set the ETH state to Ready */
lypinator 0:bb348c97df44 1508 heth->State= HAL_ETH_STATE_READY;
lypinator 0:bb348c97df44 1509
lypinator 0:bb348c97df44 1510 /* Process Unlocked */
lypinator 0:bb348c97df44 1511 __HAL_UNLOCK(heth);
lypinator 0:bb348c97df44 1512
lypinator 0:bb348c97df44 1513 /* Return function status */
lypinator 0:bb348c97df44 1514 return HAL_OK;
lypinator 0:bb348c97df44 1515 }
lypinator 0:bb348c97df44 1516
lypinator 0:bb348c97df44 1517 /**
lypinator 0:bb348c97df44 1518 * @}
lypinator 0:bb348c97df44 1519 */
lypinator 0:bb348c97df44 1520
lypinator 0:bb348c97df44 1521 /** @defgroup ETH_Exported_Functions_Group4 Peripheral State functions
lypinator 0:bb348c97df44 1522 * @brief Peripheral State functions
lypinator 0:bb348c97df44 1523 *
lypinator 0:bb348c97df44 1524 @verbatim
lypinator 0:bb348c97df44 1525 ===============================================================================
lypinator 0:bb348c97df44 1526 ##### Peripheral State functions #####
lypinator 0:bb348c97df44 1527 ===============================================================================
lypinator 0:bb348c97df44 1528 [..]
lypinator 0:bb348c97df44 1529 This subsection permits to get in run-time the status of the peripheral
lypinator 0:bb348c97df44 1530 and the data flow.
lypinator 0:bb348c97df44 1531 (+) Get the ETH handle state:
lypinator 0:bb348c97df44 1532 HAL_ETH_GetState();
lypinator 0:bb348c97df44 1533
lypinator 0:bb348c97df44 1534
lypinator 0:bb348c97df44 1535 @endverbatim
lypinator 0:bb348c97df44 1536 * @{
lypinator 0:bb348c97df44 1537 */
lypinator 0:bb348c97df44 1538
lypinator 0:bb348c97df44 1539 /**
lypinator 0:bb348c97df44 1540 * @brief Return the ETH HAL state
lypinator 0:bb348c97df44 1541 * @param heth pointer to a ETH_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 1542 * the configuration information for ETHERNET module
lypinator 0:bb348c97df44 1543 * @retval HAL state
lypinator 0:bb348c97df44 1544 */
lypinator 0:bb348c97df44 1545 HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth)
lypinator 0:bb348c97df44 1546 {
lypinator 0:bb348c97df44 1547 /* Return ETH state */
lypinator 0:bb348c97df44 1548 return heth->State;
lypinator 0:bb348c97df44 1549 }
lypinator 0:bb348c97df44 1550
lypinator 0:bb348c97df44 1551 /**
lypinator 0:bb348c97df44 1552 * @}
lypinator 0:bb348c97df44 1553 */
lypinator 0:bb348c97df44 1554
lypinator 0:bb348c97df44 1555 /**
lypinator 0:bb348c97df44 1556 * @}
lypinator 0:bb348c97df44 1557 */
lypinator 0:bb348c97df44 1558
lypinator 0:bb348c97df44 1559 /** @addtogroup ETH_Private_Functions
lypinator 0:bb348c97df44 1560 * @{
lypinator 0:bb348c97df44 1561 */
lypinator 0:bb348c97df44 1562
lypinator 0:bb348c97df44 1563 /**
lypinator 0:bb348c97df44 1564 * @brief Configures Ethernet MAC and DMA with default parameters.
lypinator 0:bb348c97df44 1565 * @param heth pointer to a ETH_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 1566 * the configuration information for ETHERNET module
lypinator 0:bb348c97df44 1567 * @param err Ethernet Init error
lypinator 0:bb348c97df44 1568 * @retval HAL status
lypinator 0:bb348c97df44 1569 */
lypinator 0:bb348c97df44 1570 static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err)
lypinator 0:bb348c97df44 1571 {
lypinator 0:bb348c97df44 1572 ETH_MACInitTypeDef macinit;
lypinator 0:bb348c97df44 1573 ETH_DMAInitTypeDef dmainit;
lypinator 0:bb348c97df44 1574 uint32_t tmpreg1 = 0U;
lypinator 0:bb348c97df44 1575
lypinator 0:bb348c97df44 1576 if (err != ETH_SUCCESS) /* Auto-negotiation failed */
lypinator 0:bb348c97df44 1577 {
lypinator 0:bb348c97df44 1578 /* Set Ethernet duplex mode to Full-duplex */
lypinator 0:bb348c97df44 1579 (heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX;
lypinator 0:bb348c97df44 1580
lypinator 0:bb348c97df44 1581 /* Set Ethernet speed to 100M */
lypinator 0:bb348c97df44 1582 (heth->Init).Speed = ETH_SPEED_100M;
lypinator 0:bb348c97df44 1583 }
lypinator 0:bb348c97df44 1584
lypinator 0:bb348c97df44 1585 /* Ethernet MAC default initialization **************************************/
lypinator 0:bb348c97df44 1586 macinit.Watchdog = ETH_WATCHDOG_ENABLE;
lypinator 0:bb348c97df44 1587 macinit.Jabber = ETH_JABBER_ENABLE;
lypinator 0:bb348c97df44 1588 macinit.InterFrameGap = ETH_INTERFRAMEGAP_96BIT;
lypinator 0:bb348c97df44 1589 macinit.CarrierSense = ETH_CARRIERSENCE_ENABLE;
lypinator 0:bb348c97df44 1590 macinit.ReceiveOwn = ETH_RECEIVEOWN_ENABLE;
lypinator 0:bb348c97df44 1591 macinit.LoopbackMode = ETH_LOOPBACKMODE_DISABLE;
lypinator 0:bb348c97df44 1592 if(heth->Init.ChecksumMode == ETH_CHECKSUM_BY_HARDWARE)
lypinator 0:bb348c97df44 1593 {
lypinator 0:bb348c97df44 1594 macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_ENABLE;
lypinator 0:bb348c97df44 1595 }
lypinator 0:bb348c97df44 1596 else
lypinator 0:bb348c97df44 1597 {
lypinator 0:bb348c97df44 1598 macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_DISABLE;
lypinator 0:bb348c97df44 1599 }
lypinator 0:bb348c97df44 1600 macinit.RetryTransmission = ETH_RETRYTRANSMISSION_DISABLE;
lypinator 0:bb348c97df44 1601 macinit.AutomaticPadCRCStrip = ETH_AUTOMATICPADCRCSTRIP_DISABLE;
lypinator 0:bb348c97df44 1602 macinit.BackOffLimit = ETH_BACKOFFLIMIT_10;
lypinator 0:bb348c97df44 1603 macinit.DeferralCheck = ETH_DEFFERRALCHECK_DISABLE;
lypinator 0:bb348c97df44 1604 macinit.ReceiveAll = ETH_RECEIVEAll_DISABLE;
lypinator 0:bb348c97df44 1605 macinit.SourceAddrFilter = ETH_SOURCEADDRFILTER_DISABLE;
lypinator 0:bb348c97df44 1606 macinit.PassControlFrames = ETH_PASSCONTROLFRAMES_BLOCKALL;
lypinator 0:bb348c97df44 1607 macinit.BroadcastFramesReception = ETH_BROADCASTFRAMESRECEPTION_ENABLE;
lypinator 0:bb348c97df44 1608 macinit.DestinationAddrFilter = ETH_DESTINATIONADDRFILTER_NORMAL;
lypinator 0:bb348c97df44 1609 macinit.PromiscuousMode = ETH_PROMISCUOUS_MODE_DISABLE;
lypinator 0:bb348c97df44 1610 macinit.MulticastFramesFilter = ETH_MULTICASTFRAMESFILTER_PERFECT;
lypinator 0:bb348c97df44 1611 macinit.UnicastFramesFilter = ETH_UNICASTFRAMESFILTER_PERFECT;
lypinator 0:bb348c97df44 1612 macinit.HashTableHigh = 0x0U;
lypinator 0:bb348c97df44 1613 macinit.HashTableLow = 0x0U;
lypinator 0:bb348c97df44 1614 macinit.PauseTime = 0x0U;
lypinator 0:bb348c97df44 1615 macinit.ZeroQuantaPause = ETH_ZEROQUANTAPAUSE_DISABLE;
lypinator 0:bb348c97df44 1616 macinit.PauseLowThreshold = ETH_PAUSELOWTHRESHOLD_MINUS4;
lypinator 0:bb348c97df44 1617 macinit.UnicastPauseFrameDetect = ETH_UNICASTPAUSEFRAMEDETECT_DISABLE;
lypinator 0:bb348c97df44 1618 macinit.ReceiveFlowControl = ETH_RECEIVEFLOWCONTROL_DISABLE;
lypinator 0:bb348c97df44 1619 macinit.TransmitFlowControl = ETH_TRANSMITFLOWCONTROL_DISABLE;
lypinator 0:bb348c97df44 1620 macinit.VLANTagComparison = ETH_VLANTAGCOMPARISON_16BIT;
lypinator 0:bb348c97df44 1621 macinit.VLANTagIdentifier = 0x0U;
lypinator 0:bb348c97df44 1622
lypinator 0:bb348c97df44 1623 /*------------------------ ETHERNET MACCR Configuration --------------------*/
lypinator 0:bb348c97df44 1624 /* Get the ETHERNET MACCR value */
lypinator 0:bb348c97df44 1625 tmpreg1 = (heth->Instance)->MACCR;
lypinator 0:bb348c97df44 1626 /* Clear WD, PCE, PS, TE and RE bits */
lypinator 0:bb348c97df44 1627 tmpreg1 &= ETH_MACCR_CLEAR_MASK;
lypinator 0:bb348c97df44 1628 /* Set the WD bit according to ETH Watchdog value */
lypinator 0:bb348c97df44 1629 /* Set the JD: bit according to ETH Jabber value */
lypinator 0:bb348c97df44 1630 /* Set the IFG bit according to ETH InterFrameGap value */
lypinator 0:bb348c97df44 1631 /* Set the DCRS bit according to ETH CarrierSense value */
lypinator 0:bb348c97df44 1632 /* Set the FES bit according to ETH Speed value */
lypinator 0:bb348c97df44 1633 /* Set the DO bit according to ETH ReceiveOwn value */
lypinator 0:bb348c97df44 1634 /* Set the LM bit according to ETH LoopbackMode value */
lypinator 0:bb348c97df44 1635 /* Set the DM bit according to ETH Mode value */
lypinator 0:bb348c97df44 1636 /* Set the IPCO bit according to ETH ChecksumOffload value */
lypinator 0:bb348c97df44 1637 /* Set the DR bit according to ETH RetryTransmission value */
lypinator 0:bb348c97df44 1638 /* Set the ACS bit according to ETH AutomaticPadCRCStrip value */
lypinator 0:bb348c97df44 1639 /* Set the BL bit according to ETH BackOffLimit value */
lypinator 0:bb348c97df44 1640 /* Set the DC bit according to ETH DeferralCheck value */
lypinator 0:bb348c97df44 1641 tmpreg1 |= (uint32_t)(macinit.Watchdog |
lypinator 0:bb348c97df44 1642 macinit.Jabber |
lypinator 0:bb348c97df44 1643 macinit.InterFrameGap |
lypinator 0:bb348c97df44 1644 macinit.CarrierSense |
lypinator 0:bb348c97df44 1645 (heth->Init).Speed |
lypinator 0:bb348c97df44 1646 macinit.ReceiveOwn |
lypinator 0:bb348c97df44 1647 macinit.LoopbackMode |
lypinator 0:bb348c97df44 1648 (heth->Init).DuplexMode |
lypinator 0:bb348c97df44 1649 macinit.ChecksumOffload |
lypinator 0:bb348c97df44 1650 macinit.RetryTransmission |
lypinator 0:bb348c97df44 1651 macinit.AutomaticPadCRCStrip |
lypinator 0:bb348c97df44 1652 macinit.BackOffLimit |
lypinator 0:bb348c97df44 1653 macinit.DeferralCheck);
lypinator 0:bb348c97df44 1654
lypinator 0:bb348c97df44 1655 /* Write to ETHERNET MACCR */
lypinator 0:bb348c97df44 1656 (heth->Instance)->MACCR = (uint32_t)tmpreg1;
lypinator 0:bb348c97df44 1657
lypinator 0:bb348c97df44 1658 /* Wait until the write operation will be taken into account:
lypinator 0:bb348c97df44 1659 at least four TX_CLK/RX_CLK clock cycles */
lypinator 0:bb348c97df44 1660 tmpreg1 = (heth->Instance)->MACCR;
lypinator 0:bb348c97df44 1661 HAL_Delay(ETH_REG_WRITE_DELAY);
lypinator 0:bb348c97df44 1662 (heth->Instance)->MACCR = tmpreg1;
lypinator 0:bb348c97df44 1663
lypinator 0:bb348c97df44 1664 /*----------------------- ETHERNET MACFFR Configuration --------------------*/
lypinator 0:bb348c97df44 1665 /* Set the RA bit according to ETH ReceiveAll value */
lypinator 0:bb348c97df44 1666 /* Set the SAF and SAIF bits according to ETH SourceAddrFilter value */
lypinator 0:bb348c97df44 1667 /* Set the PCF bit according to ETH PassControlFrames value */
lypinator 0:bb348c97df44 1668 /* Set the DBF bit according to ETH BroadcastFramesReception value */
lypinator 0:bb348c97df44 1669 /* Set the DAIF bit according to ETH DestinationAddrFilter value */
lypinator 0:bb348c97df44 1670 /* Set the PR bit according to ETH PromiscuousMode value */
lypinator 0:bb348c97df44 1671 /* Set the PM, HMC and HPF bits according to ETH MulticastFramesFilter value */
lypinator 0:bb348c97df44 1672 /* Set the HUC and HPF bits according to ETH UnicastFramesFilter value */
lypinator 0:bb348c97df44 1673 /* Write to ETHERNET MACFFR */
lypinator 0:bb348c97df44 1674 (heth->Instance)->MACFFR = (uint32_t)(macinit.ReceiveAll |
lypinator 0:bb348c97df44 1675 macinit.SourceAddrFilter |
lypinator 0:bb348c97df44 1676 macinit.PassControlFrames |
lypinator 0:bb348c97df44 1677 macinit.BroadcastFramesReception |
lypinator 0:bb348c97df44 1678 macinit.DestinationAddrFilter |
lypinator 0:bb348c97df44 1679 macinit.PromiscuousMode |
lypinator 0:bb348c97df44 1680 macinit.MulticastFramesFilter |
lypinator 0:bb348c97df44 1681 macinit.UnicastFramesFilter);
lypinator 0:bb348c97df44 1682
lypinator 0:bb348c97df44 1683 /* Wait until the write operation will be taken into account:
lypinator 0:bb348c97df44 1684 at least four TX_CLK/RX_CLK clock cycles */
lypinator 0:bb348c97df44 1685 tmpreg1 = (heth->Instance)->MACFFR;
lypinator 0:bb348c97df44 1686 HAL_Delay(ETH_REG_WRITE_DELAY);
lypinator 0:bb348c97df44 1687 (heth->Instance)->MACFFR = tmpreg1;
lypinator 0:bb348c97df44 1688
lypinator 0:bb348c97df44 1689 /*--------------- ETHERNET MACHTHR and MACHTLR Configuration --------------*/
lypinator 0:bb348c97df44 1690 /* Write to ETHERNET MACHTHR */
lypinator 0:bb348c97df44 1691 (heth->Instance)->MACHTHR = (uint32_t)macinit.HashTableHigh;
lypinator 0:bb348c97df44 1692
lypinator 0:bb348c97df44 1693 /* Write to ETHERNET MACHTLR */
lypinator 0:bb348c97df44 1694 (heth->Instance)->MACHTLR = (uint32_t)macinit.HashTableLow;
lypinator 0:bb348c97df44 1695 /*----------------------- ETHERNET MACFCR Configuration -------------------*/
lypinator 0:bb348c97df44 1696
lypinator 0:bb348c97df44 1697 /* Get the ETHERNET MACFCR value */
lypinator 0:bb348c97df44 1698 tmpreg1 = (heth->Instance)->MACFCR;
lypinator 0:bb348c97df44 1699 /* Clear xx bits */
lypinator 0:bb348c97df44 1700 tmpreg1 &= ETH_MACFCR_CLEAR_MASK;
lypinator 0:bb348c97df44 1701
lypinator 0:bb348c97df44 1702 /* Set the PT bit according to ETH PauseTime value */
lypinator 0:bb348c97df44 1703 /* Set the DZPQ bit according to ETH ZeroQuantaPause value */
lypinator 0:bb348c97df44 1704 /* Set the PLT bit according to ETH PauseLowThreshold value */
lypinator 0:bb348c97df44 1705 /* Set the UP bit according to ETH UnicastPauseFrameDetect value */
lypinator 0:bb348c97df44 1706 /* Set the RFE bit according to ETH ReceiveFlowControl value */
lypinator 0:bb348c97df44 1707 /* Set the TFE bit according to ETH TransmitFlowControl value */
lypinator 0:bb348c97df44 1708 tmpreg1 |= (uint32_t)((macinit.PauseTime << 16U) |
lypinator 0:bb348c97df44 1709 macinit.ZeroQuantaPause |
lypinator 0:bb348c97df44 1710 macinit.PauseLowThreshold |
lypinator 0:bb348c97df44 1711 macinit.UnicastPauseFrameDetect |
lypinator 0:bb348c97df44 1712 macinit.ReceiveFlowControl |
lypinator 0:bb348c97df44 1713 macinit.TransmitFlowControl);
lypinator 0:bb348c97df44 1714
lypinator 0:bb348c97df44 1715 /* Write to ETHERNET MACFCR */
lypinator 0:bb348c97df44 1716 (heth->Instance)->MACFCR = (uint32_t)tmpreg1;
lypinator 0:bb348c97df44 1717
lypinator 0:bb348c97df44 1718 /* Wait until the write operation will be taken into account:
lypinator 0:bb348c97df44 1719 at least four TX_CLK/RX_CLK clock cycles */
lypinator 0:bb348c97df44 1720 tmpreg1 = (heth->Instance)->MACFCR;
lypinator 0:bb348c97df44 1721 HAL_Delay(ETH_REG_WRITE_DELAY);
lypinator 0:bb348c97df44 1722 (heth->Instance)->MACFCR = tmpreg1;
lypinator 0:bb348c97df44 1723
lypinator 0:bb348c97df44 1724 /*----------------------- ETHERNET MACVLANTR Configuration ----------------*/
lypinator 0:bb348c97df44 1725 /* Set the ETV bit according to ETH VLANTagComparison value */
lypinator 0:bb348c97df44 1726 /* Set the VL bit according to ETH VLANTagIdentifier value */
lypinator 0:bb348c97df44 1727 (heth->Instance)->MACVLANTR = (uint32_t)(macinit.VLANTagComparison |
lypinator 0:bb348c97df44 1728 macinit.VLANTagIdentifier);
lypinator 0:bb348c97df44 1729
lypinator 0:bb348c97df44 1730 /* Wait until the write operation will be taken into account:
lypinator 0:bb348c97df44 1731 at least four TX_CLK/RX_CLK clock cycles */
lypinator 0:bb348c97df44 1732 tmpreg1 = (heth->Instance)->MACVLANTR;
lypinator 0:bb348c97df44 1733 HAL_Delay(ETH_REG_WRITE_DELAY);
lypinator 0:bb348c97df44 1734 (heth->Instance)->MACVLANTR = tmpreg1;
lypinator 0:bb348c97df44 1735
lypinator 0:bb348c97df44 1736 /* Ethernet DMA default initialization ************************************/
lypinator 0:bb348c97df44 1737 dmainit.DropTCPIPChecksumErrorFrame = ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE;
lypinator 0:bb348c97df44 1738 dmainit.ReceiveStoreForward = ETH_RECEIVESTOREFORWARD_ENABLE;
lypinator 0:bb348c97df44 1739 dmainit.FlushReceivedFrame = ETH_FLUSHRECEIVEDFRAME_ENABLE;
lypinator 0:bb348c97df44 1740 dmainit.TransmitStoreForward = ETH_TRANSMITSTOREFORWARD_ENABLE;
lypinator 0:bb348c97df44 1741 dmainit.TransmitThresholdControl = ETH_TRANSMITTHRESHOLDCONTROL_64BYTES;
lypinator 0:bb348c97df44 1742 dmainit.ForwardErrorFrames = ETH_FORWARDERRORFRAMES_DISABLE;
lypinator 0:bb348c97df44 1743 dmainit.ForwardUndersizedGoodFrames = ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE;
lypinator 0:bb348c97df44 1744 dmainit.ReceiveThresholdControl = ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES;
lypinator 0:bb348c97df44 1745 dmainit.SecondFrameOperate = ETH_SECONDFRAMEOPERARTE_ENABLE;
lypinator 0:bb348c97df44 1746 dmainit.AddressAlignedBeats = ETH_ADDRESSALIGNEDBEATS_ENABLE;
lypinator 0:bb348c97df44 1747 dmainit.FixedBurst = ETH_FIXEDBURST_ENABLE;
lypinator 0:bb348c97df44 1748 dmainit.RxDMABurstLength = ETH_RXDMABURSTLENGTH_32BEAT;
lypinator 0:bb348c97df44 1749 dmainit.TxDMABurstLength = ETH_TXDMABURSTLENGTH_32BEAT;
lypinator 0:bb348c97df44 1750 dmainit.EnhancedDescriptorFormat = ETH_DMAENHANCEDDESCRIPTOR_ENABLE;
lypinator 0:bb348c97df44 1751 dmainit.DescriptorSkipLength = 0x0U;
lypinator 0:bb348c97df44 1752 dmainit.DMAArbitration = ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1;
lypinator 0:bb348c97df44 1753
lypinator 0:bb348c97df44 1754 /* Get the ETHERNET DMAOMR value */
lypinator 0:bb348c97df44 1755 tmpreg1 = (heth->Instance)->DMAOMR;
lypinator 0:bb348c97df44 1756 /* Clear xx bits */
lypinator 0:bb348c97df44 1757 tmpreg1 &= ETH_DMAOMR_CLEAR_MASK;
lypinator 0:bb348c97df44 1758
lypinator 0:bb348c97df44 1759 /* Set the DT bit according to ETH DropTCPIPChecksumErrorFrame value */
lypinator 0:bb348c97df44 1760 /* Set the RSF bit according to ETH ReceiveStoreForward value */
lypinator 0:bb348c97df44 1761 /* Set the DFF bit according to ETH FlushReceivedFrame value */
lypinator 0:bb348c97df44 1762 /* Set the TSF bit according to ETH TransmitStoreForward value */
lypinator 0:bb348c97df44 1763 /* Set the TTC bit according to ETH TransmitThresholdControl value */
lypinator 0:bb348c97df44 1764 /* Set the FEF bit according to ETH ForwardErrorFrames value */
lypinator 0:bb348c97df44 1765 /* Set the FUF bit according to ETH ForwardUndersizedGoodFrames value */
lypinator 0:bb348c97df44 1766 /* Set the RTC bit according to ETH ReceiveThresholdControl value */
lypinator 0:bb348c97df44 1767 /* Set the OSF bit according to ETH SecondFrameOperate value */
lypinator 0:bb348c97df44 1768 tmpreg1 |= (uint32_t)(dmainit.DropTCPIPChecksumErrorFrame |
lypinator 0:bb348c97df44 1769 dmainit.ReceiveStoreForward |
lypinator 0:bb348c97df44 1770 dmainit.FlushReceivedFrame |
lypinator 0:bb348c97df44 1771 dmainit.TransmitStoreForward |
lypinator 0:bb348c97df44 1772 dmainit.TransmitThresholdControl |
lypinator 0:bb348c97df44 1773 dmainit.ForwardErrorFrames |
lypinator 0:bb348c97df44 1774 dmainit.ForwardUndersizedGoodFrames |
lypinator 0:bb348c97df44 1775 dmainit.ReceiveThresholdControl |
lypinator 0:bb348c97df44 1776 dmainit.SecondFrameOperate);
lypinator 0:bb348c97df44 1777
lypinator 0:bb348c97df44 1778 /* Write to ETHERNET DMAOMR */
lypinator 0:bb348c97df44 1779 (heth->Instance)->DMAOMR = (uint32_t)tmpreg1;
lypinator 0:bb348c97df44 1780
lypinator 0:bb348c97df44 1781 /* Wait until the write operation will be taken into account:
lypinator 0:bb348c97df44 1782 at least four TX_CLK/RX_CLK clock cycles */
lypinator 0:bb348c97df44 1783 tmpreg1 = (heth->Instance)->DMAOMR;
lypinator 0:bb348c97df44 1784 HAL_Delay(ETH_REG_WRITE_DELAY);
lypinator 0:bb348c97df44 1785 (heth->Instance)->DMAOMR = tmpreg1;
lypinator 0:bb348c97df44 1786
lypinator 0:bb348c97df44 1787 /*----------------------- ETHERNET DMABMR Configuration ------------------*/
lypinator 0:bb348c97df44 1788 /* Set the AAL bit according to ETH AddressAlignedBeats value */
lypinator 0:bb348c97df44 1789 /* Set the FB bit according to ETH FixedBurst value */
lypinator 0:bb348c97df44 1790 /* Set the RPBL and 4*PBL bits according to ETH RxDMABurstLength value */
lypinator 0:bb348c97df44 1791 /* Set the PBL and 4*PBL bits according to ETH TxDMABurstLength value */
lypinator 0:bb348c97df44 1792 /* Set the Enhanced DMA descriptors bit according to ETH EnhancedDescriptorFormat value*/
lypinator 0:bb348c97df44 1793 /* Set the DSL bit according to ETH DesciptorSkipLength value */
lypinator 0:bb348c97df44 1794 /* Set the PR and DA bits according to ETH DMAArbitration value */
lypinator 0:bb348c97df44 1795 (heth->Instance)->DMABMR = (uint32_t)(dmainit.AddressAlignedBeats |
lypinator 0:bb348c97df44 1796 dmainit.FixedBurst |
lypinator 0:bb348c97df44 1797 dmainit.RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
lypinator 0:bb348c97df44 1798 dmainit.TxDMABurstLength |
lypinator 0:bb348c97df44 1799 dmainit.EnhancedDescriptorFormat |
lypinator 0:bb348c97df44 1800 (dmainit.DescriptorSkipLength << 2U) |
lypinator 0:bb348c97df44 1801 dmainit.DMAArbitration |
lypinator 0:bb348c97df44 1802 ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
lypinator 0:bb348c97df44 1803
lypinator 0:bb348c97df44 1804 /* Wait until the write operation will be taken into account:
lypinator 0:bb348c97df44 1805 at least four TX_CLK/RX_CLK clock cycles */
lypinator 0:bb348c97df44 1806 tmpreg1 = (heth->Instance)->DMABMR;
lypinator 0:bb348c97df44 1807 HAL_Delay(ETH_REG_WRITE_DELAY);
lypinator 0:bb348c97df44 1808 (heth->Instance)->DMABMR = tmpreg1;
lypinator 0:bb348c97df44 1809
lypinator 0:bb348c97df44 1810 if((heth->Init).RxMode == ETH_RXINTERRUPT_MODE)
lypinator 0:bb348c97df44 1811 {
lypinator 0:bb348c97df44 1812 /* Enable the Ethernet Rx Interrupt */
lypinator 0:bb348c97df44 1813 __HAL_ETH_DMA_ENABLE_IT((heth), ETH_DMA_IT_NIS | ETH_DMA_IT_R);
lypinator 0:bb348c97df44 1814 }
lypinator 0:bb348c97df44 1815
lypinator 0:bb348c97df44 1816 /* Initialize MAC address in ethernet MAC */
lypinator 0:bb348c97df44 1817 ETH_MACAddressConfig(heth, ETH_MAC_ADDRESS0, heth->Init.MACAddr);
lypinator 0:bb348c97df44 1818 }
lypinator 0:bb348c97df44 1819
lypinator 0:bb348c97df44 1820 /**
lypinator 0:bb348c97df44 1821 * @brief Configures the selected MAC address.
lypinator 0:bb348c97df44 1822 * @param heth pointer to a ETH_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 1823 * the configuration information for ETHERNET module
lypinator 0:bb348c97df44 1824 * @param MacAddr The MAC address to configure
lypinator 0:bb348c97df44 1825 * This parameter can be one of the following values:
lypinator 0:bb348c97df44 1826 * @arg ETH_MAC_Address0: MAC Address0
lypinator 0:bb348c97df44 1827 * @arg ETH_MAC_Address1: MAC Address1
lypinator 0:bb348c97df44 1828 * @arg ETH_MAC_Address2: MAC Address2
lypinator 0:bb348c97df44 1829 * @arg ETH_MAC_Address3: MAC Address3
lypinator 0:bb348c97df44 1830 * @param Addr Pointer to MAC address buffer data (6 bytes)
lypinator 0:bb348c97df44 1831 * @retval HAL status
lypinator 0:bb348c97df44 1832 */
lypinator 0:bb348c97df44 1833 static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr)
lypinator 0:bb348c97df44 1834 {
lypinator 0:bb348c97df44 1835 uint32_t tmpreg1;
lypinator 0:bb348c97df44 1836
lypinator 0:bb348c97df44 1837 /* Prevent unused argument(s) compilation warning */
lypinator 0:bb348c97df44 1838 UNUSED(heth);
lypinator 0:bb348c97df44 1839
lypinator 0:bb348c97df44 1840 /* Check the parameters */
lypinator 0:bb348c97df44 1841 assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr));
lypinator 0:bb348c97df44 1842
lypinator 0:bb348c97df44 1843 /* Calculate the selected MAC address high register */
lypinator 0:bb348c97df44 1844 tmpreg1 = ((uint32_t)Addr[5U] << 8U) | (uint32_t)Addr[4U];
lypinator 0:bb348c97df44 1845 /* Load the selected MAC address high register */
lypinator 0:bb348c97df44 1846 (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_HBASE + MacAddr))) = tmpreg1;
lypinator 0:bb348c97df44 1847 /* Calculate the selected MAC address low register */
lypinator 0:bb348c97df44 1848 tmpreg1 = ((uint32_t)Addr[3U] << 24U) | ((uint32_t)Addr[2U] << 16U) | ((uint32_t)Addr[1U] << 8U) | Addr[0U];
lypinator 0:bb348c97df44 1849
lypinator 0:bb348c97df44 1850 /* Load the selected MAC address low register */
lypinator 0:bb348c97df44 1851 (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_LBASE + MacAddr))) = tmpreg1;
lypinator 0:bb348c97df44 1852 }
lypinator 0:bb348c97df44 1853
lypinator 0:bb348c97df44 1854 /**
lypinator 0:bb348c97df44 1855 * @brief Enables the MAC transmission.
lypinator 0:bb348c97df44 1856 * @param heth pointer to a ETH_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 1857 * the configuration information for ETHERNET module
lypinator 0:bb348c97df44 1858 * @retval None
lypinator 0:bb348c97df44 1859 */
lypinator 0:bb348c97df44 1860 static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth)
lypinator 0:bb348c97df44 1861 {
lypinator 0:bb348c97df44 1862 __IO uint32_t tmpreg1 = 0U;
lypinator 0:bb348c97df44 1863
lypinator 0:bb348c97df44 1864 /* Enable the MAC transmission */
lypinator 0:bb348c97df44 1865 (heth->Instance)->MACCR |= ETH_MACCR_TE;
lypinator 0:bb348c97df44 1866
lypinator 0:bb348c97df44 1867 /* Wait until the write operation will be taken into account:
lypinator 0:bb348c97df44 1868 at least four TX_CLK/RX_CLK clock cycles */
lypinator 0:bb348c97df44 1869 tmpreg1 = (heth->Instance)->MACCR;
lypinator 0:bb348c97df44 1870 ETH_Delay(ETH_REG_WRITE_DELAY);
lypinator 0:bb348c97df44 1871 (heth->Instance)->MACCR = tmpreg1;
lypinator 0:bb348c97df44 1872 }
lypinator 0:bb348c97df44 1873
lypinator 0:bb348c97df44 1874 /**
lypinator 0:bb348c97df44 1875 * @brief Disables the MAC transmission.
lypinator 0:bb348c97df44 1876 * @param heth pointer to a ETH_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 1877 * the configuration information for ETHERNET module
lypinator 0:bb348c97df44 1878 * @retval None
lypinator 0:bb348c97df44 1879 */
lypinator 0:bb348c97df44 1880 static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth)
lypinator 0:bb348c97df44 1881 {
lypinator 0:bb348c97df44 1882 __IO uint32_t tmpreg1 = 0U;
lypinator 0:bb348c97df44 1883
lypinator 0:bb348c97df44 1884 /* Disable the MAC transmission */
lypinator 0:bb348c97df44 1885 (heth->Instance)->MACCR &= ~ETH_MACCR_TE;
lypinator 0:bb348c97df44 1886
lypinator 0:bb348c97df44 1887 /* Wait until the write operation will be taken into account:
lypinator 0:bb348c97df44 1888 at least four TX_CLK/RX_CLK clock cycles */
lypinator 0:bb348c97df44 1889 tmpreg1 = (heth->Instance)->MACCR;
lypinator 0:bb348c97df44 1890 ETH_Delay(ETH_REG_WRITE_DELAY);
lypinator 0:bb348c97df44 1891 (heth->Instance)->MACCR = tmpreg1;
lypinator 0:bb348c97df44 1892 }
lypinator 0:bb348c97df44 1893
lypinator 0:bb348c97df44 1894 /**
lypinator 0:bb348c97df44 1895 * @brief Enables the MAC reception.
lypinator 0:bb348c97df44 1896 * @param heth pointer to a ETH_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 1897 * the configuration information for ETHERNET module
lypinator 0:bb348c97df44 1898 * @retval None
lypinator 0:bb348c97df44 1899 */
lypinator 0:bb348c97df44 1900 static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth)
lypinator 0:bb348c97df44 1901 {
lypinator 0:bb348c97df44 1902 __IO uint32_t tmpreg1 = 0U;
lypinator 0:bb348c97df44 1903
lypinator 0:bb348c97df44 1904 /* Enable the MAC reception */
lypinator 0:bb348c97df44 1905 (heth->Instance)->MACCR |= ETH_MACCR_RE;
lypinator 0:bb348c97df44 1906
lypinator 0:bb348c97df44 1907 /* Wait until the write operation will be taken into account:
lypinator 0:bb348c97df44 1908 at least four TX_CLK/RX_CLK clock cycles */
lypinator 0:bb348c97df44 1909 tmpreg1 = (heth->Instance)->MACCR;
lypinator 0:bb348c97df44 1910 ETH_Delay(ETH_REG_WRITE_DELAY);
lypinator 0:bb348c97df44 1911 (heth->Instance)->MACCR = tmpreg1;
lypinator 0:bb348c97df44 1912 }
lypinator 0:bb348c97df44 1913
lypinator 0:bb348c97df44 1914 /**
lypinator 0:bb348c97df44 1915 * @brief Disables the MAC reception.
lypinator 0:bb348c97df44 1916 * @param heth pointer to a ETH_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 1917 * the configuration information for ETHERNET module
lypinator 0:bb348c97df44 1918 * @retval None
lypinator 0:bb348c97df44 1919 */
lypinator 0:bb348c97df44 1920 static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth)
lypinator 0:bb348c97df44 1921 {
lypinator 0:bb348c97df44 1922 __IO uint32_t tmpreg1 = 0U;
lypinator 0:bb348c97df44 1923
lypinator 0:bb348c97df44 1924 /* Disable the MAC reception */
lypinator 0:bb348c97df44 1925 (heth->Instance)->MACCR &= ~ETH_MACCR_RE;
lypinator 0:bb348c97df44 1926
lypinator 0:bb348c97df44 1927 /* Wait until the write operation will be taken into account:
lypinator 0:bb348c97df44 1928 at least four TX_CLK/RX_CLK clock cycles */
lypinator 0:bb348c97df44 1929 tmpreg1 = (heth->Instance)->MACCR;
lypinator 0:bb348c97df44 1930 ETH_Delay(ETH_REG_WRITE_DELAY);
lypinator 0:bb348c97df44 1931 (heth->Instance)->MACCR = tmpreg1;
lypinator 0:bb348c97df44 1932 }
lypinator 0:bb348c97df44 1933
lypinator 0:bb348c97df44 1934 /**
lypinator 0:bb348c97df44 1935 * @brief Enables the DMA transmission.
lypinator 0:bb348c97df44 1936 * @param heth pointer to a ETH_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 1937 * the configuration information for ETHERNET module
lypinator 0:bb348c97df44 1938 * @retval None
lypinator 0:bb348c97df44 1939 */
lypinator 0:bb348c97df44 1940 static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth)
lypinator 0:bb348c97df44 1941 {
lypinator 0:bb348c97df44 1942 /* Enable the DMA transmission */
lypinator 0:bb348c97df44 1943 (heth->Instance)->DMAOMR |= ETH_DMAOMR_ST;
lypinator 0:bb348c97df44 1944 }
lypinator 0:bb348c97df44 1945
lypinator 0:bb348c97df44 1946 /**
lypinator 0:bb348c97df44 1947 * @brief Disables the DMA transmission.
lypinator 0:bb348c97df44 1948 * @param heth pointer to a ETH_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 1949 * the configuration information for ETHERNET module
lypinator 0:bb348c97df44 1950 * @retval None
lypinator 0:bb348c97df44 1951 */
lypinator 0:bb348c97df44 1952 static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth)
lypinator 0:bb348c97df44 1953 {
lypinator 0:bb348c97df44 1954 /* Disable the DMA transmission */
lypinator 0:bb348c97df44 1955 (heth->Instance)->DMAOMR &= ~ETH_DMAOMR_ST;
lypinator 0:bb348c97df44 1956 }
lypinator 0:bb348c97df44 1957
lypinator 0:bb348c97df44 1958 /**
lypinator 0:bb348c97df44 1959 * @brief Enables the DMA reception.
lypinator 0:bb348c97df44 1960 * @param heth pointer to a ETH_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 1961 * the configuration information for ETHERNET module
lypinator 0:bb348c97df44 1962 * @retval None
lypinator 0:bb348c97df44 1963 */
lypinator 0:bb348c97df44 1964 static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth)
lypinator 0:bb348c97df44 1965 {
lypinator 0:bb348c97df44 1966 /* Enable the DMA reception */
lypinator 0:bb348c97df44 1967 (heth->Instance)->DMAOMR |= ETH_DMAOMR_SR;
lypinator 0:bb348c97df44 1968 }
lypinator 0:bb348c97df44 1969
lypinator 0:bb348c97df44 1970 /**
lypinator 0:bb348c97df44 1971 * @brief Disables the DMA reception.
lypinator 0:bb348c97df44 1972 * @param heth pointer to a ETH_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 1973 * the configuration information for ETHERNET module
lypinator 0:bb348c97df44 1974 * @retval None
lypinator 0:bb348c97df44 1975 */
lypinator 0:bb348c97df44 1976 static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth)
lypinator 0:bb348c97df44 1977 {
lypinator 0:bb348c97df44 1978 /* Disable the DMA reception */
lypinator 0:bb348c97df44 1979 (heth->Instance)->DMAOMR &= ~ETH_DMAOMR_SR;
lypinator 0:bb348c97df44 1980 }
lypinator 0:bb348c97df44 1981
lypinator 0:bb348c97df44 1982 /**
lypinator 0:bb348c97df44 1983 * @brief Clears the ETHERNET transmit FIFO.
lypinator 0:bb348c97df44 1984 * @param heth pointer to a ETH_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 1985 * the configuration information for ETHERNET module
lypinator 0:bb348c97df44 1986 * @retval None
lypinator 0:bb348c97df44 1987 */
lypinator 0:bb348c97df44 1988 static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth)
lypinator 0:bb348c97df44 1989 {
lypinator 0:bb348c97df44 1990 __IO uint32_t tmpreg1 = 0U;
lypinator 0:bb348c97df44 1991
lypinator 0:bb348c97df44 1992 /* Set the Flush Transmit FIFO bit */
lypinator 0:bb348c97df44 1993 (heth->Instance)->DMAOMR |= ETH_DMAOMR_FTF;
lypinator 0:bb348c97df44 1994
lypinator 0:bb348c97df44 1995 /* Wait until the write operation will be taken into account:
lypinator 0:bb348c97df44 1996 at least four TX_CLK/RX_CLK clock cycles */
lypinator 0:bb348c97df44 1997 tmpreg1 = (heth->Instance)->DMAOMR;
lypinator 0:bb348c97df44 1998 ETH_Delay(ETH_REG_WRITE_DELAY);
lypinator 0:bb348c97df44 1999 (heth->Instance)->DMAOMR = tmpreg1;
lypinator 0:bb348c97df44 2000 }
lypinator 0:bb348c97df44 2001
lypinator 0:bb348c97df44 2002 /**
lypinator 0:bb348c97df44 2003 * @brief This function provides delay (in milliseconds) based on CPU cycles method.
lypinator 0:bb348c97df44 2004 * @param mdelay specifies the delay time length, in milliseconds.
lypinator 0:bb348c97df44 2005 * @retval None
lypinator 0:bb348c97df44 2006 */
lypinator 0:bb348c97df44 2007 static void ETH_Delay(uint32_t mdelay)
lypinator 0:bb348c97df44 2008 {
lypinator 0:bb348c97df44 2009 __IO uint32_t Delay = mdelay * (SystemCoreClock / 8U / 1000U);
lypinator 0:bb348c97df44 2010 do
lypinator 0:bb348c97df44 2011 {
lypinator 0:bb348c97df44 2012 __NOP();
lypinator 0:bb348c97df44 2013 }
lypinator 0:bb348c97df44 2014 while (Delay --);
lypinator 0:bb348c97df44 2015 }
lypinator 0:bb348c97df44 2016
lypinator 0:bb348c97df44 2017 /**
lypinator 0:bb348c97df44 2018 * @}
lypinator 0:bb348c97df44 2019 */
lypinator 0:bb348c97df44 2020
lypinator 0:bb348c97df44 2021 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx ||\
lypinator 0:bb348c97df44 2022 STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
lypinator 0:bb348c97df44 2023 #endif /* HAL_ETH_MODULE_ENABLED */
lypinator 0:bb348c97df44 2024 /**
lypinator 0:bb348c97df44 2025 * @}
lypinator 0:bb348c97df44 2026 */
lypinator 0:bb348c97df44 2027
lypinator 0:bb348c97df44 2028 /**
lypinator 0:bb348c97df44 2029 * @}
lypinator 0:bb348c97df44 2030 */
lypinator 0:bb348c97df44 2031
lypinator 0:bb348c97df44 2032 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/