Thomas Lyp / DevLibMemoryController

Initial commit

Dependencies:   FastPWM

mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dma2d.c@0:bb348c97df44, 2020-09-16 (annotated)

Committer:
lypinator
Date:
Wed Sep 16 01:11:49 2020 +0000
Revision:
0:bb348c97df44
Added PWM

Who changed what in which revision?

UserRevisionLine numberNew contents of line
lypinator 0:bb348c97df44 1 /**
lypinator 0:bb348c97df44 2 ******************************************************************************
lypinator 0:bb348c97df44 3 * @file stm32f4xx_hal_dma2d.c
lypinator 0:bb348c97df44 4 * @author MCD Application Team
lypinator 0:bb348c97df44 5 * @brief DMA2D HAL module driver.
lypinator 0:bb348c97df44 6 * This file provides firmware functions to manage the following
lypinator 0:bb348c97df44 7 * functionalities of the DMA2D peripheral:
lypinator 0:bb348c97df44 8 * + Initialization and de-initialization functions
lypinator 0:bb348c97df44 9 * + IO operation functions
lypinator 0:bb348c97df44 10 * + Peripheral Control functions
lypinator 0:bb348c97df44 11 * + Peripheral State and Errors functions
lypinator 0:bb348c97df44 12 *
lypinator 0:bb348c97df44 13 @verbatim
lypinator 0:bb348c97df44 14 ==============================================================================
lypinator 0:bb348c97df44 15 ##### How to use this driver #####
lypinator 0:bb348c97df44 16 ==============================================================================
lypinator 0:bb348c97df44 17 [..]
lypinator 0:bb348c97df44 18 (#) Program the required configuration through the following parameters:
lypinator 0:bb348c97df44 19 the transfer mode, the output color mode and the output offset using
lypinator 0:bb348c97df44 20 HAL_DMA2D_Init() function.
lypinator 0:bb348c97df44 21
lypinator 0:bb348c97df44 22 (#) Program the required configuration through the following parameters:
lypinator 0:bb348c97df44 23 the input color mode, the input color, the input alpha value, the alpha mode,
lypinator 0:bb348c97df44 24 and the input offset using HAL_DMA2D_ConfigLayer() function for foreground
lypinator 0:bb348c97df44 25 or/and background layer.
lypinator 0:bb348c97df44 26
lypinator 0:bb348c97df44 27 *** Polling mode IO operation ***
lypinator 0:bb348c97df44 28 =================================
lypinator 0:bb348c97df44 29 [..]
lypinator 0:bb348c97df44 30 (#) Configure pdata parameter (explained hereafter), destination and data length
lypinator 0:bb348c97df44 31 and enable the transfer using HAL_DMA2D_Start().
lypinator 0:bb348c97df44 32 (#) Wait for end of transfer using HAL_DMA2D_PollForTransfer(), at this stage
lypinator 0:bb348c97df44 33 user can specify the value of timeout according to his end application.
lypinator 0:bb348c97df44 34
lypinator 0:bb348c97df44 35 *** Interrupt mode IO operation ***
lypinator 0:bb348c97df44 36 ===================================
lypinator 0:bb348c97df44 37 [..]
lypinator 0:bb348c97df44 38 (#) Configure pdata parameter, destination and data length and enable
lypinator 0:bb348c97df44 39 the transfer using HAL_DMA2D_Start_IT().
lypinator 0:bb348c97df44 40 (#) Use HAL_DMA2D_IRQHandler() called under DMA2D_IRQHandler() interrupt subroutine
lypinator 0:bb348c97df44 41 (#) At the end of data transfer HAL_DMA2D_IRQHandler() function is executed and user can
lypinator 0:bb348c97df44 42 add his own function by customization of function pointer XferCpltCallback (member
lypinator 0:bb348c97df44 43 of DMA2D handle structure).
lypinator 0:bb348c97df44 44 (#) In case of error, the HAL_DMA2D_IRQHandler() function will call the callback
lypinator 0:bb348c97df44 45 XferErrorCallback.
lypinator 0:bb348c97df44 46
lypinator 0:bb348c97df44 47 -@- In Register-to-Memory transfer mode, pdata parameter is the register
lypinator 0:bb348c97df44 48 color, in Memory-to-memory or Memory-to-Memory with pixel format
lypinator 0:bb348c97df44 49 conversion pdata is the source address.
lypinator 0:bb348c97df44 50
lypinator 0:bb348c97df44 51 -@- Configure the foreground source address, the background source address,
lypinator 0:bb348c97df44 52 the destination and data length then Enable the transfer using
lypinator 0:bb348c97df44 53 HAL_DMA2D_BlendingStart() in polling mode and HAL_DMA2D_BlendingStart_IT()
lypinator 0:bb348c97df44 54 in interrupt mode
lypinator 0:bb348c97df44 55
lypinator 0:bb348c97df44 56 -@- HAL_DMA2D_BlendingStart() and HAL_DMA2D_BlendingStart_IT() functions
lypinator 0:bb348c97df44 57 are used if the memory to memory with blending transfer mode is selected.
lypinator 0:bb348c97df44 58
lypinator 0:bb348c97df44 59 (#) Optionally, configure and enable the CLUT using HAL_DMA2D_CLUTLoad() in polling
lypinator 0:bb348c97df44 60 mode or HAL_DMA2D_CLUTLoad_IT() in interrupt mode.
lypinator 0:bb348c97df44 61
lypinator 0:bb348c97df44 62 (#) Optionally, configure the line watermark in using the API HAL_DMA2D_ProgramLineEvent()
lypinator 0:bb348c97df44 63
lypinator 0:bb348c97df44 64 (#) Optionally, configure the dead time value in the AHB clock cycle inserted between two
lypinator 0:bb348c97df44 65 consecutive accesses on the AHB master port in using the API HAL_DMA2D_ConfigDeadTime()
lypinator 0:bb348c97df44 66 and enable/disable the functionality with the APIs HAL_DMA2D_EnableDeadTime() or
lypinator 0:bb348c97df44 67 HAL_DMA2D_DisableDeadTime().
lypinator 0:bb348c97df44 68
lypinator 0:bb348c97df44 69 (#) The transfer can be suspended, resumed and aborted using the following
lypinator 0:bb348c97df44 70 functions: HAL_DMA2D_Suspend(), HAL_DMA2D_Resume(), HAL_DMA2D_Abort().
lypinator 0:bb348c97df44 71
lypinator 0:bb348c97df44 72 (#) The CLUT loading can be suspended, resumed and aborted using the following
lypinator 0:bb348c97df44 73 functions: HAL_DMA2D_CLUTLoading_Suspend(), HAL_DMA2D_CLUTLoading_Resume(),
lypinator 0:bb348c97df44 74 HAL_DMA2D_CLUTLoading_Abort().
lypinator 0:bb348c97df44 75
lypinator 0:bb348c97df44 76 (#) To control the DMA2D state, use the following function: HAL_DMA2D_GetState().
lypinator 0:bb348c97df44 77
lypinator 0:bb348c97df44 78 (#) To read the DMA2D error code, use the following function: HAL_DMA2D_GetError().
lypinator 0:bb348c97df44 79
lypinator 0:bb348c97df44 80 *** DMA2D HAL driver macros list ***
lypinator 0:bb348c97df44 81 =============================================
lypinator 0:bb348c97df44 82 [..]
lypinator 0:bb348c97df44 83 Below the list of most used macros in DMA2D HAL driver :
lypinator 0:bb348c97df44 84
lypinator 0:bb348c97df44 85 (+) __HAL_DMA2D_ENABLE: Enable the DMA2D peripheral.
lypinator 0:bb348c97df44 86 (+) __HAL_DMA2D_GET_FLAG: Get the DMA2D pending flags.
lypinator 0:bb348c97df44 87 (+) __HAL_DMA2D_CLEAR_FLAG: Clear the DMA2D pending flags.
lypinator 0:bb348c97df44 88 (+) __HAL_DMA2D_ENABLE_IT: Enable the specified DMA2D interrupts.
lypinator 0:bb348c97df44 89 (+) __HAL_DMA2D_DISABLE_IT: Disable the specified DMA2D interrupts.
lypinator 0:bb348c97df44 90 (+) __HAL_DMA2D_GET_IT_SOURCE: Check whether the specified DMA2D interrupt is enabled or not
lypinator 0:bb348c97df44 91
lypinator 0:bb348c97df44 92 [..]
lypinator 0:bb348c97df44 93 (@) You can refer to the DMA2D HAL driver header file for more useful macros
lypinator 0:bb348c97df44 94
lypinator 0:bb348c97df44 95 @endverbatim
lypinator 0:bb348c97df44 96 ******************************************************************************
lypinator 0:bb348c97df44 97 * @attention
lypinator 0:bb348c97df44 98 *
lypinator 0:bb348c97df44 99 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
lypinator 0:bb348c97df44 100 *
lypinator 0:bb348c97df44 101 * Redistribution and use in source and binary forms, with or without modification,
lypinator 0:bb348c97df44 102 * are permitted provided that the following conditions are met:
lypinator 0:bb348c97df44 103 * 1. Redistributions of source code must retain the above copyright notice,
lypinator 0:bb348c97df44 104 * this list of conditions and the following disclaimer.
lypinator 0:bb348c97df44 105 * 2. Redistributions in binary form must reproduce the above copyright notice,
lypinator 0:bb348c97df44 106 * this list of conditions and the following disclaimer in the documentation
lypinator 0:bb348c97df44 107 * and/or other materials provided with the distribution.
lypinator 0:bb348c97df44 108 * 3. Neither the name of STMicroelectronics nor the names of its contributors
lypinator 0:bb348c97df44 109 * may be used to endorse or promote products derived from this software
lypinator 0:bb348c97df44 110 * without specific prior written permission.
lypinator 0:bb348c97df44 111 *
lypinator 0:bb348c97df44 112 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
lypinator 0:bb348c97df44 113 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
lypinator 0:bb348c97df44 114 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
lypinator 0:bb348c97df44 115 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
lypinator 0:bb348c97df44 116 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
lypinator 0:bb348c97df44 117 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
lypinator 0:bb348c97df44 118 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
lypinator 0:bb348c97df44 119 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
lypinator 0:bb348c97df44 120 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
lypinator 0:bb348c97df44 121 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
lypinator 0:bb348c97df44 122 *
lypinator 0:bb348c97df44 123 ******************************************************************************
lypinator 0:bb348c97df44 124 */
lypinator 0:bb348c97df44 125
lypinator 0:bb348c97df44 126 /* Includes ------------------------------------------------------------------*/
lypinator 0:bb348c97df44 127 #include "stm32f4xx_hal.h"
lypinator 0:bb348c97df44 128
lypinator 0:bb348c97df44 129 /** @addtogroup STM32F4xx_HAL_Driver
lypinator 0:bb348c97df44 130 * @{
lypinator 0:bb348c97df44 131 */
lypinator 0:bb348c97df44 132
lypinator 0:bb348c97df44 133 /** @defgroup DMA2D DMA2D
lypinator 0:bb348c97df44 134 * @brief DMA2D HAL module driver
lypinator 0:bb348c97df44 135 * @{
lypinator 0:bb348c97df44 136 */
lypinator 0:bb348c97df44 137
lypinator 0:bb348c97df44 138 #ifdef HAL_DMA2D_MODULE_ENABLED
lypinator 0:bb348c97df44 139
lypinator 0:bb348c97df44 140 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
lypinator 0:bb348c97df44 141
lypinator 0:bb348c97df44 142 /* Private types -------------------------------------------------------------*/
lypinator 0:bb348c97df44 143 /* Private define ------------------------------------------------------------*/
lypinator 0:bb348c97df44 144 /** @defgroup DMA2D_Private_Constants DMA2D Private Constants
lypinator 0:bb348c97df44 145 * @{
lypinator 0:bb348c97df44 146 */
lypinator 0:bb348c97df44 147
lypinator 0:bb348c97df44 148 /** @defgroup DMA2D_TimeOut DMA2D Time Out
lypinator 0:bb348c97df44 149 * @{
lypinator 0:bb348c97df44 150 */
lypinator 0:bb348c97df44 151 #define DMA2D_TIMEOUT_ABORT 1000U /*!< 1s */
lypinator 0:bb348c97df44 152 #define DMA2D_TIMEOUT_SUSPEND 1000U /*!< 1s */
lypinator 0:bb348c97df44 153 /**
lypinator 0:bb348c97df44 154 * @}
lypinator 0:bb348c97df44 155 */
lypinator 0:bb348c97df44 156
lypinator 0:bb348c97df44 157 /** @defgroup DMA2D_Shifts DMA2D Shifts
lypinator 0:bb348c97df44 158 * @{
lypinator 0:bb348c97df44 159 */
lypinator 0:bb348c97df44 160 #define DMA2D_POSITION_FGPFCCR_CS (uint32_t)DMA2D_FGPFCCR_CS_Pos /*!< Required left shift to set foreground CLUT size */
lypinator 0:bb348c97df44 161 #define DMA2D_POSITION_BGPFCCR_CS (uint32_t)DMA2D_BGPFCCR_CS_Pos /*!< Required left shift to set background CLUT size */
lypinator 0:bb348c97df44 162
lypinator 0:bb348c97df44 163 #define DMA2D_POSITION_FGPFCCR_CCM (uint32_t)DMA2D_FGPFCCR_CCM_Pos /*!< Required left shift to set foreground CLUT color mode */
lypinator 0:bb348c97df44 164 #define DMA2D_POSITION_BGPFCCR_CCM (uint32_t)DMA2D_BGPFCCR_CCM_Pos /*!< Required left shift to set background CLUT color mode */
lypinator 0:bb348c97df44 165
lypinator 0:bb348c97df44 166 #define DMA2D_POSITION_AMTCR_DT (uint32_t)DMA2D_AMTCR_DT_Pos /*!< Required left shift to set deadtime value */
lypinator 0:bb348c97df44 167
lypinator 0:bb348c97df44 168 #define DMA2D_POSITION_FGPFCCR_AM (uint32_t)DMA2D_FGPFCCR_AM_Pos /*!< Required left shift to set foreground alpha mode */
lypinator 0:bb348c97df44 169 #define DMA2D_POSITION_BGPFCCR_AM (uint32_t)DMA2D_BGPFCCR_AM_Pos /*!< Required left shift to set background alpha mode */
lypinator 0:bb348c97df44 170
lypinator 0:bb348c97df44 171 #define DMA2D_POSITION_FGPFCCR_ALPHA (uint32_t)DMA2D_FGPFCCR_ALPHA_Pos /*!< Required left shift to set foreground alpha value */
lypinator 0:bb348c97df44 172 #define DMA2D_POSITION_BGPFCCR_ALPHA (uint32_t)DMA2D_BGPFCCR_ALPHA_Pos /*!< Required left shift to set background alpha value */
lypinator 0:bb348c97df44 173
lypinator 0:bb348c97df44 174 #define DMA2D_POSITION_NLR_PL (uint32_t)DMA2D_NLR_PL_Pos /*!< Required left shift to set pixels per lines value */
lypinator 0:bb348c97df44 175 /**
lypinator 0:bb348c97df44 176 * @}
lypinator 0:bb348c97df44 177 */
lypinator 0:bb348c97df44 178
lypinator 0:bb348c97df44 179 /**
lypinator 0:bb348c97df44 180 * @}
lypinator 0:bb348c97df44 181 */
lypinator 0:bb348c97df44 182
lypinator 0:bb348c97df44 183 /* Private variables ---------------------------------------------------------*/
lypinator 0:bb348c97df44 184 /* Private constants ---------------------------------------------------------*/
lypinator 0:bb348c97df44 185 /* Private macro -------------------------------------------------------------*/
lypinator 0:bb348c97df44 186 /* Private function prototypes -----------------------------------------------*/
lypinator 0:bb348c97df44 187 /** @addtogroup DMA2D_Private_Functions_Prototypes
lypinator 0:bb348c97df44 188 * @{
lypinator 0:bb348c97df44 189 */
lypinator 0:bb348c97df44 190 static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height);
lypinator 0:bb348c97df44 191 /**
lypinator 0:bb348c97df44 192 * @}
lypinator 0:bb348c97df44 193 */
lypinator 0:bb348c97df44 194
lypinator 0:bb348c97df44 195 /* Private functions ---------------------------------------------------------*/
lypinator 0:bb348c97df44 196 /* Exported functions --------------------------------------------------------*/
lypinator 0:bb348c97df44 197 /** @defgroup DMA2D_Exported_Functions DMA2D Exported Functions
lypinator 0:bb348c97df44 198 * @{
lypinator 0:bb348c97df44 199 */
lypinator 0:bb348c97df44 200
lypinator 0:bb348c97df44 201 /** @defgroup DMA2D_Exported_Functions_Group1 Initialization and de-initialization functions
lypinator 0:bb348c97df44 202 * @brief Initialization and Configuration functions
lypinator 0:bb348c97df44 203 *
lypinator 0:bb348c97df44 204 @verbatim
lypinator 0:bb348c97df44 205 ===============================================================================
lypinator 0:bb348c97df44 206 ##### Initialization and Configuration functions #####
lypinator 0:bb348c97df44 207 ===============================================================================
lypinator 0:bb348c97df44 208 [..] This section provides functions allowing to:
lypinator 0:bb348c97df44 209 (+) Initialize and configure the DMA2D
lypinator 0:bb348c97df44 210 (+) De-initialize the DMA2D
lypinator 0:bb348c97df44 211
lypinator 0:bb348c97df44 212 @endverbatim
lypinator 0:bb348c97df44 213 * @{
lypinator 0:bb348c97df44 214 */
lypinator 0:bb348c97df44 215
lypinator 0:bb348c97df44 216 /**
lypinator 0:bb348c97df44 217 * @brief Initialize the DMA2D according to the specified
lypinator 0:bb348c97df44 218 * parameters in the DMA2D_InitTypeDef and create the associated handle.
lypinator 0:bb348c97df44 219 * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 220 * the configuration information for the DMA2D.
lypinator 0:bb348c97df44 221 * @retval HAL status
lypinator 0:bb348c97df44 222 */
lypinator 0:bb348c97df44 223 HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d)
lypinator 0:bb348c97df44 224 {
lypinator 0:bb348c97df44 225 /* Check the DMA2D peripheral state */
lypinator 0:bb348c97df44 226 if(hdma2d == NULL)
lypinator 0:bb348c97df44 227 {
lypinator 0:bb348c97df44 228 return HAL_ERROR;
lypinator 0:bb348c97df44 229 }
lypinator 0:bb348c97df44 230
lypinator 0:bb348c97df44 231 /* Check the parameters */
lypinator 0:bb348c97df44 232 assert_param(IS_DMA2D_ALL_INSTANCE(hdma2d->Instance));
lypinator 0:bb348c97df44 233 assert_param(IS_DMA2D_MODE(hdma2d->Init.Mode));
lypinator 0:bb348c97df44 234 assert_param(IS_DMA2D_CMODE(hdma2d->Init.ColorMode));
lypinator 0:bb348c97df44 235 assert_param(IS_DMA2D_OFFSET(hdma2d->Init.OutputOffset));
lypinator 0:bb348c97df44 236
lypinator 0:bb348c97df44 237 if(hdma2d->State == HAL_DMA2D_STATE_RESET)
lypinator 0:bb348c97df44 238 {
lypinator 0:bb348c97df44 239 /* Allocate lock resource and initialize it */
lypinator 0:bb348c97df44 240 hdma2d->Lock = HAL_UNLOCKED;
lypinator 0:bb348c97df44 241 /* Init the low level hardware */
lypinator 0:bb348c97df44 242 HAL_DMA2D_MspInit(hdma2d);
lypinator 0:bb348c97df44 243 }
lypinator 0:bb348c97df44 244
lypinator 0:bb348c97df44 245 /* Change DMA2D peripheral state */
lypinator 0:bb348c97df44 246 hdma2d->State = HAL_DMA2D_STATE_BUSY;
lypinator 0:bb348c97df44 247
lypinator 0:bb348c97df44 248 /* DMA2D CR register configuration -------------------------------------------*/
lypinator 0:bb348c97df44 249 MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_MODE, hdma2d->Init.Mode);
lypinator 0:bb348c97df44 250
lypinator 0:bb348c97df44 251 /* DMA2D OPFCCR register configuration ---------------------------------------*/
lypinator 0:bb348c97df44 252 MODIFY_REG(hdma2d->Instance->OPFCCR, DMA2D_OPFCCR_CM, hdma2d->Init.ColorMode);
lypinator 0:bb348c97df44 253
lypinator 0:bb348c97df44 254 /* DMA2D OOR register configuration ------------------------------------------*/
lypinator 0:bb348c97df44 255 MODIFY_REG(hdma2d->Instance->OOR, DMA2D_OOR_LO, hdma2d->Init.OutputOffset);
lypinator 0:bb348c97df44 256
lypinator 0:bb348c97df44 257 /* Update error code */
lypinator 0:bb348c97df44 258 hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE;
lypinator 0:bb348c97df44 259
lypinator 0:bb348c97df44 260 /* Initialize the DMA2D state*/
lypinator 0:bb348c97df44 261 hdma2d->State = HAL_DMA2D_STATE_READY;
lypinator 0:bb348c97df44 262
lypinator 0:bb348c97df44 263 return HAL_OK;
lypinator 0:bb348c97df44 264 }
lypinator 0:bb348c97df44 265
lypinator 0:bb348c97df44 266 /**
lypinator 0:bb348c97df44 267 * @brief Deinitializes the DMA2D peripheral registers to their default reset
lypinator 0:bb348c97df44 268 * values.
lypinator 0:bb348c97df44 269 * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 270 * the configuration information for the DMA2D.
lypinator 0:bb348c97df44 271 * @retval None
lypinator 0:bb348c97df44 272 */
lypinator 0:bb348c97df44 273
lypinator 0:bb348c97df44 274 HAL_StatusTypeDef HAL_DMA2D_DeInit(DMA2D_HandleTypeDef *hdma2d)
lypinator 0:bb348c97df44 275 {
lypinator 0:bb348c97df44 276 /* Check the DMA2D peripheral state */
lypinator 0:bb348c97df44 277 if(hdma2d == NULL)
lypinator 0:bb348c97df44 278 {
lypinator 0:bb348c97df44 279 return HAL_ERROR;
lypinator 0:bb348c97df44 280 }
lypinator 0:bb348c97df44 281
lypinator 0:bb348c97df44 282 /* Before aborting any DMA2D transfer or CLUT loading, check
lypinator 0:bb348c97df44 283 first whether or not DMA2D clock is enabled */
lypinator 0:bb348c97df44 284 if (__HAL_RCC_DMA2D_IS_CLK_ENABLED())
lypinator 0:bb348c97df44 285 {
lypinator 0:bb348c97df44 286 /* Abort DMA2D transfer if any */
lypinator 0:bb348c97df44 287 if ((hdma2d->Instance->CR & DMA2D_CR_START) == DMA2D_CR_START)
lypinator 0:bb348c97df44 288 {
lypinator 0:bb348c97df44 289 if (HAL_DMA2D_Abort(hdma2d) != HAL_OK)
lypinator 0:bb348c97df44 290 {
lypinator 0:bb348c97df44 291 /* Issue when aborting DMA2D transfer */
lypinator 0:bb348c97df44 292 return HAL_ERROR;
lypinator 0:bb348c97df44 293 }
lypinator 0:bb348c97df44 294 }
lypinator 0:bb348c97df44 295 else
lypinator 0:bb348c97df44 296 {
lypinator 0:bb348c97df44 297 /* Abort background CLUT loading if any */
lypinator 0:bb348c97df44 298 if ((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START)
lypinator 0:bb348c97df44 299 {
lypinator 0:bb348c97df44 300 if (HAL_DMA2D_CLUTLoading_Abort(hdma2d, 0U) != HAL_OK)
lypinator 0:bb348c97df44 301 {
lypinator 0:bb348c97df44 302 /* Issue when aborting background CLUT loading */
lypinator 0:bb348c97df44 303 return HAL_ERROR;
lypinator 0:bb348c97df44 304 }
lypinator 0:bb348c97df44 305 }
lypinator 0:bb348c97df44 306 else
lypinator 0:bb348c97df44 307 {
lypinator 0:bb348c97df44 308 /* Abort foreground CLUT loading if any */
lypinator 0:bb348c97df44 309 if ((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) == DMA2D_FGPFCCR_START)
lypinator 0:bb348c97df44 310 {
lypinator 0:bb348c97df44 311 if (HAL_DMA2D_CLUTLoading_Abort(hdma2d, 1U) != HAL_OK)
lypinator 0:bb348c97df44 312 {
lypinator 0:bb348c97df44 313 /* Issue when aborting foreground CLUT loading */
lypinator 0:bb348c97df44 314 return HAL_ERROR;
lypinator 0:bb348c97df44 315 }
lypinator 0:bb348c97df44 316 }
lypinator 0:bb348c97df44 317 }
lypinator 0:bb348c97df44 318 }
lypinator 0:bb348c97df44 319 }
lypinator 0:bb348c97df44 320
lypinator 0:bb348c97df44 321 /* Carry on with de-initialization of low level hardware */
lypinator 0:bb348c97df44 322 HAL_DMA2D_MspDeInit(hdma2d);
lypinator 0:bb348c97df44 323
lypinator 0:bb348c97df44 324 /* Reset DMA2D control registers*/
lypinator 0:bb348c97df44 325 hdma2d->Instance->CR = 0U;
lypinator 0:bb348c97df44 326 hdma2d->Instance->FGOR = 0U;
lypinator 0:bb348c97df44 327 hdma2d->Instance->BGOR = 0U;
lypinator 0:bb348c97df44 328 hdma2d->Instance->FGPFCCR = 0U;
lypinator 0:bb348c97df44 329 hdma2d->Instance->BGPFCCR = 0U;
lypinator 0:bb348c97df44 330 hdma2d->Instance->OPFCCR = 0U;
lypinator 0:bb348c97df44 331
lypinator 0:bb348c97df44 332 /* Update error code */
lypinator 0:bb348c97df44 333 hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE;
lypinator 0:bb348c97df44 334
lypinator 0:bb348c97df44 335 /* Initialize the DMA2D state*/
lypinator 0:bb348c97df44 336 hdma2d->State = HAL_DMA2D_STATE_RESET;
lypinator 0:bb348c97df44 337
lypinator 0:bb348c97df44 338 /* Release Lock */
lypinator 0:bb348c97df44 339 __HAL_UNLOCK(hdma2d);
lypinator 0:bb348c97df44 340
lypinator 0:bb348c97df44 341 return HAL_OK;
lypinator 0:bb348c97df44 342 }
lypinator 0:bb348c97df44 343
lypinator 0:bb348c97df44 344 /**
lypinator 0:bb348c97df44 345 * @brief Initializes the DMA2D MSP.
lypinator 0:bb348c97df44 346 * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 347 * the configuration information for the DMA2D.
lypinator 0:bb348c97df44 348 * @retval None
lypinator 0:bb348c97df44 349 */
lypinator 0:bb348c97df44 350 __weak void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d)
lypinator 0:bb348c97df44 351 {
lypinator 0:bb348c97df44 352 /* Prevent unused argument(s) compilation warning */
lypinator 0:bb348c97df44 353 UNUSED(hdma2d);
lypinator 0:bb348c97df44 354
lypinator 0:bb348c97df44 355 /* NOTE : This function should not be modified; when the callback is needed,
lypinator 0:bb348c97df44 356 the HAL_DMA2D_MspInit can be implemented in the user file.
lypinator 0:bb348c97df44 357 */
lypinator 0:bb348c97df44 358 }
lypinator 0:bb348c97df44 359
lypinator 0:bb348c97df44 360 /**
lypinator 0:bb348c97df44 361 * @brief DeInitializes the DMA2D MSP.
lypinator 0:bb348c97df44 362 * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 363 * the configuration information for the DMA2D.
lypinator 0:bb348c97df44 364 * @retval None
lypinator 0:bb348c97df44 365 */
lypinator 0:bb348c97df44 366 __weak void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d)
lypinator 0:bb348c97df44 367 {
lypinator 0:bb348c97df44 368 /* Prevent unused argument(s) compilation warning */
lypinator 0:bb348c97df44 369 UNUSED(hdma2d);
lypinator 0:bb348c97df44 370
lypinator 0:bb348c97df44 371 /* NOTE : This function should not be modified; when the callback is needed,
lypinator 0:bb348c97df44 372 the HAL_DMA2D_MspDeInit can be implemented in the user file.
lypinator 0:bb348c97df44 373 */
lypinator 0:bb348c97df44 374 }
lypinator 0:bb348c97df44 375
lypinator 0:bb348c97df44 376 /**
lypinator 0:bb348c97df44 377 * @}
lypinator 0:bb348c97df44 378 */
lypinator 0:bb348c97df44 379
lypinator 0:bb348c97df44 380 /** @defgroup DMA2D_Exported_Functions_Group2 IO operation functions
lypinator 0:bb348c97df44 381 * @brief IO operation functions
lypinator 0:bb348c97df44 382 *
lypinator 0:bb348c97df44 383 @verbatim
lypinator 0:bb348c97df44 384 ===============================================================================
lypinator 0:bb348c97df44 385 ##### IO operation functions #####
lypinator 0:bb348c97df44 386 ===============================================================================
lypinator 0:bb348c97df44 387 [..] This section provides functions allowing to:
lypinator 0:bb348c97df44 388 (+) Configure the pdata, destination address and data size then
lypinator 0:bb348c97df44 389 start the DMA2D transfer.
lypinator 0:bb348c97df44 390 (+) Configure the source for foreground and background, destination address
lypinator 0:bb348c97df44 391 and data size then start a MultiBuffer DMA2D transfer.
lypinator 0:bb348c97df44 392 (+) Configure the pdata, destination address and data size then
lypinator 0:bb348c97df44 393 start the DMA2D transfer with interrupt.
lypinator 0:bb348c97df44 394 (+) Configure the source for foreground and background, destination address
lypinator 0:bb348c97df44 395 and data size then start a MultiBuffer DMA2D transfer with interrupt.
lypinator 0:bb348c97df44 396 (+) Abort DMA2D transfer.
lypinator 0:bb348c97df44 397 (+) Suspend DMA2D transfer.
lypinator 0:bb348c97df44 398 (+) Resume DMA2D transfer.
lypinator 0:bb348c97df44 399 (+) Enable CLUT transfer.
lypinator 0:bb348c97df44 400 (+) Configure CLUT loading then start transfer in polling mode.
lypinator 0:bb348c97df44 401 (+) Configure CLUT loading then start transfer in interrupt mode.
lypinator 0:bb348c97df44 402 (+) Abort DMA2D CLUT loading.
lypinator 0:bb348c97df44 403 (+) Suspend DMA2D CLUT loading.
lypinator 0:bb348c97df44 404 (+) Resume DMA2D CLUT loading.
lypinator 0:bb348c97df44 405 (+) Poll for transfer complete.
lypinator 0:bb348c97df44 406 (+) handle DMA2D interrupt request.
lypinator 0:bb348c97df44 407 (+) Transfer watermark callback.
lypinator 0:bb348c97df44 408 (+) CLUT Transfer Complete callback.
lypinator 0:bb348c97df44 409
lypinator 0:bb348c97df44 410 @endverbatim
lypinator 0:bb348c97df44 411 * @{
lypinator 0:bb348c97df44 412 */
lypinator 0:bb348c97df44 413
lypinator 0:bb348c97df44 414 /**
lypinator 0:bb348c97df44 415 * @brief Start the DMA2D Transfer.
lypinator 0:bb348c97df44 416 * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 417 * the configuration information for the DMA2D.
lypinator 0:bb348c97df44 418 * @param pdata Configure the source memory Buffer address if
lypinator 0:bb348c97df44 419 * Memory-to-Memory or Memory-to-Memory with pixel format
lypinator 0:bb348c97df44 420 * conversion mode is selected, or configure
lypinator 0:bb348c97df44 421 * the color value if Register-to-Memory mode is selected.
lypinator 0:bb348c97df44 422 * @param DstAddress The destination memory Buffer address.
lypinator 0:bb348c97df44 423 * @param Width The width of data to be transferred from source to destination (expressed in number of pixels per line).
lypinator 0:bb348c97df44 424 * @param Height The height of data to be transferred from source to destination (expressed in number of lines).
lypinator 0:bb348c97df44 425 * @retval HAL status
lypinator 0:bb348c97df44 426 */
lypinator 0:bb348c97df44 427 HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
lypinator 0:bb348c97df44 428 {
lypinator 0:bb348c97df44 429 /* Check the parameters */
lypinator 0:bb348c97df44 430 assert_param(IS_DMA2D_LINE(Height));
lypinator 0:bb348c97df44 431 assert_param(IS_DMA2D_PIXEL(Width));
lypinator 0:bb348c97df44 432
lypinator 0:bb348c97df44 433 /* Process locked */
lypinator 0:bb348c97df44 434 __HAL_LOCK(hdma2d);
lypinator 0:bb348c97df44 435
lypinator 0:bb348c97df44 436 /* Change DMA2D peripheral state */
lypinator 0:bb348c97df44 437 hdma2d->State = HAL_DMA2D_STATE_BUSY;
lypinator 0:bb348c97df44 438
lypinator 0:bb348c97df44 439 /* Configure the source, destination address and the data size */
lypinator 0:bb348c97df44 440 DMA2D_SetConfig(hdma2d, pdata, DstAddress, Width, Height);
lypinator 0:bb348c97df44 441
lypinator 0:bb348c97df44 442 /* Enable the Peripheral */
lypinator 0:bb348c97df44 443 __HAL_DMA2D_ENABLE(hdma2d);
lypinator 0:bb348c97df44 444
lypinator 0:bb348c97df44 445 return HAL_OK;
lypinator 0:bb348c97df44 446 }
lypinator 0:bb348c97df44 447
lypinator 0:bb348c97df44 448 /**
lypinator 0:bb348c97df44 449 * @brief Start the DMA2D Transfer with interrupt enabled.
lypinator 0:bb348c97df44 450 * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 451 * the configuration information for the DMA2D.
lypinator 0:bb348c97df44 452 * @param pdata Configure the source memory Buffer address if
lypinator 0:bb348c97df44 453 * the Memory-to-Memory or Memory-to-Memory with pixel format
lypinator 0:bb348c97df44 454 * conversion mode is selected, or configure
lypinator 0:bb348c97df44 455 * the color value if Register-to-Memory mode is selected.
lypinator 0:bb348c97df44 456 * @param DstAddress The destination memory Buffer address.
lypinator 0:bb348c97df44 457 * @param Width The width of data to be transferred from source to destination (expressed in number of pixels per line).
lypinator 0:bb348c97df44 458 * @param Height The height of data to be transferred from source to destination (expressed in number of lines).
lypinator 0:bb348c97df44 459 * @retval HAL status
lypinator 0:bb348c97df44 460 */
lypinator 0:bb348c97df44 461 HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
lypinator 0:bb348c97df44 462 {
lypinator 0:bb348c97df44 463 /* Check the parameters */
lypinator 0:bb348c97df44 464 assert_param(IS_DMA2D_LINE(Height));
lypinator 0:bb348c97df44 465 assert_param(IS_DMA2D_PIXEL(Width));
lypinator 0:bb348c97df44 466
lypinator 0:bb348c97df44 467 /* Process locked */
lypinator 0:bb348c97df44 468 __HAL_LOCK(hdma2d);
lypinator 0:bb348c97df44 469
lypinator 0:bb348c97df44 470 /* Change DMA2D peripheral state */
lypinator 0:bb348c97df44 471 hdma2d->State = HAL_DMA2D_STATE_BUSY;
lypinator 0:bb348c97df44 472
lypinator 0:bb348c97df44 473 /* Configure the source, destination address and the data size */
lypinator 0:bb348c97df44 474 DMA2D_SetConfig(hdma2d, pdata, DstAddress, Width, Height);
lypinator 0:bb348c97df44 475
lypinator 0:bb348c97df44 476 /* Enable the transfer complete, transfer error and configuration error interrupts */
lypinator 0:bb348c97df44 477 __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC|DMA2D_IT_TE|DMA2D_IT_CE);
lypinator 0:bb348c97df44 478
lypinator 0:bb348c97df44 479 /* Enable the Peripheral */
lypinator 0:bb348c97df44 480 __HAL_DMA2D_ENABLE(hdma2d);
lypinator 0:bb348c97df44 481
lypinator 0:bb348c97df44 482 return HAL_OK;
lypinator 0:bb348c97df44 483 }
lypinator 0:bb348c97df44 484
lypinator 0:bb348c97df44 485 /**
lypinator 0:bb348c97df44 486 * @brief Start the multi-source DMA2D Transfer.
lypinator 0:bb348c97df44 487 * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 488 * the configuration information for the DMA2D.
lypinator 0:bb348c97df44 489 * @param SrcAddress1 The source memory Buffer address for the foreground layer.
lypinator 0:bb348c97df44 490 * @param SrcAddress2 The source memory Buffer address for the background layer.
lypinator 0:bb348c97df44 491 * @param DstAddress The destination memory Buffer address.
lypinator 0:bb348c97df44 492 * @param Width The width of data to be transferred from source to destination (expressed in number of pixels per line).
lypinator 0:bb348c97df44 493 * @param Height The height of data to be transferred from source to destination (expressed in number of lines).
lypinator 0:bb348c97df44 494 * @retval HAL status
lypinator 0:bb348c97df44 495 */
lypinator 0:bb348c97df44 496 HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height)
lypinator 0:bb348c97df44 497 {
lypinator 0:bb348c97df44 498 /* Check the parameters */
lypinator 0:bb348c97df44 499 assert_param(IS_DMA2D_LINE(Height));
lypinator 0:bb348c97df44 500 assert_param(IS_DMA2D_PIXEL(Width));
lypinator 0:bb348c97df44 501
lypinator 0:bb348c97df44 502 /* Process locked */
lypinator 0:bb348c97df44 503 __HAL_LOCK(hdma2d);
lypinator 0:bb348c97df44 504
lypinator 0:bb348c97df44 505 /* Change DMA2D peripheral state */
lypinator 0:bb348c97df44 506 hdma2d->State = HAL_DMA2D_STATE_BUSY;
lypinator 0:bb348c97df44 507
lypinator 0:bb348c97df44 508 /* Configure DMA2D Stream source2 address */
lypinator 0:bb348c97df44 509 WRITE_REG(hdma2d->Instance->BGMAR, SrcAddress2);
lypinator 0:bb348c97df44 510
lypinator 0:bb348c97df44 511 /* Configure the source, destination address and the data size */
lypinator 0:bb348c97df44 512 DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height);
lypinator 0:bb348c97df44 513
lypinator 0:bb348c97df44 514 /* Enable the Peripheral */
lypinator 0:bb348c97df44 515 __HAL_DMA2D_ENABLE(hdma2d);
lypinator 0:bb348c97df44 516
lypinator 0:bb348c97df44 517 return HAL_OK;
lypinator 0:bb348c97df44 518 }
lypinator 0:bb348c97df44 519
lypinator 0:bb348c97df44 520 /**
lypinator 0:bb348c97df44 521 * @brief Start the multi-source DMA2D Transfer with interrupt enabled.
lypinator 0:bb348c97df44 522 * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 523 * the configuration information for the DMA2D.
lypinator 0:bb348c97df44 524 * @param SrcAddress1 The source memory Buffer address for the foreground layer.
lypinator 0:bb348c97df44 525 * @param SrcAddress2 The source memory Buffer address for the background layer.
lypinator 0:bb348c97df44 526 * @param DstAddress The destination memory Buffer address.
lypinator 0:bb348c97df44 527 * @param Width The width of data to be transferred from source to destination (expressed in number of pixels per line).
lypinator 0:bb348c97df44 528 * @param Height The height of data to be transferred from source to destination (expressed in number of lines).
lypinator 0:bb348c97df44 529 * @retval HAL status
lypinator 0:bb348c97df44 530 */
lypinator 0:bb348c97df44 531 HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height)
lypinator 0:bb348c97df44 532 {
lypinator 0:bb348c97df44 533 /* Check the parameters */
lypinator 0:bb348c97df44 534 assert_param(IS_DMA2D_LINE(Height));
lypinator 0:bb348c97df44 535 assert_param(IS_DMA2D_PIXEL(Width));
lypinator 0:bb348c97df44 536
lypinator 0:bb348c97df44 537 /* Process locked */
lypinator 0:bb348c97df44 538 __HAL_LOCK(hdma2d);
lypinator 0:bb348c97df44 539
lypinator 0:bb348c97df44 540 /* Change DMA2D peripheral state */
lypinator 0:bb348c97df44 541 hdma2d->State = HAL_DMA2D_STATE_BUSY;
lypinator 0:bb348c97df44 542
lypinator 0:bb348c97df44 543 /* Configure DMA2D Stream source2 address */
lypinator 0:bb348c97df44 544 WRITE_REG(hdma2d->Instance->BGMAR, SrcAddress2);
lypinator 0:bb348c97df44 545
lypinator 0:bb348c97df44 546 /* Configure the source, destination address and the data size */
lypinator 0:bb348c97df44 547 DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height);
lypinator 0:bb348c97df44 548
lypinator 0:bb348c97df44 549 /* Enable the transfer complete, transfer error and configuration error interrupts */
lypinator 0:bb348c97df44 550 __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC|DMA2D_IT_TE|DMA2D_IT_CE);
lypinator 0:bb348c97df44 551
lypinator 0:bb348c97df44 552 /* Enable the Peripheral */
lypinator 0:bb348c97df44 553 __HAL_DMA2D_ENABLE(hdma2d);
lypinator 0:bb348c97df44 554
lypinator 0:bb348c97df44 555 return HAL_OK;
lypinator 0:bb348c97df44 556 }
lypinator 0:bb348c97df44 557
lypinator 0:bb348c97df44 558 /**
lypinator 0:bb348c97df44 559 * @brief Abort the DMA2D Transfer.
lypinator 0:bb348c97df44 560 * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 561 * the configuration information for the DMA2D.
lypinator 0:bb348c97df44 562 * @retval HAL status
lypinator 0:bb348c97df44 563 */
lypinator 0:bb348c97df44 564 HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d)
lypinator 0:bb348c97df44 565 {
lypinator 0:bb348c97df44 566 uint32_t tickstart = 0U;
lypinator 0:bb348c97df44 567
lypinator 0:bb348c97df44 568 /* Abort the DMA2D transfer */
lypinator 0:bb348c97df44 569 /* START bit is reset to make sure not to set it again, in the event the HW clears it
lypinator 0:bb348c97df44 570 between the register read and the register write by the CPU (writing 0 has no
lypinator 0:bb348c97df44 571 effect on START bitvalue) */
lypinator 0:bb348c97df44 572 MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_ABORT|DMA2D_CR_START, DMA2D_CR_ABORT);
lypinator 0:bb348c97df44 573
lypinator 0:bb348c97df44 574 /* Get tick */
lypinator 0:bb348c97df44 575 tickstart = HAL_GetTick();
lypinator 0:bb348c97df44 576
lypinator 0:bb348c97df44 577 /* Check if the DMA2D is effectively disabled */
lypinator 0:bb348c97df44 578 while((hdma2d->Instance->CR & DMA2D_CR_START) != RESET)
lypinator 0:bb348c97df44 579 {
lypinator 0:bb348c97df44 580 if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_ABORT)
lypinator 0:bb348c97df44 581 {
lypinator 0:bb348c97df44 582 /* Update error code */
lypinator 0:bb348c97df44 583 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
lypinator 0:bb348c97df44 584
lypinator 0:bb348c97df44 585 /* Change the DMA2D state */
lypinator 0:bb348c97df44 586 hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
lypinator 0:bb348c97df44 587
lypinator 0:bb348c97df44 588 /* Process Unlocked */
lypinator 0:bb348c97df44 589 __HAL_UNLOCK(hdma2d);
lypinator 0:bb348c97df44 590
lypinator 0:bb348c97df44 591 return HAL_TIMEOUT;
lypinator 0:bb348c97df44 592 }
lypinator 0:bb348c97df44 593 }
lypinator 0:bb348c97df44 594
lypinator 0:bb348c97df44 595 /* Disable the Transfer Complete, Transfer Error and Configuration Error interrupts */
lypinator 0:bb348c97df44 596 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TC|DMA2D_IT_TE|DMA2D_IT_CE);
lypinator 0:bb348c97df44 597
lypinator 0:bb348c97df44 598 /* Change the DMA2D state*/
lypinator 0:bb348c97df44 599 hdma2d->State = HAL_DMA2D_STATE_READY;
lypinator 0:bb348c97df44 600
lypinator 0:bb348c97df44 601 /* Process Unlocked */
lypinator 0:bb348c97df44 602 __HAL_UNLOCK(hdma2d);
lypinator 0:bb348c97df44 603
lypinator 0:bb348c97df44 604 return HAL_OK;
lypinator 0:bb348c97df44 605 }
lypinator 0:bb348c97df44 606
lypinator 0:bb348c97df44 607 /**
lypinator 0:bb348c97df44 608 * @brief Suspend the DMA2D Transfer.
lypinator 0:bb348c97df44 609 * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 610 * the configuration information for the DMA2D.
lypinator 0:bb348c97df44 611 * @retval HAL status
lypinator 0:bb348c97df44 612 */
lypinator 0:bb348c97df44 613 HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d)
lypinator 0:bb348c97df44 614 {
lypinator 0:bb348c97df44 615 uint32_t tickstart = 0U;
lypinator 0:bb348c97df44 616
lypinator 0:bb348c97df44 617 /* Suspend the DMA2D transfer */
lypinator 0:bb348c97df44 618 /* START bit is reset to make sure not to set it again, in the event the HW clears it
lypinator 0:bb348c97df44 619 between the register read and the register write by the CPU (writing 0 has no
lypinator 0:bb348c97df44 620 effect on START bitvalue) */
lypinator 0:bb348c97df44 621 MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_SUSP|DMA2D_CR_START, DMA2D_CR_SUSP);
lypinator 0:bb348c97df44 622
lypinator 0:bb348c97df44 623 /* Get tick */
lypinator 0:bb348c97df44 624 tickstart = HAL_GetTick();
lypinator 0:bb348c97df44 625
lypinator 0:bb348c97df44 626 /* Check if the DMA2D is effectively suspended */
lypinator 0:bb348c97df44 627 while (((hdma2d->Instance->CR & DMA2D_CR_SUSP) != DMA2D_CR_SUSP) \
lypinator 0:bb348c97df44 628 && ((hdma2d->Instance->CR & DMA2D_CR_START) == DMA2D_CR_START))
lypinator 0:bb348c97df44 629 {
lypinator 0:bb348c97df44 630 if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_SUSPEND)
lypinator 0:bb348c97df44 631 {
lypinator 0:bb348c97df44 632 /* Update error code */
lypinator 0:bb348c97df44 633 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
lypinator 0:bb348c97df44 634
lypinator 0:bb348c97df44 635 /* Change the DMA2D state */
lypinator 0:bb348c97df44 636 hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
lypinator 0:bb348c97df44 637
lypinator 0:bb348c97df44 638 return HAL_TIMEOUT;
lypinator 0:bb348c97df44 639 }
lypinator 0:bb348c97df44 640 }
lypinator 0:bb348c97df44 641
lypinator 0:bb348c97df44 642 /* Check whether or not a transfer is actually suspended and change the DMA2D state accordingly */
lypinator 0:bb348c97df44 643 if ((hdma2d->Instance->CR & DMA2D_CR_START) != RESET)
lypinator 0:bb348c97df44 644 {
lypinator 0:bb348c97df44 645 hdma2d->State = HAL_DMA2D_STATE_SUSPEND;
lypinator 0:bb348c97df44 646 }
lypinator 0:bb348c97df44 647 else
lypinator 0:bb348c97df44 648 {
lypinator 0:bb348c97df44 649 /* Make sure SUSP bit is cleared since it is meaningless
lypinator 0:bb348c97df44 650 when no tranfer is on-going */
lypinator 0:bb348c97df44 651 CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
lypinator 0:bb348c97df44 652 }
lypinator 0:bb348c97df44 653
lypinator 0:bb348c97df44 654 return HAL_OK;
lypinator 0:bb348c97df44 655 }
lypinator 0:bb348c97df44 656
lypinator 0:bb348c97df44 657 /**
lypinator 0:bb348c97df44 658 * @brief Resume the DMA2D Transfer.
lypinator 0:bb348c97df44 659 * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 660 * the configuration information for the DMA2D.
lypinator 0:bb348c97df44 661 * @retval HAL status
lypinator 0:bb348c97df44 662 */
lypinator 0:bb348c97df44 663 HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d)
lypinator 0:bb348c97df44 664 {
lypinator 0:bb348c97df44 665 /* Check the SUSP and START bits */
lypinator 0:bb348c97df44 666 if((hdma2d->Instance->CR & (DMA2D_CR_SUSP | DMA2D_CR_START)) == (DMA2D_CR_SUSP | DMA2D_CR_START))
lypinator 0:bb348c97df44 667 {
lypinator 0:bb348c97df44 668 /* Ongoing transfer is suspended: change the DMA2D state before resuming */
lypinator 0:bb348c97df44 669 hdma2d->State = HAL_DMA2D_STATE_BUSY;
lypinator 0:bb348c97df44 670 }
lypinator 0:bb348c97df44 671
lypinator 0:bb348c97df44 672 /* Resume the DMA2D transfer */
lypinator 0:bb348c97df44 673 /* START bit is reset to make sure not to set it again, in the event the HW clears it
lypinator 0:bb348c97df44 674 between the register read and the register write by the CPU (writing 0 has no
lypinator 0:bb348c97df44 675 effect on START bitvalue) */
lypinator 0:bb348c97df44 676 CLEAR_BIT(hdma2d->Instance->CR, (DMA2D_CR_SUSP|DMA2D_CR_START));
lypinator 0:bb348c97df44 677
lypinator 0:bb348c97df44 678 return HAL_OK;
lypinator 0:bb348c97df44 679 }
lypinator 0:bb348c97df44 680
lypinator 0:bb348c97df44 681 /**
lypinator 0:bb348c97df44 682 * @brief Enable the DMA2D CLUT Transfer.
lypinator 0:bb348c97df44 683 * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 684 * the configuration information for the DMA2D.
lypinator 0:bb348c97df44 685 * @param LayerIdx DMA2D Layer index.
lypinator 0:bb348c97df44 686 * This parameter can be one of the following values:
lypinator 0:bb348c97df44 687 * 0(background) / 1(foreground)
lypinator 0:bb348c97df44 688 * @retval HAL status
lypinator 0:bb348c97df44 689 */
lypinator 0:bb348c97df44 690 HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
lypinator 0:bb348c97df44 691 {
lypinator 0:bb348c97df44 692 /* Check the parameters */
lypinator 0:bb348c97df44 693 assert_param(IS_DMA2D_LAYER(LayerIdx));
lypinator 0:bb348c97df44 694
lypinator 0:bb348c97df44 695 /* Process locked */
lypinator 0:bb348c97df44 696 __HAL_LOCK(hdma2d);
lypinator 0:bb348c97df44 697
lypinator 0:bb348c97df44 698 /* Change DMA2D peripheral state */
lypinator 0:bb348c97df44 699 hdma2d->State = HAL_DMA2D_STATE_BUSY;
lypinator 0:bb348c97df44 700
lypinator 0:bb348c97df44 701 if(LayerIdx == 0U)
lypinator 0:bb348c97df44 702 {
lypinator 0:bb348c97df44 703 /* Enable the background CLUT loading */
lypinator 0:bb348c97df44 704 SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
lypinator 0:bb348c97df44 705 }
lypinator 0:bb348c97df44 706 else
lypinator 0:bb348c97df44 707 {
lypinator 0:bb348c97df44 708 /* Enable the foreground CLUT loading */
lypinator 0:bb348c97df44 709 SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
lypinator 0:bb348c97df44 710 }
lypinator 0:bb348c97df44 711
lypinator 0:bb348c97df44 712 return HAL_OK;
lypinator 0:bb348c97df44 713 }
lypinator 0:bb348c97df44 714
lypinator 0:bb348c97df44 715 /**
lypinator 0:bb348c97df44 716 * @brief Start DMA2D CLUT Loading.
lypinator 0:bb348c97df44 717 * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 718 * the configuration information for the DMA2D.
lypinator 0:bb348c97df44 719 * @param CLUTCfg Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
lypinator 0:bb348c97df44 720 * the configuration information for the color look up table.
lypinator 0:bb348c97df44 721 * @param LayerIdx DMA2D Layer index.
lypinator 0:bb348c97df44 722 * This parameter can be one of the following values:
lypinator 0:bb348c97df44 723 * 0(background) / 1(foreground)
lypinator 0:bb348c97df44 724 * @note Invoking this API is similar to calling HAL_DMA2D_ConfigCLUT() then HAL_DMA2D_EnableCLUT().
lypinator 0:bb348c97df44 725 * @retval HAL status
lypinator 0:bb348c97df44 726 */
lypinator 0:bb348c97df44 727 HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
lypinator 0:bb348c97df44 728 {
lypinator 0:bb348c97df44 729 /* Check the parameters */
lypinator 0:bb348c97df44 730 assert_param(IS_DMA2D_LAYER(LayerIdx));
lypinator 0:bb348c97df44 731 assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode));
lypinator 0:bb348c97df44 732 assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size));
lypinator 0:bb348c97df44 733
lypinator 0:bb348c97df44 734 /* Process locked */
lypinator 0:bb348c97df44 735 __HAL_LOCK(hdma2d);
lypinator 0:bb348c97df44 736
lypinator 0:bb348c97df44 737 /* Change DMA2D peripheral state */
lypinator 0:bb348c97df44 738 hdma2d->State = HAL_DMA2D_STATE_BUSY;
lypinator 0:bb348c97df44 739
lypinator 0:bb348c97df44 740 /* Configure the CLUT of the background DMA2D layer */
lypinator 0:bb348c97df44 741 if(LayerIdx == 0U)
lypinator 0:bb348c97df44 742 {
lypinator 0:bb348c97df44 743 /* Write background CLUT memory address */
lypinator 0:bb348c97df44 744 WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);
lypinator 0:bb348c97df44 745
lypinator 0:bb348c97df44 746 /* Write background CLUT size and CLUT color mode */
lypinator 0:bb348c97df44 747 MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
lypinator 0:bb348c97df44 748 ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_BGPFCCR_CCM)));
lypinator 0:bb348c97df44 749
lypinator 0:bb348c97df44 750 /* Enable the CLUT loading for the background */
lypinator 0:bb348c97df44 751 SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
lypinator 0:bb348c97df44 752 }
lypinator 0:bb348c97df44 753 /* Configure the CLUT of the foreground DMA2D layer */
lypinator 0:bb348c97df44 754 else
lypinator 0:bb348c97df44 755 {
lypinator 0:bb348c97df44 756 /* Write foreground CLUT memory address */
lypinator 0:bb348c97df44 757 WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT);
lypinator 0:bb348c97df44 758
lypinator 0:bb348c97df44 759 /* Write foreground CLUT size and CLUT color mode */
lypinator 0:bb348c97df44 760 MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
lypinator 0:bb348c97df44 761 ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_FGPFCCR_CCM)));
lypinator 0:bb348c97df44 762
lypinator 0:bb348c97df44 763 /* Enable the CLUT loading for the foreground */
lypinator 0:bb348c97df44 764 SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
lypinator 0:bb348c97df44 765 }
lypinator 0:bb348c97df44 766
lypinator 0:bb348c97df44 767 return HAL_OK;
lypinator 0:bb348c97df44 768 }
lypinator 0:bb348c97df44 769
lypinator 0:bb348c97df44 770 /**
lypinator 0:bb348c97df44 771 * @brief Start DMA2D CLUT Loading with interrupt enabled.
lypinator 0:bb348c97df44 772 * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 773 * the configuration information for the DMA2D.
lypinator 0:bb348c97df44 774 * @param CLUTCfg Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
lypinator 0:bb348c97df44 775 * the configuration information for the color look up table.
lypinator 0:bb348c97df44 776 * @param LayerIdx DMA2D Layer index.
lypinator 0:bb348c97df44 777 * This parameter can be one of the following values:
lypinator 0:bb348c97df44 778 * 0(background) / 1(foreground)
lypinator 0:bb348c97df44 779 * @retval HAL status
lypinator 0:bb348c97df44 780 */
lypinator 0:bb348c97df44 781 HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
lypinator 0:bb348c97df44 782 {
lypinator 0:bb348c97df44 783 /* Check the parameters */
lypinator 0:bb348c97df44 784 assert_param(IS_DMA2D_LAYER(LayerIdx));
lypinator 0:bb348c97df44 785 assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode));
lypinator 0:bb348c97df44 786 assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size));
lypinator 0:bb348c97df44 787
lypinator 0:bb348c97df44 788 /* Process locked */
lypinator 0:bb348c97df44 789 __HAL_LOCK(hdma2d);
lypinator 0:bb348c97df44 790
lypinator 0:bb348c97df44 791 /* Change DMA2D peripheral state */
lypinator 0:bb348c97df44 792 hdma2d->State = HAL_DMA2D_STATE_BUSY;
lypinator 0:bb348c97df44 793
lypinator 0:bb348c97df44 794 /* Configure the CLUT of the background DMA2D layer */
lypinator 0:bb348c97df44 795 if(LayerIdx == 0U)
lypinator 0:bb348c97df44 796 {
lypinator 0:bb348c97df44 797 /* Write background CLUT memory address */
lypinator 0:bb348c97df44 798 WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);
lypinator 0:bb348c97df44 799
lypinator 0:bb348c97df44 800 /* Write background CLUT size and CLUT color mode */
lypinator 0:bb348c97df44 801 MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
lypinator 0:bb348c97df44 802 ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_BGPFCCR_CCM)));
lypinator 0:bb348c97df44 803
lypinator 0:bb348c97df44 804 /* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */
lypinator 0:bb348c97df44 805 __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE);
lypinator 0:bb348c97df44 806
lypinator 0:bb348c97df44 807 /* Enable the CLUT loading for the background */
lypinator 0:bb348c97df44 808 SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
lypinator 0:bb348c97df44 809 }
lypinator 0:bb348c97df44 810 /* Configure the CLUT of the foreground DMA2D layer */
lypinator 0:bb348c97df44 811 else
lypinator 0:bb348c97df44 812 {
lypinator 0:bb348c97df44 813 /* Write foreground CLUT memory address */
lypinator 0:bb348c97df44 814 WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT);
lypinator 0:bb348c97df44 815
lypinator 0:bb348c97df44 816 /* Write foreground CLUT size and CLUT color mode */
lypinator 0:bb348c97df44 817 MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
lypinator 0:bb348c97df44 818 ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_FGPFCCR_CCM)));
lypinator 0:bb348c97df44 819
lypinator 0:bb348c97df44 820 /* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */
lypinator 0:bb348c97df44 821 __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE);
lypinator 0:bb348c97df44 822
lypinator 0:bb348c97df44 823 /* Enable the CLUT loading for the foreground */
lypinator 0:bb348c97df44 824 SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
lypinator 0:bb348c97df44 825 }
lypinator 0:bb348c97df44 826
lypinator 0:bb348c97df44 827 return HAL_OK;
lypinator 0:bb348c97df44 828 }
lypinator 0:bb348c97df44 829
lypinator 0:bb348c97df44 830 /**
lypinator 0:bb348c97df44 831 * @brief Abort the DMA2D CLUT loading.
lypinator 0:bb348c97df44 832 * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 833 * the configuration information for the DMA2D.
lypinator 0:bb348c97df44 834 * @param LayerIdx DMA2D Layer index.
lypinator 0:bb348c97df44 835 * This parameter can be one of the following values:
lypinator 0:bb348c97df44 836 * 0(background) / 1(foreground)
lypinator 0:bb348c97df44 837 * @retval HAL status
lypinator 0:bb348c97df44 838 */
lypinator 0:bb348c97df44 839 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
lypinator 0:bb348c97df44 840 {
lypinator 0:bb348c97df44 841 uint32_t tickstart = 0U;
lypinator 0:bb348c97df44 842 __IO uint32_t * reg = &(hdma2d->Instance->BGPFCCR); /* by default, point at background register */
lypinator 0:bb348c97df44 843
lypinator 0:bb348c97df44 844 /* Abort the CLUT loading */
lypinator 0:bb348c97df44 845 SET_BIT(hdma2d->Instance->CR, DMA2D_CR_ABORT);
lypinator 0:bb348c97df44 846
lypinator 0:bb348c97df44 847 /* If foreground CLUT loading is considered, update local variables */
lypinator 0:bb348c97df44 848 if(LayerIdx == 1)
lypinator 0:bb348c97df44 849 {
lypinator 0:bb348c97df44 850 reg = &(hdma2d->Instance->FGPFCCR);
lypinator 0:bb348c97df44 851 }
lypinator 0:bb348c97df44 852
lypinator 0:bb348c97df44 853 /* Get tick */
lypinator 0:bb348c97df44 854 tickstart = HAL_GetTick();
lypinator 0:bb348c97df44 855
lypinator 0:bb348c97df44 856 /* Check if the CLUT loading is aborted */
lypinator 0:bb348c97df44 857 while((*reg & DMA2D_BGPFCCR_START) != RESET)
lypinator 0:bb348c97df44 858 {
lypinator 0:bb348c97df44 859 if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_ABORT)
lypinator 0:bb348c97df44 860 {
lypinator 0:bb348c97df44 861 /* Update error code */
lypinator 0:bb348c97df44 862 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
lypinator 0:bb348c97df44 863
lypinator 0:bb348c97df44 864 /* Change the DMA2D state */
lypinator 0:bb348c97df44 865 hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
lypinator 0:bb348c97df44 866
lypinator 0:bb348c97df44 867 /* Process Unlocked */
lypinator 0:bb348c97df44 868 __HAL_UNLOCK(hdma2d);
lypinator 0:bb348c97df44 869
lypinator 0:bb348c97df44 870 return HAL_TIMEOUT;
lypinator 0:bb348c97df44 871 }
lypinator 0:bb348c97df44 872 }
lypinator 0:bb348c97df44 873
lypinator 0:bb348c97df44 874 /* Disable the CLUT Transfer Complete, Transfer Error, Configuration Error and CLUT Access Error interrupts */
lypinator 0:bb348c97df44 875 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE);
lypinator 0:bb348c97df44 876
lypinator 0:bb348c97df44 877 /* Change the DMA2D state*/
lypinator 0:bb348c97df44 878 hdma2d->State = HAL_DMA2D_STATE_READY;
lypinator 0:bb348c97df44 879
lypinator 0:bb348c97df44 880 /* Process Unlocked */
lypinator 0:bb348c97df44 881 __HAL_UNLOCK(hdma2d);
lypinator 0:bb348c97df44 882
lypinator 0:bb348c97df44 883 return HAL_OK;
lypinator 0:bb348c97df44 884 }
lypinator 0:bb348c97df44 885
lypinator 0:bb348c97df44 886 /**
lypinator 0:bb348c97df44 887 * @brief Suspend the DMA2D CLUT loading.
lypinator 0:bb348c97df44 888 * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 889 * the configuration information for the DMA2D.
lypinator 0:bb348c97df44 890 * @param LayerIdx DMA2D Layer index.
lypinator 0:bb348c97df44 891 * This parameter can be one of the following values:
lypinator 0:bb348c97df44 892 * 0(background) / 1(foreground)
lypinator 0:bb348c97df44 893 * @retval HAL status
lypinator 0:bb348c97df44 894 */
lypinator 0:bb348c97df44 895 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
lypinator 0:bb348c97df44 896 {
lypinator 0:bb348c97df44 897 uint32_t tickstart = 0U;
lypinator 0:bb348c97df44 898 __IO uint32_t * reg = &(hdma2d->Instance->BGPFCCR); /* by default, point at background register */
lypinator 0:bb348c97df44 899
lypinator 0:bb348c97df44 900 /* Suspend the CLUT loading */
lypinator 0:bb348c97df44 901 SET_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
lypinator 0:bb348c97df44 902
lypinator 0:bb348c97df44 903 /* If foreground CLUT loading is considered, update local variables */
lypinator 0:bb348c97df44 904 if(LayerIdx == 1U)
lypinator 0:bb348c97df44 905 {
lypinator 0:bb348c97df44 906 reg = &(hdma2d->Instance->FGPFCCR);
lypinator 0:bb348c97df44 907 }
lypinator 0:bb348c97df44 908
lypinator 0:bb348c97df44 909 /* Get tick */
lypinator 0:bb348c97df44 910 tickstart = HAL_GetTick();
lypinator 0:bb348c97df44 911
lypinator 0:bb348c97df44 912 /* Check if the CLUT loading is suspended */
lypinator 0:bb348c97df44 913 while (((hdma2d->Instance->CR & DMA2D_CR_SUSP) != DMA2D_CR_SUSP) \
lypinator 0:bb348c97df44 914 && ((*reg & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START))
lypinator 0:bb348c97df44 915 {
lypinator 0:bb348c97df44 916 if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_SUSPEND)
lypinator 0:bb348c97df44 917 {
lypinator 0:bb348c97df44 918 /* Update error code */
lypinator 0:bb348c97df44 919 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
lypinator 0:bb348c97df44 920
lypinator 0:bb348c97df44 921 /* Change the DMA2D state */
lypinator 0:bb348c97df44 922 hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
lypinator 0:bb348c97df44 923
lypinator 0:bb348c97df44 924 return HAL_TIMEOUT;
lypinator 0:bb348c97df44 925 }
lypinator 0:bb348c97df44 926 }
lypinator 0:bb348c97df44 927
lypinator 0:bb348c97df44 928 /* Check whether or not a transfer is actually suspended and change the DMA2D state accordingly */
lypinator 0:bb348c97df44 929 if ((*reg & DMA2D_BGPFCCR_START) != RESET)
lypinator 0:bb348c97df44 930 {
lypinator 0:bb348c97df44 931 hdma2d->State = HAL_DMA2D_STATE_SUSPEND;
lypinator 0:bb348c97df44 932 }
lypinator 0:bb348c97df44 933 else
lypinator 0:bb348c97df44 934 {
lypinator 0:bb348c97df44 935 /* Make sure SUSP bit is cleared since it is meaningless
lypinator 0:bb348c97df44 936 when no tranfer is on-going */
lypinator 0:bb348c97df44 937 CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
lypinator 0:bb348c97df44 938 }
lypinator 0:bb348c97df44 939
lypinator 0:bb348c97df44 940 return HAL_OK;
lypinator 0:bb348c97df44 941 }
lypinator 0:bb348c97df44 942
lypinator 0:bb348c97df44 943 /**
lypinator 0:bb348c97df44 944 * @brief Resume the DMA2D CLUT loading.
lypinator 0:bb348c97df44 945 * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 946 * the configuration information for the DMA2D.
lypinator 0:bb348c97df44 947 * @param LayerIdx DMA2D Layer index.
lypinator 0:bb348c97df44 948 * This parameter can be one of the following values:
lypinator 0:bb348c97df44 949 * 0(background) / 1(foreground)
lypinator 0:bb348c97df44 950 * @retval HAL status
lypinator 0:bb348c97df44 951 */
lypinator 0:bb348c97df44 952 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
lypinator 0:bb348c97df44 953 {
lypinator 0:bb348c97df44 954 /* Check the SUSP and START bits for background or foreground CLUT loading */
lypinator 0:bb348c97df44 955 if(LayerIdx == 0U)
lypinator 0:bb348c97df44 956 {
lypinator 0:bb348c97df44 957 /* Background CLUT loading suspension check */
lypinator 0:bb348c97df44 958 if (((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP)
lypinator 0:bb348c97df44 959 && ((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START))
lypinator 0:bb348c97df44 960 {
lypinator 0:bb348c97df44 961 /* Ongoing CLUT loading is suspended: change the DMA2D state before resuming */
lypinator 0:bb348c97df44 962 hdma2d->State = HAL_DMA2D_STATE_BUSY;
lypinator 0:bb348c97df44 963 }
lypinator 0:bb348c97df44 964 }
lypinator 0:bb348c97df44 965 else
lypinator 0:bb348c97df44 966 {
lypinator 0:bb348c97df44 967 /* Foreground CLUT loading suspension check */
lypinator 0:bb348c97df44 968 if (((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP)
lypinator 0:bb348c97df44 969 && ((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) == DMA2D_FGPFCCR_START))
lypinator 0:bb348c97df44 970 {
lypinator 0:bb348c97df44 971 /* Ongoing CLUT loading is suspended: change the DMA2D state before resuming */
lypinator 0:bb348c97df44 972 hdma2d->State = HAL_DMA2D_STATE_BUSY;
lypinator 0:bb348c97df44 973 }
lypinator 0:bb348c97df44 974 }
lypinator 0:bb348c97df44 975
lypinator 0:bb348c97df44 976 /* Resume the CLUT loading */
lypinator 0:bb348c97df44 977 CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
lypinator 0:bb348c97df44 978
lypinator 0:bb348c97df44 979 return HAL_OK;
lypinator 0:bb348c97df44 980 }
lypinator 0:bb348c97df44 981
lypinator 0:bb348c97df44 982 /**
lypinator 0:bb348c97df44 983 * @brief Polling for transfer complete or CLUT loading.
lypinator 0:bb348c97df44 984 * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 985 * the configuration information for the DMA2D.
lypinator 0:bb348c97df44 986 * @param Timeout Timeout duration
lypinator 0:bb348c97df44 987 * @retval HAL status
lypinator 0:bb348c97df44 988 */
lypinator 0:bb348c97df44 989 HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout)
lypinator 0:bb348c97df44 990 {
lypinator 0:bb348c97df44 991 uint32_t tickstart = 0U;
lypinator 0:bb348c97df44 992 __IO uint32_t isrflags = 0x0U;
lypinator 0:bb348c97df44 993
lypinator 0:bb348c97df44 994 /* Polling for DMA2D transfer */
lypinator 0:bb348c97df44 995 if((hdma2d->Instance->CR & DMA2D_CR_START) != RESET)
lypinator 0:bb348c97df44 996 {
lypinator 0:bb348c97df44 997 /* Get tick */
lypinator 0:bb348c97df44 998 tickstart = HAL_GetTick();
lypinator 0:bb348c97df44 999
lypinator 0:bb348c97df44 1000 while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TC) == RESET)
lypinator 0:bb348c97df44 1001 {
lypinator 0:bb348c97df44 1002 isrflags = READ_REG(hdma2d->Instance->ISR);
lypinator 0:bb348c97df44 1003 if ((isrflags & (DMA2D_FLAG_CE|DMA2D_FLAG_TE)) != RESET)
lypinator 0:bb348c97df44 1004 {
lypinator 0:bb348c97df44 1005 if ((isrflags & DMA2D_FLAG_CE) != RESET)
lypinator 0:bb348c97df44 1006 {
lypinator 0:bb348c97df44 1007 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;
lypinator 0:bb348c97df44 1008 }
lypinator 0:bb348c97df44 1009 if ((isrflags & DMA2D_FLAG_TE) != RESET)
lypinator 0:bb348c97df44 1010 {
lypinator 0:bb348c97df44 1011 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;
lypinator 0:bb348c97df44 1012 }
lypinator 0:bb348c97df44 1013 /* Clear the transfer and configuration error flags */
lypinator 0:bb348c97df44 1014 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE | DMA2D_FLAG_TE);
lypinator 0:bb348c97df44 1015
lypinator 0:bb348c97df44 1016 /* Change DMA2D state */
lypinator 0:bb348c97df44 1017 hdma2d->State = HAL_DMA2D_STATE_ERROR;
lypinator 0:bb348c97df44 1018
lypinator 0:bb348c97df44 1019 /* Process unlocked */
lypinator 0:bb348c97df44 1020 __HAL_UNLOCK(hdma2d);
lypinator 0:bb348c97df44 1021
lypinator 0:bb348c97df44 1022 return HAL_ERROR;
lypinator 0:bb348c97df44 1023 }
lypinator 0:bb348c97df44 1024 /* Check for the Timeout */
lypinator 0:bb348c97df44 1025 if(Timeout != HAL_MAX_DELAY)
lypinator 0:bb348c97df44 1026 {
lypinator 0:bb348c97df44 1027 if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
lypinator 0:bb348c97df44 1028 {
lypinator 0:bb348c97df44 1029 /* Update error code */
lypinator 0:bb348c97df44 1030 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
lypinator 0:bb348c97df44 1031
lypinator 0:bb348c97df44 1032 /* Change the DMA2D state */
lypinator 0:bb348c97df44 1033 hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
lypinator 0:bb348c97df44 1034
lypinator 0:bb348c97df44 1035 /* Process unlocked */
lypinator 0:bb348c97df44 1036 __HAL_UNLOCK(hdma2d);
lypinator 0:bb348c97df44 1037
lypinator 0:bb348c97df44 1038 return HAL_TIMEOUT;
lypinator 0:bb348c97df44 1039 }
lypinator 0:bb348c97df44 1040 }
lypinator 0:bb348c97df44 1041 }
lypinator 0:bb348c97df44 1042 }
lypinator 0:bb348c97df44 1043 /* Polling for CLUT loading (foreground or background) */
lypinator 0:bb348c97df44 1044 if (((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) != RESET) ||
lypinator 0:bb348c97df44 1045 ((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) != RESET))
lypinator 0:bb348c97df44 1046 {
lypinator 0:bb348c97df44 1047 /* Get tick */
lypinator 0:bb348c97df44 1048 tickstart = HAL_GetTick();
lypinator 0:bb348c97df44 1049
lypinator 0:bb348c97df44 1050 while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CTC) == RESET)
lypinator 0:bb348c97df44 1051 {
lypinator 0:bb348c97df44 1052 isrflags = READ_REG(hdma2d->Instance->ISR);
lypinator 0:bb348c97df44 1053 if ((isrflags & (DMA2D_FLAG_CAE|DMA2D_FLAG_CE|DMA2D_FLAG_TE)) != RESET)
lypinator 0:bb348c97df44 1054 {
lypinator 0:bb348c97df44 1055 if ((isrflags & DMA2D_FLAG_CAE) != RESET)
lypinator 0:bb348c97df44 1056 {
lypinator 0:bb348c97df44 1057 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CAE;
lypinator 0:bb348c97df44 1058 }
lypinator 0:bb348c97df44 1059 if ((isrflags & DMA2D_FLAG_CE) != RESET)
lypinator 0:bb348c97df44 1060 {
lypinator 0:bb348c97df44 1061 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;
lypinator 0:bb348c97df44 1062 }
lypinator 0:bb348c97df44 1063 if ((isrflags & DMA2D_FLAG_TE) != RESET)
lypinator 0:bb348c97df44 1064 {
lypinator 0:bb348c97df44 1065 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;
lypinator 0:bb348c97df44 1066 }
lypinator 0:bb348c97df44 1067 /* Clear the CLUT Access Error, Configuration Error and Transfer Error flags */
lypinator 0:bb348c97df44 1068 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE | DMA2D_FLAG_CE | DMA2D_FLAG_TE);
lypinator 0:bb348c97df44 1069
lypinator 0:bb348c97df44 1070 /* Change DMA2D state */
lypinator 0:bb348c97df44 1071 hdma2d->State= HAL_DMA2D_STATE_ERROR;
lypinator 0:bb348c97df44 1072
lypinator 0:bb348c97df44 1073 /* Process unlocked */
lypinator 0:bb348c97df44 1074 __HAL_UNLOCK(hdma2d);
lypinator 0:bb348c97df44 1075
lypinator 0:bb348c97df44 1076 return HAL_ERROR;
lypinator 0:bb348c97df44 1077 }
lypinator 0:bb348c97df44 1078 /* Check for the Timeout */
lypinator 0:bb348c97df44 1079 if(Timeout != HAL_MAX_DELAY)
lypinator 0:bb348c97df44 1080 {
lypinator 0:bb348c97df44 1081 if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
lypinator 0:bb348c97df44 1082 {
lypinator 0:bb348c97df44 1083 /* Update error code */
lypinator 0:bb348c97df44 1084 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
lypinator 0:bb348c97df44 1085
lypinator 0:bb348c97df44 1086 /* Change the DMA2D state */
lypinator 0:bb348c97df44 1087 hdma2d->State= HAL_DMA2D_STATE_TIMEOUT;
lypinator 0:bb348c97df44 1088
lypinator 0:bb348c97df44 1089 /* Process unlocked */
lypinator 0:bb348c97df44 1090 __HAL_UNLOCK(hdma2d);
lypinator 0:bb348c97df44 1091
lypinator 0:bb348c97df44 1092 return HAL_TIMEOUT;
lypinator 0:bb348c97df44 1093 }
lypinator 0:bb348c97df44 1094 }
lypinator 0:bb348c97df44 1095 }
lypinator 0:bb348c97df44 1096 }
lypinator 0:bb348c97df44 1097
lypinator 0:bb348c97df44 1098 /* Clear the transfer complete and CLUT loading flags */
lypinator 0:bb348c97df44 1099 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC|DMA2D_FLAG_CTC);
lypinator 0:bb348c97df44 1100
lypinator 0:bb348c97df44 1101 /* Change DMA2D state */
lypinator 0:bb348c97df44 1102 hdma2d->State = HAL_DMA2D_STATE_READY;
lypinator 0:bb348c97df44 1103
lypinator 0:bb348c97df44 1104 /* Process unlocked */
lypinator 0:bb348c97df44 1105 __HAL_UNLOCK(hdma2d);
lypinator 0:bb348c97df44 1106
lypinator 0:bb348c97df44 1107 return HAL_OK;
lypinator 0:bb348c97df44 1108 }
lypinator 0:bb348c97df44 1109 /**
lypinator 0:bb348c97df44 1110 * @brief Handle DMA2D interrupt request.
lypinator 0:bb348c97df44 1111 * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 1112 * the configuration information for the DMA2D.
lypinator 0:bb348c97df44 1113 * @retval HAL status
lypinator 0:bb348c97df44 1114 */
lypinator 0:bb348c97df44 1115 void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d)
lypinator 0:bb348c97df44 1116 {
lypinator 0:bb348c97df44 1117 uint32_t isrflags = READ_REG(hdma2d->Instance->ISR);
lypinator 0:bb348c97df44 1118 uint32_t crflags = READ_REG(hdma2d->Instance->CR);
lypinator 0:bb348c97df44 1119
lypinator 0:bb348c97df44 1120 /* Transfer Error Interrupt management ***************************************/
lypinator 0:bb348c97df44 1121 if ((isrflags & DMA2D_FLAG_TE) != RESET)
lypinator 0:bb348c97df44 1122 {
lypinator 0:bb348c97df44 1123 if ((crflags & DMA2D_IT_TE) != RESET)
lypinator 0:bb348c97df44 1124 {
lypinator 0:bb348c97df44 1125 /* Disable the transfer Error interrupt */
lypinator 0:bb348c97df44 1126 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TE);
lypinator 0:bb348c97df44 1127
lypinator 0:bb348c97df44 1128 /* Update error code */
lypinator 0:bb348c97df44 1129 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;
lypinator 0:bb348c97df44 1130
lypinator 0:bb348c97df44 1131 /* Clear the transfer error flag */
lypinator 0:bb348c97df44 1132 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TE);
lypinator 0:bb348c97df44 1133
lypinator 0:bb348c97df44 1134 /* Change DMA2D state */
lypinator 0:bb348c97df44 1135 hdma2d->State = HAL_DMA2D_STATE_ERROR;
lypinator 0:bb348c97df44 1136
lypinator 0:bb348c97df44 1137 /* Process Unlocked */
lypinator 0:bb348c97df44 1138 __HAL_UNLOCK(hdma2d);
lypinator 0:bb348c97df44 1139
lypinator 0:bb348c97df44 1140 if(hdma2d->XferErrorCallback != NULL)
lypinator 0:bb348c97df44 1141 {
lypinator 0:bb348c97df44 1142 /* Transfer error Callback */
lypinator 0:bb348c97df44 1143 hdma2d->XferErrorCallback(hdma2d);
lypinator 0:bb348c97df44 1144 }
lypinator 0:bb348c97df44 1145 }
lypinator 0:bb348c97df44 1146 }
lypinator 0:bb348c97df44 1147 /* Configuration Error Interrupt management **********************************/
lypinator 0:bb348c97df44 1148 if ((isrflags & DMA2D_FLAG_CE) != RESET)
lypinator 0:bb348c97df44 1149 {
lypinator 0:bb348c97df44 1150 if ((crflags & DMA2D_IT_CE) != RESET)
lypinator 0:bb348c97df44 1151 {
lypinator 0:bb348c97df44 1152 /* Disable the Configuration Error interrupt */
lypinator 0:bb348c97df44 1153 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CE);
lypinator 0:bb348c97df44 1154
lypinator 0:bb348c97df44 1155 /* Clear the Configuration error flag */
lypinator 0:bb348c97df44 1156 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE);
lypinator 0:bb348c97df44 1157
lypinator 0:bb348c97df44 1158 /* Update error code */
lypinator 0:bb348c97df44 1159 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;
lypinator 0:bb348c97df44 1160
lypinator 0:bb348c97df44 1161 /* Change DMA2D state */
lypinator 0:bb348c97df44 1162 hdma2d->State = HAL_DMA2D_STATE_ERROR;
lypinator 0:bb348c97df44 1163
lypinator 0:bb348c97df44 1164 /* Process Unlocked */
lypinator 0:bb348c97df44 1165 __HAL_UNLOCK(hdma2d);
lypinator 0:bb348c97df44 1166
lypinator 0:bb348c97df44 1167 if(hdma2d->XferErrorCallback != NULL)
lypinator 0:bb348c97df44 1168 {
lypinator 0:bb348c97df44 1169 /* Transfer error Callback */
lypinator 0:bb348c97df44 1170 hdma2d->XferErrorCallback(hdma2d);
lypinator 0:bb348c97df44 1171 }
lypinator 0:bb348c97df44 1172 }
lypinator 0:bb348c97df44 1173 }
lypinator 0:bb348c97df44 1174 /* CLUT access Error Interrupt management ***********************************/
lypinator 0:bb348c97df44 1175 if ((isrflags & DMA2D_FLAG_CAE) != RESET)
lypinator 0:bb348c97df44 1176 {
lypinator 0:bb348c97df44 1177 if ((crflags & DMA2D_IT_CAE) != RESET)
lypinator 0:bb348c97df44 1178 {
lypinator 0:bb348c97df44 1179 /* Disable the CLUT access error interrupt */
lypinator 0:bb348c97df44 1180 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CAE);
lypinator 0:bb348c97df44 1181
lypinator 0:bb348c97df44 1182 /* Clear the CLUT access error flag */
lypinator 0:bb348c97df44 1183 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE);
lypinator 0:bb348c97df44 1184
lypinator 0:bb348c97df44 1185 /* Update error code */
lypinator 0:bb348c97df44 1186 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CAE;
lypinator 0:bb348c97df44 1187
lypinator 0:bb348c97df44 1188 /* Change DMA2D state */
lypinator 0:bb348c97df44 1189 hdma2d->State = HAL_DMA2D_STATE_ERROR;
lypinator 0:bb348c97df44 1190
lypinator 0:bb348c97df44 1191 /* Process Unlocked */
lypinator 0:bb348c97df44 1192 __HAL_UNLOCK(hdma2d);
lypinator 0:bb348c97df44 1193
lypinator 0:bb348c97df44 1194 if(hdma2d->XferErrorCallback != NULL)
lypinator 0:bb348c97df44 1195 {
lypinator 0:bb348c97df44 1196 /* Transfer error Callback */
lypinator 0:bb348c97df44 1197 hdma2d->XferErrorCallback(hdma2d);
lypinator 0:bb348c97df44 1198 }
lypinator 0:bb348c97df44 1199 }
lypinator 0:bb348c97df44 1200 }
lypinator 0:bb348c97df44 1201 /* Transfer watermark Interrupt management **********************************/
lypinator 0:bb348c97df44 1202 if ((isrflags & DMA2D_FLAG_TW) != RESET)
lypinator 0:bb348c97df44 1203 {
lypinator 0:bb348c97df44 1204 if ((crflags & DMA2D_IT_TW) != RESET)
lypinator 0:bb348c97df44 1205 {
lypinator 0:bb348c97df44 1206 /* Disable the transfer watermark interrupt */
lypinator 0:bb348c97df44 1207 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TW);
lypinator 0:bb348c97df44 1208
lypinator 0:bb348c97df44 1209 /* Clear the transfer watermark flag */
lypinator 0:bb348c97df44 1210 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TW);
lypinator 0:bb348c97df44 1211
lypinator 0:bb348c97df44 1212 /* Transfer watermark Callback */
lypinator 0:bb348c97df44 1213 HAL_DMA2D_LineEventCallback(hdma2d);
lypinator 0:bb348c97df44 1214 }
lypinator 0:bb348c97df44 1215 }
lypinator 0:bb348c97df44 1216 /* Transfer Complete Interrupt management ************************************/
lypinator 0:bb348c97df44 1217 if ((isrflags & DMA2D_FLAG_TC) != RESET)
lypinator 0:bb348c97df44 1218 {
lypinator 0:bb348c97df44 1219 if ((crflags & DMA2D_IT_TC) != RESET)
lypinator 0:bb348c97df44 1220 {
lypinator 0:bb348c97df44 1221 /* Disable the transfer complete interrupt */
lypinator 0:bb348c97df44 1222 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TC);
lypinator 0:bb348c97df44 1223
lypinator 0:bb348c97df44 1224 /* Clear the transfer complete flag */
lypinator 0:bb348c97df44 1225 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC);
lypinator 0:bb348c97df44 1226
lypinator 0:bb348c97df44 1227 /* Update error code */
lypinator 0:bb348c97df44 1228 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_NONE;
lypinator 0:bb348c97df44 1229
lypinator 0:bb348c97df44 1230 /* Change DMA2D state */
lypinator 0:bb348c97df44 1231 hdma2d->State = HAL_DMA2D_STATE_READY;
lypinator 0:bb348c97df44 1232
lypinator 0:bb348c97df44 1233 /* Process Unlocked */
lypinator 0:bb348c97df44 1234 __HAL_UNLOCK(hdma2d);
lypinator 0:bb348c97df44 1235
lypinator 0:bb348c97df44 1236 if(hdma2d->XferCpltCallback != NULL)
lypinator 0:bb348c97df44 1237 {
lypinator 0:bb348c97df44 1238 /* Transfer complete Callback */
lypinator 0:bb348c97df44 1239 hdma2d->XferCpltCallback(hdma2d);
lypinator 0:bb348c97df44 1240 }
lypinator 0:bb348c97df44 1241 }
lypinator 0:bb348c97df44 1242 }
lypinator 0:bb348c97df44 1243 /* CLUT Transfer Complete Interrupt management ******************************/
lypinator 0:bb348c97df44 1244 if ((isrflags & DMA2D_FLAG_CTC) != RESET)
lypinator 0:bb348c97df44 1245 {
lypinator 0:bb348c97df44 1246 if ((crflags & DMA2D_IT_CTC) != RESET)
lypinator 0:bb348c97df44 1247 {
lypinator 0:bb348c97df44 1248 /* Disable the CLUT transfer complete interrupt */
lypinator 0:bb348c97df44 1249 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CTC);
lypinator 0:bb348c97df44 1250
lypinator 0:bb348c97df44 1251 /* Clear the CLUT transfer complete flag */
lypinator 0:bb348c97df44 1252 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CTC);
lypinator 0:bb348c97df44 1253
lypinator 0:bb348c97df44 1254 /* Update error code */
lypinator 0:bb348c97df44 1255 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_NONE;
lypinator 0:bb348c97df44 1256
lypinator 0:bb348c97df44 1257 /* Change DMA2D state */
lypinator 0:bb348c97df44 1258 hdma2d->State = HAL_DMA2D_STATE_READY;
lypinator 0:bb348c97df44 1259
lypinator 0:bb348c97df44 1260 /* Process Unlocked */
lypinator 0:bb348c97df44 1261 __HAL_UNLOCK(hdma2d);
lypinator 0:bb348c97df44 1262
lypinator 0:bb348c97df44 1263 /* CLUT Transfer complete Callback */
lypinator 0:bb348c97df44 1264 HAL_DMA2D_CLUTLoadingCpltCallback(hdma2d);
lypinator 0:bb348c97df44 1265 }
lypinator 0:bb348c97df44 1266 }
lypinator 0:bb348c97df44 1267 }
lypinator 0:bb348c97df44 1268
lypinator 0:bb348c97df44 1269 /**
lypinator 0:bb348c97df44 1270 * @brief Transfer watermark callback.
lypinator 0:bb348c97df44 1271 * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 1272 * the configuration information for the DMA2D.
lypinator 0:bb348c97df44 1273 * @retval None
lypinator 0:bb348c97df44 1274 */
lypinator 0:bb348c97df44 1275 __weak void HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef *hdma2d)
lypinator 0:bb348c97df44 1276 {
lypinator 0:bb348c97df44 1277 /* Prevent unused argument(s) compilation warning */
lypinator 0:bb348c97df44 1278 UNUSED(hdma2d);
lypinator 0:bb348c97df44 1279
lypinator 0:bb348c97df44 1280 /* NOTE : This function should not be modified; when the callback is needed,
lypinator 0:bb348c97df44 1281 the HAL_DMA2D_LineEventCallback can be implemented in the user file.
lypinator 0:bb348c97df44 1282 */
lypinator 0:bb348c97df44 1283 }
lypinator 0:bb348c97df44 1284
lypinator 0:bb348c97df44 1285 /**
lypinator 0:bb348c97df44 1286 * @brief CLUT Transfer Complete callback.
lypinator 0:bb348c97df44 1287 * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 1288 * the configuration information for the DMA2D.
lypinator 0:bb348c97df44 1289 * @retval None
lypinator 0:bb348c97df44 1290 */
lypinator 0:bb348c97df44 1291 __weak void HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d)
lypinator 0:bb348c97df44 1292 {
lypinator 0:bb348c97df44 1293 /* Prevent unused argument(s) compilation warning */
lypinator 0:bb348c97df44 1294 UNUSED(hdma2d);
lypinator 0:bb348c97df44 1295
lypinator 0:bb348c97df44 1296 /* NOTE : This function should not be modified; when the callback is needed,
lypinator 0:bb348c97df44 1297 the HAL_DMA2D_CLUTLoadingCpltCallback can be implemented in the user file.
lypinator 0:bb348c97df44 1298 */
lypinator 0:bb348c97df44 1299 }
lypinator 0:bb348c97df44 1300
lypinator 0:bb348c97df44 1301 /**
lypinator 0:bb348c97df44 1302 * @}
lypinator 0:bb348c97df44 1303 */
lypinator 0:bb348c97df44 1304
lypinator 0:bb348c97df44 1305 /** @defgroup DMA2D_Exported_Functions_Group3 Peripheral Control functions
lypinator 0:bb348c97df44 1306 * @brief Peripheral Control functions
lypinator 0:bb348c97df44 1307 *
lypinator 0:bb348c97df44 1308 @verbatim
lypinator 0:bb348c97df44 1309 ===============================================================================
lypinator 0:bb348c97df44 1310 ##### Peripheral Control functions #####
lypinator 0:bb348c97df44 1311 ===============================================================================
lypinator 0:bb348c97df44 1312 [..] This section provides functions allowing to:
lypinator 0:bb348c97df44 1313 (+) Configure the DMA2D foreground or background layer parameters.
lypinator 0:bb348c97df44 1314 (+) Configure the DMA2D CLUT transfer.
lypinator 0:bb348c97df44 1315 (+) Configure the line watermark
lypinator 0:bb348c97df44 1316 (+) Configure the dead time value.
lypinator 0:bb348c97df44 1317 (+) Enable or disable the dead time value functionality.
lypinator 0:bb348c97df44 1318
lypinator 0:bb348c97df44 1319 @endverbatim
lypinator 0:bb348c97df44 1320 * @{
lypinator 0:bb348c97df44 1321 */
lypinator 0:bb348c97df44 1322
lypinator 0:bb348c97df44 1323 /**
lypinator 0:bb348c97df44 1324 * @brief Configure the DMA2D Layer according to the specified
lypinator 0:bb348c97df44 1325 * parameters in the DMA2D_InitTypeDef and create the associated handle.
lypinator 0:bb348c97df44 1326 * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 1327 * the configuration information for the DMA2D.
lypinator 0:bb348c97df44 1328 * @param LayerIdx DMA2D Layer index.
lypinator 0:bb348c97df44 1329 * This parameter can be one of the following values:
lypinator 0:bb348c97df44 1330 * 0(background) / 1(foreground)
lypinator 0:bb348c97df44 1331 * @retval HAL status
lypinator 0:bb348c97df44 1332 */
lypinator 0:bb348c97df44 1333 HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
lypinator 0:bb348c97df44 1334 {
lypinator 0:bb348c97df44 1335 DMA2D_LayerCfgTypeDef *pLayerCfg = &hdma2d->LayerCfg[LayerIdx];
lypinator 0:bb348c97df44 1336 uint32_t regValue = 0U;
lypinator 0:bb348c97df44 1337
lypinator 0:bb348c97df44 1338 /* Check the parameters */
lypinator 0:bb348c97df44 1339 assert_param(IS_DMA2D_LAYER(LayerIdx));
lypinator 0:bb348c97df44 1340 assert_param(IS_DMA2D_OFFSET(pLayerCfg->InputOffset));
lypinator 0:bb348c97df44 1341 if(hdma2d->Init.Mode != DMA2D_R2M)
lypinator 0:bb348c97df44 1342 {
lypinator 0:bb348c97df44 1343 assert_param(IS_DMA2D_INPUT_COLOR_MODE(pLayerCfg->InputColorMode));
lypinator 0:bb348c97df44 1344 if(hdma2d->Init.Mode != DMA2D_M2M)
lypinator 0:bb348c97df44 1345 {
lypinator 0:bb348c97df44 1346 assert_param(IS_DMA2D_ALPHA_MODE(pLayerCfg->AlphaMode));
lypinator 0:bb348c97df44 1347 }
lypinator 0:bb348c97df44 1348 }
lypinator 0:bb348c97df44 1349
lypinator 0:bb348c97df44 1350 /* Process locked */
lypinator 0:bb348c97df44 1351 __HAL_LOCK(hdma2d);
lypinator 0:bb348c97df44 1352
lypinator 0:bb348c97df44 1353 /* Change DMA2D peripheral state */
lypinator 0:bb348c97df44 1354 hdma2d->State = HAL_DMA2D_STATE_BUSY;
lypinator 0:bb348c97df44 1355
lypinator 0:bb348c97df44 1356 /* DMA2D BGPFCR register configuration -----------------------------------*/
lypinator 0:bb348c97df44 1357 /* Prepare the value to be written to the BGPFCCR register */
lypinator 0:bb348c97df44 1358
lypinator 0:bb348c97df44 1359 if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
lypinator 0:bb348c97df44 1360 {
lypinator 0:bb348c97df44 1361 regValue = pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << DMA2D_POSITION_BGPFCCR_AM) | (pLayerCfg->InputAlpha & DMA2D_BGPFCCR_ALPHA);
lypinator 0:bb348c97df44 1362 }
lypinator 0:bb348c97df44 1363 else
lypinator 0:bb348c97df44 1364 {
lypinator 0:bb348c97df44 1365 regValue = pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << DMA2D_POSITION_BGPFCCR_AM) | (pLayerCfg->InputAlpha << DMA2D_POSITION_BGPFCCR_ALPHA);
lypinator 0:bb348c97df44 1366 }
lypinator 0:bb348c97df44 1367
lypinator 0:bb348c97df44 1368 /* Configure the background DMA2D layer */
lypinator 0:bb348c97df44 1369 if(LayerIdx == 0)
lypinator 0:bb348c97df44 1370 {
lypinator 0:bb348c97df44 1371 /* Write DMA2D BGPFCCR register */
lypinator 0:bb348c97df44 1372 MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CM | DMA2D_BGPFCCR_AM | DMA2D_BGPFCCR_ALPHA), regValue);
lypinator 0:bb348c97df44 1373
lypinator 0:bb348c97df44 1374 /* DMA2D BGOR register configuration -------------------------------------*/
lypinator 0:bb348c97df44 1375 WRITE_REG(hdma2d->Instance->BGOR, pLayerCfg->InputOffset);
lypinator 0:bb348c97df44 1376
lypinator 0:bb348c97df44 1377 /* DMA2D BGCOLR register configuration -------------------------------------*/
lypinator 0:bb348c97df44 1378 if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
lypinator 0:bb348c97df44 1379 {
lypinator 0:bb348c97df44 1380 WRITE_REG(hdma2d->Instance->BGCOLR, pLayerCfg->InputAlpha & (DMA2D_BGCOLR_BLUE|DMA2D_BGCOLR_GREEN|DMA2D_BGCOLR_RED));
lypinator 0:bb348c97df44 1381 }
lypinator 0:bb348c97df44 1382 }
lypinator 0:bb348c97df44 1383 /* Configure the foreground DMA2D layer */
lypinator 0:bb348c97df44 1384 else
lypinator 0:bb348c97df44 1385 {
lypinator 0:bb348c97df44 1386 /* Write DMA2D FGPFCCR register */
lypinator 0:bb348c97df44 1387 MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_BGPFCCR_CM | DMA2D_BGPFCCR_AM | DMA2D_BGPFCCR_ALPHA), regValue);
lypinator 0:bb348c97df44 1388
lypinator 0:bb348c97df44 1389 /* DMA2D FGOR register configuration -------------------------------------*/
lypinator 0:bb348c97df44 1390 WRITE_REG(hdma2d->Instance->FGOR, pLayerCfg->InputOffset);
lypinator 0:bb348c97df44 1391
lypinator 0:bb348c97df44 1392 /* DMA2D FGCOLR register configuration -------------------------------------*/
lypinator 0:bb348c97df44 1393 if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
lypinator 0:bb348c97df44 1394 {
lypinator 0:bb348c97df44 1395 WRITE_REG(hdma2d->Instance->FGCOLR, pLayerCfg->InputAlpha & (DMA2D_FGCOLR_BLUE|DMA2D_FGCOLR_GREEN|DMA2D_FGCOLR_RED));
lypinator 0:bb348c97df44 1396 }
lypinator 0:bb348c97df44 1397 }
lypinator 0:bb348c97df44 1398 /* Initialize the DMA2D state*/
lypinator 0:bb348c97df44 1399 hdma2d->State = HAL_DMA2D_STATE_READY;
lypinator 0:bb348c97df44 1400
lypinator 0:bb348c97df44 1401 /* Process unlocked */
lypinator 0:bb348c97df44 1402 __HAL_UNLOCK(hdma2d);
lypinator 0:bb348c97df44 1403
lypinator 0:bb348c97df44 1404 return HAL_OK;
lypinator 0:bb348c97df44 1405 }
lypinator 0:bb348c97df44 1406
lypinator 0:bb348c97df44 1407 /**
lypinator 0:bb348c97df44 1408 * @brief Configure the DMA2D CLUT Transfer.
lypinator 0:bb348c97df44 1409 * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 1410 * the configuration information for the DMA2D.
lypinator 0:bb348c97df44 1411 * @param CLUTCfg Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
lypinator 0:bb348c97df44 1412 * the configuration information for the color look up table.
lypinator 0:bb348c97df44 1413 * @param LayerIdx DMA2D Layer index.
lypinator 0:bb348c97df44 1414 * This parameter can be one of the following values:
lypinator 0:bb348c97df44 1415 * 0(background) / 1(foreground)
lypinator 0:bb348c97df44 1416 * @retval HAL status
lypinator 0:bb348c97df44 1417 */
lypinator 0:bb348c97df44 1418 HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
lypinator 0:bb348c97df44 1419 {
lypinator 0:bb348c97df44 1420 /* Check the parameters */
lypinator 0:bb348c97df44 1421 assert_param(IS_DMA2D_LAYER(LayerIdx));
lypinator 0:bb348c97df44 1422 assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode));
lypinator 0:bb348c97df44 1423 assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size));
lypinator 0:bb348c97df44 1424
lypinator 0:bb348c97df44 1425 /* Process locked */
lypinator 0:bb348c97df44 1426 __HAL_LOCK(hdma2d);
lypinator 0:bb348c97df44 1427
lypinator 0:bb348c97df44 1428 /* Change DMA2D peripheral state */
lypinator 0:bb348c97df44 1429 hdma2d->State = HAL_DMA2D_STATE_BUSY;
lypinator 0:bb348c97df44 1430
lypinator 0:bb348c97df44 1431 /* Configure the CLUT of the background DMA2D layer */
lypinator 0:bb348c97df44 1432 if(LayerIdx == 0U)
lypinator 0:bb348c97df44 1433 {
lypinator 0:bb348c97df44 1434 /* Write background CLUT memory address */
lypinator 0:bb348c97df44 1435 WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);
lypinator 0:bb348c97df44 1436
lypinator 0:bb348c97df44 1437 /* Write background CLUT size and CLUT color mode */
lypinator 0:bb348c97df44 1438 MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
lypinator 0:bb348c97df44 1439 ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_BGPFCCR_CCM)));
lypinator 0:bb348c97df44 1440 }
lypinator 0:bb348c97df44 1441 /* Configure the CLUT of the foreground DMA2D layer */
lypinator 0:bb348c97df44 1442 else
lypinator 0:bb348c97df44 1443 {
lypinator 0:bb348c97df44 1444 /* Write foreground CLUT memory address */
lypinator 0:bb348c97df44 1445 WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT);
lypinator 0:bb348c97df44 1446
lypinator 0:bb348c97df44 1447 /* Write foreground CLUT size and CLUT color mode */
lypinator 0:bb348c97df44 1448 MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
lypinator 0:bb348c97df44 1449 ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_FGPFCCR_CCM)));
lypinator 0:bb348c97df44 1450 }
lypinator 0:bb348c97df44 1451
lypinator 0:bb348c97df44 1452 /* Set the DMA2D state to Ready */
lypinator 0:bb348c97df44 1453 hdma2d->State = HAL_DMA2D_STATE_READY;
lypinator 0:bb348c97df44 1454
lypinator 0:bb348c97df44 1455 /* Process unlocked */
lypinator 0:bb348c97df44 1456 __HAL_UNLOCK(hdma2d);
lypinator 0:bb348c97df44 1457
lypinator 0:bb348c97df44 1458 return HAL_OK;
lypinator 0:bb348c97df44 1459 }
lypinator 0:bb348c97df44 1460
lypinator 0:bb348c97df44 1461 /**
lypinator 0:bb348c97df44 1462 * @brief Configure the line watermark.
lypinator 0:bb348c97df44 1463 * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 1464 * the configuration information for the DMA2D.
lypinator 0:bb348c97df44 1465 * @param Line Line Watermark configuration (maximum 16-bit long value expected).
lypinator 0:bb348c97df44 1466 * @note HAL_DMA2D_ProgramLineEvent() API enables the transfer watermark interrupt.
lypinator 0:bb348c97df44 1467 * @note The transfer watermark interrupt is disabled once it has occurred.
lypinator 0:bb348c97df44 1468 * @retval HAL status
lypinator 0:bb348c97df44 1469 */
lypinator 0:bb348c97df44 1470
lypinator 0:bb348c97df44 1471 HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line)
lypinator 0:bb348c97df44 1472 {
lypinator 0:bb348c97df44 1473 /* Check the parameters */
lypinator 0:bb348c97df44 1474 assert_param(IS_DMA2D_LINEWATERMARK(Line));
lypinator 0:bb348c97df44 1475
lypinator 0:bb348c97df44 1476 if (Line > DMA2D_LWR_LW)
lypinator 0:bb348c97df44 1477 {
lypinator 0:bb348c97df44 1478 return HAL_ERROR;
lypinator 0:bb348c97df44 1479 }
lypinator 0:bb348c97df44 1480 else
lypinator 0:bb348c97df44 1481 {
lypinator 0:bb348c97df44 1482 /* Process locked */
lypinator 0:bb348c97df44 1483 __HAL_LOCK(hdma2d);
lypinator 0:bb348c97df44 1484
lypinator 0:bb348c97df44 1485 /* Change DMA2D peripheral state */
lypinator 0:bb348c97df44 1486 hdma2d->State = HAL_DMA2D_STATE_BUSY;
lypinator 0:bb348c97df44 1487
lypinator 0:bb348c97df44 1488 /* Sets the Line watermark configuration */
lypinator 0:bb348c97df44 1489 WRITE_REG(hdma2d->Instance->LWR, Line);
lypinator 0:bb348c97df44 1490
lypinator 0:bb348c97df44 1491 /* Enable the Line interrupt */
lypinator 0:bb348c97df44 1492 __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TW);
lypinator 0:bb348c97df44 1493
lypinator 0:bb348c97df44 1494 /* Initialize the DMA2D state */
lypinator 0:bb348c97df44 1495 hdma2d->State = HAL_DMA2D_STATE_READY;
lypinator 0:bb348c97df44 1496
lypinator 0:bb348c97df44 1497 /* Process unlocked */
lypinator 0:bb348c97df44 1498 __HAL_UNLOCK(hdma2d);
lypinator 0:bb348c97df44 1499
lypinator 0:bb348c97df44 1500 return HAL_OK;
lypinator 0:bb348c97df44 1501 }
lypinator 0:bb348c97df44 1502 }
lypinator 0:bb348c97df44 1503
lypinator 0:bb348c97df44 1504 /**
lypinator 0:bb348c97df44 1505 * @brief Enable DMA2D dead time feature.
lypinator 0:bb348c97df44 1506 * @param hdma2d DMA2D handle.
lypinator 0:bb348c97df44 1507 * @retval HAL status
lypinator 0:bb348c97df44 1508 */
lypinator 0:bb348c97df44 1509 HAL_StatusTypeDef HAL_DMA2D_EnableDeadTime(DMA2D_HandleTypeDef *hdma2d)
lypinator 0:bb348c97df44 1510 {
lypinator 0:bb348c97df44 1511 /* Process Locked */
lypinator 0:bb348c97df44 1512 __HAL_LOCK(hdma2d);
lypinator 0:bb348c97df44 1513
lypinator 0:bb348c97df44 1514 hdma2d->State = HAL_DMA2D_STATE_BUSY;
lypinator 0:bb348c97df44 1515
lypinator 0:bb348c97df44 1516 /* Set DMA2D_AMTCR EN bit */
lypinator 0:bb348c97df44 1517 SET_BIT(hdma2d->Instance->AMTCR, DMA2D_AMTCR_EN);
lypinator 0:bb348c97df44 1518
lypinator 0:bb348c97df44 1519 hdma2d->State = HAL_DMA2D_STATE_READY;
lypinator 0:bb348c97df44 1520
lypinator 0:bb348c97df44 1521 /* Process Unlocked */
lypinator 0:bb348c97df44 1522 __HAL_UNLOCK(hdma2d);
lypinator 0:bb348c97df44 1523
lypinator 0:bb348c97df44 1524 return HAL_OK;
lypinator 0:bb348c97df44 1525 }
lypinator 0:bb348c97df44 1526
lypinator 0:bb348c97df44 1527 /**
lypinator 0:bb348c97df44 1528 * @brief Disable DMA2D dead time feature.
lypinator 0:bb348c97df44 1529 * @param hdma2d DMA2D handle.
lypinator 0:bb348c97df44 1530 * @retval HAL status
lypinator 0:bb348c97df44 1531 */
lypinator 0:bb348c97df44 1532 HAL_StatusTypeDef HAL_DMA2D_DisableDeadTime(DMA2D_HandleTypeDef *hdma2d)
lypinator 0:bb348c97df44 1533 {
lypinator 0:bb348c97df44 1534 /* Process Locked */
lypinator 0:bb348c97df44 1535 __HAL_LOCK(hdma2d);
lypinator 0:bb348c97df44 1536
lypinator 0:bb348c97df44 1537 hdma2d->State = HAL_DMA2D_STATE_BUSY;
lypinator 0:bb348c97df44 1538
lypinator 0:bb348c97df44 1539 /* Clear DMA2D_AMTCR EN bit */
lypinator 0:bb348c97df44 1540 CLEAR_BIT(hdma2d->Instance->AMTCR, DMA2D_AMTCR_EN);
lypinator 0:bb348c97df44 1541
lypinator 0:bb348c97df44 1542 hdma2d->State = HAL_DMA2D_STATE_READY;
lypinator 0:bb348c97df44 1543
lypinator 0:bb348c97df44 1544 /* Process Unlocked */
lypinator 0:bb348c97df44 1545 __HAL_UNLOCK(hdma2d);
lypinator 0:bb348c97df44 1546
lypinator 0:bb348c97df44 1547 return HAL_OK;
lypinator 0:bb348c97df44 1548 }
lypinator 0:bb348c97df44 1549
lypinator 0:bb348c97df44 1550 /**
lypinator 0:bb348c97df44 1551 * @brief Configure dead time.
lypinator 0:bb348c97df44 1552 * @note The dead time value represents the guaranteed minimum number of cycles between
lypinator 0:bb348c97df44 1553 * two consecutive transactions on the AHB bus.
lypinator 0:bb348c97df44 1554 * @param hdma2d DMA2D handle.
lypinator 0:bb348c97df44 1555 * @param DeadTime dead time value.
lypinator 0:bb348c97df44 1556 * @retval HAL status
lypinator 0:bb348c97df44 1557 */
lypinator 0:bb348c97df44 1558 HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t DeadTime)
lypinator 0:bb348c97df44 1559 {
lypinator 0:bb348c97df44 1560 /* Process Locked */
lypinator 0:bb348c97df44 1561 __HAL_LOCK(hdma2d);
lypinator 0:bb348c97df44 1562
lypinator 0:bb348c97df44 1563 hdma2d->State = HAL_DMA2D_STATE_BUSY;
lypinator 0:bb348c97df44 1564
lypinator 0:bb348c97df44 1565 /* Set DMA2D_AMTCR DT field */
lypinator 0:bb348c97df44 1566 MODIFY_REG(hdma2d->Instance->AMTCR, DMA2D_AMTCR_DT, (((uint32_t) DeadTime) << DMA2D_POSITION_AMTCR_DT));
lypinator 0:bb348c97df44 1567
lypinator 0:bb348c97df44 1568 hdma2d->State = HAL_DMA2D_STATE_READY;
lypinator 0:bb348c97df44 1569
lypinator 0:bb348c97df44 1570 /* Process Unlocked */
lypinator 0:bb348c97df44 1571 __HAL_UNLOCK(hdma2d);
lypinator 0:bb348c97df44 1572
lypinator 0:bb348c97df44 1573 return HAL_OK;
lypinator 0:bb348c97df44 1574 }
lypinator 0:bb348c97df44 1575
lypinator 0:bb348c97df44 1576 /**
lypinator 0:bb348c97df44 1577 * @}
lypinator 0:bb348c97df44 1578 */
lypinator 0:bb348c97df44 1579
lypinator 0:bb348c97df44 1580 /** @defgroup DMA2D_Exported_Functions_Group4 Peripheral State and Error functions
lypinator 0:bb348c97df44 1581 * @brief Peripheral State functions
lypinator 0:bb348c97df44 1582 *
lypinator 0:bb348c97df44 1583 @verbatim
lypinator 0:bb348c97df44 1584 ===============================================================================
lypinator 0:bb348c97df44 1585 ##### Peripheral State and Errors functions #####
lypinator 0:bb348c97df44 1586 ===============================================================================
lypinator 0:bb348c97df44 1587 [..]
lypinator 0:bb348c97df44 1588 This subsection provides functions allowing to :
lypinator 0:bb348c97df44 1589 (+) Get the DMA2D state
lypinator 0:bb348c97df44 1590 (+) Get the DMA2D error code
lypinator 0:bb348c97df44 1591
lypinator 0:bb348c97df44 1592 @endverbatim
lypinator 0:bb348c97df44 1593 * @{
lypinator 0:bb348c97df44 1594 */
lypinator 0:bb348c97df44 1595
lypinator 0:bb348c97df44 1596 /**
lypinator 0:bb348c97df44 1597 * @brief Return the DMA2D state
lypinator 0:bb348c97df44 1598 * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 1599 * the configuration information for the DMA2D.
lypinator 0:bb348c97df44 1600 * @retval HAL state
lypinator 0:bb348c97df44 1601 */
lypinator 0:bb348c97df44 1602 HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d)
lypinator 0:bb348c97df44 1603 {
lypinator 0:bb348c97df44 1604 return hdma2d->State;
lypinator 0:bb348c97df44 1605 }
lypinator 0:bb348c97df44 1606
lypinator 0:bb348c97df44 1607 /**
lypinator 0:bb348c97df44 1608 * @brief Return the DMA2D error code
lypinator 0:bb348c97df44 1609 * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 1610 * the configuration information for DMA2D.
lypinator 0:bb348c97df44 1611 * @retval DMA2D Error Code
lypinator 0:bb348c97df44 1612 */
lypinator 0:bb348c97df44 1613 uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d)
lypinator 0:bb348c97df44 1614 {
lypinator 0:bb348c97df44 1615 return hdma2d->ErrorCode;
lypinator 0:bb348c97df44 1616 }
lypinator 0:bb348c97df44 1617
lypinator 0:bb348c97df44 1618 /**
lypinator 0:bb348c97df44 1619 * @}
lypinator 0:bb348c97df44 1620 */
lypinator 0:bb348c97df44 1621
lypinator 0:bb348c97df44 1622 /**
lypinator 0:bb348c97df44 1623 * @}
lypinator 0:bb348c97df44 1624 */
lypinator 0:bb348c97df44 1625
lypinator 0:bb348c97df44 1626 /** @defgroup DMA2D_Private_Functions DMA2D Private Functions
lypinator 0:bb348c97df44 1627 * @{
lypinator 0:bb348c97df44 1628 */
lypinator 0:bb348c97df44 1629
lypinator 0:bb348c97df44 1630 /**
lypinator 0:bb348c97df44 1631 * @brief Set the DMA2D transfer parameters.
lypinator 0:bb348c97df44 1632 * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 1633 * the configuration information for the specified DMA2D.
lypinator 0:bb348c97df44 1634 * @param pdata The source memory Buffer address
lypinator 0:bb348c97df44 1635 * @param DstAddress The destination memory Buffer address
lypinator 0:bb348c97df44 1636 * @param Width The width of data to be transferred from source to destination.
lypinator 0:bb348c97df44 1637 * @param Height The height of data to be transferred from source to destination.
lypinator 0:bb348c97df44 1638 * @retval HAL status
lypinator 0:bb348c97df44 1639 */
lypinator 0:bb348c97df44 1640 static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
lypinator 0:bb348c97df44 1641 {
lypinator 0:bb348c97df44 1642 uint32_t tmp = 0U;
lypinator 0:bb348c97df44 1643 uint32_t tmp1 = 0U;
lypinator 0:bb348c97df44 1644 uint32_t tmp2 = 0U;
lypinator 0:bb348c97df44 1645 uint32_t tmp3 = 0U;
lypinator 0:bb348c97df44 1646 uint32_t tmp4 = 0U;
lypinator 0:bb348c97df44 1647
lypinator 0:bb348c97df44 1648 /* Configure DMA2D data size */
lypinator 0:bb348c97df44 1649 MODIFY_REG(hdma2d->Instance->NLR, (DMA2D_NLR_NL|DMA2D_NLR_PL), (Height| (Width << DMA2D_POSITION_NLR_PL)));
lypinator 0:bb348c97df44 1650
lypinator 0:bb348c97df44 1651 /* Configure DMA2D destination address */
lypinator 0:bb348c97df44 1652 WRITE_REG(hdma2d->Instance->OMAR, DstAddress);
lypinator 0:bb348c97df44 1653
lypinator 0:bb348c97df44 1654 /* Register to memory DMA2D mode selected */
lypinator 0:bb348c97df44 1655 if (hdma2d->Init.Mode == DMA2D_R2M)
lypinator 0:bb348c97df44 1656 {
lypinator 0:bb348c97df44 1657 tmp1 = pdata & DMA2D_OCOLR_ALPHA_1;
lypinator 0:bb348c97df44 1658 tmp2 = pdata & DMA2D_OCOLR_RED_1;
lypinator 0:bb348c97df44 1659 tmp3 = pdata & DMA2D_OCOLR_GREEN_1;
lypinator 0:bb348c97df44 1660 tmp4 = pdata & DMA2D_OCOLR_BLUE_1;
lypinator 0:bb348c97df44 1661
lypinator 0:bb348c97df44 1662 /* Prepare the value to be written to the OCOLR register according to the color mode */
lypinator 0:bb348c97df44 1663 if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_ARGB8888)
lypinator 0:bb348c97df44 1664 {
lypinator 0:bb348c97df44 1665 tmp = (tmp3 | tmp2 | tmp1| tmp4);
lypinator 0:bb348c97df44 1666 }
lypinator 0:bb348c97df44 1667 else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_RGB888)
lypinator 0:bb348c97df44 1668 {
lypinator 0:bb348c97df44 1669 tmp = (tmp3 | tmp2 | tmp4);
lypinator 0:bb348c97df44 1670 }
lypinator 0:bb348c97df44 1671 else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_RGB565)
lypinator 0:bb348c97df44 1672 {
lypinator 0:bb348c97df44 1673 tmp2 = (tmp2 >> 19U);
lypinator 0:bb348c97df44 1674 tmp3 = (tmp3 >> 10U);
lypinator 0:bb348c97df44 1675 tmp4 = (tmp4 >> 3U);
lypinator 0:bb348c97df44 1676 tmp = ((tmp3 << 5U) | (tmp2 << 11U) | tmp4);
lypinator 0:bb348c97df44 1677 }
lypinator 0:bb348c97df44 1678 else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_ARGB1555)
lypinator 0:bb348c97df44 1679 {
lypinator 0:bb348c97df44 1680 tmp1 = (tmp1 >> 31U);
lypinator 0:bb348c97df44 1681 tmp2 = (tmp2 >> 19U);
lypinator 0:bb348c97df44 1682 tmp3 = (tmp3 >> 11U);
lypinator 0:bb348c97df44 1683 tmp4 = (tmp4 >> 3U);
lypinator 0:bb348c97df44 1684 tmp = ((tmp3 << 5U) | (tmp2 << 10U) | (tmp1 << 15U) | tmp4);
lypinator 0:bb348c97df44 1685 }
lypinator 0:bb348c97df44 1686 else /* Dhdma2d->Init.ColorMode = DMA2D_OUTPUT_ARGB4444 */
lypinator 0:bb348c97df44 1687 {
lypinator 0:bb348c97df44 1688 tmp1 = (tmp1 >> 28U);
lypinator 0:bb348c97df44 1689 tmp2 = (tmp2 >> 20U);
lypinator 0:bb348c97df44 1690 tmp3 = (tmp3 >> 12U);
lypinator 0:bb348c97df44 1691 tmp4 = (tmp4 >> 4U);
lypinator 0:bb348c97df44 1692 tmp = ((tmp3 << 4U) | (tmp2 << 8U) | (tmp1 << 12U) | tmp4);
lypinator 0:bb348c97df44 1693 }
lypinator 0:bb348c97df44 1694 /* Write to DMA2D OCOLR register */
lypinator 0:bb348c97df44 1695 WRITE_REG(hdma2d->Instance->OCOLR, tmp);
lypinator 0:bb348c97df44 1696 }
lypinator 0:bb348c97df44 1697 else /* M2M, M2M_PFC or M2M_Blending DMA2D Mode */
lypinator 0:bb348c97df44 1698 {
lypinator 0:bb348c97df44 1699 /* Configure DMA2D source address */
lypinator 0:bb348c97df44 1700 WRITE_REG(hdma2d->Instance->FGMAR, pdata);
lypinator 0:bb348c97df44 1701 }
lypinator 0:bb348c97df44 1702 }
lypinator 0:bb348c97df44 1703
lypinator 0:bb348c97df44 1704 /**
lypinator 0:bb348c97df44 1705 * @}
lypinator 0:bb348c97df44 1706 */
lypinator 0:bb348c97df44 1707 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
lypinator 0:bb348c97df44 1708 #endif /* HAL_DMA2D_MODULE_ENABLED */
lypinator 0:bb348c97df44 1709 /**
lypinator 0:bb348c97df44 1710 * @}
lypinator 0:bb348c97df44 1711 */
lypinator 0:bb348c97df44 1712
lypinator 0:bb348c97df44 1713 /**
lypinator 0:bb348c97df44 1714 * @}
lypinator 0:bb348c97df44 1715 */
lypinator 0:bb348c97df44 1716
lypinator 0:bb348c97df44 1717 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/