Thomas Lyp / DevLibMemoryController

Initial commit

Dependencies:   FastPWM

mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dma.h@0:bb348c97df44, 2020-09-16 (annotated)

Committer:
lypinator
Date:
Wed Sep 16 01:11:49 2020 +0000
Revision:
0:bb348c97df44
Added PWM

Who changed what in which revision?

UserRevisionLine numberNew contents of line
lypinator 0:bb348c97df44 1 /**
lypinator 0:bb348c97df44 2 ******************************************************************************
lypinator 0:bb348c97df44 3 * @file stm32f4xx_hal_dma.h
lypinator 0:bb348c97df44 4 * @author MCD Application Team
lypinator 0:bb348c97df44 5 * @brief Header file of DMA HAL module.
lypinator 0:bb348c97df44 6 ******************************************************************************
lypinator 0:bb348c97df44 7 * @attention
lypinator 0:bb348c97df44 8 *
lypinator 0:bb348c97df44 9 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
lypinator 0:bb348c97df44 10 *
lypinator 0:bb348c97df44 11 * Redistribution and use in source and binary forms, with or without modification,
lypinator 0:bb348c97df44 12 * are permitted provided that the following conditions are met:
lypinator 0:bb348c97df44 13 * 1. Redistributions of source code must retain the above copyright notice,
lypinator 0:bb348c97df44 14 * this list of conditions and the following disclaimer.
lypinator 0:bb348c97df44 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
lypinator 0:bb348c97df44 16 * this list of conditions and the following disclaimer in the documentation
lypinator 0:bb348c97df44 17 * and/or other materials provided with the distribution.
lypinator 0:bb348c97df44 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
lypinator 0:bb348c97df44 19 * may be used to endorse or promote products derived from this software
lypinator 0:bb348c97df44 20 * without specific prior written permission.
lypinator 0:bb348c97df44 21 *
lypinator 0:bb348c97df44 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
lypinator 0:bb348c97df44 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
lypinator 0:bb348c97df44 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
lypinator 0:bb348c97df44 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
lypinator 0:bb348c97df44 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
lypinator 0:bb348c97df44 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
lypinator 0:bb348c97df44 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
lypinator 0:bb348c97df44 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
lypinator 0:bb348c97df44 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
lypinator 0:bb348c97df44 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
lypinator 0:bb348c97df44 32 *
lypinator 0:bb348c97df44 33 ******************************************************************************
lypinator 0:bb348c97df44 34 */
lypinator 0:bb348c97df44 35
lypinator 0:bb348c97df44 36 /* Define to prevent recursive inclusion -------------------------------------*/
lypinator 0:bb348c97df44 37 #ifndef __STM32F4xx_HAL_DMA_H
lypinator 0:bb348c97df44 38 #define __STM32F4xx_HAL_DMA_H
lypinator 0:bb348c97df44 39
lypinator 0:bb348c97df44 40 #ifdef __cplusplus
lypinator 0:bb348c97df44 41 extern "C" {
lypinator 0:bb348c97df44 42 #endif
lypinator 0:bb348c97df44 43
lypinator 0:bb348c97df44 44 /* Includes ------------------------------------------------------------------*/
lypinator 0:bb348c97df44 45 #include "stm32f4xx_hal_def.h"
lypinator 0:bb348c97df44 46
lypinator 0:bb348c97df44 47 /** @addtogroup STM32F4xx_HAL_Driver
lypinator 0:bb348c97df44 48 * @{
lypinator 0:bb348c97df44 49 */
lypinator 0:bb348c97df44 50
lypinator 0:bb348c97df44 51 /** @addtogroup DMA
lypinator 0:bb348c97df44 52 * @{
lypinator 0:bb348c97df44 53 */
lypinator 0:bb348c97df44 54
lypinator 0:bb348c97df44 55 /* Exported types ------------------------------------------------------------*/
lypinator 0:bb348c97df44 56
lypinator 0:bb348c97df44 57 /** @defgroup DMA_Exported_Types DMA Exported Types
lypinator 0:bb348c97df44 58 * @brief DMA Exported Types
lypinator 0:bb348c97df44 59 * @{
lypinator 0:bb348c97df44 60 */
lypinator 0:bb348c97df44 61
lypinator 0:bb348c97df44 62 /**
lypinator 0:bb348c97df44 63 * @brief DMA Configuration Structure definition
lypinator 0:bb348c97df44 64 */
lypinator 0:bb348c97df44 65 typedef struct
lypinator 0:bb348c97df44 66 {
lypinator 0:bb348c97df44 67 uint32_t Channel; /*!< Specifies the channel used for the specified stream.
lypinator 0:bb348c97df44 68 This parameter can be a value of @ref DMA_Channel_selection */
lypinator 0:bb348c97df44 69
lypinator 0:bb348c97df44 70 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
lypinator 0:bb348c97df44 71 from memory to memory or from peripheral to memory.
lypinator 0:bb348c97df44 72 This parameter can be a value of @ref DMA_Data_transfer_direction */
lypinator 0:bb348c97df44 73
lypinator 0:bb348c97df44 74 uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
lypinator 0:bb348c97df44 75 This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
lypinator 0:bb348c97df44 76
lypinator 0:bb348c97df44 77 uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
lypinator 0:bb348c97df44 78 This parameter can be a value of @ref DMA_Memory_incremented_mode */
lypinator 0:bb348c97df44 79
lypinator 0:bb348c97df44 80 uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
lypinator 0:bb348c97df44 81 This parameter can be a value of @ref DMA_Peripheral_data_size */
lypinator 0:bb348c97df44 82
lypinator 0:bb348c97df44 83 uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
lypinator 0:bb348c97df44 84 This parameter can be a value of @ref DMA_Memory_data_size */
lypinator 0:bb348c97df44 85
lypinator 0:bb348c97df44 86 uint32_t Mode; /*!< Specifies the operation mode of the DMAy Streamx.
lypinator 0:bb348c97df44 87 This parameter can be a value of @ref DMA_mode
lypinator 0:bb348c97df44 88 @note The circular buffer mode cannot be used if the memory-to-memory
lypinator 0:bb348c97df44 89 data transfer is configured on the selected Stream */
lypinator 0:bb348c97df44 90
lypinator 0:bb348c97df44 91 uint32_t Priority; /*!< Specifies the software priority for the DMAy Streamx.
lypinator 0:bb348c97df44 92 This parameter can be a value of @ref DMA_Priority_level */
lypinator 0:bb348c97df44 93
lypinator 0:bb348c97df44 94 uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream.
lypinator 0:bb348c97df44 95 This parameter can be a value of @ref DMA_FIFO_direct_mode
lypinator 0:bb348c97df44 96 @note The Direct mode (FIFO mode disabled) cannot be used if the
lypinator 0:bb348c97df44 97 memory-to-memory data transfer is configured on the selected stream */
lypinator 0:bb348c97df44 98
lypinator 0:bb348c97df44 99 uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level.
lypinator 0:bb348c97df44 100 This parameter can be a value of @ref DMA_FIFO_threshold_level */
lypinator 0:bb348c97df44 101
lypinator 0:bb348c97df44 102 uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers.
lypinator 0:bb348c97df44 103 It specifies the amount of data to be transferred in a single non interruptible
lypinator 0:bb348c97df44 104 transaction.
lypinator 0:bb348c97df44 105 This parameter can be a value of @ref DMA_Memory_burst
lypinator 0:bb348c97df44 106 @note The burst mode is possible only if the address Increment mode is enabled. */
lypinator 0:bb348c97df44 107
lypinator 0:bb348c97df44 108 uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers.
lypinator 0:bb348c97df44 109 It specifies the amount of data to be transferred in a single non interruptible
lypinator 0:bb348c97df44 110 transaction.
lypinator 0:bb348c97df44 111 This parameter can be a value of @ref DMA_Peripheral_burst
lypinator 0:bb348c97df44 112 @note The burst mode is possible only if the address Increment mode is enabled. */
lypinator 0:bb348c97df44 113 }DMA_InitTypeDef;
lypinator 0:bb348c97df44 114
lypinator 0:bb348c97df44 115
lypinator 0:bb348c97df44 116 /**
lypinator 0:bb348c97df44 117 * @brief HAL DMA State structures definition
lypinator 0:bb348c97df44 118 */
lypinator 0:bb348c97df44 119 typedef enum
lypinator 0:bb348c97df44 120 {
lypinator 0:bb348c97df44 121 HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */
lypinator 0:bb348c97df44 122 HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */
lypinator 0:bb348c97df44 123 HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */
lypinator 0:bb348c97df44 124 HAL_DMA_STATE_TIMEOUT = 0x03U, /*!< DMA timeout state */
lypinator 0:bb348c97df44 125 HAL_DMA_STATE_ERROR = 0x04U, /*!< DMA error state */
lypinator 0:bb348c97df44 126 HAL_DMA_STATE_ABORT = 0x05U, /*!< DMA Abort state */
lypinator 0:bb348c97df44 127 }HAL_DMA_StateTypeDef;
lypinator 0:bb348c97df44 128
lypinator 0:bb348c97df44 129 /**
lypinator 0:bb348c97df44 130 * @brief HAL DMA Error Code structure definition
lypinator 0:bb348c97df44 131 */
lypinator 0:bb348c97df44 132 typedef enum
lypinator 0:bb348c97df44 133 {
lypinator 0:bb348c97df44 134 HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */
lypinator 0:bb348c97df44 135 HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */
lypinator 0:bb348c97df44 136 }HAL_DMA_LevelCompleteTypeDef;
lypinator 0:bb348c97df44 137
lypinator 0:bb348c97df44 138 /**
lypinator 0:bb348c97df44 139 * @brief HAL DMA Error Code structure definition
lypinator 0:bb348c97df44 140 */
lypinator 0:bb348c97df44 141 typedef enum
lypinator 0:bb348c97df44 142 {
lypinator 0:bb348c97df44 143 HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */
lypinator 0:bb348c97df44 144 HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half Transfer */
lypinator 0:bb348c97df44 145 HAL_DMA_XFER_M1CPLT_CB_ID = 0x02U, /*!< M1 Full Transfer */
lypinator 0:bb348c97df44 146 HAL_DMA_XFER_M1HALFCPLT_CB_ID = 0x03U, /*!< M1 Half Transfer */
lypinator 0:bb348c97df44 147 HAL_DMA_XFER_ERROR_CB_ID = 0x04U, /*!< Error */
lypinator 0:bb348c97df44 148 HAL_DMA_XFER_ABORT_CB_ID = 0x05U, /*!< Abort */
lypinator 0:bb348c97df44 149 HAL_DMA_XFER_ALL_CB_ID = 0x06U /*!< All */
lypinator 0:bb348c97df44 150 }HAL_DMA_CallbackIDTypeDef;
lypinator 0:bb348c97df44 151
lypinator 0:bb348c97df44 152 /**
lypinator 0:bb348c97df44 153 * @brief DMA handle Structure definition
lypinator 0:bb348c97df44 154 */
lypinator 0:bb348c97df44 155 typedef struct __DMA_HandleTypeDef
lypinator 0:bb348c97df44 156 {
lypinator 0:bb348c97df44 157 DMA_Stream_TypeDef *Instance; /*!< Register base address */
lypinator 0:bb348c97df44 158
lypinator 0:bb348c97df44 159 DMA_InitTypeDef Init; /*!< DMA communication parameters */
lypinator 0:bb348c97df44 160
lypinator 0:bb348c97df44 161 HAL_LockTypeDef Lock; /*!< DMA locking object */
lypinator 0:bb348c97df44 162
lypinator 0:bb348c97df44 163 __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
lypinator 0:bb348c97df44 164
lypinator 0:bb348c97df44 165 void *Parent; /*!< Parent object state */
lypinator 0:bb348c97df44 166
lypinator 0:bb348c97df44 167 void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */
lypinator 0:bb348c97df44 168
lypinator 0:bb348c97df44 169 void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */
lypinator 0:bb348c97df44 170
lypinator 0:bb348c97df44 171 void (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete Memory1 callback */
lypinator 0:bb348c97df44 172
lypinator 0:bb348c97df44 173 void (* XferM1HalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Half complete Memory1 callback */
lypinator 0:bb348c97df44 174
lypinator 0:bb348c97df44 175 void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
lypinator 0:bb348c97df44 176
lypinator 0:bb348c97df44 177 void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Abort callback */
lypinator 0:bb348c97df44 178
lypinator 0:bb348c97df44 179 __IO uint32_t ErrorCode; /*!< DMA Error code */
lypinator 0:bb348c97df44 180
lypinator 0:bb348c97df44 181 uint32_t StreamBaseAddress; /*!< DMA Stream Base Address */
lypinator 0:bb348c97df44 182
lypinator 0:bb348c97df44 183 uint32_t StreamIndex; /*!< DMA Stream Index */
lypinator 0:bb348c97df44 184
lypinator 0:bb348c97df44 185 }DMA_HandleTypeDef;
lypinator 0:bb348c97df44 186
lypinator 0:bb348c97df44 187 /**
lypinator 0:bb348c97df44 188 * @}
lypinator 0:bb348c97df44 189 */
lypinator 0:bb348c97df44 190
lypinator 0:bb348c97df44 191 /* Exported constants --------------------------------------------------------*/
lypinator 0:bb348c97df44 192
lypinator 0:bb348c97df44 193 /** @defgroup DMA_Exported_Constants DMA Exported Constants
lypinator 0:bb348c97df44 194 * @brief DMA Exported constants
lypinator 0:bb348c97df44 195 * @{
lypinator 0:bb348c97df44 196 */
lypinator 0:bb348c97df44 197
lypinator 0:bb348c97df44 198 /** @defgroup DMA_Error_Code DMA Error Code
lypinator 0:bb348c97df44 199 * @brief DMA Error Code
lypinator 0:bb348c97df44 200 * @{
lypinator 0:bb348c97df44 201 */
lypinator 0:bb348c97df44 202 #define HAL_DMA_ERROR_NONE 0x00000000U /*!< No error */
lypinator 0:bb348c97df44 203 #define HAL_DMA_ERROR_TE 0x00000001U /*!< Transfer error */
lypinator 0:bb348c97df44 204 #define HAL_DMA_ERROR_FE 0x00000002U /*!< FIFO error */
lypinator 0:bb348c97df44 205 #define HAL_DMA_ERROR_DME 0x00000004U /*!< Direct Mode error */
lypinator 0:bb348c97df44 206 #define HAL_DMA_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */
lypinator 0:bb348c97df44 207 #define HAL_DMA_ERROR_PARAM 0x00000040U /*!< Parameter error */
lypinator 0:bb348c97df44 208 #define HAL_DMA_ERROR_NO_XFER 0x00000080U /*!< Abort requested with no Xfer ongoing */
lypinator 0:bb348c97df44 209 #define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U /*!< Not supported mode */
lypinator 0:bb348c97df44 210 /**
lypinator 0:bb348c97df44 211 * @}
lypinator 0:bb348c97df44 212 */
lypinator 0:bb348c97df44 213
lypinator 0:bb348c97df44 214 /** @defgroup DMA_Channel_selection DMA Channel selection
lypinator 0:bb348c97df44 215 * @brief DMA channel selection
lypinator 0:bb348c97df44 216 * @{
lypinator 0:bb348c97df44 217 */
lypinator 0:bb348c97df44 218 #define DMA_CHANNEL_0 0x00000000U /*!< DMA Channel 0 */
lypinator 0:bb348c97df44 219 #define DMA_CHANNEL_1 0x02000000U /*!< DMA Channel 1 */
lypinator 0:bb348c97df44 220 #define DMA_CHANNEL_2 0x04000000U /*!< DMA Channel 2 */
lypinator 0:bb348c97df44 221 #define DMA_CHANNEL_3 0x06000000U /*!< DMA Channel 3 */
lypinator 0:bb348c97df44 222 #define DMA_CHANNEL_4 0x08000000U /*!< DMA Channel 4 */
lypinator 0:bb348c97df44 223 #define DMA_CHANNEL_5 0x0A000000U /*!< DMA Channel 5 */
lypinator 0:bb348c97df44 224 #define DMA_CHANNEL_6 0x0C000000U /*!< DMA Channel 6 */
lypinator 0:bb348c97df44 225 #define DMA_CHANNEL_7 0x0E000000U /*!< DMA Channel 7 */
lypinator 0:bb348c97df44 226 #if defined (DMA_SxCR_CHSEL_3)
lypinator 0:bb348c97df44 227 #define DMA_CHANNEL_8 0x10000000U /*!< DMA Channel 8 */
lypinator 0:bb348c97df44 228 #define DMA_CHANNEL_9 0x12000000U /*!< DMA Channel 9 */
lypinator 0:bb348c97df44 229 #define DMA_CHANNEL_10 0x14000000U /*!< DMA Channel 10 */
lypinator 0:bb348c97df44 230 #define DMA_CHANNEL_11 0x16000000U /*!< DMA Channel 11 */
lypinator 0:bb348c97df44 231 #define DMA_CHANNEL_12 0x18000000U /*!< DMA Channel 12 */
lypinator 0:bb348c97df44 232 #define DMA_CHANNEL_13 0x1A000000U /*!< DMA Channel 13 */
lypinator 0:bb348c97df44 233 #define DMA_CHANNEL_14 0x1C000000U /*!< DMA Channel 14 */
lypinator 0:bb348c97df44 234 #define DMA_CHANNEL_15 0x1E000000U /*!< DMA Channel 15 */
lypinator 0:bb348c97df44 235 #endif /* DMA_SxCR_CHSEL_3 */
lypinator 0:bb348c97df44 236 /**
lypinator 0:bb348c97df44 237 * @}
lypinator 0:bb348c97df44 238 */
lypinator 0:bb348c97df44 239
lypinator 0:bb348c97df44 240 /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
lypinator 0:bb348c97df44 241 * @brief DMA data transfer direction
lypinator 0:bb348c97df44 242 * @{
lypinator 0:bb348c97df44 243 */
lypinator 0:bb348c97df44 244 #define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */
lypinator 0:bb348c97df44 245 #define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_SxCR_DIR_0) /*!< Memory to peripheral direction */
lypinator 0:bb348c97df44 246 #define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_SxCR_DIR_1) /*!< Memory to memory direction */
lypinator 0:bb348c97df44 247 /**
lypinator 0:bb348c97df44 248 * @}
lypinator 0:bb348c97df44 249 */
lypinator 0:bb348c97df44 250
lypinator 0:bb348c97df44 251 /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
lypinator 0:bb348c97df44 252 * @brief DMA peripheral incremented mode
lypinator 0:bb348c97df44 253 * @{
lypinator 0:bb348c97df44 254 */
lypinator 0:bb348c97df44 255 #define DMA_PINC_ENABLE ((uint32_t)DMA_SxCR_PINC) /*!< Peripheral increment mode enable */
lypinator 0:bb348c97df44 256 #define DMA_PINC_DISABLE 0x00000000U /*!< Peripheral increment mode disable */
lypinator 0:bb348c97df44 257 /**
lypinator 0:bb348c97df44 258 * @}
lypinator 0:bb348c97df44 259 */
lypinator 0:bb348c97df44 260
lypinator 0:bb348c97df44 261 /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
lypinator 0:bb348c97df44 262 * @brief DMA memory incremented mode
lypinator 0:bb348c97df44 263 * @{
lypinator 0:bb348c97df44 264 */
lypinator 0:bb348c97df44 265 #define DMA_MINC_ENABLE ((uint32_t)DMA_SxCR_MINC) /*!< Memory increment mode enable */
lypinator 0:bb348c97df44 266 #define DMA_MINC_DISABLE 0x00000000U /*!< Memory increment mode disable */
lypinator 0:bb348c97df44 267 /**
lypinator 0:bb348c97df44 268 * @}
lypinator 0:bb348c97df44 269 */
lypinator 0:bb348c97df44 270
lypinator 0:bb348c97df44 271 /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
lypinator 0:bb348c97df44 272 * @brief DMA peripheral data size
lypinator 0:bb348c97df44 273 * @{
lypinator 0:bb348c97df44 274 */
lypinator 0:bb348c97df44 275 #define DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment: Byte */
lypinator 0:bb348c97df44 276 #define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */
lypinator 0:bb348c97df44 277 #define DMA_PDATAALIGN_WORD ((uint32_t)DMA_SxCR_PSIZE_1) /*!< Peripheral data alignment: Word */
lypinator 0:bb348c97df44 278 /**
lypinator 0:bb348c97df44 279 * @}
lypinator 0:bb348c97df44 280 */
lypinator 0:bb348c97df44 281
lypinator 0:bb348c97df44 282 /** @defgroup DMA_Memory_data_size DMA Memory data size
lypinator 0:bb348c97df44 283 * @brief DMA memory data size
lypinator 0:bb348c97df44 284 * @{
lypinator 0:bb348c97df44 285 */
lypinator 0:bb348c97df44 286 #define DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment: Byte */
lypinator 0:bb348c97df44 287 #define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_MSIZE_0) /*!< Memory data alignment: HalfWord */
lypinator 0:bb348c97df44 288 #define DMA_MDATAALIGN_WORD ((uint32_t)DMA_SxCR_MSIZE_1) /*!< Memory data alignment: Word */
lypinator 0:bb348c97df44 289 /**
lypinator 0:bb348c97df44 290 * @}
lypinator 0:bb348c97df44 291 */
lypinator 0:bb348c97df44 292
lypinator 0:bb348c97df44 293 /** @defgroup DMA_mode DMA mode
lypinator 0:bb348c97df44 294 * @brief DMA mode
lypinator 0:bb348c97df44 295 * @{
lypinator 0:bb348c97df44 296 */
lypinator 0:bb348c97df44 297 #define DMA_NORMAL 0x00000000U /*!< Normal mode */
lypinator 0:bb348c97df44 298 #define DMA_CIRCULAR ((uint32_t)DMA_SxCR_CIRC) /*!< Circular mode */
lypinator 0:bb348c97df44 299 #define DMA_PFCTRL ((uint32_t)DMA_SxCR_PFCTRL) /*!< Peripheral flow control mode */
lypinator 0:bb348c97df44 300 /**
lypinator 0:bb348c97df44 301 * @}
lypinator 0:bb348c97df44 302 */
lypinator 0:bb348c97df44 303
lypinator 0:bb348c97df44 304 /** @defgroup DMA_Priority_level DMA Priority level
lypinator 0:bb348c97df44 305 * @brief DMA priority levels
lypinator 0:bb348c97df44 306 * @{
lypinator 0:bb348c97df44 307 */
lypinator 0:bb348c97df44 308 #define DMA_PRIORITY_LOW 0x00000000U /*!< Priority level: Low */
lypinator 0:bb348c97df44 309 #define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_SxCR_PL_0) /*!< Priority level: Medium */
lypinator 0:bb348c97df44 310 #define DMA_PRIORITY_HIGH ((uint32_t)DMA_SxCR_PL_1) /*!< Priority level: High */
lypinator 0:bb348c97df44 311 #define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_SxCR_PL) /*!< Priority level: Very High */
lypinator 0:bb348c97df44 312 /**
lypinator 0:bb348c97df44 313 * @}
lypinator 0:bb348c97df44 314 */
lypinator 0:bb348c97df44 315
lypinator 0:bb348c97df44 316 /** @defgroup DMA_FIFO_direct_mode DMA FIFO direct mode
lypinator 0:bb348c97df44 317 * @brief DMA FIFO direct mode
lypinator 0:bb348c97df44 318 * @{
lypinator 0:bb348c97df44 319 */
lypinator 0:bb348c97df44 320 #define DMA_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable */
lypinator 0:bb348c97df44 321 #define DMA_FIFOMODE_ENABLE ((uint32_t)DMA_SxFCR_DMDIS) /*!< FIFO mode enable */
lypinator 0:bb348c97df44 322 /**
lypinator 0:bb348c97df44 323 * @}
lypinator 0:bb348c97df44 324 */
lypinator 0:bb348c97df44 325
lypinator 0:bb348c97df44 326 /** @defgroup DMA_FIFO_threshold_level DMA FIFO threshold level
lypinator 0:bb348c97df44 327 * @brief DMA FIFO level
lypinator 0:bb348c97df44 328 * @{
lypinator 0:bb348c97df44 329 */
lypinator 0:bb348c97df44 330 #define DMA_FIFO_THRESHOLD_1QUARTERFULL 0x00000000U /*!< FIFO threshold 1 quart full configuration */
lypinator 0:bb348c97df44 331 #define DMA_FIFO_THRESHOLD_HALFFULL ((uint32_t)DMA_SxFCR_FTH_0) /*!< FIFO threshold half full configuration */
lypinator 0:bb348c97df44 332 #define DMA_FIFO_THRESHOLD_3QUARTERSFULL ((uint32_t)DMA_SxFCR_FTH_1) /*!< FIFO threshold 3 quarts full configuration */
lypinator 0:bb348c97df44 333 #define DMA_FIFO_THRESHOLD_FULL ((uint32_t)DMA_SxFCR_FTH) /*!< FIFO threshold full configuration */
lypinator 0:bb348c97df44 334 /**
lypinator 0:bb348c97df44 335 * @}
lypinator 0:bb348c97df44 336 */
lypinator 0:bb348c97df44 337
lypinator 0:bb348c97df44 338 /** @defgroup DMA_Memory_burst DMA Memory burst
lypinator 0:bb348c97df44 339 * @brief DMA memory burst
lypinator 0:bb348c97df44 340 * @{
lypinator 0:bb348c97df44 341 */
lypinator 0:bb348c97df44 342 #define DMA_MBURST_SINGLE 0x00000000U
lypinator 0:bb348c97df44 343 #define DMA_MBURST_INC4 ((uint32_t)DMA_SxCR_MBURST_0)
lypinator 0:bb348c97df44 344 #define DMA_MBURST_INC8 ((uint32_t)DMA_SxCR_MBURST_1)
lypinator 0:bb348c97df44 345 #define DMA_MBURST_INC16 ((uint32_t)DMA_SxCR_MBURST)
lypinator 0:bb348c97df44 346 /**
lypinator 0:bb348c97df44 347 * @}
lypinator 0:bb348c97df44 348 */
lypinator 0:bb348c97df44 349
lypinator 0:bb348c97df44 350 /** @defgroup DMA_Peripheral_burst DMA Peripheral burst
lypinator 0:bb348c97df44 351 * @brief DMA peripheral burst
lypinator 0:bb348c97df44 352 * @{
lypinator 0:bb348c97df44 353 */
lypinator 0:bb348c97df44 354 #define DMA_PBURST_SINGLE 0x00000000U
lypinator 0:bb348c97df44 355 #define DMA_PBURST_INC4 ((uint32_t)DMA_SxCR_PBURST_0)
lypinator 0:bb348c97df44 356 #define DMA_PBURST_INC8 ((uint32_t)DMA_SxCR_PBURST_1)
lypinator 0:bb348c97df44 357 #define DMA_PBURST_INC16 ((uint32_t)DMA_SxCR_PBURST)
lypinator 0:bb348c97df44 358 /**
lypinator 0:bb348c97df44 359 * @}
lypinator 0:bb348c97df44 360 */
lypinator 0:bb348c97df44 361
lypinator 0:bb348c97df44 362 /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
lypinator 0:bb348c97df44 363 * @brief DMA interrupts definition
lypinator 0:bb348c97df44 364 * @{
lypinator 0:bb348c97df44 365 */
lypinator 0:bb348c97df44 366 #define DMA_IT_TC ((uint32_t)DMA_SxCR_TCIE)
lypinator 0:bb348c97df44 367 #define DMA_IT_HT ((uint32_t)DMA_SxCR_HTIE)
lypinator 0:bb348c97df44 368 #define DMA_IT_TE ((uint32_t)DMA_SxCR_TEIE)
lypinator 0:bb348c97df44 369 #define DMA_IT_DME ((uint32_t)DMA_SxCR_DMEIE)
lypinator 0:bb348c97df44 370 #define DMA_IT_FE 0x00000080U
lypinator 0:bb348c97df44 371 /**
lypinator 0:bb348c97df44 372 * @}
lypinator 0:bb348c97df44 373 */
lypinator 0:bb348c97df44 374
lypinator 0:bb348c97df44 375 /** @defgroup DMA_flag_definitions DMA flag definitions
lypinator 0:bb348c97df44 376 * @brief DMA flag definitions
lypinator 0:bb348c97df44 377 * @{
lypinator 0:bb348c97df44 378 */
lypinator 0:bb348c97df44 379 #define DMA_FLAG_FEIF0_4 0x00000001U
lypinator 0:bb348c97df44 380 #define DMA_FLAG_DMEIF0_4 0x00000004U
lypinator 0:bb348c97df44 381 #define DMA_FLAG_TEIF0_4 0x00000008U
lypinator 0:bb348c97df44 382 #define DMA_FLAG_HTIF0_4 0x00000010U
lypinator 0:bb348c97df44 383 #define DMA_FLAG_TCIF0_4 0x00000020U
lypinator 0:bb348c97df44 384 #define DMA_FLAG_FEIF1_5 0x00000040U
lypinator 0:bb348c97df44 385 #define DMA_FLAG_DMEIF1_5 0x00000100U
lypinator 0:bb348c97df44 386 #define DMA_FLAG_TEIF1_5 0x00000200U
lypinator 0:bb348c97df44 387 #define DMA_FLAG_HTIF1_5 0x00000400U
lypinator 0:bb348c97df44 388 #define DMA_FLAG_TCIF1_5 0x00000800U
lypinator 0:bb348c97df44 389 #define DMA_FLAG_FEIF2_6 0x00010000U
lypinator 0:bb348c97df44 390 #define DMA_FLAG_DMEIF2_6 0x00040000U
lypinator 0:bb348c97df44 391 #define DMA_FLAG_TEIF2_6 0x00080000U
lypinator 0:bb348c97df44 392 #define DMA_FLAG_HTIF2_6 0x00100000U
lypinator 0:bb348c97df44 393 #define DMA_FLAG_TCIF2_6 0x00200000U
lypinator 0:bb348c97df44 394 #define DMA_FLAG_FEIF3_7 0x00400000U
lypinator 0:bb348c97df44 395 #define DMA_FLAG_DMEIF3_7 0x01000000U
lypinator 0:bb348c97df44 396 #define DMA_FLAG_TEIF3_7 0x02000000U
lypinator 0:bb348c97df44 397 #define DMA_FLAG_HTIF3_7 0x04000000U
lypinator 0:bb348c97df44 398 #define DMA_FLAG_TCIF3_7 0x08000000U
lypinator 0:bb348c97df44 399 /**
lypinator 0:bb348c97df44 400 * @}
lypinator 0:bb348c97df44 401 */
lypinator 0:bb348c97df44 402
lypinator 0:bb348c97df44 403 /**
lypinator 0:bb348c97df44 404 * @}
lypinator 0:bb348c97df44 405 */
lypinator 0:bb348c97df44 406
lypinator 0:bb348c97df44 407 /* Exported macro ------------------------------------------------------------*/
lypinator 0:bb348c97df44 408
lypinator 0:bb348c97df44 409 /** @brief Reset DMA handle state
lypinator 0:bb348c97df44 410 * @param __HANDLE__ specifies the DMA handle.
lypinator 0:bb348c97df44 411 * @retval None
lypinator 0:bb348c97df44 412 */
lypinator 0:bb348c97df44 413 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
lypinator 0:bb348c97df44 414
lypinator 0:bb348c97df44 415 /**
lypinator 0:bb348c97df44 416 * @brief Return the current DMA Stream FIFO filled level.
lypinator 0:bb348c97df44 417 * @param __HANDLE__ DMA handle
lypinator 0:bb348c97df44 418 * @retval The FIFO filling state.
lypinator 0:bb348c97df44 419 * - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full
lypinator 0:bb348c97df44 420 * and not empty.
lypinator 0:bb348c97df44 421 * - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full.
lypinator 0:bb348c97df44 422 * - DMA_FIFOStatus_HalfFull: if more than 1 half-full.
lypinator 0:bb348c97df44 423 * - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full.
lypinator 0:bb348c97df44 424 * - DMA_FIFOStatus_Empty: when FIFO is empty
lypinator 0:bb348c97df44 425 * - DMA_FIFOStatus_Full: when FIFO is full
lypinator 0:bb348c97df44 426 */
lypinator 0:bb348c97df44 427 #define __HAL_DMA_GET_FS(__HANDLE__) (((__HANDLE__)->Instance->FCR & (DMA_SxFCR_FS)))
lypinator 0:bb348c97df44 428
lypinator 0:bb348c97df44 429 /**
lypinator 0:bb348c97df44 430 * @brief Enable the specified DMA Stream.
lypinator 0:bb348c97df44 431 * @param __HANDLE__ DMA handle
lypinator 0:bb348c97df44 432 * @retval None
lypinator 0:bb348c97df44 433 */
lypinator 0:bb348c97df44 434 #define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA_SxCR_EN)
lypinator 0:bb348c97df44 435
lypinator 0:bb348c97df44 436 /**
lypinator 0:bb348c97df44 437 * @brief Disable the specified DMA Stream.
lypinator 0:bb348c97df44 438 * @param __HANDLE__ DMA handle
lypinator 0:bb348c97df44 439 * @retval None
lypinator 0:bb348c97df44 440 */
lypinator 0:bb348c97df44 441 #define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~DMA_SxCR_EN)
lypinator 0:bb348c97df44 442
lypinator 0:bb348c97df44 443 /* Interrupt & Flag management */
lypinator 0:bb348c97df44 444
lypinator 0:bb348c97df44 445 /**
lypinator 0:bb348c97df44 446 * @brief Return the current DMA Stream transfer complete flag.
lypinator 0:bb348c97df44 447 * @param __HANDLE__ DMA handle
lypinator 0:bb348c97df44 448 * @retval The specified transfer complete flag index.
lypinator 0:bb348c97df44 449 */
lypinator 0:bb348c97df44 450 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
lypinator 0:bb348c97df44 451 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\
lypinator 0:bb348c97df44 452 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\
lypinator 0:bb348c97df44 453 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\
lypinator 0:bb348c97df44 454 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\
lypinator 0:bb348c97df44 455 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\
lypinator 0:bb348c97df44 456 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\
lypinator 0:bb348c97df44 457 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\
lypinator 0:bb348c97df44 458 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\
lypinator 0:bb348c97df44 459 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\
lypinator 0:bb348c97df44 460 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\
lypinator 0:bb348c97df44 461 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\
lypinator 0:bb348c97df44 462 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\
lypinator 0:bb348c97df44 463 DMA_FLAG_TCIF3_7)
lypinator 0:bb348c97df44 464
lypinator 0:bb348c97df44 465 /**
lypinator 0:bb348c97df44 466 * @brief Return the current DMA Stream half transfer complete flag.
lypinator 0:bb348c97df44 467 * @param __HANDLE__ DMA handle
lypinator 0:bb348c97df44 468 * @retval The specified half transfer complete flag index.
lypinator 0:bb348c97df44 469 */
lypinator 0:bb348c97df44 470 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
lypinator 0:bb348c97df44 471 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\
lypinator 0:bb348c97df44 472 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\
lypinator 0:bb348c97df44 473 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\
lypinator 0:bb348c97df44 474 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\
lypinator 0:bb348c97df44 475 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\
lypinator 0:bb348c97df44 476 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\
lypinator 0:bb348c97df44 477 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\
lypinator 0:bb348c97df44 478 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\
lypinator 0:bb348c97df44 479 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\
lypinator 0:bb348c97df44 480 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\
lypinator 0:bb348c97df44 481 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\
lypinator 0:bb348c97df44 482 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\
lypinator 0:bb348c97df44 483 DMA_FLAG_HTIF3_7)
lypinator 0:bb348c97df44 484
lypinator 0:bb348c97df44 485 /**
lypinator 0:bb348c97df44 486 * @brief Return the current DMA Stream transfer error flag.
lypinator 0:bb348c97df44 487 * @param __HANDLE__ DMA handle
lypinator 0:bb348c97df44 488 * @retval The specified transfer error flag index.
lypinator 0:bb348c97df44 489 */
lypinator 0:bb348c97df44 490 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
lypinator 0:bb348c97df44 491 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\
lypinator 0:bb348c97df44 492 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\
lypinator 0:bb348c97df44 493 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\
lypinator 0:bb348c97df44 494 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\
lypinator 0:bb348c97df44 495 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\
lypinator 0:bb348c97df44 496 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\
lypinator 0:bb348c97df44 497 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\
lypinator 0:bb348c97df44 498 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\
lypinator 0:bb348c97df44 499 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\
lypinator 0:bb348c97df44 500 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\
lypinator 0:bb348c97df44 501 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\
lypinator 0:bb348c97df44 502 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\
lypinator 0:bb348c97df44 503 DMA_FLAG_TEIF3_7)
lypinator 0:bb348c97df44 504
lypinator 0:bb348c97df44 505 /**
lypinator 0:bb348c97df44 506 * @brief Return the current DMA Stream FIFO error flag.
lypinator 0:bb348c97df44 507 * @param __HANDLE__ DMA handle
lypinator 0:bb348c97df44 508 * @retval The specified FIFO error flag index.
lypinator 0:bb348c97df44 509 */
lypinator 0:bb348c97df44 510 #define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)\
lypinator 0:bb348c97df44 511 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_FEIF0_4 :\
lypinator 0:bb348c97df44 512 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_FEIF0_4 :\
lypinator 0:bb348c97df44 513 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_FEIF0_4 :\
lypinator 0:bb348c97df44 514 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_FEIF0_4 :\
lypinator 0:bb348c97df44 515 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_FEIF1_5 :\
lypinator 0:bb348c97df44 516 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_FEIF1_5 :\
lypinator 0:bb348c97df44 517 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\
lypinator 0:bb348c97df44 518 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_FEIF1_5 :\
lypinator 0:bb348c97df44 519 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_FEIF2_6 :\
lypinator 0:bb348c97df44 520 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_FEIF2_6 :\
lypinator 0:bb348c97df44 521 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_FEIF2_6 :\
lypinator 0:bb348c97df44 522 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_FEIF2_6 :\
lypinator 0:bb348c97df44 523 DMA_FLAG_FEIF3_7)
lypinator 0:bb348c97df44 524
lypinator 0:bb348c97df44 525 /**
lypinator 0:bb348c97df44 526 * @brief Return the current DMA Stream direct mode error flag.
lypinator 0:bb348c97df44 527 * @param __HANDLE__ DMA handle
lypinator 0:bb348c97df44 528 * @retval The specified direct mode error flag index.
lypinator 0:bb348c97df44 529 */
lypinator 0:bb348c97df44 530 #define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)\
lypinator 0:bb348c97df44 531 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_DMEIF0_4 :\
lypinator 0:bb348c97df44 532 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_DMEIF0_4 :\
lypinator 0:bb348c97df44 533 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_DMEIF0_4 :\
lypinator 0:bb348c97df44 534 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_DMEIF0_4 :\
lypinator 0:bb348c97df44 535 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_DMEIF1_5 :\
lypinator 0:bb348c97df44 536 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_DMEIF1_5 :\
lypinator 0:bb348c97df44 537 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\
lypinator 0:bb348c97df44 538 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_DMEIF1_5 :\
lypinator 0:bb348c97df44 539 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_DMEIF2_6 :\
lypinator 0:bb348c97df44 540 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_DMEIF2_6 :\
lypinator 0:bb348c97df44 541 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_DMEIF2_6 :\
lypinator 0:bb348c97df44 542 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_DMEIF2_6 :\
lypinator 0:bb348c97df44 543 DMA_FLAG_DMEIF3_7)
lypinator 0:bb348c97df44 544
lypinator 0:bb348c97df44 545 /**
lypinator 0:bb348c97df44 546 * @brief Get the DMA Stream pending flags.
lypinator 0:bb348c97df44 547 * @param __HANDLE__ DMA handle
lypinator 0:bb348c97df44 548 * @param __FLAG__ Get the specified flag.
lypinator 0:bb348c97df44 549 * This parameter can be any combination of the following values:
lypinator 0:bb348c97df44 550 * @arg DMA_FLAG_TCIFx: Transfer complete flag.
lypinator 0:bb348c97df44 551 * @arg DMA_FLAG_HTIFx: Half transfer complete flag.
lypinator 0:bb348c97df44 552 * @arg DMA_FLAG_TEIFx: Transfer error flag.
lypinator 0:bb348c97df44 553 * @arg DMA_FLAG_DMEIFx: Direct mode error flag.
lypinator 0:bb348c97df44 554 * @arg DMA_FLAG_FEIFx: FIFO error flag.
lypinator 0:bb348c97df44 555 * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
lypinator 0:bb348c97df44 556 * @retval The state of FLAG (SET or RESET).
lypinator 0:bb348c97df44 557 */
lypinator 0:bb348c97df44 558 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
lypinator 0:bb348c97df44 559 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\
lypinator 0:bb348c97df44 560 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) :\
lypinator 0:bb348c97df44 561 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__)))
lypinator 0:bb348c97df44 562
lypinator 0:bb348c97df44 563 /**
lypinator 0:bb348c97df44 564 * @brief Clear the DMA Stream pending flags.
lypinator 0:bb348c97df44 565 * @param __HANDLE__ DMA handle
lypinator 0:bb348c97df44 566 * @param __FLAG__ specifies the flag to clear.
lypinator 0:bb348c97df44 567 * This parameter can be any combination of the following values:
lypinator 0:bb348c97df44 568 * @arg DMA_FLAG_TCIFx: Transfer complete flag.
lypinator 0:bb348c97df44 569 * @arg DMA_FLAG_HTIFx: Half transfer complete flag.
lypinator 0:bb348c97df44 570 * @arg DMA_FLAG_TEIFx: Transfer error flag.
lypinator 0:bb348c97df44 571 * @arg DMA_FLAG_DMEIFx: Direct mode error flag.
lypinator 0:bb348c97df44 572 * @arg DMA_FLAG_FEIFx: FIFO error flag.
lypinator 0:bb348c97df44 573 * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
lypinator 0:bb348c97df44 574 * @retval None
lypinator 0:bb348c97df44 575 */
lypinator 0:bb348c97df44 576 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
lypinator 0:bb348c97df44 577 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\
lypinator 0:bb348c97df44 578 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\
lypinator 0:bb348c97df44 579 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__)))
lypinator 0:bb348c97df44 580
lypinator 0:bb348c97df44 581 /**
lypinator 0:bb348c97df44 582 * @brief Enable the specified DMA Stream interrupts.
lypinator 0:bb348c97df44 583 * @param __HANDLE__ DMA handle
lypinator 0:bb348c97df44 584 * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.
lypinator 0:bb348c97df44 585 * This parameter can be any combination of the following values:
lypinator 0:bb348c97df44 586 * @arg DMA_IT_TC: Transfer complete interrupt mask.
lypinator 0:bb348c97df44 587 * @arg DMA_IT_HT: Half transfer complete interrupt mask.
lypinator 0:bb348c97df44 588 * @arg DMA_IT_TE: Transfer error interrupt mask.
lypinator 0:bb348c97df44 589 * @arg DMA_IT_FE: FIFO error interrupt mask.
lypinator 0:bb348c97df44 590 * @arg DMA_IT_DME: Direct mode error interrupt.
lypinator 0:bb348c97df44 591 * @retval None
lypinator 0:bb348c97df44 592 */
lypinator 0:bb348c97df44 593 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
lypinator 0:bb348c97df44 594 ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR |= (__INTERRUPT__)))
lypinator 0:bb348c97df44 595
lypinator 0:bb348c97df44 596 /**
lypinator 0:bb348c97df44 597 * @brief Disable the specified DMA Stream interrupts.
lypinator 0:bb348c97df44 598 * @param __HANDLE__ DMA handle
lypinator 0:bb348c97df44 599 * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.
lypinator 0:bb348c97df44 600 * This parameter can be any combination of the following values:
lypinator 0:bb348c97df44 601 * @arg DMA_IT_TC: Transfer complete interrupt mask.
lypinator 0:bb348c97df44 602 * @arg DMA_IT_HT: Half transfer complete interrupt mask.
lypinator 0:bb348c97df44 603 * @arg DMA_IT_TE: Transfer error interrupt mask.
lypinator 0:bb348c97df44 604 * @arg DMA_IT_FE: FIFO error interrupt mask.
lypinator 0:bb348c97df44 605 * @arg DMA_IT_DME: Direct mode error interrupt.
lypinator 0:bb348c97df44 606 * @retval None
lypinator 0:bb348c97df44 607 */
lypinator 0:bb348c97df44 608 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
lypinator 0:bb348c97df44 609 ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR &= ~(__INTERRUPT__)))
lypinator 0:bb348c97df44 610
lypinator 0:bb348c97df44 611 /**
lypinator 0:bb348c97df44 612 * @brief Check whether the specified DMA Stream interrupt is enabled or disabled.
lypinator 0:bb348c97df44 613 * @param __HANDLE__ DMA handle
lypinator 0:bb348c97df44 614 * @param __INTERRUPT__ specifies the DMA interrupt source to check.
lypinator 0:bb348c97df44 615 * This parameter can be one of the following values:
lypinator 0:bb348c97df44 616 * @arg DMA_IT_TC: Transfer complete interrupt mask.
lypinator 0:bb348c97df44 617 * @arg DMA_IT_HT: Half transfer complete interrupt mask.
lypinator 0:bb348c97df44 618 * @arg DMA_IT_TE: Transfer error interrupt mask.
lypinator 0:bb348c97df44 619 * @arg DMA_IT_FE: FIFO error interrupt mask.
lypinator 0:bb348c97df44 620 * @arg DMA_IT_DME: Direct mode error interrupt.
lypinator 0:bb348c97df44 621 * @retval The state of DMA_IT.
lypinator 0:bb348c97df44 622 */
lypinator 0:bb348c97df44 623 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
lypinator 0:bb348c97df44 624 ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) : \
lypinator 0:bb348c97df44 625 ((__HANDLE__)->Instance->FCR & (__INTERRUPT__)))
lypinator 0:bb348c97df44 626
lypinator 0:bb348c97df44 627 /**
lypinator 0:bb348c97df44 628 * @brief Writes the number of data units to be transferred on the DMA Stream.
lypinator 0:bb348c97df44 629 * @param __HANDLE__ DMA handle
lypinator 0:bb348c97df44 630 * @param __COUNTER__ Number of data units to be transferred (from 0 to 65535)
lypinator 0:bb348c97df44 631 * Number of data items depends only on the Peripheral data format.
lypinator 0:bb348c97df44 632 *
lypinator 0:bb348c97df44 633 * @note If Peripheral data format is Bytes: number of data units is equal
lypinator 0:bb348c97df44 634 * to total number of bytes to be transferred.
lypinator 0:bb348c97df44 635 *
lypinator 0:bb348c97df44 636 * @note If Peripheral data format is Half-Word: number of data units is
lypinator 0:bb348c97df44 637 * equal to total number of bytes to be transferred / 2.
lypinator 0:bb348c97df44 638 *
lypinator 0:bb348c97df44 639 * @note If Peripheral data format is Word: number of data units is equal
lypinator 0:bb348c97df44 640 * to total number of bytes to be transferred / 4.
lypinator 0:bb348c97df44 641 *
lypinator 0:bb348c97df44 642 * @retval The number of remaining data units in the current DMAy Streamx transfer.
lypinator 0:bb348c97df44 643 */
lypinator 0:bb348c97df44 644 #define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->NDTR = (uint16_t)(__COUNTER__))
lypinator 0:bb348c97df44 645
lypinator 0:bb348c97df44 646 /**
lypinator 0:bb348c97df44 647 * @brief Returns the number of remaining data units in the current DMAy Streamx transfer.
lypinator 0:bb348c97df44 648 * @param __HANDLE__ DMA handle
lypinator 0:bb348c97df44 649 *
lypinator 0:bb348c97df44 650 * @retval The number of remaining data units in the current DMA Stream transfer.
lypinator 0:bb348c97df44 651 */
lypinator 0:bb348c97df44 652 #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->NDTR)
lypinator 0:bb348c97df44 653
lypinator 0:bb348c97df44 654
lypinator 0:bb348c97df44 655 /* Include DMA HAL Extension module */
lypinator 0:bb348c97df44 656 #include "stm32f4xx_hal_dma_ex.h"
lypinator 0:bb348c97df44 657
lypinator 0:bb348c97df44 658 /* Exported functions --------------------------------------------------------*/
lypinator 0:bb348c97df44 659
lypinator 0:bb348c97df44 660 /** @defgroup DMA_Exported_Functions DMA Exported Functions
lypinator 0:bb348c97df44 661 * @brief DMA Exported functions
lypinator 0:bb348c97df44 662 * @{
lypinator 0:bb348c97df44 663 */
lypinator 0:bb348c97df44 664
lypinator 0:bb348c97df44 665 /** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
lypinator 0:bb348c97df44 666 * @brief Initialization and de-initialization functions
lypinator 0:bb348c97df44 667 * @{
lypinator 0:bb348c97df44 668 */
lypinator 0:bb348c97df44 669 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
lypinator 0:bb348c97df44 670 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma);
lypinator 0:bb348c97df44 671 /**
lypinator 0:bb348c97df44 672 * @}
lypinator 0:bb348c97df44 673 */
lypinator 0:bb348c97df44 674
lypinator 0:bb348c97df44 675 /** @defgroup DMA_Exported_Functions_Group2 I/O operation functions
lypinator 0:bb348c97df44 676 * @brief I/O operation functions
lypinator 0:bb348c97df44 677 * @{
lypinator 0:bb348c97df44 678 */
lypinator 0:bb348c97df44 679 HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
lypinator 0:bb348c97df44 680 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
lypinator 0:bb348c97df44 681 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
lypinator 0:bb348c97df44 682 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
lypinator 0:bb348c97df44 683 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout);
lypinator 0:bb348c97df44 684 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
lypinator 0:bb348c97df44 685 HAL_StatusTypeDef HAL_DMA_CleanCallbacks(DMA_HandleTypeDef *hdma);
lypinator 0:bb348c97df44 686 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma));
lypinator 0:bb348c97df44 687 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
lypinator 0:bb348c97df44 688
lypinator 0:bb348c97df44 689 /**
lypinator 0:bb348c97df44 690 * @}
lypinator 0:bb348c97df44 691 */
lypinator 0:bb348c97df44 692
lypinator 0:bb348c97df44 693 /** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions
lypinator 0:bb348c97df44 694 * @brief Peripheral State functions
lypinator 0:bb348c97df44 695 * @{
lypinator 0:bb348c97df44 696 */
lypinator 0:bb348c97df44 697 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
lypinator 0:bb348c97df44 698 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
lypinator 0:bb348c97df44 699 /**
lypinator 0:bb348c97df44 700 * @}
lypinator 0:bb348c97df44 701 */
lypinator 0:bb348c97df44 702 /**
lypinator 0:bb348c97df44 703 * @}
lypinator 0:bb348c97df44 704 */
lypinator 0:bb348c97df44 705 /* Private Constants -------------------------------------------------------------*/
lypinator 0:bb348c97df44 706 /** @defgroup DMA_Private_Constants DMA Private Constants
lypinator 0:bb348c97df44 707 * @brief DMA private defines and constants
lypinator 0:bb348c97df44 708 * @{
lypinator 0:bb348c97df44 709 */
lypinator 0:bb348c97df44 710 /**
lypinator 0:bb348c97df44 711 * @}
lypinator 0:bb348c97df44 712 */
lypinator 0:bb348c97df44 713
lypinator 0:bb348c97df44 714 /* Private macros ------------------------------------------------------------*/
lypinator 0:bb348c97df44 715 /** @defgroup DMA_Private_Macros DMA Private Macros
lypinator 0:bb348c97df44 716 * @brief DMA private macros
lypinator 0:bb348c97df44 717 * @{
lypinator 0:bb348c97df44 718 */
lypinator 0:bb348c97df44 719 #if defined (DMA_SxCR_CHSEL_3)
lypinator 0:bb348c97df44 720 #define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \
lypinator 0:bb348c97df44 721 ((CHANNEL) == DMA_CHANNEL_1) || \
lypinator 0:bb348c97df44 722 ((CHANNEL) == DMA_CHANNEL_2) || \
lypinator 0:bb348c97df44 723 ((CHANNEL) == DMA_CHANNEL_3) || \
lypinator 0:bb348c97df44 724 ((CHANNEL) == DMA_CHANNEL_4) || \
lypinator 0:bb348c97df44 725 ((CHANNEL) == DMA_CHANNEL_5) || \
lypinator 0:bb348c97df44 726 ((CHANNEL) == DMA_CHANNEL_6) || \
lypinator 0:bb348c97df44 727 ((CHANNEL) == DMA_CHANNEL_7) || \
lypinator 0:bb348c97df44 728 ((CHANNEL) == DMA_CHANNEL_8) || \
lypinator 0:bb348c97df44 729 ((CHANNEL) == DMA_CHANNEL_9) || \
lypinator 0:bb348c97df44 730 ((CHANNEL) == DMA_CHANNEL_10)|| \
lypinator 0:bb348c97df44 731 ((CHANNEL) == DMA_CHANNEL_11)|| \
lypinator 0:bb348c97df44 732 ((CHANNEL) == DMA_CHANNEL_12)|| \
lypinator 0:bb348c97df44 733 ((CHANNEL) == DMA_CHANNEL_13)|| \
lypinator 0:bb348c97df44 734 ((CHANNEL) == DMA_CHANNEL_14)|| \
lypinator 0:bb348c97df44 735 ((CHANNEL) == DMA_CHANNEL_15))
lypinator 0:bb348c97df44 736 #else
lypinator 0:bb348c97df44 737 #define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \
lypinator 0:bb348c97df44 738 ((CHANNEL) == DMA_CHANNEL_1) || \
lypinator 0:bb348c97df44 739 ((CHANNEL) == DMA_CHANNEL_2) || \
lypinator 0:bb348c97df44 740 ((CHANNEL) == DMA_CHANNEL_3) || \
lypinator 0:bb348c97df44 741 ((CHANNEL) == DMA_CHANNEL_4) || \
lypinator 0:bb348c97df44 742 ((CHANNEL) == DMA_CHANNEL_5) || \
lypinator 0:bb348c97df44 743 ((CHANNEL) == DMA_CHANNEL_6) || \
lypinator 0:bb348c97df44 744 ((CHANNEL) == DMA_CHANNEL_7))
lypinator 0:bb348c97df44 745 #endif /* DMA_SxCR_CHSEL_3 */
lypinator 0:bb348c97df44 746
lypinator 0:bb348c97df44 747 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
lypinator 0:bb348c97df44 748 ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
lypinator 0:bb348c97df44 749 ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
lypinator 0:bb348c97df44 750
lypinator 0:bb348c97df44 751 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x01U) && ((SIZE) < 0x10000U))
lypinator 0:bb348c97df44 752
lypinator 0:bb348c97df44 753 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
lypinator 0:bb348c97df44 754 ((STATE) == DMA_PINC_DISABLE))
lypinator 0:bb348c97df44 755
lypinator 0:bb348c97df44 756 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
lypinator 0:bb348c97df44 757 ((STATE) == DMA_MINC_DISABLE))
lypinator 0:bb348c97df44 758
lypinator 0:bb348c97df44 759 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
lypinator 0:bb348c97df44 760 ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
lypinator 0:bb348c97df44 761 ((SIZE) == DMA_PDATAALIGN_WORD))
lypinator 0:bb348c97df44 762
lypinator 0:bb348c97df44 763 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
lypinator 0:bb348c97df44 764 ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
lypinator 0:bb348c97df44 765 ((SIZE) == DMA_MDATAALIGN_WORD ))
lypinator 0:bb348c97df44 766
lypinator 0:bb348c97df44 767 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
lypinator 0:bb348c97df44 768 ((MODE) == DMA_CIRCULAR) || \
lypinator 0:bb348c97df44 769 ((MODE) == DMA_PFCTRL))
lypinator 0:bb348c97df44 770
lypinator 0:bb348c97df44 771 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
lypinator 0:bb348c97df44 772 ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
lypinator 0:bb348c97df44 773 ((PRIORITY) == DMA_PRIORITY_HIGH) || \
lypinator 0:bb348c97df44 774 ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
lypinator 0:bb348c97df44 775
lypinator 0:bb348c97df44 776 #define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || \
lypinator 0:bb348c97df44 777 ((STATE) == DMA_FIFOMODE_ENABLE))
lypinator 0:bb348c97df44 778
lypinator 0:bb348c97df44 779 #define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) || \
lypinator 0:bb348c97df44 780 ((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL) || \
lypinator 0:bb348c97df44 781 ((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) || \
lypinator 0:bb348c97df44 782 ((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL))
lypinator 0:bb348c97df44 783
lypinator 0:bb348c97df44 784 #define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MBURST_SINGLE) || \
lypinator 0:bb348c97df44 785 ((BURST) == DMA_MBURST_INC4) || \
lypinator 0:bb348c97df44 786 ((BURST) == DMA_MBURST_INC8) || \
lypinator 0:bb348c97df44 787 ((BURST) == DMA_MBURST_INC16))
lypinator 0:bb348c97df44 788
lypinator 0:bb348c97df44 789 #define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PBURST_SINGLE) || \
lypinator 0:bb348c97df44 790 ((BURST) == DMA_PBURST_INC4) || \
lypinator 0:bb348c97df44 791 ((BURST) == DMA_PBURST_INC8) || \
lypinator 0:bb348c97df44 792 ((BURST) == DMA_PBURST_INC16))
lypinator 0:bb348c97df44 793 /**
lypinator 0:bb348c97df44 794 * @}
lypinator 0:bb348c97df44 795 */
lypinator 0:bb348c97df44 796
lypinator 0:bb348c97df44 797 /* Private functions ---------------------------------------------------------*/
lypinator 0:bb348c97df44 798 /** @defgroup DMA_Private_Functions DMA Private Functions
lypinator 0:bb348c97df44 799 * @brief DMA private functions
lypinator 0:bb348c97df44 800 * @{
lypinator 0:bb348c97df44 801 */
lypinator 0:bb348c97df44 802 /**
lypinator 0:bb348c97df44 803 * @}
lypinator 0:bb348c97df44 804 */
lypinator 0:bb348c97df44 805
lypinator 0:bb348c97df44 806 /**
lypinator 0:bb348c97df44 807 * @}
lypinator 0:bb348c97df44 808 */
lypinator 0:bb348c97df44 809
lypinator 0:bb348c97df44 810 /**
lypinator 0:bb348c97df44 811 * @}
lypinator 0:bb348c97df44 812 */
lypinator 0:bb348c97df44 813
lypinator 0:bb348c97df44 814 #ifdef __cplusplus
lypinator 0:bb348c97df44 815 }
lypinator 0:bb348c97df44 816 #endif
lypinator 0:bb348c97df44 817
lypinator 0:bb348c97df44 818 #endif /* __STM32F4xx_HAL_DMA_H */
lypinator 0:bb348c97df44 819
lypinator 0:bb348c97df44 820 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/