Thomas Lyp / DevLibMemoryController

Initial commit

Dependencies:   FastPWM

mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dma.c@0:bb348c97df44, 2020-09-16 (annotated)

Committer:
lypinator
Date:
Wed Sep 16 01:11:49 2020 +0000
Revision:
0:bb348c97df44
Added PWM

Who changed what in which revision?

UserRevisionLine numberNew contents of line
lypinator 0:bb348c97df44 1 /**
lypinator 0:bb348c97df44 2 ******************************************************************************
lypinator 0:bb348c97df44 3 * @file stm32f4xx_hal_dma.c
lypinator 0:bb348c97df44 4 * @author MCD Application Team
lypinator 0:bb348c97df44 5 * @brief DMA HAL module driver.
lypinator 0:bb348c97df44 6 *
lypinator 0:bb348c97df44 7 * This file provides firmware functions to manage the following
lypinator 0:bb348c97df44 8 * functionalities of the Direct Memory Access (DMA) peripheral:
lypinator 0:bb348c97df44 9 * + Initialization and de-initialization functions
lypinator 0:bb348c97df44 10 * + IO operation functions
lypinator 0:bb348c97df44 11 * + Peripheral State and errors functions
lypinator 0:bb348c97df44 12 @verbatim
lypinator 0:bb348c97df44 13 ==============================================================================
lypinator 0:bb348c97df44 14 ##### How to use this driver #####
lypinator 0:bb348c97df44 15 ==============================================================================
lypinator 0:bb348c97df44 16 [..]
lypinator 0:bb348c97df44 17 (#) Enable and configure the peripheral to be connected to the DMA Stream
lypinator 0:bb348c97df44 18 (except for internal SRAM/FLASH memories: no initialization is
lypinator 0:bb348c97df44 19 necessary) please refer to Reference manual for connection between peripherals
lypinator 0:bb348c97df44 20 and DMA requests.
lypinator 0:bb348c97df44 21
lypinator 0:bb348c97df44 22 (#) For a given Stream, program the required configuration through the following parameters:
lypinator 0:bb348c97df44 23 Transfer Direction, Source and Destination data formats,
lypinator 0:bb348c97df44 24 Circular, Normal or peripheral flow control mode, Stream Priority level,
lypinator 0:bb348c97df44 25 Source and Destination Increment mode, FIFO mode and its Threshold (if needed),
lypinator 0:bb348c97df44 26 Burst mode for Source and/or Destination (if needed) using HAL_DMA_Init() function.
lypinator 0:bb348c97df44 27
lypinator 0:bb348c97df44 28 -@- Prior to HAL_DMA_Init() the clock must be enabled for DMA through the following macros:
lypinator 0:bb348c97df44 29 __HAL_RCC_DMA1_CLK_ENABLE() or __HAL_RCC_DMA2_CLK_ENABLE().
lypinator 0:bb348c97df44 30
lypinator 0:bb348c97df44 31 *** Polling mode IO operation ***
lypinator 0:bb348c97df44 32 =================================
lypinator 0:bb348c97df44 33 [..]
lypinator 0:bb348c97df44 34 (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source
lypinator 0:bb348c97df44 35 address and destination address and the Length of data to be transferred.
lypinator 0:bb348c97df44 36 (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this
lypinator 0:bb348c97df44 37 case a fixed Timeout can be configured by User depending from his application.
lypinator 0:bb348c97df44 38 (+) Use HAL_DMA_Abort() function to abort the current transfer.
lypinator 0:bb348c97df44 39
lypinator 0:bb348c97df44 40 *** Interrupt mode IO operation ***
lypinator 0:bb348c97df44 41 ===================================
lypinator 0:bb348c97df44 42 [..]
lypinator 0:bb348c97df44 43 (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
lypinator 0:bb348c97df44 44 (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
lypinator 0:bb348c97df44 45 (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of
lypinator 0:bb348c97df44 46 Source address and destination address and the Length of data to be transferred. In this
lypinator 0:bb348c97df44 47 case the DMA interrupt is configured
lypinator 0:bb348c97df44 48 (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
lypinator 0:bb348c97df44 49 (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
lypinator 0:bb348c97df44 50 add his own function by customization of function pointer XferCpltCallback and
lypinator 0:bb348c97df44 51 XferErrorCallback (i.e a member of DMA handle structure).
lypinator 0:bb348c97df44 52 [..]
lypinator 0:bb348c97df44 53 (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
lypinator 0:bb348c97df44 54 detection.
lypinator 0:bb348c97df44 55
lypinator 0:bb348c97df44 56 (#) Use HAL_DMA_Abort_IT() function to abort the current transfer
lypinator 0:bb348c97df44 57
lypinator 0:bb348c97df44 58 -@- In Memory-to-Memory transfer mode, Circular mode is not allowed.
lypinator 0:bb348c97df44 59
lypinator 0:bb348c97df44 60 -@- The FIFO is used mainly to reduce bus usage and to allow data packing/unpacking: it is
lypinator 0:bb348c97df44 61 possible to set different Data Sizes for the Peripheral and the Memory (ie. you can set
lypinator 0:bb348c97df44 62 Half-Word data size for the peripheral to access its data register and set Word data size
lypinator 0:bb348c97df44 63 for the Memory to gain in access time. Each two half words will be packed and written in
lypinator 0:bb348c97df44 64 a single access to a Word in the Memory).
lypinator 0:bb348c97df44 65
lypinator 0:bb348c97df44 66 -@- When FIFO is disabled, it is not allowed to configure different Data Sizes for Source
lypinator 0:bb348c97df44 67 and Destination. In this case the Peripheral Data Size will be applied to both Source
lypinator 0:bb348c97df44 68 and Destination.
lypinator 0:bb348c97df44 69
lypinator 0:bb348c97df44 70 *** DMA HAL driver macros list ***
lypinator 0:bb348c97df44 71 =============================================
lypinator 0:bb348c97df44 72 [..]
lypinator 0:bb348c97df44 73 Below the list of most used macros in DMA HAL driver.
lypinator 0:bb348c97df44 74
lypinator 0:bb348c97df44 75 (+) __HAL_DMA_ENABLE: Enable the specified DMA Stream.
lypinator 0:bb348c97df44 76 (+) __HAL_DMA_DISABLE: Disable the specified DMA Stream.
lypinator 0:bb348c97df44 77 (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Stream interrupt has occurred or not.
lypinator 0:bb348c97df44 78
lypinator 0:bb348c97df44 79 [..]
lypinator 0:bb348c97df44 80 (@) You can refer to the DMA HAL driver header file for more useful macros
lypinator 0:bb348c97df44 81
lypinator 0:bb348c97df44 82 @endverbatim
lypinator 0:bb348c97df44 83 ******************************************************************************
lypinator 0:bb348c97df44 84 * @attention
lypinator 0:bb348c97df44 85 *
lypinator 0:bb348c97df44 86 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
lypinator 0:bb348c97df44 87 *
lypinator 0:bb348c97df44 88 * Redistribution and use in source and binary forms, with or without modification,
lypinator 0:bb348c97df44 89 * are permitted provided that the following conditions are met:
lypinator 0:bb348c97df44 90 * 1. Redistributions of source code must retain the above copyright notice,
lypinator 0:bb348c97df44 91 * this list of conditions and the following disclaimer.
lypinator 0:bb348c97df44 92 * 2. Redistributions in binary form must reproduce the above copyright notice,
lypinator 0:bb348c97df44 93 * this list of conditions and the following disclaimer in the documentation
lypinator 0:bb348c97df44 94 * and/or other materials provided with the distribution.
lypinator 0:bb348c97df44 95 * 3. Neither the name of STMicroelectronics nor the names of its contributors
lypinator 0:bb348c97df44 96 * may be used to endorse or promote products derived from this software
lypinator 0:bb348c97df44 97 * without specific prior written permission.
lypinator 0:bb348c97df44 98 *
lypinator 0:bb348c97df44 99 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
lypinator 0:bb348c97df44 100 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
lypinator 0:bb348c97df44 101 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
lypinator 0:bb348c97df44 102 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
lypinator 0:bb348c97df44 103 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
lypinator 0:bb348c97df44 104 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
lypinator 0:bb348c97df44 105 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
lypinator 0:bb348c97df44 106 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
lypinator 0:bb348c97df44 107 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
lypinator 0:bb348c97df44 108 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
lypinator 0:bb348c97df44 109 *
lypinator 0:bb348c97df44 110 ******************************************************************************
lypinator 0:bb348c97df44 111 */
lypinator 0:bb348c97df44 112
lypinator 0:bb348c97df44 113 /* Includes ------------------------------------------------------------------*/
lypinator 0:bb348c97df44 114 #include "stm32f4xx_hal.h"
lypinator 0:bb348c97df44 115
lypinator 0:bb348c97df44 116 /** @addtogroup STM32F4xx_HAL_Driver
lypinator 0:bb348c97df44 117 * @{
lypinator 0:bb348c97df44 118 */
lypinator 0:bb348c97df44 119
lypinator 0:bb348c97df44 120 /** @defgroup DMA DMA
lypinator 0:bb348c97df44 121 * @brief DMA HAL module driver
lypinator 0:bb348c97df44 122 * @{
lypinator 0:bb348c97df44 123 */
lypinator 0:bb348c97df44 124
lypinator 0:bb348c97df44 125 #ifdef HAL_DMA_MODULE_ENABLED
lypinator 0:bb348c97df44 126
lypinator 0:bb348c97df44 127 /* Private types -------------------------------------------------------------*/
lypinator 0:bb348c97df44 128 typedef struct
lypinator 0:bb348c97df44 129 {
lypinator 0:bb348c97df44 130 __IO uint32_t ISR; /*!< DMA interrupt status register */
lypinator 0:bb348c97df44 131 __IO uint32_t Reserved0;
lypinator 0:bb348c97df44 132 __IO uint32_t IFCR; /*!< DMA interrupt flag clear register */
lypinator 0:bb348c97df44 133 } DMA_Base_Registers;
lypinator 0:bb348c97df44 134
lypinator 0:bb348c97df44 135 /* Private variables ---------------------------------------------------------*/
lypinator 0:bb348c97df44 136 /* Private constants ---------------------------------------------------------*/
lypinator 0:bb348c97df44 137 /** @addtogroup DMA_Private_Constants
lypinator 0:bb348c97df44 138 * @{
lypinator 0:bb348c97df44 139 */
lypinator 0:bb348c97df44 140 #define HAL_TIMEOUT_DMA_ABORT 5U /* 5 ms */
lypinator 0:bb348c97df44 141 /**
lypinator 0:bb348c97df44 142 * @}
lypinator 0:bb348c97df44 143 */
lypinator 0:bb348c97df44 144 /* Private macros ------------------------------------------------------------*/
lypinator 0:bb348c97df44 145 /* Private functions ---------------------------------------------------------*/
lypinator 0:bb348c97df44 146 /** @addtogroup DMA_Private_Functions
lypinator 0:bb348c97df44 147 * @{
lypinator 0:bb348c97df44 148 */
lypinator 0:bb348c97df44 149 static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
lypinator 0:bb348c97df44 150 static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma);
lypinator 0:bb348c97df44 151 static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma);
lypinator 0:bb348c97df44 152
lypinator 0:bb348c97df44 153 /**
lypinator 0:bb348c97df44 154 * @}
lypinator 0:bb348c97df44 155 */
lypinator 0:bb348c97df44 156
lypinator 0:bb348c97df44 157 /* Exported functions ---------------------------------------------------------*/
lypinator 0:bb348c97df44 158 /** @addtogroup DMA_Exported_Functions
lypinator 0:bb348c97df44 159 * @{
lypinator 0:bb348c97df44 160 */
lypinator 0:bb348c97df44 161
lypinator 0:bb348c97df44 162 /** @addtogroup DMA_Exported_Functions_Group1
lypinator 0:bb348c97df44 163 *
lypinator 0:bb348c97df44 164 @verbatim
lypinator 0:bb348c97df44 165 ===============================================================================
lypinator 0:bb348c97df44 166 ##### Initialization and de-initialization functions #####
lypinator 0:bb348c97df44 167 ===============================================================================
lypinator 0:bb348c97df44 168 [..]
lypinator 0:bb348c97df44 169 This section provides functions allowing to initialize the DMA Stream source
lypinator 0:bb348c97df44 170 and destination addresses, incrementation and data sizes, transfer direction,
lypinator 0:bb348c97df44 171 circular/normal mode selection, memory-to-memory mode selection and Stream priority value.
lypinator 0:bb348c97df44 172 [..]
lypinator 0:bb348c97df44 173 The HAL_DMA_Init() function follows the DMA configuration procedures as described in
lypinator 0:bb348c97df44 174 reference manual.
lypinator 0:bb348c97df44 175
lypinator 0:bb348c97df44 176 @endverbatim
lypinator 0:bb348c97df44 177 * @{
lypinator 0:bb348c97df44 178 */
lypinator 0:bb348c97df44 179
lypinator 0:bb348c97df44 180 /**
lypinator 0:bb348c97df44 181 * @brief Initialize the DMA according to the specified
lypinator 0:bb348c97df44 182 * parameters in the DMA_InitTypeDef and create the associated handle.
lypinator 0:bb348c97df44 183 * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 184 * the configuration information for the specified DMA Stream.
lypinator 0:bb348c97df44 185 * @retval HAL status
lypinator 0:bb348c97df44 186 */
lypinator 0:bb348c97df44 187 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
lypinator 0:bb348c97df44 188 {
lypinator 0:bb348c97df44 189 uint32_t tmp = 0U;
lypinator 0:bb348c97df44 190 uint32_t tickstart = HAL_GetTick();
lypinator 0:bb348c97df44 191 DMA_Base_Registers *regs;
lypinator 0:bb348c97df44 192
lypinator 0:bb348c97df44 193 /* Check the DMA peripheral state */
lypinator 0:bb348c97df44 194 if(hdma == NULL)
lypinator 0:bb348c97df44 195 {
lypinator 0:bb348c97df44 196 return HAL_ERROR;
lypinator 0:bb348c97df44 197 }
lypinator 0:bb348c97df44 198
lypinator 0:bb348c97df44 199 /* Check the parameters */
lypinator 0:bb348c97df44 200 assert_param(IS_DMA_STREAM_ALL_INSTANCE(hdma->Instance));
lypinator 0:bb348c97df44 201 assert_param(IS_DMA_CHANNEL(hdma->Init.Channel));
lypinator 0:bb348c97df44 202 assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));
lypinator 0:bb348c97df44 203 assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc));
lypinator 0:bb348c97df44 204 assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc));
lypinator 0:bb348c97df44 205 assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));
lypinator 0:bb348c97df44 206 assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
lypinator 0:bb348c97df44 207 assert_param(IS_DMA_MODE(hdma->Init.Mode));
lypinator 0:bb348c97df44 208 assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
lypinator 0:bb348c97df44 209 assert_param(IS_DMA_FIFO_MODE_STATE(hdma->Init.FIFOMode));
lypinator 0:bb348c97df44 210 /* Check the memory burst, peripheral burst and FIFO threshold parameters only
lypinator 0:bb348c97df44 211 when FIFO mode is enabled */
lypinator 0:bb348c97df44 212 if(hdma->Init.FIFOMode != DMA_FIFOMODE_DISABLE)
lypinator 0:bb348c97df44 213 {
lypinator 0:bb348c97df44 214 assert_param(IS_DMA_FIFO_THRESHOLD(hdma->Init.FIFOThreshold));
lypinator 0:bb348c97df44 215 assert_param(IS_DMA_MEMORY_BURST(hdma->Init.MemBurst));
lypinator 0:bb348c97df44 216 assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst));
lypinator 0:bb348c97df44 217 }
lypinator 0:bb348c97df44 218
lypinator 0:bb348c97df44 219 /* Allocate lock resource */
lypinator 0:bb348c97df44 220 __HAL_UNLOCK(hdma);
lypinator 0:bb348c97df44 221
lypinator 0:bb348c97df44 222 /* Change DMA peripheral state */
lypinator 0:bb348c97df44 223 hdma->State = HAL_DMA_STATE_BUSY;
lypinator 0:bb348c97df44 224
lypinator 0:bb348c97df44 225 /* Disable the peripheral */
lypinator 0:bb348c97df44 226 __HAL_DMA_DISABLE(hdma);
lypinator 0:bb348c97df44 227
lypinator 0:bb348c97df44 228 /* Check if the DMA Stream is effectively disabled */
lypinator 0:bb348c97df44 229 while((hdma->Instance->CR & DMA_SxCR_EN) != RESET)
lypinator 0:bb348c97df44 230 {
lypinator 0:bb348c97df44 231 /* Check for the Timeout */
lypinator 0:bb348c97df44 232 if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT)
lypinator 0:bb348c97df44 233 {
lypinator 0:bb348c97df44 234 /* Update error code */
lypinator 0:bb348c97df44 235 hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
lypinator 0:bb348c97df44 236
lypinator 0:bb348c97df44 237 /* Change the DMA state */
lypinator 0:bb348c97df44 238 hdma->State = HAL_DMA_STATE_TIMEOUT;
lypinator 0:bb348c97df44 239
lypinator 0:bb348c97df44 240 return HAL_TIMEOUT;
lypinator 0:bb348c97df44 241 }
lypinator 0:bb348c97df44 242 }
lypinator 0:bb348c97df44 243
lypinator 0:bb348c97df44 244 /* Get the CR register value */
lypinator 0:bb348c97df44 245 tmp = hdma->Instance->CR;
lypinator 0:bb348c97df44 246
lypinator 0:bb348c97df44 247 /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits */
lypinator 0:bb348c97df44 248 tmp &= ((uint32_t)~(DMA_SxCR_CHSEL | DMA_SxCR_MBURST | DMA_SxCR_PBURST | \
lypinator 0:bb348c97df44 249 DMA_SxCR_PL | DMA_SxCR_MSIZE | DMA_SxCR_PSIZE | \
lypinator 0:bb348c97df44 250 DMA_SxCR_MINC | DMA_SxCR_PINC | DMA_SxCR_CIRC | \
lypinator 0:bb348c97df44 251 DMA_SxCR_DIR | DMA_SxCR_CT | DMA_SxCR_DBM));
lypinator 0:bb348c97df44 252
lypinator 0:bb348c97df44 253 /* Prepare the DMA Stream configuration */
lypinator 0:bb348c97df44 254 tmp |= hdma->Init.Channel | hdma->Init.Direction |
lypinator 0:bb348c97df44 255 hdma->Init.PeriphInc | hdma->Init.MemInc |
lypinator 0:bb348c97df44 256 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
lypinator 0:bb348c97df44 257 hdma->Init.Mode | hdma->Init.Priority;
lypinator 0:bb348c97df44 258
lypinator 0:bb348c97df44 259 /* the Memory burst and peripheral burst are not used when the FIFO is disabled */
lypinator 0:bb348c97df44 260 if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)
lypinator 0:bb348c97df44 261 {
lypinator 0:bb348c97df44 262 /* Get memory burst and peripheral burst */
lypinator 0:bb348c97df44 263 tmp |= hdma->Init.MemBurst | hdma->Init.PeriphBurst;
lypinator 0:bb348c97df44 264 }
lypinator 0:bb348c97df44 265
lypinator 0:bb348c97df44 266 /* Write to DMA Stream CR register */
lypinator 0:bb348c97df44 267 hdma->Instance->CR = tmp;
lypinator 0:bb348c97df44 268
lypinator 0:bb348c97df44 269 /* Get the FCR register value */
lypinator 0:bb348c97df44 270 tmp = hdma->Instance->FCR;
lypinator 0:bb348c97df44 271
lypinator 0:bb348c97df44 272 /* Clear Direct mode and FIFO threshold bits */
lypinator 0:bb348c97df44 273 tmp &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH);
lypinator 0:bb348c97df44 274
lypinator 0:bb348c97df44 275 /* Prepare the DMA Stream FIFO configuration */
lypinator 0:bb348c97df44 276 tmp |= hdma->Init.FIFOMode;
lypinator 0:bb348c97df44 277
lypinator 0:bb348c97df44 278 /* The FIFO threshold is not used when the FIFO mode is disabled */
lypinator 0:bb348c97df44 279 if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)
lypinator 0:bb348c97df44 280 {
lypinator 0:bb348c97df44 281 /* Get the FIFO threshold */
lypinator 0:bb348c97df44 282 tmp |= hdma->Init.FIFOThreshold;
lypinator 0:bb348c97df44 283
lypinator 0:bb348c97df44 284 /* Check compatibility between FIFO threshold level and size of the memory burst */
lypinator 0:bb348c97df44 285 /* for INCR4, INCR8, INCR16 bursts */
lypinator 0:bb348c97df44 286 if (hdma->Init.MemBurst != DMA_MBURST_SINGLE)
lypinator 0:bb348c97df44 287 {
lypinator 0:bb348c97df44 288 if (DMA_CheckFifoParam(hdma) != HAL_OK)
lypinator 0:bb348c97df44 289 {
lypinator 0:bb348c97df44 290 /* Update error code */
lypinator 0:bb348c97df44 291 hdma->ErrorCode = HAL_DMA_ERROR_PARAM;
lypinator 0:bb348c97df44 292
lypinator 0:bb348c97df44 293 /* Change the DMA state */
lypinator 0:bb348c97df44 294 hdma->State = HAL_DMA_STATE_READY;
lypinator 0:bb348c97df44 295
lypinator 0:bb348c97df44 296 return HAL_ERROR;
lypinator 0:bb348c97df44 297 }
lypinator 0:bb348c97df44 298 }
lypinator 0:bb348c97df44 299 }
lypinator 0:bb348c97df44 300
lypinator 0:bb348c97df44 301 /* Write to DMA Stream FCR */
lypinator 0:bb348c97df44 302 hdma->Instance->FCR = tmp;
lypinator 0:bb348c97df44 303
lypinator 0:bb348c97df44 304 /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate
lypinator 0:bb348c97df44 305 DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */
lypinator 0:bb348c97df44 306 regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);
lypinator 0:bb348c97df44 307
lypinator 0:bb348c97df44 308 /* Clear all interrupt flags */
lypinator 0:bb348c97df44 309 regs->IFCR = 0x3FU << hdma->StreamIndex;
lypinator 0:bb348c97df44 310
lypinator 0:bb348c97df44 311 /* Initialize the error code */
lypinator 0:bb348c97df44 312 hdma->ErrorCode = HAL_DMA_ERROR_NONE;
lypinator 0:bb348c97df44 313
lypinator 0:bb348c97df44 314 /* Initialize the DMA state */
lypinator 0:bb348c97df44 315 hdma->State = HAL_DMA_STATE_READY;
lypinator 0:bb348c97df44 316
lypinator 0:bb348c97df44 317 return HAL_OK;
lypinator 0:bb348c97df44 318 }
lypinator 0:bb348c97df44 319
lypinator 0:bb348c97df44 320 /**
lypinator 0:bb348c97df44 321 * @brief DeInitializes the DMA peripheral
lypinator 0:bb348c97df44 322 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 323 * the configuration information for the specified DMA Stream.
lypinator 0:bb348c97df44 324 * @retval HAL status
lypinator 0:bb348c97df44 325 */
lypinator 0:bb348c97df44 326 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
lypinator 0:bb348c97df44 327 {
lypinator 0:bb348c97df44 328 DMA_Base_Registers *regs;
lypinator 0:bb348c97df44 329
lypinator 0:bb348c97df44 330 /* Check the DMA peripheral state */
lypinator 0:bb348c97df44 331 if(hdma == NULL)
lypinator 0:bb348c97df44 332 {
lypinator 0:bb348c97df44 333 return HAL_ERROR;
lypinator 0:bb348c97df44 334 }
lypinator 0:bb348c97df44 335
lypinator 0:bb348c97df44 336 /* Check the DMA peripheral state */
lypinator 0:bb348c97df44 337 if(hdma->State == HAL_DMA_STATE_BUSY)
lypinator 0:bb348c97df44 338 {
lypinator 0:bb348c97df44 339 /* Return error status */
lypinator 0:bb348c97df44 340 return HAL_BUSY;
lypinator 0:bb348c97df44 341 }
lypinator 0:bb348c97df44 342
lypinator 0:bb348c97df44 343 /* Check the parameters */
lypinator 0:bb348c97df44 344 assert_param(IS_DMA_STREAM_ALL_INSTANCE(hdma->Instance));
lypinator 0:bb348c97df44 345
lypinator 0:bb348c97df44 346 /* Disable the selected DMA Streamx */
lypinator 0:bb348c97df44 347 __HAL_DMA_DISABLE(hdma);
lypinator 0:bb348c97df44 348
lypinator 0:bb348c97df44 349 /* Reset DMA Streamx control register */
lypinator 0:bb348c97df44 350 hdma->Instance->CR = 0U;
lypinator 0:bb348c97df44 351
lypinator 0:bb348c97df44 352 /* Reset DMA Streamx number of data to transfer register */
lypinator 0:bb348c97df44 353 hdma->Instance->NDTR = 0U;
lypinator 0:bb348c97df44 354
lypinator 0:bb348c97df44 355 /* Reset DMA Streamx peripheral address register */
lypinator 0:bb348c97df44 356 hdma->Instance->PAR = 0U;
lypinator 0:bb348c97df44 357
lypinator 0:bb348c97df44 358 /* Reset DMA Streamx memory 0 address register */
lypinator 0:bb348c97df44 359 hdma->Instance->M0AR = 0U;
lypinator 0:bb348c97df44 360
lypinator 0:bb348c97df44 361 /* Reset DMA Streamx memory 1 address register */
lypinator 0:bb348c97df44 362 hdma->Instance->M1AR = 0U;
lypinator 0:bb348c97df44 363
lypinator 0:bb348c97df44 364 /* Reset DMA Streamx FIFO control register */
lypinator 0:bb348c97df44 365 hdma->Instance->FCR = 0x00000021U;
lypinator 0:bb348c97df44 366
lypinator 0:bb348c97df44 367 /* Get DMA steam Base Address */
lypinator 0:bb348c97df44 368 regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);
lypinator 0:bb348c97df44 369
lypinator 0:bb348c97df44 370 /* Clear all interrupt flags at correct offset within the register */
lypinator 0:bb348c97df44 371 regs->IFCR = 0x3FU << hdma->StreamIndex;
lypinator 0:bb348c97df44 372
lypinator 0:bb348c97df44 373 /* Initialize the error code */
lypinator 0:bb348c97df44 374 hdma->ErrorCode = HAL_DMA_ERROR_NONE;
lypinator 0:bb348c97df44 375
lypinator 0:bb348c97df44 376 /* Initialize the DMA state */
lypinator 0:bb348c97df44 377 hdma->State = HAL_DMA_STATE_RESET;
lypinator 0:bb348c97df44 378
lypinator 0:bb348c97df44 379 /* Release Lock */
lypinator 0:bb348c97df44 380 __HAL_UNLOCK(hdma);
lypinator 0:bb348c97df44 381
lypinator 0:bb348c97df44 382 return HAL_OK;
lypinator 0:bb348c97df44 383 }
lypinator 0:bb348c97df44 384
lypinator 0:bb348c97df44 385 /**
lypinator 0:bb348c97df44 386 * @}
lypinator 0:bb348c97df44 387 */
lypinator 0:bb348c97df44 388
lypinator 0:bb348c97df44 389 /** @addtogroup DMA_Exported_Functions_Group2
lypinator 0:bb348c97df44 390 *
lypinator 0:bb348c97df44 391 @verbatim
lypinator 0:bb348c97df44 392 ===============================================================================
lypinator 0:bb348c97df44 393 ##### IO operation functions #####
lypinator 0:bb348c97df44 394 ===============================================================================
lypinator 0:bb348c97df44 395 [..] This section provides functions allowing to:
lypinator 0:bb348c97df44 396 (+) Configure the source, destination address and data length and Start DMA transfer
lypinator 0:bb348c97df44 397 (+) Configure the source, destination address and data length and
lypinator 0:bb348c97df44 398 Start DMA transfer with interrupt
lypinator 0:bb348c97df44 399 (+) Abort DMA transfer
lypinator 0:bb348c97df44 400 (+) Poll for transfer complete
lypinator 0:bb348c97df44 401 (+) Handle DMA interrupt request
lypinator 0:bb348c97df44 402
lypinator 0:bb348c97df44 403 @endverbatim
lypinator 0:bb348c97df44 404 * @{
lypinator 0:bb348c97df44 405 */
lypinator 0:bb348c97df44 406
lypinator 0:bb348c97df44 407 /**
lypinator 0:bb348c97df44 408 * @brief Starts the DMA Transfer.
lypinator 0:bb348c97df44 409 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 410 * the configuration information for the specified DMA Stream.
lypinator 0:bb348c97df44 411 * @param SrcAddress The source memory Buffer address
lypinator 0:bb348c97df44 412 * @param DstAddress The destination memory Buffer address
lypinator 0:bb348c97df44 413 * @param DataLength The length of data to be transferred from source to destination
lypinator 0:bb348c97df44 414 * @retval HAL status
lypinator 0:bb348c97df44 415 */
lypinator 0:bb348c97df44 416 HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
lypinator 0:bb348c97df44 417 {
lypinator 0:bb348c97df44 418 HAL_StatusTypeDef status = HAL_OK;
lypinator 0:bb348c97df44 419
lypinator 0:bb348c97df44 420 /* Check the parameters */
lypinator 0:bb348c97df44 421 assert_param(IS_DMA_BUFFER_SIZE(DataLength));
lypinator 0:bb348c97df44 422
lypinator 0:bb348c97df44 423 /* Process locked */
lypinator 0:bb348c97df44 424 __HAL_LOCK(hdma);
lypinator 0:bb348c97df44 425
lypinator 0:bb348c97df44 426 if(HAL_DMA_STATE_READY == hdma->State)
lypinator 0:bb348c97df44 427 {
lypinator 0:bb348c97df44 428 /* Change DMA peripheral state */
lypinator 0:bb348c97df44 429 hdma->State = HAL_DMA_STATE_BUSY;
lypinator 0:bb348c97df44 430
lypinator 0:bb348c97df44 431 /* Initialize the error code */
lypinator 0:bb348c97df44 432 hdma->ErrorCode = HAL_DMA_ERROR_NONE;
lypinator 0:bb348c97df44 433
lypinator 0:bb348c97df44 434 /* Configure the source, destination address and the data length */
lypinator 0:bb348c97df44 435 DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
lypinator 0:bb348c97df44 436
lypinator 0:bb348c97df44 437 /* Enable the Peripheral */
lypinator 0:bb348c97df44 438 __HAL_DMA_ENABLE(hdma);
lypinator 0:bb348c97df44 439 }
lypinator 0:bb348c97df44 440 else
lypinator 0:bb348c97df44 441 {
lypinator 0:bb348c97df44 442 /* Process unlocked */
lypinator 0:bb348c97df44 443 __HAL_UNLOCK(hdma);
lypinator 0:bb348c97df44 444
lypinator 0:bb348c97df44 445 /* Return error status */
lypinator 0:bb348c97df44 446 status = HAL_BUSY;
lypinator 0:bb348c97df44 447 }
lypinator 0:bb348c97df44 448 return status;
lypinator 0:bb348c97df44 449 }
lypinator 0:bb348c97df44 450
lypinator 0:bb348c97df44 451 /**
lypinator 0:bb348c97df44 452 * @brief Start the DMA Transfer with interrupt enabled.
lypinator 0:bb348c97df44 453 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 454 * the configuration information for the specified DMA Stream.
lypinator 0:bb348c97df44 455 * @param SrcAddress The source memory Buffer address
lypinator 0:bb348c97df44 456 * @param DstAddress The destination memory Buffer address
lypinator 0:bb348c97df44 457 * @param DataLength The length of data to be transferred from source to destination
lypinator 0:bb348c97df44 458 * @retval HAL status
lypinator 0:bb348c97df44 459 */
lypinator 0:bb348c97df44 460 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
lypinator 0:bb348c97df44 461 {
lypinator 0:bb348c97df44 462 HAL_StatusTypeDef status = HAL_OK;
lypinator 0:bb348c97df44 463
lypinator 0:bb348c97df44 464 /* calculate DMA base and stream number */
lypinator 0:bb348c97df44 465 DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
lypinator 0:bb348c97df44 466
lypinator 0:bb348c97df44 467 /* Check the parameters */
lypinator 0:bb348c97df44 468 assert_param(IS_DMA_BUFFER_SIZE(DataLength));
lypinator 0:bb348c97df44 469
lypinator 0:bb348c97df44 470 /* Process locked */
lypinator 0:bb348c97df44 471 __HAL_LOCK(hdma);
lypinator 0:bb348c97df44 472
lypinator 0:bb348c97df44 473 if(HAL_DMA_STATE_READY == hdma->State)
lypinator 0:bb348c97df44 474 {
lypinator 0:bb348c97df44 475 /* Change DMA peripheral state */
lypinator 0:bb348c97df44 476 hdma->State = HAL_DMA_STATE_BUSY;
lypinator 0:bb348c97df44 477
lypinator 0:bb348c97df44 478 /* Initialize the error code */
lypinator 0:bb348c97df44 479 hdma->ErrorCode = HAL_DMA_ERROR_NONE;
lypinator 0:bb348c97df44 480
lypinator 0:bb348c97df44 481 /* Configure the source, destination address and the data length */
lypinator 0:bb348c97df44 482 DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
lypinator 0:bb348c97df44 483
lypinator 0:bb348c97df44 484 /* Clear all interrupt flags at correct offset within the register */
lypinator 0:bb348c97df44 485 regs->IFCR = 0x3FU << hdma->StreamIndex;
lypinator 0:bb348c97df44 486
lypinator 0:bb348c97df44 487 /* Enable Common interrupts*/
lypinator 0:bb348c97df44 488 hdma->Instance->CR |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME;
lypinator 0:bb348c97df44 489 hdma->Instance->FCR |= DMA_IT_FE;
lypinator 0:bb348c97df44 490
lypinator 0:bb348c97df44 491 if(hdma->XferHalfCpltCallback != NULL)
lypinator 0:bb348c97df44 492 {
lypinator 0:bb348c97df44 493 hdma->Instance->CR |= DMA_IT_HT;
lypinator 0:bb348c97df44 494 }
lypinator 0:bb348c97df44 495
lypinator 0:bb348c97df44 496 /* Enable the Peripheral */
lypinator 0:bb348c97df44 497 __HAL_DMA_ENABLE(hdma);
lypinator 0:bb348c97df44 498 }
lypinator 0:bb348c97df44 499 else
lypinator 0:bb348c97df44 500 {
lypinator 0:bb348c97df44 501 /* Process unlocked */
lypinator 0:bb348c97df44 502 __HAL_UNLOCK(hdma);
lypinator 0:bb348c97df44 503
lypinator 0:bb348c97df44 504 /* Return error status */
lypinator 0:bb348c97df44 505 status = HAL_BUSY;
lypinator 0:bb348c97df44 506 }
lypinator 0:bb348c97df44 507
lypinator 0:bb348c97df44 508 return status;
lypinator 0:bb348c97df44 509 }
lypinator 0:bb348c97df44 510
lypinator 0:bb348c97df44 511 /**
lypinator 0:bb348c97df44 512 * @brief Aborts the DMA Transfer.
lypinator 0:bb348c97df44 513 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 514 * the configuration information for the specified DMA Stream.
lypinator 0:bb348c97df44 515 *
lypinator 0:bb348c97df44 516 * @note After disabling a DMA Stream, a check for wait until the DMA Stream is
lypinator 0:bb348c97df44 517 * effectively disabled is added. If a Stream is disabled
lypinator 0:bb348c97df44 518 * while a data transfer is ongoing, the current data will be transferred
lypinator 0:bb348c97df44 519 * and the Stream will be effectively disabled only after the transfer of
lypinator 0:bb348c97df44 520 * this single data is finished.
lypinator 0:bb348c97df44 521 * @retval HAL status
lypinator 0:bb348c97df44 522 */
lypinator 0:bb348c97df44 523 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
lypinator 0:bb348c97df44 524 {
lypinator 0:bb348c97df44 525 /* calculate DMA base and stream number */
lypinator 0:bb348c97df44 526 DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
lypinator 0:bb348c97df44 527
lypinator 0:bb348c97df44 528 uint32_t tickstart = HAL_GetTick();
lypinator 0:bb348c97df44 529
lypinator 0:bb348c97df44 530 if(hdma->State != HAL_DMA_STATE_BUSY)
lypinator 0:bb348c97df44 531 {
lypinator 0:bb348c97df44 532 hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
lypinator 0:bb348c97df44 533
lypinator 0:bb348c97df44 534 /* Process Unlocked */
lypinator 0:bb348c97df44 535 __HAL_UNLOCK(hdma);
lypinator 0:bb348c97df44 536
lypinator 0:bb348c97df44 537 return HAL_ERROR;
lypinator 0:bb348c97df44 538 }
lypinator 0:bb348c97df44 539 else
lypinator 0:bb348c97df44 540 {
lypinator 0:bb348c97df44 541 /* Disable all the transfer interrupts */
lypinator 0:bb348c97df44 542 hdma->Instance->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME);
lypinator 0:bb348c97df44 543 hdma->Instance->FCR &= ~(DMA_IT_FE);
lypinator 0:bb348c97df44 544
lypinator 0:bb348c97df44 545 if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))
lypinator 0:bb348c97df44 546 {
lypinator 0:bb348c97df44 547 hdma->Instance->CR &= ~(DMA_IT_HT);
lypinator 0:bb348c97df44 548 }
lypinator 0:bb348c97df44 549
lypinator 0:bb348c97df44 550 /* Disable the stream */
lypinator 0:bb348c97df44 551 __HAL_DMA_DISABLE(hdma);
lypinator 0:bb348c97df44 552
lypinator 0:bb348c97df44 553 /* Check if the DMA Stream is effectively disabled */
lypinator 0:bb348c97df44 554 while((hdma->Instance->CR & DMA_SxCR_EN) != RESET)
lypinator 0:bb348c97df44 555 {
lypinator 0:bb348c97df44 556 /* Check for the Timeout */
lypinator 0:bb348c97df44 557 if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT)
lypinator 0:bb348c97df44 558 {
lypinator 0:bb348c97df44 559 /* Update error code */
lypinator 0:bb348c97df44 560 hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
lypinator 0:bb348c97df44 561
lypinator 0:bb348c97df44 562 /* Process Unlocked */
lypinator 0:bb348c97df44 563 __HAL_UNLOCK(hdma);
lypinator 0:bb348c97df44 564
lypinator 0:bb348c97df44 565 /* Change the DMA state */
lypinator 0:bb348c97df44 566 hdma->State = HAL_DMA_STATE_TIMEOUT;
lypinator 0:bb348c97df44 567
lypinator 0:bb348c97df44 568 return HAL_TIMEOUT;
lypinator 0:bb348c97df44 569 }
lypinator 0:bb348c97df44 570 }
lypinator 0:bb348c97df44 571
lypinator 0:bb348c97df44 572 /* Clear all interrupt flags at correct offset within the register */
lypinator 0:bb348c97df44 573 regs->IFCR = 0x3FU << hdma->StreamIndex;
lypinator 0:bb348c97df44 574
lypinator 0:bb348c97df44 575 /* Process Unlocked */
lypinator 0:bb348c97df44 576 __HAL_UNLOCK(hdma);
lypinator 0:bb348c97df44 577
lypinator 0:bb348c97df44 578 /* Change the DMA state*/
lypinator 0:bb348c97df44 579 hdma->State = HAL_DMA_STATE_READY;
lypinator 0:bb348c97df44 580 }
lypinator 0:bb348c97df44 581 return HAL_OK;
lypinator 0:bb348c97df44 582 }
lypinator 0:bb348c97df44 583
lypinator 0:bb348c97df44 584 /**
lypinator 0:bb348c97df44 585 * @brief Aborts the DMA Transfer in Interrupt mode.
lypinator 0:bb348c97df44 586 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 587 * the configuration information for the specified DMA Stream.
lypinator 0:bb348c97df44 588 * @retval HAL status
lypinator 0:bb348c97df44 589 */
lypinator 0:bb348c97df44 590 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
lypinator 0:bb348c97df44 591 {
lypinator 0:bb348c97df44 592 if(hdma->State != HAL_DMA_STATE_BUSY)
lypinator 0:bb348c97df44 593 {
lypinator 0:bb348c97df44 594 hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
lypinator 0:bb348c97df44 595 return HAL_ERROR;
lypinator 0:bb348c97df44 596 }
lypinator 0:bb348c97df44 597 else
lypinator 0:bb348c97df44 598 {
lypinator 0:bb348c97df44 599 /* Set Abort State */
lypinator 0:bb348c97df44 600 hdma->State = HAL_DMA_STATE_ABORT;
lypinator 0:bb348c97df44 601
lypinator 0:bb348c97df44 602 /* Disable the stream */
lypinator 0:bb348c97df44 603 __HAL_DMA_DISABLE(hdma);
lypinator 0:bb348c97df44 604 }
lypinator 0:bb348c97df44 605
lypinator 0:bb348c97df44 606 return HAL_OK;
lypinator 0:bb348c97df44 607 }
lypinator 0:bb348c97df44 608
lypinator 0:bb348c97df44 609 /**
lypinator 0:bb348c97df44 610 * @brief Polling for transfer complete.
lypinator 0:bb348c97df44 611 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 612 * the configuration information for the specified DMA Stream.
lypinator 0:bb348c97df44 613 * @param CompleteLevel Specifies the DMA level complete.
lypinator 0:bb348c97df44 614 * @note The polling mode is kept in this version for legacy. it is recommanded to use the IT model instead.
lypinator 0:bb348c97df44 615 * This model could be used for debug purpose.
lypinator 0:bb348c97df44 616 * @note The HAL_DMA_PollForTransfer API cannot be used in circular and double buffering mode (automatic circular mode).
lypinator 0:bb348c97df44 617 * @param Timeout Timeout duration.
lypinator 0:bb348c97df44 618 * @retval HAL status
lypinator 0:bb348c97df44 619 */
lypinator 0:bb348c97df44 620 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout)
lypinator 0:bb348c97df44 621 {
lypinator 0:bb348c97df44 622 HAL_StatusTypeDef status = HAL_OK;
lypinator 0:bb348c97df44 623 uint32_t mask_cpltlevel;
lypinator 0:bb348c97df44 624 uint32_t tickstart = HAL_GetTick();
lypinator 0:bb348c97df44 625 uint32_t tmpisr;
lypinator 0:bb348c97df44 626
lypinator 0:bb348c97df44 627 /* calculate DMA base and stream number */
lypinator 0:bb348c97df44 628 DMA_Base_Registers *regs;
lypinator 0:bb348c97df44 629
lypinator 0:bb348c97df44 630 if(HAL_DMA_STATE_BUSY != hdma->State)
lypinator 0:bb348c97df44 631 {
lypinator 0:bb348c97df44 632 /* No transfer ongoing */
lypinator 0:bb348c97df44 633 hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
lypinator 0:bb348c97df44 634 __HAL_UNLOCK(hdma);
lypinator 0:bb348c97df44 635 return HAL_ERROR;
lypinator 0:bb348c97df44 636 }
lypinator 0:bb348c97df44 637
lypinator 0:bb348c97df44 638 /* Polling mode not supported in circular mode and double buffering mode */
lypinator 0:bb348c97df44 639 if ((hdma->Instance->CR & DMA_SxCR_CIRC) != RESET)
lypinator 0:bb348c97df44 640 {
lypinator 0:bb348c97df44 641 hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
lypinator 0:bb348c97df44 642 return HAL_ERROR;
lypinator 0:bb348c97df44 643 }
lypinator 0:bb348c97df44 644
lypinator 0:bb348c97df44 645 /* Get the level transfer complete flag */
lypinator 0:bb348c97df44 646 if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
lypinator 0:bb348c97df44 647 {
lypinator 0:bb348c97df44 648 /* Transfer Complete flag */
lypinator 0:bb348c97df44 649 mask_cpltlevel = DMA_FLAG_TCIF0_4 << hdma->StreamIndex;
lypinator 0:bb348c97df44 650 }
lypinator 0:bb348c97df44 651 else
lypinator 0:bb348c97df44 652 {
lypinator 0:bb348c97df44 653 /* Half Transfer Complete flag */
lypinator 0:bb348c97df44 654 mask_cpltlevel = DMA_FLAG_HTIF0_4 << hdma->StreamIndex;
lypinator 0:bb348c97df44 655 }
lypinator 0:bb348c97df44 656
lypinator 0:bb348c97df44 657 regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
lypinator 0:bb348c97df44 658 tmpisr = regs->ISR;
lypinator 0:bb348c97df44 659
lypinator 0:bb348c97df44 660 while(((tmpisr & mask_cpltlevel) == RESET) && ((hdma->ErrorCode & HAL_DMA_ERROR_TE) == RESET))
lypinator 0:bb348c97df44 661 {
lypinator 0:bb348c97df44 662 /* Check for the Timeout (Not applicable in circular mode)*/
lypinator 0:bb348c97df44 663 if(Timeout != HAL_MAX_DELAY)
lypinator 0:bb348c97df44 664 {
lypinator 0:bb348c97df44 665 if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
lypinator 0:bb348c97df44 666 {
lypinator 0:bb348c97df44 667 /* Update error code */
lypinator 0:bb348c97df44 668 hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
lypinator 0:bb348c97df44 669
lypinator 0:bb348c97df44 670 /* Process Unlocked */
lypinator 0:bb348c97df44 671 __HAL_UNLOCK(hdma);
lypinator 0:bb348c97df44 672
lypinator 0:bb348c97df44 673 /* Change the DMA state */
lypinator 0:bb348c97df44 674 hdma->State = HAL_DMA_STATE_READY;
lypinator 0:bb348c97df44 675
lypinator 0:bb348c97df44 676 return HAL_TIMEOUT;
lypinator 0:bb348c97df44 677 }
lypinator 0:bb348c97df44 678 }
lypinator 0:bb348c97df44 679
lypinator 0:bb348c97df44 680 /* Get the ISR register value */
lypinator 0:bb348c97df44 681 tmpisr = regs->ISR;
lypinator 0:bb348c97df44 682
lypinator 0:bb348c97df44 683 if((tmpisr & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET)
lypinator 0:bb348c97df44 684 {
lypinator 0:bb348c97df44 685 /* Update error code */
lypinator 0:bb348c97df44 686 hdma->ErrorCode |= HAL_DMA_ERROR_TE;
lypinator 0:bb348c97df44 687
lypinator 0:bb348c97df44 688 /* Clear the transfer error flag */
lypinator 0:bb348c97df44 689 regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex;
lypinator 0:bb348c97df44 690 }
lypinator 0:bb348c97df44 691
lypinator 0:bb348c97df44 692 if((tmpisr & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET)
lypinator 0:bb348c97df44 693 {
lypinator 0:bb348c97df44 694 /* Update error code */
lypinator 0:bb348c97df44 695 hdma->ErrorCode |= HAL_DMA_ERROR_FE;
lypinator 0:bb348c97df44 696
lypinator 0:bb348c97df44 697 /* Clear the FIFO error flag */
lypinator 0:bb348c97df44 698 regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex;
lypinator 0:bb348c97df44 699 }
lypinator 0:bb348c97df44 700
lypinator 0:bb348c97df44 701 if((tmpisr & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET)
lypinator 0:bb348c97df44 702 {
lypinator 0:bb348c97df44 703 /* Update error code */
lypinator 0:bb348c97df44 704 hdma->ErrorCode |= HAL_DMA_ERROR_DME;
lypinator 0:bb348c97df44 705
lypinator 0:bb348c97df44 706 /* Clear the Direct Mode error flag */
lypinator 0:bb348c97df44 707 regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex;
lypinator 0:bb348c97df44 708 }
lypinator 0:bb348c97df44 709 }
lypinator 0:bb348c97df44 710
lypinator 0:bb348c97df44 711 if(hdma->ErrorCode != HAL_DMA_ERROR_NONE)
lypinator 0:bb348c97df44 712 {
lypinator 0:bb348c97df44 713 if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != RESET)
lypinator 0:bb348c97df44 714 {
lypinator 0:bb348c97df44 715 HAL_DMA_Abort(hdma);
lypinator 0:bb348c97df44 716
lypinator 0:bb348c97df44 717 /* Clear the half transfer and transfer complete flags */
lypinator 0:bb348c97df44 718 regs->IFCR = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << hdma->StreamIndex;
lypinator 0:bb348c97df44 719
lypinator 0:bb348c97df44 720 /* Process Unlocked */
lypinator 0:bb348c97df44 721 __HAL_UNLOCK(hdma);
lypinator 0:bb348c97df44 722
lypinator 0:bb348c97df44 723 /* Change the DMA state */
lypinator 0:bb348c97df44 724 hdma->State= HAL_DMA_STATE_READY;
lypinator 0:bb348c97df44 725
lypinator 0:bb348c97df44 726 return HAL_ERROR;
lypinator 0:bb348c97df44 727 }
lypinator 0:bb348c97df44 728 }
lypinator 0:bb348c97df44 729
lypinator 0:bb348c97df44 730 /* Get the level transfer complete flag */
lypinator 0:bb348c97df44 731 if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
lypinator 0:bb348c97df44 732 {
lypinator 0:bb348c97df44 733 /* Clear the half transfer and transfer complete flags */
lypinator 0:bb348c97df44 734 regs->IFCR = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << hdma->StreamIndex;
lypinator 0:bb348c97df44 735
lypinator 0:bb348c97df44 736 /* Process Unlocked */
lypinator 0:bb348c97df44 737 __HAL_UNLOCK(hdma);
lypinator 0:bb348c97df44 738
lypinator 0:bb348c97df44 739 hdma->State = HAL_DMA_STATE_READY;
lypinator 0:bb348c97df44 740 }
lypinator 0:bb348c97df44 741 else
lypinator 0:bb348c97df44 742 {
lypinator 0:bb348c97df44 743 /* Clear the half transfer and transfer complete flags */
lypinator 0:bb348c97df44 744 regs->IFCR = (DMA_FLAG_HTIF0_4) << hdma->StreamIndex;
lypinator 0:bb348c97df44 745 }
lypinator 0:bb348c97df44 746
lypinator 0:bb348c97df44 747 return status;
lypinator 0:bb348c97df44 748 }
lypinator 0:bb348c97df44 749
lypinator 0:bb348c97df44 750 /**
lypinator 0:bb348c97df44 751 * @brief Handles DMA interrupt request.
lypinator 0:bb348c97df44 752 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 753 * the configuration information for the specified DMA Stream.
lypinator 0:bb348c97df44 754 * @retval None
lypinator 0:bb348c97df44 755 */
lypinator 0:bb348c97df44 756 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
lypinator 0:bb348c97df44 757 {
lypinator 0:bb348c97df44 758 uint32_t tmpisr;
lypinator 0:bb348c97df44 759 __IO uint32_t count = 0U;
lypinator 0:bb348c97df44 760 uint32_t timeout = SystemCoreClock / 9600U;
lypinator 0:bb348c97df44 761
lypinator 0:bb348c97df44 762 /* calculate DMA base and stream number */
lypinator 0:bb348c97df44 763 DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
lypinator 0:bb348c97df44 764
lypinator 0:bb348c97df44 765 tmpisr = regs->ISR;
lypinator 0:bb348c97df44 766
lypinator 0:bb348c97df44 767 /* Transfer Error Interrupt management ***************************************/
lypinator 0:bb348c97df44 768 if ((tmpisr & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET)
lypinator 0:bb348c97df44 769 {
lypinator 0:bb348c97df44 770 if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != RESET)
lypinator 0:bb348c97df44 771 {
lypinator 0:bb348c97df44 772 /* Disable the transfer error interrupt */
lypinator 0:bb348c97df44 773 hdma->Instance->CR &= ~(DMA_IT_TE);
lypinator 0:bb348c97df44 774
lypinator 0:bb348c97df44 775 /* Clear the transfer error flag */
lypinator 0:bb348c97df44 776 regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex;
lypinator 0:bb348c97df44 777
lypinator 0:bb348c97df44 778 /* Update error code */
lypinator 0:bb348c97df44 779 hdma->ErrorCode |= HAL_DMA_ERROR_TE;
lypinator 0:bb348c97df44 780 }
lypinator 0:bb348c97df44 781 }
lypinator 0:bb348c97df44 782 /* FIFO Error Interrupt management ******************************************/
lypinator 0:bb348c97df44 783 if ((tmpisr & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET)
lypinator 0:bb348c97df44 784 {
lypinator 0:bb348c97df44 785 if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_FE) != RESET)
lypinator 0:bb348c97df44 786 {
lypinator 0:bb348c97df44 787 /* Clear the FIFO error flag */
lypinator 0:bb348c97df44 788 regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex;
lypinator 0:bb348c97df44 789
lypinator 0:bb348c97df44 790 /* Update error code */
lypinator 0:bb348c97df44 791 hdma->ErrorCode |= HAL_DMA_ERROR_FE;
lypinator 0:bb348c97df44 792 }
lypinator 0:bb348c97df44 793 }
lypinator 0:bb348c97df44 794 /* Direct Mode Error Interrupt management ***********************************/
lypinator 0:bb348c97df44 795 if ((tmpisr & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET)
lypinator 0:bb348c97df44 796 {
lypinator 0:bb348c97df44 797 if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DME) != RESET)
lypinator 0:bb348c97df44 798 {
lypinator 0:bb348c97df44 799 /* Clear the direct mode error flag */
lypinator 0:bb348c97df44 800 regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex;
lypinator 0:bb348c97df44 801
lypinator 0:bb348c97df44 802 /* Update error code */
lypinator 0:bb348c97df44 803 hdma->ErrorCode |= HAL_DMA_ERROR_DME;
lypinator 0:bb348c97df44 804 }
lypinator 0:bb348c97df44 805 }
lypinator 0:bb348c97df44 806 /* Half Transfer Complete Interrupt management ******************************/
lypinator 0:bb348c97df44 807 if ((tmpisr & (DMA_FLAG_HTIF0_4 << hdma->StreamIndex)) != RESET)
lypinator 0:bb348c97df44 808 {
lypinator 0:bb348c97df44 809 if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != RESET)
lypinator 0:bb348c97df44 810 {
lypinator 0:bb348c97df44 811 /* Clear the half transfer complete flag */
lypinator 0:bb348c97df44 812 regs->IFCR = DMA_FLAG_HTIF0_4 << hdma->StreamIndex;
lypinator 0:bb348c97df44 813
lypinator 0:bb348c97df44 814 /* Multi_Buffering mode enabled */
lypinator 0:bb348c97df44 815 if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET)
lypinator 0:bb348c97df44 816 {
lypinator 0:bb348c97df44 817 /* Current memory buffer used is Memory 0 */
lypinator 0:bb348c97df44 818 if((hdma->Instance->CR & DMA_SxCR_CT) == RESET)
lypinator 0:bb348c97df44 819 {
lypinator 0:bb348c97df44 820 if(hdma->XferHalfCpltCallback != NULL)
lypinator 0:bb348c97df44 821 {
lypinator 0:bb348c97df44 822 /* Half transfer callback */
lypinator 0:bb348c97df44 823 hdma->XferHalfCpltCallback(hdma);
lypinator 0:bb348c97df44 824 }
lypinator 0:bb348c97df44 825 }
lypinator 0:bb348c97df44 826 /* Current memory buffer used is Memory 1 */
lypinator 0:bb348c97df44 827 else
lypinator 0:bb348c97df44 828 {
lypinator 0:bb348c97df44 829 if(hdma->XferM1HalfCpltCallback != NULL)
lypinator 0:bb348c97df44 830 {
lypinator 0:bb348c97df44 831 /* Half transfer callback */
lypinator 0:bb348c97df44 832 hdma->XferM1HalfCpltCallback(hdma);
lypinator 0:bb348c97df44 833 }
lypinator 0:bb348c97df44 834 }
lypinator 0:bb348c97df44 835 }
lypinator 0:bb348c97df44 836 else
lypinator 0:bb348c97df44 837 {
lypinator 0:bb348c97df44 838 /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
lypinator 0:bb348c97df44 839 if((hdma->Instance->CR & DMA_SxCR_CIRC) == RESET)
lypinator 0:bb348c97df44 840 {
lypinator 0:bb348c97df44 841 /* Disable the half transfer interrupt */
lypinator 0:bb348c97df44 842 hdma->Instance->CR &= ~(DMA_IT_HT);
lypinator 0:bb348c97df44 843 }
lypinator 0:bb348c97df44 844
lypinator 0:bb348c97df44 845 if(hdma->XferHalfCpltCallback != NULL)
lypinator 0:bb348c97df44 846 {
lypinator 0:bb348c97df44 847 /* Half transfer callback */
lypinator 0:bb348c97df44 848 hdma->XferHalfCpltCallback(hdma);
lypinator 0:bb348c97df44 849 }
lypinator 0:bb348c97df44 850 }
lypinator 0:bb348c97df44 851 }
lypinator 0:bb348c97df44 852 }
lypinator 0:bb348c97df44 853 /* Transfer Complete Interrupt management ***********************************/
lypinator 0:bb348c97df44 854 if ((tmpisr & (DMA_FLAG_TCIF0_4 << hdma->StreamIndex)) != RESET)
lypinator 0:bb348c97df44 855 {
lypinator 0:bb348c97df44 856 if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != RESET)
lypinator 0:bb348c97df44 857 {
lypinator 0:bb348c97df44 858 /* Clear the transfer complete flag */
lypinator 0:bb348c97df44 859 regs->IFCR = DMA_FLAG_TCIF0_4 << hdma->StreamIndex;
lypinator 0:bb348c97df44 860
lypinator 0:bb348c97df44 861 if(HAL_DMA_STATE_ABORT == hdma->State)
lypinator 0:bb348c97df44 862 {
lypinator 0:bb348c97df44 863 /* Disable all the transfer interrupts */
lypinator 0:bb348c97df44 864 hdma->Instance->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME);
lypinator 0:bb348c97df44 865 hdma->Instance->FCR &= ~(DMA_IT_FE);
lypinator 0:bb348c97df44 866
lypinator 0:bb348c97df44 867 if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))
lypinator 0:bb348c97df44 868 {
lypinator 0:bb348c97df44 869 hdma->Instance->CR &= ~(DMA_IT_HT);
lypinator 0:bb348c97df44 870 }
lypinator 0:bb348c97df44 871
lypinator 0:bb348c97df44 872 /* Clear all interrupt flags at correct offset within the register */
lypinator 0:bb348c97df44 873 regs->IFCR = 0x3FU << hdma->StreamIndex;
lypinator 0:bb348c97df44 874
lypinator 0:bb348c97df44 875 /* Process Unlocked */
lypinator 0:bb348c97df44 876 __HAL_UNLOCK(hdma);
lypinator 0:bb348c97df44 877
lypinator 0:bb348c97df44 878 /* Change the DMA state */
lypinator 0:bb348c97df44 879 hdma->State = HAL_DMA_STATE_READY;
lypinator 0:bb348c97df44 880
lypinator 0:bb348c97df44 881 if(hdma->XferAbortCallback != NULL)
lypinator 0:bb348c97df44 882 {
lypinator 0:bb348c97df44 883 hdma->XferAbortCallback(hdma);
lypinator 0:bb348c97df44 884 }
lypinator 0:bb348c97df44 885 return;
lypinator 0:bb348c97df44 886 }
lypinator 0:bb348c97df44 887
lypinator 0:bb348c97df44 888 if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET)
lypinator 0:bb348c97df44 889 {
lypinator 0:bb348c97df44 890 /* Current memory buffer used is Memory 0 */
lypinator 0:bb348c97df44 891 if((hdma->Instance->CR & DMA_SxCR_CT) == RESET)
lypinator 0:bb348c97df44 892 {
lypinator 0:bb348c97df44 893 if(hdma->XferM1CpltCallback != NULL)
lypinator 0:bb348c97df44 894 {
lypinator 0:bb348c97df44 895 /* Transfer complete Callback for memory1 */
lypinator 0:bb348c97df44 896 hdma->XferM1CpltCallback(hdma);
lypinator 0:bb348c97df44 897 }
lypinator 0:bb348c97df44 898 }
lypinator 0:bb348c97df44 899 /* Current memory buffer used is Memory 1 */
lypinator 0:bb348c97df44 900 else
lypinator 0:bb348c97df44 901 {
lypinator 0:bb348c97df44 902 if(hdma->XferCpltCallback != NULL)
lypinator 0:bb348c97df44 903 {
lypinator 0:bb348c97df44 904 /* Transfer complete Callback for memory0 */
lypinator 0:bb348c97df44 905 hdma->XferCpltCallback(hdma);
lypinator 0:bb348c97df44 906 }
lypinator 0:bb348c97df44 907 }
lypinator 0:bb348c97df44 908 }
lypinator 0:bb348c97df44 909 /* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */
lypinator 0:bb348c97df44 910 else
lypinator 0:bb348c97df44 911 {
lypinator 0:bb348c97df44 912 if((hdma->Instance->CR & DMA_SxCR_CIRC) == RESET)
lypinator 0:bb348c97df44 913 {
lypinator 0:bb348c97df44 914 /* Disable the transfer complete interrupt */
lypinator 0:bb348c97df44 915 hdma->Instance->CR &= ~(DMA_IT_TC);
lypinator 0:bb348c97df44 916
lypinator 0:bb348c97df44 917 /* Process Unlocked */
lypinator 0:bb348c97df44 918 __HAL_UNLOCK(hdma);
lypinator 0:bb348c97df44 919
lypinator 0:bb348c97df44 920 /* Change the DMA state */
lypinator 0:bb348c97df44 921 hdma->State = HAL_DMA_STATE_READY;
lypinator 0:bb348c97df44 922 }
lypinator 0:bb348c97df44 923
lypinator 0:bb348c97df44 924 if(hdma->XferCpltCallback != NULL)
lypinator 0:bb348c97df44 925 {
lypinator 0:bb348c97df44 926 /* Transfer complete callback */
lypinator 0:bb348c97df44 927 hdma->XferCpltCallback(hdma);
lypinator 0:bb348c97df44 928 }
lypinator 0:bb348c97df44 929 }
lypinator 0:bb348c97df44 930 }
lypinator 0:bb348c97df44 931 }
lypinator 0:bb348c97df44 932
lypinator 0:bb348c97df44 933 /* manage error case */
lypinator 0:bb348c97df44 934 if(hdma->ErrorCode != HAL_DMA_ERROR_NONE)
lypinator 0:bb348c97df44 935 {
lypinator 0:bb348c97df44 936 if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != RESET)
lypinator 0:bb348c97df44 937 {
lypinator 0:bb348c97df44 938 hdma->State = HAL_DMA_STATE_ABORT;
lypinator 0:bb348c97df44 939
lypinator 0:bb348c97df44 940 /* Disable the stream */
lypinator 0:bb348c97df44 941 __HAL_DMA_DISABLE(hdma);
lypinator 0:bb348c97df44 942
lypinator 0:bb348c97df44 943 do
lypinator 0:bb348c97df44 944 {
lypinator 0:bb348c97df44 945 if (++count > timeout)
lypinator 0:bb348c97df44 946 {
lypinator 0:bb348c97df44 947 break;
lypinator 0:bb348c97df44 948 }
lypinator 0:bb348c97df44 949 }
lypinator 0:bb348c97df44 950 while((hdma->Instance->CR & DMA_SxCR_EN) != RESET);
lypinator 0:bb348c97df44 951
lypinator 0:bb348c97df44 952 /* Process Unlocked */
lypinator 0:bb348c97df44 953 __HAL_UNLOCK(hdma);
lypinator 0:bb348c97df44 954
lypinator 0:bb348c97df44 955 /* Change the DMA state */
lypinator 0:bb348c97df44 956 hdma->State = HAL_DMA_STATE_READY;
lypinator 0:bb348c97df44 957 }
lypinator 0:bb348c97df44 958
lypinator 0:bb348c97df44 959 if(hdma->XferErrorCallback != NULL)
lypinator 0:bb348c97df44 960 {
lypinator 0:bb348c97df44 961 /* Transfer error callback */
lypinator 0:bb348c97df44 962 hdma->XferErrorCallback(hdma);
lypinator 0:bb348c97df44 963 }
lypinator 0:bb348c97df44 964 }
lypinator 0:bb348c97df44 965 }
lypinator 0:bb348c97df44 966
lypinator 0:bb348c97df44 967 /**
lypinator 0:bb348c97df44 968 * @brief Register callbacks
lypinator 0:bb348c97df44 969 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 970 * the configuration information for the specified DMA Stream.
lypinator 0:bb348c97df44 971 * @param CallbackID User Callback identifer
lypinator 0:bb348c97df44 972 * a DMA_HandleTypeDef structure as parameter.
lypinator 0:bb348c97df44 973 * @param pCallback pointer to private callbacsk function which has pointer to
lypinator 0:bb348c97df44 974 * a DMA_HandleTypeDef structure as parameter.
lypinator 0:bb348c97df44 975 * @retval HAL status
lypinator 0:bb348c97df44 976 */
lypinator 0:bb348c97df44 977 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma))
lypinator 0:bb348c97df44 978 {
lypinator 0:bb348c97df44 979
lypinator 0:bb348c97df44 980 HAL_StatusTypeDef status = HAL_OK;
lypinator 0:bb348c97df44 981
lypinator 0:bb348c97df44 982 /* Process locked */
lypinator 0:bb348c97df44 983 __HAL_LOCK(hdma);
lypinator 0:bb348c97df44 984
lypinator 0:bb348c97df44 985 if(HAL_DMA_STATE_READY == hdma->State)
lypinator 0:bb348c97df44 986 {
lypinator 0:bb348c97df44 987 switch (CallbackID)
lypinator 0:bb348c97df44 988 {
lypinator 0:bb348c97df44 989 case HAL_DMA_XFER_CPLT_CB_ID:
lypinator 0:bb348c97df44 990 hdma->XferCpltCallback = pCallback;
lypinator 0:bb348c97df44 991 break;
lypinator 0:bb348c97df44 992
lypinator 0:bb348c97df44 993 case HAL_DMA_XFER_HALFCPLT_CB_ID:
lypinator 0:bb348c97df44 994 hdma->XferHalfCpltCallback = pCallback;
lypinator 0:bb348c97df44 995 break;
lypinator 0:bb348c97df44 996
lypinator 0:bb348c97df44 997 case HAL_DMA_XFER_M1CPLT_CB_ID:
lypinator 0:bb348c97df44 998 hdma->XferM1CpltCallback = pCallback;
lypinator 0:bb348c97df44 999 break;
lypinator 0:bb348c97df44 1000
lypinator 0:bb348c97df44 1001 case HAL_DMA_XFER_M1HALFCPLT_CB_ID:
lypinator 0:bb348c97df44 1002 hdma->XferM1HalfCpltCallback = pCallback;
lypinator 0:bb348c97df44 1003 break;
lypinator 0:bb348c97df44 1004
lypinator 0:bb348c97df44 1005 case HAL_DMA_XFER_ERROR_CB_ID:
lypinator 0:bb348c97df44 1006 hdma->XferErrorCallback = pCallback;
lypinator 0:bb348c97df44 1007 break;
lypinator 0:bb348c97df44 1008
lypinator 0:bb348c97df44 1009 case HAL_DMA_XFER_ABORT_CB_ID:
lypinator 0:bb348c97df44 1010 hdma->XferAbortCallback = pCallback;
lypinator 0:bb348c97df44 1011 break;
lypinator 0:bb348c97df44 1012
lypinator 0:bb348c97df44 1013 default:
lypinator 0:bb348c97df44 1014 break;
lypinator 0:bb348c97df44 1015 }
lypinator 0:bb348c97df44 1016 }
lypinator 0:bb348c97df44 1017 else
lypinator 0:bb348c97df44 1018 {
lypinator 0:bb348c97df44 1019 /* Return error status */
lypinator 0:bb348c97df44 1020 status = HAL_ERROR;
lypinator 0:bb348c97df44 1021 }
lypinator 0:bb348c97df44 1022
lypinator 0:bb348c97df44 1023 /* Release Lock */
lypinator 0:bb348c97df44 1024 __HAL_UNLOCK(hdma);
lypinator 0:bb348c97df44 1025
lypinator 0:bb348c97df44 1026 return status;
lypinator 0:bb348c97df44 1027 }
lypinator 0:bb348c97df44 1028
lypinator 0:bb348c97df44 1029 /**
lypinator 0:bb348c97df44 1030 * @brief UnRegister callbacks
lypinator 0:bb348c97df44 1031 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 1032 * the configuration information for the specified DMA Stream.
lypinator 0:bb348c97df44 1033 * @param CallbackID User Callback identifer
lypinator 0:bb348c97df44 1034 * a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
lypinator 0:bb348c97df44 1035 * @retval HAL status
lypinator 0:bb348c97df44 1036 */
lypinator 0:bb348c97df44 1037 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)
lypinator 0:bb348c97df44 1038 {
lypinator 0:bb348c97df44 1039 HAL_StatusTypeDef status = HAL_OK;
lypinator 0:bb348c97df44 1040
lypinator 0:bb348c97df44 1041 /* Process locked */
lypinator 0:bb348c97df44 1042 __HAL_LOCK(hdma);
lypinator 0:bb348c97df44 1043
lypinator 0:bb348c97df44 1044 if(HAL_DMA_STATE_READY == hdma->State)
lypinator 0:bb348c97df44 1045 {
lypinator 0:bb348c97df44 1046 switch (CallbackID)
lypinator 0:bb348c97df44 1047 {
lypinator 0:bb348c97df44 1048 case HAL_DMA_XFER_CPLT_CB_ID:
lypinator 0:bb348c97df44 1049 hdma->XferCpltCallback = NULL;
lypinator 0:bb348c97df44 1050 break;
lypinator 0:bb348c97df44 1051
lypinator 0:bb348c97df44 1052 case HAL_DMA_XFER_HALFCPLT_CB_ID:
lypinator 0:bb348c97df44 1053 hdma->XferHalfCpltCallback = NULL;
lypinator 0:bb348c97df44 1054 break;
lypinator 0:bb348c97df44 1055
lypinator 0:bb348c97df44 1056 case HAL_DMA_XFER_M1CPLT_CB_ID:
lypinator 0:bb348c97df44 1057 hdma->XferM1CpltCallback = NULL;
lypinator 0:bb348c97df44 1058 break;
lypinator 0:bb348c97df44 1059
lypinator 0:bb348c97df44 1060 case HAL_DMA_XFER_M1HALFCPLT_CB_ID:
lypinator 0:bb348c97df44 1061 hdma->XferM1HalfCpltCallback = NULL;
lypinator 0:bb348c97df44 1062 break;
lypinator 0:bb348c97df44 1063
lypinator 0:bb348c97df44 1064 case HAL_DMA_XFER_ERROR_CB_ID:
lypinator 0:bb348c97df44 1065 hdma->XferErrorCallback = NULL;
lypinator 0:bb348c97df44 1066 break;
lypinator 0:bb348c97df44 1067
lypinator 0:bb348c97df44 1068 case HAL_DMA_XFER_ABORT_CB_ID:
lypinator 0:bb348c97df44 1069 hdma->XferAbortCallback = NULL;
lypinator 0:bb348c97df44 1070 break;
lypinator 0:bb348c97df44 1071
lypinator 0:bb348c97df44 1072 case HAL_DMA_XFER_ALL_CB_ID:
lypinator 0:bb348c97df44 1073 hdma->XferCpltCallback = NULL;
lypinator 0:bb348c97df44 1074 hdma->XferHalfCpltCallback = NULL;
lypinator 0:bb348c97df44 1075 hdma->XferM1CpltCallback = NULL;
lypinator 0:bb348c97df44 1076 hdma->XferM1HalfCpltCallback = NULL;
lypinator 0:bb348c97df44 1077 hdma->XferErrorCallback = NULL;
lypinator 0:bb348c97df44 1078 hdma->XferAbortCallback = NULL;
lypinator 0:bb348c97df44 1079 break;
lypinator 0:bb348c97df44 1080
lypinator 0:bb348c97df44 1081 default:
lypinator 0:bb348c97df44 1082 status = HAL_ERROR;
lypinator 0:bb348c97df44 1083 break;
lypinator 0:bb348c97df44 1084 }
lypinator 0:bb348c97df44 1085 }
lypinator 0:bb348c97df44 1086 else
lypinator 0:bb348c97df44 1087 {
lypinator 0:bb348c97df44 1088 status = HAL_ERROR;
lypinator 0:bb348c97df44 1089 }
lypinator 0:bb348c97df44 1090
lypinator 0:bb348c97df44 1091 /* Release Lock */
lypinator 0:bb348c97df44 1092 __HAL_UNLOCK(hdma);
lypinator 0:bb348c97df44 1093
lypinator 0:bb348c97df44 1094 return status;
lypinator 0:bb348c97df44 1095 }
lypinator 0:bb348c97df44 1096
lypinator 0:bb348c97df44 1097 /**
lypinator 0:bb348c97df44 1098 * @}
lypinator 0:bb348c97df44 1099 */
lypinator 0:bb348c97df44 1100
lypinator 0:bb348c97df44 1101 /** @addtogroup DMA_Exported_Functions_Group3
lypinator 0:bb348c97df44 1102 *
lypinator 0:bb348c97df44 1103 @verbatim
lypinator 0:bb348c97df44 1104 ===============================================================================
lypinator 0:bb348c97df44 1105 ##### State and Errors functions #####
lypinator 0:bb348c97df44 1106 ===============================================================================
lypinator 0:bb348c97df44 1107 [..]
lypinator 0:bb348c97df44 1108 This subsection provides functions allowing to
lypinator 0:bb348c97df44 1109 (+) Check the DMA state
lypinator 0:bb348c97df44 1110 (+) Get error code
lypinator 0:bb348c97df44 1111
lypinator 0:bb348c97df44 1112 @endverbatim
lypinator 0:bb348c97df44 1113 * @{
lypinator 0:bb348c97df44 1114 */
lypinator 0:bb348c97df44 1115
lypinator 0:bb348c97df44 1116 /**
lypinator 0:bb348c97df44 1117 * @brief Returns the DMA state.
lypinator 0:bb348c97df44 1118 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 1119 * the configuration information for the specified DMA Stream.
lypinator 0:bb348c97df44 1120 * @retval HAL state
lypinator 0:bb348c97df44 1121 */
lypinator 0:bb348c97df44 1122 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
lypinator 0:bb348c97df44 1123 {
lypinator 0:bb348c97df44 1124 return hdma->State;
lypinator 0:bb348c97df44 1125 }
lypinator 0:bb348c97df44 1126
lypinator 0:bb348c97df44 1127 /**
lypinator 0:bb348c97df44 1128 * @brief Return the DMA error code
lypinator 0:bb348c97df44 1129 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 1130 * the configuration information for the specified DMA Stream.
lypinator 0:bb348c97df44 1131 * @retval DMA Error Code
lypinator 0:bb348c97df44 1132 */
lypinator 0:bb348c97df44 1133 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
lypinator 0:bb348c97df44 1134 {
lypinator 0:bb348c97df44 1135 return hdma->ErrorCode;
lypinator 0:bb348c97df44 1136 }
lypinator 0:bb348c97df44 1137
lypinator 0:bb348c97df44 1138 /**
lypinator 0:bb348c97df44 1139 * @}
lypinator 0:bb348c97df44 1140 */
lypinator 0:bb348c97df44 1141
lypinator 0:bb348c97df44 1142 /**
lypinator 0:bb348c97df44 1143 * @}
lypinator 0:bb348c97df44 1144 */
lypinator 0:bb348c97df44 1145
lypinator 0:bb348c97df44 1146 /** @addtogroup DMA_Private_Functions
lypinator 0:bb348c97df44 1147 * @{
lypinator 0:bb348c97df44 1148 */
lypinator 0:bb348c97df44 1149
lypinator 0:bb348c97df44 1150 /**
lypinator 0:bb348c97df44 1151 * @brief Sets the DMA Transfer parameter.
lypinator 0:bb348c97df44 1152 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 1153 * the configuration information for the specified DMA Stream.
lypinator 0:bb348c97df44 1154 * @param SrcAddress The source memory Buffer address
lypinator 0:bb348c97df44 1155 * @param DstAddress The destination memory Buffer address
lypinator 0:bb348c97df44 1156 * @param DataLength The length of data to be transferred from source to destination
lypinator 0:bb348c97df44 1157 * @retval HAL status
lypinator 0:bb348c97df44 1158 */
lypinator 0:bb348c97df44 1159 static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
lypinator 0:bb348c97df44 1160 {
lypinator 0:bb348c97df44 1161 /* Clear DBM bit */
lypinator 0:bb348c97df44 1162 hdma->Instance->CR &= (uint32_t)(~DMA_SxCR_DBM);
lypinator 0:bb348c97df44 1163
lypinator 0:bb348c97df44 1164 /* Configure DMA Stream data length */
lypinator 0:bb348c97df44 1165 hdma->Instance->NDTR = DataLength;
lypinator 0:bb348c97df44 1166
lypinator 0:bb348c97df44 1167 /* Memory to Peripheral */
lypinator 0:bb348c97df44 1168 if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
lypinator 0:bb348c97df44 1169 {
lypinator 0:bb348c97df44 1170 /* Configure DMA Stream destination address */
lypinator 0:bb348c97df44 1171 hdma->Instance->PAR = DstAddress;
lypinator 0:bb348c97df44 1172
lypinator 0:bb348c97df44 1173 /* Configure DMA Stream source address */
lypinator 0:bb348c97df44 1174 hdma->Instance->M0AR = SrcAddress;
lypinator 0:bb348c97df44 1175 }
lypinator 0:bb348c97df44 1176 /* Peripheral to Memory */
lypinator 0:bb348c97df44 1177 else
lypinator 0:bb348c97df44 1178 {
lypinator 0:bb348c97df44 1179 /* Configure DMA Stream source address */
lypinator 0:bb348c97df44 1180 hdma->Instance->PAR = SrcAddress;
lypinator 0:bb348c97df44 1181
lypinator 0:bb348c97df44 1182 /* Configure DMA Stream destination address */
lypinator 0:bb348c97df44 1183 hdma->Instance->M0AR = DstAddress;
lypinator 0:bb348c97df44 1184 }
lypinator 0:bb348c97df44 1185 }
lypinator 0:bb348c97df44 1186
lypinator 0:bb348c97df44 1187 /**
lypinator 0:bb348c97df44 1188 * @brief Returns the DMA Stream base address depending on stream number
lypinator 0:bb348c97df44 1189 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 1190 * the configuration information for the specified DMA Stream.
lypinator 0:bb348c97df44 1191 * @retval Stream base address
lypinator 0:bb348c97df44 1192 */
lypinator 0:bb348c97df44 1193 static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma)
lypinator 0:bb348c97df44 1194 {
lypinator 0:bb348c97df44 1195 uint32_t stream_number = (((uint32_t)hdma->Instance & 0xFFU) - 16U) / 24U;
lypinator 0:bb348c97df44 1196
lypinator 0:bb348c97df44 1197 /* lookup table for necessary bitshift of flags within status registers */
lypinator 0:bb348c97df44 1198 static const uint8_t flagBitshiftOffset[8U] = {0U, 6U, 16U, 22U, 0U, 6U, 16U, 22U};
lypinator 0:bb348c97df44 1199 hdma->StreamIndex = flagBitshiftOffset[stream_number];
lypinator 0:bb348c97df44 1200
lypinator 0:bb348c97df44 1201 if (stream_number > 3U)
lypinator 0:bb348c97df44 1202 {
lypinator 0:bb348c97df44 1203 /* return pointer to HISR and HIFCR */
lypinator 0:bb348c97df44 1204 hdma->StreamBaseAddress = (((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU)) + 4U);
lypinator 0:bb348c97df44 1205 }
lypinator 0:bb348c97df44 1206 else
lypinator 0:bb348c97df44 1207 {
lypinator 0:bb348c97df44 1208 /* return pointer to LISR and LIFCR */
lypinator 0:bb348c97df44 1209 hdma->StreamBaseAddress = ((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU));
lypinator 0:bb348c97df44 1210 }
lypinator 0:bb348c97df44 1211
lypinator 0:bb348c97df44 1212 return hdma->StreamBaseAddress;
lypinator 0:bb348c97df44 1213 }
lypinator 0:bb348c97df44 1214
lypinator 0:bb348c97df44 1215 /**
lypinator 0:bb348c97df44 1216 * @brief Check compatibility between FIFO threshold level and size of the memory burst
lypinator 0:bb348c97df44 1217 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
lypinator 0:bb348c97df44 1218 * the configuration information for the specified DMA Stream.
lypinator 0:bb348c97df44 1219 * @retval HAL status
lypinator 0:bb348c97df44 1220 */
lypinator 0:bb348c97df44 1221 static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma)
lypinator 0:bb348c97df44 1222 {
lypinator 0:bb348c97df44 1223 HAL_StatusTypeDef status = HAL_OK;
lypinator 0:bb348c97df44 1224 uint32_t tmp = hdma->Init.FIFOThreshold;
lypinator 0:bb348c97df44 1225
lypinator 0:bb348c97df44 1226 /* Memory Data size equal to Byte */
lypinator 0:bb348c97df44 1227 if(hdma->Init.MemDataAlignment == DMA_MDATAALIGN_BYTE)
lypinator 0:bb348c97df44 1228 {
lypinator 0:bb348c97df44 1229 switch (tmp)
lypinator 0:bb348c97df44 1230 {
lypinator 0:bb348c97df44 1231 case DMA_FIFO_THRESHOLD_1QUARTERFULL:
lypinator 0:bb348c97df44 1232 case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
lypinator 0:bb348c97df44 1233 if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
lypinator 0:bb348c97df44 1234 {
lypinator 0:bb348c97df44 1235 status = HAL_ERROR;
lypinator 0:bb348c97df44 1236 }
lypinator 0:bb348c97df44 1237 break;
lypinator 0:bb348c97df44 1238 case DMA_FIFO_THRESHOLD_HALFFULL:
lypinator 0:bb348c97df44 1239 if (hdma->Init.MemBurst == DMA_MBURST_INC16)
lypinator 0:bb348c97df44 1240 {
lypinator 0:bb348c97df44 1241 status = HAL_ERROR;
lypinator 0:bb348c97df44 1242 }
lypinator 0:bb348c97df44 1243 break;
lypinator 0:bb348c97df44 1244 case DMA_FIFO_THRESHOLD_FULL:
lypinator 0:bb348c97df44 1245 break;
lypinator 0:bb348c97df44 1246 default:
lypinator 0:bb348c97df44 1247 break;
lypinator 0:bb348c97df44 1248 }
lypinator 0:bb348c97df44 1249 }
lypinator 0:bb348c97df44 1250
lypinator 0:bb348c97df44 1251 /* Memory Data size equal to Half-Word */
lypinator 0:bb348c97df44 1252 else if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
lypinator 0:bb348c97df44 1253 {
lypinator 0:bb348c97df44 1254 switch (tmp)
lypinator 0:bb348c97df44 1255 {
lypinator 0:bb348c97df44 1256 case DMA_FIFO_THRESHOLD_1QUARTERFULL:
lypinator 0:bb348c97df44 1257 case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
lypinator 0:bb348c97df44 1258 status = HAL_ERROR;
lypinator 0:bb348c97df44 1259 break;
lypinator 0:bb348c97df44 1260 case DMA_FIFO_THRESHOLD_HALFFULL:
lypinator 0:bb348c97df44 1261 if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
lypinator 0:bb348c97df44 1262 {
lypinator 0:bb348c97df44 1263 status = HAL_ERROR;
lypinator 0:bb348c97df44 1264 }
lypinator 0:bb348c97df44 1265 break;
lypinator 0:bb348c97df44 1266 case DMA_FIFO_THRESHOLD_FULL:
lypinator 0:bb348c97df44 1267 if (hdma->Init.MemBurst == DMA_MBURST_INC16)
lypinator 0:bb348c97df44 1268 {
lypinator 0:bb348c97df44 1269 status = HAL_ERROR;
lypinator 0:bb348c97df44 1270 }
lypinator 0:bb348c97df44 1271 break;
lypinator 0:bb348c97df44 1272 default:
lypinator 0:bb348c97df44 1273 break;
lypinator 0:bb348c97df44 1274 }
lypinator 0:bb348c97df44 1275 }
lypinator 0:bb348c97df44 1276
lypinator 0:bb348c97df44 1277 /* Memory Data size equal to Word */
lypinator 0:bb348c97df44 1278 else
lypinator 0:bb348c97df44 1279 {
lypinator 0:bb348c97df44 1280 switch (tmp)
lypinator 0:bb348c97df44 1281 {
lypinator 0:bb348c97df44 1282 case DMA_FIFO_THRESHOLD_1QUARTERFULL:
lypinator 0:bb348c97df44 1283 case DMA_FIFO_THRESHOLD_HALFFULL:
lypinator 0:bb348c97df44 1284 case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
lypinator 0:bb348c97df44 1285 status = HAL_ERROR;
lypinator 0:bb348c97df44 1286 break;
lypinator 0:bb348c97df44 1287 case DMA_FIFO_THRESHOLD_FULL:
lypinator 0:bb348c97df44 1288 if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
lypinator 0:bb348c97df44 1289 {
lypinator 0:bb348c97df44 1290 status = HAL_ERROR;
lypinator 0:bb348c97df44 1291 }
lypinator 0:bb348c97df44 1292 break;
lypinator 0:bb348c97df44 1293 default:
lypinator 0:bb348c97df44 1294 break;
lypinator 0:bb348c97df44 1295 }
lypinator 0:bb348c97df44 1296 }
lypinator 0:bb348c97df44 1297
lypinator 0:bb348c97df44 1298 return status;
lypinator 0:bb348c97df44 1299 }
lypinator 0:bb348c97df44 1300
lypinator 0:bb348c97df44 1301 /**
lypinator 0:bb348c97df44 1302 * @}
lypinator 0:bb348c97df44 1303 */
lypinator 0:bb348c97df44 1304
lypinator 0:bb348c97df44 1305 #endif /* HAL_DMA_MODULE_ENABLED */
lypinator 0:bb348c97df44 1306 /**
lypinator 0:bb348c97df44 1307 * @}
lypinator 0:bb348c97df44 1308 */
lypinator 0:bb348c97df44 1309
lypinator 0:bb348c97df44 1310 /**
lypinator 0:bb348c97df44 1311 * @}
lypinator 0:bb348c97df44 1312 */
lypinator 0:bb348c97df44 1313
lypinator 0:bb348c97df44 1314 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/