Thomas Lyp / DevLibMemoryController

Initial commit

Dependencies:   FastPWM

mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_cortex.h@0:bb348c97df44, 2020-09-16 (annotated)

Committer:
lypinator
Date:
Wed Sep 16 01:11:49 2020 +0000
Revision:
0:bb348c97df44
Added PWM

Who changed what in which revision?

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lypinator 0:bb348c97df44 1 /**
lypinator 0:bb348c97df44 2 ******************************************************************************
lypinator 0:bb348c97df44 3 * @file stm32f4xx_hal_cortex.h
lypinator 0:bb348c97df44 4 * @author MCD Application Team
lypinator 0:bb348c97df44 5 * @brief Header file of CORTEX HAL module.
lypinator 0:bb348c97df44 6 ******************************************************************************
lypinator 0:bb348c97df44 7 * @attention
lypinator 0:bb348c97df44 8 *
lypinator 0:bb348c97df44 9 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
lypinator 0:bb348c97df44 10 *
lypinator 0:bb348c97df44 11 * Redistribution and use in source and binary forms, with or without modification,
lypinator 0:bb348c97df44 12 * are permitted provided that the following conditions are met:
lypinator 0:bb348c97df44 13 * 1. Redistributions of source code must retain the above copyright notice,
lypinator 0:bb348c97df44 14 * this list of conditions and the following disclaimer.
lypinator 0:bb348c97df44 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
lypinator 0:bb348c97df44 16 * this list of conditions and the following disclaimer in the documentation
lypinator 0:bb348c97df44 17 * and/or other materials provided with the distribution.
lypinator 0:bb348c97df44 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
lypinator 0:bb348c97df44 19 * may be used to endorse or promote products derived from this software
lypinator 0:bb348c97df44 20 * without specific prior written permission.
lypinator 0:bb348c97df44 21 *
lypinator 0:bb348c97df44 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
lypinator 0:bb348c97df44 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
lypinator 0:bb348c97df44 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
lypinator 0:bb348c97df44 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
lypinator 0:bb348c97df44 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
lypinator 0:bb348c97df44 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
lypinator 0:bb348c97df44 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
lypinator 0:bb348c97df44 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
lypinator 0:bb348c97df44 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
lypinator 0:bb348c97df44 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
lypinator 0:bb348c97df44 32 *
lypinator 0:bb348c97df44 33 ******************************************************************************
lypinator 0:bb348c97df44 34 */
lypinator 0:bb348c97df44 35
lypinator 0:bb348c97df44 36 /* Define to prevent recursive inclusion -------------------------------------*/
lypinator 0:bb348c97df44 37 #ifndef __STM32F4xx_HAL_CORTEX_H
lypinator 0:bb348c97df44 38 #define __STM32F4xx_HAL_CORTEX_H
lypinator 0:bb348c97df44 39
lypinator 0:bb348c97df44 40 #ifdef __cplusplus
lypinator 0:bb348c97df44 41 extern "C" {
lypinator 0:bb348c97df44 42 #endif
lypinator 0:bb348c97df44 43
lypinator 0:bb348c97df44 44 /* Includes ------------------------------------------------------------------*/
lypinator 0:bb348c97df44 45 #include "stm32f4xx_hal_def.h"
lypinator 0:bb348c97df44 46
lypinator 0:bb348c97df44 47 /** @addtogroup STM32F4xx_HAL_Driver
lypinator 0:bb348c97df44 48 * @{
lypinator 0:bb348c97df44 49 */
lypinator 0:bb348c97df44 50
lypinator 0:bb348c97df44 51 /** @addtogroup CORTEX
lypinator 0:bb348c97df44 52 * @{
lypinator 0:bb348c97df44 53 */
lypinator 0:bb348c97df44 54 /* Exported types ------------------------------------------------------------*/
lypinator 0:bb348c97df44 55 /** @defgroup CORTEX_Exported_Types Cortex Exported Types
lypinator 0:bb348c97df44 56 * @{
lypinator 0:bb348c97df44 57 */
lypinator 0:bb348c97df44 58
lypinator 0:bb348c97df44 59 #if (__MPU_PRESENT == 1U)
lypinator 0:bb348c97df44 60 /** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
lypinator 0:bb348c97df44 61 * @brief MPU Region initialization structure
lypinator 0:bb348c97df44 62 * @{
lypinator 0:bb348c97df44 63 */
lypinator 0:bb348c97df44 64 typedef struct
lypinator 0:bb348c97df44 65 {
lypinator 0:bb348c97df44 66 uint8_t Enable; /*!< Specifies the status of the region.
lypinator 0:bb348c97df44 67 This parameter can be a value of @ref CORTEX_MPU_Region_Enable */
lypinator 0:bb348c97df44 68 uint8_t Number; /*!< Specifies the number of the region to protect.
lypinator 0:bb348c97df44 69 This parameter can be a value of @ref CORTEX_MPU_Region_Number */
lypinator 0:bb348c97df44 70 uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */
lypinator 0:bb348c97df44 71 uint8_t Size; /*!< Specifies the size of the region to protect.
lypinator 0:bb348c97df44 72 This parameter can be a value of @ref CORTEX_MPU_Region_Size */
lypinator 0:bb348c97df44 73 uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable.
lypinator 0:bb348c97df44 74 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
lypinator 0:bb348c97df44 75 uint8_t TypeExtField; /*!< Specifies the TEX field level.
lypinator 0:bb348c97df44 76 This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */
lypinator 0:bb348c97df44 77 uint8_t AccessPermission; /*!< Specifies the region access permission type.
lypinator 0:bb348c97df44 78 This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */
lypinator 0:bb348c97df44 79 uint8_t DisableExec; /*!< Specifies the instruction access status.
lypinator 0:bb348c97df44 80 This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */
lypinator 0:bb348c97df44 81 uint8_t IsShareable; /*!< Specifies the shareability status of the protected region.
lypinator 0:bb348c97df44 82 This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */
lypinator 0:bb348c97df44 83 uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected.
lypinator 0:bb348c97df44 84 This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */
lypinator 0:bb348c97df44 85 uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region.
lypinator 0:bb348c97df44 86 This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */
lypinator 0:bb348c97df44 87 }MPU_Region_InitTypeDef;
lypinator 0:bb348c97df44 88 /**
lypinator 0:bb348c97df44 89 * @}
lypinator 0:bb348c97df44 90 */
lypinator 0:bb348c97df44 91 #endif /* __MPU_PRESENT */
lypinator 0:bb348c97df44 92
lypinator 0:bb348c97df44 93 /**
lypinator 0:bb348c97df44 94 * @}
lypinator 0:bb348c97df44 95 */
lypinator 0:bb348c97df44 96
lypinator 0:bb348c97df44 97 /* Exported constants --------------------------------------------------------*/
lypinator 0:bb348c97df44 98
lypinator 0:bb348c97df44 99 /** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
lypinator 0:bb348c97df44 100 * @{
lypinator 0:bb348c97df44 101 */
lypinator 0:bb348c97df44 102
lypinator 0:bb348c97df44 103 /** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
lypinator 0:bb348c97df44 104 * @{
lypinator 0:bb348c97df44 105 */
lypinator 0:bb348c97df44 106 #define NVIC_PRIORITYGROUP_0 0x00000007U /*!< 0 bits for pre-emption priority
lypinator 0:bb348c97df44 107 4 bits for subpriority */
lypinator 0:bb348c97df44 108 #define NVIC_PRIORITYGROUP_1 0x00000006U /*!< 1 bits for pre-emption priority
lypinator 0:bb348c97df44 109 3 bits for subpriority */
lypinator 0:bb348c97df44 110 #define NVIC_PRIORITYGROUP_2 0x00000005U /*!< 2 bits for pre-emption priority
lypinator 0:bb348c97df44 111 2 bits for subpriority */
lypinator 0:bb348c97df44 112 #define NVIC_PRIORITYGROUP_3 0x00000004U /*!< 3 bits for pre-emption priority
lypinator 0:bb348c97df44 113 1 bits for subpriority */
lypinator 0:bb348c97df44 114 #define NVIC_PRIORITYGROUP_4 0x00000003U /*!< 4 bits for pre-emption priority
lypinator 0:bb348c97df44 115 0 bits for subpriority */
lypinator 0:bb348c97df44 116 /**
lypinator 0:bb348c97df44 117 * @}
lypinator 0:bb348c97df44 118 */
lypinator 0:bb348c97df44 119
lypinator 0:bb348c97df44 120 /** @defgroup CORTEX_SysTick_clock_source CORTEX _SysTick clock source
lypinator 0:bb348c97df44 121 * @{
lypinator 0:bb348c97df44 122 */
lypinator 0:bb348c97df44 123 #define SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U
lypinator 0:bb348c97df44 124 #define SYSTICK_CLKSOURCE_HCLK 0x00000004U
lypinator 0:bb348c97df44 125
lypinator 0:bb348c97df44 126 /**
lypinator 0:bb348c97df44 127 * @}
lypinator 0:bb348c97df44 128 */
lypinator 0:bb348c97df44 129
lypinator 0:bb348c97df44 130 #if (__MPU_PRESENT == 1)
lypinator 0:bb348c97df44 131 /** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control
lypinator 0:bb348c97df44 132 * @{
lypinator 0:bb348c97df44 133 */
lypinator 0:bb348c97df44 134 #define MPU_HFNMI_PRIVDEF_NONE 0x00000000U
lypinator 0:bb348c97df44 135 #define MPU_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk
lypinator 0:bb348c97df44 136 #define MPU_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk
lypinator 0:bb348c97df44 137 #define MPU_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk)
lypinator 0:bb348c97df44 138
lypinator 0:bb348c97df44 139 /**
lypinator 0:bb348c97df44 140 * @}
lypinator 0:bb348c97df44 141 */
lypinator 0:bb348c97df44 142
lypinator 0:bb348c97df44 143 /** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
lypinator 0:bb348c97df44 144 * @{
lypinator 0:bb348c97df44 145 */
lypinator 0:bb348c97df44 146 #define MPU_REGION_ENABLE ((uint8_t)0x01)
lypinator 0:bb348c97df44 147 #define MPU_REGION_DISABLE ((uint8_t)0x00)
lypinator 0:bb348c97df44 148 /**
lypinator 0:bb348c97df44 149 * @}
lypinator 0:bb348c97df44 150 */
lypinator 0:bb348c97df44 151
lypinator 0:bb348c97df44 152 /** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
lypinator 0:bb348c97df44 153 * @{
lypinator 0:bb348c97df44 154 */
lypinator 0:bb348c97df44 155 #define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00)
lypinator 0:bb348c97df44 156 #define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01)
lypinator 0:bb348c97df44 157 /**
lypinator 0:bb348c97df44 158 * @}
lypinator 0:bb348c97df44 159 */
lypinator 0:bb348c97df44 160
lypinator 0:bb348c97df44 161 /** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
lypinator 0:bb348c97df44 162 * @{
lypinator 0:bb348c97df44 163 */
lypinator 0:bb348c97df44 164 #define MPU_ACCESS_SHAREABLE ((uint8_t)0x01)
lypinator 0:bb348c97df44 165 #define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00)
lypinator 0:bb348c97df44 166 /**
lypinator 0:bb348c97df44 167 * @}
lypinator 0:bb348c97df44 168 */
lypinator 0:bb348c97df44 169
lypinator 0:bb348c97df44 170 /** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
lypinator 0:bb348c97df44 171 * @{
lypinator 0:bb348c97df44 172 */
lypinator 0:bb348c97df44 173 #define MPU_ACCESS_CACHEABLE ((uint8_t)0x01)
lypinator 0:bb348c97df44 174 #define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00)
lypinator 0:bb348c97df44 175 /**
lypinator 0:bb348c97df44 176 * @}
lypinator 0:bb348c97df44 177 */
lypinator 0:bb348c97df44 178
lypinator 0:bb348c97df44 179 /** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
lypinator 0:bb348c97df44 180 * @{
lypinator 0:bb348c97df44 181 */
lypinator 0:bb348c97df44 182 #define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01)
lypinator 0:bb348c97df44 183 #define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00)
lypinator 0:bb348c97df44 184 /**
lypinator 0:bb348c97df44 185 * @}
lypinator 0:bb348c97df44 186 */
lypinator 0:bb348c97df44 187
lypinator 0:bb348c97df44 188 /** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels
lypinator 0:bb348c97df44 189 * @{
lypinator 0:bb348c97df44 190 */
lypinator 0:bb348c97df44 191 #define MPU_TEX_LEVEL0 ((uint8_t)0x00)
lypinator 0:bb348c97df44 192 #define MPU_TEX_LEVEL1 ((uint8_t)0x01)
lypinator 0:bb348c97df44 193 #define MPU_TEX_LEVEL2 ((uint8_t)0x02)
lypinator 0:bb348c97df44 194 /**
lypinator 0:bb348c97df44 195 * @}
lypinator 0:bb348c97df44 196 */
lypinator 0:bb348c97df44 197
lypinator 0:bb348c97df44 198 /** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
lypinator 0:bb348c97df44 199 * @{
lypinator 0:bb348c97df44 200 */
lypinator 0:bb348c97df44 201 #define MPU_REGION_SIZE_32B ((uint8_t)0x04)
lypinator 0:bb348c97df44 202 #define MPU_REGION_SIZE_64B ((uint8_t)0x05)
lypinator 0:bb348c97df44 203 #define MPU_REGION_SIZE_128B ((uint8_t)0x06)
lypinator 0:bb348c97df44 204 #define MPU_REGION_SIZE_256B ((uint8_t)0x07)
lypinator 0:bb348c97df44 205 #define MPU_REGION_SIZE_512B ((uint8_t)0x08)
lypinator 0:bb348c97df44 206 #define MPU_REGION_SIZE_1KB ((uint8_t)0x09)
lypinator 0:bb348c97df44 207 #define MPU_REGION_SIZE_2KB ((uint8_t)0x0A)
lypinator 0:bb348c97df44 208 #define MPU_REGION_SIZE_4KB ((uint8_t)0x0B)
lypinator 0:bb348c97df44 209 #define MPU_REGION_SIZE_8KB ((uint8_t)0x0C)
lypinator 0:bb348c97df44 210 #define MPU_REGION_SIZE_16KB ((uint8_t)0x0D)
lypinator 0:bb348c97df44 211 #define MPU_REGION_SIZE_32KB ((uint8_t)0x0E)
lypinator 0:bb348c97df44 212 #define MPU_REGION_SIZE_64KB ((uint8_t)0x0F)
lypinator 0:bb348c97df44 213 #define MPU_REGION_SIZE_128KB ((uint8_t)0x10)
lypinator 0:bb348c97df44 214 #define MPU_REGION_SIZE_256KB ((uint8_t)0x11)
lypinator 0:bb348c97df44 215 #define MPU_REGION_SIZE_512KB ((uint8_t)0x12)
lypinator 0:bb348c97df44 216 #define MPU_REGION_SIZE_1MB ((uint8_t)0x13)
lypinator 0:bb348c97df44 217 #define MPU_REGION_SIZE_2MB ((uint8_t)0x14)
lypinator 0:bb348c97df44 218 #define MPU_REGION_SIZE_4MB ((uint8_t)0x15)
lypinator 0:bb348c97df44 219 #define MPU_REGION_SIZE_8MB ((uint8_t)0x16)
lypinator 0:bb348c97df44 220 #define MPU_REGION_SIZE_16MB ((uint8_t)0x17)
lypinator 0:bb348c97df44 221 #define MPU_REGION_SIZE_32MB ((uint8_t)0x18)
lypinator 0:bb348c97df44 222 #define MPU_REGION_SIZE_64MB ((uint8_t)0x19)
lypinator 0:bb348c97df44 223 #define MPU_REGION_SIZE_128MB ((uint8_t)0x1A)
lypinator 0:bb348c97df44 224 #define MPU_REGION_SIZE_256MB ((uint8_t)0x1B)
lypinator 0:bb348c97df44 225 #define MPU_REGION_SIZE_512MB ((uint8_t)0x1C)
lypinator 0:bb348c97df44 226 #define MPU_REGION_SIZE_1GB ((uint8_t)0x1D)
lypinator 0:bb348c97df44 227 #define MPU_REGION_SIZE_2GB ((uint8_t)0x1E)
lypinator 0:bb348c97df44 228 #define MPU_REGION_SIZE_4GB ((uint8_t)0x1F)
lypinator 0:bb348c97df44 229 /**
lypinator 0:bb348c97df44 230 * @}
lypinator 0:bb348c97df44 231 */
lypinator 0:bb348c97df44 232
lypinator 0:bb348c97df44 233 /** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
lypinator 0:bb348c97df44 234 * @{
lypinator 0:bb348c97df44 235 */
lypinator 0:bb348c97df44 236 #define MPU_REGION_NO_ACCESS ((uint8_t)0x00)
lypinator 0:bb348c97df44 237 #define MPU_REGION_PRIV_RW ((uint8_t)0x01)
lypinator 0:bb348c97df44 238 #define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02)
lypinator 0:bb348c97df44 239 #define MPU_REGION_FULL_ACCESS ((uint8_t)0x03)
lypinator 0:bb348c97df44 240 #define MPU_REGION_PRIV_RO ((uint8_t)0x05)
lypinator 0:bb348c97df44 241 #define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06)
lypinator 0:bb348c97df44 242 /**
lypinator 0:bb348c97df44 243 * @}
lypinator 0:bb348c97df44 244 */
lypinator 0:bb348c97df44 245
lypinator 0:bb348c97df44 246 /** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
lypinator 0:bb348c97df44 247 * @{
lypinator 0:bb348c97df44 248 */
lypinator 0:bb348c97df44 249 #define MPU_REGION_NUMBER0 ((uint8_t)0x00)
lypinator 0:bb348c97df44 250 #define MPU_REGION_NUMBER1 ((uint8_t)0x01)
lypinator 0:bb348c97df44 251 #define MPU_REGION_NUMBER2 ((uint8_t)0x02)
lypinator 0:bb348c97df44 252 #define MPU_REGION_NUMBER3 ((uint8_t)0x03)
lypinator 0:bb348c97df44 253 #define MPU_REGION_NUMBER4 ((uint8_t)0x04)
lypinator 0:bb348c97df44 254 #define MPU_REGION_NUMBER5 ((uint8_t)0x05)
lypinator 0:bb348c97df44 255 #define MPU_REGION_NUMBER6 ((uint8_t)0x06)
lypinator 0:bb348c97df44 256 #define MPU_REGION_NUMBER7 ((uint8_t)0x07)
lypinator 0:bb348c97df44 257 /**
lypinator 0:bb348c97df44 258 * @}
lypinator 0:bb348c97df44 259 */
lypinator 0:bb348c97df44 260 #endif /* __MPU_PRESENT */
lypinator 0:bb348c97df44 261
lypinator 0:bb348c97df44 262 /**
lypinator 0:bb348c97df44 263 * @}
lypinator 0:bb348c97df44 264 */
lypinator 0:bb348c97df44 265
lypinator 0:bb348c97df44 266
lypinator 0:bb348c97df44 267 /* Exported Macros -----------------------------------------------------------*/
lypinator 0:bb348c97df44 268
lypinator 0:bb348c97df44 269 /* Exported functions --------------------------------------------------------*/
lypinator 0:bb348c97df44 270 /** @addtogroup CORTEX_Exported_Functions
lypinator 0:bb348c97df44 271 * @{
lypinator 0:bb348c97df44 272 */
lypinator 0:bb348c97df44 273
lypinator 0:bb348c97df44 274 /** @addtogroup CORTEX_Exported_Functions_Group1
lypinator 0:bb348c97df44 275 * @{
lypinator 0:bb348c97df44 276 */
lypinator 0:bb348c97df44 277 /* Initialization and de-initialization functions *****************************/
lypinator 0:bb348c97df44 278 void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
lypinator 0:bb348c97df44 279 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
lypinator 0:bb348c97df44 280 void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
lypinator 0:bb348c97df44 281 void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
lypinator 0:bb348c97df44 282 void HAL_NVIC_SystemReset(void);
lypinator 0:bb348c97df44 283 uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
lypinator 0:bb348c97df44 284 /**
lypinator 0:bb348c97df44 285 * @}
lypinator 0:bb348c97df44 286 */
lypinator 0:bb348c97df44 287
lypinator 0:bb348c97df44 288 /** @addtogroup CORTEX_Exported_Functions_Group2
lypinator 0:bb348c97df44 289 * @{
lypinator 0:bb348c97df44 290 */
lypinator 0:bb348c97df44 291 /* Peripheral Control functions ***********************************************/
lypinator 0:bb348c97df44 292 uint32_t HAL_NVIC_GetPriorityGrouping(void);
lypinator 0:bb348c97df44 293 void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);
lypinator 0:bb348c97df44 294 uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
lypinator 0:bb348c97df44 295 void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
lypinator 0:bb348c97df44 296 void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
lypinator 0:bb348c97df44 297 uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);
lypinator 0:bb348c97df44 298 void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
lypinator 0:bb348c97df44 299 void HAL_SYSTICK_IRQHandler(void);
lypinator 0:bb348c97df44 300 void HAL_SYSTICK_Callback(void);
lypinator 0:bb348c97df44 301
lypinator 0:bb348c97df44 302 #if (__MPU_PRESENT == 1U)
lypinator 0:bb348c97df44 303 void HAL_MPU_Enable(uint32_t MPU_Control);
lypinator 0:bb348c97df44 304 void HAL_MPU_Disable(void);
lypinator 0:bb348c97df44 305 void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
lypinator 0:bb348c97df44 306 #endif /* __MPU_PRESENT */
lypinator 0:bb348c97df44 307 /**
lypinator 0:bb348c97df44 308 * @}
lypinator 0:bb348c97df44 309 */
lypinator 0:bb348c97df44 310
lypinator 0:bb348c97df44 311 /**
lypinator 0:bb348c97df44 312 * @}
lypinator 0:bb348c97df44 313 */
lypinator 0:bb348c97df44 314
lypinator 0:bb348c97df44 315 /* Private types -------------------------------------------------------------*/
lypinator 0:bb348c97df44 316 /* Private variables ---------------------------------------------------------*/
lypinator 0:bb348c97df44 317 /* Private constants ---------------------------------------------------------*/
lypinator 0:bb348c97df44 318 /* Private macros ------------------------------------------------------------*/
lypinator 0:bb348c97df44 319 /** @defgroup CORTEX_Private_Macros CORTEX Private Macros
lypinator 0:bb348c97df44 320 * @{
lypinator 0:bb348c97df44 321 */
lypinator 0:bb348c97df44 322 #define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \
lypinator 0:bb348c97df44 323 ((GROUP) == NVIC_PRIORITYGROUP_1) || \
lypinator 0:bb348c97df44 324 ((GROUP) == NVIC_PRIORITYGROUP_2) || \
lypinator 0:bb348c97df44 325 ((GROUP) == NVIC_PRIORITYGROUP_3) || \
lypinator 0:bb348c97df44 326 ((GROUP) == NVIC_PRIORITYGROUP_4))
lypinator 0:bb348c97df44 327
lypinator 0:bb348c97df44 328 #define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)
lypinator 0:bb348c97df44 329
lypinator 0:bb348c97df44 330 #define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)
lypinator 0:bb348c97df44 331
lypinator 0:bb348c97df44 332 #define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= (IRQn_Type)0x00U)
lypinator 0:bb348c97df44 333
lypinator 0:bb348c97df44 334 #define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
lypinator 0:bb348c97df44 335 ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
lypinator 0:bb348c97df44 336
lypinator 0:bb348c97df44 337 #if (__MPU_PRESENT == 1U)
lypinator 0:bb348c97df44 338 #define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \
lypinator 0:bb348c97df44 339 ((STATE) == MPU_REGION_DISABLE))
lypinator 0:bb348c97df44 340
lypinator 0:bb348c97df44 341 #define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
lypinator 0:bb348c97df44 342 ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
lypinator 0:bb348c97df44 343
lypinator 0:bb348c97df44 344 #define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \
lypinator 0:bb348c97df44 345 ((STATE) == MPU_ACCESS_NOT_SHAREABLE))
lypinator 0:bb348c97df44 346
lypinator 0:bb348c97df44 347 #define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \
lypinator 0:bb348c97df44 348 ((STATE) == MPU_ACCESS_NOT_CACHEABLE))
lypinator 0:bb348c97df44 349
lypinator 0:bb348c97df44 350 #define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \
lypinator 0:bb348c97df44 351 ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
lypinator 0:bb348c97df44 352
lypinator 0:bb348c97df44 353 #define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \
lypinator 0:bb348c97df44 354 ((TYPE) == MPU_TEX_LEVEL1) || \
lypinator 0:bb348c97df44 355 ((TYPE) == MPU_TEX_LEVEL2))
lypinator 0:bb348c97df44 356
lypinator 0:bb348c97df44 357 #define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \
lypinator 0:bb348c97df44 358 ((TYPE) == MPU_REGION_PRIV_RW) || \
lypinator 0:bb348c97df44 359 ((TYPE) == MPU_REGION_PRIV_RW_URO) || \
lypinator 0:bb348c97df44 360 ((TYPE) == MPU_REGION_FULL_ACCESS) || \
lypinator 0:bb348c97df44 361 ((TYPE) == MPU_REGION_PRIV_RO) || \
lypinator 0:bb348c97df44 362 ((TYPE) == MPU_REGION_PRIV_RO_URO))
lypinator 0:bb348c97df44 363
lypinator 0:bb348c97df44 364 #define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \
lypinator 0:bb348c97df44 365 ((NUMBER) == MPU_REGION_NUMBER1) || \
lypinator 0:bb348c97df44 366 ((NUMBER) == MPU_REGION_NUMBER2) || \
lypinator 0:bb348c97df44 367 ((NUMBER) == MPU_REGION_NUMBER3) || \
lypinator 0:bb348c97df44 368 ((NUMBER) == MPU_REGION_NUMBER4) || \
lypinator 0:bb348c97df44 369 ((NUMBER) == MPU_REGION_NUMBER5) || \
lypinator 0:bb348c97df44 370 ((NUMBER) == MPU_REGION_NUMBER6) || \
lypinator 0:bb348c97df44 371 ((NUMBER) == MPU_REGION_NUMBER7))
lypinator 0:bb348c97df44 372
lypinator 0:bb348c97df44 373 #define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \
lypinator 0:bb348c97df44 374 ((SIZE) == MPU_REGION_SIZE_64B) || \
lypinator 0:bb348c97df44 375 ((SIZE) == MPU_REGION_SIZE_128B) || \
lypinator 0:bb348c97df44 376 ((SIZE) == MPU_REGION_SIZE_256B) || \
lypinator 0:bb348c97df44 377 ((SIZE) == MPU_REGION_SIZE_512B) || \
lypinator 0:bb348c97df44 378 ((SIZE) == MPU_REGION_SIZE_1KB) || \
lypinator 0:bb348c97df44 379 ((SIZE) == MPU_REGION_SIZE_2KB) || \
lypinator 0:bb348c97df44 380 ((SIZE) == MPU_REGION_SIZE_4KB) || \
lypinator 0:bb348c97df44 381 ((SIZE) == MPU_REGION_SIZE_8KB) || \
lypinator 0:bb348c97df44 382 ((SIZE) == MPU_REGION_SIZE_16KB) || \
lypinator 0:bb348c97df44 383 ((SIZE) == MPU_REGION_SIZE_32KB) || \
lypinator 0:bb348c97df44 384 ((SIZE) == MPU_REGION_SIZE_64KB) || \
lypinator 0:bb348c97df44 385 ((SIZE) == MPU_REGION_SIZE_128KB) || \
lypinator 0:bb348c97df44 386 ((SIZE) == MPU_REGION_SIZE_256KB) || \
lypinator 0:bb348c97df44 387 ((SIZE) == MPU_REGION_SIZE_512KB) || \
lypinator 0:bb348c97df44 388 ((SIZE) == MPU_REGION_SIZE_1MB) || \
lypinator 0:bb348c97df44 389 ((SIZE) == MPU_REGION_SIZE_2MB) || \
lypinator 0:bb348c97df44 390 ((SIZE) == MPU_REGION_SIZE_4MB) || \
lypinator 0:bb348c97df44 391 ((SIZE) == MPU_REGION_SIZE_8MB) || \
lypinator 0:bb348c97df44 392 ((SIZE) == MPU_REGION_SIZE_16MB) || \
lypinator 0:bb348c97df44 393 ((SIZE) == MPU_REGION_SIZE_32MB) || \
lypinator 0:bb348c97df44 394 ((SIZE) == MPU_REGION_SIZE_64MB) || \
lypinator 0:bb348c97df44 395 ((SIZE) == MPU_REGION_SIZE_128MB) || \
lypinator 0:bb348c97df44 396 ((SIZE) == MPU_REGION_SIZE_256MB) || \
lypinator 0:bb348c97df44 397 ((SIZE) == MPU_REGION_SIZE_512MB) || \
lypinator 0:bb348c97df44 398 ((SIZE) == MPU_REGION_SIZE_1GB) || \
lypinator 0:bb348c97df44 399 ((SIZE) == MPU_REGION_SIZE_2GB) || \
lypinator 0:bb348c97df44 400 ((SIZE) == MPU_REGION_SIZE_4GB))
lypinator 0:bb348c97df44 401
lypinator 0:bb348c97df44 402 #define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF)
lypinator 0:bb348c97df44 403 #endif /* __MPU_PRESENT */
lypinator 0:bb348c97df44 404
lypinator 0:bb348c97df44 405 /**
lypinator 0:bb348c97df44 406 * @}
lypinator 0:bb348c97df44 407 */
lypinator 0:bb348c97df44 408
lypinator 0:bb348c97df44 409 /* Private functions ---------------------------------------------------------*/
lypinator 0:bb348c97df44 410
lypinator 0:bb348c97df44 411 /**
lypinator 0:bb348c97df44 412 * @}
lypinator 0:bb348c97df44 413 */
lypinator 0:bb348c97df44 414
lypinator 0:bb348c97df44 415 /**
lypinator 0:bb348c97df44 416 * @}
lypinator 0:bb348c97df44 417 */
lypinator 0:bb348c97df44 418
lypinator 0:bb348c97df44 419 #ifdef __cplusplus
lypinator 0:bb348c97df44 420 }
lypinator 0:bb348c97df44 421 #endif
lypinator 0:bb348c97df44 422
lypinator 0:bb348c97df44 423 #endif /* __STM32F4xx_HAL_CORTEX_H */
lypinator 0:bb348c97df44 424
lypinator 0:bb348c97df44 425
lypinator 0:bb348c97df44 426 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/