Thomas Lyp / DevLibMemoryController

Initial commit

Dependencies:   FastPWM

mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446ZE/system_clock.c@0:bb348c97df44, 2020-09-16 (annotated)

Committer:
lypinator
Date:
Wed Sep 16 01:11:49 2020 +0000
Revision:
0:bb348c97df44
Added PWM

Who changed what in which revision?

UserRevisionLine numberNew contents of line
lypinator 0:bb348c97df44 1 /* mbed Microcontroller Library
lypinator 0:bb348c97df44 2 * Copyright (c) 2006-2017 ARM Limited
lypinator 0:bb348c97df44 3 *
lypinator 0:bb348c97df44 4 * Licensed under the Apache License, Version 2.0 (the "License");
lypinator 0:bb348c97df44 5 * you may not use this file except in compliance with the License.
lypinator 0:bb348c97df44 6 * You may obtain a copy of the License at
lypinator 0:bb348c97df44 7 *
lypinator 0:bb348c97df44 8 * http://www.apache.org/licenses/LICENSE-2.0
lypinator 0:bb348c97df44 9 *
lypinator 0:bb348c97df44 10 * Unless required by applicable law or agreed to in writing, software
lypinator 0:bb348c97df44 11 * distributed under the License is distributed on an "AS IS" BASIS,
lypinator 0:bb348c97df44 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
lypinator 0:bb348c97df44 13 * See the License for the specific language governing permissions and
lypinator 0:bb348c97df44 14 * limitations under the License.
lypinator 0:bb348c97df44 15 */
lypinator 0:bb348c97df44 16
lypinator 0:bb348c97df44 17 /**
lypinator 0:bb348c97df44 18 * This file configures the system clock as follows:
lypinator 0:bb348c97df44 19 *-----------------------------------------------------------------------------
lypinator 0:bb348c97df44 20 * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock)
lypinator 0:bb348c97df44 21 * | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal)
lypinator 0:bb348c97df44 22 * | 3- USE_PLL_HSI (internal 16 MHz)
lypinator 0:bb348c97df44 23 *-----------------------------------------------------------------------------
lypinator 0:bb348c97df44 24 * SYSCLK(MHz) | 180
lypinator 0:bb348c97df44 25 * AHBCLK (MHz) | 180
lypinator 0:bb348c97df44 26 * APB1CLK (MHz) | 45
lypinator 0:bb348c97df44 27 * APB2CLK (MHz) | 90
lypinator 0:bb348c97df44 28 * USB capable | YES
lypinator 0:bb348c97df44 29 *-----------------------------------------------------------------------------
lypinator 0:bb348c97df44 30 **/
lypinator 0:bb348c97df44 31
lypinator 0:bb348c97df44 32 #include "stm32f4xx.h"
lypinator 0:bb348c97df44 33 #include "mbed_error.h"
lypinator 0:bb348c97df44 34
lypinator 0:bb348c97df44 35
lypinator 0:bb348c97df44 36 /*!< Uncomment the following line if you need to relocate your vector Table in
lypinator 0:bb348c97df44 37 Internal SRAM. */
lypinator 0:bb348c97df44 38 /* #define VECT_TAB_SRAM */
lypinator 0:bb348c97df44 39 #define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
lypinator 0:bb348c97df44 40 This value must be a multiple of 0x200. */
lypinator 0:bb348c97df44 41
lypinator 0:bb348c97df44 42
lypinator 0:bb348c97df44 43 // clock source is selected with CLOCK_SOURCE in json config
lypinator 0:bb348c97df44 44 #define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO)
lypinator 0:bb348c97df44 45 #define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default)
lypinator 0:bb348c97df44 46 #define USE_PLL_HSI 0x2 // Use HSI internal clock
lypinator 0:bb348c97df44 47
lypinator 0:bb348c97df44 48 //#define DEBUG_MCO (1) // Output the MCO1/MCO2 on PA8/PC9 for debugging (0=OFF, 1=ON)
lypinator 0:bb348c97df44 49
lypinator 0:bb348c97df44 50
lypinator 0:bb348c97df44 51 #if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
lypinator 0:bb348c97df44 52 uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
lypinator 0:bb348c97df44 53 #endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
lypinator 0:bb348c97df44 54
lypinator 0:bb348c97df44 55 #if ((CLOCK_SOURCE) & USE_PLL_HSI)
lypinator 0:bb348c97df44 56 uint8_t SetSysClock_PLL_HSI(void);
lypinator 0:bb348c97df44 57 #endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
lypinator 0:bb348c97df44 58
lypinator 0:bb348c97df44 59
lypinator 0:bb348c97df44 60 /**
lypinator 0:bb348c97df44 61 * @brief Setup the microcontroller system
lypinator 0:bb348c97df44 62 * Initialize the FPU setting, vector table location and External memory
lypinator 0:bb348c97df44 63 * configuration.
lypinator 0:bb348c97df44 64 * @param None
lypinator 0:bb348c97df44 65 * @retval None
lypinator 0:bb348c97df44 66 */
lypinator 0:bb348c97df44 67 void SystemInit(void)
lypinator 0:bb348c97df44 68 {
lypinator 0:bb348c97df44 69 /* FPU settings ------------------------------------------------------------*/
lypinator 0:bb348c97df44 70 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
lypinator 0:bb348c97df44 71 SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */
lypinator 0:bb348c97df44 72 #endif
lypinator 0:bb348c97df44 73 /* Reset the RCC clock configuration to the default reset state ------------*/
lypinator 0:bb348c97df44 74 /* Set HSION bit */
lypinator 0:bb348c97df44 75 RCC->CR |= (uint32_t)0x00000001;
lypinator 0:bb348c97df44 76
lypinator 0:bb348c97df44 77 /* Reset CFGR register */
lypinator 0:bb348c97df44 78 RCC->CFGR = 0x00000000;
lypinator 0:bb348c97df44 79
lypinator 0:bb348c97df44 80 /* Reset HSEON, CSSON and PLLON bits */
lypinator 0:bb348c97df44 81 RCC->CR &= (uint32_t)0xFEF6FFFF;
lypinator 0:bb348c97df44 82
lypinator 0:bb348c97df44 83 /* Reset PLLCFGR register */
lypinator 0:bb348c97df44 84 RCC->PLLCFGR = 0x24003010;
lypinator 0:bb348c97df44 85
lypinator 0:bb348c97df44 86 /* Reset HSEBYP bit */
lypinator 0:bb348c97df44 87 RCC->CR &= (uint32_t)0xFFFBFFFF;
lypinator 0:bb348c97df44 88
lypinator 0:bb348c97df44 89 /* Disable all interrupts */
lypinator 0:bb348c97df44 90 RCC->CIR = 0x00000000;
lypinator 0:bb348c97df44 91
lypinator 0:bb348c97df44 92 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
lypinator 0:bb348c97df44 93 SystemInit_ExtMemCtl();
lypinator 0:bb348c97df44 94 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
lypinator 0:bb348c97df44 95
lypinator 0:bb348c97df44 96 /* Configure the Vector Table location add offset address ------------------*/
lypinator 0:bb348c97df44 97 #ifdef VECT_TAB_SRAM
lypinator 0:bb348c97df44 98 SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
lypinator 0:bb348c97df44 99 #else
lypinator 0:bb348c97df44 100 SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
lypinator 0:bb348c97df44 101 #endif
lypinator 0:bb348c97df44 102
lypinator 0:bb348c97df44 103 }
lypinator 0:bb348c97df44 104
lypinator 0:bb348c97df44 105
lypinator 0:bb348c97df44 106 /**
lypinator 0:bb348c97df44 107 * @brief Configures the System clock source, PLL Multiplier and Divider factors,
lypinator 0:bb348c97df44 108 * AHB/APBx prescalers and Flash settings
lypinator 0:bb348c97df44 109 * @note This function should be called only once the RCC clock configuration
lypinator 0:bb348c97df44 110 * is reset to the default reset state (done in SystemInit() function).
lypinator 0:bb348c97df44 111 * @param None
lypinator 0:bb348c97df44 112 * @retval None
lypinator 0:bb348c97df44 113 */
lypinator 0:bb348c97df44 114
lypinator 0:bb348c97df44 115 void SetSysClock(void)
lypinator 0:bb348c97df44 116 {
lypinator 0:bb348c97df44 117 #if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
lypinator 0:bb348c97df44 118 /* 1- Try to start with HSE and external clock */
lypinator 0:bb348c97df44 119 if (SetSysClock_PLL_HSE(1) == 0)
lypinator 0:bb348c97df44 120 #endif
lypinator 0:bb348c97df44 121 {
lypinator 0:bb348c97df44 122 #if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
lypinator 0:bb348c97df44 123 /* 2- If fail try to start with HSE and external xtal */
lypinator 0:bb348c97df44 124 if (SetSysClock_PLL_HSE(0) == 0)
lypinator 0:bb348c97df44 125 #endif
lypinator 0:bb348c97df44 126 {
lypinator 0:bb348c97df44 127 #if ((CLOCK_SOURCE) & USE_PLL_HSI)
lypinator 0:bb348c97df44 128 /* 3- If fail start with HSI clock */
lypinator 0:bb348c97df44 129 if (SetSysClock_PLL_HSI() == 0)
lypinator 0:bb348c97df44 130 #endif
lypinator 0:bb348c97df44 131 {
lypinator 0:bb348c97df44 132 {
lypinator 0:bb348c97df44 133 error("SetSysClock failed\n");
lypinator 0:bb348c97df44 134 }
lypinator 0:bb348c97df44 135 }
lypinator 0:bb348c97df44 136 }
lypinator 0:bb348c97df44 137 }
lypinator 0:bb348c97df44 138
lypinator 0:bb348c97df44 139 // Output clock on MCO2 pin(PC9) for debugging purpose
lypinator 0:bb348c97df44 140 #if DEBUG_MCO == 1
lypinator 0:bb348c97df44 141 HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_4);
lypinator 0:bb348c97df44 142 #endif
lypinator 0:bb348c97df44 143 }
lypinator 0:bb348c97df44 144
lypinator 0:bb348c97df44 145 #if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
lypinator 0:bb348c97df44 146 /******************************************************************************/
lypinator 0:bb348c97df44 147 /* PLL (clocked by HSE) used as System clock source */
lypinator 0:bb348c97df44 148 /******************************************************************************/
lypinator 0:bb348c97df44 149 uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
lypinator 0:bb348c97df44 150 {
lypinator 0:bb348c97df44 151 RCC_OscInitTypeDef RCC_OscInitStruct;
lypinator 0:bb348c97df44 152 RCC_ClkInitTypeDef RCC_ClkInitStruct;
lypinator 0:bb348c97df44 153 RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
lypinator 0:bb348c97df44 154
lypinator 0:bb348c97df44 155 /* Enable Power Control clock */
lypinator 0:bb348c97df44 156 __HAL_RCC_PWR_CLK_ENABLE();
lypinator 0:bb348c97df44 157
lypinator 0:bb348c97df44 158 /* The voltage scaling allows optimizing the power consumption when the device is
lypinator 0:bb348c97df44 159 clocked below the maximum system frequency, to update the voltage scaling value
lypinator 0:bb348c97df44 160 regarding system frequency refer to product datasheet. */
lypinator 0:bb348c97df44 161 __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
lypinator 0:bb348c97df44 162
lypinator 0:bb348c97df44 163 /* Enable HSE oscillator and activate PLL with HSE as source */
lypinator 0:bb348c97df44 164 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
lypinator 0:bb348c97df44 165 if (bypass == 0) {
lypinator 0:bb348c97df44 166 RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
lypinator 0:bb348c97df44 167 } else {
lypinator 0:bb348c97df44 168 RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
lypinator 0:bb348c97df44 169 }
lypinator 0:bb348c97df44 170 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
lypinator 0:bb348c97df44 171 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
lypinator 0:bb348c97df44 172 RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 1 MHz (8 MHz / 8)
lypinator 0:bb348c97df44 173 RCC_OscInitStruct.PLL.PLLN = 360; // VCO output clock = 360 MHz (1 MHz * 360)
lypinator 0:bb348c97df44 174 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // PLLCLK = 180 MHz (360 MHz / 2)
lypinator 0:bb348c97df44 175 RCC_OscInitStruct.PLL.PLLQ = 7; //
lypinator 0:bb348c97df44 176 RCC_OscInitStruct.PLL.PLLR = 2; //
lypinator 0:bb348c97df44 177 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
lypinator 0:bb348c97df44 178 return 0; // FAIL
lypinator 0:bb348c97df44 179 }
lypinator 0:bb348c97df44 180
lypinator 0:bb348c97df44 181 // Activate the OverDrive to reach the 180 MHz Frequency
lypinator 0:bb348c97df44 182 if (HAL_PWREx_EnableOverDrive() != HAL_OK) {
lypinator 0:bb348c97df44 183 return 0; // FAIL
lypinator 0:bb348c97df44 184 }
lypinator 0:bb348c97df44 185
lypinator 0:bb348c97df44 186 // Select PLLSAI output as USB clock source
lypinator 0:bb348c97df44 187 PeriphClkInitStruct.PLLSAI.PLLSAIM = 8;
lypinator 0:bb348c97df44 188 PeriphClkInitStruct.PLLSAI.PLLSAIN = 384;
lypinator 0:bb348c97df44 189 PeriphClkInitStruct.PLLSAI.PLLSAIP = RCC_PLLSAIP_DIV8;
lypinator 0:bb348c97df44 190 PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48;
lypinator 0:bb348c97df44 191 PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLSAIP;
lypinator 0:bb348c97df44 192 HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
lypinator 0:bb348c97df44 193
lypinator 0:bb348c97df44 194 /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
lypinator 0:bb348c97df44 195 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
lypinator 0:bb348c97df44 196 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
lypinator 0:bb348c97df44 197 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 180 MHz
lypinator 0:bb348c97df44 198 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; // 45 MHz
lypinator 0:bb348c97df44 199 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; // 90 MHz
lypinator 0:bb348c97df44 200 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) {
lypinator 0:bb348c97df44 201 return 0; // FAIL
lypinator 0:bb348c97df44 202 }
lypinator 0:bb348c97df44 203
lypinator 0:bb348c97df44 204 // Output clock on MCO1 pin(PA8) for debugging purpose
lypinator 0:bb348c97df44 205 #if DEBUG_MCO == 1
lypinator 0:bb348c97df44 206 if (bypass == 0) {
lypinator 0:bb348c97df44 207 HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz with xtal
lypinator 0:bb348c97df44 208 } else {
lypinator 0:bb348c97df44 209 HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz with external clock (MCO)
lypinator 0:bb348c97df44 210 }
lypinator 0:bb348c97df44 211 #endif
lypinator 0:bb348c97df44 212
lypinator 0:bb348c97df44 213 return 1; // OK
lypinator 0:bb348c97df44 214 }
lypinator 0:bb348c97df44 215 #endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
lypinator 0:bb348c97df44 216
lypinator 0:bb348c97df44 217 #if ((CLOCK_SOURCE) & USE_PLL_HSI)
lypinator 0:bb348c97df44 218 /******************************************************************************/
lypinator 0:bb348c97df44 219 /* PLL (clocked by HSI) used as System clock source */
lypinator 0:bb348c97df44 220 /******************************************************************************/
lypinator 0:bb348c97df44 221 uint8_t SetSysClock_PLL_HSI(void)
lypinator 0:bb348c97df44 222 {
lypinator 0:bb348c97df44 223 RCC_OscInitTypeDef RCC_OscInitStruct;
lypinator 0:bb348c97df44 224 RCC_ClkInitTypeDef RCC_ClkInitStruct;
lypinator 0:bb348c97df44 225 RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
lypinator 0:bb348c97df44 226
lypinator 0:bb348c97df44 227 /* Enable Power Control clock */
lypinator 0:bb348c97df44 228 __HAL_RCC_PWR_CLK_ENABLE();
lypinator 0:bb348c97df44 229
lypinator 0:bb348c97df44 230 /* The voltage scaling allows optimizing the power consumption when the device is
lypinator 0:bb348c97df44 231 clocked below the maximum system frequency, to update the voltage scaling value
lypinator 0:bb348c97df44 232 regarding system frequency refer to product datasheet. */
lypinator 0:bb348c97df44 233 __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
lypinator 0:bb348c97df44 234
lypinator 0:bb348c97df44 235 /* Enable HSI oscillator and activate PLL with HSI as source */
lypinator 0:bb348c97df44 236 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
lypinator 0:bb348c97df44 237 RCC_OscInitStruct.HSIState = RCC_HSI_ON;
lypinator 0:bb348c97df44 238 RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
lypinator 0:bb348c97df44 239 RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
lypinator 0:bb348c97df44 240 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
lypinator 0:bb348c97df44 241 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
lypinator 0:bb348c97df44 242 RCC_OscInitStruct.PLL.PLLM = 16; // VCO input clock = 1 MHz (16 MHz / 16)
lypinator 0:bb348c97df44 243 RCC_OscInitStruct.PLL.PLLN = 360; // VCO output clock = 360 MHz (1 MHz * 360)
lypinator 0:bb348c97df44 244 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // PLLCLK = 180 MHz (360 MHz / 2)
lypinator 0:bb348c97df44 245 RCC_OscInitStruct.PLL.PLLQ = 7; //
lypinator 0:bb348c97df44 246 RCC_OscInitStruct.PLL.PLLR = 6; //
lypinator 0:bb348c97df44 247 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
lypinator 0:bb348c97df44 248 return 0; // FAIL
lypinator 0:bb348c97df44 249 }
lypinator 0:bb348c97df44 250
lypinator 0:bb348c97df44 251 /* Select PLLSAI output as USB clock source */
lypinator 0:bb348c97df44 252 PeriphClkInitStruct.PLLSAI.PLLSAIM = 8;
lypinator 0:bb348c97df44 253 PeriphClkInitStruct.PLLSAI.PLLSAIN = 192;
lypinator 0:bb348c97df44 254 PeriphClkInitStruct.PLLSAI.PLLSAIP = RCC_PLLSAIP_DIV8;
lypinator 0:bb348c97df44 255 PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48;
lypinator 0:bb348c97df44 256 PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLSAIP;
lypinator 0:bb348c97df44 257 HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
lypinator 0:bb348c97df44 258
lypinator 0:bb348c97df44 259 /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
lypinator 0:bb348c97df44 260 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
lypinator 0:bb348c97df44 261 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 180 MHz
lypinator 0:bb348c97df44 262 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 180 MHz
lypinator 0:bb348c97df44 263 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; // 45 MHz
lypinator 0:bb348c97df44 264 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; // 90 MHz
lypinator 0:bb348c97df44 265 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) {
lypinator 0:bb348c97df44 266 return 0; // FAIL
lypinator 0:bb348c97df44 267 }
lypinator 0:bb348c97df44 268
lypinator 0:bb348c97df44 269 // Output clock on MCO1 pin(PA8) for debugging purpose
lypinator 0:bb348c97df44 270 #if DEBUG_MCO == 1
lypinator 0:bb348c97df44 271 HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
lypinator 0:bb348c97df44 272 #endif
lypinator 0:bb348c97df44 273
lypinator 0:bb348c97df44 274 return 1; // OK
lypinator 0:bb348c97df44 275 }
lypinator 0:bb348c97df44 276 #endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */