Thomas Lyp / DevLibMemoryController

Initial commit

Dependencies:   FastPWM

mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/TARGET_UBLOX_C030/system_clock.c@0:bb348c97df44, 2020-09-16 (annotated)

Committer:
lypinator
Date:
Wed Sep 16 01:11:49 2020 +0000
Revision:
0:bb348c97df44
Added PWM

Who changed what in which revision?

UserRevisionLine numberNew contents of line
lypinator 0:bb348c97df44 1 /* mbed Microcontroller Library
lypinator 0:bb348c97df44 2 * Copyright (c) 2006-2017 ARM Limited
lypinator 0:bb348c97df44 3 *
lypinator 0:bb348c97df44 4 * Licensed under the Apache License, Version 2.0 (the "License");
lypinator 0:bb348c97df44 5 * you may not use this file except in compliance with the License.
lypinator 0:bb348c97df44 6 * You may obtain a copy of the License at
lypinator 0:bb348c97df44 7 *
lypinator 0:bb348c97df44 8 * http://www.apache.org/licenses/LICENSE-2.0
lypinator 0:bb348c97df44 9 *
lypinator 0:bb348c97df44 10 * Unless required by applicable law or agreed to in writing, software
lypinator 0:bb348c97df44 11 * distributed under the License is distributed on an "AS IS" BASIS,
lypinator 0:bb348c97df44 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
lypinator 0:bb348c97df44 13 * See the License for the specific language governing permissions and
lypinator 0:bb348c97df44 14 * limitations under the License.
lypinator 0:bb348c97df44 15 */
lypinator 0:bb348c97df44 16
lypinator 0:bb348c97df44 17 /**
lypinator 0:bb348c97df44 18 * This file configures the system clock as follows:
lypinator 0:bb348c97df44 19 *----------------------------------------------------------------------------------------------------------------------------------------
lypinator 0:bb348c97df44 20 * System clock source | PLL_HSE_XTAL | PLL_HSE_XTAL | PLL_HSE_XTAL | PLL_HSE_XTAL
lypinator 0:bb348c97df44 21 * | (external 8 MHz clock) | (external 8 MHz clock) | (external 12 MHz clock)| (external 12 MHz clock)
lypinator 0:bb348c97df44 22 *----------------------------------------------------------------------------------------------------------------------------------------
lypinator 0:bb348c97df44 23 * SYSCLK(MHz) | 168 | 84 | 168 | 84
lypinator 0:bb348c97df44 24 *----------------------------------------------------------------------------------------------------------------------------------------
lypinator 0:bb348c97df44 25 * AHBCLK (MHz) | 168 | 84 | 168 | 84
lypinator 0:bb348c97df44 26 *----------------------------------------------------------------------------------------------------------------------------------------
lypinator 0:bb348c97df44 27 * APB1CLK (MHz) | 42 | 42 | 42 | 42
lypinator 0:bb348c97df44 28 *----------------------------------------------------------------------------------------------------------------------------------------
lypinator 0:bb348c97df44 29 * APB2CLK (MHz) | 84 | 84 | 84 | 84
lypinator 0:bb348c97df44 30 *----------------------------------------------------------------------------------------------------------------------------------------
lypinator 0:bb348c97df44 31 * USB capable (48 MHz precise clock) | YES | YES | YES | YES
lypinator 0:bb348c97df44 32 *----------------------------------------------------------------------------------------------------------------------------------------
lypinator 0:bb348c97df44 33 **/
lypinator 0:bb348c97df44 34
lypinator 0:bb348c97df44 35 #include "ublox_low_level_api.h"
lypinator 0:bb348c97df44 36 #include "stm32f4xx.h"
lypinator 0:bb348c97df44 37 #include "nvic_addr.h"
lypinator 0:bb348c97df44 38
lypinator 0:bb348c97df44 39 /*!< Uncomment the following line if you need to relocate your vector Table in
lypinator 0:bb348c97df44 40 Internal SRAM. */
lypinator 0:bb348c97df44 41 /* #define VECT_TAB_SRAM */
lypinator 0:bb348c97df44 42 #define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
lypinator 0:bb348c97df44 43 This value must be a multiple of 0x200. */
lypinator 0:bb348c97df44 44
lypinator 0:bb348c97df44 45
lypinator 0:bb348c97df44 46 /* Select the SYSCLOCK to start with (0=OFF, 1=ON) */
lypinator 0:bb348c97df44 47 #define USE_SYSCLOCK_168 (1) /* Use external 8MHz or 12 MHz xtal and sets SYSCLK to 168MHz */
lypinator 0:bb348c97df44 48 #define USE_SYSCLOCK_84 (0) /* Use external 8MHz or 12 MHz xtal and sets SYSCLK to 84MHz */
lypinator 0:bb348c97df44 49
lypinator 0:bb348c97df44 50
lypinator 0:bb348c97df44 51 void SetSysClock(void);
lypinator 0:bb348c97df44 52
lypinator 0:bb348c97df44 53 /**
lypinator 0:bb348c97df44 54 * @brief Setup the microcontroller system
lypinator 0:bb348c97df44 55 * Initialize the FPU setting, vector table location and External memory
lypinator 0:bb348c97df44 56 * configuration.
lypinator 0:bb348c97df44 57 * @param None
lypinator 0:bb348c97df44 58 * @retval None
lypinator 0:bb348c97df44 59 */
lypinator 0:bb348c97df44 60 void SystemInit(void)
lypinator 0:bb348c97df44 61 {
lypinator 0:bb348c97df44 62 /* FPU settings ------------------------------------------------------------*/
lypinator 0:bb348c97df44 63 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
lypinator 0:bb348c97df44 64 SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */
lypinator 0:bb348c97df44 65 #endif
lypinator 0:bb348c97df44 66 /* Reset the RCC clock configuration to the default reset state ------------*/
lypinator 0:bb348c97df44 67 /* Set HSION bit */
lypinator 0:bb348c97df44 68 RCC->CR |= (uint32_t)0x00000001;
lypinator 0:bb348c97df44 69
lypinator 0:bb348c97df44 70 /* Reset CFGR register */
lypinator 0:bb348c97df44 71 RCC->CFGR = 0x00000000;
lypinator 0:bb348c97df44 72
lypinator 0:bb348c97df44 73 /* Reset HSEON, CSSON and PLLON bits */
lypinator 0:bb348c97df44 74 RCC->CR &= (uint32_t)0xFEF6FFFF;
lypinator 0:bb348c97df44 75
lypinator 0:bb348c97df44 76 /* Reset PLLCFGR register */
lypinator 0:bb348c97df44 77 RCC->PLLCFGR = 0x24003010;
lypinator 0:bb348c97df44 78
lypinator 0:bb348c97df44 79 /* Reset HSEBYP bit */
lypinator 0:bb348c97df44 80 RCC->CR &= (uint32_t)0xFFFBFFFF;
lypinator 0:bb348c97df44 81
lypinator 0:bb348c97df44 82 /* Disable all interrupts */
lypinator 0:bb348c97df44 83 RCC->CIR = 0x00000000;
lypinator 0:bb348c97df44 84
lypinator 0:bb348c97df44 85 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
lypinator 0:bb348c97df44 86 SystemInit_ExtMemCtl();
lypinator 0:bb348c97df44 87 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
lypinator 0:bb348c97df44 88
lypinator 0:bb348c97df44 89 /* Configure the Vector Table location add offset address ------------------*/
lypinator 0:bb348c97df44 90 #ifdef VECT_TAB_SRAM
lypinator 0:bb348c97df44 91 SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
lypinator 0:bb348c97df44 92 #else
lypinator 0:bb348c97df44 93 SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
lypinator 0:bb348c97df44 94 #endif
lypinator 0:bb348c97df44 95
lypinator 0:bb348c97df44 96 ublox_board_init();
lypinator 0:bb348c97df44 97 }
lypinator 0:bb348c97df44 98
lypinator 0:bb348c97df44 99
lypinator 0:bb348c97df44 100
lypinator 0:bb348c97df44 101 /** System Clock Configuration
lypinator 0:bb348c97df44 102 */
lypinator 0:bb348c97df44 103 #if USE_SYSCLOCK_168 != 0
lypinator 0:bb348c97df44 104 /*
lypinator 0:bb348c97df44 105 * Set SYSCLK=168MHZ
lypinator 0:bb348c97df44 106 */
lypinator 0:bb348c97df44 107 void SetSysClock(void)
lypinator 0:bb348c97df44 108 {
lypinator 0:bb348c97df44 109
lypinator 0:bb348c97df44 110 RCC_OscInitTypeDef RCC_OscInitStruct;
lypinator 0:bb348c97df44 111 RCC_ClkInitTypeDef RCC_ClkInitStruct;
lypinator 0:bb348c97df44 112
lypinator 0:bb348c97df44 113 __HAL_RCC_PWR_CLK_ENABLE();
lypinator 0:bb348c97df44 114
lypinator 0:bb348c97df44 115 __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
lypinator 0:bb348c97df44 116
lypinator 0:bb348c97df44 117 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
lypinator 0:bb348c97df44 118 RCC_OscInitStruct.HSEState = RCC_HSE_ON;
lypinator 0:bb348c97df44 119 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
lypinator 0:bb348c97df44 120 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
lypinator 0:bb348c97df44 121 #ifdef USE_DEBUG_8MHz_XTAL
lypinator 0:bb348c97df44 122 RCC_OscInitStruct.PLL.PLLM = 8;
lypinator 0:bb348c97df44 123 #else
lypinator 0:bb348c97df44 124 RCC_OscInitStruct.PLL.PLLM = 12;
lypinator 0:bb348c97df44 125 #endif
lypinator 0:bb348c97df44 126 RCC_OscInitStruct.PLL.PLLN = 336;
lypinator 0:bb348c97df44 127 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
lypinator 0:bb348c97df44 128 RCC_OscInitStruct.PLL.PLLQ = 7;
lypinator 0:bb348c97df44 129 HAL_RCC_OscConfig(&RCC_OscInitStruct);
lypinator 0:bb348c97df44 130
lypinator 0:bb348c97df44 131 RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1
lypinator 0:bb348c97df44 132 | RCC_CLOCKTYPE_PCLK2;
lypinator 0:bb348c97df44 133 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
lypinator 0:bb348c97df44 134 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
lypinator 0:bb348c97df44 135 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
lypinator 0:bb348c97df44 136 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
lypinator 0:bb348c97df44 137 HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5);
lypinator 0:bb348c97df44 138
lypinator 0:bb348c97df44 139 // HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_3);
lypinator 0:bb348c97df44 140
lypinator 0:bb348c97df44 141
lypinator 0:bb348c97df44 142 }
lypinator 0:bb348c97df44 143
lypinator 0:bb348c97df44 144 #elif USE_SYSCLOCK_84 != 0
lypinator 0:bb348c97df44 145 /*
lypinator 0:bb348c97df44 146 Set SYSCLK=84MHZ
lypinator 0:bb348c97df44 147 */
lypinator 0:bb348c97df44 148 void SetSysClock(void)
lypinator 0:bb348c97df44 149 {
lypinator 0:bb348c97df44 150
lypinator 0:bb348c97df44 151 RCC_OscInitTypeDef RCC_OscInitStruct;
lypinator 0:bb348c97df44 152 RCC_ClkInitTypeDef RCC_ClkInitStruct;
lypinator 0:bb348c97df44 153
lypinator 0:bb348c97df44 154 __HAL_RCC_PWR_CLK_ENABLE();
lypinator 0:bb348c97df44 155
lypinator 0:bb348c97df44 156 __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE3);
lypinator 0:bb348c97df44 157
lypinator 0:bb348c97df44 158 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
lypinator 0:bb348c97df44 159 RCC_OscInitStruct.HSEState = RCC_HSE_ON;
lypinator 0:bb348c97df44 160 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
lypinator 0:bb348c97df44 161 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
lypinator 0:bb348c97df44 162 #ifdef USE_DEBUG_8MHz_XTAL
lypinator 0:bb348c97df44 163 RCC_OscInitStruct.PLL.PLLM = 8;
lypinator 0:bb348c97df44 164 #else
lypinator 0:bb348c97df44 165 RCC_OscInitStruct.PLL.PLLM = 12;
lypinator 0:bb348c97df44 166 #endif
lypinator 0:bb348c97df44 167 RCC_OscInitStruct.PLL.PLLN = 336;
lypinator 0:bb348c97df44 168 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4;
lypinator 0:bb348c97df44 169 RCC_OscInitStruct.PLL.PLLQ = 7;
lypinator 0:bb348c97df44 170 HAL_RCC_OscConfig(&RCC_OscInitStruct);
lypinator 0:bb348c97df44 171
lypinator 0:bb348c97df44 172
lypinator 0:bb348c97df44 173 RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1
lypinator 0:bb348c97df44 174 | RCC_CLOCKTYPE_PCLK2;
lypinator 0:bb348c97df44 175 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
lypinator 0:bb348c97df44 176 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
lypinator 0:bb348c97df44 177 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
lypinator 0:bb348c97df44 178 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
lypinator 0:bb348c97df44 179 HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2);
lypinator 0:bb348c97df44 180
lypinator 0:bb348c97df44 181 // HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_3);
lypinator 0:bb348c97df44 182
lypinator 0:bb348c97df44 183 }
lypinator 0:bb348c97df44 184 #endif