Thomas Lyp / DevLibMemoryController

Initial commit

Dependencies:   FastPWM

mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/device/stm32f412zx.h@0:bb348c97df44, 2020-09-16 (annotated)

Committer:
lypinator
Date:
Wed Sep 16 01:11:49 2020 +0000
Revision:
0:bb348c97df44
Added PWM

Who changed what in which revision?

UserRevisionLine numberNew contents of line
lypinator 0:bb348c97df44 1 /**
lypinator 0:bb348c97df44 2 ******************************************************************************
lypinator 0:bb348c97df44 3 * @file stm32f412zx.h
lypinator 0:bb348c97df44 4 * @author MCD Application Team
lypinator 0:bb348c97df44 5 * @brief CMSIS STM32F412Zx Device Peripheral Access Layer Header File.
lypinator 0:bb348c97df44 6 *
lypinator 0:bb348c97df44 7 * This file contains:
lypinator 0:bb348c97df44 8 * - Data structures and the address mapping for all peripherals
lypinator 0:bb348c97df44 9 * - peripherals registers declarations and bits definition
lypinator 0:bb348c97df44 10 * - Macros to access peripheral's registers hardware
lypinator 0:bb348c97df44 11 *
lypinator 0:bb348c97df44 12 ******************************************************************************
lypinator 0:bb348c97df44 13 * @attention
lypinator 0:bb348c97df44 14 *
lypinator 0:bb348c97df44 15 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
lypinator 0:bb348c97df44 16 *
lypinator 0:bb348c97df44 17 * Redistribution and use in source and binary forms, with or without modification,
lypinator 0:bb348c97df44 18 * are permitted provided that the following conditions are met:
lypinator 0:bb348c97df44 19 * 1. Redistributions of source code must retain the above copyright notice,
lypinator 0:bb348c97df44 20 * this list of conditions and the following disclaimer.
lypinator 0:bb348c97df44 21 * 2. Redistributions in binary form must reproduce the above copyright notice,
lypinator 0:bb348c97df44 22 * this list of conditions and the following disclaimer in the documentation
lypinator 0:bb348c97df44 23 * and/or other materials provided with the distribution.
lypinator 0:bb348c97df44 24 * 3. Neither the name of STMicroelectronics nor the names of its contributors
lypinator 0:bb348c97df44 25 * may be used to endorse or promote products derived from this software
lypinator 0:bb348c97df44 26 * without specific prior written permission.
lypinator 0:bb348c97df44 27 *
lypinator 0:bb348c97df44 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
lypinator 0:bb348c97df44 29 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
lypinator 0:bb348c97df44 30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
lypinator 0:bb348c97df44 31 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
lypinator 0:bb348c97df44 32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
lypinator 0:bb348c97df44 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
lypinator 0:bb348c97df44 34 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
lypinator 0:bb348c97df44 35 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
lypinator 0:bb348c97df44 36 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
lypinator 0:bb348c97df44 37 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
lypinator 0:bb348c97df44 38 *
lypinator 0:bb348c97df44 39 ******************************************************************************
lypinator 0:bb348c97df44 40 */
lypinator 0:bb348c97df44 41
lypinator 0:bb348c97df44 42 /** @addtogroup CMSIS_Device
lypinator 0:bb348c97df44 43 * @{
lypinator 0:bb348c97df44 44 */
lypinator 0:bb348c97df44 45
lypinator 0:bb348c97df44 46 /** @addtogroup stm32f412zx
lypinator 0:bb348c97df44 47 * @{
lypinator 0:bb348c97df44 48 */
lypinator 0:bb348c97df44 49
lypinator 0:bb348c97df44 50 #ifndef __STM32F412Zx_H
lypinator 0:bb348c97df44 51 #define __STM32F412Zx_H
lypinator 0:bb348c97df44 52
lypinator 0:bb348c97df44 53 #ifdef __cplusplus
lypinator 0:bb348c97df44 54 extern "C" {
lypinator 0:bb348c97df44 55 #endif /* __cplusplus */
lypinator 0:bb348c97df44 56
lypinator 0:bb348c97df44 57 /** @addtogroup Configuration_section_for_CMSIS
lypinator 0:bb348c97df44 58 * @{
lypinator 0:bb348c97df44 59 */
lypinator 0:bb348c97df44 60
lypinator 0:bb348c97df44 61 /**
lypinator 0:bb348c97df44 62 * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
lypinator 0:bb348c97df44 63 */
lypinator 0:bb348c97df44 64 #define __CM4_REV 0x0001U /*!< Core revision r0p1 */
lypinator 0:bb348c97df44 65 #define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */
lypinator 0:bb348c97df44 66 #define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */
lypinator 0:bb348c97df44 67 #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
lypinator 0:bb348c97df44 68 /* MBED */
lypinator 0:bb348c97df44 69 #ifndef __FPU_PRESENT
lypinator 0:bb348c97df44 70 #define __FPU_PRESENT 1U /*!< FPU present */
lypinator 0:bb348c97df44 71 #endif /* __FPU_PRESENT */
lypinator 0:bb348c97df44 72 /* MBED */
lypinator 0:bb348c97df44 73
lypinator 0:bb348c97df44 74 /**
lypinator 0:bb348c97df44 75 * @}
lypinator 0:bb348c97df44 76 */
lypinator 0:bb348c97df44 77
lypinator 0:bb348c97df44 78 /** @addtogroup Peripheral_interrupt_number_definition
lypinator 0:bb348c97df44 79 * @{
lypinator 0:bb348c97df44 80 */
lypinator 0:bb348c97df44 81
lypinator 0:bb348c97df44 82 /**
lypinator 0:bb348c97df44 83 * @brief STM32F4XX Interrupt Number Definition, according to the selected device
lypinator 0:bb348c97df44 84 * in @ref Library_configuration_section
lypinator 0:bb348c97df44 85 */
lypinator 0:bb348c97df44 86 typedef enum
lypinator 0:bb348c97df44 87 {
lypinator 0:bb348c97df44 88 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
lypinator 0:bb348c97df44 89 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
lypinator 0:bb348c97df44 90 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
lypinator 0:bb348c97df44 91 BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
lypinator 0:bb348c97df44 92 UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
lypinator 0:bb348c97df44 93 SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
lypinator 0:bb348c97df44 94 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
lypinator 0:bb348c97df44 95 PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
lypinator 0:bb348c97df44 96 SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
lypinator 0:bb348c97df44 97 /****** STM32 specific Interrupt Numbers **********************************************************************/
lypinator 0:bb348c97df44 98 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
lypinator 0:bb348c97df44 99 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
lypinator 0:bb348c97df44 100 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
lypinator 0:bb348c97df44 101 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
lypinator 0:bb348c97df44 102 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
lypinator 0:bb348c97df44 103 RCC_IRQn = 5, /*!< RCC global Interrupt */
lypinator 0:bb348c97df44 104 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
lypinator 0:bb348c97df44 105 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
lypinator 0:bb348c97df44 106 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
lypinator 0:bb348c97df44 107 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
lypinator 0:bb348c97df44 108 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
lypinator 0:bb348c97df44 109 DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
lypinator 0:bb348c97df44 110 DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
lypinator 0:bb348c97df44 111 DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
lypinator 0:bb348c97df44 112 DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
lypinator 0:bb348c97df44 113 DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
lypinator 0:bb348c97df44 114 DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
lypinator 0:bb348c97df44 115 DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
lypinator 0:bb348c97df44 116 ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
lypinator 0:bb348c97df44 117 CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
lypinator 0:bb348c97df44 118 CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
lypinator 0:bb348c97df44 119 CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
lypinator 0:bb348c97df44 120 CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
lypinator 0:bb348c97df44 121 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
lypinator 0:bb348c97df44 122 TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
lypinator 0:bb348c97df44 123 TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
lypinator 0:bb348c97df44 124 TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
lypinator 0:bb348c97df44 125 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
lypinator 0:bb348c97df44 126 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
lypinator 0:bb348c97df44 127 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
lypinator 0:bb348c97df44 128 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
lypinator 0:bb348c97df44 129 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
lypinator 0:bb348c97df44 130 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
lypinator 0:bb348c97df44 131 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
lypinator 0:bb348c97df44 132 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
lypinator 0:bb348c97df44 133 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
lypinator 0:bb348c97df44 134 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
lypinator 0:bb348c97df44 135 USART1_IRQn = 37, /*!< USART1 global Interrupt */
lypinator 0:bb348c97df44 136 USART2_IRQn = 38, /*!< USART2 global Interrupt */
lypinator 0:bb348c97df44 137 USART3_IRQn = 39, /*!< USART3 global Interrupt */
lypinator 0:bb348c97df44 138 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
lypinator 0:bb348c97df44 139 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
lypinator 0:bb348c97df44 140 OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
lypinator 0:bb348c97df44 141 TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
lypinator 0:bb348c97df44 142 TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
lypinator 0:bb348c97df44 143 TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
lypinator 0:bb348c97df44 144 TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare global interrupt */
lypinator 0:bb348c97df44 145 DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
lypinator 0:bb348c97df44 146 SDIO_IRQn = 49, /*!< SDIO global Interrupt */
lypinator 0:bb348c97df44 147 TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
lypinator 0:bb348c97df44 148 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
lypinator 0:bb348c97df44 149 TIM6_IRQn = 54, /*!< TIM6 global interrupt */
lypinator 0:bb348c97df44 150 TIM7_IRQn = 55, /*!< TIM7 global interrupt */
lypinator 0:bb348c97df44 151 DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
lypinator 0:bb348c97df44 152 DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
lypinator 0:bb348c97df44 153 DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
lypinator 0:bb348c97df44 154 DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
lypinator 0:bb348c97df44 155 DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
lypinator 0:bb348c97df44 156 DFSDM1_FLT0_IRQn = 61, /*!< DFSDM1 Filter 0 global Interrupt */
lypinator 0:bb348c97df44 157 DFSDM1_FLT1_IRQn = 62, /*!< DFSDM1 Filter 1 global Interrupt */
lypinator 0:bb348c97df44 158 CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
lypinator 0:bb348c97df44 159 CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
lypinator 0:bb348c97df44 160 CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
lypinator 0:bb348c97df44 161 CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
lypinator 0:bb348c97df44 162 OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
lypinator 0:bb348c97df44 163 DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
lypinator 0:bb348c97df44 164 DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
lypinator 0:bb348c97df44 165 DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
lypinator 0:bb348c97df44 166 USART6_IRQn = 71, /*!< USART6 global interrupt */
lypinator 0:bb348c97df44 167 I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
lypinator 0:bb348c97df44 168 I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
lypinator 0:bb348c97df44 169 RNG_IRQn = 80, /*!< RNG global Interrupt */
lypinator 0:bb348c97df44 170 FPU_IRQn = 81, /*!< FPU global interrupt */
lypinator 0:bb348c97df44 171 SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
lypinator 0:bb348c97df44 172 SPI5_IRQn = 85, /*!< SPI5 global Interrupt */
lypinator 0:bb348c97df44 173 QUADSPI_IRQn = 92, /*!< QuadSPI global Interrupt */
lypinator 0:bb348c97df44 174 FMPI2C1_EV_IRQn = 95, /*!< FMPI2C1 Event Interrupt */
lypinator 0:bb348c97df44 175 FMPI2C1_ER_IRQn = 96 /*!< FMPI2C1 Error Interrupt */
lypinator 0:bb348c97df44 176 } IRQn_Type;
lypinator 0:bb348c97df44 177
lypinator 0:bb348c97df44 178 /**
lypinator 0:bb348c97df44 179 * @}
lypinator 0:bb348c97df44 180 */
lypinator 0:bb348c97df44 181
lypinator 0:bb348c97df44 182 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
lypinator 0:bb348c97df44 183 #include "system_stm32f4xx.h"
lypinator 0:bb348c97df44 184 #include <stdint.h>
lypinator 0:bb348c97df44 185
lypinator 0:bb348c97df44 186 /** @addtogroup Peripheral_registers_structures
lypinator 0:bb348c97df44 187 * @{
lypinator 0:bb348c97df44 188 */
lypinator 0:bb348c97df44 189
lypinator 0:bb348c97df44 190 /**
lypinator 0:bb348c97df44 191 * @brief Analog to Digital Converter
lypinator 0:bb348c97df44 192 */
lypinator 0:bb348c97df44 193
lypinator 0:bb348c97df44 194 typedef struct
lypinator 0:bb348c97df44 195 {
lypinator 0:bb348c97df44 196 __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
lypinator 0:bb348c97df44 197 __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
lypinator 0:bb348c97df44 198 __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
lypinator 0:bb348c97df44 199 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
lypinator 0:bb348c97df44 200 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
lypinator 0:bb348c97df44 201 __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
lypinator 0:bb348c97df44 202 __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
lypinator 0:bb348c97df44 203 __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
lypinator 0:bb348c97df44 204 __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
lypinator 0:bb348c97df44 205 __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
lypinator 0:bb348c97df44 206 __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
lypinator 0:bb348c97df44 207 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
lypinator 0:bb348c97df44 208 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
lypinator 0:bb348c97df44 209 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
lypinator 0:bb348c97df44 210 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
lypinator 0:bb348c97df44 211 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
lypinator 0:bb348c97df44 212 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
lypinator 0:bb348c97df44 213 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
lypinator 0:bb348c97df44 214 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
lypinator 0:bb348c97df44 215 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
lypinator 0:bb348c97df44 216 } ADC_TypeDef;
lypinator 0:bb348c97df44 217
lypinator 0:bb348c97df44 218 typedef struct
lypinator 0:bb348c97df44 219 {
lypinator 0:bb348c97df44 220 __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
lypinator 0:bb348c97df44 221 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
lypinator 0:bb348c97df44 222 __IO uint32_t CDR; /*!< ADC common regular data register for dual
lypinator 0:bb348c97df44 223 AND triple modes, Address offset: ADC1 base address + 0x308 */
lypinator 0:bb348c97df44 224 } ADC_Common_TypeDef;
lypinator 0:bb348c97df44 225
lypinator 0:bb348c97df44 226
lypinator 0:bb348c97df44 227 /**
lypinator 0:bb348c97df44 228 * @brief Controller Area Network TxMailBox
lypinator 0:bb348c97df44 229 */
lypinator 0:bb348c97df44 230
lypinator 0:bb348c97df44 231 typedef struct
lypinator 0:bb348c97df44 232 {
lypinator 0:bb348c97df44 233 __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
lypinator 0:bb348c97df44 234 __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
lypinator 0:bb348c97df44 235 __IO uint32_t TDLR; /*!< CAN mailbox data low register */
lypinator 0:bb348c97df44 236 __IO uint32_t TDHR; /*!< CAN mailbox data high register */
lypinator 0:bb348c97df44 237 } CAN_TxMailBox_TypeDef;
lypinator 0:bb348c97df44 238
lypinator 0:bb348c97df44 239 /**
lypinator 0:bb348c97df44 240 * @brief Controller Area Network FIFOMailBox
lypinator 0:bb348c97df44 241 */
lypinator 0:bb348c97df44 242
lypinator 0:bb348c97df44 243 typedef struct
lypinator 0:bb348c97df44 244 {
lypinator 0:bb348c97df44 245 __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
lypinator 0:bb348c97df44 246 __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
lypinator 0:bb348c97df44 247 __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
lypinator 0:bb348c97df44 248 __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
lypinator 0:bb348c97df44 249 } CAN_FIFOMailBox_TypeDef;
lypinator 0:bb348c97df44 250
lypinator 0:bb348c97df44 251 /**
lypinator 0:bb348c97df44 252 * @brief Controller Area Network FilterRegister
lypinator 0:bb348c97df44 253 */
lypinator 0:bb348c97df44 254
lypinator 0:bb348c97df44 255 typedef struct
lypinator 0:bb348c97df44 256 {
lypinator 0:bb348c97df44 257 __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
lypinator 0:bb348c97df44 258 __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
lypinator 0:bb348c97df44 259 } CAN_FilterRegister_TypeDef;
lypinator 0:bb348c97df44 260
lypinator 0:bb348c97df44 261 /**
lypinator 0:bb348c97df44 262 * @brief Controller Area Network
lypinator 0:bb348c97df44 263 */
lypinator 0:bb348c97df44 264
lypinator 0:bb348c97df44 265 typedef struct
lypinator 0:bb348c97df44 266 {
lypinator 0:bb348c97df44 267 __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
lypinator 0:bb348c97df44 268 __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
lypinator 0:bb348c97df44 269 __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
lypinator 0:bb348c97df44 270 __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
lypinator 0:bb348c97df44 271 __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
lypinator 0:bb348c97df44 272 __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
lypinator 0:bb348c97df44 273 __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
lypinator 0:bb348c97df44 274 __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
lypinator 0:bb348c97df44 275 uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
lypinator 0:bb348c97df44 276 CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
lypinator 0:bb348c97df44 277 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
lypinator 0:bb348c97df44 278 uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
lypinator 0:bb348c97df44 279 __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
lypinator 0:bb348c97df44 280 __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
lypinator 0:bb348c97df44 281 uint32_t RESERVED2; /*!< Reserved, 0x208 */
lypinator 0:bb348c97df44 282 __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
lypinator 0:bb348c97df44 283 uint32_t RESERVED3; /*!< Reserved, 0x210 */
lypinator 0:bb348c97df44 284 __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
lypinator 0:bb348c97df44 285 uint32_t RESERVED4; /*!< Reserved, 0x218 */
lypinator 0:bb348c97df44 286 __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
lypinator 0:bb348c97df44 287 uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
lypinator 0:bb348c97df44 288 CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
lypinator 0:bb348c97df44 289 } CAN_TypeDef;
lypinator 0:bb348c97df44 290
lypinator 0:bb348c97df44 291 /**
lypinator 0:bb348c97df44 292 * @brief CRC calculation unit
lypinator 0:bb348c97df44 293 */
lypinator 0:bb348c97df44 294
lypinator 0:bb348c97df44 295 typedef struct
lypinator 0:bb348c97df44 296 {
lypinator 0:bb348c97df44 297 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
lypinator 0:bb348c97df44 298 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
lypinator 0:bb348c97df44 299 uint8_t RESERVED0; /*!< Reserved, 0x05 */
lypinator 0:bb348c97df44 300 uint16_t RESERVED1; /*!< Reserved, 0x06 */
lypinator 0:bb348c97df44 301 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
lypinator 0:bb348c97df44 302 } CRC_TypeDef;
lypinator 0:bb348c97df44 303
lypinator 0:bb348c97df44 304 /**
lypinator 0:bb348c97df44 305 * @brief DFSDM module registers
lypinator 0:bb348c97df44 306 */
lypinator 0:bb348c97df44 307 typedef struct
lypinator 0:bb348c97df44 308 {
lypinator 0:bb348c97df44 309 __IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */
lypinator 0:bb348c97df44 310 __IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */
lypinator 0:bb348c97df44 311 __IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */
lypinator 0:bb348c97df44 312 __IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */
lypinator 0:bb348c97df44 313 __IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */
lypinator 0:bb348c97df44 314 __IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */
lypinator 0:bb348c97df44 315 __IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */
lypinator 0:bb348c97df44 316 __IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */
lypinator 0:bb348c97df44 317 __IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */
lypinator 0:bb348c97df44 318 __IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */
lypinator 0:bb348c97df44 319 __IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */
lypinator 0:bb348c97df44 320 __IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */
lypinator 0:bb348c97df44 321 __IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */
lypinator 0:bb348c97df44 322 __IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */
lypinator 0:bb348c97df44 323 __IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */
lypinator 0:bb348c97df44 324 } DFSDM_Filter_TypeDef;
lypinator 0:bb348c97df44 325
lypinator 0:bb348c97df44 326 /**
lypinator 0:bb348c97df44 327 * @brief DFSDM channel configuration registers
lypinator 0:bb348c97df44 328 */
lypinator 0:bb348c97df44 329 typedef struct
lypinator 0:bb348c97df44 330 {
lypinator 0:bb348c97df44 331 __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */
lypinator 0:bb348c97df44 332 __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */
lypinator 0:bb348c97df44 333 __IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and
lypinator 0:bb348c97df44 334 short circuit detector register, Address offset: 0x08 */
lypinator 0:bb348c97df44 335 __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */
lypinator 0:bb348c97df44 336 __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */
lypinator 0:bb348c97df44 337 } DFSDM_Channel_TypeDef;
lypinator 0:bb348c97df44 338
lypinator 0:bb348c97df44 339 /**
lypinator 0:bb348c97df44 340 * @brief Debug MCU
lypinator 0:bb348c97df44 341 */
lypinator 0:bb348c97df44 342
lypinator 0:bb348c97df44 343 typedef struct
lypinator 0:bb348c97df44 344 {
lypinator 0:bb348c97df44 345 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
lypinator 0:bb348c97df44 346 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
lypinator 0:bb348c97df44 347 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
lypinator 0:bb348c97df44 348 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
lypinator 0:bb348c97df44 349 }DBGMCU_TypeDef;
lypinator 0:bb348c97df44 350
lypinator 0:bb348c97df44 351
lypinator 0:bb348c97df44 352 /**
lypinator 0:bb348c97df44 353 * @brief DMA Controller
lypinator 0:bb348c97df44 354 */
lypinator 0:bb348c97df44 355
lypinator 0:bb348c97df44 356 typedef struct
lypinator 0:bb348c97df44 357 {
lypinator 0:bb348c97df44 358 __IO uint32_t CR; /*!< DMA stream x configuration register */
lypinator 0:bb348c97df44 359 __IO uint32_t NDTR; /*!< DMA stream x number of data register */
lypinator 0:bb348c97df44 360 __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
lypinator 0:bb348c97df44 361 __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
lypinator 0:bb348c97df44 362 __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
lypinator 0:bb348c97df44 363 __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
lypinator 0:bb348c97df44 364 } DMA_Stream_TypeDef;
lypinator 0:bb348c97df44 365
lypinator 0:bb348c97df44 366 typedef struct
lypinator 0:bb348c97df44 367 {
lypinator 0:bb348c97df44 368 __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
lypinator 0:bb348c97df44 369 __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
lypinator 0:bb348c97df44 370 __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
lypinator 0:bb348c97df44 371 __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
lypinator 0:bb348c97df44 372 } DMA_TypeDef;
lypinator 0:bb348c97df44 373
lypinator 0:bb348c97df44 374 /**
lypinator 0:bb348c97df44 375 * @brief External Interrupt/Event Controller
lypinator 0:bb348c97df44 376 */
lypinator 0:bb348c97df44 377
lypinator 0:bb348c97df44 378 typedef struct
lypinator 0:bb348c97df44 379 {
lypinator 0:bb348c97df44 380 __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
lypinator 0:bb348c97df44 381 __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
lypinator 0:bb348c97df44 382 __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
lypinator 0:bb348c97df44 383 __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
lypinator 0:bb348c97df44 384 __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
lypinator 0:bb348c97df44 385 __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
lypinator 0:bb348c97df44 386 } EXTI_TypeDef;
lypinator 0:bb348c97df44 387
lypinator 0:bb348c97df44 388 /**
lypinator 0:bb348c97df44 389 * @brief FLASH Registers
lypinator 0:bb348c97df44 390 */
lypinator 0:bb348c97df44 391
lypinator 0:bb348c97df44 392 typedef struct
lypinator 0:bb348c97df44 393 {
lypinator 0:bb348c97df44 394 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
lypinator 0:bb348c97df44 395 __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
lypinator 0:bb348c97df44 396 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
lypinator 0:bb348c97df44 397 __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
lypinator 0:bb348c97df44 398 __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
lypinator 0:bb348c97df44 399 __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
lypinator 0:bb348c97df44 400 __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
lypinator 0:bb348c97df44 401 } FLASH_TypeDef;
lypinator 0:bb348c97df44 402
lypinator 0:bb348c97df44 403
lypinator 0:bb348c97df44 404
lypinator 0:bb348c97df44 405 /**
lypinator 0:bb348c97df44 406 * @brief Flexible Static Memory Controller
lypinator 0:bb348c97df44 407 */
lypinator 0:bb348c97df44 408
lypinator 0:bb348c97df44 409 typedef struct
lypinator 0:bb348c97df44 410 {
lypinator 0:bb348c97df44 411 __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
lypinator 0:bb348c97df44 412 } FSMC_Bank1_TypeDef;
lypinator 0:bb348c97df44 413
lypinator 0:bb348c97df44 414 /**
lypinator 0:bb348c97df44 415 * @brief Flexible Static Memory Controller Bank1E
lypinator 0:bb348c97df44 416 */
lypinator 0:bb348c97df44 417
lypinator 0:bb348c97df44 418 typedef struct
lypinator 0:bb348c97df44 419 {
lypinator 0:bb348c97df44 420 __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
lypinator 0:bb348c97df44 421 } FSMC_Bank1E_TypeDef;
lypinator 0:bb348c97df44 422 /**
lypinator 0:bb348c97df44 423 * @brief General Purpose I/O
lypinator 0:bb348c97df44 424 */
lypinator 0:bb348c97df44 425
lypinator 0:bb348c97df44 426 typedef struct
lypinator 0:bb348c97df44 427 {
lypinator 0:bb348c97df44 428 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
lypinator 0:bb348c97df44 429 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
lypinator 0:bb348c97df44 430 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
lypinator 0:bb348c97df44 431 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
lypinator 0:bb348c97df44 432 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
lypinator 0:bb348c97df44 433 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
lypinator 0:bb348c97df44 434 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
lypinator 0:bb348c97df44 435 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
lypinator 0:bb348c97df44 436 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
lypinator 0:bb348c97df44 437 } GPIO_TypeDef;
lypinator 0:bb348c97df44 438
lypinator 0:bb348c97df44 439 /**
lypinator 0:bb348c97df44 440 * @brief System configuration controller
lypinator 0:bb348c97df44 441 */
lypinator 0:bb348c97df44 442
lypinator 0:bb348c97df44 443 typedef struct
lypinator 0:bb348c97df44 444 {
lypinator 0:bb348c97df44 445 __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
lypinator 0:bb348c97df44 446 __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
lypinator 0:bb348c97df44 447 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
lypinator 0:bb348c97df44 448 uint32_t RESERVED; /*!< Reserved, 0x18 */
lypinator 0:bb348c97df44 449 __IO uint32_t CFGR2; /*!< SYSCFG Configuration register2, Address offset: 0x1C */
lypinator 0:bb348c97df44 450 __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
lypinator 0:bb348c97df44 451 __IO uint32_t CFGR; /*!< SYSCFG Configuration register, Address offset: 0x24 */
lypinator 0:bb348c97df44 452 } SYSCFG_TypeDef;
lypinator 0:bb348c97df44 453
lypinator 0:bb348c97df44 454 /**
lypinator 0:bb348c97df44 455 * @brief Inter-integrated Circuit Interface
lypinator 0:bb348c97df44 456 */
lypinator 0:bb348c97df44 457
lypinator 0:bb348c97df44 458 typedef struct
lypinator 0:bb348c97df44 459 {
lypinator 0:bb348c97df44 460 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
lypinator 0:bb348c97df44 461 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
lypinator 0:bb348c97df44 462 __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
lypinator 0:bb348c97df44 463 __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
lypinator 0:bb348c97df44 464 __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
lypinator 0:bb348c97df44 465 __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
lypinator 0:bb348c97df44 466 __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
lypinator 0:bb348c97df44 467 __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
lypinator 0:bb348c97df44 468 __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
lypinator 0:bb348c97df44 469 __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */
lypinator 0:bb348c97df44 470 } I2C_TypeDef;
lypinator 0:bb348c97df44 471
lypinator 0:bb348c97df44 472 /**
lypinator 0:bb348c97df44 473 * @brief Inter-integrated Circuit Interface
lypinator 0:bb348c97df44 474 */
lypinator 0:bb348c97df44 475
lypinator 0:bb348c97df44 476 typedef struct
lypinator 0:bb348c97df44 477 {
lypinator 0:bb348c97df44 478 __IO uint32_t CR1; /*!< FMPI2C Control register 1, Address offset: 0x00 */
lypinator 0:bb348c97df44 479 __IO uint32_t CR2; /*!< FMPI2C Control register 2, Address offset: 0x04 */
lypinator 0:bb348c97df44 480 __IO uint32_t OAR1; /*!< FMPI2C Own address 1 register, Address offset: 0x08 */
lypinator 0:bb348c97df44 481 __IO uint32_t OAR2; /*!< FMPI2C Own address 2 register, Address offset: 0x0C */
lypinator 0:bb348c97df44 482 __IO uint32_t TIMINGR; /*!< FMPI2C Timing register, Address offset: 0x10 */
lypinator 0:bb348c97df44 483 __IO uint32_t TIMEOUTR; /*!< FMPI2C Timeout register, Address offset: 0x14 */
lypinator 0:bb348c97df44 484 __IO uint32_t ISR; /*!< FMPI2C Interrupt and status register, Address offset: 0x18 */
lypinator 0:bb348c97df44 485 __IO uint32_t ICR; /*!< FMPI2C Interrupt clear register, Address offset: 0x1C */
lypinator 0:bb348c97df44 486 __IO uint32_t PECR; /*!< FMPI2C PEC register, Address offset: 0x20 */
lypinator 0:bb348c97df44 487 __IO uint32_t RXDR; /*!< FMPI2C Receive data register, Address offset: 0x24 */
lypinator 0:bb348c97df44 488 __IO uint32_t TXDR; /*!< FMPI2C Transmit data register, Address offset: 0x28 */
lypinator 0:bb348c97df44 489 } FMPI2C_TypeDef;
lypinator 0:bb348c97df44 490
lypinator 0:bb348c97df44 491 /**
lypinator 0:bb348c97df44 492 * @brief Independent WATCHDOG
lypinator 0:bb348c97df44 493 */
lypinator 0:bb348c97df44 494
lypinator 0:bb348c97df44 495 typedef struct
lypinator 0:bb348c97df44 496 {
lypinator 0:bb348c97df44 497 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
lypinator 0:bb348c97df44 498 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
lypinator 0:bb348c97df44 499 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
lypinator 0:bb348c97df44 500 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
lypinator 0:bb348c97df44 501 } IWDG_TypeDef;
lypinator 0:bb348c97df44 502
lypinator 0:bb348c97df44 503
lypinator 0:bb348c97df44 504 /**
lypinator 0:bb348c97df44 505 * @brief Power Control
lypinator 0:bb348c97df44 506 */
lypinator 0:bb348c97df44 507
lypinator 0:bb348c97df44 508 typedef struct
lypinator 0:bb348c97df44 509 {
lypinator 0:bb348c97df44 510 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
lypinator 0:bb348c97df44 511 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
lypinator 0:bb348c97df44 512 } PWR_TypeDef;
lypinator 0:bb348c97df44 513
lypinator 0:bb348c97df44 514 /**
lypinator 0:bb348c97df44 515 * @brief Reset and Clock Control
lypinator 0:bb348c97df44 516 */
lypinator 0:bb348c97df44 517
lypinator 0:bb348c97df44 518 typedef struct
lypinator 0:bb348c97df44 519 {
lypinator 0:bb348c97df44 520 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
lypinator 0:bb348c97df44 521 __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
lypinator 0:bb348c97df44 522 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
lypinator 0:bb348c97df44 523 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
lypinator 0:bb348c97df44 524 __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
lypinator 0:bb348c97df44 525 __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
lypinator 0:bb348c97df44 526 __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
lypinator 0:bb348c97df44 527 uint32_t RESERVED0; /*!< Reserved, 0x1C */
lypinator 0:bb348c97df44 528 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
lypinator 0:bb348c97df44 529 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
lypinator 0:bb348c97df44 530 uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
lypinator 0:bb348c97df44 531 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
lypinator 0:bb348c97df44 532 __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
lypinator 0:bb348c97df44 533 __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
lypinator 0:bb348c97df44 534 uint32_t RESERVED2; /*!< Reserved, 0x3C */
lypinator 0:bb348c97df44 535 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
lypinator 0:bb348c97df44 536 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
lypinator 0:bb348c97df44 537 uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
lypinator 0:bb348c97df44 538 __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
lypinator 0:bb348c97df44 539 __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
lypinator 0:bb348c97df44 540 __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
lypinator 0:bb348c97df44 541 uint32_t RESERVED4; /*!< Reserved, 0x5C */
lypinator 0:bb348c97df44 542 __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
lypinator 0:bb348c97df44 543 __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
lypinator 0:bb348c97df44 544 uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
lypinator 0:bb348c97df44 545 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
lypinator 0:bb348c97df44 546 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
lypinator 0:bb348c97df44 547 uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
lypinator 0:bb348c97df44 548 __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
lypinator 0:bb348c97df44 549 __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
lypinator 0:bb348c97df44 550 uint32_t RESERVED7; /*!< Reserved, 0x88 */
lypinator 0:bb348c97df44 551 __IO uint32_t DCKCFGR; /*!< RCC Dedicated Clocks configuration register, Address offset: 0x8C */
lypinator 0:bb348c97df44 552 __IO uint32_t CKGATENR; /*!< RCC Clocks Gated ENable Register, Address offset: 0x90 */
lypinator 0:bb348c97df44 553 __IO uint32_t DCKCFGR2; /*!< RCC Dedicated Clocks configuration register 2, Address offset: 0x94 */
lypinator 0:bb348c97df44 554 } RCC_TypeDef;
lypinator 0:bb348c97df44 555
lypinator 0:bb348c97df44 556 /**
lypinator 0:bb348c97df44 557 * @brief Real-Time Clock
lypinator 0:bb348c97df44 558 */
lypinator 0:bb348c97df44 559
lypinator 0:bb348c97df44 560 typedef struct
lypinator 0:bb348c97df44 561 {
lypinator 0:bb348c97df44 562 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
lypinator 0:bb348c97df44 563 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
lypinator 0:bb348c97df44 564 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
lypinator 0:bb348c97df44 565 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
lypinator 0:bb348c97df44 566 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
lypinator 0:bb348c97df44 567 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
lypinator 0:bb348c97df44 568 __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
lypinator 0:bb348c97df44 569 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
lypinator 0:bb348c97df44 570 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
lypinator 0:bb348c97df44 571 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
lypinator 0:bb348c97df44 572 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
lypinator 0:bb348c97df44 573 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
lypinator 0:bb348c97df44 574 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
lypinator 0:bb348c97df44 575 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
lypinator 0:bb348c97df44 576 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
lypinator 0:bb348c97df44 577 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
lypinator 0:bb348c97df44 578 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
lypinator 0:bb348c97df44 579 __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
lypinator 0:bb348c97df44 580 __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
lypinator 0:bb348c97df44 581 uint32_t RESERVED7; /*!< Reserved, 0x4C */
lypinator 0:bb348c97df44 582 __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
lypinator 0:bb348c97df44 583 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
lypinator 0:bb348c97df44 584 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
lypinator 0:bb348c97df44 585 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
lypinator 0:bb348c97df44 586 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
lypinator 0:bb348c97df44 587 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
lypinator 0:bb348c97df44 588 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
lypinator 0:bb348c97df44 589 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
lypinator 0:bb348c97df44 590 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
lypinator 0:bb348c97df44 591 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
lypinator 0:bb348c97df44 592 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
lypinator 0:bb348c97df44 593 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
lypinator 0:bb348c97df44 594 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
lypinator 0:bb348c97df44 595 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
lypinator 0:bb348c97df44 596 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
lypinator 0:bb348c97df44 597 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
lypinator 0:bb348c97df44 598 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
lypinator 0:bb348c97df44 599 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
lypinator 0:bb348c97df44 600 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
lypinator 0:bb348c97df44 601 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
lypinator 0:bb348c97df44 602 } RTC_TypeDef;
lypinator 0:bb348c97df44 603
lypinator 0:bb348c97df44 604 /**
lypinator 0:bb348c97df44 605 * @brief SD host Interface
lypinator 0:bb348c97df44 606 */
lypinator 0:bb348c97df44 607
lypinator 0:bb348c97df44 608 typedef struct
lypinator 0:bb348c97df44 609 {
lypinator 0:bb348c97df44 610 __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
lypinator 0:bb348c97df44 611 __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
lypinator 0:bb348c97df44 612 __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
lypinator 0:bb348c97df44 613 __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
lypinator 0:bb348c97df44 614 __IO const uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
lypinator 0:bb348c97df44 615 __IO const uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
lypinator 0:bb348c97df44 616 __IO const uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
lypinator 0:bb348c97df44 617 __IO const uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
lypinator 0:bb348c97df44 618 __IO const uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
lypinator 0:bb348c97df44 619 __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
lypinator 0:bb348c97df44 620 __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
lypinator 0:bb348c97df44 621 __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
lypinator 0:bb348c97df44 622 __IO const uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
lypinator 0:bb348c97df44 623 __IO const uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
lypinator 0:bb348c97df44 624 __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
lypinator 0:bb348c97df44 625 __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
lypinator 0:bb348c97df44 626 uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
lypinator 0:bb348c97df44 627 __IO const uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
lypinator 0:bb348c97df44 628 uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
lypinator 0:bb348c97df44 629 __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
lypinator 0:bb348c97df44 630 } SDIO_TypeDef;
lypinator 0:bb348c97df44 631
lypinator 0:bb348c97df44 632 /**
lypinator 0:bb348c97df44 633 * @brief Serial Peripheral Interface
lypinator 0:bb348c97df44 634 */
lypinator 0:bb348c97df44 635
lypinator 0:bb348c97df44 636 typedef struct
lypinator 0:bb348c97df44 637 {
lypinator 0:bb348c97df44 638 __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
lypinator 0:bb348c97df44 639 __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
lypinator 0:bb348c97df44 640 __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
lypinator 0:bb348c97df44 641 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
lypinator 0:bb348c97df44 642 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
lypinator 0:bb348c97df44 643 __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
lypinator 0:bb348c97df44 644 __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
lypinator 0:bb348c97df44 645 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
lypinator 0:bb348c97df44 646 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
lypinator 0:bb348c97df44 647 } SPI_TypeDef;
lypinator 0:bb348c97df44 648
lypinator 0:bb348c97df44 649 /**
lypinator 0:bb348c97df44 650 * @brief QUAD Serial Peripheral Interface
lypinator 0:bb348c97df44 651 */
lypinator 0:bb348c97df44 652
lypinator 0:bb348c97df44 653 typedef struct
lypinator 0:bb348c97df44 654 {
lypinator 0:bb348c97df44 655 __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */
lypinator 0:bb348c97df44 656 __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */
lypinator 0:bb348c97df44 657 __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */
lypinator 0:bb348c97df44 658 __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */
lypinator 0:bb348c97df44 659 __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */
lypinator 0:bb348c97df44 660 __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */
lypinator 0:bb348c97df44 661 __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */
lypinator 0:bb348c97df44 662 __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */
lypinator 0:bb348c97df44 663 __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */
lypinator 0:bb348c97df44 664 __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */
lypinator 0:bb348c97df44 665 __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */
lypinator 0:bb348c97df44 666 __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */
lypinator 0:bb348c97df44 667 __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */
lypinator 0:bb348c97df44 668 } QUADSPI_TypeDef;
lypinator 0:bb348c97df44 669
lypinator 0:bb348c97df44 670 /**
lypinator 0:bb348c97df44 671 * @brief TIM
lypinator 0:bb348c97df44 672 */
lypinator 0:bb348c97df44 673
lypinator 0:bb348c97df44 674 typedef struct
lypinator 0:bb348c97df44 675 {
lypinator 0:bb348c97df44 676 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
lypinator 0:bb348c97df44 677 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
lypinator 0:bb348c97df44 678 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
lypinator 0:bb348c97df44 679 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
lypinator 0:bb348c97df44 680 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
lypinator 0:bb348c97df44 681 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
lypinator 0:bb348c97df44 682 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
lypinator 0:bb348c97df44 683 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
lypinator 0:bb348c97df44 684 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
lypinator 0:bb348c97df44 685 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
lypinator 0:bb348c97df44 686 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
lypinator 0:bb348c97df44 687 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
lypinator 0:bb348c97df44 688 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
lypinator 0:bb348c97df44 689 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
lypinator 0:bb348c97df44 690 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
lypinator 0:bb348c97df44 691 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
lypinator 0:bb348c97df44 692 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
lypinator 0:bb348c97df44 693 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
lypinator 0:bb348c97df44 694 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
lypinator 0:bb348c97df44 695 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
lypinator 0:bb348c97df44 696 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
lypinator 0:bb348c97df44 697 } TIM_TypeDef;
lypinator 0:bb348c97df44 698
lypinator 0:bb348c97df44 699 /**
lypinator 0:bb348c97df44 700 * @brief Universal Synchronous Asynchronous Receiver Transmitter
lypinator 0:bb348c97df44 701 */
lypinator 0:bb348c97df44 702
lypinator 0:bb348c97df44 703 typedef struct
lypinator 0:bb348c97df44 704 {
lypinator 0:bb348c97df44 705 __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
lypinator 0:bb348c97df44 706 __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
lypinator 0:bb348c97df44 707 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
lypinator 0:bb348c97df44 708 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
lypinator 0:bb348c97df44 709 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
lypinator 0:bb348c97df44 710 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
lypinator 0:bb348c97df44 711 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
lypinator 0:bb348c97df44 712 } USART_TypeDef;
lypinator 0:bb348c97df44 713
lypinator 0:bb348c97df44 714 /**
lypinator 0:bb348c97df44 715 * @brief Window WATCHDOG
lypinator 0:bb348c97df44 716 */
lypinator 0:bb348c97df44 717
lypinator 0:bb348c97df44 718 typedef struct
lypinator 0:bb348c97df44 719 {
lypinator 0:bb348c97df44 720 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
lypinator 0:bb348c97df44 721 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
lypinator 0:bb348c97df44 722 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
lypinator 0:bb348c97df44 723 } WWDG_TypeDef;
lypinator 0:bb348c97df44 724
lypinator 0:bb348c97df44 725 /**
lypinator 0:bb348c97df44 726 * @brief RNG
lypinator 0:bb348c97df44 727 */
lypinator 0:bb348c97df44 728
lypinator 0:bb348c97df44 729 typedef struct
lypinator 0:bb348c97df44 730 {
lypinator 0:bb348c97df44 731 __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
lypinator 0:bb348c97df44 732 __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
lypinator 0:bb348c97df44 733 __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
lypinator 0:bb348c97df44 734 } RNG_TypeDef;
lypinator 0:bb348c97df44 735
lypinator 0:bb348c97df44 736 /**
lypinator 0:bb348c97df44 737 * @brief USB_OTG_Core_Registers
lypinator 0:bb348c97df44 738 */
lypinator 0:bb348c97df44 739 typedef struct
lypinator 0:bb348c97df44 740 {
lypinator 0:bb348c97df44 741 __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */
lypinator 0:bb348c97df44 742 __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */
lypinator 0:bb348c97df44 743 __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */
lypinator 0:bb348c97df44 744 __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */
lypinator 0:bb348c97df44 745 __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */
lypinator 0:bb348c97df44 746 __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */
lypinator 0:bb348c97df44 747 __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */
lypinator 0:bb348c97df44 748 __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */
lypinator 0:bb348c97df44 749 __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */
lypinator 0:bb348c97df44 750 __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */
lypinator 0:bb348c97df44 751 __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */
lypinator 0:bb348c97df44 752 __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */
lypinator 0:bb348c97df44 753 uint32_t Reserved30[2]; /*!< Reserved 030h */
lypinator 0:bb348c97df44 754 __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */
lypinator 0:bb348c97df44 755 __IO uint32_t CID; /*!< User ID Register 03Ch */
lypinator 0:bb348c97df44 756 uint32_t Reserved5[3]; /*!< Reserved 040h-048h */
lypinator 0:bb348c97df44 757 __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */
lypinator 0:bb348c97df44 758 uint32_t Reserved6; /*!< Reserved 050h */
lypinator 0:bb348c97df44 759 __IO uint32_t GLPMCFG; /*!< LPM Register 054h */
lypinator 0:bb348c97df44 760 uint32_t Reserved; /*!< Reserved 058h */
lypinator 0:bb348c97df44 761 __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */
lypinator 0:bb348c97df44 762 uint32_t Reserved43[40]; /*!< Reserved 058h-0FFh */
lypinator 0:bb348c97df44 763 __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */
lypinator 0:bb348c97df44 764 __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
lypinator 0:bb348c97df44 765 } USB_OTG_GlobalTypeDef;
lypinator 0:bb348c97df44 766
lypinator 0:bb348c97df44 767 /**
lypinator 0:bb348c97df44 768 * @brief USB_OTG_device_Registers
lypinator 0:bb348c97df44 769 */
lypinator 0:bb348c97df44 770 typedef struct
lypinator 0:bb348c97df44 771 {
lypinator 0:bb348c97df44 772 __IO uint32_t DCFG; /*!< dev Configuration Register 800h */
lypinator 0:bb348c97df44 773 __IO uint32_t DCTL; /*!< dev Control Register 804h */
lypinator 0:bb348c97df44 774 __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */
lypinator 0:bb348c97df44 775 uint32_t Reserved0C; /*!< Reserved 80Ch */
lypinator 0:bb348c97df44 776 __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */
lypinator 0:bb348c97df44 777 __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */
lypinator 0:bb348c97df44 778 __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */
lypinator 0:bb348c97df44 779 __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */
lypinator 0:bb348c97df44 780 uint32_t Reserved20; /*!< Reserved 820h */
lypinator 0:bb348c97df44 781 uint32_t Reserved9; /*!< Reserved 824h */
lypinator 0:bb348c97df44 782 __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */
lypinator 0:bb348c97df44 783 __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */
lypinator 0:bb348c97df44 784 __IO uint32_t DTHRCTL; /*!< dev threshold 830h */
lypinator 0:bb348c97df44 785 __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */
lypinator 0:bb348c97df44 786 __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */
lypinator 0:bb348c97df44 787 __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */
lypinator 0:bb348c97df44 788 uint32_t Reserved40; /*!< dedicated EP mask 840h */
lypinator 0:bb348c97df44 789 __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */
lypinator 0:bb348c97df44 790 uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */
lypinator 0:bb348c97df44 791 __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */
lypinator 0:bb348c97df44 792 } USB_OTG_DeviceTypeDef;
lypinator 0:bb348c97df44 793
lypinator 0:bb348c97df44 794 /**
lypinator 0:bb348c97df44 795 * @brief USB_OTG_IN_Endpoint-Specific_Register
lypinator 0:bb348c97df44 796 */
lypinator 0:bb348c97df44 797 typedef struct
lypinator 0:bb348c97df44 798 {
lypinator 0:bb348c97df44 799 __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
lypinator 0:bb348c97df44 800 uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */
lypinator 0:bb348c97df44 801 __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
lypinator 0:bb348c97df44 802 uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */
lypinator 0:bb348c97df44 803 __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
lypinator 0:bb348c97df44 804 __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
lypinator 0:bb348c97df44 805 __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
lypinator 0:bb348c97df44 806 uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
lypinator 0:bb348c97df44 807 } USB_OTG_INEndpointTypeDef;
lypinator 0:bb348c97df44 808
lypinator 0:bb348c97df44 809 /**
lypinator 0:bb348c97df44 810 * @brief USB_OTG_OUT_Endpoint-Specific_Registers
lypinator 0:bb348c97df44 811 */
lypinator 0:bb348c97df44 812 typedef struct
lypinator 0:bb348c97df44 813 {
lypinator 0:bb348c97df44 814 __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */
lypinator 0:bb348c97df44 815 uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */
lypinator 0:bb348c97df44 816 __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */
lypinator 0:bb348c97df44 817 uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */
lypinator 0:bb348c97df44 818 __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */
lypinator 0:bb348c97df44 819 __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */
lypinator 0:bb348c97df44 820 uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
lypinator 0:bb348c97df44 821 } USB_OTG_OUTEndpointTypeDef;
lypinator 0:bb348c97df44 822
lypinator 0:bb348c97df44 823 /**
lypinator 0:bb348c97df44 824 * @brief USB_OTG_Host_Mode_Register_Structures
lypinator 0:bb348c97df44 825 */
lypinator 0:bb348c97df44 826 typedef struct
lypinator 0:bb348c97df44 827 {
lypinator 0:bb348c97df44 828 __IO uint32_t HCFG; /*!< Host Configuration Register 400h */
lypinator 0:bb348c97df44 829 __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */
lypinator 0:bb348c97df44 830 __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */
lypinator 0:bb348c97df44 831 uint32_t Reserved40C; /*!< Reserved 40Ch */
lypinator 0:bb348c97df44 832 __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */
lypinator 0:bb348c97df44 833 __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */
lypinator 0:bb348c97df44 834 __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */
lypinator 0:bb348c97df44 835 } USB_OTG_HostTypeDef;
lypinator 0:bb348c97df44 836
lypinator 0:bb348c97df44 837 /**
lypinator 0:bb348c97df44 838 * @brief USB_OTG_Host_Channel_Specific_Registers
lypinator 0:bb348c97df44 839 */
lypinator 0:bb348c97df44 840 typedef struct
lypinator 0:bb348c97df44 841 {
lypinator 0:bb348c97df44 842 __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */
lypinator 0:bb348c97df44 843 __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */
lypinator 0:bb348c97df44 844 __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */
lypinator 0:bb348c97df44 845 __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */
lypinator 0:bb348c97df44 846 __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */
lypinator 0:bb348c97df44 847 __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */
lypinator 0:bb348c97df44 848 uint32_t Reserved[2]; /*!< Reserved */
lypinator 0:bb348c97df44 849 } USB_OTG_HostChannelTypeDef;
lypinator 0:bb348c97df44 850
lypinator 0:bb348c97df44 851 /**
lypinator 0:bb348c97df44 852 * @}
lypinator 0:bb348c97df44 853 */
lypinator 0:bb348c97df44 854
lypinator 0:bb348c97df44 855 /** @addtogroup Peripheral_memory_map
lypinator 0:bb348c97df44 856 * @{
lypinator 0:bb348c97df44 857 */
lypinator 0:bb348c97df44 858 #define FLASH_BASE 0x08000000U /*!< FLASH(up to 1 MB) base address in the alias region */
lypinator 0:bb348c97df44 859 #define SRAM1_BASE 0x20000000U /*!< SRAM1(256 KB) base address in the alias region */
lypinator 0:bb348c97df44 860 #define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */
lypinator 0:bb348c97df44 861 #define FSMC_R_BASE 0xA0000000U /*!< FSMC registers base address */
lypinator 0:bb348c97df44 862 #define QSPI_R_BASE 0xA0001000U /*!< QuadSPI registers base address */
lypinator 0:bb348c97df44 863 #define SRAM1_BB_BASE 0x22000000U /*!< SRAM1(256 KB) base address in the bit-band region */
lypinator 0:bb348c97df44 864 #define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */
lypinator 0:bb348c97df44 865 #define FLASH_END 0x080FFFFFU /*!< FLASH end address */
lypinator 0:bb348c97df44 866 #define FLASH_OTP_BASE 0x1FFF7800U /*!< Base address of : (up to 528 Bytes) embedded FLASH OTP Area */
lypinator 0:bb348c97df44 867 #define FLASH_OTP_END 0x1FFF7A0FU /*!< End address of : (up to 528 Bytes) embedded FLASH OTP Area */
lypinator 0:bb348c97df44 868
lypinator 0:bb348c97df44 869 /* Legacy defines */
lypinator 0:bb348c97df44 870 #define SRAM_BASE SRAM1_BASE
lypinator 0:bb348c97df44 871 #define SRAM_BB_BASE SRAM1_BB_BASE
lypinator 0:bb348c97df44 872
lypinator 0:bb348c97df44 873 /*!< Peripheral memory map */
lypinator 0:bb348c97df44 874 #define APB1PERIPH_BASE PERIPH_BASE
lypinator 0:bb348c97df44 875 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
lypinator 0:bb348c97df44 876 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
lypinator 0:bb348c97df44 877 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)
lypinator 0:bb348c97df44 878
lypinator 0:bb348c97df44 879 /*!< APB1 peripherals */
lypinator 0:bb348c97df44 880 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
lypinator 0:bb348c97df44 881 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)
lypinator 0:bb348c97df44 882 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800U)
lypinator 0:bb348c97df44 883 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
lypinator 0:bb348c97df44 884 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000U)
lypinator 0:bb348c97df44 885 #define TIM7_BASE (APB1PERIPH_BASE + 0x1400U)
lypinator 0:bb348c97df44 886 #define TIM12_BASE (APB1PERIPH_BASE + 0x1800U)
lypinator 0:bb348c97df44 887 #define TIM13_BASE (APB1PERIPH_BASE + 0x1C00U)
lypinator 0:bb348c97df44 888 #define TIM14_BASE (APB1PERIPH_BASE + 0x2000U)
lypinator 0:bb348c97df44 889 #define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
lypinator 0:bb348c97df44 890 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
lypinator 0:bb348c97df44 891 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
lypinator 0:bb348c97df44 892 #define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400U)
lypinator 0:bb348c97df44 893 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
lypinator 0:bb348c97df44 894 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
lypinator 0:bb348c97df44 895 #define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000U)
lypinator 0:bb348c97df44 896 #define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
lypinator 0:bb348c97df44 897 #define USART3_BASE (APB1PERIPH_BASE + 0x4800U)
lypinator 0:bb348c97df44 898 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
lypinator 0:bb348c97df44 899 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
lypinator 0:bb348c97df44 900 #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
lypinator 0:bb348c97df44 901 #define FMPI2C1_BASE (APB1PERIPH_BASE + 0x6000U)
lypinator 0:bb348c97df44 902 #define CAN1_BASE (APB1PERIPH_BASE + 0x6400U)
lypinator 0:bb348c97df44 903 #define CAN2_BASE (APB1PERIPH_BASE + 0x6800U)
lypinator 0:bb348c97df44 904 #define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
lypinator 0:bb348c97df44 905
lypinator 0:bb348c97df44 906 /*!< APB2 peripherals */
lypinator 0:bb348c97df44 907 #define TIM1_BASE (APB2PERIPH_BASE + 0x0000U)
lypinator 0:bb348c97df44 908 #define TIM8_BASE (APB2PERIPH_BASE + 0x0400U)
lypinator 0:bb348c97df44 909 #define USART1_BASE (APB2PERIPH_BASE + 0x1000U)
lypinator 0:bb348c97df44 910 #define USART6_BASE (APB2PERIPH_BASE + 0x1400U)
lypinator 0:bb348c97df44 911 #define ADC1_BASE (APB2PERIPH_BASE + 0x2000U)
lypinator 0:bb348c97df44 912 #define ADC1_COMMON_BASE (APB2PERIPH_BASE + 0x2300U)
lypinator 0:bb348c97df44 913 /* Legacy define */
lypinator 0:bb348c97df44 914 #define ADC_BASE ADC1_COMMON_BASE
lypinator 0:bb348c97df44 915 #define SDIO_BASE (APB2PERIPH_BASE + 0x2C00U)
lypinator 0:bb348c97df44 916 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
lypinator 0:bb348c97df44 917 #define SPI4_BASE (APB2PERIPH_BASE + 0x3400U)
lypinator 0:bb348c97df44 918 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)
lypinator 0:bb348c97df44 919 #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)
lypinator 0:bb348c97df44 920 #define TIM9_BASE (APB2PERIPH_BASE + 0x4000U)
lypinator 0:bb348c97df44 921 #define TIM10_BASE (APB2PERIPH_BASE + 0x4400U)
lypinator 0:bb348c97df44 922 #define TIM11_BASE (APB2PERIPH_BASE + 0x4800U)
lypinator 0:bb348c97df44 923 #define SPI5_BASE (APB2PERIPH_BASE + 0x5000U)
lypinator 0:bb348c97df44 924 #define DFSDM1_BASE (APB2PERIPH_BASE + 0x6000U)
lypinator 0:bb348c97df44 925 #define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00U)
lypinator 0:bb348c97df44 926 #define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20U)
lypinator 0:bb348c97df44 927 #define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40U)
lypinator 0:bb348c97df44 928 #define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x60U)
lypinator 0:bb348c97df44 929 #define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x100U)
lypinator 0:bb348c97df44 930 #define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180U)
lypinator 0:bb348c97df44 931
lypinator 0:bb348c97df44 932 /*!< AHB1 peripherals */
lypinator 0:bb348c97df44 933 #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)
lypinator 0:bb348c97df44 934 #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)
lypinator 0:bb348c97df44 935 #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)
lypinator 0:bb348c97df44 936 #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U)
lypinator 0:bb348c97df44 937 #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U)
lypinator 0:bb348c97df44 938 #define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400U)
lypinator 0:bb348c97df44 939 #define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800U)
lypinator 0:bb348c97df44 940 #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)
lypinator 0:bb348c97df44 941 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
lypinator 0:bb348c97df44 942 #define RCC_BASE (AHB1PERIPH_BASE + 0x3800U)
lypinator 0:bb348c97df44 943 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)
lypinator 0:bb348c97df44 944 #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)
lypinator 0:bb348c97df44 945 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010U)
lypinator 0:bb348c97df44 946 #define DMA1_Stream1_BASE (DMA1_BASE + 0x028U)
lypinator 0:bb348c97df44 947 #define DMA1_Stream2_BASE (DMA1_BASE + 0x040U)
lypinator 0:bb348c97df44 948 #define DMA1_Stream3_BASE (DMA1_BASE + 0x058U)
lypinator 0:bb348c97df44 949 #define DMA1_Stream4_BASE (DMA1_BASE + 0x070U)
lypinator 0:bb348c97df44 950 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088U)
lypinator 0:bb348c97df44 951 #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)
lypinator 0:bb348c97df44 952 #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)
lypinator 0:bb348c97df44 953 #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)
lypinator 0:bb348c97df44 954 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010U)
lypinator 0:bb348c97df44 955 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028U)
lypinator 0:bb348c97df44 956 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040U)
lypinator 0:bb348c97df44 957 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058U)
lypinator 0:bb348c97df44 958 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070U)
lypinator 0:bb348c97df44 959 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088U)
lypinator 0:bb348c97df44 960 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)
lypinator 0:bb348c97df44 961 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)
lypinator 0:bb348c97df44 962
lypinator 0:bb348c97df44 963 /*!< AHB2 peripherals */
lypinator 0:bb348c97df44 964 #define RNG_BASE (AHB2PERIPH_BASE + 0x60800U)
lypinator 0:bb348c97df44 965
lypinator 0:bb348c97df44 966
lypinator 0:bb348c97df44 967 /*!< FSMC Bankx registers base address */
lypinator 0:bb348c97df44 968 #define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000U)
lypinator 0:bb348c97df44 969 #define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104U)
lypinator 0:bb348c97df44 970
lypinator 0:bb348c97df44 971 /*!< Debug MCU registers base address */
lypinator 0:bb348c97df44 972 #define DBGMCU_BASE 0xE0042000U
lypinator 0:bb348c97df44 973 /*!< USB registers base address */
lypinator 0:bb348c97df44 974 #define USB_OTG_FS_PERIPH_BASE 0x50000000U
lypinator 0:bb348c97df44 975
lypinator 0:bb348c97df44 976 #define USB_OTG_GLOBAL_BASE 0x000U
lypinator 0:bb348c97df44 977 #define USB_OTG_DEVICE_BASE 0x800U
lypinator 0:bb348c97df44 978 #define USB_OTG_IN_ENDPOINT_BASE 0x900U
lypinator 0:bb348c97df44 979 #define USB_OTG_OUT_ENDPOINT_BASE 0xB00U
lypinator 0:bb348c97df44 980 #define USB_OTG_EP_REG_SIZE 0x20U
lypinator 0:bb348c97df44 981 #define USB_OTG_HOST_BASE 0x400U
lypinator 0:bb348c97df44 982 #define USB_OTG_HOST_PORT_BASE 0x440U
lypinator 0:bb348c97df44 983 #define USB_OTG_HOST_CHANNEL_BASE 0x500U
lypinator 0:bb348c97df44 984 #define USB_OTG_HOST_CHANNEL_SIZE 0x20U
lypinator 0:bb348c97df44 985 #define USB_OTG_PCGCCTL_BASE 0xE00U
lypinator 0:bb348c97df44 986 #define USB_OTG_FIFO_BASE 0x1000U
lypinator 0:bb348c97df44 987 #define USB_OTG_FIFO_SIZE 0x1000U
lypinator 0:bb348c97df44 988
lypinator 0:bb348c97df44 989 #define UID_BASE 0x1FFF7A10U /*!< Unique device ID register base address */
lypinator 0:bb348c97df44 990 #define FLASHSIZE_BASE 0x1FFF7A22U /*!< FLASH Size register base address */
lypinator 0:bb348c97df44 991 #define PACKAGE_BASE 0x1FFF7BF0U /*!< Package size register base address */
lypinator 0:bb348c97df44 992 /**
lypinator 0:bb348c97df44 993 * @}
lypinator 0:bb348c97df44 994 */
lypinator 0:bb348c97df44 995
lypinator 0:bb348c97df44 996 /** @addtogroup Peripheral_declaration
lypinator 0:bb348c97df44 997 * @{
lypinator 0:bb348c97df44 998 */
lypinator 0:bb348c97df44 999 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
lypinator 0:bb348c97df44 1000 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
lypinator 0:bb348c97df44 1001 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
lypinator 0:bb348c97df44 1002 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
lypinator 0:bb348c97df44 1003 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
lypinator 0:bb348c97df44 1004 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
lypinator 0:bb348c97df44 1005 #define TIM12 ((TIM_TypeDef *) TIM12_BASE)
lypinator 0:bb348c97df44 1006 #define TIM13 ((TIM_TypeDef *) TIM13_BASE)
lypinator 0:bb348c97df44 1007 #define TIM14 ((TIM_TypeDef *) TIM14_BASE)
lypinator 0:bb348c97df44 1008 #define RTC ((RTC_TypeDef *) RTC_BASE)
lypinator 0:bb348c97df44 1009 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
lypinator 0:bb348c97df44 1010 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
lypinator 0:bb348c97df44 1011 #define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
lypinator 0:bb348c97df44 1012 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
lypinator 0:bb348c97df44 1013 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
lypinator 0:bb348c97df44 1014 #define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
lypinator 0:bb348c97df44 1015 #define USART2 ((USART_TypeDef *) USART2_BASE)
lypinator 0:bb348c97df44 1016 #define USART3 ((USART_TypeDef *) USART3_BASE)
lypinator 0:bb348c97df44 1017 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
lypinator 0:bb348c97df44 1018 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
lypinator 0:bb348c97df44 1019 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
lypinator 0:bb348c97df44 1020 #define FMPI2C1 ((FMPI2C_TypeDef *) FMPI2C1_BASE)
lypinator 0:bb348c97df44 1021 #define CAN1 ((CAN_TypeDef *) CAN1_BASE)
lypinator 0:bb348c97df44 1022 #define CAN2 ((CAN_TypeDef *) CAN2_BASE)
lypinator 0:bb348c97df44 1023 #define PWR ((PWR_TypeDef *) PWR_BASE)
lypinator 0:bb348c97df44 1024 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
lypinator 0:bb348c97df44 1025 #define TIM8 ((TIM_TypeDef *) TIM8_BASE)
lypinator 0:bb348c97df44 1026 #define USART1 ((USART_TypeDef *) USART1_BASE)
lypinator 0:bb348c97df44 1027 #define USART6 ((USART_TypeDef *) USART6_BASE)
lypinator 0:bb348c97df44 1028 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
lypinator 0:bb348c97df44 1029 #define ADC1_COMMON ((ADC_Common_TypeDef *) ADC1_COMMON_BASE)
lypinator 0:bb348c97df44 1030 /* Legacy define */
lypinator 0:bb348c97df44 1031 #define ADC ADC1_COMMON
lypinator 0:bb348c97df44 1032 #define SDIO ((SDIO_TypeDef *) SDIO_BASE)
lypinator 0:bb348c97df44 1033 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
lypinator 0:bb348c97df44 1034 #define SPI4 ((SPI_TypeDef *) SPI4_BASE)
lypinator 0:bb348c97df44 1035 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
lypinator 0:bb348c97df44 1036 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
lypinator 0:bb348c97df44 1037 #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
lypinator 0:bb348c97df44 1038 #define TIM10 ((TIM_TypeDef *) TIM10_BASE)
lypinator 0:bb348c97df44 1039 #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
lypinator 0:bb348c97df44 1040 #define SPI5 ((SPI_TypeDef *) SPI5_BASE)
lypinator 0:bb348c97df44 1041 #define DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)
lypinator 0:bb348c97df44 1042 #define DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)
lypinator 0:bb348c97df44 1043 #define DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)
lypinator 0:bb348c97df44 1044 #define DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)
lypinator 0:bb348c97df44 1045 #define DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)
lypinator 0:bb348c97df44 1046 #define DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)
lypinator 0:bb348c97df44 1047 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
lypinator 0:bb348c97df44 1048 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
lypinator 0:bb348c97df44 1049 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
lypinator 0:bb348c97df44 1050 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
lypinator 0:bb348c97df44 1051 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
lypinator 0:bb348c97df44 1052 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
lypinator 0:bb348c97df44 1053 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
lypinator 0:bb348c97df44 1054 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
lypinator 0:bb348c97df44 1055 #define CRC ((CRC_TypeDef *) CRC_BASE)
lypinator 0:bb348c97df44 1056 #define RCC ((RCC_TypeDef *) RCC_BASE)
lypinator 0:bb348c97df44 1057 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
lypinator 0:bb348c97df44 1058 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
lypinator 0:bb348c97df44 1059 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
lypinator 0:bb348c97df44 1060 #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
lypinator 0:bb348c97df44 1061 #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
lypinator 0:bb348c97df44 1062 #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
lypinator 0:bb348c97df44 1063 #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
lypinator 0:bb348c97df44 1064 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
lypinator 0:bb348c97df44 1065 #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
lypinator 0:bb348c97df44 1066 #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
lypinator 0:bb348c97df44 1067 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
lypinator 0:bb348c97df44 1068 #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
lypinator 0:bb348c97df44 1069 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
lypinator 0:bb348c97df44 1070 #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
lypinator 0:bb348c97df44 1071 #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
lypinator 0:bb348c97df44 1072 #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
lypinator 0:bb348c97df44 1073 #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
lypinator 0:bb348c97df44 1074 #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
lypinator 0:bb348c97df44 1075 #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
lypinator 0:bb348c97df44 1076 #define RNG ((RNG_TypeDef *) RNG_BASE)
lypinator 0:bb348c97df44 1077 #define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
lypinator 0:bb348c97df44 1078 #define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
lypinator 0:bb348c97df44 1079 #define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
lypinator 0:bb348c97df44 1080 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
lypinator 0:bb348c97df44 1081 #define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
lypinator 0:bb348c97df44 1082
lypinator 0:bb348c97df44 1083 /**
lypinator 0:bb348c97df44 1084 * @}
lypinator 0:bb348c97df44 1085 */
lypinator 0:bb348c97df44 1086
lypinator 0:bb348c97df44 1087 /** @addtogroup Exported_constants
lypinator 0:bb348c97df44 1088 * @{
lypinator 0:bb348c97df44 1089 */
lypinator 0:bb348c97df44 1090
lypinator 0:bb348c97df44 1091 /** @addtogroup Peripheral_Registers_Bits_Definition
lypinator 0:bb348c97df44 1092 * @{
lypinator 0:bb348c97df44 1093 */
lypinator 0:bb348c97df44 1094
lypinator 0:bb348c97df44 1095 /******************************************************************************/
lypinator 0:bb348c97df44 1096 /* Peripheral Registers_Bits_Definition */
lypinator 0:bb348c97df44 1097 /******************************************************************************/
lypinator 0:bb348c97df44 1098
lypinator 0:bb348c97df44 1099 /******************************************************************************/
lypinator 0:bb348c97df44 1100 /* */
lypinator 0:bb348c97df44 1101 /* Analog to Digital Converter */
lypinator 0:bb348c97df44 1102 /* */
lypinator 0:bb348c97df44 1103 /******************************************************************************/
lypinator 0:bb348c97df44 1104
lypinator 0:bb348c97df44 1105 /******************** Bit definition for ADC_SR register ********************/
lypinator 0:bb348c97df44 1106 #define ADC_SR_AWD_Pos (0U)
lypinator 0:bb348c97df44 1107 #define ADC_SR_AWD_Msk (0x1U << ADC_SR_AWD_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 1108 #define ADC_SR_AWD ADC_SR_AWD_Msk /*!<Analog watchdog flag */
lypinator 0:bb348c97df44 1109 #define ADC_SR_EOC_Pos (1U)
lypinator 0:bb348c97df44 1110 #define ADC_SR_EOC_Msk (0x1U << ADC_SR_EOC_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 1111 #define ADC_SR_EOC ADC_SR_EOC_Msk /*!<End of conversion */
lypinator 0:bb348c97df44 1112 #define ADC_SR_JEOC_Pos (2U)
lypinator 0:bb348c97df44 1113 #define ADC_SR_JEOC_Msk (0x1U << ADC_SR_JEOC_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 1114 #define ADC_SR_JEOC ADC_SR_JEOC_Msk /*!<Injected channel end of conversion */
lypinator 0:bb348c97df44 1115 #define ADC_SR_JSTRT_Pos (3U)
lypinator 0:bb348c97df44 1116 #define ADC_SR_JSTRT_Msk (0x1U << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 1117 #define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!<Injected channel Start flag */
lypinator 0:bb348c97df44 1118 #define ADC_SR_STRT_Pos (4U)
lypinator 0:bb348c97df44 1119 #define ADC_SR_STRT_Msk (0x1U << ADC_SR_STRT_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 1120 #define ADC_SR_STRT ADC_SR_STRT_Msk /*!<Regular channel Start flag */
lypinator 0:bb348c97df44 1121 #define ADC_SR_OVR_Pos (5U)
lypinator 0:bb348c97df44 1122 #define ADC_SR_OVR_Msk (0x1U << ADC_SR_OVR_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 1123 #define ADC_SR_OVR ADC_SR_OVR_Msk /*!<Overrun flag */
lypinator 0:bb348c97df44 1124
lypinator 0:bb348c97df44 1125 /******************* Bit definition for ADC_CR1 register ********************/
lypinator 0:bb348c97df44 1126 #define ADC_CR1_AWDCH_Pos (0U)
lypinator 0:bb348c97df44 1127 #define ADC_CR1_AWDCH_Msk (0x1FU << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */
lypinator 0:bb348c97df44 1128 #define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
lypinator 0:bb348c97df44 1129 #define ADC_CR1_AWDCH_0 (0x01U << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 1130 #define ADC_CR1_AWDCH_1 (0x02U << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 1131 #define ADC_CR1_AWDCH_2 (0x04U << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 1132 #define ADC_CR1_AWDCH_3 (0x08U << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 1133 #define ADC_CR1_AWDCH_4 (0x10U << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 1134 #define ADC_CR1_EOCIE_Pos (5U)
lypinator 0:bb348c97df44 1135 #define ADC_CR1_EOCIE_Msk (0x1U << ADC_CR1_EOCIE_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 1136 #define ADC_CR1_EOCIE ADC_CR1_EOCIE_Msk /*!<Interrupt enable for EOC */
lypinator 0:bb348c97df44 1137 #define ADC_CR1_AWDIE_Pos (6U)
lypinator 0:bb348c97df44 1138 #define ADC_CR1_AWDIE_Msk (0x1U << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 1139 #define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!<AAnalog Watchdog interrupt enable */
lypinator 0:bb348c97df44 1140 #define ADC_CR1_JEOCIE_Pos (7U)
lypinator 0:bb348c97df44 1141 #define ADC_CR1_JEOCIE_Msk (0x1U << ADC_CR1_JEOCIE_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 1142 #define ADC_CR1_JEOCIE ADC_CR1_JEOCIE_Msk /*!<Interrupt enable for injected channels */
lypinator 0:bb348c97df44 1143 #define ADC_CR1_SCAN_Pos (8U)
lypinator 0:bb348c97df44 1144 #define ADC_CR1_SCAN_Msk (0x1U << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 1145 #define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!<Scan mode */
lypinator 0:bb348c97df44 1146 #define ADC_CR1_AWDSGL_Pos (9U)
lypinator 0:bb348c97df44 1147 #define ADC_CR1_AWDSGL_Msk (0x1U << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 1148 #define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!<Enable the watchdog on a single channel in scan mode */
lypinator 0:bb348c97df44 1149 #define ADC_CR1_JAUTO_Pos (10U)
lypinator 0:bb348c97df44 1150 #define ADC_CR1_JAUTO_Msk (0x1U << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 1151 #define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!<Automatic injected group conversion */
lypinator 0:bb348c97df44 1152 #define ADC_CR1_DISCEN_Pos (11U)
lypinator 0:bb348c97df44 1153 #define ADC_CR1_DISCEN_Msk (0x1U << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 1154 #define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!<Discontinuous mode on regular channels */
lypinator 0:bb348c97df44 1155 #define ADC_CR1_JDISCEN_Pos (12U)
lypinator 0:bb348c97df44 1156 #define ADC_CR1_JDISCEN_Msk (0x1U << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 1157 #define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!<Discontinuous mode on injected channels */
lypinator 0:bb348c97df44 1158 #define ADC_CR1_DISCNUM_Pos (13U)
lypinator 0:bb348c97df44 1159 #define ADC_CR1_DISCNUM_Msk (0x7U << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */
lypinator 0:bb348c97df44 1160 #define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
lypinator 0:bb348c97df44 1161 #define ADC_CR1_DISCNUM_0 (0x1U << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 1162 #define ADC_CR1_DISCNUM_1 (0x2U << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 1163 #define ADC_CR1_DISCNUM_2 (0x4U << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 1164 #define ADC_CR1_JAWDEN_Pos (22U)
lypinator 0:bb348c97df44 1165 #define ADC_CR1_JAWDEN_Msk (0x1U << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 1166 #define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!<Analog watchdog enable on injected channels */
lypinator 0:bb348c97df44 1167 #define ADC_CR1_AWDEN_Pos (23U)
lypinator 0:bb348c97df44 1168 #define ADC_CR1_AWDEN_Msk (0x1U << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */
lypinator 0:bb348c97df44 1169 #define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!<Analog watchdog enable on regular channels */
lypinator 0:bb348c97df44 1170 #define ADC_CR1_RES_Pos (24U)
lypinator 0:bb348c97df44 1171 #define ADC_CR1_RES_Msk (0x3U << ADC_CR1_RES_Pos) /*!< 0x03000000 */
lypinator 0:bb348c97df44 1172 #define ADC_CR1_RES ADC_CR1_RES_Msk /*!<RES[2:0] bits (Resolution) */
lypinator 0:bb348c97df44 1173 #define ADC_CR1_RES_0 (0x1U << ADC_CR1_RES_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 1174 #define ADC_CR1_RES_1 (0x2U << ADC_CR1_RES_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 1175 #define ADC_CR1_OVRIE_Pos (26U)
lypinator 0:bb348c97df44 1176 #define ADC_CR1_OVRIE_Msk (0x1U << ADC_CR1_OVRIE_Pos) /*!< 0x04000000 */
lypinator 0:bb348c97df44 1177 #define ADC_CR1_OVRIE ADC_CR1_OVRIE_Msk /*!<overrun interrupt enable */
lypinator 0:bb348c97df44 1178
lypinator 0:bb348c97df44 1179 /******************* Bit definition for ADC_CR2 register ********************/
lypinator 0:bb348c97df44 1180 #define ADC_CR2_ADON_Pos (0U)
lypinator 0:bb348c97df44 1181 #define ADC_CR2_ADON_Msk (0x1U << ADC_CR2_ADON_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 1182 #define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!<A/D Converter ON / OFF */
lypinator 0:bb348c97df44 1183 #define ADC_CR2_CONT_Pos (1U)
lypinator 0:bb348c97df44 1184 #define ADC_CR2_CONT_Msk (0x1U << ADC_CR2_CONT_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 1185 #define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!<Continuous Conversion */
lypinator 0:bb348c97df44 1186 #define ADC_CR2_DMA_Pos (8U)
lypinator 0:bb348c97df44 1187 #define ADC_CR2_DMA_Msk (0x1U << ADC_CR2_DMA_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 1188 #define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!<Direct Memory access mode */
lypinator 0:bb348c97df44 1189 #define ADC_CR2_DDS_Pos (9U)
lypinator 0:bb348c97df44 1190 #define ADC_CR2_DDS_Msk (0x1U << ADC_CR2_DDS_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 1191 #define ADC_CR2_DDS ADC_CR2_DDS_Msk /*!<DMA disable selection (Single ADC) */
lypinator 0:bb348c97df44 1192 #define ADC_CR2_EOCS_Pos (10U)
lypinator 0:bb348c97df44 1193 #define ADC_CR2_EOCS_Msk (0x1U << ADC_CR2_EOCS_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 1194 #define ADC_CR2_EOCS ADC_CR2_EOCS_Msk /*!<End of conversion selection */
lypinator 0:bb348c97df44 1195 #define ADC_CR2_ALIGN_Pos (11U)
lypinator 0:bb348c97df44 1196 #define ADC_CR2_ALIGN_Msk (0x1U << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 1197 #define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!<Data Alignment */
lypinator 0:bb348c97df44 1198 #define ADC_CR2_JEXTSEL_Pos (16U)
lypinator 0:bb348c97df44 1199 #define ADC_CR2_JEXTSEL_Msk (0xFU << ADC_CR2_JEXTSEL_Pos) /*!< 0x000F0000 */
lypinator 0:bb348c97df44 1200 #define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!<JEXTSEL[3:0] bits (External event select for injected group) */
lypinator 0:bb348c97df44 1201 #define ADC_CR2_JEXTSEL_0 (0x1U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 1202 #define ADC_CR2_JEXTSEL_1 (0x2U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 1203 #define ADC_CR2_JEXTSEL_2 (0x4U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 1204 #define ADC_CR2_JEXTSEL_3 (0x8U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 1205 #define ADC_CR2_JEXTEN_Pos (20U)
lypinator 0:bb348c97df44 1206 #define ADC_CR2_JEXTEN_Msk (0x3U << ADC_CR2_JEXTEN_Pos) /*!< 0x00300000 */
lypinator 0:bb348c97df44 1207 #define ADC_CR2_JEXTEN ADC_CR2_JEXTEN_Msk /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
lypinator 0:bb348c97df44 1208 #define ADC_CR2_JEXTEN_0 (0x1U << ADC_CR2_JEXTEN_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 1209 #define ADC_CR2_JEXTEN_1 (0x2U << ADC_CR2_JEXTEN_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 1210 #define ADC_CR2_JSWSTART_Pos (22U)
lypinator 0:bb348c97df44 1211 #define ADC_CR2_JSWSTART_Msk (0x1U << ADC_CR2_JSWSTART_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 1212 #define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!<Start Conversion of injected channels */
lypinator 0:bb348c97df44 1213 #define ADC_CR2_EXTSEL_Pos (24U)
lypinator 0:bb348c97df44 1214 #define ADC_CR2_EXTSEL_Msk (0xFU << ADC_CR2_EXTSEL_Pos) /*!< 0x0F000000 */
lypinator 0:bb348c97df44 1215 #define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
lypinator 0:bb348c97df44 1216 #define ADC_CR2_EXTSEL_0 (0x1U << ADC_CR2_EXTSEL_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 1217 #define ADC_CR2_EXTSEL_1 (0x2U << ADC_CR2_EXTSEL_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 1218 #define ADC_CR2_EXTSEL_2 (0x4U << ADC_CR2_EXTSEL_Pos) /*!< 0x04000000 */
lypinator 0:bb348c97df44 1219 #define ADC_CR2_EXTSEL_3 (0x8U << ADC_CR2_EXTSEL_Pos) /*!< 0x08000000 */
lypinator 0:bb348c97df44 1220 #define ADC_CR2_EXTEN_Pos (28U)
lypinator 0:bb348c97df44 1221 #define ADC_CR2_EXTEN_Msk (0x3U << ADC_CR2_EXTEN_Pos) /*!< 0x30000000 */
lypinator 0:bb348c97df44 1222 #define ADC_CR2_EXTEN ADC_CR2_EXTEN_Msk /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
lypinator 0:bb348c97df44 1223 #define ADC_CR2_EXTEN_0 (0x1U << ADC_CR2_EXTEN_Pos) /*!< 0x10000000 */
lypinator 0:bb348c97df44 1224 #define ADC_CR2_EXTEN_1 (0x2U << ADC_CR2_EXTEN_Pos) /*!< 0x20000000 */
lypinator 0:bb348c97df44 1225 #define ADC_CR2_SWSTART_Pos (30U)
lypinator 0:bb348c97df44 1226 #define ADC_CR2_SWSTART_Msk (0x1U << ADC_CR2_SWSTART_Pos) /*!< 0x40000000 */
lypinator 0:bb348c97df44 1227 #define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!<Start Conversion of regular channels */
lypinator 0:bb348c97df44 1228
lypinator 0:bb348c97df44 1229 /****************** Bit definition for ADC_SMPR1 register *******************/
lypinator 0:bb348c97df44 1230 #define ADC_SMPR1_SMP10_Pos (0U)
lypinator 0:bb348c97df44 1231 #define ADC_SMPR1_SMP10_Msk (0x7U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000007 */
lypinator 0:bb348c97df44 1232 #define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
lypinator 0:bb348c97df44 1233 #define ADC_SMPR1_SMP10_0 (0x1U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 1234 #define ADC_SMPR1_SMP10_1 (0x2U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 1235 #define ADC_SMPR1_SMP10_2 (0x4U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 1236 #define ADC_SMPR1_SMP11_Pos (3U)
lypinator 0:bb348c97df44 1237 #define ADC_SMPR1_SMP11_Msk (0x7U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000038 */
lypinator 0:bb348c97df44 1238 #define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
lypinator 0:bb348c97df44 1239 #define ADC_SMPR1_SMP11_0 (0x1U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 1240 #define ADC_SMPR1_SMP11_1 (0x2U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 1241 #define ADC_SMPR1_SMP11_2 (0x4U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 1242 #define ADC_SMPR1_SMP12_Pos (6U)
lypinator 0:bb348c97df44 1243 #define ADC_SMPR1_SMP12_Msk (0x7U << ADC_SMPR1_SMP12_Pos) /*!< 0x000001C0 */
lypinator 0:bb348c97df44 1244 #define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
lypinator 0:bb348c97df44 1245 #define ADC_SMPR1_SMP12_0 (0x1U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 1246 #define ADC_SMPR1_SMP12_1 (0x2U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 1247 #define ADC_SMPR1_SMP12_2 (0x4U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 1248 #define ADC_SMPR1_SMP13_Pos (9U)
lypinator 0:bb348c97df44 1249 #define ADC_SMPR1_SMP13_Msk (0x7U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000E00 */
lypinator 0:bb348c97df44 1250 #define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
lypinator 0:bb348c97df44 1251 #define ADC_SMPR1_SMP13_0 (0x1U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 1252 #define ADC_SMPR1_SMP13_1 (0x2U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 1253 #define ADC_SMPR1_SMP13_2 (0x4U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 1254 #define ADC_SMPR1_SMP14_Pos (12U)
lypinator 0:bb348c97df44 1255 #define ADC_SMPR1_SMP14_Msk (0x7U << ADC_SMPR1_SMP14_Pos) /*!< 0x00007000 */
lypinator 0:bb348c97df44 1256 #define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
lypinator 0:bb348c97df44 1257 #define ADC_SMPR1_SMP14_0 (0x1U << ADC_SMPR1_SMP14_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 1258 #define ADC_SMPR1_SMP14_1 (0x2U << ADC_SMPR1_SMP14_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 1259 #define ADC_SMPR1_SMP14_2 (0x4U << ADC_SMPR1_SMP14_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 1260 #define ADC_SMPR1_SMP15_Pos (15U)
lypinator 0:bb348c97df44 1261 #define ADC_SMPR1_SMP15_Msk (0x7U << ADC_SMPR1_SMP15_Pos) /*!< 0x00038000 */
lypinator 0:bb348c97df44 1262 #define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
lypinator 0:bb348c97df44 1263 #define ADC_SMPR1_SMP15_0 (0x1U << ADC_SMPR1_SMP15_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 1264 #define ADC_SMPR1_SMP15_1 (0x2U << ADC_SMPR1_SMP15_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 1265 #define ADC_SMPR1_SMP15_2 (0x4U << ADC_SMPR1_SMP15_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 1266 #define ADC_SMPR1_SMP16_Pos (18U)
lypinator 0:bb348c97df44 1267 #define ADC_SMPR1_SMP16_Msk (0x7U << ADC_SMPR1_SMP16_Pos) /*!< 0x001C0000 */
lypinator 0:bb348c97df44 1268 #define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
lypinator 0:bb348c97df44 1269 #define ADC_SMPR1_SMP16_0 (0x1U << ADC_SMPR1_SMP16_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 1270 #define ADC_SMPR1_SMP16_1 (0x2U << ADC_SMPR1_SMP16_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 1271 #define ADC_SMPR1_SMP16_2 (0x4U << ADC_SMPR1_SMP16_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 1272 #define ADC_SMPR1_SMP17_Pos (21U)
lypinator 0:bb348c97df44 1273 #define ADC_SMPR1_SMP17_Msk (0x7U << ADC_SMPR1_SMP17_Pos) /*!< 0x00E00000 */
lypinator 0:bb348c97df44 1274 #define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
lypinator 0:bb348c97df44 1275 #define ADC_SMPR1_SMP17_0 (0x1U << ADC_SMPR1_SMP17_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 1276 #define ADC_SMPR1_SMP17_1 (0x2U << ADC_SMPR1_SMP17_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 1277 #define ADC_SMPR1_SMP17_2 (0x4U << ADC_SMPR1_SMP17_Pos) /*!< 0x00800000 */
lypinator 0:bb348c97df44 1278 #define ADC_SMPR1_SMP18_Pos (24U)
lypinator 0:bb348c97df44 1279 #define ADC_SMPR1_SMP18_Msk (0x7U << ADC_SMPR1_SMP18_Pos) /*!< 0x07000000 */
lypinator 0:bb348c97df44 1280 #define ADC_SMPR1_SMP18 ADC_SMPR1_SMP18_Msk /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
lypinator 0:bb348c97df44 1281 #define ADC_SMPR1_SMP18_0 (0x1U << ADC_SMPR1_SMP18_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 1282 #define ADC_SMPR1_SMP18_1 (0x2U << ADC_SMPR1_SMP18_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 1283 #define ADC_SMPR1_SMP18_2 (0x4U << ADC_SMPR1_SMP18_Pos) /*!< 0x04000000 */
lypinator 0:bb348c97df44 1284
lypinator 0:bb348c97df44 1285 /****************** Bit definition for ADC_SMPR2 register *******************/
lypinator 0:bb348c97df44 1286 #define ADC_SMPR2_SMP0_Pos (0U)
lypinator 0:bb348c97df44 1287 #define ADC_SMPR2_SMP0_Msk (0x7U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000007 */
lypinator 0:bb348c97df44 1288 #define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
lypinator 0:bb348c97df44 1289 #define ADC_SMPR2_SMP0_0 (0x1U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 1290 #define ADC_SMPR2_SMP0_1 (0x2U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 1291 #define ADC_SMPR2_SMP0_2 (0x4U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 1292 #define ADC_SMPR2_SMP1_Pos (3U)
lypinator 0:bb348c97df44 1293 #define ADC_SMPR2_SMP1_Msk (0x7U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000038 */
lypinator 0:bb348c97df44 1294 #define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
lypinator 0:bb348c97df44 1295 #define ADC_SMPR2_SMP1_0 (0x1U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 1296 #define ADC_SMPR2_SMP1_1 (0x2U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 1297 #define ADC_SMPR2_SMP1_2 (0x4U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 1298 #define ADC_SMPR2_SMP2_Pos (6U)
lypinator 0:bb348c97df44 1299 #define ADC_SMPR2_SMP2_Msk (0x7U << ADC_SMPR2_SMP2_Pos) /*!< 0x000001C0 */
lypinator 0:bb348c97df44 1300 #define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
lypinator 0:bb348c97df44 1301 #define ADC_SMPR2_SMP2_0 (0x1U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 1302 #define ADC_SMPR2_SMP2_1 (0x2U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 1303 #define ADC_SMPR2_SMP2_2 (0x4U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 1304 #define ADC_SMPR2_SMP3_Pos (9U)
lypinator 0:bb348c97df44 1305 #define ADC_SMPR2_SMP3_Msk (0x7U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000E00 */
lypinator 0:bb348c97df44 1306 #define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
lypinator 0:bb348c97df44 1307 #define ADC_SMPR2_SMP3_0 (0x1U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 1308 #define ADC_SMPR2_SMP3_1 (0x2U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 1309 #define ADC_SMPR2_SMP3_2 (0x4U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 1310 #define ADC_SMPR2_SMP4_Pos (12U)
lypinator 0:bb348c97df44 1311 #define ADC_SMPR2_SMP4_Msk (0x7U << ADC_SMPR2_SMP4_Pos) /*!< 0x00007000 */
lypinator 0:bb348c97df44 1312 #define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
lypinator 0:bb348c97df44 1313 #define ADC_SMPR2_SMP4_0 (0x1U << ADC_SMPR2_SMP4_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 1314 #define ADC_SMPR2_SMP4_1 (0x2U << ADC_SMPR2_SMP4_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 1315 #define ADC_SMPR2_SMP4_2 (0x4U << ADC_SMPR2_SMP4_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 1316 #define ADC_SMPR2_SMP5_Pos (15U)
lypinator 0:bb348c97df44 1317 #define ADC_SMPR2_SMP5_Msk (0x7U << ADC_SMPR2_SMP5_Pos) /*!< 0x00038000 */
lypinator 0:bb348c97df44 1318 #define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
lypinator 0:bb348c97df44 1319 #define ADC_SMPR2_SMP5_0 (0x1U << ADC_SMPR2_SMP5_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 1320 #define ADC_SMPR2_SMP5_1 (0x2U << ADC_SMPR2_SMP5_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 1321 #define ADC_SMPR2_SMP5_2 (0x4U << ADC_SMPR2_SMP5_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 1322 #define ADC_SMPR2_SMP6_Pos (18U)
lypinator 0:bb348c97df44 1323 #define ADC_SMPR2_SMP6_Msk (0x7U << ADC_SMPR2_SMP6_Pos) /*!< 0x001C0000 */
lypinator 0:bb348c97df44 1324 #define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
lypinator 0:bb348c97df44 1325 #define ADC_SMPR2_SMP6_0 (0x1U << ADC_SMPR2_SMP6_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 1326 #define ADC_SMPR2_SMP6_1 (0x2U << ADC_SMPR2_SMP6_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 1327 #define ADC_SMPR2_SMP6_2 (0x4U << ADC_SMPR2_SMP6_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 1328 #define ADC_SMPR2_SMP7_Pos (21U)
lypinator 0:bb348c97df44 1329 #define ADC_SMPR2_SMP7_Msk (0x7U << ADC_SMPR2_SMP7_Pos) /*!< 0x00E00000 */
lypinator 0:bb348c97df44 1330 #define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
lypinator 0:bb348c97df44 1331 #define ADC_SMPR2_SMP7_0 (0x1U << ADC_SMPR2_SMP7_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 1332 #define ADC_SMPR2_SMP7_1 (0x2U << ADC_SMPR2_SMP7_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 1333 #define ADC_SMPR2_SMP7_2 (0x4U << ADC_SMPR2_SMP7_Pos) /*!< 0x00800000 */
lypinator 0:bb348c97df44 1334 #define ADC_SMPR2_SMP8_Pos (24U)
lypinator 0:bb348c97df44 1335 #define ADC_SMPR2_SMP8_Msk (0x7U << ADC_SMPR2_SMP8_Pos) /*!< 0x07000000 */
lypinator 0:bb348c97df44 1336 #define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
lypinator 0:bb348c97df44 1337 #define ADC_SMPR2_SMP8_0 (0x1U << ADC_SMPR2_SMP8_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 1338 #define ADC_SMPR2_SMP8_1 (0x2U << ADC_SMPR2_SMP8_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 1339 #define ADC_SMPR2_SMP8_2 (0x4U << ADC_SMPR2_SMP8_Pos) /*!< 0x04000000 */
lypinator 0:bb348c97df44 1340 #define ADC_SMPR2_SMP9_Pos (27U)
lypinator 0:bb348c97df44 1341 #define ADC_SMPR2_SMP9_Msk (0x7U << ADC_SMPR2_SMP9_Pos) /*!< 0x38000000 */
lypinator 0:bb348c97df44 1342 #define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
lypinator 0:bb348c97df44 1343 #define ADC_SMPR2_SMP9_0 (0x1U << ADC_SMPR2_SMP9_Pos) /*!< 0x08000000 */
lypinator 0:bb348c97df44 1344 #define ADC_SMPR2_SMP9_1 (0x2U << ADC_SMPR2_SMP9_Pos) /*!< 0x10000000 */
lypinator 0:bb348c97df44 1345 #define ADC_SMPR2_SMP9_2 (0x4U << ADC_SMPR2_SMP9_Pos) /*!< 0x20000000 */
lypinator 0:bb348c97df44 1346
lypinator 0:bb348c97df44 1347 /****************** Bit definition for ADC_JOFR1 register *******************/
lypinator 0:bb348c97df44 1348 #define ADC_JOFR1_JOFFSET1_Pos (0U)
lypinator 0:bb348c97df44 1349 #define ADC_JOFR1_JOFFSET1_Msk (0xFFFU << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */
lypinator 0:bb348c97df44 1350 #define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!<Data offset for injected channel 1 */
lypinator 0:bb348c97df44 1351
lypinator 0:bb348c97df44 1352 /****************** Bit definition for ADC_JOFR2 register *******************/
lypinator 0:bb348c97df44 1353 #define ADC_JOFR2_JOFFSET2_Pos (0U)
lypinator 0:bb348c97df44 1354 #define ADC_JOFR2_JOFFSET2_Msk (0xFFFU << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */
lypinator 0:bb348c97df44 1355 #define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!<Data offset for injected channel 2 */
lypinator 0:bb348c97df44 1356
lypinator 0:bb348c97df44 1357 /****************** Bit definition for ADC_JOFR3 register *******************/
lypinator 0:bb348c97df44 1358 #define ADC_JOFR3_JOFFSET3_Pos (0U)
lypinator 0:bb348c97df44 1359 #define ADC_JOFR3_JOFFSET3_Msk (0xFFFU << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */
lypinator 0:bb348c97df44 1360 #define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!<Data offset for injected channel 3 */
lypinator 0:bb348c97df44 1361
lypinator 0:bb348c97df44 1362 /****************** Bit definition for ADC_JOFR4 register *******************/
lypinator 0:bb348c97df44 1363 #define ADC_JOFR4_JOFFSET4_Pos (0U)
lypinator 0:bb348c97df44 1364 #define ADC_JOFR4_JOFFSET4_Msk (0xFFFU << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */
lypinator 0:bb348c97df44 1365 #define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!<Data offset for injected channel 4 */
lypinator 0:bb348c97df44 1366
lypinator 0:bb348c97df44 1367 /******************* Bit definition for ADC_HTR register ********************/
lypinator 0:bb348c97df44 1368 #define ADC_HTR_HT_Pos (0U)
lypinator 0:bb348c97df44 1369 #define ADC_HTR_HT_Msk (0xFFFU << ADC_HTR_HT_Pos) /*!< 0x00000FFF */
lypinator 0:bb348c97df44 1370 #define ADC_HTR_HT ADC_HTR_HT_Msk /*!<Analog watchdog high threshold */
lypinator 0:bb348c97df44 1371
lypinator 0:bb348c97df44 1372 /******************* Bit definition for ADC_LTR register ********************/
lypinator 0:bb348c97df44 1373 #define ADC_LTR_LT_Pos (0U)
lypinator 0:bb348c97df44 1374 #define ADC_LTR_LT_Msk (0xFFFU << ADC_LTR_LT_Pos) /*!< 0x00000FFF */
lypinator 0:bb348c97df44 1375 #define ADC_LTR_LT ADC_LTR_LT_Msk /*!<Analog watchdog low threshold */
lypinator 0:bb348c97df44 1376
lypinator 0:bb348c97df44 1377 /******************* Bit definition for ADC_SQR1 register *******************/
lypinator 0:bb348c97df44 1378 #define ADC_SQR1_SQ13_Pos (0U)
lypinator 0:bb348c97df44 1379 #define ADC_SQR1_SQ13_Msk (0x1FU << ADC_SQR1_SQ13_Pos) /*!< 0x0000001F */
lypinator 0:bb348c97df44 1380 #define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
lypinator 0:bb348c97df44 1381 #define ADC_SQR1_SQ13_0 (0x01U << ADC_SQR1_SQ13_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 1382 #define ADC_SQR1_SQ13_1 (0x02U << ADC_SQR1_SQ13_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 1383 #define ADC_SQR1_SQ13_2 (0x04U << ADC_SQR1_SQ13_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 1384 #define ADC_SQR1_SQ13_3 (0x08U << ADC_SQR1_SQ13_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 1385 #define ADC_SQR1_SQ13_4 (0x10U << ADC_SQR1_SQ13_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 1386 #define ADC_SQR1_SQ14_Pos (5U)
lypinator 0:bb348c97df44 1387 #define ADC_SQR1_SQ14_Msk (0x1FU << ADC_SQR1_SQ14_Pos) /*!< 0x000003E0 */
lypinator 0:bb348c97df44 1388 #define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
lypinator 0:bb348c97df44 1389 #define ADC_SQR1_SQ14_0 (0x01U << ADC_SQR1_SQ14_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 1390 #define ADC_SQR1_SQ14_1 (0x02U << ADC_SQR1_SQ14_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 1391 #define ADC_SQR1_SQ14_2 (0x04U << ADC_SQR1_SQ14_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 1392 #define ADC_SQR1_SQ14_3 (0x08U << ADC_SQR1_SQ14_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 1393 #define ADC_SQR1_SQ14_4 (0x10U << ADC_SQR1_SQ14_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 1394 #define ADC_SQR1_SQ15_Pos (10U)
lypinator 0:bb348c97df44 1395 #define ADC_SQR1_SQ15_Msk (0x1FU << ADC_SQR1_SQ15_Pos) /*!< 0x00007C00 */
lypinator 0:bb348c97df44 1396 #define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
lypinator 0:bb348c97df44 1397 #define ADC_SQR1_SQ15_0 (0x01U << ADC_SQR1_SQ15_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 1398 #define ADC_SQR1_SQ15_1 (0x02U << ADC_SQR1_SQ15_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 1399 #define ADC_SQR1_SQ15_2 (0x04U << ADC_SQR1_SQ15_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 1400 #define ADC_SQR1_SQ15_3 (0x08U << ADC_SQR1_SQ15_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 1401 #define ADC_SQR1_SQ15_4 (0x10U << ADC_SQR1_SQ15_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 1402 #define ADC_SQR1_SQ16_Pos (15U)
lypinator 0:bb348c97df44 1403 #define ADC_SQR1_SQ16_Msk (0x1FU << ADC_SQR1_SQ16_Pos) /*!< 0x000F8000 */
lypinator 0:bb348c97df44 1404 #define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
lypinator 0:bb348c97df44 1405 #define ADC_SQR1_SQ16_0 (0x01U << ADC_SQR1_SQ16_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 1406 #define ADC_SQR1_SQ16_1 (0x02U << ADC_SQR1_SQ16_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 1407 #define ADC_SQR1_SQ16_2 (0x04U << ADC_SQR1_SQ16_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 1408 #define ADC_SQR1_SQ16_3 (0x08U << ADC_SQR1_SQ16_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 1409 #define ADC_SQR1_SQ16_4 (0x10U << ADC_SQR1_SQ16_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 1410 #define ADC_SQR1_L_Pos (20U)
lypinator 0:bb348c97df44 1411 #define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x00F00000 */
lypinator 0:bb348c97df44 1412 #define ADC_SQR1_L ADC_SQR1_L_Msk /*!<L[3:0] bits (Regular channel sequence length) */
lypinator 0:bb348c97df44 1413 #define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 1414 #define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 1415 #define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 1416 #define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00800000 */
lypinator 0:bb348c97df44 1417
lypinator 0:bb348c97df44 1418 /******************* Bit definition for ADC_SQR2 register *******************/
lypinator 0:bb348c97df44 1419 #define ADC_SQR2_SQ7_Pos (0U)
lypinator 0:bb348c97df44 1420 #define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0000001F */
lypinator 0:bb348c97df44 1421 #define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
lypinator 0:bb348c97df44 1422 #define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 1423 #define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 1424 #define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 1425 #define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 1426 #define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 1427 #define ADC_SQR2_SQ8_Pos (5U)
lypinator 0:bb348c97df44 1428 #define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x000003E0 */
lypinator 0:bb348c97df44 1429 #define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
lypinator 0:bb348c97df44 1430 #define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 1431 #define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 1432 #define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 1433 #define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 1434 #define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 1435 #define ADC_SQR2_SQ9_Pos (10U)
lypinator 0:bb348c97df44 1436 #define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x00007C00 */
lypinator 0:bb348c97df44 1437 #define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
lypinator 0:bb348c97df44 1438 #define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 1439 #define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 1440 #define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 1441 #define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 1442 #define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 1443 #define ADC_SQR2_SQ10_Pos (15U)
lypinator 0:bb348c97df44 1444 #define ADC_SQR2_SQ10_Msk (0x1FU << ADC_SQR2_SQ10_Pos) /*!< 0x000F8000 */
lypinator 0:bb348c97df44 1445 #define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
lypinator 0:bb348c97df44 1446 #define ADC_SQR2_SQ10_0 (0x01U << ADC_SQR2_SQ10_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 1447 #define ADC_SQR2_SQ10_1 (0x02U << ADC_SQR2_SQ10_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 1448 #define ADC_SQR2_SQ10_2 (0x04U << ADC_SQR2_SQ10_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 1449 #define ADC_SQR2_SQ10_3 (0x08U << ADC_SQR2_SQ10_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 1450 #define ADC_SQR2_SQ10_4 (0x10U << ADC_SQR2_SQ10_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 1451 #define ADC_SQR2_SQ11_Pos (20U)
lypinator 0:bb348c97df44 1452 #define ADC_SQR2_SQ11_Msk (0x1FU << ADC_SQR2_SQ11_Pos) /*!< 0x01F00000 */
lypinator 0:bb348c97df44 1453 #define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
lypinator 0:bb348c97df44 1454 #define ADC_SQR2_SQ11_0 (0x01U << ADC_SQR2_SQ11_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 1455 #define ADC_SQR2_SQ11_1 (0x02U << ADC_SQR2_SQ11_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 1456 #define ADC_SQR2_SQ11_2 (0x04U << ADC_SQR2_SQ11_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 1457 #define ADC_SQR2_SQ11_3 (0x08U << ADC_SQR2_SQ11_Pos) /*!< 0x00800000 */
lypinator 0:bb348c97df44 1458 #define ADC_SQR2_SQ11_4 (0x10U << ADC_SQR2_SQ11_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 1459 #define ADC_SQR2_SQ12_Pos (25U)
lypinator 0:bb348c97df44 1460 #define ADC_SQR2_SQ12_Msk (0x1FU << ADC_SQR2_SQ12_Pos) /*!< 0x3E000000 */
lypinator 0:bb348c97df44 1461 #define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
lypinator 0:bb348c97df44 1462 #define ADC_SQR2_SQ12_0 (0x01U << ADC_SQR2_SQ12_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 1463 #define ADC_SQR2_SQ12_1 (0x02U << ADC_SQR2_SQ12_Pos) /*!< 0x04000000 */
lypinator 0:bb348c97df44 1464 #define ADC_SQR2_SQ12_2 (0x04U << ADC_SQR2_SQ12_Pos) /*!< 0x08000000 */
lypinator 0:bb348c97df44 1465 #define ADC_SQR2_SQ12_3 (0x08U << ADC_SQR2_SQ12_Pos) /*!< 0x10000000 */
lypinator 0:bb348c97df44 1466 #define ADC_SQR2_SQ12_4 (0x10U << ADC_SQR2_SQ12_Pos) /*!< 0x20000000 */
lypinator 0:bb348c97df44 1467
lypinator 0:bb348c97df44 1468 /******************* Bit definition for ADC_SQR3 register *******************/
lypinator 0:bb348c97df44 1469 #define ADC_SQR3_SQ1_Pos (0U)
lypinator 0:bb348c97df44 1470 #define ADC_SQR3_SQ1_Msk (0x1FU << ADC_SQR3_SQ1_Pos) /*!< 0x0000001F */
lypinator 0:bb348c97df44 1471 #define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
lypinator 0:bb348c97df44 1472 #define ADC_SQR3_SQ1_0 (0x01U << ADC_SQR3_SQ1_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 1473 #define ADC_SQR3_SQ1_1 (0x02U << ADC_SQR3_SQ1_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 1474 #define ADC_SQR3_SQ1_2 (0x04U << ADC_SQR3_SQ1_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 1475 #define ADC_SQR3_SQ1_3 (0x08U << ADC_SQR3_SQ1_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 1476 #define ADC_SQR3_SQ1_4 (0x10U << ADC_SQR3_SQ1_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 1477 #define ADC_SQR3_SQ2_Pos (5U)
lypinator 0:bb348c97df44 1478 #define ADC_SQR3_SQ2_Msk (0x1FU << ADC_SQR3_SQ2_Pos) /*!< 0x000003E0 */
lypinator 0:bb348c97df44 1479 #define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
lypinator 0:bb348c97df44 1480 #define ADC_SQR3_SQ2_0 (0x01U << ADC_SQR3_SQ2_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 1481 #define ADC_SQR3_SQ2_1 (0x02U << ADC_SQR3_SQ2_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 1482 #define ADC_SQR3_SQ2_2 (0x04U << ADC_SQR3_SQ2_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 1483 #define ADC_SQR3_SQ2_3 (0x08U << ADC_SQR3_SQ2_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 1484 #define ADC_SQR3_SQ2_4 (0x10U << ADC_SQR3_SQ2_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 1485 #define ADC_SQR3_SQ3_Pos (10U)
lypinator 0:bb348c97df44 1486 #define ADC_SQR3_SQ3_Msk (0x1FU << ADC_SQR3_SQ3_Pos) /*!< 0x00007C00 */
lypinator 0:bb348c97df44 1487 #define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
lypinator 0:bb348c97df44 1488 #define ADC_SQR3_SQ3_0 (0x01U << ADC_SQR3_SQ3_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 1489 #define ADC_SQR3_SQ3_1 (0x02U << ADC_SQR3_SQ3_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 1490 #define ADC_SQR3_SQ3_2 (0x04U << ADC_SQR3_SQ3_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 1491 #define ADC_SQR3_SQ3_3 (0x08U << ADC_SQR3_SQ3_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 1492 #define ADC_SQR3_SQ3_4 (0x10U << ADC_SQR3_SQ3_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 1493 #define ADC_SQR3_SQ4_Pos (15U)
lypinator 0:bb348c97df44 1494 #define ADC_SQR3_SQ4_Msk (0x1FU << ADC_SQR3_SQ4_Pos) /*!< 0x000F8000 */
lypinator 0:bb348c97df44 1495 #define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
lypinator 0:bb348c97df44 1496 #define ADC_SQR3_SQ4_0 (0x01U << ADC_SQR3_SQ4_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 1497 #define ADC_SQR3_SQ4_1 (0x02U << ADC_SQR3_SQ4_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 1498 #define ADC_SQR3_SQ4_2 (0x04U << ADC_SQR3_SQ4_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 1499 #define ADC_SQR3_SQ4_3 (0x08U << ADC_SQR3_SQ4_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 1500 #define ADC_SQR3_SQ4_4 (0x10U << ADC_SQR3_SQ4_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 1501 #define ADC_SQR3_SQ5_Pos (20U)
lypinator 0:bb348c97df44 1502 #define ADC_SQR3_SQ5_Msk (0x1FU << ADC_SQR3_SQ5_Pos) /*!< 0x01F00000 */
lypinator 0:bb348c97df44 1503 #define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
lypinator 0:bb348c97df44 1504 #define ADC_SQR3_SQ5_0 (0x01U << ADC_SQR3_SQ5_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 1505 #define ADC_SQR3_SQ5_1 (0x02U << ADC_SQR3_SQ5_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 1506 #define ADC_SQR3_SQ5_2 (0x04U << ADC_SQR3_SQ5_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 1507 #define ADC_SQR3_SQ5_3 (0x08U << ADC_SQR3_SQ5_Pos) /*!< 0x00800000 */
lypinator 0:bb348c97df44 1508 #define ADC_SQR3_SQ5_4 (0x10U << ADC_SQR3_SQ5_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 1509 #define ADC_SQR3_SQ6_Pos (25U)
lypinator 0:bb348c97df44 1510 #define ADC_SQR3_SQ6_Msk (0x1FU << ADC_SQR3_SQ6_Pos) /*!< 0x3E000000 */
lypinator 0:bb348c97df44 1511 #define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
lypinator 0:bb348c97df44 1512 #define ADC_SQR3_SQ6_0 (0x01U << ADC_SQR3_SQ6_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 1513 #define ADC_SQR3_SQ6_1 (0x02U << ADC_SQR3_SQ6_Pos) /*!< 0x04000000 */
lypinator 0:bb348c97df44 1514 #define ADC_SQR3_SQ6_2 (0x04U << ADC_SQR3_SQ6_Pos) /*!< 0x08000000 */
lypinator 0:bb348c97df44 1515 #define ADC_SQR3_SQ6_3 (0x08U << ADC_SQR3_SQ6_Pos) /*!< 0x10000000 */
lypinator 0:bb348c97df44 1516 #define ADC_SQR3_SQ6_4 (0x10U << ADC_SQR3_SQ6_Pos) /*!< 0x20000000 */
lypinator 0:bb348c97df44 1517
lypinator 0:bb348c97df44 1518 /******************* Bit definition for ADC_JSQR register *******************/
lypinator 0:bb348c97df44 1519 #define ADC_JSQR_JSQ1_Pos (0U)
lypinator 0:bb348c97df44 1520 #define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */
lypinator 0:bb348c97df44 1521 #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
lypinator 0:bb348c97df44 1522 #define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 1523 #define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 1524 #define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 1525 #define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 1526 #define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 1527 #define ADC_JSQR_JSQ2_Pos (5U)
lypinator 0:bb348c97df44 1528 #define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */
lypinator 0:bb348c97df44 1529 #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
lypinator 0:bb348c97df44 1530 #define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 1531 #define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 1532 #define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 1533 #define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 1534 #define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 1535 #define ADC_JSQR_JSQ3_Pos (10U)
lypinator 0:bb348c97df44 1536 #define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */
lypinator 0:bb348c97df44 1537 #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
lypinator 0:bb348c97df44 1538 #define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 1539 #define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 1540 #define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 1541 #define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 1542 #define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 1543 #define ADC_JSQR_JSQ4_Pos (15U)
lypinator 0:bb348c97df44 1544 #define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */
lypinator 0:bb348c97df44 1545 #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
lypinator 0:bb348c97df44 1546 #define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 1547 #define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 1548 #define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 1549 #define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 1550 #define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 1551 #define ADC_JSQR_JL_Pos (20U)
lypinator 0:bb348c97df44 1552 #define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00300000 */
lypinator 0:bb348c97df44 1553 #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!<JL[1:0] bits (Injected Sequence length) */
lypinator 0:bb348c97df44 1554 #define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 1555 #define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 1556
lypinator 0:bb348c97df44 1557 /******************* Bit definition for ADC_JDR1 register *******************/
lypinator 0:bb348c97df44 1558 #define ADC_JDR1_JDATA_Pos (0U)
lypinator 0:bb348c97df44 1559 #define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */
lypinator 0:bb348c97df44 1560 #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!<Injected data */
lypinator 0:bb348c97df44 1561
lypinator 0:bb348c97df44 1562 /******************* Bit definition for ADC_JDR2 register *******************/
lypinator 0:bb348c97df44 1563 #define ADC_JDR2_JDATA_Pos (0U)
lypinator 0:bb348c97df44 1564 #define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */
lypinator 0:bb348c97df44 1565 #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!<Injected data */
lypinator 0:bb348c97df44 1566
lypinator 0:bb348c97df44 1567 /******************* Bit definition for ADC_JDR3 register *******************/
lypinator 0:bb348c97df44 1568 #define ADC_JDR3_JDATA_Pos (0U)
lypinator 0:bb348c97df44 1569 #define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */
lypinator 0:bb348c97df44 1570 #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!<Injected data */
lypinator 0:bb348c97df44 1571
lypinator 0:bb348c97df44 1572 /******************* Bit definition for ADC_JDR4 register *******************/
lypinator 0:bb348c97df44 1573 #define ADC_JDR4_JDATA_Pos (0U)
lypinator 0:bb348c97df44 1574 #define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */
lypinator 0:bb348c97df44 1575 #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!<Injected data */
lypinator 0:bb348c97df44 1576
lypinator 0:bb348c97df44 1577 /******************** Bit definition for ADC_DR register ********************/
lypinator 0:bb348c97df44 1578 #define ADC_DR_DATA_Pos (0U)
lypinator 0:bb348c97df44 1579 #define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
lypinator 0:bb348c97df44 1580 #define ADC_DR_DATA ADC_DR_DATA_Msk /*!<Regular data */
lypinator 0:bb348c97df44 1581 #define ADC_DR_ADC2DATA_Pos (16U)
lypinator 0:bb348c97df44 1582 #define ADC_DR_ADC2DATA_Msk (0xFFFFU << ADC_DR_ADC2DATA_Pos) /*!< 0xFFFF0000 */
lypinator 0:bb348c97df44 1583 #define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk /*!<ADC2 data */
lypinator 0:bb348c97df44 1584
lypinator 0:bb348c97df44 1585 /******************* Bit definition for ADC_CSR register ********************/
lypinator 0:bb348c97df44 1586 #define ADC_CSR_AWD1_Pos (0U)
lypinator 0:bb348c97df44 1587 #define ADC_CSR_AWD1_Msk (0x1U << ADC_CSR_AWD1_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 1588 #define ADC_CSR_AWD1 ADC_CSR_AWD1_Msk /*!<ADC1 Analog watchdog flag */
lypinator 0:bb348c97df44 1589 #define ADC_CSR_EOC1_Pos (1U)
lypinator 0:bb348c97df44 1590 #define ADC_CSR_EOC1_Msk (0x1U << ADC_CSR_EOC1_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 1591 #define ADC_CSR_EOC1 ADC_CSR_EOC1_Msk /*!<ADC1 End of conversion */
lypinator 0:bb348c97df44 1592 #define ADC_CSR_JEOC1_Pos (2U)
lypinator 0:bb348c97df44 1593 #define ADC_CSR_JEOC1_Msk (0x1U << ADC_CSR_JEOC1_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 1594 #define ADC_CSR_JEOC1 ADC_CSR_JEOC1_Msk /*!<ADC1 Injected channel end of conversion */
lypinator 0:bb348c97df44 1595 #define ADC_CSR_JSTRT1_Pos (3U)
lypinator 0:bb348c97df44 1596 #define ADC_CSR_JSTRT1_Msk (0x1U << ADC_CSR_JSTRT1_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 1597 #define ADC_CSR_JSTRT1 ADC_CSR_JSTRT1_Msk /*!<ADC1 Injected channel Start flag */
lypinator 0:bb348c97df44 1598 #define ADC_CSR_STRT1_Pos (4U)
lypinator 0:bb348c97df44 1599 #define ADC_CSR_STRT1_Msk (0x1U << ADC_CSR_STRT1_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 1600 #define ADC_CSR_STRT1 ADC_CSR_STRT1_Msk /*!<ADC1 Regular channel Start flag */
lypinator 0:bb348c97df44 1601 #define ADC_CSR_OVR1_Pos (5U)
lypinator 0:bb348c97df44 1602 #define ADC_CSR_OVR1_Msk (0x1U << ADC_CSR_OVR1_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 1603 #define ADC_CSR_OVR1 ADC_CSR_OVR1_Msk /*!<ADC1 DMA overrun flag */
lypinator 0:bb348c97df44 1604
lypinator 0:bb348c97df44 1605 /* Legacy defines */
lypinator 0:bb348c97df44 1606 #define ADC_CSR_DOVR1 ADC_CSR_OVR1
lypinator 0:bb348c97df44 1607
lypinator 0:bb348c97df44 1608 /******************* Bit definition for ADC_CCR register ********************/
lypinator 0:bb348c97df44 1609 #define ADC_CCR_MULTI_Pos (0U)
lypinator 0:bb348c97df44 1610 #define ADC_CCR_MULTI_Msk (0x1FU << ADC_CCR_MULTI_Pos) /*!< 0x0000001F */
lypinator 0:bb348c97df44 1611 #define ADC_CCR_MULTI ADC_CCR_MULTI_Msk /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
lypinator 0:bb348c97df44 1612 #define ADC_CCR_MULTI_0 (0x01U << ADC_CCR_MULTI_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 1613 #define ADC_CCR_MULTI_1 (0x02U << ADC_CCR_MULTI_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 1614 #define ADC_CCR_MULTI_2 (0x04U << ADC_CCR_MULTI_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 1615 #define ADC_CCR_MULTI_3 (0x08U << ADC_CCR_MULTI_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 1616 #define ADC_CCR_MULTI_4 (0x10U << ADC_CCR_MULTI_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 1617 #define ADC_CCR_DELAY_Pos (8U)
lypinator 0:bb348c97df44 1618 #define ADC_CCR_DELAY_Msk (0xFU << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */
lypinator 0:bb348c97df44 1619 #define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
lypinator 0:bb348c97df44 1620 #define ADC_CCR_DELAY_0 (0x1U << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 1621 #define ADC_CCR_DELAY_1 (0x2U << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 1622 #define ADC_CCR_DELAY_2 (0x4U << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 1623 #define ADC_CCR_DELAY_3 (0x8U << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 1624 #define ADC_CCR_DDS_Pos (13U)
lypinator 0:bb348c97df44 1625 #define ADC_CCR_DDS_Msk (0x1U << ADC_CCR_DDS_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 1626 #define ADC_CCR_DDS ADC_CCR_DDS_Msk /*!<DMA disable selection (Multi-ADC mode) */
lypinator 0:bb348c97df44 1627 #define ADC_CCR_DMA_Pos (14U)
lypinator 0:bb348c97df44 1628 #define ADC_CCR_DMA_Msk (0x3U << ADC_CCR_DMA_Pos) /*!< 0x0000C000 */
lypinator 0:bb348c97df44 1629 #define ADC_CCR_DMA ADC_CCR_DMA_Msk /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
lypinator 0:bb348c97df44 1630 #define ADC_CCR_DMA_0 (0x1U << ADC_CCR_DMA_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 1631 #define ADC_CCR_DMA_1 (0x2U << ADC_CCR_DMA_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 1632 #define ADC_CCR_ADCPRE_Pos (16U)
lypinator 0:bb348c97df44 1633 #define ADC_CCR_ADCPRE_Msk (0x3U << ADC_CCR_ADCPRE_Pos) /*!< 0x00030000 */
lypinator 0:bb348c97df44 1634 #define ADC_CCR_ADCPRE ADC_CCR_ADCPRE_Msk /*!<ADCPRE[1:0] bits (ADC prescaler) */
lypinator 0:bb348c97df44 1635 #define ADC_CCR_ADCPRE_0 (0x1U << ADC_CCR_ADCPRE_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 1636 #define ADC_CCR_ADCPRE_1 (0x2U << ADC_CCR_ADCPRE_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 1637 #define ADC_CCR_VBATE_Pos (22U)
lypinator 0:bb348c97df44 1638 #define ADC_CCR_VBATE_Msk (0x1U << ADC_CCR_VBATE_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 1639 #define ADC_CCR_VBATE ADC_CCR_VBATE_Msk /*!<VBAT Enable */
lypinator 0:bb348c97df44 1640 #define ADC_CCR_TSVREFE_Pos (23U)
lypinator 0:bb348c97df44 1641 #define ADC_CCR_TSVREFE_Msk (0x1U << ADC_CCR_TSVREFE_Pos) /*!< 0x00800000 */
lypinator 0:bb348c97df44 1642 #define ADC_CCR_TSVREFE ADC_CCR_TSVREFE_Msk /*!<Temperature Sensor and VREFINT Enable */
lypinator 0:bb348c97df44 1643
lypinator 0:bb348c97df44 1644 /******************* Bit definition for ADC_CDR register ********************/
lypinator 0:bb348c97df44 1645 #define ADC_CDR_DATA1_Pos (0U)
lypinator 0:bb348c97df44 1646 #define ADC_CDR_DATA1_Msk (0xFFFFU << ADC_CDR_DATA1_Pos) /*!< 0x0000FFFF */
lypinator 0:bb348c97df44 1647 #define ADC_CDR_DATA1 ADC_CDR_DATA1_Msk /*!<1st data of a pair of regular conversions */
lypinator 0:bb348c97df44 1648 #define ADC_CDR_DATA2_Pos (16U)
lypinator 0:bb348c97df44 1649 #define ADC_CDR_DATA2_Msk (0xFFFFU << ADC_CDR_DATA2_Pos) /*!< 0xFFFF0000 */
lypinator 0:bb348c97df44 1650 #define ADC_CDR_DATA2 ADC_CDR_DATA2_Msk /*!<2nd data of a pair of regular conversions */
lypinator 0:bb348c97df44 1651
lypinator 0:bb348c97df44 1652 /* Legacy defines */
lypinator 0:bb348c97df44 1653 #define ADC_CDR_RDATA_MST ADC_CDR_DATA1
lypinator 0:bb348c97df44 1654 #define ADC_CDR_RDATA_SLV ADC_CDR_DATA2
lypinator 0:bb348c97df44 1655
lypinator 0:bb348c97df44 1656 /******************************************************************************/
lypinator 0:bb348c97df44 1657 /* */
lypinator 0:bb348c97df44 1658 /* Controller Area Network */
lypinator 0:bb348c97df44 1659 /* */
lypinator 0:bb348c97df44 1660 /******************************************************************************/
lypinator 0:bb348c97df44 1661 /*!<CAN control and status registers */
lypinator 0:bb348c97df44 1662 /******************* Bit definition for CAN_MCR register ********************/
lypinator 0:bb348c97df44 1663 #define CAN_MCR_INRQ_Pos (0U)
lypinator 0:bb348c97df44 1664 #define CAN_MCR_INRQ_Msk (0x1U << CAN_MCR_INRQ_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 1665 #define CAN_MCR_INRQ CAN_MCR_INRQ_Msk /*!<Initialization Request */
lypinator 0:bb348c97df44 1666 #define CAN_MCR_SLEEP_Pos (1U)
lypinator 0:bb348c97df44 1667 #define CAN_MCR_SLEEP_Msk (0x1U << CAN_MCR_SLEEP_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 1668 #define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk /*!<Sleep Mode Request */
lypinator 0:bb348c97df44 1669 #define CAN_MCR_TXFP_Pos (2U)
lypinator 0:bb348c97df44 1670 #define CAN_MCR_TXFP_Msk (0x1U << CAN_MCR_TXFP_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 1671 #define CAN_MCR_TXFP CAN_MCR_TXFP_Msk /*!<Transmit FIFO Priority */
lypinator 0:bb348c97df44 1672 #define CAN_MCR_RFLM_Pos (3U)
lypinator 0:bb348c97df44 1673 #define CAN_MCR_RFLM_Msk (0x1U << CAN_MCR_RFLM_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 1674 #define CAN_MCR_RFLM CAN_MCR_RFLM_Msk /*!<Receive FIFO Locked Mode */
lypinator 0:bb348c97df44 1675 #define CAN_MCR_NART_Pos (4U)
lypinator 0:bb348c97df44 1676 #define CAN_MCR_NART_Msk (0x1U << CAN_MCR_NART_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 1677 #define CAN_MCR_NART CAN_MCR_NART_Msk /*!<No Automatic Retransmission */
lypinator 0:bb348c97df44 1678 #define CAN_MCR_AWUM_Pos (5U)
lypinator 0:bb348c97df44 1679 #define CAN_MCR_AWUM_Msk (0x1U << CAN_MCR_AWUM_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 1680 #define CAN_MCR_AWUM CAN_MCR_AWUM_Msk /*!<Automatic Wakeup Mode */
lypinator 0:bb348c97df44 1681 #define CAN_MCR_ABOM_Pos (6U)
lypinator 0:bb348c97df44 1682 #define CAN_MCR_ABOM_Msk (0x1U << CAN_MCR_ABOM_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 1683 #define CAN_MCR_ABOM CAN_MCR_ABOM_Msk /*!<Automatic Bus-Off Management */
lypinator 0:bb348c97df44 1684 #define CAN_MCR_TTCM_Pos (7U)
lypinator 0:bb348c97df44 1685 #define CAN_MCR_TTCM_Msk (0x1U << CAN_MCR_TTCM_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 1686 #define CAN_MCR_TTCM CAN_MCR_TTCM_Msk /*!<Time Triggered Communication Mode */
lypinator 0:bb348c97df44 1687 #define CAN_MCR_RESET_Pos (15U)
lypinator 0:bb348c97df44 1688 #define CAN_MCR_RESET_Msk (0x1U << CAN_MCR_RESET_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 1689 #define CAN_MCR_RESET CAN_MCR_RESET_Msk /*!<bxCAN software master reset */
lypinator 0:bb348c97df44 1690 #define CAN_MCR_DBF_Pos (16U)
lypinator 0:bb348c97df44 1691 #define CAN_MCR_DBF_Msk (0x1U << CAN_MCR_DBF_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 1692 #define CAN_MCR_DBF CAN_MCR_DBF_Msk /*!<bxCAN Debug freeze */
lypinator 0:bb348c97df44 1693 /******************* Bit definition for CAN_MSR register ********************/
lypinator 0:bb348c97df44 1694 #define CAN_MSR_INAK_Pos (0U)
lypinator 0:bb348c97df44 1695 #define CAN_MSR_INAK_Msk (0x1U << CAN_MSR_INAK_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 1696 #define CAN_MSR_INAK CAN_MSR_INAK_Msk /*!<Initialization Acknowledge */
lypinator 0:bb348c97df44 1697 #define CAN_MSR_SLAK_Pos (1U)
lypinator 0:bb348c97df44 1698 #define CAN_MSR_SLAK_Msk (0x1U << CAN_MSR_SLAK_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 1699 #define CAN_MSR_SLAK CAN_MSR_SLAK_Msk /*!<Sleep Acknowledge */
lypinator 0:bb348c97df44 1700 #define CAN_MSR_ERRI_Pos (2U)
lypinator 0:bb348c97df44 1701 #define CAN_MSR_ERRI_Msk (0x1U << CAN_MSR_ERRI_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 1702 #define CAN_MSR_ERRI CAN_MSR_ERRI_Msk /*!<Error Interrupt */
lypinator 0:bb348c97df44 1703 #define CAN_MSR_WKUI_Pos (3U)
lypinator 0:bb348c97df44 1704 #define CAN_MSR_WKUI_Msk (0x1U << CAN_MSR_WKUI_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 1705 #define CAN_MSR_WKUI CAN_MSR_WKUI_Msk /*!<Wakeup Interrupt */
lypinator 0:bb348c97df44 1706 #define CAN_MSR_SLAKI_Pos (4U)
lypinator 0:bb348c97df44 1707 #define CAN_MSR_SLAKI_Msk (0x1U << CAN_MSR_SLAKI_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 1708 #define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk /*!<Sleep Acknowledge Interrupt */
lypinator 0:bb348c97df44 1709 #define CAN_MSR_TXM_Pos (8U)
lypinator 0:bb348c97df44 1710 #define CAN_MSR_TXM_Msk (0x1U << CAN_MSR_TXM_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 1711 #define CAN_MSR_TXM CAN_MSR_TXM_Msk /*!<Transmit Mode */
lypinator 0:bb348c97df44 1712 #define CAN_MSR_RXM_Pos (9U)
lypinator 0:bb348c97df44 1713 #define CAN_MSR_RXM_Msk (0x1U << CAN_MSR_RXM_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 1714 #define CAN_MSR_RXM CAN_MSR_RXM_Msk /*!<Receive Mode */
lypinator 0:bb348c97df44 1715 #define CAN_MSR_SAMP_Pos (10U)
lypinator 0:bb348c97df44 1716 #define CAN_MSR_SAMP_Msk (0x1U << CAN_MSR_SAMP_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 1717 #define CAN_MSR_SAMP CAN_MSR_SAMP_Msk /*!<Last Sample Point */
lypinator 0:bb348c97df44 1718 #define CAN_MSR_RX_Pos (11U)
lypinator 0:bb348c97df44 1719 #define CAN_MSR_RX_Msk (0x1U << CAN_MSR_RX_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 1720 #define CAN_MSR_RX CAN_MSR_RX_Msk /*!<CAN Rx Signal */
lypinator 0:bb348c97df44 1721
lypinator 0:bb348c97df44 1722 /******************* Bit definition for CAN_TSR register ********************/
lypinator 0:bb348c97df44 1723 #define CAN_TSR_RQCP0_Pos (0U)
lypinator 0:bb348c97df44 1724 #define CAN_TSR_RQCP0_Msk (0x1U << CAN_TSR_RQCP0_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 1725 #define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk /*!<Request Completed Mailbox0 */
lypinator 0:bb348c97df44 1726 #define CAN_TSR_TXOK0_Pos (1U)
lypinator 0:bb348c97df44 1727 #define CAN_TSR_TXOK0_Msk (0x1U << CAN_TSR_TXOK0_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 1728 #define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk /*!<Transmission OK of Mailbox0 */
lypinator 0:bb348c97df44 1729 #define CAN_TSR_ALST0_Pos (2U)
lypinator 0:bb348c97df44 1730 #define CAN_TSR_ALST0_Msk (0x1U << CAN_TSR_ALST0_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 1731 #define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk /*!<Arbitration Lost for Mailbox0 */
lypinator 0:bb348c97df44 1732 #define CAN_TSR_TERR0_Pos (3U)
lypinator 0:bb348c97df44 1733 #define CAN_TSR_TERR0_Msk (0x1U << CAN_TSR_TERR0_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 1734 #define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk /*!<Transmission Error of Mailbox0 */
lypinator 0:bb348c97df44 1735 #define CAN_TSR_ABRQ0_Pos (7U)
lypinator 0:bb348c97df44 1736 #define CAN_TSR_ABRQ0_Msk (0x1U << CAN_TSR_ABRQ0_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 1737 #define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk /*!<Abort Request for Mailbox0 */
lypinator 0:bb348c97df44 1738 #define CAN_TSR_RQCP1_Pos (8U)
lypinator 0:bb348c97df44 1739 #define CAN_TSR_RQCP1_Msk (0x1U << CAN_TSR_RQCP1_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 1740 #define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk /*!<Request Completed Mailbox1 */
lypinator 0:bb348c97df44 1741 #define CAN_TSR_TXOK1_Pos (9U)
lypinator 0:bb348c97df44 1742 #define CAN_TSR_TXOK1_Msk (0x1U << CAN_TSR_TXOK1_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 1743 #define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk /*!<Transmission OK of Mailbox1 */
lypinator 0:bb348c97df44 1744 #define CAN_TSR_ALST1_Pos (10U)
lypinator 0:bb348c97df44 1745 #define CAN_TSR_ALST1_Msk (0x1U << CAN_TSR_ALST1_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 1746 #define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk /*!<Arbitration Lost for Mailbox1 */
lypinator 0:bb348c97df44 1747 #define CAN_TSR_TERR1_Pos (11U)
lypinator 0:bb348c97df44 1748 #define CAN_TSR_TERR1_Msk (0x1U << CAN_TSR_TERR1_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 1749 #define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk /*!<Transmission Error of Mailbox1 */
lypinator 0:bb348c97df44 1750 #define CAN_TSR_ABRQ1_Pos (15U)
lypinator 0:bb348c97df44 1751 #define CAN_TSR_ABRQ1_Msk (0x1U << CAN_TSR_ABRQ1_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 1752 #define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk /*!<Abort Request for Mailbox 1 */
lypinator 0:bb348c97df44 1753 #define CAN_TSR_RQCP2_Pos (16U)
lypinator 0:bb348c97df44 1754 #define CAN_TSR_RQCP2_Msk (0x1U << CAN_TSR_RQCP2_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 1755 #define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk /*!<Request Completed Mailbox2 */
lypinator 0:bb348c97df44 1756 #define CAN_TSR_TXOK2_Pos (17U)
lypinator 0:bb348c97df44 1757 #define CAN_TSR_TXOK2_Msk (0x1U << CAN_TSR_TXOK2_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 1758 #define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk /*!<Transmission OK of Mailbox 2 */
lypinator 0:bb348c97df44 1759 #define CAN_TSR_ALST2_Pos (18U)
lypinator 0:bb348c97df44 1760 #define CAN_TSR_ALST2_Msk (0x1U << CAN_TSR_ALST2_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 1761 #define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk /*!<Arbitration Lost for mailbox 2 */
lypinator 0:bb348c97df44 1762 #define CAN_TSR_TERR2_Pos (19U)
lypinator 0:bb348c97df44 1763 #define CAN_TSR_TERR2_Msk (0x1U << CAN_TSR_TERR2_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 1764 #define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk /*!<Transmission Error of Mailbox 2 */
lypinator 0:bb348c97df44 1765 #define CAN_TSR_ABRQ2_Pos (23U)
lypinator 0:bb348c97df44 1766 #define CAN_TSR_ABRQ2_Msk (0x1U << CAN_TSR_ABRQ2_Pos) /*!< 0x00800000 */
lypinator 0:bb348c97df44 1767 #define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk /*!<Abort Request for Mailbox 2 */
lypinator 0:bb348c97df44 1768 #define CAN_TSR_CODE_Pos (24U)
lypinator 0:bb348c97df44 1769 #define CAN_TSR_CODE_Msk (0x3U << CAN_TSR_CODE_Pos) /*!< 0x03000000 */
lypinator 0:bb348c97df44 1770 #define CAN_TSR_CODE CAN_TSR_CODE_Msk /*!<Mailbox Code */
lypinator 0:bb348c97df44 1771
lypinator 0:bb348c97df44 1772 #define CAN_TSR_TME_Pos (26U)
lypinator 0:bb348c97df44 1773 #define CAN_TSR_TME_Msk (0x7U << CAN_TSR_TME_Pos) /*!< 0x1C000000 */
lypinator 0:bb348c97df44 1774 #define CAN_TSR_TME CAN_TSR_TME_Msk /*!<TME[2:0] bits */
lypinator 0:bb348c97df44 1775 #define CAN_TSR_TME0_Pos (26U)
lypinator 0:bb348c97df44 1776 #define CAN_TSR_TME0_Msk (0x1U << CAN_TSR_TME0_Pos) /*!< 0x04000000 */
lypinator 0:bb348c97df44 1777 #define CAN_TSR_TME0 CAN_TSR_TME0_Msk /*!<Transmit Mailbox 0 Empty */
lypinator 0:bb348c97df44 1778 #define CAN_TSR_TME1_Pos (27U)
lypinator 0:bb348c97df44 1779 #define CAN_TSR_TME1_Msk (0x1U << CAN_TSR_TME1_Pos) /*!< 0x08000000 */
lypinator 0:bb348c97df44 1780 #define CAN_TSR_TME1 CAN_TSR_TME1_Msk /*!<Transmit Mailbox 1 Empty */
lypinator 0:bb348c97df44 1781 #define CAN_TSR_TME2_Pos (28U)
lypinator 0:bb348c97df44 1782 #define CAN_TSR_TME2_Msk (0x1U << CAN_TSR_TME2_Pos) /*!< 0x10000000 */
lypinator 0:bb348c97df44 1783 #define CAN_TSR_TME2 CAN_TSR_TME2_Msk /*!<Transmit Mailbox 2 Empty */
lypinator 0:bb348c97df44 1784
lypinator 0:bb348c97df44 1785 #define CAN_TSR_LOW_Pos (29U)
lypinator 0:bb348c97df44 1786 #define CAN_TSR_LOW_Msk (0x7U << CAN_TSR_LOW_Pos) /*!< 0xE0000000 */
lypinator 0:bb348c97df44 1787 #define CAN_TSR_LOW CAN_TSR_LOW_Msk /*!<LOW[2:0] bits */
lypinator 0:bb348c97df44 1788 #define CAN_TSR_LOW0_Pos (29U)
lypinator 0:bb348c97df44 1789 #define CAN_TSR_LOW0_Msk (0x1U << CAN_TSR_LOW0_Pos) /*!< 0x20000000 */
lypinator 0:bb348c97df44 1790 #define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk /*!<Lowest Priority Flag for Mailbox 0 */
lypinator 0:bb348c97df44 1791 #define CAN_TSR_LOW1_Pos (30U)
lypinator 0:bb348c97df44 1792 #define CAN_TSR_LOW1_Msk (0x1U << CAN_TSR_LOW1_Pos) /*!< 0x40000000 */
lypinator 0:bb348c97df44 1793 #define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk /*!<Lowest Priority Flag for Mailbox 1 */
lypinator 0:bb348c97df44 1794 #define CAN_TSR_LOW2_Pos (31U)
lypinator 0:bb348c97df44 1795 #define CAN_TSR_LOW2_Msk (0x1U << CAN_TSR_LOW2_Pos) /*!< 0x80000000 */
lypinator 0:bb348c97df44 1796 #define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk /*!<Lowest Priority Flag for Mailbox 2 */
lypinator 0:bb348c97df44 1797
lypinator 0:bb348c97df44 1798 /******************* Bit definition for CAN_RF0R register *******************/
lypinator 0:bb348c97df44 1799 #define CAN_RF0R_FMP0_Pos (0U)
lypinator 0:bb348c97df44 1800 #define CAN_RF0R_FMP0_Msk (0x3U << CAN_RF0R_FMP0_Pos) /*!< 0x00000003 */
lypinator 0:bb348c97df44 1801 #define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk /*!<FIFO 0 Message Pending */
lypinator 0:bb348c97df44 1802 #define CAN_RF0R_FULL0_Pos (3U)
lypinator 0:bb348c97df44 1803 #define CAN_RF0R_FULL0_Msk (0x1U << CAN_RF0R_FULL0_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 1804 #define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk /*!<FIFO 0 Full */
lypinator 0:bb348c97df44 1805 #define CAN_RF0R_FOVR0_Pos (4U)
lypinator 0:bb348c97df44 1806 #define CAN_RF0R_FOVR0_Msk (0x1U << CAN_RF0R_FOVR0_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 1807 #define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk /*!<FIFO 0 Overrun */
lypinator 0:bb348c97df44 1808 #define CAN_RF0R_RFOM0_Pos (5U)
lypinator 0:bb348c97df44 1809 #define CAN_RF0R_RFOM0_Msk (0x1U << CAN_RF0R_RFOM0_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 1810 #define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk /*!<Release FIFO 0 Output Mailbox */
lypinator 0:bb348c97df44 1811
lypinator 0:bb348c97df44 1812 /******************* Bit definition for CAN_RF1R register *******************/
lypinator 0:bb348c97df44 1813 #define CAN_RF1R_FMP1_Pos (0U)
lypinator 0:bb348c97df44 1814 #define CAN_RF1R_FMP1_Msk (0x3U << CAN_RF1R_FMP1_Pos) /*!< 0x00000003 */
lypinator 0:bb348c97df44 1815 #define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk /*!<FIFO 1 Message Pending */
lypinator 0:bb348c97df44 1816 #define CAN_RF1R_FULL1_Pos (3U)
lypinator 0:bb348c97df44 1817 #define CAN_RF1R_FULL1_Msk (0x1U << CAN_RF1R_FULL1_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 1818 #define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk /*!<FIFO 1 Full */
lypinator 0:bb348c97df44 1819 #define CAN_RF1R_FOVR1_Pos (4U)
lypinator 0:bb348c97df44 1820 #define CAN_RF1R_FOVR1_Msk (0x1U << CAN_RF1R_FOVR1_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 1821 #define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk /*!<FIFO 1 Overrun */
lypinator 0:bb348c97df44 1822 #define CAN_RF1R_RFOM1_Pos (5U)
lypinator 0:bb348c97df44 1823 #define CAN_RF1R_RFOM1_Msk (0x1U << CAN_RF1R_RFOM1_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 1824 #define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk /*!<Release FIFO 1 Output Mailbox */
lypinator 0:bb348c97df44 1825
lypinator 0:bb348c97df44 1826 /******************** Bit definition for CAN_IER register *******************/
lypinator 0:bb348c97df44 1827 #define CAN_IER_TMEIE_Pos (0U)
lypinator 0:bb348c97df44 1828 #define CAN_IER_TMEIE_Msk (0x1U << CAN_IER_TMEIE_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 1829 #define CAN_IER_TMEIE CAN_IER_TMEIE_Msk /*!<Transmit Mailbox Empty Interrupt Enable */
lypinator 0:bb348c97df44 1830 #define CAN_IER_FMPIE0_Pos (1U)
lypinator 0:bb348c97df44 1831 #define CAN_IER_FMPIE0_Msk (0x1U << CAN_IER_FMPIE0_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 1832 #define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk /*!<FIFO Message Pending Interrupt Enable */
lypinator 0:bb348c97df44 1833 #define CAN_IER_FFIE0_Pos (2U)
lypinator 0:bb348c97df44 1834 #define CAN_IER_FFIE0_Msk (0x1U << CAN_IER_FFIE0_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 1835 #define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk /*!<FIFO Full Interrupt Enable */
lypinator 0:bb348c97df44 1836 #define CAN_IER_FOVIE0_Pos (3U)
lypinator 0:bb348c97df44 1837 #define CAN_IER_FOVIE0_Msk (0x1U << CAN_IER_FOVIE0_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 1838 #define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk /*!<FIFO Overrun Interrupt Enable */
lypinator 0:bb348c97df44 1839 #define CAN_IER_FMPIE1_Pos (4U)
lypinator 0:bb348c97df44 1840 #define CAN_IER_FMPIE1_Msk (0x1U << CAN_IER_FMPIE1_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 1841 #define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk /*!<FIFO Message Pending Interrupt Enable */
lypinator 0:bb348c97df44 1842 #define CAN_IER_FFIE1_Pos (5U)
lypinator 0:bb348c97df44 1843 #define CAN_IER_FFIE1_Msk (0x1U << CAN_IER_FFIE1_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 1844 #define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk /*!<FIFO Full Interrupt Enable */
lypinator 0:bb348c97df44 1845 #define CAN_IER_FOVIE1_Pos (6U)
lypinator 0:bb348c97df44 1846 #define CAN_IER_FOVIE1_Msk (0x1U << CAN_IER_FOVIE1_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 1847 #define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk /*!<FIFO Overrun Interrupt Enable */
lypinator 0:bb348c97df44 1848 #define CAN_IER_EWGIE_Pos (8U)
lypinator 0:bb348c97df44 1849 #define CAN_IER_EWGIE_Msk (0x1U << CAN_IER_EWGIE_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 1850 #define CAN_IER_EWGIE CAN_IER_EWGIE_Msk /*!<Error Warning Interrupt Enable */
lypinator 0:bb348c97df44 1851 #define CAN_IER_EPVIE_Pos (9U)
lypinator 0:bb348c97df44 1852 #define CAN_IER_EPVIE_Msk (0x1U << CAN_IER_EPVIE_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 1853 #define CAN_IER_EPVIE CAN_IER_EPVIE_Msk /*!<Error Passive Interrupt Enable */
lypinator 0:bb348c97df44 1854 #define CAN_IER_BOFIE_Pos (10U)
lypinator 0:bb348c97df44 1855 #define CAN_IER_BOFIE_Msk (0x1U << CAN_IER_BOFIE_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 1856 #define CAN_IER_BOFIE CAN_IER_BOFIE_Msk /*!<Bus-Off Interrupt Enable */
lypinator 0:bb348c97df44 1857 #define CAN_IER_LECIE_Pos (11U)
lypinator 0:bb348c97df44 1858 #define CAN_IER_LECIE_Msk (0x1U << CAN_IER_LECIE_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 1859 #define CAN_IER_LECIE CAN_IER_LECIE_Msk /*!<Last Error Code Interrupt Enable */
lypinator 0:bb348c97df44 1860 #define CAN_IER_ERRIE_Pos (15U)
lypinator 0:bb348c97df44 1861 #define CAN_IER_ERRIE_Msk (0x1U << CAN_IER_ERRIE_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 1862 #define CAN_IER_ERRIE CAN_IER_ERRIE_Msk /*!<Error Interrupt Enable */
lypinator 0:bb348c97df44 1863 #define CAN_IER_WKUIE_Pos (16U)
lypinator 0:bb348c97df44 1864 #define CAN_IER_WKUIE_Msk (0x1U << CAN_IER_WKUIE_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 1865 #define CAN_IER_WKUIE CAN_IER_WKUIE_Msk /*!<Wakeup Interrupt Enable */
lypinator 0:bb348c97df44 1866 #define CAN_IER_SLKIE_Pos (17U)
lypinator 0:bb348c97df44 1867 #define CAN_IER_SLKIE_Msk (0x1U << CAN_IER_SLKIE_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 1868 #define CAN_IER_SLKIE CAN_IER_SLKIE_Msk /*!<Sleep Interrupt Enable */
lypinator 0:bb348c97df44 1869 #define CAN_IER_EWGIE_Pos (8U)
lypinator 0:bb348c97df44 1870
lypinator 0:bb348c97df44 1871 /******************** Bit definition for CAN_ESR register *******************/
lypinator 0:bb348c97df44 1872 #define CAN_ESR_EWGF_Pos (0U)
lypinator 0:bb348c97df44 1873 #define CAN_ESR_EWGF_Msk (0x1U << CAN_ESR_EWGF_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 1874 #define CAN_ESR_EWGF CAN_ESR_EWGF_Msk /*!<Error Warning Flag */
lypinator 0:bb348c97df44 1875 #define CAN_ESR_EPVF_Pos (1U)
lypinator 0:bb348c97df44 1876 #define CAN_ESR_EPVF_Msk (0x1U << CAN_ESR_EPVF_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 1877 #define CAN_ESR_EPVF CAN_ESR_EPVF_Msk /*!<Error Passive Flag */
lypinator 0:bb348c97df44 1878 #define CAN_ESR_BOFF_Pos (2U)
lypinator 0:bb348c97df44 1879 #define CAN_ESR_BOFF_Msk (0x1U << CAN_ESR_BOFF_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 1880 #define CAN_ESR_BOFF CAN_ESR_BOFF_Msk /*!<Bus-Off Flag */
lypinator 0:bb348c97df44 1881
lypinator 0:bb348c97df44 1882 #define CAN_ESR_LEC_Pos (4U)
lypinator 0:bb348c97df44 1883 #define CAN_ESR_LEC_Msk (0x7U << CAN_ESR_LEC_Pos) /*!< 0x00000070 */
lypinator 0:bb348c97df44 1884 #define CAN_ESR_LEC CAN_ESR_LEC_Msk /*!<LEC[2:0] bits (Last Error Code) */
lypinator 0:bb348c97df44 1885 #define CAN_ESR_LEC_0 (0x1U << CAN_ESR_LEC_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 1886 #define CAN_ESR_LEC_1 (0x2U << CAN_ESR_LEC_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 1887 #define CAN_ESR_LEC_2 (0x4U << CAN_ESR_LEC_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 1888
lypinator 0:bb348c97df44 1889 #define CAN_ESR_TEC_Pos (16U)
lypinator 0:bb348c97df44 1890 #define CAN_ESR_TEC_Msk (0xFFU << CAN_ESR_TEC_Pos) /*!< 0x00FF0000 */
lypinator 0:bb348c97df44 1891 #define CAN_ESR_TEC CAN_ESR_TEC_Msk /*!<Least significant byte of the 9-bit Transmit Error Counter */
lypinator 0:bb348c97df44 1892 #define CAN_ESR_REC_Pos (24U)
lypinator 0:bb348c97df44 1893 #define CAN_ESR_REC_Msk (0xFFU << CAN_ESR_REC_Pos) /*!< 0xFF000000 */
lypinator 0:bb348c97df44 1894 #define CAN_ESR_REC CAN_ESR_REC_Msk /*!<Receive Error Counter */
lypinator 0:bb348c97df44 1895
lypinator 0:bb348c97df44 1896 /******************* Bit definition for CAN_BTR register ********************/
lypinator 0:bb348c97df44 1897 #define CAN_BTR_BRP_Pos (0U)
lypinator 0:bb348c97df44 1898 #define CAN_BTR_BRP_Msk (0x3FFU << CAN_BTR_BRP_Pos) /*!< 0x000003FF */
lypinator 0:bb348c97df44 1899 #define CAN_BTR_BRP CAN_BTR_BRP_Msk /*!<Baud Rate Prescaler */
lypinator 0:bb348c97df44 1900 #define CAN_BTR_TS1_Pos (16U)
lypinator 0:bb348c97df44 1901 #define CAN_BTR_TS1_Msk (0xFU << CAN_BTR_TS1_Pos) /*!< 0x000F0000 */
lypinator 0:bb348c97df44 1902 #define CAN_BTR_TS1 CAN_BTR_TS1_Msk /*!<Time Segment 1 */
lypinator 0:bb348c97df44 1903 #define CAN_BTR_TS1_0 (0x1U << CAN_BTR_TS1_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 1904 #define CAN_BTR_TS1_1 (0x2U << CAN_BTR_TS1_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 1905 #define CAN_BTR_TS1_2 (0x4U << CAN_BTR_TS1_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 1906 #define CAN_BTR_TS1_3 (0x8U << CAN_BTR_TS1_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 1907 #define CAN_BTR_TS2_Pos (20U)
lypinator 0:bb348c97df44 1908 #define CAN_BTR_TS2_Msk (0x7U << CAN_BTR_TS2_Pos) /*!< 0x00700000 */
lypinator 0:bb348c97df44 1909 #define CAN_BTR_TS2 CAN_BTR_TS2_Msk /*!<Time Segment 2 */
lypinator 0:bb348c97df44 1910 #define CAN_BTR_TS2_0 (0x1U << CAN_BTR_TS2_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 1911 #define CAN_BTR_TS2_1 (0x2U << CAN_BTR_TS2_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 1912 #define CAN_BTR_TS2_2 (0x4U << CAN_BTR_TS2_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 1913 #define CAN_BTR_SJW_Pos (24U)
lypinator 0:bb348c97df44 1914 #define CAN_BTR_SJW_Msk (0x3U << CAN_BTR_SJW_Pos) /*!< 0x03000000 */
lypinator 0:bb348c97df44 1915 #define CAN_BTR_SJW CAN_BTR_SJW_Msk /*!<Resynchronization Jump Width */
lypinator 0:bb348c97df44 1916 #define CAN_BTR_SJW_0 (0x1U << CAN_BTR_SJW_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 1917 #define CAN_BTR_SJW_1 (0x2U << CAN_BTR_SJW_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 1918 #define CAN_BTR_LBKM_Pos (30U)
lypinator 0:bb348c97df44 1919 #define CAN_BTR_LBKM_Msk (0x1U << CAN_BTR_LBKM_Pos) /*!< 0x40000000 */
lypinator 0:bb348c97df44 1920 #define CAN_BTR_LBKM CAN_BTR_LBKM_Msk /*!<Loop Back Mode (Debug) */
lypinator 0:bb348c97df44 1921 #define CAN_BTR_SILM_Pos (31U)
lypinator 0:bb348c97df44 1922 #define CAN_BTR_SILM_Msk (0x1U << CAN_BTR_SILM_Pos) /*!< 0x80000000 */
lypinator 0:bb348c97df44 1923 #define CAN_BTR_SILM CAN_BTR_SILM_Msk /*!<Silent Mode */
lypinator 0:bb348c97df44 1924
lypinator 0:bb348c97df44 1925
lypinator 0:bb348c97df44 1926 /*!<Mailbox registers */
lypinator 0:bb348c97df44 1927 /****************** Bit definition for CAN_TI0R register ********************/
lypinator 0:bb348c97df44 1928 #define CAN_TI0R_TXRQ_Pos (0U)
lypinator 0:bb348c97df44 1929 #define CAN_TI0R_TXRQ_Msk (0x1U << CAN_TI0R_TXRQ_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 1930 #define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk /*!<Transmit Mailbox Request */
lypinator 0:bb348c97df44 1931 #define CAN_TI0R_RTR_Pos (1U)
lypinator 0:bb348c97df44 1932 #define CAN_TI0R_RTR_Msk (0x1U << CAN_TI0R_RTR_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 1933 #define CAN_TI0R_RTR CAN_TI0R_RTR_Msk /*!<Remote Transmission Request */
lypinator 0:bb348c97df44 1934 #define CAN_TI0R_IDE_Pos (2U)
lypinator 0:bb348c97df44 1935 #define CAN_TI0R_IDE_Msk (0x1U << CAN_TI0R_IDE_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 1936 #define CAN_TI0R_IDE CAN_TI0R_IDE_Msk /*!<Identifier Extension */
lypinator 0:bb348c97df44 1937 #define CAN_TI0R_EXID_Pos (3U)
lypinator 0:bb348c97df44 1938 #define CAN_TI0R_EXID_Msk (0x3FFFFU << CAN_TI0R_EXID_Pos) /*!< 0x001FFFF8 */
lypinator 0:bb348c97df44 1939 #define CAN_TI0R_EXID CAN_TI0R_EXID_Msk /*!<Extended Identifier */
lypinator 0:bb348c97df44 1940 #define CAN_TI0R_STID_Pos (21U)
lypinator 0:bb348c97df44 1941 #define CAN_TI0R_STID_Msk (0x7FFU << CAN_TI0R_STID_Pos) /*!< 0xFFE00000 */
lypinator 0:bb348c97df44 1942 #define CAN_TI0R_STID CAN_TI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
lypinator 0:bb348c97df44 1943
lypinator 0:bb348c97df44 1944 /****************** Bit definition for CAN_TDT0R register *******************/
lypinator 0:bb348c97df44 1945 #define CAN_TDT0R_DLC_Pos (0U)
lypinator 0:bb348c97df44 1946 #define CAN_TDT0R_DLC_Msk (0xFU << CAN_TDT0R_DLC_Pos) /*!< 0x0000000F */
lypinator 0:bb348c97df44 1947 #define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk /*!<Data Length Code */
lypinator 0:bb348c97df44 1948 #define CAN_TDT0R_TGT_Pos (8U)
lypinator 0:bb348c97df44 1949 #define CAN_TDT0R_TGT_Msk (0x1U << CAN_TDT0R_TGT_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 1950 #define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk /*!<Transmit Global Time */
lypinator 0:bb348c97df44 1951 #define CAN_TDT0R_TIME_Pos (16U)
lypinator 0:bb348c97df44 1952 #define CAN_TDT0R_TIME_Msk (0xFFFFU << CAN_TDT0R_TIME_Pos) /*!< 0xFFFF0000 */
lypinator 0:bb348c97df44 1953 #define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk /*!<Message Time Stamp */
lypinator 0:bb348c97df44 1954
lypinator 0:bb348c97df44 1955 /****************** Bit definition for CAN_TDL0R register *******************/
lypinator 0:bb348c97df44 1956 #define CAN_TDL0R_DATA0_Pos (0U)
lypinator 0:bb348c97df44 1957 #define CAN_TDL0R_DATA0_Msk (0xFFU << CAN_TDL0R_DATA0_Pos) /*!< 0x000000FF */
lypinator 0:bb348c97df44 1958 #define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk /*!<Data byte 0 */
lypinator 0:bb348c97df44 1959 #define CAN_TDL0R_DATA1_Pos (8U)
lypinator 0:bb348c97df44 1960 #define CAN_TDL0R_DATA1_Msk (0xFFU << CAN_TDL0R_DATA1_Pos) /*!< 0x0000FF00 */
lypinator 0:bb348c97df44 1961 #define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk /*!<Data byte 1 */
lypinator 0:bb348c97df44 1962 #define CAN_TDL0R_DATA2_Pos (16U)
lypinator 0:bb348c97df44 1963 #define CAN_TDL0R_DATA2_Msk (0xFFU << CAN_TDL0R_DATA2_Pos) /*!< 0x00FF0000 */
lypinator 0:bb348c97df44 1964 #define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk /*!<Data byte 2 */
lypinator 0:bb348c97df44 1965 #define CAN_TDL0R_DATA3_Pos (24U)
lypinator 0:bb348c97df44 1966 #define CAN_TDL0R_DATA3_Msk (0xFFU << CAN_TDL0R_DATA3_Pos) /*!< 0xFF000000 */
lypinator 0:bb348c97df44 1967 #define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk /*!<Data byte 3 */
lypinator 0:bb348c97df44 1968
lypinator 0:bb348c97df44 1969 /****************** Bit definition for CAN_TDH0R register *******************/
lypinator 0:bb348c97df44 1970 #define CAN_TDH0R_DATA4_Pos (0U)
lypinator 0:bb348c97df44 1971 #define CAN_TDH0R_DATA4_Msk (0xFFU << CAN_TDH0R_DATA4_Pos) /*!< 0x000000FF */
lypinator 0:bb348c97df44 1972 #define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk /*!<Data byte 4 */
lypinator 0:bb348c97df44 1973 #define CAN_TDH0R_DATA5_Pos (8U)
lypinator 0:bb348c97df44 1974 #define CAN_TDH0R_DATA5_Msk (0xFFU << CAN_TDH0R_DATA5_Pos) /*!< 0x0000FF00 */
lypinator 0:bb348c97df44 1975 #define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk /*!<Data byte 5 */
lypinator 0:bb348c97df44 1976 #define CAN_TDH0R_DATA6_Pos (16U)
lypinator 0:bb348c97df44 1977 #define CAN_TDH0R_DATA6_Msk (0xFFU << CAN_TDH0R_DATA6_Pos) /*!< 0x00FF0000 */
lypinator 0:bb348c97df44 1978 #define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk /*!<Data byte 6 */
lypinator 0:bb348c97df44 1979 #define CAN_TDH0R_DATA7_Pos (24U)
lypinator 0:bb348c97df44 1980 #define CAN_TDH0R_DATA7_Msk (0xFFU << CAN_TDH0R_DATA7_Pos) /*!< 0xFF000000 */
lypinator 0:bb348c97df44 1981 #define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk /*!<Data byte 7 */
lypinator 0:bb348c97df44 1982
lypinator 0:bb348c97df44 1983 /******************* Bit definition for CAN_TI1R register *******************/
lypinator 0:bb348c97df44 1984 #define CAN_TI1R_TXRQ_Pos (0U)
lypinator 0:bb348c97df44 1985 #define CAN_TI1R_TXRQ_Msk (0x1U << CAN_TI1R_TXRQ_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 1986 #define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk /*!<Transmit Mailbox Request */
lypinator 0:bb348c97df44 1987 #define CAN_TI1R_RTR_Pos (1U)
lypinator 0:bb348c97df44 1988 #define CAN_TI1R_RTR_Msk (0x1U << CAN_TI1R_RTR_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 1989 #define CAN_TI1R_RTR CAN_TI1R_RTR_Msk /*!<Remote Transmission Request */
lypinator 0:bb348c97df44 1990 #define CAN_TI1R_IDE_Pos (2U)
lypinator 0:bb348c97df44 1991 #define CAN_TI1R_IDE_Msk (0x1U << CAN_TI1R_IDE_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 1992 #define CAN_TI1R_IDE CAN_TI1R_IDE_Msk /*!<Identifier Extension */
lypinator 0:bb348c97df44 1993 #define CAN_TI1R_EXID_Pos (3U)
lypinator 0:bb348c97df44 1994 #define CAN_TI1R_EXID_Msk (0x3FFFFU << CAN_TI1R_EXID_Pos) /*!< 0x001FFFF8 */
lypinator 0:bb348c97df44 1995 #define CAN_TI1R_EXID CAN_TI1R_EXID_Msk /*!<Extended Identifier */
lypinator 0:bb348c97df44 1996 #define CAN_TI1R_STID_Pos (21U)
lypinator 0:bb348c97df44 1997 #define CAN_TI1R_STID_Msk (0x7FFU << CAN_TI1R_STID_Pos) /*!< 0xFFE00000 */
lypinator 0:bb348c97df44 1998 #define CAN_TI1R_STID CAN_TI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
lypinator 0:bb348c97df44 1999
lypinator 0:bb348c97df44 2000 /******************* Bit definition for CAN_TDT1R register ******************/
lypinator 0:bb348c97df44 2001 #define CAN_TDT1R_DLC_Pos (0U)
lypinator 0:bb348c97df44 2002 #define CAN_TDT1R_DLC_Msk (0xFU << CAN_TDT1R_DLC_Pos) /*!< 0x0000000F */
lypinator 0:bb348c97df44 2003 #define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk /*!<Data Length Code */
lypinator 0:bb348c97df44 2004 #define CAN_TDT1R_TGT_Pos (8U)
lypinator 0:bb348c97df44 2005 #define CAN_TDT1R_TGT_Msk (0x1U << CAN_TDT1R_TGT_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 2006 #define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk /*!<Transmit Global Time */
lypinator 0:bb348c97df44 2007 #define CAN_TDT1R_TIME_Pos (16U)
lypinator 0:bb348c97df44 2008 #define CAN_TDT1R_TIME_Msk (0xFFFFU << CAN_TDT1R_TIME_Pos) /*!< 0xFFFF0000 */
lypinator 0:bb348c97df44 2009 #define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk /*!<Message Time Stamp */
lypinator 0:bb348c97df44 2010
lypinator 0:bb348c97df44 2011 /******************* Bit definition for CAN_TDL1R register ******************/
lypinator 0:bb348c97df44 2012 #define CAN_TDL1R_DATA0_Pos (0U)
lypinator 0:bb348c97df44 2013 #define CAN_TDL1R_DATA0_Msk (0xFFU << CAN_TDL1R_DATA0_Pos) /*!< 0x000000FF */
lypinator 0:bb348c97df44 2014 #define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk /*!<Data byte 0 */
lypinator 0:bb348c97df44 2015 #define CAN_TDL1R_DATA1_Pos (8U)
lypinator 0:bb348c97df44 2016 #define CAN_TDL1R_DATA1_Msk (0xFFU << CAN_TDL1R_DATA1_Pos) /*!< 0x0000FF00 */
lypinator 0:bb348c97df44 2017 #define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk /*!<Data byte 1 */
lypinator 0:bb348c97df44 2018 #define CAN_TDL1R_DATA2_Pos (16U)
lypinator 0:bb348c97df44 2019 #define CAN_TDL1R_DATA2_Msk (0xFFU << CAN_TDL1R_DATA2_Pos) /*!< 0x00FF0000 */
lypinator 0:bb348c97df44 2020 #define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk /*!<Data byte 2 */
lypinator 0:bb348c97df44 2021 #define CAN_TDL1R_DATA3_Pos (24U)
lypinator 0:bb348c97df44 2022 #define CAN_TDL1R_DATA3_Msk (0xFFU << CAN_TDL1R_DATA3_Pos) /*!< 0xFF000000 */
lypinator 0:bb348c97df44 2023 #define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk /*!<Data byte 3 */
lypinator 0:bb348c97df44 2024
lypinator 0:bb348c97df44 2025 /******************* Bit definition for CAN_TDH1R register ******************/
lypinator 0:bb348c97df44 2026 #define CAN_TDH1R_DATA4_Pos (0U)
lypinator 0:bb348c97df44 2027 #define CAN_TDH1R_DATA4_Msk (0xFFU << CAN_TDH1R_DATA4_Pos) /*!< 0x000000FF */
lypinator 0:bb348c97df44 2028 #define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk /*!<Data byte 4 */
lypinator 0:bb348c97df44 2029 #define CAN_TDH1R_DATA5_Pos (8U)
lypinator 0:bb348c97df44 2030 #define CAN_TDH1R_DATA5_Msk (0xFFU << CAN_TDH1R_DATA5_Pos) /*!< 0x0000FF00 */
lypinator 0:bb348c97df44 2031 #define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk /*!<Data byte 5 */
lypinator 0:bb348c97df44 2032 #define CAN_TDH1R_DATA6_Pos (16U)
lypinator 0:bb348c97df44 2033 #define CAN_TDH1R_DATA6_Msk (0xFFU << CAN_TDH1R_DATA6_Pos) /*!< 0x00FF0000 */
lypinator 0:bb348c97df44 2034 #define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk /*!<Data byte 6 */
lypinator 0:bb348c97df44 2035 #define CAN_TDH1R_DATA7_Pos (24U)
lypinator 0:bb348c97df44 2036 #define CAN_TDH1R_DATA7_Msk (0xFFU << CAN_TDH1R_DATA7_Pos) /*!< 0xFF000000 */
lypinator 0:bb348c97df44 2037 #define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk /*!<Data byte 7 */
lypinator 0:bb348c97df44 2038
lypinator 0:bb348c97df44 2039 /******************* Bit definition for CAN_TI2R register *******************/
lypinator 0:bb348c97df44 2040 #define CAN_TI2R_TXRQ_Pos (0U)
lypinator 0:bb348c97df44 2041 #define CAN_TI2R_TXRQ_Msk (0x1U << CAN_TI2R_TXRQ_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 2042 #define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk /*!<Transmit Mailbox Request */
lypinator 0:bb348c97df44 2043 #define CAN_TI2R_RTR_Pos (1U)
lypinator 0:bb348c97df44 2044 #define CAN_TI2R_RTR_Msk (0x1U << CAN_TI2R_RTR_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 2045 #define CAN_TI2R_RTR CAN_TI2R_RTR_Msk /*!<Remote Transmission Request */
lypinator 0:bb348c97df44 2046 #define CAN_TI2R_IDE_Pos (2U)
lypinator 0:bb348c97df44 2047 #define CAN_TI2R_IDE_Msk (0x1U << CAN_TI2R_IDE_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 2048 #define CAN_TI2R_IDE CAN_TI2R_IDE_Msk /*!<Identifier Extension */
lypinator 0:bb348c97df44 2049 #define CAN_TI2R_EXID_Pos (3U)
lypinator 0:bb348c97df44 2050 #define CAN_TI2R_EXID_Msk (0x3FFFFU << CAN_TI2R_EXID_Pos) /*!< 0x001FFFF8 */
lypinator 0:bb348c97df44 2051 #define CAN_TI2R_EXID CAN_TI2R_EXID_Msk /*!<Extended identifier */
lypinator 0:bb348c97df44 2052 #define CAN_TI2R_STID_Pos (21U)
lypinator 0:bb348c97df44 2053 #define CAN_TI2R_STID_Msk (0x7FFU << CAN_TI2R_STID_Pos) /*!< 0xFFE00000 */
lypinator 0:bb348c97df44 2054 #define CAN_TI2R_STID CAN_TI2R_STID_Msk /*!<Standard Identifier or Extended Identifier */
lypinator 0:bb348c97df44 2055
lypinator 0:bb348c97df44 2056 /******************* Bit definition for CAN_TDT2R register ******************/
lypinator 0:bb348c97df44 2057 #define CAN_TDT2R_DLC_Pos (0U)
lypinator 0:bb348c97df44 2058 #define CAN_TDT2R_DLC_Msk (0xFU << CAN_TDT2R_DLC_Pos) /*!< 0x0000000F */
lypinator 0:bb348c97df44 2059 #define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk /*!<Data Length Code */
lypinator 0:bb348c97df44 2060 #define CAN_TDT2R_TGT_Pos (8U)
lypinator 0:bb348c97df44 2061 #define CAN_TDT2R_TGT_Msk (0x1U << CAN_TDT2R_TGT_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 2062 #define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk /*!<Transmit Global Time */
lypinator 0:bb348c97df44 2063 #define CAN_TDT2R_TIME_Pos (16U)
lypinator 0:bb348c97df44 2064 #define CAN_TDT2R_TIME_Msk (0xFFFFU << CAN_TDT2R_TIME_Pos) /*!< 0xFFFF0000 */
lypinator 0:bb348c97df44 2065 #define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk /*!<Message Time Stamp */
lypinator 0:bb348c97df44 2066
lypinator 0:bb348c97df44 2067 /******************* Bit definition for CAN_TDL2R register ******************/
lypinator 0:bb348c97df44 2068 #define CAN_TDL2R_DATA0_Pos (0U)
lypinator 0:bb348c97df44 2069 #define CAN_TDL2R_DATA0_Msk (0xFFU << CAN_TDL2R_DATA0_Pos) /*!< 0x000000FF */
lypinator 0:bb348c97df44 2070 #define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk /*!<Data byte 0 */
lypinator 0:bb348c97df44 2071 #define CAN_TDL2R_DATA1_Pos (8U)
lypinator 0:bb348c97df44 2072 #define CAN_TDL2R_DATA1_Msk (0xFFU << CAN_TDL2R_DATA1_Pos) /*!< 0x0000FF00 */
lypinator 0:bb348c97df44 2073 #define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk /*!<Data byte 1 */
lypinator 0:bb348c97df44 2074 #define CAN_TDL2R_DATA2_Pos (16U)
lypinator 0:bb348c97df44 2075 #define CAN_TDL2R_DATA2_Msk (0xFFU << CAN_TDL2R_DATA2_Pos) /*!< 0x00FF0000 */
lypinator 0:bb348c97df44 2076 #define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk /*!<Data byte 2 */
lypinator 0:bb348c97df44 2077 #define CAN_TDL2R_DATA3_Pos (24U)
lypinator 0:bb348c97df44 2078 #define CAN_TDL2R_DATA3_Msk (0xFFU << CAN_TDL2R_DATA3_Pos) /*!< 0xFF000000 */
lypinator 0:bb348c97df44 2079 #define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk /*!<Data byte 3 */
lypinator 0:bb348c97df44 2080
lypinator 0:bb348c97df44 2081 /******************* Bit definition for CAN_TDH2R register ******************/
lypinator 0:bb348c97df44 2082 #define CAN_TDH2R_DATA4_Pos (0U)
lypinator 0:bb348c97df44 2083 #define CAN_TDH2R_DATA4_Msk (0xFFU << CAN_TDH2R_DATA4_Pos) /*!< 0x000000FF */
lypinator 0:bb348c97df44 2084 #define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk /*!<Data byte 4 */
lypinator 0:bb348c97df44 2085 #define CAN_TDH2R_DATA5_Pos (8U)
lypinator 0:bb348c97df44 2086 #define CAN_TDH2R_DATA5_Msk (0xFFU << CAN_TDH2R_DATA5_Pos) /*!< 0x0000FF00 */
lypinator 0:bb348c97df44 2087 #define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk /*!<Data byte 5 */
lypinator 0:bb348c97df44 2088 #define CAN_TDH2R_DATA6_Pos (16U)
lypinator 0:bb348c97df44 2089 #define CAN_TDH2R_DATA6_Msk (0xFFU << CAN_TDH2R_DATA6_Pos) /*!< 0x00FF0000 */
lypinator 0:bb348c97df44 2090 #define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk /*!<Data byte 6 */
lypinator 0:bb348c97df44 2091 #define CAN_TDH2R_DATA7_Pos (24U)
lypinator 0:bb348c97df44 2092 #define CAN_TDH2R_DATA7_Msk (0xFFU << CAN_TDH2R_DATA7_Pos) /*!< 0xFF000000 */
lypinator 0:bb348c97df44 2093 #define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk /*!<Data byte 7 */
lypinator 0:bb348c97df44 2094
lypinator 0:bb348c97df44 2095 /******************* Bit definition for CAN_RI0R register *******************/
lypinator 0:bb348c97df44 2096 #define CAN_RI0R_RTR_Pos (1U)
lypinator 0:bb348c97df44 2097 #define CAN_RI0R_RTR_Msk (0x1U << CAN_RI0R_RTR_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 2098 #define CAN_RI0R_RTR CAN_RI0R_RTR_Msk /*!<Remote Transmission Request */
lypinator 0:bb348c97df44 2099 #define CAN_RI0R_IDE_Pos (2U)
lypinator 0:bb348c97df44 2100 #define CAN_RI0R_IDE_Msk (0x1U << CAN_RI0R_IDE_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 2101 #define CAN_RI0R_IDE CAN_RI0R_IDE_Msk /*!<Identifier Extension */
lypinator 0:bb348c97df44 2102 #define CAN_RI0R_EXID_Pos (3U)
lypinator 0:bb348c97df44 2103 #define CAN_RI0R_EXID_Msk (0x3FFFFU << CAN_RI0R_EXID_Pos) /*!< 0x001FFFF8 */
lypinator 0:bb348c97df44 2104 #define CAN_RI0R_EXID CAN_RI0R_EXID_Msk /*!<Extended Identifier */
lypinator 0:bb348c97df44 2105 #define CAN_RI0R_STID_Pos (21U)
lypinator 0:bb348c97df44 2106 #define CAN_RI0R_STID_Msk (0x7FFU << CAN_RI0R_STID_Pos) /*!< 0xFFE00000 */
lypinator 0:bb348c97df44 2107 #define CAN_RI0R_STID CAN_RI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
lypinator 0:bb348c97df44 2108
lypinator 0:bb348c97df44 2109 /******************* Bit definition for CAN_RDT0R register ******************/
lypinator 0:bb348c97df44 2110 #define CAN_RDT0R_DLC_Pos (0U)
lypinator 0:bb348c97df44 2111 #define CAN_RDT0R_DLC_Msk (0xFU << CAN_RDT0R_DLC_Pos) /*!< 0x0000000F */
lypinator 0:bb348c97df44 2112 #define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk /*!<Data Length Code */
lypinator 0:bb348c97df44 2113 #define CAN_RDT0R_FMI_Pos (8U)
lypinator 0:bb348c97df44 2114 #define CAN_RDT0R_FMI_Msk (0xFFU << CAN_RDT0R_FMI_Pos) /*!< 0x0000FF00 */
lypinator 0:bb348c97df44 2115 #define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk /*!<Filter Match Index */
lypinator 0:bb348c97df44 2116 #define CAN_RDT0R_TIME_Pos (16U)
lypinator 0:bb348c97df44 2117 #define CAN_RDT0R_TIME_Msk (0xFFFFU << CAN_RDT0R_TIME_Pos) /*!< 0xFFFF0000 */
lypinator 0:bb348c97df44 2118 #define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk /*!<Message Time Stamp */
lypinator 0:bb348c97df44 2119
lypinator 0:bb348c97df44 2120 /******************* Bit definition for CAN_RDL0R register ******************/
lypinator 0:bb348c97df44 2121 #define CAN_RDL0R_DATA0_Pos (0U)
lypinator 0:bb348c97df44 2122 #define CAN_RDL0R_DATA0_Msk (0xFFU << CAN_RDL0R_DATA0_Pos) /*!< 0x000000FF */
lypinator 0:bb348c97df44 2123 #define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk /*!<Data byte 0 */
lypinator 0:bb348c97df44 2124 #define CAN_RDL0R_DATA1_Pos (8U)
lypinator 0:bb348c97df44 2125 #define CAN_RDL0R_DATA1_Msk (0xFFU << CAN_RDL0R_DATA1_Pos) /*!< 0x0000FF00 */
lypinator 0:bb348c97df44 2126 #define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk /*!<Data byte 1 */
lypinator 0:bb348c97df44 2127 #define CAN_RDL0R_DATA2_Pos (16U)
lypinator 0:bb348c97df44 2128 #define CAN_RDL0R_DATA2_Msk (0xFFU << CAN_RDL0R_DATA2_Pos) /*!< 0x00FF0000 */
lypinator 0:bb348c97df44 2129 #define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk /*!<Data byte 2 */
lypinator 0:bb348c97df44 2130 #define CAN_RDL0R_DATA3_Pos (24U)
lypinator 0:bb348c97df44 2131 #define CAN_RDL0R_DATA3_Msk (0xFFU << CAN_RDL0R_DATA3_Pos) /*!< 0xFF000000 */
lypinator 0:bb348c97df44 2132 #define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk /*!<Data byte 3 */
lypinator 0:bb348c97df44 2133
lypinator 0:bb348c97df44 2134 /******************* Bit definition for CAN_RDH0R register ******************/
lypinator 0:bb348c97df44 2135 #define CAN_RDH0R_DATA4_Pos (0U)
lypinator 0:bb348c97df44 2136 #define CAN_RDH0R_DATA4_Msk (0xFFU << CAN_RDH0R_DATA4_Pos) /*!< 0x000000FF */
lypinator 0:bb348c97df44 2137 #define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk /*!<Data byte 4 */
lypinator 0:bb348c97df44 2138 #define CAN_RDH0R_DATA5_Pos (8U)
lypinator 0:bb348c97df44 2139 #define CAN_RDH0R_DATA5_Msk (0xFFU << CAN_RDH0R_DATA5_Pos) /*!< 0x0000FF00 */
lypinator 0:bb348c97df44 2140 #define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk /*!<Data byte 5 */
lypinator 0:bb348c97df44 2141 #define CAN_RDH0R_DATA6_Pos (16U)
lypinator 0:bb348c97df44 2142 #define CAN_RDH0R_DATA6_Msk (0xFFU << CAN_RDH0R_DATA6_Pos) /*!< 0x00FF0000 */
lypinator 0:bb348c97df44 2143 #define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk /*!<Data byte 6 */
lypinator 0:bb348c97df44 2144 #define CAN_RDH0R_DATA7_Pos (24U)
lypinator 0:bb348c97df44 2145 #define CAN_RDH0R_DATA7_Msk (0xFFU << CAN_RDH0R_DATA7_Pos) /*!< 0xFF000000 */
lypinator 0:bb348c97df44 2146 #define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk /*!<Data byte 7 */
lypinator 0:bb348c97df44 2147
lypinator 0:bb348c97df44 2148 /******************* Bit definition for CAN_RI1R register *******************/
lypinator 0:bb348c97df44 2149 #define CAN_RI1R_RTR_Pos (1U)
lypinator 0:bb348c97df44 2150 #define CAN_RI1R_RTR_Msk (0x1U << CAN_RI1R_RTR_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 2151 #define CAN_RI1R_RTR CAN_RI1R_RTR_Msk /*!<Remote Transmission Request */
lypinator 0:bb348c97df44 2152 #define CAN_RI1R_IDE_Pos (2U)
lypinator 0:bb348c97df44 2153 #define CAN_RI1R_IDE_Msk (0x1U << CAN_RI1R_IDE_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 2154 #define CAN_RI1R_IDE CAN_RI1R_IDE_Msk /*!<Identifier Extension */
lypinator 0:bb348c97df44 2155 #define CAN_RI1R_EXID_Pos (3U)
lypinator 0:bb348c97df44 2156 #define CAN_RI1R_EXID_Msk (0x3FFFFU << CAN_RI1R_EXID_Pos) /*!< 0x001FFFF8 */
lypinator 0:bb348c97df44 2157 #define CAN_RI1R_EXID CAN_RI1R_EXID_Msk /*!<Extended identifier */
lypinator 0:bb348c97df44 2158 #define CAN_RI1R_STID_Pos (21U)
lypinator 0:bb348c97df44 2159 #define CAN_RI1R_STID_Msk (0x7FFU << CAN_RI1R_STID_Pos) /*!< 0xFFE00000 */
lypinator 0:bb348c97df44 2160 #define CAN_RI1R_STID CAN_RI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
lypinator 0:bb348c97df44 2161
lypinator 0:bb348c97df44 2162 /******************* Bit definition for CAN_RDT1R register ******************/
lypinator 0:bb348c97df44 2163 #define CAN_RDT1R_DLC_Pos (0U)
lypinator 0:bb348c97df44 2164 #define CAN_RDT1R_DLC_Msk (0xFU << CAN_RDT1R_DLC_Pos) /*!< 0x0000000F */
lypinator 0:bb348c97df44 2165 #define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk /*!<Data Length Code */
lypinator 0:bb348c97df44 2166 #define CAN_RDT1R_FMI_Pos (8U)
lypinator 0:bb348c97df44 2167 #define CAN_RDT1R_FMI_Msk (0xFFU << CAN_RDT1R_FMI_Pos) /*!< 0x0000FF00 */
lypinator 0:bb348c97df44 2168 #define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk /*!<Filter Match Index */
lypinator 0:bb348c97df44 2169 #define CAN_RDT1R_TIME_Pos (16U)
lypinator 0:bb348c97df44 2170 #define CAN_RDT1R_TIME_Msk (0xFFFFU << CAN_RDT1R_TIME_Pos) /*!< 0xFFFF0000 */
lypinator 0:bb348c97df44 2171 #define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk /*!<Message Time Stamp */
lypinator 0:bb348c97df44 2172
lypinator 0:bb348c97df44 2173 /******************* Bit definition for CAN_RDL1R register ******************/
lypinator 0:bb348c97df44 2174 #define CAN_RDL1R_DATA0_Pos (0U)
lypinator 0:bb348c97df44 2175 #define CAN_RDL1R_DATA0_Msk (0xFFU << CAN_RDL1R_DATA0_Pos) /*!< 0x000000FF */
lypinator 0:bb348c97df44 2176 #define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk /*!<Data byte 0 */
lypinator 0:bb348c97df44 2177 #define CAN_RDL1R_DATA1_Pos (8U)
lypinator 0:bb348c97df44 2178 #define CAN_RDL1R_DATA1_Msk (0xFFU << CAN_RDL1R_DATA1_Pos) /*!< 0x0000FF00 */
lypinator 0:bb348c97df44 2179 #define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk /*!<Data byte 1 */
lypinator 0:bb348c97df44 2180 #define CAN_RDL1R_DATA2_Pos (16U)
lypinator 0:bb348c97df44 2181 #define CAN_RDL1R_DATA2_Msk (0xFFU << CAN_RDL1R_DATA2_Pos) /*!< 0x00FF0000 */
lypinator 0:bb348c97df44 2182 #define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk /*!<Data byte 2 */
lypinator 0:bb348c97df44 2183 #define CAN_RDL1R_DATA3_Pos (24U)
lypinator 0:bb348c97df44 2184 #define CAN_RDL1R_DATA3_Msk (0xFFU << CAN_RDL1R_DATA3_Pos) /*!< 0xFF000000 */
lypinator 0:bb348c97df44 2185 #define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk /*!<Data byte 3 */
lypinator 0:bb348c97df44 2186
lypinator 0:bb348c97df44 2187 /******************* Bit definition for CAN_RDH1R register ******************/
lypinator 0:bb348c97df44 2188 #define CAN_RDH1R_DATA4_Pos (0U)
lypinator 0:bb348c97df44 2189 #define CAN_RDH1R_DATA4_Msk (0xFFU << CAN_RDH1R_DATA4_Pos) /*!< 0x000000FF */
lypinator 0:bb348c97df44 2190 #define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk /*!<Data byte 4 */
lypinator 0:bb348c97df44 2191 #define CAN_RDH1R_DATA5_Pos (8U)
lypinator 0:bb348c97df44 2192 #define CAN_RDH1R_DATA5_Msk (0xFFU << CAN_RDH1R_DATA5_Pos) /*!< 0x0000FF00 */
lypinator 0:bb348c97df44 2193 #define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk /*!<Data byte 5 */
lypinator 0:bb348c97df44 2194 #define CAN_RDH1R_DATA6_Pos (16U)
lypinator 0:bb348c97df44 2195 #define CAN_RDH1R_DATA6_Msk (0xFFU << CAN_RDH1R_DATA6_Pos) /*!< 0x00FF0000 */
lypinator 0:bb348c97df44 2196 #define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk /*!<Data byte 6 */
lypinator 0:bb348c97df44 2197 #define CAN_RDH1R_DATA7_Pos (24U)
lypinator 0:bb348c97df44 2198 #define CAN_RDH1R_DATA7_Msk (0xFFU << CAN_RDH1R_DATA7_Pos) /*!< 0xFF000000 */
lypinator 0:bb348c97df44 2199 #define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk /*!<Data byte 7 */
lypinator 0:bb348c97df44 2200
lypinator 0:bb348c97df44 2201 /*!<CAN filter registers */
lypinator 0:bb348c97df44 2202 /******************* Bit definition for CAN_FMR register ********************/
lypinator 0:bb348c97df44 2203 #define CAN_FMR_FINIT_Pos (0U)
lypinator 0:bb348c97df44 2204 #define CAN_FMR_FINIT_Msk (0x1U << CAN_FMR_FINIT_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 2205 #define CAN_FMR_FINIT CAN_FMR_FINIT_Msk /*!<Filter Init Mode */
lypinator 0:bb348c97df44 2206 #define CAN_FMR_CAN2SB_Pos (8U)
lypinator 0:bb348c97df44 2207 #define CAN_FMR_CAN2SB_Msk (0x3FU << CAN_FMR_CAN2SB_Pos) /*!< 0x00003F00 */
lypinator 0:bb348c97df44 2208 #define CAN_FMR_CAN2SB CAN_FMR_CAN2SB_Msk /*!<CAN2 start bank */
lypinator 0:bb348c97df44 2209
lypinator 0:bb348c97df44 2210 /******************* Bit definition for CAN_FM1R register *******************/
lypinator 0:bb348c97df44 2211 #define CAN_FM1R_FBM_Pos (0U)
lypinator 0:bb348c97df44 2212 #define CAN_FM1R_FBM_Msk (0xFFFFFFFU << CAN_FM1R_FBM_Pos) /*!< 0x0FFFFFFF */
lypinator 0:bb348c97df44 2213 #define CAN_FM1R_FBM CAN_FM1R_FBM_Msk /*!<Filter Mode */
lypinator 0:bb348c97df44 2214 #define CAN_FM1R_FBM0_Pos (0U)
lypinator 0:bb348c97df44 2215 #define CAN_FM1R_FBM0_Msk (0x1U << CAN_FM1R_FBM0_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 2216 #define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk /*!<Filter Init Mode bit 0 */
lypinator 0:bb348c97df44 2217 #define CAN_FM1R_FBM1_Pos (1U)
lypinator 0:bb348c97df44 2218 #define CAN_FM1R_FBM1_Msk (0x1U << CAN_FM1R_FBM1_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 2219 #define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk /*!<Filter Init Mode bit 1 */
lypinator 0:bb348c97df44 2220 #define CAN_FM1R_FBM2_Pos (2U)
lypinator 0:bb348c97df44 2221 #define CAN_FM1R_FBM2_Msk (0x1U << CAN_FM1R_FBM2_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 2222 #define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk /*!<Filter Init Mode bit 2 */
lypinator 0:bb348c97df44 2223 #define CAN_FM1R_FBM3_Pos (3U)
lypinator 0:bb348c97df44 2224 #define CAN_FM1R_FBM3_Msk (0x1U << CAN_FM1R_FBM3_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 2225 #define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk /*!<Filter Init Mode bit 3 */
lypinator 0:bb348c97df44 2226 #define CAN_FM1R_FBM4_Pos (4U)
lypinator 0:bb348c97df44 2227 #define CAN_FM1R_FBM4_Msk (0x1U << CAN_FM1R_FBM4_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 2228 #define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk /*!<Filter Init Mode bit 4 */
lypinator 0:bb348c97df44 2229 #define CAN_FM1R_FBM5_Pos (5U)
lypinator 0:bb348c97df44 2230 #define CAN_FM1R_FBM5_Msk (0x1U << CAN_FM1R_FBM5_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 2231 #define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk /*!<Filter Init Mode bit 5 */
lypinator 0:bb348c97df44 2232 #define CAN_FM1R_FBM6_Pos (6U)
lypinator 0:bb348c97df44 2233 #define CAN_FM1R_FBM6_Msk (0x1U << CAN_FM1R_FBM6_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 2234 #define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk /*!<Filter Init Mode bit 6 */
lypinator 0:bb348c97df44 2235 #define CAN_FM1R_FBM7_Pos (7U)
lypinator 0:bb348c97df44 2236 #define CAN_FM1R_FBM7_Msk (0x1U << CAN_FM1R_FBM7_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 2237 #define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk /*!<Filter Init Mode bit 7 */
lypinator 0:bb348c97df44 2238 #define CAN_FM1R_FBM8_Pos (8U)
lypinator 0:bb348c97df44 2239 #define CAN_FM1R_FBM8_Msk (0x1U << CAN_FM1R_FBM8_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 2240 #define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk /*!<Filter Init Mode bit 8 */
lypinator 0:bb348c97df44 2241 #define CAN_FM1R_FBM9_Pos (9U)
lypinator 0:bb348c97df44 2242 #define CAN_FM1R_FBM9_Msk (0x1U << CAN_FM1R_FBM9_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 2243 #define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk /*!<Filter Init Mode bit 9 */
lypinator 0:bb348c97df44 2244 #define CAN_FM1R_FBM10_Pos (10U)
lypinator 0:bb348c97df44 2245 #define CAN_FM1R_FBM10_Msk (0x1U << CAN_FM1R_FBM10_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 2246 #define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk /*!<Filter Init Mode bit 10 */
lypinator 0:bb348c97df44 2247 #define CAN_FM1R_FBM11_Pos (11U)
lypinator 0:bb348c97df44 2248 #define CAN_FM1R_FBM11_Msk (0x1U << CAN_FM1R_FBM11_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 2249 #define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk /*!<Filter Init Mode bit 11 */
lypinator 0:bb348c97df44 2250 #define CAN_FM1R_FBM12_Pos (12U)
lypinator 0:bb348c97df44 2251 #define CAN_FM1R_FBM12_Msk (0x1U << CAN_FM1R_FBM12_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 2252 #define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk /*!<Filter Init Mode bit 12 */
lypinator 0:bb348c97df44 2253 #define CAN_FM1R_FBM13_Pos (13U)
lypinator 0:bb348c97df44 2254 #define CAN_FM1R_FBM13_Msk (0x1U << CAN_FM1R_FBM13_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 2255 #define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk /*!<Filter Init Mode bit 13 */
lypinator 0:bb348c97df44 2256 #define CAN_FM1R_FBM14_Pos (14U)
lypinator 0:bb348c97df44 2257 #define CAN_FM1R_FBM14_Msk (0x1U << CAN_FM1R_FBM14_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 2258 #define CAN_FM1R_FBM14 CAN_FM1R_FBM14_Msk /*!<Filter Init Mode bit 14 */
lypinator 0:bb348c97df44 2259 #define CAN_FM1R_FBM15_Pos (15U)
lypinator 0:bb348c97df44 2260 #define CAN_FM1R_FBM15_Msk (0x1U << CAN_FM1R_FBM15_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 2261 #define CAN_FM1R_FBM15 CAN_FM1R_FBM15_Msk /*!<Filter Init Mode bit 15 */
lypinator 0:bb348c97df44 2262 #define CAN_FM1R_FBM16_Pos (16U)
lypinator 0:bb348c97df44 2263 #define CAN_FM1R_FBM16_Msk (0x1U << CAN_FM1R_FBM16_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 2264 #define CAN_FM1R_FBM16 CAN_FM1R_FBM16_Msk /*!<Filter Init Mode bit 16 */
lypinator 0:bb348c97df44 2265 #define CAN_FM1R_FBM17_Pos (17U)
lypinator 0:bb348c97df44 2266 #define CAN_FM1R_FBM17_Msk (0x1U << CAN_FM1R_FBM17_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 2267 #define CAN_FM1R_FBM17 CAN_FM1R_FBM17_Msk /*!<Filter Init Mode bit 17 */
lypinator 0:bb348c97df44 2268 #define CAN_FM1R_FBM18_Pos (18U)
lypinator 0:bb348c97df44 2269 #define CAN_FM1R_FBM18_Msk (0x1U << CAN_FM1R_FBM18_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 2270 #define CAN_FM1R_FBM18 CAN_FM1R_FBM18_Msk /*!<Filter Init Mode bit 18 */
lypinator 0:bb348c97df44 2271 #define CAN_FM1R_FBM19_Pos (19U)
lypinator 0:bb348c97df44 2272 #define CAN_FM1R_FBM19_Msk (0x1U << CAN_FM1R_FBM19_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 2273 #define CAN_FM1R_FBM19 CAN_FM1R_FBM19_Msk /*!<Filter Init Mode bit 19 */
lypinator 0:bb348c97df44 2274 #define CAN_FM1R_FBM20_Pos (20U)
lypinator 0:bb348c97df44 2275 #define CAN_FM1R_FBM20_Msk (0x1U << CAN_FM1R_FBM20_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 2276 #define CAN_FM1R_FBM20 CAN_FM1R_FBM20_Msk /*!<Filter Init Mode bit 20 */
lypinator 0:bb348c97df44 2277 #define CAN_FM1R_FBM21_Pos (21U)
lypinator 0:bb348c97df44 2278 #define CAN_FM1R_FBM21_Msk (0x1U << CAN_FM1R_FBM21_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 2279 #define CAN_FM1R_FBM21 CAN_FM1R_FBM21_Msk /*!<Filter Init Mode bit 21 */
lypinator 0:bb348c97df44 2280 #define CAN_FM1R_FBM22_Pos (22U)
lypinator 0:bb348c97df44 2281 #define CAN_FM1R_FBM22_Msk (0x1U << CAN_FM1R_FBM22_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 2282 #define CAN_FM1R_FBM22 CAN_FM1R_FBM22_Msk /*!<Filter Init Mode bit 22 */
lypinator 0:bb348c97df44 2283 #define CAN_FM1R_FBM23_Pos (23U)
lypinator 0:bb348c97df44 2284 #define CAN_FM1R_FBM23_Msk (0x1U << CAN_FM1R_FBM23_Pos) /*!< 0x00800000 */
lypinator 0:bb348c97df44 2285 #define CAN_FM1R_FBM23 CAN_FM1R_FBM23_Msk /*!<Filter Init Mode bit 23 */
lypinator 0:bb348c97df44 2286 #define CAN_FM1R_FBM24_Pos (24U)
lypinator 0:bb348c97df44 2287 #define CAN_FM1R_FBM24_Msk (0x1U << CAN_FM1R_FBM24_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 2288 #define CAN_FM1R_FBM24 CAN_FM1R_FBM24_Msk /*!<Filter Init Mode bit 24 */
lypinator 0:bb348c97df44 2289 #define CAN_FM1R_FBM25_Pos (25U)
lypinator 0:bb348c97df44 2290 #define CAN_FM1R_FBM25_Msk (0x1U << CAN_FM1R_FBM25_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 2291 #define CAN_FM1R_FBM25 CAN_FM1R_FBM25_Msk /*!<Filter Init Mode bit 25 */
lypinator 0:bb348c97df44 2292 #define CAN_FM1R_FBM26_Pos (26U)
lypinator 0:bb348c97df44 2293 #define CAN_FM1R_FBM26_Msk (0x1U << CAN_FM1R_FBM26_Pos) /*!< 0x04000000 */
lypinator 0:bb348c97df44 2294 #define CAN_FM1R_FBM26 CAN_FM1R_FBM26_Msk /*!<Filter Init Mode bit 26 */
lypinator 0:bb348c97df44 2295 #define CAN_FM1R_FBM27_Pos (27U)
lypinator 0:bb348c97df44 2296 #define CAN_FM1R_FBM27_Msk (0x1U << CAN_FM1R_FBM27_Pos) /*!< 0x08000000 */
lypinator 0:bb348c97df44 2297 #define CAN_FM1R_FBM27 CAN_FM1R_FBM27_Msk /*!<Filter Init Mode bit 27 */
lypinator 0:bb348c97df44 2298
lypinator 0:bb348c97df44 2299 /******************* Bit definition for CAN_FS1R register *******************/
lypinator 0:bb348c97df44 2300 #define CAN_FS1R_FSC_Pos (0U)
lypinator 0:bb348c97df44 2301 #define CAN_FS1R_FSC_Msk (0xFFFFFFFU << CAN_FS1R_FSC_Pos) /*!< 0x0FFFFFFF */
lypinator 0:bb348c97df44 2302 #define CAN_FS1R_FSC CAN_FS1R_FSC_Msk /*!<Filter Scale Configuration */
lypinator 0:bb348c97df44 2303 #define CAN_FS1R_FSC0_Pos (0U)
lypinator 0:bb348c97df44 2304 #define CAN_FS1R_FSC0_Msk (0x1U << CAN_FS1R_FSC0_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 2305 #define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk /*!<Filter Scale Configuration bit 0 */
lypinator 0:bb348c97df44 2306 #define CAN_FS1R_FSC1_Pos (1U)
lypinator 0:bb348c97df44 2307 #define CAN_FS1R_FSC1_Msk (0x1U << CAN_FS1R_FSC1_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 2308 #define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk /*!<Filter Scale Configuration bit 1 */
lypinator 0:bb348c97df44 2309 #define CAN_FS1R_FSC2_Pos (2U)
lypinator 0:bb348c97df44 2310 #define CAN_FS1R_FSC2_Msk (0x1U << CAN_FS1R_FSC2_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 2311 #define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk /*!<Filter Scale Configuration bit 2 */
lypinator 0:bb348c97df44 2312 #define CAN_FS1R_FSC3_Pos (3U)
lypinator 0:bb348c97df44 2313 #define CAN_FS1R_FSC3_Msk (0x1U << CAN_FS1R_FSC3_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 2314 #define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk /*!<Filter Scale Configuration bit 3 */
lypinator 0:bb348c97df44 2315 #define CAN_FS1R_FSC4_Pos (4U)
lypinator 0:bb348c97df44 2316 #define CAN_FS1R_FSC4_Msk (0x1U << CAN_FS1R_FSC4_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 2317 #define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk /*!<Filter Scale Configuration bit 4 */
lypinator 0:bb348c97df44 2318 #define CAN_FS1R_FSC5_Pos (5U)
lypinator 0:bb348c97df44 2319 #define CAN_FS1R_FSC5_Msk (0x1U << CAN_FS1R_FSC5_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 2320 #define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk /*!<Filter Scale Configuration bit 5 */
lypinator 0:bb348c97df44 2321 #define CAN_FS1R_FSC6_Pos (6U)
lypinator 0:bb348c97df44 2322 #define CAN_FS1R_FSC6_Msk (0x1U << CAN_FS1R_FSC6_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 2323 #define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk /*!<Filter Scale Configuration bit 6 */
lypinator 0:bb348c97df44 2324 #define CAN_FS1R_FSC7_Pos (7U)
lypinator 0:bb348c97df44 2325 #define CAN_FS1R_FSC7_Msk (0x1U << CAN_FS1R_FSC7_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 2326 #define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk /*!<Filter Scale Configuration bit 7 */
lypinator 0:bb348c97df44 2327 #define CAN_FS1R_FSC8_Pos (8U)
lypinator 0:bb348c97df44 2328 #define CAN_FS1R_FSC8_Msk (0x1U << CAN_FS1R_FSC8_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 2329 #define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk /*!<Filter Scale Configuration bit 8 */
lypinator 0:bb348c97df44 2330 #define CAN_FS1R_FSC9_Pos (9U)
lypinator 0:bb348c97df44 2331 #define CAN_FS1R_FSC9_Msk (0x1U << CAN_FS1R_FSC9_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 2332 #define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk /*!<Filter Scale Configuration bit 9 */
lypinator 0:bb348c97df44 2333 #define CAN_FS1R_FSC10_Pos (10U)
lypinator 0:bb348c97df44 2334 #define CAN_FS1R_FSC10_Msk (0x1U << CAN_FS1R_FSC10_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 2335 #define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk /*!<Filter Scale Configuration bit 10 */
lypinator 0:bb348c97df44 2336 #define CAN_FS1R_FSC11_Pos (11U)
lypinator 0:bb348c97df44 2337 #define CAN_FS1R_FSC11_Msk (0x1U << CAN_FS1R_FSC11_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 2338 #define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk /*!<Filter Scale Configuration bit 11 */
lypinator 0:bb348c97df44 2339 #define CAN_FS1R_FSC12_Pos (12U)
lypinator 0:bb348c97df44 2340 #define CAN_FS1R_FSC12_Msk (0x1U << CAN_FS1R_FSC12_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 2341 #define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk /*!<Filter Scale Configuration bit 12 */
lypinator 0:bb348c97df44 2342 #define CAN_FS1R_FSC13_Pos (13U)
lypinator 0:bb348c97df44 2343 #define CAN_FS1R_FSC13_Msk (0x1U << CAN_FS1R_FSC13_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 2344 #define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk /*!<Filter Scale Configuration bit 13 */
lypinator 0:bb348c97df44 2345 #define CAN_FS1R_FSC14_Pos (14U)
lypinator 0:bb348c97df44 2346 #define CAN_FS1R_FSC14_Msk (0x1U << CAN_FS1R_FSC14_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 2347 #define CAN_FS1R_FSC14 CAN_FS1R_FSC14_Msk /*!<Filter Scale Configuration bit 14 */
lypinator 0:bb348c97df44 2348 #define CAN_FS1R_FSC15_Pos (15U)
lypinator 0:bb348c97df44 2349 #define CAN_FS1R_FSC15_Msk (0x1U << CAN_FS1R_FSC15_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 2350 #define CAN_FS1R_FSC15 CAN_FS1R_FSC15_Msk /*!<Filter Scale Configuration bit 15 */
lypinator 0:bb348c97df44 2351 #define CAN_FS1R_FSC16_Pos (16U)
lypinator 0:bb348c97df44 2352 #define CAN_FS1R_FSC16_Msk (0x1U << CAN_FS1R_FSC16_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 2353 #define CAN_FS1R_FSC16 CAN_FS1R_FSC16_Msk /*!<Filter Scale Configuration bit 16 */
lypinator 0:bb348c97df44 2354 #define CAN_FS1R_FSC17_Pos (17U)
lypinator 0:bb348c97df44 2355 #define CAN_FS1R_FSC17_Msk (0x1U << CAN_FS1R_FSC17_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 2356 #define CAN_FS1R_FSC17 CAN_FS1R_FSC17_Msk /*!<Filter Scale Configuration bit 17 */
lypinator 0:bb348c97df44 2357 #define CAN_FS1R_FSC18_Pos (18U)
lypinator 0:bb348c97df44 2358 #define CAN_FS1R_FSC18_Msk (0x1U << CAN_FS1R_FSC18_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 2359 #define CAN_FS1R_FSC18 CAN_FS1R_FSC18_Msk /*!<Filter Scale Configuration bit 18 */
lypinator 0:bb348c97df44 2360 #define CAN_FS1R_FSC19_Pos (19U)
lypinator 0:bb348c97df44 2361 #define CAN_FS1R_FSC19_Msk (0x1U << CAN_FS1R_FSC19_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 2362 #define CAN_FS1R_FSC19 CAN_FS1R_FSC19_Msk /*!<Filter Scale Configuration bit 19 */
lypinator 0:bb348c97df44 2363 #define CAN_FS1R_FSC20_Pos (20U)
lypinator 0:bb348c97df44 2364 #define CAN_FS1R_FSC20_Msk (0x1U << CAN_FS1R_FSC20_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 2365 #define CAN_FS1R_FSC20 CAN_FS1R_FSC20_Msk /*!<Filter Scale Configuration bit 20 */
lypinator 0:bb348c97df44 2366 #define CAN_FS1R_FSC21_Pos (21U)
lypinator 0:bb348c97df44 2367 #define CAN_FS1R_FSC21_Msk (0x1U << CAN_FS1R_FSC21_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 2368 #define CAN_FS1R_FSC21 CAN_FS1R_FSC21_Msk /*!<Filter Scale Configuration bit 21 */
lypinator 0:bb348c97df44 2369 #define CAN_FS1R_FSC22_Pos (22U)
lypinator 0:bb348c97df44 2370 #define CAN_FS1R_FSC22_Msk (0x1U << CAN_FS1R_FSC22_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 2371 #define CAN_FS1R_FSC22 CAN_FS1R_FSC22_Msk /*!<Filter Scale Configuration bit 22 */
lypinator 0:bb348c97df44 2372 #define CAN_FS1R_FSC23_Pos (23U)
lypinator 0:bb348c97df44 2373 #define CAN_FS1R_FSC23_Msk (0x1U << CAN_FS1R_FSC23_Pos) /*!< 0x00800000 */
lypinator 0:bb348c97df44 2374 #define CAN_FS1R_FSC23 CAN_FS1R_FSC23_Msk /*!<Filter Scale Configuration bit 23 */
lypinator 0:bb348c97df44 2375 #define CAN_FS1R_FSC24_Pos (24U)
lypinator 0:bb348c97df44 2376 #define CAN_FS1R_FSC24_Msk (0x1U << CAN_FS1R_FSC24_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 2377 #define CAN_FS1R_FSC24 CAN_FS1R_FSC24_Msk /*!<Filter Scale Configuration bit 24 */
lypinator 0:bb348c97df44 2378 #define CAN_FS1R_FSC25_Pos (25U)
lypinator 0:bb348c97df44 2379 #define CAN_FS1R_FSC25_Msk (0x1U << CAN_FS1R_FSC25_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 2380 #define CAN_FS1R_FSC25 CAN_FS1R_FSC25_Msk /*!<Filter Scale Configuration bit 25 */
lypinator 0:bb348c97df44 2381 #define CAN_FS1R_FSC26_Pos (26U)
lypinator 0:bb348c97df44 2382 #define CAN_FS1R_FSC26_Msk (0x1U << CAN_FS1R_FSC26_Pos) /*!< 0x04000000 */
lypinator 0:bb348c97df44 2383 #define CAN_FS1R_FSC26 CAN_FS1R_FSC26_Msk /*!<Filter Scale Configuration bit 26 */
lypinator 0:bb348c97df44 2384 #define CAN_FS1R_FSC27_Pos (27U)
lypinator 0:bb348c97df44 2385 #define CAN_FS1R_FSC27_Msk (0x1U << CAN_FS1R_FSC27_Pos) /*!< 0x08000000 */
lypinator 0:bb348c97df44 2386 #define CAN_FS1R_FSC27 CAN_FS1R_FSC27_Msk /*!<Filter Scale Configuration bit 27 */
lypinator 0:bb348c97df44 2387
lypinator 0:bb348c97df44 2388 /****************** Bit definition for CAN_FFA1R register *******************/
lypinator 0:bb348c97df44 2389 #define CAN_FFA1R_FFA_Pos (0U)
lypinator 0:bb348c97df44 2390 #define CAN_FFA1R_FFA_Msk (0xFFFFFFFU << CAN_FFA1R_FFA_Pos) /*!< 0x0FFFFFFF */
lypinator 0:bb348c97df44 2391 #define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk /*!<Filter FIFO Assignment */
lypinator 0:bb348c97df44 2392 #define CAN_FFA1R_FFA0_Pos (0U)
lypinator 0:bb348c97df44 2393 #define CAN_FFA1R_FFA0_Msk (0x1U << CAN_FFA1R_FFA0_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 2394 #define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk /*!<Filter FIFO Assignment bit 0 */
lypinator 0:bb348c97df44 2395 #define CAN_FFA1R_FFA1_Pos (1U)
lypinator 0:bb348c97df44 2396 #define CAN_FFA1R_FFA1_Msk (0x1U << CAN_FFA1R_FFA1_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 2397 #define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk /*!<Filter FIFO Assignment bit 1 */
lypinator 0:bb348c97df44 2398 #define CAN_FFA1R_FFA2_Pos (2U)
lypinator 0:bb348c97df44 2399 #define CAN_FFA1R_FFA2_Msk (0x1U << CAN_FFA1R_FFA2_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 2400 #define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk /*!<Filter FIFO Assignment bit 2 */
lypinator 0:bb348c97df44 2401 #define CAN_FFA1R_FFA3_Pos (3U)
lypinator 0:bb348c97df44 2402 #define CAN_FFA1R_FFA3_Msk (0x1U << CAN_FFA1R_FFA3_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 2403 #define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk /*!<Filter FIFO Assignment bit 3 */
lypinator 0:bb348c97df44 2404 #define CAN_FFA1R_FFA4_Pos (4U)
lypinator 0:bb348c97df44 2405 #define CAN_FFA1R_FFA4_Msk (0x1U << CAN_FFA1R_FFA4_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 2406 #define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk /*!<Filter FIFO Assignment bit 4 */
lypinator 0:bb348c97df44 2407 #define CAN_FFA1R_FFA5_Pos (5U)
lypinator 0:bb348c97df44 2408 #define CAN_FFA1R_FFA5_Msk (0x1U << CAN_FFA1R_FFA5_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 2409 #define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk /*!<Filter FIFO Assignment bit 5 */
lypinator 0:bb348c97df44 2410 #define CAN_FFA1R_FFA6_Pos (6U)
lypinator 0:bb348c97df44 2411 #define CAN_FFA1R_FFA6_Msk (0x1U << CAN_FFA1R_FFA6_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 2412 #define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk /*!<Filter FIFO Assignment bit 6 */
lypinator 0:bb348c97df44 2413 #define CAN_FFA1R_FFA7_Pos (7U)
lypinator 0:bb348c97df44 2414 #define CAN_FFA1R_FFA7_Msk (0x1U << CAN_FFA1R_FFA7_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 2415 #define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk /*!<Filter FIFO Assignment bit 7 */
lypinator 0:bb348c97df44 2416 #define CAN_FFA1R_FFA8_Pos (8U)
lypinator 0:bb348c97df44 2417 #define CAN_FFA1R_FFA8_Msk (0x1U << CAN_FFA1R_FFA8_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 2418 #define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk /*!<Filter FIFO Assignment bit 8 */
lypinator 0:bb348c97df44 2419 #define CAN_FFA1R_FFA9_Pos (9U)
lypinator 0:bb348c97df44 2420 #define CAN_FFA1R_FFA9_Msk (0x1U << CAN_FFA1R_FFA9_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 2421 #define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk /*!<Filter FIFO Assignment bit 9 */
lypinator 0:bb348c97df44 2422 #define CAN_FFA1R_FFA10_Pos (10U)
lypinator 0:bb348c97df44 2423 #define CAN_FFA1R_FFA10_Msk (0x1U << CAN_FFA1R_FFA10_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 2424 #define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk /*!<Filter FIFO Assignment bit 10 */
lypinator 0:bb348c97df44 2425 #define CAN_FFA1R_FFA11_Pos (11U)
lypinator 0:bb348c97df44 2426 #define CAN_FFA1R_FFA11_Msk (0x1U << CAN_FFA1R_FFA11_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 2427 #define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk /*!<Filter FIFO Assignment bit 11 */
lypinator 0:bb348c97df44 2428 #define CAN_FFA1R_FFA12_Pos (12U)
lypinator 0:bb348c97df44 2429 #define CAN_FFA1R_FFA12_Msk (0x1U << CAN_FFA1R_FFA12_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 2430 #define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk /*!<Filter FIFO Assignment bit 12 */
lypinator 0:bb348c97df44 2431 #define CAN_FFA1R_FFA13_Pos (13U)
lypinator 0:bb348c97df44 2432 #define CAN_FFA1R_FFA13_Msk (0x1U << CAN_FFA1R_FFA13_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 2433 #define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk /*!<Filter FIFO Assignment bit 13 */
lypinator 0:bb348c97df44 2434 #define CAN_FFA1R_FFA14_Pos (14U)
lypinator 0:bb348c97df44 2435 #define CAN_FFA1R_FFA14_Msk (0x1U << CAN_FFA1R_FFA14_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 2436 #define CAN_FFA1R_FFA14 CAN_FFA1R_FFA14_Msk /*!<Filter FIFO Assignment bit 14 */
lypinator 0:bb348c97df44 2437 #define CAN_FFA1R_FFA15_Pos (15U)
lypinator 0:bb348c97df44 2438 #define CAN_FFA1R_FFA15_Msk (0x1U << CAN_FFA1R_FFA15_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 2439 #define CAN_FFA1R_FFA15 CAN_FFA1R_FFA15_Msk /*!<Filter FIFO Assignment bit 15 */
lypinator 0:bb348c97df44 2440 #define CAN_FFA1R_FFA16_Pos (16U)
lypinator 0:bb348c97df44 2441 #define CAN_FFA1R_FFA16_Msk (0x1U << CAN_FFA1R_FFA16_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 2442 #define CAN_FFA1R_FFA16 CAN_FFA1R_FFA16_Msk /*!<Filter FIFO Assignment bit 16 */
lypinator 0:bb348c97df44 2443 #define CAN_FFA1R_FFA17_Pos (17U)
lypinator 0:bb348c97df44 2444 #define CAN_FFA1R_FFA17_Msk (0x1U << CAN_FFA1R_FFA17_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 2445 #define CAN_FFA1R_FFA17 CAN_FFA1R_FFA17_Msk /*!<Filter FIFO Assignment bit 17 */
lypinator 0:bb348c97df44 2446 #define CAN_FFA1R_FFA18_Pos (18U)
lypinator 0:bb348c97df44 2447 #define CAN_FFA1R_FFA18_Msk (0x1U << CAN_FFA1R_FFA18_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 2448 #define CAN_FFA1R_FFA18 CAN_FFA1R_FFA18_Msk /*!<Filter FIFO Assignment bit 18 */
lypinator 0:bb348c97df44 2449 #define CAN_FFA1R_FFA19_Pos (19U)
lypinator 0:bb348c97df44 2450 #define CAN_FFA1R_FFA19_Msk (0x1U << CAN_FFA1R_FFA19_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 2451 #define CAN_FFA1R_FFA19 CAN_FFA1R_FFA19_Msk /*!<Filter FIFO Assignment bit 19 */
lypinator 0:bb348c97df44 2452 #define CAN_FFA1R_FFA20_Pos (20U)
lypinator 0:bb348c97df44 2453 #define CAN_FFA1R_FFA20_Msk (0x1U << CAN_FFA1R_FFA20_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 2454 #define CAN_FFA1R_FFA20 CAN_FFA1R_FFA20_Msk /*!<Filter FIFO Assignment bit 20 */
lypinator 0:bb348c97df44 2455 #define CAN_FFA1R_FFA21_Pos (21U)
lypinator 0:bb348c97df44 2456 #define CAN_FFA1R_FFA21_Msk (0x1U << CAN_FFA1R_FFA21_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 2457 #define CAN_FFA1R_FFA21 CAN_FFA1R_FFA21_Msk /*!<Filter FIFO Assignment bit 21 */
lypinator 0:bb348c97df44 2458 #define CAN_FFA1R_FFA22_Pos (22U)
lypinator 0:bb348c97df44 2459 #define CAN_FFA1R_FFA22_Msk (0x1U << CAN_FFA1R_FFA22_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 2460 #define CAN_FFA1R_FFA22 CAN_FFA1R_FFA22_Msk /*!<Filter FIFO Assignment bit 22 */
lypinator 0:bb348c97df44 2461 #define CAN_FFA1R_FFA23_Pos (23U)
lypinator 0:bb348c97df44 2462 #define CAN_FFA1R_FFA23_Msk (0x1U << CAN_FFA1R_FFA23_Pos) /*!< 0x00800000 */
lypinator 0:bb348c97df44 2463 #define CAN_FFA1R_FFA23 CAN_FFA1R_FFA23_Msk /*!<Filter FIFO Assignment bit 23 */
lypinator 0:bb348c97df44 2464 #define CAN_FFA1R_FFA24_Pos (24U)
lypinator 0:bb348c97df44 2465 #define CAN_FFA1R_FFA24_Msk (0x1U << CAN_FFA1R_FFA24_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 2466 #define CAN_FFA1R_FFA24 CAN_FFA1R_FFA24_Msk /*!<Filter FIFO Assignment bit 24 */
lypinator 0:bb348c97df44 2467 #define CAN_FFA1R_FFA25_Pos (25U)
lypinator 0:bb348c97df44 2468 #define CAN_FFA1R_FFA25_Msk (0x1U << CAN_FFA1R_FFA25_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 2469 #define CAN_FFA1R_FFA25 CAN_FFA1R_FFA25_Msk /*!<Filter FIFO Assignment bit 25 */
lypinator 0:bb348c97df44 2470 #define CAN_FFA1R_FFA26_Pos (26U)
lypinator 0:bb348c97df44 2471 #define CAN_FFA1R_FFA26_Msk (0x1U << CAN_FFA1R_FFA26_Pos) /*!< 0x04000000 */
lypinator 0:bb348c97df44 2472 #define CAN_FFA1R_FFA26 CAN_FFA1R_FFA26_Msk /*!<Filter FIFO Assignment bit 26 */
lypinator 0:bb348c97df44 2473 #define CAN_FFA1R_FFA27_Pos (27U)
lypinator 0:bb348c97df44 2474 #define CAN_FFA1R_FFA27_Msk (0x1U << CAN_FFA1R_FFA27_Pos) /*!< 0x08000000 */
lypinator 0:bb348c97df44 2475 #define CAN_FFA1R_FFA27 CAN_FFA1R_FFA27_Msk /*!<Filter FIFO Assignment bit 27 */
lypinator 0:bb348c97df44 2476
lypinator 0:bb348c97df44 2477 /******************* Bit definition for CAN_FA1R register *******************/
lypinator 0:bb348c97df44 2478 #define CAN_FA1R_FACT_Pos (0U)
lypinator 0:bb348c97df44 2479 #define CAN_FA1R_FACT_Msk (0xFFFFFFFU << CAN_FA1R_FACT_Pos) /*!< 0x0FFFFFFF */
lypinator 0:bb348c97df44 2480 #define CAN_FA1R_FACT CAN_FA1R_FACT_Msk /*!<Filter Active */
lypinator 0:bb348c97df44 2481 #define CAN_FA1R_FACT0_Pos (0U)
lypinator 0:bb348c97df44 2482 #define CAN_FA1R_FACT0_Msk (0x1U << CAN_FA1R_FACT0_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 2483 #define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk /*!<Filter Active bit 0 */
lypinator 0:bb348c97df44 2484 #define CAN_FA1R_FACT1_Pos (1U)
lypinator 0:bb348c97df44 2485 #define CAN_FA1R_FACT1_Msk (0x1U << CAN_FA1R_FACT1_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 2486 #define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk /*!<Filter Active bit 1 */
lypinator 0:bb348c97df44 2487 #define CAN_FA1R_FACT2_Pos (2U)
lypinator 0:bb348c97df44 2488 #define CAN_FA1R_FACT2_Msk (0x1U << CAN_FA1R_FACT2_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 2489 #define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk /*!<Filter Active bit 2 */
lypinator 0:bb348c97df44 2490 #define CAN_FA1R_FACT3_Pos (3U)
lypinator 0:bb348c97df44 2491 #define CAN_FA1R_FACT3_Msk (0x1U << CAN_FA1R_FACT3_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 2492 #define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk /*!<Filter Active bit 3 */
lypinator 0:bb348c97df44 2493 #define CAN_FA1R_FACT4_Pos (4U)
lypinator 0:bb348c97df44 2494 #define CAN_FA1R_FACT4_Msk (0x1U << CAN_FA1R_FACT4_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 2495 #define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk /*!<Filter Active bit 4 */
lypinator 0:bb348c97df44 2496 #define CAN_FA1R_FACT5_Pos (5U)
lypinator 0:bb348c97df44 2497 #define CAN_FA1R_FACT5_Msk (0x1U << CAN_FA1R_FACT5_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 2498 #define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk /*!<Filter Active bit 5 */
lypinator 0:bb348c97df44 2499 #define CAN_FA1R_FACT6_Pos (6U)
lypinator 0:bb348c97df44 2500 #define CAN_FA1R_FACT6_Msk (0x1U << CAN_FA1R_FACT6_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 2501 #define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk /*!<Filter Active bit 6 */
lypinator 0:bb348c97df44 2502 #define CAN_FA1R_FACT7_Pos (7U)
lypinator 0:bb348c97df44 2503 #define CAN_FA1R_FACT7_Msk (0x1U << CAN_FA1R_FACT7_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 2504 #define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk /*!<Filter Active bit 7 */
lypinator 0:bb348c97df44 2505 #define CAN_FA1R_FACT8_Pos (8U)
lypinator 0:bb348c97df44 2506 #define CAN_FA1R_FACT8_Msk (0x1U << CAN_FA1R_FACT8_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 2507 #define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk /*!<Filter Active bit 8 */
lypinator 0:bb348c97df44 2508 #define CAN_FA1R_FACT9_Pos (9U)
lypinator 0:bb348c97df44 2509 #define CAN_FA1R_FACT9_Msk (0x1U << CAN_FA1R_FACT9_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 2510 #define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk /*!<Filter Active bit 9 */
lypinator 0:bb348c97df44 2511 #define CAN_FA1R_FACT10_Pos (10U)
lypinator 0:bb348c97df44 2512 #define CAN_FA1R_FACT10_Msk (0x1U << CAN_FA1R_FACT10_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 2513 #define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk /*!<Filter Active bit 10 */
lypinator 0:bb348c97df44 2514 #define CAN_FA1R_FACT11_Pos (11U)
lypinator 0:bb348c97df44 2515 #define CAN_FA1R_FACT11_Msk (0x1U << CAN_FA1R_FACT11_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 2516 #define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk /*!<Filter Active bit 11 */
lypinator 0:bb348c97df44 2517 #define CAN_FA1R_FACT12_Pos (12U)
lypinator 0:bb348c97df44 2518 #define CAN_FA1R_FACT12_Msk (0x1U << CAN_FA1R_FACT12_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 2519 #define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk /*!<Filter Active bit 12 */
lypinator 0:bb348c97df44 2520 #define CAN_FA1R_FACT13_Pos (13U)
lypinator 0:bb348c97df44 2521 #define CAN_FA1R_FACT13_Msk (0x1U << CAN_FA1R_FACT13_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 2522 #define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk /*!<Filter Active bit 13 */
lypinator 0:bb348c97df44 2523 #define CAN_FA1R_FACT14_Pos (14U)
lypinator 0:bb348c97df44 2524 #define CAN_FA1R_FACT14_Msk (0x1U << CAN_FA1R_FACT14_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 2525 #define CAN_FA1R_FACT14 CAN_FA1R_FACT14_Msk /*!<Filter Active bit 14 */
lypinator 0:bb348c97df44 2526 #define CAN_FA1R_FACT15_Pos (15U)
lypinator 0:bb348c97df44 2527 #define CAN_FA1R_FACT15_Msk (0x1U << CAN_FA1R_FACT15_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 2528 #define CAN_FA1R_FACT15 CAN_FA1R_FACT15_Msk /*!<Filter Active bit 15 */
lypinator 0:bb348c97df44 2529 #define CAN_FA1R_FACT16_Pos (16U)
lypinator 0:bb348c97df44 2530 #define CAN_FA1R_FACT16_Msk (0x1U << CAN_FA1R_FACT16_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 2531 #define CAN_FA1R_FACT16 CAN_FA1R_FACT16_Msk /*!<Filter Active bit 16 */
lypinator 0:bb348c97df44 2532 #define CAN_FA1R_FACT17_Pos (17U)
lypinator 0:bb348c97df44 2533 #define CAN_FA1R_FACT17_Msk (0x1U << CAN_FA1R_FACT17_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 2534 #define CAN_FA1R_FACT17 CAN_FA1R_FACT17_Msk /*!<Filter Active bit 17 */
lypinator 0:bb348c97df44 2535 #define CAN_FA1R_FACT18_Pos (18U)
lypinator 0:bb348c97df44 2536 #define CAN_FA1R_FACT18_Msk (0x1U << CAN_FA1R_FACT18_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 2537 #define CAN_FA1R_FACT18 CAN_FA1R_FACT18_Msk /*!<Filter Active bit 18 */
lypinator 0:bb348c97df44 2538 #define CAN_FA1R_FACT19_Pos (19U)
lypinator 0:bb348c97df44 2539 #define CAN_FA1R_FACT19_Msk (0x1U << CAN_FA1R_FACT19_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 2540 #define CAN_FA1R_FACT19 CAN_FA1R_FACT19_Msk /*!<Filter Active bit 19 */
lypinator 0:bb348c97df44 2541 #define CAN_FA1R_FACT20_Pos (20U)
lypinator 0:bb348c97df44 2542 #define CAN_FA1R_FACT20_Msk (0x1U << CAN_FA1R_FACT20_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 2543 #define CAN_FA1R_FACT20 CAN_FA1R_FACT20_Msk /*!<Filter Active bit 20 */
lypinator 0:bb348c97df44 2544 #define CAN_FA1R_FACT21_Pos (21U)
lypinator 0:bb348c97df44 2545 #define CAN_FA1R_FACT21_Msk (0x1U << CAN_FA1R_FACT21_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 2546 #define CAN_FA1R_FACT21 CAN_FA1R_FACT21_Msk /*!<Filter Active bit 21 */
lypinator 0:bb348c97df44 2547 #define CAN_FA1R_FACT22_Pos (22U)
lypinator 0:bb348c97df44 2548 #define CAN_FA1R_FACT22_Msk (0x1U << CAN_FA1R_FACT22_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 2549 #define CAN_FA1R_FACT22 CAN_FA1R_FACT22_Msk /*!<Filter Active bit 22 */
lypinator 0:bb348c97df44 2550 #define CAN_FA1R_FACT23_Pos (23U)
lypinator 0:bb348c97df44 2551 #define CAN_FA1R_FACT23_Msk (0x1U << CAN_FA1R_FACT23_Pos) /*!< 0x00800000 */
lypinator 0:bb348c97df44 2552 #define CAN_FA1R_FACT23 CAN_FA1R_FACT23_Msk /*!<Filter Active bit 23 */
lypinator 0:bb348c97df44 2553 #define CAN_FA1R_FACT24_Pos (24U)
lypinator 0:bb348c97df44 2554 #define CAN_FA1R_FACT24_Msk (0x1U << CAN_FA1R_FACT24_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 2555 #define CAN_FA1R_FACT24 CAN_FA1R_FACT24_Msk /*!<Filter Active bit 24 */
lypinator 0:bb348c97df44 2556 #define CAN_FA1R_FACT25_Pos (25U)
lypinator 0:bb348c97df44 2557 #define CAN_FA1R_FACT25_Msk (0x1U << CAN_FA1R_FACT25_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 2558 #define CAN_FA1R_FACT25 CAN_FA1R_FACT25_Msk /*!<Filter Active bit 25 */
lypinator 0:bb348c97df44 2559 #define CAN_FA1R_FACT26_Pos (26U)
lypinator 0:bb348c97df44 2560 #define CAN_FA1R_FACT26_Msk (0x1U << CAN_FA1R_FACT26_Pos) /*!< 0x04000000 */
lypinator 0:bb348c97df44 2561 #define CAN_FA1R_FACT26 CAN_FA1R_FACT26_Msk /*!<Filter Active bit 26 */
lypinator 0:bb348c97df44 2562 #define CAN_FA1R_FACT27_Pos (27U)
lypinator 0:bb348c97df44 2563 #define CAN_FA1R_FACT27_Msk (0x1U << CAN_FA1R_FACT27_Pos) /*!< 0x08000000 */
lypinator 0:bb348c97df44 2564 #define CAN_FA1R_FACT27 CAN_FA1R_FACT27_Msk /*!<Filter Active bit 27 */
lypinator 0:bb348c97df44 2565
lypinator 0:bb348c97df44 2566
lypinator 0:bb348c97df44 2567 /******************* Bit definition for CAN_F0R1 register *******************/
lypinator 0:bb348c97df44 2568 #define CAN_F0R1_FB0_Pos (0U)
lypinator 0:bb348c97df44 2569 #define CAN_F0R1_FB0_Msk (0x1U << CAN_F0R1_FB0_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 2570 #define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk /*!<Filter bit 0 */
lypinator 0:bb348c97df44 2571 #define CAN_F0R1_FB1_Pos (1U)
lypinator 0:bb348c97df44 2572 #define CAN_F0R1_FB1_Msk (0x1U << CAN_F0R1_FB1_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 2573 #define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk /*!<Filter bit 1 */
lypinator 0:bb348c97df44 2574 #define CAN_F0R1_FB2_Pos (2U)
lypinator 0:bb348c97df44 2575 #define CAN_F0R1_FB2_Msk (0x1U << CAN_F0R1_FB2_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 2576 #define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk /*!<Filter bit 2 */
lypinator 0:bb348c97df44 2577 #define CAN_F0R1_FB3_Pos (3U)
lypinator 0:bb348c97df44 2578 #define CAN_F0R1_FB3_Msk (0x1U << CAN_F0R1_FB3_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 2579 #define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk /*!<Filter bit 3 */
lypinator 0:bb348c97df44 2580 #define CAN_F0R1_FB4_Pos (4U)
lypinator 0:bb348c97df44 2581 #define CAN_F0R1_FB4_Msk (0x1U << CAN_F0R1_FB4_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 2582 #define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk /*!<Filter bit 4 */
lypinator 0:bb348c97df44 2583 #define CAN_F0R1_FB5_Pos (5U)
lypinator 0:bb348c97df44 2584 #define CAN_F0R1_FB5_Msk (0x1U << CAN_F0R1_FB5_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 2585 #define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk /*!<Filter bit 5 */
lypinator 0:bb348c97df44 2586 #define CAN_F0R1_FB6_Pos (6U)
lypinator 0:bb348c97df44 2587 #define CAN_F0R1_FB6_Msk (0x1U << CAN_F0R1_FB6_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 2588 #define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk /*!<Filter bit 6 */
lypinator 0:bb348c97df44 2589 #define CAN_F0R1_FB7_Pos (7U)
lypinator 0:bb348c97df44 2590 #define CAN_F0R1_FB7_Msk (0x1U << CAN_F0R1_FB7_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 2591 #define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk /*!<Filter bit 7 */
lypinator 0:bb348c97df44 2592 #define CAN_F0R1_FB8_Pos (8U)
lypinator 0:bb348c97df44 2593 #define CAN_F0R1_FB8_Msk (0x1U << CAN_F0R1_FB8_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 2594 #define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk /*!<Filter bit 8 */
lypinator 0:bb348c97df44 2595 #define CAN_F0R1_FB9_Pos (9U)
lypinator 0:bb348c97df44 2596 #define CAN_F0R1_FB9_Msk (0x1U << CAN_F0R1_FB9_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 2597 #define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk /*!<Filter bit 9 */
lypinator 0:bb348c97df44 2598 #define CAN_F0R1_FB10_Pos (10U)
lypinator 0:bb348c97df44 2599 #define CAN_F0R1_FB10_Msk (0x1U << CAN_F0R1_FB10_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 2600 #define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk /*!<Filter bit 10 */
lypinator 0:bb348c97df44 2601 #define CAN_F0R1_FB11_Pos (11U)
lypinator 0:bb348c97df44 2602 #define CAN_F0R1_FB11_Msk (0x1U << CAN_F0R1_FB11_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 2603 #define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk /*!<Filter bit 11 */
lypinator 0:bb348c97df44 2604 #define CAN_F0R1_FB12_Pos (12U)
lypinator 0:bb348c97df44 2605 #define CAN_F0R1_FB12_Msk (0x1U << CAN_F0R1_FB12_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 2606 #define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk /*!<Filter bit 12 */
lypinator 0:bb348c97df44 2607 #define CAN_F0R1_FB13_Pos (13U)
lypinator 0:bb348c97df44 2608 #define CAN_F0R1_FB13_Msk (0x1U << CAN_F0R1_FB13_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 2609 #define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk /*!<Filter bit 13 */
lypinator 0:bb348c97df44 2610 #define CAN_F0R1_FB14_Pos (14U)
lypinator 0:bb348c97df44 2611 #define CAN_F0R1_FB14_Msk (0x1U << CAN_F0R1_FB14_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 2612 #define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk /*!<Filter bit 14 */
lypinator 0:bb348c97df44 2613 #define CAN_F0R1_FB15_Pos (15U)
lypinator 0:bb348c97df44 2614 #define CAN_F0R1_FB15_Msk (0x1U << CAN_F0R1_FB15_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 2615 #define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk /*!<Filter bit 15 */
lypinator 0:bb348c97df44 2616 #define CAN_F0R1_FB16_Pos (16U)
lypinator 0:bb348c97df44 2617 #define CAN_F0R1_FB16_Msk (0x1U << CAN_F0R1_FB16_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 2618 #define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk /*!<Filter bit 16 */
lypinator 0:bb348c97df44 2619 #define CAN_F0R1_FB17_Pos (17U)
lypinator 0:bb348c97df44 2620 #define CAN_F0R1_FB17_Msk (0x1U << CAN_F0R1_FB17_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 2621 #define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk /*!<Filter bit 17 */
lypinator 0:bb348c97df44 2622 #define CAN_F0R1_FB18_Pos (18U)
lypinator 0:bb348c97df44 2623 #define CAN_F0R1_FB18_Msk (0x1U << CAN_F0R1_FB18_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 2624 #define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk /*!<Filter bit 18 */
lypinator 0:bb348c97df44 2625 #define CAN_F0R1_FB19_Pos (19U)
lypinator 0:bb348c97df44 2626 #define CAN_F0R1_FB19_Msk (0x1U << CAN_F0R1_FB19_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 2627 #define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk /*!<Filter bit 19 */
lypinator 0:bb348c97df44 2628 #define CAN_F0R1_FB20_Pos (20U)
lypinator 0:bb348c97df44 2629 #define CAN_F0R1_FB20_Msk (0x1U << CAN_F0R1_FB20_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 2630 #define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk /*!<Filter bit 20 */
lypinator 0:bb348c97df44 2631 #define CAN_F0R1_FB21_Pos (21U)
lypinator 0:bb348c97df44 2632 #define CAN_F0R1_FB21_Msk (0x1U << CAN_F0R1_FB21_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 2633 #define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk /*!<Filter bit 21 */
lypinator 0:bb348c97df44 2634 #define CAN_F0R1_FB22_Pos (22U)
lypinator 0:bb348c97df44 2635 #define CAN_F0R1_FB22_Msk (0x1U << CAN_F0R1_FB22_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 2636 #define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk /*!<Filter bit 22 */
lypinator 0:bb348c97df44 2637 #define CAN_F0R1_FB23_Pos (23U)
lypinator 0:bb348c97df44 2638 #define CAN_F0R1_FB23_Msk (0x1U << CAN_F0R1_FB23_Pos) /*!< 0x00800000 */
lypinator 0:bb348c97df44 2639 #define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk /*!<Filter bit 23 */
lypinator 0:bb348c97df44 2640 #define CAN_F0R1_FB24_Pos (24U)
lypinator 0:bb348c97df44 2641 #define CAN_F0R1_FB24_Msk (0x1U << CAN_F0R1_FB24_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 2642 #define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk /*!<Filter bit 24 */
lypinator 0:bb348c97df44 2643 #define CAN_F0R1_FB25_Pos (25U)
lypinator 0:bb348c97df44 2644 #define CAN_F0R1_FB25_Msk (0x1U << CAN_F0R1_FB25_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 2645 #define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk /*!<Filter bit 25 */
lypinator 0:bb348c97df44 2646 #define CAN_F0R1_FB26_Pos (26U)
lypinator 0:bb348c97df44 2647 #define CAN_F0R1_FB26_Msk (0x1U << CAN_F0R1_FB26_Pos) /*!< 0x04000000 */
lypinator 0:bb348c97df44 2648 #define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk /*!<Filter bit 26 */
lypinator 0:bb348c97df44 2649 #define CAN_F0R1_FB27_Pos (27U)
lypinator 0:bb348c97df44 2650 #define CAN_F0R1_FB27_Msk (0x1U << CAN_F0R1_FB27_Pos) /*!< 0x08000000 */
lypinator 0:bb348c97df44 2651 #define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk /*!<Filter bit 27 */
lypinator 0:bb348c97df44 2652 #define CAN_F0R1_FB28_Pos (28U)
lypinator 0:bb348c97df44 2653 #define CAN_F0R1_FB28_Msk (0x1U << CAN_F0R1_FB28_Pos) /*!< 0x10000000 */
lypinator 0:bb348c97df44 2654 #define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk /*!<Filter bit 28 */
lypinator 0:bb348c97df44 2655 #define CAN_F0R1_FB29_Pos (29U)
lypinator 0:bb348c97df44 2656 #define CAN_F0R1_FB29_Msk (0x1U << CAN_F0R1_FB29_Pos) /*!< 0x20000000 */
lypinator 0:bb348c97df44 2657 #define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk /*!<Filter bit 29 */
lypinator 0:bb348c97df44 2658 #define CAN_F0R1_FB30_Pos (30U)
lypinator 0:bb348c97df44 2659 #define CAN_F0R1_FB30_Msk (0x1U << CAN_F0R1_FB30_Pos) /*!< 0x40000000 */
lypinator 0:bb348c97df44 2660 #define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk /*!<Filter bit 30 */
lypinator 0:bb348c97df44 2661 #define CAN_F0R1_FB31_Pos (31U)
lypinator 0:bb348c97df44 2662 #define CAN_F0R1_FB31_Msk (0x1U << CAN_F0R1_FB31_Pos) /*!< 0x80000000 */
lypinator 0:bb348c97df44 2663 #define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk /*!<Filter bit 31 */
lypinator 0:bb348c97df44 2664
lypinator 0:bb348c97df44 2665 /******************* Bit definition for CAN_F1R1 register *******************/
lypinator 0:bb348c97df44 2666 #define CAN_F1R1_FB0_Pos (0U)
lypinator 0:bb348c97df44 2667 #define CAN_F1R1_FB0_Msk (0x1U << CAN_F1R1_FB0_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 2668 #define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk /*!<Filter bit 0 */
lypinator 0:bb348c97df44 2669 #define CAN_F1R1_FB1_Pos (1U)
lypinator 0:bb348c97df44 2670 #define CAN_F1R1_FB1_Msk (0x1U << CAN_F1R1_FB1_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 2671 #define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk /*!<Filter bit 1 */
lypinator 0:bb348c97df44 2672 #define CAN_F1R1_FB2_Pos (2U)
lypinator 0:bb348c97df44 2673 #define CAN_F1R1_FB2_Msk (0x1U << CAN_F1R1_FB2_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 2674 #define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk /*!<Filter bit 2 */
lypinator 0:bb348c97df44 2675 #define CAN_F1R1_FB3_Pos (3U)
lypinator 0:bb348c97df44 2676 #define CAN_F1R1_FB3_Msk (0x1U << CAN_F1R1_FB3_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 2677 #define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk /*!<Filter bit 3 */
lypinator 0:bb348c97df44 2678 #define CAN_F1R1_FB4_Pos (4U)
lypinator 0:bb348c97df44 2679 #define CAN_F1R1_FB4_Msk (0x1U << CAN_F1R1_FB4_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 2680 #define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk /*!<Filter bit 4 */
lypinator 0:bb348c97df44 2681 #define CAN_F1R1_FB5_Pos (5U)
lypinator 0:bb348c97df44 2682 #define CAN_F1R1_FB5_Msk (0x1U << CAN_F1R1_FB5_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 2683 #define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk /*!<Filter bit 5 */
lypinator 0:bb348c97df44 2684 #define CAN_F1R1_FB6_Pos (6U)
lypinator 0:bb348c97df44 2685 #define CAN_F1R1_FB6_Msk (0x1U << CAN_F1R1_FB6_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 2686 #define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk /*!<Filter bit 6 */
lypinator 0:bb348c97df44 2687 #define CAN_F1R1_FB7_Pos (7U)
lypinator 0:bb348c97df44 2688 #define CAN_F1R1_FB7_Msk (0x1U << CAN_F1R1_FB7_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 2689 #define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk /*!<Filter bit 7 */
lypinator 0:bb348c97df44 2690 #define CAN_F1R1_FB8_Pos (8U)
lypinator 0:bb348c97df44 2691 #define CAN_F1R1_FB8_Msk (0x1U << CAN_F1R1_FB8_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 2692 #define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk /*!<Filter bit 8 */
lypinator 0:bb348c97df44 2693 #define CAN_F1R1_FB9_Pos (9U)
lypinator 0:bb348c97df44 2694 #define CAN_F1R1_FB9_Msk (0x1U << CAN_F1R1_FB9_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 2695 #define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk /*!<Filter bit 9 */
lypinator 0:bb348c97df44 2696 #define CAN_F1R1_FB10_Pos (10U)
lypinator 0:bb348c97df44 2697 #define CAN_F1R1_FB10_Msk (0x1U << CAN_F1R1_FB10_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 2698 #define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk /*!<Filter bit 10 */
lypinator 0:bb348c97df44 2699 #define CAN_F1R1_FB11_Pos (11U)
lypinator 0:bb348c97df44 2700 #define CAN_F1R1_FB11_Msk (0x1U << CAN_F1R1_FB11_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 2701 #define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk /*!<Filter bit 11 */
lypinator 0:bb348c97df44 2702 #define CAN_F1R1_FB12_Pos (12U)
lypinator 0:bb348c97df44 2703 #define CAN_F1R1_FB12_Msk (0x1U << CAN_F1R1_FB12_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 2704 #define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk /*!<Filter bit 12 */
lypinator 0:bb348c97df44 2705 #define CAN_F1R1_FB13_Pos (13U)
lypinator 0:bb348c97df44 2706 #define CAN_F1R1_FB13_Msk (0x1U << CAN_F1R1_FB13_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 2707 #define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk /*!<Filter bit 13 */
lypinator 0:bb348c97df44 2708 #define CAN_F1R1_FB14_Pos (14U)
lypinator 0:bb348c97df44 2709 #define CAN_F1R1_FB14_Msk (0x1U << CAN_F1R1_FB14_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 2710 #define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk /*!<Filter bit 14 */
lypinator 0:bb348c97df44 2711 #define CAN_F1R1_FB15_Pos (15U)
lypinator 0:bb348c97df44 2712 #define CAN_F1R1_FB15_Msk (0x1U << CAN_F1R1_FB15_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 2713 #define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk /*!<Filter bit 15 */
lypinator 0:bb348c97df44 2714 #define CAN_F1R1_FB16_Pos (16U)
lypinator 0:bb348c97df44 2715 #define CAN_F1R1_FB16_Msk (0x1U << CAN_F1R1_FB16_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 2716 #define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk /*!<Filter bit 16 */
lypinator 0:bb348c97df44 2717 #define CAN_F1R1_FB17_Pos (17U)
lypinator 0:bb348c97df44 2718 #define CAN_F1R1_FB17_Msk (0x1U << CAN_F1R1_FB17_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 2719 #define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk /*!<Filter bit 17 */
lypinator 0:bb348c97df44 2720 #define CAN_F1R1_FB18_Pos (18U)
lypinator 0:bb348c97df44 2721 #define CAN_F1R1_FB18_Msk (0x1U << CAN_F1R1_FB18_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 2722 #define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk /*!<Filter bit 18 */
lypinator 0:bb348c97df44 2723 #define CAN_F1R1_FB19_Pos (19U)
lypinator 0:bb348c97df44 2724 #define CAN_F1R1_FB19_Msk (0x1U << CAN_F1R1_FB19_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 2725 #define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk /*!<Filter bit 19 */
lypinator 0:bb348c97df44 2726 #define CAN_F1R1_FB20_Pos (20U)
lypinator 0:bb348c97df44 2727 #define CAN_F1R1_FB20_Msk (0x1U << CAN_F1R1_FB20_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 2728 #define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk /*!<Filter bit 20 */
lypinator 0:bb348c97df44 2729 #define CAN_F1R1_FB21_Pos (21U)
lypinator 0:bb348c97df44 2730 #define CAN_F1R1_FB21_Msk (0x1U << CAN_F1R1_FB21_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 2731 #define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk /*!<Filter bit 21 */
lypinator 0:bb348c97df44 2732 #define CAN_F1R1_FB22_Pos (22U)
lypinator 0:bb348c97df44 2733 #define CAN_F1R1_FB22_Msk (0x1U << CAN_F1R1_FB22_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 2734 #define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk /*!<Filter bit 22 */
lypinator 0:bb348c97df44 2735 #define CAN_F1R1_FB23_Pos (23U)
lypinator 0:bb348c97df44 2736 #define CAN_F1R1_FB23_Msk (0x1U << CAN_F1R1_FB23_Pos) /*!< 0x00800000 */
lypinator 0:bb348c97df44 2737 #define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk /*!<Filter bit 23 */
lypinator 0:bb348c97df44 2738 #define CAN_F1R1_FB24_Pos (24U)
lypinator 0:bb348c97df44 2739 #define CAN_F1R1_FB24_Msk (0x1U << CAN_F1R1_FB24_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 2740 #define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk /*!<Filter bit 24 */
lypinator 0:bb348c97df44 2741 #define CAN_F1R1_FB25_Pos (25U)
lypinator 0:bb348c97df44 2742 #define CAN_F1R1_FB25_Msk (0x1U << CAN_F1R1_FB25_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 2743 #define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk /*!<Filter bit 25 */
lypinator 0:bb348c97df44 2744 #define CAN_F1R1_FB26_Pos (26U)
lypinator 0:bb348c97df44 2745 #define CAN_F1R1_FB26_Msk (0x1U << CAN_F1R1_FB26_Pos) /*!< 0x04000000 */
lypinator 0:bb348c97df44 2746 #define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk /*!<Filter bit 26 */
lypinator 0:bb348c97df44 2747 #define CAN_F1R1_FB27_Pos (27U)
lypinator 0:bb348c97df44 2748 #define CAN_F1R1_FB27_Msk (0x1U << CAN_F1R1_FB27_Pos) /*!< 0x08000000 */
lypinator 0:bb348c97df44 2749 #define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk /*!<Filter bit 27 */
lypinator 0:bb348c97df44 2750 #define CAN_F1R1_FB28_Pos (28U)
lypinator 0:bb348c97df44 2751 #define CAN_F1R1_FB28_Msk (0x1U << CAN_F1R1_FB28_Pos) /*!< 0x10000000 */
lypinator 0:bb348c97df44 2752 #define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk /*!<Filter bit 28 */
lypinator 0:bb348c97df44 2753 #define CAN_F1R1_FB29_Pos (29U)
lypinator 0:bb348c97df44 2754 #define CAN_F1R1_FB29_Msk (0x1U << CAN_F1R1_FB29_Pos) /*!< 0x20000000 */
lypinator 0:bb348c97df44 2755 #define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk /*!<Filter bit 29 */
lypinator 0:bb348c97df44 2756 #define CAN_F1R1_FB30_Pos (30U)
lypinator 0:bb348c97df44 2757 #define CAN_F1R1_FB30_Msk (0x1U << CAN_F1R1_FB30_Pos) /*!< 0x40000000 */
lypinator 0:bb348c97df44 2758 #define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk /*!<Filter bit 30 */
lypinator 0:bb348c97df44 2759 #define CAN_F1R1_FB31_Pos (31U)
lypinator 0:bb348c97df44 2760 #define CAN_F1R1_FB31_Msk (0x1U << CAN_F1R1_FB31_Pos) /*!< 0x80000000 */
lypinator 0:bb348c97df44 2761 #define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk /*!<Filter bit 31 */
lypinator 0:bb348c97df44 2762
lypinator 0:bb348c97df44 2763 /******************* Bit definition for CAN_F2R1 register *******************/
lypinator 0:bb348c97df44 2764 #define CAN_F2R1_FB0_Pos (0U)
lypinator 0:bb348c97df44 2765 #define CAN_F2R1_FB0_Msk (0x1U << CAN_F2R1_FB0_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 2766 #define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk /*!<Filter bit 0 */
lypinator 0:bb348c97df44 2767 #define CAN_F2R1_FB1_Pos (1U)
lypinator 0:bb348c97df44 2768 #define CAN_F2R1_FB1_Msk (0x1U << CAN_F2R1_FB1_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 2769 #define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk /*!<Filter bit 1 */
lypinator 0:bb348c97df44 2770 #define CAN_F2R1_FB2_Pos (2U)
lypinator 0:bb348c97df44 2771 #define CAN_F2R1_FB2_Msk (0x1U << CAN_F2R1_FB2_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 2772 #define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk /*!<Filter bit 2 */
lypinator 0:bb348c97df44 2773 #define CAN_F2R1_FB3_Pos (3U)
lypinator 0:bb348c97df44 2774 #define CAN_F2R1_FB3_Msk (0x1U << CAN_F2R1_FB3_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 2775 #define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk /*!<Filter bit 3 */
lypinator 0:bb348c97df44 2776 #define CAN_F2R1_FB4_Pos (4U)
lypinator 0:bb348c97df44 2777 #define CAN_F2R1_FB4_Msk (0x1U << CAN_F2R1_FB4_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 2778 #define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk /*!<Filter bit 4 */
lypinator 0:bb348c97df44 2779 #define CAN_F2R1_FB5_Pos (5U)
lypinator 0:bb348c97df44 2780 #define CAN_F2R1_FB5_Msk (0x1U << CAN_F2R1_FB5_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 2781 #define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk /*!<Filter bit 5 */
lypinator 0:bb348c97df44 2782 #define CAN_F2R1_FB6_Pos (6U)
lypinator 0:bb348c97df44 2783 #define CAN_F2R1_FB6_Msk (0x1U << CAN_F2R1_FB6_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 2784 #define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk /*!<Filter bit 6 */
lypinator 0:bb348c97df44 2785 #define CAN_F2R1_FB7_Pos (7U)
lypinator 0:bb348c97df44 2786 #define CAN_F2R1_FB7_Msk (0x1U << CAN_F2R1_FB7_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 2787 #define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk /*!<Filter bit 7 */
lypinator 0:bb348c97df44 2788 #define CAN_F2R1_FB8_Pos (8U)
lypinator 0:bb348c97df44 2789 #define CAN_F2R1_FB8_Msk (0x1U << CAN_F2R1_FB8_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 2790 #define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk /*!<Filter bit 8 */
lypinator 0:bb348c97df44 2791 #define CAN_F2R1_FB9_Pos (9U)
lypinator 0:bb348c97df44 2792 #define CAN_F2R1_FB9_Msk (0x1U << CAN_F2R1_FB9_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 2793 #define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk /*!<Filter bit 9 */
lypinator 0:bb348c97df44 2794 #define CAN_F2R1_FB10_Pos (10U)
lypinator 0:bb348c97df44 2795 #define CAN_F2R1_FB10_Msk (0x1U << CAN_F2R1_FB10_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 2796 #define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk /*!<Filter bit 10 */
lypinator 0:bb348c97df44 2797 #define CAN_F2R1_FB11_Pos (11U)
lypinator 0:bb348c97df44 2798 #define CAN_F2R1_FB11_Msk (0x1U << CAN_F2R1_FB11_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 2799 #define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk /*!<Filter bit 11 */
lypinator 0:bb348c97df44 2800 #define CAN_F2R1_FB12_Pos (12U)
lypinator 0:bb348c97df44 2801 #define CAN_F2R1_FB12_Msk (0x1U << CAN_F2R1_FB12_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 2802 #define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk /*!<Filter bit 12 */
lypinator 0:bb348c97df44 2803 #define CAN_F2R1_FB13_Pos (13U)
lypinator 0:bb348c97df44 2804 #define CAN_F2R1_FB13_Msk (0x1U << CAN_F2R1_FB13_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 2805 #define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk /*!<Filter bit 13 */
lypinator 0:bb348c97df44 2806 #define CAN_F2R1_FB14_Pos (14U)
lypinator 0:bb348c97df44 2807 #define CAN_F2R1_FB14_Msk (0x1U << CAN_F2R1_FB14_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 2808 #define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk /*!<Filter bit 14 */
lypinator 0:bb348c97df44 2809 #define CAN_F2R1_FB15_Pos (15U)
lypinator 0:bb348c97df44 2810 #define CAN_F2R1_FB15_Msk (0x1U << CAN_F2R1_FB15_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 2811 #define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk /*!<Filter bit 15 */
lypinator 0:bb348c97df44 2812 #define CAN_F2R1_FB16_Pos (16U)
lypinator 0:bb348c97df44 2813 #define CAN_F2R1_FB16_Msk (0x1U << CAN_F2R1_FB16_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 2814 #define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk /*!<Filter bit 16 */
lypinator 0:bb348c97df44 2815 #define CAN_F2R1_FB17_Pos (17U)
lypinator 0:bb348c97df44 2816 #define CAN_F2R1_FB17_Msk (0x1U << CAN_F2R1_FB17_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 2817 #define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk /*!<Filter bit 17 */
lypinator 0:bb348c97df44 2818 #define CAN_F2R1_FB18_Pos (18U)
lypinator 0:bb348c97df44 2819 #define CAN_F2R1_FB18_Msk (0x1U << CAN_F2R1_FB18_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 2820 #define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk /*!<Filter bit 18 */
lypinator 0:bb348c97df44 2821 #define CAN_F2R1_FB19_Pos (19U)
lypinator 0:bb348c97df44 2822 #define CAN_F2R1_FB19_Msk (0x1U << CAN_F2R1_FB19_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 2823 #define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk /*!<Filter bit 19 */
lypinator 0:bb348c97df44 2824 #define CAN_F2R1_FB20_Pos (20U)
lypinator 0:bb348c97df44 2825 #define CAN_F2R1_FB20_Msk (0x1U << CAN_F2R1_FB20_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 2826 #define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk /*!<Filter bit 20 */
lypinator 0:bb348c97df44 2827 #define CAN_F2R1_FB21_Pos (21U)
lypinator 0:bb348c97df44 2828 #define CAN_F2R1_FB21_Msk (0x1U << CAN_F2R1_FB21_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 2829 #define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk /*!<Filter bit 21 */
lypinator 0:bb348c97df44 2830 #define CAN_F2R1_FB22_Pos (22U)
lypinator 0:bb348c97df44 2831 #define CAN_F2R1_FB22_Msk (0x1U << CAN_F2R1_FB22_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 2832 #define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk /*!<Filter bit 22 */
lypinator 0:bb348c97df44 2833 #define CAN_F2R1_FB23_Pos (23U)
lypinator 0:bb348c97df44 2834 #define CAN_F2R1_FB23_Msk (0x1U << CAN_F2R1_FB23_Pos) /*!< 0x00800000 */
lypinator 0:bb348c97df44 2835 #define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk /*!<Filter bit 23 */
lypinator 0:bb348c97df44 2836 #define CAN_F2R1_FB24_Pos (24U)
lypinator 0:bb348c97df44 2837 #define CAN_F2R1_FB24_Msk (0x1U << CAN_F2R1_FB24_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 2838 #define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk /*!<Filter bit 24 */
lypinator 0:bb348c97df44 2839 #define CAN_F2R1_FB25_Pos (25U)
lypinator 0:bb348c97df44 2840 #define CAN_F2R1_FB25_Msk (0x1U << CAN_F2R1_FB25_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 2841 #define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk /*!<Filter bit 25 */
lypinator 0:bb348c97df44 2842 #define CAN_F2R1_FB26_Pos (26U)
lypinator 0:bb348c97df44 2843 #define CAN_F2R1_FB26_Msk (0x1U << CAN_F2R1_FB26_Pos) /*!< 0x04000000 */
lypinator 0:bb348c97df44 2844 #define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk /*!<Filter bit 26 */
lypinator 0:bb348c97df44 2845 #define CAN_F2R1_FB27_Pos (27U)
lypinator 0:bb348c97df44 2846 #define CAN_F2R1_FB27_Msk (0x1U << CAN_F2R1_FB27_Pos) /*!< 0x08000000 */
lypinator 0:bb348c97df44 2847 #define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk /*!<Filter bit 27 */
lypinator 0:bb348c97df44 2848 #define CAN_F2R1_FB28_Pos (28U)
lypinator 0:bb348c97df44 2849 #define CAN_F2R1_FB28_Msk (0x1U << CAN_F2R1_FB28_Pos) /*!< 0x10000000 */
lypinator 0:bb348c97df44 2850 #define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk /*!<Filter bit 28 */
lypinator 0:bb348c97df44 2851 #define CAN_F2R1_FB29_Pos (29U)
lypinator 0:bb348c97df44 2852 #define CAN_F2R1_FB29_Msk (0x1U << CAN_F2R1_FB29_Pos) /*!< 0x20000000 */
lypinator 0:bb348c97df44 2853 #define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk /*!<Filter bit 29 */
lypinator 0:bb348c97df44 2854 #define CAN_F2R1_FB30_Pos (30U)
lypinator 0:bb348c97df44 2855 #define CAN_F2R1_FB30_Msk (0x1U << CAN_F2R1_FB30_Pos) /*!< 0x40000000 */
lypinator 0:bb348c97df44 2856 #define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk /*!<Filter bit 30 */
lypinator 0:bb348c97df44 2857 #define CAN_F2R1_FB31_Pos (31U)
lypinator 0:bb348c97df44 2858 #define CAN_F2R1_FB31_Msk (0x1U << CAN_F2R1_FB31_Pos) /*!< 0x80000000 */
lypinator 0:bb348c97df44 2859 #define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk /*!<Filter bit 31 */
lypinator 0:bb348c97df44 2860
lypinator 0:bb348c97df44 2861 /******************* Bit definition for CAN_F3R1 register *******************/
lypinator 0:bb348c97df44 2862 #define CAN_F3R1_FB0_Pos (0U)
lypinator 0:bb348c97df44 2863 #define CAN_F3R1_FB0_Msk (0x1U << CAN_F3R1_FB0_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 2864 #define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk /*!<Filter bit 0 */
lypinator 0:bb348c97df44 2865 #define CAN_F3R1_FB1_Pos (1U)
lypinator 0:bb348c97df44 2866 #define CAN_F3R1_FB1_Msk (0x1U << CAN_F3R1_FB1_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 2867 #define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk /*!<Filter bit 1 */
lypinator 0:bb348c97df44 2868 #define CAN_F3R1_FB2_Pos (2U)
lypinator 0:bb348c97df44 2869 #define CAN_F3R1_FB2_Msk (0x1U << CAN_F3R1_FB2_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 2870 #define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk /*!<Filter bit 2 */
lypinator 0:bb348c97df44 2871 #define CAN_F3R1_FB3_Pos (3U)
lypinator 0:bb348c97df44 2872 #define CAN_F3R1_FB3_Msk (0x1U << CAN_F3R1_FB3_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 2873 #define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk /*!<Filter bit 3 */
lypinator 0:bb348c97df44 2874 #define CAN_F3R1_FB4_Pos (4U)
lypinator 0:bb348c97df44 2875 #define CAN_F3R1_FB4_Msk (0x1U << CAN_F3R1_FB4_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 2876 #define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk /*!<Filter bit 4 */
lypinator 0:bb348c97df44 2877 #define CAN_F3R1_FB5_Pos (5U)
lypinator 0:bb348c97df44 2878 #define CAN_F3R1_FB5_Msk (0x1U << CAN_F3R1_FB5_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 2879 #define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk /*!<Filter bit 5 */
lypinator 0:bb348c97df44 2880 #define CAN_F3R1_FB6_Pos (6U)
lypinator 0:bb348c97df44 2881 #define CAN_F3R1_FB6_Msk (0x1U << CAN_F3R1_FB6_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 2882 #define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk /*!<Filter bit 6 */
lypinator 0:bb348c97df44 2883 #define CAN_F3R1_FB7_Pos (7U)
lypinator 0:bb348c97df44 2884 #define CAN_F3R1_FB7_Msk (0x1U << CAN_F3R1_FB7_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 2885 #define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk /*!<Filter bit 7 */
lypinator 0:bb348c97df44 2886 #define CAN_F3R1_FB8_Pos (8U)
lypinator 0:bb348c97df44 2887 #define CAN_F3R1_FB8_Msk (0x1U << CAN_F3R1_FB8_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 2888 #define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk /*!<Filter bit 8 */
lypinator 0:bb348c97df44 2889 #define CAN_F3R1_FB9_Pos (9U)
lypinator 0:bb348c97df44 2890 #define CAN_F3R1_FB9_Msk (0x1U << CAN_F3R1_FB9_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 2891 #define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk /*!<Filter bit 9 */
lypinator 0:bb348c97df44 2892 #define CAN_F3R1_FB10_Pos (10U)
lypinator 0:bb348c97df44 2893 #define CAN_F3R1_FB10_Msk (0x1U << CAN_F3R1_FB10_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 2894 #define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk /*!<Filter bit 10 */
lypinator 0:bb348c97df44 2895 #define CAN_F3R1_FB11_Pos (11U)
lypinator 0:bb348c97df44 2896 #define CAN_F3R1_FB11_Msk (0x1U << CAN_F3R1_FB11_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 2897 #define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk /*!<Filter bit 11 */
lypinator 0:bb348c97df44 2898 #define CAN_F3R1_FB12_Pos (12U)
lypinator 0:bb348c97df44 2899 #define CAN_F3R1_FB12_Msk (0x1U << CAN_F3R1_FB12_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 2900 #define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk /*!<Filter bit 12 */
lypinator 0:bb348c97df44 2901 #define CAN_F3R1_FB13_Pos (13U)
lypinator 0:bb348c97df44 2902 #define CAN_F3R1_FB13_Msk (0x1U << CAN_F3R1_FB13_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 2903 #define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk /*!<Filter bit 13 */
lypinator 0:bb348c97df44 2904 #define CAN_F3R1_FB14_Pos (14U)
lypinator 0:bb348c97df44 2905 #define CAN_F3R1_FB14_Msk (0x1U << CAN_F3R1_FB14_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 2906 #define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk /*!<Filter bit 14 */
lypinator 0:bb348c97df44 2907 #define CAN_F3R1_FB15_Pos (15U)
lypinator 0:bb348c97df44 2908 #define CAN_F3R1_FB15_Msk (0x1U << CAN_F3R1_FB15_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 2909 #define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk /*!<Filter bit 15 */
lypinator 0:bb348c97df44 2910 #define CAN_F3R1_FB16_Pos (16U)
lypinator 0:bb348c97df44 2911 #define CAN_F3R1_FB16_Msk (0x1U << CAN_F3R1_FB16_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 2912 #define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk /*!<Filter bit 16 */
lypinator 0:bb348c97df44 2913 #define CAN_F3R1_FB17_Pos (17U)
lypinator 0:bb348c97df44 2914 #define CAN_F3R1_FB17_Msk (0x1U << CAN_F3R1_FB17_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 2915 #define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk /*!<Filter bit 17 */
lypinator 0:bb348c97df44 2916 #define CAN_F3R1_FB18_Pos (18U)
lypinator 0:bb348c97df44 2917 #define CAN_F3R1_FB18_Msk (0x1U << CAN_F3R1_FB18_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 2918 #define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk /*!<Filter bit 18 */
lypinator 0:bb348c97df44 2919 #define CAN_F3R1_FB19_Pos (19U)
lypinator 0:bb348c97df44 2920 #define CAN_F3R1_FB19_Msk (0x1U << CAN_F3R1_FB19_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 2921 #define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk /*!<Filter bit 19 */
lypinator 0:bb348c97df44 2922 #define CAN_F3R1_FB20_Pos (20U)
lypinator 0:bb348c97df44 2923 #define CAN_F3R1_FB20_Msk (0x1U << CAN_F3R1_FB20_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 2924 #define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk /*!<Filter bit 20 */
lypinator 0:bb348c97df44 2925 #define CAN_F3R1_FB21_Pos (21U)
lypinator 0:bb348c97df44 2926 #define CAN_F3R1_FB21_Msk (0x1U << CAN_F3R1_FB21_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 2927 #define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk /*!<Filter bit 21 */
lypinator 0:bb348c97df44 2928 #define CAN_F3R1_FB22_Pos (22U)
lypinator 0:bb348c97df44 2929 #define CAN_F3R1_FB22_Msk (0x1U << CAN_F3R1_FB22_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 2930 #define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk /*!<Filter bit 22 */
lypinator 0:bb348c97df44 2931 #define CAN_F3R1_FB23_Pos (23U)
lypinator 0:bb348c97df44 2932 #define CAN_F3R1_FB23_Msk (0x1U << CAN_F3R1_FB23_Pos) /*!< 0x00800000 */
lypinator 0:bb348c97df44 2933 #define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk /*!<Filter bit 23 */
lypinator 0:bb348c97df44 2934 #define CAN_F3R1_FB24_Pos (24U)
lypinator 0:bb348c97df44 2935 #define CAN_F3R1_FB24_Msk (0x1U << CAN_F3R1_FB24_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 2936 #define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk /*!<Filter bit 24 */
lypinator 0:bb348c97df44 2937 #define CAN_F3R1_FB25_Pos (25U)
lypinator 0:bb348c97df44 2938 #define CAN_F3R1_FB25_Msk (0x1U << CAN_F3R1_FB25_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 2939 #define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk /*!<Filter bit 25 */
lypinator 0:bb348c97df44 2940 #define CAN_F3R1_FB26_Pos (26U)
lypinator 0:bb348c97df44 2941 #define CAN_F3R1_FB26_Msk (0x1U << CAN_F3R1_FB26_Pos) /*!< 0x04000000 */
lypinator 0:bb348c97df44 2942 #define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk /*!<Filter bit 26 */
lypinator 0:bb348c97df44 2943 #define CAN_F3R1_FB27_Pos (27U)
lypinator 0:bb348c97df44 2944 #define CAN_F3R1_FB27_Msk (0x1U << CAN_F3R1_FB27_Pos) /*!< 0x08000000 */
lypinator 0:bb348c97df44 2945 #define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk /*!<Filter bit 27 */
lypinator 0:bb348c97df44 2946 #define CAN_F3R1_FB28_Pos (28U)
lypinator 0:bb348c97df44 2947 #define CAN_F3R1_FB28_Msk (0x1U << CAN_F3R1_FB28_Pos) /*!< 0x10000000 */
lypinator 0:bb348c97df44 2948 #define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk /*!<Filter bit 28 */
lypinator 0:bb348c97df44 2949 #define CAN_F3R1_FB29_Pos (29U)
lypinator 0:bb348c97df44 2950 #define CAN_F3R1_FB29_Msk (0x1U << CAN_F3R1_FB29_Pos) /*!< 0x20000000 */
lypinator 0:bb348c97df44 2951 #define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk /*!<Filter bit 29 */
lypinator 0:bb348c97df44 2952 #define CAN_F3R1_FB30_Pos (30U)
lypinator 0:bb348c97df44 2953 #define CAN_F3R1_FB30_Msk (0x1U << CAN_F3R1_FB30_Pos) /*!< 0x40000000 */
lypinator 0:bb348c97df44 2954 #define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk /*!<Filter bit 30 */
lypinator 0:bb348c97df44 2955 #define CAN_F3R1_FB31_Pos (31U)
lypinator 0:bb348c97df44 2956 #define CAN_F3R1_FB31_Msk (0x1U << CAN_F3R1_FB31_Pos) /*!< 0x80000000 */
lypinator 0:bb348c97df44 2957 #define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk /*!<Filter bit 31 */
lypinator 0:bb348c97df44 2958
lypinator 0:bb348c97df44 2959 /******************* Bit definition for CAN_F4R1 register *******************/
lypinator 0:bb348c97df44 2960 #define CAN_F4R1_FB0_Pos (0U)
lypinator 0:bb348c97df44 2961 #define CAN_F4R1_FB0_Msk (0x1U << CAN_F4R1_FB0_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 2962 #define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk /*!<Filter bit 0 */
lypinator 0:bb348c97df44 2963 #define CAN_F4R1_FB1_Pos (1U)
lypinator 0:bb348c97df44 2964 #define CAN_F4R1_FB1_Msk (0x1U << CAN_F4R1_FB1_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 2965 #define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk /*!<Filter bit 1 */
lypinator 0:bb348c97df44 2966 #define CAN_F4R1_FB2_Pos (2U)
lypinator 0:bb348c97df44 2967 #define CAN_F4R1_FB2_Msk (0x1U << CAN_F4R1_FB2_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 2968 #define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk /*!<Filter bit 2 */
lypinator 0:bb348c97df44 2969 #define CAN_F4R1_FB3_Pos (3U)
lypinator 0:bb348c97df44 2970 #define CAN_F4R1_FB3_Msk (0x1U << CAN_F4R1_FB3_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 2971 #define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk /*!<Filter bit 3 */
lypinator 0:bb348c97df44 2972 #define CAN_F4R1_FB4_Pos (4U)
lypinator 0:bb348c97df44 2973 #define CAN_F4R1_FB4_Msk (0x1U << CAN_F4R1_FB4_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 2974 #define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk /*!<Filter bit 4 */
lypinator 0:bb348c97df44 2975 #define CAN_F4R1_FB5_Pos (5U)
lypinator 0:bb348c97df44 2976 #define CAN_F4R1_FB5_Msk (0x1U << CAN_F4R1_FB5_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 2977 #define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk /*!<Filter bit 5 */
lypinator 0:bb348c97df44 2978 #define CAN_F4R1_FB6_Pos (6U)
lypinator 0:bb348c97df44 2979 #define CAN_F4R1_FB6_Msk (0x1U << CAN_F4R1_FB6_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 2980 #define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk /*!<Filter bit 6 */
lypinator 0:bb348c97df44 2981 #define CAN_F4R1_FB7_Pos (7U)
lypinator 0:bb348c97df44 2982 #define CAN_F4R1_FB7_Msk (0x1U << CAN_F4R1_FB7_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 2983 #define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk /*!<Filter bit 7 */
lypinator 0:bb348c97df44 2984 #define CAN_F4R1_FB8_Pos (8U)
lypinator 0:bb348c97df44 2985 #define CAN_F4R1_FB8_Msk (0x1U << CAN_F4R1_FB8_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 2986 #define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk /*!<Filter bit 8 */
lypinator 0:bb348c97df44 2987 #define CAN_F4R1_FB9_Pos (9U)
lypinator 0:bb348c97df44 2988 #define CAN_F4R1_FB9_Msk (0x1U << CAN_F4R1_FB9_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 2989 #define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk /*!<Filter bit 9 */
lypinator 0:bb348c97df44 2990 #define CAN_F4R1_FB10_Pos (10U)
lypinator 0:bb348c97df44 2991 #define CAN_F4R1_FB10_Msk (0x1U << CAN_F4R1_FB10_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 2992 #define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk /*!<Filter bit 10 */
lypinator 0:bb348c97df44 2993 #define CAN_F4R1_FB11_Pos (11U)
lypinator 0:bb348c97df44 2994 #define CAN_F4R1_FB11_Msk (0x1U << CAN_F4R1_FB11_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 2995 #define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk /*!<Filter bit 11 */
lypinator 0:bb348c97df44 2996 #define CAN_F4R1_FB12_Pos (12U)
lypinator 0:bb348c97df44 2997 #define CAN_F4R1_FB12_Msk (0x1U << CAN_F4R1_FB12_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 2998 #define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk /*!<Filter bit 12 */
lypinator 0:bb348c97df44 2999 #define CAN_F4R1_FB13_Pos (13U)
lypinator 0:bb348c97df44 3000 #define CAN_F4R1_FB13_Msk (0x1U << CAN_F4R1_FB13_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 3001 #define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk /*!<Filter bit 13 */
lypinator 0:bb348c97df44 3002 #define CAN_F4R1_FB14_Pos (14U)
lypinator 0:bb348c97df44 3003 #define CAN_F4R1_FB14_Msk (0x1U << CAN_F4R1_FB14_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 3004 #define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk /*!<Filter bit 14 */
lypinator 0:bb348c97df44 3005 #define CAN_F4R1_FB15_Pos (15U)
lypinator 0:bb348c97df44 3006 #define CAN_F4R1_FB15_Msk (0x1U << CAN_F4R1_FB15_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 3007 #define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk /*!<Filter bit 15 */
lypinator 0:bb348c97df44 3008 #define CAN_F4R1_FB16_Pos (16U)
lypinator 0:bb348c97df44 3009 #define CAN_F4R1_FB16_Msk (0x1U << CAN_F4R1_FB16_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 3010 #define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk /*!<Filter bit 16 */
lypinator 0:bb348c97df44 3011 #define CAN_F4R1_FB17_Pos (17U)
lypinator 0:bb348c97df44 3012 #define CAN_F4R1_FB17_Msk (0x1U << CAN_F4R1_FB17_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 3013 #define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk /*!<Filter bit 17 */
lypinator 0:bb348c97df44 3014 #define CAN_F4R1_FB18_Pos (18U)
lypinator 0:bb348c97df44 3015 #define CAN_F4R1_FB18_Msk (0x1U << CAN_F4R1_FB18_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 3016 #define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk /*!<Filter bit 18 */
lypinator 0:bb348c97df44 3017 #define CAN_F4R1_FB19_Pos (19U)
lypinator 0:bb348c97df44 3018 #define CAN_F4R1_FB19_Msk (0x1U << CAN_F4R1_FB19_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 3019 #define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk /*!<Filter bit 19 */
lypinator 0:bb348c97df44 3020 #define CAN_F4R1_FB20_Pos (20U)
lypinator 0:bb348c97df44 3021 #define CAN_F4R1_FB20_Msk (0x1U << CAN_F4R1_FB20_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 3022 #define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk /*!<Filter bit 20 */
lypinator 0:bb348c97df44 3023 #define CAN_F4R1_FB21_Pos (21U)
lypinator 0:bb348c97df44 3024 #define CAN_F4R1_FB21_Msk (0x1U << CAN_F4R1_FB21_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 3025 #define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk /*!<Filter bit 21 */
lypinator 0:bb348c97df44 3026 #define CAN_F4R1_FB22_Pos (22U)
lypinator 0:bb348c97df44 3027 #define CAN_F4R1_FB22_Msk (0x1U << CAN_F4R1_FB22_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 3028 #define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk /*!<Filter bit 22 */
lypinator 0:bb348c97df44 3029 #define CAN_F4R1_FB23_Pos (23U)
lypinator 0:bb348c97df44 3030 #define CAN_F4R1_FB23_Msk (0x1U << CAN_F4R1_FB23_Pos) /*!< 0x00800000 */
lypinator 0:bb348c97df44 3031 #define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk /*!<Filter bit 23 */
lypinator 0:bb348c97df44 3032 #define CAN_F4R1_FB24_Pos (24U)
lypinator 0:bb348c97df44 3033 #define CAN_F4R1_FB24_Msk (0x1U << CAN_F4R1_FB24_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 3034 #define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk /*!<Filter bit 24 */
lypinator 0:bb348c97df44 3035 #define CAN_F4R1_FB25_Pos (25U)
lypinator 0:bb348c97df44 3036 #define CAN_F4R1_FB25_Msk (0x1U << CAN_F4R1_FB25_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 3037 #define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk /*!<Filter bit 25 */
lypinator 0:bb348c97df44 3038 #define CAN_F4R1_FB26_Pos (26U)
lypinator 0:bb348c97df44 3039 #define CAN_F4R1_FB26_Msk (0x1U << CAN_F4R1_FB26_Pos) /*!< 0x04000000 */
lypinator 0:bb348c97df44 3040 #define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk /*!<Filter bit 26 */
lypinator 0:bb348c97df44 3041 #define CAN_F4R1_FB27_Pos (27U)
lypinator 0:bb348c97df44 3042 #define CAN_F4R1_FB27_Msk (0x1U << CAN_F4R1_FB27_Pos) /*!< 0x08000000 */
lypinator 0:bb348c97df44 3043 #define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk /*!<Filter bit 27 */
lypinator 0:bb348c97df44 3044 #define CAN_F4R1_FB28_Pos (28U)
lypinator 0:bb348c97df44 3045 #define CAN_F4R1_FB28_Msk (0x1U << CAN_F4R1_FB28_Pos) /*!< 0x10000000 */
lypinator 0:bb348c97df44 3046 #define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk /*!<Filter bit 28 */
lypinator 0:bb348c97df44 3047 #define CAN_F4R1_FB29_Pos (29U)
lypinator 0:bb348c97df44 3048 #define CAN_F4R1_FB29_Msk (0x1U << CAN_F4R1_FB29_Pos) /*!< 0x20000000 */
lypinator 0:bb348c97df44 3049 #define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk /*!<Filter bit 29 */
lypinator 0:bb348c97df44 3050 #define CAN_F4R1_FB30_Pos (30U)
lypinator 0:bb348c97df44 3051 #define CAN_F4R1_FB30_Msk (0x1U << CAN_F4R1_FB30_Pos) /*!< 0x40000000 */
lypinator 0:bb348c97df44 3052 #define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk /*!<Filter bit 30 */
lypinator 0:bb348c97df44 3053 #define CAN_F4R1_FB31_Pos (31U)
lypinator 0:bb348c97df44 3054 #define CAN_F4R1_FB31_Msk (0x1U << CAN_F4R1_FB31_Pos) /*!< 0x80000000 */
lypinator 0:bb348c97df44 3055 #define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk /*!<Filter bit 31 */
lypinator 0:bb348c97df44 3056
lypinator 0:bb348c97df44 3057 /******************* Bit definition for CAN_F5R1 register *******************/
lypinator 0:bb348c97df44 3058 #define CAN_F5R1_FB0_Pos (0U)
lypinator 0:bb348c97df44 3059 #define CAN_F5R1_FB0_Msk (0x1U << CAN_F5R1_FB0_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 3060 #define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk /*!<Filter bit 0 */
lypinator 0:bb348c97df44 3061 #define CAN_F5R1_FB1_Pos (1U)
lypinator 0:bb348c97df44 3062 #define CAN_F5R1_FB1_Msk (0x1U << CAN_F5R1_FB1_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 3063 #define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk /*!<Filter bit 1 */
lypinator 0:bb348c97df44 3064 #define CAN_F5R1_FB2_Pos (2U)
lypinator 0:bb348c97df44 3065 #define CAN_F5R1_FB2_Msk (0x1U << CAN_F5R1_FB2_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 3066 #define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk /*!<Filter bit 2 */
lypinator 0:bb348c97df44 3067 #define CAN_F5R1_FB3_Pos (3U)
lypinator 0:bb348c97df44 3068 #define CAN_F5R1_FB3_Msk (0x1U << CAN_F5R1_FB3_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 3069 #define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk /*!<Filter bit 3 */
lypinator 0:bb348c97df44 3070 #define CAN_F5R1_FB4_Pos (4U)
lypinator 0:bb348c97df44 3071 #define CAN_F5R1_FB4_Msk (0x1U << CAN_F5R1_FB4_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 3072 #define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk /*!<Filter bit 4 */
lypinator 0:bb348c97df44 3073 #define CAN_F5R1_FB5_Pos (5U)
lypinator 0:bb348c97df44 3074 #define CAN_F5R1_FB5_Msk (0x1U << CAN_F5R1_FB5_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 3075 #define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk /*!<Filter bit 5 */
lypinator 0:bb348c97df44 3076 #define CAN_F5R1_FB6_Pos (6U)
lypinator 0:bb348c97df44 3077 #define CAN_F5R1_FB6_Msk (0x1U << CAN_F5R1_FB6_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 3078 #define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk /*!<Filter bit 6 */
lypinator 0:bb348c97df44 3079 #define CAN_F5R1_FB7_Pos (7U)
lypinator 0:bb348c97df44 3080 #define CAN_F5R1_FB7_Msk (0x1U << CAN_F5R1_FB7_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 3081 #define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk /*!<Filter bit 7 */
lypinator 0:bb348c97df44 3082 #define CAN_F5R1_FB8_Pos (8U)
lypinator 0:bb348c97df44 3083 #define CAN_F5R1_FB8_Msk (0x1U << CAN_F5R1_FB8_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 3084 #define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk /*!<Filter bit 8 */
lypinator 0:bb348c97df44 3085 #define CAN_F5R1_FB9_Pos (9U)
lypinator 0:bb348c97df44 3086 #define CAN_F5R1_FB9_Msk (0x1U << CAN_F5R1_FB9_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 3087 #define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk /*!<Filter bit 9 */
lypinator 0:bb348c97df44 3088 #define CAN_F5R1_FB10_Pos (10U)
lypinator 0:bb348c97df44 3089 #define CAN_F5R1_FB10_Msk (0x1U << CAN_F5R1_FB10_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 3090 #define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk /*!<Filter bit 10 */
lypinator 0:bb348c97df44 3091 #define CAN_F5R1_FB11_Pos (11U)
lypinator 0:bb348c97df44 3092 #define CAN_F5R1_FB11_Msk (0x1U << CAN_F5R1_FB11_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 3093 #define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk /*!<Filter bit 11 */
lypinator 0:bb348c97df44 3094 #define CAN_F5R1_FB12_Pos (12U)
lypinator 0:bb348c97df44 3095 #define CAN_F5R1_FB12_Msk (0x1U << CAN_F5R1_FB12_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 3096 #define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk /*!<Filter bit 12 */
lypinator 0:bb348c97df44 3097 #define CAN_F5R1_FB13_Pos (13U)
lypinator 0:bb348c97df44 3098 #define CAN_F5R1_FB13_Msk (0x1U << CAN_F5R1_FB13_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 3099 #define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk /*!<Filter bit 13 */
lypinator 0:bb348c97df44 3100 #define CAN_F5R1_FB14_Pos (14U)
lypinator 0:bb348c97df44 3101 #define CAN_F5R1_FB14_Msk (0x1U << CAN_F5R1_FB14_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 3102 #define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk /*!<Filter bit 14 */
lypinator 0:bb348c97df44 3103 #define CAN_F5R1_FB15_Pos (15U)
lypinator 0:bb348c97df44 3104 #define CAN_F5R1_FB15_Msk (0x1U << CAN_F5R1_FB15_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 3105 #define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk /*!<Filter bit 15 */
lypinator 0:bb348c97df44 3106 #define CAN_F5R1_FB16_Pos (16U)
lypinator 0:bb348c97df44 3107 #define CAN_F5R1_FB16_Msk (0x1U << CAN_F5R1_FB16_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 3108 #define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk /*!<Filter bit 16 */
lypinator 0:bb348c97df44 3109 #define CAN_F5R1_FB17_Pos (17U)
lypinator 0:bb348c97df44 3110 #define CAN_F5R1_FB17_Msk (0x1U << CAN_F5R1_FB17_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 3111 #define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk /*!<Filter bit 17 */
lypinator 0:bb348c97df44 3112 #define CAN_F5R1_FB18_Pos (18U)
lypinator 0:bb348c97df44 3113 #define CAN_F5R1_FB18_Msk (0x1U << CAN_F5R1_FB18_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 3114 #define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk /*!<Filter bit 18 */
lypinator 0:bb348c97df44 3115 #define CAN_F5R1_FB19_Pos (19U)
lypinator 0:bb348c97df44 3116 #define CAN_F5R1_FB19_Msk (0x1U << CAN_F5R1_FB19_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 3117 #define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk /*!<Filter bit 19 */
lypinator 0:bb348c97df44 3118 #define CAN_F5R1_FB20_Pos (20U)
lypinator 0:bb348c97df44 3119 #define CAN_F5R1_FB20_Msk (0x1U << CAN_F5R1_FB20_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 3120 #define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk /*!<Filter bit 20 */
lypinator 0:bb348c97df44 3121 #define CAN_F5R1_FB21_Pos (21U)
lypinator 0:bb348c97df44 3122 #define CAN_F5R1_FB21_Msk (0x1U << CAN_F5R1_FB21_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 3123 #define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk /*!<Filter bit 21 */
lypinator 0:bb348c97df44 3124 #define CAN_F5R1_FB22_Pos (22U)
lypinator 0:bb348c97df44 3125 #define CAN_F5R1_FB22_Msk (0x1U << CAN_F5R1_FB22_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 3126 #define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk /*!<Filter bit 22 */
lypinator 0:bb348c97df44 3127 #define CAN_F5R1_FB23_Pos (23U)
lypinator 0:bb348c97df44 3128 #define CAN_F5R1_FB23_Msk (0x1U << CAN_F5R1_FB23_Pos) /*!< 0x00800000 */
lypinator 0:bb348c97df44 3129 #define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk /*!<Filter bit 23 */
lypinator 0:bb348c97df44 3130 #define CAN_F5R1_FB24_Pos (24U)
lypinator 0:bb348c97df44 3131 #define CAN_F5R1_FB24_Msk (0x1U << CAN_F5R1_FB24_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 3132 #define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk /*!<Filter bit 24 */
lypinator 0:bb348c97df44 3133 #define CAN_F5R1_FB25_Pos (25U)
lypinator 0:bb348c97df44 3134 #define CAN_F5R1_FB25_Msk (0x1U << CAN_F5R1_FB25_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 3135 #define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk /*!<Filter bit 25 */
lypinator 0:bb348c97df44 3136 #define CAN_F5R1_FB26_Pos (26U)
lypinator 0:bb348c97df44 3137 #define CAN_F5R1_FB26_Msk (0x1U << CAN_F5R1_FB26_Pos) /*!< 0x04000000 */
lypinator 0:bb348c97df44 3138 #define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk /*!<Filter bit 26 */
lypinator 0:bb348c97df44 3139 #define CAN_F5R1_FB27_Pos (27U)
lypinator 0:bb348c97df44 3140 #define CAN_F5R1_FB27_Msk (0x1U << CAN_F5R1_FB27_Pos) /*!< 0x08000000 */
lypinator 0:bb348c97df44 3141 #define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk /*!<Filter bit 27 */
lypinator 0:bb348c97df44 3142 #define CAN_F5R1_FB28_Pos (28U)
lypinator 0:bb348c97df44 3143 #define CAN_F5R1_FB28_Msk (0x1U << CAN_F5R1_FB28_Pos) /*!< 0x10000000 */
lypinator 0:bb348c97df44 3144 #define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk /*!<Filter bit 28 */
lypinator 0:bb348c97df44 3145 #define CAN_F5R1_FB29_Pos (29U)
lypinator 0:bb348c97df44 3146 #define CAN_F5R1_FB29_Msk (0x1U << CAN_F5R1_FB29_Pos) /*!< 0x20000000 */
lypinator 0:bb348c97df44 3147 #define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk /*!<Filter bit 29 */
lypinator 0:bb348c97df44 3148 #define CAN_F5R1_FB30_Pos (30U)
lypinator 0:bb348c97df44 3149 #define CAN_F5R1_FB30_Msk (0x1U << CAN_F5R1_FB30_Pos) /*!< 0x40000000 */
lypinator 0:bb348c97df44 3150 #define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk /*!<Filter bit 30 */
lypinator 0:bb348c97df44 3151 #define CAN_F5R1_FB31_Pos (31U)
lypinator 0:bb348c97df44 3152 #define CAN_F5R1_FB31_Msk (0x1U << CAN_F5R1_FB31_Pos) /*!< 0x80000000 */
lypinator 0:bb348c97df44 3153 #define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk /*!<Filter bit 31 */
lypinator 0:bb348c97df44 3154
lypinator 0:bb348c97df44 3155 /******************* Bit definition for CAN_F6R1 register *******************/
lypinator 0:bb348c97df44 3156 #define CAN_F6R1_FB0_Pos (0U)
lypinator 0:bb348c97df44 3157 #define CAN_F6R1_FB0_Msk (0x1U << CAN_F6R1_FB0_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 3158 #define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk /*!<Filter bit 0 */
lypinator 0:bb348c97df44 3159 #define CAN_F6R1_FB1_Pos (1U)
lypinator 0:bb348c97df44 3160 #define CAN_F6R1_FB1_Msk (0x1U << CAN_F6R1_FB1_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 3161 #define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk /*!<Filter bit 1 */
lypinator 0:bb348c97df44 3162 #define CAN_F6R1_FB2_Pos (2U)
lypinator 0:bb348c97df44 3163 #define CAN_F6R1_FB2_Msk (0x1U << CAN_F6R1_FB2_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 3164 #define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk /*!<Filter bit 2 */
lypinator 0:bb348c97df44 3165 #define CAN_F6R1_FB3_Pos (3U)
lypinator 0:bb348c97df44 3166 #define CAN_F6R1_FB3_Msk (0x1U << CAN_F6R1_FB3_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 3167 #define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk /*!<Filter bit 3 */
lypinator 0:bb348c97df44 3168 #define CAN_F6R1_FB4_Pos (4U)
lypinator 0:bb348c97df44 3169 #define CAN_F6R1_FB4_Msk (0x1U << CAN_F6R1_FB4_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 3170 #define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk /*!<Filter bit 4 */
lypinator 0:bb348c97df44 3171 #define CAN_F6R1_FB5_Pos (5U)
lypinator 0:bb348c97df44 3172 #define CAN_F6R1_FB5_Msk (0x1U << CAN_F6R1_FB5_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 3173 #define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk /*!<Filter bit 5 */
lypinator 0:bb348c97df44 3174 #define CAN_F6R1_FB6_Pos (6U)
lypinator 0:bb348c97df44 3175 #define CAN_F6R1_FB6_Msk (0x1U << CAN_F6R1_FB6_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 3176 #define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk /*!<Filter bit 6 */
lypinator 0:bb348c97df44 3177 #define CAN_F6R1_FB7_Pos (7U)
lypinator 0:bb348c97df44 3178 #define CAN_F6R1_FB7_Msk (0x1U << CAN_F6R1_FB7_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 3179 #define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk /*!<Filter bit 7 */
lypinator 0:bb348c97df44 3180 #define CAN_F6R1_FB8_Pos (8U)
lypinator 0:bb348c97df44 3181 #define CAN_F6R1_FB8_Msk (0x1U << CAN_F6R1_FB8_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 3182 #define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk /*!<Filter bit 8 */
lypinator 0:bb348c97df44 3183 #define CAN_F6R1_FB9_Pos (9U)
lypinator 0:bb348c97df44 3184 #define CAN_F6R1_FB9_Msk (0x1U << CAN_F6R1_FB9_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 3185 #define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk /*!<Filter bit 9 */
lypinator 0:bb348c97df44 3186 #define CAN_F6R1_FB10_Pos (10U)
lypinator 0:bb348c97df44 3187 #define CAN_F6R1_FB10_Msk (0x1U << CAN_F6R1_FB10_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 3188 #define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk /*!<Filter bit 10 */
lypinator 0:bb348c97df44 3189 #define CAN_F6R1_FB11_Pos (11U)
lypinator 0:bb348c97df44 3190 #define CAN_F6R1_FB11_Msk (0x1U << CAN_F6R1_FB11_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 3191 #define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk /*!<Filter bit 11 */
lypinator 0:bb348c97df44 3192 #define CAN_F6R1_FB12_Pos (12U)
lypinator 0:bb348c97df44 3193 #define CAN_F6R1_FB12_Msk (0x1U << CAN_F6R1_FB12_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 3194 #define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk /*!<Filter bit 12 */
lypinator 0:bb348c97df44 3195 #define CAN_F6R1_FB13_Pos (13U)
lypinator 0:bb348c97df44 3196 #define CAN_F6R1_FB13_Msk (0x1U << CAN_F6R1_FB13_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 3197 #define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk /*!<Filter bit 13 */
lypinator 0:bb348c97df44 3198 #define CAN_F6R1_FB14_Pos (14U)
lypinator 0:bb348c97df44 3199 #define CAN_F6R1_FB14_Msk (0x1U << CAN_F6R1_FB14_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 3200 #define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk /*!<Filter bit 14 */
lypinator 0:bb348c97df44 3201 #define CAN_F6R1_FB15_Pos (15U)
lypinator 0:bb348c97df44 3202 #define CAN_F6R1_FB15_Msk (0x1U << CAN_F6R1_FB15_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 3203 #define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk /*!<Filter bit 15 */
lypinator 0:bb348c97df44 3204 #define CAN_F6R1_FB16_Pos (16U)
lypinator 0:bb348c97df44 3205 #define CAN_F6R1_FB16_Msk (0x1U << CAN_F6R1_FB16_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 3206 #define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk /*!<Filter bit 16 */
lypinator 0:bb348c97df44 3207 #define CAN_F6R1_FB17_Pos (17U)
lypinator 0:bb348c97df44 3208 #define CAN_F6R1_FB17_Msk (0x1U << CAN_F6R1_FB17_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 3209 #define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk /*!<Filter bit 17 */
lypinator 0:bb348c97df44 3210 #define CAN_F6R1_FB18_Pos (18U)
lypinator 0:bb348c97df44 3211 #define CAN_F6R1_FB18_Msk (0x1U << CAN_F6R1_FB18_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 3212 #define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk /*!<Filter bit 18 */
lypinator 0:bb348c97df44 3213 #define CAN_F6R1_FB19_Pos (19U)
lypinator 0:bb348c97df44 3214 #define CAN_F6R1_FB19_Msk (0x1U << CAN_F6R1_FB19_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 3215 #define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk /*!<Filter bit 19 */
lypinator 0:bb348c97df44 3216 #define CAN_F6R1_FB20_Pos (20U)
lypinator 0:bb348c97df44 3217 #define CAN_F6R1_FB20_Msk (0x1U << CAN_F6R1_FB20_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 3218 #define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk /*!<Filter bit 20 */
lypinator 0:bb348c97df44 3219 #define CAN_F6R1_FB21_Pos (21U)
lypinator 0:bb348c97df44 3220 #define CAN_F6R1_FB21_Msk (0x1U << CAN_F6R1_FB21_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 3221 #define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk /*!<Filter bit 21 */
lypinator 0:bb348c97df44 3222 #define CAN_F6R1_FB22_Pos (22U)
lypinator 0:bb348c97df44 3223 #define CAN_F6R1_FB22_Msk (0x1U << CAN_F6R1_FB22_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 3224 #define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk /*!<Filter bit 22 */
lypinator 0:bb348c97df44 3225 #define CAN_F6R1_FB23_Pos (23U)
lypinator 0:bb348c97df44 3226 #define CAN_F6R1_FB23_Msk (0x1U << CAN_F6R1_FB23_Pos) /*!< 0x00800000 */
lypinator 0:bb348c97df44 3227 #define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk /*!<Filter bit 23 */
lypinator 0:bb348c97df44 3228 #define CAN_F6R1_FB24_Pos (24U)
lypinator 0:bb348c97df44 3229 #define CAN_F6R1_FB24_Msk (0x1U << CAN_F6R1_FB24_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 3230 #define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk /*!<Filter bit 24 */
lypinator 0:bb348c97df44 3231 #define CAN_F6R1_FB25_Pos (25U)
lypinator 0:bb348c97df44 3232 #define CAN_F6R1_FB25_Msk (0x1U << CAN_F6R1_FB25_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 3233 #define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk /*!<Filter bit 25 */
lypinator 0:bb348c97df44 3234 #define CAN_F6R1_FB26_Pos (26U)
lypinator 0:bb348c97df44 3235 #define CAN_F6R1_FB26_Msk (0x1U << CAN_F6R1_FB26_Pos) /*!< 0x04000000 */
lypinator 0:bb348c97df44 3236 #define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk /*!<Filter bit 26 */
lypinator 0:bb348c97df44 3237 #define CAN_F6R1_FB27_Pos (27U)
lypinator 0:bb348c97df44 3238 #define CAN_F6R1_FB27_Msk (0x1U << CAN_F6R1_FB27_Pos) /*!< 0x08000000 */
lypinator 0:bb348c97df44 3239 #define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk /*!<Filter bit 27 */
lypinator 0:bb348c97df44 3240 #define CAN_F6R1_FB28_Pos (28U)
lypinator 0:bb348c97df44 3241 #define CAN_F6R1_FB28_Msk (0x1U << CAN_F6R1_FB28_Pos) /*!< 0x10000000 */
lypinator 0:bb348c97df44 3242 #define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk /*!<Filter bit 28 */
lypinator 0:bb348c97df44 3243 #define CAN_F6R1_FB29_Pos (29U)
lypinator 0:bb348c97df44 3244 #define CAN_F6R1_FB29_Msk (0x1U << CAN_F6R1_FB29_Pos) /*!< 0x20000000 */
lypinator 0:bb348c97df44 3245 #define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk /*!<Filter bit 29 */
lypinator 0:bb348c97df44 3246 #define CAN_F6R1_FB30_Pos (30U)
lypinator 0:bb348c97df44 3247 #define CAN_F6R1_FB30_Msk (0x1U << CAN_F6R1_FB30_Pos) /*!< 0x40000000 */
lypinator 0:bb348c97df44 3248 #define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk /*!<Filter bit 30 */
lypinator 0:bb348c97df44 3249 #define CAN_F6R1_FB31_Pos (31U)
lypinator 0:bb348c97df44 3250 #define CAN_F6R1_FB31_Msk (0x1U << CAN_F6R1_FB31_Pos) /*!< 0x80000000 */
lypinator 0:bb348c97df44 3251 #define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk /*!<Filter bit 31 */
lypinator 0:bb348c97df44 3252
lypinator 0:bb348c97df44 3253 /******************* Bit definition for CAN_F7R1 register *******************/
lypinator 0:bb348c97df44 3254 #define CAN_F7R1_FB0_Pos (0U)
lypinator 0:bb348c97df44 3255 #define CAN_F7R1_FB0_Msk (0x1U << CAN_F7R1_FB0_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 3256 #define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk /*!<Filter bit 0 */
lypinator 0:bb348c97df44 3257 #define CAN_F7R1_FB1_Pos (1U)
lypinator 0:bb348c97df44 3258 #define CAN_F7R1_FB1_Msk (0x1U << CAN_F7R1_FB1_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 3259 #define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk /*!<Filter bit 1 */
lypinator 0:bb348c97df44 3260 #define CAN_F7R1_FB2_Pos (2U)
lypinator 0:bb348c97df44 3261 #define CAN_F7R1_FB2_Msk (0x1U << CAN_F7R1_FB2_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 3262 #define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk /*!<Filter bit 2 */
lypinator 0:bb348c97df44 3263 #define CAN_F7R1_FB3_Pos (3U)
lypinator 0:bb348c97df44 3264 #define CAN_F7R1_FB3_Msk (0x1U << CAN_F7R1_FB3_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 3265 #define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk /*!<Filter bit 3 */
lypinator 0:bb348c97df44 3266 #define CAN_F7R1_FB4_Pos (4U)
lypinator 0:bb348c97df44 3267 #define CAN_F7R1_FB4_Msk (0x1U << CAN_F7R1_FB4_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 3268 #define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk /*!<Filter bit 4 */
lypinator 0:bb348c97df44 3269 #define CAN_F7R1_FB5_Pos (5U)
lypinator 0:bb348c97df44 3270 #define CAN_F7R1_FB5_Msk (0x1U << CAN_F7R1_FB5_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 3271 #define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk /*!<Filter bit 5 */
lypinator 0:bb348c97df44 3272 #define CAN_F7R1_FB6_Pos (6U)
lypinator 0:bb348c97df44 3273 #define CAN_F7R1_FB6_Msk (0x1U << CAN_F7R1_FB6_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 3274 #define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk /*!<Filter bit 6 */
lypinator 0:bb348c97df44 3275 #define CAN_F7R1_FB7_Pos (7U)
lypinator 0:bb348c97df44 3276 #define CAN_F7R1_FB7_Msk (0x1U << CAN_F7R1_FB7_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 3277 #define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk /*!<Filter bit 7 */
lypinator 0:bb348c97df44 3278 #define CAN_F7R1_FB8_Pos (8U)
lypinator 0:bb348c97df44 3279 #define CAN_F7R1_FB8_Msk (0x1U << CAN_F7R1_FB8_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 3280 #define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk /*!<Filter bit 8 */
lypinator 0:bb348c97df44 3281 #define CAN_F7R1_FB9_Pos (9U)
lypinator 0:bb348c97df44 3282 #define CAN_F7R1_FB9_Msk (0x1U << CAN_F7R1_FB9_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 3283 #define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk /*!<Filter bit 9 */
lypinator 0:bb348c97df44 3284 #define CAN_F7R1_FB10_Pos (10U)
lypinator 0:bb348c97df44 3285 #define CAN_F7R1_FB10_Msk (0x1U << CAN_F7R1_FB10_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 3286 #define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk /*!<Filter bit 10 */
lypinator 0:bb348c97df44 3287 #define CAN_F7R1_FB11_Pos (11U)
lypinator 0:bb348c97df44 3288 #define CAN_F7R1_FB11_Msk (0x1U << CAN_F7R1_FB11_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 3289 #define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk /*!<Filter bit 11 */
lypinator 0:bb348c97df44 3290 #define CAN_F7R1_FB12_Pos (12U)
lypinator 0:bb348c97df44 3291 #define CAN_F7R1_FB12_Msk (0x1U << CAN_F7R1_FB12_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 3292 #define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk /*!<Filter bit 12 */
lypinator 0:bb348c97df44 3293 #define CAN_F7R1_FB13_Pos (13U)
lypinator 0:bb348c97df44 3294 #define CAN_F7R1_FB13_Msk (0x1U << CAN_F7R1_FB13_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 3295 #define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk /*!<Filter bit 13 */
lypinator 0:bb348c97df44 3296 #define CAN_F7R1_FB14_Pos (14U)
lypinator 0:bb348c97df44 3297 #define CAN_F7R1_FB14_Msk (0x1U << CAN_F7R1_FB14_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 3298 #define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk /*!<Filter bit 14 */
lypinator 0:bb348c97df44 3299 #define CAN_F7R1_FB15_Pos (15U)
lypinator 0:bb348c97df44 3300 #define CAN_F7R1_FB15_Msk (0x1U << CAN_F7R1_FB15_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 3301 #define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk /*!<Filter bit 15 */
lypinator 0:bb348c97df44 3302 #define CAN_F7R1_FB16_Pos (16U)
lypinator 0:bb348c97df44 3303 #define CAN_F7R1_FB16_Msk (0x1U << CAN_F7R1_FB16_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 3304 #define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk /*!<Filter bit 16 */
lypinator 0:bb348c97df44 3305 #define CAN_F7R1_FB17_Pos (17U)
lypinator 0:bb348c97df44 3306 #define CAN_F7R1_FB17_Msk (0x1U << CAN_F7R1_FB17_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 3307 #define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk /*!<Filter bit 17 */
lypinator 0:bb348c97df44 3308 #define CAN_F7R1_FB18_Pos (18U)
lypinator 0:bb348c97df44 3309 #define CAN_F7R1_FB18_Msk (0x1U << CAN_F7R1_FB18_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 3310 #define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk /*!<Filter bit 18 */
lypinator 0:bb348c97df44 3311 #define CAN_F7R1_FB19_Pos (19U)
lypinator 0:bb348c97df44 3312 #define CAN_F7R1_FB19_Msk (0x1U << CAN_F7R1_FB19_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 3313 #define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk /*!<Filter bit 19 */
lypinator 0:bb348c97df44 3314 #define CAN_F7R1_FB20_Pos (20U)
lypinator 0:bb348c97df44 3315 #define CAN_F7R1_FB20_Msk (0x1U << CAN_F7R1_FB20_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 3316 #define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk /*!<Filter bit 20 */
lypinator 0:bb348c97df44 3317 #define CAN_F7R1_FB21_Pos (21U)
lypinator 0:bb348c97df44 3318 #define CAN_F7R1_FB21_Msk (0x1U << CAN_F7R1_FB21_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 3319 #define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk /*!<Filter bit 21 */
lypinator 0:bb348c97df44 3320 #define CAN_F7R1_FB22_Pos (22U)
lypinator 0:bb348c97df44 3321 #define CAN_F7R1_FB22_Msk (0x1U << CAN_F7R1_FB22_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 3322 #define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk /*!<Filter bit 22 */
lypinator 0:bb348c97df44 3323 #define CAN_F7R1_FB23_Pos (23U)
lypinator 0:bb348c97df44 3324 #define CAN_F7R1_FB23_Msk (0x1U << CAN_F7R1_FB23_Pos) /*!< 0x00800000 */
lypinator 0:bb348c97df44 3325 #define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk /*!<Filter bit 23 */
lypinator 0:bb348c97df44 3326 #define CAN_F7R1_FB24_Pos (24U)
lypinator 0:bb348c97df44 3327 #define CAN_F7R1_FB24_Msk (0x1U << CAN_F7R1_FB24_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 3328 #define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk /*!<Filter bit 24 */
lypinator 0:bb348c97df44 3329 #define CAN_F7R1_FB25_Pos (25U)
lypinator 0:bb348c97df44 3330 #define CAN_F7R1_FB25_Msk (0x1U << CAN_F7R1_FB25_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 3331 #define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk /*!<Filter bit 25 */
lypinator 0:bb348c97df44 3332 #define CAN_F7R1_FB26_Pos (26U)
lypinator 0:bb348c97df44 3333 #define CAN_F7R1_FB26_Msk (0x1U << CAN_F7R1_FB26_Pos) /*!< 0x04000000 */
lypinator 0:bb348c97df44 3334 #define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk /*!<Filter bit 26 */
lypinator 0:bb348c97df44 3335 #define CAN_F7R1_FB27_Pos (27U)
lypinator 0:bb348c97df44 3336 #define CAN_F7R1_FB27_Msk (0x1U << CAN_F7R1_FB27_Pos) /*!< 0x08000000 */
lypinator 0:bb348c97df44 3337 #define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk /*!<Filter bit 27 */
lypinator 0:bb348c97df44 3338 #define CAN_F7R1_FB28_Pos (28U)
lypinator 0:bb348c97df44 3339 #define CAN_F7R1_FB28_Msk (0x1U << CAN_F7R1_FB28_Pos) /*!< 0x10000000 */
lypinator 0:bb348c97df44 3340 #define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk /*!<Filter bit 28 */
lypinator 0:bb348c97df44 3341 #define CAN_F7R1_FB29_Pos (29U)
lypinator 0:bb348c97df44 3342 #define CAN_F7R1_FB29_Msk (0x1U << CAN_F7R1_FB29_Pos) /*!< 0x20000000 */
lypinator 0:bb348c97df44 3343 #define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk /*!<Filter bit 29 */
lypinator 0:bb348c97df44 3344 #define CAN_F7R1_FB30_Pos (30U)
lypinator 0:bb348c97df44 3345 #define CAN_F7R1_FB30_Msk (0x1U << CAN_F7R1_FB30_Pos) /*!< 0x40000000 */
lypinator 0:bb348c97df44 3346 #define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk /*!<Filter bit 30 */
lypinator 0:bb348c97df44 3347 #define CAN_F7R1_FB31_Pos (31U)
lypinator 0:bb348c97df44 3348 #define CAN_F7R1_FB31_Msk (0x1U << CAN_F7R1_FB31_Pos) /*!< 0x80000000 */
lypinator 0:bb348c97df44 3349 #define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk /*!<Filter bit 31 */
lypinator 0:bb348c97df44 3350
lypinator 0:bb348c97df44 3351 /******************* Bit definition for CAN_F8R1 register *******************/
lypinator 0:bb348c97df44 3352 #define CAN_F8R1_FB0_Pos (0U)
lypinator 0:bb348c97df44 3353 #define CAN_F8R1_FB0_Msk (0x1U << CAN_F8R1_FB0_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 3354 #define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk /*!<Filter bit 0 */
lypinator 0:bb348c97df44 3355 #define CAN_F8R1_FB1_Pos (1U)
lypinator 0:bb348c97df44 3356 #define CAN_F8R1_FB1_Msk (0x1U << CAN_F8R1_FB1_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 3357 #define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk /*!<Filter bit 1 */
lypinator 0:bb348c97df44 3358 #define CAN_F8R1_FB2_Pos (2U)
lypinator 0:bb348c97df44 3359 #define CAN_F8R1_FB2_Msk (0x1U << CAN_F8R1_FB2_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 3360 #define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk /*!<Filter bit 2 */
lypinator 0:bb348c97df44 3361 #define CAN_F8R1_FB3_Pos (3U)
lypinator 0:bb348c97df44 3362 #define CAN_F8R1_FB3_Msk (0x1U << CAN_F8R1_FB3_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 3363 #define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk /*!<Filter bit 3 */
lypinator 0:bb348c97df44 3364 #define CAN_F8R1_FB4_Pos (4U)
lypinator 0:bb348c97df44 3365 #define CAN_F8R1_FB4_Msk (0x1U << CAN_F8R1_FB4_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 3366 #define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk /*!<Filter bit 4 */
lypinator 0:bb348c97df44 3367 #define CAN_F8R1_FB5_Pos (5U)
lypinator 0:bb348c97df44 3368 #define CAN_F8R1_FB5_Msk (0x1U << CAN_F8R1_FB5_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 3369 #define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk /*!<Filter bit 5 */
lypinator 0:bb348c97df44 3370 #define CAN_F8R1_FB6_Pos (6U)
lypinator 0:bb348c97df44 3371 #define CAN_F8R1_FB6_Msk (0x1U << CAN_F8R1_FB6_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 3372 #define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk /*!<Filter bit 6 */
lypinator 0:bb348c97df44 3373 #define CAN_F8R1_FB7_Pos (7U)
lypinator 0:bb348c97df44 3374 #define CAN_F8R1_FB7_Msk (0x1U << CAN_F8R1_FB7_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 3375 #define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk /*!<Filter bit 7 */
lypinator 0:bb348c97df44 3376 #define CAN_F8R1_FB8_Pos (8U)
lypinator 0:bb348c97df44 3377 #define CAN_F8R1_FB8_Msk (0x1U << CAN_F8R1_FB8_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 3378 #define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk /*!<Filter bit 8 */
lypinator 0:bb348c97df44 3379 #define CAN_F8R1_FB9_Pos (9U)
lypinator 0:bb348c97df44 3380 #define CAN_F8R1_FB9_Msk (0x1U << CAN_F8R1_FB9_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 3381 #define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk /*!<Filter bit 9 */
lypinator 0:bb348c97df44 3382 #define CAN_F8R1_FB10_Pos (10U)
lypinator 0:bb348c97df44 3383 #define CAN_F8R1_FB10_Msk (0x1U << CAN_F8R1_FB10_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 3384 #define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk /*!<Filter bit 10 */
lypinator 0:bb348c97df44 3385 #define CAN_F8R1_FB11_Pos (11U)
lypinator 0:bb348c97df44 3386 #define CAN_F8R1_FB11_Msk (0x1U << CAN_F8R1_FB11_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 3387 #define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk /*!<Filter bit 11 */
lypinator 0:bb348c97df44 3388 #define CAN_F8R1_FB12_Pos (12U)
lypinator 0:bb348c97df44 3389 #define CAN_F8R1_FB12_Msk (0x1U << CAN_F8R1_FB12_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 3390 #define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk /*!<Filter bit 12 */
lypinator 0:bb348c97df44 3391 #define CAN_F8R1_FB13_Pos (13U)
lypinator 0:bb348c97df44 3392 #define CAN_F8R1_FB13_Msk (0x1U << CAN_F8R1_FB13_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 3393 #define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk /*!<Filter bit 13 */
lypinator 0:bb348c97df44 3394 #define CAN_F8R1_FB14_Pos (14U)
lypinator 0:bb348c97df44 3395 #define CAN_F8R1_FB14_Msk (0x1U << CAN_F8R1_FB14_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 3396 #define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk /*!<Filter bit 14 */
lypinator 0:bb348c97df44 3397 #define CAN_F8R1_FB15_Pos (15U)
lypinator 0:bb348c97df44 3398 #define CAN_F8R1_FB15_Msk (0x1U << CAN_F8R1_FB15_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 3399 #define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk /*!<Filter bit 15 */
lypinator 0:bb348c97df44 3400 #define CAN_F8R1_FB16_Pos (16U)
lypinator 0:bb348c97df44 3401 #define CAN_F8R1_FB16_Msk (0x1U << CAN_F8R1_FB16_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 3402 #define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk /*!<Filter bit 16 */
lypinator 0:bb348c97df44 3403 #define CAN_F8R1_FB17_Pos (17U)
lypinator 0:bb348c97df44 3404 #define CAN_F8R1_FB17_Msk (0x1U << CAN_F8R1_FB17_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 3405 #define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk /*!<Filter bit 17 */
lypinator 0:bb348c97df44 3406 #define CAN_F8R1_FB18_Pos (18U)
lypinator 0:bb348c97df44 3407 #define CAN_F8R1_FB18_Msk (0x1U << CAN_F8R1_FB18_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 3408 #define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk /*!<Filter bit 18 */
lypinator 0:bb348c97df44 3409 #define CAN_F8R1_FB19_Pos (19U)
lypinator 0:bb348c97df44 3410 #define CAN_F8R1_FB19_Msk (0x1U << CAN_F8R1_FB19_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 3411 #define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk /*!<Filter bit 19 */
lypinator 0:bb348c97df44 3412 #define CAN_F8R1_FB20_Pos (20U)
lypinator 0:bb348c97df44 3413 #define CAN_F8R1_FB20_Msk (0x1U << CAN_F8R1_FB20_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 3414 #define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk /*!<Filter bit 20 */
lypinator 0:bb348c97df44 3415 #define CAN_F8R1_FB21_Pos (21U)
lypinator 0:bb348c97df44 3416 #define CAN_F8R1_FB21_Msk (0x1U << CAN_F8R1_FB21_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 3417 #define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk /*!<Filter bit 21 */
lypinator 0:bb348c97df44 3418 #define CAN_F8R1_FB22_Pos (22U)
lypinator 0:bb348c97df44 3419 #define CAN_F8R1_FB22_Msk (0x1U << CAN_F8R1_FB22_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 3420 #define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk /*!<Filter bit 22 */
lypinator 0:bb348c97df44 3421 #define CAN_F8R1_FB23_Pos (23U)
lypinator 0:bb348c97df44 3422 #define CAN_F8R1_FB23_Msk (0x1U << CAN_F8R1_FB23_Pos) /*!< 0x00800000 */
lypinator 0:bb348c97df44 3423 #define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk /*!<Filter bit 23 */
lypinator 0:bb348c97df44 3424 #define CAN_F8R1_FB24_Pos (24U)
lypinator 0:bb348c97df44 3425 #define CAN_F8R1_FB24_Msk (0x1U << CAN_F8R1_FB24_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 3426 #define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk /*!<Filter bit 24 */
lypinator 0:bb348c97df44 3427 #define CAN_F8R1_FB25_Pos (25U)
lypinator 0:bb348c97df44 3428 #define CAN_F8R1_FB25_Msk (0x1U << CAN_F8R1_FB25_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 3429 #define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk /*!<Filter bit 25 */
lypinator 0:bb348c97df44 3430 #define CAN_F8R1_FB26_Pos (26U)
lypinator 0:bb348c97df44 3431 #define CAN_F8R1_FB26_Msk (0x1U << CAN_F8R1_FB26_Pos) /*!< 0x04000000 */
lypinator 0:bb348c97df44 3432 #define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk /*!<Filter bit 26 */
lypinator 0:bb348c97df44 3433 #define CAN_F8R1_FB27_Pos (27U)
lypinator 0:bb348c97df44 3434 #define CAN_F8R1_FB27_Msk (0x1U << CAN_F8R1_FB27_Pos) /*!< 0x08000000 */
lypinator 0:bb348c97df44 3435 #define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk /*!<Filter bit 27 */
lypinator 0:bb348c97df44 3436 #define CAN_F8R1_FB28_Pos (28U)
lypinator 0:bb348c97df44 3437 #define CAN_F8R1_FB28_Msk (0x1U << CAN_F8R1_FB28_Pos) /*!< 0x10000000 */
lypinator 0:bb348c97df44 3438 #define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk /*!<Filter bit 28 */
lypinator 0:bb348c97df44 3439 #define CAN_F8R1_FB29_Pos (29U)
lypinator 0:bb348c97df44 3440 #define CAN_F8R1_FB29_Msk (0x1U << CAN_F8R1_FB29_Pos) /*!< 0x20000000 */
lypinator 0:bb348c97df44 3441 #define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk /*!<Filter bit 29 */
lypinator 0:bb348c97df44 3442 #define CAN_F8R1_FB30_Pos (30U)
lypinator 0:bb348c97df44 3443 #define CAN_F8R1_FB30_Msk (0x1U << CAN_F8R1_FB30_Pos) /*!< 0x40000000 */
lypinator 0:bb348c97df44 3444 #define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk /*!<Filter bit 30 */
lypinator 0:bb348c97df44 3445 #define CAN_F8R1_FB31_Pos (31U)
lypinator 0:bb348c97df44 3446 #define CAN_F8R1_FB31_Msk (0x1U << CAN_F8R1_FB31_Pos) /*!< 0x80000000 */
lypinator 0:bb348c97df44 3447 #define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk /*!<Filter bit 31 */
lypinator 0:bb348c97df44 3448
lypinator 0:bb348c97df44 3449 /******************* Bit definition for CAN_F9R1 register *******************/
lypinator 0:bb348c97df44 3450 #define CAN_F9R1_FB0_Pos (0U)
lypinator 0:bb348c97df44 3451 #define CAN_F9R1_FB0_Msk (0x1U << CAN_F9R1_FB0_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 3452 #define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk /*!<Filter bit 0 */
lypinator 0:bb348c97df44 3453 #define CAN_F9R1_FB1_Pos (1U)
lypinator 0:bb348c97df44 3454 #define CAN_F9R1_FB1_Msk (0x1U << CAN_F9R1_FB1_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 3455 #define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk /*!<Filter bit 1 */
lypinator 0:bb348c97df44 3456 #define CAN_F9R1_FB2_Pos (2U)
lypinator 0:bb348c97df44 3457 #define CAN_F9R1_FB2_Msk (0x1U << CAN_F9R1_FB2_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 3458 #define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk /*!<Filter bit 2 */
lypinator 0:bb348c97df44 3459 #define CAN_F9R1_FB3_Pos (3U)
lypinator 0:bb348c97df44 3460 #define CAN_F9R1_FB3_Msk (0x1U << CAN_F9R1_FB3_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 3461 #define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk /*!<Filter bit 3 */
lypinator 0:bb348c97df44 3462 #define CAN_F9R1_FB4_Pos (4U)
lypinator 0:bb348c97df44 3463 #define CAN_F9R1_FB4_Msk (0x1U << CAN_F9R1_FB4_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 3464 #define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk /*!<Filter bit 4 */
lypinator 0:bb348c97df44 3465 #define CAN_F9R1_FB5_Pos (5U)
lypinator 0:bb348c97df44 3466 #define CAN_F9R1_FB5_Msk (0x1U << CAN_F9R1_FB5_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 3467 #define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk /*!<Filter bit 5 */
lypinator 0:bb348c97df44 3468 #define CAN_F9R1_FB6_Pos (6U)
lypinator 0:bb348c97df44 3469 #define CAN_F9R1_FB6_Msk (0x1U << CAN_F9R1_FB6_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 3470 #define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk /*!<Filter bit 6 */
lypinator 0:bb348c97df44 3471 #define CAN_F9R1_FB7_Pos (7U)
lypinator 0:bb348c97df44 3472 #define CAN_F9R1_FB7_Msk (0x1U << CAN_F9R1_FB7_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 3473 #define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk /*!<Filter bit 7 */
lypinator 0:bb348c97df44 3474 #define CAN_F9R1_FB8_Pos (8U)
lypinator 0:bb348c97df44 3475 #define CAN_F9R1_FB8_Msk (0x1U << CAN_F9R1_FB8_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 3476 #define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk /*!<Filter bit 8 */
lypinator 0:bb348c97df44 3477 #define CAN_F9R1_FB9_Pos (9U)
lypinator 0:bb348c97df44 3478 #define CAN_F9R1_FB9_Msk (0x1U << CAN_F9R1_FB9_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 3479 #define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk /*!<Filter bit 9 */
lypinator 0:bb348c97df44 3480 #define CAN_F9R1_FB10_Pos (10U)
lypinator 0:bb348c97df44 3481 #define CAN_F9R1_FB10_Msk (0x1U << CAN_F9R1_FB10_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 3482 #define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk /*!<Filter bit 10 */
lypinator 0:bb348c97df44 3483 #define CAN_F9R1_FB11_Pos (11U)
lypinator 0:bb348c97df44 3484 #define CAN_F9R1_FB11_Msk (0x1U << CAN_F9R1_FB11_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 3485 #define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk /*!<Filter bit 11 */
lypinator 0:bb348c97df44 3486 #define CAN_F9R1_FB12_Pos (12U)
lypinator 0:bb348c97df44 3487 #define CAN_F9R1_FB12_Msk (0x1U << CAN_F9R1_FB12_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 3488 #define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk /*!<Filter bit 12 */
lypinator 0:bb348c97df44 3489 #define CAN_F9R1_FB13_Pos (13U)
lypinator 0:bb348c97df44 3490 #define CAN_F9R1_FB13_Msk (0x1U << CAN_F9R1_FB13_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 3491 #define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk /*!<Filter bit 13 */
lypinator 0:bb348c97df44 3492 #define CAN_F9R1_FB14_Pos (14U)
lypinator 0:bb348c97df44 3493 #define CAN_F9R1_FB14_Msk (0x1U << CAN_F9R1_FB14_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 3494 #define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk /*!<Filter bit 14 */
lypinator 0:bb348c97df44 3495 #define CAN_F9R1_FB15_Pos (15U)
lypinator 0:bb348c97df44 3496 #define CAN_F9R1_FB15_Msk (0x1U << CAN_F9R1_FB15_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 3497 #define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk /*!<Filter bit 15 */
lypinator 0:bb348c97df44 3498 #define CAN_F9R1_FB16_Pos (16U)
lypinator 0:bb348c97df44 3499 #define CAN_F9R1_FB16_Msk (0x1U << CAN_F9R1_FB16_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 3500 #define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk /*!<Filter bit 16 */
lypinator 0:bb348c97df44 3501 #define CAN_F9R1_FB17_Pos (17U)
lypinator 0:bb348c97df44 3502 #define CAN_F9R1_FB17_Msk (0x1U << CAN_F9R1_FB17_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 3503 #define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk /*!<Filter bit 17 */
lypinator 0:bb348c97df44 3504 #define CAN_F9R1_FB18_Pos (18U)
lypinator 0:bb348c97df44 3505 #define CAN_F9R1_FB18_Msk (0x1U << CAN_F9R1_FB18_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 3506 #define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk /*!<Filter bit 18 */
lypinator 0:bb348c97df44 3507 #define CAN_F9R1_FB19_Pos (19U)
lypinator 0:bb348c97df44 3508 #define CAN_F9R1_FB19_Msk (0x1U << CAN_F9R1_FB19_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 3509 #define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk /*!<Filter bit 19 */
lypinator 0:bb348c97df44 3510 #define CAN_F9R1_FB20_Pos (20U)
lypinator 0:bb348c97df44 3511 #define CAN_F9R1_FB20_Msk (0x1U << CAN_F9R1_FB20_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 3512 #define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk /*!<Filter bit 20 */
lypinator 0:bb348c97df44 3513 #define CAN_F9R1_FB21_Pos (21U)
lypinator 0:bb348c97df44 3514 #define CAN_F9R1_FB21_Msk (0x1U << CAN_F9R1_FB21_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 3515 #define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk /*!<Filter bit 21 */
lypinator 0:bb348c97df44 3516 #define CAN_F9R1_FB22_Pos (22U)
lypinator 0:bb348c97df44 3517 #define CAN_F9R1_FB22_Msk (0x1U << CAN_F9R1_FB22_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 3518 #define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk /*!<Filter bit 22 */
lypinator 0:bb348c97df44 3519 #define CAN_F9R1_FB23_Pos (23U)
lypinator 0:bb348c97df44 3520 #define CAN_F9R1_FB23_Msk (0x1U << CAN_F9R1_FB23_Pos) /*!< 0x00800000 */
lypinator 0:bb348c97df44 3521 #define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk /*!<Filter bit 23 */
lypinator 0:bb348c97df44 3522 #define CAN_F9R1_FB24_Pos (24U)
lypinator 0:bb348c97df44 3523 #define CAN_F9R1_FB24_Msk (0x1U << CAN_F9R1_FB24_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 3524 #define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk /*!<Filter bit 24 */
lypinator 0:bb348c97df44 3525 #define CAN_F9R1_FB25_Pos (25U)
lypinator 0:bb348c97df44 3526 #define CAN_F9R1_FB25_Msk (0x1U << CAN_F9R1_FB25_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 3527 #define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk /*!<Filter bit 25 */
lypinator 0:bb348c97df44 3528 #define CAN_F9R1_FB26_Pos (26U)
lypinator 0:bb348c97df44 3529 #define CAN_F9R1_FB26_Msk (0x1U << CAN_F9R1_FB26_Pos) /*!< 0x04000000 */
lypinator 0:bb348c97df44 3530 #define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk /*!<Filter bit 26 */
lypinator 0:bb348c97df44 3531 #define CAN_F9R1_FB27_Pos (27U)
lypinator 0:bb348c97df44 3532 #define CAN_F9R1_FB27_Msk (0x1U << CAN_F9R1_FB27_Pos) /*!< 0x08000000 */
lypinator 0:bb348c97df44 3533 #define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk /*!<Filter bit 27 */
lypinator 0:bb348c97df44 3534 #define CAN_F9R1_FB28_Pos (28U)
lypinator 0:bb348c97df44 3535 #define CAN_F9R1_FB28_Msk (0x1U << CAN_F9R1_FB28_Pos) /*!< 0x10000000 */
lypinator 0:bb348c97df44 3536 #define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk /*!<Filter bit 28 */
lypinator 0:bb348c97df44 3537 #define CAN_F9R1_FB29_Pos (29U)
lypinator 0:bb348c97df44 3538 #define CAN_F9R1_FB29_Msk (0x1U << CAN_F9R1_FB29_Pos) /*!< 0x20000000 */
lypinator 0:bb348c97df44 3539 #define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk /*!<Filter bit 29 */
lypinator 0:bb348c97df44 3540 #define CAN_F9R1_FB30_Pos (30U)
lypinator 0:bb348c97df44 3541 #define CAN_F9R1_FB30_Msk (0x1U << CAN_F9R1_FB30_Pos) /*!< 0x40000000 */
lypinator 0:bb348c97df44 3542 #define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk /*!<Filter bit 30 */
lypinator 0:bb348c97df44 3543 #define CAN_F9R1_FB31_Pos (31U)
lypinator 0:bb348c97df44 3544 #define CAN_F9R1_FB31_Msk (0x1U << CAN_F9R1_FB31_Pos) /*!< 0x80000000 */
lypinator 0:bb348c97df44 3545 #define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk /*!<Filter bit 31 */
lypinator 0:bb348c97df44 3546
lypinator 0:bb348c97df44 3547 /******************* Bit definition for CAN_F10R1 register ******************/
lypinator 0:bb348c97df44 3548 #define CAN_F10R1_FB0_Pos (0U)
lypinator 0:bb348c97df44 3549 #define CAN_F10R1_FB0_Msk (0x1U << CAN_F10R1_FB0_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 3550 #define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk /*!<Filter bit 0 */
lypinator 0:bb348c97df44 3551 #define CAN_F10R1_FB1_Pos (1U)
lypinator 0:bb348c97df44 3552 #define CAN_F10R1_FB1_Msk (0x1U << CAN_F10R1_FB1_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 3553 #define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk /*!<Filter bit 1 */
lypinator 0:bb348c97df44 3554 #define CAN_F10R1_FB2_Pos (2U)
lypinator 0:bb348c97df44 3555 #define CAN_F10R1_FB2_Msk (0x1U << CAN_F10R1_FB2_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 3556 #define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk /*!<Filter bit 2 */
lypinator 0:bb348c97df44 3557 #define CAN_F10R1_FB3_Pos (3U)
lypinator 0:bb348c97df44 3558 #define CAN_F10R1_FB3_Msk (0x1U << CAN_F10R1_FB3_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 3559 #define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk /*!<Filter bit 3 */
lypinator 0:bb348c97df44 3560 #define CAN_F10R1_FB4_Pos (4U)
lypinator 0:bb348c97df44 3561 #define CAN_F10R1_FB4_Msk (0x1U << CAN_F10R1_FB4_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 3562 #define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk /*!<Filter bit 4 */
lypinator 0:bb348c97df44 3563 #define CAN_F10R1_FB5_Pos (5U)
lypinator 0:bb348c97df44 3564 #define CAN_F10R1_FB5_Msk (0x1U << CAN_F10R1_FB5_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 3565 #define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk /*!<Filter bit 5 */
lypinator 0:bb348c97df44 3566 #define CAN_F10R1_FB6_Pos (6U)
lypinator 0:bb348c97df44 3567 #define CAN_F10R1_FB6_Msk (0x1U << CAN_F10R1_FB6_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 3568 #define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk /*!<Filter bit 6 */
lypinator 0:bb348c97df44 3569 #define CAN_F10R1_FB7_Pos (7U)
lypinator 0:bb348c97df44 3570 #define CAN_F10R1_FB7_Msk (0x1U << CAN_F10R1_FB7_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 3571 #define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk /*!<Filter bit 7 */
lypinator 0:bb348c97df44 3572 #define CAN_F10R1_FB8_Pos (8U)
lypinator 0:bb348c97df44 3573 #define CAN_F10R1_FB8_Msk (0x1U << CAN_F10R1_FB8_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 3574 #define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk /*!<Filter bit 8 */
lypinator 0:bb348c97df44 3575 #define CAN_F10R1_FB9_Pos (9U)
lypinator 0:bb348c97df44 3576 #define CAN_F10R1_FB9_Msk (0x1U << CAN_F10R1_FB9_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 3577 #define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk /*!<Filter bit 9 */
lypinator 0:bb348c97df44 3578 #define CAN_F10R1_FB10_Pos (10U)
lypinator 0:bb348c97df44 3579 #define CAN_F10R1_FB10_Msk (0x1U << CAN_F10R1_FB10_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 3580 #define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk /*!<Filter bit 10 */
lypinator 0:bb348c97df44 3581 #define CAN_F10R1_FB11_Pos (11U)
lypinator 0:bb348c97df44 3582 #define CAN_F10R1_FB11_Msk (0x1U << CAN_F10R1_FB11_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 3583 #define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk /*!<Filter bit 11 */
lypinator 0:bb348c97df44 3584 #define CAN_F10R1_FB12_Pos (12U)
lypinator 0:bb348c97df44 3585 #define CAN_F10R1_FB12_Msk (0x1U << CAN_F10R1_FB12_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 3586 #define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk /*!<Filter bit 12 */
lypinator 0:bb348c97df44 3587 #define CAN_F10R1_FB13_Pos (13U)
lypinator 0:bb348c97df44 3588 #define CAN_F10R1_FB13_Msk (0x1U << CAN_F10R1_FB13_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 3589 #define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk /*!<Filter bit 13 */
lypinator 0:bb348c97df44 3590 #define CAN_F10R1_FB14_Pos (14U)
lypinator 0:bb348c97df44 3591 #define CAN_F10R1_FB14_Msk (0x1U << CAN_F10R1_FB14_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 3592 #define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk /*!<Filter bit 14 */
lypinator 0:bb348c97df44 3593 #define CAN_F10R1_FB15_Pos (15U)
lypinator 0:bb348c97df44 3594 #define CAN_F10R1_FB15_Msk (0x1U << CAN_F10R1_FB15_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 3595 #define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk /*!<Filter bit 15 */
lypinator 0:bb348c97df44 3596 #define CAN_F10R1_FB16_Pos (16U)
lypinator 0:bb348c97df44 3597 #define CAN_F10R1_FB16_Msk (0x1U << CAN_F10R1_FB16_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 3598 #define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk /*!<Filter bit 16 */
lypinator 0:bb348c97df44 3599 #define CAN_F10R1_FB17_Pos (17U)
lypinator 0:bb348c97df44 3600 #define CAN_F10R1_FB17_Msk (0x1U << CAN_F10R1_FB17_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 3601 #define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk /*!<Filter bit 17 */
lypinator 0:bb348c97df44 3602 #define CAN_F10R1_FB18_Pos (18U)
lypinator 0:bb348c97df44 3603 #define CAN_F10R1_FB18_Msk (0x1U << CAN_F10R1_FB18_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 3604 #define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk /*!<Filter bit 18 */
lypinator 0:bb348c97df44 3605 #define CAN_F10R1_FB19_Pos (19U)
lypinator 0:bb348c97df44 3606 #define CAN_F10R1_FB19_Msk (0x1U << CAN_F10R1_FB19_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 3607 #define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk /*!<Filter bit 19 */
lypinator 0:bb348c97df44 3608 #define CAN_F10R1_FB20_Pos (20U)
lypinator 0:bb348c97df44 3609 #define CAN_F10R1_FB20_Msk (0x1U << CAN_F10R1_FB20_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 3610 #define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk /*!<Filter bit 20 */
lypinator 0:bb348c97df44 3611 #define CAN_F10R1_FB21_Pos (21U)
lypinator 0:bb348c97df44 3612 #define CAN_F10R1_FB21_Msk (0x1U << CAN_F10R1_FB21_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 3613 #define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk /*!<Filter bit 21 */
lypinator 0:bb348c97df44 3614 #define CAN_F10R1_FB22_Pos (22U)
lypinator 0:bb348c97df44 3615 #define CAN_F10R1_FB22_Msk (0x1U << CAN_F10R1_FB22_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 3616 #define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk /*!<Filter bit 22 */
lypinator 0:bb348c97df44 3617 #define CAN_F10R1_FB23_Pos (23U)
lypinator 0:bb348c97df44 3618 #define CAN_F10R1_FB23_Msk (0x1U << CAN_F10R1_FB23_Pos) /*!< 0x00800000 */
lypinator 0:bb348c97df44 3619 #define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk /*!<Filter bit 23 */
lypinator 0:bb348c97df44 3620 #define CAN_F10R1_FB24_Pos (24U)
lypinator 0:bb348c97df44 3621 #define CAN_F10R1_FB24_Msk (0x1U << CAN_F10R1_FB24_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 3622 #define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk /*!<Filter bit 24 */
lypinator 0:bb348c97df44 3623 #define CAN_F10R1_FB25_Pos (25U)
lypinator 0:bb348c97df44 3624 #define CAN_F10R1_FB25_Msk (0x1U << CAN_F10R1_FB25_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 3625 #define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk /*!<Filter bit 25 */
lypinator 0:bb348c97df44 3626 #define CAN_F10R1_FB26_Pos (26U)
lypinator 0:bb348c97df44 3627 #define CAN_F10R1_FB26_Msk (0x1U << CAN_F10R1_FB26_Pos) /*!< 0x04000000 */
lypinator 0:bb348c97df44 3628 #define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk /*!<Filter bit 26 */
lypinator 0:bb348c97df44 3629 #define CAN_F10R1_FB27_Pos (27U)
lypinator 0:bb348c97df44 3630 #define CAN_F10R1_FB27_Msk (0x1U << CAN_F10R1_FB27_Pos) /*!< 0x08000000 */
lypinator 0:bb348c97df44 3631 #define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk /*!<Filter bit 27 */
lypinator 0:bb348c97df44 3632 #define CAN_F10R1_FB28_Pos (28U)
lypinator 0:bb348c97df44 3633 #define CAN_F10R1_FB28_Msk (0x1U << CAN_F10R1_FB28_Pos) /*!< 0x10000000 */
lypinator 0:bb348c97df44 3634 #define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk /*!<Filter bit 28 */
lypinator 0:bb348c97df44 3635 #define CAN_F10R1_FB29_Pos (29U)
lypinator 0:bb348c97df44 3636 #define CAN_F10R1_FB29_Msk (0x1U << CAN_F10R1_FB29_Pos) /*!< 0x20000000 */
lypinator 0:bb348c97df44 3637 #define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk /*!<Filter bit 29 */
lypinator 0:bb348c97df44 3638 #define CAN_F10R1_FB30_Pos (30U)
lypinator 0:bb348c97df44 3639 #define CAN_F10R1_FB30_Msk (0x1U << CAN_F10R1_FB30_Pos) /*!< 0x40000000 */
lypinator 0:bb348c97df44 3640 #define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk /*!<Filter bit 30 */
lypinator 0:bb348c97df44 3641 #define CAN_F10R1_FB31_Pos (31U)
lypinator 0:bb348c97df44 3642 #define CAN_F10R1_FB31_Msk (0x1U << CAN_F10R1_FB31_Pos) /*!< 0x80000000 */
lypinator 0:bb348c97df44 3643 #define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk /*!<Filter bit 31 */
lypinator 0:bb348c97df44 3644
lypinator 0:bb348c97df44 3645 /******************* Bit definition for CAN_F11R1 register ******************/
lypinator 0:bb348c97df44 3646 #define CAN_F11R1_FB0_Pos (0U)
lypinator 0:bb348c97df44 3647 #define CAN_F11R1_FB0_Msk (0x1U << CAN_F11R1_FB0_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 3648 #define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk /*!<Filter bit 0 */
lypinator 0:bb348c97df44 3649 #define CAN_F11R1_FB1_Pos (1U)
lypinator 0:bb348c97df44 3650 #define CAN_F11R1_FB1_Msk (0x1U << CAN_F11R1_FB1_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 3651 #define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk /*!<Filter bit 1 */
lypinator 0:bb348c97df44 3652 #define CAN_F11R1_FB2_Pos (2U)
lypinator 0:bb348c97df44 3653 #define CAN_F11R1_FB2_Msk (0x1U << CAN_F11R1_FB2_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 3654 #define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk /*!<Filter bit 2 */
lypinator 0:bb348c97df44 3655 #define CAN_F11R1_FB3_Pos (3U)
lypinator 0:bb348c97df44 3656 #define CAN_F11R1_FB3_Msk (0x1U << CAN_F11R1_FB3_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 3657 #define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk /*!<Filter bit 3 */
lypinator 0:bb348c97df44 3658 #define CAN_F11R1_FB4_Pos (4U)
lypinator 0:bb348c97df44 3659 #define CAN_F11R1_FB4_Msk (0x1U << CAN_F11R1_FB4_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 3660 #define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk /*!<Filter bit 4 */
lypinator 0:bb348c97df44 3661 #define CAN_F11R1_FB5_Pos (5U)
lypinator 0:bb348c97df44 3662 #define CAN_F11R1_FB5_Msk (0x1U << CAN_F11R1_FB5_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 3663 #define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk /*!<Filter bit 5 */
lypinator 0:bb348c97df44 3664 #define CAN_F11R1_FB6_Pos (6U)
lypinator 0:bb348c97df44 3665 #define CAN_F11R1_FB6_Msk (0x1U << CAN_F11R1_FB6_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 3666 #define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk /*!<Filter bit 6 */
lypinator 0:bb348c97df44 3667 #define CAN_F11R1_FB7_Pos (7U)
lypinator 0:bb348c97df44 3668 #define CAN_F11R1_FB7_Msk (0x1U << CAN_F11R1_FB7_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 3669 #define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk /*!<Filter bit 7 */
lypinator 0:bb348c97df44 3670 #define CAN_F11R1_FB8_Pos (8U)
lypinator 0:bb348c97df44 3671 #define CAN_F11R1_FB8_Msk (0x1U << CAN_F11R1_FB8_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 3672 #define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk /*!<Filter bit 8 */
lypinator 0:bb348c97df44 3673 #define CAN_F11R1_FB9_Pos (9U)
lypinator 0:bb348c97df44 3674 #define CAN_F11R1_FB9_Msk (0x1U << CAN_F11R1_FB9_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 3675 #define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk /*!<Filter bit 9 */
lypinator 0:bb348c97df44 3676 #define CAN_F11R1_FB10_Pos (10U)
lypinator 0:bb348c97df44 3677 #define CAN_F11R1_FB10_Msk (0x1U << CAN_F11R1_FB10_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 3678 #define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk /*!<Filter bit 10 */
lypinator 0:bb348c97df44 3679 #define CAN_F11R1_FB11_Pos (11U)
lypinator 0:bb348c97df44 3680 #define CAN_F11R1_FB11_Msk (0x1U << CAN_F11R1_FB11_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 3681 #define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk /*!<Filter bit 11 */
lypinator 0:bb348c97df44 3682 #define CAN_F11R1_FB12_Pos (12U)
lypinator 0:bb348c97df44 3683 #define CAN_F11R1_FB12_Msk (0x1U << CAN_F11R1_FB12_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 3684 #define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk /*!<Filter bit 12 */
lypinator 0:bb348c97df44 3685 #define CAN_F11R1_FB13_Pos (13U)
lypinator 0:bb348c97df44 3686 #define CAN_F11R1_FB13_Msk (0x1U << CAN_F11R1_FB13_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 3687 #define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk /*!<Filter bit 13 */
lypinator 0:bb348c97df44 3688 #define CAN_F11R1_FB14_Pos (14U)
lypinator 0:bb348c97df44 3689 #define CAN_F11R1_FB14_Msk (0x1U << CAN_F11R1_FB14_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 3690 #define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk /*!<Filter bit 14 */
lypinator 0:bb348c97df44 3691 #define CAN_F11R1_FB15_Pos (15U)
lypinator 0:bb348c97df44 3692 #define CAN_F11R1_FB15_Msk (0x1U << CAN_F11R1_FB15_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 3693 #define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk /*!<Filter bit 15 */
lypinator 0:bb348c97df44 3694 #define CAN_F11R1_FB16_Pos (16U)
lypinator 0:bb348c97df44 3695 #define CAN_F11R1_FB16_Msk (0x1U << CAN_F11R1_FB16_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 3696 #define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk /*!<Filter bit 16 */
lypinator 0:bb348c97df44 3697 #define CAN_F11R1_FB17_Pos (17U)
lypinator 0:bb348c97df44 3698 #define CAN_F11R1_FB17_Msk (0x1U << CAN_F11R1_FB17_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 3699 #define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk /*!<Filter bit 17 */
lypinator 0:bb348c97df44 3700 #define CAN_F11R1_FB18_Pos (18U)
lypinator 0:bb348c97df44 3701 #define CAN_F11R1_FB18_Msk (0x1U << CAN_F11R1_FB18_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 3702 #define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk /*!<Filter bit 18 */
lypinator 0:bb348c97df44 3703 #define CAN_F11R1_FB19_Pos (19U)
lypinator 0:bb348c97df44 3704 #define CAN_F11R1_FB19_Msk (0x1U << CAN_F11R1_FB19_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 3705 #define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk /*!<Filter bit 19 */
lypinator 0:bb348c97df44 3706 #define CAN_F11R1_FB20_Pos (20U)
lypinator 0:bb348c97df44 3707 #define CAN_F11R1_FB20_Msk (0x1U << CAN_F11R1_FB20_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 3708 #define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk /*!<Filter bit 20 */
lypinator 0:bb348c97df44 3709 #define CAN_F11R1_FB21_Pos (21U)
lypinator 0:bb348c97df44 3710 #define CAN_F11R1_FB21_Msk (0x1U << CAN_F11R1_FB21_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 3711 #define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk /*!<Filter bit 21 */
lypinator 0:bb348c97df44 3712 #define CAN_F11R1_FB22_Pos (22U)
lypinator 0:bb348c97df44 3713 #define CAN_F11R1_FB22_Msk (0x1U << CAN_F11R1_FB22_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 3714 #define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk /*!<Filter bit 22 */
lypinator 0:bb348c97df44 3715 #define CAN_F11R1_FB23_Pos (23U)
lypinator 0:bb348c97df44 3716 #define CAN_F11R1_FB23_Msk (0x1U << CAN_F11R1_FB23_Pos) /*!< 0x00800000 */
lypinator 0:bb348c97df44 3717 #define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk /*!<Filter bit 23 */
lypinator 0:bb348c97df44 3718 #define CAN_F11R1_FB24_Pos (24U)
lypinator 0:bb348c97df44 3719 #define CAN_F11R1_FB24_Msk (0x1U << CAN_F11R1_FB24_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 3720 #define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk /*!<Filter bit 24 */
lypinator 0:bb348c97df44 3721 #define CAN_F11R1_FB25_Pos (25U)
lypinator 0:bb348c97df44 3722 #define CAN_F11R1_FB25_Msk (0x1U << CAN_F11R1_FB25_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 3723 #define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk /*!<Filter bit 25 */
lypinator 0:bb348c97df44 3724 #define CAN_F11R1_FB26_Pos (26U)
lypinator 0:bb348c97df44 3725 #define CAN_F11R1_FB26_Msk (0x1U << CAN_F11R1_FB26_Pos) /*!< 0x04000000 */
lypinator 0:bb348c97df44 3726 #define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk /*!<Filter bit 26 */
lypinator 0:bb348c97df44 3727 #define CAN_F11R1_FB27_Pos (27U)
lypinator 0:bb348c97df44 3728 #define CAN_F11R1_FB27_Msk (0x1U << CAN_F11R1_FB27_Pos) /*!< 0x08000000 */
lypinator 0:bb348c97df44 3729 #define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk /*!<Filter bit 27 */
lypinator 0:bb348c97df44 3730 #define CAN_F11R1_FB28_Pos (28U)
lypinator 0:bb348c97df44 3731 #define CAN_F11R1_FB28_Msk (0x1U << CAN_F11R1_FB28_Pos) /*!< 0x10000000 */
lypinator 0:bb348c97df44 3732 #define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk /*!<Filter bit 28 */
lypinator 0:bb348c97df44 3733 #define CAN_F11R1_FB29_Pos (29U)
lypinator 0:bb348c97df44 3734 #define CAN_F11R1_FB29_Msk (0x1U << CAN_F11R1_FB29_Pos) /*!< 0x20000000 */
lypinator 0:bb348c97df44 3735 #define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk /*!<Filter bit 29 */
lypinator 0:bb348c97df44 3736 #define CAN_F11R1_FB30_Pos (30U)
lypinator 0:bb348c97df44 3737 #define CAN_F11R1_FB30_Msk (0x1U << CAN_F11R1_FB30_Pos) /*!< 0x40000000 */
lypinator 0:bb348c97df44 3738 #define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk /*!<Filter bit 30 */
lypinator 0:bb348c97df44 3739 #define CAN_F11R1_FB31_Pos (31U)
lypinator 0:bb348c97df44 3740 #define CAN_F11R1_FB31_Msk (0x1U << CAN_F11R1_FB31_Pos) /*!< 0x80000000 */
lypinator 0:bb348c97df44 3741 #define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk /*!<Filter bit 31 */
lypinator 0:bb348c97df44 3742
lypinator 0:bb348c97df44 3743 /******************* Bit definition for CAN_F12R1 register ******************/
lypinator 0:bb348c97df44 3744 #define CAN_F12R1_FB0_Pos (0U)
lypinator 0:bb348c97df44 3745 #define CAN_F12R1_FB0_Msk (0x1U << CAN_F12R1_FB0_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 3746 #define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk /*!<Filter bit 0 */
lypinator 0:bb348c97df44 3747 #define CAN_F12R1_FB1_Pos (1U)
lypinator 0:bb348c97df44 3748 #define CAN_F12R1_FB1_Msk (0x1U << CAN_F12R1_FB1_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 3749 #define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk /*!<Filter bit 1 */
lypinator 0:bb348c97df44 3750 #define CAN_F12R1_FB2_Pos (2U)
lypinator 0:bb348c97df44 3751 #define CAN_F12R1_FB2_Msk (0x1U << CAN_F12R1_FB2_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 3752 #define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk /*!<Filter bit 2 */
lypinator 0:bb348c97df44 3753 #define CAN_F12R1_FB3_Pos (3U)
lypinator 0:bb348c97df44 3754 #define CAN_F12R1_FB3_Msk (0x1U << CAN_F12R1_FB3_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 3755 #define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk /*!<Filter bit 3 */
lypinator 0:bb348c97df44 3756 #define CAN_F12R1_FB4_Pos (4U)
lypinator 0:bb348c97df44 3757 #define CAN_F12R1_FB4_Msk (0x1U << CAN_F12R1_FB4_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 3758 #define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk /*!<Filter bit 4 */
lypinator 0:bb348c97df44 3759 #define CAN_F12R1_FB5_Pos (5U)
lypinator 0:bb348c97df44 3760 #define CAN_F12R1_FB5_Msk (0x1U << CAN_F12R1_FB5_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 3761 #define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk /*!<Filter bit 5 */
lypinator 0:bb348c97df44 3762 #define CAN_F12R1_FB6_Pos (6U)
lypinator 0:bb348c97df44 3763 #define CAN_F12R1_FB6_Msk (0x1U << CAN_F12R1_FB6_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 3764 #define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk /*!<Filter bit 6 */
lypinator 0:bb348c97df44 3765 #define CAN_F12R1_FB7_Pos (7U)
lypinator 0:bb348c97df44 3766 #define CAN_F12R1_FB7_Msk (0x1U << CAN_F12R1_FB7_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 3767 #define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk /*!<Filter bit 7 */
lypinator 0:bb348c97df44 3768 #define CAN_F12R1_FB8_Pos (8U)
lypinator 0:bb348c97df44 3769 #define CAN_F12R1_FB8_Msk (0x1U << CAN_F12R1_FB8_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 3770 #define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk /*!<Filter bit 8 */
lypinator 0:bb348c97df44 3771 #define CAN_F12R1_FB9_Pos (9U)
lypinator 0:bb348c97df44 3772 #define CAN_F12R1_FB9_Msk (0x1U << CAN_F12R1_FB9_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 3773 #define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk /*!<Filter bit 9 */
lypinator 0:bb348c97df44 3774 #define CAN_F12R1_FB10_Pos (10U)
lypinator 0:bb348c97df44 3775 #define CAN_F12R1_FB10_Msk (0x1U << CAN_F12R1_FB10_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 3776 #define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk /*!<Filter bit 10 */
lypinator 0:bb348c97df44 3777 #define CAN_F12R1_FB11_Pos (11U)
lypinator 0:bb348c97df44 3778 #define CAN_F12R1_FB11_Msk (0x1U << CAN_F12R1_FB11_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 3779 #define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk /*!<Filter bit 11 */
lypinator 0:bb348c97df44 3780 #define CAN_F12R1_FB12_Pos (12U)
lypinator 0:bb348c97df44 3781 #define CAN_F12R1_FB12_Msk (0x1U << CAN_F12R1_FB12_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 3782 #define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk /*!<Filter bit 12 */
lypinator 0:bb348c97df44 3783 #define CAN_F12R1_FB13_Pos (13U)
lypinator 0:bb348c97df44 3784 #define CAN_F12R1_FB13_Msk (0x1U << CAN_F12R1_FB13_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 3785 #define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk /*!<Filter bit 13 */
lypinator 0:bb348c97df44 3786 #define CAN_F12R1_FB14_Pos (14U)
lypinator 0:bb348c97df44 3787 #define CAN_F12R1_FB14_Msk (0x1U << CAN_F12R1_FB14_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 3788 #define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk /*!<Filter bit 14 */
lypinator 0:bb348c97df44 3789 #define CAN_F12R1_FB15_Pos (15U)
lypinator 0:bb348c97df44 3790 #define CAN_F12R1_FB15_Msk (0x1U << CAN_F12R1_FB15_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 3791 #define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk /*!<Filter bit 15 */
lypinator 0:bb348c97df44 3792 #define CAN_F12R1_FB16_Pos (16U)
lypinator 0:bb348c97df44 3793 #define CAN_F12R1_FB16_Msk (0x1U << CAN_F12R1_FB16_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 3794 #define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk /*!<Filter bit 16 */
lypinator 0:bb348c97df44 3795 #define CAN_F12R1_FB17_Pos (17U)
lypinator 0:bb348c97df44 3796 #define CAN_F12R1_FB17_Msk (0x1U << CAN_F12R1_FB17_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 3797 #define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk /*!<Filter bit 17 */
lypinator 0:bb348c97df44 3798 #define CAN_F12R1_FB18_Pos (18U)
lypinator 0:bb348c97df44 3799 #define CAN_F12R1_FB18_Msk (0x1U << CAN_F12R1_FB18_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 3800 #define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk /*!<Filter bit 18 */
lypinator 0:bb348c97df44 3801 #define CAN_F12R1_FB19_Pos (19U)
lypinator 0:bb348c97df44 3802 #define CAN_F12R1_FB19_Msk (0x1U << CAN_F12R1_FB19_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 3803 #define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk /*!<Filter bit 19 */
lypinator 0:bb348c97df44 3804 #define CAN_F12R1_FB20_Pos (20U)
lypinator 0:bb348c97df44 3805 #define CAN_F12R1_FB20_Msk (0x1U << CAN_F12R1_FB20_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 3806 #define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk /*!<Filter bit 20 */
lypinator 0:bb348c97df44 3807 #define CAN_F12R1_FB21_Pos (21U)
lypinator 0:bb348c97df44 3808 #define CAN_F12R1_FB21_Msk (0x1U << CAN_F12R1_FB21_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 3809 #define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk /*!<Filter bit 21 */
lypinator 0:bb348c97df44 3810 #define CAN_F12R1_FB22_Pos (22U)
lypinator 0:bb348c97df44 3811 #define CAN_F12R1_FB22_Msk (0x1U << CAN_F12R1_FB22_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 3812 #define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk /*!<Filter bit 22 */
lypinator 0:bb348c97df44 3813 #define CAN_F12R1_FB23_Pos (23U)
lypinator 0:bb348c97df44 3814 #define CAN_F12R1_FB23_Msk (0x1U << CAN_F12R1_FB23_Pos) /*!< 0x00800000 */
lypinator 0:bb348c97df44 3815 #define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk /*!<Filter bit 23 */
lypinator 0:bb348c97df44 3816 #define CAN_F12R1_FB24_Pos (24U)
lypinator 0:bb348c97df44 3817 #define CAN_F12R1_FB24_Msk (0x1U << CAN_F12R1_FB24_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 3818 #define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk /*!<Filter bit 24 */
lypinator 0:bb348c97df44 3819 #define CAN_F12R1_FB25_Pos (25U)
lypinator 0:bb348c97df44 3820 #define CAN_F12R1_FB25_Msk (0x1U << CAN_F12R1_FB25_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 3821 #define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk /*!<Filter bit 25 */
lypinator 0:bb348c97df44 3822 #define CAN_F12R1_FB26_Pos (26U)
lypinator 0:bb348c97df44 3823 #define CAN_F12R1_FB26_Msk (0x1U << CAN_F12R1_FB26_Pos) /*!< 0x04000000 */
lypinator 0:bb348c97df44 3824 #define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk /*!<Filter bit 26 */
lypinator 0:bb348c97df44 3825 #define CAN_F12R1_FB27_Pos (27U)
lypinator 0:bb348c97df44 3826 #define CAN_F12R1_FB27_Msk (0x1U << CAN_F12R1_FB27_Pos) /*!< 0x08000000 */
lypinator 0:bb348c97df44 3827 #define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk /*!<Filter bit 27 */
lypinator 0:bb348c97df44 3828 #define CAN_F12R1_FB28_Pos (28U)
lypinator 0:bb348c97df44 3829 #define CAN_F12R1_FB28_Msk (0x1U << CAN_F12R1_FB28_Pos) /*!< 0x10000000 */
lypinator 0:bb348c97df44 3830 #define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk /*!<Filter bit 28 */
lypinator 0:bb348c97df44 3831 #define CAN_F12R1_FB29_Pos (29U)
lypinator 0:bb348c97df44 3832 #define CAN_F12R1_FB29_Msk (0x1U << CAN_F12R1_FB29_Pos) /*!< 0x20000000 */
lypinator 0:bb348c97df44 3833 #define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk /*!<Filter bit 29 */
lypinator 0:bb348c97df44 3834 #define CAN_F12R1_FB30_Pos (30U)
lypinator 0:bb348c97df44 3835 #define CAN_F12R1_FB30_Msk (0x1U << CAN_F12R1_FB30_Pos) /*!< 0x40000000 */
lypinator 0:bb348c97df44 3836 #define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk /*!<Filter bit 30 */
lypinator 0:bb348c97df44 3837 #define CAN_F12R1_FB31_Pos (31U)
lypinator 0:bb348c97df44 3838 #define CAN_F12R1_FB31_Msk (0x1U << CAN_F12R1_FB31_Pos) /*!< 0x80000000 */
lypinator 0:bb348c97df44 3839 #define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk /*!<Filter bit 31 */
lypinator 0:bb348c97df44 3840
lypinator 0:bb348c97df44 3841 /******************* Bit definition for CAN_F13R1 register ******************/
lypinator 0:bb348c97df44 3842 #define CAN_F13R1_FB0_Pos (0U)
lypinator 0:bb348c97df44 3843 #define CAN_F13R1_FB0_Msk (0x1U << CAN_F13R1_FB0_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 3844 #define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk /*!<Filter bit 0 */
lypinator 0:bb348c97df44 3845 #define CAN_F13R1_FB1_Pos (1U)
lypinator 0:bb348c97df44 3846 #define CAN_F13R1_FB1_Msk (0x1U << CAN_F13R1_FB1_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 3847 #define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk /*!<Filter bit 1 */
lypinator 0:bb348c97df44 3848 #define CAN_F13R1_FB2_Pos (2U)
lypinator 0:bb348c97df44 3849 #define CAN_F13R1_FB2_Msk (0x1U << CAN_F13R1_FB2_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 3850 #define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk /*!<Filter bit 2 */
lypinator 0:bb348c97df44 3851 #define CAN_F13R1_FB3_Pos (3U)
lypinator 0:bb348c97df44 3852 #define CAN_F13R1_FB3_Msk (0x1U << CAN_F13R1_FB3_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 3853 #define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk /*!<Filter bit 3 */
lypinator 0:bb348c97df44 3854 #define CAN_F13R1_FB4_Pos (4U)
lypinator 0:bb348c97df44 3855 #define CAN_F13R1_FB4_Msk (0x1U << CAN_F13R1_FB4_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 3856 #define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk /*!<Filter bit 4 */
lypinator 0:bb348c97df44 3857 #define CAN_F13R1_FB5_Pos (5U)
lypinator 0:bb348c97df44 3858 #define CAN_F13R1_FB5_Msk (0x1U << CAN_F13R1_FB5_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 3859 #define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk /*!<Filter bit 5 */
lypinator 0:bb348c97df44 3860 #define CAN_F13R1_FB6_Pos (6U)
lypinator 0:bb348c97df44 3861 #define CAN_F13R1_FB6_Msk (0x1U << CAN_F13R1_FB6_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 3862 #define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk /*!<Filter bit 6 */
lypinator 0:bb348c97df44 3863 #define CAN_F13R1_FB7_Pos (7U)
lypinator 0:bb348c97df44 3864 #define CAN_F13R1_FB7_Msk (0x1U << CAN_F13R1_FB7_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 3865 #define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk /*!<Filter bit 7 */
lypinator 0:bb348c97df44 3866 #define CAN_F13R1_FB8_Pos (8U)
lypinator 0:bb348c97df44 3867 #define CAN_F13R1_FB8_Msk (0x1U << CAN_F13R1_FB8_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 3868 #define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk /*!<Filter bit 8 */
lypinator 0:bb348c97df44 3869 #define CAN_F13R1_FB9_Pos (9U)
lypinator 0:bb348c97df44 3870 #define CAN_F13R1_FB9_Msk (0x1U << CAN_F13R1_FB9_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 3871 #define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk /*!<Filter bit 9 */
lypinator 0:bb348c97df44 3872 #define CAN_F13R1_FB10_Pos (10U)
lypinator 0:bb348c97df44 3873 #define CAN_F13R1_FB10_Msk (0x1U << CAN_F13R1_FB10_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 3874 #define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk /*!<Filter bit 10 */
lypinator 0:bb348c97df44 3875 #define CAN_F13R1_FB11_Pos (11U)
lypinator 0:bb348c97df44 3876 #define CAN_F13R1_FB11_Msk (0x1U << CAN_F13R1_FB11_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 3877 #define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk /*!<Filter bit 11 */
lypinator 0:bb348c97df44 3878 #define CAN_F13R1_FB12_Pos (12U)
lypinator 0:bb348c97df44 3879 #define CAN_F13R1_FB12_Msk (0x1U << CAN_F13R1_FB12_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 3880 #define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk /*!<Filter bit 12 */
lypinator 0:bb348c97df44 3881 #define CAN_F13R1_FB13_Pos (13U)
lypinator 0:bb348c97df44 3882 #define CAN_F13R1_FB13_Msk (0x1U << CAN_F13R1_FB13_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 3883 #define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk /*!<Filter bit 13 */
lypinator 0:bb348c97df44 3884 #define CAN_F13R1_FB14_Pos (14U)
lypinator 0:bb348c97df44 3885 #define CAN_F13R1_FB14_Msk (0x1U << CAN_F13R1_FB14_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 3886 #define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk /*!<Filter bit 14 */
lypinator 0:bb348c97df44 3887 #define CAN_F13R1_FB15_Pos (15U)
lypinator 0:bb348c97df44 3888 #define CAN_F13R1_FB15_Msk (0x1U << CAN_F13R1_FB15_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 3889 #define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk /*!<Filter bit 15 */
lypinator 0:bb348c97df44 3890 #define CAN_F13R1_FB16_Pos (16U)
lypinator 0:bb348c97df44 3891 #define CAN_F13R1_FB16_Msk (0x1U << CAN_F13R1_FB16_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 3892 #define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk /*!<Filter bit 16 */
lypinator 0:bb348c97df44 3893 #define CAN_F13R1_FB17_Pos (17U)
lypinator 0:bb348c97df44 3894 #define CAN_F13R1_FB17_Msk (0x1U << CAN_F13R1_FB17_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 3895 #define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk /*!<Filter bit 17 */
lypinator 0:bb348c97df44 3896 #define CAN_F13R1_FB18_Pos (18U)
lypinator 0:bb348c97df44 3897 #define CAN_F13R1_FB18_Msk (0x1U << CAN_F13R1_FB18_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 3898 #define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk /*!<Filter bit 18 */
lypinator 0:bb348c97df44 3899 #define CAN_F13R1_FB19_Pos (19U)
lypinator 0:bb348c97df44 3900 #define CAN_F13R1_FB19_Msk (0x1U << CAN_F13R1_FB19_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 3901 #define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk /*!<Filter bit 19 */
lypinator 0:bb348c97df44 3902 #define CAN_F13R1_FB20_Pos (20U)
lypinator 0:bb348c97df44 3903 #define CAN_F13R1_FB20_Msk (0x1U << CAN_F13R1_FB20_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 3904 #define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk /*!<Filter bit 20 */
lypinator 0:bb348c97df44 3905 #define CAN_F13R1_FB21_Pos (21U)
lypinator 0:bb348c97df44 3906 #define CAN_F13R1_FB21_Msk (0x1U << CAN_F13R1_FB21_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 3907 #define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk /*!<Filter bit 21 */
lypinator 0:bb348c97df44 3908 #define CAN_F13R1_FB22_Pos (22U)
lypinator 0:bb348c97df44 3909 #define CAN_F13R1_FB22_Msk (0x1U << CAN_F13R1_FB22_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 3910 #define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk /*!<Filter bit 22 */
lypinator 0:bb348c97df44 3911 #define CAN_F13R1_FB23_Pos (23U)
lypinator 0:bb348c97df44 3912 #define CAN_F13R1_FB23_Msk (0x1U << CAN_F13R1_FB23_Pos) /*!< 0x00800000 */
lypinator 0:bb348c97df44 3913 #define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk /*!<Filter bit 23 */
lypinator 0:bb348c97df44 3914 #define CAN_F13R1_FB24_Pos (24U)
lypinator 0:bb348c97df44 3915 #define CAN_F13R1_FB24_Msk (0x1U << CAN_F13R1_FB24_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 3916 #define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk /*!<Filter bit 24 */
lypinator 0:bb348c97df44 3917 #define CAN_F13R1_FB25_Pos (25U)
lypinator 0:bb348c97df44 3918 #define CAN_F13R1_FB25_Msk (0x1U << CAN_F13R1_FB25_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 3919 #define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk /*!<Filter bit 25 */
lypinator 0:bb348c97df44 3920 #define CAN_F13R1_FB26_Pos (26U)
lypinator 0:bb348c97df44 3921 #define CAN_F13R1_FB26_Msk (0x1U << CAN_F13R1_FB26_Pos) /*!< 0x04000000 */
lypinator 0:bb348c97df44 3922 #define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk /*!<Filter bit 26 */
lypinator 0:bb348c97df44 3923 #define CAN_F13R1_FB27_Pos (27U)
lypinator 0:bb348c97df44 3924 #define CAN_F13R1_FB27_Msk (0x1U << CAN_F13R1_FB27_Pos) /*!< 0x08000000 */
lypinator 0:bb348c97df44 3925 #define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk /*!<Filter bit 27 */
lypinator 0:bb348c97df44 3926 #define CAN_F13R1_FB28_Pos (28U)
lypinator 0:bb348c97df44 3927 #define CAN_F13R1_FB28_Msk (0x1U << CAN_F13R1_FB28_Pos) /*!< 0x10000000 */
lypinator 0:bb348c97df44 3928 #define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk /*!<Filter bit 28 */
lypinator 0:bb348c97df44 3929 #define CAN_F13R1_FB29_Pos (29U)
lypinator 0:bb348c97df44 3930 #define CAN_F13R1_FB29_Msk (0x1U << CAN_F13R1_FB29_Pos) /*!< 0x20000000 */
lypinator 0:bb348c97df44 3931 #define CAN_F13R1_FB29 CAN_F13R1_FB29_Msk /*!<Filter bit 29 */
lypinator 0:bb348c97df44 3932 #define CAN_F13R1_FB30_Pos (30U)
lypinator 0:bb348c97df44 3933 #define CAN_F13R1_FB30_Msk (0x1U << CAN_F13R1_FB30_Pos) /*!< 0x40000000 */
lypinator 0:bb348c97df44 3934 #define CAN_F13R1_FB30 CAN_F13R1_FB30_Msk /*!<Filter bit 30 */
lypinator 0:bb348c97df44 3935 #define CAN_F13R1_FB31_Pos (31U)
lypinator 0:bb348c97df44 3936 #define CAN_F13R1_FB31_Msk (0x1U << CAN_F13R1_FB31_Pos) /*!< 0x80000000 */
lypinator 0:bb348c97df44 3937 #define CAN_F13R1_FB31 CAN_F13R1_FB31_Msk /*!<Filter bit 31 */
lypinator 0:bb348c97df44 3938
lypinator 0:bb348c97df44 3939 /******************* Bit definition for CAN_F0R2 register *******************/
lypinator 0:bb348c97df44 3940 #define CAN_F0R2_FB0_Pos (0U)
lypinator 0:bb348c97df44 3941 #define CAN_F0R2_FB0_Msk (0x1U << CAN_F0R2_FB0_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 3942 #define CAN_F0R2_FB0 CAN_F0R2_FB0_Msk /*!<Filter bit 0 */
lypinator 0:bb348c97df44 3943 #define CAN_F0R2_FB1_Pos (1U)
lypinator 0:bb348c97df44 3944 #define CAN_F0R2_FB1_Msk (0x1U << CAN_F0R2_FB1_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 3945 #define CAN_F0R2_FB1 CAN_F0R2_FB1_Msk /*!<Filter bit 1 */
lypinator 0:bb348c97df44 3946 #define CAN_F0R2_FB2_Pos (2U)
lypinator 0:bb348c97df44 3947 #define CAN_F0R2_FB2_Msk (0x1U << CAN_F0R2_FB2_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 3948 #define CAN_F0R2_FB2 CAN_F0R2_FB2_Msk /*!<Filter bit 2 */
lypinator 0:bb348c97df44 3949 #define CAN_F0R2_FB3_Pos (3U)
lypinator 0:bb348c97df44 3950 #define CAN_F0R2_FB3_Msk (0x1U << CAN_F0R2_FB3_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 3951 #define CAN_F0R2_FB3 CAN_F0R2_FB3_Msk /*!<Filter bit 3 */
lypinator 0:bb348c97df44 3952 #define CAN_F0R2_FB4_Pos (4U)
lypinator 0:bb348c97df44 3953 #define CAN_F0R2_FB4_Msk (0x1U << CAN_F0R2_FB4_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 3954 #define CAN_F0R2_FB4 CAN_F0R2_FB4_Msk /*!<Filter bit 4 */
lypinator 0:bb348c97df44 3955 #define CAN_F0R2_FB5_Pos (5U)
lypinator 0:bb348c97df44 3956 #define CAN_F0R2_FB5_Msk (0x1U << CAN_F0R2_FB5_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 3957 #define CAN_F0R2_FB5 CAN_F0R2_FB5_Msk /*!<Filter bit 5 */
lypinator 0:bb348c97df44 3958 #define CAN_F0R2_FB6_Pos (6U)
lypinator 0:bb348c97df44 3959 #define CAN_F0R2_FB6_Msk (0x1U << CAN_F0R2_FB6_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 3960 #define CAN_F0R2_FB6 CAN_F0R2_FB6_Msk /*!<Filter bit 6 */
lypinator 0:bb348c97df44 3961 #define CAN_F0R2_FB7_Pos (7U)
lypinator 0:bb348c97df44 3962 #define CAN_F0R2_FB7_Msk (0x1U << CAN_F0R2_FB7_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 3963 #define CAN_F0R2_FB7 CAN_F0R2_FB7_Msk /*!<Filter bit 7 */
lypinator 0:bb348c97df44 3964 #define CAN_F0R2_FB8_Pos (8U)
lypinator 0:bb348c97df44 3965 #define CAN_F0R2_FB8_Msk (0x1U << CAN_F0R2_FB8_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 3966 #define CAN_F0R2_FB8 CAN_F0R2_FB8_Msk /*!<Filter bit 8 */
lypinator 0:bb348c97df44 3967 #define CAN_F0R2_FB9_Pos (9U)
lypinator 0:bb348c97df44 3968 #define CAN_F0R2_FB9_Msk (0x1U << CAN_F0R2_FB9_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 3969 #define CAN_F0R2_FB9 CAN_F0R2_FB9_Msk /*!<Filter bit 9 */
lypinator 0:bb348c97df44 3970 #define CAN_F0R2_FB10_Pos (10U)
lypinator 0:bb348c97df44 3971 #define CAN_F0R2_FB10_Msk (0x1U << CAN_F0R2_FB10_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 3972 #define CAN_F0R2_FB10 CAN_F0R2_FB10_Msk /*!<Filter bit 10 */
lypinator 0:bb348c97df44 3973 #define CAN_F0R2_FB11_Pos (11U)
lypinator 0:bb348c97df44 3974 #define CAN_F0R2_FB11_Msk (0x1U << CAN_F0R2_FB11_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 3975 #define CAN_F0R2_FB11 CAN_F0R2_FB11_Msk /*!<Filter bit 11 */
lypinator 0:bb348c97df44 3976 #define CAN_F0R2_FB12_Pos (12U)
lypinator 0:bb348c97df44 3977 #define CAN_F0R2_FB12_Msk (0x1U << CAN_F0R2_FB12_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 3978 #define CAN_F0R2_FB12 CAN_F0R2_FB12_Msk /*!<Filter bit 12 */
lypinator 0:bb348c97df44 3979 #define CAN_F0R2_FB13_Pos (13U)
lypinator 0:bb348c97df44 3980 #define CAN_F0R2_FB13_Msk (0x1U << CAN_F0R2_FB13_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 3981 #define CAN_F0R2_FB13 CAN_F0R2_FB13_Msk /*!<Filter bit 13 */
lypinator 0:bb348c97df44 3982 #define CAN_F0R2_FB14_Pos (14U)
lypinator 0:bb348c97df44 3983 #define CAN_F0R2_FB14_Msk (0x1U << CAN_F0R2_FB14_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 3984 #define CAN_F0R2_FB14 CAN_F0R2_FB14_Msk /*!<Filter bit 14 */
lypinator 0:bb348c97df44 3985 #define CAN_F0R2_FB15_Pos (15U)
lypinator 0:bb348c97df44 3986 #define CAN_F0R2_FB15_Msk (0x1U << CAN_F0R2_FB15_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 3987 #define CAN_F0R2_FB15 CAN_F0R2_FB15_Msk /*!<Filter bit 15 */
lypinator 0:bb348c97df44 3988 #define CAN_F0R2_FB16_Pos (16U)
lypinator 0:bb348c97df44 3989 #define CAN_F0R2_FB16_Msk (0x1U << CAN_F0R2_FB16_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 3990 #define CAN_F0R2_FB16 CAN_F0R2_FB16_Msk /*!<Filter bit 16 */
lypinator 0:bb348c97df44 3991 #define CAN_F0R2_FB17_Pos (17U)
lypinator 0:bb348c97df44 3992 #define CAN_F0R2_FB17_Msk (0x1U << CAN_F0R2_FB17_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 3993 #define CAN_F0R2_FB17 CAN_F0R2_FB17_Msk /*!<Filter bit 17 */
lypinator 0:bb348c97df44 3994 #define CAN_F0R2_FB18_Pos (18U)
lypinator 0:bb348c97df44 3995 #define CAN_F0R2_FB18_Msk (0x1U << CAN_F0R2_FB18_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 3996 #define CAN_F0R2_FB18 CAN_F0R2_FB18_Msk /*!<Filter bit 18 */
lypinator 0:bb348c97df44 3997 #define CAN_F0R2_FB19_Pos (19U)
lypinator 0:bb348c97df44 3998 #define CAN_F0R2_FB19_Msk (0x1U << CAN_F0R2_FB19_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 3999 #define CAN_F0R2_FB19 CAN_F0R2_FB19_Msk /*!<Filter bit 19 */
lypinator 0:bb348c97df44 4000 #define CAN_F0R2_FB20_Pos (20U)
lypinator 0:bb348c97df44 4001 #define CAN_F0R2_FB20_Msk (0x1U << CAN_F0R2_FB20_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 4002 #define CAN_F0R2_FB20 CAN_F0R2_FB20_Msk /*!<Filter bit 20 */
lypinator 0:bb348c97df44 4003 #define CAN_F0R2_FB21_Pos (21U)
lypinator 0:bb348c97df44 4004 #define CAN_F0R2_FB21_Msk (0x1U << CAN_F0R2_FB21_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 4005 #define CAN_F0R2_FB21 CAN_F0R2_FB21_Msk /*!<Filter bit 21 */
lypinator 0:bb348c97df44 4006 #define CAN_F0R2_FB22_Pos (22U)
lypinator 0:bb348c97df44 4007 #define CAN_F0R2_FB22_Msk (0x1U << CAN_F0R2_FB22_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 4008 #define CAN_F0R2_FB22 CAN_F0R2_FB22_Msk /*!<Filter bit 22 */
lypinator 0:bb348c97df44 4009 #define CAN_F0R2_FB23_Pos (23U)
lypinator 0:bb348c97df44 4010 #define CAN_F0R2_FB23_Msk (0x1U << CAN_F0R2_FB23_Pos) /*!< 0x00800000 */
lypinator 0:bb348c97df44 4011 #define CAN_F0R2_FB23 CAN_F0R2_FB23_Msk /*!<Filter bit 23 */
lypinator 0:bb348c97df44 4012 #define CAN_F0R2_FB24_Pos (24U)
lypinator 0:bb348c97df44 4013 #define CAN_F0R2_FB24_Msk (0x1U << CAN_F0R2_FB24_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 4014 #define CAN_F0R2_FB24 CAN_F0R2_FB24_Msk /*!<Filter bit 24 */
lypinator 0:bb348c97df44 4015 #define CAN_F0R2_FB25_Pos (25U)
lypinator 0:bb348c97df44 4016 #define CAN_F0R2_FB25_Msk (0x1U << CAN_F0R2_FB25_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 4017 #define CAN_F0R2_FB25 CAN_F0R2_FB25_Msk /*!<Filter bit 25 */
lypinator 0:bb348c97df44 4018 #define CAN_F0R2_FB26_Pos (26U)
lypinator 0:bb348c97df44 4019 #define CAN_F0R2_FB26_Msk (0x1U << CAN_F0R2_FB26_Pos) /*!< 0x04000000 */
lypinator 0:bb348c97df44 4020 #define CAN_F0R2_FB26 CAN_F0R2_FB26_Msk /*!<Filter bit 26 */
lypinator 0:bb348c97df44 4021 #define CAN_F0R2_FB27_Pos (27U)
lypinator 0:bb348c97df44 4022 #define CAN_F0R2_FB27_Msk (0x1U << CAN_F0R2_FB27_Pos) /*!< 0x08000000 */
lypinator 0:bb348c97df44 4023 #define CAN_F0R2_FB27 CAN_F0R2_FB27_Msk /*!<Filter bit 27 */
lypinator 0:bb348c97df44 4024 #define CAN_F0R2_FB28_Pos (28U)
lypinator 0:bb348c97df44 4025 #define CAN_F0R2_FB28_Msk (0x1U << CAN_F0R2_FB28_Pos) /*!< 0x10000000 */
lypinator 0:bb348c97df44 4026 #define CAN_F0R2_FB28 CAN_F0R2_FB28_Msk /*!<Filter bit 28 */
lypinator 0:bb348c97df44 4027 #define CAN_F0R2_FB29_Pos (29U)
lypinator 0:bb348c97df44 4028 #define CAN_F0R2_FB29_Msk (0x1U << CAN_F0R2_FB29_Pos) /*!< 0x20000000 */
lypinator 0:bb348c97df44 4029 #define CAN_F0R2_FB29 CAN_F0R2_FB29_Msk /*!<Filter bit 29 */
lypinator 0:bb348c97df44 4030 #define CAN_F0R2_FB30_Pos (30U)
lypinator 0:bb348c97df44 4031 #define CAN_F0R2_FB30_Msk (0x1U << CAN_F0R2_FB30_Pos) /*!< 0x40000000 */
lypinator 0:bb348c97df44 4032 #define CAN_F0R2_FB30 CAN_F0R2_FB30_Msk /*!<Filter bit 30 */
lypinator 0:bb348c97df44 4033 #define CAN_F0R2_FB31_Pos (31U)
lypinator 0:bb348c97df44 4034 #define CAN_F0R2_FB31_Msk (0x1U << CAN_F0R2_FB31_Pos) /*!< 0x80000000 */
lypinator 0:bb348c97df44 4035 #define CAN_F0R2_FB31 CAN_F0R2_FB31_Msk /*!<Filter bit 31 */
lypinator 0:bb348c97df44 4036
lypinator 0:bb348c97df44 4037 /******************* Bit definition for CAN_F1R2 register *******************/
lypinator 0:bb348c97df44 4038 #define CAN_F1R2_FB0_Pos (0U)
lypinator 0:bb348c97df44 4039 #define CAN_F1R2_FB0_Msk (0x1U << CAN_F1R2_FB0_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 4040 #define CAN_F1R2_FB0 CAN_F1R2_FB0_Msk /*!<Filter bit 0 */
lypinator 0:bb348c97df44 4041 #define CAN_F1R2_FB1_Pos (1U)
lypinator 0:bb348c97df44 4042 #define CAN_F1R2_FB1_Msk (0x1U << CAN_F1R2_FB1_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 4043 #define CAN_F1R2_FB1 CAN_F1R2_FB1_Msk /*!<Filter bit 1 */
lypinator 0:bb348c97df44 4044 #define CAN_F1R2_FB2_Pos (2U)
lypinator 0:bb348c97df44 4045 #define CAN_F1R2_FB2_Msk (0x1U << CAN_F1R2_FB2_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 4046 #define CAN_F1R2_FB2 CAN_F1R2_FB2_Msk /*!<Filter bit 2 */
lypinator 0:bb348c97df44 4047 #define CAN_F1R2_FB3_Pos (3U)
lypinator 0:bb348c97df44 4048 #define CAN_F1R2_FB3_Msk (0x1U << CAN_F1R2_FB3_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 4049 #define CAN_F1R2_FB3 CAN_F1R2_FB3_Msk /*!<Filter bit 3 */
lypinator 0:bb348c97df44 4050 #define CAN_F1R2_FB4_Pos (4U)
lypinator 0:bb348c97df44 4051 #define CAN_F1R2_FB4_Msk (0x1U << CAN_F1R2_FB4_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 4052 #define CAN_F1R2_FB4 CAN_F1R2_FB4_Msk /*!<Filter bit 4 */
lypinator 0:bb348c97df44 4053 #define CAN_F1R2_FB5_Pos (5U)
lypinator 0:bb348c97df44 4054 #define CAN_F1R2_FB5_Msk (0x1U << CAN_F1R2_FB5_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 4055 #define CAN_F1R2_FB5 CAN_F1R2_FB5_Msk /*!<Filter bit 5 */
lypinator 0:bb348c97df44 4056 #define CAN_F1R2_FB6_Pos (6U)
lypinator 0:bb348c97df44 4057 #define CAN_F1R2_FB6_Msk (0x1U << CAN_F1R2_FB6_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 4058 #define CAN_F1R2_FB6 CAN_F1R2_FB6_Msk /*!<Filter bit 6 */
lypinator 0:bb348c97df44 4059 #define CAN_F1R2_FB7_Pos (7U)
lypinator 0:bb348c97df44 4060 #define CAN_F1R2_FB7_Msk (0x1U << CAN_F1R2_FB7_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 4061 #define CAN_F1R2_FB7 CAN_F1R2_FB7_Msk /*!<Filter bit 7 */
lypinator 0:bb348c97df44 4062 #define CAN_F1R2_FB8_Pos (8U)
lypinator 0:bb348c97df44 4063 #define CAN_F1R2_FB8_Msk (0x1U << CAN_F1R2_FB8_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 4064 #define CAN_F1R2_FB8 CAN_F1R2_FB8_Msk /*!<Filter bit 8 */
lypinator 0:bb348c97df44 4065 #define CAN_F1R2_FB9_Pos (9U)
lypinator 0:bb348c97df44 4066 #define CAN_F1R2_FB9_Msk (0x1U << CAN_F1R2_FB9_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 4067 #define CAN_F1R2_FB9 CAN_F1R2_FB9_Msk /*!<Filter bit 9 */
lypinator 0:bb348c97df44 4068 #define CAN_F1R2_FB10_Pos (10U)
lypinator 0:bb348c97df44 4069 #define CAN_F1R2_FB10_Msk (0x1U << CAN_F1R2_FB10_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 4070 #define CAN_F1R2_FB10 CAN_F1R2_FB10_Msk /*!<Filter bit 10 */
lypinator 0:bb348c97df44 4071 #define CAN_F1R2_FB11_Pos (11U)
lypinator 0:bb348c97df44 4072 #define CAN_F1R2_FB11_Msk (0x1U << CAN_F1R2_FB11_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 4073 #define CAN_F1R2_FB11 CAN_F1R2_FB11_Msk /*!<Filter bit 11 */
lypinator 0:bb348c97df44 4074 #define CAN_F1R2_FB12_Pos (12U)
lypinator 0:bb348c97df44 4075 #define CAN_F1R2_FB12_Msk (0x1U << CAN_F1R2_FB12_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 4076 #define CAN_F1R2_FB12 CAN_F1R2_FB12_Msk /*!<Filter bit 12 */
lypinator 0:bb348c97df44 4077 #define CAN_F1R2_FB13_Pos (13U)
lypinator 0:bb348c97df44 4078 #define CAN_F1R2_FB13_Msk (0x1U << CAN_F1R2_FB13_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 4079 #define CAN_F1R2_FB13 CAN_F1R2_FB13_Msk /*!<Filter bit 13 */
lypinator 0:bb348c97df44 4080 #define CAN_F1R2_FB14_Pos (14U)
lypinator 0:bb348c97df44 4081 #define CAN_F1R2_FB14_Msk (0x1U << CAN_F1R2_FB14_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 4082 #define CAN_F1R2_FB14 CAN_F1R2_FB14_Msk /*!<Filter bit 14 */
lypinator 0:bb348c97df44 4083 #define CAN_F1R2_FB15_Pos (15U)
lypinator 0:bb348c97df44 4084 #define CAN_F1R2_FB15_Msk (0x1U << CAN_F1R2_FB15_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 4085 #define CAN_F1R2_FB15 CAN_F1R2_FB15_Msk /*!<Filter bit 15 */
lypinator 0:bb348c97df44 4086 #define CAN_F1R2_FB16_Pos (16U)
lypinator 0:bb348c97df44 4087 #define CAN_F1R2_FB16_Msk (0x1U << CAN_F1R2_FB16_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 4088 #define CAN_F1R2_FB16 CAN_F1R2_FB16_Msk /*!<Filter bit 16 */
lypinator 0:bb348c97df44 4089 #define CAN_F1R2_FB17_Pos (17U)
lypinator 0:bb348c97df44 4090 #define CAN_F1R2_FB17_Msk (0x1U << CAN_F1R2_FB17_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 4091 #define CAN_F1R2_FB17 CAN_F1R2_FB17_Msk /*!<Filter bit 17 */
lypinator 0:bb348c97df44 4092 #define CAN_F1R2_FB18_Pos (18U)
lypinator 0:bb348c97df44 4093 #define CAN_F1R2_FB18_Msk (0x1U << CAN_F1R2_FB18_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 4094 #define CAN_F1R2_FB18 CAN_F1R2_FB18_Msk /*!<Filter bit 18 */
lypinator 0:bb348c97df44 4095 #define CAN_F1R2_FB19_Pos (19U)
lypinator 0:bb348c97df44 4096 #define CAN_F1R2_FB19_Msk (0x1U << CAN_F1R2_FB19_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 4097 #define CAN_F1R2_FB19 CAN_F1R2_FB19_Msk /*!<Filter bit 19 */
lypinator 0:bb348c97df44 4098 #define CAN_F1R2_FB20_Pos (20U)
lypinator 0:bb348c97df44 4099 #define CAN_F1R2_FB20_Msk (0x1U << CAN_F1R2_FB20_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 4100 #define CAN_F1R2_FB20 CAN_F1R2_FB20_Msk /*!<Filter bit 20 */
lypinator 0:bb348c97df44 4101 #define CAN_F1R2_FB21_Pos (21U)
lypinator 0:bb348c97df44 4102 #define CAN_F1R2_FB21_Msk (0x1U << CAN_F1R2_FB21_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 4103 #define CAN_F1R2_FB21 CAN_F1R2_FB21_Msk /*!<Filter bit 21 */
lypinator 0:bb348c97df44 4104 #define CAN_F1R2_FB22_Pos (22U)
lypinator 0:bb348c97df44 4105 #define CAN_F1R2_FB22_Msk (0x1U << CAN_F1R2_FB22_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 4106 #define CAN_F1R2_FB22 CAN_F1R2_FB22_Msk /*!<Filter bit 22 */
lypinator 0:bb348c97df44 4107 #define CAN_F1R2_FB23_Pos (23U)
lypinator 0:bb348c97df44 4108 #define CAN_F1R2_FB23_Msk (0x1U << CAN_F1R2_FB23_Pos) /*!< 0x00800000 */
lypinator 0:bb348c97df44 4109 #define CAN_F1R2_FB23 CAN_F1R2_FB23_Msk /*!<Filter bit 23 */
lypinator 0:bb348c97df44 4110 #define CAN_F1R2_FB24_Pos (24U)
lypinator 0:bb348c97df44 4111 #define CAN_F1R2_FB24_Msk (0x1U << CAN_F1R2_FB24_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 4112 #define CAN_F1R2_FB24 CAN_F1R2_FB24_Msk /*!<Filter bit 24 */
lypinator 0:bb348c97df44 4113 #define CAN_F1R2_FB25_Pos (25U)
lypinator 0:bb348c97df44 4114 #define CAN_F1R2_FB25_Msk (0x1U << CAN_F1R2_FB25_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 4115 #define CAN_F1R2_FB25 CAN_F1R2_FB25_Msk /*!<Filter bit 25 */
lypinator 0:bb348c97df44 4116 #define CAN_F1R2_FB26_Pos (26U)
lypinator 0:bb348c97df44 4117 #define CAN_F1R2_FB26_Msk (0x1U << CAN_F1R2_FB26_Pos) /*!< 0x04000000 */
lypinator 0:bb348c97df44 4118 #define CAN_F1R2_FB26 CAN_F1R2_FB26_Msk /*!<Filter bit 26 */
lypinator 0:bb348c97df44 4119 #define CAN_F1R2_FB27_Pos (27U)
lypinator 0:bb348c97df44 4120 #define CAN_F1R2_FB27_Msk (0x1U << CAN_F1R2_FB27_Pos) /*!< 0x08000000 */
lypinator 0:bb348c97df44 4121 #define CAN_F1R2_FB27 CAN_F1R2_FB27_Msk /*!<Filter bit 27 */
lypinator 0:bb348c97df44 4122 #define CAN_F1R2_FB28_Pos (28U)
lypinator 0:bb348c97df44 4123 #define CAN_F1R2_FB28_Msk (0x1U << CAN_F1R2_FB28_Pos) /*!< 0x10000000 */
lypinator 0:bb348c97df44 4124 #define CAN_F1R2_FB28 CAN_F1R2_FB28_Msk /*!<Filter bit 28 */
lypinator 0:bb348c97df44 4125 #define CAN_F1R2_FB29_Pos (29U)
lypinator 0:bb348c97df44 4126 #define CAN_F1R2_FB29_Msk (0x1U << CAN_F1R2_FB29_Pos) /*!< 0x20000000 */
lypinator 0:bb348c97df44 4127 #define CAN_F1R2_FB29 CAN_F1R2_FB29_Msk /*!<Filter bit 29 */
lypinator 0:bb348c97df44 4128 #define CAN_F1R2_FB30_Pos (30U)
lypinator 0:bb348c97df44 4129 #define CAN_F1R2_FB30_Msk (0x1U << CAN_F1R2_FB30_Pos) /*!< 0x40000000 */
lypinator 0:bb348c97df44 4130 #define CAN_F1R2_FB30 CAN_F1R2_FB30_Msk /*!<Filter bit 30 */
lypinator 0:bb348c97df44 4131 #define CAN_F1R2_FB31_Pos (31U)
lypinator 0:bb348c97df44 4132 #define CAN_F1R2_FB31_Msk (0x1U << CAN_F1R2_FB31_Pos) /*!< 0x80000000 */
lypinator 0:bb348c97df44 4133 #define CAN_F1R2_FB31 CAN_F1R2_FB31_Msk /*!<Filter bit 31 */
lypinator 0:bb348c97df44 4134
lypinator 0:bb348c97df44 4135 /******************* Bit definition for CAN_F2R2 register *******************/
lypinator 0:bb348c97df44 4136 #define CAN_F2R2_FB0_Pos (0U)
lypinator 0:bb348c97df44 4137 #define CAN_F2R2_FB0_Msk (0x1U << CAN_F2R2_FB0_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 4138 #define CAN_F2R2_FB0 CAN_F2R2_FB0_Msk /*!<Filter bit 0 */
lypinator 0:bb348c97df44 4139 #define CAN_F2R2_FB1_Pos (1U)
lypinator 0:bb348c97df44 4140 #define CAN_F2R2_FB1_Msk (0x1U << CAN_F2R2_FB1_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 4141 #define CAN_F2R2_FB1 CAN_F2R2_FB1_Msk /*!<Filter bit 1 */
lypinator 0:bb348c97df44 4142 #define CAN_F2R2_FB2_Pos (2U)
lypinator 0:bb348c97df44 4143 #define CAN_F2R2_FB2_Msk (0x1U << CAN_F2R2_FB2_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 4144 #define CAN_F2R2_FB2 CAN_F2R2_FB2_Msk /*!<Filter bit 2 */
lypinator 0:bb348c97df44 4145 #define CAN_F2R2_FB3_Pos (3U)
lypinator 0:bb348c97df44 4146 #define CAN_F2R2_FB3_Msk (0x1U << CAN_F2R2_FB3_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 4147 #define CAN_F2R2_FB3 CAN_F2R2_FB3_Msk /*!<Filter bit 3 */
lypinator 0:bb348c97df44 4148 #define CAN_F2R2_FB4_Pos (4U)
lypinator 0:bb348c97df44 4149 #define CAN_F2R2_FB4_Msk (0x1U << CAN_F2R2_FB4_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 4150 #define CAN_F2R2_FB4 CAN_F2R2_FB4_Msk /*!<Filter bit 4 */
lypinator 0:bb348c97df44 4151 #define CAN_F2R2_FB5_Pos (5U)
lypinator 0:bb348c97df44 4152 #define CAN_F2R2_FB5_Msk (0x1U << CAN_F2R2_FB5_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 4153 #define CAN_F2R2_FB5 CAN_F2R2_FB5_Msk /*!<Filter bit 5 */
lypinator 0:bb348c97df44 4154 #define CAN_F2R2_FB6_Pos (6U)
lypinator 0:bb348c97df44 4155 #define CAN_F2R2_FB6_Msk (0x1U << CAN_F2R2_FB6_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 4156 #define CAN_F2R2_FB6 CAN_F2R2_FB6_Msk /*!<Filter bit 6 */
lypinator 0:bb348c97df44 4157 #define CAN_F2R2_FB7_Pos (7U)
lypinator 0:bb348c97df44 4158 #define CAN_F2R2_FB7_Msk (0x1U << CAN_F2R2_FB7_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 4159 #define CAN_F2R2_FB7 CAN_F2R2_FB7_Msk /*!<Filter bit 7 */
lypinator 0:bb348c97df44 4160 #define CAN_F2R2_FB8_Pos (8U)
lypinator 0:bb348c97df44 4161 #define CAN_F2R2_FB8_Msk (0x1U << CAN_F2R2_FB8_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 4162 #define CAN_F2R2_FB8 CAN_F2R2_FB8_Msk /*!<Filter bit 8 */
lypinator 0:bb348c97df44 4163 #define CAN_F2R2_FB9_Pos (9U)
lypinator 0:bb348c97df44 4164 #define CAN_F2R2_FB9_Msk (0x1U << CAN_F2R2_FB9_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 4165 #define CAN_F2R2_FB9 CAN_F2R2_FB9_Msk /*!<Filter bit 9 */
lypinator 0:bb348c97df44 4166 #define CAN_F2R2_FB10_Pos (10U)
lypinator 0:bb348c97df44 4167 #define CAN_F2R2_FB10_Msk (0x1U << CAN_F2R2_FB10_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 4168 #define CAN_F2R2_FB10 CAN_F2R2_FB10_Msk /*!<Filter bit 10 */
lypinator 0:bb348c97df44 4169 #define CAN_F2R2_FB11_Pos (11U)
lypinator 0:bb348c97df44 4170 #define CAN_F2R2_FB11_Msk (0x1U << CAN_F2R2_FB11_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 4171 #define CAN_F2R2_FB11 CAN_F2R2_FB11_Msk /*!<Filter bit 11 */
lypinator 0:bb348c97df44 4172 #define CAN_F2R2_FB12_Pos (12U)
lypinator 0:bb348c97df44 4173 #define CAN_F2R2_FB12_Msk (0x1U << CAN_F2R2_FB12_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 4174 #define CAN_F2R2_FB12 CAN_F2R2_FB12_Msk /*!<Filter bit 12 */
lypinator 0:bb348c97df44 4175 #define CAN_F2R2_FB13_Pos (13U)
lypinator 0:bb348c97df44 4176 #define CAN_F2R2_FB13_Msk (0x1U << CAN_F2R2_FB13_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 4177 #define CAN_F2R2_FB13 CAN_F2R2_FB13_Msk /*!<Filter bit 13 */
lypinator 0:bb348c97df44 4178 #define CAN_F2R2_FB14_Pos (14U)
lypinator 0:bb348c97df44 4179 #define CAN_F2R2_FB14_Msk (0x1U << CAN_F2R2_FB14_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 4180 #define CAN_F2R2_FB14 CAN_F2R2_FB14_Msk /*!<Filter bit 14 */
lypinator 0:bb348c97df44 4181 #define CAN_F2R2_FB15_Pos (15U)
lypinator 0:bb348c97df44 4182 #define CAN_F2R2_FB15_Msk (0x1U << CAN_F2R2_FB15_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 4183 #define CAN_F2R2_FB15 CAN_F2R2_FB15_Msk /*!<Filter bit 15 */
lypinator 0:bb348c97df44 4184 #define CAN_F2R2_FB16_Pos (16U)
lypinator 0:bb348c97df44 4185 #define CAN_F2R2_FB16_Msk (0x1U << CAN_F2R2_FB16_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 4186 #define CAN_F2R2_FB16 CAN_F2R2_FB16_Msk /*!<Filter bit 16 */
lypinator 0:bb348c97df44 4187 #define CAN_F2R2_FB17_Pos (17U)
lypinator 0:bb348c97df44 4188 #define CAN_F2R2_FB17_Msk (0x1U << CAN_F2R2_FB17_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 4189 #define CAN_F2R2_FB17 CAN_F2R2_FB17_Msk /*!<Filter bit 17 */
lypinator 0:bb348c97df44 4190 #define CAN_F2R2_FB18_Pos (18U)
lypinator 0:bb348c97df44 4191 #define CAN_F2R2_FB18_Msk (0x1U << CAN_F2R2_FB18_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 4192 #define CAN_F2R2_FB18 CAN_F2R2_FB18_Msk /*!<Filter bit 18 */
lypinator 0:bb348c97df44 4193 #define CAN_F2R2_FB19_Pos (19U)
lypinator 0:bb348c97df44 4194 #define CAN_F2R2_FB19_Msk (0x1U << CAN_F2R2_FB19_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 4195 #define CAN_F2R2_FB19 CAN_F2R2_FB19_Msk /*!<Filter bit 19 */
lypinator 0:bb348c97df44 4196 #define CAN_F2R2_FB20_Pos (20U)
lypinator 0:bb348c97df44 4197 #define CAN_F2R2_FB20_Msk (0x1U << CAN_F2R2_FB20_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 4198 #define CAN_F2R2_FB20 CAN_F2R2_FB20_Msk /*!<Filter bit 20 */
lypinator 0:bb348c97df44 4199 #define CAN_F2R2_FB21_Pos (21U)
lypinator 0:bb348c97df44 4200 #define CAN_F2R2_FB21_Msk (0x1U << CAN_F2R2_FB21_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 4201 #define CAN_F2R2_FB21 CAN_F2R2_FB21_Msk /*!<Filter bit 21 */
lypinator 0:bb348c97df44 4202 #define CAN_F2R2_FB22_Pos (22U)
lypinator 0:bb348c97df44 4203 #define CAN_F2R2_FB22_Msk (0x1U << CAN_F2R2_FB22_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 4204 #define CAN_F2R2_FB22 CAN_F2R2_FB22_Msk /*!<Filter bit 22 */
lypinator 0:bb348c97df44 4205 #define CAN_F2R2_FB23_Pos (23U)
lypinator 0:bb348c97df44 4206 #define CAN_F2R2_FB23_Msk (0x1U << CAN_F2R2_FB23_Pos) /*!< 0x00800000 */
lypinator 0:bb348c97df44 4207 #define CAN_F2R2_FB23 CAN_F2R2_FB23_Msk /*!<Filter bit 23 */
lypinator 0:bb348c97df44 4208 #define CAN_F2R2_FB24_Pos (24U)
lypinator 0:bb348c97df44 4209 #define CAN_F2R2_FB24_Msk (0x1U << CAN_F2R2_FB24_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 4210 #define CAN_F2R2_FB24 CAN_F2R2_FB24_Msk /*!<Filter bit 24 */
lypinator 0:bb348c97df44 4211 #define CAN_F2R2_FB25_Pos (25U)
lypinator 0:bb348c97df44 4212 #define CAN_F2R2_FB25_Msk (0x1U << CAN_F2R2_FB25_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 4213 #define CAN_F2R2_FB25 CAN_F2R2_FB25_Msk /*!<Filter bit 25 */
lypinator 0:bb348c97df44 4214 #define CAN_F2R2_FB26_Pos (26U)
lypinator 0:bb348c97df44 4215 #define CAN_F2R2_FB26_Msk (0x1U << CAN_F2R2_FB26_Pos) /*!< 0x04000000 */
lypinator 0:bb348c97df44 4216 #define CAN_F2R2_FB26 CAN_F2R2_FB26_Msk /*!<Filter bit 26 */
lypinator 0:bb348c97df44 4217 #define CAN_F2R2_FB27_Pos (27U)
lypinator 0:bb348c97df44 4218 #define CAN_F2R2_FB27_Msk (0x1U << CAN_F2R2_FB27_Pos) /*!< 0x08000000 */
lypinator 0:bb348c97df44 4219 #define CAN_F2R2_FB27 CAN_F2R2_FB27_Msk /*!<Filter bit 27 */
lypinator 0:bb348c97df44 4220 #define CAN_F2R2_FB28_Pos (28U)
lypinator 0:bb348c97df44 4221 #define CAN_F2R2_FB28_Msk (0x1U << CAN_F2R2_FB28_Pos) /*!< 0x10000000 */
lypinator 0:bb348c97df44 4222 #define CAN_F2R2_FB28 CAN_F2R2_FB28_Msk /*!<Filter bit 28 */
lypinator 0:bb348c97df44 4223 #define CAN_F2R2_FB29_Pos (29U)
lypinator 0:bb348c97df44 4224 #define CAN_F2R2_FB29_Msk (0x1U << CAN_F2R2_FB29_Pos) /*!< 0x20000000 */
lypinator 0:bb348c97df44 4225 #define CAN_F2R2_FB29 CAN_F2R2_FB29_Msk /*!<Filter bit 29 */
lypinator 0:bb348c97df44 4226 #define CAN_F2R2_FB30_Pos (30U)
lypinator 0:bb348c97df44 4227 #define CAN_F2R2_FB30_Msk (0x1U << CAN_F2R2_FB30_Pos) /*!< 0x40000000 */
lypinator 0:bb348c97df44 4228 #define CAN_F2R2_FB30 CAN_F2R2_FB30_Msk /*!<Filter bit 30 */
lypinator 0:bb348c97df44 4229 #define CAN_F2R2_FB31_Pos (31U)
lypinator 0:bb348c97df44 4230 #define CAN_F2R2_FB31_Msk (0x1U << CAN_F2R2_FB31_Pos) /*!< 0x80000000 */
lypinator 0:bb348c97df44 4231 #define CAN_F2R2_FB31 CAN_F2R2_FB31_Msk /*!<Filter bit 31 */
lypinator 0:bb348c97df44 4232
lypinator 0:bb348c97df44 4233 /******************* Bit definition for CAN_F3R2 register *******************/
lypinator 0:bb348c97df44 4234 #define CAN_F3R2_FB0_Pos (0U)
lypinator 0:bb348c97df44 4235 #define CAN_F3R2_FB0_Msk (0x1U << CAN_F3R2_FB0_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 4236 #define CAN_F3R2_FB0 CAN_F3R2_FB0_Msk /*!<Filter bit 0 */
lypinator 0:bb348c97df44 4237 #define CAN_F3R2_FB1_Pos (1U)
lypinator 0:bb348c97df44 4238 #define CAN_F3R2_FB1_Msk (0x1U << CAN_F3R2_FB1_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 4239 #define CAN_F3R2_FB1 CAN_F3R2_FB1_Msk /*!<Filter bit 1 */
lypinator 0:bb348c97df44 4240 #define CAN_F3R2_FB2_Pos (2U)
lypinator 0:bb348c97df44 4241 #define CAN_F3R2_FB2_Msk (0x1U << CAN_F3R2_FB2_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 4242 #define CAN_F3R2_FB2 CAN_F3R2_FB2_Msk /*!<Filter bit 2 */
lypinator 0:bb348c97df44 4243 #define CAN_F3R2_FB3_Pos (3U)
lypinator 0:bb348c97df44 4244 #define CAN_F3R2_FB3_Msk (0x1U << CAN_F3R2_FB3_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 4245 #define CAN_F3R2_FB3 CAN_F3R2_FB3_Msk /*!<Filter bit 3 */
lypinator 0:bb348c97df44 4246 #define CAN_F3R2_FB4_Pos (4U)
lypinator 0:bb348c97df44 4247 #define CAN_F3R2_FB4_Msk (0x1U << CAN_F3R2_FB4_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 4248 #define CAN_F3R2_FB4 CAN_F3R2_FB4_Msk /*!<Filter bit 4 */
lypinator 0:bb348c97df44 4249 #define CAN_F3R2_FB5_Pos (5U)
lypinator 0:bb348c97df44 4250 #define CAN_F3R2_FB5_Msk (0x1U << CAN_F3R2_FB5_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 4251 #define CAN_F3R2_FB5 CAN_F3R2_FB5_Msk /*!<Filter bit 5 */
lypinator 0:bb348c97df44 4252 #define CAN_F3R2_FB6_Pos (6U)
lypinator 0:bb348c97df44 4253 #define CAN_F3R2_FB6_Msk (0x1U << CAN_F3R2_FB6_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 4254 #define CAN_F3R2_FB6 CAN_F3R2_FB6_Msk /*!<Filter bit 6 */
lypinator 0:bb348c97df44 4255 #define CAN_F3R2_FB7_Pos (7U)
lypinator 0:bb348c97df44 4256 #define CAN_F3R2_FB7_Msk (0x1U << CAN_F3R2_FB7_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 4257 #define CAN_F3R2_FB7 CAN_F3R2_FB7_Msk /*!<Filter bit 7 */
lypinator 0:bb348c97df44 4258 #define CAN_F3R2_FB8_Pos (8U)
lypinator 0:bb348c97df44 4259 #define CAN_F3R2_FB8_Msk (0x1U << CAN_F3R2_FB8_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 4260 #define CAN_F3R2_FB8 CAN_F3R2_FB8_Msk /*!<Filter bit 8 */
lypinator 0:bb348c97df44 4261 #define CAN_F3R2_FB9_Pos (9U)
lypinator 0:bb348c97df44 4262 #define CAN_F3R2_FB9_Msk (0x1U << CAN_F3R2_FB9_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 4263 #define CAN_F3R2_FB9 CAN_F3R2_FB9_Msk /*!<Filter bit 9 */
lypinator 0:bb348c97df44 4264 #define CAN_F3R2_FB10_Pos (10U)
lypinator 0:bb348c97df44 4265 #define CAN_F3R2_FB10_Msk (0x1U << CAN_F3R2_FB10_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 4266 #define CAN_F3R2_FB10 CAN_F3R2_FB10_Msk /*!<Filter bit 10 */
lypinator 0:bb348c97df44 4267 #define CAN_F3R2_FB11_Pos (11U)
lypinator 0:bb348c97df44 4268 #define CAN_F3R2_FB11_Msk (0x1U << CAN_F3R2_FB11_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 4269 #define CAN_F3R2_FB11 CAN_F3R2_FB11_Msk /*!<Filter bit 11 */
lypinator 0:bb348c97df44 4270 #define CAN_F3R2_FB12_Pos (12U)
lypinator 0:bb348c97df44 4271 #define CAN_F3R2_FB12_Msk (0x1U << CAN_F3R2_FB12_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 4272 #define CAN_F3R2_FB12 CAN_F3R2_FB12_Msk /*!<Filter bit 12 */
lypinator 0:bb348c97df44 4273 #define CAN_F3R2_FB13_Pos (13U)
lypinator 0:bb348c97df44 4274 #define CAN_F3R2_FB13_Msk (0x1U << CAN_F3R2_FB13_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 4275 #define CAN_F3R2_FB13 CAN_F3R2_FB13_Msk /*!<Filter bit 13 */
lypinator 0:bb348c97df44 4276 #define CAN_F3R2_FB14_Pos (14U)
lypinator 0:bb348c97df44 4277 #define CAN_F3R2_FB14_Msk (0x1U << CAN_F3R2_FB14_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 4278 #define CAN_F3R2_FB14 CAN_F3R2_FB14_Msk /*!<Filter bit 14 */
lypinator 0:bb348c97df44 4279 #define CAN_F3R2_FB15_Pos (15U)
lypinator 0:bb348c97df44 4280 #define CAN_F3R2_FB15_Msk (0x1U << CAN_F3R2_FB15_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 4281 #define CAN_F3R2_FB15 CAN_F3R2_FB15_Msk /*!<Filter bit 15 */
lypinator 0:bb348c97df44 4282 #define CAN_F3R2_FB16_Pos (16U)
lypinator 0:bb348c97df44 4283 #define CAN_F3R2_FB16_Msk (0x1U << CAN_F3R2_FB16_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 4284 #define CAN_F3R2_FB16 CAN_F3R2_FB16_Msk /*!<Filter bit 16 */
lypinator 0:bb348c97df44 4285 #define CAN_F3R2_FB17_Pos (17U)
lypinator 0:bb348c97df44 4286 #define CAN_F3R2_FB17_Msk (0x1U << CAN_F3R2_FB17_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 4287 #define CAN_F3R2_FB17 CAN_F3R2_FB17_Msk /*!<Filter bit 17 */
lypinator 0:bb348c97df44 4288 #define CAN_F3R2_FB18_Pos (18U)
lypinator 0:bb348c97df44 4289 #define CAN_F3R2_FB18_Msk (0x1U << CAN_F3R2_FB18_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 4290 #define CAN_F3R2_FB18 CAN_F3R2_FB18_Msk /*!<Filter bit 18 */
lypinator 0:bb348c97df44 4291 #define CAN_F3R2_FB19_Pos (19U)
lypinator 0:bb348c97df44 4292 #define CAN_F3R2_FB19_Msk (0x1U << CAN_F3R2_FB19_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 4293 #define CAN_F3R2_FB19 CAN_F3R2_FB19_Msk /*!<Filter bit 19 */
lypinator 0:bb348c97df44 4294 #define CAN_F3R2_FB20_Pos (20U)
lypinator 0:bb348c97df44 4295 #define CAN_F3R2_FB20_Msk (0x1U << CAN_F3R2_FB20_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 4296 #define CAN_F3R2_FB20 CAN_F3R2_FB20_Msk /*!<Filter bit 20 */
lypinator 0:bb348c97df44 4297 #define CAN_F3R2_FB21_Pos (21U)
lypinator 0:bb348c97df44 4298 #define CAN_F3R2_FB21_Msk (0x1U << CAN_F3R2_FB21_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 4299 #define CAN_F3R2_FB21 CAN_F3R2_FB21_Msk /*!<Filter bit 21 */
lypinator 0:bb348c97df44 4300 #define CAN_F3R2_FB22_Pos (22U)
lypinator 0:bb348c97df44 4301 #define CAN_F3R2_FB22_Msk (0x1U << CAN_F3R2_FB22_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 4302 #define CAN_F3R2_FB22 CAN_F3R2_FB22_Msk /*!<Filter bit 22 */
lypinator 0:bb348c97df44 4303 #define CAN_F3R2_FB23_Pos (23U)
lypinator 0:bb348c97df44 4304 #define CAN_F3R2_FB23_Msk (0x1U << CAN_F3R2_FB23_Pos) /*!< 0x00800000 */
lypinator 0:bb348c97df44 4305 #define CAN_F3R2_FB23 CAN_F3R2_FB23_Msk /*!<Filter bit 23 */
lypinator 0:bb348c97df44 4306 #define CAN_F3R2_FB24_Pos (24U)
lypinator 0:bb348c97df44 4307 #define CAN_F3R2_FB24_Msk (0x1U << CAN_F3R2_FB24_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 4308 #define CAN_F3R2_FB24 CAN_F3R2_FB24_Msk /*!<Filter bit 24 */
lypinator 0:bb348c97df44 4309 #define CAN_F3R2_FB25_Pos (25U)
lypinator 0:bb348c97df44 4310 #define CAN_F3R2_FB25_Msk (0x1U << CAN_F3R2_FB25_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 4311 #define CAN_F3R2_FB25 CAN_F3R2_FB25_Msk /*!<Filter bit 25 */
lypinator 0:bb348c97df44 4312 #define CAN_F3R2_FB26_Pos (26U)
lypinator 0:bb348c97df44 4313 #define CAN_F3R2_FB26_Msk (0x1U << CAN_F3R2_FB26_Pos) /*!< 0x04000000 */
lypinator 0:bb348c97df44 4314 #define CAN_F3R2_FB26 CAN_F3R2_FB26_Msk /*!<Filter bit 26 */
lypinator 0:bb348c97df44 4315 #define CAN_F3R2_FB27_Pos (27U)
lypinator 0:bb348c97df44 4316 #define CAN_F3R2_FB27_Msk (0x1U << CAN_F3R2_FB27_Pos) /*!< 0x08000000 */
lypinator 0:bb348c97df44 4317 #define CAN_F3R2_FB27 CAN_F3R2_FB27_Msk /*!<Filter bit 27 */
lypinator 0:bb348c97df44 4318 #define CAN_F3R2_FB28_Pos (28U)
lypinator 0:bb348c97df44 4319 #define CAN_F3R2_FB28_Msk (0x1U << CAN_F3R2_FB28_Pos) /*!< 0x10000000 */
lypinator 0:bb348c97df44 4320 #define CAN_F3R2_FB28 CAN_F3R2_FB28_Msk /*!<Filter bit 28 */
lypinator 0:bb348c97df44 4321 #define CAN_F3R2_FB29_Pos (29U)
lypinator 0:bb348c97df44 4322 #define CAN_F3R2_FB29_Msk (0x1U << CAN_F3R2_FB29_Pos) /*!< 0x20000000 */
lypinator 0:bb348c97df44 4323 #define CAN_F3R2_FB29 CAN_F3R2_FB29_Msk /*!<Filter bit 29 */
lypinator 0:bb348c97df44 4324 #define CAN_F3R2_FB30_Pos (30U)
lypinator 0:bb348c97df44 4325 #define CAN_F3R2_FB30_Msk (0x1U << CAN_F3R2_FB30_Pos) /*!< 0x40000000 */
lypinator 0:bb348c97df44 4326 #define CAN_F3R2_FB30 CAN_F3R2_FB30_Msk /*!<Filter bit 30 */
lypinator 0:bb348c97df44 4327 #define CAN_F3R2_FB31_Pos (31U)
lypinator 0:bb348c97df44 4328 #define CAN_F3R2_FB31_Msk (0x1U << CAN_F3R2_FB31_Pos) /*!< 0x80000000 */
lypinator 0:bb348c97df44 4329 #define CAN_F3R2_FB31 CAN_F3R2_FB31_Msk /*!<Filter bit 31 */
lypinator 0:bb348c97df44 4330
lypinator 0:bb348c97df44 4331 /******************* Bit definition for CAN_F4R2 register *******************/
lypinator 0:bb348c97df44 4332 #define CAN_F4R2_FB0_Pos (0U)
lypinator 0:bb348c97df44 4333 #define CAN_F4R2_FB0_Msk (0x1U << CAN_F4R2_FB0_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 4334 #define CAN_F4R2_FB0 CAN_F4R2_FB0_Msk /*!<Filter bit 0 */
lypinator 0:bb348c97df44 4335 #define CAN_F4R2_FB1_Pos (1U)
lypinator 0:bb348c97df44 4336 #define CAN_F4R2_FB1_Msk (0x1U << CAN_F4R2_FB1_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 4337 #define CAN_F4R2_FB1 CAN_F4R2_FB1_Msk /*!<Filter bit 1 */
lypinator 0:bb348c97df44 4338 #define CAN_F4R2_FB2_Pos (2U)
lypinator 0:bb348c97df44 4339 #define CAN_F4R2_FB2_Msk (0x1U << CAN_F4R2_FB2_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 4340 #define CAN_F4R2_FB2 CAN_F4R2_FB2_Msk /*!<Filter bit 2 */
lypinator 0:bb348c97df44 4341 #define CAN_F4R2_FB3_Pos (3U)
lypinator 0:bb348c97df44 4342 #define CAN_F4R2_FB3_Msk (0x1U << CAN_F4R2_FB3_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 4343 #define CAN_F4R2_FB3 CAN_F4R2_FB3_Msk /*!<Filter bit 3 */
lypinator 0:bb348c97df44 4344 #define CAN_F4R2_FB4_Pos (4U)
lypinator 0:bb348c97df44 4345 #define CAN_F4R2_FB4_Msk (0x1U << CAN_F4R2_FB4_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 4346 #define CAN_F4R2_FB4 CAN_F4R2_FB4_Msk /*!<Filter bit 4 */
lypinator 0:bb348c97df44 4347 #define CAN_F4R2_FB5_Pos (5U)
lypinator 0:bb348c97df44 4348 #define CAN_F4R2_FB5_Msk (0x1U << CAN_F4R2_FB5_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 4349 #define CAN_F4R2_FB5 CAN_F4R2_FB5_Msk /*!<Filter bit 5 */
lypinator 0:bb348c97df44 4350 #define CAN_F4R2_FB6_Pos (6U)
lypinator 0:bb348c97df44 4351 #define CAN_F4R2_FB6_Msk (0x1U << CAN_F4R2_FB6_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 4352 #define CAN_F4R2_FB6 CAN_F4R2_FB6_Msk /*!<Filter bit 6 */
lypinator 0:bb348c97df44 4353 #define CAN_F4R2_FB7_Pos (7U)
lypinator 0:bb348c97df44 4354 #define CAN_F4R2_FB7_Msk (0x1U << CAN_F4R2_FB7_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 4355 #define CAN_F4R2_FB7 CAN_F4R2_FB7_Msk /*!<Filter bit 7 */
lypinator 0:bb348c97df44 4356 #define CAN_F4R2_FB8_Pos (8U)
lypinator 0:bb348c97df44 4357 #define CAN_F4R2_FB8_Msk (0x1U << CAN_F4R2_FB8_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 4358 #define CAN_F4R2_FB8 CAN_F4R2_FB8_Msk /*!<Filter bit 8 */
lypinator 0:bb348c97df44 4359 #define CAN_F4R2_FB9_Pos (9U)
lypinator 0:bb348c97df44 4360 #define CAN_F4R2_FB9_Msk (0x1U << CAN_F4R2_FB9_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 4361 #define CAN_F4R2_FB9 CAN_F4R2_FB9_Msk /*!<Filter bit 9 */
lypinator 0:bb348c97df44 4362 #define CAN_F4R2_FB10_Pos (10U)
lypinator 0:bb348c97df44 4363 #define CAN_F4R2_FB10_Msk (0x1U << CAN_F4R2_FB10_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 4364 #define CAN_F4R2_FB10 CAN_F4R2_FB10_Msk /*!<Filter bit 10 */
lypinator 0:bb348c97df44 4365 #define CAN_F4R2_FB11_Pos (11U)
lypinator 0:bb348c97df44 4366 #define CAN_F4R2_FB11_Msk (0x1U << CAN_F4R2_FB11_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 4367 #define CAN_F4R2_FB11 CAN_F4R2_FB11_Msk /*!<Filter bit 11 */
lypinator 0:bb348c97df44 4368 #define CAN_F4R2_FB12_Pos (12U)
lypinator 0:bb348c97df44 4369 #define CAN_F4R2_FB12_Msk (0x1U << CAN_F4R2_FB12_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 4370 #define CAN_F4R2_FB12 CAN_F4R2_FB12_Msk /*!<Filter bit 12 */
lypinator 0:bb348c97df44 4371 #define CAN_F4R2_FB13_Pos (13U)
lypinator 0:bb348c97df44 4372 #define CAN_F4R2_FB13_Msk (0x1U << CAN_F4R2_FB13_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 4373 #define CAN_F4R2_FB13 CAN_F4R2_FB13_Msk /*!<Filter bit 13 */
lypinator 0:bb348c97df44 4374 #define CAN_F4R2_FB14_Pos (14U)
lypinator 0:bb348c97df44 4375 #define CAN_F4R2_FB14_Msk (0x1U << CAN_F4R2_FB14_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 4376 #define CAN_F4R2_FB14 CAN_F4R2_FB14_Msk /*!<Filter bit 14 */
lypinator 0:bb348c97df44 4377 #define CAN_F4R2_FB15_Pos (15U)
lypinator 0:bb348c97df44 4378 #define CAN_F4R2_FB15_Msk (0x1U << CAN_F4R2_FB15_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 4379 #define CAN_F4R2_FB15 CAN_F4R2_FB15_Msk /*!<Filter bit 15 */
lypinator 0:bb348c97df44 4380 #define CAN_F4R2_FB16_Pos (16U)
lypinator 0:bb348c97df44 4381 #define CAN_F4R2_FB16_Msk (0x1U << CAN_F4R2_FB16_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 4382 #define CAN_F4R2_FB16 CAN_F4R2_FB16_Msk /*!<Filter bit 16 */
lypinator 0:bb348c97df44 4383 #define CAN_F4R2_FB17_Pos (17U)
lypinator 0:bb348c97df44 4384 #define CAN_F4R2_FB17_Msk (0x1U << CAN_F4R2_FB17_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 4385 #define CAN_F4R2_FB17 CAN_F4R2_FB17_Msk /*!<Filter bit 17 */
lypinator 0:bb348c97df44 4386 #define CAN_F4R2_FB18_Pos (18U)
lypinator 0:bb348c97df44 4387 #define CAN_F4R2_FB18_Msk (0x1U << CAN_F4R2_FB18_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 4388 #define CAN_F4R2_FB18 CAN_F4R2_FB18_Msk /*!<Filter bit 18 */
lypinator 0:bb348c97df44 4389 #define CAN_F4R2_FB19_Pos (19U)
lypinator 0:bb348c97df44 4390 #define CAN_F4R2_FB19_Msk (0x1U << CAN_F4R2_FB19_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 4391 #define CAN_F4R2_FB19 CAN_F4R2_FB19_Msk /*!<Filter bit 19 */
lypinator 0:bb348c97df44 4392 #define CAN_F4R2_FB20_Pos (20U)
lypinator 0:bb348c97df44 4393 #define CAN_F4R2_FB20_Msk (0x1U << CAN_F4R2_FB20_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 4394 #define CAN_F4R2_FB20 CAN_F4R2_FB20_Msk /*!<Filter bit 20 */
lypinator 0:bb348c97df44 4395 #define CAN_F4R2_FB21_Pos (21U)
lypinator 0:bb348c97df44 4396 #define CAN_F4R2_FB21_Msk (0x1U << CAN_F4R2_FB21_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 4397 #define CAN_F4R2_FB21 CAN_F4R2_FB21_Msk /*!<Filter bit 21 */
lypinator 0:bb348c97df44 4398 #define CAN_F4R2_FB22_Pos (22U)
lypinator 0:bb348c97df44 4399 #define CAN_F4R2_FB22_Msk (0x1U << CAN_F4R2_FB22_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 4400 #define CAN_F4R2_FB22 CAN_F4R2_FB22_Msk /*!<Filter bit 22 */
lypinator 0:bb348c97df44 4401 #define CAN_F4R2_FB23_Pos (23U)
lypinator 0:bb348c97df44 4402 #define CAN_F4R2_FB23_Msk (0x1U << CAN_F4R2_FB23_Pos) /*!< 0x00800000 */
lypinator 0:bb348c97df44 4403 #define CAN_F4R2_FB23 CAN_F4R2_FB23_Msk /*!<Filter bit 23 */
lypinator 0:bb348c97df44 4404 #define CAN_F4R2_FB24_Pos (24U)
lypinator 0:bb348c97df44 4405 #define CAN_F4R2_FB24_Msk (0x1U << CAN_F4R2_FB24_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 4406 #define CAN_F4R2_FB24 CAN_F4R2_FB24_Msk /*!<Filter bit 24 */
lypinator 0:bb348c97df44 4407 #define CAN_F4R2_FB25_Pos (25U)
lypinator 0:bb348c97df44 4408 #define CAN_F4R2_FB25_Msk (0x1U << CAN_F4R2_FB25_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 4409 #define CAN_F4R2_FB25 CAN_F4R2_FB25_Msk /*!<Filter bit 25 */
lypinator 0:bb348c97df44 4410 #define CAN_F4R2_FB26_Pos (26U)
lypinator 0:bb348c97df44 4411 #define CAN_F4R2_FB26_Msk (0x1U << CAN_F4R2_FB26_Pos) /*!< 0x04000000 */
lypinator 0:bb348c97df44 4412 #define CAN_F4R2_FB26 CAN_F4R2_FB26_Msk /*!<Filter bit 26 */
lypinator 0:bb348c97df44 4413 #define CAN_F4R2_FB27_Pos (27U)
lypinator 0:bb348c97df44 4414 #define CAN_F4R2_FB27_Msk (0x1U << CAN_F4R2_FB27_Pos) /*!< 0x08000000 */
lypinator 0:bb348c97df44 4415 #define CAN_F4R2_FB27 CAN_F4R2_FB27_Msk /*!<Filter bit 27 */
lypinator 0:bb348c97df44 4416 #define CAN_F4R2_FB28_Pos (28U)
lypinator 0:bb348c97df44 4417 #define CAN_F4R2_FB28_Msk (0x1U << CAN_F4R2_FB28_Pos) /*!< 0x10000000 */
lypinator 0:bb348c97df44 4418 #define CAN_F4R2_FB28 CAN_F4R2_FB28_Msk /*!<Filter bit 28 */
lypinator 0:bb348c97df44 4419 #define CAN_F4R2_FB29_Pos (29U)
lypinator 0:bb348c97df44 4420 #define CAN_F4R2_FB29_Msk (0x1U << CAN_F4R2_FB29_Pos) /*!< 0x20000000 */
lypinator 0:bb348c97df44 4421 #define CAN_F4R2_FB29 CAN_F4R2_FB29_Msk /*!<Filter bit 29 */
lypinator 0:bb348c97df44 4422 #define CAN_F4R2_FB30_Pos (30U)
lypinator 0:bb348c97df44 4423 #define CAN_F4R2_FB30_Msk (0x1U << CAN_F4R2_FB30_Pos) /*!< 0x40000000 */
lypinator 0:bb348c97df44 4424 #define CAN_F4R2_FB30 CAN_F4R2_FB30_Msk /*!<Filter bit 30 */
lypinator 0:bb348c97df44 4425 #define CAN_F4R2_FB31_Pos (31U)
lypinator 0:bb348c97df44 4426 #define CAN_F4R2_FB31_Msk (0x1U << CAN_F4R2_FB31_Pos) /*!< 0x80000000 */
lypinator 0:bb348c97df44 4427 #define CAN_F4R2_FB31 CAN_F4R2_FB31_Msk /*!<Filter bit 31 */
lypinator 0:bb348c97df44 4428
lypinator 0:bb348c97df44 4429 /******************* Bit definition for CAN_F5R2 register *******************/
lypinator 0:bb348c97df44 4430 #define CAN_F5R2_FB0_Pos (0U)
lypinator 0:bb348c97df44 4431 #define CAN_F5R2_FB0_Msk (0x1U << CAN_F5R2_FB0_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 4432 #define CAN_F5R2_FB0 CAN_F5R2_FB0_Msk /*!<Filter bit 0 */
lypinator 0:bb348c97df44 4433 #define CAN_F5R2_FB1_Pos (1U)
lypinator 0:bb348c97df44 4434 #define CAN_F5R2_FB1_Msk (0x1U << CAN_F5R2_FB1_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 4435 #define CAN_F5R2_FB1 CAN_F5R2_FB1_Msk /*!<Filter bit 1 */
lypinator 0:bb348c97df44 4436 #define CAN_F5R2_FB2_Pos (2U)
lypinator 0:bb348c97df44 4437 #define CAN_F5R2_FB2_Msk (0x1U << CAN_F5R2_FB2_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 4438 #define CAN_F5R2_FB2 CAN_F5R2_FB2_Msk /*!<Filter bit 2 */
lypinator 0:bb348c97df44 4439 #define CAN_F5R2_FB3_Pos (3U)
lypinator 0:bb348c97df44 4440 #define CAN_F5R2_FB3_Msk (0x1U << CAN_F5R2_FB3_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 4441 #define CAN_F5R2_FB3 CAN_F5R2_FB3_Msk /*!<Filter bit 3 */
lypinator 0:bb348c97df44 4442 #define CAN_F5R2_FB4_Pos (4U)
lypinator 0:bb348c97df44 4443 #define CAN_F5R2_FB4_Msk (0x1U << CAN_F5R2_FB4_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 4444 #define CAN_F5R2_FB4 CAN_F5R2_FB4_Msk /*!<Filter bit 4 */
lypinator 0:bb348c97df44 4445 #define CAN_F5R2_FB5_Pos (5U)
lypinator 0:bb348c97df44 4446 #define CAN_F5R2_FB5_Msk (0x1U << CAN_F5R2_FB5_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 4447 #define CAN_F5R2_FB5 CAN_F5R2_FB5_Msk /*!<Filter bit 5 */
lypinator 0:bb348c97df44 4448 #define CAN_F5R2_FB6_Pos (6U)
lypinator 0:bb348c97df44 4449 #define CAN_F5R2_FB6_Msk (0x1U << CAN_F5R2_FB6_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 4450 #define CAN_F5R2_FB6 CAN_F5R2_FB6_Msk /*!<Filter bit 6 */
lypinator 0:bb348c97df44 4451 #define CAN_F5R2_FB7_Pos (7U)
lypinator 0:bb348c97df44 4452 #define CAN_F5R2_FB7_Msk (0x1U << CAN_F5R2_FB7_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 4453 #define CAN_F5R2_FB7 CAN_F5R2_FB7_Msk /*!<Filter bit 7 */
lypinator 0:bb348c97df44 4454 #define CAN_F5R2_FB8_Pos (8U)
lypinator 0:bb348c97df44 4455 #define CAN_F5R2_FB8_Msk (0x1U << CAN_F5R2_FB8_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 4456 #define CAN_F5R2_FB8 CAN_F5R2_FB8_Msk /*!<Filter bit 8 */
lypinator 0:bb348c97df44 4457 #define CAN_F5R2_FB9_Pos (9U)
lypinator 0:bb348c97df44 4458 #define CAN_F5R2_FB9_Msk (0x1U << CAN_F5R2_FB9_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 4459 #define CAN_F5R2_FB9 CAN_F5R2_FB9_Msk /*!<Filter bit 9 */
lypinator 0:bb348c97df44 4460 #define CAN_F5R2_FB10_Pos (10U)
lypinator 0:bb348c97df44 4461 #define CAN_F5R2_FB10_Msk (0x1U << CAN_F5R2_FB10_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 4462 #define CAN_F5R2_FB10 CAN_F5R2_FB10_Msk /*!<Filter bit 10 */
lypinator 0:bb348c97df44 4463 #define CAN_F5R2_FB11_Pos (11U)
lypinator 0:bb348c97df44 4464 #define CAN_F5R2_FB11_Msk (0x1U << CAN_F5R2_FB11_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 4465 #define CAN_F5R2_FB11 CAN_F5R2_FB11_Msk /*!<Filter bit 11 */
lypinator 0:bb348c97df44 4466 #define CAN_F5R2_FB12_Pos (12U)
lypinator 0:bb348c97df44 4467 #define CAN_F5R2_FB12_Msk (0x1U << CAN_F5R2_FB12_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 4468 #define CAN_F5R2_FB12 CAN_F5R2_FB12_Msk /*!<Filter bit 12 */
lypinator 0:bb348c97df44 4469 #define CAN_F5R2_FB13_Pos (13U)
lypinator 0:bb348c97df44 4470 #define CAN_F5R2_FB13_Msk (0x1U << CAN_F5R2_FB13_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 4471 #define CAN_F5R2_FB13 CAN_F5R2_FB13_Msk /*!<Filter bit 13 */
lypinator 0:bb348c97df44 4472 #define CAN_F5R2_FB14_Pos (14U)
lypinator 0:bb348c97df44 4473 #define CAN_F5R2_FB14_Msk (0x1U << CAN_F5R2_FB14_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 4474 #define CAN_F5R2_FB14 CAN_F5R2_FB14_Msk /*!<Filter bit 14 */
lypinator 0:bb348c97df44 4475 #define CAN_F5R2_FB15_Pos (15U)
lypinator 0:bb348c97df44 4476 #define CAN_F5R2_FB15_Msk (0x1U << CAN_F5R2_FB15_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 4477 #define CAN_F5R2_FB15 CAN_F5R2_FB15_Msk /*!<Filter bit 15 */
lypinator 0:bb348c97df44 4478 #define CAN_F5R2_FB16_Pos (16U)
lypinator 0:bb348c97df44 4479 #define CAN_F5R2_FB16_Msk (0x1U << CAN_F5R2_FB16_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 4480 #define CAN_F5R2_FB16 CAN_F5R2_FB16_Msk /*!<Filter bit 16 */
lypinator 0:bb348c97df44 4481 #define CAN_F5R2_FB17_Pos (17U)
lypinator 0:bb348c97df44 4482 #define CAN_F5R2_FB17_Msk (0x1U << CAN_F5R2_FB17_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 4483 #define CAN_F5R2_FB17 CAN_F5R2_FB17_Msk /*!<Filter bit 17 */
lypinator 0:bb348c97df44 4484 #define CAN_F5R2_FB18_Pos (18U)
lypinator 0:bb348c97df44 4485 #define CAN_F5R2_FB18_Msk (0x1U << CAN_F5R2_FB18_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 4486 #define CAN_F5R2_FB18 CAN_F5R2_FB18_Msk /*!<Filter bit 18 */
lypinator 0:bb348c97df44 4487 #define CAN_F5R2_FB19_Pos (19U)
lypinator 0:bb348c97df44 4488 #define CAN_F5R2_FB19_Msk (0x1U << CAN_F5R2_FB19_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 4489 #define CAN_F5R2_FB19 CAN_F5R2_FB19_Msk /*!<Filter bit 19 */
lypinator 0:bb348c97df44 4490 #define CAN_F5R2_FB20_Pos (20U)
lypinator 0:bb348c97df44 4491 #define CAN_F5R2_FB20_Msk (0x1U << CAN_F5R2_FB20_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 4492 #define CAN_F5R2_FB20 CAN_F5R2_FB20_Msk /*!<Filter bit 20 */
lypinator 0:bb348c97df44 4493 #define CAN_F5R2_FB21_Pos (21U)
lypinator 0:bb348c97df44 4494 #define CAN_F5R2_FB21_Msk (0x1U << CAN_F5R2_FB21_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 4495 #define CAN_F5R2_FB21 CAN_F5R2_FB21_Msk /*!<Filter bit 21 */
lypinator 0:bb348c97df44 4496 #define CAN_F5R2_FB22_Pos (22U)
lypinator 0:bb348c97df44 4497 #define CAN_F5R2_FB22_Msk (0x1U << CAN_F5R2_FB22_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 4498 #define CAN_F5R2_FB22 CAN_F5R2_FB22_Msk /*!<Filter bit 22 */
lypinator 0:bb348c97df44 4499 #define CAN_F5R2_FB23_Pos (23U)
lypinator 0:bb348c97df44 4500 #define CAN_F5R2_FB23_Msk (0x1U << CAN_F5R2_FB23_Pos) /*!< 0x00800000 */
lypinator 0:bb348c97df44 4501 #define CAN_F5R2_FB23 CAN_F5R2_FB23_Msk /*!<Filter bit 23 */
lypinator 0:bb348c97df44 4502 #define CAN_F5R2_FB24_Pos (24U)
lypinator 0:bb348c97df44 4503 #define CAN_F5R2_FB24_Msk (0x1U << CAN_F5R2_FB24_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 4504 #define CAN_F5R2_FB24 CAN_F5R2_FB24_Msk /*!<Filter bit 24 */
lypinator 0:bb348c97df44 4505 #define CAN_F5R2_FB25_Pos (25U)
lypinator 0:bb348c97df44 4506 #define CAN_F5R2_FB25_Msk (0x1U << CAN_F5R2_FB25_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 4507 #define CAN_F5R2_FB25 CAN_F5R2_FB25_Msk /*!<Filter bit 25 */
lypinator 0:bb348c97df44 4508 #define CAN_F5R2_FB26_Pos (26U)
lypinator 0:bb348c97df44 4509 #define CAN_F5R2_FB26_Msk (0x1U << CAN_F5R2_FB26_Pos) /*!< 0x04000000 */
lypinator 0:bb348c97df44 4510 #define CAN_F5R2_FB26 CAN_F5R2_FB26_Msk /*!<Filter bit 26 */
lypinator 0:bb348c97df44 4511 #define CAN_F5R2_FB27_Pos (27U)
lypinator 0:bb348c97df44 4512 #define CAN_F5R2_FB27_Msk (0x1U << CAN_F5R2_FB27_Pos) /*!< 0x08000000 */
lypinator 0:bb348c97df44 4513 #define CAN_F5R2_FB27 CAN_F5R2_FB27_Msk /*!<Filter bit 27 */
lypinator 0:bb348c97df44 4514 #define CAN_F5R2_FB28_Pos (28U)
lypinator 0:bb348c97df44 4515 #define CAN_F5R2_FB28_Msk (0x1U << CAN_F5R2_FB28_Pos) /*!< 0x10000000 */
lypinator 0:bb348c97df44 4516 #define CAN_F5R2_FB28 CAN_F5R2_FB28_Msk /*!<Filter bit 28 */
lypinator 0:bb348c97df44 4517 #define CAN_F5R2_FB29_Pos (29U)
lypinator 0:bb348c97df44 4518 #define CAN_F5R2_FB29_Msk (0x1U << CAN_F5R2_FB29_Pos) /*!< 0x20000000 */
lypinator 0:bb348c97df44 4519 #define CAN_F5R2_FB29 CAN_F5R2_FB29_Msk /*!<Filter bit 29 */
lypinator 0:bb348c97df44 4520 #define CAN_F5R2_FB30_Pos (30U)
lypinator 0:bb348c97df44 4521 #define CAN_F5R2_FB30_Msk (0x1U << CAN_F5R2_FB30_Pos) /*!< 0x40000000 */
lypinator 0:bb348c97df44 4522 #define CAN_F5R2_FB30 CAN_F5R2_FB30_Msk /*!<Filter bit 30 */
lypinator 0:bb348c97df44 4523 #define CAN_F5R2_FB31_Pos (31U)
lypinator 0:bb348c97df44 4524 #define CAN_F5R2_FB31_Msk (0x1U << CAN_F5R2_FB31_Pos) /*!< 0x80000000 */
lypinator 0:bb348c97df44 4525 #define CAN_F5R2_FB31 CAN_F5R2_FB31_Msk /*!<Filter bit 31 */
lypinator 0:bb348c97df44 4526
lypinator 0:bb348c97df44 4527 /******************* Bit definition for CAN_F6R2 register *******************/
lypinator 0:bb348c97df44 4528 #define CAN_F6R2_FB0_Pos (0U)
lypinator 0:bb348c97df44 4529 #define CAN_F6R2_FB0_Msk (0x1U << CAN_F6R2_FB0_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 4530 #define CAN_F6R2_FB0 CAN_F6R2_FB0_Msk /*!<Filter bit 0 */
lypinator 0:bb348c97df44 4531 #define CAN_F6R2_FB1_Pos (1U)
lypinator 0:bb348c97df44 4532 #define CAN_F6R2_FB1_Msk (0x1U << CAN_F6R2_FB1_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 4533 #define CAN_F6R2_FB1 CAN_F6R2_FB1_Msk /*!<Filter bit 1 */
lypinator 0:bb348c97df44 4534 #define CAN_F6R2_FB2_Pos (2U)
lypinator 0:bb348c97df44 4535 #define CAN_F6R2_FB2_Msk (0x1U << CAN_F6R2_FB2_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 4536 #define CAN_F6R2_FB2 CAN_F6R2_FB2_Msk /*!<Filter bit 2 */
lypinator 0:bb348c97df44 4537 #define CAN_F6R2_FB3_Pos (3U)
lypinator 0:bb348c97df44 4538 #define CAN_F6R2_FB3_Msk (0x1U << CAN_F6R2_FB3_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 4539 #define CAN_F6R2_FB3 CAN_F6R2_FB3_Msk /*!<Filter bit 3 */
lypinator 0:bb348c97df44 4540 #define CAN_F6R2_FB4_Pos (4U)
lypinator 0:bb348c97df44 4541 #define CAN_F6R2_FB4_Msk (0x1U << CAN_F6R2_FB4_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 4542 #define CAN_F6R2_FB4 CAN_F6R2_FB4_Msk /*!<Filter bit 4 */
lypinator 0:bb348c97df44 4543 #define CAN_F6R2_FB5_Pos (5U)
lypinator 0:bb348c97df44 4544 #define CAN_F6R2_FB5_Msk (0x1U << CAN_F6R2_FB5_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 4545 #define CAN_F6R2_FB5 CAN_F6R2_FB5_Msk /*!<Filter bit 5 */
lypinator 0:bb348c97df44 4546 #define CAN_F6R2_FB6_Pos (6U)
lypinator 0:bb348c97df44 4547 #define CAN_F6R2_FB6_Msk (0x1U << CAN_F6R2_FB6_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 4548 #define CAN_F6R2_FB6 CAN_F6R2_FB6_Msk /*!<Filter bit 6 */
lypinator 0:bb348c97df44 4549 #define CAN_F6R2_FB7_Pos (7U)
lypinator 0:bb348c97df44 4550 #define CAN_F6R2_FB7_Msk (0x1U << CAN_F6R2_FB7_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 4551 #define CAN_F6R2_FB7 CAN_F6R2_FB7_Msk /*!<Filter bit 7 */
lypinator 0:bb348c97df44 4552 #define CAN_F6R2_FB8_Pos (8U)
lypinator 0:bb348c97df44 4553 #define CAN_F6R2_FB8_Msk (0x1U << CAN_F6R2_FB8_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 4554 #define CAN_F6R2_FB8 CAN_F6R2_FB8_Msk /*!<Filter bit 8 */
lypinator 0:bb348c97df44 4555 #define CAN_F6R2_FB9_Pos (9U)
lypinator 0:bb348c97df44 4556 #define CAN_F6R2_FB9_Msk (0x1U << CAN_F6R2_FB9_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 4557 #define CAN_F6R2_FB9 CAN_F6R2_FB9_Msk /*!<Filter bit 9 */
lypinator 0:bb348c97df44 4558 #define CAN_F6R2_FB10_Pos (10U)
lypinator 0:bb348c97df44 4559 #define CAN_F6R2_FB10_Msk (0x1U << CAN_F6R2_FB10_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 4560 #define CAN_F6R2_FB10 CAN_F6R2_FB10_Msk /*!<Filter bit 10 */
lypinator 0:bb348c97df44 4561 #define CAN_F6R2_FB11_Pos (11U)
lypinator 0:bb348c97df44 4562 #define CAN_F6R2_FB11_Msk (0x1U << CAN_F6R2_FB11_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 4563 #define CAN_F6R2_FB11 CAN_F6R2_FB11_Msk /*!<Filter bit 11 */
lypinator 0:bb348c97df44 4564 #define CAN_F6R2_FB12_Pos (12U)
lypinator 0:bb348c97df44 4565 #define CAN_F6R2_FB12_Msk (0x1U << CAN_F6R2_FB12_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 4566 #define CAN_F6R2_FB12 CAN_F6R2_FB12_Msk /*!<Filter bit 12 */
lypinator 0:bb348c97df44 4567 #define CAN_F6R2_FB13_Pos (13U)
lypinator 0:bb348c97df44 4568 #define CAN_F6R2_FB13_Msk (0x1U << CAN_F6R2_FB13_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 4569 #define CAN_F6R2_FB13 CAN_F6R2_FB13_Msk /*!<Filter bit 13 */
lypinator 0:bb348c97df44 4570 #define CAN_F6R2_FB14_Pos (14U)
lypinator 0:bb348c97df44 4571 #define CAN_F6R2_FB14_Msk (0x1U << CAN_F6R2_FB14_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 4572 #define CAN_F6R2_FB14 CAN_F6R2_FB14_Msk /*!<Filter bit 14 */
lypinator 0:bb348c97df44 4573 #define CAN_F6R2_FB15_Pos (15U)
lypinator 0:bb348c97df44 4574 #define CAN_F6R2_FB15_Msk (0x1U << CAN_F6R2_FB15_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 4575 #define CAN_F6R2_FB15 CAN_F6R2_FB15_Msk /*!<Filter bit 15 */
lypinator 0:bb348c97df44 4576 #define CAN_F6R2_FB16_Pos (16U)
lypinator 0:bb348c97df44 4577 #define CAN_F6R2_FB16_Msk (0x1U << CAN_F6R2_FB16_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 4578 #define CAN_F6R2_FB16 CAN_F6R2_FB16_Msk /*!<Filter bit 16 */
lypinator 0:bb348c97df44 4579 #define CAN_F6R2_FB17_Pos (17U)
lypinator 0:bb348c97df44 4580 #define CAN_F6R2_FB17_Msk (0x1U << CAN_F6R2_FB17_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 4581 #define CAN_F6R2_FB17 CAN_F6R2_FB17_Msk /*!<Filter bit 17 */
lypinator 0:bb348c97df44 4582 #define CAN_F6R2_FB18_Pos (18U)
lypinator 0:bb348c97df44 4583 #define CAN_F6R2_FB18_Msk (0x1U << CAN_F6R2_FB18_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 4584 #define CAN_F6R2_FB18 CAN_F6R2_FB18_Msk /*!<Filter bit 18 */
lypinator 0:bb348c97df44 4585 #define CAN_F6R2_FB19_Pos (19U)
lypinator 0:bb348c97df44 4586 #define CAN_F6R2_FB19_Msk (0x1U << CAN_F6R2_FB19_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 4587 #define CAN_F6R2_FB19 CAN_F6R2_FB19_Msk /*!<Filter bit 19 */
lypinator 0:bb348c97df44 4588 #define CAN_F6R2_FB20_Pos (20U)
lypinator 0:bb348c97df44 4589 #define CAN_F6R2_FB20_Msk (0x1U << CAN_F6R2_FB20_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 4590 #define CAN_F6R2_FB20 CAN_F6R2_FB20_Msk /*!<Filter bit 20 */
lypinator 0:bb348c97df44 4591 #define CAN_F6R2_FB21_Pos (21U)
lypinator 0:bb348c97df44 4592 #define CAN_F6R2_FB21_Msk (0x1U << CAN_F6R2_FB21_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 4593 #define CAN_F6R2_FB21 CAN_F6R2_FB21_Msk /*!<Filter bit 21 */
lypinator 0:bb348c97df44 4594 #define CAN_F6R2_FB22_Pos (22U)
lypinator 0:bb348c97df44 4595 #define CAN_F6R2_FB22_Msk (0x1U << CAN_F6R2_FB22_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 4596 #define CAN_F6R2_FB22 CAN_F6R2_FB22_Msk /*!<Filter bit 22 */
lypinator 0:bb348c97df44 4597 #define CAN_F6R2_FB23_Pos (23U)
lypinator 0:bb348c97df44 4598 #define CAN_F6R2_FB23_Msk (0x1U << CAN_F6R2_FB23_Pos) /*!< 0x00800000 */
lypinator 0:bb348c97df44 4599 #define CAN_F6R2_FB23 CAN_F6R2_FB23_Msk /*!<Filter bit 23 */
lypinator 0:bb348c97df44 4600 #define CAN_F6R2_FB24_Pos (24U)
lypinator 0:bb348c97df44 4601 #define CAN_F6R2_FB24_Msk (0x1U << CAN_F6R2_FB24_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 4602 #define CAN_F6R2_FB24 CAN_F6R2_FB24_Msk /*!<Filter bit 24 */
lypinator 0:bb348c97df44 4603 #define CAN_F6R2_FB25_Pos (25U)
lypinator 0:bb348c97df44 4604 #define CAN_F6R2_FB25_Msk (0x1U << CAN_F6R2_FB25_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 4605 #define CAN_F6R2_FB25 CAN_F6R2_FB25_Msk /*!<Filter bit 25 */
lypinator 0:bb348c97df44 4606 #define CAN_F6R2_FB26_Pos (26U)
lypinator 0:bb348c97df44 4607 #define CAN_F6R2_FB26_Msk (0x1U << CAN_F6R2_FB26_Pos) /*!< 0x04000000 */
lypinator 0:bb348c97df44 4608 #define CAN_F6R2_FB26 CAN_F6R2_FB26_Msk /*!<Filter bit 26 */
lypinator 0:bb348c97df44 4609 #define CAN_F6R2_FB27_Pos (27U)
lypinator 0:bb348c97df44 4610 #define CAN_F6R2_FB27_Msk (0x1U << CAN_F6R2_FB27_Pos) /*!< 0x08000000 */
lypinator 0:bb348c97df44 4611 #define CAN_F6R2_FB27 CAN_F6R2_FB27_Msk /*!<Filter bit 27 */
lypinator 0:bb348c97df44 4612 #define CAN_F6R2_FB28_Pos (28U)
lypinator 0:bb348c97df44 4613 #define CAN_F6R2_FB28_Msk (0x1U << CAN_F6R2_FB28_Pos) /*!< 0x10000000 */
lypinator 0:bb348c97df44 4614 #define CAN_F6R2_FB28 CAN_F6R2_FB28_Msk /*!<Filter bit 28 */
lypinator 0:bb348c97df44 4615 #define CAN_F6R2_FB29_Pos (29U)
lypinator 0:bb348c97df44 4616 #define CAN_F6R2_FB29_Msk (0x1U << CAN_F6R2_FB29_Pos) /*!< 0x20000000 */
lypinator 0:bb348c97df44 4617 #define CAN_F6R2_FB29 CAN_F6R2_FB29_Msk /*!<Filter bit 29 */
lypinator 0:bb348c97df44 4618 #define CAN_F6R2_FB30_Pos (30U)
lypinator 0:bb348c97df44 4619 #define CAN_F6R2_FB30_Msk (0x1U << CAN_F6R2_FB30_Pos) /*!< 0x40000000 */
lypinator 0:bb348c97df44 4620 #define CAN_F6R2_FB30 CAN_F6R2_FB30_Msk /*!<Filter bit 30 */
lypinator 0:bb348c97df44 4621 #define CAN_F6R2_FB31_Pos (31U)
lypinator 0:bb348c97df44 4622 #define CAN_F6R2_FB31_Msk (0x1U << CAN_F6R2_FB31_Pos) /*!< 0x80000000 */
lypinator 0:bb348c97df44 4623 #define CAN_F6R2_FB31 CAN_F6R2_FB31_Msk /*!<Filter bit 31 */
lypinator 0:bb348c97df44 4624
lypinator 0:bb348c97df44 4625 /******************* Bit definition for CAN_F7R2 register *******************/
lypinator 0:bb348c97df44 4626 #define CAN_F7R2_FB0_Pos (0U)
lypinator 0:bb348c97df44 4627 #define CAN_F7R2_FB0_Msk (0x1U << CAN_F7R2_FB0_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 4628 #define CAN_F7R2_FB0 CAN_F7R2_FB0_Msk /*!<Filter bit 0 */
lypinator 0:bb348c97df44 4629 #define CAN_F7R2_FB1_Pos (1U)
lypinator 0:bb348c97df44 4630 #define CAN_F7R2_FB1_Msk (0x1U << CAN_F7R2_FB1_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 4631 #define CAN_F7R2_FB1 CAN_F7R2_FB1_Msk /*!<Filter bit 1 */
lypinator 0:bb348c97df44 4632 #define CAN_F7R2_FB2_Pos (2U)
lypinator 0:bb348c97df44 4633 #define CAN_F7R2_FB2_Msk (0x1U << CAN_F7R2_FB2_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 4634 #define CAN_F7R2_FB2 CAN_F7R2_FB2_Msk /*!<Filter bit 2 */
lypinator 0:bb348c97df44 4635 #define CAN_F7R2_FB3_Pos (3U)
lypinator 0:bb348c97df44 4636 #define CAN_F7R2_FB3_Msk (0x1U << CAN_F7R2_FB3_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 4637 #define CAN_F7R2_FB3 CAN_F7R2_FB3_Msk /*!<Filter bit 3 */
lypinator 0:bb348c97df44 4638 #define CAN_F7R2_FB4_Pos (4U)
lypinator 0:bb348c97df44 4639 #define CAN_F7R2_FB4_Msk (0x1U << CAN_F7R2_FB4_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 4640 #define CAN_F7R2_FB4 CAN_F7R2_FB4_Msk /*!<Filter bit 4 */
lypinator 0:bb348c97df44 4641 #define CAN_F7R2_FB5_Pos (5U)
lypinator 0:bb348c97df44 4642 #define CAN_F7R2_FB5_Msk (0x1U << CAN_F7R2_FB5_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 4643 #define CAN_F7R2_FB5 CAN_F7R2_FB5_Msk /*!<Filter bit 5 */
lypinator 0:bb348c97df44 4644 #define CAN_F7R2_FB6_Pos (6U)
lypinator 0:bb348c97df44 4645 #define CAN_F7R2_FB6_Msk (0x1U << CAN_F7R2_FB6_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 4646 #define CAN_F7R2_FB6 CAN_F7R2_FB6_Msk /*!<Filter bit 6 */
lypinator 0:bb348c97df44 4647 #define CAN_F7R2_FB7_Pos (7U)
lypinator 0:bb348c97df44 4648 #define CAN_F7R2_FB7_Msk (0x1U << CAN_F7R2_FB7_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 4649 #define CAN_F7R2_FB7 CAN_F7R2_FB7_Msk /*!<Filter bit 7 */
lypinator 0:bb348c97df44 4650 #define CAN_F7R2_FB8_Pos (8U)
lypinator 0:bb348c97df44 4651 #define CAN_F7R2_FB8_Msk (0x1U << CAN_F7R2_FB8_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 4652 #define CAN_F7R2_FB8 CAN_F7R2_FB8_Msk /*!<Filter bit 8 */
lypinator 0:bb348c97df44 4653 #define CAN_F7R2_FB9_Pos (9U)
lypinator 0:bb348c97df44 4654 #define CAN_F7R2_FB9_Msk (0x1U << CAN_F7R2_FB9_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 4655 #define CAN_F7R2_FB9 CAN_F7R2_FB9_Msk /*!<Filter bit 9 */
lypinator 0:bb348c97df44 4656 #define CAN_F7R2_FB10_Pos (10U)
lypinator 0:bb348c97df44 4657 #define CAN_F7R2_FB10_Msk (0x1U << CAN_F7R2_FB10_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 4658 #define CAN_F7R2_FB10 CAN_F7R2_FB10_Msk /*!<Filter bit 10 */
lypinator 0:bb348c97df44 4659 #define CAN_F7R2_FB11_Pos (11U)
lypinator 0:bb348c97df44 4660 #define CAN_F7R2_FB11_Msk (0x1U << CAN_F7R2_FB11_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 4661 #define CAN_F7R2_FB11 CAN_F7R2_FB11_Msk /*!<Filter bit 11 */
lypinator 0:bb348c97df44 4662 #define CAN_F7R2_FB12_Pos (12U)
lypinator 0:bb348c97df44 4663 #define CAN_F7R2_FB12_Msk (0x1U << CAN_F7R2_FB12_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 4664 #define CAN_F7R2_FB12 CAN_F7R2_FB12_Msk /*!<Filter bit 12 */
lypinator 0:bb348c97df44 4665 #define CAN_F7R2_FB13_Pos (13U)
lypinator 0:bb348c97df44 4666 #define CAN_F7R2_FB13_Msk (0x1U << CAN_F7R2_FB13_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 4667 #define CAN_F7R2_FB13 CAN_F7R2_FB13_Msk /*!<Filter bit 13 */
lypinator 0:bb348c97df44 4668 #define CAN_F7R2_FB14_Pos (14U)
lypinator 0:bb348c97df44 4669 #define CAN_F7R2_FB14_Msk (0x1U << CAN_F7R2_FB14_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 4670 #define CAN_F7R2_FB14 CAN_F7R2_FB14_Msk /*!<Filter bit 14 */
lypinator 0:bb348c97df44 4671 #define CAN_F7R2_FB15_Pos (15U)
lypinator 0:bb348c97df44 4672 #define CAN_F7R2_FB15_Msk (0x1U << CAN_F7R2_FB15_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 4673 #define CAN_F7R2_FB15 CAN_F7R2_FB15_Msk /*!<Filter bit 15 */
lypinator 0:bb348c97df44 4674 #define CAN_F7R2_FB16_Pos (16U)
lypinator 0:bb348c97df44 4675 #define CAN_F7R2_FB16_Msk (0x1U << CAN_F7R2_FB16_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 4676 #define CAN_F7R2_FB16 CAN_F7R2_FB16_Msk /*!<Filter bit 16 */
lypinator 0:bb348c97df44 4677 #define CAN_F7R2_FB17_Pos (17U)
lypinator 0:bb348c97df44 4678 #define CAN_F7R2_FB17_Msk (0x1U << CAN_F7R2_FB17_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 4679 #define CAN_F7R2_FB17 CAN_F7R2_FB17_Msk /*!<Filter bit 17 */
lypinator 0:bb348c97df44 4680 #define CAN_F7R2_FB18_Pos (18U)
lypinator 0:bb348c97df44 4681 #define CAN_F7R2_FB18_Msk (0x1U << CAN_F7R2_FB18_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 4682 #define CAN_F7R2_FB18 CAN_F7R2_FB18_Msk /*!<Filter bit 18 */
lypinator 0:bb348c97df44 4683 #define CAN_F7R2_FB19_Pos (19U)
lypinator 0:bb348c97df44 4684 #define CAN_F7R2_FB19_Msk (0x1U << CAN_F7R2_FB19_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 4685 #define CAN_F7R2_FB19 CAN_F7R2_FB19_Msk /*!<Filter bit 19 */
lypinator 0:bb348c97df44 4686 #define CAN_F7R2_FB20_Pos (20U)
lypinator 0:bb348c97df44 4687 #define CAN_F7R2_FB20_Msk (0x1U << CAN_F7R2_FB20_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 4688 #define CAN_F7R2_FB20 CAN_F7R2_FB20_Msk /*!<Filter bit 20 */
lypinator 0:bb348c97df44 4689 #define CAN_F7R2_FB21_Pos (21U)
lypinator 0:bb348c97df44 4690 #define CAN_F7R2_FB21_Msk (0x1U << CAN_F7R2_FB21_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 4691 #define CAN_F7R2_FB21 CAN_F7R2_FB21_Msk /*!<Filter bit 21 */
lypinator 0:bb348c97df44 4692 #define CAN_F7R2_FB22_Pos (22U)
lypinator 0:bb348c97df44 4693 #define CAN_F7R2_FB22_Msk (0x1U << CAN_F7R2_FB22_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 4694 #define CAN_F7R2_FB22 CAN_F7R2_FB22_Msk /*!<Filter bit 22 */
lypinator 0:bb348c97df44 4695 #define CAN_F7R2_FB23_Pos (23U)
lypinator 0:bb348c97df44 4696 #define CAN_F7R2_FB23_Msk (0x1U << CAN_F7R2_FB23_Pos) /*!< 0x00800000 */
lypinator 0:bb348c97df44 4697 #define CAN_F7R2_FB23 CAN_F7R2_FB23_Msk /*!<Filter bit 23 */
lypinator 0:bb348c97df44 4698 #define CAN_F7R2_FB24_Pos (24U)
lypinator 0:bb348c97df44 4699 #define CAN_F7R2_FB24_Msk (0x1U << CAN_F7R2_FB24_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 4700 #define CAN_F7R2_FB24 CAN_F7R2_FB24_Msk /*!<Filter bit 24 */
lypinator 0:bb348c97df44 4701 #define CAN_F7R2_FB25_Pos (25U)
lypinator 0:bb348c97df44 4702 #define CAN_F7R2_FB25_Msk (0x1U << CAN_F7R2_FB25_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 4703 #define CAN_F7R2_FB25 CAN_F7R2_FB25_Msk /*!<Filter bit 25 */
lypinator 0:bb348c97df44 4704 #define CAN_F7R2_FB26_Pos (26U)
lypinator 0:bb348c97df44 4705 #define CAN_F7R2_FB26_Msk (0x1U << CAN_F7R2_FB26_Pos) /*!< 0x04000000 */
lypinator 0:bb348c97df44 4706 #define CAN_F7R2_FB26 CAN_F7R2_FB26_Msk /*!<Filter bit 26 */
lypinator 0:bb348c97df44 4707 #define CAN_F7R2_FB27_Pos (27U)
lypinator 0:bb348c97df44 4708 #define CAN_F7R2_FB27_Msk (0x1U << CAN_F7R2_FB27_Pos) /*!< 0x08000000 */
lypinator 0:bb348c97df44 4709 #define CAN_F7R2_FB27 CAN_F7R2_FB27_Msk /*!<Filter bit 27 */
lypinator 0:bb348c97df44 4710 #define CAN_F7R2_FB28_Pos (28U)
lypinator 0:bb348c97df44 4711 #define CAN_F7R2_FB28_Msk (0x1U << CAN_F7R2_FB28_Pos) /*!< 0x10000000 */
lypinator 0:bb348c97df44 4712 #define CAN_F7R2_FB28 CAN_F7R2_FB28_Msk /*!<Filter bit 28 */
lypinator 0:bb348c97df44 4713 #define CAN_F7R2_FB29_Pos (29U)
lypinator 0:bb348c97df44 4714 #define CAN_F7R2_FB29_Msk (0x1U << CAN_F7R2_FB29_Pos) /*!< 0x20000000 */
lypinator 0:bb348c97df44 4715 #define CAN_F7R2_FB29 CAN_F7R2_FB29_Msk /*!<Filter bit 29 */
lypinator 0:bb348c97df44 4716 #define CAN_F7R2_FB30_Pos (30U)
lypinator 0:bb348c97df44 4717 #define CAN_F7R2_FB30_Msk (0x1U << CAN_F7R2_FB30_Pos) /*!< 0x40000000 */
lypinator 0:bb348c97df44 4718 #define CAN_F7R2_FB30 CAN_F7R2_FB30_Msk /*!<Filter bit 30 */
lypinator 0:bb348c97df44 4719 #define CAN_F7R2_FB31_Pos (31U)
lypinator 0:bb348c97df44 4720 #define CAN_F7R2_FB31_Msk (0x1U << CAN_F7R2_FB31_Pos) /*!< 0x80000000 */
lypinator 0:bb348c97df44 4721 #define CAN_F7R2_FB31 CAN_F7R2_FB31_Msk /*!<Filter bit 31 */
lypinator 0:bb348c97df44 4722
lypinator 0:bb348c97df44 4723 /******************* Bit definition for CAN_F8R2 register *******************/
lypinator 0:bb348c97df44 4724 #define CAN_F8R2_FB0_Pos (0U)
lypinator 0:bb348c97df44 4725 #define CAN_F8R2_FB0_Msk (0x1U << CAN_F8R2_FB0_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 4726 #define CAN_F8R2_FB0 CAN_F8R2_FB0_Msk /*!<Filter bit 0 */
lypinator 0:bb348c97df44 4727 #define CAN_F8R2_FB1_Pos (1U)
lypinator 0:bb348c97df44 4728 #define CAN_F8R2_FB1_Msk (0x1U << CAN_F8R2_FB1_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 4729 #define CAN_F8R2_FB1 CAN_F8R2_FB1_Msk /*!<Filter bit 1 */
lypinator 0:bb348c97df44 4730 #define CAN_F8R2_FB2_Pos (2U)
lypinator 0:bb348c97df44 4731 #define CAN_F8R2_FB2_Msk (0x1U << CAN_F8R2_FB2_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 4732 #define CAN_F8R2_FB2 CAN_F8R2_FB2_Msk /*!<Filter bit 2 */
lypinator 0:bb348c97df44 4733 #define CAN_F8R2_FB3_Pos (3U)
lypinator 0:bb348c97df44 4734 #define CAN_F8R2_FB3_Msk (0x1U << CAN_F8R2_FB3_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 4735 #define CAN_F8R2_FB3 CAN_F8R2_FB3_Msk /*!<Filter bit 3 */
lypinator 0:bb348c97df44 4736 #define CAN_F8R2_FB4_Pos (4U)
lypinator 0:bb348c97df44 4737 #define CAN_F8R2_FB4_Msk (0x1U << CAN_F8R2_FB4_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 4738 #define CAN_F8R2_FB4 CAN_F8R2_FB4_Msk /*!<Filter bit 4 */
lypinator 0:bb348c97df44 4739 #define CAN_F8R2_FB5_Pos (5U)
lypinator 0:bb348c97df44 4740 #define CAN_F8R2_FB5_Msk (0x1U << CAN_F8R2_FB5_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 4741 #define CAN_F8R2_FB5 CAN_F8R2_FB5_Msk /*!<Filter bit 5 */
lypinator 0:bb348c97df44 4742 #define CAN_F8R2_FB6_Pos (6U)
lypinator 0:bb348c97df44 4743 #define CAN_F8R2_FB6_Msk (0x1U << CAN_F8R2_FB6_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 4744 #define CAN_F8R2_FB6 CAN_F8R2_FB6_Msk /*!<Filter bit 6 */
lypinator 0:bb348c97df44 4745 #define CAN_F8R2_FB7_Pos (7U)
lypinator 0:bb348c97df44 4746 #define CAN_F8R2_FB7_Msk (0x1U << CAN_F8R2_FB7_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 4747 #define CAN_F8R2_FB7 CAN_F8R2_FB7_Msk /*!<Filter bit 7 */
lypinator 0:bb348c97df44 4748 #define CAN_F8R2_FB8_Pos (8U)
lypinator 0:bb348c97df44 4749 #define CAN_F8R2_FB8_Msk (0x1U << CAN_F8R2_FB8_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 4750 #define CAN_F8R2_FB8 CAN_F8R2_FB8_Msk /*!<Filter bit 8 */
lypinator 0:bb348c97df44 4751 #define CAN_F8R2_FB9_Pos (9U)
lypinator 0:bb348c97df44 4752 #define CAN_F8R2_FB9_Msk (0x1U << CAN_F8R2_FB9_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 4753 #define CAN_F8R2_FB9 CAN_F8R2_FB9_Msk /*!<Filter bit 9 */
lypinator 0:bb348c97df44 4754 #define CAN_F8R2_FB10_Pos (10U)
lypinator 0:bb348c97df44 4755 #define CAN_F8R2_FB10_Msk (0x1U << CAN_F8R2_FB10_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 4756 #define CAN_F8R2_FB10 CAN_F8R2_FB10_Msk /*!<Filter bit 10 */
lypinator 0:bb348c97df44 4757 #define CAN_F8R2_FB11_Pos (11U)
lypinator 0:bb348c97df44 4758 #define CAN_F8R2_FB11_Msk (0x1U << CAN_F8R2_FB11_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 4759 #define CAN_F8R2_FB11 CAN_F8R2_FB11_Msk /*!<Filter bit 11 */
lypinator 0:bb348c97df44 4760 #define CAN_F8R2_FB12_Pos (12U)
lypinator 0:bb348c97df44 4761 #define CAN_F8R2_FB12_Msk (0x1U << CAN_F8R2_FB12_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 4762 #define CAN_F8R2_FB12 CAN_F8R2_FB12_Msk /*!<Filter bit 12 */
lypinator 0:bb348c97df44 4763 #define CAN_F8R2_FB13_Pos (13U)
lypinator 0:bb348c97df44 4764 #define CAN_F8R2_FB13_Msk (0x1U << CAN_F8R2_FB13_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 4765 #define CAN_F8R2_FB13 CAN_F8R2_FB13_Msk /*!<Filter bit 13 */
lypinator 0:bb348c97df44 4766 #define CAN_F8R2_FB14_Pos (14U)
lypinator 0:bb348c97df44 4767 #define CAN_F8R2_FB14_Msk (0x1U << CAN_F8R2_FB14_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 4768 #define CAN_F8R2_FB14 CAN_F8R2_FB14_Msk /*!<Filter bit 14 */
lypinator 0:bb348c97df44 4769 #define CAN_F8R2_FB15_Pos (15U)
lypinator 0:bb348c97df44 4770 #define CAN_F8R2_FB15_Msk (0x1U << CAN_F8R2_FB15_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 4771 #define CAN_F8R2_FB15 CAN_F8R2_FB15_Msk /*!<Filter bit 15 */
lypinator 0:bb348c97df44 4772 #define CAN_F8R2_FB16_Pos (16U)
lypinator 0:bb348c97df44 4773 #define CAN_F8R2_FB16_Msk (0x1U << CAN_F8R2_FB16_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 4774 #define CAN_F8R2_FB16 CAN_F8R2_FB16_Msk /*!<Filter bit 16 */
lypinator 0:bb348c97df44 4775 #define CAN_F8R2_FB17_Pos (17U)
lypinator 0:bb348c97df44 4776 #define CAN_F8R2_FB17_Msk (0x1U << CAN_F8R2_FB17_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 4777 #define CAN_F8R2_FB17 CAN_F8R2_FB17_Msk /*!<Filter bit 17 */
lypinator 0:bb348c97df44 4778 #define CAN_F8R2_FB18_Pos (18U)
lypinator 0:bb348c97df44 4779 #define CAN_F8R2_FB18_Msk (0x1U << CAN_F8R2_FB18_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 4780 #define CAN_F8R2_FB18 CAN_F8R2_FB18_Msk /*!<Filter bit 18 */
lypinator 0:bb348c97df44 4781 #define CAN_F8R2_FB19_Pos (19U)
lypinator 0:bb348c97df44 4782 #define CAN_F8R2_FB19_Msk (0x1U << CAN_F8R2_FB19_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 4783 #define CAN_F8R2_FB19 CAN_F8R2_FB19_Msk /*!<Filter bit 19 */
lypinator 0:bb348c97df44 4784 #define CAN_F8R2_FB20_Pos (20U)
lypinator 0:bb348c97df44 4785 #define CAN_F8R2_FB20_Msk (0x1U << CAN_F8R2_FB20_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 4786 #define CAN_F8R2_FB20 CAN_F8R2_FB20_Msk /*!<Filter bit 20 */
lypinator 0:bb348c97df44 4787 #define CAN_F8R2_FB21_Pos (21U)
lypinator 0:bb348c97df44 4788 #define CAN_F8R2_FB21_Msk (0x1U << CAN_F8R2_FB21_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 4789 #define CAN_F8R2_FB21 CAN_F8R2_FB21_Msk /*!<Filter bit 21 */
lypinator 0:bb348c97df44 4790 #define CAN_F8R2_FB22_Pos (22U)
lypinator 0:bb348c97df44 4791 #define CAN_F8R2_FB22_Msk (0x1U << CAN_F8R2_FB22_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 4792 #define CAN_F8R2_FB22 CAN_F8R2_FB22_Msk /*!<Filter bit 22 */
lypinator 0:bb348c97df44 4793 #define CAN_F8R2_FB23_Pos (23U)
lypinator 0:bb348c97df44 4794 #define CAN_F8R2_FB23_Msk (0x1U << CAN_F8R2_FB23_Pos) /*!< 0x00800000 */
lypinator 0:bb348c97df44 4795 #define CAN_F8R2_FB23 CAN_F8R2_FB23_Msk /*!<Filter bit 23 */
lypinator 0:bb348c97df44 4796 #define CAN_F8R2_FB24_Pos (24U)
lypinator 0:bb348c97df44 4797 #define CAN_F8R2_FB24_Msk (0x1U << CAN_F8R2_FB24_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 4798 #define CAN_F8R2_FB24 CAN_F8R2_FB24_Msk /*!<Filter bit 24 */
lypinator 0:bb348c97df44 4799 #define CAN_F8R2_FB25_Pos (25U)
lypinator 0:bb348c97df44 4800 #define CAN_F8R2_FB25_Msk (0x1U << CAN_F8R2_FB25_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 4801 #define CAN_F8R2_FB25 CAN_F8R2_FB25_Msk /*!<Filter bit 25 */
lypinator 0:bb348c97df44 4802 #define CAN_F8R2_FB26_Pos (26U)
lypinator 0:bb348c97df44 4803 #define CAN_F8R2_FB26_Msk (0x1U << CAN_F8R2_FB26_Pos) /*!< 0x04000000 */
lypinator 0:bb348c97df44 4804 #define CAN_F8R2_FB26 CAN_F8R2_FB26_Msk /*!<Filter bit 26 */
lypinator 0:bb348c97df44 4805 #define CAN_F8R2_FB27_Pos (27U)
lypinator 0:bb348c97df44 4806 #define CAN_F8R2_FB27_Msk (0x1U << CAN_F8R2_FB27_Pos) /*!< 0x08000000 */
lypinator 0:bb348c97df44 4807 #define CAN_F8R2_FB27 CAN_F8R2_FB27_Msk /*!<Filter bit 27 */
lypinator 0:bb348c97df44 4808 #define CAN_F8R2_FB28_Pos (28U)
lypinator 0:bb348c97df44 4809 #define CAN_F8R2_FB28_Msk (0x1U << CAN_F8R2_FB28_Pos) /*!< 0x10000000 */
lypinator 0:bb348c97df44 4810 #define CAN_F8R2_FB28 CAN_F8R2_FB28_Msk /*!<Filter bit 28 */
lypinator 0:bb348c97df44 4811 #define CAN_F8R2_FB29_Pos (29U)
lypinator 0:bb348c97df44 4812 #define CAN_F8R2_FB29_Msk (0x1U << CAN_F8R2_FB29_Pos) /*!< 0x20000000 */
lypinator 0:bb348c97df44 4813 #define CAN_F8R2_FB29 CAN_F8R2_FB29_Msk /*!<Filter bit 29 */
lypinator 0:bb348c97df44 4814 #define CAN_F8R2_FB30_Pos (30U)
lypinator 0:bb348c97df44 4815 #define CAN_F8R2_FB30_Msk (0x1U << CAN_F8R2_FB30_Pos) /*!< 0x40000000 */
lypinator 0:bb348c97df44 4816 #define CAN_F8R2_FB30 CAN_F8R2_FB30_Msk /*!<Filter bit 30 */
lypinator 0:bb348c97df44 4817 #define CAN_F8R2_FB31_Pos (31U)
lypinator 0:bb348c97df44 4818 #define CAN_F8R2_FB31_Msk (0x1U << CAN_F8R2_FB31_Pos) /*!< 0x80000000 */
lypinator 0:bb348c97df44 4819 #define CAN_F8R2_FB31 CAN_F8R2_FB31_Msk /*!<Filter bit 31 */
lypinator 0:bb348c97df44 4820
lypinator 0:bb348c97df44 4821 /******************* Bit definition for CAN_F9R2 register *******************/
lypinator 0:bb348c97df44 4822 #define CAN_F9R2_FB0_Pos (0U)
lypinator 0:bb348c97df44 4823 #define CAN_F9R2_FB0_Msk (0x1U << CAN_F9R2_FB0_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 4824 #define CAN_F9R2_FB0 CAN_F9R2_FB0_Msk /*!<Filter bit 0 */
lypinator 0:bb348c97df44 4825 #define CAN_F9R2_FB1_Pos (1U)
lypinator 0:bb348c97df44 4826 #define CAN_F9R2_FB1_Msk (0x1U << CAN_F9R2_FB1_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 4827 #define CAN_F9R2_FB1 CAN_F9R2_FB1_Msk /*!<Filter bit 1 */
lypinator 0:bb348c97df44 4828 #define CAN_F9R2_FB2_Pos (2U)
lypinator 0:bb348c97df44 4829 #define CAN_F9R2_FB2_Msk (0x1U << CAN_F9R2_FB2_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 4830 #define CAN_F9R2_FB2 CAN_F9R2_FB2_Msk /*!<Filter bit 2 */
lypinator 0:bb348c97df44 4831 #define CAN_F9R2_FB3_Pos (3U)
lypinator 0:bb348c97df44 4832 #define CAN_F9R2_FB3_Msk (0x1U << CAN_F9R2_FB3_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 4833 #define CAN_F9R2_FB3 CAN_F9R2_FB3_Msk /*!<Filter bit 3 */
lypinator 0:bb348c97df44 4834 #define CAN_F9R2_FB4_Pos (4U)
lypinator 0:bb348c97df44 4835 #define CAN_F9R2_FB4_Msk (0x1U << CAN_F9R2_FB4_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 4836 #define CAN_F9R2_FB4 CAN_F9R2_FB4_Msk /*!<Filter bit 4 */
lypinator 0:bb348c97df44 4837 #define CAN_F9R2_FB5_Pos (5U)
lypinator 0:bb348c97df44 4838 #define CAN_F9R2_FB5_Msk (0x1U << CAN_F9R2_FB5_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 4839 #define CAN_F9R2_FB5 CAN_F9R2_FB5_Msk /*!<Filter bit 5 */
lypinator 0:bb348c97df44 4840 #define CAN_F9R2_FB6_Pos (6U)
lypinator 0:bb348c97df44 4841 #define CAN_F9R2_FB6_Msk (0x1U << CAN_F9R2_FB6_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 4842 #define CAN_F9R2_FB6 CAN_F9R2_FB6_Msk /*!<Filter bit 6 */
lypinator 0:bb348c97df44 4843 #define CAN_F9R2_FB7_Pos (7U)
lypinator 0:bb348c97df44 4844 #define CAN_F9R2_FB7_Msk (0x1U << CAN_F9R2_FB7_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 4845 #define CAN_F9R2_FB7 CAN_F9R2_FB7_Msk /*!<Filter bit 7 */
lypinator 0:bb348c97df44 4846 #define CAN_F9R2_FB8_Pos (8U)
lypinator 0:bb348c97df44 4847 #define CAN_F9R2_FB8_Msk (0x1U << CAN_F9R2_FB8_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 4848 #define CAN_F9R2_FB8 CAN_F9R2_FB8_Msk /*!<Filter bit 8 */
lypinator 0:bb348c97df44 4849 #define CAN_F9R2_FB9_Pos (9U)
lypinator 0:bb348c97df44 4850 #define CAN_F9R2_FB9_Msk (0x1U << CAN_F9R2_FB9_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 4851 #define CAN_F9R2_FB9 CAN_F9R2_FB9_Msk /*!<Filter bit 9 */
lypinator 0:bb348c97df44 4852 #define CAN_F9R2_FB10_Pos (10U)
lypinator 0:bb348c97df44 4853 #define CAN_F9R2_FB10_Msk (0x1U << CAN_F9R2_FB10_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 4854 #define CAN_F9R2_FB10 CAN_F9R2_FB10_Msk /*!<Filter bit 10 */
lypinator 0:bb348c97df44 4855 #define CAN_F9R2_FB11_Pos (11U)
lypinator 0:bb348c97df44 4856 #define CAN_F9R2_FB11_Msk (0x1U << CAN_F9R2_FB11_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 4857 #define CAN_F9R2_FB11 CAN_F9R2_FB11_Msk /*!<Filter bit 11 */
lypinator 0:bb348c97df44 4858 #define CAN_F9R2_FB12_Pos (12U)
lypinator 0:bb348c97df44 4859 #define CAN_F9R2_FB12_Msk (0x1U << CAN_F9R2_FB12_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 4860 #define CAN_F9R2_FB12 CAN_F9R2_FB12_Msk /*!<Filter bit 12 */
lypinator 0:bb348c97df44 4861 #define CAN_F9R2_FB13_Pos (13U)
lypinator 0:bb348c97df44 4862 #define CAN_F9R2_FB13_Msk (0x1U << CAN_F9R2_FB13_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 4863 #define CAN_F9R2_FB13 CAN_F9R2_FB13_Msk /*!<Filter bit 13 */
lypinator 0:bb348c97df44 4864 #define CAN_F9R2_FB14_Pos (14U)
lypinator 0:bb348c97df44 4865 #define CAN_F9R2_FB14_Msk (0x1U << CAN_F9R2_FB14_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 4866 #define CAN_F9R2_FB14 CAN_F9R2_FB14_Msk /*!<Filter bit 14 */
lypinator 0:bb348c97df44 4867 #define CAN_F9R2_FB15_Pos (15U)
lypinator 0:bb348c97df44 4868 #define CAN_F9R2_FB15_Msk (0x1U << CAN_F9R2_FB15_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 4869 #define CAN_F9R2_FB15 CAN_F9R2_FB15_Msk /*!<Filter bit 15 */
lypinator 0:bb348c97df44 4870 #define CAN_F9R2_FB16_Pos (16U)
lypinator 0:bb348c97df44 4871 #define CAN_F9R2_FB16_Msk (0x1U << CAN_F9R2_FB16_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 4872 #define CAN_F9R2_FB16 CAN_F9R2_FB16_Msk /*!<Filter bit 16 */
lypinator 0:bb348c97df44 4873 #define CAN_F9R2_FB17_Pos (17U)
lypinator 0:bb348c97df44 4874 #define CAN_F9R2_FB17_Msk (0x1U << CAN_F9R2_FB17_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 4875 #define CAN_F9R2_FB17 CAN_F9R2_FB17_Msk /*!<Filter bit 17 */
lypinator 0:bb348c97df44 4876 #define CAN_F9R2_FB18_Pos (18U)
lypinator 0:bb348c97df44 4877 #define CAN_F9R2_FB18_Msk (0x1U << CAN_F9R2_FB18_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 4878 #define CAN_F9R2_FB18 CAN_F9R2_FB18_Msk /*!<Filter bit 18 */
lypinator 0:bb348c97df44 4879 #define CAN_F9R2_FB19_Pos (19U)
lypinator 0:bb348c97df44 4880 #define CAN_F9R2_FB19_Msk (0x1U << CAN_F9R2_FB19_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 4881 #define CAN_F9R2_FB19 CAN_F9R2_FB19_Msk /*!<Filter bit 19 */
lypinator 0:bb348c97df44 4882 #define CAN_F9R2_FB20_Pos (20U)
lypinator 0:bb348c97df44 4883 #define CAN_F9R2_FB20_Msk (0x1U << CAN_F9R2_FB20_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 4884 #define CAN_F9R2_FB20 CAN_F9R2_FB20_Msk /*!<Filter bit 20 */
lypinator 0:bb348c97df44 4885 #define CAN_F9R2_FB21_Pos (21U)
lypinator 0:bb348c97df44 4886 #define CAN_F9R2_FB21_Msk (0x1U << CAN_F9R2_FB21_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 4887 #define CAN_F9R2_FB21 CAN_F9R2_FB21_Msk /*!<Filter bit 21 */
lypinator 0:bb348c97df44 4888 #define CAN_F9R2_FB22_Pos (22U)
lypinator 0:bb348c97df44 4889 #define CAN_F9R2_FB22_Msk (0x1U << CAN_F9R2_FB22_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 4890 #define CAN_F9R2_FB22 CAN_F9R2_FB22_Msk /*!<Filter bit 22 */
lypinator 0:bb348c97df44 4891 #define CAN_F9R2_FB23_Pos (23U)
lypinator 0:bb348c97df44 4892 #define CAN_F9R2_FB23_Msk (0x1U << CAN_F9R2_FB23_Pos) /*!< 0x00800000 */
lypinator 0:bb348c97df44 4893 #define CAN_F9R2_FB23 CAN_F9R2_FB23_Msk /*!<Filter bit 23 */
lypinator 0:bb348c97df44 4894 #define CAN_F9R2_FB24_Pos (24U)
lypinator 0:bb348c97df44 4895 #define CAN_F9R2_FB24_Msk (0x1U << CAN_F9R2_FB24_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 4896 #define CAN_F9R2_FB24 CAN_F9R2_FB24_Msk /*!<Filter bit 24 */
lypinator 0:bb348c97df44 4897 #define CAN_F9R2_FB25_Pos (25U)
lypinator 0:bb348c97df44 4898 #define CAN_F9R2_FB25_Msk (0x1U << CAN_F9R2_FB25_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 4899 #define CAN_F9R2_FB25 CAN_F9R2_FB25_Msk /*!<Filter bit 25 */
lypinator 0:bb348c97df44 4900 #define CAN_F9R2_FB26_Pos (26U)
lypinator 0:bb348c97df44 4901 #define CAN_F9R2_FB26_Msk (0x1U << CAN_F9R2_FB26_Pos) /*!< 0x04000000 */
lypinator 0:bb348c97df44 4902 #define CAN_F9R2_FB26 CAN_F9R2_FB26_Msk /*!<Filter bit 26 */
lypinator 0:bb348c97df44 4903 #define CAN_F9R2_FB27_Pos (27U)
lypinator 0:bb348c97df44 4904 #define CAN_F9R2_FB27_Msk (0x1U << CAN_F9R2_FB27_Pos) /*!< 0x08000000 */
lypinator 0:bb348c97df44 4905 #define CAN_F9R2_FB27 CAN_F9R2_FB27_Msk /*!<Filter bit 27 */
lypinator 0:bb348c97df44 4906 #define CAN_F9R2_FB28_Pos (28U)
lypinator 0:bb348c97df44 4907 #define CAN_F9R2_FB28_Msk (0x1U << CAN_F9R2_FB28_Pos) /*!< 0x10000000 */
lypinator 0:bb348c97df44 4908 #define CAN_F9R2_FB28 CAN_F9R2_FB28_Msk /*!<Filter bit 28 */
lypinator 0:bb348c97df44 4909 #define CAN_F9R2_FB29_Pos (29U)
lypinator 0:bb348c97df44 4910 #define CAN_F9R2_FB29_Msk (0x1U << CAN_F9R2_FB29_Pos) /*!< 0x20000000 */
lypinator 0:bb348c97df44 4911 #define CAN_F9R2_FB29 CAN_F9R2_FB29_Msk /*!<Filter bit 29 */
lypinator 0:bb348c97df44 4912 #define CAN_F9R2_FB30_Pos (30U)
lypinator 0:bb348c97df44 4913 #define CAN_F9R2_FB30_Msk (0x1U << CAN_F9R2_FB30_Pos) /*!< 0x40000000 */
lypinator 0:bb348c97df44 4914 #define CAN_F9R2_FB30 CAN_F9R2_FB30_Msk /*!<Filter bit 30 */
lypinator 0:bb348c97df44 4915 #define CAN_F9R2_FB31_Pos (31U)
lypinator 0:bb348c97df44 4916 #define CAN_F9R2_FB31_Msk (0x1U << CAN_F9R2_FB31_Pos) /*!< 0x80000000 */
lypinator 0:bb348c97df44 4917 #define CAN_F9R2_FB31 CAN_F9R2_FB31_Msk /*!<Filter bit 31 */
lypinator 0:bb348c97df44 4918
lypinator 0:bb348c97df44 4919 /******************* Bit definition for CAN_F10R2 register ******************/
lypinator 0:bb348c97df44 4920 #define CAN_F10R2_FB0_Pos (0U)
lypinator 0:bb348c97df44 4921 #define CAN_F10R2_FB0_Msk (0x1U << CAN_F10R2_FB0_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 4922 #define CAN_F10R2_FB0 CAN_F10R2_FB0_Msk /*!<Filter bit 0 */
lypinator 0:bb348c97df44 4923 #define CAN_F10R2_FB1_Pos (1U)
lypinator 0:bb348c97df44 4924 #define CAN_F10R2_FB1_Msk (0x1U << CAN_F10R2_FB1_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 4925 #define CAN_F10R2_FB1 CAN_F10R2_FB1_Msk /*!<Filter bit 1 */
lypinator 0:bb348c97df44 4926 #define CAN_F10R2_FB2_Pos (2U)
lypinator 0:bb348c97df44 4927 #define CAN_F10R2_FB2_Msk (0x1U << CAN_F10R2_FB2_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 4928 #define CAN_F10R2_FB2 CAN_F10R2_FB2_Msk /*!<Filter bit 2 */
lypinator 0:bb348c97df44 4929 #define CAN_F10R2_FB3_Pos (3U)
lypinator 0:bb348c97df44 4930 #define CAN_F10R2_FB3_Msk (0x1U << CAN_F10R2_FB3_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 4931 #define CAN_F10R2_FB3 CAN_F10R2_FB3_Msk /*!<Filter bit 3 */
lypinator 0:bb348c97df44 4932 #define CAN_F10R2_FB4_Pos (4U)
lypinator 0:bb348c97df44 4933 #define CAN_F10R2_FB4_Msk (0x1U << CAN_F10R2_FB4_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 4934 #define CAN_F10R2_FB4 CAN_F10R2_FB4_Msk /*!<Filter bit 4 */
lypinator 0:bb348c97df44 4935 #define CAN_F10R2_FB5_Pos (5U)
lypinator 0:bb348c97df44 4936 #define CAN_F10R2_FB5_Msk (0x1U << CAN_F10R2_FB5_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 4937 #define CAN_F10R2_FB5 CAN_F10R2_FB5_Msk /*!<Filter bit 5 */
lypinator 0:bb348c97df44 4938 #define CAN_F10R2_FB6_Pos (6U)
lypinator 0:bb348c97df44 4939 #define CAN_F10R2_FB6_Msk (0x1U << CAN_F10R2_FB6_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 4940 #define CAN_F10R2_FB6 CAN_F10R2_FB6_Msk /*!<Filter bit 6 */
lypinator 0:bb348c97df44 4941 #define CAN_F10R2_FB7_Pos (7U)
lypinator 0:bb348c97df44 4942 #define CAN_F10R2_FB7_Msk (0x1U << CAN_F10R2_FB7_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 4943 #define CAN_F10R2_FB7 CAN_F10R2_FB7_Msk /*!<Filter bit 7 */
lypinator 0:bb348c97df44 4944 #define CAN_F10R2_FB8_Pos (8U)
lypinator 0:bb348c97df44 4945 #define CAN_F10R2_FB8_Msk (0x1U << CAN_F10R2_FB8_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 4946 #define CAN_F10R2_FB8 CAN_F10R2_FB8_Msk /*!<Filter bit 8 */
lypinator 0:bb348c97df44 4947 #define CAN_F10R2_FB9_Pos (9U)
lypinator 0:bb348c97df44 4948 #define CAN_F10R2_FB9_Msk (0x1U << CAN_F10R2_FB9_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 4949 #define CAN_F10R2_FB9 CAN_F10R2_FB9_Msk /*!<Filter bit 9 */
lypinator 0:bb348c97df44 4950 /*
lypinator 0:bb348c97df44 4951 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
lypinator 0:bb348c97df44 4952 */
lypinator 0:bb348c97df44 4953 #define QSPI1_V2_1L /*!< QSPI Virtual Version */
lypinator 0:bb348c97df44 4954
lypinator 0:bb348c97df44 4955 #define CAN_F10R2_FB10_Pos (10U)
lypinator 0:bb348c97df44 4956 #define CAN_F10R2_FB10_Msk (0x1U << CAN_F10R2_FB10_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 4957 #define CAN_F10R2_FB10 CAN_F10R2_FB10_Msk /*!<Filter bit 10 */
lypinator 0:bb348c97df44 4958 #define CAN_F10R2_FB11_Pos (11U)
lypinator 0:bb348c97df44 4959 #define CAN_F10R2_FB11_Msk (0x1U << CAN_F10R2_FB11_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 4960 #define CAN_F10R2_FB11 CAN_F10R2_FB11_Msk /*!<Filter bit 11 */
lypinator 0:bb348c97df44 4961 #define CAN_F10R2_FB12_Pos (12U)
lypinator 0:bb348c97df44 4962 #define CAN_F10R2_FB12_Msk (0x1U << CAN_F10R2_FB12_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 4963 #define CAN_F10R2_FB12 CAN_F10R2_FB12_Msk /*!<Filter bit 12 */
lypinator 0:bb348c97df44 4964 #define CAN_F10R2_FB13_Pos (13U)
lypinator 0:bb348c97df44 4965 #define CAN_F10R2_FB13_Msk (0x1U << CAN_F10R2_FB13_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 4966 #define CAN_F10R2_FB13 CAN_F10R2_FB13_Msk /*!<Filter bit 13 */
lypinator 0:bb348c97df44 4967 #define CAN_F10R2_FB14_Pos (14U)
lypinator 0:bb348c97df44 4968 #define CAN_F10R2_FB14_Msk (0x1U << CAN_F10R2_FB14_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 4969 #define CAN_F10R2_FB14 CAN_F10R2_FB14_Msk /*!<Filter bit 14 */
lypinator 0:bb348c97df44 4970 #define CAN_F10R2_FB15_Pos (15U)
lypinator 0:bb348c97df44 4971 #define CAN_F10R2_FB15_Msk (0x1U << CAN_F10R2_FB15_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 4972 #define CAN_F10R2_FB15 CAN_F10R2_FB15_Msk /*!<Filter bit 15 */
lypinator 0:bb348c97df44 4973 #define CAN_F10R2_FB16_Pos (16U)
lypinator 0:bb348c97df44 4974 #define CAN_F10R2_FB16_Msk (0x1U << CAN_F10R2_FB16_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 4975 #define CAN_F10R2_FB16 CAN_F10R2_FB16_Msk /*!<Filter bit 16 */
lypinator 0:bb348c97df44 4976 #define CAN_F10R2_FB17_Pos (17U)
lypinator 0:bb348c97df44 4977 #define CAN_F10R2_FB17_Msk (0x1U << CAN_F10R2_FB17_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 4978 #define CAN_F10R2_FB17 CAN_F10R2_FB17_Msk /*!<Filter bit 17 */
lypinator 0:bb348c97df44 4979 #define CAN_F10R2_FB18_Pos (18U)
lypinator 0:bb348c97df44 4980 #define CAN_F10R2_FB18_Msk (0x1U << CAN_F10R2_FB18_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 4981 #define CAN_F10R2_FB18 CAN_F10R2_FB18_Msk /*!<Filter bit 18 */
lypinator 0:bb348c97df44 4982 #define CAN_F10R2_FB19_Pos (19U)
lypinator 0:bb348c97df44 4983 #define CAN_F10R2_FB19_Msk (0x1U << CAN_F10R2_FB19_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 4984 #define CAN_F10R2_FB19 CAN_F10R2_FB19_Msk /*!<Filter bit 19 */
lypinator 0:bb348c97df44 4985 #define CAN_F10R2_FB20_Pos (20U)
lypinator 0:bb348c97df44 4986 #define CAN_F10R2_FB20_Msk (0x1U << CAN_F10R2_FB20_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 4987 #define CAN_F10R2_FB20 CAN_F10R2_FB20_Msk /*!<Filter bit 20 */
lypinator 0:bb348c97df44 4988 #define CAN_F10R2_FB21_Pos (21U)
lypinator 0:bb348c97df44 4989 #define CAN_F10R2_FB21_Msk (0x1U << CAN_F10R2_FB21_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 4990 #define CAN_F10R2_FB21 CAN_F10R2_FB21_Msk /*!<Filter bit 21 */
lypinator 0:bb348c97df44 4991 #define CAN_F10R2_FB22_Pos (22U)
lypinator 0:bb348c97df44 4992 #define CAN_F10R2_FB22_Msk (0x1U << CAN_F10R2_FB22_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 4993 #define CAN_F10R2_FB22 CAN_F10R2_FB22_Msk /*!<Filter bit 22 */
lypinator 0:bb348c97df44 4994 #define CAN_F10R2_FB23_Pos (23U)
lypinator 0:bb348c97df44 4995 #define CAN_F10R2_FB23_Msk (0x1U << CAN_F10R2_FB23_Pos) /*!< 0x00800000 */
lypinator 0:bb348c97df44 4996 #define CAN_F10R2_FB23 CAN_F10R2_FB23_Msk /*!<Filter bit 23 */
lypinator 0:bb348c97df44 4997 #define CAN_F10R2_FB24_Pos (24U)
lypinator 0:bb348c97df44 4998 #define CAN_F10R2_FB24_Msk (0x1U << CAN_F10R2_FB24_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 4999 #define CAN_F10R2_FB24 CAN_F10R2_FB24_Msk /*!<Filter bit 24 */
lypinator 0:bb348c97df44 5000 #define CAN_F10R2_FB25_Pos (25U)
lypinator 0:bb348c97df44 5001 #define CAN_F10R2_FB25_Msk (0x1U << CAN_F10R2_FB25_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 5002 #define CAN_F10R2_FB25 CAN_F10R2_FB25_Msk /*!<Filter bit 25 */
lypinator 0:bb348c97df44 5003 #define CAN_F10R2_FB26_Pos (26U)
lypinator 0:bb348c97df44 5004 #define CAN_F10R2_FB26_Msk (0x1U << CAN_F10R2_FB26_Pos) /*!< 0x04000000 */
lypinator 0:bb348c97df44 5005 #define CAN_F10R2_FB26 CAN_F10R2_FB26_Msk /*!<Filter bit 26 */
lypinator 0:bb348c97df44 5006 #define CAN_F10R2_FB27_Pos (27U)
lypinator 0:bb348c97df44 5007 #define CAN_F10R2_FB27_Msk (0x1U << CAN_F10R2_FB27_Pos) /*!< 0x08000000 */
lypinator 0:bb348c97df44 5008 #define CAN_F10R2_FB27 CAN_F10R2_FB27_Msk /*!<Filter bit 27 */
lypinator 0:bb348c97df44 5009 #define CAN_F10R2_FB28_Pos (28U)
lypinator 0:bb348c97df44 5010 #define CAN_F10R2_FB28_Msk (0x1U << CAN_F10R2_FB28_Pos) /*!< 0x10000000 */
lypinator 0:bb348c97df44 5011 #define CAN_F10R2_FB28 CAN_F10R2_FB28_Msk /*!<Filter bit 28 */
lypinator 0:bb348c97df44 5012 #define CAN_F10R2_FB29_Pos (29U)
lypinator 0:bb348c97df44 5013 #define CAN_F10R2_FB29_Msk (0x1U << CAN_F10R2_FB29_Pos) /*!< 0x20000000 */
lypinator 0:bb348c97df44 5014 #define CAN_F10R2_FB29 CAN_F10R2_FB29_Msk /*!<Filter bit 29 */
lypinator 0:bb348c97df44 5015 #define CAN_F10R2_FB30_Pos (30U)
lypinator 0:bb348c97df44 5016 #define CAN_F10R2_FB30_Msk (0x1U << CAN_F10R2_FB30_Pos) /*!< 0x40000000 */
lypinator 0:bb348c97df44 5017 #define CAN_F10R2_FB30 CAN_F10R2_FB30_Msk /*!<Filter bit 30 */
lypinator 0:bb348c97df44 5018 #define CAN_F10R2_FB31_Pos (31U)
lypinator 0:bb348c97df44 5019 #define CAN_F10R2_FB31_Msk (0x1U << CAN_F10R2_FB31_Pos) /*!< 0x80000000 */
lypinator 0:bb348c97df44 5020 #define CAN_F10R2_FB31 CAN_F10R2_FB31_Msk /*!<Filter bit 31 */
lypinator 0:bb348c97df44 5021
lypinator 0:bb348c97df44 5022 /******************* Bit definition for CAN_F11R2 register ******************/
lypinator 0:bb348c97df44 5023 #define CAN_F11R2_FB0_Pos (0U)
lypinator 0:bb348c97df44 5024 #define CAN_F11R2_FB0_Msk (0x1U << CAN_F11R2_FB0_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 5025 #define CAN_F11R2_FB0 CAN_F11R2_FB0_Msk /*!<Filter bit 0 */
lypinator 0:bb348c97df44 5026 #define CAN_F11R2_FB1_Pos (1U)
lypinator 0:bb348c97df44 5027 #define CAN_F11R2_FB1_Msk (0x1U << CAN_F11R2_FB1_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 5028 #define CAN_F11R2_FB1 CAN_F11R2_FB1_Msk /*!<Filter bit 1 */
lypinator 0:bb348c97df44 5029 #define CAN_F11R2_FB2_Pos (2U)
lypinator 0:bb348c97df44 5030 #define CAN_F11R2_FB2_Msk (0x1U << CAN_F11R2_FB2_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 5031 #define CAN_F11R2_FB2 CAN_F11R2_FB2_Msk /*!<Filter bit 2 */
lypinator 0:bb348c97df44 5032 #define CAN_F11R2_FB3_Pos (3U)
lypinator 0:bb348c97df44 5033 #define CAN_F11R2_FB3_Msk (0x1U << CAN_F11R2_FB3_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 5034 #define CAN_F11R2_FB3 CAN_F11R2_FB3_Msk /*!<Filter bit 3 */
lypinator 0:bb348c97df44 5035 #define CAN_F11R2_FB4_Pos (4U)
lypinator 0:bb348c97df44 5036 #define CAN_F11R2_FB4_Msk (0x1U << CAN_F11R2_FB4_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 5037 #define CAN_F11R2_FB4 CAN_F11R2_FB4_Msk /*!<Filter bit 4 */
lypinator 0:bb348c97df44 5038 #define CAN_F11R2_FB5_Pos (5U)
lypinator 0:bb348c97df44 5039 #define CAN_F11R2_FB5_Msk (0x1U << CAN_F11R2_FB5_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 5040 #define CAN_F11R2_FB5 CAN_F11R2_FB5_Msk /*!<Filter bit 5 */
lypinator 0:bb348c97df44 5041 #define CAN_F11R2_FB6_Pos (6U)
lypinator 0:bb348c97df44 5042 #define CAN_F11R2_FB6_Msk (0x1U << CAN_F11R2_FB6_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 5043 #define CAN_F11R2_FB6 CAN_F11R2_FB6_Msk /*!<Filter bit 6 */
lypinator 0:bb348c97df44 5044 #define CAN_F11R2_FB7_Pos (7U)
lypinator 0:bb348c97df44 5045 #define CAN_F11R2_FB7_Msk (0x1U << CAN_F11R2_FB7_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 5046 #define CAN_F11R2_FB7 CAN_F11R2_FB7_Msk /*!<Filter bit 7 */
lypinator 0:bb348c97df44 5047 #define CAN_F11R2_FB8_Pos (8U)
lypinator 0:bb348c97df44 5048 #define CAN_F11R2_FB8_Msk (0x1U << CAN_F11R2_FB8_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 5049 #define CAN_F11R2_FB8 CAN_F11R2_FB8_Msk /*!<Filter bit 8 */
lypinator 0:bb348c97df44 5050 #define CAN_F11R2_FB9_Pos (9U)
lypinator 0:bb348c97df44 5051 #define CAN_F11R2_FB9_Msk (0x1U << CAN_F11R2_FB9_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 5052 #define CAN_F11R2_FB9 CAN_F11R2_FB9_Msk /*!<Filter bit 9 */
lypinator 0:bb348c97df44 5053 #define CAN_F11R2_FB10_Pos (10U)
lypinator 0:bb348c97df44 5054 #define CAN_F11R2_FB10_Msk (0x1U << CAN_F11R2_FB10_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 5055 #define CAN_F11R2_FB10 CAN_F11R2_FB10_Msk /*!<Filter bit 10 */
lypinator 0:bb348c97df44 5056 #define CAN_F11R2_FB11_Pos (11U)
lypinator 0:bb348c97df44 5057 #define CAN_F11R2_FB11_Msk (0x1U << CAN_F11R2_FB11_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 5058 #define CAN_F11R2_FB11 CAN_F11R2_FB11_Msk /*!<Filter bit 11 */
lypinator 0:bb348c97df44 5059 #define CAN_F11R2_FB12_Pos (12U)
lypinator 0:bb348c97df44 5060 #define CAN_F11R2_FB12_Msk (0x1U << CAN_F11R2_FB12_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 5061 #define CAN_F11R2_FB12 CAN_F11R2_FB12_Msk /*!<Filter bit 12 */
lypinator 0:bb348c97df44 5062 #define CAN_F11R2_FB13_Pos (13U)
lypinator 0:bb348c97df44 5063 #define CAN_F11R2_FB13_Msk (0x1U << CAN_F11R2_FB13_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 5064 #define CAN_F11R2_FB13 CAN_F11R2_FB13_Msk /*!<Filter bit 13 */
lypinator 0:bb348c97df44 5065 #define CAN_F11R2_FB14_Pos (14U)
lypinator 0:bb348c97df44 5066 #define CAN_F11R2_FB14_Msk (0x1U << CAN_F11R2_FB14_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 5067 #define CAN_F11R2_FB14 CAN_F11R2_FB14_Msk /*!<Filter bit 14 */
lypinator 0:bb348c97df44 5068 #define CAN_F11R2_FB15_Pos (15U)
lypinator 0:bb348c97df44 5069 #define CAN_F11R2_FB15_Msk (0x1U << CAN_F11R2_FB15_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 5070 #define CAN_F11R2_FB15 CAN_F11R2_FB15_Msk /*!<Filter bit 15 */
lypinator 0:bb348c97df44 5071 #define CAN_F11R2_FB16_Pos (16U)
lypinator 0:bb348c97df44 5072 #define CAN_F11R2_FB16_Msk (0x1U << CAN_F11R2_FB16_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 5073 #define CAN_F11R2_FB16 CAN_F11R2_FB16_Msk /*!<Filter bit 16 */
lypinator 0:bb348c97df44 5074 #define CAN_F11R2_FB17_Pos (17U)
lypinator 0:bb348c97df44 5075 #define CAN_F11R2_FB17_Msk (0x1U << CAN_F11R2_FB17_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 5076 #define CAN_F11R2_FB17 CAN_F11R2_FB17_Msk /*!<Filter bit 17 */
lypinator 0:bb348c97df44 5077 #define CAN_F11R2_FB18_Pos (18U)
lypinator 0:bb348c97df44 5078 #define CAN_F11R2_FB18_Msk (0x1U << CAN_F11R2_FB18_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 5079 #define CAN_F11R2_FB18 CAN_F11R2_FB18_Msk /*!<Filter bit 18 */
lypinator 0:bb348c97df44 5080 #define CAN_F11R2_FB19_Pos (19U)
lypinator 0:bb348c97df44 5081 #define CAN_F11R2_FB19_Msk (0x1U << CAN_F11R2_FB19_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 5082 #define CAN_F11R2_FB19 CAN_F11R2_FB19_Msk /*!<Filter bit 19 */
lypinator 0:bb348c97df44 5083 #define CAN_F11R2_FB20_Pos (20U)
lypinator 0:bb348c97df44 5084 #define CAN_F11R2_FB20_Msk (0x1U << CAN_F11R2_FB20_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 5085 #define CAN_F11R2_FB20 CAN_F11R2_FB20_Msk /*!<Filter bit 20 */
lypinator 0:bb348c97df44 5086 #define CAN_F11R2_FB21_Pos (21U)
lypinator 0:bb348c97df44 5087 #define CAN_F11R2_FB21_Msk (0x1U << CAN_F11R2_FB21_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 5088 #define CAN_F11R2_FB21 CAN_F11R2_FB21_Msk /*!<Filter bit 21 */
lypinator 0:bb348c97df44 5089 #define CAN_F11R2_FB22_Pos (22U)
lypinator 0:bb348c97df44 5090 #define CAN_F11R2_FB22_Msk (0x1U << CAN_F11R2_FB22_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 5091 #define CAN_F11R2_FB22 CAN_F11R2_FB22_Msk /*!<Filter bit 22 */
lypinator 0:bb348c97df44 5092 #define CAN_F11R2_FB23_Pos (23U)
lypinator 0:bb348c97df44 5093 #define CAN_F11R2_FB23_Msk (0x1U << CAN_F11R2_FB23_Pos) /*!< 0x00800000 */
lypinator 0:bb348c97df44 5094 #define CAN_F11R2_FB23 CAN_F11R2_FB23_Msk /*!<Filter bit 23 */
lypinator 0:bb348c97df44 5095 #define CAN_F11R2_FB24_Pos (24U)
lypinator 0:bb348c97df44 5096 #define CAN_F11R2_FB24_Msk (0x1U << CAN_F11R2_FB24_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 5097 #define CAN_F11R2_FB24 CAN_F11R2_FB24_Msk /*!<Filter bit 24 */
lypinator 0:bb348c97df44 5098 #define CAN_F11R2_FB25_Pos (25U)
lypinator 0:bb348c97df44 5099 #define CAN_F11R2_FB25_Msk (0x1U << CAN_F11R2_FB25_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 5100 #define CAN_F11R2_FB25 CAN_F11R2_FB25_Msk /*!<Filter bit 25 */
lypinator 0:bb348c97df44 5101 #define CAN_F11R2_FB26_Pos (26U)
lypinator 0:bb348c97df44 5102 #define CAN_F11R2_FB26_Msk (0x1U << CAN_F11R2_FB26_Pos) /*!< 0x04000000 */
lypinator 0:bb348c97df44 5103 #define CAN_F11R2_FB26 CAN_F11R2_FB26_Msk /*!<Filter bit 26 */
lypinator 0:bb348c97df44 5104 #define CAN_F11R2_FB27_Pos (27U)
lypinator 0:bb348c97df44 5105 #define CAN_F11R2_FB27_Msk (0x1U << CAN_F11R2_FB27_Pos) /*!< 0x08000000 */
lypinator 0:bb348c97df44 5106 #define CAN_F11R2_FB27 CAN_F11R2_FB27_Msk /*!<Filter bit 27 */
lypinator 0:bb348c97df44 5107 #define CAN_F11R2_FB28_Pos (28U)
lypinator 0:bb348c97df44 5108 #define CAN_F11R2_FB28_Msk (0x1U << CAN_F11R2_FB28_Pos) /*!< 0x10000000 */
lypinator 0:bb348c97df44 5109 #define CAN_F11R2_FB28 CAN_F11R2_FB28_Msk /*!<Filter bit 28 */
lypinator 0:bb348c97df44 5110 #define CAN_F11R2_FB29_Pos (29U)
lypinator 0:bb348c97df44 5111 #define CAN_F11R2_FB29_Msk (0x1U << CAN_F11R2_FB29_Pos) /*!< 0x20000000 */
lypinator 0:bb348c97df44 5112 #define CAN_F11R2_FB29 CAN_F11R2_FB29_Msk /*!<Filter bit 29 */
lypinator 0:bb348c97df44 5113 #define CAN_F11R2_FB30_Pos (30U)
lypinator 0:bb348c97df44 5114 #define CAN_F11R2_FB30_Msk (0x1U << CAN_F11R2_FB30_Pos) /*!< 0x40000000 */
lypinator 0:bb348c97df44 5115 #define CAN_F11R2_FB30 CAN_F11R2_FB30_Msk /*!<Filter bit 30 */
lypinator 0:bb348c97df44 5116 #define CAN_F11R2_FB31_Pos (31U)
lypinator 0:bb348c97df44 5117 #define CAN_F11R2_FB31_Msk (0x1U << CAN_F11R2_FB31_Pos) /*!< 0x80000000 */
lypinator 0:bb348c97df44 5118 #define CAN_F11R2_FB31 CAN_F11R2_FB31_Msk /*!<Filter bit 31 */
lypinator 0:bb348c97df44 5119
lypinator 0:bb348c97df44 5120 /******************* Bit definition for CAN_F12R2 register ******************/
lypinator 0:bb348c97df44 5121 #define CAN_F12R2_FB0_Pos (0U)
lypinator 0:bb348c97df44 5122 #define CAN_F12R2_FB0_Msk (0x1U << CAN_F12R2_FB0_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 5123 #define CAN_F12R2_FB0 CAN_F12R2_FB0_Msk /*!<Filter bit 0 */
lypinator 0:bb348c97df44 5124 #define CAN_F12R2_FB1_Pos (1U)
lypinator 0:bb348c97df44 5125 #define CAN_F12R2_FB1_Msk (0x1U << CAN_F12R2_FB1_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 5126 #define CAN_F12R2_FB1 CAN_F12R2_FB1_Msk /*!<Filter bit 1 */
lypinator 0:bb348c97df44 5127 #define CAN_F12R2_FB2_Pos (2U)
lypinator 0:bb348c97df44 5128 #define CAN_F12R2_FB2_Msk (0x1U << CAN_F12R2_FB2_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 5129 #define CAN_F12R2_FB2 CAN_F12R2_FB2_Msk /*!<Filter bit 2 */
lypinator 0:bb348c97df44 5130 #define CAN_F12R2_FB3_Pos (3U)
lypinator 0:bb348c97df44 5131 #define CAN_F12R2_FB3_Msk (0x1U << CAN_F12R2_FB3_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 5132 #define CAN_F12R2_FB3 CAN_F12R2_FB3_Msk /*!<Filter bit 3 */
lypinator 0:bb348c97df44 5133 #define CAN_F12R2_FB4_Pos (4U)
lypinator 0:bb348c97df44 5134 #define CAN_F12R2_FB4_Msk (0x1U << CAN_F12R2_FB4_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 5135 #define CAN_F12R2_FB4 CAN_F12R2_FB4_Msk /*!<Filter bit 4 */
lypinator 0:bb348c97df44 5136 #define CAN_F12R2_FB5_Pos (5U)
lypinator 0:bb348c97df44 5137 #define CAN_F12R2_FB5_Msk (0x1U << CAN_F12R2_FB5_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 5138 #define CAN_F12R2_FB5 CAN_F12R2_FB5_Msk /*!<Filter bit 5 */
lypinator 0:bb348c97df44 5139 #define CAN_F12R2_FB6_Pos (6U)
lypinator 0:bb348c97df44 5140 #define CAN_F12R2_FB6_Msk (0x1U << CAN_F12R2_FB6_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 5141 #define CAN_F12R2_FB6 CAN_F12R2_FB6_Msk /*!<Filter bit 6 */
lypinator 0:bb348c97df44 5142 #define CAN_F12R2_FB7_Pos (7U)
lypinator 0:bb348c97df44 5143 #define CAN_F12R2_FB7_Msk (0x1U << CAN_F12R2_FB7_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 5144 #define CAN_F12R2_FB7 CAN_F12R2_FB7_Msk /*!<Filter bit 7 */
lypinator 0:bb348c97df44 5145 #define CAN_F12R2_FB8_Pos (8U)
lypinator 0:bb348c97df44 5146 #define CAN_F12R2_FB8_Msk (0x1U << CAN_F12R2_FB8_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 5147 #define CAN_F12R2_FB8 CAN_F12R2_FB8_Msk /*!<Filter bit 8 */
lypinator 0:bb348c97df44 5148 #define CAN_F12R2_FB9_Pos (9U)
lypinator 0:bb348c97df44 5149 #define CAN_F12R2_FB9_Msk (0x1U << CAN_F12R2_FB9_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 5150 #define CAN_F12R2_FB9 CAN_F12R2_FB9_Msk /*!<Filter bit 9 */
lypinator 0:bb348c97df44 5151 #define CAN_F12R2_FB10_Pos (10U)
lypinator 0:bb348c97df44 5152 #define CAN_F12R2_FB10_Msk (0x1U << CAN_F12R2_FB10_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 5153 #define CAN_F12R2_FB10 CAN_F12R2_FB10_Msk /*!<Filter bit 10 */
lypinator 0:bb348c97df44 5154 #define CAN_F12R2_FB11_Pos (11U)
lypinator 0:bb348c97df44 5155 #define CAN_F12R2_FB11_Msk (0x1U << CAN_F12R2_FB11_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 5156 #define CAN_F12R2_FB11 CAN_F12R2_FB11_Msk /*!<Filter bit 11 */
lypinator 0:bb348c97df44 5157 #define CAN_F12R2_FB12_Pos (12U)
lypinator 0:bb348c97df44 5158 #define CAN_F12R2_FB12_Msk (0x1U << CAN_F12R2_FB12_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 5159 #define CAN_F12R2_FB12 CAN_F12R2_FB12_Msk /*!<Filter bit 12 */
lypinator 0:bb348c97df44 5160 #define CAN_F12R2_FB13_Pos (13U)
lypinator 0:bb348c97df44 5161 #define CAN_F12R2_FB13_Msk (0x1U << CAN_F12R2_FB13_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 5162 #define CAN_F12R2_FB13 CAN_F12R2_FB13_Msk /*!<Filter bit 13 */
lypinator 0:bb348c97df44 5163 #define CAN_F12R2_FB14_Pos (14U)
lypinator 0:bb348c97df44 5164 #define CAN_F12R2_FB14_Msk (0x1U << CAN_F12R2_FB14_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 5165 #define CAN_F12R2_FB14 CAN_F12R2_FB14_Msk /*!<Filter bit 14 */
lypinator 0:bb348c97df44 5166 #define CAN_F12R2_FB15_Pos (15U)
lypinator 0:bb348c97df44 5167 #define CAN_F12R2_FB15_Msk (0x1U << CAN_F12R2_FB15_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 5168 #define CAN_F12R2_FB15 CAN_F12R2_FB15_Msk /*!<Filter bit 15 */
lypinator 0:bb348c97df44 5169 #define CAN_F12R2_FB16_Pos (16U)
lypinator 0:bb348c97df44 5170 #define CAN_F12R2_FB16_Msk (0x1U << CAN_F12R2_FB16_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 5171 #define CAN_F12R2_FB16 CAN_F12R2_FB16_Msk /*!<Filter bit 16 */
lypinator 0:bb348c97df44 5172 #define CAN_F12R2_FB17_Pos (17U)
lypinator 0:bb348c97df44 5173 #define CAN_F12R2_FB17_Msk (0x1U << CAN_F12R2_FB17_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 5174 #define CAN_F12R2_FB17 CAN_F12R2_FB17_Msk /*!<Filter bit 17 */
lypinator 0:bb348c97df44 5175 #define CAN_F12R2_FB18_Pos (18U)
lypinator 0:bb348c97df44 5176 #define CAN_F12R2_FB18_Msk (0x1U << CAN_F12R2_FB18_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 5177 #define CAN_F12R2_FB18 CAN_F12R2_FB18_Msk /*!<Filter bit 18 */
lypinator 0:bb348c97df44 5178 #define CAN_F12R2_FB19_Pos (19U)
lypinator 0:bb348c97df44 5179 #define CAN_F12R2_FB19_Msk (0x1U << CAN_F12R2_FB19_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 5180 #define CAN_F12R2_FB19 CAN_F12R2_FB19_Msk /*!<Filter bit 19 */
lypinator 0:bb348c97df44 5181 #define CAN_F12R2_FB20_Pos (20U)
lypinator 0:bb348c97df44 5182 #define CAN_F12R2_FB20_Msk (0x1U << CAN_F12R2_FB20_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 5183 #define CAN_F12R2_FB20 CAN_F12R2_FB20_Msk /*!<Filter bit 20 */
lypinator 0:bb348c97df44 5184 #define CAN_F12R2_FB21_Pos (21U)
lypinator 0:bb348c97df44 5185 #define CAN_F12R2_FB21_Msk (0x1U << CAN_F12R2_FB21_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 5186 #define CAN_F12R2_FB21 CAN_F12R2_FB21_Msk /*!<Filter bit 21 */
lypinator 0:bb348c97df44 5187 #define CAN_F12R2_FB22_Pos (22U)
lypinator 0:bb348c97df44 5188 #define CAN_F12R2_FB22_Msk (0x1U << CAN_F12R2_FB22_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 5189 #define CAN_F12R2_FB22 CAN_F12R2_FB22_Msk /*!<Filter bit 22 */
lypinator 0:bb348c97df44 5190 #define CAN_F12R2_FB23_Pos (23U)
lypinator 0:bb348c97df44 5191 #define CAN_F12R2_FB23_Msk (0x1U << CAN_F12R2_FB23_Pos) /*!< 0x00800000 */
lypinator 0:bb348c97df44 5192 #define CAN_F12R2_FB23 CAN_F12R2_FB23_Msk /*!<Filter bit 23 */
lypinator 0:bb348c97df44 5193 #define CAN_F12R2_FB24_Pos (24U)
lypinator 0:bb348c97df44 5194 #define CAN_F12R2_FB24_Msk (0x1U << CAN_F12R2_FB24_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 5195 #define CAN_F12R2_FB24 CAN_F12R2_FB24_Msk /*!<Filter bit 24 */
lypinator 0:bb348c97df44 5196 #define CAN_F12R2_FB25_Pos (25U)
lypinator 0:bb348c97df44 5197 #define CAN_F12R2_FB25_Msk (0x1U << CAN_F12R2_FB25_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 5198 #define CAN_F12R2_FB25 CAN_F12R2_FB25_Msk /*!<Filter bit 25 */
lypinator 0:bb348c97df44 5199 #define CAN_F12R2_FB26_Pos (26U)
lypinator 0:bb348c97df44 5200 #define CAN_F12R2_FB26_Msk (0x1U << CAN_F12R2_FB26_Pos) /*!< 0x04000000 */
lypinator 0:bb348c97df44 5201 #define CAN_F12R2_FB26 CAN_F12R2_FB26_Msk /*!<Filter bit 26 */
lypinator 0:bb348c97df44 5202 #define CAN_F12R2_FB27_Pos (27U)
lypinator 0:bb348c97df44 5203 #define CAN_F12R2_FB27_Msk (0x1U << CAN_F12R2_FB27_Pos) /*!< 0x08000000 */
lypinator 0:bb348c97df44 5204 #define CAN_F12R2_FB27 CAN_F12R2_FB27_Msk /*!<Filter bit 27 */
lypinator 0:bb348c97df44 5205 #define CAN_F12R2_FB28_Pos (28U)
lypinator 0:bb348c97df44 5206 #define CAN_F12R2_FB28_Msk (0x1U << CAN_F12R2_FB28_Pos) /*!< 0x10000000 */
lypinator 0:bb348c97df44 5207 #define CAN_F12R2_FB28 CAN_F12R2_FB28_Msk /*!<Filter bit 28 */
lypinator 0:bb348c97df44 5208 #define CAN_F12R2_FB29_Pos (29U)
lypinator 0:bb348c97df44 5209 #define CAN_F12R2_FB29_Msk (0x1U << CAN_F12R2_FB29_Pos) /*!< 0x20000000 */
lypinator 0:bb348c97df44 5210 #define CAN_F12R2_FB29 CAN_F12R2_FB29_Msk /*!<Filter bit 29 */
lypinator 0:bb348c97df44 5211 #define CAN_F12R2_FB30_Pos (30U)
lypinator 0:bb348c97df44 5212 #define CAN_F12R2_FB30_Msk (0x1U << CAN_F12R2_FB30_Pos) /*!< 0x40000000 */
lypinator 0:bb348c97df44 5213 #define CAN_F12R2_FB30 CAN_F12R2_FB30_Msk /*!<Filter bit 30 */
lypinator 0:bb348c97df44 5214 #define CAN_F12R2_FB31_Pos (31U)
lypinator 0:bb348c97df44 5215 #define CAN_F12R2_FB31_Msk (0x1U << CAN_F12R2_FB31_Pos) /*!< 0x80000000 */
lypinator 0:bb348c97df44 5216 #define CAN_F12R2_FB31 CAN_F12R2_FB31_Msk /*!<Filter bit 31 */
lypinator 0:bb348c97df44 5217
lypinator 0:bb348c97df44 5218 /******************* Bit definition for CAN_F13R2 register ******************/
lypinator 0:bb348c97df44 5219 #define CAN_F13R2_FB0_Pos (0U)
lypinator 0:bb348c97df44 5220 #define CAN_F13R2_FB0_Msk (0x1U << CAN_F13R2_FB0_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 5221 #define CAN_F13R2_FB0 CAN_F13R2_FB0_Msk /*!<Filter bit 0 */
lypinator 0:bb348c97df44 5222 #define CAN_F13R2_FB1_Pos (1U)
lypinator 0:bb348c97df44 5223 #define CAN_F13R2_FB1_Msk (0x1U << CAN_F13R2_FB1_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 5224 #define CAN_F13R2_FB1 CAN_F13R2_FB1_Msk /*!<Filter bit 1 */
lypinator 0:bb348c97df44 5225 #define CAN_F13R2_FB2_Pos (2U)
lypinator 0:bb348c97df44 5226 #define CAN_F13R2_FB2_Msk (0x1U << CAN_F13R2_FB2_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 5227 #define CAN_F13R2_FB2 CAN_F13R2_FB2_Msk /*!<Filter bit 2 */
lypinator 0:bb348c97df44 5228 #define CAN_F13R2_FB3_Pos (3U)
lypinator 0:bb348c97df44 5229 #define CAN_F13R2_FB3_Msk (0x1U << CAN_F13R2_FB3_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 5230 #define CAN_F13R2_FB3 CAN_F13R2_FB3_Msk /*!<Filter bit 3 */
lypinator 0:bb348c97df44 5231 #define CAN_F13R2_FB4_Pos (4U)
lypinator 0:bb348c97df44 5232 #define CAN_F13R2_FB4_Msk (0x1U << CAN_F13R2_FB4_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 5233 #define CAN_F13R2_FB4 CAN_F13R2_FB4_Msk /*!<Filter bit 4 */
lypinator 0:bb348c97df44 5234 #define CAN_F13R2_FB5_Pos (5U)
lypinator 0:bb348c97df44 5235 #define CAN_F13R2_FB5_Msk (0x1U << CAN_F13R2_FB5_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 5236 #define CAN_F13R2_FB5 CAN_F13R2_FB5_Msk /*!<Filter bit 5 */
lypinator 0:bb348c97df44 5237 #define CAN_F13R2_FB6_Pos (6U)
lypinator 0:bb348c97df44 5238 #define CAN_F13R2_FB6_Msk (0x1U << CAN_F13R2_FB6_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 5239 #define CAN_F13R2_FB6 CAN_F13R2_FB6_Msk /*!<Filter bit 6 */
lypinator 0:bb348c97df44 5240 #define CAN_F13R2_FB7_Pos (7U)
lypinator 0:bb348c97df44 5241 #define CAN_F13R2_FB7_Msk (0x1U << CAN_F13R2_FB7_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 5242 #define CAN_F13R2_FB7 CAN_F13R2_FB7_Msk /*!<Filter bit 7 */
lypinator 0:bb348c97df44 5243 #define CAN_F13R2_FB8_Pos (8U)
lypinator 0:bb348c97df44 5244 #define CAN_F13R2_FB8_Msk (0x1U << CAN_F13R2_FB8_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 5245 #define CAN_F13R2_FB8 CAN_F13R2_FB8_Msk /*!<Filter bit 8 */
lypinator 0:bb348c97df44 5246 #define CAN_F13R2_FB9_Pos (9U)
lypinator 0:bb348c97df44 5247 #define CAN_F13R2_FB9_Msk (0x1U << CAN_F13R2_FB9_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 5248 #define CAN_F13R2_FB9 CAN_F13R2_FB9_Msk /*!<Filter bit 9 */
lypinator 0:bb348c97df44 5249 #define CAN_F13R2_FB10_Pos (10U)
lypinator 0:bb348c97df44 5250 #define CAN_F13R2_FB10_Msk (0x1U << CAN_F13R2_FB10_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 5251 #define CAN_F13R2_FB10 CAN_F13R2_FB10_Msk /*!<Filter bit 10 */
lypinator 0:bb348c97df44 5252 #define CAN_F13R2_FB11_Pos (11U)
lypinator 0:bb348c97df44 5253 #define CAN_F13R2_FB11_Msk (0x1U << CAN_F13R2_FB11_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 5254 #define CAN_F13R2_FB11 CAN_F13R2_FB11_Msk /*!<Filter bit 11 */
lypinator 0:bb348c97df44 5255 #define CAN_F13R2_FB12_Pos (12U)
lypinator 0:bb348c97df44 5256 #define CAN_F13R2_FB12_Msk (0x1U << CAN_F13R2_FB12_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 5257 #define CAN_F13R2_FB12 CAN_F13R2_FB12_Msk /*!<Filter bit 12 */
lypinator 0:bb348c97df44 5258 #define CAN_F13R2_FB13_Pos (13U)
lypinator 0:bb348c97df44 5259 #define CAN_F13R2_FB13_Msk (0x1U << CAN_F13R2_FB13_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 5260 #define CAN_F13R2_FB13 CAN_F13R2_FB13_Msk /*!<Filter bit 13 */
lypinator 0:bb348c97df44 5261 #define CAN_F13R2_FB14_Pos (14U)
lypinator 0:bb348c97df44 5262 #define CAN_F13R2_FB14_Msk (0x1U << CAN_F13R2_FB14_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 5263 #define CAN_F13R2_FB14 CAN_F13R2_FB14_Msk /*!<Filter bit 14 */
lypinator 0:bb348c97df44 5264 #define CAN_F13R2_FB15_Pos (15U)
lypinator 0:bb348c97df44 5265 #define CAN_F13R2_FB15_Msk (0x1U << CAN_F13R2_FB15_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 5266 #define CAN_F13R2_FB15 CAN_F13R2_FB15_Msk /*!<Filter bit 15 */
lypinator 0:bb348c97df44 5267 #define CAN_F13R2_FB16_Pos (16U)
lypinator 0:bb348c97df44 5268 #define CAN_F13R2_FB16_Msk (0x1U << CAN_F13R2_FB16_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 5269 #define CAN_F13R2_FB16 CAN_F13R2_FB16_Msk /*!<Filter bit 16 */
lypinator 0:bb348c97df44 5270 #define CAN_F13R2_FB17_Pos (17U)
lypinator 0:bb348c97df44 5271 #define CAN_F13R2_FB17_Msk (0x1U << CAN_F13R2_FB17_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 5272 #define CAN_F13R2_FB17 CAN_F13R2_FB17_Msk /*!<Filter bit 17 */
lypinator 0:bb348c97df44 5273 #define CAN_F13R2_FB18_Pos (18U)
lypinator 0:bb348c97df44 5274 #define CAN_F13R2_FB18_Msk (0x1U << CAN_F13R2_FB18_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 5275 #define CAN_F13R2_FB18 CAN_F13R2_FB18_Msk /*!<Filter bit 18 */
lypinator 0:bb348c97df44 5276 #define CAN_F13R2_FB19_Pos (19U)
lypinator 0:bb348c97df44 5277 #define CAN_F13R2_FB19_Msk (0x1U << CAN_F13R2_FB19_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 5278 #define CAN_F13R2_FB19 CAN_F13R2_FB19_Msk /*!<Filter bit 19 */
lypinator 0:bb348c97df44 5279 #define CAN_F13R2_FB20_Pos (20U)
lypinator 0:bb348c97df44 5280 #define CAN_F13R2_FB20_Msk (0x1U << CAN_F13R2_FB20_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 5281 #define CAN_F13R2_FB20 CAN_F13R2_FB20_Msk /*!<Filter bit 20 */
lypinator 0:bb348c97df44 5282 #define CAN_F13R2_FB21_Pos (21U)
lypinator 0:bb348c97df44 5283 #define CAN_F13R2_FB21_Msk (0x1U << CAN_F13R2_FB21_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 5284 #define CAN_F13R2_FB21 CAN_F13R2_FB21_Msk /*!<Filter bit 21 */
lypinator 0:bb348c97df44 5285 #define CAN_F13R2_FB22_Pos (22U)
lypinator 0:bb348c97df44 5286 #define CAN_F13R2_FB22_Msk (0x1U << CAN_F13R2_FB22_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 5287 #define CAN_F13R2_FB22 CAN_F13R2_FB22_Msk /*!<Filter bit 22 */
lypinator 0:bb348c97df44 5288 #define CAN_F13R2_FB23_Pos (23U)
lypinator 0:bb348c97df44 5289 #define CAN_F13R2_FB23_Msk (0x1U << CAN_F13R2_FB23_Pos) /*!< 0x00800000 */
lypinator 0:bb348c97df44 5290 #define CAN_F13R2_FB23 CAN_F13R2_FB23_Msk /*!<Filter bit 23 */
lypinator 0:bb348c97df44 5291 #define CAN_F13R2_FB24_Pos (24U)
lypinator 0:bb348c97df44 5292 #define CAN_F13R2_FB24_Msk (0x1U << CAN_F13R2_FB24_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 5293 #define CAN_F13R2_FB24 CAN_F13R2_FB24_Msk /*!<Filter bit 24 */
lypinator 0:bb348c97df44 5294 #define CAN_F13R2_FB25_Pos (25U)
lypinator 0:bb348c97df44 5295 #define CAN_F13R2_FB25_Msk (0x1U << CAN_F13R2_FB25_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 5296 #define CAN_F13R2_FB25 CAN_F13R2_FB25_Msk /*!<Filter bit 25 */
lypinator 0:bb348c97df44 5297 #define CAN_F13R2_FB26_Pos (26U)
lypinator 0:bb348c97df44 5298 #define CAN_F13R2_FB26_Msk (0x1U << CAN_F13R2_FB26_Pos) /*!< 0x04000000 */
lypinator 0:bb348c97df44 5299 #define CAN_F13R2_FB26 CAN_F13R2_FB26_Msk /*!<Filter bit 26 */
lypinator 0:bb348c97df44 5300 #define CAN_F13R2_FB27_Pos (27U)
lypinator 0:bb348c97df44 5301 #define CAN_F13R2_FB27_Msk (0x1U << CAN_F13R2_FB27_Pos) /*!< 0x08000000 */
lypinator 0:bb348c97df44 5302 #define CAN_F13R2_FB27 CAN_F13R2_FB27_Msk /*!<Filter bit 27 */
lypinator 0:bb348c97df44 5303 #define CAN_F13R2_FB28_Pos (28U)
lypinator 0:bb348c97df44 5304 #define CAN_F13R2_FB28_Msk (0x1U << CAN_F13R2_FB28_Pos) /*!< 0x10000000 */
lypinator 0:bb348c97df44 5305 #define CAN_F13R2_FB28 CAN_F13R2_FB28_Msk /*!<Filter bit 28 */
lypinator 0:bb348c97df44 5306 #define CAN_F13R2_FB29_Pos (29U)
lypinator 0:bb348c97df44 5307 #define CAN_F13R2_FB29_Msk (0x1U << CAN_F13R2_FB29_Pos) /*!< 0x20000000 */
lypinator 0:bb348c97df44 5308 #define CAN_F13R2_FB29 CAN_F13R2_FB29_Msk /*!<Filter bit 29 */
lypinator 0:bb348c97df44 5309 #define CAN_F13R2_FB30_Pos (30U)
lypinator 0:bb348c97df44 5310 #define CAN_F13R2_FB30_Msk (0x1U << CAN_F13R2_FB30_Pos) /*!< 0x40000000 */
lypinator 0:bb348c97df44 5311 #define CAN_F13R2_FB30 CAN_F13R2_FB30_Msk /*!<Filter bit 30 */
lypinator 0:bb348c97df44 5312 #define CAN_F13R2_FB31_Pos (31U)
lypinator 0:bb348c97df44 5313 #define CAN_F13R2_FB31_Msk (0x1U << CAN_F13R2_FB31_Pos) /*!< 0x80000000 */
lypinator 0:bb348c97df44 5314 #define CAN_F13R2_FB31 CAN_F13R2_FB31_Msk /*!<Filter bit 31 */
lypinator 0:bb348c97df44 5315
lypinator 0:bb348c97df44 5316 /******************************************************************************/
lypinator 0:bb348c97df44 5317 /* */
lypinator 0:bb348c97df44 5318 /* CRC calculation unit */
lypinator 0:bb348c97df44 5319 /* */
lypinator 0:bb348c97df44 5320 /******************************************************************************/
lypinator 0:bb348c97df44 5321 /******************* Bit definition for CRC_DR register *********************/
lypinator 0:bb348c97df44 5322 #define CRC_DR_DR_Pos (0U)
lypinator 0:bb348c97df44 5323 #define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
lypinator 0:bb348c97df44 5324 #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
lypinator 0:bb348c97df44 5325
lypinator 0:bb348c97df44 5326
lypinator 0:bb348c97df44 5327 /******************* Bit definition for CRC_IDR register ********************/
lypinator 0:bb348c97df44 5328 #define CRC_IDR_IDR_Pos (0U)
lypinator 0:bb348c97df44 5329 #define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
lypinator 0:bb348c97df44 5330 #define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */
lypinator 0:bb348c97df44 5331
lypinator 0:bb348c97df44 5332
lypinator 0:bb348c97df44 5333 /******************** Bit definition for CRC_CR register ********************/
lypinator 0:bb348c97df44 5334 #define CRC_CR_RESET_Pos (0U)
lypinator 0:bb348c97df44 5335 #define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 5336 #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET bit */
lypinator 0:bb348c97df44 5337
lypinator 0:bb348c97df44 5338 /******************************************************************************/
lypinator 0:bb348c97df44 5339 /* */
lypinator 0:bb348c97df44 5340 /* Digital Filter for Sigma Delta Modulators */
lypinator 0:bb348c97df44 5341 /* */
lypinator 0:bb348c97df44 5342 /******************************************************************************/
lypinator 0:bb348c97df44 5343
lypinator 0:bb348c97df44 5344 /**************** DFSDM channel configuration registers ********************/
lypinator 0:bb348c97df44 5345
lypinator 0:bb348c97df44 5346 /*************** Bit definition for DFSDM_CHCFGR1 register ******************/
lypinator 0:bb348c97df44 5347 #define DFSDM_CHCFGR1_DFSDMEN_Pos (31U)
lypinator 0:bb348c97df44 5348 #define DFSDM_CHCFGR1_DFSDMEN_Msk (0x1U << DFSDM_CHCFGR1_DFSDMEN_Pos) /*!< 0x80000000 */
lypinator 0:bb348c97df44 5349 #define DFSDM_CHCFGR1_DFSDMEN DFSDM_CHCFGR1_DFSDMEN_Msk /*!< Global enable for DFSDM interface */
lypinator 0:bb348c97df44 5350 #define DFSDM_CHCFGR1_CKOUTSRC_Pos (30U)
lypinator 0:bb348c97df44 5351 #define DFSDM_CHCFGR1_CKOUTSRC_Msk (0x1U << DFSDM_CHCFGR1_CKOUTSRC_Pos) /*!< 0x40000000 */
lypinator 0:bb348c97df44 5352 #define DFSDM_CHCFGR1_CKOUTSRC DFSDM_CHCFGR1_CKOUTSRC_Msk /*!< Output serial clock source selection */
lypinator 0:bb348c97df44 5353 #define DFSDM_CHCFGR1_CKOUTDIV_Pos (16U)
lypinator 0:bb348c97df44 5354 #define DFSDM_CHCFGR1_CKOUTDIV_Msk (0xFFU << DFSDM_CHCFGR1_CKOUTDIV_Pos) /*!< 0x00FF0000 */
lypinator 0:bb348c97df44 5355 #define DFSDM_CHCFGR1_CKOUTDIV DFSDM_CHCFGR1_CKOUTDIV_Msk /*!< CKOUTDIV[7:0] output serial clock divider */
lypinator 0:bb348c97df44 5356 #define DFSDM_CHCFGR1_DATPACK_Pos (14U)
lypinator 0:bb348c97df44 5357 #define DFSDM_CHCFGR1_DATPACK_Msk (0x3U << DFSDM_CHCFGR1_DATPACK_Pos) /*!< 0x0000C000 */
lypinator 0:bb348c97df44 5358 #define DFSDM_CHCFGR1_DATPACK DFSDM_CHCFGR1_DATPACK_Msk /*!< DATPACK[1:0] Data packing mode */
lypinator 0:bb348c97df44 5359 #define DFSDM_CHCFGR1_DATPACK_1 (0x2U << DFSDM_CHCFGR1_DATPACK_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 5360 #define DFSDM_CHCFGR1_DATPACK_0 (0x1U << DFSDM_CHCFGR1_DATPACK_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 5361 #define DFSDM_CHCFGR1_DATMPX_Pos (12U)
lypinator 0:bb348c97df44 5362 #define DFSDM_CHCFGR1_DATMPX_Msk (0x3U << DFSDM_CHCFGR1_DATMPX_Pos) /*!< 0x00003000 */
lypinator 0:bb348c97df44 5363 #define DFSDM_CHCFGR1_DATMPX DFSDM_CHCFGR1_DATMPX_Msk /*!< DATMPX[1:0] Input data multiplexer for channel y */
lypinator 0:bb348c97df44 5364 #define DFSDM_CHCFGR1_DATMPX_1 (0x2U << DFSDM_CHCFGR1_DATMPX_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 5365 #define DFSDM_CHCFGR1_DATMPX_0 (0x1U << DFSDM_CHCFGR1_DATMPX_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 5366 #define DFSDM_CHCFGR1_CHINSEL_Pos (8U)
lypinator 0:bb348c97df44 5367 #define DFSDM_CHCFGR1_CHINSEL_Msk (0x1U << DFSDM_CHCFGR1_CHINSEL_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 5368 #define DFSDM_CHCFGR1_CHINSEL DFSDM_CHCFGR1_CHINSEL_Msk /*!< Serial inputs selection for channel y */
lypinator 0:bb348c97df44 5369 #define DFSDM_CHCFGR1_CHEN_Pos (7U)
lypinator 0:bb348c97df44 5370 #define DFSDM_CHCFGR1_CHEN_Msk (0x1U << DFSDM_CHCFGR1_CHEN_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 5371 #define DFSDM_CHCFGR1_CHEN DFSDM_CHCFGR1_CHEN_Msk /*!< Channel y enable */
lypinator 0:bb348c97df44 5372 #define DFSDM_CHCFGR1_CKABEN_Pos (6U)
lypinator 0:bb348c97df44 5373 #define DFSDM_CHCFGR1_CKABEN_Msk (0x1U << DFSDM_CHCFGR1_CKABEN_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 5374 #define DFSDM_CHCFGR1_CKABEN DFSDM_CHCFGR1_CKABEN_Msk /*!< Clock absence detector enable on channel y */
lypinator 0:bb348c97df44 5375 #define DFSDM_CHCFGR1_SCDEN_Pos (5U)
lypinator 0:bb348c97df44 5376 #define DFSDM_CHCFGR1_SCDEN_Msk (0x1U << DFSDM_CHCFGR1_SCDEN_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 5377 #define DFSDM_CHCFGR1_SCDEN DFSDM_CHCFGR1_SCDEN_Msk /*!< Short circuit detector enable on channel y */
lypinator 0:bb348c97df44 5378 #define DFSDM_CHCFGR1_SPICKSEL_Pos (2U)
lypinator 0:bb348c97df44 5379 #define DFSDM_CHCFGR1_SPICKSEL_Msk (0x3U << DFSDM_CHCFGR1_SPICKSEL_Pos) /*!< 0x0000000C */
lypinator 0:bb348c97df44 5380 #define DFSDM_CHCFGR1_SPICKSEL DFSDM_CHCFGR1_SPICKSEL_Msk /*!< SPICKSEL[1:0] SPI clock select for channel y */
lypinator 0:bb348c97df44 5381 #define DFSDM_CHCFGR1_SPICKSEL_1 (0x2U << DFSDM_CHCFGR1_SPICKSEL_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 5382 #define DFSDM_CHCFGR1_SPICKSEL_0 (0x1U << DFSDM_CHCFGR1_SPICKSEL_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 5383 #define DFSDM_CHCFGR1_SITP_Pos (0U)
lypinator 0:bb348c97df44 5384 #define DFSDM_CHCFGR1_SITP_Msk (0x3U << DFSDM_CHCFGR1_SITP_Pos) /*!< 0x00000003 */
lypinator 0:bb348c97df44 5385 #define DFSDM_CHCFGR1_SITP DFSDM_CHCFGR1_SITP_Msk /*!< SITP[1:0] Serial interface type for channel y */
lypinator 0:bb348c97df44 5386 #define DFSDM_CHCFGR1_SITP_1 (0x2U << DFSDM_CHCFGR1_SITP_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 5387 #define DFSDM_CHCFGR1_SITP_0 (0x1U << DFSDM_CHCFGR1_SITP_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 5388
lypinator 0:bb348c97df44 5389 /*************** Bit definition for DFSDM_CHCFGR2 register ******************/
lypinator 0:bb348c97df44 5390 #define DFSDM_CHCFGR2_OFFSET_Pos (8U)
lypinator 0:bb348c97df44 5391 #define DFSDM_CHCFGR2_OFFSET_Msk (0xFFFFFFU << DFSDM_CHCFGR2_OFFSET_Pos) /*!< 0xFFFFFF00 */
lypinator 0:bb348c97df44 5392 #define DFSDM_CHCFGR2_OFFSET DFSDM_CHCFGR2_OFFSET_Msk /*!< OFFSET[23:0] 24-bit calibration offset for channel y */
lypinator 0:bb348c97df44 5393 #define DFSDM_CHCFGR2_DTRBS_Pos (3U)
lypinator 0:bb348c97df44 5394 #define DFSDM_CHCFGR2_DTRBS_Msk (0x1FU << DFSDM_CHCFGR2_DTRBS_Pos) /*!< 0x000000F8 */
lypinator 0:bb348c97df44 5395 #define DFSDM_CHCFGR2_DTRBS DFSDM_CHCFGR2_DTRBS_Msk /*!< DTRBS[4:0] Data right bit-shift for channel y */
lypinator 0:bb348c97df44 5396
lypinator 0:bb348c97df44 5397 /**************** Bit definition for DFSDM_CHAWSCDR register *****************/
lypinator 0:bb348c97df44 5398 #define DFSDM_CHAWSCDR_AWFORD_Pos (22U)
lypinator 0:bb348c97df44 5399 #define DFSDM_CHAWSCDR_AWFORD_Msk (0x3U << DFSDM_CHAWSCDR_AWFORD_Pos) /*!< 0x00C00000 */
lypinator 0:bb348c97df44 5400 #define DFSDM_CHAWSCDR_AWFORD DFSDM_CHAWSCDR_AWFORD_Msk /*!< AWFORD[1:0] Analog watchdog Sinc filter order on channel y */
lypinator 0:bb348c97df44 5401 #define DFSDM_CHAWSCDR_AWFORD_1 (0x2U << DFSDM_CHAWSCDR_AWFORD_Pos) /*!< 0x00800000 */
lypinator 0:bb348c97df44 5402 #define DFSDM_CHAWSCDR_AWFORD_0 (0x1U << DFSDM_CHAWSCDR_AWFORD_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 5403 #define DFSDM_CHAWSCDR_AWFOSR_Pos (16U)
lypinator 0:bb348c97df44 5404 #define DFSDM_CHAWSCDR_AWFOSR_Msk (0x1FU << DFSDM_CHAWSCDR_AWFOSR_Pos) /*!< 0x001F0000 */
lypinator 0:bb348c97df44 5405 #define DFSDM_CHAWSCDR_AWFOSR DFSDM_CHAWSCDR_AWFOSR_Msk /*!< AWFOSR[4:0] Analog watchdog filter oversampling ratio on channel y */
lypinator 0:bb348c97df44 5406 #define DFSDM_CHAWSCDR_BKSCD_Pos (12U)
lypinator 0:bb348c97df44 5407 #define DFSDM_CHAWSCDR_BKSCD_Msk (0xFU << DFSDM_CHAWSCDR_BKSCD_Pos) /*!< 0x0000F000 */
lypinator 0:bb348c97df44 5408 #define DFSDM_CHAWSCDR_BKSCD DFSDM_CHAWSCDR_BKSCD_Msk /*!< BKSCD[3:0] Break signal assignment for short circuit detector on channel y */
lypinator 0:bb348c97df44 5409 #define DFSDM_CHAWSCDR_SCDT_Pos (0U)
lypinator 0:bb348c97df44 5410 #define DFSDM_CHAWSCDR_SCDT_Msk (0xFFU << DFSDM_CHAWSCDR_SCDT_Pos) /*!< 0x000000FF */
lypinator 0:bb348c97df44 5411 #define DFSDM_CHAWSCDR_SCDT DFSDM_CHAWSCDR_SCDT_Msk /*!< SCDT[7:0] Short circuit detector threshold for channel y */
lypinator 0:bb348c97df44 5412
lypinator 0:bb348c97df44 5413 /**************** Bit definition for DFSDM_CHWDATR register *******************/
lypinator 0:bb348c97df44 5414 #define DFSDM_CHWDATR_WDATA_Pos (0U)
lypinator 0:bb348c97df44 5415 #define DFSDM_CHWDATR_WDATA_Msk (0xFFFFU << DFSDM_CHWDATR_WDATA_Pos) /*!< 0x0000FFFF */
lypinator 0:bb348c97df44 5416 #define DFSDM_CHWDATR_WDATA DFSDM_CHWDATR_WDATA_Msk /*!< WDATA[15:0] Input channel y watchdog data */
lypinator 0:bb348c97df44 5417
lypinator 0:bb348c97df44 5418 /**************** Bit definition for DFSDM_CHDATINR register *****************/
lypinator 0:bb348c97df44 5419 #define DFSDM_CHDATINR_INDAT0_Pos (0U)
lypinator 0:bb348c97df44 5420 #define DFSDM_CHDATINR_INDAT0_Msk (0xFFFFU << DFSDM_CHDATINR_INDAT0_Pos) /*!< 0x0000FFFF */
lypinator 0:bb348c97df44 5421 #define DFSDM_CHDATINR_INDAT0 DFSDM_CHDATINR_INDAT0_Msk /*!< INDAT0[31:16] Input data for channel y or channel (y+1) */
lypinator 0:bb348c97df44 5422 #define DFSDM_CHDATINR_INDAT1_Pos (16U)
lypinator 0:bb348c97df44 5423 #define DFSDM_CHDATINR_INDAT1_Msk (0xFFFFU << DFSDM_CHDATINR_INDAT1_Pos) /*!< 0xFFFF0000 */
lypinator 0:bb348c97df44 5424 #define DFSDM_CHDATINR_INDAT1 DFSDM_CHDATINR_INDAT1_Msk /*!< INDAT0[15:0] Input data for channel y */
lypinator 0:bb348c97df44 5425
lypinator 0:bb348c97df44 5426 /************************ DFSDM module registers ****************************/
lypinator 0:bb348c97df44 5427
lypinator 0:bb348c97df44 5428 /***************** Bit definition for DFSDM_FLTCR1 register *******************/
lypinator 0:bb348c97df44 5429 #define DFSDM_FLTCR1_AWFSEL_Pos (30U)
lypinator 0:bb348c97df44 5430 #define DFSDM_FLTCR1_AWFSEL_Msk (0x1U << DFSDM_FLTCR1_AWFSEL_Pos) /*!< 0x40000000 */
lypinator 0:bb348c97df44 5431 #define DFSDM_FLTCR1_AWFSEL DFSDM_FLTCR1_AWFSEL_Msk /*!< Analog watchdog fast mode select */
lypinator 0:bb348c97df44 5432 #define DFSDM_FLTCR1_FAST_Pos (29U)
lypinator 0:bb348c97df44 5433 #define DFSDM_FLTCR1_FAST_Msk (0x1U << DFSDM_FLTCR1_FAST_Pos) /*!< 0x20000000 */
lypinator 0:bb348c97df44 5434 #define DFSDM_FLTCR1_FAST DFSDM_FLTCR1_FAST_Msk /*!< Fast conversion mode selection */
lypinator 0:bb348c97df44 5435 #define DFSDM_FLTCR1_RCH_Pos (24U)
lypinator 0:bb348c97df44 5436 #define DFSDM_FLTCR1_RCH_Msk (0x7U << DFSDM_FLTCR1_RCH_Pos) /*!< 0x07000000 */
lypinator 0:bb348c97df44 5437 #define DFSDM_FLTCR1_RCH DFSDM_FLTCR1_RCH_Msk /*!< RCH[2:0] Regular channel selection */
lypinator 0:bb348c97df44 5438 #define DFSDM_FLTCR1_RDMAEN_Pos (21U)
lypinator 0:bb348c97df44 5439 #define DFSDM_FLTCR1_RDMAEN_Msk (0x1U << DFSDM_FLTCR1_RDMAEN_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 5440 #define DFSDM_FLTCR1_RDMAEN DFSDM_FLTCR1_RDMAEN_Msk /*!< DMA channel enabled to read data for the regular conversion */
lypinator 0:bb348c97df44 5441 #define DFSDM_FLTCR1_RSYNC_Pos (19U)
lypinator 0:bb348c97df44 5442 #define DFSDM_FLTCR1_RSYNC_Msk (0x1U << DFSDM_FLTCR1_RSYNC_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 5443 #define DFSDM_FLTCR1_RSYNC DFSDM_FLTCR1_RSYNC_Msk /*!< Launch regular conversion synchronously with DFSDMx */
lypinator 0:bb348c97df44 5444 #define DFSDM_FLTCR1_RCONT_Pos (18U)
lypinator 0:bb348c97df44 5445 #define DFSDM_FLTCR1_RCONT_Msk (0x1U << DFSDM_FLTCR1_RCONT_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 5446 #define DFSDM_FLTCR1_RCONT DFSDM_FLTCR1_RCONT_Msk /*!< Continuous mode selection for regular conversions */
lypinator 0:bb348c97df44 5447 #define DFSDM_FLTCR1_RSWSTART_Pos (17U)
lypinator 0:bb348c97df44 5448 #define DFSDM_FLTCR1_RSWSTART_Msk (0x1U << DFSDM_FLTCR1_RSWSTART_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 5449 #define DFSDM_FLTCR1_RSWSTART DFSDM_FLTCR1_RSWSTART_Msk /*!< Software start of a conversion on the regular channel */
lypinator 0:bb348c97df44 5450 #define DFSDM_FLTCR1_JEXTEN_Pos (13U)
lypinator 0:bb348c97df44 5451 #define DFSDM_FLTCR1_JEXTEN_Msk (0x3U << DFSDM_FLTCR1_JEXTEN_Pos) /*!< 0x00006000 */
lypinator 0:bb348c97df44 5452 #define DFSDM_FLTCR1_JEXTEN DFSDM_FLTCR1_JEXTEN_Msk /*!< JEXTEN[1:0] Trigger enable and trigger edge selection for injected conversions */
lypinator 0:bb348c97df44 5453 #define DFSDM_FLTCR1_JEXTEN_1 (0x2U << DFSDM_FLTCR1_JEXTEN_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 5454 #define DFSDM_FLTCR1_JEXTEN_0 (0x1U << DFSDM_FLTCR1_JEXTEN_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 5455 #define DFSDM_FLTCR1_JEXTSEL_Pos (8U)
lypinator 0:bb348c97df44 5456 #define DFSDM_FLTCR1_JEXTSEL_Msk (0x7U << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000700 */
lypinator 0:bb348c97df44 5457 #define DFSDM_FLTCR1_JEXTSEL DFSDM_FLTCR1_JEXTSEL_Msk /*!< JEXTSEL[2:0]Trigger signal selection for launching injected conversions */
lypinator 0:bb348c97df44 5458 #define DFSDM_FLTCR1_JEXTSEL_2 (0x4U << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 5459 #define DFSDM_FLTCR1_JEXTSEL_1 (0x2U << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 5460 #define DFSDM_FLTCR1_JEXTSEL_0 (0x1U << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 5461 #define DFSDM_FLTCR1_JDMAEN_Pos (5U)
lypinator 0:bb348c97df44 5462 #define DFSDM_FLTCR1_JDMAEN_Msk (0x1U << DFSDM_FLTCR1_JDMAEN_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 5463 #define DFSDM_FLTCR1_JDMAEN DFSDM_FLTCR1_JDMAEN_Msk /*!< DMA channel enabled to read data for the injected channel group */
lypinator 0:bb348c97df44 5464 #define DFSDM_FLTCR1_JSCAN_Pos (4U)
lypinator 0:bb348c97df44 5465 #define DFSDM_FLTCR1_JSCAN_Msk (0x1U << DFSDM_FLTCR1_JSCAN_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 5466 #define DFSDM_FLTCR1_JSCAN DFSDM_FLTCR1_JSCAN_Msk /*!< Scanning conversion in continuous mode selection for injected conversions */
lypinator 0:bb348c97df44 5467 #define DFSDM_FLTCR1_JSYNC_Pos (3U)
lypinator 0:bb348c97df44 5468 #define DFSDM_FLTCR1_JSYNC_Msk (0x1U << DFSDM_FLTCR1_JSYNC_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 5469 #define DFSDM_FLTCR1_JSYNC DFSDM_FLTCR1_JSYNC_Msk /*!< Launch an injected conversion synchronously with DFSDMx JSWSTART trigger */
lypinator 0:bb348c97df44 5470 #define DFSDM_FLTCR1_JSWSTART_Pos (1U)
lypinator 0:bb348c97df44 5471 #define DFSDM_FLTCR1_JSWSTART_Msk (0x1U << DFSDM_FLTCR1_JSWSTART_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 5472 #define DFSDM_FLTCR1_JSWSTART DFSDM_FLTCR1_JSWSTART_Msk /*!< Start the conversion of the injected group of channels */
lypinator 0:bb348c97df44 5473 #define DFSDM_FLTCR1_DFEN_Pos (0U)
lypinator 0:bb348c97df44 5474 #define DFSDM_FLTCR1_DFEN_Msk (0x1U << DFSDM_FLTCR1_DFEN_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 5475 #define DFSDM_FLTCR1_DFEN DFSDM_FLTCR1_DFEN_Msk /*!< DFSDM enable */
lypinator 0:bb348c97df44 5476
lypinator 0:bb348c97df44 5477 /***************** Bit definition for DFSDM_FLTCR2 register *******************/
lypinator 0:bb348c97df44 5478 #define DFSDM_FLTCR2_AWDCH_Pos (16U)
lypinator 0:bb348c97df44 5479 #define DFSDM_FLTCR2_AWDCH_Msk (0xFU << DFSDM_FLTCR2_AWDCH_Pos) /*!< 0x000F0000 */
lypinator 0:bb348c97df44 5480 #define DFSDM_FLTCR2_AWDCH DFSDM_FLTCR2_AWDCH_Msk /*!< AWDCH[7:0] Analog watchdog channel selection */
lypinator 0:bb348c97df44 5481 #define DFSDM_FLTCR2_EXCH_Pos (8U)
lypinator 0:bb348c97df44 5482 #define DFSDM_FLTCR2_EXCH_Msk (0xFU << DFSDM_FLTCR2_EXCH_Pos) /*!< 0x00000F00 */
lypinator 0:bb348c97df44 5483 #define DFSDM_FLTCR2_EXCH DFSDM_FLTCR2_EXCH_Msk /*!< EXCH[7:0] Extreme detector channel selection */
lypinator 0:bb348c97df44 5484 #define DFSDM_FLTCR2_CKABIE_Pos (6U)
lypinator 0:bb348c97df44 5485 #define DFSDM_FLTCR2_CKABIE_Msk (0x1U << DFSDM_FLTCR2_CKABIE_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 5486 #define DFSDM_FLTCR2_CKABIE DFSDM_FLTCR2_CKABIE_Msk /*!< Clock absence interrupt enable */
lypinator 0:bb348c97df44 5487 #define DFSDM_FLTCR2_SCDIE_Pos (5U)
lypinator 0:bb348c97df44 5488 #define DFSDM_FLTCR2_SCDIE_Msk (0x1U << DFSDM_FLTCR2_SCDIE_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 5489 #define DFSDM_FLTCR2_SCDIE DFSDM_FLTCR2_SCDIE_Msk /*!< Short circuit detector interrupt enable */
lypinator 0:bb348c97df44 5490 #define DFSDM_FLTCR2_AWDIE_Pos (4U)
lypinator 0:bb348c97df44 5491 #define DFSDM_FLTCR2_AWDIE_Msk (0x1U << DFSDM_FLTCR2_AWDIE_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 5492 #define DFSDM_FLTCR2_AWDIE DFSDM_FLTCR2_AWDIE_Msk /*!< Analog watchdog interrupt enable */
lypinator 0:bb348c97df44 5493 #define DFSDM_FLTCR2_ROVRIE_Pos (3U)
lypinator 0:bb348c97df44 5494 #define DFSDM_FLTCR2_ROVRIE_Msk (0x1U << DFSDM_FLTCR2_ROVRIE_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 5495 #define DFSDM_FLTCR2_ROVRIE DFSDM_FLTCR2_ROVRIE_Msk /*!< Regular data overrun interrupt enable */
lypinator 0:bb348c97df44 5496 #define DFSDM_FLTCR2_JOVRIE_Pos (2U)
lypinator 0:bb348c97df44 5497 #define DFSDM_FLTCR2_JOVRIE_Msk (0x1U << DFSDM_FLTCR2_JOVRIE_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 5498 #define DFSDM_FLTCR2_JOVRIE DFSDM_FLTCR2_JOVRIE_Msk /*!< Injected data overrun interrupt enable */
lypinator 0:bb348c97df44 5499 #define DFSDM_FLTCR2_REOCIE_Pos (1U)
lypinator 0:bb348c97df44 5500 #define DFSDM_FLTCR2_REOCIE_Msk (0x1U << DFSDM_FLTCR2_REOCIE_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 5501 #define DFSDM_FLTCR2_REOCIE DFSDM_FLTCR2_REOCIE_Msk /*!< Regular end of conversion interrupt enable */
lypinator 0:bb348c97df44 5502 #define DFSDM_FLTCR2_JEOCIE_Pos (0U)
lypinator 0:bb348c97df44 5503 #define DFSDM_FLTCR2_JEOCIE_Msk (0x1U << DFSDM_FLTCR2_JEOCIE_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 5504 #define DFSDM_FLTCR2_JEOCIE DFSDM_FLTCR2_JEOCIE_Msk /*!< Injected end of conversion interrupt enable */
lypinator 0:bb348c97df44 5505
lypinator 0:bb348c97df44 5506 /***************** Bit definition for DFSDM_FLTISR register *******************/
lypinator 0:bb348c97df44 5507 #define DFSDM_FLTISR_SCDF_Pos (24U)
lypinator 0:bb348c97df44 5508 #define DFSDM_FLTISR_SCDF_Msk (0xFU << DFSDM_FLTISR_SCDF_Pos) /*!< 0x0F000000 */
lypinator 0:bb348c97df44 5509 #define DFSDM_FLTISR_SCDF DFSDM_FLTISR_SCDF_Msk /*!< SCDF[7:0] Short circuit detector flag */
lypinator 0:bb348c97df44 5510 #define DFSDM_FLTISR_CKABF_Pos (16U)
lypinator 0:bb348c97df44 5511 #define DFSDM_FLTISR_CKABF_Msk (0xFU << DFSDM_FLTISR_CKABF_Pos) /*!< 0x000F0000 */
lypinator 0:bb348c97df44 5512 #define DFSDM_FLTISR_CKABF DFSDM_FLTISR_CKABF_Msk /*!< CKABF[7:0] Clock absence flag */
lypinator 0:bb348c97df44 5513 #define DFSDM_FLTISR_RCIP_Pos (14U)
lypinator 0:bb348c97df44 5514 #define DFSDM_FLTISR_RCIP_Msk (0x1U << DFSDM_FLTISR_RCIP_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 5515 #define DFSDM_FLTISR_RCIP DFSDM_FLTISR_RCIP_Msk /*!< Regular conversion in progress status */
lypinator 0:bb348c97df44 5516 #define DFSDM_FLTISR_JCIP_Pos (13U)
lypinator 0:bb348c97df44 5517 #define DFSDM_FLTISR_JCIP_Msk (0x1U << DFSDM_FLTISR_JCIP_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 5518 #define DFSDM_FLTISR_JCIP DFSDM_FLTISR_JCIP_Msk /*!< Injected conversion in progress status */
lypinator 0:bb348c97df44 5519 #define DFSDM_FLTISR_AWDF_Pos (4U)
lypinator 0:bb348c97df44 5520 #define DFSDM_FLTISR_AWDF_Msk (0x1U << DFSDM_FLTISR_AWDF_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 5521 #define DFSDM_FLTISR_AWDF DFSDM_FLTISR_AWDF_Msk /*!< Analog watchdog */
lypinator 0:bb348c97df44 5522 #define DFSDM_FLTISR_ROVRF_Pos (3U)
lypinator 0:bb348c97df44 5523 #define DFSDM_FLTISR_ROVRF_Msk (0x1U << DFSDM_FLTISR_ROVRF_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 5524 #define DFSDM_FLTISR_ROVRF DFSDM_FLTISR_ROVRF_Msk /*!< Regular conversion overrun flag */
lypinator 0:bb348c97df44 5525 #define DFSDM_FLTISR_JOVRF_Pos (2U)
lypinator 0:bb348c97df44 5526 #define DFSDM_FLTISR_JOVRF_Msk (0x1U << DFSDM_FLTISR_JOVRF_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 5527 #define DFSDM_FLTISR_JOVRF DFSDM_FLTISR_JOVRF_Msk /*!< Injected conversion overrun flag */
lypinator 0:bb348c97df44 5528 #define DFSDM_FLTISR_REOCF_Pos (1U)
lypinator 0:bb348c97df44 5529 #define DFSDM_FLTISR_REOCF_Msk (0x1U << DFSDM_FLTISR_REOCF_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 5530 #define DFSDM_FLTISR_REOCF DFSDM_FLTISR_REOCF_Msk /*!< End of regular conversion flag */
lypinator 0:bb348c97df44 5531 #define DFSDM_FLTISR_JEOCF_Pos (0U)
lypinator 0:bb348c97df44 5532 #define DFSDM_FLTISR_JEOCF_Msk (0x1U << DFSDM_FLTISR_JEOCF_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 5533 #define DFSDM_FLTISR_JEOCF DFSDM_FLTISR_JEOCF_Msk /*!< End of injected conversion flag */
lypinator 0:bb348c97df44 5534
lypinator 0:bb348c97df44 5535 /***************** Bit definition for DFSDM_FLTICR register *******************/
lypinator 0:bb348c97df44 5536 #define DFSDM_FLTICR_CLRSCSDF_Pos (24U)
lypinator 0:bb348c97df44 5537 #define DFSDM_FLTICR_CLRSCSDF_Msk (0xFU << DFSDM_FLTICR_CLRSCSDF_Pos) /*!< 0x0F000000 */
lypinator 0:bb348c97df44 5538 #define DFSDM_FLTICR_CLRSCSDF DFSDM_FLTICR_CLRSCSDF_Msk /*!< CLRSCSDF[7:0] Clear the short circuit detector flag */
lypinator 0:bb348c97df44 5539 #define DFSDM_FLTICR_CLRCKABF_Pos (16U)
lypinator 0:bb348c97df44 5540 #define DFSDM_FLTICR_CLRCKABF_Msk (0xFU << DFSDM_FLTICR_CLRCKABF_Pos) /*!< 0x000F0000 */
lypinator 0:bb348c97df44 5541 #define DFSDM_FLTICR_CLRCKABF DFSDM_FLTICR_CLRCKABF_Msk /*!< CLRCKABF[7:0] Clear the clock absence flag */
lypinator 0:bb348c97df44 5542 #define DFSDM_FLTICR_CLRROVRF_Pos (3U)
lypinator 0:bb348c97df44 5543 #define DFSDM_FLTICR_CLRROVRF_Msk (0x1U << DFSDM_FLTICR_CLRROVRF_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 5544 #define DFSDM_FLTICR_CLRROVRF DFSDM_FLTICR_CLRROVRF_Msk /*!< Clear the regular conversion overrun flag */
lypinator 0:bb348c97df44 5545 #define DFSDM_FLTICR_CLRJOVRF_Pos (2U)
lypinator 0:bb348c97df44 5546 #define DFSDM_FLTICR_CLRJOVRF_Msk (0x1U << DFSDM_FLTICR_CLRJOVRF_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 5547 #define DFSDM_FLTICR_CLRJOVRF DFSDM_FLTICR_CLRJOVRF_Msk /*!< Clear the injected conversion overrun flag */
lypinator 0:bb348c97df44 5548
lypinator 0:bb348c97df44 5549 /**************** Bit definition for DFSDM_FLTJCHGR register ******************/
lypinator 0:bb348c97df44 5550 #define DFSDM_FLTJCHGR_JCHG_Pos (0U)
lypinator 0:bb348c97df44 5551 #define DFSDM_FLTJCHGR_JCHG_Msk (0xFU << DFSDM_FLTJCHGR_JCHG_Pos) /*!< 0x0000000F */
lypinator 0:bb348c97df44 5552 #define DFSDM_FLTJCHGR_JCHG DFSDM_FLTJCHGR_JCHG_Msk /*!< JCHG[7:0] Injected channel group selection */
lypinator 0:bb348c97df44 5553 /***************** Bit definition for DFSDM_FLTFCR register *******************/
lypinator 0:bb348c97df44 5554 #define DFSDM_FLTFCR_FORD_Pos (29U)
lypinator 0:bb348c97df44 5555 #define DFSDM_FLTFCR_FORD_Msk (0x7U << DFSDM_FLTFCR_FORD_Pos) /*!< 0xE0000000 */
lypinator 0:bb348c97df44 5556 #define DFSDM_FLTFCR_FORD DFSDM_FLTFCR_FORD_Msk /*!< FORD[2:0] Sinc filter order */
lypinator 0:bb348c97df44 5557 #define DFSDM_FLTFCR_FORD_2 (0x4U << DFSDM_FLTFCR_FORD_Pos) /*!< 0x80000000 */
lypinator 0:bb348c97df44 5558 #define DFSDM_FLTFCR_FORD_1 (0x2U << DFSDM_FLTFCR_FORD_Pos) /*!< 0x40000000 */
lypinator 0:bb348c97df44 5559 #define DFSDM_FLTFCR_FORD_0 (0x1U << DFSDM_FLTFCR_FORD_Pos) /*!< 0x20000000 */
lypinator 0:bb348c97df44 5560 #define DFSDM_FLTFCR_FOSR_Pos (16U)
lypinator 0:bb348c97df44 5561 #define DFSDM_FLTFCR_FOSR_Msk (0x3FFU << DFSDM_FLTFCR_FOSR_Pos) /*!< 0x03FF0000 */
lypinator 0:bb348c97df44 5562 #define DFSDM_FLTFCR_FOSR DFSDM_FLTFCR_FOSR_Msk /*!< FOSR[9:0] Sinc filter oversampling ratio (decimation rate) */
lypinator 0:bb348c97df44 5563 #define DFSDM_FLTFCR_IOSR_Pos (0U)
lypinator 0:bb348c97df44 5564 #define DFSDM_FLTFCR_IOSR_Msk (0xFFU << DFSDM_FLTFCR_IOSR_Pos) /*!< 0x000000FF */
lypinator 0:bb348c97df44 5565 #define DFSDM_FLTFCR_IOSR DFSDM_FLTFCR_IOSR_Msk /*!< IOSR[7:0] Integrator oversampling ratio (averaging length) */
lypinator 0:bb348c97df44 5566
lypinator 0:bb348c97df44 5567 /*************** Bit definition for DFSDM_FLTJDATAR register *****************/
lypinator 0:bb348c97df44 5568 #define DFSDM_FLTJDATAR_JDATA_Pos (8U)
lypinator 0:bb348c97df44 5569 #define DFSDM_FLTJDATAR_JDATA_Msk (0xFFFFFFU << DFSDM_FLTJDATAR_JDATA_Pos) /*!< 0xFFFFFF00 */
lypinator 0:bb348c97df44 5570 #define DFSDM_FLTJDATAR_JDATA DFSDM_FLTJDATAR_JDATA_Msk /*!< JDATA[23:0] Injected group conversion data */
lypinator 0:bb348c97df44 5571 #define DFSDM_FLTJDATAR_JDATACH_Pos (0U)
lypinator 0:bb348c97df44 5572 #define DFSDM_FLTJDATAR_JDATACH_Msk (0x7U << DFSDM_FLTJDATAR_JDATACH_Pos) /*!< 0x00000007 */
lypinator 0:bb348c97df44 5573 #define DFSDM_FLTJDATAR_JDATACH DFSDM_FLTJDATAR_JDATACH_Msk /*!< JDATACH[2:0] Injected channel most recently converted */
lypinator 0:bb348c97df44 5574
lypinator 0:bb348c97df44 5575 /*************** Bit definition for DFSDM_FLTRDATAR register *****************/
lypinator 0:bb348c97df44 5576 #define DFSDM_FLTRDATAR_RDATA_Pos (8U)
lypinator 0:bb348c97df44 5577 #define DFSDM_FLTRDATAR_RDATA_Msk (0xFFFFFFU << DFSDM_FLTRDATAR_RDATA_Pos) /*!< 0xFFFFFF00 */
lypinator 0:bb348c97df44 5578 #define DFSDM_FLTRDATAR_RDATA DFSDM_FLTRDATAR_RDATA_Msk /*!< RDATA[23:0] Regular channel conversion data */
lypinator 0:bb348c97df44 5579 #define DFSDM_FLTRDATAR_RPEND_Pos (4U)
lypinator 0:bb348c97df44 5580 #define DFSDM_FLTRDATAR_RPEND_Msk (0x1U << DFSDM_FLTRDATAR_RPEND_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 5581 #define DFSDM_FLTRDATAR_RPEND DFSDM_FLTRDATAR_RPEND_Msk /*!< RPEND Regular channel pending data */
lypinator 0:bb348c97df44 5582 #define DFSDM_FLTRDATAR_RDATACH_Pos (0U)
lypinator 0:bb348c97df44 5583 #define DFSDM_FLTRDATAR_RDATACH_Msk (0x7U << DFSDM_FLTRDATAR_RDATACH_Pos) /*!< 0x00000007 */
lypinator 0:bb348c97df44 5584 #define DFSDM_FLTRDATAR_RDATACH DFSDM_FLTRDATAR_RDATACH_Msk /*!< RDATACH[2:0] Regular channel most recently converted */
lypinator 0:bb348c97df44 5585
lypinator 0:bb348c97df44 5586 /*************** Bit definition for DFSDM_FLTAWHTR register ******************/
lypinator 0:bb348c97df44 5587 #define DFSDM_FLTAWHTR_AWHT_Pos (8U)
lypinator 0:bb348c97df44 5588 #define DFSDM_FLTAWHTR_AWHT_Msk (0xFFFFFFU << DFSDM_FLTAWHTR_AWHT_Pos) /*!< 0xFFFFFF00 */
lypinator 0:bb348c97df44 5589 #define DFSDM_FLTAWHTR_AWHT DFSDM_FLTAWHTR_AWHT_Msk /*!< AWHT[23:0] Analog watchdog high threshold */
lypinator 0:bb348c97df44 5590 #define DFSDM_FLTAWHTR_BKAWH_Pos (0U)
lypinator 0:bb348c97df44 5591 #define DFSDM_FLTAWHTR_BKAWH_Msk (0xFU << DFSDM_FLTAWHTR_BKAWH_Pos) /*!< 0x0000000F */
lypinator 0:bb348c97df44 5592 #define DFSDM_FLTAWHTR_BKAWH DFSDM_FLTAWHTR_BKAWH_Msk /*!< BKAWH[3:0] Break signal assignment to analog watchdog high threshold event */
lypinator 0:bb348c97df44 5593
lypinator 0:bb348c97df44 5594 /*************** Bit definition for DFSDM_FLTAWLTR register ******************/
lypinator 0:bb348c97df44 5595 #define DFSDM_FLTAWLTR_AWLT_Pos (8U)
lypinator 0:bb348c97df44 5596 #define DFSDM_FLTAWLTR_AWLT_Msk (0xFFFFFFU << DFSDM_FLTAWLTR_AWLT_Pos) /*!< 0xFFFFFF00 */
lypinator 0:bb348c97df44 5597 #define DFSDM_FLTAWLTR_AWLT DFSDM_FLTAWLTR_AWLT_Msk /*!< AWLT[23:0] Analog watchdog low threshold */
lypinator 0:bb348c97df44 5598 #define DFSDM_FLTAWLTR_BKAWL_Pos (0U)
lypinator 0:bb348c97df44 5599 #define DFSDM_FLTAWLTR_BKAWL_Msk (0xFU << DFSDM_FLTAWLTR_BKAWL_Pos) /*!< 0x0000000F */
lypinator 0:bb348c97df44 5600 #define DFSDM_FLTAWLTR_BKAWL DFSDM_FLTAWLTR_BKAWL_Msk /*!< BKAWL[3:0] Break signal assignment to analog watchdog low threshold event */
lypinator 0:bb348c97df44 5601
lypinator 0:bb348c97df44 5602 /*************** Bit definition for DFSDM_FLTAWSR register *******************/
lypinator 0:bb348c97df44 5603 #define DFSDM_FLTAWSR_AWHTF_Pos (8U)
lypinator 0:bb348c97df44 5604 #define DFSDM_FLTAWSR_AWHTF_Msk (0xFU << DFSDM_FLTAWSR_AWHTF_Pos) /*!< 0x00000F00 */
lypinator 0:bb348c97df44 5605 #define DFSDM_FLTAWSR_AWHTF DFSDM_FLTAWSR_AWHTF_Msk /*!< AWHTF[15:8] Analog watchdog high threshold error on given channels */
lypinator 0:bb348c97df44 5606 #define DFSDM_FLTAWSR_AWLTF_Pos (0U)
lypinator 0:bb348c97df44 5607 #define DFSDM_FLTAWSR_AWLTF_Msk (0xFU << DFSDM_FLTAWSR_AWLTF_Pos) /*!< 0x0000000F */
lypinator 0:bb348c97df44 5608 #define DFSDM_FLTAWSR_AWLTF DFSDM_FLTAWSR_AWLTF_Msk /*!< AWLTF[7:0] Analog watchdog low threshold error on given channels */
lypinator 0:bb348c97df44 5609
lypinator 0:bb348c97df44 5610 /*************** Bit definition for DFSDM_FLTAWCFR register ******************/
lypinator 0:bb348c97df44 5611 #define DFSDM_FLTAWCFR_CLRAWHTF_Pos (8U)
lypinator 0:bb348c97df44 5612 #define DFSDM_FLTAWCFR_CLRAWHTF_Msk (0xFU << DFSDM_FLTAWCFR_CLRAWHTF_Pos) /*!< 0x00000F00 */
lypinator 0:bb348c97df44 5613 #define DFSDM_FLTAWCFR_CLRAWHTF DFSDM_FLTAWCFR_CLRAWHTF_Msk /*!< CLRAWHTF[15:8] Clear the Analog watchdog high threshold flag */
lypinator 0:bb348c97df44 5614 #define DFSDM_FLTAWCFR_CLRAWLTF_Pos (0U)
lypinator 0:bb348c97df44 5615 #define DFSDM_FLTAWCFR_CLRAWLTF_Msk (0xFU << DFSDM_FLTAWCFR_CLRAWLTF_Pos) /*!< 0x0000000F */
lypinator 0:bb348c97df44 5616 #define DFSDM_FLTAWCFR_CLRAWLTF DFSDM_FLTAWCFR_CLRAWLTF_Msk /*!< CLRAWLTF[7:0] Clear the Analog watchdog low threshold flag */
lypinator 0:bb348c97df44 5617
lypinator 0:bb348c97df44 5618 /*************** Bit definition for DFSDM_FLTEXMAX register ******************/
lypinator 0:bb348c97df44 5619 #define DFSDM_FLTEXMAX_EXMAX_Pos (8U)
lypinator 0:bb348c97df44 5620 #define DFSDM_FLTEXMAX_EXMAX_Msk (0xFFFFFFU << DFSDM_FLTEXMAX_EXMAX_Pos) /*!< 0xFFFFFF00 */
lypinator 0:bb348c97df44 5621 #define DFSDM_FLTEXMAX_EXMAX DFSDM_FLTEXMAX_EXMAX_Msk /*!< EXMAX[23:0] Extreme detector maximum value */
lypinator 0:bb348c97df44 5622 #define DFSDM_FLTEXMAX_EXMAXCH_Pos (0U)
lypinator 0:bb348c97df44 5623 #define DFSDM_FLTEXMAX_EXMAXCH_Msk (0x7U << DFSDM_FLTEXMAX_EXMAXCH_Pos) /*!< 0x00000007 */
lypinator 0:bb348c97df44 5624 #define DFSDM_FLTEXMAX_EXMAXCH DFSDM_FLTEXMAX_EXMAXCH_Msk /*!< EXMAXCH[2:0] Extreme detector maximum data channel */
lypinator 0:bb348c97df44 5625
lypinator 0:bb348c97df44 5626 /*************** Bit definition for DFSDM_FLTEXMIN register ******************/
lypinator 0:bb348c97df44 5627 #define DFSDM_FLTEXMIN_EXMIN_Pos (8U)
lypinator 0:bb348c97df44 5628 #define DFSDM_FLTEXMIN_EXMIN_Msk (0xFFFFFFU << DFSDM_FLTEXMIN_EXMIN_Pos) /*!< 0xFFFFFF00 */
lypinator 0:bb348c97df44 5629 #define DFSDM_FLTEXMIN_EXMIN DFSDM_FLTEXMIN_EXMIN_Msk /*!< EXMIN[23:0] Extreme detector minimum value */
lypinator 0:bb348c97df44 5630 #define DFSDM_FLTEXMIN_EXMINCH_Pos (0U)
lypinator 0:bb348c97df44 5631 #define DFSDM_FLTEXMIN_EXMINCH_Msk (0x7U << DFSDM_FLTEXMIN_EXMINCH_Pos) /*!< 0x00000007 */
lypinator 0:bb348c97df44 5632 #define DFSDM_FLTEXMIN_EXMINCH DFSDM_FLTEXMIN_EXMINCH_Msk /*!< EXMINCH[2:0] Extreme detector minimum data channel */
lypinator 0:bb348c97df44 5633
lypinator 0:bb348c97df44 5634 /*************** Bit definition for DFSDM_FLTCNVTIMR register ****************/
lypinator 0:bb348c97df44 5635 #define DFSDM_FLTCNVTIMR_CNVCNT_Pos (4U)
lypinator 0:bb348c97df44 5636 #define DFSDM_FLTCNVTIMR_CNVCNT_Msk (0xFFFFFFFU << DFSDM_FLTCNVTIMR_CNVCNT_Pos) /*!< 0xFFFFFFF0 */
lypinator 0:bb348c97df44 5637 #define DFSDM_FLTCNVTIMR_CNVCNT DFSDM_FLTCNVTIMR_CNVCNT_Msk /*!< CNVCNT[27:0]: 28-bit timer counting conversion time */
lypinator 0:bb348c97df44 5638
lypinator 0:bb348c97df44 5639 /******************************************************************************/
lypinator 0:bb348c97df44 5640 /* */
lypinator 0:bb348c97df44 5641 /* DMA Controller */
lypinator 0:bb348c97df44 5642 /* */
lypinator 0:bb348c97df44 5643 /******************************************************************************/
lypinator 0:bb348c97df44 5644 /******************** Bits definition for DMA_SxCR register *****************/
lypinator 0:bb348c97df44 5645 #define DMA_SxCR_CHSEL_Pos (25U)
lypinator 0:bb348c97df44 5646 #define DMA_SxCR_CHSEL_Msk (0x7U << DMA_SxCR_CHSEL_Pos) /*!< 0x0E000000 */
lypinator 0:bb348c97df44 5647 #define DMA_SxCR_CHSEL DMA_SxCR_CHSEL_Msk
lypinator 0:bb348c97df44 5648 #define DMA_SxCR_CHSEL_0 0x02000000U
lypinator 0:bb348c97df44 5649 #define DMA_SxCR_CHSEL_1 0x04000000U
lypinator 0:bb348c97df44 5650 #define DMA_SxCR_CHSEL_2 0x08000000U
lypinator 0:bb348c97df44 5651 #define DMA_SxCR_MBURST_Pos (23U)
lypinator 0:bb348c97df44 5652 #define DMA_SxCR_MBURST_Msk (0x3U << DMA_SxCR_MBURST_Pos) /*!< 0x01800000 */
lypinator 0:bb348c97df44 5653 #define DMA_SxCR_MBURST DMA_SxCR_MBURST_Msk
lypinator 0:bb348c97df44 5654 #define DMA_SxCR_MBURST_0 (0x1U << DMA_SxCR_MBURST_Pos) /*!< 0x00800000 */
lypinator 0:bb348c97df44 5655 #define DMA_SxCR_MBURST_1 (0x2U << DMA_SxCR_MBURST_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 5656 #define DMA_SxCR_PBURST_Pos (21U)
lypinator 0:bb348c97df44 5657 #define DMA_SxCR_PBURST_Msk (0x3U << DMA_SxCR_PBURST_Pos) /*!< 0x00600000 */
lypinator 0:bb348c97df44 5658 #define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk
lypinator 0:bb348c97df44 5659 #define DMA_SxCR_PBURST_0 (0x1U << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 5660 #define DMA_SxCR_PBURST_1 (0x2U << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 5661 #define DMA_SxCR_CT_Pos (19U)
lypinator 0:bb348c97df44 5662 #define DMA_SxCR_CT_Msk (0x1U << DMA_SxCR_CT_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 5663 #define DMA_SxCR_CT DMA_SxCR_CT_Msk
lypinator 0:bb348c97df44 5664 #define DMA_SxCR_DBM_Pos (18U)
lypinator 0:bb348c97df44 5665 #define DMA_SxCR_DBM_Msk (0x1U << DMA_SxCR_DBM_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 5666 #define DMA_SxCR_DBM DMA_SxCR_DBM_Msk
lypinator 0:bb348c97df44 5667 #define DMA_SxCR_PL_Pos (16U)
lypinator 0:bb348c97df44 5668 #define DMA_SxCR_PL_Msk (0x3U << DMA_SxCR_PL_Pos) /*!< 0x00030000 */
lypinator 0:bb348c97df44 5669 #define DMA_SxCR_PL DMA_SxCR_PL_Msk
lypinator 0:bb348c97df44 5670 #define DMA_SxCR_PL_0 (0x1U << DMA_SxCR_PL_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 5671 #define DMA_SxCR_PL_1 (0x2U << DMA_SxCR_PL_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 5672 #define DMA_SxCR_PINCOS_Pos (15U)
lypinator 0:bb348c97df44 5673 #define DMA_SxCR_PINCOS_Msk (0x1U << DMA_SxCR_PINCOS_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 5674 #define DMA_SxCR_PINCOS DMA_SxCR_PINCOS_Msk
lypinator 0:bb348c97df44 5675 #define DMA_SxCR_MSIZE_Pos (13U)
lypinator 0:bb348c97df44 5676 #define DMA_SxCR_MSIZE_Msk (0x3U << DMA_SxCR_MSIZE_Pos) /*!< 0x00006000 */
lypinator 0:bb348c97df44 5677 #define DMA_SxCR_MSIZE DMA_SxCR_MSIZE_Msk
lypinator 0:bb348c97df44 5678 #define DMA_SxCR_MSIZE_0 (0x1U << DMA_SxCR_MSIZE_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 5679 #define DMA_SxCR_MSIZE_1 (0x2U << DMA_SxCR_MSIZE_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 5680 #define DMA_SxCR_PSIZE_Pos (11U)
lypinator 0:bb348c97df44 5681 #define DMA_SxCR_PSIZE_Msk (0x3U << DMA_SxCR_PSIZE_Pos) /*!< 0x00001800 */
lypinator 0:bb348c97df44 5682 #define DMA_SxCR_PSIZE DMA_SxCR_PSIZE_Msk
lypinator 0:bb348c97df44 5683 #define DMA_SxCR_PSIZE_0 (0x1U << DMA_SxCR_PSIZE_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 5684 #define DMA_SxCR_PSIZE_1 (0x2U << DMA_SxCR_PSIZE_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 5685 #define DMA_SxCR_MINC_Pos (10U)
lypinator 0:bb348c97df44 5686 #define DMA_SxCR_MINC_Msk (0x1U << DMA_SxCR_MINC_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 5687 #define DMA_SxCR_MINC DMA_SxCR_MINC_Msk
lypinator 0:bb348c97df44 5688 #define DMA_SxCR_PINC_Pos (9U)
lypinator 0:bb348c97df44 5689 #define DMA_SxCR_PINC_Msk (0x1U << DMA_SxCR_PINC_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 5690 #define DMA_SxCR_PINC DMA_SxCR_PINC_Msk
lypinator 0:bb348c97df44 5691 #define DMA_SxCR_CIRC_Pos (8U)
lypinator 0:bb348c97df44 5692 #define DMA_SxCR_CIRC_Msk (0x1U << DMA_SxCR_CIRC_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 5693 #define DMA_SxCR_CIRC DMA_SxCR_CIRC_Msk
lypinator 0:bb348c97df44 5694 #define DMA_SxCR_DIR_Pos (6U)
lypinator 0:bb348c97df44 5695 #define DMA_SxCR_DIR_Msk (0x3U << DMA_SxCR_DIR_Pos) /*!< 0x000000C0 */
lypinator 0:bb348c97df44 5696 #define DMA_SxCR_DIR DMA_SxCR_DIR_Msk
lypinator 0:bb348c97df44 5697 #define DMA_SxCR_DIR_0 (0x1U << DMA_SxCR_DIR_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 5698 #define DMA_SxCR_DIR_1 (0x2U << DMA_SxCR_DIR_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 5699 #define DMA_SxCR_PFCTRL_Pos (5U)
lypinator 0:bb348c97df44 5700 #define DMA_SxCR_PFCTRL_Msk (0x1U << DMA_SxCR_PFCTRL_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 5701 #define DMA_SxCR_PFCTRL DMA_SxCR_PFCTRL_Msk
lypinator 0:bb348c97df44 5702 #define DMA_SxCR_TCIE_Pos (4U)
lypinator 0:bb348c97df44 5703 #define DMA_SxCR_TCIE_Msk (0x1U << DMA_SxCR_TCIE_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 5704 #define DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk
lypinator 0:bb348c97df44 5705 #define DMA_SxCR_HTIE_Pos (3U)
lypinator 0:bb348c97df44 5706 #define DMA_SxCR_HTIE_Msk (0x1U << DMA_SxCR_HTIE_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 5707 #define DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk
lypinator 0:bb348c97df44 5708 #define DMA_SxCR_TEIE_Pos (2U)
lypinator 0:bb348c97df44 5709 #define DMA_SxCR_TEIE_Msk (0x1U << DMA_SxCR_TEIE_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 5710 #define DMA_SxCR_TEIE DMA_SxCR_TEIE_Msk
lypinator 0:bb348c97df44 5711 #define DMA_SxCR_DMEIE_Pos (1U)
lypinator 0:bb348c97df44 5712 #define DMA_SxCR_DMEIE_Msk (0x1U << DMA_SxCR_DMEIE_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 5713 #define DMA_SxCR_DMEIE DMA_SxCR_DMEIE_Msk
lypinator 0:bb348c97df44 5714 #define DMA_SxCR_EN_Pos (0U)
lypinator 0:bb348c97df44 5715 #define DMA_SxCR_EN_Msk (0x1U << DMA_SxCR_EN_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 5716 #define DMA_SxCR_EN DMA_SxCR_EN_Msk
lypinator 0:bb348c97df44 5717
lypinator 0:bb348c97df44 5718 /* Legacy defines */
lypinator 0:bb348c97df44 5719 #define DMA_SxCR_ACK_Pos (20U)
lypinator 0:bb348c97df44 5720 #define DMA_SxCR_ACK_Msk (0x1U << DMA_SxCR_ACK_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 5721 #define DMA_SxCR_ACK DMA_SxCR_ACK_Msk
lypinator 0:bb348c97df44 5722
lypinator 0:bb348c97df44 5723 /******************** Bits definition for DMA_SxCNDTR register **************/
lypinator 0:bb348c97df44 5724 #define DMA_SxNDT_Pos (0U)
lypinator 0:bb348c97df44 5725 #define DMA_SxNDT_Msk (0xFFFFU << DMA_SxNDT_Pos) /*!< 0x0000FFFF */
lypinator 0:bb348c97df44 5726 #define DMA_SxNDT DMA_SxNDT_Msk
lypinator 0:bb348c97df44 5727 #define DMA_SxNDT_0 (0x0001U << DMA_SxNDT_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 5728 #define DMA_SxNDT_1 (0x0002U << DMA_SxNDT_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 5729 #define DMA_SxNDT_2 (0x0004U << DMA_SxNDT_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 5730 #define DMA_SxNDT_3 (0x0008U << DMA_SxNDT_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 5731 #define DMA_SxNDT_4 (0x0010U << DMA_SxNDT_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 5732 #define DMA_SxNDT_5 (0x0020U << DMA_SxNDT_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 5733 #define DMA_SxNDT_6 (0x0040U << DMA_SxNDT_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 5734 #define DMA_SxNDT_7 (0x0080U << DMA_SxNDT_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 5735 #define DMA_SxNDT_8 (0x0100U << DMA_SxNDT_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 5736 #define DMA_SxNDT_9 (0x0200U << DMA_SxNDT_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 5737 #define DMA_SxNDT_10 (0x0400U << DMA_SxNDT_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 5738 #define DMA_SxNDT_11 (0x0800U << DMA_SxNDT_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 5739 #define DMA_SxNDT_12 (0x1000U << DMA_SxNDT_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 5740 #define DMA_SxNDT_13 (0x2000U << DMA_SxNDT_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 5741 #define DMA_SxNDT_14 (0x4000U << DMA_SxNDT_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 5742 #define DMA_SxNDT_15 (0x8000U << DMA_SxNDT_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 5743
lypinator 0:bb348c97df44 5744 /******************** Bits definition for DMA_SxFCR register ****************/
lypinator 0:bb348c97df44 5745 #define DMA_SxFCR_FEIE_Pos (7U)
lypinator 0:bb348c97df44 5746 #define DMA_SxFCR_FEIE_Msk (0x1U << DMA_SxFCR_FEIE_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 5747 #define DMA_SxFCR_FEIE DMA_SxFCR_FEIE_Msk
lypinator 0:bb348c97df44 5748 #define DMA_SxFCR_FS_Pos (3U)
lypinator 0:bb348c97df44 5749 #define DMA_SxFCR_FS_Msk (0x7U << DMA_SxFCR_FS_Pos) /*!< 0x00000038 */
lypinator 0:bb348c97df44 5750 #define DMA_SxFCR_FS DMA_SxFCR_FS_Msk
lypinator 0:bb348c97df44 5751 #define DMA_SxFCR_FS_0 (0x1U << DMA_SxFCR_FS_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 5752 #define DMA_SxFCR_FS_1 (0x2U << DMA_SxFCR_FS_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 5753 #define DMA_SxFCR_FS_2 (0x4U << DMA_SxFCR_FS_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 5754 #define DMA_SxFCR_DMDIS_Pos (2U)
lypinator 0:bb348c97df44 5755 #define DMA_SxFCR_DMDIS_Msk (0x1U << DMA_SxFCR_DMDIS_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 5756 #define DMA_SxFCR_DMDIS DMA_SxFCR_DMDIS_Msk
lypinator 0:bb348c97df44 5757 #define DMA_SxFCR_FTH_Pos (0U)
lypinator 0:bb348c97df44 5758 #define DMA_SxFCR_FTH_Msk (0x3U << DMA_SxFCR_FTH_Pos) /*!< 0x00000003 */
lypinator 0:bb348c97df44 5759 #define DMA_SxFCR_FTH DMA_SxFCR_FTH_Msk
lypinator 0:bb348c97df44 5760 #define DMA_SxFCR_FTH_0 (0x1U << DMA_SxFCR_FTH_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 5761 #define DMA_SxFCR_FTH_1 (0x2U << DMA_SxFCR_FTH_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 5762
lypinator 0:bb348c97df44 5763 /******************** Bits definition for DMA_LISR register *****************/
lypinator 0:bb348c97df44 5764 #define DMA_LISR_TCIF3_Pos (27U)
lypinator 0:bb348c97df44 5765 #define DMA_LISR_TCIF3_Msk (0x1U << DMA_LISR_TCIF3_Pos) /*!< 0x08000000 */
lypinator 0:bb348c97df44 5766 #define DMA_LISR_TCIF3 DMA_LISR_TCIF3_Msk
lypinator 0:bb348c97df44 5767 #define DMA_LISR_HTIF3_Pos (26U)
lypinator 0:bb348c97df44 5768 #define DMA_LISR_HTIF3_Msk (0x1U << DMA_LISR_HTIF3_Pos) /*!< 0x04000000 */
lypinator 0:bb348c97df44 5769 #define DMA_LISR_HTIF3 DMA_LISR_HTIF3_Msk
lypinator 0:bb348c97df44 5770 #define DMA_LISR_TEIF3_Pos (25U)
lypinator 0:bb348c97df44 5771 #define DMA_LISR_TEIF3_Msk (0x1U << DMA_LISR_TEIF3_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 5772 #define DMA_LISR_TEIF3 DMA_LISR_TEIF3_Msk
lypinator 0:bb348c97df44 5773 #define DMA_LISR_DMEIF3_Pos (24U)
lypinator 0:bb348c97df44 5774 #define DMA_LISR_DMEIF3_Msk (0x1U << DMA_LISR_DMEIF3_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 5775 #define DMA_LISR_DMEIF3 DMA_LISR_DMEIF3_Msk
lypinator 0:bb348c97df44 5776 #define DMA_LISR_FEIF3_Pos (22U)
lypinator 0:bb348c97df44 5777 #define DMA_LISR_FEIF3_Msk (0x1U << DMA_LISR_FEIF3_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 5778 #define DMA_LISR_FEIF3 DMA_LISR_FEIF3_Msk
lypinator 0:bb348c97df44 5779 #define DMA_LISR_TCIF2_Pos (21U)
lypinator 0:bb348c97df44 5780 #define DMA_LISR_TCIF2_Msk (0x1U << DMA_LISR_TCIF2_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 5781 #define DMA_LISR_TCIF2 DMA_LISR_TCIF2_Msk
lypinator 0:bb348c97df44 5782 #define DMA_LISR_HTIF2_Pos (20U)
lypinator 0:bb348c97df44 5783 #define DMA_LISR_HTIF2_Msk (0x1U << DMA_LISR_HTIF2_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 5784 #define DMA_LISR_HTIF2 DMA_LISR_HTIF2_Msk
lypinator 0:bb348c97df44 5785 #define DMA_LISR_TEIF2_Pos (19U)
lypinator 0:bb348c97df44 5786 #define DMA_LISR_TEIF2_Msk (0x1U << DMA_LISR_TEIF2_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 5787 #define DMA_LISR_TEIF2 DMA_LISR_TEIF2_Msk
lypinator 0:bb348c97df44 5788 #define DMA_LISR_DMEIF2_Pos (18U)
lypinator 0:bb348c97df44 5789 #define DMA_LISR_DMEIF2_Msk (0x1U << DMA_LISR_DMEIF2_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 5790 #define DMA_LISR_DMEIF2 DMA_LISR_DMEIF2_Msk
lypinator 0:bb348c97df44 5791 #define DMA_LISR_FEIF2_Pos (16U)
lypinator 0:bb348c97df44 5792 #define DMA_LISR_FEIF2_Msk (0x1U << DMA_LISR_FEIF2_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 5793 #define DMA_LISR_FEIF2 DMA_LISR_FEIF2_Msk
lypinator 0:bb348c97df44 5794 #define DMA_LISR_TCIF1_Pos (11U)
lypinator 0:bb348c97df44 5795 #define DMA_LISR_TCIF1_Msk (0x1U << DMA_LISR_TCIF1_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 5796 #define DMA_LISR_TCIF1 DMA_LISR_TCIF1_Msk
lypinator 0:bb348c97df44 5797 #define DMA_LISR_HTIF1_Pos (10U)
lypinator 0:bb348c97df44 5798 #define DMA_LISR_HTIF1_Msk (0x1U << DMA_LISR_HTIF1_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 5799 #define DMA_LISR_HTIF1 DMA_LISR_HTIF1_Msk
lypinator 0:bb348c97df44 5800 #define DMA_LISR_TEIF1_Pos (9U)
lypinator 0:bb348c97df44 5801 #define DMA_LISR_TEIF1_Msk (0x1U << DMA_LISR_TEIF1_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 5802 #define DMA_LISR_TEIF1 DMA_LISR_TEIF1_Msk
lypinator 0:bb348c97df44 5803 #define DMA_LISR_DMEIF1_Pos (8U)
lypinator 0:bb348c97df44 5804 #define DMA_LISR_DMEIF1_Msk (0x1U << DMA_LISR_DMEIF1_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 5805 #define DMA_LISR_DMEIF1 DMA_LISR_DMEIF1_Msk
lypinator 0:bb348c97df44 5806 #define DMA_LISR_FEIF1_Pos (6U)
lypinator 0:bb348c97df44 5807 #define DMA_LISR_FEIF1_Msk (0x1U << DMA_LISR_FEIF1_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 5808 #define DMA_LISR_FEIF1 DMA_LISR_FEIF1_Msk
lypinator 0:bb348c97df44 5809 #define DMA_LISR_TCIF0_Pos (5U)
lypinator 0:bb348c97df44 5810 #define DMA_LISR_TCIF0_Msk (0x1U << DMA_LISR_TCIF0_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 5811 #define DMA_LISR_TCIF0 DMA_LISR_TCIF0_Msk
lypinator 0:bb348c97df44 5812 #define DMA_LISR_HTIF0_Pos (4U)
lypinator 0:bb348c97df44 5813 #define DMA_LISR_HTIF0_Msk (0x1U << DMA_LISR_HTIF0_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 5814 #define DMA_LISR_HTIF0 DMA_LISR_HTIF0_Msk
lypinator 0:bb348c97df44 5815 #define DMA_LISR_TEIF0_Pos (3U)
lypinator 0:bb348c97df44 5816 #define DMA_LISR_TEIF0_Msk (0x1U << DMA_LISR_TEIF0_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 5817 #define DMA_LISR_TEIF0 DMA_LISR_TEIF0_Msk
lypinator 0:bb348c97df44 5818 #define DMA_LISR_DMEIF0_Pos (2U)
lypinator 0:bb348c97df44 5819 #define DMA_LISR_DMEIF0_Msk (0x1U << DMA_LISR_DMEIF0_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 5820 #define DMA_LISR_DMEIF0 DMA_LISR_DMEIF0_Msk
lypinator 0:bb348c97df44 5821 #define DMA_LISR_FEIF0_Pos (0U)
lypinator 0:bb348c97df44 5822 #define DMA_LISR_FEIF0_Msk (0x1U << DMA_LISR_FEIF0_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 5823 #define DMA_LISR_FEIF0 DMA_LISR_FEIF0_Msk
lypinator 0:bb348c97df44 5824
lypinator 0:bb348c97df44 5825 /******************** Bits definition for DMA_HISR register *****************/
lypinator 0:bb348c97df44 5826 #define DMA_HISR_TCIF7_Pos (27U)
lypinator 0:bb348c97df44 5827 #define DMA_HISR_TCIF7_Msk (0x1U << DMA_HISR_TCIF7_Pos) /*!< 0x08000000 */
lypinator 0:bb348c97df44 5828 #define DMA_HISR_TCIF7 DMA_HISR_TCIF7_Msk
lypinator 0:bb348c97df44 5829 #define DMA_HISR_HTIF7_Pos (26U)
lypinator 0:bb348c97df44 5830 #define DMA_HISR_HTIF7_Msk (0x1U << DMA_HISR_HTIF7_Pos) /*!< 0x04000000 */
lypinator 0:bb348c97df44 5831 #define DMA_HISR_HTIF7 DMA_HISR_HTIF7_Msk
lypinator 0:bb348c97df44 5832 #define DMA_HISR_TEIF7_Pos (25U)
lypinator 0:bb348c97df44 5833 #define DMA_HISR_TEIF7_Msk (0x1U << DMA_HISR_TEIF7_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 5834 #define DMA_HISR_TEIF7 DMA_HISR_TEIF7_Msk
lypinator 0:bb348c97df44 5835 #define DMA_HISR_DMEIF7_Pos (24U)
lypinator 0:bb348c97df44 5836 #define DMA_HISR_DMEIF7_Msk (0x1U << DMA_HISR_DMEIF7_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 5837 #define DMA_HISR_DMEIF7 DMA_HISR_DMEIF7_Msk
lypinator 0:bb348c97df44 5838 #define DMA_HISR_FEIF7_Pos (22U)
lypinator 0:bb348c97df44 5839 #define DMA_HISR_FEIF7_Msk (0x1U << DMA_HISR_FEIF7_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 5840 #define DMA_HISR_FEIF7 DMA_HISR_FEIF7_Msk
lypinator 0:bb348c97df44 5841 #define DMA_HISR_TCIF6_Pos (21U)
lypinator 0:bb348c97df44 5842 #define DMA_HISR_TCIF6_Msk (0x1U << DMA_HISR_TCIF6_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 5843 #define DMA_HISR_TCIF6 DMA_HISR_TCIF6_Msk
lypinator 0:bb348c97df44 5844 #define DMA_HISR_HTIF6_Pos (20U)
lypinator 0:bb348c97df44 5845 #define DMA_HISR_HTIF6_Msk (0x1U << DMA_HISR_HTIF6_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 5846 #define DMA_HISR_HTIF6 DMA_HISR_HTIF6_Msk
lypinator 0:bb348c97df44 5847 #define DMA_HISR_TEIF6_Pos (19U)
lypinator 0:bb348c97df44 5848 #define DMA_HISR_TEIF6_Msk (0x1U << DMA_HISR_TEIF6_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 5849 #define DMA_HISR_TEIF6 DMA_HISR_TEIF6_Msk
lypinator 0:bb348c97df44 5850 #define DMA_HISR_DMEIF6_Pos (18U)
lypinator 0:bb348c97df44 5851 #define DMA_HISR_DMEIF6_Msk (0x1U << DMA_HISR_DMEIF6_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 5852 #define DMA_HISR_DMEIF6 DMA_HISR_DMEIF6_Msk
lypinator 0:bb348c97df44 5853 #define DMA_HISR_FEIF6_Pos (16U)
lypinator 0:bb348c97df44 5854 #define DMA_HISR_FEIF6_Msk (0x1U << DMA_HISR_FEIF6_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 5855 #define DMA_HISR_FEIF6 DMA_HISR_FEIF6_Msk
lypinator 0:bb348c97df44 5856 #define DMA_HISR_TCIF5_Pos (11U)
lypinator 0:bb348c97df44 5857 #define DMA_HISR_TCIF5_Msk (0x1U << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 5858 #define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk
lypinator 0:bb348c97df44 5859 #define DMA_HISR_HTIF5_Pos (10U)
lypinator 0:bb348c97df44 5860 #define DMA_HISR_HTIF5_Msk (0x1U << DMA_HISR_HTIF5_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 5861 #define DMA_HISR_HTIF5 DMA_HISR_HTIF5_Msk
lypinator 0:bb348c97df44 5862 #define DMA_HISR_TEIF5_Pos (9U)
lypinator 0:bb348c97df44 5863 #define DMA_HISR_TEIF5_Msk (0x1U << DMA_HISR_TEIF5_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 5864 #define DMA_HISR_TEIF5 DMA_HISR_TEIF5_Msk
lypinator 0:bb348c97df44 5865 #define DMA_HISR_DMEIF5_Pos (8U)
lypinator 0:bb348c97df44 5866 #define DMA_HISR_DMEIF5_Msk (0x1U << DMA_HISR_DMEIF5_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 5867 #define DMA_HISR_DMEIF5 DMA_HISR_DMEIF5_Msk
lypinator 0:bb348c97df44 5868 #define DMA_HISR_FEIF5_Pos (6U)
lypinator 0:bb348c97df44 5869 #define DMA_HISR_FEIF5_Msk (0x1U << DMA_HISR_FEIF5_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 5870 #define DMA_HISR_FEIF5 DMA_HISR_FEIF5_Msk
lypinator 0:bb348c97df44 5871 #define DMA_HISR_TCIF4_Pos (5U)
lypinator 0:bb348c97df44 5872 #define DMA_HISR_TCIF4_Msk (0x1U << DMA_HISR_TCIF4_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 5873 #define DMA_HISR_TCIF4 DMA_HISR_TCIF4_Msk
lypinator 0:bb348c97df44 5874 #define DMA_HISR_HTIF4_Pos (4U)
lypinator 0:bb348c97df44 5875 #define DMA_HISR_HTIF4_Msk (0x1U << DMA_HISR_HTIF4_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 5876 #define DMA_HISR_HTIF4 DMA_HISR_HTIF4_Msk
lypinator 0:bb348c97df44 5877 #define DMA_HISR_TEIF4_Pos (3U)
lypinator 0:bb348c97df44 5878 #define DMA_HISR_TEIF4_Msk (0x1U << DMA_HISR_TEIF4_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 5879 #define DMA_HISR_TEIF4 DMA_HISR_TEIF4_Msk
lypinator 0:bb348c97df44 5880 #define DMA_HISR_DMEIF4_Pos (2U)
lypinator 0:bb348c97df44 5881 #define DMA_HISR_DMEIF4_Msk (0x1U << DMA_HISR_DMEIF4_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 5882 #define DMA_HISR_DMEIF4 DMA_HISR_DMEIF4_Msk
lypinator 0:bb348c97df44 5883 #define DMA_HISR_FEIF4_Pos (0U)
lypinator 0:bb348c97df44 5884 #define DMA_HISR_FEIF4_Msk (0x1U << DMA_HISR_FEIF4_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 5885 #define DMA_HISR_FEIF4 DMA_HISR_FEIF4_Msk
lypinator 0:bb348c97df44 5886
lypinator 0:bb348c97df44 5887 /******************** Bits definition for DMA_LIFCR register ****************/
lypinator 0:bb348c97df44 5888 #define DMA_LIFCR_CTCIF3_Pos (27U)
lypinator 0:bb348c97df44 5889 #define DMA_LIFCR_CTCIF3_Msk (0x1U << DMA_LIFCR_CTCIF3_Pos) /*!< 0x08000000 */
lypinator 0:bb348c97df44 5890 #define DMA_LIFCR_CTCIF3 DMA_LIFCR_CTCIF3_Msk
lypinator 0:bb348c97df44 5891 #define DMA_LIFCR_CHTIF3_Pos (26U)
lypinator 0:bb348c97df44 5892 #define DMA_LIFCR_CHTIF3_Msk (0x1U << DMA_LIFCR_CHTIF3_Pos) /*!< 0x04000000 */
lypinator 0:bb348c97df44 5893 #define DMA_LIFCR_CHTIF3 DMA_LIFCR_CHTIF3_Msk
lypinator 0:bb348c97df44 5894 #define DMA_LIFCR_CTEIF3_Pos (25U)
lypinator 0:bb348c97df44 5895 #define DMA_LIFCR_CTEIF3_Msk (0x1U << DMA_LIFCR_CTEIF3_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 5896 #define DMA_LIFCR_CTEIF3 DMA_LIFCR_CTEIF3_Msk
lypinator 0:bb348c97df44 5897 #define DMA_LIFCR_CDMEIF3_Pos (24U)
lypinator 0:bb348c97df44 5898 #define DMA_LIFCR_CDMEIF3_Msk (0x1U << DMA_LIFCR_CDMEIF3_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 5899 #define DMA_LIFCR_CDMEIF3 DMA_LIFCR_CDMEIF3_Msk
lypinator 0:bb348c97df44 5900 #define DMA_LIFCR_CFEIF3_Pos (22U)
lypinator 0:bb348c97df44 5901 #define DMA_LIFCR_CFEIF3_Msk (0x1U << DMA_LIFCR_CFEIF3_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 5902 #define DMA_LIFCR_CFEIF3 DMA_LIFCR_CFEIF3_Msk
lypinator 0:bb348c97df44 5903 #define DMA_LIFCR_CTCIF2_Pos (21U)
lypinator 0:bb348c97df44 5904 #define DMA_LIFCR_CTCIF2_Msk (0x1U << DMA_LIFCR_CTCIF2_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 5905 #define DMA_LIFCR_CTCIF2 DMA_LIFCR_CTCIF2_Msk
lypinator 0:bb348c97df44 5906 #define DMA_LIFCR_CHTIF2_Pos (20U)
lypinator 0:bb348c97df44 5907 #define DMA_LIFCR_CHTIF2_Msk (0x1U << DMA_LIFCR_CHTIF2_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 5908 #define DMA_LIFCR_CHTIF2 DMA_LIFCR_CHTIF2_Msk
lypinator 0:bb348c97df44 5909 #define DMA_LIFCR_CTEIF2_Pos (19U)
lypinator 0:bb348c97df44 5910 #define DMA_LIFCR_CTEIF2_Msk (0x1U << DMA_LIFCR_CTEIF2_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 5911 #define DMA_LIFCR_CTEIF2 DMA_LIFCR_CTEIF2_Msk
lypinator 0:bb348c97df44 5912 #define DMA_LIFCR_CDMEIF2_Pos (18U)
lypinator 0:bb348c97df44 5913 #define DMA_LIFCR_CDMEIF2_Msk (0x1U << DMA_LIFCR_CDMEIF2_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 5914 #define DMA_LIFCR_CDMEIF2 DMA_LIFCR_CDMEIF2_Msk
lypinator 0:bb348c97df44 5915 #define DMA_LIFCR_CFEIF2_Pos (16U)
lypinator 0:bb348c97df44 5916 #define DMA_LIFCR_CFEIF2_Msk (0x1U << DMA_LIFCR_CFEIF2_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 5917 #define DMA_LIFCR_CFEIF2 DMA_LIFCR_CFEIF2_Msk
lypinator 0:bb348c97df44 5918 #define DMA_LIFCR_CTCIF1_Pos (11U)
lypinator 0:bb348c97df44 5919 #define DMA_LIFCR_CTCIF1_Msk (0x1U << DMA_LIFCR_CTCIF1_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 5920 #define DMA_LIFCR_CTCIF1 DMA_LIFCR_CTCIF1_Msk
lypinator 0:bb348c97df44 5921 #define DMA_LIFCR_CHTIF1_Pos (10U)
lypinator 0:bb348c97df44 5922 #define DMA_LIFCR_CHTIF1_Msk (0x1U << DMA_LIFCR_CHTIF1_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 5923 #define DMA_LIFCR_CHTIF1 DMA_LIFCR_CHTIF1_Msk
lypinator 0:bb348c97df44 5924 #define DMA_LIFCR_CTEIF1_Pos (9U)
lypinator 0:bb348c97df44 5925 #define DMA_LIFCR_CTEIF1_Msk (0x1U << DMA_LIFCR_CTEIF1_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 5926 #define DMA_LIFCR_CTEIF1 DMA_LIFCR_CTEIF1_Msk
lypinator 0:bb348c97df44 5927 #define DMA_LIFCR_CDMEIF1_Pos (8U)
lypinator 0:bb348c97df44 5928 #define DMA_LIFCR_CDMEIF1_Msk (0x1U << DMA_LIFCR_CDMEIF1_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 5929 #define DMA_LIFCR_CDMEIF1 DMA_LIFCR_CDMEIF1_Msk
lypinator 0:bb348c97df44 5930 #define DMA_LIFCR_CFEIF1_Pos (6U)
lypinator 0:bb348c97df44 5931 #define DMA_LIFCR_CFEIF1_Msk (0x1U << DMA_LIFCR_CFEIF1_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 5932 #define DMA_LIFCR_CFEIF1 DMA_LIFCR_CFEIF1_Msk
lypinator 0:bb348c97df44 5933 #define DMA_LIFCR_CTCIF0_Pos (5U)
lypinator 0:bb348c97df44 5934 #define DMA_LIFCR_CTCIF0_Msk (0x1U << DMA_LIFCR_CTCIF0_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 5935 #define DMA_LIFCR_CTCIF0 DMA_LIFCR_CTCIF0_Msk
lypinator 0:bb348c97df44 5936 #define DMA_LIFCR_CHTIF0_Pos (4U)
lypinator 0:bb348c97df44 5937 #define DMA_LIFCR_CHTIF0_Msk (0x1U << DMA_LIFCR_CHTIF0_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 5938 #define DMA_LIFCR_CHTIF0 DMA_LIFCR_CHTIF0_Msk
lypinator 0:bb348c97df44 5939 #define DMA_LIFCR_CTEIF0_Pos (3U)
lypinator 0:bb348c97df44 5940 #define DMA_LIFCR_CTEIF0_Msk (0x1U << DMA_LIFCR_CTEIF0_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 5941 #define DMA_LIFCR_CTEIF0 DMA_LIFCR_CTEIF0_Msk
lypinator 0:bb348c97df44 5942 #define DMA_LIFCR_CDMEIF0_Pos (2U)
lypinator 0:bb348c97df44 5943 #define DMA_LIFCR_CDMEIF0_Msk (0x1U << DMA_LIFCR_CDMEIF0_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 5944 #define DMA_LIFCR_CDMEIF0 DMA_LIFCR_CDMEIF0_Msk
lypinator 0:bb348c97df44 5945 #define DMA_LIFCR_CFEIF0_Pos (0U)
lypinator 0:bb348c97df44 5946 #define DMA_LIFCR_CFEIF0_Msk (0x1U << DMA_LIFCR_CFEIF0_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 5947 #define DMA_LIFCR_CFEIF0 DMA_LIFCR_CFEIF0_Msk
lypinator 0:bb348c97df44 5948
lypinator 0:bb348c97df44 5949 /******************** Bits definition for DMA_HIFCR register ****************/
lypinator 0:bb348c97df44 5950 #define DMA_HIFCR_CTCIF7_Pos (27U)
lypinator 0:bb348c97df44 5951 #define DMA_HIFCR_CTCIF7_Msk (0x1U << DMA_HIFCR_CTCIF7_Pos) /*!< 0x08000000 */
lypinator 0:bb348c97df44 5952 #define DMA_HIFCR_CTCIF7 DMA_HIFCR_CTCIF7_Msk
lypinator 0:bb348c97df44 5953 #define DMA_HIFCR_CHTIF7_Pos (26U)
lypinator 0:bb348c97df44 5954 #define DMA_HIFCR_CHTIF7_Msk (0x1U << DMA_HIFCR_CHTIF7_Pos) /*!< 0x04000000 */
lypinator 0:bb348c97df44 5955 #define DMA_HIFCR_CHTIF7 DMA_HIFCR_CHTIF7_Msk
lypinator 0:bb348c97df44 5956 #define DMA_HIFCR_CTEIF7_Pos (25U)
lypinator 0:bb348c97df44 5957 #define DMA_HIFCR_CTEIF7_Msk (0x1U << DMA_HIFCR_CTEIF7_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 5958 #define DMA_HIFCR_CTEIF7 DMA_HIFCR_CTEIF7_Msk
lypinator 0:bb348c97df44 5959 #define DMA_HIFCR_CDMEIF7_Pos (24U)
lypinator 0:bb348c97df44 5960 #define DMA_HIFCR_CDMEIF7_Msk (0x1U << DMA_HIFCR_CDMEIF7_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 5961 #define DMA_HIFCR_CDMEIF7 DMA_HIFCR_CDMEIF7_Msk
lypinator 0:bb348c97df44 5962 #define DMA_HIFCR_CFEIF7_Pos (22U)
lypinator 0:bb348c97df44 5963 #define DMA_HIFCR_CFEIF7_Msk (0x1U << DMA_HIFCR_CFEIF7_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 5964 #define DMA_HIFCR_CFEIF7 DMA_HIFCR_CFEIF7_Msk
lypinator 0:bb348c97df44 5965 #define DMA_HIFCR_CTCIF6_Pos (21U)
lypinator 0:bb348c97df44 5966 #define DMA_HIFCR_CTCIF6_Msk (0x1U << DMA_HIFCR_CTCIF6_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 5967 #define DMA_HIFCR_CTCIF6 DMA_HIFCR_CTCIF6_Msk
lypinator 0:bb348c97df44 5968 #define DMA_HIFCR_CHTIF6_Pos (20U)
lypinator 0:bb348c97df44 5969 #define DMA_HIFCR_CHTIF6_Msk (0x1U << DMA_HIFCR_CHTIF6_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 5970 #define DMA_HIFCR_CHTIF6 DMA_HIFCR_CHTIF6_Msk
lypinator 0:bb348c97df44 5971 #define DMA_HIFCR_CTEIF6_Pos (19U)
lypinator 0:bb348c97df44 5972 #define DMA_HIFCR_CTEIF6_Msk (0x1U << DMA_HIFCR_CTEIF6_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 5973 #define DMA_HIFCR_CTEIF6 DMA_HIFCR_CTEIF6_Msk
lypinator 0:bb348c97df44 5974 #define DMA_HIFCR_CDMEIF6_Pos (18U)
lypinator 0:bb348c97df44 5975 #define DMA_HIFCR_CDMEIF6_Msk (0x1U << DMA_HIFCR_CDMEIF6_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 5976 #define DMA_HIFCR_CDMEIF6 DMA_HIFCR_CDMEIF6_Msk
lypinator 0:bb348c97df44 5977 #define DMA_HIFCR_CFEIF6_Pos (16U)
lypinator 0:bb348c97df44 5978 #define DMA_HIFCR_CFEIF6_Msk (0x1U << DMA_HIFCR_CFEIF6_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 5979 #define DMA_HIFCR_CFEIF6 DMA_HIFCR_CFEIF6_Msk
lypinator 0:bb348c97df44 5980 #define DMA_HIFCR_CTCIF5_Pos (11U)
lypinator 0:bb348c97df44 5981 #define DMA_HIFCR_CTCIF5_Msk (0x1U << DMA_HIFCR_CTCIF5_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 5982 #define DMA_HIFCR_CTCIF5 DMA_HIFCR_CTCIF5_Msk
lypinator 0:bb348c97df44 5983 #define DMA_HIFCR_CHTIF5_Pos (10U)
lypinator 0:bb348c97df44 5984 #define DMA_HIFCR_CHTIF5_Msk (0x1U << DMA_HIFCR_CHTIF5_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 5985 #define DMA_HIFCR_CHTIF5 DMA_HIFCR_CHTIF5_Msk
lypinator 0:bb348c97df44 5986 #define DMA_HIFCR_CTEIF5_Pos (9U)
lypinator 0:bb348c97df44 5987 #define DMA_HIFCR_CTEIF5_Msk (0x1U << DMA_HIFCR_CTEIF5_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 5988 #define DMA_HIFCR_CTEIF5 DMA_HIFCR_CTEIF5_Msk
lypinator 0:bb348c97df44 5989 #define DMA_HIFCR_CDMEIF5_Pos (8U)
lypinator 0:bb348c97df44 5990 #define DMA_HIFCR_CDMEIF5_Msk (0x1U << DMA_HIFCR_CDMEIF5_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 5991 #define DMA_HIFCR_CDMEIF5 DMA_HIFCR_CDMEIF5_Msk
lypinator 0:bb348c97df44 5992 #define DMA_HIFCR_CFEIF5_Pos (6U)
lypinator 0:bb348c97df44 5993 #define DMA_HIFCR_CFEIF5_Msk (0x1U << DMA_HIFCR_CFEIF5_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 5994 #define DMA_HIFCR_CFEIF5 DMA_HIFCR_CFEIF5_Msk
lypinator 0:bb348c97df44 5995 #define DMA_HIFCR_CTCIF4_Pos (5U)
lypinator 0:bb348c97df44 5996 #define DMA_HIFCR_CTCIF4_Msk (0x1U << DMA_HIFCR_CTCIF4_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 5997 #define DMA_HIFCR_CTCIF4 DMA_HIFCR_CTCIF4_Msk
lypinator 0:bb348c97df44 5998 #define DMA_HIFCR_CHTIF4_Pos (4U)
lypinator 0:bb348c97df44 5999 #define DMA_HIFCR_CHTIF4_Msk (0x1U << DMA_HIFCR_CHTIF4_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 6000 #define DMA_HIFCR_CHTIF4 DMA_HIFCR_CHTIF4_Msk
lypinator 0:bb348c97df44 6001 #define DMA_HIFCR_CTEIF4_Pos (3U)
lypinator 0:bb348c97df44 6002 #define DMA_HIFCR_CTEIF4_Msk (0x1U << DMA_HIFCR_CTEIF4_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 6003 #define DMA_HIFCR_CTEIF4 DMA_HIFCR_CTEIF4_Msk
lypinator 0:bb348c97df44 6004 #define DMA_HIFCR_CDMEIF4_Pos (2U)
lypinator 0:bb348c97df44 6005 #define DMA_HIFCR_CDMEIF4_Msk (0x1U << DMA_HIFCR_CDMEIF4_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 6006 #define DMA_HIFCR_CDMEIF4 DMA_HIFCR_CDMEIF4_Msk
lypinator 0:bb348c97df44 6007 #define DMA_HIFCR_CFEIF4_Pos (0U)
lypinator 0:bb348c97df44 6008 #define DMA_HIFCR_CFEIF4_Msk (0x1U << DMA_HIFCR_CFEIF4_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 6009 #define DMA_HIFCR_CFEIF4 DMA_HIFCR_CFEIF4_Msk
lypinator 0:bb348c97df44 6010
lypinator 0:bb348c97df44 6011 /****************** Bit definition for DMA_SxPAR register ********************/
lypinator 0:bb348c97df44 6012 #define DMA_SxPAR_PA_Pos (0U)
lypinator 0:bb348c97df44 6013 #define DMA_SxPAR_PA_Msk (0xFFFFFFFFU << DMA_SxPAR_PA_Pos) /*!< 0xFFFFFFFF */
lypinator 0:bb348c97df44 6014 #define DMA_SxPAR_PA DMA_SxPAR_PA_Msk /*!< Peripheral Address */
lypinator 0:bb348c97df44 6015
lypinator 0:bb348c97df44 6016 /****************** Bit definition for DMA_SxM0AR register ********************/
lypinator 0:bb348c97df44 6017 #define DMA_SxM0AR_M0A_Pos (0U)
lypinator 0:bb348c97df44 6018 #define DMA_SxM0AR_M0A_Msk (0xFFFFFFFFU << DMA_SxM0AR_M0A_Pos) /*!< 0xFFFFFFFF */
lypinator 0:bb348c97df44 6019 #define DMA_SxM0AR_M0A DMA_SxM0AR_M0A_Msk /*!< Memory Address */
lypinator 0:bb348c97df44 6020
lypinator 0:bb348c97df44 6021 /****************** Bit definition for DMA_SxM1AR register ********************/
lypinator 0:bb348c97df44 6022 #define DMA_SxM1AR_M1A_Pos (0U)
lypinator 0:bb348c97df44 6023 #define DMA_SxM1AR_M1A_Msk (0xFFFFFFFFU << DMA_SxM1AR_M1A_Pos) /*!< 0xFFFFFFFF */
lypinator 0:bb348c97df44 6024 #define DMA_SxM1AR_M1A DMA_SxM1AR_M1A_Msk /*!< Memory Address */
lypinator 0:bb348c97df44 6025
lypinator 0:bb348c97df44 6026
lypinator 0:bb348c97df44 6027 /******************************************************************************/
lypinator 0:bb348c97df44 6028 /* */
lypinator 0:bb348c97df44 6029 /* External Interrupt/Event Controller */
lypinator 0:bb348c97df44 6030 /* */
lypinator 0:bb348c97df44 6031 /******************************************************************************/
lypinator 0:bb348c97df44 6032 /******************* Bit definition for EXTI_IMR register *******************/
lypinator 0:bb348c97df44 6033 #define EXTI_IMR_MR0_Pos (0U)
lypinator 0:bb348c97df44 6034 #define EXTI_IMR_MR0_Msk (0x1U << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 6035 #define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */
lypinator 0:bb348c97df44 6036 #define EXTI_IMR_MR1_Pos (1U)
lypinator 0:bb348c97df44 6037 #define EXTI_IMR_MR1_Msk (0x1U << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 6038 #define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */
lypinator 0:bb348c97df44 6039 #define EXTI_IMR_MR2_Pos (2U)
lypinator 0:bb348c97df44 6040 #define EXTI_IMR_MR2_Msk (0x1U << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 6041 #define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */
lypinator 0:bb348c97df44 6042 #define EXTI_IMR_MR3_Pos (3U)
lypinator 0:bb348c97df44 6043 #define EXTI_IMR_MR3_Msk (0x1U << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 6044 #define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */
lypinator 0:bb348c97df44 6045 #define EXTI_IMR_MR4_Pos (4U)
lypinator 0:bb348c97df44 6046 #define EXTI_IMR_MR4_Msk (0x1U << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 6047 #define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */
lypinator 0:bb348c97df44 6048 #define EXTI_IMR_MR5_Pos (5U)
lypinator 0:bb348c97df44 6049 #define EXTI_IMR_MR5_Msk (0x1U << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 6050 #define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */
lypinator 0:bb348c97df44 6051 #define EXTI_IMR_MR6_Pos (6U)
lypinator 0:bb348c97df44 6052 #define EXTI_IMR_MR6_Msk (0x1U << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 6053 #define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */
lypinator 0:bb348c97df44 6054 #define EXTI_IMR_MR7_Pos (7U)
lypinator 0:bb348c97df44 6055 #define EXTI_IMR_MR7_Msk (0x1U << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 6056 #define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */
lypinator 0:bb348c97df44 6057 #define EXTI_IMR_MR8_Pos (8U)
lypinator 0:bb348c97df44 6058 #define EXTI_IMR_MR8_Msk (0x1U << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 6059 #define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */
lypinator 0:bb348c97df44 6060 #define EXTI_IMR_MR9_Pos (9U)
lypinator 0:bb348c97df44 6061 #define EXTI_IMR_MR9_Msk (0x1U << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 6062 #define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */
lypinator 0:bb348c97df44 6063 #define EXTI_IMR_MR10_Pos (10U)
lypinator 0:bb348c97df44 6064 #define EXTI_IMR_MR10_Msk (0x1U << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 6065 #define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */
lypinator 0:bb348c97df44 6066 #define EXTI_IMR_MR11_Pos (11U)
lypinator 0:bb348c97df44 6067 #define EXTI_IMR_MR11_Msk (0x1U << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 6068 #define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */
lypinator 0:bb348c97df44 6069 #define EXTI_IMR_MR12_Pos (12U)
lypinator 0:bb348c97df44 6070 #define EXTI_IMR_MR12_Msk (0x1U << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 6071 #define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */
lypinator 0:bb348c97df44 6072 #define EXTI_IMR_MR13_Pos (13U)
lypinator 0:bb348c97df44 6073 #define EXTI_IMR_MR13_Msk (0x1U << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 6074 #define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */
lypinator 0:bb348c97df44 6075 #define EXTI_IMR_MR14_Pos (14U)
lypinator 0:bb348c97df44 6076 #define EXTI_IMR_MR14_Msk (0x1U << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 6077 #define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */
lypinator 0:bb348c97df44 6078 #define EXTI_IMR_MR15_Pos (15U)
lypinator 0:bb348c97df44 6079 #define EXTI_IMR_MR15_Msk (0x1U << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 6080 #define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */
lypinator 0:bb348c97df44 6081 #define EXTI_IMR_MR16_Pos (16U)
lypinator 0:bb348c97df44 6082 #define EXTI_IMR_MR16_Msk (0x1U << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 6083 #define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */
lypinator 0:bb348c97df44 6084 #define EXTI_IMR_MR17_Pos (17U)
lypinator 0:bb348c97df44 6085 #define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 6086 #define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */
lypinator 0:bb348c97df44 6087 #define EXTI_IMR_MR18_Pos (18U)
lypinator 0:bb348c97df44 6088 #define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 6089 #define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */
lypinator 0:bb348c97df44 6090 #define EXTI_IMR_MR19_Pos (19U)
lypinator 0:bb348c97df44 6091 #define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 6092 #define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */
lypinator 0:bb348c97df44 6093 #define EXTI_IMR_MR20_Pos (20U)
lypinator 0:bb348c97df44 6094 #define EXTI_IMR_MR20_Msk (0x1U << EXTI_IMR_MR20_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 6095 #define EXTI_IMR_MR20 EXTI_IMR_MR20_Msk /*!< Interrupt Mask on line 20 */
lypinator 0:bb348c97df44 6096 #define EXTI_IMR_MR21_Pos (21U)
lypinator 0:bb348c97df44 6097 #define EXTI_IMR_MR21_Msk (0x1U << EXTI_IMR_MR21_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 6098 #define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk /*!< Interrupt Mask on line 21 */
lypinator 0:bb348c97df44 6099 #define EXTI_IMR_MR22_Pos (22U)
lypinator 0:bb348c97df44 6100 #define EXTI_IMR_MR22_Msk (0x1U << EXTI_IMR_MR22_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 6101 #define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk /*!< Interrupt Mask on line 22 */
lypinator 0:bb348c97df44 6102
lypinator 0:bb348c97df44 6103 /* Reference Defines */
lypinator 0:bb348c97df44 6104 #define EXTI_IMR_IM0 EXTI_IMR_MR0
lypinator 0:bb348c97df44 6105 #define EXTI_IMR_IM1 EXTI_IMR_MR1
lypinator 0:bb348c97df44 6106 #define EXTI_IMR_IM2 EXTI_IMR_MR2
lypinator 0:bb348c97df44 6107 #define EXTI_IMR_IM3 EXTI_IMR_MR3
lypinator 0:bb348c97df44 6108 #define EXTI_IMR_IM4 EXTI_IMR_MR4
lypinator 0:bb348c97df44 6109 #define EXTI_IMR_IM5 EXTI_IMR_MR5
lypinator 0:bb348c97df44 6110 #define EXTI_IMR_IM6 EXTI_IMR_MR6
lypinator 0:bb348c97df44 6111 #define EXTI_IMR_IM7 EXTI_IMR_MR7
lypinator 0:bb348c97df44 6112 #define EXTI_IMR_IM8 EXTI_IMR_MR8
lypinator 0:bb348c97df44 6113 #define EXTI_IMR_IM9 EXTI_IMR_MR9
lypinator 0:bb348c97df44 6114 #define EXTI_IMR_IM10 EXTI_IMR_MR10
lypinator 0:bb348c97df44 6115 #define EXTI_IMR_IM11 EXTI_IMR_MR11
lypinator 0:bb348c97df44 6116 #define EXTI_IMR_IM12 EXTI_IMR_MR12
lypinator 0:bb348c97df44 6117 #define EXTI_IMR_IM13 EXTI_IMR_MR13
lypinator 0:bb348c97df44 6118 #define EXTI_IMR_IM14 EXTI_IMR_MR14
lypinator 0:bb348c97df44 6119 #define EXTI_IMR_IM15 EXTI_IMR_MR15
lypinator 0:bb348c97df44 6120 #define EXTI_IMR_IM16 EXTI_IMR_MR16
lypinator 0:bb348c97df44 6121 #define EXTI_IMR_IM17 EXTI_IMR_MR17
lypinator 0:bb348c97df44 6122 #define EXTI_IMR_IM18 EXTI_IMR_MR18
lypinator 0:bb348c97df44 6123 #define EXTI_IMR_IM19 EXTI_IMR_MR19
lypinator 0:bb348c97df44 6124 #define EXTI_IMR_IM20 EXTI_IMR_MR20
lypinator 0:bb348c97df44 6125 #define EXTI_IMR_IM21 EXTI_IMR_MR21
lypinator 0:bb348c97df44 6126 #define EXTI_IMR_IM22 EXTI_IMR_MR22
lypinator 0:bb348c97df44 6127 #define EXTI_IMR_IM_Pos (0U)
lypinator 0:bb348c97df44 6128 #define EXTI_IMR_IM_Msk (0x7FFFFFU << EXTI_IMR_IM_Pos) /*!< 0x007FFFFF */
lypinator 0:bb348c97df44 6129 #define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */
lypinator 0:bb348c97df44 6130
lypinator 0:bb348c97df44 6131 /******************* Bit definition for EXTI_EMR register *******************/
lypinator 0:bb348c97df44 6132 #define EXTI_EMR_MR0_Pos (0U)
lypinator 0:bb348c97df44 6133 #define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 6134 #define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */
lypinator 0:bb348c97df44 6135 #define EXTI_EMR_MR1_Pos (1U)
lypinator 0:bb348c97df44 6136 #define EXTI_EMR_MR1_Msk (0x1U << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 6137 #define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */
lypinator 0:bb348c97df44 6138 #define EXTI_EMR_MR2_Pos (2U)
lypinator 0:bb348c97df44 6139 #define EXTI_EMR_MR2_Msk (0x1U << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 6140 #define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */
lypinator 0:bb348c97df44 6141 #define EXTI_EMR_MR3_Pos (3U)
lypinator 0:bb348c97df44 6142 #define EXTI_EMR_MR3_Msk (0x1U << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 6143 #define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */
lypinator 0:bb348c97df44 6144 #define EXTI_EMR_MR4_Pos (4U)
lypinator 0:bb348c97df44 6145 #define EXTI_EMR_MR4_Msk (0x1U << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 6146 #define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */
lypinator 0:bb348c97df44 6147 #define EXTI_EMR_MR5_Pos (5U)
lypinator 0:bb348c97df44 6148 #define EXTI_EMR_MR5_Msk (0x1U << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 6149 #define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */
lypinator 0:bb348c97df44 6150 #define EXTI_EMR_MR6_Pos (6U)
lypinator 0:bb348c97df44 6151 #define EXTI_EMR_MR6_Msk (0x1U << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 6152 #define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */
lypinator 0:bb348c97df44 6153 #define EXTI_EMR_MR7_Pos (7U)
lypinator 0:bb348c97df44 6154 #define EXTI_EMR_MR7_Msk (0x1U << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 6155 #define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */
lypinator 0:bb348c97df44 6156 #define EXTI_EMR_MR8_Pos (8U)
lypinator 0:bb348c97df44 6157 #define EXTI_EMR_MR8_Msk (0x1U << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 6158 #define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */
lypinator 0:bb348c97df44 6159 #define EXTI_EMR_MR9_Pos (9U)
lypinator 0:bb348c97df44 6160 #define EXTI_EMR_MR9_Msk (0x1U << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 6161 #define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */
lypinator 0:bb348c97df44 6162 #define EXTI_EMR_MR10_Pos (10U)
lypinator 0:bb348c97df44 6163 #define EXTI_EMR_MR10_Msk (0x1U << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 6164 #define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */
lypinator 0:bb348c97df44 6165 #define EXTI_EMR_MR11_Pos (11U)
lypinator 0:bb348c97df44 6166 #define EXTI_EMR_MR11_Msk (0x1U << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 6167 #define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */
lypinator 0:bb348c97df44 6168 #define EXTI_EMR_MR12_Pos (12U)
lypinator 0:bb348c97df44 6169 #define EXTI_EMR_MR12_Msk (0x1U << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 6170 #define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */
lypinator 0:bb348c97df44 6171 #define EXTI_EMR_MR13_Pos (13U)
lypinator 0:bb348c97df44 6172 #define EXTI_EMR_MR13_Msk (0x1U << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 6173 #define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */
lypinator 0:bb348c97df44 6174 #define EXTI_EMR_MR14_Pos (14U)
lypinator 0:bb348c97df44 6175 #define EXTI_EMR_MR14_Msk (0x1U << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 6176 #define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */
lypinator 0:bb348c97df44 6177 #define EXTI_EMR_MR15_Pos (15U)
lypinator 0:bb348c97df44 6178 #define EXTI_EMR_MR15_Msk (0x1U << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 6179 #define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */
lypinator 0:bb348c97df44 6180 #define EXTI_EMR_MR16_Pos (16U)
lypinator 0:bb348c97df44 6181 #define EXTI_EMR_MR16_Msk (0x1U << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 6182 #define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */
lypinator 0:bb348c97df44 6183 #define EXTI_EMR_MR17_Pos (17U)
lypinator 0:bb348c97df44 6184 #define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 6185 #define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */
lypinator 0:bb348c97df44 6186 #define EXTI_EMR_MR18_Pos (18U)
lypinator 0:bb348c97df44 6187 #define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 6188 #define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */
lypinator 0:bb348c97df44 6189 #define EXTI_EMR_MR19_Pos (19U)
lypinator 0:bb348c97df44 6190 #define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 6191 #define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */
lypinator 0:bb348c97df44 6192 #define EXTI_EMR_MR20_Pos (20U)
lypinator 0:bb348c97df44 6193 #define EXTI_EMR_MR20_Msk (0x1U << EXTI_EMR_MR20_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 6194 #define EXTI_EMR_MR20 EXTI_EMR_MR20_Msk /*!< Event Mask on line 20 */
lypinator 0:bb348c97df44 6195 #define EXTI_EMR_MR21_Pos (21U)
lypinator 0:bb348c97df44 6196 #define EXTI_EMR_MR21_Msk (0x1U << EXTI_EMR_MR21_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 6197 #define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk /*!< Event Mask on line 21 */
lypinator 0:bb348c97df44 6198 #define EXTI_EMR_MR22_Pos (22U)
lypinator 0:bb348c97df44 6199 #define EXTI_EMR_MR22_Msk (0x1U << EXTI_EMR_MR22_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 6200 #define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk /*!< Event Mask on line 22 */
lypinator 0:bb348c97df44 6201
lypinator 0:bb348c97df44 6202 /* Reference Defines */
lypinator 0:bb348c97df44 6203 #define EXTI_EMR_EM0 EXTI_EMR_MR0
lypinator 0:bb348c97df44 6204 #define EXTI_EMR_EM1 EXTI_EMR_MR1
lypinator 0:bb348c97df44 6205 #define EXTI_EMR_EM2 EXTI_EMR_MR2
lypinator 0:bb348c97df44 6206 #define EXTI_EMR_EM3 EXTI_EMR_MR3
lypinator 0:bb348c97df44 6207 #define EXTI_EMR_EM4 EXTI_EMR_MR4
lypinator 0:bb348c97df44 6208 #define EXTI_EMR_EM5 EXTI_EMR_MR5
lypinator 0:bb348c97df44 6209 #define EXTI_EMR_EM6 EXTI_EMR_MR6
lypinator 0:bb348c97df44 6210 #define EXTI_EMR_EM7 EXTI_EMR_MR7
lypinator 0:bb348c97df44 6211 #define EXTI_EMR_EM8 EXTI_EMR_MR8
lypinator 0:bb348c97df44 6212 #define EXTI_EMR_EM9 EXTI_EMR_MR9
lypinator 0:bb348c97df44 6213 #define EXTI_EMR_EM10 EXTI_EMR_MR10
lypinator 0:bb348c97df44 6214 #define EXTI_EMR_EM11 EXTI_EMR_MR11
lypinator 0:bb348c97df44 6215 #define EXTI_EMR_EM12 EXTI_EMR_MR12
lypinator 0:bb348c97df44 6216 #define EXTI_EMR_EM13 EXTI_EMR_MR13
lypinator 0:bb348c97df44 6217 #define EXTI_EMR_EM14 EXTI_EMR_MR14
lypinator 0:bb348c97df44 6218 #define EXTI_EMR_EM15 EXTI_EMR_MR15
lypinator 0:bb348c97df44 6219 #define EXTI_EMR_EM16 EXTI_EMR_MR16
lypinator 0:bb348c97df44 6220 #define EXTI_EMR_EM17 EXTI_EMR_MR17
lypinator 0:bb348c97df44 6221 #define EXTI_EMR_EM18 EXTI_EMR_MR18
lypinator 0:bb348c97df44 6222 #define EXTI_EMR_EM19 EXTI_EMR_MR19
lypinator 0:bb348c97df44 6223 #define EXTI_EMR_EM20 EXTI_EMR_MR20
lypinator 0:bb348c97df44 6224 #define EXTI_EMR_EM21 EXTI_EMR_MR21
lypinator 0:bb348c97df44 6225 #define EXTI_EMR_EM22 EXTI_EMR_MR22
lypinator 0:bb348c97df44 6226
lypinator 0:bb348c97df44 6227 /****************** Bit definition for EXTI_RTSR register *******************/
lypinator 0:bb348c97df44 6228 #define EXTI_RTSR_TR0_Pos (0U)
lypinator 0:bb348c97df44 6229 #define EXTI_RTSR_TR0_Msk (0x1U << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 6230 #define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */
lypinator 0:bb348c97df44 6231 #define EXTI_RTSR_TR1_Pos (1U)
lypinator 0:bb348c97df44 6232 #define EXTI_RTSR_TR1_Msk (0x1U << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 6233 #define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */
lypinator 0:bb348c97df44 6234 #define EXTI_RTSR_TR2_Pos (2U)
lypinator 0:bb348c97df44 6235 #define EXTI_RTSR_TR2_Msk (0x1U << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 6236 #define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */
lypinator 0:bb348c97df44 6237 #define EXTI_RTSR_TR3_Pos (3U)
lypinator 0:bb348c97df44 6238 #define EXTI_RTSR_TR3_Msk (0x1U << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 6239 #define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */
lypinator 0:bb348c97df44 6240 #define EXTI_RTSR_TR4_Pos (4U)
lypinator 0:bb348c97df44 6241 #define EXTI_RTSR_TR4_Msk (0x1U << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 6242 #define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */
lypinator 0:bb348c97df44 6243 #define EXTI_RTSR_TR5_Pos (5U)
lypinator 0:bb348c97df44 6244 #define EXTI_RTSR_TR5_Msk (0x1U << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 6245 #define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */
lypinator 0:bb348c97df44 6246 #define EXTI_RTSR_TR6_Pos (6U)
lypinator 0:bb348c97df44 6247 #define EXTI_RTSR_TR6_Msk (0x1U << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 6248 #define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */
lypinator 0:bb348c97df44 6249 #define EXTI_RTSR_TR7_Pos (7U)
lypinator 0:bb348c97df44 6250 #define EXTI_RTSR_TR7_Msk (0x1U << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 6251 #define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */
lypinator 0:bb348c97df44 6252 #define EXTI_RTSR_TR8_Pos (8U)
lypinator 0:bb348c97df44 6253 #define EXTI_RTSR_TR8_Msk (0x1U << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 6254 #define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */
lypinator 0:bb348c97df44 6255 #define EXTI_RTSR_TR9_Pos (9U)
lypinator 0:bb348c97df44 6256 #define EXTI_RTSR_TR9_Msk (0x1U << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 6257 #define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */
lypinator 0:bb348c97df44 6258 #define EXTI_RTSR_TR10_Pos (10U)
lypinator 0:bb348c97df44 6259 #define EXTI_RTSR_TR10_Msk (0x1U << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 6260 #define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */
lypinator 0:bb348c97df44 6261 #define EXTI_RTSR_TR11_Pos (11U)
lypinator 0:bb348c97df44 6262 #define EXTI_RTSR_TR11_Msk (0x1U << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 6263 #define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */
lypinator 0:bb348c97df44 6264 #define EXTI_RTSR_TR12_Pos (12U)
lypinator 0:bb348c97df44 6265 #define EXTI_RTSR_TR12_Msk (0x1U << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 6266 #define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */
lypinator 0:bb348c97df44 6267 #define EXTI_RTSR_TR13_Pos (13U)
lypinator 0:bb348c97df44 6268 #define EXTI_RTSR_TR13_Msk (0x1U << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 6269 #define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */
lypinator 0:bb348c97df44 6270 #define EXTI_RTSR_TR14_Pos (14U)
lypinator 0:bb348c97df44 6271 #define EXTI_RTSR_TR14_Msk (0x1U << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 6272 #define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */
lypinator 0:bb348c97df44 6273 #define EXTI_RTSR_TR15_Pos (15U)
lypinator 0:bb348c97df44 6274 #define EXTI_RTSR_TR15_Msk (0x1U << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 6275 #define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */
lypinator 0:bb348c97df44 6276 #define EXTI_RTSR_TR16_Pos (16U)
lypinator 0:bb348c97df44 6277 #define EXTI_RTSR_TR16_Msk (0x1U << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 6278 #define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */
lypinator 0:bb348c97df44 6279 #define EXTI_RTSR_TR17_Pos (17U)
lypinator 0:bb348c97df44 6280 #define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 6281 #define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */
lypinator 0:bb348c97df44 6282 #define EXTI_RTSR_TR18_Pos (18U)
lypinator 0:bb348c97df44 6283 #define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 6284 #define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */
lypinator 0:bb348c97df44 6285 #define EXTI_RTSR_TR19_Pos (19U)
lypinator 0:bb348c97df44 6286 #define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 6287 #define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */
lypinator 0:bb348c97df44 6288 #define EXTI_RTSR_TR20_Pos (20U)
lypinator 0:bb348c97df44 6289 #define EXTI_RTSR_TR20_Msk (0x1U << EXTI_RTSR_TR20_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 6290 #define EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk /*!< Rising trigger event configuration bit of line 20 */
lypinator 0:bb348c97df44 6291 #define EXTI_RTSR_TR21_Pos (21U)
lypinator 0:bb348c97df44 6292 #define EXTI_RTSR_TR21_Msk (0x1U << EXTI_RTSR_TR21_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 6293 #define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk /*!< Rising trigger event configuration bit of line 21 */
lypinator 0:bb348c97df44 6294 #define EXTI_RTSR_TR22_Pos (22U)
lypinator 0:bb348c97df44 6295 #define EXTI_RTSR_TR22_Msk (0x1U << EXTI_RTSR_TR22_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 6296 #define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk /*!< Rising trigger event configuration bit of line 22 */
lypinator 0:bb348c97df44 6297
lypinator 0:bb348c97df44 6298 /****************** Bit definition for EXTI_FTSR register *******************/
lypinator 0:bb348c97df44 6299 #define EXTI_FTSR_TR0_Pos (0U)
lypinator 0:bb348c97df44 6300 #define EXTI_FTSR_TR0_Msk (0x1U << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 6301 #define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */
lypinator 0:bb348c97df44 6302 #define EXTI_FTSR_TR1_Pos (1U)
lypinator 0:bb348c97df44 6303 #define EXTI_FTSR_TR1_Msk (0x1U << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 6304 #define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */
lypinator 0:bb348c97df44 6305 #define EXTI_FTSR_TR2_Pos (2U)
lypinator 0:bb348c97df44 6306 #define EXTI_FTSR_TR2_Msk (0x1U << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 6307 #define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */
lypinator 0:bb348c97df44 6308 #define EXTI_FTSR_TR3_Pos (3U)
lypinator 0:bb348c97df44 6309 #define EXTI_FTSR_TR3_Msk (0x1U << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 6310 #define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */
lypinator 0:bb348c97df44 6311 #define EXTI_FTSR_TR4_Pos (4U)
lypinator 0:bb348c97df44 6312 #define EXTI_FTSR_TR4_Msk (0x1U << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 6313 #define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */
lypinator 0:bb348c97df44 6314 #define EXTI_FTSR_TR5_Pos (5U)
lypinator 0:bb348c97df44 6315 #define EXTI_FTSR_TR5_Msk (0x1U << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 6316 #define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */
lypinator 0:bb348c97df44 6317 #define EXTI_FTSR_TR6_Pos (6U)
lypinator 0:bb348c97df44 6318 #define EXTI_FTSR_TR6_Msk (0x1U << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 6319 #define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */
lypinator 0:bb348c97df44 6320 #define EXTI_FTSR_TR7_Pos (7U)
lypinator 0:bb348c97df44 6321 #define EXTI_FTSR_TR7_Msk (0x1U << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 6322 #define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */
lypinator 0:bb348c97df44 6323 #define EXTI_FTSR_TR8_Pos (8U)
lypinator 0:bb348c97df44 6324 #define EXTI_FTSR_TR8_Msk (0x1U << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 6325 #define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */
lypinator 0:bb348c97df44 6326 #define EXTI_FTSR_TR9_Pos (9U)
lypinator 0:bb348c97df44 6327 #define EXTI_FTSR_TR9_Msk (0x1U << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 6328 #define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */
lypinator 0:bb348c97df44 6329 #define EXTI_FTSR_TR10_Pos (10U)
lypinator 0:bb348c97df44 6330 #define EXTI_FTSR_TR10_Msk (0x1U << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 6331 #define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */
lypinator 0:bb348c97df44 6332 #define EXTI_FTSR_TR11_Pos (11U)
lypinator 0:bb348c97df44 6333 #define EXTI_FTSR_TR11_Msk (0x1U << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 6334 #define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */
lypinator 0:bb348c97df44 6335 #define EXTI_FTSR_TR12_Pos (12U)
lypinator 0:bb348c97df44 6336 #define EXTI_FTSR_TR12_Msk (0x1U << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 6337 #define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */
lypinator 0:bb348c97df44 6338 #define EXTI_FTSR_TR13_Pos (13U)
lypinator 0:bb348c97df44 6339 #define EXTI_FTSR_TR13_Msk (0x1U << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 6340 #define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */
lypinator 0:bb348c97df44 6341 #define EXTI_FTSR_TR14_Pos (14U)
lypinator 0:bb348c97df44 6342 #define EXTI_FTSR_TR14_Msk (0x1U << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 6343 #define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */
lypinator 0:bb348c97df44 6344 #define EXTI_FTSR_TR15_Pos (15U)
lypinator 0:bb348c97df44 6345 #define EXTI_FTSR_TR15_Msk (0x1U << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 6346 #define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */
lypinator 0:bb348c97df44 6347 #define EXTI_FTSR_TR16_Pos (16U)
lypinator 0:bb348c97df44 6348 #define EXTI_FTSR_TR16_Msk (0x1U << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 6349 #define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */
lypinator 0:bb348c97df44 6350 #define EXTI_FTSR_TR17_Pos (17U)
lypinator 0:bb348c97df44 6351 #define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 6352 #define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */
lypinator 0:bb348c97df44 6353 #define EXTI_FTSR_TR18_Pos (18U)
lypinator 0:bb348c97df44 6354 #define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 6355 #define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */
lypinator 0:bb348c97df44 6356 #define EXTI_FTSR_TR19_Pos (19U)
lypinator 0:bb348c97df44 6357 #define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 6358 #define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */
lypinator 0:bb348c97df44 6359 #define EXTI_FTSR_TR20_Pos (20U)
lypinator 0:bb348c97df44 6360 #define EXTI_FTSR_TR20_Msk (0x1U << EXTI_FTSR_TR20_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 6361 #define EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk /*!< Falling trigger event configuration bit of line 20 */
lypinator 0:bb348c97df44 6362 #define EXTI_FTSR_TR21_Pos (21U)
lypinator 0:bb348c97df44 6363 #define EXTI_FTSR_TR21_Msk (0x1U << EXTI_FTSR_TR21_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 6364 #define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk /*!< Falling trigger event configuration bit of line 21 */
lypinator 0:bb348c97df44 6365 #define EXTI_FTSR_TR22_Pos (22U)
lypinator 0:bb348c97df44 6366 #define EXTI_FTSR_TR22_Msk (0x1U << EXTI_FTSR_TR22_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 6367 #define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk /*!< Falling trigger event configuration bit of line 22 */
lypinator 0:bb348c97df44 6368
lypinator 0:bb348c97df44 6369 /****************** Bit definition for EXTI_SWIER register ******************/
lypinator 0:bb348c97df44 6370 #define EXTI_SWIER_SWIER0_Pos (0U)
lypinator 0:bb348c97df44 6371 #define EXTI_SWIER_SWIER0_Msk (0x1U << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 6372 #define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */
lypinator 0:bb348c97df44 6373 #define EXTI_SWIER_SWIER1_Pos (1U)
lypinator 0:bb348c97df44 6374 #define EXTI_SWIER_SWIER1_Msk (0x1U << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 6375 #define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */
lypinator 0:bb348c97df44 6376 #define EXTI_SWIER_SWIER2_Pos (2U)
lypinator 0:bb348c97df44 6377 #define EXTI_SWIER_SWIER2_Msk (0x1U << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 6378 #define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */
lypinator 0:bb348c97df44 6379 #define EXTI_SWIER_SWIER3_Pos (3U)
lypinator 0:bb348c97df44 6380 #define EXTI_SWIER_SWIER3_Msk (0x1U << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 6381 #define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */
lypinator 0:bb348c97df44 6382 #define EXTI_SWIER_SWIER4_Pos (4U)
lypinator 0:bb348c97df44 6383 #define EXTI_SWIER_SWIER4_Msk (0x1U << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 6384 #define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */
lypinator 0:bb348c97df44 6385 #define EXTI_SWIER_SWIER5_Pos (5U)
lypinator 0:bb348c97df44 6386 #define EXTI_SWIER_SWIER5_Msk (0x1U << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 6387 #define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */
lypinator 0:bb348c97df44 6388 #define EXTI_SWIER_SWIER6_Pos (6U)
lypinator 0:bb348c97df44 6389 #define EXTI_SWIER_SWIER6_Msk (0x1U << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 6390 #define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */
lypinator 0:bb348c97df44 6391 #define EXTI_SWIER_SWIER7_Pos (7U)
lypinator 0:bb348c97df44 6392 #define EXTI_SWIER_SWIER7_Msk (0x1U << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 6393 #define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */
lypinator 0:bb348c97df44 6394 #define EXTI_SWIER_SWIER8_Pos (8U)
lypinator 0:bb348c97df44 6395 #define EXTI_SWIER_SWIER8_Msk (0x1U << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 6396 #define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */
lypinator 0:bb348c97df44 6397 #define EXTI_SWIER_SWIER9_Pos (9U)
lypinator 0:bb348c97df44 6398 #define EXTI_SWIER_SWIER9_Msk (0x1U << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 6399 #define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */
lypinator 0:bb348c97df44 6400 #define EXTI_SWIER_SWIER10_Pos (10U)
lypinator 0:bb348c97df44 6401 #define EXTI_SWIER_SWIER10_Msk (0x1U << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 6402 #define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */
lypinator 0:bb348c97df44 6403 #define EXTI_SWIER_SWIER11_Pos (11U)
lypinator 0:bb348c97df44 6404 #define EXTI_SWIER_SWIER11_Msk (0x1U << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 6405 #define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */
lypinator 0:bb348c97df44 6406 #define EXTI_SWIER_SWIER12_Pos (12U)
lypinator 0:bb348c97df44 6407 #define EXTI_SWIER_SWIER12_Msk (0x1U << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 6408 #define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */
lypinator 0:bb348c97df44 6409 #define EXTI_SWIER_SWIER13_Pos (13U)
lypinator 0:bb348c97df44 6410 #define EXTI_SWIER_SWIER13_Msk (0x1U << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 6411 #define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */
lypinator 0:bb348c97df44 6412 #define EXTI_SWIER_SWIER14_Pos (14U)
lypinator 0:bb348c97df44 6413 #define EXTI_SWIER_SWIER14_Msk (0x1U << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 6414 #define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */
lypinator 0:bb348c97df44 6415 #define EXTI_SWIER_SWIER15_Pos (15U)
lypinator 0:bb348c97df44 6416 #define EXTI_SWIER_SWIER15_Msk (0x1U << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 6417 #define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */
lypinator 0:bb348c97df44 6418 #define EXTI_SWIER_SWIER16_Pos (16U)
lypinator 0:bb348c97df44 6419 #define EXTI_SWIER_SWIER16_Msk (0x1U << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 6420 #define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */
lypinator 0:bb348c97df44 6421 #define EXTI_SWIER_SWIER17_Pos (17U)
lypinator 0:bb348c97df44 6422 #define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 6423 #define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */
lypinator 0:bb348c97df44 6424 #define EXTI_SWIER_SWIER18_Pos (18U)
lypinator 0:bb348c97df44 6425 #define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 6426 #define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */
lypinator 0:bb348c97df44 6427 #define EXTI_SWIER_SWIER19_Pos (19U)
lypinator 0:bb348c97df44 6428 #define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 6429 #define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */
lypinator 0:bb348c97df44 6430 #define EXTI_SWIER_SWIER20_Pos (20U)
lypinator 0:bb348c97df44 6431 #define EXTI_SWIER_SWIER20_Msk (0x1U << EXTI_SWIER_SWIER20_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 6432 #define EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk /*!< Software Interrupt on line 20 */
lypinator 0:bb348c97df44 6433 #define EXTI_SWIER_SWIER21_Pos (21U)
lypinator 0:bb348c97df44 6434 #define EXTI_SWIER_SWIER21_Msk (0x1U << EXTI_SWIER_SWIER21_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 6435 #define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk /*!< Software Interrupt on line 21 */
lypinator 0:bb348c97df44 6436 #define EXTI_SWIER_SWIER22_Pos (22U)
lypinator 0:bb348c97df44 6437 #define EXTI_SWIER_SWIER22_Msk (0x1U << EXTI_SWIER_SWIER22_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 6438 #define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk /*!< Software Interrupt on line 22 */
lypinator 0:bb348c97df44 6439
lypinator 0:bb348c97df44 6440 /******************* Bit definition for EXTI_PR register ********************/
lypinator 0:bb348c97df44 6441 #define EXTI_PR_PR0_Pos (0U)
lypinator 0:bb348c97df44 6442 #define EXTI_PR_PR0_Msk (0x1U << EXTI_PR_PR0_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 6443 #define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */
lypinator 0:bb348c97df44 6444 #define EXTI_PR_PR1_Pos (1U)
lypinator 0:bb348c97df44 6445 #define EXTI_PR_PR1_Msk (0x1U << EXTI_PR_PR1_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 6446 #define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */
lypinator 0:bb348c97df44 6447 #define EXTI_PR_PR2_Pos (2U)
lypinator 0:bb348c97df44 6448 #define EXTI_PR_PR2_Msk (0x1U << EXTI_PR_PR2_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 6449 #define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */
lypinator 0:bb348c97df44 6450 #define EXTI_PR_PR3_Pos (3U)
lypinator 0:bb348c97df44 6451 #define EXTI_PR_PR3_Msk (0x1U << EXTI_PR_PR3_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 6452 #define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */
lypinator 0:bb348c97df44 6453 #define EXTI_PR_PR4_Pos (4U)
lypinator 0:bb348c97df44 6454 #define EXTI_PR_PR4_Msk (0x1U << EXTI_PR_PR4_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 6455 #define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */
lypinator 0:bb348c97df44 6456 #define EXTI_PR_PR5_Pos (5U)
lypinator 0:bb348c97df44 6457 #define EXTI_PR_PR5_Msk (0x1U << EXTI_PR_PR5_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 6458 #define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */
lypinator 0:bb348c97df44 6459 #define EXTI_PR_PR6_Pos (6U)
lypinator 0:bb348c97df44 6460 #define EXTI_PR_PR6_Msk (0x1U << EXTI_PR_PR6_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 6461 #define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */
lypinator 0:bb348c97df44 6462 #define EXTI_PR_PR7_Pos (7U)
lypinator 0:bb348c97df44 6463 #define EXTI_PR_PR7_Msk (0x1U << EXTI_PR_PR7_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 6464 #define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */
lypinator 0:bb348c97df44 6465 #define EXTI_PR_PR8_Pos (8U)
lypinator 0:bb348c97df44 6466 #define EXTI_PR_PR8_Msk (0x1U << EXTI_PR_PR8_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 6467 #define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */
lypinator 0:bb348c97df44 6468 #define EXTI_PR_PR9_Pos (9U)
lypinator 0:bb348c97df44 6469 #define EXTI_PR_PR9_Msk (0x1U << EXTI_PR_PR9_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 6470 #define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */
lypinator 0:bb348c97df44 6471 #define EXTI_PR_PR10_Pos (10U)
lypinator 0:bb348c97df44 6472 #define EXTI_PR_PR10_Msk (0x1U << EXTI_PR_PR10_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 6473 #define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */
lypinator 0:bb348c97df44 6474 #define EXTI_PR_PR11_Pos (11U)
lypinator 0:bb348c97df44 6475 #define EXTI_PR_PR11_Msk (0x1U << EXTI_PR_PR11_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 6476 #define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */
lypinator 0:bb348c97df44 6477 #define EXTI_PR_PR12_Pos (12U)
lypinator 0:bb348c97df44 6478 #define EXTI_PR_PR12_Msk (0x1U << EXTI_PR_PR12_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 6479 #define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */
lypinator 0:bb348c97df44 6480 #define EXTI_PR_PR13_Pos (13U)
lypinator 0:bb348c97df44 6481 #define EXTI_PR_PR13_Msk (0x1U << EXTI_PR_PR13_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 6482 #define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */
lypinator 0:bb348c97df44 6483 #define EXTI_PR_PR14_Pos (14U)
lypinator 0:bb348c97df44 6484 #define EXTI_PR_PR14_Msk (0x1U << EXTI_PR_PR14_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 6485 #define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */
lypinator 0:bb348c97df44 6486 #define EXTI_PR_PR15_Pos (15U)
lypinator 0:bb348c97df44 6487 #define EXTI_PR_PR15_Msk (0x1U << EXTI_PR_PR15_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 6488 #define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */
lypinator 0:bb348c97df44 6489 #define EXTI_PR_PR16_Pos (16U)
lypinator 0:bb348c97df44 6490 #define EXTI_PR_PR16_Msk (0x1U << EXTI_PR_PR16_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 6491 #define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */
lypinator 0:bb348c97df44 6492 #define EXTI_PR_PR17_Pos (17U)
lypinator 0:bb348c97df44 6493 #define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 6494 #define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */
lypinator 0:bb348c97df44 6495 #define EXTI_PR_PR18_Pos (18U)
lypinator 0:bb348c97df44 6496 #define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 6497 #define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */
lypinator 0:bb348c97df44 6498 #define EXTI_PR_PR19_Pos (19U)
lypinator 0:bb348c97df44 6499 #define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 6500 #define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */
lypinator 0:bb348c97df44 6501 #define EXTI_PR_PR20_Pos (20U)
lypinator 0:bb348c97df44 6502 #define EXTI_PR_PR20_Msk (0x1U << EXTI_PR_PR20_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 6503 #define EXTI_PR_PR20 EXTI_PR_PR20_Msk /*!< Pending bit for line 20 */
lypinator 0:bb348c97df44 6504 #define EXTI_PR_PR21_Pos (21U)
lypinator 0:bb348c97df44 6505 #define EXTI_PR_PR21_Msk (0x1U << EXTI_PR_PR21_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 6506 #define EXTI_PR_PR21 EXTI_PR_PR21_Msk /*!< Pending bit for line 21 */
lypinator 0:bb348c97df44 6507 #define EXTI_PR_PR22_Pos (22U)
lypinator 0:bb348c97df44 6508 #define EXTI_PR_PR22_Msk (0x1U << EXTI_PR_PR22_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 6509 #define EXTI_PR_PR22 EXTI_PR_PR22_Msk /*!< Pending bit for line 22 */
lypinator 0:bb348c97df44 6510
lypinator 0:bb348c97df44 6511 /******************************************************************************/
lypinator 0:bb348c97df44 6512 /* */
lypinator 0:bb348c97df44 6513 /* FLASH */
lypinator 0:bb348c97df44 6514 /* */
lypinator 0:bb348c97df44 6515 /******************************************************************************/
lypinator 0:bb348c97df44 6516 /******************* Bits definition for FLASH_ACR register *****************/
lypinator 0:bb348c97df44 6517 #define FLASH_ACR_LATENCY_Pos (0U)
lypinator 0:bb348c97df44 6518 #define FLASH_ACR_LATENCY_Msk (0xFU << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
lypinator 0:bb348c97df44 6519 #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
lypinator 0:bb348c97df44 6520 #define FLASH_ACR_LATENCY_0WS 0x00000000U
lypinator 0:bb348c97df44 6521 #define FLASH_ACR_LATENCY_1WS 0x00000001U
lypinator 0:bb348c97df44 6522 #define FLASH_ACR_LATENCY_2WS 0x00000002U
lypinator 0:bb348c97df44 6523 #define FLASH_ACR_LATENCY_3WS 0x00000003U
lypinator 0:bb348c97df44 6524 #define FLASH_ACR_LATENCY_4WS 0x00000004U
lypinator 0:bb348c97df44 6525 #define FLASH_ACR_LATENCY_5WS 0x00000005U
lypinator 0:bb348c97df44 6526 #define FLASH_ACR_LATENCY_6WS 0x00000006U
lypinator 0:bb348c97df44 6527 #define FLASH_ACR_LATENCY_7WS 0x00000007U
lypinator 0:bb348c97df44 6528
lypinator 0:bb348c97df44 6529 #define FLASH_ACR_PRFTEN_Pos (8U)
lypinator 0:bb348c97df44 6530 #define FLASH_ACR_PRFTEN_Msk (0x1U << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 6531 #define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk
lypinator 0:bb348c97df44 6532 #define FLASH_ACR_ICEN_Pos (9U)
lypinator 0:bb348c97df44 6533 #define FLASH_ACR_ICEN_Msk (0x1U << FLASH_ACR_ICEN_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 6534 #define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk
lypinator 0:bb348c97df44 6535 #define FLASH_ACR_DCEN_Pos (10U)
lypinator 0:bb348c97df44 6536 #define FLASH_ACR_DCEN_Msk (0x1U << FLASH_ACR_DCEN_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 6537 #define FLASH_ACR_DCEN FLASH_ACR_DCEN_Msk
lypinator 0:bb348c97df44 6538 #define FLASH_ACR_ICRST_Pos (11U)
lypinator 0:bb348c97df44 6539 #define FLASH_ACR_ICRST_Msk (0x1U << FLASH_ACR_ICRST_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 6540 #define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk
lypinator 0:bb348c97df44 6541 #define FLASH_ACR_DCRST_Pos (12U)
lypinator 0:bb348c97df44 6542 #define FLASH_ACR_DCRST_Msk (0x1U << FLASH_ACR_DCRST_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 6543 #define FLASH_ACR_DCRST FLASH_ACR_DCRST_Msk
lypinator 0:bb348c97df44 6544 #define FLASH_ACR_BYTE0_ADDRESS_Pos (10U)
lypinator 0:bb348c97df44 6545 #define FLASH_ACR_BYTE0_ADDRESS_Msk (0x10008FU << FLASH_ACR_BYTE0_ADDRESS_Pos) /*!< 0x40023C00 */
lypinator 0:bb348c97df44 6546 #define FLASH_ACR_BYTE0_ADDRESS FLASH_ACR_BYTE0_ADDRESS_Msk
lypinator 0:bb348c97df44 6547 #define FLASH_ACR_BYTE2_ADDRESS_Pos (0U)
lypinator 0:bb348c97df44 6548 #define FLASH_ACR_BYTE2_ADDRESS_Msk (0x40023C03U << FLASH_ACR_BYTE2_ADDRESS_Pos) /*!< 0x40023C03 */
lypinator 0:bb348c97df44 6549 #define FLASH_ACR_BYTE2_ADDRESS FLASH_ACR_BYTE2_ADDRESS_Msk
lypinator 0:bb348c97df44 6550
lypinator 0:bb348c97df44 6551 /******************* Bits definition for FLASH_SR register ******************/
lypinator 0:bb348c97df44 6552 #define FLASH_SR_EOP_Pos (0U)
lypinator 0:bb348c97df44 6553 #define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 6554 #define FLASH_SR_EOP FLASH_SR_EOP_Msk
lypinator 0:bb348c97df44 6555 #define FLASH_SR_SOP_Pos (1U)
lypinator 0:bb348c97df44 6556 #define FLASH_SR_SOP_Msk (0x1U << FLASH_SR_SOP_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 6557 #define FLASH_SR_SOP FLASH_SR_SOP_Msk
lypinator 0:bb348c97df44 6558 #define FLASH_SR_WRPERR_Pos (4U)
lypinator 0:bb348c97df44 6559 #define FLASH_SR_WRPERR_Msk (0x1U << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 6560 #define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
lypinator 0:bb348c97df44 6561 #define FLASH_SR_PGAERR_Pos (5U)
lypinator 0:bb348c97df44 6562 #define FLASH_SR_PGAERR_Msk (0x1U << FLASH_SR_PGAERR_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 6563 #define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk
lypinator 0:bb348c97df44 6564 #define FLASH_SR_PGPERR_Pos (6U)
lypinator 0:bb348c97df44 6565 #define FLASH_SR_PGPERR_Msk (0x1U << FLASH_SR_PGPERR_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 6566 #define FLASH_SR_PGPERR FLASH_SR_PGPERR_Msk
lypinator 0:bb348c97df44 6567 #define FLASH_SR_PGSERR_Pos (7U)
lypinator 0:bb348c97df44 6568 #define FLASH_SR_PGSERR_Msk (0x1U << FLASH_SR_PGSERR_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 6569 #define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk
lypinator 0:bb348c97df44 6570 #define FLASH_SR_RDERR_Pos (8U)
lypinator 0:bb348c97df44 6571 #define FLASH_SR_RDERR_Msk (0x1U << FLASH_SR_RDERR_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 6572 #define FLASH_SR_RDERR FLASH_SR_RDERR_Msk
lypinator 0:bb348c97df44 6573 #define FLASH_SR_BSY_Pos (16U)
lypinator 0:bb348c97df44 6574 #define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 6575 #define FLASH_SR_BSY FLASH_SR_BSY_Msk
lypinator 0:bb348c97df44 6576
lypinator 0:bb348c97df44 6577 /******************* Bits definition for FLASH_CR register ******************/
lypinator 0:bb348c97df44 6578 #define FLASH_CR_PG_Pos (0U)
lypinator 0:bb348c97df44 6579 #define FLASH_CR_PG_Msk (0x1U << FLASH_CR_PG_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 6580 #define FLASH_CR_PG FLASH_CR_PG_Msk
lypinator 0:bb348c97df44 6581 #define FLASH_CR_SER_Pos (1U)
lypinator 0:bb348c97df44 6582 #define FLASH_CR_SER_Msk (0x1U << FLASH_CR_SER_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 6583 #define FLASH_CR_SER FLASH_CR_SER_Msk
lypinator 0:bb348c97df44 6584 #define FLASH_CR_MER_Pos (2U)
lypinator 0:bb348c97df44 6585 #define FLASH_CR_MER_Msk (0x1U << FLASH_CR_MER_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 6586 #define FLASH_CR_MER FLASH_CR_MER_Msk
lypinator 0:bb348c97df44 6587 #define FLASH_CR_SNB_Pos (3U)
lypinator 0:bb348c97df44 6588 #define FLASH_CR_SNB_Msk (0x1FU << FLASH_CR_SNB_Pos) /*!< 0x000000F8 */
lypinator 0:bb348c97df44 6589 #define FLASH_CR_SNB FLASH_CR_SNB_Msk
lypinator 0:bb348c97df44 6590 #define FLASH_CR_SNB_0 (0x01U << FLASH_CR_SNB_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 6591 #define FLASH_CR_SNB_1 (0x02U << FLASH_CR_SNB_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 6592 #define FLASH_CR_SNB_2 (0x04U << FLASH_CR_SNB_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 6593 #define FLASH_CR_SNB_3 (0x08U << FLASH_CR_SNB_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 6594 #define FLASH_CR_SNB_4 (0x10U << FLASH_CR_SNB_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 6595 #define FLASH_CR_PSIZE_Pos (8U)
lypinator 0:bb348c97df44 6596 #define FLASH_CR_PSIZE_Msk (0x3U << FLASH_CR_PSIZE_Pos) /*!< 0x00000300 */
lypinator 0:bb348c97df44 6597 #define FLASH_CR_PSIZE FLASH_CR_PSIZE_Msk
lypinator 0:bb348c97df44 6598 #define FLASH_CR_PSIZE_0 (0x1U << FLASH_CR_PSIZE_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 6599 #define FLASH_CR_PSIZE_1 (0x2U << FLASH_CR_PSIZE_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 6600 #define FLASH_CR_STRT_Pos (16U)
lypinator 0:bb348c97df44 6601 #define FLASH_CR_STRT_Msk (0x1U << FLASH_CR_STRT_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 6602 #define FLASH_CR_STRT FLASH_CR_STRT_Msk
lypinator 0:bb348c97df44 6603 #define FLASH_CR_EOPIE_Pos (24U)
lypinator 0:bb348c97df44 6604 #define FLASH_CR_EOPIE_Msk (0x1U << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 6605 #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
lypinator 0:bb348c97df44 6606 #define FLASH_CR_LOCK_Pos (31U)
lypinator 0:bb348c97df44 6607 #define FLASH_CR_LOCK_Msk (0x1U << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */
lypinator 0:bb348c97df44 6608 #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
lypinator 0:bb348c97df44 6609
lypinator 0:bb348c97df44 6610 /******************* Bits definition for FLASH_OPTCR register ***************/
lypinator 0:bb348c97df44 6611 #define FLASH_OPTCR_OPTLOCK_Pos (0U)
lypinator 0:bb348c97df44 6612 #define FLASH_OPTCR_OPTLOCK_Msk (0x1U << FLASH_OPTCR_OPTLOCK_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 6613 #define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk
lypinator 0:bb348c97df44 6614 #define FLASH_OPTCR_OPTSTRT_Pos (1U)
lypinator 0:bb348c97df44 6615 #define FLASH_OPTCR_OPTSTRT_Msk (0x1U << FLASH_OPTCR_OPTSTRT_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 6616 #define FLASH_OPTCR_OPTSTRT FLASH_OPTCR_OPTSTRT_Msk
lypinator 0:bb348c97df44 6617
lypinator 0:bb348c97df44 6618 #define FLASH_OPTCR_BOR_LEV_0 0x00000004U
lypinator 0:bb348c97df44 6619 #define FLASH_OPTCR_BOR_LEV_1 0x00000008U
lypinator 0:bb348c97df44 6620 #define FLASH_OPTCR_BOR_LEV_Pos (2U)
lypinator 0:bb348c97df44 6621 #define FLASH_OPTCR_BOR_LEV_Msk (0x3U << FLASH_OPTCR_BOR_LEV_Pos) /*!< 0x0000000C */
lypinator 0:bb348c97df44 6622 #define FLASH_OPTCR_BOR_LEV FLASH_OPTCR_BOR_LEV_Msk
lypinator 0:bb348c97df44 6623 #define FLASH_OPTCR_WDG_SW_Pos (5U)
lypinator 0:bb348c97df44 6624 #define FLASH_OPTCR_WDG_SW_Msk (0x1U << FLASH_OPTCR_WDG_SW_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 6625 #define FLASH_OPTCR_WDG_SW FLASH_OPTCR_WDG_SW_Msk
lypinator 0:bb348c97df44 6626 #define FLASH_OPTCR_nRST_STOP_Pos (6U)
lypinator 0:bb348c97df44 6627 #define FLASH_OPTCR_nRST_STOP_Msk (0x1U << FLASH_OPTCR_nRST_STOP_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 6628 #define FLASH_OPTCR_nRST_STOP FLASH_OPTCR_nRST_STOP_Msk
lypinator 0:bb348c97df44 6629 #define FLASH_OPTCR_nRST_STDBY_Pos (7U)
lypinator 0:bb348c97df44 6630 #define FLASH_OPTCR_nRST_STDBY_Msk (0x1U << FLASH_OPTCR_nRST_STDBY_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 6631 #define FLASH_OPTCR_nRST_STDBY FLASH_OPTCR_nRST_STDBY_Msk
lypinator 0:bb348c97df44 6632 #define FLASH_OPTCR_RDP_Pos (8U)
lypinator 0:bb348c97df44 6633 #define FLASH_OPTCR_RDP_Msk (0xFFU << FLASH_OPTCR_RDP_Pos) /*!< 0x0000FF00 */
lypinator 0:bb348c97df44 6634 #define FLASH_OPTCR_RDP FLASH_OPTCR_RDP_Msk
lypinator 0:bb348c97df44 6635 #define FLASH_OPTCR_RDP_0 (0x01U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 6636 #define FLASH_OPTCR_RDP_1 (0x02U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 6637 #define FLASH_OPTCR_RDP_2 (0x04U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 6638 #define FLASH_OPTCR_RDP_3 (0x08U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 6639 #define FLASH_OPTCR_RDP_4 (0x10U << FLASH_OPTCR_RDP_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 6640 #define FLASH_OPTCR_RDP_5 (0x20U << FLASH_OPTCR_RDP_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 6641 #define FLASH_OPTCR_RDP_6 (0x40U << FLASH_OPTCR_RDP_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 6642 #define FLASH_OPTCR_RDP_7 (0x80U << FLASH_OPTCR_RDP_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 6643 #define FLASH_OPTCR_nWRP_Pos (16U)
lypinator 0:bb348c97df44 6644 #define FLASH_OPTCR_nWRP_Msk (0xFFFU << FLASH_OPTCR_nWRP_Pos) /*!< 0x0FFF0000 */
lypinator 0:bb348c97df44 6645 #define FLASH_OPTCR_nWRP FLASH_OPTCR_nWRP_Msk
lypinator 0:bb348c97df44 6646 #define FLASH_OPTCR_nWRP_0 0x00010000U
lypinator 0:bb348c97df44 6647 #define FLASH_OPTCR_nWRP_1 0x00020000U
lypinator 0:bb348c97df44 6648 #define FLASH_OPTCR_nWRP_2 0x00040000U
lypinator 0:bb348c97df44 6649 #define FLASH_OPTCR_nWRP_3 0x00080000U
lypinator 0:bb348c97df44 6650 #define FLASH_OPTCR_nWRP_4 0x00100000U
lypinator 0:bb348c97df44 6651 #define FLASH_OPTCR_nWRP_5 0x00200000U
lypinator 0:bb348c97df44 6652 #define FLASH_OPTCR_nWRP_6 0x00400000U
lypinator 0:bb348c97df44 6653 #define FLASH_OPTCR_nWRP_7 0x00800000U
lypinator 0:bb348c97df44 6654 #define FLASH_OPTCR_nWRP_8 0x01000000U
lypinator 0:bb348c97df44 6655 #define FLASH_OPTCR_nWRP_9 0x02000000U
lypinator 0:bb348c97df44 6656 #define FLASH_OPTCR_nWRP_10 0x04000000U
lypinator 0:bb348c97df44 6657 #define FLASH_OPTCR_nWRP_11 0x08000000U
lypinator 0:bb348c97df44 6658
lypinator 0:bb348c97df44 6659 /****************** Bits definition for FLASH_OPTCR1 register ***************/
lypinator 0:bb348c97df44 6660 #define FLASH_OPTCR1_nWRP_Pos (16U)
lypinator 0:bb348c97df44 6661 #define FLASH_OPTCR1_nWRP_Msk (0xFFFU << FLASH_OPTCR1_nWRP_Pos) /*!< 0x0FFF0000 */
lypinator 0:bb348c97df44 6662 #define FLASH_OPTCR1_nWRP FLASH_OPTCR1_nWRP_Msk
lypinator 0:bb348c97df44 6663 #define FLASH_OPTCR1_nWRP_0 (0x001U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 6664 #define FLASH_OPTCR1_nWRP_1 (0x002U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 6665 #define FLASH_OPTCR1_nWRP_2 (0x004U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 6666 #define FLASH_OPTCR1_nWRP_3 (0x008U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 6667 #define FLASH_OPTCR1_nWRP_4 (0x010U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 6668 #define FLASH_OPTCR1_nWRP_5 (0x020U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 6669 #define FLASH_OPTCR1_nWRP_6 (0x040U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 6670 #define FLASH_OPTCR1_nWRP_7 (0x080U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00800000 */
lypinator 0:bb348c97df44 6671 #define FLASH_OPTCR1_nWRP_8 (0x100U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 6672 #define FLASH_OPTCR1_nWRP_9 (0x200U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 6673 #define FLASH_OPTCR1_nWRP_10 (0x400U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x04000000 */
lypinator 0:bb348c97df44 6674 #define FLASH_OPTCR1_nWRP_11 (0x800U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x08000000 */
lypinator 0:bb348c97df44 6675
lypinator 0:bb348c97df44 6676 /******************************************************************************/
lypinator 0:bb348c97df44 6677 /* */
lypinator 0:bb348c97df44 6678 /* Flexible Static Memory Controller */
lypinator 0:bb348c97df44 6679 /* */
lypinator 0:bb348c97df44 6680 /******************************************************************************/
lypinator 0:bb348c97df44 6681 /****************** Bit definition for FSMC_BCR1 register *******************/
lypinator 0:bb348c97df44 6682 #define FSMC_BCR1_MBKEN_Pos (0U)
lypinator 0:bb348c97df44 6683 #define FSMC_BCR1_MBKEN_Msk (0x1U << FSMC_BCR1_MBKEN_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 6684 #define FSMC_BCR1_MBKEN FSMC_BCR1_MBKEN_Msk /*!<Memory bank enable bit */
lypinator 0:bb348c97df44 6685 #define FSMC_BCR1_MUXEN_Pos (1U)
lypinator 0:bb348c97df44 6686 #define FSMC_BCR1_MUXEN_Msk (0x1U << FSMC_BCR1_MUXEN_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 6687 #define FSMC_BCR1_MUXEN FSMC_BCR1_MUXEN_Msk /*!<Address/data multiplexing enable bit */
lypinator 0:bb348c97df44 6688
lypinator 0:bb348c97df44 6689 #define FSMC_BCR1_MTYP_Pos (2U)
lypinator 0:bb348c97df44 6690 #define FSMC_BCR1_MTYP_Msk (0x3U << FSMC_BCR1_MTYP_Pos) /*!< 0x0000000C */
lypinator 0:bb348c97df44 6691 #define FSMC_BCR1_MTYP FSMC_BCR1_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
lypinator 0:bb348c97df44 6692 #define FSMC_BCR1_MTYP_0 (0x1U << FSMC_BCR1_MTYP_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 6693 #define FSMC_BCR1_MTYP_1 (0x2U << FSMC_BCR1_MTYP_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 6694
lypinator 0:bb348c97df44 6695 #define FSMC_BCR1_MWID_Pos (4U)
lypinator 0:bb348c97df44 6696 #define FSMC_BCR1_MWID_Msk (0x3U << FSMC_BCR1_MWID_Pos) /*!< 0x00000030 */
lypinator 0:bb348c97df44 6697 #define FSMC_BCR1_MWID FSMC_BCR1_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
lypinator 0:bb348c97df44 6698 #define FSMC_BCR1_MWID_0 (0x1U << FSMC_BCR1_MWID_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 6699 #define FSMC_BCR1_MWID_1 (0x2U << FSMC_BCR1_MWID_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 6700
lypinator 0:bb348c97df44 6701 #define FSMC_BCR1_FACCEN_Pos (6U)
lypinator 0:bb348c97df44 6702 #define FSMC_BCR1_FACCEN_Msk (0x1U << FSMC_BCR1_FACCEN_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 6703 #define FSMC_BCR1_FACCEN FSMC_BCR1_FACCEN_Msk /*!<Flash access enable */
lypinator 0:bb348c97df44 6704 #define FSMC_BCR1_BURSTEN_Pos (8U)
lypinator 0:bb348c97df44 6705 #define FSMC_BCR1_BURSTEN_Msk (0x1U << FSMC_BCR1_BURSTEN_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 6706 #define FSMC_BCR1_BURSTEN FSMC_BCR1_BURSTEN_Msk /*!<Burst enable bit */
lypinator 0:bb348c97df44 6707 #define FSMC_BCR1_WAITPOL_Pos (9U)
lypinator 0:bb348c97df44 6708 #define FSMC_BCR1_WAITPOL_Msk (0x1U << FSMC_BCR1_WAITPOL_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 6709 #define FSMC_BCR1_WAITPOL FSMC_BCR1_WAITPOL_Msk /*!<Wait signal polarity bit */
lypinator 0:bb348c97df44 6710 #define FSMC_BCR1_WAITCFG_Pos (11U)
lypinator 0:bb348c97df44 6711 #define FSMC_BCR1_WAITCFG_Msk (0x1U << FSMC_BCR1_WAITCFG_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 6712 #define FSMC_BCR1_WAITCFG FSMC_BCR1_WAITCFG_Msk /*!<Wait timing configuration */
lypinator 0:bb348c97df44 6713 #define FSMC_BCR1_WREN_Pos (12U)
lypinator 0:bb348c97df44 6714 #define FSMC_BCR1_WREN_Msk (0x1U << FSMC_BCR1_WREN_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 6715 #define FSMC_BCR1_WREN FSMC_BCR1_WREN_Msk /*!<Write enable bit */
lypinator 0:bb348c97df44 6716 #define FSMC_BCR1_WAITEN_Pos (13U)
lypinator 0:bb348c97df44 6717 #define FSMC_BCR1_WAITEN_Msk (0x1U << FSMC_BCR1_WAITEN_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 6718 #define FSMC_BCR1_WAITEN FSMC_BCR1_WAITEN_Msk /*!<Wait enable bit */
lypinator 0:bb348c97df44 6719 #define FSMC_BCR1_EXTMOD_Pos (14U)
lypinator 0:bb348c97df44 6720 #define FSMC_BCR1_EXTMOD_Msk (0x1U << FSMC_BCR1_EXTMOD_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 6721 #define FSMC_BCR1_EXTMOD FSMC_BCR1_EXTMOD_Msk /*!<Extended mode enable */
lypinator 0:bb348c97df44 6722 #define FSMC_BCR1_ASYNCWAIT_Pos (15U)
lypinator 0:bb348c97df44 6723 #define FSMC_BCR1_ASYNCWAIT_Msk (0x1U << FSMC_BCR1_ASYNCWAIT_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 6724 #define FSMC_BCR1_ASYNCWAIT FSMC_BCR1_ASYNCWAIT_Msk /*!<Asynchronous wait */
lypinator 0:bb348c97df44 6725 #define FSMC_BCR1_CPSIZE_Pos (16U)
lypinator 0:bb348c97df44 6726 #define FSMC_BCR1_CPSIZE_Msk (0x7U << FSMC_BCR1_CPSIZE_Pos) /*!< 0x00070000 */
lypinator 0:bb348c97df44 6727 #define FSMC_BCR1_CPSIZE FSMC_BCR1_CPSIZE_Msk /*!<CRAM page size */
lypinator 0:bb348c97df44 6728 #define FSMC_BCR1_CPSIZE_0 (0x1U << FSMC_BCR1_CPSIZE_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 6729 #define FSMC_BCR1_CPSIZE_1 (0x2U << FSMC_BCR1_CPSIZE_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 6730 #define FSMC_BCR1_CPSIZE_2 (0x4U << FSMC_BCR1_CPSIZE_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 6731 #define FSMC_BCR1_CBURSTRW_Pos (19U)
lypinator 0:bb348c97df44 6732 #define FSMC_BCR1_CBURSTRW_Msk (0x1U << FSMC_BCR1_CBURSTRW_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 6733 #define FSMC_BCR1_CBURSTRW FSMC_BCR1_CBURSTRW_Msk /*!<Write burst enable */
lypinator 0:bb348c97df44 6734 #define FSMC_BCR1_CCLKEN_Pos (20U)
lypinator 0:bb348c97df44 6735 #define FSMC_BCR1_CCLKEN_Msk (0x1U << FSMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 6736 #define FSMC_BCR1_CCLKEN FSMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
lypinator 0:bb348c97df44 6737 #define FSMC_BCR1_WFDIS_Pos (21U)
lypinator 0:bb348c97df44 6738 #define FSMC_BCR1_WFDIS_Msk (0x1U << FSMC_BCR1_WFDIS_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 6739 #define FSMC_BCR1_WFDIS FSMC_BCR1_WFDIS_Msk /*!<Write FIFO Disable */
lypinator 0:bb348c97df44 6740
lypinator 0:bb348c97df44 6741 /****************** Bit definition for FSMC_BCR2 register *******************/
lypinator 0:bb348c97df44 6742 #define FSMC_BCR2_MBKEN_Pos (0U)
lypinator 0:bb348c97df44 6743 #define FSMC_BCR2_MBKEN_Msk (0x1U << FSMC_BCR2_MBKEN_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 6744 #define FSMC_BCR2_MBKEN FSMC_BCR2_MBKEN_Msk /*!<Memory bank enable bit */
lypinator 0:bb348c97df44 6745 #define FSMC_BCR2_MUXEN_Pos (1U)
lypinator 0:bb348c97df44 6746 #define FSMC_BCR2_MUXEN_Msk (0x1U << FSMC_BCR2_MUXEN_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 6747 #define FSMC_BCR2_MUXEN FSMC_BCR2_MUXEN_Msk /*!<Address/data multiplexing enable bit */
lypinator 0:bb348c97df44 6748
lypinator 0:bb348c97df44 6749 #define FSMC_BCR2_MTYP_Pos (2U)
lypinator 0:bb348c97df44 6750 #define FSMC_BCR2_MTYP_Msk (0x3U << FSMC_BCR2_MTYP_Pos) /*!< 0x0000000C */
lypinator 0:bb348c97df44 6751 #define FSMC_BCR2_MTYP FSMC_BCR2_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
lypinator 0:bb348c97df44 6752 #define FSMC_BCR2_MTYP_0 (0x1U << FSMC_BCR2_MTYP_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 6753 #define FSMC_BCR2_MTYP_1 (0x2U << FSMC_BCR2_MTYP_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 6754
lypinator 0:bb348c97df44 6755 #define FSMC_BCR2_MWID_Pos (4U)
lypinator 0:bb348c97df44 6756 #define FSMC_BCR2_MWID_Msk (0x3U << FSMC_BCR2_MWID_Pos) /*!< 0x00000030 */
lypinator 0:bb348c97df44 6757 #define FSMC_BCR2_MWID FSMC_BCR2_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
lypinator 0:bb348c97df44 6758 #define FSMC_BCR2_MWID_0 (0x1U << FSMC_BCR2_MWID_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 6759 #define FSMC_BCR2_MWID_1 (0x2U << FSMC_BCR2_MWID_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 6760
lypinator 0:bb348c97df44 6761 #define FSMC_BCR2_FACCEN_Pos (6U)
lypinator 0:bb348c97df44 6762 #define FSMC_BCR2_FACCEN_Msk (0x1U << FSMC_BCR2_FACCEN_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 6763 #define FSMC_BCR2_FACCEN FSMC_BCR2_FACCEN_Msk /*!<Flash access enable */
lypinator 0:bb348c97df44 6764 #define FSMC_BCR2_BURSTEN_Pos (8U)
lypinator 0:bb348c97df44 6765 #define FSMC_BCR2_BURSTEN_Msk (0x1U << FSMC_BCR2_BURSTEN_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 6766 #define FSMC_BCR2_BURSTEN FSMC_BCR2_BURSTEN_Msk /*!<Burst enable bit */
lypinator 0:bb348c97df44 6767 #define FSMC_BCR2_WAITPOL_Pos (9U)
lypinator 0:bb348c97df44 6768 #define FSMC_BCR2_WAITPOL_Msk (0x1U << FSMC_BCR2_WAITPOL_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 6769 #define FSMC_BCR2_WAITPOL FSMC_BCR2_WAITPOL_Msk /*!<Wait signal polarity bit */
lypinator 0:bb348c97df44 6770 #define FSMC_BCR2_WAITCFG_Pos (11U)
lypinator 0:bb348c97df44 6771 #define FSMC_BCR2_WAITCFG_Msk (0x1U << FSMC_BCR2_WAITCFG_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 6772 #define FSMC_BCR2_WAITCFG FSMC_BCR2_WAITCFG_Msk /*!<Wait timing configuration */
lypinator 0:bb348c97df44 6773 #define FSMC_BCR2_WREN_Pos (12U)
lypinator 0:bb348c97df44 6774 #define FSMC_BCR2_WREN_Msk (0x1U << FSMC_BCR2_WREN_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 6775 #define FSMC_BCR2_WREN FSMC_BCR2_WREN_Msk /*!<Write enable bit */
lypinator 0:bb348c97df44 6776 #define FSMC_BCR2_WAITEN_Pos (13U)
lypinator 0:bb348c97df44 6777 #define FSMC_BCR2_WAITEN_Msk (0x1U << FSMC_BCR2_WAITEN_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 6778 #define FSMC_BCR2_WAITEN FSMC_BCR2_WAITEN_Msk /*!<Wait enable bit */
lypinator 0:bb348c97df44 6779 #define FSMC_BCR2_EXTMOD_Pos (14U)
lypinator 0:bb348c97df44 6780 #define FSMC_BCR2_EXTMOD_Msk (0x1U << FSMC_BCR2_EXTMOD_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 6781 #define FSMC_BCR2_EXTMOD FSMC_BCR2_EXTMOD_Msk /*!<Extended mode enable */
lypinator 0:bb348c97df44 6782 #define FSMC_BCR2_ASYNCWAIT_Pos (15U)
lypinator 0:bb348c97df44 6783 #define FSMC_BCR2_ASYNCWAIT_Msk (0x1U << FSMC_BCR2_ASYNCWAIT_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 6784 #define FSMC_BCR2_ASYNCWAIT FSMC_BCR2_ASYNCWAIT_Msk /*!<Asynchronous wait */
lypinator 0:bb348c97df44 6785 #define FSMC_BCR2_CPSIZE_Pos (16U)
lypinator 0:bb348c97df44 6786 #define FSMC_BCR2_CPSIZE_Msk (0x7U << FSMC_BCR2_CPSIZE_Pos) /*!< 0x00070000 */
lypinator 0:bb348c97df44 6787 #define FSMC_BCR2_CPSIZE FSMC_BCR2_CPSIZE_Msk /*!<CRAM page size */
lypinator 0:bb348c97df44 6788 #define FSMC_BCR2_CPSIZE_0 (0x1U << FSMC_BCR2_CPSIZE_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 6789 #define FSMC_BCR2_CPSIZE_1 (0x2U << FSMC_BCR2_CPSIZE_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 6790 #define FSMC_BCR2_CPSIZE_2 (0x4U << FSMC_BCR2_CPSIZE_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 6791 #define FSMC_BCR2_CBURSTRW_Pos (19U)
lypinator 0:bb348c97df44 6792 #define FSMC_BCR2_CBURSTRW_Msk (0x1U << FSMC_BCR2_CBURSTRW_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 6793 #define FSMC_BCR2_CBURSTRW FSMC_BCR2_CBURSTRW_Msk /*!<Write burst enable */
lypinator 0:bb348c97df44 6794
lypinator 0:bb348c97df44 6795 /****************** Bit definition for FSMC_BCR3 register *******************/
lypinator 0:bb348c97df44 6796 #define FSMC_BCR3_MBKEN_Pos (0U)
lypinator 0:bb348c97df44 6797 #define FSMC_BCR3_MBKEN_Msk (0x1U << FSMC_BCR3_MBKEN_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 6798 #define FSMC_BCR3_MBKEN FSMC_BCR3_MBKEN_Msk /*!<Memory bank enable bit */
lypinator 0:bb348c97df44 6799 #define FSMC_BCR3_MUXEN_Pos (1U)
lypinator 0:bb348c97df44 6800 #define FSMC_BCR3_MUXEN_Msk (0x1U << FSMC_BCR3_MUXEN_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 6801 #define FSMC_BCR3_MUXEN FSMC_BCR3_MUXEN_Msk /*!<Address/data multiplexing enable bit */
lypinator 0:bb348c97df44 6802
lypinator 0:bb348c97df44 6803 #define FSMC_BCR3_MTYP_Pos (2U)
lypinator 0:bb348c97df44 6804 #define FSMC_BCR3_MTYP_Msk (0x3U << FSMC_BCR3_MTYP_Pos) /*!< 0x0000000C */
lypinator 0:bb348c97df44 6805 #define FSMC_BCR3_MTYP FSMC_BCR3_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
lypinator 0:bb348c97df44 6806 #define FSMC_BCR3_MTYP_0 (0x1U << FSMC_BCR3_MTYP_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 6807 #define FSMC_BCR3_MTYP_1 (0x2U << FSMC_BCR3_MTYP_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 6808
lypinator 0:bb348c97df44 6809 #define FSMC_BCR3_MWID_Pos (4U)
lypinator 0:bb348c97df44 6810 #define FSMC_BCR3_MWID_Msk (0x3U << FSMC_BCR3_MWID_Pos) /*!< 0x00000030 */
lypinator 0:bb348c97df44 6811 #define FSMC_BCR3_MWID FSMC_BCR3_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
lypinator 0:bb348c97df44 6812 #define FSMC_BCR3_MWID_0 (0x1U << FSMC_BCR3_MWID_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 6813 #define FSMC_BCR3_MWID_1 (0x2U << FSMC_BCR3_MWID_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 6814
lypinator 0:bb348c97df44 6815 #define FSMC_BCR3_FACCEN_Pos (6U)
lypinator 0:bb348c97df44 6816 #define FSMC_BCR3_FACCEN_Msk (0x1U << FSMC_BCR3_FACCEN_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 6817 #define FSMC_BCR3_FACCEN FSMC_BCR3_FACCEN_Msk /*!<Flash access enable */
lypinator 0:bb348c97df44 6818 #define FSMC_BCR3_BURSTEN_Pos (8U)
lypinator 0:bb348c97df44 6819 #define FSMC_BCR3_BURSTEN_Msk (0x1U << FSMC_BCR3_BURSTEN_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 6820 #define FSMC_BCR3_BURSTEN FSMC_BCR3_BURSTEN_Msk /*!<Burst enable bit */
lypinator 0:bb348c97df44 6821 #define FSMC_BCR3_WAITPOL_Pos (9U)
lypinator 0:bb348c97df44 6822 #define FSMC_BCR3_WAITPOL_Msk (0x1U << FSMC_BCR3_WAITPOL_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 6823 #define FSMC_BCR3_WAITPOL FSMC_BCR3_WAITPOL_Msk /*!<Wait signal polarity bit */
lypinator 0:bb348c97df44 6824 #define FSMC_BCR3_WAITCFG_Pos (11U)
lypinator 0:bb348c97df44 6825 #define FSMC_BCR3_WAITCFG_Msk (0x1U << FSMC_BCR3_WAITCFG_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 6826 #define FSMC_BCR3_WAITCFG FSMC_BCR3_WAITCFG_Msk /*!<Wait timing configuration */
lypinator 0:bb348c97df44 6827 #define FSMC_BCR3_WREN_Pos (12U)
lypinator 0:bb348c97df44 6828 #define FSMC_BCR3_WREN_Msk (0x1U << FSMC_BCR3_WREN_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 6829 #define FSMC_BCR3_WREN FSMC_BCR3_WREN_Msk /*!<Write enable bit */
lypinator 0:bb348c97df44 6830 #define FSMC_BCR3_WAITEN_Pos (13U)
lypinator 0:bb348c97df44 6831 #define FSMC_BCR3_WAITEN_Msk (0x1U << FSMC_BCR3_WAITEN_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 6832 #define FSMC_BCR3_WAITEN FSMC_BCR3_WAITEN_Msk /*!<Wait enable bit */
lypinator 0:bb348c97df44 6833 #define FSMC_BCR3_EXTMOD_Pos (14U)
lypinator 0:bb348c97df44 6834 #define FSMC_BCR3_EXTMOD_Msk (0x1U << FSMC_BCR3_EXTMOD_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 6835 #define FSMC_BCR3_EXTMOD FSMC_BCR3_EXTMOD_Msk /*!<Extended mode enable */
lypinator 0:bb348c97df44 6836 #define FSMC_BCR3_ASYNCWAIT_Pos (15U)
lypinator 0:bb348c97df44 6837 #define FSMC_BCR3_ASYNCWAIT_Msk (0x1U << FSMC_BCR3_ASYNCWAIT_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 6838 #define FSMC_BCR3_ASYNCWAIT FSMC_BCR3_ASYNCWAIT_Msk /*!<Asynchronous wait */
lypinator 0:bb348c97df44 6839 #define FSMC_BCR3_CPSIZE_Pos (16U)
lypinator 0:bb348c97df44 6840 #define FSMC_BCR3_CPSIZE_Msk (0x7U << FSMC_BCR3_CPSIZE_Pos) /*!< 0x00070000 */
lypinator 0:bb348c97df44 6841 #define FSMC_BCR3_CPSIZE FSMC_BCR3_CPSIZE_Msk /*!<CRAM page size */
lypinator 0:bb348c97df44 6842 #define FSMC_BCR3_CPSIZE_0 (0x1U << FSMC_BCR3_CPSIZE_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 6843 #define FSMC_BCR3_CPSIZE_1 (0x2U << FSMC_BCR3_CPSIZE_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 6844 #define FSMC_BCR3_CPSIZE_2 (0x4U << FSMC_BCR3_CPSIZE_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 6845 #define FSMC_BCR3_CBURSTRW_Pos (19U)
lypinator 0:bb348c97df44 6846 #define FSMC_BCR3_CBURSTRW_Msk (0x1U << FSMC_BCR3_CBURSTRW_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 6847 #define FSMC_BCR3_CBURSTRW FSMC_BCR3_CBURSTRW_Msk /*!<Write burst enable */
lypinator 0:bb348c97df44 6848
lypinator 0:bb348c97df44 6849 /****************** Bit definition for FSMC_BCR4 register *******************/
lypinator 0:bb348c97df44 6850 #define FSMC_BCR4_MBKEN_Pos (0U)
lypinator 0:bb348c97df44 6851 #define FSMC_BCR4_MBKEN_Msk (0x1U << FSMC_BCR4_MBKEN_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 6852 #define FSMC_BCR4_MBKEN FSMC_BCR4_MBKEN_Msk /*!<Memory bank enable bit */
lypinator 0:bb348c97df44 6853 #define FSMC_BCR4_MUXEN_Pos (1U)
lypinator 0:bb348c97df44 6854 #define FSMC_BCR4_MUXEN_Msk (0x1U << FSMC_BCR4_MUXEN_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 6855 #define FSMC_BCR4_MUXEN FSMC_BCR4_MUXEN_Msk /*!<Address/data multiplexing enable bit */
lypinator 0:bb348c97df44 6856
lypinator 0:bb348c97df44 6857 #define FSMC_BCR4_MTYP_Pos (2U)
lypinator 0:bb348c97df44 6858 #define FSMC_BCR4_MTYP_Msk (0x3U << FSMC_BCR4_MTYP_Pos) /*!< 0x0000000C */
lypinator 0:bb348c97df44 6859 #define FSMC_BCR4_MTYP FSMC_BCR4_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
lypinator 0:bb348c97df44 6860 #define FSMC_BCR4_MTYP_0 (0x1U << FSMC_BCR4_MTYP_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 6861 #define FSMC_BCR4_MTYP_1 (0x2U << FSMC_BCR4_MTYP_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 6862
lypinator 0:bb348c97df44 6863 #define FSMC_BCR4_MWID_Pos (4U)
lypinator 0:bb348c97df44 6864 #define FSMC_BCR4_MWID_Msk (0x3U << FSMC_BCR4_MWID_Pos) /*!< 0x00000030 */
lypinator 0:bb348c97df44 6865 #define FSMC_BCR4_MWID FSMC_BCR4_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
lypinator 0:bb348c97df44 6866 #define FSMC_BCR4_MWID_0 (0x1U << FSMC_BCR4_MWID_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 6867 #define FSMC_BCR4_MWID_1 (0x2U << FSMC_BCR4_MWID_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 6868
lypinator 0:bb348c97df44 6869 #define FSMC_BCR4_FACCEN_Pos (6U)
lypinator 0:bb348c97df44 6870 #define FSMC_BCR4_FACCEN_Msk (0x1U << FSMC_BCR4_FACCEN_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 6871 #define FSMC_BCR4_FACCEN FSMC_BCR4_FACCEN_Msk /*!<Flash access enable */
lypinator 0:bb348c97df44 6872 #define FSMC_BCR4_BURSTEN_Pos (8U)
lypinator 0:bb348c97df44 6873 #define FSMC_BCR4_BURSTEN_Msk (0x1U << FSMC_BCR4_BURSTEN_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 6874 #define FSMC_BCR4_BURSTEN FSMC_BCR4_BURSTEN_Msk /*!<Burst enable bit */
lypinator 0:bb348c97df44 6875 #define FSMC_BCR4_WAITPOL_Pos (9U)
lypinator 0:bb348c97df44 6876 #define FSMC_BCR4_WAITPOL_Msk (0x1U << FSMC_BCR4_WAITPOL_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 6877 #define FSMC_BCR4_WAITPOL FSMC_BCR4_WAITPOL_Msk /*!<Wait signal polarity bit */
lypinator 0:bb348c97df44 6878 #define FSMC_BCR4_WAITCFG_Pos (11U)
lypinator 0:bb348c97df44 6879 #define FSMC_BCR4_WAITCFG_Msk (0x1U << FSMC_BCR4_WAITCFG_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 6880 #define FSMC_BCR4_WAITCFG FSMC_BCR4_WAITCFG_Msk /*!<Wait timing configuration */
lypinator 0:bb348c97df44 6881 #define FSMC_BCR4_WREN_Pos (12U)
lypinator 0:bb348c97df44 6882 #define FSMC_BCR4_WREN_Msk (0x1U << FSMC_BCR4_WREN_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 6883 #define FSMC_BCR4_WREN FSMC_BCR4_WREN_Msk /*!<Write enable bit */
lypinator 0:bb348c97df44 6884 #define FSMC_BCR4_WAITEN_Pos (13U)
lypinator 0:bb348c97df44 6885 #define FSMC_BCR4_WAITEN_Msk (0x1U << FSMC_BCR4_WAITEN_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 6886 #define FSMC_BCR4_WAITEN FSMC_BCR4_WAITEN_Msk /*!<Wait enable bit */
lypinator 0:bb348c97df44 6887 #define FSMC_BCR4_EXTMOD_Pos (14U)
lypinator 0:bb348c97df44 6888 #define FSMC_BCR4_EXTMOD_Msk (0x1U << FSMC_BCR4_EXTMOD_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 6889 #define FSMC_BCR4_EXTMOD FSMC_BCR4_EXTMOD_Msk /*!<Extended mode enable */
lypinator 0:bb348c97df44 6890 #define FSMC_BCR4_ASYNCWAIT_Pos (15U)
lypinator 0:bb348c97df44 6891 #define FSMC_BCR4_ASYNCWAIT_Msk (0x1U << FSMC_BCR4_ASYNCWAIT_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 6892 #define FSMC_BCR4_ASYNCWAIT FSMC_BCR4_ASYNCWAIT_Msk /*!<Asynchronous wait */
lypinator 0:bb348c97df44 6893 #define FSMC_BCR4_CPSIZE_Pos (16U)
lypinator 0:bb348c97df44 6894 #define FSMC_BCR4_CPSIZE_Msk (0x7U << FSMC_BCR4_CPSIZE_Pos) /*!< 0x00070000 */
lypinator 0:bb348c97df44 6895 #define FSMC_BCR4_CPSIZE FSMC_BCR4_CPSIZE_Msk /*!<CRAM page size */
lypinator 0:bb348c97df44 6896 #define FSMC_BCR4_CPSIZE_0 (0x1U << FSMC_BCR4_CPSIZE_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 6897 #define FSMC_BCR4_CPSIZE_1 (0x2U << FSMC_BCR4_CPSIZE_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 6898 #define FSMC_BCR4_CPSIZE_2 (0x4U << FSMC_BCR4_CPSIZE_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 6899 #define FSMC_BCR4_CBURSTRW_Pos (19U)
lypinator 0:bb348c97df44 6900 #define FSMC_BCR4_CBURSTRW_Msk (0x1U << FSMC_BCR4_CBURSTRW_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 6901 #define FSMC_BCR4_CBURSTRW FSMC_BCR4_CBURSTRW_Msk /*!<Write burst enable */
lypinator 0:bb348c97df44 6902
lypinator 0:bb348c97df44 6903 /****************** Bit definition for FSMC_BTR1 register ******************/
lypinator 0:bb348c97df44 6904 #define FSMC_BTR1_ADDSET_Pos (0U)
lypinator 0:bb348c97df44 6905 #define FSMC_BTR1_ADDSET_Msk (0xFU << FSMC_BTR1_ADDSET_Pos) /*!< 0x0000000F */
lypinator 0:bb348c97df44 6906 #define FSMC_BTR1_ADDSET FSMC_BTR1_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
lypinator 0:bb348c97df44 6907 #define FSMC_BTR1_ADDSET_0 (0x1U << FSMC_BTR1_ADDSET_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 6908 #define FSMC_BTR1_ADDSET_1 (0x2U << FSMC_BTR1_ADDSET_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 6909 #define FSMC_BTR1_ADDSET_2 (0x4U << FSMC_BTR1_ADDSET_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 6910 #define FSMC_BTR1_ADDSET_3 (0x8U << FSMC_BTR1_ADDSET_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 6911
lypinator 0:bb348c97df44 6912 #define FSMC_BTR1_ADDHLD_Pos (4U)
lypinator 0:bb348c97df44 6913 #define FSMC_BTR1_ADDHLD_Msk (0xFU << FSMC_BTR1_ADDHLD_Pos) /*!< 0x000000F0 */
lypinator 0:bb348c97df44 6914 #define FSMC_BTR1_ADDHLD FSMC_BTR1_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
lypinator 0:bb348c97df44 6915 #define FSMC_BTR1_ADDHLD_0 (0x1U << FSMC_BTR1_ADDHLD_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 6916 #define FSMC_BTR1_ADDHLD_1 (0x2U << FSMC_BTR1_ADDHLD_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 6917 #define FSMC_BTR1_ADDHLD_2 (0x4U << FSMC_BTR1_ADDHLD_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 6918 #define FSMC_BTR1_ADDHLD_3 (0x8U << FSMC_BTR1_ADDHLD_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 6919
lypinator 0:bb348c97df44 6920 #define FSMC_BTR1_DATAST_Pos (8U)
lypinator 0:bb348c97df44 6921 #define FSMC_BTR1_DATAST_Msk (0xFFU << FSMC_BTR1_DATAST_Pos) /*!< 0x0000FF00 */
lypinator 0:bb348c97df44 6922 #define FSMC_BTR1_DATAST FSMC_BTR1_DATAST_Msk /*!<DATAST [7:0] bits (Data-phase duration) */
lypinator 0:bb348c97df44 6923 #define FSMC_BTR1_DATAST_0 (0x01U << FSMC_BTR1_DATAST_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 6924 #define FSMC_BTR1_DATAST_1 (0x02U << FSMC_BTR1_DATAST_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 6925 #define FSMC_BTR1_DATAST_2 (0x04U << FSMC_BTR1_DATAST_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 6926 #define FSMC_BTR1_DATAST_3 (0x08U << FSMC_BTR1_DATAST_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 6927 #define FSMC_BTR1_DATAST_4 (0x10U << FSMC_BTR1_DATAST_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 6928 #define FSMC_BTR1_DATAST_5 (0x20U << FSMC_BTR1_DATAST_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 6929 #define FSMC_BTR1_DATAST_6 (0x40U << FSMC_BTR1_DATAST_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 6930 #define FSMC_BTR1_DATAST_7 (0x80U << FSMC_BTR1_DATAST_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 6931
lypinator 0:bb348c97df44 6932 #define FSMC_BTR1_BUSTURN_Pos (16U)
lypinator 0:bb348c97df44 6933 #define FSMC_BTR1_BUSTURN_Msk (0xFU << FSMC_BTR1_BUSTURN_Pos) /*!< 0x000F0000 */
lypinator 0:bb348c97df44 6934 #define FSMC_BTR1_BUSTURN FSMC_BTR1_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
lypinator 0:bb348c97df44 6935 #define FSMC_BTR1_BUSTURN_0 (0x1U << FSMC_BTR1_BUSTURN_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 6936 #define FSMC_BTR1_BUSTURN_1 (0x2U << FSMC_BTR1_BUSTURN_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 6937 #define FSMC_BTR1_BUSTURN_2 (0x4U << FSMC_BTR1_BUSTURN_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 6938 #define FSMC_BTR1_BUSTURN_3 (0x8U << FSMC_BTR1_BUSTURN_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 6939
lypinator 0:bb348c97df44 6940 #define FSMC_BTR1_CLKDIV_Pos (20U)
lypinator 0:bb348c97df44 6941 #define FSMC_BTR1_CLKDIV_Msk (0xFU << FSMC_BTR1_CLKDIV_Pos) /*!< 0x00F00000 */
lypinator 0:bb348c97df44 6942 #define FSMC_BTR1_CLKDIV FSMC_BTR1_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
lypinator 0:bb348c97df44 6943 #define FSMC_BTR1_CLKDIV_0 (0x1U << FSMC_BTR1_CLKDIV_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 6944 #define FSMC_BTR1_CLKDIV_1 (0x2U << FSMC_BTR1_CLKDIV_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 6945 #define FSMC_BTR1_CLKDIV_2 (0x4U << FSMC_BTR1_CLKDIV_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 6946 #define FSMC_BTR1_CLKDIV_3 (0x8U << FSMC_BTR1_CLKDIV_Pos) /*!< 0x00800000 */
lypinator 0:bb348c97df44 6947
lypinator 0:bb348c97df44 6948 #define FSMC_BTR1_DATLAT_Pos (24U)
lypinator 0:bb348c97df44 6949 #define FSMC_BTR1_DATLAT_Msk (0xFU << FSMC_BTR1_DATLAT_Pos) /*!< 0x0F000000 */
lypinator 0:bb348c97df44 6950 #define FSMC_BTR1_DATLAT FSMC_BTR1_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
lypinator 0:bb348c97df44 6951 #define FSMC_BTR1_DATLAT_0 (0x1U << FSMC_BTR1_DATLAT_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 6952 #define FSMC_BTR1_DATLAT_1 (0x2U << FSMC_BTR1_DATLAT_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 6953 #define FSMC_BTR1_DATLAT_2 (0x4U << FSMC_BTR1_DATLAT_Pos) /*!< 0x04000000 */
lypinator 0:bb348c97df44 6954 #define FSMC_BTR1_DATLAT_3 (0x8U << FSMC_BTR1_DATLAT_Pos) /*!< 0x08000000 */
lypinator 0:bb348c97df44 6955
lypinator 0:bb348c97df44 6956 #define FSMC_BTR1_ACCMOD_Pos (28U)
lypinator 0:bb348c97df44 6957 #define FSMC_BTR1_ACCMOD_Msk (0x3U << FSMC_BTR1_ACCMOD_Pos) /*!< 0x30000000 */
lypinator 0:bb348c97df44 6958 #define FSMC_BTR1_ACCMOD FSMC_BTR1_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
lypinator 0:bb348c97df44 6959 #define FSMC_BTR1_ACCMOD_0 (0x1U << FSMC_BTR1_ACCMOD_Pos) /*!< 0x10000000 */
lypinator 0:bb348c97df44 6960 #define FSMC_BTR1_ACCMOD_1 (0x2U << FSMC_BTR1_ACCMOD_Pos) /*!< 0x20000000 */
lypinator 0:bb348c97df44 6961
lypinator 0:bb348c97df44 6962 /****************** Bit definition for FSMC_BTR2 register *******************/
lypinator 0:bb348c97df44 6963 #define FSMC_BTR2_ADDSET_Pos (0U)
lypinator 0:bb348c97df44 6964 #define FSMC_BTR2_ADDSET_Msk (0xFU << FSMC_BTR2_ADDSET_Pos) /*!< 0x0000000F */
lypinator 0:bb348c97df44 6965 #define FSMC_BTR2_ADDSET FSMC_BTR2_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
lypinator 0:bb348c97df44 6966 #define FSMC_BTR2_ADDSET_0 (0x1U << FSMC_BTR2_ADDSET_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 6967 #define FSMC_BTR2_ADDSET_1 (0x2U << FSMC_BTR2_ADDSET_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 6968 #define FSMC_BTR2_ADDSET_2 (0x4U << FSMC_BTR2_ADDSET_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 6969 #define FSMC_BTR2_ADDSET_3 (0x8U << FSMC_BTR2_ADDSET_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 6970
lypinator 0:bb348c97df44 6971 #define FSMC_BTR2_ADDHLD_Pos (4U)
lypinator 0:bb348c97df44 6972 #define FSMC_BTR2_ADDHLD_Msk (0xFU << FSMC_BTR2_ADDHLD_Pos) /*!< 0x000000F0 */
lypinator 0:bb348c97df44 6973 #define FSMC_BTR2_ADDHLD FSMC_BTR2_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
lypinator 0:bb348c97df44 6974 #define FSMC_BTR2_ADDHLD_0 (0x1U << FSMC_BTR2_ADDHLD_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 6975 #define FSMC_BTR2_ADDHLD_1 (0x2U << FSMC_BTR2_ADDHLD_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 6976 #define FSMC_BTR2_ADDHLD_2 (0x4U << FSMC_BTR2_ADDHLD_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 6977 #define FSMC_BTR2_ADDHLD_3 (0x8U << FSMC_BTR2_ADDHLD_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 6978
lypinator 0:bb348c97df44 6979 #define FSMC_BTR2_DATAST_Pos (8U)
lypinator 0:bb348c97df44 6980 #define FSMC_BTR2_DATAST_Msk (0xFFU << FSMC_BTR2_DATAST_Pos) /*!< 0x0000FF00 */
lypinator 0:bb348c97df44 6981 #define FSMC_BTR2_DATAST FSMC_BTR2_DATAST_Msk /*!<DATAST [7:0] bits (Data-phase duration) */
lypinator 0:bb348c97df44 6982 #define FSMC_BTR2_DATAST_0 (0x01U << FSMC_BTR2_DATAST_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 6983 #define FSMC_BTR2_DATAST_1 (0x02U << FSMC_BTR2_DATAST_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 6984 #define FSMC_BTR2_DATAST_2 (0x04U << FSMC_BTR2_DATAST_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 6985 #define FSMC_BTR2_DATAST_3 (0x08U << FSMC_BTR2_DATAST_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 6986 #define FSMC_BTR2_DATAST_4 (0x10U << FSMC_BTR2_DATAST_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 6987 #define FSMC_BTR2_DATAST_5 (0x20U << FSMC_BTR2_DATAST_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 6988 #define FSMC_BTR2_DATAST_6 (0x40U << FSMC_BTR2_DATAST_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 6989 #define FSMC_BTR2_DATAST_7 (0x80U << FSMC_BTR2_DATAST_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 6990
lypinator 0:bb348c97df44 6991 #define FSMC_BTR2_BUSTURN_Pos (16U)
lypinator 0:bb348c97df44 6992 #define FSMC_BTR2_BUSTURN_Msk (0xFU << FSMC_BTR2_BUSTURN_Pos) /*!< 0x000F0000 */
lypinator 0:bb348c97df44 6993 #define FSMC_BTR2_BUSTURN FSMC_BTR2_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
lypinator 0:bb348c97df44 6994 #define FSMC_BTR2_BUSTURN_0 (0x1U << FSMC_BTR2_BUSTURN_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 6995 #define FSMC_BTR2_BUSTURN_1 (0x2U << FSMC_BTR2_BUSTURN_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 6996 #define FSMC_BTR2_BUSTURN_2 (0x4U << FSMC_BTR2_BUSTURN_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 6997 #define FSMC_BTR2_BUSTURN_3 (0x8U << FSMC_BTR2_BUSTURN_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 6998
lypinator 0:bb348c97df44 6999 #define FSMC_BTR2_CLKDIV_Pos (20U)
lypinator 0:bb348c97df44 7000 #define FSMC_BTR2_CLKDIV_Msk (0xFU << FSMC_BTR2_CLKDIV_Pos) /*!< 0x00F00000 */
lypinator 0:bb348c97df44 7001 #define FSMC_BTR2_CLKDIV FSMC_BTR2_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
lypinator 0:bb348c97df44 7002 #define FSMC_BTR2_CLKDIV_0 (0x1U << FSMC_BTR2_CLKDIV_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 7003 #define FSMC_BTR2_CLKDIV_1 (0x2U << FSMC_BTR2_CLKDIV_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 7004 #define FSMC_BTR2_CLKDIV_2 (0x4U << FSMC_BTR2_CLKDIV_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 7005 #define FSMC_BTR2_CLKDIV_3 (0x8U << FSMC_BTR2_CLKDIV_Pos) /*!< 0x00800000 */
lypinator 0:bb348c97df44 7006
lypinator 0:bb348c97df44 7007 #define FSMC_BTR2_DATLAT_Pos (24U)
lypinator 0:bb348c97df44 7008 #define FSMC_BTR2_DATLAT_Msk (0xFU << FSMC_BTR2_DATLAT_Pos) /*!< 0x0F000000 */
lypinator 0:bb348c97df44 7009 #define FSMC_BTR2_DATLAT FSMC_BTR2_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
lypinator 0:bb348c97df44 7010 #define FSMC_BTR2_DATLAT_0 (0x1U << FSMC_BTR2_DATLAT_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 7011 #define FSMC_BTR2_DATLAT_1 (0x2U << FSMC_BTR2_DATLAT_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 7012 #define FSMC_BTR2_DATLAT_2 (0x4U << FSMC_BTR2_DATLAT_Pos) /*!< 0x04000000 */
lypinator 0:bb348c97df44 7013 #define FSMC_BTR2_DATLAT_3 (0x8U << FSMC_BTR2_DATLAT_Pos) /*!< 0x08000000 */
lypinator 0:bb348c97df44 7014
lypinator 0:bb348c97df44 7015 #define FSMC_BTR2_ACCMOD_Pos (28U)
lypinator 0:bb348c97df44 7016 #define FSMC_BTR2_ACCMOD_Msk (0x3U << FSMC_BTR2_ACCMOD_Pos) /*!< 0x30000000 */
lypinator 0:bb348c97df44 7017 #define FSMC_BTR2_ACCMOD FSMC_BTR2_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
lypinator 0:bb348c97df44 7018 #define FSMC_BTR2_ACCMOD_0 (0x1U << FSMC_BTR2_ACCMOD_Pos) /*!< 0x10000000 */
lypinator 0:bb348c97df44 7019 #define FSMC_BTR2_ACCMOD_1 (0x2U << FSMC_BTR2_ACCMOD_Pos) /*!< 0x20000000 */
lypinator 0:bb348c97df44 7020
lypinator 0:bb348c97df44 7021 /******************* Bit definition for FSMC_BTR3 register *******************/
lypinator 0:bb348c97df44 7022 #define FSMC_BTR3_ADDSET_Pos (0U)
lypinator 0:bb348c97df44 7023 #define FSMC_BTR3_ADDSET_Msk (0xFU << FSMC_BTR3_ADDSET_Pos) /*!< 0x0000000F */
lypinator 0:bb348c97df44 7024 #define FSMC_BTR3_ADDSET FSMC_BTR3_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
lypinator 0:bb348c97df44 7025 #define FSMC_BTR3_ADDSET_0 (0x1U << FSMC_BTR3_ADDSET_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 7026 #define FSMC_BTR3_ADDSET_1 (0x2U << FSMC_BTR3_ADDSET_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 7027 #define FSMC_BTR3_ADDSET_2 (0x4U << FSMC_BTR3_ADDSET_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 7028 #define FSMC_BTR3_ADDSET_3 (0x8U << FSMC_BTR3_ADDSET_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 7029
lypinator 0:bb348c97df44 7030 #define FSMC_BTR3_ADDHLD_Pos (4U)
lypinator 0:bb348c97df44 7031 #define FSMC_BTR3_ADDHLD_Msk (0xFU << FSMC_BTR3_ADDHLD_Pos) /*!< 0x000000F0 */
lypinator 0:bb348c97df44 7032 #define FSMC_BTR3_ADDHLD FSMC_BTR3_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
lypinator 0:bb348c97df44 7033 #define FSMC_BTR3_ADDHLD_0 (0x1U << FSMC_BTR3_ADDHLD_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 7034 #define FSMC_BTR3_ADDHLD_1 (0x2U << FSMC_BTR3_ADDHLD_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 7035 #define FSMC_BTR3_ADDHLD_2 (0x4U << FSMC_BTR3_ADDHLD_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 7036 #define FSMC_BTR3_ADDHLD_3 (0x8U << FSMC_BTR3_ADDHLD_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 7037
lypinator 0:bb348c97df44 7038 #define FSMC_BTR3_DATAST_Pos (8U)
lypinator 0:bb348c97df44 7039 #define FSMC_BTR3_DATAST_Msk (0xFFU << FSMC_BTR3_DATAST_Pos) /*!< 0x0000FF00 */
lypinator 0:bb348c97df44 7040 #define FSMC_BTR3_DATAST FSMC_BTR3_DATAST_Msk /*!<DATAST [7:0] bits (Data-phase duration) */
lypinator 0:bb348c97df44 7041 #define FSMC_BTR3_DATAST_0 (0x01U << FSMC_BTR3_DATAST_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 7042 #define FSMC_BTR3_DATAST_1 (0x02U << FSMC_BTR3_DATAST_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 7043 #define FSMC_BTR3_DATAST_2 (0x04U << FSMC_BTR3_DATAST_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 7044 #define FSMC_BTR3_DATAST_3 (0x08U << FSMC_BTR3_DATAST_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 7045 #define FSMC_BTR3_DATAST_4 (0x10U << FSMC_BTR3_DATAST_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 7046 #define FSMC_BTR3_DATAST_5 (0x20U << FSMC_BTR3_DATAST_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 7047 #define FSMC_BTR3_DATAST_6 (0x40U << FSMC_BTR3_DATAST_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 7048 #define FSMC_BTR3_DATAST_7 (0x80U << FSMC_BTR3_DATAST_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 7049
lypinator 0:bb348c97df44 7050 #define FSMC_BTR3_BUSTURN_Pos (16U)
lypinator 0:bb348c97df44 7051 #define FSMC_BTR3_BUSTURN_Msk (0xFU << FSMC_BTR3_BUSTURN_Pos) /*!< 0x000F0000 */
lypinator 0:bb348c97df44 7052 #define FSMC_BTR3_BUSTURN FSMC_BTR3_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
lypinator 0:bb348c97df44 7053 #define FSMC_BTR3_BUSTURN_0 (0x1U << FSMC_BTR3_BUSTURN_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 7054 #define FSMC_BTR3_BUSTURN_1 (0x2U << FSMC_BTR3_BUSTURN_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 7055 #define FSMC_BTR3_BUSTURN_2 (0x4U << FSMC_BTR3_BUSTURN_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 7056 #define FSMC_BTR3_BUSTURN_3 (0x8U << FSMC_BTR3_BUSTURN_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 7057
lypinator 0:bb348c97df44 7058 #define FSMC_BTR3_CLKDIV_Pos (20U)
lypinator 0:bb348c97df44 7059 #define FSMC_BTR3_CLKDIV_Msk (0xFU << FSMC_BTR3_CLKDIV_Pos) /*!< 0x00F00000 */
lypinator 0:bb348c97df44 7060 #define FSMC_BTR3_CLKDIV FSMC_BTR3_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
lypinator 0:bb348c97df44 7061 #define FSMC_BTR3_CLKDIV_0 (0x1U << FSMC_BTR3_CLKDIV_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 7062 #define FSMC_BTR3_CLKDIV_1 (0x2U << FSMC_BTR3_CLKDIV_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 7063 #define FSMC_BTR3_CLKDIV_2 (0x4U << FSMC_BTR3_CLKDIV_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 7064 #define FSMC_BTR3_CLKDIV_3 (0x8U << FSMC_BTR3_CLKDIV_Pos) /*!< 0x00800000 */
lypinator 0:bb348c97df44 7065
lypinator 0:bb348c97df44 7066 #define FSMC_BTR3_DATLAT_Pos (24U)
lypinator 0:bb348c97df44 7067 #define FSMC_BTR3_DATLAT_Msk (0xFU << FSMC_BTR3_DATLAT_Pos) /*!< 0x0F000000 */
lypinator 0:bb348c97df44 7068 #define FSMC_BTR3_DATLAT FSMC_BTR3_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
lypinator 0:bb348c97df44 7069 #define FSMC_BTR3_DATLAT_0 (0x1U << FSMC_BTR3_DATLAT_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 7070 #define FSMC_BTR3_DATLAT_1 (0x2U << FSMC_BTR3_DATLAT_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 7071 #define FSMC_BTR3_DATLAT_2 (0x4U << FSMC_BTR3_DATLAT_Pos) /*!< 0x04000000 */
lypinator 0:bb348c97df44 7072 #define FSMC_BTR3_DATLAT_3 (0x8U << FSMC_BTR3_DATLAT_Pos) /*!< 0x08000000 */
lypinator 0:bb348c97df44 7073
lypinator 0:bb348c97df44 7074 #define FSMC_BTR3_ACCMOD_Pos (28U)
lypinator 0:bb348c97df44 7075 #define FSMC_BTR3_ACCMOD_Msk (0x3U << FSMC_BTR3_ACCMOD_Pos) /*!< 0x30000000 */
lypinator 0:bb348c97df44 7076 #define FSMC_BTR3_ACCMOD FSMC_BTR3_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
lypinator 0:bb348c97df44 7077 #define FSMC_BTR3_ACCMOD_0 (0x1U << FSMC_BTR3_ACCMOD_Pos) /*!< 0x10000000 */
lypinator 0:bb348c97df44 7078 #define FSMC_BTR3_ACCMOD_1 (0x2U << FSMC_BTR3_ACCMOD_Pos) /*!< 0x20000000 */
lypinator 0:bb348c97df44 7079
lypinator 0:bb348c97df44 7080 /****************** Bit definition for FSMC_BTR4 register *******************/
lypinator 0:bb348c97df44 7081 #define FSMC_BTR4_ADDSET_Pos (0U)
lypinator 0:bb348c97df44 7082 #define FSMC_BTR4_ADDSET_Msk (0xFU << FSMC_BTR4_ADDSET_Pos) /*!< 0x0000000F */
lypinator 0:bb348c97df44 7083 #define FSMC_BTR4_ADDSET FSMC_BTR4_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
lypinator 0:bb348c97df44 7084 #define FSMC_BTR4_ADDSET_0 (0x1U << FSMC_BTR4_ADDSET_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 7085 #define FSMC_BTR4_ADDSET_1 (0x2U << FSMC_BTR4_ADDSET_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 7086 #define FSMC_BTR4_ADDSET_2 (0x4U << FSMC_BTR4_ADDSET_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 7087 #define FSMC_BTR4_ADDSET_3 (0x8U << FSMC_BTR4_ADDSET_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 7088
lypinator 0:bb348c97df44 7089 #define FSMC_BTR4_ADDHLD_Pos (4U)
lypinator 0:bb348c97df44 7090 #define FSMC_BTR4_ADDHLD_Msk (0xFU << FSMC_BTR4_ADDHLD_Pos) /*!< 0x000000F0 */
lypinator 0:bb348c97df44 7091 #define FSMC_BTR4_ADDHLD FSMC_BTR4_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
lypinator 0:bb348c97df44 7092 #define FSMC_BTR4_ADDHLD_0 (0x1U << FSMC_BTR4_ADDHLD_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 7093 #define FSMC_BTR4_ADDHLD_1 (0x2U << FSMC_BTR4_ADDHLD_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 7094 #define FSMC_BTR4_ADDHLD_2 (0x4U << FSMC_BTR4_ADDHLD_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 7095 #define FSMC_BTR4_ADDHLD_3 (0x8U << FSMC_BTR4_ADDHLD_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 7096
lypinator 0:bb348c97df44 7097 #define FSMC_BTR4_DATAST_Pos (8U)
lypinator 0:bb348c97df44 7098 #define FSMC_BTR4_DATAST_Msk (0xFFU << FSMC_BTR4_DATAST_Pos) /*!< 0x0000FF00 */
lypinator 0:bb348c97df44 7099 #define FSMC_BTR4_DATAST FSMC_BTR4_DATAST_Msk /*!<DATAST [7:0] bits (Data-phase duration) */
lypinator 0:bb348c97df44 7100 #define FSMC_BTR4_DATAST_0 (0x01U << FSMC_BTR4_DATAST_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 7101 #define FSMC_BTR4_DATAST_1 (0x02U << FSMC_BTR4_DATAST_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 7102 #define FSMC_BTR4_DATAST_2 (0x04U << FSMC_BTR4_DATAST_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 7103 #define FSMC_BTR4_DATAST_3 (0x08U << FSMC_BTR4_DATAST_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 7104 #define FSMC_BTR4_DATAST_4 (0x10U << FSMC_BTR4_DATAST_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 7105 #define FSMC_BTR4_DATAST_5 (0x20U << FSMC_BTR4_DATAST_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 7106 #define FSMC_BTR4_DATAST_6 (0x40U << FSMC_BTR4_DATAST_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 7107 #define FSMC_BTR4_DATAST_7 (0x80U << FSMC_BTR4_DATAST_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 7108
lypinator 0:bb348c97df44 7109 #define FSMC_BTR4_BUSTURN_Pos (16U)
lypinator 0:bb348c97df44 7110 #define FSMC_BTR4_BUSTURN_Msk (0xFU << FSMC_BTR4_BUSTURN_Pos) /*!< 0x000F0000 */
lypinator 0:bb348c97df44 7111 #define FSMC_BTR4_BUSTURN FSMC_BTR4_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
lypinator 0:bb348c97df44 7112 #define FSMC_BTR4_BUSTURN_0 (0x1U << FSMC_BTR4_BUSTURN_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 7113 #define FSMC_BTR4_BUSTURN_1 (0x2U << FSMC_BTR4_BUSTURN_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 7114 #define FSMC_BTR4_BUSTURN_2 (0x4U << FSMC_BTR4_BUSTURN_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 7115 #define FSMC_BTR4_BUSTURN_3 (0x8U << FSMC_BTR4_BUSTURN_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 7116
lypinator 0:bb348c97df44 7117 #define FSMC_BTR4_CLKDIV_Pos (20U)
lypinator 0:bb348c97df44 7118 #define FSMC_BTR4_CLKDIV_Msk (0xFU << FSMC_BTR4_CLKDIV_Pos) /*!< 0x00F00000 */
lypinator 0:bb348c97df44 7119 #define FSMC_BTR4_CLKDIV FSMC_BTR4_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
lypinator 0:bb348c97df44 7120 #define FSMC_BTR4_CLKDIV_0 (0x1U << FSMC_BTR4_CLKDIV_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 7121 #define FSMC_BTR4_CLKDIV_1 (0x2U << FSMC_BTR4_CLKDIV_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 7122 #define FSMC_BTR4_CLKDIV_2 (0x4U << FSMC_BTR4_CLKDIV_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 7123 #define FSMC_BTR4_CLKDIV_3 (0x8U << FSMC_BTR4_CLKDIV_Pos) /*!< 0x00800000 */
lypinator 0:bb348c97df44 7124
lypinator 0:bb348c97df44 7125 #define FSMC_BTR4_DATLAT_Pos (24U)
lypinator 0:bb348c97df44 7126 #define FSMC_BTR4_DATLAT_Msk (0xFU << FSMC_BTR4_DATLAT_Pos) /*!< 0x0F000000 */
lypinator 0:bb348c97df44 7127 #define FSMC_BTR4_DATLAT FSMC_BTR4_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
lypinator 0:bb348c97df44 7128 #define FSMC_BTR4_DATLAT_0 (0x1U << FSMC_BTR4_DATLAT_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 7129 #define FSMC_BTR4_DATLAT_1 (0x2U << FSMC_BTR4_DATLAT_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 7130 #define FSMC_BTR4_DATLAT_2 (0x4U << FSMC_BTR4_DATLAT_Pos) /*!< 0x04000000 */
lypinator 0:bb348c97df44 7131 #define FSMC_BTR4_DATLAT_3 (0x8U << FSMC_BTR4_DATLAT_Pos) /*!< 0x08000000 */
lypinator 0:bb348c97df44 7132
lypinator 0:bb348c97df44 7133 #define FSMC_BTR4_ACCMOD_Pos (28U)
lypinator 0:bb348c97df44 7134 #define FSMC_BTR4_ACCMOD_Msk (0x3U << FSMC_BTR4_ACCMOD_Pos) /*!< 0x30000000 */
lypinator 0:bb348c97df44 7135 #define FSMC_BTR4_ACCMOD FSMC_BTR4_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
lypinator 0:bb348c97df44 7136 #define FSMC_BTR4_ACCMOD_0 (0x1U << FSMC_BTR4_ACCMOD_Pos) /*!< 0x10000000 */
lypinator 0:bb348c97df44 7137 #define FSMC_BTR4_ACCMOD_1 (0x2U << FSMC_BTR4_ACCMOD_Pos) /*!< 0x20000000 */
lypinator 0:bb348c97df44 7138
lypinator 0:bb348c97df44 7139 /****************** Bit definition for FSMC_BWTR1 register ******************/
lypinator 0:bb348c97df44 7140 #define FSMC_BWTR1_ADDSET_Pos (0U)
lypinator 0:bb348c97df44 7141 #define FSMC_BWTR1_ADDSET_Msk (0xFU << FSMC_BWTR1_ADDSET_Pos) /*!< 0x0000000F */
lypinator 0:bb348c97df44 7142 #define FSMC_BWTR1_ADDSET FSMC_BWTR1_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
lypinator 0:bb348c97df44 7143 #define FSMC_BWTR1_ADDSET_0 (0x1U << FSMC_BWTR1_ADDSET_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 7144 #define FSMC_BWTR1_ADDSET_1 (0x2U << FSMC_BWTR1_ADDSET_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 7145 #define FSMC_BWTR1_ADDSET_2 (0x4U << FSMC_BWTR1_ADDSET_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 7146 #define FSMC_BWTR1_ADDSET_3 (0x8U << FSMC_BWTR1_ADDSET_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 7147
lypinator 0:bb348c97df44 7148 #define FSMC_BWTR1_ADDHLD_Pos (4U)
lypinator 0:bb348c97df44 7149 #define FSMC_BWTR1_ADDHLD_Msk (0xFU << FSMC_BWTR1_ADDHLD_Pos) /*!< 0x000000F0 */
lypinator 0:bb348c97df44 7150 #define FSMC_BWTR1_ADDHLD FSMC_BWTR1_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
lypinator 0:bb348c97df44 7151 #define FSMC_BWTR1_ADDHLD_0 (0x1U << FSMC_BWTR1_ADDHLD_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 7152 #define FSMC_BWTR1_ADDHLD_1 (0x2U << FSMC_BWTR1_ADDHLD_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 7153 #define FSMC_BWTR1_ADDHLD_2 (0x4U << FSMC_BWTR1_ADDHLD_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 7154 #define FSMC_BWTR1_ADDHLD_3 (0x8U << FSMC_BWTR1_ADDHLD_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 7155
lypinator 0:bb348c97df44 7156 #define FSMC_BWTR1_DATAST_Pos (8U)
lypinator 0:bb348c97df44 7157 #define FSMC_BWTR1_DATAST_Msk (0xFFU << FSMC_BWTR1_DATAST_Pos) /*!< 0x0000FF00 */
lypinator 0:bb348c97df44 7158 #define FSMC_BWTR1_DATAST FSMC_BWTR1_DATAST_Msk /*!<DATAST [7:0] bits (Data-phase duration) */
lypinator 0:bb348c97df44 7159 #define FSMC_BWTR1_DATAST_0 (0x01U << FSMC_BWTR1_DATAST_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 7160 #define FSMC_BWTR1_DATAST_1 (0x02U << FSMC_BWTR1_DATAST_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 7161 #define FSMC_BWTR1_DATAST_2 (0x04U << FSMC_BWTR1_DATAST_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 7162 #define FSMC_BWTR1_DATAST_3 (0x08U << FSMC_BWTR1_DATAST_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 7163 #define FSMC_BWTR1_DATAST_4 (0x10U << FSMC_BWTR1_DATAST_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 7164 #define FSMC_BWTR1_DATAST_5 (0x20U << FSMC_BWTR1_DATAST_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 7165 #define FSMC_BWTR1_DATAST_6 (0x40U << FSMC_BWTR1_DATAST_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 7166 #define FSMC_BWTR1_DATAST_7 (0x80U << FSMC_BWTR1_DATAST_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 7167
lypinator 0:bb348c97df44 7168 #define FSMC_BWTR1_BUSTURN_Pos (16U)
lypinator 0:bb348c97df44 7169 #define FSMC_BWTR1_BUSTURN_Msk (0xFU << FSMC_BWTR1_BUSTURN_Pos) /*!< 0x000F0000 */
lypinator 0:bb348c97df44 7170 #define FSMC_BWTR1_BUSTURN FSMC_BWTR1_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
lypinator 0:bb348c97df44 7171 #define FSMC_BWTR1_BUSTURN_0 (0x1U << FSMC_BWTR1_BUSTURN_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 7172 #define FSMC_BWTR1_BUSTURN_1 (0x2U << FSMC_BWTR1_BUSTURN_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 7173 #define FSMC_BWTR1_BUSTURN_2 (0x4U << FSMC_BWTR1_BUSTURN_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 7174 #define FSMC_BWTR1_BUSTURN_3 (0x8U << FSMC_BWTR1_BUSTURN_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 7175
lypinator 0:bb348c97df44 7176 #define FSMC_BWTR1_ACCMOD_Pos (28U)
lypinator 0:bb348c97df44 7177 #define FSMC_BWTR1_ACCMOD_Msk (0x3U << FSMC_BWTR1_ACCMOD_Pos) /*!< 0x30000000 */
lypinator 0:bb348c97df44 7178 #define FSMC_BWTR1_ACCMOD FSMC_BWTR1_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
lypinator 0:bb348c97df44 7179 #define FSMC_BWTR1_ACCMOD_0 (0x1U << FSMC_BWTR1_ACCMOD_Pos) /*!< 0x10000000 */
lypinator 0:bb348c97df44 7180 #define FSMC_BWTR1_ACCMOD_1 (0x2U << FSMC_BWTR1_ACCMOD_Pos) /*!< 0x20000000 */
lypinator 0:bb348c97df44 7181
lypinator 0:bb348c97df44 7182 /****************** Bit definition for FSMC_BWTR2 register ******************/
lypinator 0:bb348c97df44 7183 #define FSMC_BWTR2_ADDSET_Pos (0U)
lypinator 0:bb348c97df44 7184 #define FSMC_BWTR2_ADDSET_Msk (0xFU << FSMC_BWTR2_ADDSET_Pos) /*!< 0x0000000F */
lypinator 0:bb348c97df44 7185 #define FSMC_BWTR2_ADDSET FSMC_BWTR2_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
lypinator 0:bb348c97df44 7186 #define FSMC_BWTR2_ADDSET_0 (0x1U << FSMC_BWTR2_ADDSET_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 7187 #define FSMC_BWTR2_ADDSET_1 (0x2U << FSMC_BWTR2_ADDSET_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 7188 #define FSMC_BWTR2_ADDSET_2 (0x4U << FSMC_BWTR2_ADDSET_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 7189 #define FSMC_BWTR2_ADDSET_3 (0x8U << FSMC_BWTR2_ADDSET_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 7190
lypinator 0:bb348c97df44 7191 #define FSMC_BWTR2_ADDHLD_Pos (4U)
lypinator 0:bb348c97df44 7192 #define FSMC_BWTR2_ADDHLD_Msk (0xFU << FSMC_BWTR2_ADDHLD_Pos) /*!< 0x000000F0 */
lypinator 0:bb348c97df44 7193 #define FSMC_BWTR2_ADDHLD FSMC_BWTR2_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
lypinator 0:bb348c97df44 7194 #define FSMC_BWTR2_ADDHLD_0 (0x1U << FSMC_BWTR2_ADDHLD_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 7195 #define FSMC_BWTR2_ADDHLD_1 (0x2U << FSMC_BWTR2_ADDHLD_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 7196 #define FSMC_BWTR2_ADDHLD_2 (0x4U << FSMC_BWTR2_ADDHLD_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 7197 #define FSMC_BWTR2_ADDHLD_3 (0x8U << FSMC_BWTR2_ADDHLD_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 7198
lypinator 0:bb348c97df44 7199 #define FSMC_BWTR2_DATAST_Pos (8U)
lypinator 0:bb348c97df44 7200 #define FSMC_BWTR2_DATAST_Msk (0xFFU << FSMC_BWTR2_DATAST_Pos) /*!< 0x0000FF00 */
lypinator 0:bb348c97df44 7201 #define FSMC_BWTR2_DATAST FSMC_BWTR2_DATAST_Msk /*!<DATAST [7:0] bits (Data-phase duration) */
lypinator 0:bb348c97df44 7202 #define FSMC_BWTR2_DATAST_0 (0x01U << FSMC_BWTR2_DATAST_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 7203 #define FSMC_BWTR2_DATAST_1 (0x02U << FSMC_BWTR2_DATAST_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 7204 #define FSMC_BWTR2_DATAST_2 (0x04U << FSMC_BWTR2_DATAST_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 7205 #define FSMC_BWTR2_DATAST_3 (0x08U << FSMC_BWTR2_DATAST_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 7206 #define FSMC_BWTR2_DATAST_4 (0x10U << FSMC_BWTR2_DATAST_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 7207 #define FSMC_BWTR2_DATAST_5 (0x20U << FSMC_BWTR2_DATAST_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 7208 #define FSMC_BWTR2_DATAST_6 (0x40U << FSMC_BWTR2_DATAST_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 7209 #define FSMC_BWTR2_DATAST_7 (0x80U << FSMC_BWTR2_DATAST_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 7210
lypinator 0:bb348c97df44 7211 #define FSMC_BWTR2_BUSTURN_Pos (16U)
lypinator 0:bb348c97df44 7212 #define FSMC_BWTR2_BUSTURN_Msk (0xFU << FSMC_BWTR2_BUSTURN_Pos) /*!< 0x000F0000 */
lypinator 0:bb348c97df44 7213 #define FSMC_BWTR2_BUSTURN FSMC_BWTR2_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
lypinator 0:bb348c97df44 7214 #define FSMC_BWTR2_BUSTURN_0 (0x1U << FSMC_BWTR2_BUSTURN_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 7215 #define FSMC_BWTR2_BUSTURN_1 (0x2U << FSMC_BWTR2_BUSTURN_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 7216 #define FSMC_BWTR2_BUSTURN_2 (0x4U << FSMC_BWTR2_BUSTURN_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 7217 #define FSMC_BWTR2_BUSTURN_3 (0x8U << FSMC_BWTR2_BUSTURN_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 7218
lypinator 0:bb348c97df44 7219 #define FSMC_BWTR2_ACCMOD_Pos (28U)
lypinator 0:bb348c97df44 7220 #define FSMC_BWTR2_ACCMOD_Msk (0x3U << FSMC_BWTR2_ACCMOD_Pos) /*!< 0x30000000 */
lypinator 0:bb348c97df44 7221 #define FSMC_BWTR2_ACCMOD FSMC_BWTR2_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
lypinator 0:bb348c97df44 7222 #define FSMC_BWTR2_ACCMOD_0 (0x1U << FSMC_BWTR2_ACCMOD_Pos) /*!< 0x10000000 */
lypinator 0:bb348c97df44 7223 #define FSMC_BWTR2_ACCMOD_1 (0x2U << FSMC_BWTR2_ACCMOD_Pos) /*!< 0x20000000 */
lypinator 0:bb348c97df44 7224
lypinator 0:bb348c97df44 7225 /****************** Bit definition for FSMC_BWTR3 register ******************/
lypinator 0:bb348c97df44 7226 #define FSMC_BWTR3_ADDSET_Pos (0U)
lypinator 0:bb348c97df44 7227 #define FSMC_BWTR3_ADDSET_Msk (0xFU << FSMC_BWTR3_ADDSET_Pos) /*!< 0x0000000F */
lypinator 0:bb348c97df44 7228 #define FSMC_BWTR3_ADDSET FSMC_BWTR3_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
lypinator 0:bb348c97df44 7229 #define FSMC_BWTR3_ADDSET_0 (0x1U << FSMC_BWTR3_ADDSET_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 7230 #define FSMC_BWTR3_ADDSET_1 (0x2U << FSMC_BWTR3_ADDSET_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 7231 #define FSMC_BWTR3_ADDSET_2 (0x4U << FSMC_BWTR3_ADDSET_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 7232 #define FSMC_BWTR3_ADDSET_3 (0x8U << FSMC_BWTR3_ADDSET_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 7233
lypinator 0:bb348c97df44 7234 #define FSMC_BWTR3_ADDHLD_Pos (4U)
lypinator 0:bb348c97df44 7235 #define FSMC_BWTR3_ADDHLD_Msk (0xFU << FSMC_BWTR3_ADDHLD_Pos) /*!< 0x000000F0 */
lypinator 0:bb348c97df44 7236 #define FSMC_BWTR3_ADDHLD FSMC_BWTR3_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
lypinator 0:bb348c97df44 7237 #define FSMC_BWTR3_ADDHLD_0 (0x1U << FSMC_BWTR3_ADDHLD_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 7238 #define FSMC_BWTR3_ADDHLD_1 (0x2U << FSMC_BWTR3_ADDHLD_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 7239 #define FSMC_BWTR3_ADDHLD_2 (0x4U << FSMC_BWTR3_ADDHLD_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 7240 #define FSMC_BWTR3_ADDHLD_3 (0x8U << FSMC_BWTR3_ADDHLD_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 7241
lypinator 0:bb348c97df44 7242 #define FSMC_BWTR3_DATAST_Pos (8U)
lypinator 0:bb348c97df44 7243 #define FSMC_BWTR3_DATAST_Msk (0xFFU << FSMC_BWTR3_DATAST_Pos) /*!< 0x0000FF00 */
lypinator 0:bb348c97df44 7244 #define FSMC_BWTR3_DATAST FSMC_BWTR3_DATAST_Msk /*!<DATAST [7:0] bits (Data-phase duration) */
lypinator 0:bb348c97df44 7245 #define FSMC_BWTR3_DATAST_0 (0x01U << FSMC_BWTR3_DATAST_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 7246 #define FSMC_BWTR3_DATAST_1 (0x02U << FSMC_BWTR3_DATAST_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 7247 #define FSMC_BWTR3_DATAST_2 (0x04U << FSMC_BWTR3_DATAST_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 7248 #define FSMC_BWTR3_DATAST_3 (0x08U << FSMC_BWTR3_DATAST_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 7249 #define FSMC_BWTR3_DATAST_4 (0x10U << FSMC_BWTR3_DATAST_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 7250 #define FSMC_BWTR3_DATAST_5 (0x20U << FSMC_BWTR3_DATAST_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 7251 #define FSMC_BWTR3_DATAST_6 (0x40U << FSMC_BWTR3_DATAST_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 7252 #define FSMC_BWTR3_DATAST_7 (0x80U << FSMC_BWTR3_DATAST_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 7253
lypinator 0:bb348c97df44 7254 #define FSMC_BWTR3_BUSTURN_Pos (16U)
lypinator 0:bb348c97df44 7255 #define FSMC_BWTR3_BUSTURN_Msk (0xFU << FSMC_BWTR3_BUSTURN_Pos) /*!< 0x000F0000 */
lypinator 0:bb348c97df44 7256 #define FSMC_BWTR3_BUSTURN FSMC_BWTR3_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
lypinator 0:bb348c97df44 7257 #define FSMC_BWTR3_BUSTURN_0 (0x1U << FSMC_BWTR3_BUSTURN_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 7258 #define FSMC_BWTR3_BUSTURN_1 (0x2U << FSMC_BWTR3_BUSTURN_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 7259 #define FSMC_BWTR3_BUSTURN_2 (0x4U << FSMC_BWTR3_BUSTURN_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 7260 #define FSMC_BWTR3_BUSTURN_3 (0x8U << FSMC_BWTR3_BUSTURN_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 7261
lypinator 0:bb348c97df44 7262 #define FSMC_BWTR3_ACCMOD_Pos (28U)
lypinator 0:bb348c97df44 7263 #define FSMC_BWTR3_ACCMOD_Msk (0x3U << FSMC_BWTR3_ACCMOD_Pos) /*!< 0x30000000 */
lypinator 0:bb348c97df44 7264 #define FSMC_BWTR3_ACCMOD FSMC_BWTR3_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
lypinator 0:bb348c97df44 7265 #define FSMC_BWTR3_ACCMOD_0 (0x1U << FSMC_BWTR3_ACCMOD_Pos) /*!< 0x10000000 */
lypinator 0:bb348c97df44 7266 #define FSMC_BWTR3_ACCMOD_1 (0x2U << FSMC_BWTR3_ACCMOD_Pos) /*!< 0x20000000 */
lypinator 0:bb348c97df44 7267
lypinator 0:bb348c97df44 7268 /****************** Bit definition for FSMC_BWTR4 register ******************/
lypinator 0:bb348c97df44 7269 #define FSMC_BWTR4_ADDSET_Pos (0U)
lypinator 0:bb348c97df44 7270 #define FSMC_BWTR4_ADDSET_Msk (0xFU << FSMC_BWTR4_ADDSET_Pos) /*!< 0x0000000F */
lypinator 0:bb348c97df44 7271 #define FSMC_BWTR4_ADDSET FSMC_BWTR4_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
lypinator 0:bb348c97df44 7272 #define FSMC_BWTR4_ADDSET_0 (0x1U << FSMC_BWTR4_ADDSET_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 7273 #define FSMC_BWTR4_ADDSET_1 (0x2U << FSMC_BWTR4_ADDSET_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 7274 #define FSMC_BWTR4_ADDSET_2 (0x4U << FSMC_BWTR4_ADDSET_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 7275 #define FSMC_BWTR4_ADDSET_3 (0x8U << FSMC_BWTR4_ADDSET_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 7276
lypinator 0:bb348c97df44 7277 #define FSMC_BWTR4_ADDHLD_Pos (4U)
lypinator 0:bb348c97df44 7278 #define FSMC_BWTR4_ADDHLD_Msk (0xFU << FSMC_BWTR4_ADDHLD_Pos) /*!< 0x000000F0 */
lypinator 0:bb348c97df44 7279 #define FSMC_BWTR4_ADDHLD FSMC_BWTR4_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
lypinator 0:bb348c97df44 7280 #define FSMC_BWTR4_ADDHLD_0 (0x1U << FSMC_BWTR4_ADDHLD_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 7281 #define FSMC_BWTR4_ADDHLD_1 (0x2U << FSMC_BWTR4_ADDHLD_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 7282 #define FSMC_BWTR4_ADDHLD_2 (0x4U << FSMC_BWTR4_ADDHLD_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 7283 #define FSMC_BWTR4_ADDHLD_3 (0x8U << FSMC_BWTR4_ADDHLD_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 7284
lypinator 0:bb348c97df44 7285 #define FSMC_BWTR4_DATAST_Pos (8U)
lypinator 0:bb348c97df44 7286 #define FSMC_BWTR4_DATAST_Msk (0xFFU << FSMC_BWTR4_DATAST_Pos) /*!< 0x0000FF00 */
lypinator 0:bb348c97df44 7287 #define FSMC_BWTR4_DATAST FSMC_BWTR4_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
lypinator 0:bb348c97df44 7288 #define FSMC_BWTR4_DATAST_0 0x00000100U /*!<Bit 0 */
lypinator 0:bb348c97df44 7289 #define FSMC_BWTR4_DATAST_1 0x00000200U /*!<Bit 1 */
lypinator 0:bb348c97df44 7290 #define FSMC_BWTR4_DATAST_2 0x00000400U /*!<Bit 2 */
lypinator 0:bb348c97df44 7291 #define FSMC_BWTR4_DATAST_3 0x00000800U /*!<Bit 3 */
lypinator 0:bb348c97df44 7292 #define FSMC_BWTR4_DATAST_4 0x00001000U /*!<Bit 4 */
lypinator 0:bb348c97df44 7293 #define FSMC_BWTR4_DATAST_5 0x00002000U /*!<Bit 5 */
lypinator 0:bb348c97df44 7294 #define FSMC_BWTR4_DATAST_6 0x00004000U /*!<Bit 6 */
lypinator 0:bb348c97df44 7295 #define FSMC_BWTR4_DATAST_7 0x00008000U /*!<Bit 7 */
lypinator 0:bb348c97df44 7296
lypinator 0:bb348c97df44 7297 #define FSMC_BWTR4_BUSTURN_Pos (16U)
lypinator 0:bb348c97df44 7298 #define FSMC_BWTR4_BUSTURN_Msk (0xFU << FSMC_BWTR4_BUSTURN_Pos) /*!< 0x000F0000 */
lypinator 0:bb348c97df44 7299 #define FSMC_BWTR4_BUSTURN FSMC_BWTR4_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
lypinator 0:bb348c97df44 7300 #define FSMC_BWTR4_BUSTURN_0 (0x1U << FSMC_BWTR4_BUSTURN_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 7301 #define FSMC_BWTR4_BUSTURN_1 (0x2U << FSMC_BWTR4_BUSTURN_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 7302 #define FSMC_BWTR4_BUSTURN_2 (0x4U << FSMC_BWTR4_BUSTURN_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 7303 #define FSMC_BWTR4_BUSTURN_3 (0x8U << FSMC_BWTR4_BUSTURN_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 7304
lypinator 0:bb348c97df44 7305 #define FSMC_BWTR4_ACCMOD_Pos (28U)
lypinator 0:bb348c97df44 7306 #define FSMC_BWTR4_ACCMOD_Msk (0x3U << FSMC_BWTR4_ACCMOD_Pos) /*!< 0x30000000 */
lypinator 0:bb348c97df44 7307 #define FSMC_BWTR4_ACCMOD FSMC_BWTR4_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
lypinator 0:bb348c97df44 7308 #define FSMC_BWTR4_ACCMOD_0 (0x1U << FSMC_BWTR4_ACCMOD_Pos) /*!< 0x10000000 */
lypinator 0:bb348c97df44 7309 #define FSMC_BWTR4_ACCMOD_1 (0x2U << FSMC_BWTR4_ACCMOD_Pos) /*!< 0x20000000 */
lypinator 0:bb348c97df44 7310
lypinator 0:bb348c97df44 7311 /******************************************************************************/
lypinator 0:bb348c97df44 7312 /* */
lypinator 0:bb348c97df44 7313 /* General Purpose I/O */
lypinator 0:bb348c97df44 7314 /* */
lypinator 0:bb348c97df44 7315 /******************************************************************************/
lypinator 0:bb348c97df44 7316 /****************** Bits definition for GPIO_MODER register *****************/
lypinator 0:bb348c97df44 7317 #define GPIO_MODER_MODE0_Pos (0U)
lypinator 0:bb348c97df44 7318 #define GPIO_MODER_MODE0_Msk (0x3U << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */
lypinator 0:bb348c97df44 7319 #define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
lypinator 0:bb348c97df44 7320 #define GPIO_MODER_MODE0_0 (0x1U << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 7321 #define GPIO_MODER_MODE0_1 (0x2U << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 7322 #define GPIO_MODER_MODE1_Pos (2U)
lypinator 0:bb348c97df44 7323 #define GPIO_MODER_MODE1_Msk (0x3U << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */
lypinator 0:bb348c97df44 7324 #define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
lypinator 0:bb348c97df44 7325 #define GPIO_MODER_MODE1_0 (0x1U << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 7326 #define GPIO_MODER_MODE1_1 (0x2U << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 7327 #define GPIO_MODER_MODE2_Pos (4U)
lypinator 0:bb348c97df44 7328 #define GPIO_MODER_MODE2_Msk (0x3U << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */
lypinator 0:bb348c97df44 7329 #define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
lypinator 0:bb348c97df44 7330 #define GPIO_MODER_MODE2_0 (0x1U << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 7331 #define GPIO_MODER_MODE2_1 (0x2U << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 7332 #define GPIO_MODER_MODE3_Pos (6U)
lypinator 0:bb348c97df44 7333 #define GPIO_MODER_MODE3_Msk (0x3U << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */
lypinator 0:bb348c97df44 7334 #define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
lypinator 0:bb348c97df44 7335 #define GPIO_MODER_MODE3_0 (0x1U << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 7336 #define GPIO_MODER_MODE3_1 (0x2U << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 7337 #define GPIO_MODER_MODE4_Pos (8U)
lypinator 0:bb348c97df44 7338 #define GPIO_MODER_MODE4_Msk (0x3U << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */
lypinator 0:bb348c97df44 7339 #define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
lypinator 0:bb348c97df44 7340 #define GPIO_MODER_MODE4_0 (0x1U << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 7341 #define GPIO_MODER_MODE4_1 (0x2U << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 7342 #define GPIO_MODER_MODE5_Pos (10U)
lypinator 0:bb348c97df44 7343 #define GPIO_MODER_MODE5_Msk (0x3U << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */
lypinator 0:bb348c97df44 7344 #define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
lypinator 0:bb348c97df44 7345 #define GPIO_MODER_MODE5_0 (0x1U << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 7346 #define GPIO_MODER_MODE5_1 (0x2U << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 7347 #define GPIO_MODER_MODE6_Pos (12U)
lypinator 0:bb348c97df44 7348 #define GPIO_MODER_MODE6_Msk (0x3U << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */
lypinator 0:bb348c97df44 7349 #define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
lypinator 0:bb348c97df44 7350 #define GPIO_MODER_MODE6_0 (0x1U << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 7351 #define GPIO_MODER_MODE6_1 (0x2U << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 7352 #define GPIO_MODER_MODE7_Pos (14U)
lypinator 0:bb348c97df44 7353 #define GPIO_MODER_MODE7_Msk (0x3U << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */
lypinator 0:bb348c97df44 7354 #define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
lypinator 0:bb348c97df44 7355 #define GPIO_MODER_MODE7_0 (0x1U << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 7356 #define GPIO_MODER_MODE7_1 (0x2U << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 7357 #define GPIO_MODER_MODE8_Pos (16U)
lypinator 0:bb348c97df44 7358 #define GPIO_MODER_MODE8_Msk (0x3U << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */
lypinator 0:bb348c97df44 7359 #define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
lypinator 0:bb348c97df44 7360 #define GPIO_MODER_MODE8_0 (0x1U << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 7361 #define GPIO_MODER_MODE8_1 (0x2U << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 7362 #define GPIO_MODER_MODE9_Pos (18U)
lypinator 0:bb348c97df44 7363 #define GPIO_MODER_MODE9_Msk (0x3U << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */
lypinator 0:bb348c97df44 7364 #define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
lypinator 0:bb348c97df44 7365 #define GPIO_MODER_MODE9_0 (0x1U << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 7366 #define GPIO_MODER_MODE9_1 (0x2U << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 7367 #define GPIO_MODER_MODE10_Pos (20U)
lypinator 0:bb348c97df44 7368 #define GPIO_MODER_MODE10_Msk (0x3U << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */
lypinator 0:bb348c97df44 7369 #define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
lypinator 0:bb348c97df44 7370 #define GPIO_MODER_MODE10_0 (0x1U << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 7371 #define GPIO_MODER_MODE10_1 (0x2U << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 7372 #define GPIO_MODER_MODE11_Pos (22U)
lypinator 0:bb348c97df44 7373 #define GPIO_MODER_MODE11_Msk (0x3U << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */
lypinator 0:bb348c97df44 7374 #define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
lypinator 0:bb348c97df44 7375 #define GPIO_MODER_MODE11_0 (0x1U << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 7376 #define GPIO_MODER_MODE11_1 (0x2U << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */
lypinator 0:bb348c97df44 7377 #define GPIO_MODER_MODE12_Pos (24U)
lypinator 0:bb348c97df44 7378 #define GPIO_MODER_MODE12_Msk (0x3U << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */
lypinator 0:bb348c97df44 7379 #define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
lypinator 0:bb348c97df44 7380 #define GPIO_MODER_MODE12_0 (0x1U << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 7381 #define GPIO_MODER_MODE12_1 (0x2U << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 7382 #define GPIO_MODER_MODE13_Pos (26U)
lypinator 0:bb348c97df44 7383 #define GPIO_MODER_MODE13_Msk (0x3U << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */
lypinator 0:bb348c97df44 7384 #define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
lypinator 0:bb348c97df44 7385 #define GPIO_MODER_MODE13_0 (0x1U << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */
lypinator 0:bb348c97df44 7386 #define GPIO_MODER_MODE13_1 (0x2U << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */
lypinator 0:bb348c97df44 7387 #define GPIO_MODER_MODE14_Pos (28U)
lypinator 0:bb348c97df44 7388 #define GPIO_MODER_MODE14_Msk (0x3U << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */
lypinator 0:bb348c97df44 7389 #define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
lypinator 0:bb348c97df44 7390 #define GPIO_MODER_MODE14_0 (0x1U << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */
lypinator 0:bb348c97df44 7391 #define GPIO_MODER_MODE14_1 (0x2U << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */
lypinator 0:bb348c97df44 7392 #define GPIO_MODER_MODE15_Pos (30U)
lypinator 0:bb348c97df44 7393 #define GPIO_MODER_MODE15_Msk (0x3U << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */
lypinator 0:bb348c97df44 7394 #define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
lypinator 0:bb348c97df44 7395 #define GPIO_MODER_MODE15_0 (0x1U << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */
lypinator 0:bb348c97df44 7396 #define GPIO_MODER_MODE15_1 (0x2U << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */
lypinator 0:bb348c97df44 7397
lypinator 0:bb348c97df44 7398 /* Legacy defines */
lypinator 0:bb348c97df44 7399 #define GPIO_MODER_MODER0_Pos (0U)
lypinator 0:bb348c97df44 7400 #define GPIO_MODER_MODER0_Msk (0x3U << GPIO_MODER_MODER0_Pos) /*!< 0x00000003 */
lypinator 0:bb348c97df44 7401 #define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk
lypinator 0:bb348c97df44 7402 #define GPIO_MODER_MODER0_0 (0x1U << GPIO_MODER_MODER0_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 7403 #define GPIO_MODER_MODER0_1 (0x2U << GPIO_MODER_MODER0_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 7404 #define GPIO_MODER_MODER1_Pos (2U)
lypinator 0:bb348c97df44 7405 #define GPIO_MODER_MODER1_Msk (0x3U << GPIO_MODER_MODER1_Pos) /*!< 0x0000000C */
lypinator 0:bb348c97df44 7406 #define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk
lypinator 0:bb348c97df44 7407 #define GPIO_MODER_MODER1_0 (0x1U << GPIO_MODER_MODER1_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 7408 #define GPIO_MODER_MODER1_1 (0x2U << GPIO_MODER_MODER1_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 7409 #define GPIO_MODER_MODER2_Pos (4U)
lypinator 0:bb348c97df44 7410 #define GPIO_MODER_MODER2_Msk (0x3U << GPIO_MODER_MODER2_Pos) /*!< 0x00000030 */
lypinator 0:bb348c97df44 7411 #define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk
lypinator 0:bb348c97df44 7412 #define GPIO_MODER_MODER2_0 (0x1U << GPIO_MODER_MODER2_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 7413 #define GPIO_MODER_MODER2_1 (0x2U << GPIO_MODER_MODER2_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 7414 #define GPIO_MODER_MODER3_Pos (6U)
lypinator 0:bb348c97df44 7415 #define GPIO_MODER_MODER3_Msk (0x3U << GPIO_MODER_MODER3_Pos) /*!< 0x000000C0 */
lypinator 0:bb348c97df44 7416 #define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk
lypinator 0:bb348c97df44 7417 #define GPIO_MODER_MODER3_0 (0x1U << GPIO_MODER_MODER3_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 7418 #define GPIO_MODER_MODER3_1 (0x2U << GPIO_MODER_MODER3_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 7419 #define GPIO_MODER_MODER4_Pos (8U)
lypinator 0:bb348c97df44 7420 #define GPIO_MODER_MODER4_Msk (0x3U << GPIO_MODER_MODER4_Pos) /*!< 0x00000300 */
lypinator 0:bb348c97df44 7421 #define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk
lypinator 0:bb348c97df44 7422 #define GPIO_MODER_MODER4_0 (0x1U << GPIO_MODER_MODER4_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 7423 #define GPIO_MODER_MODER4_1 (0x2U << GPIO_MODER_MODER4_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 7424 #define GPIO_MODER_MODER5_Pos (10U)
lypinator 0:bb348c97df44 7425 #define GPIO_MODER_MODER5_Msk (0x3U << GPIO_MODER_MODER5_Pos) /*!< 0x00000C00 */
lypinator 0:bb348c97df44 7426 #define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk
lypinator 0:bb348c97df44 7427 #define GPIO_MODER_MODER5_0 (0x1U << GPIO_MODER_MODER5_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 7428 #define GPIO_MODER_MODER5_1 (0x2U << GPIO_MODER_MODER5_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 7429 #define GPIO_MODER_MODER6_Pos (12U)
lypinator 0:bb348c97df44 7430 #define GPIO_MODER_MODER6_Msk (0x3U << GPIO_MODER_MODER6_Pos) /*!< 0x00003000 */
lypinator 0:bb348c97df44 7431 #define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk
lypinator 0:bb348c97df44 7432 #define GPIO_MODER_MODER6_0 (0x1U << GPIO_MODER_MODER6_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 7433 #define GPIO_MODER_MODER6_1 (0x2U << GPIO_MODER_MODER6_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 7434 #define GPIO_MODER_MODER7_Pos (14U)
lypinator 0:bb348c97df44 7435 #define GPIO_MODER_MODER7_Msk (0x3U << GPIO_MODER_MODER7_Pos) /*!< 0x0000C000 */
lypinator 0:bb348c97df44 7436 #define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk
lypinator 0:bb348c97df44 7437 #define GPIO_MODER_MODER7_0 (0x1U << GPIO_MODER_MODER7_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 7438 #define GPIO_MODER_MODER7_1 (0x2U << GPIO_MODER_MODER7_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 7439 #define GPIO_MODER_MODER8_Pos (16U)
lypinator 0:bb348c97df44 7440 #define GPIO_MODER_MODER8_Msk (0x3U << GPIO_MODER_MODER8_Pos) /*!< 0x00030000 */
lypinator 0:bb348c97df44 7441 #define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk
lypinator 0:bb348c97df44 7442 #define GPIO_MODER_MODER8_0 (0x1U << GPIO_MODER_MODER8_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 7443 #define GPIO_MODER_MODER8_1 (0x2U << GPIO_MODER_MODER8_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 7444 #define GPIO_MODER_MODER9_Pos (18U)
lypinator 0:bb348c97df44 7445 #define GPIO_MODER_MODER9_Msk (0x3U << GPIO_MODER_MODER9_Pos) /*!< 0x000C0000 */
lypinator 0:bb348c97df44 7446 #define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk
lypinator 0:bb348c97df44 7447 #define GPIO_MODER_MODER9_0 (0x1U << GPIO_MODER_MODER9_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 7448 #define GPIO_MODER_MODER9_1 (0x2U << GPIO_MODER_MODER9_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 7449 #define GPIO_MODER_MODER10_Pos (20U)
lypinator 0:bb348c97df44 7450 #define GPIO_MODER_MODER10_Msk (0x3U << GPIO_MODER_MODER10_Pos) /*!< 0x00300000 */
lypinator 0:bb348c97df44 7451 #define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk
lypinator 0:bb348c97df44 7452 #define GPIO_MODER_MODER10_0 (0x1U << GPIO_MODER_MODER10_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 7453 #define GPIO_MODER_MODER10_1 (0x2U << GPIO_MODER_MODER10_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 7454 #define GPIO_MODER_MODER11_Pos (22U)
lypinator 0:bb348c97df44 7455 #define GPIO_MODER_MODER11_Msk (0x3U << GPIO_MODER_MODER11_Pos) /*!< 0x00C00000 */
lypinator 0:bb348c97df44 7456 #define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk
lypinator 0:bb348c97df44 7457 #define GPIO_MODER_MODER11_0 (0x1U << GPIO_MODER_MODER11_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 7458 #define GPIO_MODER_MODER11_1 (0x2U << GPIO_MODER_MODER11_Pos) /*!< 0x00800000 */
lypinator 0:bb348c97df44 7459 #define GPIO_MODER_MODER12_Pos (24U)
lypinator 0:bb348c97df44 7460 #define GPIO_MODER_MODER12_Msk (0x3U << GPIO_MODER_MODER12_Pos) /*!< 0x03000000 */
lypinator 0:bb348c97df44 7461 #define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk
lypinator 0:bb348c97df44 7462 #define GPIO_MODER_MODER12_0 (0x1U << GPIO_MODER_MODER12_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 7463 #define GPIO_MODER_MODER12_1 (0x2U << GPIO_MODER_MODER12_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 7464 #define GPIO_MODER_MODER13_Pos (26U)
lypinator 0:bb348c97df44 7465 #define GPIO_MODER_MODER13_Msk (0x3U << GPIO_MODER_MODER13_Pos) /*!< 0x0C000000 */
lypinator 0:bb348c97df44 7466 #define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk
lypinator 0:bb348c97df44 7467 #define GPIO_MODER_MODER13_0 (0x1U << GPIO_MODER_MODER13_Pos) /*!< 0x04000000 */
lypinator 0:bb348c97df44 7468 #define GPIO_MODER_MODER13_1 (0x2U << GPIO_MODER_MODER13_Pos) /*!< 0x08000000 */
lypinator 0:bb348c97df44 7469 #define GPIO_MODER_MODER14_Pos (28U)
lypinator 0:bb348c97df44 7470 #define GPIO_MODER_MODER14_Msk (0x3U << GPIO_MODER_MODER14_Pos) /*!< 0x30000000 */
lypinator 0:bb348c97df44 7471 #define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk
lypinator 0:bb348c97df44 7472 #define GPIO_MODER_MODER14_0 (0x1U << GPIO_MODER_MODER14_Pos) /*!< 0x10000000 */
lypinator 0:bb348c97df44 7473 #define GPIO_MODER_MODER14_1 (0x2U << GPIO_MODER_MODER14_Pos) /*!< 0x20000000 */
lypinator 0:bb348c97df44 7474 #define GPIO_MODER_MODER15_Pos (30U)
lypinator 0:bb348c97df44 7475 #define GPIO_MODER_MODER15_Msk (0x3U << GPIO_MODER_MODER15_Pos) /*!< 0xC0000000 */
lypinator 0:bb348c97df44 7476 #define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk
lypinator 0:bb348c97df44 7477 #define GPIO_MODER_MODER15_0 (0x1U << GPIO_MODER_MODER15_Pos) /*!< 0x40000000 */
lypinator 0:bb348c97df44 7478 #define GPIO_MODER_MODER15_1 (0x2U << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */
lypinator 0:bb348c97df44 7479
lypinator 0:bb348c97df44 7480 /****************** Bits definition for GPIO_OTYPER register ****************/
lypinator 0:bb348c97df44 7481 #define GPIO_OTYPER_OT0_Pos (0U)
lypinator 0:bb348c97df44 7482 #define GPIO_OTYPER_OT0_Msk (0x1U << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 7483 #define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
lypinator 0:bb348c97df44 7484 #define GPIO_OTYPER_OT1_Pos (1U)
lypinator 0:bb348c97df44 7485 #define GPIO_OTYPER_OT1_Msk (0x1U << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 7486 #define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
lypinator 0:bb348c97df44 7487 #define GPIO_OTYPER_OT2_Pos (2U)
lypinator 0:bb348c97df44 7488 #define GPIO_OTYPER_OT2_Msk (0x1U << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 7489 #define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
lypinator 0:bb348c97df44 7490 #define GPIO_OTYPER_OT3_Pos (3U)
lypinator 0:bb348c97df44 7491 #define GPIO_OTYPER_OT3_Msk (0x1U << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 7492 #define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
lypinator 0:bb348c97df44 7493 #define GPIO_OTYPER_OT4_Pos (4U)
lypinator 0:bb348c97df44 7494 #define GPIO_OTYPER_OT4_Msk (0x1U << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 7495 #define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
lypinator 0:bb348c97df44 7496 #define GPIO_OTYPER_OT5_Pos (5U)
lypinator 0:bb348c97df44 7497 #define GPIO_OTYPER_OT5_Msk (0x1U << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 7498 #define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
lypinator 0:bb348c97df44 7499 #define GPIO_OTYPER_OT6_Pos (6U)
lypinator 0:bb348c97df44 7500 #define GPIO_OTYPER_OT6_Msk (0x1U << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 7501 #define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
lypinator 0:bb348c97df44 7502 #define GPIO_OTYPER_OT7_Pos (7U)
lypinator 0:bb348c97df44 7503 #define GPIO_OTYPER_OT7_Msk (0x1U << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 7504 #define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
lypinator 0:bb348c97df44 7505 #define GPIO_OTYPER_OT8_Pos (8U)
lypinator 0:bb348c97df44 7506 #define GPIO_OTYPER_OT8_Msk (0x1U << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 7507 #define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
lypinator 0:bb348c97df44 7508 #define GPIO_OTYPER_OT9_Pos (9U)
lypinator 0:bb348c97df44 7509 #define GPIO_OTYPER_OT9_Msk (0x1U << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 7510 #define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
lypinator 0:bb348c97df44 7511 #define GPIO_OTYPER_OT10_Pos (10U)
lypinator 0:bb348c97df44 7512 #define GPIO_OTYPER_OT10_Msk (0x1U << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 7513 #define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
lypinator 0:bb348c97df44 7514 #define GPIO_OTYPER_OT11_Pos (11U)
lypinator 0:bb348c97df44 7515 #define GPIO_OTYPER_OT11_Msk (0x1U << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 7516 #define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
lypinator 0:bb348c97df44 7517 #define GPIO_OTYPER_OT12_Pos (12U)
lypinator 0:bb348c97df44 7518 #define GPIO_OTYPER_OT12_Msk (0x1U << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 7519 #define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
lypinator 0:bb348c97df44 7520 #define GPIO_OTYPER_OT13_Pos (13U)
lypinator 0:bb348c97df44 7521 #define GPIO_OTYPER_OT13_Msk (0x1U << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 7522 #define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
lypinator 0:bb348c97df44 7523 #define GPIO_OTYPER_OT14_Pos (14U)
lypinator 0:bb348c97df44 7524 #define GPIO_OTYPER_OT14_Msk (0x1U << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 7525 #define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
lypinator 0:bb348c97df44 7526 #define GPIO_OTYPER_OT15_Pos (15U)
lypinator 0:bb348c97df44 7527 #define GPIO_OTYPER_OT15_Msk (0x1U << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 7528 #define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
lypinator 0:bb348c97df44 7529
lypinator 0:bb348c97df44 7530 /* Legacy defines */
lypinator 0:bb348c97df44 7531 #define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0
lypinator 0:bb348c97df44 7532 #define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1
lypinator 0:bb348c97df44 7533 #define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2
lypinator 0:bb348c97df44 7534 #define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3
lypinator 0:bb348c97df44 7535 #define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4
lypinator 0:bb348c97df44 7536 #define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5
lypinator 0:bb348c97df44 7537 #define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6
lypinator 0:bb348c97df44 7538 #define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7
lypinator 0:bb348c97df44 7539 #define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8
lypinator 0:bb348c97df44 7540 #define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9
lypinator 0:bb348c97df44 7541 #define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10
lypinator 0:bb348c97df44 7542 #define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11
lypinator 0:bb348c97df44 7543 #define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12
lypinator 0:bb348c97df44 7544 #define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13
lypinator 0:bb348c97df44 7545 #define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14
lypinator 0:bb348c97df44 7546 #define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15
lypinator 0:bb348c97df44 7547
lypinator 0:bb348c97df44 7548 /****************** Bits definition for GPIO_OSPEEDR register ***************/
lypinator 0:bb348c97df44 7549 #define GPIO_OSPEEDR_OSPEED0_Pos (0U)
lypinator 0:bb348c97df44 7550 #define GPIO_OSPEEDR_OSPEED0_Msk (0x3U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */
lypinator 0:bb348c97df44 7551 #define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk
lypinator 0:bb348c97df44 7552 #define GPIO_OSPEEDR_OSPEED0_0 (0x1U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 7553 #define GPIO_OSPEEDR_OSPEED0_1 (0x2U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 7554 #define GPIO_OSPEEDR_OSPEED1_Pos (2U)
lypinator 0:bb348c97df44 7555 #define GPIO_OSPEEDR_OSPEED1_Msk (0x3U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */
lypinator 0:bb348c97df44 7556 #define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk
lypinator 0:bb348c97df44 7557 #define GPIO_OSPEEDR_OSPEED1_0 (0x1U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 7558 #define GPIO_OSPEEDR_OSPEED1_1 (0x2U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 7559 #define GPIO_OSPEEDR_OSPEED2_Pos (4U)
lypinator 0:bb348c97df44 7560 #define GPIO_OSPEEDR_OSPEED2_Msk (0x3U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */
lypinator 0:bb348c97df44 7561 #define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk
lypinator 0:bb348c97df44 7562 #define GPIO_OSPEEDR_OSPEED2_0 (0x1U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 7563 #define GPIO_OSPEEDR_OSPEED2_1 (0x2U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 7564 #define GPIO_OSPEEDR_OSPEED3_Pos (6U)
lypinator 0:bb348c97df44 7565 #define GPIO_OSPEEDR_OSPEED3_Msk (0x3U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */
lypinator 0:bb348c97df44 7566 #define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk
lypinator 0:bb348c97df44 7567 #define GPIO_OSPEEDR_OSPEED3_0 (0x1U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 7568 #define GPIO_OSPEEDR_OSPEED3_1 (0x2U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 7569 #define GPIO_OSPEEDR_OSPEED4_Pos (8U)
lypinator 0:bb348c97df44 7570 #define GPIO_OSPEEDR_OSPEED4_Msk (0x3U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */
lypinator 0:bb348c97df44 7571 #define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk
lypinator 0:bb348c97df44 7572 #define GPIO_OSPEEDR_OSPEED4_0 (0x1U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 7573 #define GPIO_OSPEEDR_OSPEED4_1 (0x2U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 7574 #define GPIO_OSPEEDR_OSPEED5_Pos (10U)
lypinator 0:bb348c97df44 7575 #define GPIO_OSPEEDR_OSPEED5_Msk (0x3U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */
lypinator 0:bb348c97df44 7576 #define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk
lypinator 0:bb348c97df44 7577 #define GPIO_OSPEEDR_OSPEED5_0 (0x1U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 7578 #define GPIO_OSPEEDR_OSPEED5_1 (0x2U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 7579 #define GPIO_OSPEEDR_OSPEED6_Pos (12U)
lypinator 0:bb348c97df44 7580 #define GPIO_OSPEEDR_OSPEED6_Msk (0x3U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */
lypinator 0:bb348c97df44 7581 #define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk
lypinator 0:bb348c97df44 7582 #define GPIO_OSPEEDR_OSPEED6_0 (0x1U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 7583 #define GPIO_OSPEEDR_OSPEED6_1 (0x2U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 7584 #define GPIO_OSPEEDR_OSPEED7_Pos (14U)
lypinator 0:bb348c97df44 7585 #define GPIO_OSPEEDR_OSPEED7_Msk (0x3U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */
lypinator 0:bb348c97df44 7586 #define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk
lypinator 0:bb348c97df44 7587 #define GPIO_OSPEEDR_OSPEED7_0 (0x1U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 7588 #define GPIO_OSPEEDR_OSPEED7_1 (0x2U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 7589 #define GPIO_OSPEEDR_OSPEED8_Pos (16U)
lypinator 0:bb348c97df44 7590 #define GPIO_OSPEEDR_OSPEED8_Msk (0x3U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */
lypinator 0:bb348c97df44 7591 #define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk
lypinator 0:bb348c97df44 7592 #define GPIO_OSPEEDR_OSPEED8_0 (0x1U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 7593 #define GPIO_OSPEEDR_OSPEED8_1 (0x2U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 7594 #define GPIO_OSPEEDR_OSPEED9_Pos (18U)
lypinator 0:bb348c97df44 7595 #define GPIO_OSPEEDR_OSPEED9_Msk (0x3U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */
lypinator 0:bb348c97df44 7596 #define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk
lypinator 0:bb348c97df44 7597 #define GPIO_OSPEEDR_OSPEED9_0 (0x1U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 7598 #define GPIO_OSPEEDR_OSPEED9_1 (0x2U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 7599 #define GPIO_OSPEEDR_OSPEED10_Pos (20U)
lypinator 0:bb348c97df44 7600 #define GPIO_OSPEEDR_OSPEED10_Msk (0x3U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */
lypinator 0:bb348c97df44 7601 #define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk
lypinator 0:bb348c97df44 7602 #define GPIO_OSPEEDR_OSPEED10_0 (0x1U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 7603 #define GPIO_OSPEEDR_OSPEED10_1 (0x2U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 7604 #define GPIO_OSPEEDR_OSPEED11_Pos (22U)
lypinator 0:bb348c97df44 7605 #define GPIO_OSPEEDR_OSPEED11_Msk (0x3U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */
lypinator 0:bb348c97df44 7606 #define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk
lypinator 0:bb348c97df44 7607 #define GPIO_OSPEEDR_OSPEED11_0 (0x1U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 7608 #define GPIO_OSPEEDR_OSPEED11_1 (0x2U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */
lypinator 0:bb348c97df44 7609 #define GPIO_OSPEEDR_OSPEED12_Pos (24U)
lypinator 0:bb348c97df44 7610 #define GPIO_OSPEEDR_OSPEED12_Msk (0x3U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */
lypinator 0:bb348c97df44 7611 #define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk
lypinator 0:bb348c97df44 7612 #define GPIO_OSPEEDR_OSPEED12_0 (0x1U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 7613 #define GPIO_OSPEEDR_OSPEED12_1 (0x2U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 7614 #define GPIO_OSPEEDR_OSPEED13_Pos (26U)
lypinator 0:bb348c97df44 7615 #define GPIO_OSPEEDR_OSPEED13_Msk (0x3U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */
lypinator 0:bb348c97df44 7616 #define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk
lypinator 0:bb348c97df44 7617 #define GPIO_OSPEEDR_OSPEED13_0 (0x1U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */
lypinator 0:bb348c97df44 7618 #define GPIO_OSPEEDR_OSPEED13_1 (0x2U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */
lypinator 0:bb348c97df44 7619 #define GPIO_OSPEEDR_OSPEED14_Pos (28U)
lypinator 0:bb348c97df44 7620 #define GPIO_OSPEEDR_OSPEED14_Msk (0x3U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */
lypinator 0:bb348c97df44 7621 #define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk
lypinator 0:bb348c97df44 7622 #define GPIO_OSPEEDR_OSPEED14_0 (0x1U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */
lypinator 0:bb348c97df44 7623 #define GPIO_OSPEEDR_OSPEED14_1 (0x2U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */
lypinator 0:bb348c97df44 7624 #define GPIO_OSPEEDR_OSPEED15_Pos (30U)
lypinator 0:bb348c97df44 7625 #define GPIO_OSPEEDR_OSPEED15_Msk (0x3U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */
lypinator 0:bb348c97df44 7626 #define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk
lypinator 0:bb348c97df44 7627 #define GPIO_OSPEEDR_OSPEED15_0 (0x1U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */
lypinator 0:bb348c97df44 7628 #define GPIO_OSPEEDR_OSPEED15_1 (0x2U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */
lypinator 0:bb348c97df44 7629
lypinator 0:bb348c97df44 7630 /* Legacy defines */
lypinator 0:bb348c97df44 7631 #define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEED0
lypinator 0:bb348c97df44 7632 #define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEED0_0
lypinator 0:bb348c97df44 7633 #define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEED0_1
lypinator 0:bb348c97df44 7634 #define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEED1
lypinator 0:bb348c97df44 7635 #define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEED1_0
lypinator 0:bb348c97df44 7636 #define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEED1_1
lypinator 0:bb348c97df44 7637 #define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEED2
lypinator 0:bb348c97df44 7638 #define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEED2_0
lypinator 0:bb348c97df44 7639 #define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEED2_1
lypinator 0:bb348c97df44 7640 #define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEED3
lypinator 0:bb348c97df44 7641 #define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEED3_0
lypinator 0:bb348c97df44 7642 #define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEED3_1
lypinator 0:bb348c97df44 7643 #define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEED4
lypinator 0:bb348c97df44 7644 #define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEED4_0
lypinator 0:bb348c97df44 7645 #define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEED4_1
lypinator 0:bb348c97df44 7646 #define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEED5
lypinator 0:bb348c97df44 7647 #define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEED5_0
lypinator 0:bb348c97df44 7648 #define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEED5_1
lypinator 0:bb348c97df44 7649 #define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEED6
lypinator 0:bb348c97df44 7650 #define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEED6_0
lypinator 0:bb348c97df44 7651 #define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEED6_1
lypinator 0:bb348c97df44 7652 #define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEED7
lypinator 0:bb348c97df44 7653 #define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEED7_0
lypinator 0:bb348c97df44 7654 #define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEED7_1
lypinator 0:bb348c97df44 7655 #define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEED8
lypinator 0:bb348c97df44 7656 #define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEED8_0
lypinator 0:bb348c97df44 7657 #define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEED8_1
lypinator 0:bb348c97df44 7658 #define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEED9
lypinator 0:bb348c97df44 7659 #define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEED9_0
lypinator 0:bb348c97df44 7660 #define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEED9_1
lypinator 0:bb348c97df44 7661 #define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEED10
lypinator 0:bb348c97df44 7662 #define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEED10_0
lypinator 0:bb348c97df44 7663 #define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEED10_1
lypinator 0:bb348c97df44 7664 #define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEED11
lypinator 0:bb348c97df44 7665 #define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEED11_0
lypinator 0:bb348c97df44 7666 #define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEED11_1
lypinator 0:bb348c97df44 7667 #define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEED12
lypinator 0:bb348c97df44 7668 #define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEED12_0
lypinator 0:bb348c97df44 7669 #define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEED12_1
lypinator 0:bb348c97df44 7670 #define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEED13
lypinator 0:bb348c97df44 7671 #define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEED13_0
lypinator 0:bb348c97df44 7672 #define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEED13_1
lypinator 0:bb348c97df44 7673 #define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEED14
lypinator 0:bb348c97df44 7674 #define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEED14_0
lypinator 0:bb348c97df44 7675 #define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEED14_1
lypinator 0:bb348c97df44 7676 #define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEED15
lypinator 0:bb348c97df44 7677 #define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEED15_0
lypinator 0:bb348c97df44 7678 #define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEED15_1
lypinator 0:bb348c97df44 7679
lypinator 0:bb348c97df44 7680 /****************** Bits definition for GPIO_PUPDR register *****************/
lypinator 0:bb348c97df44 7681 #define GPIO_PUPDR_PUPD0_Pos (0U)
lypinator 0:bb348c97df44 7682 #define GPIO_PUPDR_PUPD0_Msk (0x3U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */
lypinator 0:bb348c97df44 7683 #define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
lypinator 0:bb348c97df44 7684 #define GPIO_PUPDR_PUPD0_0 (0x1U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 7685 #define GPIO_PUPDR_PUPD0_1 (0x2U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 7686 #define GPIO_PUPDR_PUPD1_Pos (2U)
lypinator 0:bb348c97df44 7687 #define GPIO_PUPDR_PUPD1_Msk (0x3U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */
lypinator 0:bb348c97df44 7688 #define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
lypinator 0:bb348c97df44 7689 #define GPIO_PUPDR_PUPD1_0 (0x1U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 7690 #define GPIO_PUPDR_PUPD1_1 (0x2U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 7691 #define GPIO_PUPDR_PUPD2_Pos (4U)
lypinator 0:bb348c97df44 7692 #define GPIO_PUPDR_PUPD2_Msk (0x3U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */
lypinator 0:bb348c97df44 7693 #define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
lypinator 0:bb348c97df44 7694 #define GPIO_PUPDR_PUPD2_0 (0x1U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 7695 #define GPIO_PUPDR_PUPD2_1 (0x2U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 7696 #define GPIO_PUPDR_PUPD3_Pos (6U)
lypinator 0:bb348c97df44 7697 #define GPIO_PUPDR_PUPD3_Msk (0x3U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */
lypinator 0:bb348c97df44 7698 #define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
lypinator 0:bb348c97df44 7699 #define GPIO_PUPDR_PUPD3_0 (0x1U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 7700 #define GPIO_PUPDR_PUPD3_1 (0x2U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 7701 #define GPIO_PUPDR_PUPD4_Pos (8U)
lypinator 0:bb348c97df44 7702 #define GPIO_PUPDR_PUPD4_Msk (0x3U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */
lypinator 0:bb348c97df44 7703 #define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
lypinator 0:bb348c97df44 7704 #define GPIO_PUPDR_PUPD4_0 (0x1U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 7705 #define GPIO_PUPDR_PUPD4_1 (0x2U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 7706 #define GPIO_PUPDR_PUPD5_Pos (10U)
lypinator 0:bb348c97df44 7707 #define GPIO_PUPDR_PUPD5_Msk (0x3U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */
lypinator 0:bb348c97df44 7708 #define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
lypinator 0:bb348c97df44 7709 #define GPIO_PUPDR_PUPD5_0 (0x1U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 7710 #define GPIO_PUPDR_PUPD5_1 (0x2U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 7711 #define GPIO_PUPDR_PUPD6_Pos (12U)
lypinator 0:bb348c97df44 7712 #define GPIO_PUPDR_PUPD6_Msk (0x3U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */
lypinator 0:bb348c97df44 7713 #define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
lypinator 0:bb348c97df44 7714 #define GPIO_PUPDR_PUPD6_0 (0x1U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 7715 #define GPIO_PUPDR_PUPD6_1 (0x2U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 7716 #define GPIO_PUPDR_PUPD7_Pos (14U)
lypinator 0:bb348c97df44 7717 #define GPIO_PUPDR_PUPD7_Msk (0x3U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */
lypinator 0:bb348c97df44 7718 #define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
lypinator 0:bb348c97df44 7719 #define GPIO_PUPDR_PUPD7_0 (0x1U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 7720 #define GPIO_PUPDR_PUPD7_1 (0x2U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 7721 #define GPIO_PUPDR_PUPD8_Pos (16U)
lypinator 0:bb348c97df44 7722 #define GPIO_PUPDR_PUPD8_Msk (0x3U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */
lypinator 0:bb348c97df44 7723 #define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
lypinator 0:bb348c97df44 7724 #define GPIO_PUPDR_PUPD8_0 (0x1U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 7725 #define GPIO_PUPDR_PUPD8_1 (0x2U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 7726 #define GPIO_PUPDR_PUPD9_Pos (18U)
lypinator 0:bb348c97df44 7727 #define GPIO_PUPDR_PUPD9_Msk (0x3U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */
lypinator 0:bb348c97df44 7728 #define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
lypinator 0:bb348c97df44 7729 #define GPIO_PUPDR_PUPD9_0 (0x1U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 7730 #define GPIO_PUPDR_PUPD9_1 (0x2U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 7731 #define GPIO_PUPDR_PUPD10_Pos (20U)
lypinator 0:bb348c97df44 7732 #define GPIO_PUPDR_PUPD10_Msk (0x3U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */
lypinator 0:bb348c97df44 7733 #define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
lypinator 0:bb348c97df44 7734 #define GPIO_PUPDR_PUPD10_0 (0x1U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 7735 #define GPIO_PUPDR_PUPD10_1 (0x2U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 7736 #define GPIO_PUPDR_PUPD11_Pos (22U)
lypinator 0:bb348c97df44 7737 #define GPIO_PUPDR_PUPD11_Msk (0x3U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */
lypinator 0:bb348c97df44 7738 #define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
lypinator 0:bb348c97df44 7739 #define GPIO_PUPDR_PUPD11_0 (0x1U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 7740 #define GPIO_PUPDR_PUPD11_1 (0x2U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */
lypinator 0:bb348c97df44 7741 #define GPIO_PUPDR_PUPD12_Pos (24U)
lypinator 0:bb348c97df44 7742 #define GPIO_PUPDR_PUPD12_Msk (0x3U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */
lypinator 0:bb348c97df44 7743 #define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
lypinator 0:bb348c97df44 7744 #define GPIO_PUPDR_PUPD12_0 (0x1U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 7745 #define GPIO_PUPDR_PUPD12_1 (0x2U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 7746 #define GPIO_PUPDR_PUPD13_Pos (26U)
lypinator 0:bb348c97df44 7747 #define GPIO_PUPDR_PUPD13_Msk (0x3U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */
lypinator 0:bb348c97df44 7748 #define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
lypinator 0:bb348c97df44 7749 #define GPIO_PUPDR_PUPD13_0 (0x1U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */
lypinator 0:bb348c97df44 7750 #define GPIO_PUPDR_PUPD13_1 (0x2U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */
lypinator 0:bb348c97df44 7751 #define GPIO_PUPDR_PUPD14_Pos (28U)
lypinator 0:bb348c97df44 7752 #define GPIO_PUPDR_PUPD14_Msk (0x3U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */
lypinator 0:bb348c97df44 7753 #define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
lypinator 0:bb348c97df44 7754 #define GPIO_PUPDR_PUPD14_0 (0x1U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */
lypinator 0:bb348c97df44 7755 #define GPIO_PUPDR_PUPD14_1 (0x2U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */
lypinator 0:bb348c97df44 7756 #define GPIO_PUPDR_PUPD15_Pos (30U)
lypinator 0:bb348c97df44 7757 #define GPIO_PUPDR_PUPD15_Msk (0x3U << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */
lypinator 0:bb348c97df44 7758 #define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
lypinator 0:bb348c97df44 7759 #define GPIO_PUPDR_PUPD15_0 (0x1U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */
lypinator 0:bb348c97df44 7760 #define GPIO_PUPDR_PUPD15_1 (0x2U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */
lypinator 0:bb348c97df44 7761
lypinator 0:bb348c97df44 7762 /* Legacy defines */
lypinator 0:bb348c97df44 7763 #define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPD0
lypinator 0:bb348c97df44 7764 #define GPIO_PUPDR_PUPDR0_0 GPIO_PUPDR_PUPD0_0
lypinator 0:bb348c97df44 7765 #define GPIO_PUPDR_PUPDR0_1 GPIO_PUPDR_PUPD0_1
lypinator 0:bb348c97df44 7766 #define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPD1
lypinator 0:bb348c97df44 7767 #define GPIO_PUPDR_PUPDR1_0 GPIO_PUPDR_PUPD1_0
lypinator 0:bb348c97df44 7768 #define GPIO_PUPDR_PUPDR1_1 GPIO_PUPDR_PUPD1_1
lypinator 0:bb348c97df44 7769 #define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPD2
lypinator 0:bb348c97df44 7770 #define GPIO_PUPDR_PUPDR2_0 GPIO_PUPDR_PUPD2_0
lypinator 0:bb348c97df44 7771 #define GPIO_PUPDR_PUPDR2_1 GPIO_PUPDR_PUPD2_1
lypinator 0:bb348c97df44 7772 #define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPD3
lypinator 0:bb348c97df44 7773 #define GPIO_PUPDR_PUPDR3_0 GPIO_PUPDR_PUPD3_0
lypinator 0:bb348c97df44 7774 #define GPIO_PUPDR_PUPDR3_1 GPIO_PUPDR_PUPD3_1
lypinator 0:bb348c97df44 7775 #define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPD4
lypinator 0:bb348c97df44 7776 #define GPIO_PUPDR_PUPDR4_0 GPIO_PUPDR_PUPD4_0
lypinator 0:bb348c97df44 7777 #define GPIO_PUPDR_PUPDR4_1 GPIO_PUPDR_PUPD4_1
lypinator 0:bb348c97df44 7778 #define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPD5
lypinator 0:bb348c97df44 7779 #define GPIO_PUPDR_PUPDR5_0 GPIO_PUPDR_PUPD5_0
lypinator 0:bb348c97df44 7780 #define GPIO_PUPDR_PUPDR5_1 GPIO_PUPDR_PUPD5_1
lypinator 0:bb348c97df44 7781 #define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPD6
lypinator 0:bb348c97df44 7782 #define GPIO_PUPDR_PUPDR6_0 GPIO_PUPDR_PUPD6_0
lypinator 0:bb348c97df44 7783 #define GPIO_PUPDR_PUPDR6_1 GPIO_PUPDR_PUPD6_1
lypinator 0:bb348c97df44 7784 #define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPD7
lypinator 0:bb348c97df44 7785 #define GPIO_PUPDR_PUPDR7_0 GPIO_PUPDR_PUPD7_0
lypinator 0:bb348c97df44 7786 #define GPIO_PUPDR_PUPDR7_1 GPIO_PUPDR_PUPD7_1
lypinator 0:bb348c97df44 7787 #define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPD8
lypinator 0:bb348c97df44 7788 #define GPIO_PUPDR_PUPDR8_0 GPIO_PUPDR_PUPD8_0
lypinator 0:bb348c97df44 7789 #define GPIO_PUPDR_PUPDR8_1 GPIO_PUPDR_PUPD8_1
lypinator 0:bb348c97df44 7790 #define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPD9
lypinator 0:bb348c97df44 7791 #define GPIO_PUPDR_PUPDR9_0 GPIO_PUPDR_PUPD9_0
lypinator 0:bb348c97df44 7792 #define GPIO_PUPDR_PUPDR9_1 GPIO_PUPDR_PUPD9_1
lypinator 0:bb348c97df44 7793 #define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPD10
lypinator 0:bb348c97df44 7794 #define GPIO_PUPDR_PUPDR10_0 GPIO_PUPDR_PUPD10_0
lypinator 0:bb348c97df44 7795 #define GPIO_PUPDR_PUPDR10_1 GPIO_PUPDR_PUPD10_1
lypinator 0:bb348c97df44 7796 #define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPD11
lypinator 0:bb348c97df44 7797 #define GPIO_PUPDR_PUPDR11_0 GPIO_PUPDR_PUPD11_0
lypinator 0:bb348c97df44 7798 #define GPIO_PUPDR_PUPDR11_1 GPIO_PUPDR_PUPD11_1
lypinator 0:bb348c97df44 7799 #define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPD12
lypinator 0:bb348c97df44 7800 #define GPIO_PUPDR_PUPDR12_0 GPIO_PUPDR_PUPD12_0
lypinator 0:bb348c97df44 7801 #define GPIO_PUPDR_PUPDR12_1 GPIO_PUPDR_PUPD12_1
lypinator 0:bb348c97df44 7802 #define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPD13
lypinator 0:bb348c97df44 7803 #define GPIO_PUPDR_PUPDR13_0 GPIO_PUPDR_PUPD13_0
lypinator 0:bb348c97df44 7804 #define GPIO_PUPDR_PUPDR13_1 GPIO_PUPDR_PUPD13_1
lypinator 0:bb348c97df44 7805 #define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPD14
lypinator 0:bb348c97df44 7806 #define GPIO_PUPDR_PUPDR14_0 GPIO_PUPDR_PUPD14_0
lypinator 0:bb348c97df44 7807 #define GPIO_PUPDR_PUPDR14_1 GPIO_PUPDR_PUPD14_1
lypinator 0:bb348c97df44 7808 #define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPD15
lypinator 0:bb348c97df44 7809 #define GPIO_PUPDR_PUPDR15_0 GPIO_PUPDR_PUPD15_0
lypinator 0:bb348c97df44 7810 #define GPIO_PUPDR_PUPDR15_1 GPIO_PUPDR_PUPD15_1
lypinator 0:bb348c97df44 7811
lypinator 0:bb348c97df44 7812 /****************** Bits definition for GPIO_IDR register *******************/
lypinator 0:bb348c97df44 7813 #define GPIO_IDR_ID0_Pos (0U)
lypinator 0:bb348c97df44 7814 #define GPIO_IDR_ID0_Msk (0x1U << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 7815 #define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
lypinator 0:bb348c97df44 7816 #define GPIO_IDR_ID1_Pos (1U)
lypinator 0:bb348c97df44 7817 #define GPIO_IDR_ID1_Msk (0x1U << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 7818 #define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
lypinator 0:bb348c97df44 7819 #define GPIO_IDR_ID2_Pos (2U)
lypinator 0:bb348c97df44 7820 #define GPIO_IDR_ID2_Msk (0x1U << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 7821 #define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
lypinator 0:bb348c97df44 7822 #define GPIO_IDR_ID3_Pos (3U)
lypinator 0:bb348c97df44 7823 #define GPIO_IDR_ID3_Msk (0x1U << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 7824 #define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
lypinator 0:bb348c97df44 7825 #define GPIO_IDR_ID4_Pos (4U)
lypinator 0:bb348c97df44 7826 #define GPIO_IDR_ID4_Msk (0x1U << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 7827 #define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
lypinator 0:bb348c97df44 7828 #define GPIO_IDR_ID5_Pos (5U)
lypinator 0:bb348c97df44 7829 #define GPIO_IDR_ID5_Msk (0x1U << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 7830 #define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
lypinator 0:bb348c97df44 7831 #define GPIO_IDR_ID6_Pos (6U)
lypinator 0:bb348c97df44 7832 #define GPIO_IDR_ID6_Msk (0x1U << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 7833 #define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
lypinator 0:bb348c97df44 7834 #define GPIO_IDR_ID7_Pos (7U)
lypinator 0:bb348c97df44 7835 #define GPIO_IDR_ID7_Msk (0x1U << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 7836 #define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
lypinator 0:bb348c97df44 7837 #define GPIO_IDR_ID8_Pos (8U)
lypinator 0:bb348c97df44 7838 #define GPIO_IDR_ID8_Msk (0x1U << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 7839 #define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
lypinator 0:bb348c97df44 7840 #define GPIO_IDR_ID9_Pos (9U)
lypinator 0:bb348c97df44 7841 #define GPIO_IDR_ID9_Msk (0x1U << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 7842 #define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
lypinator 0:bb348c97df44 7843 #define GPIO_IDR_ID10_Pos (10U)
lypinator 0:bb348c97df44 7844 #define GPIO_IDR_ID10_Msk (0x1U << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 7845 #define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
lypinator 0:bb348c97df44 7846 #define GPIO_IDR_ID11_Pos (11U)
lypinator 0:bb348c97df44 7847 #define GPIO_IDR_ID11_Msk (0x1U << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 7848 #define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
lypinator 0:bb348c97df44 7849 #define GPIO_IDR_ID12_Pos (12U)
lypinator 0:bb348c97df44 7850 #define GPIO_IDR_ID12_Msk (0x1U << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 7851 #define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
lypinator 0:bb348c97df44 7852 #define GPIO_IDR_ID13_Pos (13U)
lypinator 0:bb348c97df44 7853 #define GPIO_IDR_ID13_Msk (0x1U << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 7854 #define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
lypinator 0:bb348c97df44 7855 #define GPIO_IDR_ID14_Pos (14U)
lypinator 0:bb348c97df44 7856 #define GPIO_IDR_ID14_Msk (0x1U << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 7857 #define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
lypinator 0:bb348c97df44 7858 #define GPIO_IDR_ID15_Pos (15U)
lypinator 0:bb348c97df44 7859 #define GPIO_IDR_ID15_Msk (0x1U << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 7860 #define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
lypinator 0:bb348c97df44 7861
lypinator 0:bb348c97df44 7862 /* Legacy defines */
lypinator 0:bb348c97df44 7863 #define GPIO_IDR_IDR_0 GPIO_IDR_ID0
lypinator 0:bb348c97df44 7864 #define GPIO_IDR_IDR_1 GPIO_IDR_ID1
lypinator 0:bb348c97df44 7865 #define GPIO_IDR_IDR_2 GPIO_IDR_ID2
lypinator 0:bb348c97df44 7866 #define GPIO_IDR_IDR_3 GPIO_IDR_ID3
lypinator 0:bb348c97df44 7867 #define GPIO_IDR_IDR_4 GPIO_IDR_ID4
lypinator 0:bb348c97df44 7868 #define GPIO_IDR_IDR_5 GPIO_IDR_ID5
lypinator 0:bb348c97df44 7869 #define GPIO_IDR_IDR_6 GPIO_IDR_ID6
lypinator 0:bb348c97df44 7870 #define GPIO_IDR_IDR_7 GPIO_IDR_ID7
lypinator 0:bb348c97df44 7871 #define GPIO_IDR_IDR_8 GPIO_IDR_ID8
lypinator 0:bb348c97df44 7872 #define GPIO_IDR_IDR_9 GPIO_IDR_ID9
lypinator 0:bb348c97df44 7873 #define GPIO_IDR_IDR_10 GPIO_IDR_ID10
lypinator 0:bb348c97df44 7874 #define GPIO_IDR_IDR_11 GPIO_IDR_ID11
lypinator 0:bb348c97df44 7875 #define GPIO_IDR_IDR_12 GPIO_IDR_ID12
lypinator 0:bb348c97df44 7876 #define GPIO_IDR_IDR_13 GPIO_IDR_ID13
lypinator 0:bb348c97df44 7877 #define GPIO_IDR_IDR_14 GPIO_IDR_ID14
lypinator 0:bb348c97df44 7878 #define GPIO_IDR_IDR_15 GPIO_IDR_ID15
lypinator 0:bb348c97df44 7879
lypinator 0:bb348c97df44 7880 /****************** Bits definition for GPIO_ODR register *******************/
lypinator 0:bb348c97df44 7881 #define GPIO_ODR_OD0_Pos (0U)
lypinator 0:bb348c97df44 7882 #define GPIO_ODR_OD0_Msk (0x1U << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 7883 #define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
lypinator 0:bb348c97df44 7884 #define GPIO_ODR_OD1_Pos (1U)
lypinator 0:bb348c97df44 7885 #define GPIO_ODR_OD1_Msk (0x1U << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 7886 #define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
lypinator 0:bb348c97df44 7887 #define GPIO_ODR_OD2_Pos (2U)
lypinator 0:bb348c97df44 7888 #define GPIO_ODR_OD2_Msk (0x1U << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 7889 #define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
lypinator 0:bb348c97df44 7890 #define GPIO_ODR_OD3_Pos (3U)
lypinator 0:bb348c97df44 7891 #define GPIO_ODR_OD3_Msk (0x1U << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 7892 #define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
lypinator 0:bb348c97df44 7893 #define GPIO_ODR_OD4_Pos (4U)
lypinator 0:bb348c97df44 7894 #define GPIO_ODR_OD4_Msk (0x1U << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 7895 #define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
lypinator 0:bb348c97df44 7896 #define GPIO_ODR_OD5_Pos (5U)
lypinator 0:bb348c97df44 7897 #define GPIO_ODR_OD5_Msk (0x1U << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 7898 #define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
lypinator 0:bb348c97df44 7899 #define GPIO_ODR_OD6_Pos (6U)
lypinator 0:bb348c97df44 7900 #define GPIO_ODR_OD6_Msk (0x1U << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 7901 #define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
lypinator 0:bb348c97df44 7902 #define GPIO_ODR_OD7_Pos (7U)
lypinator 0:bb348c97df44 7903 #define GPIO_ODR_OD7_Msk (0x1U << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 7904 #define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
lypinator 0:bb348c97df44 7905 #define GPIO_ODR_OD8_Pos (8U)
lypinator 0:bb348c97df44 7906 #define GPIO_ODR_OD8_Msk (0x1U << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 7907 #define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
lypinator 0:bb348c97df44 7908 #define GPIO_ODR_OD9_Pos (9U)
lypinator 0:bb348c97df44 7909 #define GPIO_ODR_OD9_Msk (0x1U << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 7910 #define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
lypinator 0:bb348c97df44 7911 #define GPIO_ODR_OD10_Pos (10U)
lypinator 0:bb348c97df44 7912 #define GPIO_ODR_OD10_Msk (0x1U << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 7913 #define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
lypinator 0:bb348c97df44 7914 #define GPIO_ODR_OD11_Pos (11U)
lypinator 0:bb348c97df44 7915 #define GPIO_ODR_OD11_Msk (0x1U << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 7916 #define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
lypinator 0:bb348c97df44 7917 #define GPIO_ODR_OD12_Pos (12U)
lypinator 0:bb348c97df44 7918 #define GPIO_ODR_OD12_Msk (0x1U << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 7919 #define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
lypinator 0:bb348c97df44 7920 #define GPIO_ODR_OD13_Pos (13U)
lypinator 0:bb348c97df44 7921 #define GPIO_ODR_OD13_Msk (0x1U << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 7922 #define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
lypinator 0:bb348c97df44 7923 #define GPIO_ODR_OD14_Pos (14U)
lypinator 0:bb348c97df44 7924 #define GPIO_ODR_OD14_Msk (0x1U << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 7925 #define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
lypinator 0:bb348c97df44 7926 #define GPIO_ODR_OD15_Pos (15U)
lypinator 0:bb348c97df44 7927 #define GPIO_ODR_OD15_Msk (0x1U << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 7928 #define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
lypinator 0:bb348c97df44 7929 /* Legacy defines */
lypinator 0:bb348c97df44 7930 #define GPIO_ODR_ODR_0 GPIO_ODR_OD0
lypinator 0:bb348c97df44 7931 #define GPIO_ODR_ODR_1 GPIO_ODR_OD1
lypinator 0:bb348c97df44 7932 #define GPIO_ODR_ODR_2 GPIO_ODR_OD2
lypinator 0:bb348c97df44 7933 #define GPIO_ODR_ODR_3 GPIO_ODR_OD3
lypinator 0:bb348c97df44 7934 #define GPIO_ODR_ODR_4 GPIO_ODR_OD4
lypinator 0:bb348c97df44 7935 #define GPIO_ODR_ODR_5 GPIO_ODR_OD5
lypinator 0:bb348c97df44 7936 #define GPIO_ODR_ODR_6 GPIO_ODR_OD6
lypinator 0:bb348c97df44 7937 #define GPIO_ODR_ODR_7 GPIO_ODR_OD7
lypinator 0:bb348c97df44 7938 #define GPIO_ODR_ODR_8 GPIO_ODR_OD8
lypinator 0:bb348c97df44 7939 #define GPIO_ODR_ODR_9 GPIO_ODR_OD9
lypinator 0:bb348c97df44 7940 #define GPIO_ODR_ODR_10 GPIO_ODR_OD10
lypinator 0:bb348c97df44 7941 #define GPIO_ODR_ODR_11 GPIO_ODR_OD11
lypinator 0:bb348c97df44 7942 #define GPIO_ODR_ODR_12 GPIO_ODR_OD12
lypinator 0:bb348c97df44 7943 #define GPIO_ODR_ODR_13 GPIO_ODR_OD13
lypinator 0:bb348c97df44 7944 #define GPIO_ODR_ODR_14 GPIO_ODR_OD14
lypinator 0:bb348c97df44 7945 #define GPIO_ODR_ODR_15 GPIO_ODR_OD15
lypinator 0:bb348c97df44 7946
lypinator 0:bb348c97df44 7947 /****************** Bits definition for GPIO_BSRR register ******************/
lypinator 0:bb348c97df44 7948 #define GPIO_BSRR_BS0_Pos (0U)
lypinator 0:bb348c97df44 7949 #define GPIO_BSRR_BS0_Msk (0x1U << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 7950 #define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
lypinator 0:bb348c97df44 7951 #define GPIO_BSRR_BS1_Pos (1U)
lypinator 0:bb348c97df44 7952 #define GPIO_BSRR_BS1_Msk (0x1U << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 7953 #define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
lypinator 0:bb348c97df44 7954 #define GPIO_BSRR_BS2_Pos (2U)
lypinator 0:bb348c97df44 7955 #define GPIO_BSRR_BS2_Msk (0x1U << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 7956 #define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
lypinator 0:bb348c97df44 7957 #define GPIO_BSRR_BS3_Pos (3U)
lypinator 0:bb348c97df44 7958 #define GPIO_BSRR_BS3_Msk (0x1U << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 7959 #define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
lypinator 0:bb348c97df44 7960 #define GPIO_BSRR_BS4_Pos (4U)
lypinator 0:bb348c97df44 7961 #define GPIO_BSRR_BS4_Msk (0x1U << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 7962 #define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
lypinator 0:bb348c97df44 7963 #define GPIO_BSRR_BS5_Pos (5U)
lypinator 0:bb348c97df44 7964 #define GPIO_BSRR_BS5_Msk (0x1U << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 7965 #define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
lypinator 0:bb348c97df44 7966 #define GPIO_BSRR_BS6_Pos (6U)
lypinator 0:bb348c97df44 7967 #define GPIO_BSRR_BS6_Msk (0x1U << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 7968 #define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
lypinator 0:bb348c97df44 7969 #define GPIO_BSRR_BS7_Pos (7U)
lypinator 0:bb348c97df44 7970 #define GPIO_BSRR_BS7_Msk (0x1U << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 7971 #define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
lypinator 0:bb348c97df44 7972 #define GPIO_BSRR_BS8_Pos (8U)
lypinator 0:bb348c97df44 7973 #define GPIO_BSRR_BS8_Msk (0x1U << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 7974 #define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
lypinator 0:bb348c97df44 7975 #define GPIO_BSRR_BS9_Pos (9U)
lypinator 0:bb348c97df44 7976 #define GPIO_BSRR_BS9_Msk (0x1U << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 7977 #define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
lypinator 0:bb348c97df44 7978 #define GPIO_BSRR_BS10_Pos (10U)
lypinator 0:bb348c97df44 7979 #define GPIO_BSRR_BS10_Msk (0x1U << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 7980 #define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
lypinator 0:bb348c97df44 7981 #define GPIO_BSRR_BS11_Pos (11U)
lypinator 0:bb348c97df44 7982 #define GPIO_BSRR_BS11_Msk (0x1U << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 7983 #define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
lypinator 0:bb348c97df44 7984 #define GPIO_BSRR_BS12_Pos (12U)
lypinator 0:bb348c97df44 7985 #define GPIO_BSRR_BS12_Msk (0x1U << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 7986 #define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
lypinator 0:bb348c97df44 7987 #define GPIO_BSRR_BS13_Pos (13U)
lypinator 0:bb348c97df44 7988 #define GPIO_BSRR_BS13_Msk (0x1U << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 7989 #define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
lypinator 0:bb348c97df44 7990 #define GPIO_BSRR_BS14_Pos (14U)
lypinator 0:bb348c97df44 7991 #define GPIO_BSRR_BS14_Msk (0x1U << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 7992 #define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
lypinator 0:bb348c97df44 7993 #define GPIO_BSRR_BS15_Pos (15U)
lypinator 0:bb348c97df44 7994 #define GPIO_BSRR_BS15_Msk (0x1U << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 7995 #define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
lypinator 0:bb348c97df44 7996 #define GPIO_BSRR_BR0_Pos (16U)
lypinator 0:bb348c97df44 7997 #define GPIO_BSRR_BR0_Msk (0x1U << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 7998 #define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
lypinator 0:bb348c97df44 7999 #define GPIO_BSRR_BR1_Pos (17U)
lypinator 0:bb348c97df44 8000 #define GPIO_BSRR_BR1_Msk (0x1U << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 8001 #define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
lypinator 0:bb348c97df44 8002 #define GPIO_BSRR_BR2_Pos (18U)
lypinator 0:bb348c97df44 8003 #define GPIO_BSRR_BR2_Msk (0x1U << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 8004 #define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
lypinator 0:bb348c97df44 8005 #define GPIO_BSRR_BR3_Pos (19U)
lypinator 0:bb348c97df44 8006 #define GPIO_BSRR_BR3_Msk (0x1U << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 8007 #define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
lypinator 0:bb348c97df44 8008 #define GPIO_BSRR_BR4_Pos (20U)
lypinator 0:bb348c97df44 8009 #define GPIO_BSRR_BR4_Msk (0x1U << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 8010 #define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
lypinator 0:bb348c97df44 8011 #define GPIO_BSRR_BR5_Pos (21U)
lypinator 0:bb348c97df44 8012 #define GPIO_BSRR_BR5_Msk (0x1U << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 8013 #define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
lypinator 0:bb348c97df44 8014 #define GPIO_BSRR_BR6_Pos (22U)
lypinator 0:bb348c97df44 8015 #define GPIO_BSRR_BR6_Msk (0x1U << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 8016 #define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
lypinator 0:bb348c97df44 8017 #define GPIO_BSRR_BR7_Pos (23U)
lypinator 0:bb348c97df44 8018 #define GPIO_BSRR_BR7_Msk (0x1U << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
lypinator 0:bb348c97df44 8019 #define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
lypinator 0:bb348c97df44 8020 #define GPIO_BSRR_BR8_Pos (24U)
lypinator 0:bb348c97df44 8021 #define GPIO_BSRR_BR8_Msk (0x1U << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 8022 #define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
lypinator 0:bb348c97df44 8023 #define GPIO_BSRR_BR9_Pos (25U)
lypinator 0:bb348c97df44 8024 #define GPIO_BSRR_BR9_Msk (0x1U << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 8025 #define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
lypinator 0:bb348c97df44 8026 #define GPIO_BSRR_BR10_Pos (26U)
lypinator 0:bb348c97df44 8027 #define GPIO_BSRR_BR10_Msk (0x1U << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
lypinator 0:bb348c97df44 8028 #define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
lypinator 0:bb348c97df44 8029 #define GPIO_BSRR_BR11_Pos (27U)
lypinator 0:bb348c97df44 8030 #define GPIO_BSRR_BR11_Msk (0x1U << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
lypinator 0:bb348c97df44 8031 #define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
lypinator 0:bb348c97df44 8032 #define GPIO_BSRR_BR12_Pos (28U)
lypinator 0:bb348c97df44 8033 #define GPIO_BSRR_BR12_Msk (0x1U << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
lypinator 0:bb348c97df44 8034 #define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
lypinator 0:bb348c97df44 8035 #define GPIO_BSRR_BR13_Pos (29U)
lypinator 0:bb348c97df44 8036 #define GPIO_BSRR_BR13_Msk (0x1U << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
lypinator 0:bb348c97df44 8037 #define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
lypinator 0:bb348c97df44 8038 #define GPIO_BSRR_BR14_Pos (30U)
lypinator 0:bb348c97df44 8039 #define GPIO_BSRR_BR14_Msk (0x1U << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
lypinator 0:bb348c97df44 8040 #define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
lypinator 0:bb348c97df44 8041 #define GPIO_BSRR_BR15_Pos (31U)
lypinator 0:bb348c97df44 8042 #define GPIO_BSRR_BR15_Msk (0x1U << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
lypinator 0:bb348c97df44 8043 #define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
lypinator 0:bb348c97df44 8044
lypinator 0:bb348c97df44 8045 /* Legacy defines */
lypinator 0:bb348c97df44 8046 #define GPIO_BSRR_BS_0 GPIO_BSRR_BS0
lypinator 0:bb348c97df44 8047 #define GPIO_BSRR_BS_1 GPIO_BSRR_BS1
lypinator 0:bb348c97df44 8048 #define GPIO_BSRR_BS_2 GPIO_BSRR_BS2
lypinator 0:bb348c97df44 8049 #define GPIO_BSRR_BS_3 GPIO_BSRR_BS3
lypinator 0:bb348c97df44 8050 #define GPIO_BSRR_BS_4 GPIO_BSRR_BS4
lypinator 0:bb348c97df44 8051 #define GPIO_BSRR_BS_5 GPIO_BSRR_BS5
lypinator 0:bb348c97df44 8052 #define GPIO_BSRR_BS_6 GPIO_BSRR_BS6
lypinator 0:bb348c97df44 8053 #define GPIO_BSRR_BS_7 GPIO_BSRR_BS7
lypinator 0:bb348c97df44 8054 #define GPIO_BSRR_BS_8 GPIO_BSRR_BS8
lypinator 0:bb348c97df44 8055 #define GPIO_BSRR_BS_9 GPIO_BSRR_BS9
lypinator 0:bb348c97df44 8056 #define GPIO_BSRR_BS_10 GPIO_BSRR_BS10
lypinator 0:bb348c97df44 8057 #define GPIO_BSRR_BS_11 GPIO_BSRR_BS11
lypinator 0:bb348c97df44 8058 #define GPIO_BSRR_BS_12 GPIO_BSRR_BS12
lypinator 0:bb348c97df44 8059 #define GPIO_BSRR_BS_13 GPIO_BSRR_BS13
lypinator 0:bb348c97df44 8060 #define GPIO_BSRR_BS_14 GPIO_BSRR_BS14
lypinator 0:bb348c97df44 8061 #define GPIO_BSRR_BS_15 GPIO_BSRR_BS15
lypinator 0:bb348c97df44 8062 #define GPIO_BSRR_BR_0 GPIO_BSRR_BR0
lypinator 0:bb348c97df44 8063 #define GPIO_BSRR_BR_1 GPIO_BSRR_BR1
lypinator 0:bb348c97df44 8064 #define GPIO_BSRR_BR_2 GPIO_BSRR_BR2
lypinator 0:bb348c97df44 8065 #define GPIO_BSRR_BR_3 GPIO_BSRR_BR3
lypinator 0:bb348c97df44 8066 #define GPIO_BSRR_BR_4 GPIO_BSRR_BR4
lypinator 0:bb348c97df44 8067 #define GPIO_BSRR_BR_5 GPIO_BSRR_BR5
lypinator 0:bb348c97df44 8068 #define GPIO_BSRR_BR_6 GPIO_BSRR_BR6
lypinator 0:bb348c97df44 8069 #define GPIO_BSRR_BR_7 GPIO_BSRR_BR7
lypinator 0:bb348c97df44 8070 #define GPIO_BSRR_BR_8 GPIO_BSRR_BR8
lypinator 0:bb348c97df44 8071 #define GPIO_BSRR_BR_9 GPIO_BSRR_BR9
lypinator 0:bb348c97df44 8072 #define GPIO_BSRR_BR_10 GPIO_BSRR_BR10
lypinator 0:bb348c97df44 8073 #define GPIO_BSRR_BR_11 GPIO_BSRR_BR11
lypinator 0:bb348c97df44 8074 #define GPIO_BSRR_BR_12 GPIO_BSRR_BR12
lypinator 0:bb348c97df44 8075 #define GPIO_BSRR_BR_13 GPIO_BSRR_BR13
lypinator 0:bb348c97df44 8076 #define GPIO_BSRR_BR_14 GPIO_BSRR_BR14
lypinator 0:bb348c97df44 8077 #define GPIO_BSRR_BR_15 GPIO_BSRR_BR15
lypinator 0:bb348c97df44 8078 /****************** Bit definition for GPIO_LCKR register *********************/
lypinator 0:bb348c97df44 8079 #define GPIO_LCKR_LCK0_Pos (0U)
lypinator 0:bb348c97df44 8080 #define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 8081 #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
lypinator 0:bb348c97df44 8082 #define GPIO_LCKR_LCK1_Pos (1U)
lypinator 0:bb348c97df44 8083 #define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 8084 #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
lypinator 0:bb348c97df44 8085 #define GPIO_LCKR_LCK2_Pos (2U)
lypinator 0:bb348c97df44 8086 #define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 8087 #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
lypinator 0:bb348c97df44 8088 #define GPIO_LCKR_LCK3_Pos (3U)
lypinator 0:bb348c97df44 8089 #define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 8090 #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
lypinator 0:bb348c97df44 8091 #define GPIO_LCKR_LCK4_Pos (4U)
lypinator 0:bb348c97df44 8092 #define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 8093 #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
lypinator 0:bb348c97df44 8094 #define GPIO_LCKR_LCK5_Pos (5U)
lypinator 0:bb348c97df44 8095 #define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 8096 #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
lypinator 0:bb348c97df44 8097 #define GPIO_LCKR_LCK6_Pos (6U)
lypinator 0:bb348c97df44 8098 #define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 8099 #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
lypinator 0:bb348c97df44 8100 #define GPIO_LCKR_LCK7_Pos (7U)
lypinator 0:bb348c97df44 8101 #define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 8102 #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
lypinator 0:bb348c97df44 8103 #define GPIO_LCKR_LCK8_Pos (8U)
lypinator 0:bb348c97df44 8104 #define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 8105 #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
lypinator 0:bb348c97df44 8106 #define GPIO_LCKR_LCK9_Pos (9U)
lypinator 0:bb348c97df44 8107 #define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 8108 #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
lypinator 0:bb348c97df44 8109 #define GPIO_LCKR_LCK10_Pos (10U)
lypinator 0:bb348c97df44 8110 #define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 8111 #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
lypinator 0:bb348c97df44 8112 #define GPIO_LCKR_LCK11_Pos (11U)
lypinator 0:bb348c97df44 8113 #define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 8114 #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
lypinator 0:bb348c97df44 8115 #define GPIO_LCKR_LCK12_Pos (12U)
lypinator 0:bb348c97df44 8116 #define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 8117 #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
lypinator 0:bb348c97df44 8118 #define GPIO_LCKR_LCK13_Pos (13U)
lypinator 0:bb348c97df44 8119 #define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 8120 #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
lypinator 0:bb348c97df44 8121 #define GPIO_LCKR_LCK14_Pos (14U)
lypinator 0:bb348c97df44 8122 #define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 8123 #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
lypinator 0:bb348c97df44 8124 #define GPIO_LCKR_LCK15_Pos (15U)
lypinator 0:bb348c97df44 8125 #define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 8126 #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
lypinator 0:bb348c97df44 8127 #define GPIO_LCKR_LCKK_Pos (16U)
lypinator 0:bb348c97df44 8128 #define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 8129 #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
lypinator 0:bb348c97df44 8130 /****************** Bit definition for GPIO_AFRL register *********************/
lypinator 0:bb348c97df44 8131 #define GPIO_AFRL_AFSEL0_Pos (0U)
lypinator 0:bb348c97df44 8132 #define GPIO_AFRL_AFSEL0_Msk (0xFU << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
lypinator 0:bb348c97df44 8133 #define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
lypinator 0:bb348c97df44 8134 #define GPIO_AFRL_AFSEL0_0 (0x1U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 8135 #define GPIO_AFRL_AFSEL0_1 (0x2U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 8136 #define GPIO_AFRL_AFSEL0_2 (0x4U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 8137 #define GPIO_AFRL_AFSEL0_3 (0x8U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 8138 #define GPIO_AFRL_AFSEL1_Pos (4U)
lypinator 0:bb348c97df44 8139 #define GPIO_AFRL_AFSEL1_Msk (0xFU << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
lypinator 0:bb348c97df44 8140 #define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
lypinator 0:bb348c97df44 8141 #define GPIO_AFRL_AFSEL1_0 (0x1U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 8142 #define GPIO_AFRL_AFSEL1_1 (0x2U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 8143 #define GPIO_AFRL_AFSEL1_2 (0x4U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 8144 #define GPIO_AFRL_AFSEL1_3 (0x8U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 8145 #define GPIO_AFRL_AFSEL2_Pos (8U)
lypinator 0:bb348c97df44 8146 #define GPIO_AFRL_AFSEL2_Msk (0xFU << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
lypinator 0:bb348c97df44 8147 #define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
lypinator 0:bb348c97df44 8148 #define GPIO_AFRL_AFSEL2_0 (0x1U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 8149 #define GPIO_AFRL_AFSEL2_1 (0x2U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 8150 #define GPIO_AFRL_AFSEL2_2 (0x4U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 8151 #define GPIO_AFRL_AFSEL2_3 (0x8U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 8152 #define GPIO_AFRL_AFSEL3_Pos (12U)
lypinator 0:bb348c97df44 8153 #define GPIO_AFRL_AFSEL3_Msk (0xFU << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
lypinator 0:bb348c97df44 8154 #define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
lypinator 0:bb348c97df44 8155 #define GPIO_AFRL_AFSEL3_0 (0x1U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 8156 #define GPIO_AFRL_AFSEL3_1 (0x2U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 8157 #define GPIO_AFRL_AFSEL3_2 (0x4U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 8158 #define GPIO_AFRL_AFSEL3_3 (0x8U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 8159 #define GPIO_AFRL_AFSEL4_Pos (16U)
lypinator 0:bb348c97df44 8160 #define GPIO_AFRL_AFSEL4_Msk (0xFU << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
lypinator 0:bb348c97df44 8161 #define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
lypinator 0:bb348c97df44 8162 #define GPIO_AFRL_AFSEL4_0 (0x1U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 8163 #define GPIO_AFRL_AFSEL4_1 (0x2U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 8164 #define GPIO_AFRL_AFSEL4_2 (0x4U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 8165 #define GPIO_AFRL_AFSEL4_3 (0x8U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 8166 #define GPIO_AFRL_AFSEL5_Pos (20U)
lypinator 0:bb348c97df44 8167 #define GPIO_AFRL_AFSEL5_Msk (0xFU << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
lypinator 0:bb348c97df44 8168 #define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
lypinator 0:bb348c97df44 8169 #define GPIO_AFRL_AFSEL5_0 (0x1U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 8170 #define GPIO_AFRL_AFSEL5_1 (0x2U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 8171 #define GPIO_AFRL_AFSEL5_2 (0x4U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 8172 #define GPIO_AFRL_AFSEL5_3 (0x8U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */
lypinator 0:bb348c97df44 8173 #define GPIO_AFRL_AFSEL6_Pos (24U)
lypinator 0:bb348c97df44 8174 #define GPIO_AFRL_AFSEL6_Msk (0xFU << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
lypinator 0:bb348c97df44 8175 #define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
lypinator 0:bb348c97df44 8176 #define GPIO_AFRL_AFSEL6_0 (0x1U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 8177 #define GPIO_AFRL_AFSEL6_1 (0x2U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 8178 #define GPIO_AFRL_AFSEL6_2 (0x4U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */
lypinator 0:bb348c97df44 8179 #define GPIO_AFRL_AFSEL6_3 (0x8U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */
lypinator 0:bb348c97df44 8180 #define GPIO_AFRL_AFSEL7_Pos (28U)
lypinator 0:bb348c97df44 8181 #define GPIO_AFRL_AFSEL7_Msk (0xFU << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
lypinator 0:bb348c97df44 8182 #define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
lypinator 0:bb348c97df44 8183 #define GPIO_AFRL_AFSEL7_0 (0x1U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */
lypinator 0:bb348c97df44 8184 #define GPIO_AFRL_AFSEL7_1 (0x2U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */
lypinator 0:bb348c97df44 8185 #define GPIO_AFRL_AFSEL7_2 (0x4U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */
lypinator 0:bb348c97df44 8186 #define GPIO_AFRL_AFSEL7_3 (0x8U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */
lypinator 0:bb348c97df44 8187
lypinator 0:bb348c97df44 8188 /* Legacy defines */
lypinator 0:bb348c97df44 8189 #define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
lypinator 0:bb348c97df44 8190 #define GPIO_AFRL_AFRL0_0 GPIO_AFRL_AFSEL0_0
lypinator 0:bb348c97df44 8191 #define GPIO_AFRL_AFRL0_1 GPIO_AFRL_AFSEL0_1
lypinator 0:bb348c97df44 8192 #define GPIO_AFRL_AFRL0_2 GPIO_AFRL_AFSEL0_2
lypinator 0:bb348c97df44 8193 #define GPIO_AFRL_AFRL0_3 GPIO_AFRL_AFSEL0_3
lypinator 0:bb348c97df44 8194 #define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
lypinator 0:bb348c97df44 8195 #define GPIO_AFRL_AFRL1_0 GPIO_AFRL_AFSEL1_0
lypinator 0:bb348c97df44 8196 #define GPIO_AFRL_AFRL1_1 GPIO_AFRL_AFSEL1_1
lypinator 0:bb348c97df44 8197 #define GPIO_AFRL_AFRL1_2 GPIO_AFRL_AFSEL1_2
lypinator 0:bb348c97df44 8198 #define GPIO_AFRL_AFRL1_3 GPIO_AFRL_AFSEL1_3
lypinator 0:bb348c97df44 8199 #define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
lypinator 0:bb348c97df44 8200 #define GPIO_AFRL_AFRL2_0 GPIO_AFRL_AFSEL2_0
lypinator 0:bb348c97df44 8201 #define GPIO_AFRL_AFRL2_1 GPIO_AFRL_AFSEL2_1
lypinator 0:bb348c97df44 8202 #define GPIO_AFRL_AFRL2_2 GPIO_AFRL_AFSEL2_2
lypinator 0:bb348c97df44 8203 #define GPIO_AFRL_AFRL2_3 GPIO_AFRL_AFSEL2_3
lypinator 0:bb348c97df44 8204 #define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
lypinator 0:bb348c97df44 8205 #define GPIO_AFRL_AFRL3_0 GPIO_AFRL_AFSEL3_0
lypinator 0:bb348c97df44 8206 #define GPIO_AFRL_AFRL3_1 GPIO_AFRL_AFSEL3_1
lypinator 0:bb348c97df44 8207 #define GPIO_AFRL_AFRL3_2 GPIO_AFRL_AFSEL3_2
lypinator 0:bb348c97df44 8208 #define GPIO_AFRL_AFRL3_3 GPIO_AFRL_AFSEL3_3
lypinator 0:bb348c97df44 8209 #define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
lypinator 0:bb348c97df44 8210 #define GPIO_AFRL_AFRL4_0 GPIO_AFRL_AFSEL4_0
lypinator 0:bb348c97df44 8211 #define GPIO_AFRL_AFRL4_1 GPIO_AFRL_AFSEL4_1
lypinator 0:bb348c97df44 8212 #define GPIO_AFRL_AFRL4_2 GPIO_AFRL_AFSEL4_2
lypinator 0:bb348c97df44 8213 #define GPIO_AFRL_AFRL4_3 GPIO_AFRL_AFSEL4_3
lypinator 0:bb348c97df44 8214 #define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
lypinator 0:bb348c97df44 8215 #define GPIO_AFRL_AFRL5_0 GPIO_AFRL_AFSEL5_0
lypinator 0:bb348c97df44 8216 #define GPIO_AFRL_AFRL5_1 GPIO_AFRL_AFSEL5_1
lypinator 0:bb348c97df44 8217 #define GPIO_AFRL_AFRL5_2 GPIO_AFRL_AFSEL5_2
lypinator 0:bb348c97df44 8218 #define GPIO_AFRL_AFRL5_3 GPIO_AFRL_AFSEL5_3
lypinator 0:bb348c97df44 8219 #define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
lypinator 0:bb348c97df44 8220 #define GPIO_AFRL_AFRL6_0 GPIO_AFRL_AFSEL6_0
lypinator 0:bb348c97df44 8221 #define GPIO_AFRL_AFRL6_1 GPIO_AFRL_AFSEL6_1
lypinator 0:bb348c97df44 8222 #define GPIO_AFRL_AFRL6_2 GPIO_AFRL_AFSEL6_2
lypinator 0:bb348c97df44 8223 #define GPIO_AFRL_AFRL6_3 GPIO_AFRL_AFSEL6_3
lypinator 0:bb348c97df44 8224 #define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
lypinator 0:bb348c97df44 8225 #define GPIO_AFRL_AFRL7_0 GPIO_AFRL_AFSEL7_0
lypinator 0:bb348c97df44 8226 #define GPIO_AFRL_AFRL7_1 GPIO_AFRL_AFSEL7_1
lypinator 0:bb348c97df44 8227 #define GPIO_AFRL_AFRL7_2 GPIO_AFRL_AFSEL7_2
lypinator 0:bb348c97df44 8228 #define GPIO_AFRL_AFRL7_3 GPIO_AFRL_AFSEL7_3
lypinator 0:bb348c97df44 8229
lypinator 0:bb348c97df44 8230 /****************** Bit definition for GPIO_AFRH register *********************/
lypinator 0:bb348c97df44 8231 #define GPIO_AFRH_AFSEL8_Pos (0U)
lypinator 0:bb348c97df44 8232 #define GPIO_AFRH_AFSEL8_Msk (0xFU << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
lypinator 0:bb348c97df44 8233 #define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
lypinator 0:bb348c97df44 8234 #define GPIO_AFRH_AFSEL8_0 (0x1U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 8235 #define GPIO_AFRH_AFSEL8_1 (0x2U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 8236 #define GPIO_AFRH_AFSEL8_2 (0x4U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 8237 #define GPIO_AFRH_AFSEL8_3 (0x8U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 8238 #define GPIO_AFRH_AFSEL9_Pos (4U)
lypinator 0:bb348c97df44 8239 #define GPIO_AFRH_AFSEL9_Msk (0xFU << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
lypinator 0:bb348c97df44 8240 #define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
lypinator 0:bb348c97df44 8241 #define GPIO_AFRH_AFSEL9_0 (0x1U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 8242 #define GPIO_AFRH_AFSEL9_1 (0x2U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 8243 #define GPIO_AFRH_AFSEL9_2 (0x4U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 8244 #define GPIO_AFRH_AFSEL9_3 (0x8U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 8245 #define GPIO_AFRH_AFSEL10_Pos (8U)
lypinator 0:bb348c97df44 8246 #define GPIO_AFRH_AFSEL10_Msk (0xFU << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
lypinator 0:bb348c97df44 8247 #define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
lypinator 0:bb348c97df44 8248 #define GPIO_AFRH_AFSEL10_0 (0x1U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 8249 #define GPIO_AFRH_AFSEL10_1 (0x2U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 8250 #define GPIO_AFRH_AFSEL10_2 (0x4U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 8251 #define GPIO_AFRH_AFSEL10_3 (0x8U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 8252 #define GPIO_AFRH_AFSEL11_Pos (12U)
lypinator 0:bb348c97df44 8253 #define GPIO_AFRH_AFSEL11_Msk (0xFU << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
lypinator 0:bb348c97df44 8254 #define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
lypinator 0:bb348c97df44 8255 #define GPIO_AFRH_AFSEL11_0 (0x1U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 8256 #define GPIO_AFRH_AFSEL11_1 (0x2U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 8257 #define GPIO_AFRH_AFSEL11_2 (0x4U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 8258 #define GPIO_AFRH_AFSEL11_3 (0x8U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 8259 #define GPIO_AFRH_AFSEL12_Pos (16U)
lypinator 0:bb348c97df44 8260 #define GPIO_AFRH_AFSEL12_Msk (0xFU << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
lypinator 0:bb348c97df44 8261 #define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
lypinator 0:bb348c97df44 8262 #define GPIO_AFRH_AFSEL12_0 (0x1U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 8263 #define GPIO_AFRH_AFSEL12_1 (0x2U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 8264 #define GPIO_AFRH_AFSEL12_2 (0x4U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 8265 #define GPIO_AFRH_AFSEL12_3 (0x8U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 8266 #define GPIO_AFRH_AFSEL13_Pos (20U)
lypinator 0:bb348c97df44 8267 #define GPIO_AFRH_AFSEL13_Msk (0xFU << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
lypinator 0:bb348c97df44 8268 #define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
lypinator 0:bb348c97df44 8269 #define GPIO_AFRH_AFSEL13_0 (0x1U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 8270 #define GPIO_AFRH_AFSEL13_1 (0x2U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 8271 #define GPIO_AFRH_AFSEL13_2 (0x4U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 8272 #define GPIO_AFRH_AFSEL13_3 (0x8U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */
lypinator 0:bb348c97df44 8273 #define GPIO_AFRH_AFSEL14_Pos (24U)
lypinator 0:bb348c97df44 8274 #define GPIO_AFRH_AFSEL14_Msk (0xFU << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
lypinator 0:bb348c97df44 8275 #define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
lypinator 0:bb348c97df44 8276 #define GPIO_AFRH_AFSEL14_0 (0x1U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 8277 #define GPIO_AFRH_AFSEL14_1 (0x2U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 8278 #define GPIO_AFRH_AFSEL14_2 (0x4U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */
lypinator 0:bb348c97df44 8279 #define GPIO_AFRH_AFSEL14_3 (0x8U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */
lypinator 0:bb348c97df44 8280 #define GPIO_AFRH_AFSEL15_Pos (28U)
lypinator 0:bb348c97df44 8281 #define GPIO_AFRH_AFSEL15_Msk (0xFU << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
lypinator 0:bb348c97df44 8282 #define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
lypinator 0:bb348c97df44 8283 #define GPIO_AFRH_AFSEL15_0 (0x1U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */
lypinator 0:bb348c97df44 8284 #define GPIO_AFRH_AFSEL15_1 (0x2U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */
lypinator 0:bb348c97df44 8285 #define GPIO_AFRH_AFSEL15_2 (0x4U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */
lypinator 0:bb348c97df44 8286 #define GPIO_AFRH_AFSEL15_3 (0x8U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */
lypinator 0:bb348c97df44 8287
lypinator 0:bb348c97df44 8288 /* Legacy defines */
lypinator 0:bb348c97df44 8289 #define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
lypinator 0:bb348c97df44 8290 #define GPIO_AFRH_AFRH0_0 GPIO_AFRH_AFSEL8_0
lypinator 0:bb348c97df44 8291 #define GPIO_AFRH_AFRH0_1 GPIO_AFRH_AFSEL8_1
lypinator 0:bb348c97df44 8292 #define GPIO_AFRH_AFRH0_2 GPIO_AFRH_AFSEL8_2
lypinator 0:bb348c97df44 8293 #define GPIO_AFRH_AFRH0_3 GPIO_AFRH_AFSEL8_3
lypinator 0:bb348c97df44 8294 #define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
lypinator 0:bb348c97df44 8295 #define GPIO_AFRH_AFRH1_0 GPIO_AFRH_AFSEL9_0
lypinator 0:bb348c97df44 8296 #define GPIO_AFRH_AFRH1_1 GPIO_AFRH_AFSEL9_1
lypinator 0:bb348c97df44 8297 #define GPIO_AFRH_AFRH1_2 GPIO_AFRH_AFSEL9_2
lypinator 0:bb348c97df44 8298 #define GPIO_AFRH_AFRH1_3 GPIO_AFRH_AFSEL9_3
lypinator 0:bb348c97df44 8299 #define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
lypinator 0:bb348c97df44 8300 #define GPIO_AFRH_AFRH2_0 GPIO_AFRH_AFSEL10_0
lypinator 0:bb348c97df44 8301 #define GPIO_AFRH_AFRH2_1 GPIO_AFRH_AFSEL10_1
lypinator 0:bb348c97df44 8302 #define GPIO_AFRH_AFRH2_2 GPIO_AFRH_AFSEL10_2
lypinator 0:bb348c97df44 8303 #define GPIO_AFRH_AFRH2_3 GPIO_AFRH_AFSEL10_3
lypinator 0:bb348c97df44 8304 #define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
lypinator 0:bb348c97df44 8305 #define GPIO_AFRH_AFRH3_0 GPIO_AFRH_AFSEL11_0
lypinator 0:bb348c97df44 8306 #define GPIO_AFRH_AFRH3_1 GPIO_AFRH_AFSEL11_1
lypinator 0:bb348c97df44 8307 #define GPIO_AFRH_AFRH3_2 GPIO_AFRH_AFSEL11_2
lypinator 0:bb348c97df44 8308 #define GPIO_AFRH_AFRH3_3 GPIO_AFRH_AFSEL11_3
lypinator 0:bb348c97df44 8309 #define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
lypinator 0:bb348c97df44 8310 #define GPIO_AFRH_AFRH4_0 GPIO_AFRH_AFSEL12_0
lypinator 0:bb348c97df44 8311 #define GPIO_AFRH_AFRH4_1 GPIO_AFRH_AFSEL12_1
lypinator 0:bb348c97df44 8312 #define GPIO_AFRH_AFRH4_2 GPIO_AFRH_AFSEL12_2
lypinator 0:bb348c97df44 8313 #define GPIO_AFRH_AFRH4_3 GPIO_AFRH_AFSEL12_3
lypinator 0:bb348c97df44 8314 #define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
lypinator 0:bb348c97df44 8315 #define GPIO_AFRH_AFRH5_0 GPIO_AFRH_AFSEL13_0
lypinator 0:bb348c97df44 8316 #define GPIO_AFRH_AFRH5_1 GPIO_AFRH_AFSEL13_1
lypinator 0:bb348c97df44 8317 #define GPIO_AFRH_AFRH5_2 GPIO_AFRH_AFSEL13_2
lypinator 0:bb348c97df44 8318 #define GPIO_AFRH_AFRH5_3 GPIO_AFRH_AFSEL13_3
lypinator 0:bb348c97df44 8319 #define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
lypinator 0:bb348c97df44 8320 #define GPIO_AFRH_AFRH6_0 GPIO_AFRH_AFSEL14_0
lypinator 0:bb348c97df44 8321 #define GPIO_AFRH_AFRH6_1 GPIO_AFRH_AFSEL14_1
lypinator 0:bb348c97df44 8322 #define GPIO_AFRH_AFRH6_2 GPIO_AFRH_AFSEL14_2
lypinator 0:bb348c97df44 8323 #define GPIO_AFRH_AFRH6_3 GPIO_AFRH_AFSEL14_3
lypinator 0:bb348c97df44 8324 #define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
lypinator 0:bb348c97df44 8325 #define GPIO_AFRH_AFRH7_0 GPIO_AFRH_AFSEL15_0
lypinator 0:bb348c97df44 8326 #define GPIO_AFRH_AFRH7_1 GPIO_AFRH_AFSEL15_1
lypinator 0:bb348c97df44 8327 #define GPIO_AFRH_AFRH7_2 GPIO_AFRH_AFSEL15_2
lypinator 0:bb348c97df44 8328 #define GPIO_AFRH_AFRH7_3 GPIO_AFRH_AFSEL15_3
lypinator 0:bb348c97df44 8329
lypinator 0:bb348c97df44 8330 /****************** Bits definition for GPIO_BRR register ******************/
lypinator 0:bb348c97df44 8331 #define GPIO_BRR_BR0_Pos (0U)
lypinator 0:bb348c97df44 8332 #define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 8333 #define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk
lypinator 0:bb348c97df44 8334 #define GPIO_BRR_BR1_Pos (1U)
lypinator 0:bb348c97df44 8335 #define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 8336 #define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk
lypinator 0:bb348c97df44 8337 #define GPIO_BRR_BR2_Pos (2U)
lypinator 0:bb348c97df44 8338 #define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 8339 #define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk
lypinator 0:bb348c97df44 8340 #define GPIO_BRR_BR3_Pos (3U)
lypinator 0:bb348c97df44 8341 #define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 8342 #define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk
lypinator 0:bb348c97df44 8343 #define GPIO_BRR_BR4_Pos (4U)
lypinator 0:bb348c97df44 8344 #define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 8345 #define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk
lypinator 0:bb348c97df44 8346 #define GPIO_BRR_BR5_Pos (5U)
lypinator 0:bb348c97df44 8347 #define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 8348 #define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk
lypinator 0:bb348c97df44 8349 #define GPIO_BRR_BR6_Pos (6U)
lypinator 0:bb348c97df44 8350 #define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 8351 #define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk
lypinator 0:bb348c97df44 8352 #define GPIO_BRR_BR7_Pos (7U)
lypinator 0:bb348c97df44 8353 #define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 8354 #define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk
lypinator 0:bb348c97df44 8355 #define GPIO_BRR_BR8_Pos (8U)
lypinator 0:bb348c97df44 8356 #define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 8357 #define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk
lypinator 0:bb348c97df44 8358 #define GPIO_BRR_BR9_Pos (9U)
lypinator 0:bb348c97df44 8359 #define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 8360 #define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk
lypinator 0:bb348c97df44 8361 #define GPIO_BRR_BR10_Pos (10U)
lypinator 0:bb348c97df44 8362 #define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 8363 #define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk
lypinator 0:bb348c97df44 8364 #define GPIO_BRR_BR11_Pos (11U)
lypinator 0:bb348c97df44 8365 #define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 8366 #define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk
lypinator 0:bb348c97df44 8367 #define GPIO_BRR_BR12_Pos (12U)
lypinator 0:bb348c97df44 8368 #define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 8369 #define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk
lypinator 0:bb348c97df44 8370 #define GPIO_BRR_BR13_Pos (13U)
lypinator 0:bb348c97df44 8371 #define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 8372 #define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk
lypinator 0:bb348c97df44 8373 #define GPIO_BRR_BR14_Pos (14U)
lypinator 0:bb348c97df44 8374 #define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 8375 #define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk
lypinator 0:bb348c97df44 8376 #define GPIO_BRR_BR15_Pos (15U)
lypinator 0:bb348c97df44 8377 #define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 8378 #define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk
lypinator 0:bb348c97df44 8379
lypinator 0:bb348c97df44 8380
lypinator 0:bb348c97df44 8381 /******************************************************************************/
lypinator 0:bb348c97df44 8382 /* */
lypinator 0:bb348c97df44 8383 /* Inter-integrated Circuit Interface */
lypinator 0:bb348c97df44 8384 /* */
lypinator 0:bb348c97df44 8385 /******************************************************************************/
lypinator 0:bb348c97df44 8386 /******************* Bit definition for I2C_CR1 register ********************/
lypinator 0:bb348c97df44 8387 #define I2C_CR1_PE_Pos (0U)
lypinator 0:bb348c97df44 8388 #define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 8389 #define I2C_CR1_PE I2C_CR1_PE_Msk /*!<Peripheral Enable */
lypinator 0:bb348c97df44 8390 #define I2C_CR1_SMBUS_Pos (1U)
lypinator 0:bb348c97df44 8391 #define I2C_CR1_SMBUS_Msk (0x1U << I2C_CR1_SMBUS_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 8392 #define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk /*!<SMBus Mode */
lypinator 0:bb348c97df44 8393 #define I2C_CR1_SMBTYPE_Pos (3U)
lypinator 0:bb348c97df44 8394 #define I2C_CR1_SMBTYPE_Msk (0x1U << I2C_CR1_SMBTYPE_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 8395 #define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk /*!<SMBus Type */
lypinator 0:bb348c97df44 8396 #define I2C_CR1_ENARP_Pos (4U)
lypinator 0:bb348c97df44 8397 #define I2C_CR1_ENARP_Msk (0x1U << I2C_CR1_ENARP_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 8398 #define I2C_CR1_ENARP I2C_CR1_ENARP_Msk /*!<ARP Enable */
lypinator 0:bb348c97df44 8399 #define I2C_CR1_ENPEC_Pos (5U)
lypinator 0:bb348c97df44 8400 #define I2C_CR1_ENPEC_Msk (0x1U << I2C_CR1_ENPEC_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 8401 #define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk /*!<PEC Enable */
lypinator 0:bb348c97df44 8402 #define I2C_CR1_ENGC_Pos (6U)
lypinator 0:bb348c97df44 8403 #define I2C_CR1_ENGC_Msk (0x1U << I2C_CR1_ENGC_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 8404 #define I2C_CR1_ENGC I2C_CR1_ENGC_Msk /*!<General Call Enable */
lypinator 0:bb348c97df44 8405 #define I2C_CR1_NOSTRETCH_Pos (7U)
lypinator 0:bb348c97df44 8406 #define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 8407 #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!<Clock Stretching Disable (Slave mode) */
lypinator 0:bb348c97df44 8408 #define I2C_CR1_START_Pos (8U)
lypinator 0:bb348c97df44 8409 #define I2C_CR1_START_Msk (0x1U << I2C_CR1_START_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 8410 #define I2C_CR1_START I2C_CR1_START_Msk /*!<Start Generation */
lypinator 0:bb348c97df44 8411 #define I2C_CR1_STOP_Pos (9U)
lypinator 0:bb348c97df44 8412 #define I2C_CR1_STOP_Msk (0x1U << I2C_CR1_STOP_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 8413 #define I2C_CR1_STOP I2C_CR1_STOP_Msk /*!<Stop Generation */
lypinator 0:bb348c97df44 8414 #define I2C_CR1_ACK_Pos (10U)
lypinator 0:bb348c97df44 8415 #define I2C_CR1_ACK_Msk (0x1U << I2C_CR1_ACK_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 8416 #define I2C_CR1_ACK I2C_CR1_ACK_Msk /*!<Acknowledge Enable */
lypinator 0:bb348c97df44 8417 #define I2C_CR1_POS_Pos (11U)
lypinator 0:bb348c97df44 8418 #define I2C_CR1_POS_Msk (0x1U << I2C_CR1_POS_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 8419 #define I2C_CR1_POS I2C_CR1_POS_Msk /*!<Acknowledge/PEC Position (for data reception) */
lypinator 0:bb348c97df44 8420 #define I2C_CR1_PEC_Pos (12U)
lypinator 0:bb348c97df44 8421 #define I2C_CR1_PEC_Msk (0x1U << I2C_CR1_PEC_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 8422 #define I2C_CR1_PEC I2C_CR1_PEC_Msk /*!<Packet Error Checking */
lypinator 0:bb348c97df44 8423 #define I2C_CR1_ALERT_Pos (13U)
lypinator 0:bb348c97df44 8424 #define I2C_CR1_ALERT_Msk (0x1U << I2C_CR1_ALERT_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 8425 #define I2C_CR1_ALERT I2C_CR1_ALERT_Msk /*!<SMBus Alert */
lypinator 0:bb348c97df44 8426 #define I2C_CR1_SWRST_Pos (15U)
lypinator 0:bb348c97df44 8427 #define I2C_CR1_SWRST_Msk (0x1U << I2C_CR1_SWRST_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 8428 #define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!<Software Reset */
lypinator 0:bb348c97df44 8429
lypinator 0:bb348c97df44 8430 /******************* Bit definition for I2C_CR2 register ********************/
lypinator 0:bb348c97df44 8431 #define I2C_CR2_FREQ_Pos (0U)
lypinator 0:bb348c97df44 8432 #define I2C_CR2_FREQ_Msk (0x3FU << I2C_CR2_FREQ_Pos) /*!< 0x0000003F */
lypinator 0:bb348c97df44 8433 #define I2C_CR2_FREQ I2C_CR2_FREQ_Msk /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
lypinator 0:bb348c97df44 8434 #define I2C_CR2_FREQ_0 (0x01U << I2C_CR2_FREQ_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 8435 #define I2C_CR2_FREQ_1 (0x02U << I2C_CR2_FREQ_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 8436 #define I2C_CR2_FREQ_2 (0x04U << I2C_CR2_FREQ_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 8437 #define I2C_CR2_FREQ_3 (0x08U << I2C_CR2_FREQ_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 8438 #define I2C_CR2_FREQ_4 (0x10U << I2C_CR2_FREQ_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 8439 #define I2C_CR2_FREQ_5 (0x20U << I2C_CR2_FREQ_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 8440
lypinator 0:bb348c97df44 8441 #define I2C_CR2_ITERREN_Pos (8U)
lypinator 0:bb348c97df44 8442 #define I2C_CR2_ITERREN_Msk (0x1U << I2C_CR2_ITERREN_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 8443 #define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk /*!<Error Interrupt Enable */
lypinator 0:bb348c97df44 8444 #define I2C_CR2_ITEVTEN_Pos (9U)
lypinator 0:bb348c97df44 8445 #define I2C_CR2_ITEVTEN_Msk (0x1U << I2C_CR2_ITEVTEN_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 8446 #define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk /*!<Event Interrupt Enable */
lypinator 0:bb348c97df44 8447 #define I2C_CR2_ITBUFEN_Pos (10U)
lypinator 0:bb348c97df44 8448 #define I2C_CR2_ITBUFEN_Msk (0x1U << I2C_CR2_ITBUFEN_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 8449 #define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk /*!<Buffer Interrupt Enable */
lypinator 0:bb348c97df44 8450 #define I2C_CR2_DMAEN_Pos (11U)
lypinator 0:bb348c97df44 8451 #define I2C_CR2_DMAEN_Msk (0x1U << I2C_CR2_DMAEN_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 8452 #define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk /*!<DMA Requests Enable */
lypinator 0:bb348c97df44 8453 #define I2C_CR2_LAST_Pos (12U)
lypinator 0:bb348c97df44 8454 #define I2C_CR2_LAST_Msk (0x1U << I2C_CR2_LAST_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 8455 #define I2C_CR2_LAST I2C_CR2_LAST_Msk /*!<DMA Last Transfer */
lypinator 0:bb348c97df44 8456
lypinator 0:bb348c97df44 8457 /******************* Bit definition for I2C_OAR1 register *******************/
lypinator 0:bb348c97df44 8458 #define I2C_OAR1_ADD1_7 0x000000FEU /*!<Interface Address */
lypinator 0:bb348c97df44 8459 #define I2C_OAR1_ADD8_9 0x00000300U /*!<Interface Address */
lypinator 0:bb348c97df44 8460
lypinator 0:bb348c97df44 8461 #define I2C_OAR1_ADD0_Pos (0U)
lypinator 0:bb348c97df44 8462 #define I2C_OAR1_ADD0_Msk (0x1U << I2C_OAR1_ADD0_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 8463 #define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk /*!<Bit 0 */
lypinator 0:bb348c97df44 8464 #define I2C_OAR1_ADD1_Pos (1U)
lypinator 0:bb348c97df44 8465 #define I2C_OAR1_ADD1_Msk (0x1U << I2C_OAR1_ADD1_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 8466 #define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk /*!<Bit 1 */
lypinator 0:bb348c97df44 8467 #define I2C_OAR1_ADD2_Pos (2U)
lypinator 0:bb348c97df44 8468 #define I2C_OAR1_ADD2_Msk (0x1U << I2C_OAR1_ADD2_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 8469 #define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk /*!<Bit 2 */
lypinator 0:bb348c97df44 8470 #define I2C_OAR1_ADD3_Pos (3U)
lypinator 0:bb348c97df44 8471 #define I2C_OAR1_ADD3_Msk (0x1U << I2C_OAR1_ADD3_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 8472 #define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk /*!<Bit 3 */
lypinator 0:bb348c97df44 8473 #define I2C_OAR1_ADD4_Pos (4U)
lypinator 0:bb348c97df44 8474 #define I2C_OAR1_ADD4_Msk (0x1U << I2C_OAR1_ADD4_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 8475 #define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk /*!<Bit 4 */
lypinator 0:bb348c97df44 8476 #define I2C_OAR1_ADD5_Pos (5U)
lypinator 0:bb348c97df44 8477 #define I2C_OAR1_ADD5_Msk (0x1U << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 8478 #define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk /*!<Bit 5 */
lypinator 0:bb348c97df44 8479 #define I2C_OAR1_ADD6_Pos (6U)
lypinator 0:bb348c97df44 8480 #define I2C_OAR1_ADD6_Msk (0x1U << I2C_OAR1_ADD6_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 8481 #define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk /*!<Bit 6 */
lypinator 0:bb348c97df44 8482 #define I2C_OAR1_ADD7_Pos (7U)
lypinator 0:bb348c97df44 8483 #define I2C_OAR1_ADD7_Msk (0x1U << I2C_OAR1_ADD7_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 8484 #define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk /*!<Bit 7 */
lypinator 0:bb348c97df44 8485 #define I2C_OAR1_ADD8_Pos (8U)
lypinator 0:bb348c97df44 8486 #define I2C_OAR1_ADD8_Msk (0x1U << I2C_OAR1_ADD8_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 8487 #define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk /*!<Bit 8 */
lypinator 0:bb348c97df44 8488 #define I2C_OAR1_ADD9_Pos (9U)
lypinator 0:bb348c97df44 8489 #define I2C_OAR1_ADD9_Msk (0x1U << I2C_OAR1_ADD9_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 8490 #define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk /*!<Bit 9 */
lypinator 0:bb348c97df44 8491
lypinator 0:bb348c97df44 8492 #define I2C_OAR1_ADDMODE_Pos (15U)
lypinator 0:bb348c97df44 8493 #define I2C_OAR1_ADDMODE_Msk (0x1U << I2C_OAR1_ADDMODE_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 8494 #define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk /*!<Addressing Mode (Slave mode) */
lypinator 0:bb348c97df44 8495
lypinator 0:bb348c97df44 8496 /******************* Bit definition for I2C_OAR2 register *******************/
lypinator 0:bb348c97df44 8497 #define I2C_OAR2_ENDUAL_Pos (0U)
lypinator 0:bb348c97df44 8498 #define I2C_OAR2_ENDUAL_Msk (0x1U << I2C_OAR2_ENDUAL_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 8499 #define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk /*!<Dual addressing mode enable */
lypinator 0:bb348c97df44 8500 #define I2C_OAR2_ADD2_Pos (1U)
lypinator 0:bb348c97df44 8501 #define I2C_OAR2_ADD2_Msk (0x7FU << I2C_OAR2_ADD2_Pos) /*!< 0x000000FE */
lypinator 0:bb348c97df44 8502 #define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk /*!<Interface address */
lypinator 0:bb348c97df44 8503
lypinator 0:bb348c97df44 8504 /******************** Bit definition for I2C_DR register ********************/
lypinator 0:bb348c97df44 8505 #define I2C_DR_DR_Pos (0U)
lypinator 0:bb348c97df44 8506 #define I2C_DR_DR_Msk (0xFFU << I2C_DR_DR_Pos) /*!< 0x000000FF */
lypinator 0:bb348c97df44 8507 #define I2C_DR_DR I2C_DR_DR_Msk /*!<8-bit Data Register */
lypinator 0:bb348c97df44 8508
lypinator 0:bb348c97df44 8509 /******************* Bit definition for I2C_SR1 register ********************/
lypinator 0:bb348c97df44 8510 #define I2C_SR1_SB_Pos (0U)
lypinator 0:bb348c97df44 8511 #define I2C_SR1_SB_Msk (0x1U << I2C_SR1_SB_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 8512 #define I2C_SR1_SB I2C_SR1_SB_Msk /*!<Start Bit (Master mode) */
lypinator 0:bb348c97df44 8513 #define I2C_SR1_ADDR_Pos (1U)
lypinator 0:bb348c97df44 8514 #define I2C_SR1_ADDR_Msk (0x1U << I2C_SR1_ADDR_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 8515 #define I2C_SR1_ADDR I2C_SR1_ADDR_Msk /*!<Address sent (master mode)/matched (slave mode) */
lypinator 0:bb348c97df44 8516 #define I2C_SR1_BTF_Pos (2U)
lypinator 0:bb348c97df44 8517 #define I2C_SR1_BTF_Msk (0x1U << I2C_SR1_BTF_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 8518 #define I2C_SR1_BTF I2C_SR1_BTF_Msk /*!<Byte Transfer Finished */
lypinator 0:bb348c97df44 8519 #define I2C_SR1_ADD10_Pos (3U)
lypinator 0:bb348c97df44 8520 #define I2C_SR1_ADD10_Msk (0x1U << I2C_SR1_ADD10_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 8521 #define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk /*!<10-bit header sent (Master mode) */
lypinator 0:bb348c97df44 8522 #define I2C_SR1_STOPF_Pos (4U)
lypinator 0:bb348c97df44 8523 #define I2C_SR1_STOPF_Msk (0x1U << I2C_SR1_STOPF_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 8524 #define I2C_SR1_STOPF I2C_SR1_STOPF_Msk /*!<Stop detection (Slave mode) */
lypinator 0:bb348c97df44 8525 #define I2C_SR1_RXNE_Pos (6U)
lypinator 0:bb348c97df44 8526 #define I2C_SR1_RXNE_Msk (0x1U << I2C_SR1_RXNE_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 8527 #define I2C_SR1_RXNE I2C_SR1_RXNE_Msk /*!<Data Register not Empty (receivers) */
lypinator 0:bb348c97df44 8528 #define I2C_SR1_TXE_Pos (7U)
lypinator 0:bb348c97df44 8529 #define I2C_SR1_TXE_Msk (0x1U << I2C_SR1_TXE_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 8530 #define I2C_SR1_TXE I2C_SR1_TXE_Msk /*!<Data Register Empty (transmitters) */
lypinator 0:bb348c97df44 8531 #define I2C_SR1_BERR_Pos (8U)
lypinator 0:bb348c97df44 8532 #define I2C_SR1_BERR_Msk (0x1U << I2C_SR1_BERR_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 8533 #define I2C_SR1_BERR I2C_SR1_BERR_Msk /*!<Bus Error */
lypinator 0:bb348c97df44 8534 #define I2C_SR1_ARLO_Pos (9U)
lypinator 0:bb348c97df44 8535 #define I2C_SR1_ARLO_Msk (0x1U << I2C_SR1_ARLO_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 8536 #define I2C_SR1_ARLO I2C_SR1_ARLO_Msk /*!<Arbitration Lost (master mode) */
lypinator 0:bb348c97df44 8537 #define I2C_SR1_AF_Pos (10U)
lypinator 0:bb348c97df44 8538 #define I2C_SR1_AF_Msk (0x1U << I2C_SR1_AF_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 8539 #define I2C_SR1_AF I2C_SR1_AF_Msk /*!<Acknowledge Failure */
lypinator 0:bb348c97df44 8540 #define I2C_SR1_OVR_Pos (11U)
lypinator 0:bb348c97df44 8541 #define I2C_SR1_OVR_Msk (0x1U << I2C_SR1_OVR_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 8542 #define I2C_SR1_OVR I2C_SR1_OVR_Msk /*!<Overrun/Underrun */
lypinator 0:bb348c97df44 8543 #define I2C_SR1_PECERR_Pos (12U)
lypinator 0:bb348c97df44 8544 #define I2C_SR1_PECERR_Msk (0x1U << I2C_SR1_PECERR_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 8545 #define I2C_SR1_PECERR I2C_SR1_PECERR_Msk /*!<PEC Error in reception */
lypinator 0:bb348c97df44 8546 #define I2C_SR1_TIMEOUT_Pos (14U)
lypinator 0:bb348c97df44 8547 #define I2C_SR1_TIMEOUT_Msk (0x1U << I2C_SR1_TIMEOUT_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 8548 #define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk /*!<Timeout or Tlow Error */
lypinator 0:bb348c97df44 8549 #define I2C_SR1_SMBALERT_Pos (15U)
lypinator 0:bb348c97df44 8550 #define I2C_SR1_SMBALERT_Msk (0x1U << I2C_SR1_SMBALERT_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 8551 #define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk /*!<SMBus Alert */
lypinator 0:bb348c97df44 8552
lypinator 0:bb348c97df44 8553 /******************* Bit definition for I2C_SR2 register ********************/
lypinator 0:bb348c97df44 8554 #define I2C_SR2_MSL_Pos (0U)
lypinator 0:bb348c97df44 8555 #define I2C_SR2_MSL_Msk (0x1U << I2C_SR2_MSL_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 8556 #define I2C_SR2_MSL I2C_SR2_MSL_Msk /*!<Master/Slave */
lypinator 0:bb348c97df44 8557 #define I2C_SR2_BUSY_Pos (1U)
lypinator 0:bb348c97df44 8558 #define I2C_SR2_BUSY_Msk (0x1U << I2C_SR2_BUSY_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 8559 #define I2C_SR2_BUSY I2C_SR2_BUSY_Msk /*!<Bus Busy */
lypinator 0:bb348c97df44 8560 #define I2C_SR2_TRA_Pos (2U)
lypinator 0:bb348c97df44 8561 #define I2C_SR2_TRA_Msk (0x1U << I2C_SR2_TRA_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 8562 #define I2C_SR2_TRA I2C_SR2_TRA_Msk /*!<Transmitter/Receiver */
lypinator 0:bb348c97df44 8563 #define I2C_SR2_GENCALL_Pos (4U)
lypinator 0:bb348c97df44 8564 #define I2C_SR2_GENCALL_Msk (0x1U << I2C_SR2_GENCALL_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 8565 #define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk /*!<General Call Address (Slave mode) */
lypinator 0:bb348c97df44 8566 #define I2C_SR2_SMBDEFAULT_Pos (5U)
lypinator 0:bb348c97df44 8567 #define I2C_SR2_SMBDEFAULT_Msk (0x1U << I2C_SR2_SMBDEFAULT_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 8568 #define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk /*!<SMBus Device Default Address (Slave mode) */
lypinator 0:bb348c97df44 8569 #define I2C_SR2_SMBHOST_Pos (6U)
lypinator 0:bb348c97df44 8570 #define I2C_SR2_SMBHOST_Msk (0x1U << I2C_SR2_SMBHOST_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 8571 #define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk /*!<SMBus Host Header (Slave mode) */
lypinator 0:bb348c97df44 8572 #define I2C_SR2_DUALF_Pos (7U)
lypinator 0:bb348c97df44 8573 #define I2C_SR2_DUALF_Msk (0x1U << I2C_SR2_DUALF_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 8574 #define I2C_SR2_DUALF I2C_SR2_DUALF_Msk /*!<Dual Flag (Slave mode) */
lypinator 0:bb348c97df44 8575 #define I2C_SR2_PEC_Pos (8U)
lypinator 0:bb348c97df44 8576 #define I2C_SR2_PEC_Msk (0xFFU << I2C_SR2_PEC_Pos) /*!< 0x0000FF00 */
lypinator 0:bb348c97df44 8577 #define I2C_SR2_PEC I2C_SR2_PEC_Msk /*!<Packet Error Checking Register */
lypinator 0:bb348c97df44 8578
lypinator 0:bb348c97df44 8579 /******************* Bit definition for I2C_CCR register ********************/
lypinator 0:bb348c97df44 8580 #define I2C_CCR_CCR_Pos (0U)
lypinator 0:bb348c97df44 8581 #define I2C_CCR_CCR_Msk (0xFFFU << I2C_CCR_CCR_Pos) /*!< 0x00000FFF */
lypinator 0:bb348c97df44 8582 #define I2C_CCR_CCR I2C_CCR_CCR_Msk /*!<Clock Control Register in Fast/Standard mode (Master mode) */
lypinator 0:bb348c97df44 8583 #define I2C_CCR_DUTY_Pos (14U)
lypinator 0:bb348c97df44 8584 #define I2C_CCR_DUTY_Msk (0x1U << I2C_CCR_DUTY_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 8585 #define I2C_CCR_DUTY I2C_CCR_DUTY_Msk /*!<Fast Mode Duty Cycle */
lypinator 0:bb348c97df44 8586 #define I2C_CCR_FS_Pos (15U)
lypinator 0:bb348c97df44 8587 #define I2C_CCR_FS_Msk (0x1U << I2C_CCR_FS_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 8588 #define I2C_CCR_FS I2C_CCR_FS_Msk /*!<I2C Master Mode Selection */
lypinator 0:bb348c97df44 8589
lypinator 0:bb348c97df44 8590 /****************** Bit definition for I2C_TRISE register *******************/
lypinator 0:bb348c97df44 8591 #define I2C_TRISE_TRISE_Pos (0U)
lypinator 0:bb348c97df44 8592 #define I2C_TRISE_TRISE_Msk (0x3FU << I2C_TRISE_TRISE_Pos) /*!< 0x0000003F */
lypinator 0:bb348c97df44 8593 #define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
lypinator 0:bb348c97df44 8594
lypinator 0:bb348c97df44 8595 /****************** Bit definition for I2C_FLTR register *******************/
lypinator 0:bb348c97df44 8596 #define I2C_FLTR_DNF_Pos (0U)
lypinator 0:bb348c97df44 8597 #define I2C_FLTR_DNF_Msk (0xFU << I2C_FLTR_DNF_Pos) /*!< 0x0000000F */
lypinator 0:bb348c97df44 8598 #define I2C_FLTR_DNF I2C_FLTR_DNF_Msk /*!<Digital Noise Filter */
lypinator 0:bb348c97df44 8599 #define I2C_FLTR_ANOFF_Pos (4U)
lypinator 0:bb348c97df44 8600 #define I2C_FLTR_ANOFF_Msk (0x1U << I2C_FLTR_ANOFF_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 8601 #define I2C_FLTR_ANOFF I2C_FLTR_ANOFF_Msk /*!<Analog Noise Filter OFF */
lypinator 0:bb348c97df44 8602
lypinator 0:bb348c97df44 8603 /******************************************************************************/
lypinator 0:bb348c97df44 8604 /* */
lypinator 0:bb348c97df44 8605 /* Fast Mode Plus Inter-integrated Circuit Interface (I2C) */
lypinator 0:bb348c97df44 8606 /* */
lypinator 0:bb348c97df44 8607 /******************************************************************************/
lypinator 0:bb348c97df44 8608 /******************* Bit definition for I2C_CR1 register *******************/
lypinator 0:bb348c97df44 8609 #define FMPI2C_CR1_PE_Pos (0U)
lypinator 0:bb348c97df44 8610 #define FMPI2C_CR1_PE_Msk (0x1U << FMPI2C_CR1_PE_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 8611 #define FMPI2C_CR1_PE FMPI2C_CR1_PE_Msk /*!< Peripheral enable */
lypinator 0:bb348c97df44 8612 #define FMPI2C_CR1_TXIE_Pos (1U)
lypinator 0:bb348c97df44 8613 #define FMPI2C_CR1_TXIE_Msk (0x1U << FMPI2C_CR1_TXIE_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 8614 #define FMPI2C_CR1_TXIE FMPI2C_CR1_TXIE_Msk /*!< TX interrupt enable */
lypinator 0:bb348c97df44 8615 #define FMPI2C_CR1_RXIE_Pos (2U)
lypinator 0:bb348c97df44 8616 #define FMPI2C_CR1_RXIE_Msk (0x1U << FMPI2C_CR1_RXIE_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 8617 #define FMPI2C_CR1_RXIE FMPI2C_CR1_RXIE_Msk /*!< RX interrupt enable */
lypinator 0:bb348c97df44 8618 #define FMPI2C_CR1_ADDRIE_Pos (3U)
lypinator 0:bb348c97df44 8619 #define FMPI2C_CR1_ADDRIE_Msk (0x1U << FMPI2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 8620 #define FMPI2C_CR1_ADDRIE FMPI2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */
lypinator 0:bb348c97df44 8621 #define FMPI2C_CR1_NACKIE_Pos (4U)
lypinator 0:bb348c97df44 8622 #define FMPI2C_CR1_NACKIE_Msk (0x1U << FMPI2C_CR1_NACKIE_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 8623 #define FMPI2C_CR1_NACKIE FMPI2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */
lypinator 0:bb348c97df44 8624 #define FMPI2C_CR1_STOPIE_Pos (5U)
lypinator 0:bb348c97df44 8625 #define FMPI2C_CR1_STOPIE_Msk (0x1U << FMPI2C_CR1_STOPIE_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 8626 #define FMPI2C_CR1_STOPIE FMPI2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */
lypinator 0:bb348c97df44 8627 #define FMPI2C_CR1_TCIE_Pos (6U)
lypinator 0:bb348c97df44 8628 #define FMPI2C_CR1_TCIE_Msk (0x1U << FMPI2C_CR1_TCIE_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 8629 #define FMPI2C_CR1_TCIE FMPI2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */
lypinator 0:bb348c97df44 8630 #define FMPI2C_CR1_ERRIE_Pos (7U)
lypinator 0:bb348c97df44 8631 #define FMPI2C_CR1_ERRIE_Msk (0x1U << FMPI2C_CR1_ERRIE_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 8632 #define FMPI2C_CR1_ERRIE FMPI2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */
lypinator 0:bb348c97df44 8633 #define FMPI2C_CR1_DFN_Pos (8U)
lypinator 0:bb348c97df44 8634 #define FMPI2C_CR1_DFN_Msk (0xFU << FMPI2C_CR1_DFN_Pos) /*!< 0x00000F00 */
lypinator 0:bb348c97df44 8635 #define FMPI2C_CR1_DFN FMPI2C_CR1_DFN_Msk /*!< Digital noise filter */
lypinator 0:bb348c97df44 8636 #define FMPI2C_CR1_ANFOFF_Pos (12U)
lypinator 0:bb348c97df44 8637 #define FMPI2C_CR1_ANFOFF_Msk (0x1U << FMPI2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 8638 #define FMPI2C_CR1_ANFOFF FMPI2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */
lypinator 0:bb348c97df44 8639 #define FMPI2C_CR1_TXDMAEN_Pos (14U)
lypinator 0:bb348c97df44 8640 #define FMPI2C_CR1_TXDMAEN_Msk (0x1U << FMPI2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 8641 #define FMPI2C_CR1_TXDMAEN FMPI2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */
lypinator 0:bb348c97df44 8642 #define FMPI2C_CR1_RXDMAEN_Pos (15U)
lypinator 0:bb348c97df44 8643 #define FMPI2C_CR1_RXDMAEN_Msk (0x1U << FMPI2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 8644 #define FMPI2C_CR1_RXDMAEN FMPI2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */
lypinator 0:bb348c97df44 8645 #define FMPI2C_CR1_SBC_Pos (16U)
lypinator 0:bb348c97df44 8646 #define FMPI2C_CR1_SBC_Msk (0x1U << FMPI2C_CR1_SBC_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 8647 #define FMPI2C_CR1_SBC FMPI2C_CR1_SBC_Msk /*!< Slave byte control */
lypinator 0:bb348c97df44 8648 #define FMPI2C_CR1_NOSTRETCH_Pos (17U)
lypinator 0:bb348c97df44 8649 #define FMPI2C_CR1_NOSTRETCH_Msk (0x1U << FMPI2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 8650 #define FMPI2C_CR1_NOSTRETCH FMPI2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */
lypinator 0:bb348c97df44 8651 #define FMPI2C_CR1_GCEN_Pos (19U)
lypinator 0:bb348c97df44 8652 #define FMPI2C_CR1_GCEN_Msk (0x1U << FMPI2C_CR1_GCEN_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 8653 #define FMPI2C_CR1_GCEN FMPI2C_CR1_GCEN_Msk /*!< General call enable */
lypinator 0:bb348c97df44 8654 #define FMPI2C_CR1_SMBHEN_Pos (20U)
lypinator 0:bb348c97df44 8655 #define FMPI2C_CR1_SMBHEN_Msk (0x1U << FMPI2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 8656 #define FMPI2C_CR1_SMBHEN FMPI2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */
lypinator 0:bb348c97df44 8657 #define FMPI2C_CR1_SMBDEN_Pos (21U)
lypinator 0:bb348c97df44 8658 #define FMPI2C_CR1_SMBDEN_Msk (0x1U << FMPI2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 8659 #define FMPI2C_CR1_SMBDEN FMPI2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */
lypinator 0:bb348c97df44 8660 #define FMPI2C_CR1_ALERTEN_Pos (22U)
lypinator 0:bb348c97df44 8661 #define FMPI2C_CR1_ALERTEN_Msk (0x1U << FMPI2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 8662 #define FMPI2C_CR1_ALERTEN FMPI2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */
lypinator 0:bb348c97df44 8663 #define FMPI2C_CR1_PECEN_Pos (23U)
lypinator 0:bb348c97df44 8664 #define FMPI2C_CR1_PECEN_Msk (0x1U << FMPI2C_CR1_PECEN_Pos) /*!< 0x00800000 */
lypinator 0:bb348c97df44 8665 #define FMPI2C_CR1_PECEN FMPI2C_CR1_PECEN_Msk /*!< PEC enable */
lypinator 0:bb348c97df44 8666
lypinator 0:bb348c97df44 8667 /****************** Bit definition for I2C_CR2 register ********************/
lypinator 0:bb348c97df44 8668 #define FMPI2C_CR2_SADD_Pos (0U)
lypinator 0:bb348c97df44 8669 #define FMPI2C_CR2_SADD_Msk (0x3FFU << FMPI2C_CR2_SADD_Pos) /*!< 0x000003FF */
lypinator 0:bb348c97df44 8670 #define FMPI2C_CR2_SADD FMPI2C_CR2_SADD_Msk /*!< Slave address (master mode) */
lypinator 0:bb348c97df44 8671 #define FMPI2C_CR2_RD_WRN_Pos (10U)
lypinator 0:bb348c97df44 8672 #define FMPI2C_CR2_RD_WRN_Msk (0x1U << FMPI2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 8673 #define FMPI2C_CR2_RD_WRN FMPI2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */
lypinator 0:bb348c97df44 8674 #define FMPI2C_CR2_ADD10_Pos (11U)
lypinator 0:bb348c97df44 8675 #define FMPI2C_CR2_ADD10_Msk (0x1U << FMPI2C_CR2_ADD10_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 8676 #define FMPI2C_CR2_ADD10 FMPI2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */
lypinator 0:bb348c97df44 8677 #define FMPI2C_CR2_HEAD10R_Pos (12U)
lypinator 0:bb348c97df44 8678 #define FMPI2C_CR2_HEAD10R_Msk (0x1U << FMPI2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 8679 #define FMPI2C_CR2_HEAD10R FMPI2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */
lypinator 0:bb348c97df44 8680 #define FMPI2C_CR2_START_Pos (13U)
lypinator 0:bb348c97df44 8681 #define FMPI2C_CR2_START_Msk (0x1U << FMPI2C_CR2_START_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 8682 #define FMPI2C_CR2_START FMPI2C_CR2_START_Msk /*!< START generation */
lypinator 0:bb348c97df44 8683 #define FMPI2C_CR2_STOP_Pos (14U)
lypinator 0:bb348c97df44 8684 #define FMPI2C_CR2_STOP_Msk (0x1U << FMPI2C_CR2_STOP_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 8685 #define FMPI2C_CR2_STOP FMPI2C_CR2_STOP_Msk /*!< STOP generation (master mode) */
lypinator 0:bb348c97df44 8686 #define FMPI2C_CR2_NACK_Pos (15U)
lypinator 0:bb348c97df44 8687 #define FMPI2C_CR2_NACK_Msk (0x1U << FMPI2C_CR2_NACK_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 8688 #define FMPI2C_CR2_NACK FMPI2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */
lypinator 0:bb348c97df44 8689 #define FMPI2C_CR2_NBYTES_Pos (16U)
lypinator 0:bb348c97df44 8690 #define FMPI2C_CR2_NBYTES_Msk (0xFFU << FMPI2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */
lypinator 0:bb348c97df44 8691 #define FMPI2C_CR2_NBYTES FMPI2C_CR2_NBYTES_Msk /*!< Number of bytes */
lypinator 0:bb348c97df44 8692 #define FMPI2C_CR2_RELOAD_Pos (24U)
lypinator 0:bb348c97df44 8693 #define FMPI2C_CR2_RELOAD_Msk (0x1U << FMPI2C_CR2_RELOAD_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 8694 #define FMPI2C_CR2_RELOAD FMPI2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */
lypinator 0:bb348c97df44 8695 #define FMPI2C_CR2_AUTOEND_Pos (25U)
lypinator 0:bb348c97df44 8696 #define FMPI2C_CR2_AUTOEND_Msk (0x1U << FMPI2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 8697 #define FMPI2C_CR2_AUTOEND FMPI2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */
lypinator 0:bb348c97df44 8698 #define FMPI2C_CR2_PECBYTE_Pos (26U)
lypinator 0:bb348c97df44 8699 #define FMPI2C_CR2_PECBYTE_Msk (0x1U << FMPI2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */
lypinator 0:bb348c97df44 8700 #define FMPI2C_CR2_PECBYTE FMPI2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */
lypinator 0:bb348c97df44 8701
lypinator 0:bb348c97df44 8702 /******************* Bit definition for I2C_OAR1 register ******************/
lypinator 0:bb348c97df44 8703 #define FMPI2C_OAR1_OA1_Pos (0U)
lypinator 0:bb348c97df44 8704 #define FMPI2C_OAR1_OA1_Msk (0x3FFU << FMPI2C_OAR1_OA1_Pos) /*!< 0x000003FF */
lypinator 0:bb348c97df44 8705 #define FMPI2C_OAR1_OA1 FMPI2C_OAR1_OA1_Msk /*!< Interface own address 1 */
lypinator 0:bb348c97df44 8706 #define FMPI2C_OAR1_OA1MODE_Pos (10U)
lypinator 0:bb348c97df44 8707 #define FMPI2C_OAR1_OA1MODE_Msk (0x1U << FMPI2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 8708 #define FMPI2C_OAR1_OA1MODE FMPI2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
lypinator 0:bb348c97df44 8709 #define FMPI2C_OAR1_OA1EN_Pos (15U)
lypinator 0:bb348c97df44 8710 #define FMPI2C_OAR1_OA1EN_Msk (0x1U << FMPI2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 8711 #define FMPI2C_OAR1_OA1EN FMPI2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */
lypinator 0:bb348c97df44 8712
lypinator 0:bb348c97df44 8713 /******************* Bit definition for I2C_OAR2 register ******************/
lypinator 0:bb348c97df44 8714 #define FMPI2C_OAR2_OA2_Pos (1U)
lypinator 0:bb348c97df44 8715 #define FMPI2C_OAR2_OA2_Msk (0x7FU << FMPI2C_OAR2_OA2_Pos) /*!< 0x000000FE */
lypinator 0:bb348c97df44 8716 #define FMPI2C_OAR2_OA2 FMPI2C_OAR2_OA2_Msk /*!< Interface own address 2 */
lypinator 0:bb348c97df44 8717 #define FMPI2C_OAR2_OA2MSK_Pos (8U)
lypinator 0:bb348c97df44 8718 #define FMPI2C_OAR2_OA2MSK_Msk (0x7U << FMPI2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */
lypinator 0:bb348c97df44 8719 #define FMPI2C_OAR2_OA2MSK FMPI2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */
lypinator 0:bb348c97df44 8720 #define FMPI2C_OAR2_OA2EN_Pos (15U)
lypinator 0:bb348c97df44 8721 #define FMPI2C_OAR2_OA2EN_Msk (0x1U << FMPI2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 8722 #define FMPI2C_OAR2_OA2EN FMPI2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */
lypinator 0:bb348c97df44 8723
lypinator 0:bb348c97df44 8724 /******************* Bit definition for I2C_TIMINGR register *******************/
lypinator 0:bb348c97df44 8725 #define FMPI2C_TIMINGR_SCLL_Pos (0U)
lypinator 0:bb348c97df44 8726 #define FMPI2C_TIMINGR_SCLL_Msk (0xFFU << FMPI2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */
lypinator 0:bb348c97df44 8727 #define FMPI2C_TIMINGR_SCLL FMPI2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */
lypinator 0:bb348c97df44 8728 #define FMPI2C_TIMINGR_SCLH_Pos (8U)
lypinator 0:bb348c97df44 8729 #define FMPI2C_TIMINGR_SCLH_Msk (0xFFU << FMPI2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */
lypinator 0:bb348c97df44 8730 #define FMPI2C_TIMINGR_SCLH FMPI2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */
lypinator 0:bb348c97df44 8731 #define FMPI2C_TIMINGR_SDADEL_Pos (16U)
lypinator 0:bb348c97df44 8732 #define FMPI2C_TIMINGR_SDADEL_Msk (0xFU << FMPI2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */
lypinator 0:bb348c97df44 8733 #define FMPI2C_TIMINGR_SDADEL FMPI2C_TIMINGR_SDADEL_Msk /*!< Data hold time */
lypinator 0:bb348c97df44 8734 #define FMPI2C_TIMINGR_SCLDEL_Pos (20U)
lypinator 0:bb348c97df44 8735 #define FMPI2C_TIMINGR_SCLDEL_Msk (0xFU << FMPI2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */
lypinator 0:bb348c97df44 8736 #define FMPI2C_TIMINGR_SCLDEL FMPI2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */
lypinator 0:bb348c97df44 8737 #define FMPI2C_TIMINGR_PRESC_Pos (28U)
lypinator 0:bb348c97df44 8738 #define FMPI2C_TIMINGR_PRESC_Msk (0xFU << FMPI2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */
lypinator 0:bb348c97df44 8739 #define FMPI2C_TIMINGR_PRESC FMPI2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */
lypinator 0:bb348c97df44 8740
lypinator 0:bb348c97df44 8741 /******************* Bit definition for I2C_TIMEOUTR register *******************/
lypinator 0:bb348c97df44 8742 #define FMPI2C_TIMEOUTR_TIMEOUTA_Pos (0U)
lypinator 0:bb348c97df44 8743 #define FMPI2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFU << FMPI2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */
lypinator 0:bb348c97df44 8744 #define FMPI2C_TIMEOUTR_TIMEOUTA FMPI2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */
lypinator 0:bb348c97df44 8745 #define FMPI2C_TIMEOUTR_TIDLE_Pos (12U)
lypinator 0:bb348c97df44 8746 #define FMPI2C_TIMEOUTR_TIDLE_Msk (0x1U << FMPI2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 8747 #define FMPI2C_TIMEOUTR_TIDLE FMPI2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */
lypinator 0:bb348c97df44 8748 #define FMPI2C_TIMEOUTR_TIMOUTEN_Pos (15U)
lypinator 0:bb348c97df44 8749 #define FMPI2C_TIMEOUTR_TIMOUTEN_Msk (0x1U << FMPI2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 8750 #define FMPI2C_TIMEOUTR_TIMOUTEN FMPI2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */
lypinator 0:bb348c97df44 8751 #define FMPI2C_TIMEOUTR_TIMEOUTB_Pos (16U)
lypinator 0:bb348c97df44 8752 #define FMPI2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFU << FMPI2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */
lypinator 0:bb348c97df44 8753 #define FMPI2C_TIMEOUTR_TIMEOUTB FMPI2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B */
lypinator 0:bb348c97df44 8754 #define FMPI2C_TIMEOUTR_TEXTEN_Pos (31U)
lypinator 0:bb348c97df44 8755 #define FMPI2C_TIMEOUTR_TEXTEN_Msk (0x1U << FMPI2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */
lypinator 0:bb348c97df44 8756 #define FMPI2C_TIMEOUTR_TEXTEN FMPI2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */
lypinator 0:bb348c97df44 8757
lypinator 0:bb348c97df44 8758 /****************** Bit definition for I2C_ISR register *********************/
lypinator 0:bb348c97df44 8759 #define FMPI2C_ISR_TXE_Pos (0U)
lypinator 0:bb348c97df44 8760 #define FMPI2C_ISR_TXE_Msk (0x1U << FMPI2C_ISR_TXE_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 8761 #define FMPI2C_ISR_TXE FMPI2C_ISR_TXE_Msk /*!< Transmit data register empty */
lypinator 0:bb348c97df44 8762 #define FMPI2C_ISR_TXIS_Pos (1U)
lypinator 0:bb348c97df44 8763 #define FMPI2C_ISR_TXIS_Msk (0x1U << FMPI2C_ISR_TXIS_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 8764 #define FMPI2C_ISR_TXIS FMPI2C_ISR_TXIS_Msk /*!< Transmit interrupt status */
lypinator 0:bb348c97df44 8765 #define FMPI2C_ISR_RXNE_Pos (2U)
lypinator 0:bb348c97df44 8766 #define FMPI2C_ISR_RXNE_Msk (0x1U << FMPI2C_ISR_RXNE_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 8767 #define FMPI2C_ISR_RXNE FMPI2C_ISR_RXNE_Msk /*!< Receive data register not empty */
lypinator 0:bb348c97df44 8768 #define FMPI2C_ISR_ADDR_Pos (3U)
lypinator 0:bb348c97df44 8769 #define FMPI2C_ISR_ADDR_Msk (0x1U << FMPI2C_ISR_ADDR_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 8770 #define FMPI2C_ISR_ADDR FMPI2C_ISR_ADDR_Msk /*!< Address matched (slave mode) */
lypinator 0:bb348c97df44 8771 #define FMPI2C_ISR_NACKF_Pos (4U)
lypinator 0:bb348c97df44 8772 #define FMPI2C_ISR_NACKF_Msk (0x1U << FMPI2C_ISR_NACKF_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 8773 #define FMPI2C_ISR_NACKF FMPI2C_ISR_NACKF_Msk /*!< NACK received flag */
lypinator 0:bb348c97df44 8774 #define FMPI2C_ISR_STOPF_Pos (5U)
lypinator 0:bb348c97df44 8775 #define FMPI2C_ISR_STOPF_Msk (0x1U << FMPI2C_ISR_STOPF_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 8776 #define FMPI2C_ISR_STOPF FMPI2C_ISR_STOPF_Msk /*!< STOP detection flag */
lypinator 0:bb348c97df44 8777 #define FMPI2C_ISR_TC_Pos (6U)
lypinator 0:bb348c97df44 8778 #define FMPI2C_ISR_TC_Msk (0x1U << FMPI2C_ISR_TC_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 8779 #define FMPI2C_ISR_TC FMPI2C_ISR_TC_Msk /*!< Transfer complete (master mode) */
lypinator 0:bb348c97df44 8780 #define FMPI2C_ISR_TCR_Pos (7U)
lypinator 0:bb348c97df44 8781 #define FMPI2C_ISR_TCR_Msk (0x1U << FMPI2C_ISR_TCR_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 8782 #define FMPI2C_ISR_TCR FMPI2C_ISR_TCR_Msk /*!< Transfer complete reload */
lypinator 0:bb348c97df44 8783 #define FMPI2C_ISR_BERR_Pos (8U)
lypinator 0:bb348c97df44 8784 #define FMPI2C_ISR_BERR_Msk (0x1U << FMPI2C_ISR_BERR_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 8785 #define FMPI2C_ISR_BERR FMPI2C_ISR_BERR_Msk /*!< Bus error */
lypinator 0:bb348c97df44 8786 #define FMPI2C_ISR_ARLO_Pos (9U)
lypinator 0:bb348c97df44 8787 #define FMPI2C_ISR_ARLO_Msk (0x1U << FMPI2C_ISR_ARLO_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 8788 #define FMPI2C_ISR_ARLO FMPI2C_ISR_ARLO_Msk /*!< Arbitration lost */
lypinator 0:bb348c97df44 8789 #define FMPI2C_ISR_OVR_Pos (10U)
lypinator 0:bb348c97df44 8790 #define FMPI2C_ISR_OVR_Msk (0x1U << FMPI2C_ISR_OVR_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 8791 #define FMPI2C_ISR_OVR FMPI2C_ISR_OVR_Msk /*!< Overrun/Underrun */
lypinator 0:bb348c97df44 8792 #define FMPI2C_ISR_PECERR_Pos (11U)
lypinator 0:bb348c97df44 8793 #define FMPI2C_ISR_PECERR_Msk (0x1U << FMPI2C_ISR_PECERR_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 8794 #define FMPI2C_ISR_PECERR FMPI2C_ISR_PECERR_Msk /*!< PEC error in reception */
lypinator 0:bb348c97df44 8795 #define FMPI2C_ISR_TIMEOUT_Pos (12U)
lypinator 0:bb348c97df44 8796 #define FMPI2C_ISR_TIMEOUT_Msk (0x1U << FMPI2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 8797 #define FMPI2C_ISR_TIMEOUT FMPI2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */
lypinator 0:bb348c97df44 8798 #define FMPI2C_ISR_ALERT_Pos (13U)
lypinator 0:bb348c97df44 8799 #define FMPI2C_ISR_ALERT_Msk (0x1U << FMPI2C_ISR_ALERT_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 8800 #define FMPI2C_ISR_ALERT FMPI2C_ISR_ALERT_Msk /*!< SMBus alert */
lypinator 0:bb348c97df44 8801 #define FMPI2C_ISR_BUSY_Pos (15U)
lypinator 0:bb348c97df44 8802 #define FMPI2C_ISR_BUSY_Msk (0x1U << FMPI2C_ISR_BUSY_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 8803 #define FMPI2C_ISR_BUSY FMPI2C_ISR_BUSY_Msk /*!< Bus busy */
lypinator 0:bb348c97df44 8804 #define FMPI2C_ISR_DIR_Pos (16U)
lypinator 0:bb348c97df44 8805 #define FMPI2C_ISR_DIR_Msk (0x1U << FMPI2C_ISR_DIR_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 8806 #define FMPI2C_ISR_DIR FMPI2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */
lypinator 0:bb348c97df44 8807 #define FMPI2C_ISR_ADDCODE_Pos (17U)
lypinator 0:bb348c97df44 8808 #define FMPI2C_ISR_ADDCODE_Msk (0x7FU << FMPI2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */
lypinator 0:bb348c97df44 8809 #define FMPI2C_ISR_ADDCODE FMPI2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */
lypinator 0:bb348c97df44 8810
lypinator 0:bb348c97df44 8811 /****************** Bit definition for I2C_ICR register *********************/
lypinator 0:bb348c97df44 8812 #define FMPI2C_ICR_ADDRCF_Pos (3U)
lypinator 0:bb348c97df44 8813 #define FMPI2C_ICR_ADDRCF_Msk (0x1U << FMPI2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 8814 #define FMPI2C_ICR_ADDRCF FMPI2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */
lypinator 0:bb348c97df44 8815 #define FMPI2C_ICR_NACKCF_Pos (4U)
lypinator 0:bb348c97df44 8816 #define FMPI2C_ICR_NACKCF_Msk (0x1U << FMPI2C_ICR_NACKCF_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 8817 #define FMPI2C_ICR_NACKCF FMPI2C_ICR_NACKCF_Msk /*!< NACK clear flag */
lypinator 0:bb348c97df44 8818 #define FMPI2C_ICR_STOPCF_Pos (5U)
lypinator 0:bb348c97df44 8819 #define FMPI2C_ICR_STOPCF_Msk (0x1U << FMPI2C_ICR_STOPCF_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 8820 #define FMPI2C_ICR_STOPCF FMPI2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */
lypinator 0:bb348c97df44 8821 #define FMPI2C_ICR_BERRCF_Pos (8U)
lypinator 0:bb348c97df44 8822 #define FMPI2C_ICR_BERRCF_Msk (0x1U << FMPI2C_ICR_BERRCF_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 8823 #define FMPI2C_ICR_BERRCF FMPI2C_ICR_BERRCF_Msk /*!< Bus error clear flag */
lypinator 0:bb348c97df44 8824 #define FMPI2C_ICR_ARLOCF_Pos (9U)
lypinator 0:bb348c97df44 8825 #define FMPI2C_ICR_ARLOCF_Msk (0x1U << FMPI2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 8826 #define FMPI2C_ICR_ARLOCF FMPI2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */
lypinator 0:bb348c97df44 8827 #define FMPI2C_ICR_OVRCF_Pos (10U)
lypinator 0:bb348c97df44 8828 #define FMPI2C_ICR_OVRCF_Msk (0x1U << FMPI2C_ICR_OVRCF_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 8829 #define FMPI2C_ICR_OVRCF FMPI2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */
lypinator 0:bb348c97df44 8830 #define FMPI2C_ICR_PECCF_Pos (11U)
lypinator 0:bb348c97df44 8831 #define FMPI2C_ICR_PECCF_Msk (0x1U << FMPI2C_ICR_PECCF_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 8832 #define FMPI2C_ICR_PECCF FMPI2C_ICR_PECCF_Msk /*!< PAC error clear flag */
lypinator 0:bb348c97df44 8833 #define FMPI2C_ICR_TIMOUTCF_Pos (12U)
lypinator 0:bb348c97df44 8834 #define FMPI2C_ICR_TIMOUTCF_Msk (0x1U << FMPI2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 8835 #define FMPI2C_ICR_TIMOUTCF FMPI2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */
lypinator 0:bb348c97df44 8836 #define FMPI2C_ICR_ALERTCF_Pos (13U)
lypinator 0:bb348c97df44 8837 #define FMPI2C_ICR_ALERTCF_Msk (0x1U << FMPI2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 8838 #define FMPI2C_ICR_ALERTCF FMPI2C_ICR_ALERTCF_Msk /*!< Alert clear flag */
lypinator 0:bb348c97df44 8839
lypinator 0:bb348c97df44 8840 /****************** Bit definition for I2C_PECR register *********************/
lypinator 0:bb348c97df44 8841 #define FMPI2C_PECR_PEC_Pos (0U)
lypinator 0:bb348c97df44 8842 #define FMPI2C_PECR_PEC_Msk (0xFFU << FMPI2C_PECR_PEC_Pos) /*!< 0x000000FF */
lypinator 0:bb348c97df44 8843 #define FMPI2C_PECR_PEC FMPI2C_PECR_PEC_Msk /*!< PEC register */
lypinator 0:bb348c97df44 8844
lypinator 0:bb348c97df44 8845 /****************** Bit definition for I2C_RXDR register *********************/
lypinator 0:bb348c97df44 8846 #define FMPI2C_RXDR_RXDATA_Pos (0U)
lypinator 0:bb348c97df44 8847 #define FMPI2C_RXDR_RXDATA_Msk (0xFFU << FMPI2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */
lypinator 0:bb348c97df44 8848 #define FMPI2C_RXDR_RXDATA FMPI2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */
lypinator 0:bb348c97df44 8849
lypinator 0:bb348c97df44 8850 /****************** Bit definition for I2C_TXDR register *********************/
lypinator 0:bb348c97df44 8851 #define FMPI2C_TXDR_TXDATA_Pos (0U)
lypinator 0:bb348c97df44 8852 #define FMPI2C_TXDR_TXDATA_Msk (0xFFU << FMPI2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */
lypinator 0:bb348c97df44 8853 #define FMPI2C_TXDR_TXDATA FMPI2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */
lypinator 0:bb348c97df44 8854
lypinator 0:bb348c97df44 8855
lypinator 0:bb348c97df44 8856
lypinator 0:bb348c97df44 8857 /******************************************************************************/
lypinator 0:bb348c97df44 8858 /* */
lypinator 0:bb348c97df44 8859 /* Independent WATCHDOG */
lypinator 0:bb348c97df44 8860 /* */
lypinator 0:bb348c97df44 8861 /******************************************************************************/
lypinator 0:bb348c97df44 8862 /******************* Bit definition for IWDG_KR register ********************/
lypinator 0:bb348c97df44 8863 #define IWDG_KR_KEY_Pos (0U)
lypinator 0:bb348c97df44 8864 #define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
lypinator 0:bb348c97df44 8865 #define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!<Key value (write only, read 0000h) */
lypinator 0:bb348c97df44 8866
lypinator 0:bb348c97df44 8867 /******************* Bit definition for IWDG_PR register ********************/
lypinator 0:bb348c97df44 8868 #define IWDG_PR_PR_Pos (0U)
lypinator 0:bb348c97df44 8869 #define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */
lypinator 0:bb348c97df44 8870 #define IWDG_PR_PR IWDG_PR_PR_Msk /*!<PR[2:0] (Prescaler divider) */
lypinator 0:bb348c97df44 8871 #define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x01 */
lypinator 0:bb348c97df44 8872 #define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x02 */
lypinator 0:bb348c97df44 8873 #define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x04 */
lypinator 0:bb348c97df44 8874
lypinator 0:bb348c97df44 8875 /******************* Bit definition for IWDG_RLR register *******************/
lypinator 0:bb348c97df44 8876 #define IWDG_RLR_RL_Pos (0U)
lypinator 0:bb348c97df44 8877 #define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
lypinator 0:bb348c97df44 8878 #define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!<Watchdog counter reload value */
lypinator 0:bb348c97df44 8879
lypinator 0:bb348c97df44 8880 /******************* Bit definition for IWDG_SR register ********************/
lypinator 0:bb348c97df44 8881 #define IWDG_SR_PVU_Pos (0U)
lypinator 0:bb348c97df44 8882 #define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 8883 #define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!<Watchdog prescaler value update */
lypinator 0:bb348c97df44 8884 #define IWDG_SR_RVU_Pos (1U)
lypinator 0:bb348c97df44 8885 #define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 8886 #define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!<Watchdog counter reload value update */
lypinator 0:bb348c97df44 8887
lypinator 0:bb348c97df44 8888
lypinator 0:bb348c97df44 8889
lypinator 0:bb348c97df44 8890 /******************************************************************************/
lypinator 0:bb348c97df44 8891 /* */
lypinator 0:bb348c97df44 8892 /* Power Control */
lypinator 0:bb348c97df44 8893 /* */
lypinator 0:bb348c97df44 8894 /******************************************************************************/
lypinator 0:bb348c97df44 8895 /******************** Bit definition for PWR_CR register ********************/
lypinator 0:bb348c97df44 8896 #define PWR_CR_LPDS_Pos (0U)
lypinator 0:bb348c97df44 8897 #define PWR_CR_LPDS_Msk (0x1U << PWR_CR_LPDS_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 8898 #define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-Power Deepsleep */
lypinator 0:bb348c97df44 8899 #define PWR_CR_PDDS_Pos (1U)
lypinator 0:bb348c97df44 8900 #define PWR_CR_PDDS_Msk (0x1U << PWR_CR_PDDS_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 8901 #define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */
lypinator 0:bb348c97df44 8902 #define PWR_CR_CWUF_Pos (2U)
lypinator 0:bb348c97df44 8903 #define PWR_CR_CWUF_Msk (0x1U << PWR_CR_CWUF_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 8904 #define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */
lypinator 0:bb348c97df44 8905 #define PWR_CR_CSBF_Pos (3U)
lypinator 0:bb348c97df44 8906 #define PWR_CR_CSBF_Msk (0x1U << PWR_CR_CSBF_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 8907 #define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */
lypinator 0:bb348c97df44 8908 #define PWR_CR_PVDE_Pos (4U)
lypinator 0:bb348c97df44 8909 #define PWR_CR_PVDE_Msk (0x1U << PWR_CR_PVDE_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 8910 #define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */
lypinator 0:bb348c97df44 8911
lypinator 0:bb348c97df44 8912 #define PWR_CR_PLS_Pos (5U)
lypinator 0:bb348c97df44 8913 #define PWR_CR_PLS_Msk (0x7U << PWR_CR_PLS_Pos) /*!< 0x000000E0 */
lypinator 0:bb348c97df44 8914 #define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */
lypinator 0:bb348c97df44 8915 #define PWR_CR_PLS_0 (0x1U << PWR_CR_PLS_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 8916 #define PWR_CR_PLS_1 (0x2U << PWR_CR_PLS_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 8917 #define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 8918
lypinator 0:bb348c97df44 8919 /*!< PVD level configuration */
lypinator 0:bb348c97df44 8920 #define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 0 */
lypinator 0:bb348c97df44 8921 #define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 1 */
lypinator 0:bb348c97df44 8922 #define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2 */
lypinator 0:bb348c97df44 8923 #define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 3 */
lypinator 0:bb348c97df44 8924 #define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 4 */
lypinator 0:bb348c97df44 8925 #define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 5 */
lypinator 0:bb348c97df44 8926 #define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 6 */
lypinator 0:bb348c97df44 8927 #define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 7 */
lypinator 0:bb348c97df44 8928 #define PWR_CR_DBP_Pos (8U)
lypinator 0:bb348c97df44 8929 #define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 8930 #define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */
lypinator 0:bb348c97df44 8931 #define PWR_CR_FPDS_Pos (9U)
lypinator 0:bb348c97df44 8932 #define PWR_CR_FPDS_Msk (0x1U << PWR_CR_FPDS_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 8933 #define PWR_CR_FPDS PWR_CR_FPDS_Msk /*!< Flash power down in Stop mode */
lypinator 0:bb348c97df44 8934 #define PWR_CR_LPLVDS_Pos (10U)
lypinator 0:bb348c97df44 8935 #define PWR_CR_LPLVDS_Msk (0x1U << PWR_CR_LPLVDS_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 8936 #define PWR_CR_LPLVDS PWR_CR_LPLVDS_Msk /*!< Low Power Regulator Low Voltage in Deep Sleep mode */
lypinator 0:bb348c97df44 8937 #define PWR_CR_MRLVDS_Pos (11U)
lypinator 0:bb348c97df44 8938 #define PWR_CR_MRLVDS_Msk (0x1U << PWR_CR_MRLVDS_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 8939 #define PWR_CR_MRLVDS PWR_CR_MRLVDS_Msk /*!< Main Regulator Low Voltage in Deep Sleep mode */
lypinator 0:bb348c97df44 8940 #define PWR_CR_ADCDC1_Pos (13U)
lypinator 0:bb348c97df44 8941 #define PWR_CR_ADCDC1_Msk (0x1U << PWR_CR_ADCDC1_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 8942 #define PWR_CR_ADCDC1 PWR_CR_ADCDC1_Msk /*!< Refer to AN4073 on how to use this bit */
lypinator 0:bb348c97df44 8943 #define PWR_CR_VOS_Pos (14U)
lypinator 0:bb348c97df44 8944 #define PWR_CR_VOS_Msk (0x3U << PWR_CR_VOS_Pos) /*!< 0x0000C000 */
lypinator 0:bb348c97df44 8945 #define PWR_CR_VOS PWR_CR_VOS_Msk /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
lypinator 0:bb348c97df44 8946 #define PWR_CR_VOS_0 0x00004000U /*!< Bit 0 */
lypinator 0:bb348c97df44 8947 #define PWR_CR_VOS_1 0x00008000U /*!< Bit 1 */
lypinator 0:bb348c97df44 8948 #define PWR_CR_FMSSR_Pos (20U)
lypinator 0:bb348c97df44 8949 #define PWR_CR_FMSSR_Msk (0x1U << PWR_CR_FMSSR_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 8950 #define PWR_CR_FMSSR PWR_CR_FMSSR_Msk /*!< Flash Memory Sleep System Run */
lypinator 0:bb348c97df44 8951 #define PWR_CR_FISSR_Pos (21U)
lypinator 0:bb348c97df44 8952 #define PWR_CR_FISSR_Msk (0x1U << PWR_CR_FISSR_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 8953 #define PWR_CR_FISSR PWR_CR_FISSR_Msk /*!< Flash Interface Stop while System Run */
lypinator 0:bb348c97df44 8954
lypinator 0:bb348c97df44 8955
lypinator 0:bb348c97df44 8956 /******************* Bit definition for PWR_CSR register ********************/
lypinator 0:bb348c97df44 8957 #define PWR_CSR_WUF_Pos (0U)
lypinator 0:bb348c97df44 8958 #define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 8959 #define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */
lypinator 0:bb348c97df44 8960 #define PWR_CSR_SBF_Pos (1U)
lypinator 0:bb348c97df44 8961 #define PWR_CSR_SBF_Msk (0x1U << PWR_CSR_SBF_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 8962 #define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */
lypinator 0:bb348c97df44 8963 #define PWR_CSR_PVDO_Pos (2U)
lypinator 0:bb348c97df44 8964 #define PWR_CSR_PVDO_Msk (0x1U << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 8965 #define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */
lypinator 0:bb348c97df44 8966 #define PWR_CSR_BRR_Pos (3U)
lypinator 0:bb348c97df44 8967 #define PWR_CSR_BRR_Msk (0x1U << PWR_CSR_BRR_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 8968 #define PWR_CSR_BRR PWR_CSR_BRR_Msk /*!< Backup regulator ready */
lypinator 0:bb348c97df44 8969 #define PWR_CSR_EWUP3_Pos (6U)
lypinator 0:bb348c97df44 8970 #define PWR_CSR_EWUP3_Msk (0x1U << PWR_CSR_EWUP1_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 8971 #define PWR_CSR_EWUP3 PWR_CSR_EWUP3_Msk /*!< Enable WKUP pin 3 */
lypinator 0:bb348c97df44 8972 #define PWR_CSR_EWUP2_Pos (7U)
lypinator 0:bb348c97df44 8973 #define PWR_CSR_EWUP2_Msk (0x1U << PWR_CSR_EWUP2_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 8974 #define PWR_CSR_EWUP2 PWR_CSR_EWUP2_Msk /*!< Enable WKUP pin 2 */
lypinator 0:bb348c97df44 8975 #define PWR_CSR_EWUP1_Pos (8U)
lypinator 0:bb348c97df44 8976 #define PWR_CSR_EWUP1_Msk (0x1U << PWR_CSR_EWUP1_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 8977 #define PWR_CSR_EWUP1 PWR_CSR_EWUP1_Msk /*!< Enable WKUP pin 1 */
lypinator 0:bb348c97df44 8978 #define PWR_CSR_BRE_Pos (9U)
lypinator 0:bb348c97df44 8979 #define PWR_CSR_BRE_Msk (0x1U << PWR_CSR_BRE_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 8980 #define PWR_CSR_BRE PWR_CSR_BRE_Msk /*!< Backup regulator enable */
lypinator 0:bb348c97df44 8981 #define PWR_CSR_VOSRDY_Pos (14U)
lypinator 0:bb348c97df44 8982 #define PWR_CSR_VOSRDY_Msk (0x1U << PWR_CSR_VOSRDY_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 8983 #define PWR_CSR_VOSRDY PWR_CSR_VOSRDY_Msk /*!< Regulator voltage scaling output selection ready */
lypinator 0:bb348c97df44 8984
lypinator 0:bb348c97df44 8985
lypinator 0:bb348c97df44 8986 /******************************************************************************/
lypinator 0:bb348c97df44 8987 /* */
lypinator 0:bb348c97df44 8988 /* QUADSPI */
lypinator 0:bb348c97df44 8989 /* */
lypinator 0:bb348c97df44 8990 /******************************************************************************/
lypinator 0:bb348c97df44 8991 /*
lypinator 0:bb348c97df44 8992 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
lypinator 0:bb348c97df44 8993 */
lypinator 0:bb348c97df44 8994 #define QSPI1_V2_1L /*!< QSPI Virtual Version */
lypinator 0:bb348c97df44 8995
lypinator 0:bb348c97df44 8996 /***************** Bit definition for QUADSPI_CR register *******************/
lypinator 0:bb348c97df44 8997 #define QUADSPI_CR_EN_Pos (0U)
lypinator 0:bb348c97df44 8998 #define QUADSPI_CR_EN_Msk (0x1U << QUADSPI_CR_EN_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 8999 #define QUADSPI_CR_EN QUADSPI_CR_EN_Msk /*!< Enable */
lypinator 0:bb348c97df44 9000 #define QUADSPI_CR_ABORT_Pos (1U)
lypinator 0:bb348c97df44 9001 #define QUADSPI_CR_ABORT_Msk (0x1U << QUADSPI_CR_ABORT_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 9002 #define QUADSPI_CR_ABORT QUADSPI_CR_ABORT_Msk /*!< Abort request */
lypinator 0:bb348c97df44 9003 #define QUADSPI_CR_DMAEN_Pos (2U)
lypinator 0:bb348c97df44 9004 #define QUADSPI_CR_DMAEN_Msk (0x1U << QUADSPI_CR_DMAEN_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 9005 #define QUADSPI_CR_DMAEN QUADSPI_CR_DMAEN_Msk /*!< DMA Enable */
lypinator 0:bb348c97df44 9006 #define QUADSPI_CR_TCEN_Pos (3U)
lypinator 0:bb348c97df44 9007 #define QUADSPI_CR_TCEN_Msk (0x1U << QUADSPI_CR_TCEN_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 9008 #define QUADSPI_CR_TCEN QUADSPI_CR_TCEN_Msk /*!< Timeout Counter Enable */
lypinator 0:bb348c97df44 9009 #define QUADSPI_CR_SSHIFT_Pos (4U)
lypinator 0:bb348c97df44 9010 #define QUADSPI_CR_SSHIFT_Msk (0x1U << QUADSPI_CR_SSHIFT_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 9011 #define QUADSPI_CR_SSHIFT QUADSPI_CR_SSHIFT_Msk /*!< SSHIFT Sample Shift */
lypinator 0:bb348c97df44 9012 #define QUADSPI_CR_DFM_Pos (6U)
lypinator 0:bb348c97df44 9013 #define QUADSPI_CR_DFM_Msk (0x1U << QUADSPI_CR_DFM_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 9014 #define QUADSPI_CR_DFM QUADSPI_CR_DFM_Msk /*!< Dual Flash Mode */
lypinator 0:bb348c97df44 9015 #define QUADSPI_CR_FSEL_Pos (7U)
lypinator 0:bb348c97df44 9016 #define QUADSPI_CR_FSEL_Msk (0x1U << QUADSPI_CR_FSEL_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 9017 #define QUADSPI_CR_FSEL QUADSPI_CR_FSEL_Msk /*!< Flash Select */
lypinator 0:bb348c97df44 9018 #define QUADSPI_CR_FTHRES_Pos (8U)
lypinator 0:bb348c97df44 9019 #define QUADSPI_CR_FTHRES_Msk (0x1FU << QUADSPI_CR_FTHRES_Pos) /*!< 0x00001F00 */
lypinator 0:bb348c97df44 9020 #define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk /*!< FTHRES[3:0] FIFO Level */
lypinator 0:bb348c97df44 9021 #define QUADSPI_CR_FTHRES_0 (0x01U << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 9022 #define QUADSPI_CR_FTHRES_1 (0x02U << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 9023 #define QUADSPI_CR_FTHRES_2 (0x04U << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 9024 #define QUADSPI_CR_FTHRES_3 (0x08U << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 9025 #define QUADSPI_CR_FTHRES_4 (0x10U << QUADSPI_CR_FTHRES_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 9026 #define QUADSPI_CR_TEIE_Pos (16U)
lypinator 0:bb348c97df44 9027 #define QUADSPI_CR_TEIE_Msk (0x1U << QUADSPI_CR_TEIE_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 9028 #define QUADSPI_CR_TEIE QUADSPI_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */
lypinator 0:bb348c97df44 9029 #define QUADSPI_CR_TCIE_Pos (17U)
lypinator 0:bb348c97df44 9030 #define QUADSPI_CR_TCIE_Msk (0x1U << QUADSPI_CR_TCIE_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 9031 #define QUADSPI_CR_TCIE QUADSPI_CR_TCIE_Msk /*!< Transfer Complete Interrupt Enable */
lypinator 0:bb348c97df44 9032 #define QUADSPI_CR_FTIE_Pos (18U)
lypinator 0:bb348c97df44 9033 #define QUADSPI_CR_FTIE_Msk (0x1U << QUADSPI_CR_FTIE_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 9034 #define QUADSPI_CR_FTIE QUADSPI_CR_FTIE_Msk /*!< FIFO Threshold Interrupt Enable */
lypinator 0:bb348c97df44 9035 #define QUADSPI_CR_SMIE_Pos (19U)
lypinator 0:bb348c97df44 9036 #define QUADSPI_CR_SMIE_Msk (0x1U << QUADSPI_CR_SMIE_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 9037 #define QUADSPI_CR_SMIE QUADSPI_CR_SMIE_Msk /*!< Status Match Interrupt Enable */
lypinator 0:bb348c97df44 9038 #define QUADSPI_CR_TOIE_Pos (20U)
lypinator 0:bb348c97df44 9039 #define QUADSPI_CR_TOIE_Msk (0x1U << QUADSPI_CR_TOIE_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 9040 #define QUADSPI_CR_TOIE QUADSPI_CR_TOIE_Msk /*!< TimeOut Interrupt Enable */
lypinator 0:bb348c97df44 9041 #define QUADSPI_CR_APMS_Pos (22U)
lypinator 0:bb348c97df44 9042 #define QUADSPI_CR_APMS_Msk (0x1U << QUADSPI_CR_APMS_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 9043 #define QUADSPI_CR_APMS QUADSPI_CR_APMS_Msk /*!< Bit 1 */
lypinator 0:bb348c97df44 9044 #define QUADSPI_CR_PMM_Pos (23U)
lypinator 0:bb348c97df44 9045 #define QUADSPI_CR_PMM_Msk (0x1U << QUADSPI_CR_PMM_Pos) /*!< 0x00800000 */
lypinator 0:bb348c97df44 9046 #define QUADSPI_CR_PMM QUADSPI_CR_PMM_Msk /*!< Polling Match Mode */
lypinator 0:bb348c97df44 9047 #define QUADSPI_CR_PRESCALER_Pos (24U)
lypinator 0:bb348c97df44 9048 #define QUADSPI_CR_PRESCALER_Msk (0xFFU << QUADSPI_CR_PRESCALER_Pos) /*!< 0xFF000000 */
lypinator 0:bb348c97df44 9049 #define QUADSPI_CR_PRESCALER QUADSPI_CR_PRESCALER_Msk /*!< PRESCALER[7:0] Clock prescaler */
lypinator 0:bb348c97df44 9050 #define QUADSPI_CR_PRESCALER_0 (0x01U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 9051 #define QUADSPI_CR_PRESCALER_1 (0x02U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 9052 #define QUADSPI_CR_PRESCALER_2 (0x04U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x04000000 */
lypinator 0:bb348c97df44 9053 #define QUADSPI_CR_PRESCALER_3 (0x08U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x08000000 */
lypinator 0:bb348c97df44 9054 #define QUADSPI_CR_PRESCALER_4 (0x10U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x10000000 */
lypinator 0:bb348c97df44 9055 #define QUADSPI_CR_PRESCALER_5 (0x20U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x20000000 */
lypinator 0:bb348c97df44 9056 #define QUADSPI_CR_PRESCALER_6 (0x40U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x40000000 */
lypinator 0:bb348c97df44 9057 #define QUADSPI_CR_PRESCALER_7 (0x80U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x80000000 */
lypinator 0:bb348c97df44 9058
lypinator 0:bb348c97df44 9059 /***************** Bit definition for QUADSPI_DCR register ******************/
lypinator 0:bb348c97df44 9060 #define QUADSPI_DCR_CKMODE_Pos (0U)
lypinator 0:bb348c97df44 9061 #define QUADSPI_DCR_CKMODE_Msk (0x1U << QUADSPI_DCR_CKMODE_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 9062 #define QUADSPI_DCR_CKMODE QUADSPI_DCR_CKMODE_Msk /*!< Mode 0 / Mode 3 */
lypinator 0:bb348c97df44 9063 #define QUADSPI_DCR_CSHT_Pos (8U)
lypinator 0:bb348c97df44 9064 #define QUADSPI_DCR_CSHT_Msk (0x7U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000700 */
lypinator 0:bb348c97df44 9065 #define QUADSPI_DCR_CSHT QUADSPI_DCR_CSHT_Msk /*!< CSHT[2:0]: ChipSelect High Time */
lypinator 0:bb348c97df44 9066 #define QUADSPI_DCR_CSHT_0 (0x1U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 9067 #define QUADSPI_DCR_CSHT_1 (0x2U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 9068 #define QUADSPI_DCR_CSHT_2 (0x4U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 9069 #define QUADSPI_DCR_FSIZE_Pos (16U)
lypinator 0:bb348c97df44 9070 #define QUADSPI_DCR_FSIZE_Msk (0x1FU << QUADSPI_DCR_FSIZE_Pos) /*!< 0x001F0000 */
lypinator 0:bb348c97df44 9071 #define QUADSPI_DCR_FSIZE QUADSPI_DCR_FSIZE_Msk /*!< FSIZE[4:0]: Flash Size */
lypinator 0:bb348c97df44 9072 #define QUADSPI_DCR_FSIZE_0 (0x01U << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 9073 #define QUADSPI_DCR_FSIZE_1 (0x02U << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 9074 #define QUADSPI_DCR_FSIZE_2 (0x04U << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 9075 #define QUADSPI_DCR_FSIZE_3 (0x08U << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 9076 #define QUADSPI_DCR_FSIZE_4 (0x10U << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 9077
lypinator 0:bb348c97df44 9078 /****************** Bit definition for QUADSPI_SR register *******************/
lypinator 0:bb348c97df44 9079 #define QUADSPI_SR_TEF_Pos (0U)
lypinator 0:bb348c97df44 9080 #define QUADSPI_SR_TEF_Msk (0x1U << QUADSPI_SR_TEF_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 9081 #define QUADSPI_SR_TEF QUADSPI_SR_TEF_Msk /*!< Transfer Error Flag */
lypinator 0:bb348c97df44 9082 #define QUADSPI_SR_TCF_Pos (1U)
lypinator 0:bb348c97df44 9083 #define QUADSPI_SR_TCF_Msk (0x1U << QUADSPI_SR_TCF_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 9084 #define QUADSPI_SR_TCF QUADSPI_SR_TCF_Msk /*!< Transfer Complete Flag */
lypinator 0:bb348c97df44 9085 #define QUADSPI_SR_FTF_Pos (2U)
lypinator 0:bb348c97df44 9086 #define QUADSPI_SR_FTF_Msk (0x1U << QUADSPI_SR_FTF_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 9087 #define QUADSPI_SR_FTF QUADSPI_SR_FTF_Msk /*!< FIFO Threshlod Flag */
lypinator 0:bb348c97df44 9088 #define QUADSPI_SR_SMF_Pos (3U)
lypinator 0:bb348c97df44 9089 #define QUADSPI_SR_SMF_Msk (0x1U << QUADSPI_SR_SMF_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 9090 #define QUADSPI_SR_SMF QUADSPI_SR_SMF_Msk /*!< Status Match Flag */
lypinator 0:bb348c97df44 9091 #define QUADSPI_SR_TOF_Pos (4U)
lypinator 0:bb348c97df44 9092 #define QUADSPI_SR_TOF_Msk (0x1U << QUADSPI_SR_TOF_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 9093 #define QUADSPI_SR_TOF QUADSPI_SR_TOF_Msk /*!< Timeout Flag */
lypinator 0:bb348c97df44 9094 #define QUADSPI_SR_BUSY_Pos (5U)
lypinator 0:bb348c97df44 9095 #define QUADSPI_SR_BUSY_Msk (0x1U << QUADSPI_SR_BUSY_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 9096 #define QUADSPI_SR_BUSY QUADSPI_SR_BUSY_Msk /*!< Busy */
lypinator 0:bb348c97df44 9097 #define QUADSPI_SR_FLEVEL_Pos (8U)
lypinator 0:bb348c97df44 9098 #define QUADSPI_SR_FLEVEL_Msk (0x3FU << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00003F00 */
lypinator 0:bb348c97df44 9099 #define QUADSPI_SR_FLEVEL QUADSPI_SR_FLEVEL_Msk /*!< FIFO Threshlod Flag */
lypinator 0:bb348c97df44 9100 #define QUADSPI_SR_FLEVEL_0 (0x01U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 9101 #define QUADSPI_SR_FLEVEL_1 (0x02U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 9102 #define QUADSPI_SR_FLEVEL_2 (0x04U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 9103 #define QUADSPI_SR_FLEVEL_3 (0x08U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 9104 #define QUADSPI_SR_FLEVEL_4 (0x10U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 9105 #define QUADSPI_SR_FLEVEL_5 (0x20U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 9106
lypinator 0:bb348c97df44 9107 /****************** Bit definition for QUADSPI_FCR register ******************/
lypinator 0:bb348c97df44 9108 #define QUADSPI_FCR_CTEF_Pos (0U)
lypinator 0:bb348c97df44 9109 #define QUADSPI_FCR_CTEF_Msk (0x1U << QUADSPI_FCR_CTEF_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 9110 #define QUADSPI_FCR_CTEF QUADSPI_FCR_CTEF_Msk /*!< Clear Transfer Error Flag */
lypinator 0:bb348c97df44 9111 #define QUADSPI_FCR_CTCF_Pos (1U)
lypinator 0:bb348c97df44 9112 #define QUADSPI_FCR_CTCF_Msk (0x1U << QUADSPI_FCR_CTCF_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 9113 #define QUADSPI_FCR_CTCF QUADSPI_FCR_CTCF_Msk /*!< Clear Transfer Complete Flag */
lypinator 0:bb348c97df44 9114 #define QUADSPI_FCR_CSMF_Pos (3U)
lypinator 0:bb348c97df44 9115 #define QUADSPI_FCR_CSMF_Msk (0x1U << QUADSPI_FCR_CSMF_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 9116 #define QUADSPI_FCR_CSMF QUADSPI_FCR_CSMF_Msk /*!< Clear Status Match Flag */
lypinator 0:bb348c97df44 9117 #define QUADSPI_FCR_CTOF_Pos (4U)
lypinator 0:bb348c97df44 9118 #define QUADSPI_FCR_CTOF_Msk (0x1U << QUADSPI_FCR_CTOF_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 9119 #define QUADSPI_FCR_CTOF QUADSPI_FCR_CTOF_Msk /*!< Clear Timeout Flag */
lypinator 0:bb348c97df44 9120
lypinator 0:bb348c97df44 9121 /****************** Bit definition for QUADSPI_DLR register ******************/
lypinator 0:bb348c97df44 9122 #define QUADSPI_DLR_DL_Pos (0U)
lypinator 0:bb348c97df44 9123 #define QUADSPI_DLR_DL_Msk (0xFFFFFFFFU << QUADSPI_DLR_DL_Pos) /*!< 0xFFFFFFFF */
lypinator 0:bb348c97df44 9124 #define QUADSPI_DLR_DL QUADSPI_DLR_DL_Msk /*!< DL[31:0]: Data Length */
lypinator 0:bb348c97df44 9125
lypinator 0:bb348c97df44 9126 /****************** Bit definition for QUADSPI_CCR register ******************/
lypinator 0:bb348c97df44 9127 #define QUADSPI_CCR_INSTRUCTION_Pos (0U)
lypinator 0:bb348c97df44 9128 #define QUADSPI_CCR_INSTRUCTION_Msk (0xFFU << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x000000FF */
lypinator 0:bb348c97df44 9129 #define QUADSPI_CCR_INSTRUCTION QUADSPI_CCR_INSTRUCTION_Msk /*!< INSTRUCTION[7:0]: Instruction */
lypinator 0:bb348c97df44 9130 #define QUADSPI_CCR_INSTRUCTION_0 (0x01U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 9131 #define QUADSPI_CCR_INSTRUCTION_1 (0x02U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 9132 #define QUADSPI_CCR_INSTRUCTION_2 (0x04U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 9133 #define QUADSPI_CCR_INSTRUCTION_3 (0x08U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 9134 #define QUADSPI_CCR_INSTRUCTION_4 (0x10U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 9135 #define QUADSPI_CCR_INSTRUCTION_5 (0x20U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 9136 #define QUADSPI_CCR_INSTRUCTION_6 (0x40U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 9137 #define QUADSPI_CCR_INSTRUCTION_7 (0x80U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 9138 #define QUADSPI_CCR_IMODE_Pos (8U)
lypinator 0:bb348c97df44 9139 #define QUADSPI_CCR_IMODE_Msk (0x3U << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000300 */
lypinator 0:bb348c97df44 9140 #define QUADSPI_CCR_IMODE QUADSPI_CCR_IMODE_Msk /*!< IMODE[1:0]: Instruction Mode */
lypinator 0:bb348c97df44 9141 #define QUADSPI_CCR_IMODE_0 (0x1U << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 9142 #define QUADSPI_CCR_IMODE_1 (0x2U << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 9143 #define QUADSPI_CCR_ADMODE_Pos (10U)
lypinator 0:bb348c97df44 9144 #define QUADSPI_CCR_ADMODE_Msk (0x3U << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000C00 */
lypinator 0:bb348c97df44 9145 #define QUADSPI_CCR_ADMODE QUADSPI_CCR_ADMODE_Msk /*!< ADMODE[1:0]: Address Mode */
lypinator 0:bb348c97df44 9146 #define QUADSPI_CCR_ADMODE_0 (0x1U << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 9147 #define QUADSPI_CCR_ADMODE_1 (0x2U << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 9148 #define QUADSPI_CCR_ADSIZE_Pos (12U)
lypinator 0:bb348c97df44 9149 #define QUADSPI_CCR_ADSIZE_Msk (0x3U << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00003000 */
lypinator 0:bb348c97df44 9150 #define QUADSPI_CCR_ADSIZE QUADSPI_CCR_ADSIZE_Msk /*!< ADSIZE[1:0]: Address Size */
lypinator 0:bb348c97df44 9151 #define QUADSPI_CCR_ADSIZE_0 (0x1U << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 9152 #define QUADSPI_CCR_ADSIZE_1 (0x2U << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 9153 #define QUADSPI_CCR_ABMODE_Pos (14U)
lypinator 0:bb348c97df44 9154 #define QUADSPI_CCR_ABMODE_Msk (0x3U << QUADSPI_CCR_ABMODE_Pos) /*!< 0x0000C000 */
lypinator 0:bb348c97df44 9155 #define QUADSPI_CCR_ABMODE QUADSPI_CCR_ABMODE_Msk /*!< ABMODE[1:0]: Alternate Bytes Mode */
lypinator 0:bb348c97df44 9156 #define QUADSPI_CCR_ABMODE_0 (0x1U << QUADSPI_CCR_ABMODE_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 9157 #define QUADSPI_CCR_ABMODE_1 (0x2U << QUADSPI_CCR_ABMODE_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 9158 #define QUADSPI_CCR_ABSIZE_Pos (16U)
lypinator 0:bb348c97df44 9159 #define QUADSPI_CCR_ABSIZE_Msk (0x3U << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00030000 */
lypinator 0:bb348c97df44 9160 #define QUADSPI_CCR_ABSIZE QUADSPI_CCR_ABSIZE_Msk /*!< ABSIZE[1:0]: Instruction Mode */
lypinator 0:bb348c97df44 9161 #define QUADSPI_CCR_ABSIZE_0 (0x1U << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 9162 #define QUADSPI_CCR_ABSIZE_1 (0x2U << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 9163 #define QUADSPI_CCR_DCYC_Pos (18U)
lypinator 0:bb348c97df44 9164 #define QUADSPI_CCR_DCYC_Msk (0x1FU << QUADSPI_CCR_DCYC_Pos) /*!< 0x007C0000 */
lypinator 0:bb348c97df44 9165 #define QUADSPI_CCR_DCYC QUADSPI_CCR_DCYC_Msk /*!< DCYC[4:0]: Dummy Cycles */
lypinator 0:bb348c97df44 9166 #define QUADSPI_CCR_DCYC_0 (0x01U << QUADSPI_CCR_DCYC_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 9167 #define QUADSPI_CCR_DCYC_1 (0x02U << QUADSPI_CCR_DCYC_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 9168 #define QUADSPI_CCR_DCYC_2 (0x04U << QUADSPI_CCR_DCYC_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 9169 #define QUADSPI_CCR_DCYC_3 (0x08U << QUADSPI_CCR_DCYC_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 9170 #define QUADSPI_CCR_DCYC_4 (0x10U << QUADSPI_CCR_DCYC_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 9171 #define QUADSPI_CCR_DMODE_Pos (24U)
lypinator 0:bb348c97df44 9172 #define QUADSPI_CCR_DMODE_Msk (0x3U << QUADSPI_CCR_DMODE_Pos) /*!< 0x03000000 */
lypinator 0:bb348c97df44 9173 #define QUADSPI_CCR_DMODE QUADSPI_CCR_DMODE_Msk /*!< DMODE[1:0]: Data Mode */
lypinator 0:bb348c97df44 9174 #define QUADSPI_CCR_DMODE_0 (0x1U << QUADSPI_CCR_DMODE_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 9175 #define QUADSPI_CCR_DMODE_1 (0x2U << QUADSPI_CCR_DMODE_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 9176 #define QUADSPI_CCR_FMODE_Pos (26U)
lypinator 0:bb348c97df44 9177 #define QUADSPI_CCR_FMODE_Msk (0x3U << QUADSPI_CCR_FMODE_Pos) /*!< 0x0C000000 */
lypinator 0:bb348c97df44 9178 #define QUADSPI_CCR_FMODE QUADSPI_CCR_FMODE_Msk /*!< FMODE[1:0]: Functional Mode */
lypinator 0:bb348c97df44 9179 #define QUADSPI_CCR_FMODE_0 (0x1U << QUADSPI_CCR_FMODE_Pos) /*!< 0x04000000 */
lypinator 0:bb348c97df44 9180 #define QUADSPI_CCR_FMODE_1 (0x2U << QUADSPI_CCR_FMODE_Pos) /*!< 0x08000000 */
lypinator 0:bb348c97df44 9181 #define QUADSPI_CCR_SIOO_Pos (28U)
lypinator 0:bb348c97df44 9182 #define QUADSPI_CCR_SIOO_Msk (0x1U << QUADSPI_CCR_SIOO_Pos) /*!< 0x10000000 */
lypinator 0:bb348c97df44 9183 #define QUADSPI_CCR_SIOO QUADSPI_CCR_SIOO_Msk /*!< SIOO: Send Instruction Only Once Mode */
lypinator 0:bb348c97df44 9184 #define QUADSPI_CCR_DHHC_Pos (30U)
lypinator 0:bb348c97df44 9185 #define QUADSPI_CCR_DHHC_Msk (0x1U << QUADSPI_CCR_DHHC_Pos) /*!< 0x40000000 */
lypinator 0:bb348c97df44 9186 #define QUADSPI_CCR_DHHC QUADSPI_CCR_DHHC_Msk /*!< DHHC: Delay Half Hclk Cycle */
lypinator 0:bb348c97df44 9187 #define QUADSPI_CCR_DDRM_Pos (31U)
lypinator 0:bb348c97df44 9188 #define QUADSPI_CCR_DDRM_Msk (0x1U << QUADSPI_CCR_DDRM_Pos) /*!< 0x80000000 */
lypinator 0:bb348c97df44 9189 #define QUADSPI_CCR_DDRM QUADSPI_CCR_DDRM_Msk /*!< DDRM: Double Data Rate Mode */
lypinator 0:bb348c97df44 9190 /****************** Bit definition for QUADSPI_AR register *******************/
lypinator 0:bb348c97df44 9191 #define QUADSPI_AR_ADDRESS_Pos (0U)
lypinator 0:bb348c97df44 9192 #define QUADSPI_AR_ADDRESS_Msk (0xFFFFFFFFU << QUADSPI_AR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
lypinator 0:bb348c97df44 9193 #define QUADSPI_AR_ADDRESS QUADSPI_AR_ADDRESS_Msk /*!< ADDRESS[31:0]: Address */
lypinator 0:bb348c97df44 9194
lypinator 0:bb348c97df44 9195 /****************** Bit definition for QUADSPI_ABR register ******************/
lypinator 0:bb348c97df44 9196 #define QUADSPI_ABR_ALTERNATE_Pos (0U)
lypinator 0:bb348c97df44 9197 #define QUADSPI_ABR_ALTERNATE_Msk (0xFFFFFFFFU << QUADSPI_ABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */
lypinator 0:bb348c97df44 9198 #define QUADSPI_ABR_ALTERNATE QUADSPI_ABR_ALTERNATE_Msk /*!< ALTERNATE[31:0]: Alternate Bytes */
lypinator 0:bb348c97df44 9199
lypinator 0:bb348c97df44 9200 /****************** Bit definition for QUADSPI_DR register *******************/
lypinator 0:bb348c97df44 9201 #define QUADSPI_DR_DATA_Pos (0U)
lypinator 0:bb348c97df44 9202 #define QUADSPI_DR_DATA_Msk (0xFFFFFFFFU << QUADSPI_DR_DATA_Pos) /*!< 0xFFFFFFFF */
lypinator 0:bb348c97df44 9203 #define QUADSPI_DR_DATA QUADSPI_DR_DATA_Msk /*!< DATA[31:0]: Data */
lypinator 0:bb348c97df44 9204
lypinator 0:bb348c97df44 9205 /****************** Bit definition for QUADSPI_PSMKR register ****************/
lypinator 0:bb348c97df44 9206 #define QUADSPI_PSMKR_MASK_Pos (0U)
lypinator 0:bb348c97df44 9207 #define QUADSPI_PSMKR_MASK_Msk (0xFFFFFFFFU << QUADSPI_PSMKR_MASK_Pos) /*!< 0xFFFFFFFF */
lypinator 0:bb348c97df44 9208 #define QUADSPI_PSMKR_MASK QUADSPI_PSMKR_MASK_Msk /*!< MASK[31:0]: Status Mask */
lypinator 0:bb348c97df44 9209
lypinator 0:bb348c97df44 9210 /****************** Bit definition for QUADSPI_PSMAR register ****************/
lypinator 0:bb348c97df44 9211 #define QUADSPI_PSMAR_MATCH_Pos (0U)
lypinator 0:bb348c97df44 9212 #define QUADSPI_PSMAR_MATCH_Msk (0xFFFFFFFFU << QUADSPI_PSMAR_MATCH_Pos) /*!< 0xFFFFFFFF */
lypinator 0:bb348c97df44 9213 #define QUADSPI_PSMAR_MATCH QUADSPI_PSMAR_MATCH_Msk /*!< MATCH[31:0]: Status Match */
lypinator 0:bb348c97df44 9214
lypinator 0:bb348c97df44 9215 /****************** Bit definition for QUADSPI_PIR register *****************/
lypinator 0:bb348c97df44 9216 #define QUADSPI_PIR_INTERVAL_Pos (0U)
lypinator 0:bb348c97df44 9217 #define QUADSPI_PIR_INTERVAL_Msk (0xFFFFU << QUADSPI_PIR_INTERVAL_Pos) /*!< 0x0000FFFF */
lypinator 0:bb348c97df44 9218 #define QUADSPI_PIR_INTERVAL QUADSPI_PIR_INTERVAL_Msk /*!< INTERVAL[15:0]: Polling Interval */
lypinator 0:bb348c97df44 9219
lypinator 0:bb348c97df44 9220 /****************** Bit definition for QUADSPI_LPTR register *****************/
lypinator 0:bb348c97df44 9221 #define QUADSPI_LPTR_TIMEOUT_Pos (0U)
lypinator 0:bb348c97df44 9222 #define QUADSPI_LPTR_TIMEOUT_Msk (0xFFFFU << QUADSPI_LPTR_TIMEOUT_Pos) /*!< 0x0000FFFF */
lypinator 0:bb348c97df44 9223 #define QUADSPI_LPTR_TIMEOUT QUADSPI_LPTR_TIMEOUT_Msk /*!< TIMEOUT[15:0]: Timeout period */
lypinator 0:bb348c97df44 9224
lypinator 0:bb348c97df44 9225 /******************************************************************************/
lypinator 0:bb348c97df44 9226 /* */
lypinator 0:bb348c97df44 9227 /* Reset and Clock Control */
lypinator 0:bb348c97df44 9228 /* */
lypinator 0:bb348c97df44 9229 /******************************************************************************/
lypinator 0:bb348c97df44 9230 /******************** Bit definition for RCC_CR register ********************/
lypinator 0:bb348c97df44 9231 #define RCC_CR_HSION_Pos (0U)
lypinator 0:bb348c97df44 9232 #define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 9233 #define RCC_CR_HSION RCC_CR_HSION_Msk
lypinator 0:bb348c97df44 9234 #define RCC_CR_HSIRDY_Pos (1U)
lypinator 0:bb348c97df44 9235 #define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 9236 #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk
lypinator 0:bb348c97df44 9237
lypinator 0:bb348c97df44 9238 #define RCC_CR_HSITRIM_Pos (3U)
lypinator 0:bb348c97df44 9239 #define RCC_CR_HSITRIM_Msk (0x1FU << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */
lypinator 0:bb348c97df44 9240 #define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk
lypinator 0:bb348c97df44 9241 #define RCC_CR_HSITRIM_0 (0x01U << RCC_CR_HSITRIM_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 9242 #define RCC_CR_HSITRIM_1 (0x02U << RCC_CR_HSITRIM_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 9243 #define RCC_CR_HSITRIM_2 (0x04U << RCC_CR_HSITRIM_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 9244 #define RCC_CR_HSITRIM_3 (0x08U << RCC_CR_HSITRIM_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 9245 #define RCC_CR_HSITRIM_4 (0x10U << RCC_CR_HSITRIM_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 9246
lypinator 0:bb348c97df44 9247 #define RCC_CR_HSICAL_Pos (8U)
lypinator 0:bb348c97df44 9248 #define RCC_CR_HSICAL_Msk (0xFFU << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */
lypinator 0:bb348c97df44 9249 #define RCC_CR_HSICAL RCC_CR_HSICAL_Msk
lypinator 0:bb348c97df44 9250 #define RCC_CR_HSICAL_0 (0x01U << RCC_CR_HSICAL_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 9251 #define RCC_CR_HSICAL_1 (0x02U << RCC_CR_HSICAL_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 9252 #define RCC_CR_HSICAL_2 (0x04U << RCC_CR_HSICAL_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 9253 #define RCC_CR_HSICAL_3 (0x08U << RCC_CR_HSICAL_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 9254 #define RCC_CR_HSICAL_4 (0x10U << RCC_CR_HSICAL_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 9255 #define RCC_CR_HSICAL_5 (0x20U << RCC_CR_HSICAL_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 9256 #define RCC_CR_HSICAL_6 (0x40U << RCC_CR_HSICAL_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 9257 #define RCC_CR_HSICAL_7 (0x80U << RCC_CR_HSICAL_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 9258
lypinator 0:bb348c97df44 9259 #define RCC_CR_HSEON_Pos (16U)
lypinator 0:bb348c97df44 9260 #define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 9261 #define RCC_CR_HSEON RCC_CR_HSEON_Msk
lypinator 0:bb348c97df44 9262 #define RCC_CR_HSERDY_Pos (17U)
lypinator 0:bb348c97df44 9263 #define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 9264 #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk
lypinator 0:bb348c97df44 9265 #define RCC_CR_HSEBYP_Pos (18U)
lypinator 0:bb348c97df44 9266 #define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 9267 #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk
lypinator 0:bb348c97df44 9268 #define RCC_CR_CSSON_Pos (19U)
lypinator 0:bb348c97df44 9269 #define RCC_CR_CSSON_Msk (0x1U << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 9270 #define RCC_CR_CSSON RCC_CR_CSSON_Msk
lypinator 0:bb348c97df44 9271 #define RCC_CR_PLLON_Pos (24U)
lypinator 0:bb348c97df44 9272 #define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 9273 #define RCC_CR_PLLON RCC_CR_PLLON_Msk
lypinator 0:bb348c97df44 9274 #define RCC_CR_PLLRDY_Pos (25U)
lypinator 0:bb348c97df44 9275 #define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 9276 #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk
lypinator 0:bb348c97df44 9277 /*
lypinator 0:bb348c97df44 9278 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
lypinator 0:bb348c97df44 9279 */
lypinator 0:bb348c97df44 9280 #define RCC_PLLI2S_SUPPORT /*!< Support PLLI2S oscillator */
lypinator 0:bb348c97df44 9281
lypinator 0:bb348c97df44 9282 #define RCC_CR_PLLI2SON_Pos (26U)
lypinator 0:bb348c97df44 9283 #define RCC_CR_PLLI2SON_Msk (0x1U << RCC_CR_PLLI2SON_Pos) /*!< 0x04000000 */
lypinator 0:bb348c97df44 9284 #define RCC_CR_PLLI2SON RCC_CR_PLLI2SON_Msk
lypinator 0:bb348c97df44 9285 #define RCC_CR_PLLI2SRDY_Pos (27U)
lypinator 0:bb348c97df44 9286 #define RCC_CR_PLLI2SRDY_Msk (0x1U << RCC_CR_PLLI2SRDY_Pos) /*!< 0x08000000 */
lypinator 0:bb348c97df44 9287 #define RCC_CR_PLLI2SRDY RCC_CR_PLLI2SRDY_Msk
lypinator 0:bb348c97df44 9288
lypinator 0:bb348c97df44 9289 /******************** Bit definition for RCC_PLLCFGR register ***************/
lypinator 0:bb348c97df44 9290 #define RCC_PLLCFGR_PLLM_Pos (0U)
lypinator 0:bb348c97df44 9291 #define RCC_PLLCFGR_PLLM_Msk (0x3FU << RCC_PLLCFGR_PLLM_Pos) /*!< 0x0000003F */
lypinator 0:bb348c97df44 9292 #define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk
lypinator 0:bb348c97df44 9293 #define RCC_PLLCFGR_PLLM_0 (0x01U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 9294 #define RCC_PLLCFGR_PLLM_1 (0x02U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 9295 #define RCC_PLLCFGR_PLLM_2 (0x04U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 9296 #define RCC_PLLCFGR_PLLM_3 (0x08U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 9297 #define RCC_PLLCFGR_PLLM_4 (0x10U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 9298 #define RCC_PLLCFGR_PLLM_5 (0x20U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 9299
lypinator 0:bb348c97df44 9300 #define RCC_PLLCFGR_PLLN_Pos (6U)
lypinator 0:bb348c97df44 9301 #define RCC_PLLCFGR_PLLN_Msk (0x1FFU << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00007FC0 */
lypinator 0:bb348c97df44 9302 #define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk
lypinator 0:bb348c97df44 9303 #define RCC_PLLCFGR_PLLN_0 (0x001U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 9304 #define RCC_PLLCFGR_PLLN_1 (0x002U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 9305 #define RCC_PLLCFGR_PLLN_2 (0x004U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 9306 #define RCC_PLLCFGR_PLLN_3 (0x008U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 9307 #define RCC_PLLCFGR_PLLN_4 (0x010U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 9308 #define RCC_PLLCFGR_PLLN_5 (0x020U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 9309 #define RCC_PLLCFGR_PLLN_6 (0x040U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 9310 #define RCC_PLLCFGR_PLLN_7 (0x080U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 9311 #define RCC_PLLCFGR_PLLN_8 (0x100U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 9312
lypinator 0:bb348c97df44 9313 #define RCC_PLLCFGR_PLLP_Pos (16U)
lypinator 0:bb348c97df44 9314 #define RCC_PLLCFGR_PLLP_Msk (0x3U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00030000 */
lypinator 0:bb348c97df44 9315 #define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk
lypinator 0:bb348c97df44 9316 #define RCC_PLLCFGR_PLLP_0 (0x1U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 9317 #define RCC_PLLCFGR_PLLP_1 (0x2U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 9318
lypinator 0:bb348c97df44 9319 #define RCC_PLLCFGR_PLLSRC_Pos (22U)
lypinator 0:bb348c97df44 9320 #define RCC_PLLCFGR_PLLSRC_Msk (0x1U << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 9321 #define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk
lypinator 0:bb348c97df44 9322 #define RCC_PLLCFGR_PLLSRC_HSE_Pos (22U)
lypinator 0:bb348c97df44 9323 #define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x1U << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 9324 #define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk
lypinator 0:bb348c97df44 9325 #define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
lypinator 0:bb348c97df44 9326
lypinator 0:bb348c97df44 9327 #define RCC_PLLCFGR_PLLQ_Pos (24U)
lypinator 0:bb348c97df44 9328 #define RCC_PLLCFGR_PLLQ_Msk (0xFU << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x0F000000 */
lypinator 0:bb348c97df44 9329 #define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk
lypinator 0:bb348c97df44 9330 #define RCC_PLLCFGR_PLLQ_0 (0x1U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 9331 #define RCC_PLLCFGR_PLLQ_1 (0x2U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 9332 #define RCC_PLLCFGR_PLLQ_2 (0x4U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x04000000 */
lypinator 0:bb348c97df44 9333 #define RCC_PLLCFGR_PLLQ_3 (0x8U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x08000000 */
lypinator 0:bb348c97df44 9334 /*
lypinator 0:bb348c97df44 9335 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
lypinator 0:bb348c97df44 9336 */
lypinator 0:bb348c97df44 9337 #define RCC_PLLR_I2S_CLKSOURCE_SUPPORT /*!< Support PLLR clock as I2S clock source */
lypinator 0:bb348c97df44 9338
lypinator 0:bb348c97df44 9339 #define RCC_PLLCFGR_PLLR_Pos (28U)
lypinator 0:bb348c97df44 9340 #define RCC_PLLCFGR_PLLR_Msk (0x7U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x70000000 */
lypinator 0:bb348c97df44 9341 #define RCC_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_Msk
lypinator 0:bb348c97df44 9342 #define RCC_PLLCFGR_PLLR_0 (0x1U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x10000000 */
lypinator 0:bb348c97df44 9343 #define RCC_PLLCFGR_PLLR_1 (0x2U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x20000000 */
lypinator 0:bb348c97df44 9344 #define RCC_PLLCFGR_PLLR_2 (0x4U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x40000000 */
lypinator 0:bb348c97df44 9345
lypinator 0:bb348c97df44 9346 /******************** Bit definition for RCC_CFGR register ******************/
lypinator 0:bb348c97df44 9347 /*!< SW configuration */
lypinator 0:bb348c97df44 9348 #define RCC_CFGR_SW_Pos (0U)
lypinator 0:bb348c97df44 9349 #define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
lypinator 0:bb348c97df44 9350 #define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
lypinator 0:bb348c97df44 9351 #define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 9352 #define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 9353
lypinator 0:bb348c97df44 9354 #define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */
lypinator 0:bb348c97df44 9355 #define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */
lypinator 0:bb348c97df44 9356 #define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */
lypinator 0:bb348c97df44 9357
lypinator 0:bb348c97df44 9358 /*!< SWS configuration */
lypinator 0:bb348c97df44 9359 #define RCC_CFGR_SWS_Pos (2U)
lypinator 0:bb348c97df44 9360 #define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
lypinator 0:bb348c97df44 9361 #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
lypinator 0:bb348c97df44 9362 #define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 9363 #define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 9364
lypinator 0:bb348c97df44 9365 #define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */
lypinator 0:bb348c97df44 9366 #define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */
lypinator 0:bb348c97df44 9367 #define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */
lypinator 0:bb348c97df44 9368
lypinator 0:bb348c97df44 9369 /*!< HPRE configuration */
lypinator 0:bb348c97df44 9370 #define RCC_CFGR_HPRE_Pos (4U)
lypinator 0:bb348c97df44 9371 #define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
lypinator 0:bb348c97df44 9372 #define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
lypinator 0:bb348c97df44 9373 #define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 9374 #define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 9375 #define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 9376 #define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 9377
lypinator 0:bb348c97df44 9378 #define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */
lypinator 0:bb348c97df44 9379 #define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */
lypinator 0:bb348c97df44 9380 #define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */
lypinator 0:bb348c97df44 9381 #define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */
lypinator 0:bb348c97df44 9382 #define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */
lypinator 0:bb348c97df44 9383 #define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */
lypinator 0:bb348c97df44 9384 #define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */
lypinator 0:bb348c97df44 9385 #define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */
lypinator 0:bb348c97df44 9386 #define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */
lypinator 0:bb348c97df44 9387
lypinator 0:bb348c97df44 9388 /*!< PPRE1 configuration */
lypinator 0:bb348c97df44 9389 #define RCC_CFGR_PPRE1_Pos (10U)
lypinator 0:bb348c97df44 9390 #define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /*!< 0x00001C00 */
lypinator 0:bb348c97df44 9391 #define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */
lypinator 0:bb348c97df44 9392 #define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 9393 #define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 9394 #define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 9395
lypinator 0:bb348c97df44 9396 #define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */
lypinator 0:bb348c97df44 9397 #define RCC_CFGR_PPRE1_DIV2 0x00001000U /*!< HCLK divided by 2 */
lypinator 0:bb348c97df44 9398 #define RCC_CFGR_PPRE1_DIV4 0x00001400U /*!< HCLK divided by 4 */
lypinator 0:bb348c97df44 9399 #define RCC_CFGR_PPRE1_DIV8 0x00001800U /*!< HCLK divided by 8 */
lypinator 0:bb348c97df44 9400 #define RCC_CFGR_PPRE1_DIV16 0x00001C00U /*!< HCLK divided by 16 */
lypinator 0:bb348c97df44 9401
lypinator 0:bb348c97df44 9402 /*!< PPRE2 configuration */
lypinator 0:bb348c97df44 9403 #define RCC_CFGR_PPRE2_Pos (13U)
lypinator 0:bb348c97df44 9404 #define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /*!< 0x0000E000 */
lypinator 0:bb348c97df44 9405 #define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
lypinator 0:bb348c97df44 9406 #define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 9407 #define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 9408 #define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 9409
lypinator 0:bb348c97df44 9410 #define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */
lypinator 0:bb348c97df44 9411 #define RCC_CFGR_PPRE2_DIV2 0x00008000U /*!< HCLK divided by 2 */
lypinator 0:bb348c97df44 9412 #define RCC_CFGR_PPRE2_DIV4 0x0000A000U /*!< HCLK divided by 4 */
lypinator 0:bb348c97df44 9413 #define RCC_CFGR_PPRE2_DIV8 0x0000C000U /*!< HCLK divided by 8 */
lypinator 0:bb348c97df44 9414 #define RCC_CFGR_PPRE2_DIV16 0x0000E000U /*!< HCLK divided by 16 */
lypinator 0:bb348c97df44 9415
lypinator 0:bb348c97df44 9416 /*!< RTCPRE configuration */
lypinator 0:bb348c97df44 9417 #define RCC_CFGR_RTCPRE_Pos (16U)
lypinator 0:bb348c97df44 9418 #define RCC_CFGR_RTCPRE_Msk (0x1FU << RCC_CFGR_RTCPRE_Pos) /*!< 0x001F0000 */
lypinator 0:bb348c97df44 9419 #define RCC_CFGR_RTCPRE RCC_CFGR_RTCPRE_Msk
lypinator 0:bb348c97df44 9420 #define RCC_CFGR_RTCPRE_0 (0x01U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 9421 #define RCC_CFGR_RTCPRE_1 (0x02U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 9422 #define RCC_CFGR_RTCPRE_2 (0x04U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 9423 #define RCC_CFGR_RTCPRE_3 (0x08U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 9424 #define RCC_CFGR_RTCPRE_4 (0x10U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 9425
lypinator 0:bb348c97df44 9426 /*!< MCO1 configuration */
lypinator 0:bb348c97df44 9427 #define RCC_CFGR_MCO1_Pos (21U)
lypinator 0:bb348c97df44 9428 #define RCC_CFGR_MCO1_Msk (0x3U << RCC_CFGR_MCO1_Pos) /*!< 0x00600000 */
lypinator 0:bb348c97df44 9429 #define RCC_CFGR_MCO1 RCC_CFGR_MCO1_Msk
lypinator 0:bb348c97df44 9430 #define RCC_CFGR_MCO1_0 (0x1U << RCC_CFGR_MCO1_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 9431 #define RCC_CFGR_MCO1_1 (0x2U << RCC_CFGR_MCO1_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 9432
lypinator 0:bb348c97df44 9433
lypinator 0:bb348c97df44 9434 #define RCC_CFGR_MCO1PRE_Pos (24U)
lypinator 0:bb348c97df44 9435 #define RCC_CFGR_MCO1PRE_Msk (0x7U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x07000000 */
lypinator 0:bb348c97df44 9436 #define RCC_CFGR_MCO1PRE RCC_CFGR_MCO1PRE_Msk
lypinator 0:bb348c97df44 9437 #define RCC_CFGR_MCO1PRE_0 (0x1U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 9438 #define RCC_CFGR_MCO1PRE_1 (0x2U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 9439 #define RCC_CFGR_MCO1PRE_2 (0x4U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x04000000 */
lypinator 0:bb348c97df44 9440
lypinator 0:bb348c97df44 9441 #define RCC_CFGR_MCO2PRE_Pos (27U)
lypinator 0:bb348c97df44 9442 #define RCC_CFGR_MCO2PRE_Msk (0x7U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x38000000 */
lypinator 0:bb348c97df44 9443 #define RCC_CFGR_MCO2PRE RCC_CFGR_MCO2PRE_Msk
lypinator 0:bb348c97df44 9444 #define RCC_CFGR_MCO2PRE_0 (0x1U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x08000000 */
lypinator 0:bb348c97df44 9445 #define RCC_CFGR_MCO2PRE_1 (0x2U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x10000000 */
lypinator 0:bb348c97df44 9446 #define RCC_CFGR_MCO2PRE_2 (0x4U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x20000000 */
lypinator 0:bb348c97df44 9447
lypinator 0:bb348c97df44 9448 #define RCC_CFGR_MCO2_Pos (30U)
lypinator 0:bb348c97df44 9449 #define RCC_CFGR_MCO2_Msk (0x3U << RCC_CFGR_MCO2_Pos) /*!< 0xC0000000 */
lypinator 0:bb348c97df44 9450 #define RCC_CFGR_MCO2 RCC_CFGR_MCO2_Msk
lypinator 0:bb348c97df44 9451 #define RCC_CFGR_MCO2_0 (0x1U << RCC_CFGR_MCO2_Pos) /*!< 0x40000000 */
lypinator 0:bb348c97df44 9452 #define RCC_CFGR_MCO2_1 (0x2U << RCC_CFGR_MCO2_Pos) /*!< 0x80000000 */
lypinator 0:bb348c97df44 9453
lypinator 0:bb348c97df44 9454 /******************** Bit definition for RCC_CIR register *******************/
lypinator 0:bb348c97df44 9455 #define RCC_CIR_LSIRDYF_Pos (0U)
lypinator 0:bb348c97df44 9456 #define RCC_CIR_LSIRDYF_Msk (0x1U << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 9457 #define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk
lypinator 0:bb348c97df44 9458 #define RCC_CIR_LSERDYF_Pos (1U)
lypinator 0:bb348c97df44 9459 #define RCC_CIR_LSERDYF_Msk (0x1U << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 9460 #define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk
lypinator 0:bb348c97df44 9461 #define RCC_CIR_HSIRDYF_Pos (2U)
lypinator 0:bb348c97df44 9462 #define RCC_CIR_HSIRDYF_Msk (0x1U << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 9463 #define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk
lypinator 0:bb348c97df44 9464 #define RCC_CIR_HSERDYF_Pos (3U)
lypinator 0:bb348c97df44 9465 #define RCC_CIR_HSERDYF_Msk (0x1U << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 9466 #define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk
lypinator 0:bb348c97df44 9467 #define RCC_CIR_PLLRDYF_Pos (4U)
lypinator 0:bb348c97df44 9468 #define RCC_CIR_PLLRDYF_Msk (0x1U << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 9469 #define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk
lypinator 0:bb348c97df44 9470 #define RCC_CIR_PLLI2SRDYF_Pos (5U)
lypinator 0:bb348c97df44 9471 #define RCC_CIR_PLLI2SRDYF_Msk (0x1U << RCC_CIR_PLLI2SRDYF_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 9472 #define RCC_CIR_PLLI2SRDYF RCC_CIR_PLLI2SRDYF_Msk
lypinator 0:bb348c97df44 9473
lypinator 0:bb348c97df44 9474 #define RCC_CIR_CSSF_Pos (7U)
lypinator 0:bb348c97df44 9475 #define RCC_CIR_CSSF_Msk (0x1U << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 9476 #define RCC_CIR_CSSF RCC_CIR_CSSF_Msk
lypinator 0:bb348c97df44 9477 #define RCC_CIR_LSIRDYIE_Pos (8U)
lypinator 0:bb348c97df44 9478 #define RCC_CIR_LSIRDYIE_Msk (0x1U << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 9479 #define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk
lypinator 0:bb348c97df44 9480 #define RCC_CIR_LSERDYIE_Pos (9U)
lypinator 0:bb348c97df44 9481 #define RCC_CIR_LSERDYIE_Msk (0x1U << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 9482 #define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk
lypinator 0:bb348c97df44 9483 #define RCC_CIR_HSIRDYIE_Pos (10U)
lypinator 0:bb348c97df44 9484 #define RCC_CIR_HSIRDYIE_Msk (0x1U << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 9485 #define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk
lypinator 0:bb348c97df44 9486 #define RCC_CIR_HSERDYIE_Pos (11U)
lypinator 0:bb348c97df44 9487 #define RCC_CIR_HSERDYIE_Msk (0x1U << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 9488 #define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk
lypinator 0:bb348c97df44 9489 #define RCC_CIR_PLLRDYIE_Pos (12U)
lypinator 0:bb348c97df44 9490 #define RCC_CIR_PLLRDYIE_Msk (0x1U << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 9491 #define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk
lypinator 0:bb348c97df44 9492 #define RCC_CIR_PLLI2SRDYIE_Pos (13U)
lypinator 0:bb348c97df44 9493 #define RCC_CIR_PLLI2SRDYIE_Msk (0x1U << RCC_CIR_PLLI2SRDYIE_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 9494 #define RCC_CIR_PLLI2SRDYIE RCC_CIR_PLLI2SRDYIE_Msk
lypinator 0:bb348c97df44 9495
lypinator 0:bb348c97df44 9496 #define RCC_CIR_LSIRDYC_Pos (16U)
lypinator 0:bb348c97df44 9497 #define RCC_CIR_LSIRDYC_Msk (0x1U << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 9498 #define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk
lypinator 0:bb348c97df44 9499 #define RCC_CIR_LSERDYC_Pos (17U)
lypinator 0:bb348c97df44 9500 #define RCC_CIR_LSERDYC_Msk (0x1U << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 9501 #define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk
lypinator 0:bb348c97df44 9502 #define RCC_CIR_HSIRDYC_Pos (18U)
lypinator 0:bb348c97df44 9503 #define RCC_CIR_HSIRDYC_Msk (0x1U << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 9504 #define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk
lypinator 0:bb348c97df44 9505 #define RCC_CIR_HSERDYC_Pos (19U)
lypinator 0:bb348c97df44 9506 #define RCC_CIR_HSERDYC_Msk (0x1U << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 9507 #define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk
lypinator 0:bb348c97df44 9508 #define RCC_CIR_PLLRDYC_Pos (20U)
lypinator 0:bb348c97df44 9509 #define RCC_CIR_PLLRDYC_Msk (0x1U << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 9510 #define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk
lypinator 0:bb348c97df44 9511 #define RCC_CIR_PLLI2SRDYC_Pos (21U)
lypinator 0:bb348c97df44 9512 #define RCC_CIR_PLLI2SRDYC_Msk (0x1U << RCC_CIR_PLLI2SRDYC_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 9513 #define RCC_CIR_PLLI2SRDYC RCC_CIR_PLLI2SRDYC_Msk
lypinator 0:bb348c97df44 9514
lypinator 0:bb348c97df44 9515 #define RCC_CIR_CSSC_Pos (23U)
lypinator 0:bb348c97df44 9516 #define RCC_CIR_CSSC_Msk (0x1U << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */
lypinator 0:bb348c97df44 9517 #define RCC_CIR_CSSC RCC_CIR_CSSC_Msk
lypinator 0:bb348c97df44 9518
lypinator 0:bb348c97df44 9519 /******************** Bit definition for RCC_AHB1RSTR register **************/
lypinator 0:bb348c97df44 9520 #define RCC_AHB1RSTR_GPIOARST_Pos (0U)
lypinator 0:bb348c97df44 9521 #define RCC_AHB1RSTR_GPIOARST_Msk (0x1U << RCC_AHB1RSTR_GPIOARST_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 9522 #define RCC_AHB1RSTR_GPIOARST RCC_AHB1RSTR_GPIOARST_Msk
lypinator 0:bb348c97df44 9523 #define RCC_AHB1RSTR_GPIOBRST_Pos (1U)
lypinator 0:bb348c97df44 9524 #define RCC_AHB1RSTR_GPIOBRST_Msk (0x1U << RCC_AHB1RSTR_GPIOBRST_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 9525 #define RCC_AHB1RSTR_GPIOBRST RCC_AHB1RSTR_GPIOBRST_Msk
lypinator 0:bb348c97df44 9526 #define RCC_AHB1RSTR_GPIOCRST_Pos (2U)
lypinator 0:bb348c97df44 9527 #define RCC_AHB1RSTR_GPIOCRST_Msk (0x1U << RCC_AHB1RSTR_GPIOCRST_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 9528 #define RCC_AHB1RSTR_GPIOCRST RCC_AHB1RSTR_GPIOCRST_Msk
lypinator 0:bb348c97df44 9529 #define RCC_AHB1RSTR_GPIODRST_Pos (3U)
lypinator 0:bb348c97df44 9530 #define RCC_AHB1RSTR_GPIODRST_Msk (0x1U << RCC_AHB1RSTR_GPIODRST_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 9531 #define RCC_AHB1RSTR_GPIODRST RCC_AHB1RSTR_GPIODRST_Msk
lypinator 0:bb348c97df44 9532 #define RCC_AHB1RSTR_GPIOERST_Pos (4U)
lypinator 0:bb348c97df44 9533 #define RCC_AHB1RSTR_GPIOERST_Msk (0x1U << RCC_AHB1RSTR_GPIOERST_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 9534 #define RCC_AHB1RSTR_GPIOERST RCC_AHB1RSTR_GPIOERST_Msk
lypinator 0:bb348c97df44 9535 #define RCC_AHB1RSTR_GPIOFRST_Pos (5U)
lypinator 0:bb348c97df44 9536 #define RCC_AHB1RSTR_GPIOFRST_Msk (0x1U << RCC_AHB1RSTR_GPIOFRST_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 9537 #define RCC_AHB1RSTR_GPIOFRST RCC_AHB1RSTR_GPIOFRST_Msk
lypinator 0:bb348c97df44 9538 #define RCC_AHB1RSTR_GPIOGRST_Pos (6U)
lypinator 0:bb348c97df44 9539 #define RCC_AHB1RSTR_GPIOGRST_Msk (0x1U << RCC_AHB1RSTR_GPIOGRST_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 9540 #define RCC_AHB1RSTR_GPIOGRST RCC_AHB1RSTR_GPIOGRST_Msk
lypinator 0:bb348c97df44 9541 #define RCC_AHB1RSTR_GPIOHRST_Pos (7U)
lypinator 0:bb348c97df44 9542 #define RCC_AHB1RSTR_GPIOHRST_Msk (0x1U << RCC_AHB1RSTR_GPIOHRST_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 9543 #define RCC_AHB1RSTR_GPIOHRST RCC_AHB1RSTR_GPIOHRST_Msk
lypinator 0:bb348c97df44 9544 #define RCC_AHB1RSTR_CRCRST_Pos (12U)
lypinator 0:bb348c97df44 9545 #define RCC_AHB1RSTR_CRCRST_Msk (0x1U << RCC_AHB1RSTR_CRCRST_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 9546 #define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk
lypinator 0:bb348c97df44 9547 #define RCC_AHB1RSTR_DMA1RST_Pos (21U)
lypinator 0:bb348c97df44 9548 #define RCC_AHB1RSTR_DMA1RST_Msk (0x1U << RCC_AHB1RSTR_DMA1RST_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 9549 #define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk
lypinator 0:bb348c97df44 9550 #define RCC_AHB1RSTR_DMA2RST_Pos (22U)
lypinator 0:bb348c97df44 9551 #define RCC_AHB1RSTR_DMA2RST_Msk (0x1U << RCC_AHB1RSTR_DMA2RST_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 9552 #define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk
lypinator 0:bb348c97df44 9553
lypinator 0:bb348c97df44 9554 /******************** Bit definition for RCC_AHB2RSTR register **************/
lypinator 0:bb348c97df44 9555 #define RCC_AHB2RSTR_RNGRST_Pos (6U)
lypinator 0:bb348c97df44 9556 #define RCC_AHB2RSTR_RNGRST_Msk (0x1U << RCC_AHB2RSTR_RNGRST_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 9557 #define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk
lypinator 0:bb348c97df44 9558 #define RCC_AHB2RSTR_OTGFSRST_Pos (7U)
lypinator 0:bb348c97df44 9559 #define RCC_AHB2RSTR_OTGFSRST_Msk (0x1U << RCC_AHB2RSTR_OTGFSRST_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 9560 #define RCC_AHB2RSTR_OTGFSRST RCC_AHB2RSTR_OTGFSRST_Msk
lypinator 0:bb348c97df44 9561 /******************** Bit definition for RCC_AHB3RSTR register **************/
lypinator 0:bb348c97df44 9562 #define RCC_AHB3RSTR_FSMCRST_Pos (0U)
lypinator 0:bb348c97df44 9563 #define RCC_AHB3RSTR_FSMCRST_Msk (0x1U << RCC_AHB3RSTR_FSMCRST_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 9564 #define RCC_AHB3RSTR_FSMCRST RCC_AHB3RSTR_FSMCRST_Msk
lypinator 0:bb348c97df44 9565 #define RCC_AHB3RSTR_QSPIRST_Pos (1U)
lypinator 0:bb348c97df44 9566 #define RCC_AHB3RSTR_QSPIRST_Msk (0x1U << RCC_AHB3RSTR_QSPIRST_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 9567 #define RCC_AHB3RSTR_QSPIRST RCC_AHB3RSTR_QSPIRST_Msk
lypinator 0:bb348c97df44 9568
lypinator 0:bb348c97df44 9569
lypinator 0:bb348c97df44 9570 /******************** Bit definition for RCC_APB1RSTR register **************/
lypinator 0:bb348c97df44 9571 #define RCC_APB1RSTR_TIM2RST_Pos (0U)
lypinator 0:bb348c97df44 9572 #define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 9573 #define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk
lypinator 0:bb348c97df44 9574 #define RCC_APB1RSTR_TIM3RST_Pos (1U)
lypinator 0:bb348c97df44 9575 #define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 9576 #define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk
lypinator 0:bb348c97df44 9577 #define RCC_APB1RSTR_TIM4RST_Pos (2U)
lypinator 0:bb348c97df44 9578 #define RCC_APB1RSTR_TIM4RST_Msk (0x1U << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 9579 #define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk
lypinator 0:bb348c97df44 9580 #define RCC_APB1RSTR_TIM5RST_Pos (3U)
lypinator 0:bb348c97df44 9581 #define RCC_APB1RSTR_TIM5RST_Msk (0x1U << RCC_APB1RSTR_TIM5RST_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 9582 #define RCC_APB1RSTR_TIM5RST RCC_APB1RSTR_TIM5RST_Msk
lypinator 0:bb348c97df44 9583 #define RCC_APB1RSTR_TIM6RST_Pos (4U)
lypinator 0:bb348c97df44 9584 #define RCC_APB1RSTR_TIM6RST_Msk (0x1U << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 9585 #define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk
lypinator 0:bb348c97df44 9586 #define RCC_APB1RSTR_TIM7RST_Pos (5U)
lypinator 0:bb348c97df44 9587 #define RCC_APB1RSTR_TIM7RST_Msk (0x1U << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 9588 #define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk
lypinator 0:bb348c97df44 9589 #define RCC_APB1RSTR_TIM12RST_Pos (6U)
lypinator 0:bb348c97df44 9590 #define RCC_APB1RSTR_TIM12RST_Msk (0x1U << RCC_APB1RSTR_TIM12RST_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 9591 #define RCC_APB1RSTR_TIM12RST RCC_APB1RSTR_TIM12RST_Msk
lypinator 0:bb348c97df44 9592 #define RCC_APB1RSTR_TIM13RST_Pos (7U)
lypinator 0:bb348c97df44 9593 #define RCC_APB1RSTR_TIM13RST_Msk (0x1U << RCC_APB1RSTR_TIM13RST_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 9594 #define RCC_APB1RSTR_TIM13RST RCC_APB1RSTR_TIM13RST_Msk
lypinator 0:bb348c97df44 9595 #define RCC_APB1RSTR_TIM14RST_Pos (8U)
lypinator 0:bb348c97df44 9596 #define RCC_APB1RSTR_TIM14RST_Msk (0x1U << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 9597 #define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk
lypinator 0:bb348c97df44 9598 #define RCC_APB1RSTR_WWDGRST_Pos (11U)
lypinator 0:bb348c97df44 9599 #define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 9600 #define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk
lypinator 0:bb348c97df44 9601 #define RCC_APB1RSTR_SPI2RST_Pos (14U)
lypinator 0:bb348c97df44 9602 #define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 9603 #define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk
lypinator 0:bb348c97df44 9604 #define RCC_APB1RSTR_SPI3RST_Pos (15U)
lypinator 0:bb348c97df44 9605 #define RCC_APB1RSTR_SPI3RST_Msk (0x1U << RCC_APB1RSTR_SPI3RST_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 9606 #define RCC_APB1RSTR_SPI3RST RCC_APB1RSTR_SPI3RST_Msk
lypinator 0:bb348c97df44 9607 #define RCC_APB1RSTR_USART2RST_Pos (17U)
lypinator 0:bb348c97df44 9608 #define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 9609 #define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk
lypinator 0:bb348c97df44 9610 #define RCC_APB1RSTR_USART3RST_Pos (18U)
lypinator 0:bb348c97df44 9611 #define RCC_APB1RSTR_USART3RST_Msk (0x1U << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 9612 #define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk
lypinator 0:bb348c97df44 9613 #define RCC_APB1RSTR_I2C1RST_Pos (21U)
lypinator 0:bb348c97df44 9614 #define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 9615 #define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk
lypinator 0:bb348c97df44 9616 #define RCC_APB1RSTR_I2C2RST_Pos (22U)
lypinator 0:bb348c97df44 9617 #define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 9618 #define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk
lypinator 0:bb348c97df44 9619 #define RCC_APB1RSTR_I2C3RST_Pos (23U)
lypinator 0:bb348c97df44 9620 #define RCC_APB1RSTR_I2C3RST_Msk (0x1U << RCC_APB1RSTR_I2C3RST_Pos) /*!< 0x00800000 */
lypinator 0:bb348c97df44 9621 #define RCC_APB1RSTR_I2C3RST RCC_APB1RSTR_I2C3RST_Msk
lypinator 0:bb348c97df44 9622 #define RCC_APB1RSTR_FMPI2C1RST_Pos (24U)
lypinator 0:bb348c97df44 9623 #define RCC_APB1RSTR_FMPI2C1RST_Msk (0x1U << RCC_APB1RSTR_FMPI2C1RST_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 9624 #define RCC_APB1RSTR_FMPI2C1RST RCC_APB1RSTR_FMPI2C1RST_Msk
lypinator 0:bb348c97df44 9625 #define RCC_APB1RSTR_CAN1RST_Pos (25U)
lypinator 0:bb348c97df44 9626 #define RCC_APB1RSTR_CAN1RST_Msk (0x1U << RCC_APB1RSTR_CAN1RST_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 9627 #define RCC_APB1RSTR_CAN1RST RCC_APB1RSTR_CAN1RST_Msk
lypinator 0:bb348c97df44 9628 #define RCC_APB1RSTR_CAN2RST_Pos (26U)
lypinator 0:bb348c97df44 9629 #define RCC_APB1RSTR_CAN2RST_Msk (0x1U << RCC_APB1RSTR_CAN2RST_Pos) /*!< 0x04000000 */
lypinator 0:bb348c97df44 9630 #define RCC_APB1RSTR_CAN2RST RCC_APB1RSTR_CAN2RST_Msk
lypinator 0:bb348c97df44 9631 #define RCC_APB1RSTR_PWRRST_Pos (28U)
lypinator 0:bb348c97df44 9632 #define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
lypinator 0:bb348c97df44 9633 #define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk
lypinator 0:bb348c97df44 9634
lypinator 0:bb348c97df44 9635 /******************** Bit definition for RCC_APB2RSTR register **************/
lypinator 0:bb348c97df44 9636 #define RCC_APB2RSTR_TIM1RST_Pos (0U)
lypinator 0:bb348c97df44 9637 #define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 9638 #define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
lypinator 0:bb348c97df44 9639 #define RCC_APB2RSTR_TIM8RST_Pos (1U)
lypinator 0:bb348c97df44 9640 #define RCC_APB2RSTR_TIM8RST_Msk (0x1U << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 9641 #define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk
lypinator 0:bb348c97df44 9642 #define RCC_APB2RSTR_USART1RST_Pos (4U)
lypinator 0:bb348c97df44 9643 #define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 9644 #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
lypinator 0:bb348c97df44 9645 #define RCC_APB2RSTR_USART6RST_Pos (5U)
lypinator 0:bb348c97df44 9646 #define RCC_APB2RSTR_USART6RST_Msk (0x1U << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 9647 #define RCC_APB2RSTR_USART6RST RCC_APB2RSTR_USART6RST_Msk
lypinator 0:bb348c97df44 9648 #define RCC_APB2RSTR_ADCRST_Pos (8U)
lypinator 0:bb348c97df44 9649 #define RCC_APB2RSTR_ADCRST_Msk (0x1U << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 9650 #define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk
lypinator 0:bb348c97df44 9651 #define RCC_APB2RSTR_SDIORST_Pos (11U)
lypinator 0:bb348c97df44 9652 #define RCC_APB2RSTR_SDIORST_Msk (0x1U << RCC_APB2RSTR_SDIORST_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 9653 #define RCC_APB2RSTR_SDIORST RCC_APB2RSTR_SDIORST_Msk
lypinator 0:bb348c97df44 9654 #define RCC_APB2RSTR_SPI1RST_Pos (12U)
lypinator 0:bb348c97df44 9655 #define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 9656 #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
lypinator 0:bb348c97df44 9657 #define RCC_APB2RSTR_SPI4RST_Pos (13U)
lypinator 0:bb348c97df44 9658 #define RCC_APB2RSTR_SPI4RST_Msk (0x1U << RCC_APB2RSTR_SPI4RST_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 9659 #define RCC_APB2RSTR_SPI4RST RCC_APB2RSTR_SPI4RST_Msk
lypinator 0:bb348c97df44 9660 #define RCC_APB2RSTR_SYSCFGRST_Pos (14U)
lypinator 0:bb348c97df44 9661 #define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 9662 #define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk
lypinator 0:bb348c97df44 9663 #define RCC_APB2RSTR_TIM9RST_Pos (16U)
lypinator 0:bb348c97df44 9664 #define RCC_APB2RSTR_TIM9RST_Msk (0x1U << RCC_APB2RSTR_TIM9RST_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 9665 #define RCC_APB2RSTR_TIM9RST RCC_APB2RSTR_TIM9RST_Msk
lypinator 0:bb348c97df44 9666 #define RCC_APB2RSTR_TIM10RST_Pos (17U)
lypinator 0:bb348c97df44 9667 #define RCC_APB2RSTR_TIM10RST_Msk (0x1U << RCC_APB2RSTR_TIM10RST_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 9668 #define RCC_APB2RSTR_TIM10RST RCC_APB2RSTR_TIM10RST_Msk
lypinator 0:bb348c97df44 9669 #define RCC_APB2RSTR_TIM11RST_Pos (18U)
lypinator 0:bb348c97df44 9670 #define RCC_APB2RSTR_TIM11RST_Msk (0x1U << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 9671 #define RCC_APB2RSTR_TIM11RST RCC_APB2RSTR_TIM11RST_Msk
lypinator 0:bb348c97df44 9672 #define RCC_APB2RSTR_SPI5RST_Pos (20U)
lypinator 0:bb348c97df44 9673 #define RCC_APB2RSTR_SPI5RST_Msk (0x1U << RCC_APB2RSTR_SPI5RST_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 9674 #define RCC_APB2RSTR_SPI5RST RCC_APB2RSTR_SPI5RST_Msk
lypinator 0:bb348c97df44 9675 #define RCC_APB2RSTR_DFSDM1RST_Pos (24U)
lypinator 0:bb348c97df44 9676 #define RCC_APB2RSTR_DFSDM1RST_Msk (0x1U << RCC_APB2RSTR_DFSDM1RST_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 9677 #define RCC_APB2RSTR_DFSDM1RST RCC_APB2RSTR_DFSDM1RST_Msk
lypinator 0:bb348c97df44 9678
lypinator 0:bb348c97df44 9679 /******************** Bit definition for RCC_AHB1ENR register ***************/
lypinator 0:bb348c97df44 9680 #define RCC_AHB1ENR_GPIOAEN_Pos (0U)
lypinator 0:bb348c97df44 9681 #define RCC_AHB1ENR_GPIOAEN_Msk (0x1U << RCC_AHB1ENR_GPIOAEN_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 9682 #define RCC_AHB1ENR_GPIOAEN RCC_AHB1ENR_GPIOAEN_Msk
lypinator 0:bb348c97df44 9683 #define RCC_AHB1ENR_GPIOBEN_Pos (1U)
lypinator 0:bb348c97df44 9684 #define RCC_AHB1ENR_GPIOBEN_Msk (0x1U << RCC_AHB1ENR_GPIOBEN_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 9685 #define RCC_AHB1ENR_GPIOBEN RCC_AHB1ENR_GPIOBEN_Msk
lypinator 0:bb348c97df44 9686 #define RCC_AHB1ENR_GPIOCEN_Pos (2U)
lypinator 0:bb348c97df44 9687 #define RCC_AHB1ENR_GPIOCEN_Msk (0x1U << RCC_AHB1ENR_GPIOCEN_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 9688 #define RCC_AHB1ENR_GPIOCEN RCC_AHB1ENR_GPIOCEN_Msk
lypinator 0:bb348c97df44 9689 #define RCC_AHB1ENR_GPIODEN_Pos (3U)
lypinator 0:bb348c97df44 9690 #define RCC_AHB1ENR_GPIODEN_Msk (0x1U << RCC_AHB1ENR_GPIODEN_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 9691 #define RCC_AHB1ENR_GPIODEN RCC_AHB1ENR_GPIODEN_Msk
lypinator 0:bb348c97df44 9692 #define RCC_AHB1ENR_GPIOEEN_Pos (4U)
lypinator 0:bb348c97df44 9693 #define RCC_AHB1ENR_GPIOEEN_Msk (0x1U << RCC_AHB1ENR_GPIOEEN_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 9694 #define RCC_AHB1ENR_GPIOEEN RCC_AHB1ENR_GPIOEEN_Msk
lypinator 0:bb348c97df44 9695 #define RCC_AHB1ENR_GPIOFEN_Pos (5U)
lypinator 0:bb348c97df44 9696 #define RCC_AHB1ENR_GPIOFEN_Msk (0x1U << RCC_AHB1ENR_GPIOFEN_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 9697 #define RCC_AHB1ENR_GPIOFEN RCC_AHB1ENR_GPIOFEN_Msk
lypinator 0:bb348c97df44 9698 #define RCC_AHB1ENR_GPIOGEN_Pos (6U)
lypinator 0:bb348c97df44 9699 #define RCC_AHB1ENR_GPIOGEN_Msk (0x1U << RCC_AHB1ENR_GPIOGEN_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 9700 #define RCC_AHB1ENR_GPIOGEN RCC_AHB1ENR_GPIOGEN_Msk
lypinator 0:bb348c97df44 9701 #define RCC_AHB1ENR_GPIOHEN_Pos (7U)
lypinator 0:bb348c97df44 9702 #define RCC_AHB1ENR_GPIOHEN_Msk (0x1U << RCC_AHB1ENR_GPIOHEN_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 9703 #define RCC_AHB1ENR_GPIOHEN RCC_AHB1ENR_GPIOHEN_Msk
lypinator 0:bb348c97df44 9704 #define RCC_AHB1ENR_CRCEN_Pos (12U)
lypinator 0:bb348c97df44 9705 #define RCC_AHB1ENR_CRCEN_Msk (0x1U << RCC_AHB1ENR_CRCEN_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 9706 #define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk
lypinator 0:bb348c97df44 9707 #define RCC_AHB1ENR_DMA1EN_Pos (21U)
lypinator 0:bb348c97df44 9708 #define RCC_AHB1ENR_DMA1EN_Msk (0x1U << RCC_AHB1ENR_DMA1EN_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 9709 #define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk
lypinator 0:bb348c97df44 9710 #define RCC_AHB1ENR_DMA2EN_Pos (22U)
lypinator 0:bb348c97df44 9711 #define RCC_AHB1ENR_DMA2EN_Msk (0x1U << RCC_AHB1ENR_DMA2EN_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 9712 #define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk
lypinator 0:bb348c97df44 9713 /******************** Bit definition for RCC_AHB2ENR register ***************/
lypinator 0:bb348c97df44 9714 /*
lypinator 0:bb348c97df44 9715 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
lypinator 0:bb348c97df44 9716 */
lypinator 0:bb348c97df44 9717 #define RCC_AHB2_SUPPORT /*!< AHB2 Bus is supported */
lypinator 0:bb348c97df44 9718
lypinator 0:bb348c97df44 9719 #define RCC_AHB2ENR_RNGEN_Pos (6U)
lypinator 0:bb348c97df44 9720 #define RCC_AHB2ENR_RNGEN_Msk (0x1U << RCC_AHB2ENR_RNGEN_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 9721 #define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk
lypinator 0:bb348c97df44 9722 #define RCC_AHB2ENR_OTGFSEN_Pos (7U)
lypinator 0:bb348c97df44 9723 #define RCC_AHB2ENR_OTGFSEN_Msk (0x1U << RCC_AHB2ENR_OTGFSEN_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 9724 #define RCC_AHB2ENR_OTGFSEN RCC_AHB2ENR_OTGFSEN_Msk
lypinator 0:bb348c97df44 9725
lypinator 0:bb348c97df44 9726 /******************** Bit definition for RCC_AHB3ENR register ***************/
lypinator 0:bb348c97df44 9727 /*
lypinator 0:bb348c97df44 9728 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
lypinator 0:bb348c97df44 9729 */
lypinator 0:bb348c97df44 9730 #define RCC_AHB3_SUPPORT /*!< AHB3 Bus is supported */
lypinator 0:bb348c97df44 9731
lypinator 0:bb348c97df44 9732 #define RCC_AHB3ENR_FSMCEN_Pos (0U)
lypinator 0:bb348c97df44 9733 #define RCC_AHB3ENR_FSMCEN_Msk (0x1U << RCC_AHB3ENR_FSMCEN_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 9734 #define RCC_AHB3ENR_FSMCEN RCC_AHB3ENR_FSMCEN_Msk
lypinator 0:bb348c97df44 9735 #define RCC_AHB3ENR_QSPIEN_Pos (1U)
lypinator 0:bb348c97df44 9736 #define RCC_AHB3ENR_QSPIEN_Msk (0x1U << RCC_AHB3ENR_QSPIEN_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 9737 #define RCC_AHB3ENR_QSPIEN RCC_AHB3ENR_QSPIEN_Msk
lypinator 0:bb348c97df44 9738
lypinator 0:bb348c97df44 9739 /******************** Bit definition for RCC_APB1ENR register ***************/
lypinator 0:bb348c97df44 9740 #define RCC_APB1ENR_TIM2EN_Pos (0U)
lypinator 0:bb348c97df44 9741 #define RCC_APB1ENR_TIM2EN_Msk (0x1U << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 9742 #define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk
lypinator 0:bb348c97df44 9743 #define RCC_APB1ENR_TIM3EN_Pos (1U)
lypinator 0:bb348c97df44 9744 #define RCC_APB1ENR_TIM3EN_Msk (0x1U << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 9745 #define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk
lypinator 0:bb348c97df44 9746 #define RCC_APB1ENR_TIM4EN_Pos (2U)
lypinator 0:bb348c97df44 9747 #define RCC_APB1ENR_TIM4EN_Msk (0x1U << RCC_APB1ENR_TIM4EN_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 9748 #define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk
lypinator 0:bb348c97df44 9749 #define RCC_APB1ENR_TIM5EN_Pos (3U)
lypinator 0:bb348c97df44 9750 #define RCC_APB1ENR_TIM5EN_Msk (0x1U << RCC_APB1ENR_TIM5EN_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 9751 #define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk
lypinator 0:bb348c97df44 9752 #define RCC_APB1ENR_TIM6EN_Pos (4U)
lypinator 0:bb348c97df44 9753 #define RCC_APB1ENR_TIM6EN_Msk (0x1U << RCC_APB1ENR_TIM6EN_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 9754 #define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk
lypinator 0:bb348c97df44 9755 #define RCC_APB1ENR_TIM7EN_Pos (5U)
lypinator 0:bb348c97df44 9756 #define RCC_APB1ENR_TIM7EN_Msk (0x1U << RCC_APB1ENR_TIM7EN_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 9757 #define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk
lypinator 0:bb348c97df44 9758 #define RCC_APB1ENR_TIM12EN_Pos (6U)
lypinator 0:bb348c97df44 9759 #define RCC_APB1ENR_TIM12EN_Msk (0x1U << RCC_APB1ENR_TIM12EN_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 9760 #define RCC_APB1ENR_TIM12EN RCC_APB1ENR_TIM12EN_Msk
lypinator 0:bb348c97df44 9761 #define RCC_APB1ENR_TIM13EN_Pos (7U)
lypinator 0:bb348c97df44 9762 #define RCC_APB1ENR_TIM13EN_Msk (0x1U << RCC_APB1ENR_TIM13EN_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 9763 #define RCC_APB1ENR_TIM13EN RCC_APB1ENR_TIM13EN_Msk
lypinator 0:bb348c97df44 9764 #define RCC_APB1ENR_TIM14EN_Pos (8U)
lypinator 0:bb348c97df44 9765 #define RCC_APB1ENR_TIM14EN_Msk (0x1U << RCC_APB1ENR_TIM14EN_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 9766 #define RCC_APB1ENR_TIM14EN RCC_APB1ENR_TIM14EN_Msk
lypinator 0:bb348c97df44 9767 #define RCC_APB1ENR_RTCAPBEN_Pos (10U)
lypinator 0:bb348c97df44 9768 #define RCC_APB1ENR_RTCAPBEN_Msk (0x1U << RCC_APB1ENR_RTCAPBEN_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 9769 #define RCC_APB1ENR_RTCAPBEN RCC_APB1ENR_RTCAPBEN_Msk
lypinator 0:bb348c97df44 9770 #define RCC_APB1ENR_WWDGEN_Pos (11U)
lypinator 0:bb348c97df44 9771 #define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 9772 #define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk
lypinator 0:bb348c97df44 9773 #define RCC_APB1ENR_SPI2EN_Pos (14U)
lypinator 0:bb348c97df44 9774 #define RCC_APB1ENR_SPI2EN_Msk (0x1U << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 9775 #define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk
lypinator 0:bb348c97df44 9776 #define RCC_APB1ENR_SPI3EN_Pos (15U)
lypinator 0:bb348c97df44 9777 #define RCC_APB1ENR_SPI3EN_Msk (0x1U << RCC_APB1ENR_SPI3EN_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 9778 #define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk
lypinator 0:bb348c97df44 9779 #define RCC_APB1ENR_USART2EN_Pos (17U)
lypinator 0:bb348c97df44 9780 #define RCC_APB1ENR_USART2EN_Msk (0x1U << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 9781 #define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk
lypinator 0:bb348c97df44 9782 #define RCC_APB1ENR_USART3EN_Pos (18U)
lypinator 0:bb348c97df44 9783 #define RCC_APB1ENR_USART3EN_Msk (0x1U << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 9784 #define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk
lypinator 0:bb348c97df44 9785 #define RCC_APB1ENR_I2C1EN_Pos (21U)
lypinator 0:bb348c97df44 9786 #define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 9787 #define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk
lypinator 0:bb348c97df44 9788 #define RCC_APB1ENR_I2C2EN_Pos (22U)
lypinator 0:bb348c97df44 9789 #define RCC_APB1ENR_I2C2EN_Msk (0x1U << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 9790 #define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk
lypinator 0:bb348c97df44 9791 #define RCC_APB1ENR_I2C3EN_Pos (23U)
lypinator 0:bb348c97df44 9792 #define RCC_APB1ENR_I2C3EN_Msk (0x1U << RCC_APB1ENR_I2C3EN_Pos) /*!< 0x00800000 */
lypinator 0:bb348c97df44 9793 #define RCC_APB1ENR_I2C3EN RCC_APB1ENR_I2C3EN_Msk
lypinator 0:bb348c97df44 9794 #define RCC_APB1ENR_FMPI2C1EN_Pos (24U)
lypinator 0:bb348c97df44 9795 #define RCC_APB1ENR_FMPI2C1EN_Msk (0x1U << RCC_APB1ENR_FMPI2C1EN_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 9796 #define RCC_APB1ENR_FMPI2C1EN RCC_APB1ENR_FMPI2C1EN_Msk
lypinator 0:bb348c97df44 9797 #define RCC_APB1ENR_CAN1EN_Pos (25U)
lypinator 0:bb348c97df44 9798 #define RCC_APB1ENR_CAN1EN_Msk (0x1U << RCC_APB1ENR_CAN1EN_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 9799 #define RCC_APB1ENR_CAN1EN RCC_APB1ENR_CAN1EN_Msk
lypinator 0:bb348c97df44 9800 #define RCC_APB1ENR_CAN2EN_Pos (26U)
lypinator 0:bb348c97df44 9801 #define RCC_APB1ENR_CAN2EN_Msk (0x1U << RCC_APB1ENR_CAN2EN_Pos) /*!< 0x04000000 */
lypinator 0:bb348c97df44 9802 #define RCC_APB1ENR_CAN2EN RCC_APB1ENR_CAN2EN_Msk
lypinator 0:bb348c97df44 9803 #define RCC_APB1ENR_PWREN_Pos (28U)
lypinator 0:bb348c97df44 9804 #define RCC_APB1ENR_PWREN_Msk (0x1U << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
lypinator 0:bb348c97df44 9805 #define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk
lypinator 0:bb348c97df44 9806
lypinator 0:bb348c97df44 9807 /******************** Bit definition for RCC_APB2ENR register ***************/
lypinator 0:bb348c97df44 9808 #define RCC_APB2ENR_TIM1EN_Pos (0U)
lypinator 0:bb348c97df44 9809 #define RCC_APB2ENR_TIM1EN_Msk (0x1U << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 9810 #define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
lypinator 0:bb348c97df44 9811 #define RCC_APB2ENR_TIM8EN_Pos (1U)
lypinator 0:bb348c97df44 9812 #define RCC_APB2ENR_TIM8EN_Msk (0x1U << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 9813 #define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk
lypinator 0:bb348c97df44 9814 #define RCC_APB2ENR_USART1EN_Pos (4U)
lypinator 0:bb348c97df44 9815 #define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 9816 #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
lypinator 0:bb348c97df44 9817 #define RCC_APB2ENR_USART6EN_Pos (5U)
lypinator 0:bb348c97df44 9818 #define RCC_APB2ENR_USART6EN_Msk (0x1U << RCC_APB2ENR_USART6EN_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 9819 #define RCC_APB2ENR_USART6EN RCC_APB2ENR_USART6EN_Msk
lypinator 0:bb348c97df44 9820 #define RCC_APB2ENR_ADC1EN_Pos (8U)
lypinator 0:bb348c97df44 9821 #define RCC_APB2ENR_ADC1EN_Msk (0x1U << RCC_APB2ENR_ADC1EN_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 9822 #define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk
lypinator 0:bb348c97df44 9823 #define RCC_APB2ENR_SDIOEN_Pos (11U)
lypinator 0:bb348c97df44 9824 #define RCC_APB2ENR_SDIOEN_Msk (0x1U << RCC_APB2ENR_SDIOEN_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 9825 #define RCC_APB2ENR_SDIOEN RCC_APB2ENR_SDIOEN_Msk
lypinator 0:bb348c97df44 9826 #define RCC_APB2ENR_SPI1EN_Pos (12U)
lypinator 0:bb348c97df44 9827 #define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 9828 #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
lypinator 0:bb348c97df44 9829 #define RCC_APB2ENR_SPI4EN_Pos (13U)
lypinator 0:bb348c97df44 9830 #define RCC_APB2ENR_SPI4EN_Msk (0x1U << RCC_APB2ENR_SPI4EN_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 9831 #define RCC_APB2ENR_SPI4EN RCC_APB2ENR_SPI4EN_Msk
lypinator 0:bb348c97df44 9832 #define RCC_APB2ENR_SYSCFGEN_Pos (14U)
lypinator 0:bb348c97df44 9833 #define RCC_APB2ENR_SYSCFGEN_Msk (0x1U << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 9834 #define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk
lypinator 0:bb348c97df44 9835 #define RCC_APB2ENR_EXTITEN_Pos (15U)
lypinator 0:bb348c97df44 9836 #define RCC_APB2ENR_EXTITEN_Msk (0x1U << RCC_APB2ENR_EXTITEN_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 9837 #define RCC_APB2ENR_EXTITEN RCC_APB2ENR_EXTITEN_Msk
lypinator 0:bb348c97df44 9838 #define RCC_APB2ENR_TIM9EN_Pos (16U)
lypinator 0:bb348c97df44 9839 #define RCC_APB2ENR_TIM9EN_Msk (0x1U << RCC_APB2ENR_TIM9EN_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 9840 #define RCC_APB2ENR_TIM9EN RCC_APB2ENR_TIM9EN_Msk
lypinator 0:bb348c97df44 9841 #define RCC_APB2ENR_TIM10EN_Pos (17U)
lypinator 0:bb348c97df44 9842 #define RCC_APB2ENR_TIM10EN_Msk (0x1U << RCC_APB2ENR_TIM10EN_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 9843 #define RCC_APB2ENR_TIM10EN RCC_APB2ENR_TIM10EN_Msk
lypinator 0:bb348c97df44 9844 #define RCC_APB2ENR_TIM11EN_Pos (18U)
lypinator 0:bb348c97df44 9845 #define RCC_APB2ENR_TIM11EN_Msk (0x1U << RCC_APB2ENR_TIM11EN_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 9846 #define RCC_APB2ENR_TIM11EN RCC_APB2ENR_TIM11EN_Msk
lypinator 0:bb348c97df44 9847 #define RCC_APB2ENR_SPI5EN_Pos (20U)
lypinator 0:bb348c97df44 9848 #define RCC_APB2ENR_SPI5EN_Msk (0x1U << RCC_APB2ENR_SPI5EN_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 9849 #define RCC_APB2ENR_SPI5EN RCC_APB2ENR_SPI5EN_Msk
lypinator 0:bb348c97df44 9850 #define RCC_APB2ENR_DFSDM1EN_Pos (24U)
lypinator 0:bb348c97df44 9851 #define RCC_APB2ENR_DFSDM1EN_Msk (0x1U << RCC_APB2ENR_DFSDM1EN_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 9852 #define RCC_APB2ENR_DFSDM1EN RCC_APB2ENR_DFSDM1EN_Msk
lypinator 0:bb348c97df44 9853
lypinator 0:bb348c97df44 9854 /******************** Bit definition for RCC_AHB1LPENR register *************/
lypinator 0:bb348c97df44 9855 #define RCC_AHB1LPENR_GPIOALPEN_Pos (0U)
lypinator 0:bb348c97df44 9856 #define RCC_AHB1LPENR_GPIOALPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 9857 #define RCC_AHB1LPENR_GPIOALPEN RCC_AHB1LPENR_GPIOALPEN_Msk
lypinator 0:bb348c97df44 9858 #define RCC_AHB1LPENR_GPIOBLPEN_Pos (1U)
lypinator 0:bb348c97df44 9859 #define RCC_AHB1LPENR_GPIOBLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 9860 #define RCC_AHB1LPENR_GPIOBLPEN RCC_AHB1LPENR_GPIOBLPEN_Msk
lypinator 0:bb348c97df44 9861 #define RCC_AHB1LPENR_GPIOCLPEN_Pos (2U)
lypinator 0:bb348c97df44 9862 #define RCC_AHB1LPENR_GPIOCLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 9863 #define RCC_AHB1LPENR_GPIOCLPEN RCC_AHB1LPENR_GPIOCLPEN_Msk
lypinator 0:bb348c97df44 9864 #define RCC_AHB1LPENR_GPIODLPEN_Pos (3U)
lypinator 0:bb348c97df44 9865 #define RCC_AHB1LPENR_GPIODLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 9866 #define RCC_AHB1LPENR_GPIODLPEN RCC_AHB1LPENR_GPIODLPEN_Msk
lypinator 0:bb348c97df44 9867 #define RCC_AHB1LPENR_GPIOELPEN_Pos (4U)
lypinator 0:bb348c97df44 9868 #define RCC_AHB1LPENR_GPIOELPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 9869 #define RCC_AHB1LPENR_GPIOELPEN RCC_AHB1LPENR_GPIOELPEN_Msk
lypinator 0:bb348c97df44 9870 #define RCC_AHB1LPENR_GPIOFLPEN_Pos (5U)
lypinator 0:bb348c97df44 9871 #define RCC_AHB1LPENR_GPIOFLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOFLPEN_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 9872 #define RCC_AHB1LPENR_GPIOFLPEN RCC_AHB1LPENR_GPIOFLPEN_Msk
lypinator 0:bb348c97df44 9873 #define RCC_AHB1LPENR_GPIOGLPEN_Pos (6U)
lypinator 0:bb348c97df44 9874 #define RCC_AHB1LPENR_GPIOGLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOGLPEN_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 9875 #define RCC_AHB1LPENR_GPIOGLPEN RCC_AHB1LPENR_GPIOGLPEN_Msk
lypinator 0:bb348c97df44 9876 #define RCC_AHB1LPENR_GPIOHLPEN_Pos (7U)
lypinator 0:bb348c97df44 9877 #define RCC_AHB1LPENR_GPIOHLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 9878 #define RCC_AHB1LPENR_GPIOHLPEN RCC_AHB1LPENR_GPIOHLPEN_Msk
lypinator 0:bb348c97df44 9879 #define RCC_AHB1LPENR_CRCLPEN_Pos (12U)
lypinator 0:bb348c97df44 9880 #define RCC_AHB1LPENR_CRCLPEN_Msk (0x1U << RCC_AHB1LPENR_CRCLPEN_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 9881 #define RCC_AHB1LPENR_CRCLPEN RCC_AHB1LPENR_CRCLPEN_Msk
lypinator 0:bb348c97df44 9882 #define RCC_AHB1LPENR_FLITFLPEN_Pos (15U)
lypinator 0:bb348c97df44 9883 #define RCC_AHB1LPENR_FLITFLPEN_Msk (0x1U << RCC_AHB1LPENR_FLITFLPEN_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 9884 #define RCC_AHB1LPENR_FLITFLPEN RCC_AHB1LPENR_FLITFLPEN_Msk
lypinator 0:bb348c97df44 9885 #define RCC_AHB1LPENR_SRAM1LPEN_Pos (16U)
lypinator 0:bb348c97df44 9886 #define RCC_AHB1LPENR_SRAM1LPEN_Msk (0x1U << RCC_AHB1LPENR_SRAM1LPEN_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 9887 #define RCC_AHB1LPENR_SRAM1LPEN RCC_AHB1LPENR_SRAM1LPEN_Msk
lypinator 0:bb348c97df44 9888 #define RCC_AHB1LPENR_DMA1LPEN_Pos (21U)
lypinator 0:bb348c97df44 9889 #define RCC_AHB1LPENR_DMA1LPEN_Msk (0x1U << RCC_AHB1LPENR_DMA1LPEN_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 9890 #define RCC_AHB1LPENR_DMA1LPEN RCC_AHB1LPENR_DMA1LPEN_Msk
lypinator 0:bb348c97df44 9891 #define RCC_AHB1LPENR_DMA2LPEN_Pos (22U)
lypinator 0:bb348c97df44 9892 #define RCC_AHB1LPENR_DMA2LPEN_Msk (0x1U << RCC_AHB1LPENR_DMA2LPEN_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 9893 #define RCC_AHB1LPENR_DMA2LPEN RCC_AHB1LPENR_DMA2LPEN_Msk
lypinator 0:bb348c97df44 9894
lypinator 0:bb348c97df44 9895
lypinator 0:bb348c97df44 9896 /******************** Bit definition for RCC_AHB2LPENR register *************/
lypinator 0:bb348c97df44 9897 #define RCC_AHB2LPENR_RNGLPEN_Pos (6U)
lypinator 0:bb348c97df44 9898 #define RCC_AHB2LPENR_RNGLPEN_Msk (0x1U << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 9899 #define RCC_AHB2LPENR_RNGLPEN RCC_AHB2LPENR_RNGLPEN_Msk
lypinator 0:bb348c97df44 9900 #define RCC_AHB2LPENR_OTGFSLPEN_Pos (7U)
lypinator 0:bb348c97df44 9901 #define RCC_AHB2LPENR_OTGFSLPEN_Msk (0x1U << RCC_AHB2LPENR_OTGFSLPEN_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 9902 #define RCC_AHB2LPENR_OTGFSLPEN RCC_AHB2LPENR_OTGFSLPEN_Msk
lypinator 0:bb348c97df44 9903
lypinator 0:bb348c97df44 9904 /******************** Bit definition for RCC_AHB3LPENR register *************/
lypinator 0:bb348c97df44 9905 #define RCC_AHB3LPENR_FSMCLPEN_Pos (0U)
lypinator 0:bb348c97df44 9906 #define RCC_AHB3LPENR_FSMCLPEN_Msk (0x1U << RCC_AHB3LPENR_FSMCLPEN_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 9907 #define RCC_AHB3LPENR_FSMCLPEN RCC_AHB3LPENR_FSMCLPEN_Msk
lypinator 0:bb348c97df44 9908 #define RCC_AHB3LPENR_QSPILPEN_Pos (1U)
lypinator 0:bb348c97df44 9909 #define RCC_AHB3LPENR_QSPILPEN_Msk (0x1U << RCC_AHB3LPENR_QSPILPEN_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 9910 #define RCC_AHB3LPENR_QSPILPEN RCC_AHB3LPENR_QSPILPEN_Msk
lypinator 0:bb348c97df44 9911
lypinator 0:bb348c97df44 9912 /******************** Bit definition for RCC_APB1LPENR register *************/
lypinator 0:bb348c97df44 9913 #define RCC_APB1LPENR_TIM2LPEN_Pos (0U)
lypinator 0:bb348c97df44 9914 #define RCC_APB1LPENR_TIM2LPEN_Msk (0x1U << RCC_APB1LPENR_TIM2LPEN_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 9915 #define RCC_APB1LPENR_TIM2LPEN RCC_APB1LPENR_TIM2LPEN_Msk
lypinator 0:bb348c97df44 9916 #define RCC_APB1LPENR_TIM3LPEN_Pos (1U)
lypinator 0:bb348c97df44 9917 #define RCC_APB1LPENR_TIM3LPEN_Msk (0x1U << RCC_APB1LPENR_TIM3LPEN_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 9918 #define RCC_APB1LPENR_TIM3LPEN RCC_APB1LPENR_TIM3LPEN_Msk
lypinator 0:bb348c97df44 9919 #define RCC_APB1LPENR_TIM4LPEN_Pos (2U)
lypinator 0:bb348c97df44 9920 #define RCC_APB1LPENR_TIM4LPEN_Msk (0x1U << RCC_APB1LPENR_TIM4LPEN_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 9921 #define RCC_APB1LPENR_TIM4LPEN RCC_APB1LPENR_TIM4LPEN_Msk
lypinator 0:bb348c97df44 9922 #define RCC_APB1LPENR_TIM5LPEN_Pos (3U)
lypinator 0:bb348c97df44 9923 #define RCC_APB1LPENR_TIM5LPEN_Msk (0x1U << RCC_APB1LPENR_TIM5LPEN_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 9924 #define RCC_APB1LPENR_TIM5LPEN RCC_APB1LPENR_TIM5LPEN_Msk
lypinator 0:bb348c97df44 9925 #define RCC_APB1LPENR_TIM6LPEN_Pos (4U)
lypinator 0:bb348c97df44 9926 #define RCC_APB1LPENR_TIM6LPEN_Msk (0x1U << RCC_APB1LPENR_TIM6LPEN_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 9927 #define RCC_APB1LPENR_TIM6LPEN RCC_APB1LPENR_TIM6LPEN_Msk
lypinator 0:bb348c97df44 9928 #define RCC_APB1LPENR_TIM7LPEN_Pos (5U)
lypinator 0:bb348c97df44 9929 #define RCC_APB1LPENR_TIM7LPEN_Msk (0x1U << RCC_APB1LPENR_TIM7LPEN_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 9930 #define RCC_APB1LPENR_TIM7LPEN RCC_APB1LPENR_TIM7LPEN_Msk
lypinator 0:bb348c97df44 9931 #define RCC_APB1LPENR_TIM12LPEN_Pos (6U)
lypinator 0:bb348c97df44 9932 #define RCC_APB1LPENR_TIM12LPEN_Msk (0x1U << RCC_APB1LPENR_TIM12LPEN_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 9933 #define RCC_APB1LPENR_TIM12LPEN RCC_APB1LPENR_TIM12LPEN_Msk
lypinator 0:bb348c97df44 9934 #define RCC_APB1LPENR_TIM13LPEN_Pos (7U)
lypinator 0:bb348c97df44 9935 #define RCC_APB1LPENR_TIM13LPEN_Msk (0x1U << RCC_APB1LPENR_TIM13LPEN_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 9936 #define RCC_APB1LPENR_TIM13LPEN RCC_APB1LPENR_TIM13LPEN_Msk
lypinator 0:bb348c97df44 9937 #define RCC_APB1LPENR_TIM14LPEN_Pos (8U)
lypinator 0:bb348c97df44 9938 #define RCC_APB1LPENR_TIM14LPEN_Msk (0x1U << RCC_APB1LPENR_TIM14LPEN_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 9939 #define RCC_APB1LPENR_TIM14LPEN RCC_APB1LPENR_TIM14LPEN_Msk
lypinator 0:bb348c97df44 9940 #define RCC_APB1LPENR_RTCAPBLPEN_Pos (10U)
lypinator 0:bb348c97df44 9941 #define RCC_APB1LPENR_RTCAPBLPEN_Msk (0x1U << RCC_APB1LPENR_RTCAPBLPEN_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 9942 #define RCC_APB1LPENR_RTCAPBLPEN RCC_APB1LPENR_RTCAPBLPEN_Msk
lypinator 0:bb348c97df44 9943 #define RCC_APB1LPENR_WWDGLPEN_Pos (11U)
lypinator 0:bb348c97df44 9944 #define RCC_APB1LPENR_WWDGLPEN_Msk (0x1U << RCC_APB1LPENR_WWDGLPEN_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 9945 #define RCC_APB1LPENR_WWDGLPEN RCC_APB1LPENR_WWDGLPEN_Msk
lypinator 0:bb348c97df44 9946 #define RCC_APB1LPENR_SPI2LPEN_Pos (14U)
lypinator 0:bb348c97df44 9947 #define RCC_APB1LPENR_SPI2LPEN_Msk (0x1U << RCC_APB1LPENR_SPI2LPEN_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 9948 #define RCC_APB1LPENR_SPI2LPEN RCC_APB1LPENR_SPI2LPEN_Msk
lypinator 0:bb348c97df44 9949 #define RCC_APB1LPENR_SPI3LPEN_Pos (15U)
lypinator 0:bb348c97df44 9950 #define RCC_APB1LPENR_SPI3LPEN_Msk (0x1U << RCC_APB1LPENR_SPI3LPEN_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 9951 #define RCC_APB1LPENR_SPI3LPEN RCC_APB1LPENR_SPI3LPEN_Msk
lypinator 0:bb348c97df44 9952 #define RCC_APB1LPENR_USART2LPEN_Pos (17U)
lypinator 0:bb348c97df44 9953 #define RCC_APB1LPENR_USART2LPEN_Msk (0x1U << RCC_APB1LPENR_USART2LPEN_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 9954 #define RCC_APB1LPENR_USART2LPEN RCC_APB1LPENR_USART2LPEN_Msk
lypinator 0:bb348c97df44 9955 #define RCC_APB1LPENR_USART3LPEN_Pos (18U)
lypinator 0:bb348c97df44 9956 #define RCC_APB1LPENR_USART3LPEN_Msk (0x1U << RCC_APB1LPENR_USART3LPEN_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 9957 #define RCC_APB1LPENR_USART3LPEN RCC_APB1LPENR_USART3LPEN_Msk
lypinator 0:bb348c97df44 9958 #define RCC_APB1LPENR_I2C1LPEN_Pos (21U)
lypinator 0:bb348c97df44 9959 #define RCC_APB1LPENR_I2C1LPEN_Msk (0x1U << RCC_APB1LPENR_I2C1LPEN_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 9960 #define RCC_APB1LPENR_I2C1LPEN RCC_APB1LPENR_I2C1LPEN_Msk
lypinator 0:bb348c97df44 9961 #define RCC_APB1LPENR_I2C2LPEN_Pos (22U)
lypinator 0:bb348c97df44 9962 #define RCC_APB1LPENR_I2C2LPEN_Msk (0x1U << RCC_APB1LPENR_I2C2LPEN_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 9963 #define RCC_APB1LPENR_I2C2LPEN RCC_APB1LPENR_I2C2LPEN_Msk
lypinator 0:bb348c97df44 9964 #define RCC_APB1LPENR_I2C3LPEN_Pos (23U)
lypinator 0:bb348c97df44 9965 #define RCC_APB1LPENR_I2C3LPEN_Msk (0x1U << RCC_APB1LPENR_I2C3LPEN_Pos) /*!< 0x00800000 */
lypinator 0:bb348c97df44 9966 #define RCC_APB1LPENR_I2C3LPEN RCC_APB1LPENR_I2C3LPEN_Msk
lypinator 0:bb348c97df44 9967 #define RCC_APB1LPENR_FMPI2C1LPEN_Pos (24U)
lypinator 0:bb348c97df44 9968 #define RCC_APB1LPENR_FMPI2C1LPEN_Msk (0x1U << RCC_APB1LPENR_FMPI2C1LPEN_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 9969 #define RCC_APB1LPENR_FMPI2C1LPEN RCC_APB1LPENR_FMPI2C1LPEN_Msk
lypinator 0:bb348c97df44 9970 #define RCC_APB1LPENR_CAN1LPEN_Pos (25U)
lypinator 0:bb348c97df44 9971 #define RCC_APB1LPENR_CAN1LPEN_Msk (0x1U << RCC_APB1LPENR_CAN1LPEN_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 9972 #define RCC_APB1LPENR_CAN1LPEN RCC_APB1LPENR_CAN1LPEN_Msk
lypinator 0:bb348c97df44 9973 #define RCC_APB1LPENR_CAN2LPEN_Pos (26U)
lypinator 0:bb348c97df44 9974 #define RCC_APB1LPENR_CAN2LPEN_Msk (0x1U << RCC_APB1LPENR_CAN2LPEN_Pos) /*!< 0x04000000 */
lypinator 0:bb348c97df44 9975 #define RCC_APB1LPENR_CAN2LPEN RCC_APB1LPENR_CAN2LPEN_Msk
lypinator 0:bb348c97df44 9976 #define RCC_APB1LPENR_PWRLPEN_Pos (28U)
lypinator 0:bb348c97df44 9977 #define RCC_APB1LPENR_PWRLPEN_Msk (0x1U << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */
lypinator 0:bb348c97df44 9978 #define RCC_APB1LPENR_PWRLPEN RCC_APB1LPENR_PWRLPEN_Msk
lypinator 0:bb348c97df44 9979
lypinator 0:bb348c97df44 9980 /******************** Bit definition for RCC_APB2LPENR register *************/
lypinator 0:bb348c97df44 9981 #define RCC_APB2LPENR_TIM1LPEN_Pos (0U)
lypinator 0:bb348c97df44 9982 #define RCC_APB2LPENR_TIM1LPEN_Msk (0x1U << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 9983 #define RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk
lypinator 0:bb348c97df44 9984 #define RCC_APB2LPENR_TIM8LPEN_Pos (1U)
lypinator 0:bb348c97df44 9985 #define RCC_APB2LPENR_TIM8LPEN_Msk (0x1U << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 9986 #define RCC_APB2LPENR_TIM8LPEN RCC_APB2LPENR_TIM8LPEN_Msk
lypinator 0:bb348c97df44 9987 #define RCC_APB2LPENR_USART1LPEN_Pos (4U)
lypinator 0:bb348c97df44 9988 #define RCC_APB2LPENR_USART1LPEN_Msk (0x1U << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 9989 #define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk
lypinator 0:bb348c97df44 9990 #define RCC_APB2LPENR_USART6LPEN_Pos (5U)
lypinator 0:bb348c97df44 9991 #define RCC_APB2LPENR_USART6LPEN_Msk (0x1U << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 9992 #define RCC_APB2LPENR_USART6LPEN RCC_APB2LPENR_USART6LPEN_Msk
lypinator 0:bb348c97df44 9993 #define RCC_APB2LPENR_ADC1LPEN_Pos (8U)
lypinator 0:bb348c97df44 9994 #define RCC_APB2LPENR_ADC1LPEN_Msk (0x1U << RCC_APB2LPENR_ADC1LPEN_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 9995 #define RCC_APB2LPENR_ADC1LPEN RCC_APB2LPENR_ADC1LPEN_Msk
lypinator 0:bb348c97df44 9996 #define RCC_APB2LPENR_SDIOLPEN_Pos (11U)
lypinator 0:bb348c97df44 9997 #define RCC_APB2LPENR_SDIOLPEN_Msk (0x1U << RCC_APB2LPENR_SDIOLPEN_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 9998 #define RCC_APB2LPENR_SDIOLPEN RCC_APB2LPENR_SDIOLPEN_Msk
lypinator 0:bb348c97df44 9999 #define RCC_APB2LPENR_SPI1LPEN_Pos (12U)
lypinator 0:bb348c97df44 10000 #define RCC_APB2LPENR_SPI1LPEN_Msk (0x1U << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 10001 #define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk
lypinator 0:bb348c97df44 10002 #define RCC_APB2LPENR_SPI4LPEN_Pos (13U)
lypinator 0:bb348c97df44 10003 #define RCC_APB2LPENR_SPI4LPEN_Msk (0x1U << RCC_APB2LPENR_SPI4LPEN_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 10004 #define RCC_APB2LPENR_SPI4LPEN RCC_APB2LPENR_SPI4LPEN_Msk
lypinator 0:bb348c97df44 10005 #define RCC_APB2LPENR_SYSCFGLPEN_Pos (14U)
lypinator 0:bb348c97df44 10006 #define RCC_APB2LPENR_SYSCFGLPEN_Msk (0x1U << RCC_APB2LPENR_SYSCFGLPEN_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 10007 #define RCC_APB2LPENR_SYSCFGLPEN RCC_APB2LPENR_SYSCFGLPEN_Msk
lypinator 0:bb348c97df44 10008 #define RCC_APB2LPENR_EXTITLPEN_Pos (15U)
lypinator 0:bb348c97df44 10009 #define RCC_APB2LPENR_EXTITLPEN_Msk (0x1U << RCC_APB2LPENR_EXTITLPEN_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 10010 #define RCC_APB2LPENR_EXTITLPEN RCC_APB2LPENR_EXTITLPEN_Msk
lypinator 0:bb348c97df44 10011 #define RCC_APB2LPENR_TIM9LPEN_Pos (16U)
lypinator 0:bb348c97df44 10012 #define RCC_APB2LPENR_TIM9LPEN_Msk (0x1U << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 10013 #define RCC_APB2LPENR_TIM9LPEN RCC_APB2LPENR_TIM9LPEN_Msk
lypinator 0:bb348c97df44 10014 #define RCC_APB2LPENR_TIM10LPEN_Pos (17U)
lypinator 0:bb348c97df44 10015 #define RCC_APB2LPENR_TIM10LPEN_Msk (0x1U << RCC_APB2LPENR_TIM10LPEN_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 10016 #define RCC_APB2LPENR_TIM10LPEN RCC_APB2LPENR_TIM10LPEN_Msk
lypinator 0:bb348c97df44 10017 #define RCC_APB2LPENR_TIM11LPEN_Pos (18U)
lypinator 0:bb348c97df44 10018 #define RCC_APB2LPENR_TIM11LPEN_Msk (0x1U << RCC_APB2LPENR_TIM11LPEN_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 10019 #define RCC_APB2LPENR_TIM11LPEN RCC_APB2LPENR_TIM11LPEN_Msk
lypinator 0:bb348c97df44 10020 #define RCC_APB2LPENR_SPI5LPEN_Pos (20U)
lypinator 0:bb348c97df44 10021 #define RCC_APB2LPENR_SPI5LPEN_Msk (0x1U << RCC_APB2LPENR_SPI5LPEN_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 10022 #define RCC_APB2LPENR_SPI5LPEN RCC_APB2LPENR_SPI5LPEN_Msk
lypinator 0:bb348c97df44 10023 #define RCC_APB2LPENR_DFSDM1LPEN_Pos (24U)
lypinator 0:bb348c97df44 10024 #define RCC_APB2LPENR_DFSDM1LPEN_Msk (0x1U << RCC_APB2LPENR_DFSDM1LPEN_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 10025 #define RCC_APB2LPENR_DFSDM1LPEN RCC_APB2LPENR_DFSDM1LPEN_Msk
lypinator 0:bb348c97df44 10026
lypinator 0:bb348c97df44 10027 /******************** Bit definition for RCC_BDCR register ******************/
lypinator 0:bb348c97df44 10028 #define RCC_BDCR_LSEON_Pos (0U)
lypinator 0:bb348c97df44 10029 #define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 10030 #define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
lypinator 0:bb348c97df44 10031 #define RCC_BDCR_LSERDY_Pos (1U)
lypinator 0:bb348c97df44 10032 #define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 10033 #define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
lypinator 0:bb348c97df44 10034 #define RCC_BDCR_LSEBYP_Pos (2U)
lypinator 0:bb348c97df44 10035 #define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 10036 #define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
lypinator 0:bb348c97df44 10037 #define RCC_BDCR_LSEMOD_Pos (3U)
lypinator 0:bb348c97df44 10038 #define RCC_BDCR_LSEMOD_Msk (0x1U << RCC_BDCR_LSEMOD_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 10039 #define RCC_BDCR_LSEMOD RCC_BDCR_LSEMOD_Msk
lypinator 0:bb348c97df44 10040
lypinator 0:bb348c97df44 10041 #define RCC_BDCR_RTCSEL_Pos (8U)
lypinator 0:bb348c97df44 10042 #define RCC_BDCR_RTCSEL_Msk (0x3U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
lypinator 0:bb348c97df44 10043 #define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
lypinator 0:bb348c97df44 10044 #define RCC_BDCR_RTCSEL_0 (0x1U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 10045 #define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 10046
lypinator 0:bb348c97df44 10047 #define RCC_BDCR_RTCEN_Pos (15U)
lypinator 0:bb348c97df44 10048 #define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 10049 #define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
lypinator 0:bb348c97df44 10050 #define RCC_BDCR_BDRST_Pos (16U)
lypinator 0:bb348c97df44 10051 #define RCC_BDCR_BDRST_Msk (0x1U << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 10052 #define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
lypinator 0:bb348c97df44 10053
lypinator 0:bb348c97df44 10054 /******************** Bit definition for RCC_CSR register *******************/
lypinator 0:bb348c97df44 10055 #define RCC_CSR_LSION_Pos (0U)
lypinator 0:bb348c97df44 10056 #define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 10057 #define RCC_CSR_LSION RCC_CSR_LSION_Msk
lypinator 0:bb348c97df44 10058 #define RCC_CSR_LSIRDY_Pos (1U)
lypinator 0:bb348c97df44 10059 #define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 10060 #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
lypinator 0:bb348c97df44 10061 #define RCC_CSR_RMVF_Pos (24U)
lypinator 0:bb348c97df44 10062 #define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 10063 #define RCC_CSR_RMVF RCC_CSR_RMVF_Msk
lypinator 0:bb348c97df44 10064 #define RCC_CSR_PINRSTF_Pos (26U)
lypinator 0:bb348c97df44 10065 #define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
lypinator 0:bb348c97df44 10066 #define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk
lypinator 0:bb348c97df44 10067 #define RCC_CSR_PORRSTF_Pos (27U)
lypinator 0:bb348c97df44 10068 #define RCC_CSR_PORRSTF_Msk (0x1U << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
lypinator 0:bb348c97df44 10069 #define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk
lypinator 0:bb348c97df44 10070 #define RCC_CSR_SFTRSTF_Pos (28U)
lypinator 0:bb348c97df44 10071 #define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
lypinator 0:bb348c97df44 10072 #define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk
lypinator 0:bb348c97df44 10073 #define RCC_CSR_IWDGRSTF_Pos (29U)
lypinator 0:bb348c97df44 10074 #define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
lypinator 0:bb348c97df44 10075 #define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk
lypinator 0:bb348c97df44 10076 #define RCC_CSR_WWDGRSTF_Pos (30U)
lypinator 0:bb348c97df44 10077 #define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
lypinator 0:bb348c97df44 10078 #define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk
lypinator 0:bb348c97df44 10079 #define RCC_CSR_LPWRRSTF_Pos (31U)
lypinator 0:bb348c97df44 10080 #define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
lypinator 0:bb348c97df44 10081 #define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk
lypinator 0:bb348c97df44 10082 /* Legacy defines */
lypinator 0:bb348c97df44 10083 #define RCC_CSR_PADRSTF RCC_CSR_PINRSTF
lypinator 0:bb348c97df44 10084 #define RCC_CSR_WDGRSTF RCC_CSR_IWDGRSTF
lypinator 0:bb348c97df44 10085
lypinator 0:bb348c97df44 10086 /******************** Bit definition for RCC_SSCGR register *****************/
lypinator 0:bb348c97df44 10087 #define RCC_SSCGR_MODPER_Pos (0U)
lypinator 0:bb348c97df44 10088 #define RCC_SSCGR_MODPER_Msk (0x1FFFU << RCC_SSCGR_MODPER_Pos) /*!< 0x00001FFF */
lypinator 0:bb348c97df44 10089 #define RCC_SSCGR_MODPER RCC_SSCGR_MODPER_Msk
lypinator 0:bb348c97df44 10090 #define RCC_SSCGR_INCSTEP_Pos (13U)
lypinator 0:bb348c97df44 10091 #define RCC_SSCGR_INCSTEP_Msk (0x7FFFU << RCC_SSCGR_INCSTEP_Pos) /*!< 0x0FFFE000 */
lypinator 0:bb348c97df44 10092 #define RCC_SSCGR_INCSTEP RCC_SSCGR_INCSTEP_Msk
lypinator 0:bb348c97df44 10093 #define RCC_SSCGR_SPREADSEL_Pos (30U)
lypinator 0:bb348c97df44 10094 #define RCC_SSCGR_SPREADSEL_Msk (0x1U << RCC_SSCGR_SPREADSEL_Pos) /*!< 0x40000000 */
lypinator 0:bb348c97df44 10095 #define RCC_SSCGR_SPREADSEL RCC_SSCGR_SPREADSEL_Msk
lypinator 0:bb348c97df44 10096 #define RCC_SSCGR_SSCGEN_Pos (31U)
lypinator 0:bb348c97df44 10097 #define RCC_SSCGR_SSCGEN_Msk (0x1U << RCC_SSCGR_SSCGEN_Pos) /*!< 0x80000000 */
lypinator 0:bb348c97df44 10098 #define RCC_SSCGR_SSCGEN RCC_SSCGR_SSCGEN_Msk
lypinator 0:bb348c97df44 10099
lypinator 0:bb348c97df44 10100 /******************** Bit definition for RCC_PLLI2SCFGR register ************/
lypinator 0:bb348c97df44 10101 #define RCC_PLLI2SCFGR_PLLI2SM_Pos (0U)
lypinator 0:bb348c97df44 10102 #define RCC_PLLI2SCFGR_PLLI2SM_Msk (0x3FU << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x0000003F */
lypinator 0:bb348c97df44 10103 #define RCC_PLLI2SCFGR_PLLI2SM RCC_PLLI2SCFGR_PLLI2SM_Msk
lypinator 0:bb348c97df44 10104 #define RCC_PLLI2SCFGR_PLLI2SM_0 (0x01U << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 10105 #define RCC_PLLI2SCFGR_PLLI2SM_1 (0x02U << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 10106 #define RCC_PLLI2SCFGR_PLLI2SM_2 (0x04U << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 10107 #define RCC_PLLI2SCFGR_PLLI2SM_3 (0x08U << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 10108 #define RCC_PLLI2SCFGR_PLLI2SM_4 (0x10U << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 10109 #define RCC_PLLI2SCFGR_PLLI2SM_5 (0x20U << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 10110
lypinator 0:bb348c97df44 10111 #define RCC_PLLI2SCFGR_PLLI2SN_Pos (6U)
lypinator 0:bb348c97df44 10112 #define RCC_PLLI2SCFGR_PLLI2SN_Msk (0x1FFU << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00007FC0 */
lypinator 0:bb348c97df44 10113 #define RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN_Msk
lypinator 0:bb348c97df44 10114 #define RCC_PLLI2SCFGR_PLLI2SN_0 (0x001U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 10115 #define RCC_PLLI2SCFGR_PLLI2SN_1 (0x002U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 10116 #define RCC_PLLI2SCFGR_PLLI2SN_2 (0x004U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 10117 #define RCC_PLLI2SCFGR_PLLI2SN_3 (0x008U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 10118 #define RCC_PLLI2SCFGR_PLLI2SN_4 (0x010U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 10119 #define RCC_PLLI2SCFGR_PLLI2SN_5 (0x020U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 10120 #define RCC_PLLI2SCFGR_PLLI2SN_6 (0x040U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 10121 #define RCC_PLLI2SCFGR_PLLI2SN_7 (0x080U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 10122 #define RCC_PLLI2SCFGR_PLLI2SN_8 (0x100U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 10123
lypinator 0:bb348c97df44 10124 #define RCC_PLLI2SCFGR_PLLI2SSRC_Pos (22U)
lypinator 0:bb348c97df44 10125 #define RCC_PLLI2SCFGR_PLLI2SSRC_Msk (0x1U << RCC_PLLI2SCFGR_PLLI2SSRC_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 10126 #define RCC_PLLI2SCFGR_PLLI2SSRC RCC_PLLI2SCFGR_PLLI2SSRC_Msk
lypinator 0:bb348c97df44 10127 #define RCC_PLLI2SCFGR_PLLI2SQ_Pos (24U)
lypinator 0:bb348c97df44 10128 #define RCC_PLLI2SCFGR_PLLI2SQ_Msk (0xFU << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x0F000000 */
lypinator 0:bb348c97df44 10129 #define RCC_PLLI2SCFGR_PLLI2SQ RCC_PLLI2SCFGR_PLLI2SQ_Msk
lypinator 0:bb348c97df44 10130 #define RCC_PLLI2SCFGR_PLLI2SQ_0 (0x1U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 10131 #define RCC_PLLI2SCFGR_PLLI2SQ_1 (0x2U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 10132 #define RCC_PLLI2SCFGR_PLLI2SQ_2 (0x4U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x04000000 */
lypinator 0:bb348c97df44 10133 #define RCC_PLLI2SCFGR_PLLI2SQ_3 (0x8U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x08000000 */
lypinator 0:bb348c97df44 10134 #define RCC_PLLI2SCFGR_PLLI2SR_Pos (28U)
lypinator 0:bb348c97df44 10135 #define RCC_PLLI2SCFGR_PLLI2SR_Msk (0x7U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x70000000 */
lypinator 0:bb348c97df44 10136 #define RCC_PLLI2SCFGR_PLLI2SR RCC_PLLI2SCFGR_PLLI2SR_Msk
lypinator 0:bb348c97df44 10137 #define RCC_PLLI2SCFGR_PLLI2SR_0 (0x1U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x10000000 */
lypinator 0:bb348c97df44 10138 #define RCC_PLLI2SCFGR_PLLI2SR_1 (0x2U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x20000000 */
lypinator 0:bb348c97df44 10139 #define RCC_PLLI2SCFGR_PLLI2SR_2 (0x4U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x40000000 */
lypinator 0:bb348c97df44 10140
lypinator 0:bb348c97df44 10141 /******************** Bit definition for RCC_DCKCFGR register ***************/
lypinator 0:bb348c97df44 10142
lypinator 0:bb348c97df44 10143 #define RCC_DCKCFGR_CKDFSDM1ASEL_Pos (15U)
lypinator 0:bb348c97df44 10144 #define RCC_DCKCFGR_CKDFSDM1ASEL_Msk (0x1U << RCC_DCKCFGR_CKDFSDM1ASEL_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 10145 #define RCC_DCKCFGR_CKDFSDM1ASEL RCC_DCKCFGR_CKDFSDM1ASEL_Msk
lypinator 0:bb348c97df44 10146 #define RCC_DCKCFGR_TIMPRE_Pos (24U)
lypinator 0:bb348c97df44 10147 #define RCC_DCKCFGR_TIMPRE_Msk (0x1U << RCC_DCKCFGR_TIMPRE_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 10148 #define RCC_DCKCFGR_TIMPRE RCC_DCKCFGR_TIMPRE_Msk
lypinator 0:bb348c97df44 10149 #define RCC_DCKCFGR_I2S1SRC_Pos (25U)
lypinator 0:bb348c97df44 10150 #define RCC_DCKCFGR_I2S1SRC_Msk (0x3U << RCC_DCKCFGR_I2S1SRC_Pos) /*!< 0x06000000 */
lypinator 0:bb348c97df44 10151 #define RCC_DCKCFGR_I2S1SRC RCC_DCKCFGR_I2S1SRC_Msk
lypinator 0:bb348c97df44 10152 #define RCC_DCKCFGR_I2S1SRC_0 (0x1U << RCC_DCKCFGR_I2S1SRC_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 10153 #define RCC_DCKCFGR_I2S1SRC_1 (0x2U << RCC_DCKCFGR_I2S1SRC_Pos) /*!< 0x04000000 */
lypinator 0:bb348c97df44 10154
lypinator 0:bb348c97df44 10155 #define RCC_DCKCFGR_I2S2SRC_Pos (27U)
lypinator 0:bb348c97df44 10156 #define RCC_DCKCFGR_I2S2SRC_Msk (0x3U << RCC_DCKCFGR_I2S2SRC_Pos) /*!< 0x18000000 */
lypinator 0:bb348c97df44 10157 #define RCC_DCKCFGR_I2S2SRC RCC_DCKCFGR_I2S2SRC_Msk
lypinator 0:bb348c97df44 10158 #define RCC_DCKCFGR_I2S2SRC_0 (0x1U << RCC_DCKCFGR_I2S2SRC_Pos) /*!< 0x08000000 */
lypinator 0:bb348c97df44 10159 #define RCC_DCKCFGR_I2S2SRC_1 (0x2U << RCC_DCKCFGR_I2S2SRC_Pos) /*!< 0x10000000 */
lypinator 0:bb348c97df44 10160 #define RCC_DCKCFGR_CKDFSDM1SEL_Pos (31U)
lypinator 0:bb348c97df44 10161 #define RCC_DCKCFGR_CKDFSDM1SEL_Msk (0x1U << RCC_DCKCFGR_CKDFSDM1SEL_Pos) /*!< 0x80000000 */
lypinator 0:bb348c97df44 10162 #define RCC_DCKCFGR_CKDFSDM1SEL RCC_DCKCFGR_CKDFSDM1SEL_Msk
lypinator 0:bb348c97df44 10163
lypinator 0:bb348c97df44 10164 /******************** Bit definition for RCC_CKGATENR register ***************/
lypinator 0:bb348c97df44 10165 #define RCC_CKGATENR_AHB2APB1_CKEN_Pos (0U)
lypinator 0:bb348c97df44 10166 #define RCC_CKGATENR_AHB2APB1_CKEN_Msk (0x1U << RCC_CKGATENR_AHB2APB1_CKEN_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 10167 #define RCC_CKGATENR_AHB2APB1_CKEN RCC_CKGATENR_AHB2APB1_CKEN_Msk
lypinator 0:bb348c97df44 10168 #define RCC_CKGATENR_AHB2APB2_CKEN_Pos (1U)
lypinator 0:bb348c97df44 10169 #define RCC_CKGATENR_AHB2APB2_CKEN_Msk (0x1U << RCC_CKGATENR_AHB2APB2_CKEN_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 10170 #define RCC_CKGATENR_AHB2APB2_CKEN RCC_CKGATENR_AHB2APB2_CKEN_Msk
lypinator 0:bb348c97df44 10171 #define RCC_CKGATENR_CM4DBG_CKEN_Pos (2U)
lypinator 0:bb348c97df44 10172 #define RCC_CKGATENR_CM4DBG_CKEN_Msk (0x1U << RCC_CKGATENR_CM4DBG_CKEN_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 10173 #define RCC_CKGATENR_CM4DBG_CKEN RCC_CKGATENR_CM4DBG_CKEN_Msk
lypinator 0:bb348c97df44 10174 #define RCC_CKGATENR_SPARE_CKEN_Pos (3U)
lypinator 0:bb348c97df44 10175 #define RCC_CKGATENR_SPARE_CKEN_Msk (0x1U << RCC_CKGATENR_SPARE_CKEN_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 10176 #define RCC_CKGATENR_SPARE_CKEN RCC_CKGATENR_SPARE_CKEN_Msk
lypinator 0:bb348c97df44 10177 #define RCC_CKGATENR_SRAM_CKEN_Pos (4U)
lypinator 0:bb348c97df44 10178 #define RCC_CKGATENR_SRAM_CKEN_Msk (0x1U << RCC_CKGATENR_SRAM_CKEN_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 10179 #define RCC_CKGATENR_SRAM_CKEN RCC_CKGATENR_SRAM_CKEN_Msk
lypinator 0:bb348c97df44 10180 #define RCC_CKGATENR_FLITF_CKEN_Pos (5U)
lypinator 0:bb348c97df44 10181 #define RCC_CKGATENR_FLITF_CKEN_Msk (0x1U << RCC_CKGATENR_FLITF_CKEN_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 10182 #define RCC_CKGATENR_FLITF_CKEN RCC_CKGATENR_FLITF_CKEN_Msk
lypinator 0:bb348c97df44 10183 #define RCC_CKGATENR_RCC_CKEN_Pos (6U)
lypinator 0:bb348c97df44 10184 #define RCC_CKGATENR_RCC_CKEN_Msk (0x1U << RCC_CKGATENR_RCC_CKEN_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 10185 #define RCC_CKGATENR_RCC_CKEN RCC_CKGATENR_RCC_CKEN_Msk
lypinator 0:bb348c97df44 10186 #define RCC_CKGATENR_RCC_EVTCTL_Pos (7U)
lypinator 0:bb348c97df44 10187 #define RCC_CKGATENR_RCC_EVTCTL_Msk (0x1U << RCC_CKGATENR_RCC_EVTCTL_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 10188 #define RCC_CKGATENR_RCC_EVTCTL RCC_CKGATENR_RCC_EVTCTL_Msk
lypinator 0:bb348c97df44 10189
lypinator 0:bb348c97df44 10190 /******************** Bit definition for RCC_DCKCFGR2 register ***************/
lypinator 0:bb348c97df44 10191 #define RCC_DCKCFGR2_FMPI2C1SEL_Pos (22U)
lypinator 0:bb348c97df44 10192 #define RCC_DCKCFGR2_FMPI2C1SEL_Msk (0x3U << RCC_DCKCFGR2_FMPI2C1SEL_Pos) /*!< 0x00C00000 */
lypinator 0:bb348c97df44 10193 #define RCC_DCKCFGR2_FMPI2C1SEL RCC_DCKCFGR2_FMPI2C1SEL_Msk
lypinator 0:bb348c97df44 10194 #define RCC_DCKCFGR2_FMPI2C1SEL_0 (0x1U << RCC_DCKCFGR2_FMPI2C1SEL_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 10195 #define RCC_DCKCFGR2_FMPI2C1SEL_1 (0x2U << RCC_DCKCFGR2_FMPI2C1SEL_Pos) /*!< 0x00800000 */
lypinator 0:bb348c97df44 10196 #define RCC_DCKCFGR2_CK48MSEL_Pos (27U)
lypinator 0:bb348c97df44 10197 #define RCC_DCKCFGR2_CK48MSEL_Msk (0x1U << RCC_DCKCFGR2_CK48MSEL_Pos) /*!< 0x08000000 */
lypinator 0:bb348c97df44 10198 #define RCC_DCKCFGR2_CK48MSEL RCC_DCKCFGR2_CK48MSEL_Msk
lypinator 0:bb348c97df44 10199 #define RCC_DCKCFGR2_SDIOSEL_Pos (28U)
lypinator 0:bb348c97df44 10200 #define RCC_DCKCFGR2_SDIOSEL_Msk (0x1U << RCC_DCKCFGR2_SDIOSEL_Pos) /*!< 0x10000000 */
lypinator 0:bb348c97df44 10201 #define RCC_DCKCFGR2_SDIOSEL RCC_DCKCFGR2_SDIOSEL_Msk
lypinator 0:bb348c97df44 10202
lypinator 0:bb348c97df44 10203
lypinator 0:bb348c97df44 10204 /******************************************************************************/
lypinator 0:bb348c97df44 10205 /* */
lypinator 0:bb348c97df44 10206 /* RNG */
lypinator 0:bb348c97df44 10207 /* */
lypinator 0:bb348c97df44 10208 /******************************************************************************/
lypinator 0:bb348c97df44 10209 /******************** Bits definition for RNG_CR register *******************/
lypinator 0:bb348c97df44 10210 #define RNG_CR_RNGEN_Pos (2U)
lypinator 0:bb348c97df44 10211 #define RNG_CR_RNGEN_Msk (0x1U << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 10212 #define RNG_CR_RNGEN RNG_CR_RNGEN_Msk
lypinator 0:bb348c97df44 10213 #define RNG_CR_IE_Pos (3U)
lypinator 0:bb348c97df44 10214 #define RNG_CR_IE_Msk (0x1U << RNG_CR_IE_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 10215 #define RNG_CR_IE RNG_CR_IE_Msk
lypinator 0:bb348c97df44 10216
lypinator 0:bb348c97df44 10217 /******************** Bits definition for RNG_SR register *******************/
lypinator 0:bb348c97df44 10218 #define RNG_SR_DRDY_Pos (0U)
lypinator 0:bb348c97df44 10219 #define RNG_SR_DRDY_Msk (0x1U << RNG_SR_DRDY_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 10220 #define RNG_SR_DRDY RNG_SR_DRDY_Msk
lypinator 0:bb348c97df44 10221 #define RNG_SR_CECS_Pos (1U)
lypinator 0:bb348c97df44 10222 #define RNG_SR_CECS_Msk (0x1U << RNG_SR_CECS_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 10223 #define RNG_SR_CECS RNG_SR_CECS_Msk
lypinator 0:bb348c97df44 10224 #define RNG_SR_SECS_Pos (2U)
lypinator 0:bb348c97df44 10225 #define RNG_SR_SECS_Msk (0x1U << RNG_SR_SECS_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 10226 #define RNG_SR_SECS RNG_SR_SECS_Msk
lypinator 0:bb348c97df44 10227 #define RNG_SR_CEIS_Pos (5U)
lypinator 0:bb348c97df44 10228 #define RNG_SR_CEIS_Msk (0x1U << RNG_SR_CEIS_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 10229 #define RNG_SR_CEIS RNG_SR_CEIS_Msk
lypinator 0:bb348c97df44 10230 #define RNG_SR_SEIS_Pos (6U)
lypinator 0:bb348c97df44 10231 #define RNG_SR_SEIS_Msk (0x1U << RNG_SR_SEIS_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 10232 #define RNG_SR_SEIS RNG_SR_SEIS_Msk
lypinator 0:bb348c97df44 10233
lypinator 0:bb348c97df44 10234 /******************************************************************************/
lypinator 0:bb348c97df44 10235 /* */
lypinator 0:bb348c97df44 10236 /* Real-Time Clock (RTC) */
lypinator 0:bb348c97df44 10237 /* */
lypinator 0:bb348c97df44 10238 /******************************************************************************/
lypinator 0:bb348c97df44 10239 /******************** Bits definition for RTC_TR register *******************/
lypinator 0:bb348c97df44 10240 #define RTC_TR_PM_Pos (22U)
lypinator 0:bb348c97df44 10241 #define RTC_TR_PM_Msk (0x1U << RTC_TR_PM_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 10242 #define RTC_TR_PM RTC_TR_PM_Msk
lypinator 0:bb348c97df44 10243 #define RTC_TR_HT_Pos (20U)
lypinator 0:bb348c97df44 10244 #define RTC_TR_HT_Msk (0x3U << RTC_TR_HT_Pos) /*!< 0x00300000 */
lypinator 0:bb348c97df44 10245 #define RTC_TR_HT RTC_TR_HT_Msk
lypinator 0:bb348c97df44 10246 #define RTC_TR_HT_0 (0x1U << RTC_TR_HT_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 10247 #define RTC_TR_HT_1 (0x2U << RTC_TR_HT_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 10248 #define RTC_TR_HU_Pos (16U)
lypinator 0:bb348c97df44 10249 #define RTC_TR_HU_Msk (0xFU << RTC_TR_HU_Pos) /*!< 0x000F0000 */
lypinator 0:bb348c97df44 10250 #define RTC_TR_HU RTC_TR_HU_Msk
lypinator 0:bb348c97df44 10251 #define RTC_TR_HU_0 (0x1U << RTC_TR_HU_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 10252 #define RTC_TR_HU_1 (0x2U << RTC_TR_HU_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 10253 #define RTC_TR_HU_2 (0x4U << RTC_TR_HU_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 10254 #define RTC_TR_HU_3 (0x8U << RTC_TR_HU_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 10255 #define RTC_TR_MNT_Pos (12U)
lypinator 0:bb348c97df44 10256 #define RTC_TR_MNT_Msk (0x7U << RTC_TR_MNT_Pos) /*!< 0x00007000 */
lypinator 0:bb348c97df44 10257 #define RTC_TR_MNT RTC_TR_MNT_Msk
lypinator 0:bb348c97df44 10258 #define RTC_TR_MNT_0 (0x1U << RTC_TR_MNT_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 10259 #define RTC_TR_MNT_1 (0x2U << RTC_TR_MNT_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 10260 #define RTC_TR_MNT_2 (0x4U << RTC_TR_MNT_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 10261 #define RTC_TR_MNU_Pos (8U)
lypinator 0:bb348c97df44 10262 #define RTC_TR_MNU_Msk (0xFU << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
lypinator 0:bb348c97df44 10263 #define RTC_TR_MNU RTC_TR_MNU_Msk
lypinator 0:bb348c97df44 10264 #define RTC_TR_MNU_0 (0x1U << RTC_TR_MNU_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 10265 #define RTC_TR_MNU_1 (0x2U << RTC_TR_MNU_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 10266 #define RTC_TR_MNU_2 (0x4U << RTC_TR_MNU_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 10267 #define RTC_TR_MNU_3 (0x8U << RTC_TR_MNU_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 10268 #define RTC_TR_ST_Pos (4U)
lypinator 0:bb348c97df44 10269 #define RTC_TR_ST_Msk (0x7U << RTC_TR_ST_Pos) /*!< 0x00000070 */
lypinator 0:bb348c97df44 10270 #define RTC_TR_ST RTC_TR_ST_Msk
lypinator 0:bb348c97df44 10271 #define RTC_TR_ST_0 (0x1U << RTC_TR_ST_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 10272 #define RTC_TR_ST_1 (0x2U << RTC_TR_ST_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 10273 #define RTC_TR_ST_2 (0x4U << RTC_TR_ST_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 10274 #define RTC_TR_SU_Pos (0U)
lypinator 0:bb348c97df44 10275 #define RTC_TR_SU_Msk (0xFU << RTC_TR_SU_Pos) /*!< 0x0000000F */
lypinator 0:bb348c97df44 10276 #define RTC_TR_SU RTC_TR_SU_Msk
lypinator 0:bb348c97df44 10277 #define RTC_TR_SU_0 (0x1U << RTC_TR_SU_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 10278 #define RTC_TR_SU_1 (0x2U << RTC_TR_SU_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 10279 #define RTC_TR_SU_2 (0x4U << RTC_TR_SU_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 10280 #define RTC_TR_SU_3 (0x8U << RTC_TR_SU_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 10281
lypinator 0:bb348c97df44 10282 /******************** Bits definition for RTC_DR register *******************/
lypinator 0:bb348c97df44 10283 #define RTC_DR_YT_Pos (20U)
lypinator 0:bb348c97df44 10284 #define RTC_DR_YT_Msk (0xFU << RTC_DR_YT_Pos) /*!< 0x00F00000 */
lypinator 0:bb348c97df44 10285 #define RTC_DR_YT RTC_DR_YT_Msk
lypinator 0:bb348c97df44 10286 #define RTC_DR_YT_0 (0x1U << RTC_DR_YT_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 10287 #define RTC_DR_YT_1 (0x2U << RTC_DR_YT_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 10288 #define RTC_DR_YT_2 (0x4U << RTC_DR_YT_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 10289 #define RTC_DR_YT_3 (0x8U << RTC_DR_YT_Pos) /*!< 0x00800000 */
lypinator 0:bb348c97df44 10290 #define RTC_DR_YU_Pos (16U)
lypinator 0:bb348c97df44 10291 #define RTC_DR_YU_Msk (0xFU << RTC_DR_YU_Pos) /*!< 0x000F0000 */
lypinator 0:bb348c97df44 10292 #define RTC_DR_YU RTC_DR_YU_Msk
lypinator 0:bb348c97df44 10293 #define RTC_DR_YU_0 (0x1U << RTC_DR_YU_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 10294 #define RTC_DR_YU_1 (0x2U << RTC_DR_YU_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 10295 #define RTC_DR_YU_2 (0x4U << RTC_DR_YU_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 10296 #define RTC_DR_YU_3 (0x8U << RTC_DR_YU_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 10297 #define RTC_DR_WDU_Pos (13U)
lypinator 0:bb348c97df44 10298 #define RTC_DR_WDU_Msk (0x7U << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
lypinator 0:bb348c97df44 10299 #define RTC_DR_WDU RTC_DR_WDU_Msk
lypinator 0:bb348c97df44 10300 #define RTC_DR_WDU_0 (0x1U << RTC_DR_WDU_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 10301 #define RTC_DR_WDU_1 (0x2U << RTC_DR_WDU_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 10302 #define RTC_DR_WDU_2 (0x4U << RTC_DR_WDU_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 10303 #define RTC_DR_MT_Pos (12U)
lypinator 0:bb348c97df44 10304 #define RTC_DR_MT_Msk (0x1U << RTC_DR_MT_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 10305 #define RTC_DR_MT RTC_DR_MT_Msk
lypinator 0:bb348c97df44 10306 #define RTC_DR_MU_Pos (8U)
lypinator 0:bb348c97df44 10307 #define RTC_DR_MU_Msk (0xFU << RTC_DR_MU_Pos) /*!< 0x00000F00 */
lypinator 0:bb348c97df44 10308 #define RTC_DR_MU RTC_DR_MU_Msk
lypinator 0:bb348c97df44 10309 #define RTC_DR_MU_0 (0x1U << RTC_DR_MU_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 10310 #define RTC_DR_MU_1 (0x2U << RTC_DR_MU_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 10311 #define RTC_DR_MU_2 (0x4U << RTC_DR_MU_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 10312 #define RTC_DR_MU_3 (0x8U << RTC_DR_MU_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 10313 #define RTC_DR_DT_Pos (4U)
lypinator 0:bb348c97df44 10314 #define RTC_DR_DT_Msk (0x3U << RTC_DR_DT_Pos) /*!< 0x00000030 */
lypinator 0:bb348c97df44 10315 #define RTC_DR_DT RTC_DR_DT_Msk
lypinator 0:bb348c97df44 10316 #define RTC_DR_DT_0 (0x1U << RTC_DR_DT_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 10317 #define RTC_DR_DT_1 (0x2U << RTC_DR_DT_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 10318 #define RTC_DR_DU_Pos (0U)
lypinator 0:bb348c97df44 10319 #define RTC_DR_DU_Msk (0xFU << RTC_DR_DU_Pos) /*!< 0x0000000F */
lypinator 0:bb348c97df44 10320 #define RTC_DR_DU RTC_DR_DU_Msk
lypinator 0:bb348c97df44 10321 #define RTC_DR_DU_0 (0x1U << RTC_DR_DU_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 10322 #define RTC_DR_DU_1 (0x2U << RTC_DR_DU_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 10323 #define RTC_DR_DU_2 (0x4U << RTC_DR_DU_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 10324 #define RTC_DR_DU_3 (0x8U << RTC_DR_DU_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 10325
lypinator 0:bb348c97df44 10326 /******************** Bits definition for RTC_CR register *******************/
lypinator 0:bb348c97df44 10327 #define RTC_CR_COE_Pos (23U)
lypinator 0:bb348c97df44 10328 #define RTC_CR_COE_Msk (0x1U << RTC_CR_COE_Pos) /*!< 0x00800000 */
lypinator 0:bb348c97df44 10329 #define RTC_CR_COE RTC_CR_COE_Msk
lypinator 0:bb348c97df44 10330 #define RTC_CR_OSEL_Pos (21U)
lypinator 0:bb348c97df44 10331 #define RTC_CR_OSEL_Msk (0x3U << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
lypinator 0:bb348c97df44 10332 #define RTC_CR_OSEL RTC_CR_OSEL_Msk
lypinator 0:bb348c97df44 10333 #define RTC_CR_OSEL_0 (0x1U << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 10334 #define RTC_CR_OSEL_1 (0x2U << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 10335 #define RTC_CR_POL_Pos (20U)
lypinator 0:bb348c97df44 10336 #define RTC_CR_POL_Msk (0x1U << RTC_CR_POL_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 10337 #define RTC_CR_POL RTC_CR_POL_Msk
lypinator 0:bb348c97df44 10338 #define RTC_CR_COSEL_Pos (19U)
lypinator 0:bb348c97df44 10339 #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 10340 #define RTC_CR_COSEL RTC_CR_COSEL_Msk
lypinator 0:bb348c97df44 10341 #define RTC_CR_BKP_Pos (18U)
lypinator 0:bb348c97df44 10342 #define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 10343 #define RTC_CR_BKP RTC_CR_BKP_Msk
lypinator 0:bb348c97df44 10344 #define RTC_CR_SUB1H_Pos (17U)
lypinator 0:bb348c97df44 10345 #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 10346 #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
lypinator 0:bb348c97df44 10347 #define RTC_CR_ADD1H_Pos (16U)
lypinator 0:bb348c97df44 10348 #define RTC_CR_ADD1H_Msk (0x1U << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 10349 #define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
lypinator 0:bb348c97df44 10350 #define RTC_CR_TSIE_Pos (15U)
lypinator 0:bb348c97df44 10351 #define RTC_CR_TSIE_Msk (0x1U << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 10352 #define RTC_CR_TSIE RTC_CR_TSIE_Msk
lypinator 0:bb348c97df44 10353 #define RTC_CR_WUTIE_Pos (14U)
lypinator 0:bb348c97df44 10354 #define RTC_CR_WUTIE_Msk (0x1U << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 10355 #define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
lypinator 0:bb348c97df44 10356 #define RTC_CR_ALRBIE_Pos (13U)
lypinator 0:bb348c97df44 10357 #define RTC_CR_ALRBIE_Msk (0x1U << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 10358 #define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
lypinator 0:bb348c97df44 10359 #define RTC_CR_ALRAIE_Pos (12U)
lypinator 0:bb348c97df44 10360 #define RTC_CR_ALRAIE_Msk (0x1U << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 10361 #define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
lypinator 0:bb348c97df44 10362 #define RTC_CR_TSE_Pos (11U)
lypinator 0:bb348c97df44 10363 #define RTC_CR_TSE_Msk (0x1U << RTC_CR_TSE_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 10364 #define RTC_CR_TSE RTC_CR_TSE_Msk
lypinator 0:bb348c97df44 10365 #define RTC_CR_WUTE_Pos (10U)
lypinator 0:bb348c97df44 10366 #define RTC_CR_WUTE_Msk (0x1U << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 10367 #define RTC_CR_WUTE RTC_CR_WUTE_Msk
lypinator 0:bb348c97df44 10368 #define RTC_CR_ALRBE_Pos (9U)
lypinator 0:bb348c97df44 10369 #define RTC_CR_ALRBE_Msk (0x1U << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 10370 #define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
lypinator 0:bb348c97df44 10371 #define RTC_CR_ALRAE_Pos (8U)
lypinator 0:bb348c97df44 10372 #define RTC_CR_ALRAE_Msk (0x1U << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 10373 #define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
lypinator 0:bb348c97df44 10374 #define RTC_CR_DCE_Pos (7U)
lypinator 0:bb348c97df44 10375 #define RTC_CR_DCE_Msk (0x1U << RTC_CR_DCE_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 10376 #define RTC_CR_DCE RTC_CR_DCE_Msk
lypinator 0:bb348c97df44 10377 #define RTC_CR_FMT_Pos (6U)
lypinator 0:bb348c97df44 10378 #define RTC_CR_FMT_Msk (0x1U << RTC_CR_FMT_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 10379 #define RTC_CR_FMT RTC_CR_FMT_Msk
lypinator 0:bb348c97df44 10380 #define RTC_CR_BYPSHAD_Pos (5U)
lypinator 0:bb348c97df44 10381 #define RTC_CR_BYPSHAD_Msk (0x1U << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 10382 #define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
lypinator 0:bb348c97df44 10383 #define RTC_CR_REFCKON_Pos (4U)
lypinator 0:bb348c97df44 10384 #define RTC_CR_REFCKON_Msk (0x1U << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 10385 #define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
lypinator 0:bb348c97df44 10386 #define RTC_CR_TSEDGE_Pos (3U)
lypinator 0:bb348c97df44 10387 #define RTC_CR_TSEDGE_Msk (0x1U << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 10388 #define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
lypinator 0:bb348c97df44 10389 #define RTC_CR_WUCKSEL_Pos (0U)
lypinator 0:bb348c97df44 10390 #define RTC_CR_WUCKSEL_Msk (0x7U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
lypinator 0:bb348c97df44 10391 #define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
lypinator 0:bb348c97df44 10392 #define RTC_CR_WUCKSEL_0 (0x1U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 10393 #define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 10394 #define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 10395
lypinator 0:bb348c97df44 10396 /* Legacy defines */
lypinator 0:bb348c97df44 10397 #define RTC_CR_BCK RTC_CR_BKP
lypinator 0:bb348c97df44 10398
lypinator 0:bb348c97df44 10399 /******************** Bits definition for RTC_ISR register ******************/
lypinator 0:bb348c97df44 10400 #define RTC_ISR_RECALPF_Pos (16U)
lypinator 0:bb348c97df44 10401 #define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 10402 #define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk
lypinator 0:bb348c97df44 10403 #define RTC_ISR_TAMP1F_Pos (13U)
lypinator 0:bb348c97df44 10404 #define RTC_ISR_TAMP1F_Msk (0x1U << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 10405 #define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk
lypinator 0:bb348c97df44 10406 #define RTC_ISR_TAMP2F_Pos (14U)
lypinator 0:bb348c97df44 10407 #define RTC_ISR_TAMP2F_Msk (0x1U << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 10408 #define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk
lypinator 0:bb348c97df44 10409 #define RTC_ISR_TSOVF_Pos (12U)
lypinator 0:bb348c97df44 10410 #define RTC_ISR_TSOVF_Msk (0x1U << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 10411 #define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
lypinator 0:bb348c97df44 10412 #define RTC_ISR_TSF_Pos (11U)
lypinator 0:bb348c97df44 10413 #define RTC_ISR_TSF_Msk (0x1U << RTC_ISR_TSF_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 10414 #define RTC_ISR_TSF RTC_ISR_TSF_Msk
lypinator 0:bb348c97df44 10415 #define RTC_ISR_WUTF_Pos (10U)
lypinator 0:bb348c97df44 10416 #define RTC_ISR_WUTF_Msk (0x1U << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 10417 #define RTC_ISR_WUTF RTC_ISR_WUTF_Msk
lypinator 0:bb348c97df44 10418 #define RTC_ISR_ALRBF_Pos (9U)
lypinator 0:bb348c97df44 10419 #define RTC_ISR_ALRBF_Msk (0x1U << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 10420 #define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk
lypinator 0:bb348c97df44 10421 #define RTC_ISR_ALRAF_Pos (8U)
lypinator 0:bb348c97df44 10422 #define RTC_ISR_ALRAF_Msk (0x1U << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 10423 #define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
lypinator 0:bb348c97df44 10424 #define RTC_ISR_INIT_Pos (7U)
lypinator 0:bb348c97df44 10425 #define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 10426 #define RTC_ISR_INIT RTC_ISR_INIT_Msk
lypinator 0:bb348c97df44 10427 #define RTC_ISR_INITF_Pos (6U)
lypinator 0:bb348c97df44 10428 #define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 10429 #define RTC_ISR_INITF RTC_ISR_INITF_Msk
lypinator 0:bb348c97df44 10430 #define RTC_ISR_RSF_Pos (5U)
lypinator 0:bb348c97df44 10431 #define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 10432 #define RTC_ISR_RSF RTC_ISR_RSF_Msk
lypinator 0:bb348c97df44 10433 #define RTC_ISR_INITS_Pos (4U)
lypinator 0:bb348c97df44 10434 #define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 10435 #define RTC_ISR_INITS RTC_ISR_INITS_Msk
lypinator 0:bb348c97df44 10436 #define RTC_ISR_SHPF_Pos (3U)
lypinator 0:bb348c97df44 10437 #define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 10438 #define RTC_ISR_SHPF RTC_ISR_SHPF_Msk
lypinator 0:bb348c97df44 10439 #define RTC_ISR_WUTWF_Pos (2U)
lypinator 0:bb348c97df44 10440 #define RTC_ISR_WUTWF_Msk (0x1U << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 10441 #define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk
lypinator 0:bb348c97df44 10442 #define RTC_ISR_ALRBWF_Pos (1U)
lypinator 0:bb348c97df44 10443 #define RTC_ISR_ALRBWF_Msk (0x1U << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 10444 #define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk
lypinator 0:bb348c97df44 10445 #define RTC_ISR_ALRAWF_Pos (0U)
lypinator 0:bb348c97df44 10446 #define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 10447 #define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
lypinator 0:bb348c97df44 10448
lypinator 0:bb348c97df44 10449 /******************** Bits definition for RTC_PRER register *****************/
lypinator 0:bb348c97df44 10450 #define RTC_PRER_PREDIV_A_Pos (16U)
lypinator 0:bb348c97df44 10451 #define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
lypinator 0:bb348c97df44 10452 #define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
lypinator 0:bb348c97df44 10453 #define RTC_PRER_PREDIV_S_Pos (0U)
lypinator 0:bb348c97df44 10454 #define RTC_PRER_PREDIV_S_Msk (0x7FFFU << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
lypinator 0:bb348c97df44 10455 #define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
lypinator 0:bb348c97df44 10456
lypinator 0:bb348c97df44 10457 /******************** Bits definition for RTC_WUTR register *****************/
lypinator 0:bb348c97df44 10458 #define RTC_WUTR_WUT_Pos (0U)
lypinator 0:bb348c97df44 10459 #define RTC_WUTR_WUT_Msk (0xFFFFU << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
lypinator 0:bb348c97df44 10460 #define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
lypinator 0:bb348c97df44 10461
lypinator 0:bb348c97df44 10462 /******************** Bits definition for RTC_CALIBR register ***************/
lypinator 0:bb348c97df44 10463 #define RTC_CALIBR_DCS_Pos (7U)
lypinator 0:bb348c97df44 10464 #define RTC_CALIBR_DCS_Msk (0x1U << RTC_CALIBR_DCS_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 10465 #define RTC_CALIBR_DCS RTC_CALIBR_DCS_Msk
lypinator 0:bb348c97df44 10466 #define RTC_CALIBR_DC_Pos (0U)
lypinator 0:bb348c97df44 10467 #define RTC_CALIBR_DC_Msk (0x1FU << RTC_CALIBR_DC_Pos) /*!< 0x0000001F */
lypinator 0:bb348c97df44 10468 #define RTC_CALIBR_DC RTC_CALIBR_DC_Msk
lypinator 0:bb348c97df44 10469
lypinator 0:bb348c97df44 10470 /******************** Bits definition for RTC_ALRMAR register ***************/
lypinator 0:bb348c97df44 10471 #define RTC_ALRMAR_MSK4_Pos (31U)
lypinator 0:bb348c97df44 10472 #define RTC_ALRMAR_MSK4_Msk (0x1U << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
lypinator 0:bb348c97df44 10473 #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
lypinator 0:bb348c97df44 10474 #define RTC_ALRMAR_WDSEL_Pos (30U)
lypinator 0:bb348c97df44 10475 #define RTC_ALRMAR_WDSEL_Msk (0x1U << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
lypinator 0:bb348c97df44 10476 #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
lypinator 0:bb348c97df44 10477 #define RTC_ALRMAR_DT_Pos (28U)
lypinator 0:bb348c97df44 10478 #define RTC_ALRMAR_DT_Msk (0x3U << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
lypinator 0:bb348c97df44 10479 #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
lypinator 0:bb348c97df44 10480 #define RTC_ALRMAR_DT_0 (0x1U << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
lypinator 0:bb348c97df44 10481 #define RTC_ALRMAR_DT_1 (0x2U << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
lypinator 0:bb348c97df44 10482 #define RTC_ALRMAR_DU_Pos (24U)
lypinator 0:bb348c97df44 10483 #define RTC_ALRMAR_DU_Msk (0xFU << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
lypinator 0:bb348c97df44 10484 #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
lypinator 0:bb348c97df44 10485 #define RTC_ALRMAR_DU_0 (0x1U << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 10486 #define RTC_ALRMAR_DU_1 (0x2U << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 10487 #define RTC_ALRMAR_DU_2 (0x4U << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
lypinator 0:bb348c97df44 10488 #define RTC_ALRMAR_DU_3 (0x8U << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
lypinator 0:bb348c97df44 10489 #define RTC_ALRMAR_MSK3_Pos (23U)
lypinator 0:bb348c97df44 10490 #define RTC_ALRMAR_MSK3_Msk (0x1U << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
lypinator 0:bb348c97df44 10491 #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
lypinator 0:bb348c97df44 10492 #define RTC_ALRMAR_PM_Pos (22U)
lypinator 0:bb348c97df44 10493 #define RTC_ALRMAR_PM_Msk (0x1U << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 10494 #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
lypinator 0:bb348c97df44 10495 #define RTC_ALRMAR_HT_Pos (20U)
lypinator 0:bb348c97df44 10496 #define RTC_ALRMAR_HT_Msk (0x3U << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
lypinator 0:bb348c97df44 10497 #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
lypinator 0:bb348c97df44 10498 #define RTC_ALRMAR_HT_0 (0x1U << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 10499 #define RTC_ALRMAR_HT_1 (0x2U << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 10500 #define RTC_ALRMAR_HU_Pos (16U)
lypinator 0:bb348c97df44 10501 #define RTC_ALRMAR_HU_Msk (0xFU << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
lypinator 0:bb348c97df44 10502 #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
lypinator 0:bb348c97df44 10503 #define RTC_ALRMAR_HU_0 (0x1U << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 10504 #define RTC_ALRMAR_HU_1 (0x2U << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 10505 #define RTC_ALRMAR_HU_2 (0x4U << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 10506 #define RTC_ALRMAR_HU_3 (0x8U << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 10507 #define RTC_ALRMAR_MSK2_Pos (15U)
lypinator 0:bb348c97df44 10508 #define RTC_ALRMAR_MSK2_Msk (0x1U << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 10509 #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
lypinator 0:bb348c97df44 10510 #define RTC_ALRMAR_MNT_Pos (12U)
lypinator 0:bb348c97df44 10511 #define RTC_ALRMAR_MNT_Msk (0x7U << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
lypinator 0:bb348c97df44 10512 #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
lypinator 0:bb348c97df44 10513 #define RTC_ALRMAR_MNT_0 (0x1U << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 10514 #define RTC_ALRMAR_MNT_1 (0x2U << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 10515 #define RTC_ALRMAR_MNT_2 (0x4U << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 10516 #define RTC_ALRMAR_MNU_Pos (8U)
lypinator 0:bb348c97df44 10517 #define RTC_ALRMAR_MNU_Msk (0xFU << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
lypinator 0:bb348c97df44 10518 #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
lypinator 0:bb348c97df44 10519 #define RTC_ALRMAR_MNU_0 (0x1U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 10520 #define RTC_ALRMAR_MNU_1 (0x2U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 10521 #define RTC_ALRMAR_MNU_2 (0x4U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 10522 #define RTC_ALRMAR_MNU_3 (0x8U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 10523 #define RTC_ALRMAR_MSK1_Pos (7U)
lypinator 0:bb348c97df44 10524 #define RTC_ALRMAR_MSK1_Msk (0x1U << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 10525 #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
lypinator 0:bb348c97df44 10526 #define RTC_ALRMAR_ST_Pos (4U)
lypinator 0:bb348c97df44 10527 #define RTC_ALRMAR_ST_Msk (0x7U << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
lypinator 0:bb348c97df44 10528 #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
lypinator 0:bb348c97df44 10529 #define RTC_ALRMAR_ST_0 (0x1U << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 10530 #define RTC_ALRMAR_ST_1 (0x2U << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 10531 #define RTC_ALRMAR_ST_2 (0x4U << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 10532 #define RTC_ALRMAR_SU_Pos (0U)
lypinator 0:bb348c97df44 10533 #define RTC_ALRMAR_SU_Msk (0xFU << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
lypinator 0:bb348c97df44 10534 #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
lypinator 0:bb348c97df44 10535 #define RTC_ALRMAR_SU_0 (0x1U << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 10536 #define RTC_ALRMAR_SU_1 (0x2U << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 10537 #define RTC_ALRMAR_SU_2 (0x4U << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 10538 #define RTC_ALRMAR_SU_3 (0x8U << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 10539
lypinator 0:bb348c97df44 10540 /******************** Bits definition for RTC_ALRMBR register ***************/
lypinator 0:bb348c97df44 10541 #define RTC_ALRMBR_MSK4_Pos (31U)
lypinator 0:bb348c97df44 10542 #define RTC_ALRMBR_MSK4_Msk (0x1U << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
lypinator 0:bb348c97df44 10543 #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
lypinator 0:bb348c97df44 10544 #define RTC_ALRMBR_WDSEL_Pos (30U)
lypinator 0:bb348c97df44 10545 #define RTC_ALRMBR_WDSEL_Msk (0x1U << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
lypinator 0:bb348c97df44 10546 #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
lypinator 0:bb348c97df44 10547 #define RTC_ALRMBR_DT_Pos (28U)
lypinator 0:bb348c97df44 10548 #define RTC_ALRMBR_DT_Msk (0x3U << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
lypinator 0:bb348c97df44 10549 #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
lypinator 0:bb348c97df44 10550 #define RTC_ALRMBR_DT_0 (0x1U << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
lypinator 0:bb348c97df44 10551 #define RTC_ALRMBR_DT_1 (0x2U << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
lypinator 0:bb348c97df44 10552 #define RTC_ALRMBR_DU_Pos (24U)
lypinator 0:bb348c97df44 10553 #define RTC_ALRMBR_DU_Msk (0xFU << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
lypinator 0:bb348c97df44 10554 #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
lypinator 0:bb348c97df44 10555 #define RTC_ALRMBR_DU_0 (0x1U << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 10556 #define RTC_ALRMBR_DU_1 (0x2U << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 10557 #define RTC_ALRMBR_DU_2 (0x4U << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
lypinator 0:bb348c97df44 10558 #define RTC_ALRMBR_DU_3 (0x8U << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
lypinator 0:bb348c97df44 10559 #define RTC_ALRMBR_MSK3_Pos (23U)
lypinator 0:bb348c97df44 10560 #define RTC_ALRMBR_MSK3_Msk (0x1U << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
lypinator 0:bb348c97df44 10561 #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
lypinator 0:bb348c97df44 10562 #define RTC_ALRMBR_PM_Pos (22U)
lypinator 0:bb348c97df44 10563 #define RTC_ALRMBR_PM_Msk (0x1U << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 10564 #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
lypinator 0:bb348c97df44 10565 #define RTC_ALRMBR_HT_Pos (20U)
lypinator 0:bb348c97df44 10566 #define RTC_ALRMBR_HT_Msk (0x3U << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
lypinator 0:bb348c97df44 10567 #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
lypinator 0:bb348c97df44 10568 #define RTC_ALRMBR_HT_0 (0x1U << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 10569 #define RTC_ALRMBR_HT_1 (0x2U << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 10570 #define RTC_ALRMBR_HU_Pos (16U)
lypinator 0:bb348c97df44 10571 #define RTC_ALRMBR_HU_Msk (0xFU << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
lypinator 0:bb348c97df44 10572 #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
lypinator 0:bb348c97df44 10573 #define RTC_ALRMBR_HU_0 (0x1U << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 10574 #define RTC_ALRMBR_HU_1 (0x2U << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 10575 #define RTC_ALRMBR_HU_2 (0x4U << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 10576 #define RTC_ALRMBR_HU_3 (0x8U << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 10577 #define RTC_ALRMBR_MSK2_Pos (15U)
lypinator 0:bb348c97df44 10578 #define RTC_ALRMBR_MSK2_Msk (0x1U << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 10579 #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
lypinator 0:bb348c97df44 10580 #define RTC_ALRMBR_MNT_Pos (12U)
lypinator 0:bb348c97df44 10581 #define RTC_ALRMBR_MNT_Msk (0x7U << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
lypinator 0:bb348c97df44 10582 #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
lypinator 0:bb348c97df44 10583 #define RTC_ALRMBR_MNT_0 (0x1U << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 10584 #define RTC_ALRMBR_MNT_1 (0x2U << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 10585 #define RTC_ALRMBR_MNT_2 (0x4U << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 10586 #define RTC_ALRMBR_MNU_Pos (8U)
lypinator 0:bb348c97df44 10587 #define RTC_ALRMBR_MNU_Msk (0xFU << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
lypinator 0:bb348c97df44 10588 #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
lypinator 0:bb348c97df44 10589 #define RTC_ALRMBR_MNU_0 (0x1U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 10590 #define RTC_ALRMBR_MNU_1 (0x2U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 10591 #define RTC_ALRMBR_MNU_2 (0x4U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 10592 #define RTC_ALRMBR_MNU_3 (0x8U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 10593 #define RTC_ALRMBR_MSK1_Pos (7U)
lypinator 0:bb348c97df44 10594 #define RTC_ALRMBR_MSK1_Msk (0x1U << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 10595 #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
lypinator 0:bb348c97df44 10596 #define RTC_ALRMBR_ST_Pos (4U)
lypinator 0:bb348c97df44 10597 #define RTC_ALRMBR_ST_Msk (0x7U << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
lypinator 0:bb348c97df44 10598 #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
lypinator 0:bb348c97df44 10599 #define RTC_ALRMBR_ST_0 (0x1U << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 10600 #define RTC_ALRMBR_ST_1 (0x2U << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 10601 #define RTC_ALRMBR_ST_2 (0x4U << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 10602 #define RTC_ALRMBR_SU_Pos (0U)
lypinator 0:bb348c97df44 10603 #define RTC_ALRMBR_SU_Msk (0xFU << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
lypinator 0:bb348c97df44 10604 #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
lypinator 0:bb348c97df44 10605 #define RTC_ALRMBR_SU_0 (0x1U << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 10606 #define RTC_ALRMBR_SU_1 (0x2U << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 10607 #define RTC_ALRMBR_SU_2 (0x4U << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 10608 #define RTC_ALRMBR_SU_3 (0x8U << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 10609
lypinator 0:bb348c97df44 10610 /******************** Bits definition for RTC_WPR register ******************/
lypinator 0:bb348c97df44 10611 #define RTC_WPR_KEY_Pos (0U)
lypinator 0:bb348c97df44 10612 #define RTC_WPR_KEY_Msk (0xFFU << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
lypinator 0:bb348c97df44 10613 #define RTC_WPR_KEY RTC_WPR_KEY_Msk
lypinator 0:bb348c97df44 10614
lypinator 0:bb348c97df44 10615 /******************** Bits definition for RTC_SSR register ******************/
lypinator 0:bb348c97df44 10616 #define RTC_SSR_SS_Pos (0U)
lypinator 0:bb348c97df44 10617 #define RTC_SSR_SS_Msk (0xFFFFU << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
lypinator 0:bb348c97df44 10618 #define RTC_SSR_SS RTC_SSR_SS_Msk
lypinator 0:bb348c97df44 10619
lypinator 0:bb348c97df44 10620 /******************** Bits definition for RTC_SHIFTR register ***************/
lypinator 0:bb348c97df44 10621 #define RTC_SHIFTR_SUBFS_Pos (0U)
lypinator 0:bb348c97df44 10622 #define RTC_SHIFTR_SUBFS_Msk (0x7FFFU << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
lypinator 0:bb348c97df44 10623 #define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
lypinator 0:bb348c97df44 10624 #define RTC_SHIFTR_ADD1S_Pos (31U)
lypinator 0:bb348c97df44 10625 #define RTC_SHIFTR_ADD1S_Msk (0x1U << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
lypinator 0:bb348c97df44 10626 #define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
lypinator 0:bb348c97df44 10627
lypinator 0:bb348c97df44 10628 /******************** Bits definition for RTC_TSTR register *****************/
lypinator 0:bb348c97df44 10629 #define RTC_TSTR_PM_Pos (22U)
lypinator 0:bb348c97df44 10630 #define RTC_TSTR_PM_Msk (0x1U << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 10631 #define RTC_TSTR_PM RTC_TSTR_PM_Msk
lypinator 0:bb348c97df44 10632 #define RTC_TSTR_HT_Pos (20U)
lypinator 0:bb348c97df44 10633 #define RTC_TSTR_HT_Msk (0x3U << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
lypinator 0:bb348c97df44 10634 #define RTC_TSTR_HT RTC_TSTR_HT_Msk
lypinator 0:bb348c97df44 10635 #define RTC_TSTR_HT_0 (0x1U << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 10636 #define RTC_TSTR_HT_1 (0x2U << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 10637 #define RTC_TSTR_HU_Pos (16U)
lypinator 0:bb348c97df44 10638 #define RTC_TSTR_HU_Msk (0xFU << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
lypinator 0:bb348c97df44 10639 #define RTC_TSTR_HU RTC_TSTR_HU_Msk
lypinator 0:bb348c97df44 10640 #define RTC_TSTR_HU_0 (0x1U << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 10641 #define RTC_TSTR_HU_1 (0x2U << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 10642 #define RTC_TSTR_HU_2 (0x4U << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 10643 #define RTC_TSTR_HU_3 (0x8U << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 10644 #define RTC_TSTR_MNT_Pos (12U)
lypinator 0:bb348c97df44 10645 #define RTC_TSTR_MNT_Msk (0x7U << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
lypinator 0:bb348c97df44 10646 #define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
lypinator 0:bb348c97df44 10647 #define RTC_TSTR_MNT_0 (0x1U << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 10648 #define RTC_TSTR_MNT_1 (0x2U << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 10649 #define RTC_TSTR_MNT_2 (0x4U << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 10650 #define RTC_TSTR_MNU_Pos (8U)
lypinator 0:bb348c97df44 10651 #define RTC_TSTR_MNU_Msk (0xFU << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
lypinator 0:bb348c97df44 10652 #define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
lypinator 0:bb348c97df44 10653 #define RTC_TSTR_MNU_0 (0x1U << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 10654 #define RTC_TSTR_MNU_1 (0x2U << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 10655 #define RTC_TSTR_MNU_2 (0x4U << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 10656 #define RTC_TSTR_MNU_3 (0x8U << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 10657 #define RTC_TSTR_ST_Pos (4U)
lypinator 0:bb348c97df44 10658 #define RTC_TSTR_ST_Msk (0x7U << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
lypinator 0:bb348c97df44 10659 #define RTC_TSTR_ST RTC_TSTR_ST_Msk
lypinator 0:bb348c97df44 10660 #define RTC_TSTR_ST_0 (0x1U << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 10661 #define RTC_TSTR_ST_1 (0x2U << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 10662 #define RTC_TSTR_ST_2 (0x4U << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 10663 #define RTC_TSTR_SU_Pos (0U)
lypinator 0:bb348c97df44 10664 #define RTC_TSTR_SU_Msk (0xFU << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
lypinator 0:bb348c97df44 10665 #define RTC_TSTR_SU RTC_TSTR_SU_Msk
lypinator 0:bb348c97df44 10666 #define RTC_TSTR_SU_0 (0x1U << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 10667 #define RTC_TSTR_SU_1 (0x2U << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 10668 #define RTC_TSTR_SU_2 (0x4U << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 10669 #define RTC_TSTR_SU_3 (0x8U << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 10670
lypinator 0:bb348c97df44 10671 /******************** Bits definition for RTC_TSDR register *****************/
lypinator 0:bb348c97df44 10672 #define RTC_TSDR_WDU_Pos (13U)
lypinator 0:bb348c97df44 10673 #define RTC_TSDR_WDU_Msk (0x7U << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
lypinator 0:bb348c97df44 10674 #define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
lypinator 0:bb348c97df44 10675 #define RTC_TSDR_WDU_0 (0x1U << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 10676 #define RTC_TSDR_WDU_1 (0x2U << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 10677 #define RTC_TSDR_WDU_2 (0x4U << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 10678 #define RTC_TSDR_MT_Pos (12U)
lypinator 0:bb348c97df44 10679 #define RTC_TSDR_MT_Msk (0x1U << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 10680 #define RTC_TSDR_MT RTC_TSDR_MT_Msk
lypinator 0:bb348c97df44 10681 #define RTC_TSDR_MU_Pos (8U)
lypinator 0:bb348c97df44 10682 #define RTC_TSDR_MU_Msk (0xFU << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
lypinator 0:bb348c97df44 10683 #define RTC_TSDR_MU RTC_TSDR_MU_Msk
lypinator 0:bb348c97df44 10684 #define RTC_TSDR_MU_0 (0x1U << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 10685 #define RTC_TSDR_MU_1 (0x2U << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 10686 #define RTC_TSDR_MU_2 (0x4U << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 10687 #define RTC_TSDR_MU_3 (0x8U << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 10688 #define RTC_TSDR_DT_Pos (4U)
lypinator 0:bb348c97df44 10689 #define RTC_TSDR_DT_Msk (0x3U << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
lypinator 0:bb348c97df44 10690 #define RTC_TSDR_DT RTC_TSDR_DT_Msk
lypinator 0:bb348c97df44 10691 #define RTC_TSDR_DT_0 (0x1U << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 10692 #define RTC_TSDR_DT_1 (0x2U << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 10693 #define RTC_TSDR_DU_Pos (0U)
lypinator 0:bb348c97df44 10694 #define RTC_TSDR_DU_Msk (0xFU << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
lypinator 0:bb348c97df44 10695 #define RTC_TSDR_DU RTC_TSDR_DU_Msk
lypinator 0:bb348c97df44 10696 #define RTC_TSDR_DU_0 (0x1U << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 10697 #define RTC_TSDR_DU_1 (0x2U << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 10698 #define RTC_TSDR_DU_2 (0x4U << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 10699 #define RTC_TSDR_DU_3 (0x8U << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 10700
lypinator 0:bb348c97df44 10701 /******************** Bits definition for RTC_TSSSR register ****************/
lypinator 0:bb348c97df44 10702 #define RTC_TSSSR_SS_Pos (0U)
lypinator 0:bb348c97df44 10703 #define RTC_TSSSR_SS_Msk (0xFFFFU << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
lypinator 0:bb348c97df44 10704 #define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
lypinator 0:bb348c97df44 10705
lypinator 0:bb348c97df44 10706 /******************** Bits definition for RTC_CAL register *****************/
lypinator 0:bb348c97df44 10707 #define RTC_CALR_CALP_Pos (15U)
lypinator 0:bb348c97df44 10708 #define RTC_CALR_CALP_Msk (0x1U << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 10709 #define RTC_CALR_CALP RTC_CALR_CALP_Msk
lypinator 0:bb348c97df44 10710 #define RTC_CALR_CALW8_Pos (14U)
lypinator 0:bb348c97df44 10711 #define RTC_CALR_CALW8_Msk (0x1U << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 10712 #define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
lypinator 0:bb348c97df44 10713 #define RTC_CALR_CALW16_Pos (13U)
lypinator 0:bb348c97df44 10714 #define RTC_CALR_CALW16_Msk (0x1U << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 10715 #define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
lypinator 0:bb348c97df44 10716 #define RTC_CALR_CALM_Pos (0U)
lypinator 0:bb348c97df44 10717 #define RTC_CALR_CALM_Msk (0x1FFU << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
lypinator 0:bb348c97df44 10718 #define RTC_CALR_CALM RTC_CALR_CALM_Msk
lypinator 0:bb348c97df44 10719 #define RTC_CALR_CALM_0 (0x001U << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 10720 #define RTC_CALR_CALM_1 (0x002U << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 10721 #define RTC_CALR_CALM_2 (0x004U << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 10722 #define RTC_CALR_CALM_3 (0x008U << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 10723 #define RTC_CALR_CALM_4 (0x010U << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 10724 #define RTC_CALR_CALM_5 (0x020U << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 10725 #define RTC_CALR_CALM_6 (0x040U << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 10726 #define RTC_CALR_CALM_7 (0x080U << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 10727 #define RTC_CALR_CALM_8 (0x100U << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 10728
lypinator 0:bb348c97df44 10729 /******************** Bits definition for RTC_TAFCR register ****************/
lypinator 0:bb348c97df44 10730 #define RTC_TAFCR_ALARMOUTTYPE_Pos (18U)
lypinator 0:bb348c97df44 10731 #define RTC_TAFCR_ALARMOUTTYPE_Msk (0x1U << RTC_TAFCR_ALARMOUTTYPE_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 10732 #define RTC_TAFCR_ALARMOUTTYPE RTC_TAFCR_ALARMOUTTYPE_Msk
lypinator 0:bb348c97df44 10733 #define RTC_TAFCR_TSINSEL_Pos (17U)
lypinator 0:bb348c97df44 10734 #define RTC_TAFCR_TSINSEL_Msk (0x1U << RTC_TAFCR_TSINSEL_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 10735 #define RTC_TAFCR_TSINSEL RTC_TAFCR_TSINSEL_Msk
lypinator 0:bb348c97df44 10736 #define RTC_TAFCR_TAMP1INSEL_Pos (16U)
lypinator 0:bb348c97df44 10737 #define RTC_TAFCR_TAMP1INSEL_Msk (0x1U << RTC_TAFCR_TAMP1INSEL_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 10738 #define RTC_TAFCR_TAMP1INSEL RTC_TAFCR_TAMP1INSEL_Msk
lypinator 0:bb348c97df44 10739 #define RTC_TAFCR_TAMPPUDIS_Pos (15U)
lypinator 0:bb348c97df44 10740 #define RTC_TAFCR_TAMPPUDIS_Msk (0x1U << RTC_TAFCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 10741 #define RTC_TAFCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS_Msk
lypinator 0:bb348c97df44 10742 #define RTC_TAFCR_TAMPPRCH_Pos (13U)
lypinator 0:bb348c97df44 10743 #define RTC_TAFCR_TAMPPRCH_Msk (0x3U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00006000 */
lypinator 0:bb348c97df44 10744 #define RTC_TAFCR_TAMPPRCH RTC_TAFCR_TAMPPRCH_Msk
lypinator 0:bb348c97df44 10745 #define RTC_TAFCR_TAMPPRCH_0 (0x1U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 10746 #define RTC_TAFCR_TAMPPRCH_1 (0x2U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 10747 #define RTC_TAFCR_TAMPFLT_Pos (11U)
lypinator 0:bb348c97df44 10748 #define RTC_TAFCR_TAMPFLT_Msk (0x3U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001800 */
lypinator 0:bb348c97df44 10749 #define RTC_TAFCR_TAMPFLT RTC_TAFCR_TAMPFLT_Msk
lypinator 0:bb348c97df44 10750 #define RTC_TAFCR_TAMPFLT_0 (0x1U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 10751 #define RTC_TAFCR_TAMPFLT_1 (0x2U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 10752 #define RTC_TAFCR_TAMPFREQ_Pos (8U)
lypinator 0:bb348c97df44 10753 #define RTC_TAFCR_TAMPFREQ_Msk (0x7U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000700 */
lypinator 0:bb348c97df44 10754 #define RTC_TAFCR_TAMPFREQ RTC_TAFCR_TAMPFREQ_Msk
lypinator 0:bb348c97df44 10755 #define RTC_TAFCR_TAMPFREQ_0 (0x1U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 10756 #define RTC_TAFCR_TAMPFREQ_1 (0x2U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 10757 #define RTC_TAFCR_TAMPFREQ_2 (0x4U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 10758 #define RTC_TAFCR_TAMPTS_Pos (7U)
lypinator 0:bb348c97df44 10759 #define RTC_TAFCR_TAMPTS_Msk (0x1U << RTC_TAFCR_TAMPTS_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 10760 #define RTC_TAFCR_TAMPTS RTC_TAFCR_TAMPTS_Msk
lypinator 0:bb348c97df44 10761 #define RTC_TAFCR_TAMP2TRG_Pos (4U)
lypinator 0:bb348c97df44 10762 #define RTC_TAFCR_TAMP2TRG_Msk (0x1U << RTC_TAFCR_TAMP2TRG_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 10763 #define RTC_TAFCR_TAMP2TRG RTC_TAFCR_TAMP2TRG_Msk
lypinator 0:bb348c97df44 10764 #define RTC_TAFCR_TAMP2E_Pos (3U)
lypinator 0:bb348c97df44 10765 #define RTC_TAFCR_TAMP2E_Msk (0x1U << RTC_TAFCR_TAMP2E_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 10766 #define RTC_TAFCR_TAMP2E RTC_TAFCR_TAMP2E_Msk
lypinator 0:bb348c97df44 10767 #define RTC_TAFCR_TAMPIE_Pos (2U)
lypinator 0:bb348c97df44 10768 #define RTC_TAFCR_TAMPIE_Msk (0x1U << RTC_TAFCR_TAMPIE_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 10769 #define RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk
lypinator 0:bb348c97df44 10770 #define RTC_TAFCR_TAMP1TRG_Pos (1U)
lypinator 0:bb348c97df44 10771 #define RTC_TAFCR_TAMP1TRG_Msk (0x1U << RTC_TAFCR_TAMP1TRG_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 10772 #define RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk
lypinator 0:bb348c97df44 10773 #define RTC_TAFCR_TAMP1E_Pos (0U)
lypinator 0:bb348c97df44 10774 #define RTC_TAFCR_TAMP1E_Msk (0x1U << RTC_TAFCR_TAMP1E_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 10775 #define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk
lypinator 0:bb348c97df44 10776
lypinator 0:bb348c97df44 10777 /* Legacy defines */
lypinator 0:bb348c97df44 10778 #define RTC_TAFCR_TAMPINSEL RTC_TAFCR_TAMP1INSEL
lypinator 0:bb348c97df44 10779
lypinator 0:bb348c97df44 10780 /******************** Bits definition for RTC_ALRMASSR register *************/
lypinator 0:bb348c97df44 10781 #define RTC_ALRMASSR_MASKSS_Pos (24U)
lypinator 0:bb348c97df44 10782 #define RTC_ALRMASSR_MASKSS_Msk (0xFU << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
lypinator 0:bb348c97df44 10783 #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
lypinator 0:bb348c97df44 10784 #define RTC_ALRMASSR_MASKSS_0 (0x1U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 10785 #define RTC_ALRMASSR_MASKSS_1 (0x2U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 10786 #define RTC_ALRMASSR_MASKSS_2 (0x4U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
lypinator 0:bb348c97df44 10787 #define RTC_ALRMASSR_MASKSS_3 (0x8U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
lypinator 0:bb348c97df44 10788 #define RTC_ALRMASSR_SS_Pos (0U)
lypinator 0:bb348c97df44 10789 #define RTC_ALRMASSR_SS_Msk (0x7FFFU << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
lypinator 0:bb348c97df44 10790 #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
lypinator 0:bb348c97df44 10791
lypinator 0:bb348c97df44 10792 /******************** Bits definition for RTC_ALRMBSSR register *************/
lypinator 0:bb348c97df44 10793 #define RTC_ALRMBSSR_MASKSS_Pos (24U)
lypinator 0:bb348c97df44 10794 #define RTC_ALRMBSSR_MASKSS_Msk (0xFU << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
lypinator 0:bb348c97df44 10795 #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
lypinator 0:bb348c97df44 10796 #define RTC_ALRMBSSR_MASKSS_0 (0x1U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 10797 #define RTC_ALRMBSSR_MASKSS_1 (0x2U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 10798 #define RTC_ALRMBSSR_MASKSS_2 (0x4U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
lypinator 0:bb348c97df44 10799 #define RTC_ALRMBSSR_MASKSS_3 (0x8U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
lypinator 0:bb348c97df44 10800 #define RTC_ALRMBSSR_SS_Pos (0U)
lypinator 0:bb348c97df44 10801 #define RTC_ALRMBSSR_SS_Msk (0x7FFFU << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
lypinator 0:bb348c97df44 10802 #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
lypinator 0:bb348c97df44 10803
lypinator 0:bb348c97df44 10804 /******************** Bits definition for RTC_BKP0R register ****************/
lypinator 0:bb348c97df44 10805 #define RTC_BKP0R_Pos (0U)
lypinator 0:bb348c97df44 10806 #define RTC_BKP0R_Msk (0xFFFFFFFFU << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */
lypinator 0:bb348c97df44 10807 #define RTC_BKP0R RTC_BKP0R_Msk
lypinator 0:bb348c97df44 10808
lypinator 0:bb348c97df44 10809 /******************** Bits definition for RTC_BKP1R register ****************/
lypinator 0:bb348c97df44 10810 #define RTC_BKP1R_Pos (0U)
lypinator 0:bb348c97df44 10811 #define RTC_BKP1R_Msk (0xFFFFFFFFU << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */
lypinator 0:bb348c97df44 10812 #define RTC_BKP1R RTC_BKP1R_Msk
lypinator 0:bb348c97df44 10813
lypinator 0:bb348c97df44 10814 /******************** Bits definition for RTC_BKP2R register ****************/
lypinator 0:bb348c97df44 10815 #define RTC_BKP2R_Pos (0U)
lypinator 0:bb348c97df44 10816 #define RTC_BKP2R_Msk (0xFFFFFFFFU << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */
lypinator 0:bb348c97df44 10817 #define RTC_BKP2R RTC_BKP2R_Msk
lypinator 0:bb348c97df44 10818
lypinator 0:bb348c97df44 10819 /******************** Bits definition for RTC_BKP3R register ****************/
lypinator 0:bb348c97df44 10820 #define RTC_BKP3R_Pos (0U)
lypinator 0:bb348c97df44 10821 #define RTC_BKP3R_Msk (0xFFFFFFFFU << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */
lypinator 0:bb348c97df44 10822 #define RTC_BKP3R RTC_BKP3R_Msk
lypinator 0:bb348c97df44 10823
lypinator 0:bb348c97df44 10824 /******************** Bits definition for RTC_BKP4R register ****************/
lypinator 0:bb348c97df44 10825 #define RTC_BKP4R_Pos (0U)
lypinator 0:bb348c97df44 10826 #define RTC_BKP4R_Msk (0xFFFFFFFFU << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */
lypinator 0:bb348c97df44 10827 #define RTC_BKP4R RTC_BKP4R_Msk
lypinator 0:bb348c97df44 10828
lypinator 0:bb348c97df44 10829 /******************** Bits definition for RTC_BKP5R register ****************/
lypinator 0:bb348c97df44 10830 #define RTC_BKP5R_Pos (0U)
lypinator 0:bb348c97df44 10831 #define RTC_BKP5R_Msk (0xFFFFFFFFU << RTC_BKP5R_Pos) /*!< 0xFFFFFFFF */
lypinator 0:bb348c97df44 10832 #define RTC_BKP5R RTC_BKP5R_Msk
lypinator 0:bb348c97df44 10833
lypinator 0:bb348c97df44 10834 /******************** Bits definition for RTC_BKP6R register ****************/
lypinator 0:bb348c97df44 10835 #define RTC_BKP6R_Pos (0U)
lypinator 0:bb348c97df44 10836 #define RTC_BKP6R_Msk (0xFFFFFFFFU << RTC_BKP6R_Pos) /*!< 0xFFFFFFFF */
lypinator 0:bb348c97df44 10837 #define RTC_BKP6R RTC_BKP6R_Msk
lypinator 0:bb348c97df44 10838
lypinator 0:bb348c97df44 10839 /******************** Bits definition for RTC_BKP7R register ****************/
lypinator 0:bb348c97df44 10840 #define RTC_BKP7R_Pos (0U)
lypinator 0:bb348c97df44 10841 #define RTC_BKP7R_Msk (0xFFFFFFFFU << RTC_BKP7R_Pos) /*!< 0xFFFFFFFF */
lypinator 0:bb348c97df44 10842 #define RTC_BKP7R RTC_BKP7R_Msk
lypinator 0:bb348c97df44 10843
lypinator 0:bb348c97df44 10844 /******************** Bits definition for RTC_BKP8R register ****************/
lypinator 0:bb348c97df44 10845 #define RTC_BKP8R_Pos (0U)
lypinator 0:bb348c97df44 10846 #define RTC_BKP8R_Msk (0xFFFFFFFFU << RTC_BKP8R_Pos) /*!< 0xFFFFFFFF */
lypinator 0:bb348c97df44 10847 #define RTC_BKP8R RTC_BKP8R_Msk
lypinator 0:bb348c97df44 10848
lypinator 0:bb348c97df44 10849 /******************** Bits definition for RTC_BKP9R register ****************/
lypinator 0:bb348c97df44 10850 #define RTC_BKP9R_Pos (0U)
lypinator 0:bb348c97df44 10851 #define RTC_BKP9R_Msk (0xFFFFFFFFU << RTC_BKP9R_Pos) /*!< 0xFFFFFFFF */
lypinator 0:bb348c97df44 10852 #define RTC_BKP9R RTC_BKP9R_Msk
lypinator 0:bb348c97df44 10853
lypinator 0:bb348c97df44 10854 /******************** Bits definition for RTC_BKP10R register ***************/
lypinator 0:bb348c97df44 10855 #define RTC_BKP10R_Pos (0U)
lypinator 0:bb348c97df44 10856 #define RTC_BKP10R_Msk (0xFFFFFFFFU << RTC_BKP10R_Pos) /*!< 0xFFFFFFFF */
lypinator 0:bb348c97df44 10857 #define RTC_BKP10R RTC_BKP10R_Msk
lypinator 0:bb348c97df44 10858
lypinator 0:bb348c97df44 10859 /******************** Bits definition for RTC_BKP11R register ***************/
lypinator 0:bb348c97df44 10860 #define RTC_BKP11R_Pos (0U)
lypinator 0:bb348c97df44 10861 #define RTC_BKP11R_Msk (0xFFFFFFFFU << RTC_BKP11R_Pos) /*!< 0xFFFFFFFF */
lypinator 0:bb348c97df44 10862 #define RTC_BKP11R RTC_BKP11R_Msk
lypinator 0:bb348c97df44 10863
lypinator 0:bb348c97df44 10864 /******************** Bits definition for RTC_BKP12R register ***************/
lypinator 0:bb348c97df44 10865 #define RTC_BKP12R_Pos (0U)
lypinator 0:bb348c97df44 10866 #define RTC_BKP12R_Msk (0xFFFFFFFFU << RTC_BKP12R_Pos) /*!< 0xFFFFFFFF */
lypinator 0:bb348c97df44 10867 #define RTC_BKP12R RTC_BKP12R_Msk
lypinator 0:bb348c97df44 10868
lypinator 0:bb348c97df44 10869 /******************** Bits definition for RTC_BKP13R register ***************/
lypinator 0:bb348c97df44 10870 #define RTC_BKP13R_Pos (0U)
lypinator 0:bb348c97df44 10871 #define RTC_BKP13R_Msk (0xFFFFFFFFU << RTC_BKP13R_Pos) /*!< 0xFFFFFFFF */
lypinator 0:bb348c97df44 10872 #define RTC_BKP13R RTC_BKP13R_Msk
lypinator 0:bb348c97df44 10873
lypinator 0:bb348c97df44 10874 /******************** Bits definition for RTC_BKP14R register ***************/
lypinator 0:bb348c97df44 10875 #define RTC_BKP14R_Pos (0U)
lypinator 0:bb348c97df44 10876 #define RTC_BKP14R_Msk (0xFFFFFFFFU << RTC_BKP14R_Pos) /*!< 0xFFFFFFFF */
lypinator 0:bb348c97df44 10877 #define RTC_BKP14R RTC_BKP14R_Msk
lypinator 0:bb348c97df44 10878
lypinator 0:bb348c97df44 10879 /******************** Bits definition for RTC_BKP15R register ***************/
lypinator 0:bb348c97df44 10880 #define RTC_BKP15R_Pos (0U)
lypinator 0:bb348c97df44 10881 #define RTC_BKP15R_Msk (0xFFFFFFFFU << RTC_BKP15R_Pos) /*!< 0xFFFFFFFF */
lypinator 0:bb348c97df44 10882 #define RTC_BKP15R RTC_BKP15R_Msk
lypinator 0:bb348c97df44 10883
lypinator 0:bb348c97df44 10884 /******************** Bits definition for RTC_BKP16R register ***************/
lypinator 0:bb348c97df44 10885 #define RTC_BKP16R_Pos (0U)
lypinator 0:bb348c97df44 10886 #define RTC_BKP16R_Msk (0xFFFFFFFFU << RTC_BKP16R_Pos) /*!< 0xFFFFFFFF */
lypinator 0:bb348c97df44 10887 #define RTC_BKP16R RTC_BKP16R_Msk
lypinator 0:bb348c97df44 10888
lypinator 0:bb348c97df44 10889 /******************** Bits definition for RTC_BKP17R register ***************/
lypinator 0:bb348c97df44 10890 #define RTC_BKP17R_Pos (0U)
lypinator 0:bb348c97df44 10891 #define RTC_BKP17R_Msk (0xFFFFFFFFU << RTC_BKP17R_Pos) /*!< 0xFFFFFFFF */
lypinator 0:bb348c97df44 10892 #define RTC_BKP17R RTC_BKP17R_Msk
lypinator 0:bb348c97df44 10893
lypinator 0:bb348c97df44 10894 /******************** Bits definition for RTC_BKP18R register ***************/
lypinator 0:bb348c97df44 10895 #define RTC_BKP18R_Pos (0U)
lypinator 0:bb348c97df44 10896 #define RTC_BKP18R_Msk (0xFFFFFFFFU << RTC_BKP18R_Pos) /*!< 0xFFFFFFFF */
lypinator 0:bb348c97df44 10897 #define RTC_BKP18R RTC_BKP18R_Msk
lypinator 0:bb348c97df44 10898
lypinator 0:bb348c97df44 10899 /******************** Bits definition for RTC_BKP19R register ***************/
lypinator 0:bb348c97df44 10900 #define RTC_BKP19R_Pos (0U)
lypinator 0:bb348c97df44 10901 #define RTC_BKP19R_Msk (0xFFFFFFFFU << RTC_BKP19R_Pos) /*!< 0xFFFFFFFF */
lypinator 0:bb348c97df44 10902 #define RTC_BKP19R RTC_BKP19R_Msk
lypinator 0:bb348c97df44 10903
lypinator 0:bb348c97df44 10904 /******************** Number of backup registers ******************************/
lypinator 0:bb348c97df44 10905 #define RTC_BKP_NUMBER 0x000000014U
lypinator 0:bb348c97df44 10906
lypinator 0:bb348c97df44 10907
lypinator 0:bb348c97df44 10908 /******************************************************************************/
lypinator 0:bb348c97df44 10909 /* */
lypinator 0:bb348c97df44 10910 /* SD host Interface */
lypinator 0:bb348c97df44 10911 /* */
lypinator 0:bb348c97df44 10912 /******************************************************************************/
lypinator 0:bb348c97df44 10913 /****************** Bit definition for SDIO_POWER register ******************/
lypinator 0:bb348c97df44 10914 #define SDIO_POWER_PWRCTRL_Pos (0U)
lypinator 0:bb348c97df44 10915 #define SDIO_POWER_PWRCTRL_Msk (0x3U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x00000003 */
lypinator 0:bb348c97df44 10916 #define SDIO_POWER_PWRCTRL SDIO_POWER_PWRCTRL_Msk /*!<PWRCTRL[1:0] bits (Power supply control bits) */
lypinator 0:bb348c97df44 10917 #define SDIO_POWER_PWRCTRL_0 (0x1U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x01 */
lypinator 0:bb348c97df44 10918 #define SDIO_POWER_PWRCTRL_1 (0x2U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x02 */
lypinator 0:bb348c97df44 10919
lypinator 0:bb348c97df44 10920 /****************** Bit definition for SDIO_CLKCR register ******************/
lypinator 0:bb348c97df44 10921 #define SDIO_CLKCR_CLKDIV_Pos (0U)
lypinator 0:bb348c97df44 10922 #define SDIO_CLKCR_CLKDIV_Msk (0xFFU << SDIO_CLKCR_CLKDIV_Pos) /*!< 0x000000FF */
lypinator 0:bb348c97df44 10923 #define SDIO_CLKCR_CLKDIV SDIO_CLKCR_CLKDIV_Msk /*!<Clock divide factor */
lypinator 0:bb348c97df44 10924 #define SDIO_CLKCR_CLKEN_Pos (8U)
lypinator 0:bb348c97df44 10925 #define SDIO_CLKCR_CLKEN_Msk (0x1U << SDIO_CLKCR_CLKEN_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 10926 #define SDIO_CLKCR_CLKEN SDIO_CLKCR_CLKEN_Msk /*!<Clock enable bit */
lypinator 0:bb348c97df44 10927 #define SDIO_CLKCR_PWRSAV_Pos (9U)
lypinator 0:bb348c97df44 10928 #define SDIO_CLKCR_PWRSAV_Msk (0x1U << SDIO_CLKCR_PWRSAV_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 10929 #define SDIO_CLKCR_PWRSAV SDIO_CLKCR_PWRSAV_Msk /*!<Power saving configuration bit */
lypinator 0:bb348c97df44 10930 #define SDIO_CLKCR_BYPASS_Pos (10U)
lypinator 0:bb348c97df44 10931 #define SDIO_CLKCR_BYPASS_Msk (0x1U << SDIO_CLKCR_BYPASS_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 10932 #define SDIO_CLKCR_BYPASS SDIO_CLKCR_BYPASS_Msk /*!<Clock divider bypass enable bit */
lypinator 0:bb348c97df44 10933
lypinator 0:bb348c97df44 10934 #define SDIO_CLKCR_WIDBUS_Pos (11U)
lypinator 0:bb348c97df44 10935 #define SDIO_CLKCR_WIDBUS_Msk (0x3U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x00001800 */
lypinator 0:bb348c97df44 10936 #define SDIO_CLKCR_WIDBUS SDIO_CLKCR_WIDBUS_Msk /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
lypinator 0:bb348c97df44 10937 #define SDIO_CLKCR_WIDBUS_0 (0x1U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x0800 */
lypinator 0:bb348c97df44 10938 #define SDIO_CLKCR_WIDBUS_1 (0x2U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x1000 */
lypinator 0:bb348c97df44 10939
lypinator 0:bb348c97df44 10940 #define SDIO_CLKCR_NEGEDGE_Pos (13U)
lypinator 0:bb348c97df44 10941 #define SDIO_CLKCR_NEGEDGE_Msk (0x1U << SDIO_CLKCR_NEGEDGE_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 10942 #define SDIO_CLKCR_NEGEDGE SDIO_CLKCR_NEGEDGE_Msk /*!<SDIO_CK dephasing selection bit */
lypinator 0:bb348c97df44 10943 #define SDIO_CLKCR_HWFC_EN_Pos (14U)
lypinator 0:bb348c97df44 10944 #define SDIO_CLKCR_HWFC_EN_Msk (0x1U << SDIO_CLKCR_HWFC_EN_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 10945 #define SDIO_CLKCR_HWFC_EN SDIO_CLKCR_HWFC_EN_Msk /*!<HW Flow Control enable */
lypinator 0:bb348c97df44 10946
lypinator 0:bb348c97df44 10947 /******************* Bit definition for SDIO_ARG register *******************/
lypinator 0:bb348c97df44 10948 #define SDIO_ARG_CMDARG_Pos (0U)
lypinator 0:bb348c97df44 10949 #define SDIO_ARG_CMDARG_Msk (0xFFFFFFFFU << SDIO_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */
lypinator 0:bb348c97df44 10950 #define SDIO_ARG_CMDARG SDIO_ARG_CMDARG_Msk /*!<Command argument */
lypinator 0:bb348c97df44 10951
lypinator 0:bb348c97df44 10952 /******************* Bit definition for SDIO_CMD register *******************/
lypinator 0:bb348c97df44 10953 #define SDIO_CMD_CMDINDEX_Pos (0U)
lypinator 0:bb348c97df44 10954 #define SDIO_CMD_CMDINDEX_Msk (0x3FU << SDIO_CMD_CMDINDEX_Pos) /*!< 0x0000003F */
lypinator 0:bb348c97df44 10955 #define SDIO_CMD_CMDINDEX SDIO_CMD_CMDINDEX_Msk /*!<Command Index */
lypinator 0:bb348c97df44 10956
lypinator 0:bb348c97df44 10957 #define SDIO_CMD_WAITRESP_Pos (6U)
lypinator 0:bb348c97df44 10958 #define SDIO_CMD_WAITRESP_Msk (0x3U << SDIO_CMD_WAITRESP_Pos) /*!< 0x000000C0 */
lypinator 0:bb348c97df44 10959 #define SDIO_CMD_WAITRESP SDIO_CMD_WAITRESP_Msk /*!<WAITRESP[1:0] bits (Wait for response bits) */
lypinator 0:bb348c97df44 10960 #define SDIO_CMD_WAITRESP_0 (0x1U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0040 */
lypinator 0:bb348c97df44 10961 #define SDIO_CMD_WAITRESP_1 (0x2U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0080 */
lypinator 0:bb348c97df44 10962
lypinator 0:bb348c97df44 10963 #define SDIO_CMD_WAITINT_Pos (8U)
lypinator 0:bb348c97df44 10964 #define SDIO_CMD_WAITINT_Msk (0x1U << SDIO_CMD_WAITINT_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 10965 #define SDIO_CMD_WAITINT SDIO_CMD_WAITINT_Msk /*!<CPSM Waits for Interrupt Request */
lypinator 0:bb348c97df44 10966 #define SDIO_CMD_WAITPEND_Pos (9U)
lypinator 0:bb348c97df44 10967 #define SDIO_CMD_WAITPEND_Msk (0x1U << SDIO_CMD_WAITPEND_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 10968 #define SDIO_CMD_WAITPEND SDIO_CMD_WAITPEND_Msk /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
lypinator 0:bb348c97df44 10969 #define SDIO_CMD_CPSMEN_Pos (10U)
lypinator 0:bb348c97df44 10970 #define SDIO_CMD_CPSMEN_Msk (0x1U << SDIO_CMD_CPSMEN_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 10971 #define SDIO_CMD_CPSMEN SDIO_CMD_CPSMEN_Msk /*!<Command path state machine (CPSM) Enable bit */
lypinator 0:bb348c97df44 10972 #define SDIO_CMD_SDIOSUSPEND_Pos (11U)
lypinator 0:bb348c97df44 10973 #define SDIO_CMD_SDIOSUSPEND_Msk (0x1U << SDIO_CMD_SDIOSUSPEND_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 10974 #define SDIO_CMD_SDIOSUSPEND SDIO_CMD_SDIOSUSPEND_Msk /*!<SD I/O suspend command */
lypinator 0:bb348c97df44 10975
lypinator 0:bb348c97df44 10976 /***************** Bit definition for SDIO_RESPCMD register *****************/
lypinator 0:bb348c97df44 10977 #define SDIO_RESPCMD_RESPCMD_Pos (0U)
lypinator 0:bb348c97df44 10978 #define SDIO_RESPCMD_RESPCMD_Msk (0x3FU << SDIO_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */
lypinator 0:bb348c97df44 10979 #define SDIO_RESPCMD_RESPCMD SDIO_RESPCMD_RESPCMD_Msk /*!<Response command index */
lypinator 0:bb348c97df44 10980
lypinator 0:bb348c97df44 10981 /****************** Bit definition for SDIO_RESP0 register ******************/
lypinator 0:bb348c97df44 10982 #define SDIO_RESP0_CARDSTATUS0_Pos (0U)
lypinator 0:bb348c97df44 10983 #define SDIO_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFU << SDIO_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */
lypinator 0:bb348c97df44 10984 #define SDIO_RESP0_CARDSTATUS0 SDIO_RESP0_CARDSTATUS0_Msk /*!<Card Status */
lypinator 0:bb348c97df44 10985
lypinator 0:bb348c97df44 10986 /****************** Bit definition for SDIO_RESP1 register ******************/
lypinator 0:bb348c97df44 10987 #define SDIO_RESP1_CARDSTATUS1_Pos (0U)
lypinator 0:bb348c97df44 10988 #define SDIO_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFU << SDIO_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
lypinator 0:bb348c97df44 10989 #define SDIO_RESP1_CARDSTATUS1 SDIO_RESP1_CARDSTATUS1_Msk /*!<Card Status */
lypinator 0:bb348c97df44 10990
lypinator 0:bb348c97df44 10991 /****************** Bit definition for SDIO_RESP2 register ******************/
lypinator 0:bb348c97df44 10992 #define SDIO_RESP2_CARDSTATUS2_Pos (0U)
lypinator 0:bb348c97df44 10993 #define SDIO_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFU << SDIO_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
lypinator 0:bb348c97df44 10994 #define SDIO_RESP2_CARDSTATUS2 SDIO_RESP2_CARDSTATUS2_Msk /*!<Card Status */
lypinator 0:bb348c97df44 10995
lypinator 0:bb348c97df44 10996 /****************** Bit definition for SDIO_RESP3 register ******************/
lypinator 0:bb348c97df44 10997 #define SDIO_RESP3_CARDSTATUS3_Pos (0U)
lypinator 0:bb348c97df44 10998 #define SDIO_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFU << SDIO_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
lypinator 0:bb348c97df44 10999 #define SDIO_RESP3_CARDSTATUS3 SDIO_RESP3_CARDSTATUS3_Msk /*!<Card Status */
lypinator 0:bb348c97df44 11000
lypinator 0:bb348c97df44 11001 /****************** Bit definition for SDIO_RESP4 register ******************/
lypinator 0:bb348c97df44 11002 #define SDIO_RESP4_CARDSTATUS4_Pos (0U)
lypinator 0:bb348c97df44 11003 #define SDIO_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFU << SDIO_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
lypinator 0:bb348c97df44 11004 #define SDIO_RESP4_CARDSTATUS4 SDIO_RESP4_CARDSTATUS4_Msk /*!<Card Status */
lypinator 0:bb348c97df44 11005
lypinator 0:bb348c97df44 11006 /****************** Bit definition for SDIO_DTIMER register *****************/
lypinator 0:bb348c97df44 11007 #define SDIO_DTIMER_DATATIME_Pos (0U)
lypinator 0:bb348c97df44 11008 #define SDIO_DTIMER_DATATIME_Msk (0xFFFFFFFFU << SDIO_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
lypinator 0:bb348c97df44 11009 #define SDIO_DTIMER_DATATIME SDIO_DTIMER_DATATIME_Msk /*!<Data timeout period. */
lypinator 0:bb348c97df44 11010
lypinator 0:bb348c97df44 11011 /****************** Bit definition for SDIO_DLEN register *******************/
lypinator 0:bb348c97df44 11012 #define SDIO_DLEN_DATALENGTH_Pos (0U)
lypinator 0:bb348c97df44 11013 #define SDIO_DLEN_DATALENGTH_Msk (0x1FFFFFFU << SDIO_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
lypinator 0:bb348c97df44 11014 #define SDIO_DLEN_DATALENGTH SDIO_DLEN_DATALENGTH_Msk /*!<Data length value */
lypinator 0:bb348c97df44 11015
lypinator 0:bb348c97df44 11016 /****************** Bit definition for SDIO_DCTRL register ******************/
lypinator 0:bb348c97df44 11017 #define SDIO_DCTRL_DTEN_Pos (0U)
lypinator 0:bb348c97df44 11018 #define SDIO_DCTRL_DTEN_Msk (0x1U << SDIO_DCTRL_DTEN_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 11019 #define SDIO_DCTRL_DTEN SDIO_DCTRL_DTEN_Msk /*!<Data transfer enabled bit */
lypinator 0:bb348c97df44 11020 #define SDIO_DCTRL_DTDIR_Pos (1U)
lypinator 0:bb348c97df44 11021 #define SDIO_DCTRL_DTDIR_Msk (0x1U << SDIO_DCTRL_DTDIR_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 11022 #define SDIO_DCTRL_DTDIR SDIO_DCTRL_DTDIR_Msk /*!<Data transfer direction selection */
lypinator 0:bb348c97df44 11023 #define SDIO_DCTRL_DTMODE_Pos (2U)
lypinator 0:bb348c97df44 11024 #define SDIO_DCTRL_DTMODE_Msk (0x1U << SDIO_DCTRL_DTMODE_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 11025 #define SDIO_DCTRL_DTMODE SDIO_DCTRL_DTMODE_Msk /*!<Data transfer mode selection */
lypinator 0:bb348c97df44 11026 #define SDIO_DCTRL_DMAEN_Pos (3U)
lypinator 0:bb348c97df44 11027 #define SDIO_DCTRL_DMAEN_Msk (0x1U << SDIO_DCTRL_DMAEN_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 11028 #define SDIO_DCTRL_DMAEN SDIO_DCTRL_DMAEN_Msk /*!<DMA enabled bit */
lypinator 0:bb348c97df44 11029
lypinator 0:bb348c97df44 11030 #define SDIO_DCTRL_DBLOCKSIZE_Pos (4U)
lypinator 0:bb348c97df44 11031 #define SDIO_DCTRL_DBLOCKSIZE_Msk (0xFU << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */
lypinator 0:bb348c97df44 11032 #define SDIO_DCTRL_DBLOCKSIZE SDIO_DCTRL_DBLOCKSIZE_Msk /*!<DBLOCKSIZE[3:0] bits (Data block size) */
lypinator 0:bb348c97df44 11033 #define SDIO_DCTRL_DBLOCKSIZE_0 (0x1U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0010 */
lypinator 0:bb348c97df44 11034 #define SDIO_DCTRL_DBLOCKSIZE_1 (0x2U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0020 */
lypinator 0:bb348c97df44 11035 #define SDIO_DCTRL_DBLOCKSIZE_2 (0x4U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0040 */
lypinator 0:bb348c97df44 11036 #define SDIO_DCTRL_DBLOCKSIZE_3 (0x8U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0080 */
lypinator 0:bb348c97df44 11037
lypinator 0:bb348c97df44 11038 #define SDIO_DCTRL_RWSTART_Pos (8U)
lypinator 0:bb348c97df44 11039 #define SDIO_DCTRL_RWSTART_Msk (0x1U << SDIO_DCTRL_RWSTART_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 11040 #define SDIO_DCTRL_RWSTART SDIO_DCTRL_RWSTART_Msk /*!<Read wait start */
lypinator 0:bb348c97df44 11041 #define SDIO_DCTRL_RWSTOP_Pos (9U)
lypinator 0:bb348c97df44 11042 #define SDIO_DCTRL_RWSTOP_Msk (0x1U << SDIO_DCTRL_RWSTOP_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 11043 #define SDIO_DCTRL_RWSTOP SDIO_DCTRL_RWSTOP_Msk /*!<Read wait stop */
lypinator 0:bb348c97df44 11044 #define SDIO_DCTRL_RWMOD_Pos (10U)
lypinator 0:bb348c97df44 11045 #define SDIO_DCTRL_RWMOD_Msk (0x1U << SDIO_DCTRL_RWMOD_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 11046 #define SDIO_DCTRL_RWMOD SDIO_DCTRL_RWMOD_Msk /*!<Read wait mode */
lypinator 0:bb348c97df44 11047 #define SDIO_DCTRL_SDIOEN_Pos (11U)
lypinator 0:bb348c97df44 11048 #define SDIO_DCTRL_SDIOEN_Msk (0x1U << SDIO_DCTRL_SDIOEN_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 11049 #define SDIO_DCTRL_SDIOEN SDIO_DCTRL_SDIOEN_Msk /*!<SD I/O enable functions */
lypinator 0:bb348c97df44 11050
lypinator 0:bb348c97df44 11051 /****************** Bit definition for SDIO_DCOUNT register *****************/
lypinator 0:bb348c97df44 11052 #define SDIO_DCOUNT_DATACOUNT_Pos (0U)
lypinator 0:bb348c97df44 11053 #define SDIO_DCOUNT_DATACOUNT_Msk (0x1FFFFFFU << SDIO_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
lypinator 0:bb348c97df44 11054 #define SDIO_DCOUNT_DATACOUNT SDIO_DCOUNT_DATACOUNT_Msk /*!<Data count value */
lypinator 0:bb348c97df44 11055
lypinator 0:bb348c97df44 11056 /****************** Bit definition for SDIO_STA register ********************/
lypinator 0:bb348c97df44 11057 #define SDIO_STA_CCRCFAIL_Pos (0U)
lypinator 0:bb348c97df44 11058 #define SDIO_STA_CCRCFAIL_Msk (0x1U << SDIO_STA_CCRCFAIL_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 11059 #define SDIO_STA_CCRCFAIL SDIO_STA_CCRCFAIL_Msk /*!<Command response received (CRC check failed) */
lypinator 0:bb348c97df44 11060 #define SDIO_STA_DCRCFAIL_Pos (1U)
lypinator 0:bb348c97df44 11061 #define SDIO_STA_DCRCFAIL_Msk (0x1U << SDIO_STA_DCRCFAIL_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 11062 #define SDIO_STA_DCRCFAIL SDIO_STA_DCRCFAIL_Msk /*!<Data block sent/received (CRC check failed) */
lypinator 0:bb348c97df44 11063 #define SDIO_STA_CTIMEOUT_Pos (2U)
lypinator 0:bb348c97df44 11064 #define SDIO_STA_CTIMEOUT_Msk (0x1U << SDIO_STA_CTIMEOUT_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 11065 #define SDIO_STA_CTIMEOUT SDIO_STA_CTIMEOUT_Msk /*!<Command response timeout */
lypinator 0:bb348c97df44 11066 #define SDIO_STA_DTIMEOUT_Pos (3U)
lypinator 0:bb348c97df44 11067 #define SDIO_STA_DTIMEOUT_Msk (0x1U << SDIO_STA_DTIMEOUT_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 11068 #define SDIO_STA_DTIMEOUT SDIO_STA_DTIMEOUT_Msk /*!<Data timeout */
lypinator 0:bb348c97df44 11069 #define SDIO_STA_TXUNDERR_Pos (4U)
lypinator 0:bb348c97df44 11070 #define SDIO_STA_TXUNDERR_Msk (0x1U << SDIO_STA_TXUNDERR_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 11071 #define SDIO_STA_TXUNDERR SDIO_STA_TXUNDERR_Msk /*!<Transmit FIFO underrun error */
lypinator 0:bb348c97df44 11072 #define SDIO_STA_RXOVERR_Pos (5U)
lypinator 0:bb348c97df44 11073 #define SDIO_STA_RXOVERR_Msk (0x1U << SDIO_STA_RXOVERR_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 11074 #define SDIO_STA_RXOVERR SDIO_STA_RXOVERR_Msk /*!<Received FIFO overrun error */
lypinator 0:bb348c97df44 11075 #define SDIO_STA_CMDREND_Pos (6U)
lypinator 0:bb348c97df44 11076 #define SDIO_STA_CMDREND_Msk (0x1U << SDIO_STA_CMDREND_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 11077 #define SDIO_STA_CMDREND SDIO_STA_CMDREND_Msk /*!<Command response received (CRC check passed) */
lypinator 0:bb348c97df44 11078 #define SDIO_STA_CMDSENT_Pos (7U)
lypinator 0:bb348c97df44 11079 #define SDIO_STA_CMDSENT_Msk (0x1U << SDIO_STA_CMDSENT_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 11080 #define SDIO_STA_CMDSENT SDIO_STA_CMDSENT_Msk /*!<Command sent (no response required) */
lypinator 0:bb348c97df44 11081 #define SDIO_STA_DATAEND_Pos (8U)
lypinator 0:bb348c97df44 11082 #define SDIO_STA_DATAEND_Msk (0x1U << SDIO_STA_DATAEND_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 11083 #define SDIO_STA_DATAEND SDIO_STA_DATAEND_Msk /*!<Data end (data counter, SDIDCOUNT, is zero) */
lypinator 0:bb348c97df44 11084 #define SDIO_STA_DBCKEND_Pos (10U)
lypinator 0:bb348c97df44 11085 #define SDIO_STA_DBCKEND_Msk (0x1U << SDIO_STA_DBCKEND_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 11086 #define SDIO_STA_DBCKEND SDIO_STA_DBCKEND_Msk /*!<Data block sent/received (CRC check passed) */
lypinator 0:bb348c97df44 11087 #define SDIO_STA_CMDACT_Pos (11U)
lypinator 0:bb348c97df44 11088 #define SDIO_STA_CMDACT_Msk (0x1U << SDIO_STA_CMDACT_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 11089 #define SDIO_STA_CMDACT SDIO_STA_CMDACT_Msk /*!<Command transfer in progress */
lypinator 0:bb348c97df44 11090 #define SDIO_STA_TXACT_Pos (12U)
lypinator 0:bb348c97df44 11091 #define SDIO_STA_TXACT_Msk (0x1U << SDIO_STA_TXACT_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 11092 #define SDIO_STA_TXACT SDIO_STA_TXACT_Msk /*!<Data transmit in progress */
lypinator 0:bb348c97df44 11093 #define SDIO_STA_RXACT_Pos (13U)
lypinator 0:bb348c97df44 11094 #define SDIO_STA_RXACT_Msk (0x1U << SDIO_STA_RXACT_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 11095 #define SDIO_STA_RXACT SDIO_STA_RXACT_Msk /*!<Data receive in progress */
lypinator 0:bb348c97df44 11096 #define SDIO_STA_TXFIFOHE_Pos (14U)
lypinator 0:bb348c97df44 11097 #define SDIO_STA_TXFIFOHE_Msk (0x1U << SDIO_STA_TXFIFOHE_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 11098 #define SDIO_STA_TXFIFOHE SDIO_STA_TXFIFOHE_Msk /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
lypinator 0:bb348c97df44 11099 #define SDIO_STA_RXFIFOHF_Pos (15U)
lypinator 0:bb348c97df44 11100 #define SDIO_STA_RXFIFOHF_Msk (0x1U << SDIO_STA_RXFIFOHF_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 11101 #define SDIO_STA_RXFIFOHF SDIO_STA_RXFIFOHF_Msk /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
lypinator 0:bb348c97df44 11102 #define SDIO_STA_TXFIFOF_Pos (16U)
lypinator 0:bb348c97df44 11103 #define SDIO_STA_TXFIFOF_Msk (0x1U << SDIO_STA_TXFIFOF_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 11104 #define SDIO_STA_TXFIFOF SDIO_STA_TXFIFOF_Msk /*!<Transmit FIFO full */
lypinator 0:bb348c97df44 11105 #define SDIO_STA_RXFIFOF_Pos (17U)
lypinator 0:bb348c97df44 11106 #define SDIO_STA_RXFIFOF_Msk (0x1U << SDIO_STA_RXFIFOF_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 11107 #define SDIO_STA_RXFIFOF SDIO_STA_RXFIFOF_Msk /*!<Receive FIFO full */
lypinator 0:bb348c97df44 11108 #define SDIO_STA_TXFIFOE_Pos (18U)
lypinator 0:bb348c97df44 11109 #define SDIO_STA_TXFIFOE_Msk (0x1U << SDIO_STA_TXFIFOE_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 11110 #define SDIO_STA_TXFIFOE SDIO_STA_TXFIFOE_Msk /*!<Transmit FIFO empty */
lypinator 0:bb348c97df44 11111 #define SDIO_STA_RXFIFOE_Pos (19U)
lypinator 0:bb348c97df44 11112 #define SDIO_STA_RXFIFOE_Msk (0x1U << SDIO_STA_RXFIFOE_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 11113 #define SDIO_STA_RXFIFOE SDIO_STA_RXFIFOE_Msk /*!<Receive FIFO empty */
lypinator 0:bb348c97df44 11114 #define SDIO_STA_TXDAVL_Pos (20U)
lypinator 0:bb348c97df44 11115 #define SDIO_STA_TXDAVL_Msk (0x1U << SDIO_STA_TXDAVL_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 11116 #define SDIO_STA_TXDAVL SDIO_STA_TXDAVL_Msk /*!<Data available in transmit FIFO */
lypinator 0:bb348c97df44 11117 #define SDIO_STA_RXDAVL_Pos (21U)
lypinator 0:bb348c97df44 11118 #define SDIO_STA_RXDAVL_Msk (0x1U << SDIO_STA_RXDAVL_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 11119 #define SDIO_STA_RXDAVL SDIO_STA_RXDAVL_Msk /*!<Data available in receive FIFO */
lypinator 0:bb348c97df44 11120 #define SDIO_STA_SDIOIT_Pos (22U)
lypinator 0:bb348c97df44 11121 #define SDIO_STA_SDIOIT_Msk (0x1U << SDIO_STA_SDIOIT_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 11122 #define SDIO_STA_SDIOIT SDIO_STA_SDIOIT_Msk /*!<SDIO interrupt received */
lypinator 0:bb348c97df44 11123
lypinator 0:bb348c97df44 11124 /******************* Bit definition for SDIO_ICR register *******************/
lypinator 0:bb348c97df44 11125 #define SDIO_ICR_CCRCFAILC_Pos (0U)
lypinator 0:bb348c97df44 11126 #define SDIO_ICR_CCRCFAILC_Msk (0x1U << SDIO_ICR_CCRCFAILC_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 11127 #define SDIO_ICR_CCRCFAILC SDIO_ICR_CCRCFAILC_Msk /*!<CCRCFAIL flag clear bit */
lypinator 0:bb348c97df44 11128 #define SDIO_ICR_DCRCFAILC_Pos (1U)
lypinator 0:bb348c97df44 11129 #define SDIO_ICR_DCRCFAILC_Msk (0x1U << SDIO_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 11130 #define SDIO_ICR_DCRCFAILC SDIO_ICR_DCRCFAILC_Msk /*!<DCRCFAIL flag clear bit */
lypinator 0:bb348c97df44 11131 #define SDIO_ICR_CTIMEOUTC_Pos (2U)
lypinator 0:bb348c97df44 11132 #define SDIO_ICR_CTIMEOUTC_Msk (0x1U << SDIO_ICR_CTIMEOUTC_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 11133 #define SDIO_ICR_CTIMEOUTC SDIO_ICR_CTIMEOUTC_Msk /*!<CTIMEOUT flag clear bit */
lypinator 0:bb348c97df44 11134 #define SDIO_ICR_DTIMEOUTC_Pos (3U)
lypinator 0:bb348c97df44 11135 #define SDIO_ICR_DTIMEOUTC_Msk (0x1U << SDIO_ICR_DTIMEOUTC_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 11136 #define SDIO_ICR_DTIMEOUTC SDIO_ICR_DTIMEOUTC_Msk /*!<DTIMEOUT flag clear bit */
lypinator 0:bb348c97df44 11137 #define SDIO_ICR_TXUNDERRC_Pos (4U)
lypinator 0:bb348c97df44 11138 #define SDIO_ICR_TXUNDERRC_Msk (0x1U << SDIO_ICR_TXUNDERRC_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 11139 #define SDIO_ICR_TXUNDERRC SDIO_ICR_TXUNDERRC_Msk /*!<TXUNDERR flag clear bit */
lypinator 0:bb348c97df44 11140 #define SDIO_ICR_RXOVERRC_Pos (5U)
lypinator 0:bb348c97df44 11141 #define SDIO_ICR_RXOVERRC_Msk (0x1U << SDIO_ICR_RXOVERRC_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 11142 #define SDIO_ICR_RXOVERRC SDIO_ICR_RXOVERRC_Msk /*!<RXOVERR flag clear bit */
lypinator 0:bb348c97df44 11143 #define SDIO_ICR_CMDRENDC_Pos (6U)
lypinator 0:bb348c97df44 11144 #define SDIO_ICR_CMDRENDC_Msk (0x1U << SDIO_ICR_CMDRENDC_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 11145 #define SDIO_ICR_CMDRENDC SDIO_ICR_CMDRENDC_Msk /*!<CMDREND flag clear bit */
lypinator 0:bb348c97df44 11146 #define SDIO_ICR_CMDSENTC_Pos (7U)
lypinator 0:bb348c97df44 11147 #define SDIO_ICR_CMDSENTC_Msk (0x1U << SDIO_ICR_CMDSENTC_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 11148 #define SDIO_ICR_CMDSENTC SDIO_ICR_CMDSENTC_Msk /*!<CMDSENT flag clear bit */
lypinator 0:bb348c97df44 11149 #define SDIO_ICR_DATAENDC_Pos (8U)
lypinator 0:bb348c97df44 11150 #define SDIO_ICR_DATAENDC_Msk (0x1U << SDIO_ICR_DATAENDC_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 11151 #define SDIO_ICR_DATAENDC SDIO_ICR_DATAENDC_Msk /*!<DATAEND flag clear bit */
lypinator 0:bb348c97df44 11152 #define SDIO_ICR_DBCKENDC_Pos (10U)
lypinator 0:bb348c97df44 11153 #define SDIO_ICR_DBCKENDC_Msk (0x1U << SDIO_ICR_DBCKENDC_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 11154 #define SDIO_ICR_DBCKENDC SDIO_ICR_DBCKENDC_Msk /*!<DBCKEND flag clear bit */
lypinator 0:bb348c97df44 11155 #define SDIO_ICR_SDIOITC_Pos (22U)
lypinator 0:bb348c97df44 11156 #define SDIO_ICR_SDIOITC_Msk (0x1U << SDIO_ICR_SDIOITC_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 11157 #define SDIO_ICR_SDIOITC SDIO_ICR_SDIOITC_Msk /*!<SDIOIT flag clear bit */
lypinator 0:bb348c97df44 11158
lypinator 0:bb348c97df44 11159 /****************** Bit definition for SDIO_MASK register *******************/
lypinator 0:bb348c97df44 11160 #define SDIO_MASK_CCRCFAILIE_Pos (0U)
lypinator 0:bb348c97df44 11161 #define SDIO_MASK_CCRCFAILIE_Msk (0x1U << SDIO_MASK_CCRCFAILIE_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 11162 #define SDIO_MASK_CCRCFAILIE SDIO_MASK_CCRCFAILIE_Msk /*!<Command CRC Fail Interrupt Enable */
lypinator 0:bb348c97df44 11163 #define SDIO_MASK_DCRCFAILIE_Pos (1U)
lypinator 0:bb348c97df44 11164 #define SDIO_MASK_DCRCFAILIE_Msk (0x1U << SDIO_MASK_DCRCFAILIE_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 11165 #define SDIO_MASK_DCRCFAILIE SDIO_MASK_DCRCFAILIE_Msk /*!<Data CRC Fail Interrupt Enable */
lypinator 0:bb348c97df44 11166 #define SDIO_MASK_CTIMEOUTIE_Pos (2U)
lypinator 0:bb348c97df44 11167 #define SDIO_MASK_CTIMEOUTIE_Msk (0x1U << SDIO_MASK_CTIMEOUTIE_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 11168 #define SDIO_MASK_CTIMEOUTIE SDIO_MASK_CTIMEOUTIE_Msk /*!<Command TimeOut Interrupt Enable */
lypinator 0:bb348c97df44 11169 #define SDIO_MASK_DTIMEOUTIE_Pos (3U)
lypinator 0:bb348c97df44 11170 #define SDIO_MASK_DTIMEOUTIE_Msk (0x1U << SDIO_MASK_DTIMEOUTIE_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 11171 #define SDIO_MASK_DTIMEOUTIE SDIO_MASK_DTIMEOUTIE_Msk /*!<Data TimeOut Interrupt Enable */
lypinator 0:bb348c97df44 11172 #define SDIO_MASK_TXUNDERRIE_Pos (4U)
lypinator 0:bb348c97df44 11173 #define SDIO_MASK_TXUNDERRIE_Msk (0x1U << SDIO_MASK_TXUNDERRIE_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 11174 #define SDIO_MASK_TXUNDERRIE SDIO_MASK_TXUNDERRIE_Msk /*!<Tx FIFO UnderRun Error Interrupt Enable */
lypinator 0:bb348c97df44 11175 #define SDIO_MASK_RXOVERRIE_Pos (5U)
lypinator 0:bb348c97df44 11176 #define SDIO_MASK_RXOVERRIE_Msk (0x1U << SDIO_MASK_RXOVERRIE_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 11177 #define SDIO_MASK_RXOVERRIE SDIO_MASK_RXOVERRIE_Msk /*!<Rx FIFO OverRun Error Interrupt Enable */
lypinator 0:bb348c97df44 11178 #define SDIO_MASK_CMDRENDIE_Pos (6U)
lypinator 0:bb348c97df44 11179 #define SDIO_MASK_CMDRENDIE_Msk (0x1U << SDIO_MASK_CMDRENDIE_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 11180 #define SDIO_MASK_CMDRENDIE SDIO_MASK_CMDRENDIE_Msk /*!<Command Response Received Interrupt Enable */
lypinator 0:bb348c97df44 11181 #define SDIO_MASK_CMDSENTIE_Pos (7U)
lypinator 0:bb348c97df44 11182 #define SDIO_MASK_CMDSENTIE_Msk (0x1U << SDIO_MASK_CMDSENTIE_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 11183 #define SDIO_MASK_CMDSENTIE SDIO_MASK_CMDSENTIE_Msk /*!<Command Sent Interrupt Enable */
lypinator 0:bb348c97df44 11184 #define SDIO_MASK_DATAENDIE_Pos (8U)
lypinator 0:bb348c97df44 11185 #define SDIO_MASK_DATAENDIE_Msk (0x1U << SDIO_MASK_DATAENDIE_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 11186 #define SDIO_MASK_DATAENDIE SDIO_MASK_DATAENDIE_Msk /*!<Data End Interrupt Enable */
lypinator 0:bb348c97df44 11187 #define SDIO_MASK_DBCKENDIE_Pos (10U)
lypinator 0:bb348c97df44 11188 #define SDIO_MASK_DBCKENDIE_Msk (0x1U << SDIO_MASK_DBCKENDIE_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 11189 #define SDIO_MASK_DBCKENDIE SDIO_MASK_DBCKENDIE_Msk /*!<Data Block End Interrupt Enable */
lypinator 0:bb348c97df44 11190 #define SDIO_MASK_CMDACTIE_Pos (11U)
lypinator 0:bb348c97df44 11191 #define SDIO_MASK_CMDACTIE_Msk (0x1U << SDIO_MASK_CMDACTIE_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 11192 #define SDIO_MASK_CMDACTIE SDIO_MASK_CMDACTIE_Msk /*!<CCommand Acting Interrupt Enable */
lypinator 0:bb348c97df44 11193 #define SDIO_MASK_TXACTIE_Pos (12U)
lypinator 0:bb348c97df44 11194 #define SDIO_MASK_TXACTIE_Msk (0x1U << SDIO_MASK_TXACTIE_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 11195 #define SDIO_MASK_TXACTIE SDIO_MASK_TXACTIE_Msk /*!<Data Transmit Acting Interrupt Enable */
lypinator 0:bb348c97df44 11196 #define SDIO_MASK_RXACTIE_Pos (13U)
lypinator 0:bb348c97df44 11197 #define SDIO_MASK_RXACTIE_Msk (0x1U << SDIO_MASK_RXACTIE_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 11198 #define SDIO_MASK_RXACTIE SDIO_MASK_RXACTIE_Msk /*!<Data receive acting interrupt enabled */
lypinator 0:bb348c97df44 11199 #define SDIO_MASK_TXFIFOHEIE_Pos (14U)
lypinator 0:bb348c97df44 11200 #define SDIO_MASK_TXFIFOHEIE_Msk (0x1U << SDIO_MASK_TXFIFOHEIE_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 11201 #define SDIO_MASK_TXFIFOHEIE SDIO_MASK_TXFIFOHEIE_Msk /*!<Tx FIFO Half Empty interrupt Enable */
lypinator 0:bb348c97df44 11202 #define SDIO_MASK_RXFIFOHFIE_Pos (15U)
lypinator 0:bb348c97df44 11203 #define SDIO_MASK_RXFIFOHFIE_Msk (0x1U << SDIO_MASK_RXFIFOHFIE_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 11204 #define SDIO_MASK_RXFIFOHFIE SDIO_MASK_RXFIFOHFIE_Msk /*!<Rx FIFO Half Full interrupt Enable */
lypinator 0:bb348c97df44 11205 #define SDIO_MASK_TXFIFOFIE_Pos (16U)
lypinator 0:bb348c97df44 11206 #define SDIO_MASK_TXFIFOFIE_Msk (0x1U << SDIO_MASK_TXFIFOFIE_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 11207 #define SDIO_MASK_TXFIFOFIE SDIO_MASK_TXFIFOFIE_Msk /*!<Tx FIFO Full interrupt Enable */
lypinator 0:bb348c97df44 11208 #define SDIO_MASK_RXFIFOFIE_Pos (17U)
lypinator 0:bb348c97df44 11209 #define SDIO_MASK_RXFIFOFIE_Msk (0x1U << SDIO_MASK_RXFIFOFIE_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 11210 #define SDIO_MASK_RXFIFOFIE SDIO_MASK_RXFIFOFIE_Msk /*!<Rx FIFO Full interrupt Enable */
lypinator 0:bb348c97df44 11211 #define SDIO_MASK_TXFIFOEIE_Pos (18U)
lypinator 0:bb348c97df44 11212 #define SDIO_MASK_TXFIFOEIE_Msk (0x1U << SDIO_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 11213 #define SDIO_MASK_TXFIFOEIE SDIO_MASK_TXFIFOEIE_Msk /*!<Tx FIFO Empty interrupt Enable */
lypinator 0:bb348c97df44 11214 #define SDIO_MASK_RXFIFOEIE_Pos (19U)
lypinator 0:bb348c97df44 11215 #define SDIO_MASK_RXFIFOEIE_Msk (0x1U << SDIO_MASK_RXFIFOEIE_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 11216 #define SDIO_MASK_RXFIFOEIE SDIO_MASK_RXFIFOEIE_Msk /*!<Rx FIFO Empty interrupt Enable */
lypinator 0:bb348c97df44 11217 #define SDIO_MASK_TXDAVLIE_Pos (20U)
lypinator 0:bb348c97df44 11218 #define SDIO_MASK_TXDAVLIE_Msk (0x1U << SDIO_MASK_TXDAVLIE_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 11219 #define SDIO_MASK_TXDAVLIE SDIO_MASK_TXDAVLIE_Msk /*!<Data available in Tx FIFO interrupt Enable */
lypinator 0:bb348c97df44 11220 #define SDIO_MASK_RXDAVLIE_Pos (21U)
lypinator 0:bb348c97df44 11221 #define SDIO_MASK_RXDAVLIE_Msk (0x1U << SDIO_MASK_RXDAVLIE_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 11222 #define SDIO_MASK_RXDAVLIE SDIO_MASK_RXDAVLIE_Msk /*!<Data available in Rx FIFO interrupt Enable */
lypinator 0:bb348c97df44 11223 #define SDIO_MASK_SDIOITIE_Pos (22U)
lypinator 0:bb348c97df44 11224 #define SDIO_MASK_SDIOITIE_Msk (0x1U << SDIO_MASK_SDIOITIE_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 11225 #define SDIO_MASK_SDIOITIE SDIO_MASK_SDIOITIE_Msk /*!<SDIO Mode Interrupt Received interrupt Enable */
lypinator 0:bb348c97df44 11226
lypinator 0:bb348c97df44 11227 /***************** Bit definition for SDIO_FIFOCNT register *****************/
lypinator 0:bb348c97df44 11228 #define SDIO_FIFOCNT_FIFOCOUNT_Pos (0U)
lypinator 0:bb348c97df44 11229 #define SDIO_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFU << SDIO_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */
lypinator 0:bb348c97df44 11230 #define SDIO_FIFOCNT_FIFOCOUNT SDIO_FIFOCNT_FIFOCOUNT_Msk /*!<Remaining number of words to be written to or read from the FIFO */
lypinator 0:bb348c97df44 11231
lypinator 0:bb348c97df44 11232 /****************** Bit definition for SDIO_FIFO register *******************/
lypinator 0:bb348c97df44 11233 #define SDIO_FIFO_FIFODATA_Pos (0U)
lypinator 0:bb348c97df44 11234 #define SDIO_FIFO_FIFODATA_Msk (0xFFFFFFFFU << SDIO_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
lypinator 0:bb348c97df44 11235 #define SDIO_FIFO_FIFODATA SDIO_FIFO_FIFODATA_Msk /*!<Receive and transmit FIFO data */
lypinator 0:bb348c97df44 11236
lypinator 0:bb348c97df44 11237 /******************************************************************************/
lypinator 0:bb348c97df44 11238 /* */
lypinator 0:bb348c97df44 11239 /* Serial Peripheral Interface */
lypinator 0:bb348c97df44 11240 /* */
lypinator 0:bb348c97df44 11241 /******************************************************************************/
lypinator 0:bb348c97df44 11242 #define SPI_I2S_FULLDUPLEX_SUPPORT /*!< I2S Full-Duplex support */
lypinator 0:bb348c97df44 11243 #define I2S_APB1_APB2_FEATURE /*!< I2S IP's are splited between RCC APB1 and APB2 interfaces */
lypinator 0:bb348c97df44 11244
lypinator 0:bb348c97df44 11245 /******************* Bit definition for SPI_CR1 register ********************/
lypinator 0:bb348c97df44 11246 #define SPI_CR1_CPHA_Pos (0U)
lypinator 0:bb348c97df44 11247 #define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 11248 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!<Clock Phase */
lypinator 0:bb348c97df44 11249 #define SPI_CR1_CPOL_Pos (1U)
lypinator 0:bb348c97df44 11250 #define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 11251 #define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!<Clock Polarity */
lypinator 0:bb348c97df44 11252 #define SPI_CR1_MSTR_Pos (2U)
lypinator 0:bb348c97df44 11253 #define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 11254 #define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!<Master Selection */
lypinator 0:bb348c97df44 11255
lypinator 0:bb348c97df44 11256 #define SPI_CR1_BR_Pos (3U)
lypinator 0:bb348c97df44 11257 #define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /*!< 0x00000038 */
lypinator 0:bb348c97df44 11258 #define SPI_CR1_BR SPI_CR1_BR_Msk /*!<BR[2:0] bits (Baud Rate Control) */
lypinator 0:bb348c97df44 11259 #define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 11260 #define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 11261 #define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 11262
lypinator 0:bb348c97df44 11263 #define SPI_CR1_SPE_Pos (6U)
lypinator 0:bb348c97df44 11264 #define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 11265 #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!<SPI Enable */
lypinator 0:bb348c97df44 11266 #define SPI_CR1_LSBFIRST_Pos (7U)
lypinator 0:bb348c97df44 11267 #define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 11268 #define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!<Frame Format */
lypinator 0:bb348c97df44 11269 #define SPI_CR1_SSI_Pos (8U)
lypinator 0:bb348c97df44 11270 #define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 11271 #define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!<Internal slave select */
lypinator 0:bb348c97df44 11272 #define SPI_CR1_SSM_Pos (9U)
lypinator 0:bb348c97df44 11273 #define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 11274 #define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!<Software slave management */
lypinator 0:bb348c97df44 11275 #define SPI_CR1_RXONLY_Pos (10U)
lypinator 0:bb348c97df44 11276 #define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 11277 #define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!<Receive only */
lypinator 0:bb348c97df44 11278 #define SPI_CR1_DFF_Pos (11U)
lypinator 0:bb348c97df44 11279 #define SPI_CR1_DFF_Msk (0x1U << SPI_CR1_DFF_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 11280 #define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!<Data Frame Format */
lypinator 0:bb348c97df44 11281 #define SPI_CR1_CRCNEXT_Pos (12U)
lypinator 0:bb348c97df44 11282 #define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 11283 #define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!<Transmit CRC next */
lypinator 0:bb348c97df44 11284 #define SPI_CR1_CRCEN_Pos (13U)
lypinator 0:bb348c97df44 11285 #define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 11286 #define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!<Hardware CRC calculation enable */
lypinator 0:bb348c97df44 11287 #define SPI_CR1_BIDIOE_Pos (14U)
lypinator 0:bb348c97df44 11288 #define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 11289 #define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!<Output enable in bidirectional mode */
lypinator 0:bb348c97df44 11290 #define SPI_CR1_BIDIMODE_Pos (15U)
lypinator 0:bb348c97df44 11291 #define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 11292 #define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!<Bidirectional data mode enable */
lypinator 0:bb348c97df44 11293
lypinator 0:bb348c97df44 11294 /******************* Bit definition for SPI_CR2 register ********************/
lypinator 0:bb348c97df44 11295 #define SPI_CR2_RXDMAEN_Pos (0U)
lypinator 0:bb348c97df44 11296 #define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 11297 #define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!<Rx Buffer DMA Enable */
lypinator 0:bb348c97df44 11298 #define SPI_CR2_TXDMAEN_Pos (1U)
lypinator 0:bb348c97df44 11299 #define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 11300 #define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!<Tx Buffer DMA Enable */
lypinator 0:bb348c97df44 11301 #define SPI_CR2_SSOE_Pos (2U)
lypinator 0:bb348c97df44 11302 #define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 11303 #define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!<SS Output Enable */
lypinator 0:bb348c97df44 11304 #define SPI_CR2_FRF_Pos (4U)
lypinator 0:bb348c97df44 11305 #define SPI_CR2_FRF_Msk (0x1U << SPI_CR2_FRF_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 11306 #define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!<Frame Format */
lypinator 0:bb348c97df44 11307 #define SPI_CR2_ERRIE_Pos (5U)
lypinator 0:bb348c97df44 11308 #define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 11309 #define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!<Error Interrupt Enable */
lypinator 0:bb348c97df44 11310 #define SPI_CR2_RXNEIE_Pos (6U)
lypinator 0:bb348c97df44 11311 #define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 11312 #define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!<RX buffer Not Empty Interrupt Enable */
lypinator 0:bb348c97df44 11313 #define SPI_CR2_TXEIE_Pos (7U)
lypinator 0:bb348c97df44 11314 #define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 11315 #define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!<Tx buffer Empty Interrupt Enable */
lypinator 0:bb348c97df44 11316
lypinator 0:bb348c97df44 11317 /******************** Bit definition for SPI_SR register ********************/
lypinator 0:bb348c97df44 11318 #define SPI_SR_RXNE_Pos (0U)
lypinator 0:bb348c97df44 11319 #define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 11320 #define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!<Receive buffer Not Empty */
lypinator 0:bb348c97df44 11321 #define SPI_SR_TXE_Pos (1U)
lypinator 0:bb348c97df44 11322 #define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 11323 #define SPI_SR_TXE SPI_SR_TXE_Msk /*!<Transmit buffer Empty */
lypinator 0:bb348c97df44 11324 #define SPI_SR_CHSIDE_Pos (2U)
lypinator 0:bb348c97df44 11325 #define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 11326 #define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!<Channel side */
lypinator 0:bb348c97df44 11327 #define SPI_SR_UDR_Pos (3U)
lypinator 0:bb348c97df44 11328 #define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 11329 #define SPI_SR_UDR SPI_SR_UDR_Msk /*!<Underrun flag */
lypinator 0:bb348c97df44 11330 #define SPI_SR_CRCERR_Pos (4U)
lypinator 0:bb348c97df44 11331 #define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 11332 #define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!<CRC Error flag */
lypinator 0:bb348c97df44 11333 #define SPI_SR_MODF_Pos (5U)
lypinator 0:bb348c97df44 11334 #define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 11335 #define SPI_SR_MODF SPI_SR_MODF_Msk /*!<Mode fault */
lypinator 0:bb348c97df44 11336 #define SPI_SR_OVR_Pos (6U)
lypinator 0:bb348c97df44 11337 #define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 11338 #define SPI_SR_OVR SPI_SR_OVR_Msk /*!<Overrun flag */
lypinator 0:bb348c97df44 11339 #define SPI_SR_BSY_Pos (7U)
lypinator 0:bb348c97df44 11340 #define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 11341 #define SPI_SR_BSY SPI_SR_BSY_Msk /*!<Busy flag */
lypinator 0:bb348c97df44 11342 #define SPI_SR_FRE_Pos (8U)
lypinator 0:bb348c97df44 11343 #define SPI_SR_FRE_Msk (0x1U << SPI_SR_FRE_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 11344 #define SPI_SR_FRE SPI_SR_FRE_Msk /*!<Frame format error flag */
lypinator 0:bb348c97df44 11345
lypinator 0:bb348c97df44 11346 /******************** Bit definition for SPI_DR register ********************/
lypinator 0:bb348c97df44 11347 #define SPI_DR_DR_Pos (0U)
lypinator 0:bb348c97df44 11348 #define SPI_DR_DR_Msk (0xFFFFU << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
lypinator 0:bb348c97df44 11349 #define SPI_DR_DR SPI_DR_DR_Msk /*!<Data Register */
lypinator 0:bb348c97df44 11350
lypinator 0:bb348c97df44 11351 /******************* Bit definition for SPI_CRCPR register ******************/
lypinator 0:bb348c97df44 11352 #define SPI_CRCPR_CRCPOLY_Pos (0U)
lypinator 0:bb348c97df44 11353 #define SPI_CRCPR_CRCPOLY_Msk (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
lypinator 0:bb348c97df44 11354 #define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!<CRC polynomial register */
lypinator 0:bb348c97df44 11355
lypinator 0:bb348c97df44 11356 /****************** Bit definition for SPI_RXCRCR register ******************/
lypinator 0:bb348c97df44 11357 #define SPI_RXCRCR_RXCRC_Pos (0U)
lypinator 0:bb348c97df44 11358 #define SPI_RXCRCR_RXCRC_Msk (0xFFFFU << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
lypinator 0:bb348c97df44 11359 #define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!<Rx CRC Register */
lypinator 0:bb348c97df44 11360
lypinator 0:bb348c97df44 11361 /****************** Bit definition for SPI_TXCRCR register ******************/
lypinator 0:bb348c97df44 11362 #define SPI_TXCRCR_TXCRC_Pos (0U)
lypinator 0:bb348c97df44 11363 #define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
lypinator 0:bb348c97df44 11364 #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!<Tx CRC Register */
lypinator 0:bb348c97df44 11365
lypinator 0:bb348c97df44 11366 /****************** Bit definition for SPI_I2SCFGR register *****************/
lypinator 0:bb348c97df44 11367 #define SPI_I2SCFGR_CHLEN_Pos (0U)
lypinator 0:bb348c97df44 11368 #define SPI_I2SCFGR_CHLEN_Msk (0x1U << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 11369 #define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */
lypinator 0:bb348c97df44 11370
lypinator 0:bb348c97df44 11371 #define SPI_I2SCFGR_DATLEN_Pos (1U)
lypinator 0:bb348c97df44 11372 #define SPI_I2SCFGR_DATLEN_Msk (0x3U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */
lypinator 0:bb348c97df44 11373 #define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] bits (Data length to be transferred) */
lypinator 0:bb348c97df44 11374 #define SPI_I2SCFGR_DATLEN_0 (0x1U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 11375 #define SPI_I2SCFGR_DATLEN_1 (0x2U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 11376
lypinator 0:bb348c97df44 11377 #define SPI_I2SCFGR_CKPOL_Pos (3U)
lypinator 0:bb348c97df44 11378 #define SPI_I2SCFGR_CKPOL_Msk (0x1U << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 11379 #define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<steady state clock polarity */
lypinator 0:bb348c97df44 11380
lypinator 0:bb348c97df44 11381 #define SPI_I2SCFGR_I2SSTD_Pos (4U)
lypinator 0:bb348c97df44 11382 #define SPI_I2SCFGR_I2SSTD_Msk (0x3U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */
lypinator 0:bb348c97df44 11383 #define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] bits (I2S standard selection) */
lypinator 0:bb348c97df44 11384 #define SPI_I2SCFGR_I2SSTD_0 (0x1U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 11385 #define SPI_I2SCFGR_I2SSTD_1 (0x2U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 11386
lypinator 0:bb348c97df44 11387 #define SPI_I2SCFGR_PCMSYNC_Pos (7U)
lypinator 0:bb348c97df44 11388 #define SPI_I2SCFGR_PCMSYNC_Msk (0x1U << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 11389 #define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */
lypinator 0:bb348c97df44 11390
lypinator 0:bb348c97df44 11391 #define SPI_I2SCFGR_I2SCFG_Pos (8U)
lypinator 0:bb348c97df44 11392 #define SPI_I2SCFGR_I2SCFG_Msk (0x3U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */
lypinator 0:bb348c97df44 11393 #define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[1:0] bits (I2S configuration mode) */
lypinator 0:bb348c97df44 11394 #define SPI_I2SCFGR_I2SCFG_0 (0x1U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 11395 #define SPI_I2SCFGR_I2SCFG_1 (0x2U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 11396
lypinator 0:bb348c97df44 11397 #define SPI_I2SCFGR_I2SE_Pos (10U)
lypinator 0:bb348c97df44 11398 #define SPI_I2SCFGR_I2SE_Msk (0x1U << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 11399 #define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!<I2S Enable */
lypinator 0:bb348c97df44 11400 #define SPI_I2SCFGR_I2SMOD_Pos (11U)
lypinator 0:bb348c97df44 11401 #define SPI_I2SCFGR_I2SMOD_Msk (0x1U << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 11402 #define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */
lypinator 0:bb348c97df44 11403 #define SPI_I2SCFGR_ASTRTEN_Pos (12U)
lypinator 0:bb348c97df44 11404 #define SPI_I2SCFGR_ASTRTEN_Msk (0x1U << SPI_I2SCFGR_ASTRTEN_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 11405 #define SPI_I2SCFGR_ASTRTEN SPI_I2SCFGR_ASTRTEN_Msk /*!<Asynchronous start enable */
lypinator 0:bb348c97df44 11406
lypinator 0:bb348c97df44 11407 /****************** Bit definition for SPI_I2SPR register *******************/
lypinator 0:bb348c97df44 11408 #define SPI_I2SPR_I2SDIV_Pos (0U)
lypinator 0:bb348c97df44 11409 #define SPI_I2SPR_I2SDIV_Msk (0xFFU << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */
lypinator 0:bb348c97df44 11410 #define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!<I2S Linear prescaler */
lypinator 0:bb348c97df44 11411 #define SPI_I2SPR_ODD_Pos (8U)
lypinator 0:bb348c97df44 11412 #define SPI_I2SPR_ODD_Msk (0x1U << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 11413 #define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!<Odd factor for the prescaler */
lypinator 0:bb348c97df44 11414 #define SPI_I2SPR_MCKOE_Pos (9U)
lypinator 0:bb348c97df44 11415 #define SPI_I2SPR_MCKOE_Msk (0x1U << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 11416 #define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!<Master Clock Output Enable */
lypinator 0:bb348c97df44 11417
lypinator 0:bb348c97df44 11418 /******************************************************************************/
lypinator 0:bb348c97df44 11419 /* */
lypinator 0:bb348c97df44 11420 /* SYSCFG */
lypinator 0:bb348c97df44 11421 /* */
lypinator 0:bb348c97df44 11422 /******************************************************************************/
lypinator 0:bb348c97df44 11423 /****************** Bit definition for SYSCFG_MEMRMP register ***************/
lypinator 0:bb348c97df44 11424 #define SYSCFG_MEMRMP_MEM_MODE_Pos (0U)
lypinator 0:bb348c97df44 11425 #define SYSCFG_MEMRMP_MEM_MODE_Msk (0x3U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000003 */
lypinator 0:bb348c97df44 11426 #define SYSCFG_MEMRMP_MEM_MODE SYSCFG_MEMRMP_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */
lypinator 0:bb348c97df44 11427 #define SYSCFG_MEMRMP_MEM_MODE_0 (0x1U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 11428 #define SYSCFG_MEMRMP_MEM_MODE_1 (0x2U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 11429 /****************** Bit definition for SYSCFG_PMC register ******************/
lypinator 0:bb348c97df44 11430 #define SYSCFG_PMC_ADC1DC2_Pos (16U)
lypinator 0:bb348c97df44 11431 #define SYSCFG_PMC_ADC1DC2_Msk (0x1U << SYSCFG_PMC_ADC1DC2_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 11432 #define SYSCFG_PMC_ADC1DC2 SYSCFG_PMC_ADC1DC2_Msk /*!< Refer to AN4073 on how to use this bit */
lypinator 0:bb348c97df44 11433
lypinator 0:bb348c97df44 11434 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
lypinator 0:bb348c97df44 11435 #define SYSCFG_EXTICR1_EXTI0_Pos (0U)
lypinator 0:bb348c97df44 11436 #define SYSCFG_EXTICR1_EXTI0_Msk (0xFU << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
lypinator 0:bb348c97df44 11437 #define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!<EXTI 0 configuration */
lypinator 0:bb348c97df44 11438 #define SYSCFG_EXTICR1_EXTI1_Pos (4U)
lypinator 0:bb348c97df44 11439 #define SYSCFG_EXTICR1_EXTI1_Msk (0xFU << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
lypinator 0:bb348c97df44 11440 #define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!<EXTI 1 configuration */
lypinator 0:bb348c97df44 11441 #define SYSCFG_EXTICR1_EXTI2_Pos (8U)
lypinator 0:bb348c97df44 11442 #define SYSCFG_EXTICR1_EXTI2_Msk (0xFU << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
lypinator 0:bb348c97df44 11443 #define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!<EXTI 2 configuration */
lypinator 0:bb348c97df44 11444 #define SYSCFG_EXTICR1_EXTI3_Pos (12U)
lypinator 0:bb348c97df44 11445 #define SYSCFG_EXTICR1_EXTI3_Msk (0xFU << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
lypinator 0:bb348c97df44 11446 #define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!<EXTI 3 configuration */
lypinator 0:bb348c97df44 11447 /**
lypinator 0:bb348c97df44 11448 * @brief EXTI0 configuration
lypinator 0:bb348c97df44 11449 */
lypinator 0:bb348c97df44 11450 #define SYSCFG_EXTICR1_EXTI0_PA 0x0000U /*!<PA[0] pin */
lypinator 0:bb348c97df44 11451 #define SYSCFG_EXTICR1_EXTI0_PB 0x0001U /*!<PB[0] pin */
lypinator 0:bb348c97df44 11452 #define SYSCFG_EXTICR1_EXTI0_PC 0x0002U /*!<PC[0] pin */
lypinator 0:bb348c97df44 11453 #define SYSCFG_EXTICR1_EXTI0_PD 0x0003U /*!<PD[0] pin */
lypinator 0:bb348c97df44 11454 #define SYSCFG_EXTICR1_EXTI0_PE 0x0004U /*!<PE[0] pin */
lypinator 0:bb348c97df44 11455 #define SYSCFG_EXTICR1_EXTI0_PF 0x0005U /*!<PF[0] pin */
lypinator 0:bb348c97df44 11456 #define SYSCFG_EXTICR1_EXTI0_PG 0x0006U /*!<PG[0] pin */
lypinator 0:bb348c97df44 11457 #define SYSCFG_EXTICR1_EXTI0_PH 0x0007U /*!<PH[0] pin */
lypinator 0:bb348c97df44 11458
lypinator 0:bb348c97df44 11459 /**
lypinator 0:bb348c97df44 11460 * @brief EXTI1 configuration
lypinator 0:bb348c97df44 11461 */
lypinator 0:bb348c97df44 11462 #define SYSCFG_EXTICR1_EXTI1_PA 0x0000U /*!<PA[1] pin */
lypinator 0:bb348c97df44 11463 #define SYSCFG_EXTICR1_EXTI1_PB 0x0010U /*!<PB[1] pin */
lypinator 0:bb348c97df44 11464 #define SYSCFG_EXTICR1_EXTI1_PC 0x0020U /*!<PC[1] pin */
lypinator 0:bb348c97df44 11465 #define SYSCFG_EXTICR1_EXTI1_PD 0x0030U /*!<PD[1] pin */
lypinator 0:bb348c97df44 11466 #define SYSCFG_EXTICR1_EXTI1_PE 0x0040U /*!<PE[1] pin */
lypinator 0:bb348c97df44 11467 #define SYSCFG_EXTICR1_EXTI1_PF 0x0050U /*!<PF[1] pin */
lypinator 0:bb348c97df44 11468 #define SYSCFG_EXTICR1_EXTI1_PG 0x0060U /*!<PG[1] pin */
lypinator 0:bb348c97df44 11469 #define SYSCFG_EXTICR1_EXTI1_PH 0x0070U /*!<PH[1] pin */
lypinator 0:bb348c97df44 11470
lypinator 0:bb348c97df44 11471 /**
lypinator 0:bb348c97df44 11472 * @brief EXTI2 configuration
lypinator 0:bb348c97df44 11473 */
lypinator 0:bb348c97df44 11474 #define SYSCFG_EXTICR1_EXTI2_PA 0x0000U /*!<PA[2] pin */
lypinator 0:bb348c97df44 11475 #define SYSCFG_EXTICR1_EXTI2_PB 0x0100U /*!<PB[2] pin */
lypinator 0:bb348c97df44 11476 #define SYSCFG_EXTICR1_EXTI2_PC 0x0200U /*!<PC[2] pin */
lypinator 0:bb348c97df44 11477 #define SYSCFG_EXTICR1_EXTI2_PD 0x0300U /*!<PD[2] pin */
lypinator 0:bb348c97df44 11478 #define SYSCFG_EXTICR1_EXTI2_PE 0x0400U /*!<PE[2] pin */
lypinator 0:bb348c97df44 11479 #define SYSCFG_EXTICR1_EXTI2_PF 0x0500U /*!<PF[2] pin */
lypinator 0:bb348c97df44 11480 #define SYSCFG_EXTICR1_EXTI2_PG 0x0600U /*!<PG[2] pin */
lypinator 0:bb348c97df44 11481 #define SYSCFG_EXTICR1_EXTI2_PH 0x0700U /*!<PH[2] pin */
lypinator 0:bb348c97df44 11482
lypinator 0:bb348c97df44 11483 /**
lypinator 0:bb348c97df44 11484 * @brief EXTI3 configuration
lypinator 0:bb348c97df44 11485 */
lypinator 0:bb348c97df44 11486 #define SYSCFG_EXTICR1_EXTI3_PA 0x0000U /*!<PA[3] pin */
lypinator 0:bb348c97df44 11487 #define SYSCFG_EXTICR1_EXTI3_PB 0x1000U /*!<PB[3] pin */
lypinator 0:bb348c97df44 11488 #define SYSCFG_EXTICR1_EXTI3_PC 0x2000U /*!<PC[3] pin */
lypinator 0:bb348c97df44 11489 #define SYSCFG_EXTICR1_EXTI3_PD 0x3000U /*!<PD[3] pin */
lypinator 0:bb348c97df44 11490 #define SYSCFG_EXTICR1_EXTI3_PE 0x4000U /*!<PE[3] pin */
lypinator 0:bb348c97df44 11491 #define SYSCFG_EXTICR1_EXTI3_PF 0x5000U /*!<PF[3] pin */
lypinator 0:bb348c97df44 11492 #define SYSCFG_EXTICR1_EXTI3_PG 0x6000U /*!<PG[3] pin */
lypinator 0:bb348c97df44 11493 #define SYSCFG_EXTICR1_EXTI3_PH 0x7000U /*!<PH[3] pin */
lypinator 0:bb348c97df44 11494
lypinator 0:bb348c97df44 11495 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
lypinator 0:bb348c97df44 11496 #define SYSCFG_EXTICR2_EXTI4_Pos (0U)
lypinator 0:bb348c97df44 11497 #define SYSCFG_EXTICR2_EXTI4_Msk (0xFU << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
lypinator 0:bb348c97df44 11498 #define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!<EXTI 4 configuration */
lypinator 0:bb348c97df44 11499 #define SYSCFG_EXTICR2_EXTI5_Pos (4U)
lypinator 0:bb348c97df44 11500 #define SYSCFG_EXTICR2_EXTI5_Msk (0xFU << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
lypinator 0:bb348c97df44 11501 #define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!<EXTI 5 configuration */
lypinator 0:bb348c97df44 11502 #define SYSCFG_EXTICR2_EXTI6_Pos (8U)
lypinator 0:bb348c97df44 11503 #define SYSCFG_EXTICR2_EXTI6_Msk (0xFU << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
lypinator 0:bb348c97df44 11504 #define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!<EXTI 6 configuration */
lypinator 0:bb348c97df44 11505 #define SYSCFG_EXTICR2_EXTI7_Pos (12U)
lypinator 0:bb348c97df44 11506 #define SYSCFG_EXTICR2_EXTI7_Msk (0xFU << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
lypinator 0:bb348c97df44 11507 #define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!<EXTI 7 configuration */
lypinator 0:bb348c97df44 11508
lypinator 0:bb348c97df44 11509 /**
lypinator 0:bb348c97df44 11510 * @brief EXTI4 configuration
lypinator 0:bb348c97df44 11511 */
lypinator 0:bb348c97df44 11512 #define SYSCFG_EXTICR2_EXTI4_PA 0x0000U /*!<PA[4] pin */
lypinator 0:bb348c97df44 11513 #define SYSCFG_EXTICR2_EXTI4_PB 0x0001U /*!<PB[4] pin */
lypinator 0:bb348c97df44 11514 #define SYSCFG_EXTICR2_EXTI4_PC 0x0002U /*!<PC[4] pin */
lypinator 0:bb348c97df44 11515 #define SYSCFG_EXTICR2_EXTI4_PD 0x0003U /*!<PD[4] pin */
lypinator 0:bb348c97df44 11516 #define SYSCFG_EXTICR2_EXTI4_PE 0x0004U /*!<PE[4] pin */
lypinator 0:bb348c97df44 11517 #define SYSCFG_EXTICR2_EXTI4_PF 0x0005U /*!<PF[4] pin */
lypinator 0:bb348c97df44 11518 #define SYSCFG_EXTICR2_EXTI4_PG 0x0006U /*!<PG[4] pin */
lypinator 0:bb348c97df44 11519 #define SYSCFG_EXTICR2_EXTI4_PH 0x0007U /*!<PH[4] pin */
lypinator 0:bb348c97df44 11520
lypinator 0:bb348c97df44 11521 /**
lypinator 0:bb348c97df44 11522 * @brief EXTI5 configuration
lypinator 0:bb348c97df44 11523 */
lypinator 0:bb348c97df44 11524 #define SYSCFG_EXTICR2_EXTI5_PA 0x0000U /*!<PA[5] pin */
lypinator 0:bb348c97df44 11525 #define SYSCFG_EXTICR2_EXTI5_PB 0x0010U /*!<PB[5] pin */
lypinator 0:bb348c97df44 11526 #define SYSCFG_EXTICR2_EXTI5_PC 0x0020U /*!<PC[5] pin */
lypinator 0:bb348c97df44 11527 #define SYSCFG_EXTICR2_EXTI5_PD 0x0030U /*!<PD[5] pin */
lypinator 0:bb348c97df44 11528 #define SYSCFG_EXTICR2_EXTI5_PE 0x0040U /*!<PE[5] pin */
lypinator 0:bb348c97df44 11529 #define SYSCFG_EXTICR2_EXTI5_PF 0x0050U /*!<PF[5] pin */
lypinator 0:bb348c97df44 11530 #define SYSCFG_EXTICR2_EXTI5_PG 0x0060U /*!<PG[5] pin */
lypinator 0:bb348c97df44 11531 #define SYSCFG_EXTICR2_EXTI5_PH 0x0070U /*!<PH[5] pin */
lypinator 0:bb348c97df44 11532
lypinator 0:bb348c97df44 11533 /**
lypinator 0:bb348c97df44 11534 * @brief EXTI6 configuration
lypinator 0:bb348c97df44 11535 */
lypinator 0:bb348c97df44 11536 #define SYSCFG_EXTICR2_EXTI6_PA 0x0000U /*!<PA[6] pin */
lypinator 0:bb348c97df44 11537 #define SYSCFG_EXTICR2_EXTI6_PB 0x0100U /*!<PB[6] pin */
lypinator 0:bb348c97df44 11538 #define SYSCFG_EXTICR2_EXTI6_PC 0x0200U /*!<PC[6] pin */
lypinator 0:bb348c97df44 11539 #define SYSCFG_EXTICR2_EXTI6_PD 0x0300U /*!<PD[6] pin */
lypinator 0:bb348c97df44 11540 #define SYSCFG_EXTICR2_EXTI6_PE 0x0400U /*!<PE[6] pin */
lypinator 0:bb348c97df44 11541 #define SYSCFG_EXTICR2_EXTI6_PF 0x0500U /*!<PF[6] pin */
lypinator 0:bb348c97df44 11542 #define SYSCFG_EXTICR2_EXTI6_PG 0x0600U /*!<PG[6] pin */
lypinator 0:bb348c97df44 11543 #define SYSCFG_EXTICR2_EXTI6_PH 0x0700U /*!<PH[6] pin */
lypinator 0:bb348c97df44 11544
lypinator 0:bb348c97df44 11545 /**
lypinator 0:bb348c97df44 11546 * @brief EXTI7 configuration
lypinator 0:bb348c97df44 11547 */
lypinator 0:bb348c97df44 11548 #define SYSCFG_EXTICR2_EXTI7_PA 0x0000U /*!<PA[7] pin */
lypinator 0:bb348c97df44 11549 #define SYSCFG_EXTICR2_EXTI7_PB 0x1000U /*!<PB[7] pin */
lypinator 0:bb348c97df44 11550 #define SYSCFG_EXTICR2_EXTI7_PC 0x2000U /*!<PC[7] pin */
lypinator 0:bb348c97df44 11551 #define SYSCFG_EXTICR2_EXTI7_PD 0x3000U /*!<PD[7] pin */
lypinator 0:bb348c97df44 11552 #define SYSCFG_EXTICR2_EXTI7_PE 0x4000U /*!<PE[7] pin */
lypinator 0:bb348c97df44 11553 #define SYSCFG_EXTICR2_EXTI7_PF 0x5000U /*!<PF[7] pin */
lypinator 0:bb348c97df44 11554 #define SYSCFG_EXTICR2_EXTI7_PG 0x6000U /*!<PG[7] pin */
lypinator 0:bb348c97df44 11555 #define SYSCFG_EXTICR2_EXTI7_PH 0x7000U /*!<PH[7] pin */
lypinator 0:bb348c97df44 11556
lypinator 0:bb348c97df44 11557 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
lypinator 0:bb348c97df44 11558 #define SYSCFG_EXTICR3_EXTI8_Pos (0U)
lypinator 0:bb348c97df44 11559 #define SYSCFG_EXTICR3_EXTI8_Msk (0xFU << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
lypinator 0:bb348c97df44 11560 #define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!<EXTI 8 configuration */
lypinator 0:bb348c97df44 11561 #define SYSCFG_EXTICR3_EXTI9_Pos (4U)
lypinator 0:bb348c97df44 11562 #define SYSCFG_EXTICR3_EXTI9_Msk (0xFU << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
lypinator 0:bb348c97df44 11563 #define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!<EXTI 9 configuration */
lypinator 0:bb348c97df44 11564 #define SYSCFG_EXTICR3_EXTI10_Pos (8U)
lypinator 0:bb348c97df44 11565 #define SYSCFG_EXTICR3_EXTI10_Msk (0xFU << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
lypinator 0:bb348c97df44 11566 #define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!<EXTI 10 configuration */
lypinator 0:bb348c97df44 11567 #define SYSCFG_EXTICR3_EXTI11_Pos (12U)
lypinator 0:bb348c97df44 11568 #define SYSCFG_EXTICR3_EXTI11_Msk (0xFU << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
lypinator 0:bb348c97df44 11569 #define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!<EXTI 11 configuration */
lypinator 0:bb348c97df44 11570
lypinator 0:bb348c97df44 11571 /**
lypinator 0:bb348c97df44 11572 * @brief EXTI8 configuration
lypinator 0:bb348c97df44 11573 */
lypinator 0:bb348c97df44 11574 #define SYSCFG_EXTICR3_EXTI8_PA 0x0000U /*!<PA[8] pin */
lypinator 0:bb348c97df44 11575 #define SYSCFG_EXTICR3_EXTI8_PB 0x0001U /*!<PB[8] pin */
lypinator 0:bb348c97df44 11576 #define SYSCFG_EXTICR3_EXTI8_PC 0x0002U /*!<PC[8] pin */
lypinator 0:bb348c97df44 11577 #define SYSCFG_EXTICR3_EXTI8_PD 0x0003U /*!<PD[8] pin */
lypinator 0:bb348c97df44 11578 #define SYSCFG_EXTICR3_EXTI8_PE 0x0004U /*!<PE[8] pin */
lypinator 0:bb348c97df44 11579 #define SYSCFG_EXTICR3_EXTI8_PF 0x0005U /*!<PF[8] pin */
lypinator 0:bb348c97df44 11580 #define SYSCFG_EXTICR3_EXTI8_PG 0x0006U /*!<PG[8] pin */
lypinator 0:bb348c97df44 11581 #define SYSCFG_EXTICR3_EXTI8_PH 0x0007U /*!<PH[8] pin */
lypinator 0:bb348c97df44 11582
lypinator 0:bb348c97df44 11583 /**
lypinator 0:bb348c97df44 11584 * @brief EXTI9 configuration
lypinator 0:bb348c97df44 11585 */
lypinator 0:bb348c97df44 11586 #define SYSCFG_EXTICR3_EXTI9_PA 0x0000U /*!<PA[9] pin */
lypinator 0:bb348c97df44 11587 #define SYSCFG_EXTICR3_EXTI9_PB 0x0010U /*!<PB[9] pin */
lypinator 0:bb348c97df44 11588 #define SYSCFG_EXTICR3_EXTI9_PC 0x0020U /*!<PC[9] pin */
lypinator 0:bb348c97df44 11589 #define SYSCFG_EXTICR3_EXTI9_PD 0x0030U /*!<PD[9] pin */
lypinator 0:bb348c97df44 11590 #define SYSCFG_EXTICR3_EXTI9_PE 0x0040U /*!<PE[9] pin */
lypinator 0:bb348c97df44 11591 #define SYSCFG_EXTICR3_EXTI9_PF 0x0050U /*!<PF[9] pin */
lypinator 0:bb348c97df44 11592 #define SYSCFG_EXTICR3_EXTI9_PG 0x0060U /*!<PG[9] pin */
lypinator 0:bb348c97df44 11593 #define SYSCFG_EXTICR3_EXTI9_PH 0x0070U /*!<PH[9] pin */
lypinator 0:bb348c97df44 11594
lypinator 0:bb348c97df44 11595 /**
lypinator 0:bb348c97df44 11596 * @brief EXTI10 configuration
lypinator 0:bb348c97df44 11597 */
lypinator 0:bb348c97df44 11598 #define SYSCFG_EXTICR3_EXTI10_PA 0x0000U /*!<PA[10] pin */
lypinator 0:bb348c97df44 11599 #define SYSCFG_EXTICR3_EXTI10_PB 0x0100U /*!<PB[10] pin */
lypinator 0:bb348c97df44 11600 #define SYSCFG_EXTICR3_EXTI10_PC 0x0200U /*!<PC[10] pin */
lypinator 0:bb348c97df44 11601 #define SYSCFG_EXTICR3_EXTI10_PD 0x0300U /*!<PD[10] pin */
lypinator 0:bb348c97df44 11602 #define SYSCFG_EXTICR3_EXTI10_PE 0x0400U /*!<PE[10] pin */
lypinator 0:bb348c97df44 11603 #define SYSCFG_EXTICR3_EXTI10_PF 0x0500U /*!<PF[10] pin */
lypinator 0:bb348c97df44 11604 #define SYSCFG_EXTICR3_EXTI10_PG 0x0600U /*!<PG[10] pin */
lypinator 0:bb348c97df44 11605 #define SYSCFG_EXTICR3_EXTI10_PH 0x0700U /*!<PH[10] pin */
lypinator 0:bb348c97df44 11606
lypinator 0:bb348c97df44 11607 /**
lypinator 0:bb348c97df44 11608 * @brief EXTI11 configuration
lypinator 0:bb348c97df44 11609 */
lypinator 0:bb348c97df44 11610 #define SYSCFG_EXTICR3_EXTI11_PA 0x0000U /*!<PA[11] pin */
lypinator 0:bb348c97df44 11611 #define SYSCFG_EXTICR3_EXTI11_PB 0x1000U /*!<PB[11] pin */
lypinator 0:bb348c97df44 11612 #define SYSCFG_EXTICR3_EXTI11_PC 0x2000U /*!<PC[11] pin */
lypinator 0:bb348c97df44 11613 #define SYSCFG_EXTICR3_EXTI11_PD 0x3000U /*!<PD[11] pin */
lypinator 0:bb348c97df44 11614 #define SYSCFG_EXTICR3_EXTI11_PE 0x4000U /*!<PE[11] pin */
lypinator 0:bb348c97df44 11615 #define SYSCFG_EXTICR3_EXTI11_PF 0x5000U /*!<PF[11] pin */
lypinator 0:bb348c97df44 11616 #define SYSCFG_EXTICR3_EXTI11_PG 0x6000U /*!<PG[11] pin */
lypinator 0:bb348c97df44 11617 #define SYSCFG_EXTICR3_EXTI11_PH 0x7000U /*!<PH[11] pin */
lypinator 0:bb348c97df44 11618
lypinator 0:bb348c97df44 11619 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
lypinator 0:bb348c97df44 11620 #define SYSCFG_EXTICR4_EXTI12_Pos (0U)
lypinator 0:bb348c97df44 11621 #define SYSCFG_EXTICR4_EXTI12_Msk (0xFU << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
lypinator 0:bb348c97df44 11622 #define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!<EXTI 12 configuration */
lypinator 0:bb348c97df44 11623 #define SYSCFG_EXTICR4_EXTI13_Pos (4U)
lypinator 0:bb348c97df44 11624 #define SYSCFG_EXTICR4_EXTI13_Msk (0xFU << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
lypinator 0:bb348c97df44 11625 #define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!<EXTI 13 configuration */
lypinator 0:bb348c97df44 11626 #define SYSCFG_EXTICR4_EXTI14_Pos (8U)
lypinator 0:bb348c97df44 11627 #define SYSCFG_EXTICR4_EXTI14_Msk (0xFU << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
lypinator 0:bb348c97df44 11628 #define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!<EXTI 14 configuration */
lypinator 0:bb348c97df44 11629 #define SYSCFG_EXTICR4_EXTI15_Pos (12U)
lypinator 0:bb348c97df44 11630 #define SYSCFG_EXTICR4_EXTI15_Msk (0xFU << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
lypinator 0:bb348c97df44 11631 #define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!<EXTI 15 configuration */
lypinator 0:bb348c97df44 11632
lypinator 0:bb348c97df44 11633 /**
lypinator 0:bb348c97df44 11634 * @brief EXTI12 configuration
lypinator 0:bb348c97df44 11635 */
lypinator 0:bb348c97df44 11636 #define SYSCFG_EXTICR4_EXTI12_PA 0x0000U /*!<PA[12] pin */
lypinator 0:bb348c97df44 11637 #define SYSCFG_EXTICR4_EXTI12_PB 0x0001U /*!<PB[12] pin */
lypinator 0:bb348c97df44 11638 #define SYSCFG_EXTICR4_EXTI12_PC 0x0002U /*!<PC[12] pin */
lypinator 0:bb348c97df44 11639 #define SYSCFG_EXTICR4_EXTI12_PD 0x0003U /*!<PD[12] pin */
lypinator 0:bb348c97df44 11640 #define SYSCFG_EXTICR4_EXTI12_PE 0x0004U /*!<PE[12] pin */
lypinator 0:bb348c97df44 11641 #define SYSCFG_EXTICR4_EXTI12_PF 0x0005U /*!<PF[12] pin */
lypinator 0:bb348c97df44 11642 #define SYSCFG_EXTICR4_EXTI12_PG 0x0006U /*!<PG[12] pin */
lypinator 0:bb348c97df44 11643 #define SYSCFG_EXTICR4_EXTI12_PH 0x0007U /*!<PH[12] pin */
lypinator 0:bb348c97df44 11644
lypinator 0:bb348c97df44 11645 /**
lypinator 0:bb348c97df44 11646 * @brief EXTI13 configuration
lypinator 0:bb348c97df44 11647 */
lypinator 0:bb348c97df44 11648 #define SYSCFG_EXTICR4_EXTI13_PA 0x0000U /*!<PA[13] pin */
lypinator 0:bb348c97df44 11649 #define SYSCFG_EXTICR4_EXTI13_PB 0x0010U /*!<PB[13] pin */
lypinator 0:bb348c97df44 11650 #define SYSCFG_EXTICR4_EXTI13_PC 0x0020U /*!<PC[13] pin */
lypinator 0:bb348c97df44 11651 #define SYSCFG_EXTICR4_EXTI13_PD 0x0030U /*!<PD[13] pin */
lypinator 0:bb348c97df44 11652 #define SYSCFG_EXTICR4_EXTI13_PE 0x0040U /*!<PE[13] pin */
lypinator 0:bb348c97df44 11653 #define SYSCFG_EXTICR4_EXTI13_PF 0x0050U /*!<PF[13] pin */
lypinator 0:bb348c97df44 11654 #define SYSCFG_EXTICR4_EXTI13_PG 0x0060U /*!<PG[13] pin */
lypinator 0:bb348c97df44 11655 #define SYSCFG_EXTICR4_EXTI13_PH 0x0070U /*!<PH[13] pin */
lypinator 0:bb348c97df44 11656
lypinator 0:bb348c97df44 11657 /**
lypinator 0:bb348c97df44 11658 * @brief EXTI14 configuration
lypinator 0:bb348c97df44 11659 */
lypinator 0:bb348c97df44 11660 #define SYSCFG_EXTICR4_EXTI14_PA 0x0000U /*!<PA[14] pin */
lypinator 0:bb348c97df44 11661 #define SYSCFG_EXTICR4_EXTI14_PB 0x0100U /*!<PB[14] pin */
lypinator 0:bb348c97df44 11662 #define SYSCFG_EXTICR4_EXTI14_PC 0x0200U /*!<PC[14] pin */
lypinator 0:bb348c97df44 11663 #define SYSCFG_EXTICR4_EXTI14_PD 0x0300U /*!<PD[14] pin */
lypinator 0:bb348c97df44 11664 #define SYSCFG_EXTICR4_EXTI14_PE 0x0400U /*!<PE[14] pin */
lypinator 0:bb348c97df44 11665 #define SYSCFG_EXTICR4_EXTI14_PF 0x0500U /*!<PF[14] pin */
lypinator 0:bb348c97df44 11666 #define SYSCFG_EXTICR4_EXTI14_PG 0x0600U /*!<PG[14] pin */
lypinator 0:bb348c97df44 11667 #define SYSCFG_EXTICR4_EXTI14_PH 0x0700U /*!<PH[14] pin */
lypinator 0:bb348c97df44 11668
lypinator 0:bb348c97df44 11669 /**
lypinator 0:bb348c97df44 11670 * @brief EXTI15 configuration
lypinator 0:bb348c97df44 11671 */
lypinator 0:bb348c97df44 11672 #define SYSCFG_EXTICR4_EXTI15_PA 0x0000U /*!<PA[15] pin */
lypinator 0:bb348c97df44 11673 #define SYSCFG_EXTICR4_EXTI15_PB 0x1000U /*!<PB[15] pin */
lypinator 0:bb348c97df44 11674 #define SYSCFG_EXTICR4_EXTI15_PC 0x2000U /*!<PC[15] pin */
lypinator 0:bb348c97df44 11675 #define SYSCFG_EXTICR4_EXTI15_PD 0x3000U /*!<PD[15] pin */
lypinator 0:bb348c97df44 11676 #define SYSCFG_EXTICR4_EXTI15_PE 0x4000U /*!<PE[15] pin */
lypinator 0:bb348c97df44 11677 #define SYSCFG_EXTICR4_EXTI15_PF 0x5000U /*!<PF[15] pin */
lypinator 0:bb348c97df44 11678 #define SYSCFG_EXTICR4_EXTI15_PG 0x6000U /*!<PG[15] pin */
lypinator 0:bb348c97df44 11679 #define SYSCFG_EXTICR4_EXTI15_PH 0x7000U /*!<PH[15] pin */
lypinator 0:bb348c97df44 11680
lypinator 0:bb348c97df44 11681 /****************** Bit definition for SYSCFG_CMPCR register ****************/
lypinator 0:bb348c97df44 11682 #define SYSCFG_CMPCR_CMP_PD_Pos (0U)
lypinator 0:bb348c97df44 11683 #define SYSCFG_CMPCR_CMP_PD_Msk (0x1U << SYSCFG_CMPCR_CMP_PD_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 11684 #define SYSCFG_CMPCR_CMP_PD SYSCFG_CMPCR_CMP_PD_Msk /*!<Compensation cell ready flag */
lypinator 0:bb348c97df44 11685 #define SYSCFG_CMPCR_READY_Pos (8U)
lypinator 0:bb348c97df44 11686 #define SYSCFG_CMPCR_READY_Msk (0x1U << SYSCFG_CMPCR_READY_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 11687 #define SYSCFG_CMPCR_READY SYSCFG_CMPCR_READY_Msk /*!<Compensation cell power-down */
lypinator 0:bb348c97df44 11688 /****************** Bit definition for SYSCFG_CFGR register ****************/
lypinator 0:bb348c97df44 11689 #define SYSCFG_CFGR_FMPI2C1_SCL_Pos (0U)
lypinator 0:bb348c97df44 11690 #define SYSCFG_CFGR_FMPI2C1_SCL_Msk (0x1U << SYSCFG_CFGR_FMPI2C1_SCL_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 11691 #define SYSCFG_CFGR_FMPI2C1_SCL SYSCFG_CFGR_FMPI2C1_SCL_Msk /*!<FM+ drive capability for FMPI2C1_SCL pin */
lypinator 0:bb348c97df44 11692 #define SYSCFG_CFGR_FMPI2C1_SDA_Pos (1U)
lypinator 0:bb348c97df44 11693 #define SYSCFG_CFGR_FMPI2C1_SDA_Msk (0x1U << SYSCFG_CFGR_FMPI2C1_SDA_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 11694 #define SYSCFG_CFGR_FMPI2C1_SDA SYSCFG_CFGR_FMPI2C1_SDA_Msk /*!<FM+ drive capability for FMPI2C1_SDA pin */
lypinator 0:bb348c97df44 11695
lypinator 0:bb348c97df44 11696
lypinator 0:bb348c97df44 11697 /******************************************************************************/
lypinator 0:bb348c97df44 11698 /* */
lypinator 0:bb348c97df44 11699 /* TIM */
lypinator 0:bb348c97df44 11700 /* */
lypinator 0:bb348c97df44 11701 /******************************************************************************/
lypinator 0:bb348c97df44 11702 /******************* Bit definition for TIM_CR1 register ********************/
lypinator 0:bb348c97df44 11703 #define TIM_CR1_CEN_Pos (0U)
lypinator 0:bb348c97df44 11704 #define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 11705 #define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
lypinator 0:bb348c97df44 11706 #define TIM_CR1_UDIS_Pos (1U)
lypinator 0:bb348c97df44 11707 #define TIM_CR1_UDIS_Msk (0x1U << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 11708 #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
lypinator 0:bb348c97df44 11709 #define TIM_CR1_URS_Pos (2U)
lypinator 0:bb348c97df44 11710 #define TIM_CR1_URS_Msk (0x1U << TIM_CR1_URS_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 11711 #define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
lypinator 0:bb348c97df44 11712 #define TIM_CR1_OPM_Pos (3U)
lypinator 0:bb348c97df44 11713 #define TIM_CR1_OPM_Msk (0x1U << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 11714 #define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
lypinator 0:bb348c97df44 11715 #define TIM_CR1_DIR_Pos (4U)
lypinator 0:bb348c97df44 11716 #define TIM_CR1_DIR_Msk (0x1U << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 11717 #define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
lypinator 0:bb348c97df44 11718
lypinator 0:bb348c97df44 11719 #define TIM_CR1_CMS_Pos (5U)
lypinator 0:bb348c97df44 11720 #define TIM_CR1_CMS_Msk (0x3U << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
lypinator 0:bb348c97df44 11721 #define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
lypinator 0:bb348c97df44 11722 #define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) /*!< 0x0020 */
lypinator 0:bb348c97df44 11723 #define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) /*!< 0x0040 */
lypinator 0:bb348c97df44 11724
lypinator 0:bb348c97df44 11725 #define TIM_CR1_ARPE_Pos (7U)
lypinator 0:bb348c97df44 11726 #define TIM_CR1_ARPE_Msk (0x1U << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 11727 #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
lypinator 0:bb348c97df44 11728
lypinator 0:bb348c97df44 11729 #define TIM_CR1_CKD_Pos (8U)
lypinator 0:bb348c97df44 11730 #define TIM_CR1_CKD_Msk (0x3U << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
lypinator 0:bb348c97df44 11731 #define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
lypinator 0:bb348c97df44 11732 #define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) /*!< 0x0100 */
lypinator 0:bb348c97df44 11733 #define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) /*!< 0x0200 */
lypinator 0:bb348c97df44 11734
lypinator 0:bb348c97df44 11735 /******************* Bit definition for TIM_CR2 register ********************/
lypinator 0:bb348c97df44 11736 #define TIM_CR2_CCPC_Pos (0U)
lypinator 0:bb348c97df44 11737 #define TIM_CR2_CCPC_Msk (0x1U << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 11738 #define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
lypinator 0:bb348c97df44 11739 #define TIM_CR2_CCUS_Pos (2U)
lypinator 0:bb348c97df44 11740 #define TIM_CR2_CCUS_Msk (0x1U << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 11741 #define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
lypinator 0:bb348c97df44 11742 #define TIM_CR2_CCDS_Pos (3U)
lypinator 0:bb348c97df44 11743 #define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 11744 #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
lypinator 0:bb348c97df44 11745
lypinator 0:bb348c97df44 11746 #define TIM_CR2_MMS_Pos (4U)
lypinator 0:bb348c97df44 11747 #define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
lypinator 0:bb348c97df44 11748 #define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
lypinator 0:bb348c97df44 11749 #define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /*!< 0x0010 */
lypinator 0:bb348c97df44 11750 #define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x0020 */
lypinator 0:bb348c97df44 11751 #define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /*!< 0x0040 */
lypinator 0:bb348c97df44 11752
lypinator 0:bb348c97df44 11753 #define TIM_CR2_TI1S_Pos (7U)
lypinator 0:bb348c97df44 11754 #define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 11755 #define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
lypinator 0:bb348c97df44 11756 #define TIM_CR2_OIS1_Pos (8U)
lypinator 0:bb348c97df44 11757 #define TIM_CR2_OIS1_Msk (0x1U << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 11758 #define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
lypinator 0:bb348c97df44 11759 #define TIM_CR2_OIS1N_Pos (9U)
lypinator 0:bb348c97df44 11760 #define TIM_CR2_OIS1N_Msk (0x1U << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 11761 #define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
lypinator 0:bb348c97df44 11762 #define TIM_CR2_OIS2_Pos (10U)
lypinator 0:bb348c97df44 11763 #define TIM_CR2_OIS2_Msk (0x1U << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 11764 #define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
lypinator 0:bb348c97df44 11765 #define TIM_CR2_OIS2N_Pos (11U)
lypinator 0:bb348c97df44 11766 #define TIM_CR2_OIS2N_Msk (0x1U << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 11767 #define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
lypinator 0:bb348c97df44 11768 #define TIM_CR2_OIS3_Pos (12U)
lypinator 0:bb348c97df44 11769 #define TIM_CR2_OIS3_Msk (0x1U << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 11770 #define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
lypinator 0:bb348c97df44 11771 #define TIM_CR2_OIS3N_Pos (13U)
lypinator 0:bb348c97df44 11772 #define TIM_CR2_OIS3N_Msk (0x1U << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 11773 #define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
lypinator 0:bb348c97df44 11774 #define TIM_CR2_OIS4_Pos (14U)
lypinator 0:bb348c97df44 11775 #define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 11776 #define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
lypinator 0:bb348c97df44 11777
lypinator 0:bb348c97df44 11778 /******************* Bit definition for TIM_SMCR register *******************/
lypinator 0:bb348c97df44 11779 #define TIM_SMCR_SMS_Pos (0U)
lypinator 0:bb348c97df44 11780 #define TIM_SMCR_SMS_Msk (0x7U << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */
lypinator 0:bb348c97df44 11781 #define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
lypinator 0:bb348c97df44 11782 #define TIM_SMCR_SMS_0 (0x1U << TIM_SMCR_SMS_Pos) /*!< 0x0001 */
lypinator 0:bb348c97df44 11783 #define TIM_SMCR_SMS_1 (0x2U << TIM_SMCR_SMS_Pos) /*!< 0x0002 */
lypinator 0:bb348c97df44 11784 #define TIM_SMCR_SMS_2 (0x4U << TIM_SMCR_SMS_Pos) /*!< 0x0004 */
lypinator 0:bb348c97df44 11785
lypinator 0:bb348c97df44 11786 #define TIM_SMCR_TS_Pos (4U)
lypinator 0:bb348c97df44 11787 #define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
lypinator 0:bb348c97df44 11788 #define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
lypinator 0:bb348c97df44 11789 #define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) /*!< 0x0010 */
lypinator 0:bb348c97df44 11790 #define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) /*!< 0x0020 */
lypinator 0:bb348c97df44 11791 #define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) /*!< 0x0040 */
lypinator 0:bb348c97df44 11792
lypinator 0:bb348c97df44 11793 #define TIM_SMCR_MSM_Pos (7U)
lypinator 0:bb348c97df44 11794 #define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 11795 #define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
lypinator 0:bb348c97df44 11796
lypinator 0:bb348c97df44 11797 #define TIM_SMCR_ETF_Pos (8U)
lypinator 0:bb348c97df44 11798 #define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
lypinator 0:bb348c97df44 11799 #define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
lypinator 0:bb348c97df44 11800 #define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /*!< 0x0100 */
lypinator 0:bb348c97df44 11801 #define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /*!< 0x0200 */
lypinator 0:bb348c97df44 11802 #define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /*!< 0x0400 */
lypinator 0:bb348c97df44 11803 #define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /*!< 0x0800 */
lypinator 0:bb348c97df44 11804
lypinator 0:bb348c97df44 11805 #define TIM_SMCR_ETPS_Pos (12U)
lypinator 0:bb348c97df44 11806 #define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
lypinator 0:bb348c97df44 11807 #define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
lypinator 0:bb348c97df44 11808 #define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /*!< 0x1000 */
lypinator 0:bb348c97df44 11809 #define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /*!< 0x2000 */
lypinator 0:bb348c97df44 11810
lypinator 0:bb348c97df44 11811 #define TIM_SMCR_ECE_Pos (14U)
lypinator 0:bb348c97df44 11812 #define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 11813 #define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
lypinator 0:bb348c97df44 11814 #define TIM_SMCR_ETP_Pos (15U)
lypinator 0:bb348c97df44 11815 #define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 11816 #define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
lypinator 0:bb348c97df44 11817
lypinator 0:bb348c97df44 11818 /******************* Bit definition for TIM_DIER register *******************/
lypinator 0:bb348c97df44 11819 #define TIM_DIER_UIE_Pos (0U)
lypinator 0:bb348c97df44 11820 #define TIM_DIER_UIE_Msk (0x1U << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 11821 #define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
lypinator 0:bb348c97df44 11822 #define TIM_DIER_CC1IE_Pos (1U)
lypinator 0:bb348c97df44 11823 #define TIM_DIER_CC1IE_Msk (0x1U << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 11824 #define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
lypinator 0:bb348c97df44 11825 #define TIM_DIER_CC2IE_Pos (2U)
lypinator 0:bb348c97df44 11826 #define TIM_DIER_CC2IE_Msk (0x1U << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 11827 #define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
lypinator 0:bb348c97df44 11828 #define TIM_DIER_CC3IE_Pos (3U)
lypinator 0:bb348c97df44 11829 #define TIM_DIER_CC3IE_Msk (0x1U << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 11830 #define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
lypinator 0:bb348c97df44 11831 #define TIM_DIER_CC4IE_Pos (4U)
lypinator 0:bb348c97df44 11832 #define TIM_DIER_CC4IE_Msk (0x1U << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 11833 #define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
lypinator 0:bb348c97df44 11834 #define TIM_DIER_COMIE_Pos (5U)
lypinator 0:bb348c97df44 11835 #define TIM_DIER_COMIE_Msk (0x1U << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 11836 #define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
lypinator 0:bb348c97df44 11837 #define TIM_DIER_TIE_Pos (6U)
lypinator 0:bb348c97df44 11838 #define TIM_DIER_TIE_Msk (0x1U << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 11839 #define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
lypinator 0:bb348c97df44 11840 #define TIM_DIER_BIE_Pos (7U)
lypinator 0:bb348c97df44 11841 #define TIM_DIER_BIE_Msk (0x1U << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 11842 #define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
lypinator 0:bb348c97df44 11843 #define TIM_DIER_UDE_Pos (8U)
lypinator 0:bb348c97df44 11844 #define TIM_DIER_UDE_Msk (0x1U << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 11845 #define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
lypinator 0:bb348c97df44 11846 #define TIM_DIER_CC1DE_Pos (9U)
lypinator 0:bb348c97df44 11847 #define TIM_DIER_CC1DE_Msk (0x1U << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 11848 #define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
lypinator 0:bb348c97df44 11849 #define TIM_DIER_CC2DE_Pos (10U)
lypinator 0:bb348c97df44 11850 #define TIM_DIER_CC2DE_Msk (0x1U << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 11851 #define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
lypinator 0:bb348c97df44 11852 #define TIM_DIER_CC3DE_Pos (11U)
lypinator 0:bb348c97df44 11853 #define TIM_DIER_CC3DE_Msk (0x1U << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 11854 #define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
lypinator 0:bb348c97df44 11855 #define TIM_DIER_CC4DE_Pos (12U)
lypinator 0:bb348c97df44 11856 #define TIM_DIER_CC4DE_Msk (0x1U << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 11857 #define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
lypinator 0:bb348c97df44 11858 #define TIM_DIER_COMDE_Pos (13U)
lypinator 0:bb348c97df44 11859 #define TIM_DIER_COMDE_Msk (0x1U << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 11860 #define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
lypinator 0:bb348c97df44 11861 #define TIM_DIER_TDE_Pos (14U)
lypinator 0:bb348c97df44 11862 #define TIM_DIER_TDE_Msk (0x1U << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 11863 #define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
lypinator 0:bb348c97df44 11864
lypinator 0:bb348c97df44 11865 /******************** Bit definition for TIM_SR register ********************/
lypinator 0:bb348c97df44 11866 #define TIM_SR_UIF_Pos (0U)
lypinator 0:bb348c97df44 11867 #define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 11868 #define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
lypinator 0:bb348c97df44 11869 #define TIM_SR_CC1IF_Pos (1U)
lypinator 0:bb348c97df44 11870 #define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 11871 #define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
lypinator 0:bb348c97df44 11872 #define TIM_SR_CC2IF_Pos (2U)
lypinator 0:bb348c97df44 11873 #define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 11874 #define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
lypinator 0:bb348c97df44 11875 #define TIM_SR_CC3IF_Pos (3U)
lypinator 0:bb348c97df44 11876 #define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 11877 #define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
lypinator 0:bb348c97df44 11878 #define TIM_SR_CC4IF_Pos (4U)
lypinator 0:bb348c97df44 11879 #define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 11880 #define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
lypinator 0:bb348c97df44 11881 #define TIM_SR_COMIF_Pos (5U)
lypinator 0:bb348c97df44 11882 #define TIM_SR_COMIF_Msk (0x1U << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 11883 #define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
lypinator 0:bb348c97df44 11884 #define TIM_SR_TIF_Pos (6U)
lypinator 0:bb348c97df44 11885 #define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 11886 #define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
lypinator 0:bb348c97df44 11887 #define TIM_SR_BIF_Pos (7U)
lypinator 0:bb348c97df44 11888 #define TIM_SR_BIF_Msk (0x1U << TIM_SR_BIF_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 11889 #define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
lypinator 0:bb348c97df44 11890 #define TIM_SR_CC1OF_Pos (9U)
lypinator 0:bb348c97df44 11891 #define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 11892 #define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
lypinator 0:bb348c97df44 11893 #define TIM_SR_CC2OF_Pos (10U)
lypinator 0:bb348c97df44 11894 #define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 11895 #define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
lypinator 0:bb348c97df44 11896 #define TIM_SR_CC3OF_Pos (11U)
lypinator 0:bb348c97df44 11897 #define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 11898 #define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
lypinator 0:bb348c97df44 11899 #define TIM_SR_CC4OF_Pos (12U)
lypinator 0:bb348c97df44 11900 #define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 11901 #define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
lypinator 0:bb348c97df44 11902
lypinator 0:bb348c97df44 11903 /******************* Bit definition for TIM_EGR register ********************/
lypinator 0:bb348c97df44 11904 #define TIM_EGR_UG_Pos (0U)
lypinator 0:bb348c97df44 11905 #define TIM_EGR_UG_Msk (0x1U << TIM_EGR_UG_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 11906 #define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
lypinator 0:bb348c97df44 11907 #define TIM_EGR_CC1G_Pos (1U)
lypinator 0:bb348c97df44 11908 #define TIM_EGR_CC1G_Msk (0x1U << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 11909 #define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
lypinator 0:bb348c97df44 11910 #define TIM_EGR_CC2G_Pos (2U)
lypinator 0:bb348c97df44 11911 #define TIM_EGR_CC2G_Msk (0x1U << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 11912 #define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
lypinator 0:bb348c97df44 11913 #define TIM_EGR_CC3G_Pos (3U)
lypinator 0:bb348c97df44 11914 #define TIM_EGR_CC3G_Msk (0x1U << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 11915 #define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
lypinator 0:bb348c97df44 11916 #define TIM_EGR_CC4G_Pos (4U)
lypinator 0:bb348c97df44 11917 #define TIM_EGR_CC4G_Msk (0x1U << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 11918 #define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
lypinator 0:bb348c97df44 11919 #define TIM_EGR_COMG_Pos (5U)
lypinator 0:bb348c97df44 11920 #define TIM_EGR_COMG_Msk (0x1U << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 11921 #define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
lypinator 0:bb348c97df44 11922 #define TIM_EGR_TG_Pos (6U)
lypinator 0:bb348c97df44 11923 #define TIM_EGR_TG_Msk (0x1U << TIM_EGR_TG_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 11924 #define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
lypinator 0:bb348c97df44 11925 #define TIM_EGR_BG_Pos (7U)
lypinator 0:bb348c97df44 11926 #define TIM_EGR_BG_Msk (0x1U << TIM_EGR_BG_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 11927 #define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
lypinator 0:bb348c97df44 11928
lypinator 0:bb348c97df44 11929 /****************** Bit definition for TIM_CCMR1 register *******************/
lypinator 0:bb348c97df44 11930 #define TIM_CCMR1_CC1S_Pos (0U)
lypinator 0:bb348c97df44 11931 #define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
lypinator 0:bb348c97df44 11932 #define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
lypinator 0:bb348c97df44 11933 #define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /*!< 0x0001 */
lypinator 0:bb348c97df44 11934 #define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /*!< 0x0002 */
lypinator 0:bb348c97df44 11935
lypinator 0:bb348c97df44 11936 #define TIM_CCMR1_OC1FE_Pos (2U)
lypinator 0:bb348c97df44 11937 #define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 11938 #define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
lypinator 0:bb348c97df44 11939 #define TIM_CCMR1_OC1PE_Pos (3U)
lypinator 0:bb348c97df44 11940 #define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 11941 #define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
lypinator 0:bb348c97df44 11942
lypinator 0:bb348c97df44 11943 #define TIM_CCMR1_OC1M_Pos (4U)
lypinator 0:bb348c97df44 11944 #define TIM_CCMR1_OC1M_Msk (0x7U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */
lypinator 0:bb348c97df44 11945 #define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
lypinator 0:bb348c97df44 11946 #define TIM_CCMR1_OC1M_0 (0x1U << TIM_CCMR1_OC1M_Pos) /*!< 0x0010 */
lypinator 0:bb348c97df44 11947 #define TIM_CCMR1_OC1M_1 (0x2U << TIM_CCMR1_OC1M_Pos) /*!< 0x0020 */
lypinator 0:bb348c97df44 11948 #define TIM_CCMR1_OC1M_2 (0x4U << TIM_CCMR1_OC1M_Pos) /*!< 0x0040 */
lypinator 0:bb348c97df44 11949
lypinator 0:bb348c97df44 11950 #define TIM_CCMR1_OC1CE_Pos (7U)
lypinator 0:bb348c97df44 11951 #define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 11952 #define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
lypinator 0:bb348c97df44 11953
lypinator 0:bb348c97df44 11954 #define TIM_CCMR1_CC2S_Pos (8U)
lypinator 0:bb348c97df44 11955 #define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
lypinator 0:bb348c97df44 11956 #define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
lypinator 0:bb348c97df44 11957 #define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /*!< 0x0100 */
lypinator 0:bb348c97df44 11958 #define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /*!< 0x0200 */
lypinator 0:bb348c97df44 11959
lypinator 0:bb348c97df44 11960 #define TIM_CCMR1_OC2FE_Pos (10U)
lypinator 0:bb348c97df44 11961 #define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 11962 #define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
lypinator 0:bb348c97df44 11963 #define TIM_CCMR1_OC2PE_Pos (11U)
lypinator 0:bb348c97df44 11964 #define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 11965 #define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
lypinator 0:bb348c97df44 11966
lypinator 0:bb348c97df44 11967 #define TIM_CCMR1_OC2M_Pos (12U)
lypinator 0:bb348c97df44 11968 #define TIM_CCMR1_OC2M_Msk (0x7U << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */
lypinator 0:bb348c97df44 11969 #define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
lypinator 0:bb348c97df44 11970 #define TIM_CCMR1_OC2M_0 (0x1U << TIM_CCMR1_OC2M_Pos) /*!< 0x1000 */
lypinator 0:bb348c97df44 11971 #define TIM_CCMR1_OC2M_1 (0x2U << TIM_CCMR1_OC2M_Pos) /*!< 0x2000 */
lypinator 0:bb348c97df44 11972 #define TIM_CCMR1_OC2M_2 (0x4U << TIM_CCMR1_OC2M_Pos) /*!< 0x4000 */
lypinator 0:bb348c97df44 11973
lypinator 0:bb348c97df44 11974 #define TIM_CCMR1_OC2CE_Pos (15U)
lypinator 0:bb348c97df44 11975 #define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 11976 #define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
lypinator 0:bb348c97df44 11977
lypinator 0:bb348c97df44 11978 /*----------------------------------------------------------------------------*/
lypinator 0:bb348c97df44 11979
lypinator 0:bb348c97df44 11980 #define TIM_CCMR1_IC1PSC_Pos (2U)
lypinator 0:bb348c97df44 11981 #define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
lypinator 0:bb348c97df44 11982 #define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
lypinator 0:bb348c97df44 11983 #define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0004 */
lypinator 0:bb348c97df44 11984 #define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0008 */
lypinator 0:bb348c97df44 11985
lypinator 0:bb348c97df44 11986 #define TIM_CCMR1_IC1F_Pos (4U)
lypinator 0:bb348c97df44 11987 #define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
lypinator 0:bb348c97df44 11988 #define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
lypinator 0:bb348c97df44 11989 #define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /*!< 0x0010 */
lypinator 0:bb348c97df44 11990 #define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /*!< 0x0020 */
lypinator 0:bb348c97df44 11991 #define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /*!< 0x0040 */
lypinator 0:bb348c97df44 11992 #define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /*!< 0x0080 */
lypinator 0:bb348c97df44 11993
lypinator 0:bb348c97df44 11994 #define TIM_CCMR1_IC2PSC_Pos (10U)
lypinator 0:bb348c97df44 11995 #define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
lypinator 0:bb348c97df44 11996 #define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
lypinator 0:bb348c97df44 11997 #define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x0400 */
lypinator 0:bb348c97df44 11998 #define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x0800 */
lypinator 0:bb348c97df44 11999
lypinator 0:bb348c97df44 12000 #define TIM_CCMR1_IC2F_Pos (12U)
lypinator 0:bb348c97df44 12001 #define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
lypinator 0:bb348c97df44 12002 #define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
lypinator 0:bb348c97df44 12003 #define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /*!< 0x1000 */
lypinator 0:bb348c97df44 12004 #define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /*!< 0x2000 */
lypinator 0:bb348c97df44 12005 #define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /*!< 0x4000 */
lypinator 0:bb348c97df44 12006 #define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /*!< 0x8000 */
lypinator 0:bb348c97df44 12007
lypinator 0:bb348c97df44 12008 /****************** Bit definition for TIM_CCMR2 register *******************/
lypinator 0:bb348c97df44 12009 #define TIM_CCMR2_CC3S_Pos (0U)
lypinator 0:bb348c97df44 12010 #define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
lypinator 0:bb348c97df44 12011 #define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
lypinator 0:bb348c97df44 12012 #define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /*!< 0x0001 */
lypinator 0:bb348c97df44 12013 #define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /*!< 0x0002 */
lypinator 0:bb348c97df44 12014
lypinator 0:bb348c97df44 12015 #define TIM_CCMR2_OC3FE_Pos (2U)
lypinator 0:bb348c97df44 12016 #define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 12017 #define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
lypinator 0:bb348c97df44 12018 #define TIM_CCMR2_OC3PE_Pos (3U)
lypinator 0:bb348c97df44 12019 #define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 12020 #define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
lypinator 0:bb348c97df44 12021
lypinator 0:bb348c97df44 12022 #define TIM_CCMR2_OC3M_Pos (4U)
lypinator 0:bb348c97df44 12023 #define TIM_CCMR2_OC3M_Msk (0x7U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
lypinator 0:bb348c97df44 12024 #define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
lypinator 0:bb348c97df44 12025 #define TIM_CCMR2_OC3M_0 (0x1U << TIM_CCMR2_OC3M_Pos) /*!< 0x0010 */
lypinator 0:bb348c97df44 12026 #define TIM_CCMR2_OC3M_1 (0x2U << TIM_CCMR2_OC3M_Pos) /*!< 0x0020 */
lypinator 0:bb348c97df44 12027 #define TIM_CCMR2_OC3M_2 (0x4U << TIM_CCMR2_OC3M_Pos) /*!< 0x0040 */
lypinator 0:bb348c97df44 12028
lypinator 0:bb348c97df44 12029 #define TIM_CCMR2_OC3CE_Pos (7U)
lypinator 0:bb348c97df44 12030 #define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 12031 #define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
lypinator 0:bb348c97df44 12032
lypinator 0:bb348c97df44 12033 #define TIM_CCMR2_CC4S_Pos (8U)
lypinator 0:bb348c97df44 12034 #define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
lypinator 0:bb348c97df44 12035 #define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
lypinator 0:bb348c97df44 12036 #define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /*!< 0x0100 */
lypinator 0:bb348c97df44 12037 #define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /*!< 0x0200 */
lypinator 0:bb348c97df44 12038
lypinator 0:bb348c97df44 12039 #define TIM_CCMR2_OC4FE_Pos (10U)
lypinator 0:bb348c97df44 12040 #define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 12041 #define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
lypinator 0:bb348c97df44 12042 #define TIM_CCMR2_OC4PE_Pos (11U)
lypinator 0:bb348c97df44 12043 #define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 12044 #define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
lypinator 0:bb348c97df44 12045
lypinator 0:bb348c97df44 12046 #define TIM_CCMR2_OC4M_Pos (12U)
lypinator 0:bb348c97df44 12047 #define TIM_CCMR2_OC4M_Msk (0x7U << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
lypinator 0:bb348c97df44 12048 #define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
lypinator 0:bb348c97df44 12049 #define TIM_CCMR2_OC4M_0 (0x1U << TIM_CCMR2_OC4M_Pos) /*!< 0x1000 */
lypinator 0:bb348c97df44 12050 #define TIM_CCMR2_OC4M_1 (0x2U << TIM_CCMR2_OC4M_Pos) /*!< 0x2000 */
lypinator 0:bb348c97df44 12051 #define TIM_CCMR2_OC4M_2 (0x4U << TIM_CCMR2_OC4M_Pos) /*!< 0x4000 */
lypinator 0:bb348c97df44 12052
lypinator 0:bb348c97df44 12053 #define TIM_CCMR2_OC4CE_Pos (15U)
lypinator 0:bb348c97df44 12054 #define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 12055 #define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
lypinator 0:bb348c97df44 12056
lypinator 0:bb348c97df44 12057 /*----------------------------------------------------------------------------*/
lypinator 0:bb348c97df44 12058
lypinator 0:bb348c97df44 12059 #define TIM_CCMR2_IC3PSC_Pos (2U)
lypinator 0:bb348c97df44 12060 #define TIM_CCMR2_IC3PSC_Msk (0x3U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
lypinator 0:bb348c97df44 12061 #define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
lypinator 0:bb348c97df44 12062 #define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0004 */
lypinator 0:bb348c97df44 12063 #define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0008 */
lypinator 0:bb348c97df44 12064
lypinator 0:bb348c97df44 12065 #define TIM_CCMR2_IC3F_Pos (4U)
lypinator 0:bb348c97df44 12066 #define TIM_CCMR2_IC3F_Msk (0xFU << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
lypinator 0:bb348c97df44 12067 #define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
lypinator 0:bb348c97df44 12068 #define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) /*!< 0x0010 */
lypinator 0:bb348c97df44 12069 #define TIM_CCMR2_IC3F_1 (0x2U << TIM_CCMR2_IC3F_Pos) /*!< 0x0020 */
lypinator 0:bb348c97df44 12070 #define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) /*!< 0x0040 */
lypinator 0:bb348c97df44 12071 #define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) /*!< 0x0080 */
lypinator 0:bb348c97df44 12072
lypinator 0:bb348c97df44 12073 #define TIM_CCMR2_IC4PSC_Pos (10U)
lypinator 0:bb348c97df44 12074 #define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
lypinator 0:bb348c97df44 12075 #define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
lypinator 0:bb348c97df44 12076 #define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x0400 */
lypinator 0:bb348c97df44 12077 #define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x0800 */
lypinator 0:bb348c97df44 12078
lypinator 0:bb348c97df44 12079 #define TIM_CCMR2_IC4F_Pos (12U)
lypinator 0:bb348c97df44 12080 #define TIM_CCMR2_IC4F_Msk (0xFU << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
lypinator 0:bb348c97df44 12081 #define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
lypinator 0:bb348c97df44 12082 #define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) /*!< 0x1000 */
lypinator 0:bb348c97df44 12083 #define TIM_CCMR2_IC4F_1 (0x2U << TIM_CCMR2_IC4F_Pos) /*!< 0x2000 */
lypinator 0:bb348c97df44 12084 #define TIM_CCMR2_IC4F_2 (0x4U << TIM_CCMR2_IC4F_Pos) /*!< 0x4000 */
lypinator 0:bb348c97df44 12085 #define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) /*!< 0x8000 */
lypinator 0:bb348c97df44 12086
lypinator 0:bb348c97df44 12087 /******************* Bit definition for TIM_CCER register *******************/
lypinator 0:bb348c97df44 12088 #define TIM_CCER_CC1E_Pos (0U)
lypinator 0:bb348c97df44 12089 #define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 12090 #define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
lypinator 0:bb348c97df44 12091 #define TIM_CCER_CC1P_Pos (1U)
lypinator 0:bb348c97df44 12092 #define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 12093 #define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
lypinator 0:bb348c97df44 12094 #define TIM_CCER_CC1NE_Pos (2U)
lypinator 0:bb348c97df44 12095 #define TIM_CCER_CC1NE_Msk (0x1U << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 12096 #define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
lypinator 0:bb348c97df44 12097 #define TIM_CCER_CC1NP_Pos (3U)
lypinator 0:bb348c97df44 12098 #define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 12099 #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
lypinator 0:bb348c97df44 12100 #define TIM_CCER_CC2E_Pos (4U)
lypinator 0:bb348c97df44 12101 #define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 12102 #define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
lypinator 0:bb348c97df44 12103 #define TIM_CCER_CC2P_Pos (5U)
lypinator 0:bb348c97df44 12104 #define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 12105 #define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
lypinator 0:bb348c97df44 12106 #define TIM_CCER_CC2NE_Pos (6U)
lypinator 0:bb348c97df44 12107 #define TIM_CCER_CC2NE_Msk (0x1U << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 12108 #define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
lypinator 0:bb348c97df44 12109 #define TIM_CCER_CC2NP_Pos (7U)
lypinator 0:bb348c97df44 12110 #define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 12111 #define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
lypinator 0:bb348c97df44 12112 #define TIM_CCER_CC3E_Pos (8U)
lypinator 0:bb348c97df44 12113 #define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 12114 #define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
lypinator 0:bb348c97df44 12115 #define TIM_CCER_CC3P_Pos (9U)
lypinator 0:bb348c97df44 12116 #define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 12117 #define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
lypinator 0:bb348c97df44 12118 #define TIM_CCER_CC3NE_Pos (10U)
lypinator 0:bb348c97df44 12119 #define TIM_CCER_CC3NE_Msk (0x1U << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 12120 #define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
lypinator 0:bb348c97df44 12121 #define TIM_CCER_CC3NP_Pos (11U)
lypinator 0:bb348c97df44 12122 #define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 12123 #define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
lypinator 0:bb348c97df44 12124 #define TIM_CCER_CC4E_Pos (12U)
lypinator 0:bb348c97df44 12125 #define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 12126 #define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
lypinator 0:bb348c97df44 12127 #define TIM_CCER_CC4P_Pos (13U)
lypinator 0:bb348c97df44 12128 #define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 12129 #define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
lypinator 0:bb348c97df44 12130 #define TIM_CCER_CC4NP_Pos (15U)
lypinator 0:bb348c97df44 12131 #define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 12132 #define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
lypinator 0:bb348c97df44 12133
lypinator 0:bb348c97df44 12134 /******************* Bit definition for TIM_CNT register ********************/
lypinator 0:bb348c97df44 12135 #define TIM_CNT_CNT_Pos (0U)
lypinator 0:bb348c97df44 12136 #define TIM_CNT_CNT_Msk (0xFFFFFFFFU << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
lypinator 0:bb348c97df44 12137 #define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
lypinator 0:bb348c97df44 12138
lypinator 0:bb348c97df44 12139 /******************* Bit definition for TIM_PSC register ********************/
lypinator 0:bb348c97df44 12140 #define TIM_PSC_PSC_Pos (0U)
lypinator 0:bb348c97df44 12141 #define TIM_PSC_PSC_Msk (0xFFFFU << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
lypinator 0:bb348c97df44 12142 #define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
lypinator 0:bb348c97df44 12143
lypinator 0:bb348c97df44 12144 /******************* Bit definition for TIM_ARR register ********************/
lypinator 0:bb348c97df44 12145 #define TIM_ARR_ARR_Pos (0U)
lypinator 0:bb348c97df44 12146 #define TIM_ARR_ARR_Msk (0xFFFFFFFFU << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
lypinator 0:bb348c97df44 12147 #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
lypinator 0:bb348c97df44 12148
lypinator 0:bb348c97df44 12149 /******************* Bit definition for TIM_RCR register ********************/
lypinator 0:bb348c97df44 12150 #define TIM_RCR_REP_Pos (0U)
lypinator 0:bb348c97df44 12151 #define TIM_RCR_REP_Msk (0xFFU << TIM_RCR_REP_Pos) /*!< 0x000000FF */
lypinator 0:bb348c97df44 12152 #define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
lypinator 0:bb348c97df44 12153
lypinator 0:bb348c97df44 12154 /******************* Bit definition for TIM_CCR1 register *******************/
lypinator 0:bb348c97df44 12155 #define TIM_CCR1_CCR1_Pos (0U)
lypinator 0:bb348c97df44 12156 #define TIM_CCR1_CCR1_Msk (0xFFFFU << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
lypinator 0:bb348c97df44 12157 #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
lypinator 0:bb348c97df44 12158
lypinator 0:bb348c97df44 12159 /******************* Bit definition for TIM_CCR2 register *******************/
lypinator 0:bb348c97df44 12160 #define TIM_CCR2_CCR2_Pos (0U)
lypinator 0:bb348c97df44 12161 #define TIM_CCR2_CCR2_Msk (0xFFFFU << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
lypinator 0:bb348c97df44 12162 #define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
lypinator 0:bb348c97df44 12163
lypinator 0:bb348c97df44 12164 /******************* Bit definition for TIM_CCR3 register *******************/
lypinator 0:bb348c97df44 12165 #define TIM_CCR3_CCR3_Pos (0U)
lypinator 0:bb348c97df44 12166 #define TIM_CCR3_CCR3_Msk (0xFFFFU << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
lypinator 0:bb348c97df44 12167 #define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
lypinator 0:bb348c97df44 12168
lypinator 0:bb348c97df44 12169 /******************* Bit definition for TIM_CCR4 register *******************/
lypinator 0:bb348c97df44 12170 #define TIM_CCR4_CCR4_Pos (0U)
lypinator 0:bb348c97df44 12171 #define TIM_CCR4_CCR4_Msk (0xFFFFU << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
lypinator 0:bb348c97df44 12172 #define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
lypinator 0:bb348c97df44 12173
lypinator 0:bb348c97df44 12174 /******************* Bit definition for TIM_BDTR register *******************/
lypinator 0:bb348c97df44 12175 #define TIM_BDTR_DTG_Pos (0U)
lypinator 0:bb348c97df44 12176 #define TIM_BDTR_DTG_Msk (0xFFU << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
lypinator 0:bb348c97df44 12177 #define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
lypinator 0:bb348c97df44 12178 #define TIM_BDTR_DTG_0 (0x01U << TIM_BDTR_DTG_Pos) /*!< 0x0001 */
lypinator 0:bb348c97df44 12179 #define TIM_BDTR_DTG_1 (0x02U << TIM_BDTR_DTG_Pos) /*!< 0x0002 */
lypinator 0:bb348c97df44 12180 #define TIM_BDTR_DTG_2 (0x04U << TIM_BDTR_DTG_Pos) /*!< 0x0004 */
lypinator 0:bb348c97df44 12181 #define TIM_BDTR_DTG_3 (0x08U << TIM_BDTR_DTG_Pos) /*!< 0x0008 */
lypinator 0:bb348c97df44 12182 #define TIM_BDTR_DTG_4 (0x10U << TIM_BDTR_DTG_Pos) /*!< 0x0010 */
lypinator 0:bb348c97df44 12183 #define TIM_BDTR_DTG_5 (0x20U << TIM_BDTR_DTG_Pos) /*!< 0x0020 */
lypinator 0:bb348c97df44 12184 #define TIM_BDTR_DTG_6 (0x40U << TIM_BDTR_DTG_Pos) /*!< 0x0040 */
lypinator 0:bb348c97df44 12185 #define TIM_BDTR_DTG_7 (0x80U << TIM_BDTR_DTG_Pos) /*!< 0x0080 */
lypinator 0:bb348c97df44 12186
lypinator 0:bb348c97df44 12187 #define TIM_BDTR_LOCK_Pos (8U)
lypinator 0:bb348c97df44 12188 #define TIM_BDTR_LOCK_Msk (0x3U << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
lypinator 0:bb348c97df44 12189 #define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
lypinator 0:bb348c97df44 12190 #define TIM_BDTR_LOCK_0 (0x1U << TIM_BDTR_LOCK_Pos) /*!< 0x0100 */
lypinator 0:bb348c97df44 12191 #define TIM_BDTR_LOCK_1 (0x2U << TIM_BDTR_LOCK_Pos) /*!< 0x0200 */
lypinator 0:bb348c97df44 12192
lypinator 0:bb348c97df44 12193 #define TIM_BDTR_OSSI_Pos (10U)
lypinator 0:bb348c97df44 12194 #define TIM_BDTR_OSSI_Msk (0x1U << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 12195 #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
lypinator 0:bb348c97df44 12196 #define TIM_BDTR_OSSR_Pos (11U)
lypinator 0:bb348c97df44 12197 #define TIM_BDTR_OSSR_Msk (0x1U << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 12198 #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
lypinator 0:bb348c97df44 12199 #define TIM_BDTR_BKE_Pos (12U)
lypinator 0:bb348c97df44 12200 #define TIM_BDTR_BKE_Msk (0x1U << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 12201 #define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable */
lypinator 0:bb348c97df44 12202 #define TIM_BDTR_BKP_Pos (13U)
lypinator 0:bb348c97df44 12203 #define TIM_BDTR_BKP_Msk (0x1U << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 12204 #define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity */
lypinator 0:bb348c97df44 12205 #define TIM_BDTR_AOE_Pos (14U)
lypinator 0:bb348c97df44 12206 #define TIM_BDTR_AOE_Msk (0x1U << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 12207 #define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
lypinator 0:bb348c97df44 12208 #define TIM_BDTR_MOE_Pos (15U)
lypinator 0:bb348c97df44 12209 #define TIM_BDTR_MOE_Msk (0x1U << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 12210 #define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
lypinator 0:bb348c97df44 12211
lypinator 0:bb348c97df44 12212 /******************* Bit definition for TIM_DCR register ********************/
lypinator 0:bb348c97df44 12213 #define TIM_DCR_DBA_Pos (0U)
lypinator 0:bb348c97df44 12214 #define TIM_DCR_DBA_Msk (0x1FU << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
lypinator 0:bb348c97df44 12215 #define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
lypinator 0:bb348c97df44 12216 #define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) /*!< 0x0001 */
lypinator 0:bb348c97df44 12217 #define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) /*!< 0x0002 */
lypinator 0:bb348c97df44 12218 #define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) /*!< 0x0004 */
lypinator 0:bb348c97df44 12219 #define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) /*!< 0x0008 */
lypinator 0:bb348c97df44 12220 #define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) /*!< 0x0010 */
lypinator 0:bb348c97df44 12221
lypinator 0:bb348c97df44 12222 #define TIM_DCR_DBL_Pos (8U)
lypinator 0:bb348c97df44 12223 #define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
lypinator 0:bb348c97df44 12224 #define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
lypinator 0:bb348c97df44 12225 #define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x0100 */
lypinator 0:bb348c97df44 12226 #define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /*!< 0x0200 */
lypinator 0:bb348c97df44 12227 #define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /*!< 0x0400 */
lypinator 0:bb348c97df44 12228 #define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /*!< 0x0800 */
lypinator 0:bb348c97df44 12229 #define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x1000 */
lypinator 0:bb348c97df44 12230
lypinator 0:bb348c97df44 12231 /******************* Bit definition for TIM_DMAR register *******************/
lypinator 0:bb348c97df44 12232 #define TIM_DMAR_DMAB_Pos (0U)
lypinator 0:bb348c97df44 12233 #define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
lypinator 0:bb348c97df44 12234 #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
lypinator 0:bb348c97df44 12235
lypinator 0:bb348c97df44 12236 /******************* Bit definition for TIM_OR register *********************/
lypinator 0:bb348c97df44 12237 #define TIM_OR_TI1_RMP_Pos (0U)
lypinator 0:bb348c97df44 12238 #define TIM_OR_TI1_RMP_Msk (0x3U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000003 */
lypinator 0:bb348c97df44 12239 #define TIM_OR_TI1_RMP TIM_OR_TI1_RMP_Msk /*!< TI1_RMP[1:0] bits (TIM11 Input Capture 1 remap) */
lypinator 0:bb348c97df44 12240 #define TIM_OR_TI1_RMP_0 (0x1U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 12241 #define TIM_OR_TI1_RMP_1 (0x2U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 12242
lypinator 0:bb348c97df44 12243 #define TIM_OR_TI4_RMP_Pos (6U)
lypinator 0:bb348c97df44 12244 #define TIM_OR_TI4_RMP_Msk (0x3U << TIM_OR_TI4_RMP_Pos) /*!< 0x000000C0 */
lypinator 0:bb348c97df44 12245 #define TIM_OR_TI4_RMP TIM_OR_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
lypinator 0:bb348c97df44 12246 #define TIM_OR_TI4_RMP_0 (0x1U << TIM_OR_TI4_RMP_Pos) /*!< 0x0040 */
lypinator 0:bb348c97df44 12247 #define TIM_OR_TI4_RMP_1 (0x2U << TIM_OR_TI4_RMP_Pos) /*!< 0x0080 */
lypinator 0:bb348c97df44 12248 #define TIM_OR_ITR1_RMP_Pos (10U)
lypinator 0:bb348c97df44 12249 #define TIM_OR_ITR1_RMP_Msk (0x3U << TIM_OR_ITR1_RMP_Pos) /*!< 0x00000C00 */
lypinator 0:bb348c97df44 12250 #define TIM_OR_ITR1_RMP TIM_OR_ITR1_RMP_Msk /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
lypinator 0:bb348c97df44 12251 #define TIM_OR_ITR1_RMP_0 (0x1U << TIM_OR_ITR1_RMP_Pos) /*!< 0x0400 */
lypinator 0:bb348c97df44 12252 #define TIM_OR_ITR1_RMP_1 (0x2U << TIM_OR_ITR1_RMP_Pos) /*!< 0x0800 */
lypinator 0:bb348c97df44 12253
lypinator 0:bb348c97df44 12254
lypinator 0:bb348c97df44 12255 /******************************************************************************/
lypinator 0:bb348c97df44 12256 /* */
lypinator 0:bb348c97df44 12257 /* Universal Synchronous Asynchronous Receiver Transmitter */
lypinator 0:bb348c97df44 12258 /* */
lypinator 0:bb348c97df44 12259 /******************************************************************************/
lypinator 0:bb348c97df44 12260 /******************* Bit definition for USART_SR register *******************/
lypinator 0:bb348c97df44 12261 #define USART_SR_PE_Pos (0U)
lypinator 0:bb348c97df44 12262 #define USART_SR_PE_Msk (0x1U << USART_SR_PE_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 12263 #define USART_SR_PE USART_SR_PE_Msk /*!<Parity Error */
lypinator 0:bb348c97df44 12264 #define USART_SR_FE_Pos (1U)
lypinator 0:bb348c97df44 12265 #define USART_SR_FE_Msk (0x1U << USART_SR_FE_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 12266 #define USART_SR_FE USART_SR_FE_Msk /*!<Framing Error */
lypinator 0:bb348c97df44 12267 #define USART_SR_NE_Pos (2U)
lypinator 0:bb348c97df44 12268 #define USART_SR_NE_Msk (0x1U << USART_SR_NE_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 12269 #define USART_SR_NE USART_SR_NE_Msk /*!<Noise Error Flag */
lypinator 0:bb348c97df44 12270 #define USART_SR_ORE_Pos (3U)
lypinator 0:bb348c97df44 12271 #define USART_SR_ORE_Msk (0x1U << USART_SR_ORE_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 12272 #define USART_SR_ORE USART_SR_ORE_Msk /*!<OverRun Error */
lypinator 0:bb348c97df44 12273 #define USART_SR_IDLE_Pos (4U)
lypinator 0:bb348c97df44 12274 #define USART_SR_IDLE_Msk (0x1U << USART_SR_IDLE_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 12275 #define USART_SR_IDLE USART_SR_IDLE_Msk /*!<IDLE line detected */
lypinator 0:bb348c97df44 12276 #define USART_SR_RXNE_Pos (5U)
lypinator 0:bb348c97df44 12277 #define USART_SR_RXNE_Msk (0x1U << USART_SR_RXNE_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 12278 #define USART_SR_RXNE USART_SR_RXNE_Msk /*!<Read Data Register Not Empty */
lypinator 0:bb348c97df44 12279 #define USART_SR_TC_Pos (6U)
lypinator 0:bb348c97df44 12280 #define USART_SR_TC_Msk (0x1U << USART_SR_TC_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 12281 #define USART_SR_TC USART_SR_TC_Msk /*!<Transmission Complete */
lypinator 0:bb348c97df44 12282 #define USART_SR_TXE_Pos (7U)
lypinator 0:bb348c97df44 12283 #define USART_SR_TXE_Msk (0x1U << USART_SR_TXE_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 12284 #define USART_SR_TXE USART_SR_TXE_Msk /*!<Transmit Data Register Empty */
lypinator 0:bb348c97df44 12285 #define USART_SR_LBD_Pos (8U)
lypinator 0:bb348c97df44 12286 #define USART_SR_LBD_Msk (0x1U << USART_SR_LBD_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 12287 #define USART_SR_LBD USART_SR_LBD_Msk /*!<LIN Break Detection Flag */
lypinator 0:bb348c97df44 12288 #define USART_SR_CTS_Pos (9U)
lypinator 0:bb348c97df44 12289 #define USART_SR_CTS_Msk (0x1U << USART_SR_CTS_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 12290 #define USART_SR_CTS USART_SR_CTS_Msk /*!<CTS Flag */
lypinator 0:bb348c97df44 12291
lypinator 0:bb348c97df44 12292 /******************* Bit definition for USART_DR register *******************/
lypinator 0:bb348c97df44 12293 #define USART_DR_DR_Pos (0U)
lypinator 0:bb348c97df44 12294 #define USART_DR_DR_Msk (0x1FFU << USART_DR_DR_Pos) /*!< 0x000001FF */
lypinator 0:bb348c97df44 12295 #define USART_DR_DR USART_DR_DR_Msk /*!<Data value */
lypinator 0:bb348c97df44 12296
lypinator 0:bb348c97df44 12297 /****************** Bit definition for USART_BRR register *******************/
lypinator 0:bb348c97df44 12298 #define USART_BRR_DIV_Fraction_Pos (0U)
lypinator 0:bb348c97df44 12299 #define USART_BRR_DIV_Fraction_Msk (0xFU << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */
lypinator 0:bb348c97df44 12300 #define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /*!<Fraction of USARTDIV */
lypinator 0:bb348c97df44 12301 #define USART_BRR_DIV_Mantissa_Pos (4U)
lypinator 0:bb348c97df44 12302 #define USART_BRR_DIV_Mantissa_Msk (0xFFFU << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */
lypinator 0:bb348c97df44 12303 #define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /*!<Mantissa of USARTDIV */
lypinator 0:bb348c97df44 12304
lypinator 0:bb348c97df44 12305 /****************** Bit definition for USART_CR1 register *******************/
lypinator 0:bb348c97df44 12306 #define USART_CR1_SBK_Pos (0U)
lypinator 0:bb348c97df44 12307 #define USART_CR1_SBK_Msk (0x1U << USART_CR1_SBK_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 12308 #define USART_CR1_SBK USART_CR1_SBK_Msk /*!<Send Break */
lypinator 0:bb348c97df44 12309 #define USART_CR1_RWU_Pos (1U)
lypinator 0:bb348c97df44 12310 #define USART_CR1_RWU_Msk (0x1U << USART_CR1_RWU_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 12311 #define USART_CR1_RWU USART_CR1_RWU_Msk /*!<Receiver wakeup */
lypinator 0:bb348c97df44 12312 #define USART_CR1_RE_Pos (2U)
lypinator 0:bb348c97df44 12313 #define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 12314 #define USART_CR1_RE USART_CR1_RE_Msk /*!<Receiver Enable */
lypinator 0:bb348c97df44 12315 #define USART_CR1_TE_Pos (3U)
lypinator 0:bb348c97df44 12316 #define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 12317 #define USART_CR1_TE USART_CR1_TE_Msk /*!<Transmitter Enable */
lypinator 0:bb348c97df44 12318 #define USART_CR1_IDLEIE_Pos (4U)
lypinator 0:bb348c97df44 12319 #define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 12320 #define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!<IDLE Interrupt Enable */
lypinator 0:bb348c97df44 12321 #define USART_CR1_RXNEIE_Pos (5U)
lypinator 0:bb348c97df44 12322 #define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 12323 #define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!<RXNE Interrupt Enable */
lypinator 0:bb348c97df44 12324 #define USART_CR1_TCIE_Pos (6U)
lypinator 0:bb348c97df44 12325 #define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 12326 #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!<Transmission Complete Interrupt Enable */
lypinator 0:bb348c97df44 12327 #define USART_CR1_TXEIE_Pos (7U)
lypinator 0:bb348c97df44 12328 #define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 12329 #define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!<TXE Interrupt Enable */
lypinator 0:bb348c97df44 12330 #define USART_CR1_PEIE_Pos (8U)
lypinator 0:bb348c97df44 12331 #define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 12332 #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!<PE Interrupt Enable */
lypinator 0:bb348c97df44 12333 #define USART_CR1_PS_Pos (9U)
lypinator 0:bb348c97df44 12334 #define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 12335 #define USART_CR1_PS USART_CR1_PS_Msk /*!<Parity Selection */
lypinator 0:bb348c97df44 12336 #define USART_CR1_PCE_Pos (10U)
lypinator 0:bb348c97df44 12337 #define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 12338 #define USART_CR1_PCE USART_CR1_PCE_Msk /*!<Parity Control Enable */
lypinator 0:bb348c97df44 12339 #define USART_CR1_WAKE_Pos (11U)
lypinator 0:bb348c97df44 12340 #define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 12341 #define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!<Wakeup method */
lypinator 0:bb348c97df44 12342 #define USART_CR1_M_Pos (12U)
lypinator 0:bb348c97df44 12343 #define USART_CR1_M_Msk (0x1U << USART_CR1_M_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 12344 #define USART_CR1_M USART_CR1_M_Msk /*!<Word length */
lypinator 0:bb348c97df44 12345 #define USART_CR1_UE_Pos (13U)
lypinator 0:bb348c97df44 12346 #define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 12347 #define USART_CR1_UE USART_CR1_UE_Msk /*!<USART Enable */
lypinator 0:bb348c97df44 12348 #define USART_CR1_OVER8_Pos (15U)
lypinator 0:bb348c97df44 12349 #define USART_CR1_OVER8_Msk (0x1U << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 12350 #define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!<USART Oversampling by 8 enable */
lypinator 0:bb348c97df44 12351
lypinator 0:bb348c97df44 12352 /****************** Bit definition for USART_CR2 register *******************/
lypinator 0:bb348c97df44 12353 #define USART_CR2_ADD_Pos (0U)
lypinator 0:bb348c97df44 12354 #define USART_CR2_ADD_Msk (0xFU << USART_CR2_ADD_Pos) /*!< 0x0000000F */
lypinator 0:bb348c97df44 12355 #define USART_CR2_ADD USART_CR2_ADD_Msk /*!<Address of the USART node */
lypinator 0:bb348c97df44 12356 #define USART_CR2_LBDL_Pos (5U)
lypinator 0:bb348c97df44 12357 #define USART_CR2_LBDL_Msk (0x1U << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 12358 #define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!<LIN Break Detection Length */
lypinator 0:bb348c97df44 12359 #define USART_CR2_LBDIE_Pos (6U)
lypinator 0:bb348c97df44 12360 #define USART_CR2_LBDIE_Msk (0x1U << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 12361 #define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!<LIN Break Detection Interrupt Enable */
lypinator 0:bb348c97df44 12362 #define USART_CR2_LBCL_Pos (8U)
lypinator 0:bb348c97df44 12363 #define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 12364 #define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!<Last Bit Clock pulse */
lypinator 0:bb348c97df44 12365 #define USART_CR2_CPHA_Pos (9U)
lypinator 0:bb348c97df44 12366 #define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 12367 #define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!<Clock Phase */
lypinator 0:bb348c97df44 12368 #define USART_CR2_CPOL_Pos (10U)
lypinator 0:bb348c97df44 12369 #define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 12370 #define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!<Clock Polarity */
lypinator 0:bb348c97df44 12371 #define USART_CR2_CLKEN_Pos (11U)
lypinator 0:bb348c97df44 12372 #define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 12373 #define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!<Clock Enable */
lypinator 0:bb348c97df44 12374
lypinator 0:bb348c97df44 12375 #define USART_CR2_STOP_Pos (12U)
lypinator 0:bb348c97df44 12376 #define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /*!< 0x00003000 */
lypinator 0:bb348c97df44 12377 #define USART_CR2_STOP USART_CR2_STOP_Msk /*!<STOP[1:0] bits (STOP bits) */
lypinator 0:bb348c97df44 12378 #define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /*!< 0x1000 */
lypinator 0:bb348c97df44 12379 #define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /*!< 0x2000 */
lypinator 0:bb348c97df44 12380
lypinator 0:bb348c97df44 12381 #define USART_CR2_LINEN_Pos (14U)
lypinator 0:bb348c97df44 12382 #define USART_CR2_LINEN_Msk (0x1U << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 12383 #define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!<LIN mode enable */
lypinator 0:bb348c97df44 12384
lypinator 0:bb348c97df44 12385 /****************** Bit definition for USART_CR3 register *******************/
lypinator 0:bb348c97df44 12386 #define USART_CR3_EIE_Pos (0U)
lypinator 0:bb348c97df44 12387 #define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 12388 #define USART_CR3_EIE USART_CR3_EIE_Msk /*!<Error Interrupt Enable */
lypinator 0:bb348c97df44 12389 #define USART_CR3_IREN_Pos (1U)
lypinator 0:bb348c97df44 12390 #define USART_CR3_IREN_Msk (0x1U << USART_CR3_IREN_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 12391 #define USART_CR3_IREN USART_CR3_IREN_Msk /*!<IrDA mode Enable */
lypinator 0:bb348c97df44 12392 #define USART_CR3_IRLP_Pos (2U)
lypinator 0:bb348c97df44 12393 #define USART_CR3_IRLP_Msk (0x1U << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 12394 #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!<IrDA Low-Power */
lypinator 0:bb348c97df44 12395 #define USART_CR3_HDSEL_Pos (3U)
lypinator 0:bb348c97df44 12396 #define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 12397 #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!<Half-Duplex Selection */
lypinator 0:bb348c97df44 12398 #define USART_CR3_NACK_Pos (4U)
lypinator 0:bb348c97df44 12399 #define USART_CR3_NACK_Msk (0x1U << USART_CR3_NACK_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 12400 #define USART_CR3_NACK USART_CR3_NACK_Msk /*!<Smartcard NACK enable */
lypinator 0:bb348c97df44 12401 #define USART_CR3_SCEN_Pos (5U)
lypinator 0:bb348c97df44 12402 #define USART_CR3_SCEN_Msk (0x1U << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 12403 #define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!<Smartcard mode enable */
lypinator 0:bb348c97df44 12404 #define USART_CR3_DMAR_Pos (6U)
lypinator 0:bb348c97df44 12405 #define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 12406 #define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!<DMA Enable Receiver */
lypinator 0:bb348c97df44 12407 #define USART_CR3_DMAT_Pos (7U)
lypinator 0:bb348c97df44 12408 #define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 12409 #define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!<DMA Enable Transmitter */
lypinator 0:bb348c97df44 12410 #define USART_CR3_RTSE_Pos (8U)
lypinator 0:bb348c97df44 12411 #define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 12412 #define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!<RTS Enable */
lypinator 0:bb348c97df44 12413 #define USART_CR3_CTSE_Pos (9U)
lypinator 0:bb348c97df44 12414 #define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 12415 #define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!<CTS Enable */
lypinator 0:bb348c97df44 12416 #define USART_CR3_CTSIE_Pos (10U)
lypinator 0:bb348c97df44 12417 #define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 12418 #define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!<CTS Interrupt Enable */
lypinator 0:bb348c97df44 12419 #define USART_CR3_ONEBIT_Pos (11U)
lypinator 0:bb348c97df44 12420 #define USART_CR3_ONEBIT_Msk (0x1U << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 12421 #define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!<USART One bit method enable */
lypinator 0:bb348c97df44 12422
lypinator 0:bb348c97df44 12423 /****************** Bit definition for USART_GTPR register ******************/
lypinator 0:bb348c97df44 12424 #define USART_GTPR_PSC_Pos (0U)
lypinator 0:bb348c97df44 12425 #define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
lypinator 0:bb348c97df44 12426 #define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!<PSC[7:0] bits (Prescaler value) */
lypinator 0:bb348c97df44 12427 #define USART_GTPR_PSC_0 (0x01U << USART_GTPR_PSC_Pos) /*!< 0x0001 */
lypinator 0:bb348c97df44 12428 #define USART_GTPR_PSC_1 (0x02U << USART_GTPR_PSC_Pos) /*!< 0x0002 */
lypinator 0:bb348c97df44 12429 #define USART_GTPR_PSC_2 (0x04U << USART_GTPR_PSC_Pos) /*!< 0x0004 */
lypinator 0:bb348c97df44 12430 #define USART_GTPR_PSC_3 (0x08U << USART_GTPR_PSC_Pos) /*!< 0x0008 */
lypinator 0:bb348c97df44 12431 #define USART_GTPR_PSC_4 (0x10U << USART_GTPR_PSC_Pos) /*!< 0x0010 */
lypinator 0:bb348c97df44 12432 #define USART_GTPR_PSC_5 (0x20U << USART_GTPR_PSC_Pos) /*!< 0x0020 */
lypinator 0:bb348c97df44 12433 #define USART_GTPR_PSC_6 (0x40U << USART_GTPR_PSC_Pos) /*!< 0x0040 */
lypinator 0:bb348c97df44 12434 #define USART_GTPR_PSC_7 (0x80U << USART_GTPR_PSC_Pos) /*!< 0x0080 */
lypinator 0:bb348c97df44 12435
lypinator 0:bb348c97df44 12436 #define USART_GTPR_GT_Pos (8U)
lypinator 0:bb348c97df44 12437 #define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
lypinator 0:bb348c97df44 12438 #define USART_GTPR_GT USART_GTPR_GT_Msk /*!<Guard time value */
lypinator 0:bb348c97df44 12439
lypinator 0:bb348c97df44 12440 /******************************************************************************/
lypinator 0:bb348c97df44 12441 /* */
lypinator 0:bb348c97df44 12442 /* Window WATCHDOG */
lypinator 0:bb348c97df44 12443 /* */
lypinator 0:bb348c97df44 12444 /******************************************************************************/
lypinator 0:bb348c97df44 12445 /******************* Bit definition for WWDG_CR register ********************/
lypinator 0:bb348c97df44 12446 #define WWDG_CR_T_Pos (0U)
lypinator 0:bb348c97df44 12447 #define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) /*!< 0x0000007F */
lypinator 0:bb348c97df44 12448 #define WWDG_CR_T WWDG_CR_T_Msk /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
lypinator 0:bb348c97df44 12449 #define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /*!< 0x01 */
lypinator 0:bb348c97df44 12450 #define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) /*!< 0x02 */
lypinator 0:bb348c97df44 12451 #define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) /*!< 0x04 */
lypinator 0:bb348c97df44 12452 #define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) /*!< 0x08 */
lypinator 0:bb348c97df44 12453 #define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) /*!< 0x10 */
lypinator 0:bb348c97df44 12454 #define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) /*!< 0x20 */
lypinator 0:bb348c97df44 12455 #define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) /*!< 0x40 */
lypinator 0:bb348c97df44 12456 /* Legacy defines */
lypinator 0:bb348c97df44 12457 #define WWDG_CR_T0 WWDG_CR_T_0
lypinator 0:bb348c97df44 12458 #define WWDG_CR_T1 WWDG_CR_T_1
lypinator 0:bb348c97df44 12459 #define WWDG_CR_T2 WWDG_CR_T_2
lypinator 0:bb348c97df44 12460 #define WWDG_CR_T3 WWDG_CR_T_3
lypinator 0:bb348c97df44 12461 #define WWDG_CR_T4 WWDG_CR_T_4
lypinator 0:bb348c97df44 12462 #define WWDG_CR_T5 WWDG_CR_T_5
lypinator 0:bb348c97df44 12463 #define WWDG_CR_T6 WWDG_CR_T_6
lypinator 0:bb348c97df44 12464
lypinator 0:bb348c97df44 12465 #define WWDG_CR_WDGA_Pos (7U)
lypinator 0:bb348c97df44 12466 #define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 12467 #define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!<Activation bit */
lypinator 0:bb348c97df44 12468
lypinator 0:bb348c97df44 12469 /******************* Bit definition for WWDG_CFR register *******************/
lypinator 0:bb348c97df44 12470 #define WWDG_CFR_W_Pos (0U)
lypinator 0:bb348c97df44 12471 #define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) /*!< 0x0000007F */
lypinator 0:bb348c97df44 12472 #define WWDG_CFR_W WWDG_CFR_W_Msk /*!<W[6:0] bits (7-bit window value) */
lypinator 0:bb348c97df44 12473 #define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /*!< 0x0001 */
lypinator 0:bb348c97df44 12474 #define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) /*!< 0x0002 */
lypinator 0:bb348c97df44 12475 #define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) /*!< 0x0004 */
lypinator 0:bb348c97df44 12476 #define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) /*!< 0x0008 */
lypinator 0:bb348c97df44 12477 #define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) /*!< 0x0010 */
lypinator 0:bb348c97df44 12478 #define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) /*!< 0x0020 */
lypinator 0:bb348c97df44 12479 #define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) /*!< 0x0040 */
lypinator 0:bb348c97df44 12480 /* Legacy defines */
lypinator 0:bb348c97df44 12481 #define WWDG_CFR_W0 WWDG_CFR_W_0
lypinator 0:bb348c97df44 12482 #define WWDG_CFR_W1 WWDG_CFR_W_1
lypinator 0:bb348c97df44 12483 #define WWDG_CFR_W2 WWDG_CFR_W_2
lypinator 0:bb348c97df44 12484 #define WWDG_CFR_W3 WWDG_CFR_W_3
lypinator 0:bb348c97df44 12485 #define WWDG_CFR_W4 WWDG_CFR_W_4
lypinator 0:bb348c97df44 12486 #define WWDG_CFR_W5 WWDG_CFR_W_5
lypinator 0:bb348c97df44 12487 #define WWDG_CFR_W6 WWDG_CFR_W_6
lypinator 0:bb348c97df44 12488
lypinator 0:bb348c97df44 12489 #define WWDG_CFR_WDGTB_Pos (7U)
lypinator 0:bb348c97df44 12490 #define WWDG_CFR_WDGTB_Msk (0x3U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
lypinator 0:bb348c97df44 12491 #define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!<WDGTB[1:0] bits (Timer Base) */
lypinator 0:bb348c97df44 12492 #define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /*!< 0x0080 */
lypinator 0:bb348c97df44 12493 #define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) /*!< 0x0100 */
lypinator 0:bb348c97df44 12494 /* Legacy defines */
lypinator 0:bb348c97df44 12495 #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
lypinator 0:bb348c97df44 12496 #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
lypinator 0:bb348c97df44 12497
lypinator 0:bb348c97df44 12498 #define WWDG_CFR_EWI_Pos (9U)
lypinator 0:bb348c97df44 12499 #define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 12500 #define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!<Early Wakeup Interrupt */
lypinator 0:bb348c97df44 12501
lypinator 0:bb348c97df44 12502 /******************* Bit definition for WWDG_SR register ********************/
lypinator 0:bb348c97df44 12503 #define WWDG_SR_EWIF_Pos (0U)
lypinator 0:bb348c97df44 12504 #define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 12505 #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!<Early Wakeup Interrupt Flag */
lypinator 0:bb348c97df44 12506
lypinator 0:bb348c97df44 12507
lypinator 0:bb348c97df44 12508 /******************************************************************************/
lypinator 0:bb348c97df44 12509 /* */
lypinator 0:bb348c97df44 12510 /* DBG */
lypinator 0:bb348c97df44 12511 /* */
lypinator 0:bb348c97df44 12512 /******************************************************************************/
lypinator 0:bb348c97df44 12513 /******************** Bit definition for DBGMCU_IDCODE register *************/
lypinator 0:bb348c97df44 12514 #define DBGMCU_IDCODE_DEV_ID_Pos (0U)
lypinator 0:bb348c97df44 12515 #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
lypinator 0:bb348c97df44 12516 #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
lypinator 0:bb348c97df44 12517 #define DBGMCU_IDCODE_REV_ID_Pos (16U)
lypinator 0:bb348c97df44 12518 #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
lypinator 0:bb348c97df44 12519 #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
lypinator 0:bb348c97df44 12520
lypinator 0:bb348c97df44 12521 /******************** Bit definition for DBGMCU_CR register *****************/
lypinator 0:bb348c97df44 12522 #define DBGMCU_CR_DBG_SLEEP_Pos (0U)
lypinator 0:bb348c97df44 12523 #define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 12524 #define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk
lypinator 0:bb348c97df44 12525 #define DBGMCU_CR_DBG_STOP_Pos (1U)
lypinator 0:bb348c97df44 12526 #define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 12527 #define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk
lypinator 0:bb348c97df44 12528 #define DBGMCU_CR_DBG_STANDBY_Pos (2U)
lypinator 0:bb348c97df44 12529 #define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 12530 #define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk
lypinator 0:bb348c97df44 12531 #define DBGMCU_CR_TRACE_IOEN_Pos (5U)
lypinator 0:bb348c97df44 12532 #define DBGMCU_CR_TRACE_IOEN_Msk (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 12533 #define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk
lypinator 0:bb348c97df44 12534
lypinator 0:bb348c97df44 12535 #define DBGMCU_CR_TRACE_MODE_Pos (6U)
lypinator 0:bb348c97df44 12536 #define DBGMCU_CR_TRACE_MODE_Msk (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
lypinator 0:bb348c97df44 12537 #define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk
lypinator 0:bb348c97df44 12538 #define DBGMCU_CR_TRACE_MODE_0 (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 12539 #define DBGMCU_CR_TRACE_MODE_1 (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 12540
lypinator 0:bb348c97df44 12541 /******************** Bit definition for DBGMCU_APB1_FZ register ************/
lypinator 0:bb348c97df44 12542 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)
lypinator 0:bb348c97df44 12543 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 12544 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk
lypinator 0:bb348c97df44 12545 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U)
lypinator 0:bb348c97df44 12546 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 12547 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk
lypinator 0:bb348c97df44 12548 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos (2U)
lypinator 0:bb348c97df44 12549 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 12550 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk
lypinator 0:bb348c97df44 12551 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos (3U)
lypinator 0:bb348c97df44 12552 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 12553 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk
lypinator 0:bb348c97df44 12554 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U)
lypinator 0:bb348c97df44 12555 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 12556 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk
lypinator 0:bb348c97df44 12557 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos (5U)
lypinator 0:bb348c97df44 12558 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 12559 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk
lypinator 0:bb348c97df44 12560 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos (6U)
lypinator 0:bb348c97df44 12561 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 12562 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk
lypinator 0:bb348c97df44 12563 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos (7U)
lypinator 0:bb348c97df44 12564 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 12565 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk
lypinator 0:bb348c97df44 12566 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos (8U)
lypinator 0:bb348c97df44 12567 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 12568 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk
lypinator 0:bb348c97df44 12569 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
lypinator 0:bb348c97df44 12570 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 12571 #define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk
lypinator 0:bb348c97df44 12572 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
lypinator 0:bb348c97df44 12573 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 12574 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk
lypinator 0:bb348c97df44 12575 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
lypinator 0:bb348c97df44 12576 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 12577 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk
lypinator 0:bb348c97df44 12578 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)
lypinator 0:bb348c97df44 12579 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 12580 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk
lypinator 0:bb348c97df44 12581 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U)
lypinator 0:bb348c97df44 12582 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 12583 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk
lypinator 0:bb348c97df44 12584 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos (23U)
lypinator 0:bb348c97df44 12585 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos) /*!< 0x00800000 */
lypinator 0:bb348c97df44 12586 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk
lypinator 0:bb348c97df44 12587 #define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Pos (24U)
lypinator 0:bb348c97df44 12588 #define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 12589 #define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Msk
lypinator 0:bb348c97df44 12590 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos (25U)
lypinator 0:bb348c97df44 12591 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 12592 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk
lypinator 0:bb348c97df44 12593 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos (26U)
lypinator 0:bb348c97df44 12594 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos) /*!< 0x04000000 */
lypinator 0:bb348c97df44 12595 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk
lypinator 0:bb348c97df44 12596
lypinator 0:bb348c97df44 12597 /******************** Bit definition for DBGMCU_APB2_FZ register ************/
lypinator 0:bb348c97df44 12598 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos (0U)
lypinator 0:bb348c97df44 12599 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 12600 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk
lypinator 0:bb348c97df44 12601 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos (1U)
lypinator 0:bb348c97df44 12602 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 12603 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk
lypinator 0:bb348c97df44 12604 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos (16U)
lypinator 0:bb348c97df44 12605 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 12606 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk
lypinator 0:bb348c97df44 12607 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos (17U)
lypinator 0:bb348c97df44 12608 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 12609 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk
lypinator 0:bb348c97df44 12610 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos (18U)
lypinator 0:bb348c97df44 12611 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 12612 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk
lypinator 0:bb348c97df44 12613
lypinator 0:bb348c97df44 12614 /******************************************************************************/
lypinator 0:bb348c97df44 12615 /* */
lypinator 0:bb348c97df44 12616 /* USB_OTG */
lypinator 0:bb348c97df44 12617 /* */
lypinator 0:bb348c97df44 12618 /******************************************************************************/
lypinator 0:bb348c97df44 12619 /******************** Bit definition for USB_OTG_GOTGCTL register ***********/
lypinator 0:bb348c97df44 12620 #define USB_OTG_GOTGCTL_SRQSCS_Pos (0U)
lypinator 0:bb348c97df44 12621 #define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1U << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 12622 #define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk /*!< Session request success */
lypinator 0:bb348c97df44 12623 #define USB_OTG_GOTGCTL_SRQ_Pos (1U)
lypinator 0:bb348c97df44 12624 #define USB_OTG_GOTGCTL_SRQ_Msk (0x1U << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 12625 #define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk /*!< Session request */
lypinator 0:bb348c97df44 12626 #define USB_OTG_GOTGCTL_VBVALOEN_Pos (2U)
lypinator 0:bb348c97df44 12627 #define USB_OTG_GOTGCTL_VBVALOEN_Msk (0x1U << USB_OTG_GOTGCTL_VBVALOEN_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 12628 #define USB_OTG_GOTGCTL_VBVALOEN USB_OTG_GOTGCTL_VBVALOEN_Msk /*!< VBUS valid override enable */
lypinator 0:bb348c97df44 12629 #define USB_OTG_GOTGCTL_VBVALOVAL_Pos (3U)
lypinator 0:bb348c97df44 12630 #define USB_OTG_GOTGCTL_VBVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_VBVALOVAL_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 12631 #define USB_OTG_GOTGCTL_VBVALOVAL USB_OTG_GOTGCTL_VBVALOVAL_Msk /*!< VBUS valid override value */
lypinator 0:bb348c97df44 12632 #define USB_OTG_GOTGCTL_AVALOEN_Pos (4U)
lypinator 0:bb348c97df44 12633 #define USB_OTG_GOTGCTL_AVALOEN_Msk (0x1U << USB_OTG_GOTGCTL_AVALOEN_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 12634 #define USB_OTG_GOTGCTL_AVALOEN USB_OTG_GOTGCTL_AVALOEN_Msk /*!< A-peripheral session valid override enable */
lypinator 0:bb348c97df44 12635 #define USB_OTG_GOTGCTL_AVALOVAL_Pos (5U)
lypinator 0:bb348c97df44 12636 #define USB_OTG_GOTGCTL_AVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_AVALOVAL_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 12637 #define USB_OTG_GOTGCTL_AVALOVAL USB_OTG_GOTGCTL_AVALOVAL_Msk /*!< A-peripheral session valid override value */
lypinator 0:bb348c97df44 12638 #define USB_OTG_GOTGCTL_BVALOEN_Pos (6U)
lypinator 0:bb348c97df44 12639 #define USB_OTG_GOTGCTL_BVALOEN_Msk (0x1U << USB_OTG_GOTGCTL_BVALOEN_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 12640 #define USB_OTG_GOTGCTL_BVALOEN USB_OTG_GOTGCTL_BVALOEN_Msk /*!< B-peripheral session valid override enable */
lypinator 0:bb348c97df44 12641 #define USB_OTG_GOTGCTL_BVALOVAL_Pos (7U)
lypinator 0:bb348c97df44 12642 #define USB_OTG_GOTGCTL_BVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 12643 #define USB_OTG_GOTGCTL_BVALOVAL USB_OTG_GOTGCTL_BVALOVAL_Msk /*!< B-peripheral session valid override value */
lypinator 0:bb348c97df44 12644 #define USB_OTG_GOTGCTL_HNGSCS_Pos (8U)
lypinator 0:bb348c97df44 12645 #define USB_OTG_GOTGCTL_HNGSCS_Msk (0x1U << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 12646 #define USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_Msk /*!< Host set HNP enable */
lypinator 0:bb348c97df44 12647 #define USB_OTG_GOTGCTL_HNPRQ_Pos (9U)
lypinator 0:bb348c97df44 12648 #define USB_OTG_GOTGCTL_HNPRQ_Msk (0x1U << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 12649 #define USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_Msk /*!< HNP request */
lypinator 0:bb348c97df44 12650 #define USB_OTG_GOTGCTL_HSHNPEN_Pos (10U)
lypinator 0:bb348c97df44 12651 #define USB_OTG_GOTGCTL_HSHNPEN_Msk (0x1U << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 12652 #define USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_Msk /*!< Host set HNP enable */
lypinator 0:bb348c97df44 12653 #define USB_OTG_GOTGCTL_DHNPEN_Pos (11U)
lypinator 0:bb348c97df44 12654 #define USB_OTG_GOTGCTL_DHNPEN_Msk (0x1U << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 12655 #define USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_Msk /*!< Device HNP enabled */
lypinator 0:bb348c97df44 12656 #define USB_OTG_GOTGCTL_EHEN_Pos (12U)
lypinator 0:bb348c97df44 12657 #define USB_OTG_GOTGCTL_EHEN_Msk (0x1U << USB_OTG_GOTGCTL_EHEN_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 12658 #define USB_OTG_GOTGCTL_EHEN USB_OTG_GOTGCTL_EHEN_Msk /*!< Embedded host enable */
lypinator 0:bb348c97df44 12659 #define USB_OTG_GOTGCTL_CIDSTS_Pos (16U)
lypinator 0:bb348c97df44 12660 #define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1U << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 12661 #define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk /*!< Connector ID status */
lypinator 0:bb348c97df44 12662 #define USB_OTG_GOTGCTL_DBCT_Pos (17U)
lypinator 0:bb348c97df44 12663 #define USB_OTG_GOTGCTL_DBCT_Msk (0x1U << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 12664 #define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk /*!< Long/short debounce time */
lypinator 0:bb348c97df44 12665 #define USB_OTG_GOTGCTL_ASVLD_Pos (18U)
lypinator 0:bb348c97df44 12666 #define USB_OTG_GOTGCTL_ASVLD_Msk (0x1U << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 12667 #define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid */
lypinator 0:bb348c97df44 12668 #define USB_OTG_GOTGCTL_BSESVLD_Pos (19U)
lypinator 0:bb348c97df44 12669 #define USB_OTG_GOTGCTL_BSESVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 12670 #define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSESVLD_Msk /*!< B-session valid */
lypinator 0:bb348c97df44 12671 #define USB_OTG_GOTGCTL_OTGVER_Pos (20U)
lypinator 0:bb348c97df44 12672 #define USB_OTG_GOTGCTL_OTGVER_Msk (0x1U << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 12673 #define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */
lypinator 0:bb348c97df44 12674
lypinator 0:bb348c97df44 12675 /******************** Bit definition forUSB_OTG_HCFG register ********************/
lypinator 0:bb348c97df44 12676
lypinator 0:bb348c97df44 12677 #define USB_OTG_HCFG_FSLSPCS_Pos (0U)
lypinator 0:bb348c97df44 12678 #define USB_OTG_HCFG_FSLSPCS_Msk (0x3U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */
lypinator 0:bb348c97df44 12679 #define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk /*!< FS/LS PHY clock select */
lypinator 0:bb348c97df44 12680 #define USB_OTG_HCFG_FSLSPCS_0 (0x1U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 12681 #define USB_OTG_HCFG_FSLSPCS_1 (0x2U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 12682 #define USB_OTG_HCFG_FSLSS_Pos (2U)
lypinator 0:bb348c97df44 12683 #define USB_OTG_HCFG_FSLSS_Msk (0x1U << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 12684 #define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk /*!< FS- and LS-only support */
lypinator 0:bb348c97df44 12685
lypinator 0:bb348c97df44 12686 /******************** Bit definition for USB_OTG_DCFG register ********************/
lypinator 0:bb348c97df44 12687
lypinator 0:bb348c97df44 12688 #define USB_OTG_DCFG_DSPD_Pos (0U)
lypinator 0:bb348c97df44 12689 #define USB_OTG_DCFG_DSPD_Msk (0x3U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */
lypinator 0:bb348c97df44 12690 #define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk /*!< Device speed */
lypinator 0:bb348c97df44 12691 #define USB_OTG_DCFG_DSPD_0 (0x1U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 12692 #define USB_OTG_DCFG_DSPD_1 (0x2U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 12693 #define USB_OTG_DCFG_NZLSOHSK_Pos (2U)
lypinator 0:bb348c97df44 12694 #define USB_OTG_DCFG_NZLSOHSK_Msk (0x1U << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 12695 #define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk /*!< Nonzero-length status OUT handshake */
lypinator 0:bb348c97df44 12696
lypinator 0:bb348c97df44 12697 #define USB_OTG_DCFG_DAD_Pos (4U)
lypinator 0:bb348c97df44 12698 #define USB_OTG_DCFG_DAD_Msk (0x7FU << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
lypinator 0:bb348c97df44 12699 #define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
lypinator 0:bb348c97df44 12700 #define USB_OTG_DCFG_DAD_0 (0x01U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 12701 #define USB_OTG_DCFG_DAD_1 (0x02U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 12702 #define USB_OTG_DCFG_DAD_2 (0x04U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 12703 #define USB_OTG_DCFG_DAD_3 (0x08U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 12704 #define USB_OTG_DCFG_DAD_4 (0x10U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 12705 #define USB_OTG_DCFG_DAD_5 (0x20U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 12706 #define USB_OTG_DCFG_DAD_6 (0x40U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 12707
lypinator 0:bb348c97df44 12708 #define USB_OTG_DCFG_PFIVL_Pos (11U)
lypinator 0:bb348c97df44 12709 #define USB_OTG_DCFG_PFIVL_Msk (0x3U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
lypinator 0:bb348c97df44 12710 #define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
lypinator 0:bb348c97df44 12711 #define USB_OTG_DCFG_PFIVL_0 (0x1U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 12712 #define USB_OTG_DCFG_PFIVL_1 (0x2U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 12713
lypinator 0:bb348c97df44 12714 #define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
lypinator 0:bb348c97df44 12715 #define USB_OTG_DCFG_PERSCHIVL_Msk (0x3U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
lypinator 0:bb348c97df44 12716 #define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
lypinator 0:bb348c97df44 12717 #define USB_OTG_DCFG_PERSCHIVL_0 (0x1U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 12718 #define USB_OTG_DCFG_PERSCHIVL_1 (0x2U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 12719
lypinator 0:bb348c97df44 12720 /******************** Bit definition for USB_OTG_PCGCR register ********************/
lypinator 0:bb348c97df44 12721 #define USB_OTG_PCGCR_STPPCLK_Pos (0U)
lypinator 0:bb348c97df44 12722 #define USB_OTG_PCGCR_STPPCLK_Msk (0x1U << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 12723 #define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk /*!< Stop PHY clock */
lypinator 0:bb348c97df44 12724 #define USB_OTG_PCGCR_GATEHCLK_Pos (1U)
lypinator 0:bb348c97df44 12725 #define USB_OTG_PCGCR_GATEHCLK_Msk (0x1U << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 12726 #define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk /*!< Gate HCLK */
lypinator 0:bb348c97df44 12727 #define USB_OTG_PCGCR_PHYSUSP_Pos (4U)
lypinator 0:bb348c97df44 12728 #define USB_OTG_PCGCR_PHYSUSP_Msk (0x1U << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 12729 #define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk /*!< PHY suspended */
lypinator 0:bb348c97df44 12730
lypinator 0:bb348c97df44 12731 /******************** Bit definition for USB_OTG_GOTGINT register ********************/
lypinator 0:bb348c97df44 12732 #define USB_OTG_GOTGINT_SEDET_Pos (2U)
lypinator 0:bb348c97df44 12733 #define USB_OTG_GOTGINT_SEDET_Msk (0x1U << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 12734 #define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk /*!< Session end detected */
lypinator 0:bb348c97df44 12735 #define USB_OTG_GOTGINT_SRSSCHG_Pos (8U)
lypinator 0:bb348c97df44 12736 #define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1U << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 12737 #define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk /*!< Session request success status change */
lypinator 0:bb348c97df44 12738 #define USB_OTG_GOTGINT_HNSSCHG_Pos (9U)
lypinator 0:bb348c97df44 12739 #define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1U << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 12740 #define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk /*!< Host negotiation success status change */
lypinator 0:bb348c97df44 12741 #define USB_OTG_GOTGINT_HNGDET_Pos (17U)
lypinator 0:bb348c97df44 12742 #define USB_OTG_GOTGINT_HNGDET_Msk (0x1U << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 12743 #define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk /*!< Host negotiation detected */
lypinator 0:bb348c97df44 12744 #define USB_OTG_GOTGINT_ADTOCHG_Pos (18U)
lypinator 0:bb348c97df44 12745 #define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1U << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 12746 #define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk /*!< A-device timeout change */
lypinator 0:bb348c97df44 12747 #define USB_OTG_GOTGINT_DBCDNE_Pos (19U)
lypinator 0:bb348c97df44 12748 #define USB_OTG_GOTGINT_DBCDNE_Msk (0x1U << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 12749 #define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk /*!< Debounce done */
lypinator 0:bb348c97df44 12750 #define USB_OTG_GOTGINT_IDCHNG_Pos (20U)
lypinator 0:bb348c97df44 12751 #define USB_OTG_GOTGINT_IDCHNG_Msk (0x1U << USB_OTG_GOTGINT_IDCHNG_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 12752 #define USB_OTG_GOTGINT_IDCHNG USB_OTG_GOTGINT_IDCHNG_Msk /*!< Change in ID pin input value */
lypinator 0:bb348c97df44 12753
lypinator 0:bb348c97df44 12754 /******************** Bit definition for USB_OTG_DCTL register ********************/
lypinator 0:bb348c97df44 12755 #define USB_OTG_DCTL_RWUSIG_Pos (0U)
lypinator 0:bb348c97df44 12756 #define USB_OTG_DCTL_RWUSIG_Msk (0x1U << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 12757 #define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk /*!< Remote wakeup signaling */
lypinator 0:bb348c97df44 12758 #define USB_OTG_DCTL_SDIS_Pos (1U)
lypinator 0:bb348c97df44 12759 #define USB_OTG_DCTL_SDIS_Msk (0x1U << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 12760 #define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk /*!< Soft disconnect */
lypinator 0:bb348c97df44 12761 #define USB_OTG_DCTL_GINSTS_Pos (2U)
lypinator 0:bb348c97df44 12762 #define USB_OTG_DCTL_GINSTS_Msk (0x1U << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 12763 #define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk /*!< Global IN NAK status */
lypinator 0:bb348c97df44 12764 #define USB_OTG_DCTL_GONSTS_Pos (3U)
lypinator 0:bb348c97df44 12765 #define USB_OTG_DCTL_GONSTS_Msk (0x1U << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 12766 #define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk /*!< Global OUT NAK status */
lypinator 0:bb348c97df44 12767
lypinator 0:bb348c97df44 12768 #define USB_OTG_DCTL_TCTL_Pos (4U)
lypinator 0:bb348c97df44 12769 #define USB_OTG_DCTL_TCTL_Msk (0x7U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */
lypinator 0:bb348c97df44 12770 #define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk /*!< Test control */
lypinator 0:bb348c97df44 12771 #define USB_OTG_DCTL_TCTL_0 (0x1U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 12772 #define USB_OTG_DCTL_TCTL_1 (0x2U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 12773 #define USB_OTG_DCTL_TCTL_2 (0x4U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 12774 #define USB_OTG_DCTL_SGINAK_Pos (7U)
lypinator 0:bb348c97df44 12775 #define USB_OTG_DCTL_SGINAK_Msk (0x1U << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 12776 #define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk /*!< Set global IN NAK */
lypinator 0:bb348c97df44 12777 #define USB_OTG_DCTL_CGINAK_Pos (8U)
lypinator 0:bb348c97df44 12778 #define USB_OTG_DCTL_CGINAK_Msk (0x1U << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 12779 #define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk /*!< Clear global IN NAK */
lypinator 0:bb348c97df44 12780 #define USB_OTG_DCTL_SGONAK_Pos (9U)
lypinator 0:bb348c97df44 12781 #define USB_OTG_DCTL_SGONAK_Msk (0x1U << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 12782 #define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk /*!< Set global OUT NAK */
lypinator 0:bb348c97df44 12783 #define USB_OTG_DCTL_CGONAK_Pos (10U)
lypinator 0:bb348c97df44 12784 #define USB_OTG_DCTL_CGONAK_Msk (0x1U << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 12785 #define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk /*!< Clear global OUT NAK */
lypinator 0:bb348c97df44 12786 #define USB_OTG_DCTL_POPRGDNE_Pos (11U)
lypinator 0:bb348c97df44 12787 #define USB_OTG_DCTL_POPRGDNE_Msk (0x1U << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 12788 #define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */
lypinator 0:bb348c97df44 12789
lypinator 0:bb348c97df44 12790 /******************** Bit definition for USB_OTG_HFIR register ********************/
lypinator 0:bb348c97df44 12791 #define USB_OTG_HFIR_FRIVL_Pos (0U)
lypinator 0:bb348c97df44 12792 #define USB_OTG_HFIR_FRIVL_Msk (0xFFFFU << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */
lypinator 0:bb348c97df44 12793 #define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */
lypinator 0:bb348c97df44 12794
lypinator 0:bb348c97df44 12795 /******************** Bit definition for USB_OTG_HFNUM register ********************/
lypinator 0:bb348c97df44 12796 #define USB_OTG_HFNUM_FRNUM_Pos (0U)
lypinator 0:bb348c97df44 12797 #define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFU << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */
lypinator 0:bb348c97df44 12798 #define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk /*!< Frame number */
lypinator 0:bb348c97df44 12799 #define USB_OTG_HFNUM_FTREM_Pos (16U)
lypinator 0:bb348c97df44 12800 #define USB_OTG_HFNUM_FTREM_Msk (0xFFFFU << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */
lypinator 0:bb348c97df44 12801 #define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk /*!< Frame time remaining */
lypinator 0:bb348c97df44 12802
lypinator 0:bb348c97df44 12803 /******************** Bit definition for USB_OTG_DSTS register ********************/
lypinator 0:bb348c97df44 12804 #define USB_OTG_DSTS_SUSPSTS_Pos (0U)
lypinator 0:bb348c97df44 12805 #define USB_OTG_DSTS_SUSPSTS_Msk (0x1U << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 12806 #define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk /*!< Suspend status */
lypinator 0:bb348c97df44 12807
lypinator 0:bb348c97df44 12808 #define USB_OTG_DSTS_ENUMSPD_Pos (1U)
lypinator 0:bb348c97df44 12809 #define USB_OTG_DSTS_ENUMSPD_Msk (0x3U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */
lypinator 0:bb348c97df44 12810 #define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk /*!< Enumerated speed */
lypinator 0:bb348c97df44 12811 #define USB_OTG_DSTS_ENUMSPD_0 (0x1U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 12812 #define USB_OTG_DSTS_ENUMSPD_1 (0x2U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 12813 #define USB_OTG_DSTS_EERR_Pos (3U)
lypinator 0:bb348c97df44 12814 #define USB_OTG_DSTS_EERR_Msk (0x1U << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 12815 #define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk /*!< Erratic error */
lypinator 0:bb348c97df44 12816 #define USB_OTG_DSTS_FNSOF_Pos (8U)
lypinator 0:bb348c97df44 12817 #define USB_OTG_DSTS_FNSOF_Msk (0x3FFFU << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */
lypinator 0:bb348c97df44 12818 #define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */
lypinator 0:bb348c97df44 12819
lypinator 0:bb348c97df44 12820 /******************** Bit definition for USB_OTG_GAHBCFG register ********************/
lypinator 0:bb348c97df44 12821 #define USB_OTG_GAHBCFG_GINT_Pos (0U)
lypinator 0:bb348c97df44 12822 #define USB_OTG_GAHBCFG_GINT_Msk (0x1U << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 12823 #define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */
lypinator 0:bb348c97df44 12824 #define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U)
lypinator 0:bb348c97df44 12825 #define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFU << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */
lypinator 0:bb348c97df44 12826 #define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */
lypinator 0:bb348c97df44 12827 #define USB_OTG_GAHBCFG_HBSTLEN_0 (0x0U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */
lypinator 0:bb348c97df44 12828 #define USB_OTG_GAHBCFG_HBSTLEN_1 (0x1U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */
lypinator 0:bb348c97df44 12829 #define USB_OTG_GAHBCFG_HBSTLEN_2 (0x3U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */
lypinator 0:bb348c97df44 12830 #define USB_OTG_GAHBCFG_HBSTLEN_3 (0x5U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */
lypinator 0:bb348c97df44 12831 #define USB_OTG_GAHBCFG_HBSTLEN_4 (0x7U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */
lypinator 0:bb348c97df44 12832 #define USB_OTG_GAHBCFG_DMAEN_Pos (5U)
lypinator 0:bb348c97df44 12833 #define USB_OTG_GAHBCFG_DMAEN_Msk (0x1U << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 12834 #define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk /*!< DMA enable */
lypinator 0:bb348c97df44 12835 #define USB_OTG_GAHBCFG_TXFELVL_Pos (7U)
lypinator 0:bb348c97df44 12836 #define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 12837 #define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk /*!< TxFIFO empty level */
lypinator 0:bb348c97df44 12838 #define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U)
lypinator 0:bb348c97df44 12839 #define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 12840 #define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk /*!< Periodic TxFIFO empty level */
lypinator 0:bb348c97df44 12841
lypinator 0:bb348c97df44 12842 /******************** Bit definition for USB_OTG_GUSBCFG register ********************/
lypinator 0:bb348c97df44 12843
lypinator 0:bb348c97df44 12844 #define USB_OTG_GUSBCFG_TOCAL_Pos (0U)
lypinator 0:bb348c97df44 12845 #define USB_OTG_GUSBCFG_TOCAL_Msk (0x7U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */
lypinator 0:bb348c97df44 12846 #define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk /*!< FS timeout calibration */
lypinator 0:bb348c97df44 12847 #define USB_OTG_GUSBCFG_TOCAL_0 (0x1U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 12848 #define USB_OTG_GUSBCFG_TOCAL_1 (0x2U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 12849 #define USB_OTG_GUSBCFG_TOCAL_2 (0x4U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 12850 #define USB_OTG_GUSBCFG_PHYSEL_Pos (6U)
lypinator 0:bb348c97df44 12851 #define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1U << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 12852 #define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
lypinator 0:bb348c97df44 12853 #define USB_OTG_GUSBCFG_SRPCAP_Pos (8U)
lypinator 0:bb348c97df44 12854 #define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1U << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 12855 #define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk /*!< SRP-capable */
lypinator 0:bb348c97df44 12856 #define USB_OTG_GUSBCFG_HNPCAP_Pos (9U)
lypinator 0:bb348c97df44 12857 #define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1U << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 12858 #define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk /*!< HNP-capable */
lypinator 0:bb348c97df44 12859 #define USB_OTG_GUSBCFG_TRDT_Pos (10U)
lypinator 0:bb348c97df44 12860 #define USB_OTG_GUSBCFG_TRDT_Msk (0xFU << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */
lypinator 0:bb348c97df44 12861 #define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk /*!< USB turnaround time */
lypinator 0:bb348c97df44 12862 #define USB_OTG_GUSBCFG_TRDT_0 (0x1U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 12863 #define USB_OTG_GUSBCFG_TRDT_1 (0x2U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 12864 #define USB_OTG_GUSBCFG_TRDT_2 (0x4U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 12865 #define USB_OTG_GUSBCFG_TRDT_3 (0x8U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 12866 #define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U)
lypinator 0:bb348c97df44 12867 #define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 12868 #define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */
lypinator 0:bb348c97df44 12869 #define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U)
lypinator 0:bb348c97df44 12870 #define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1U << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 12871 #define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */
lypinator 0:bb348c97df44 12872 #define USB_OTG_GUSBCFG_ULPIAR_Pos (18U)
lypinator 0:bb348c97df44 12873 #define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1U << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 12874 #define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk /*!< ULPI Auto-resume */
lypinator 0:bb348c97df44 12875 #define USB_OTG_GUSBCFG_ULPICSM_Pos (19U)
lypinator 0:bb348c97df44 12876 #define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1U << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 12877 #define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk /*!< ULPI Clock SuspendM */
lypinator 0:bb348c97df44 12878 #define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U)
lypinator 0:bb348c97df44 12879 #define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 12880 #define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive */
lypinator 0:bb348c97df44 12881 #define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U)
lypinator 0:bb348c97df44 12882 #define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 12883 #define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator */
lypinator 0:bb348c97df44 12884 #define USB_OTG_GUSBCFG_TSDPS_Pos (22U)
lypinator 0:bb348c97df44 12885 #define USB_OTG_GUSBCFG_TSDPS_Msk (0x1U << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 12886 #define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk /*!< TermSel DLine pulsing selection */
lypinator 0:bb348c97df44 12887 #define USB_OTG_GUSBCFG_PCCI_Pos (23U)
lypinator 0:bb348c97df44 12888 #define USB_OTG_GUSBCFG_PCCI_Msk (0x1U << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */
lypinator 0:bb348c97df44 12889 #define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk /*!< Indicator complement */
lypinator 0:bb348c97df44 12890 #define USB_OTG_GUSBCFG_PTCI_Pos (24U)
lypinator 0:bb348c97df44 12891 #define USB_OTG_GUSBCFG_PTCI_Msk (0x1U << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 12892 #define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk /*!< Indicator pass through */
lypinator 0:bb348c97df44 12893 #define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U)
lypinator 0:bb348c97df44 12894 #define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 12895 #define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk /*!< ULPI interface protect disable */
lypinator 0:bb348c97df44 12896 #define USB_OTG_GUSBCFG_FHMOD_Pos (29U)
lypinator 0:bb348c97df44 12897 #define USB_OTG_GUSBCFG_FHMOD_Msk (0x1U << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */
lypinator 0:bb348c97df44 12898 #define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk /*!< Forced host mode */
lypinator 0:bb348c97df44 12899 #define USB_OTG_GUSBCFG_FDMOD_Pos (30U)
lypinator 0:bb348c97df44 12900 #define USB_OTG_GUSBCFG_FDMOD_Msk (0x1U << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */
lypinator 0:bb348c97df44 12901 #define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */
lypinator 0:bb348c97df44 12902 #define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
lypinator 0:bb348c97df44 12903 #define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1U << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
lypinator 0:bb348c97df44 12904 #define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */
lypinator 0:bb348c97df44 12905
lypinator 0:bb348c97df44 12906 /******************** Bit definition for USB_OTG_GRSTCTL register ********************/
lypinator 0:bb348c97df44 12907 #define USB_OTG_GRSTCTL_CSRST_Pos (0U)
lypinator 0:bb348c97df44 12908 #define USB_OTG_GRSTCTL_CSRST_Msk (0x1U << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 12909 #define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */
lypinator 0:bb348c97df44 12910 #define USB_OTG_GRSTCTL_HSRST_Pos (1U)
lypinator 0:bb348c97df44 12911 #define USB_OTG_GRSTCTL_HSRST_Msk (0x1U << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 12912 #define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */
lypinator 0:bb348c97df44 12913 #define USB_OTG_GRSTCTL_FCRST_Pos (2U)
lypinator 0:bb348c97df44 12914 #define USB_OTG_GRSTCTL_FCRST_Msk (0x1U << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 12915 #define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */
lypinator 0:bb348c97df44 12916 #define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U)
lypinator 0:bb348c97df44 12917 #define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1U << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 12918 #define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk /*!< RxFIFO flush */
lypinator 0:bb348c97df44 12919 #define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U)
lypinator 0:bb348c97df44 12920 #define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1U << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 12921 #define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk /*!< TxFIFO flush */
lypinator 0:bb348c97df44 12922
lypinator 0:bb348c97df44 12923
lypinator 0:bb348c97df44 12924 #define USB_OTG_GRSTCTL_TXFNUM_Pos (6U)
lypinator 0:bb348c97df44 12925 #define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FU << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */
lypinator 0:bb348c97df44 12926 #define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk /*!< TxFIFO number */
lypinator 0:bb348c97df44 12927 #define USB_OTG_GRSTCTL_TXFNUM_0 (0x01U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 12928 #define USB_OTG_GRSTCTL_TXFNUM_1 (0x02U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 12929 #define USB_OTG_GRSTCTL_TXFNUM_2 (0x04U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 12930 #define USB_OTG_GRSTCTL_TXFNUM_3 (0x08U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 12931 #define USB_OTG_GRSTCTL_TXFNUM_4 (0x10U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 12932 #define USB_OTG_GRSTCTL_DMAREQ_Pos (30U)
lypinator 0:bb348c97df44 12933 #define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1U << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */
lypinator 0:bb348c97df44 12934 #define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk /*!< DMA request signal */
lypinator 0:bb348c97df44 12935 #define USB_OTG_GRSTCTL_AHBIDL_Pos (31U)
lypinator 0:bb348c97df44 12936 #define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1U << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */
lypinator 0:bb348c97df44 12937 #define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk /*!< AHB master idle */
lypinator 0:bb348c97df44 12938
lypinator 0:bb348c97df44 12939 /******************** Bit definition for USB_OTG_DIEPMSK register ********************/
lypinator 0:bb348c97df44 12940 #define USB_OTG_DIEPMSK_XFRCM_Pos (0U)
lypinator 0:bb348c97df44 12941 #define USB_OTG_DIEPMSK_XFRCM_Msk (0x1U << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 12942 #define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
lypinator 0:bb348c97df44 12943 #define USB_OTG_DIEPMSK_EPDM_Pos (1U)
lypinator 0:bb348c97df44 12944 #define USB_OTG_DIEPMSK_EPDM_Msk (0x1U << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 12945 #define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
lypinator 0:bb348c97df44 12946 #define USB_OTG_DIEPMSK_TOM_Pos (3U)
lypinator 0:bb348c97df44 12947 #define USB_OTG_DIEPMSK_TOM_Msk (0x1U << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 12948 #define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
lypinator 0:bb348c97df44 12949 #define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U)
lypinator 0:bb348c97df44 12950 #define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1U << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 12951 #define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
lypinator 0:bb348c97df44 12952 #define USB_OTG_DIEPMSK_INEPNMM_Pos (5U)
lypinator 0:bb348c97df44 12953 #define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1U << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 12954 #define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
lypinator 0:bb348c97df44 12955 #define USB_OTG_DIEPMSK_INEPNEM_Pos (6U)
lypinator 0:bb348c97df44 12956 #define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1U << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 12957 #define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
lypinator 0:bb348c97df44 12958 #define USB_OTG_DIEPMSK_TXFURM_Pos (8U)
lypinator 0:bb348c97df44 12959 #define USB_OTG_DIEPMSK_TXFURM_Msk (0x1U << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 12960 #define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk /*!< FIFO underrun mask */
lypinator 0:bb348c97df44 12961 #define USB_OTG_DIEPMSK_BIM_Pos (9U)
lypinator 0:bb348c97df44 12962 #define USB_OTG_DIEPMSK_BIM_Msk (0x1U << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 12963 #define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */
lypinator 0:bb348c97df44 12964
lypinator 0:bb348c97df44 12965 /******************** Bit definition for USB_OTG_HPTXSTS register ********************/
lypinator 0:bb348c97df44 12966 #define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U)
lypinator 0:bb348c97df44 12967 #define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFU << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */
lypinator 0:bb348c97df44 12968 #define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk /*!< Periodic transmit data FIFO space available */
lypinator 0:bb348c97df44 12969 #define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U)
lypinator 0:bb348c97df44 12970 #define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFU << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */
lypinator 0:bb348c97df44 12971 #define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk /*!< Periodic transmit request queue space available */
lypinator 0:bb348c97df44 12972 #define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 12973 #define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 12974 #define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 12975 #define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 12976 #define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 12977 #define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 12978 #define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 12979 #define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */
lypinator 0:bb348c97df44 12980
lypinator 0:bb348c97df44 12981 #define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U)
lypinator 0:bb348c97df44 12982 #define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFU << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */
lypinator 0:bb348c97df44 12983 #define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk /*!< Top of the periodic transmit request queue */
lypinator 0:bb348c97df44 12984 #define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 12985 #define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 12986 #define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */
lypinator 0:bb348c97df44 12987 #define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */
lypinator 0:bb348c97df44 12988 #define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */
lypinator 0:bb348c97df44 12989 #define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */
lypinator 0:bb348c97df44 12990 #define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */
lypinator 0:bb348c97df44 12991 #define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */
lypinator 0:bb348c97df44 12992
lypinator 0:bb348c97df44 12993 /******************** Bit definition for USB_OTG_HAINT register ********************/
lypinator 0:bb348c97df44 12994 #define USB_OTG_HAINT_HAINT_Pos (0U)
lypinator 0:bb348c97df44 12995 #define USB_OTG_HAINT_HAINT_Msk (0xFFFFU << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */
lypinator 0:bb348c97df44 12996 #define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk /*!< Channel interrupts */
lypinator 0:bb348c97df44 12997
lypinator 0:bb348c97df44 12998 /******************** Bit definition for USB_OTG_DOEPMSK register ********************/
lypinator 0:bb348c97df44 12999 #define USB_OTG_DOEPMSK_XFRCM_Pos (0U)
lypinator 0:bb348c97df44 13000 #define USB_OTG_DOEPMSK_XFRCM_Msk (0x1U << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 13001 #define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
lypinator 0:bb348c97df44 13002 #define USB_OTG_DOEPMSK_EPDM_Pos (1U)
lypinator 0:bb348c97df44 13003 #define USB_OTG_DOEPMSK_EPDM_Msk (0x1U << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 13004 #define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
lypinator 0:bb348c97df44 13005 #define USB_OTG_DOEPMSK_STUPM_Pos (3U)
lypinator 0:bb348c97df44 13006 #define USB_OTG_DOEPMSK_STUPM_Msk (0x1U << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 13007 #define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */
lypinator 0:bb348c97df44 13008 #define USB_OTG_DOEPMSK_OTEPDM_Pos (4U)
lypinator 0:bb348c97df44 13009 #define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1U << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 13010 #define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */
lypinator 0:bb348c97df44 13011 #define USB_OTG_DOEPMSK_OTEPSPRM_Pos (5U)
lypinator 0:bb348c97df44 13012 #define USB_OTG_DOEPMSK_OTEPSPRM_Msk (0x1U << USB_OTG_DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 13013 #define USB_OTG_DOEPMSK_OTEPSPRM USB_OTG_DOEPMSK_OTEPSPRM_Msk /*!< Status Phase Received mask */
lypinator 0:bb348c97df44 13014 #define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U)
lypinator 0:bb348c97df44 13015 #define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1U << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 13016 #define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */
lypinator 0:bb348c97df44 13017 #define USB_OTG_DOEPMSK_OPEM_Pos (8U)
lypinator 0:bb348c97df44 13018 #define USB_OTG_DOEPMSK_OPEM_Msk (0x1U << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 13019 #define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */
lypinator 0:bb348c97df44 13020 #define USB_OTG_DOEPMSK_BOIM_Pos (9U)
lypinator 0:bb348c97df44 13021 #define USB_OTG_DOEPMSK_BOIM_Msk (0x1U << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 13022 #define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */
lypinator 0:bb348c97df44 13023
lypinator 0:bb348c97df44 13024 /******************** Bit definition for USB_OTG_GINTSTS register ********************/
lypinator 0:bb348c97df44 13025 #define USB_OTG_GINTSTS_CMOD_Pos (0U)
lypinator 0:bb348c97df44 13026 #define USB_OTG_GINTSTS_CMOD_Msk (0x1U << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 13027 #define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk /*!< Current mode of operation */
lypinator 0:bb348c97df44 13028 #define USB_OTG_GINTSTS_MMIS_Pos (1U)
lypinator 0:bb348c97df44 13029 #define USB_OTG_GINTSTS_MMIS_Msk (0x1U << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 13030 #define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk /*!< Mode mismatch interrupt */
lypinator 0:bb348c97df44 13031 #define USB_OTG_GINTSTS_OTGINT_Pos (2U)
lypinator 0:bb348c97df44 13032 #define USB_OTG_GINTSTS_OTGINT_Msk (0x1U << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 13033 #define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk /*!< OTG interrupt */
lypinator 0:bb348c97df44 13034 #define USB_OTG_GINTSTS_SOF_Pos (3U)
lypinator 0:bb348c97df44 13035 #define USB_OTG_GINTSTS_SOF_Msk (0x1U << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 13036 #define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk /*!< Start of frame */
lypinator 0:bb348c97df44 13037 #define USB_OTG_GINTSTS_RXFLVL_Pos (4U)
lypinator 0:bb348c97df44 13038 #define USB_OTG_GINTSTS_RXFLVL_Msk (0x1U << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 13039 #define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk /*!< RxFIFO nonempty */
lypinator 0:bb348c97df44 13040 #define USB_OTG_GINTSTS_NPTXFE_Pos (5U)
lypinator 0:bb348c97df44 13041 #define USB_OTG_GINTSTS_NPTXFE_Msk (0x1U << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 13042 #define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk /*!< Nonperiodic TxFIFO empty */
lypinator 0:bb348c97df44 13043 #define USB_OTG_GINTSTS_GINAKEFF_Pos (6U)
lypinator 0:bb348c97df44 13044 #define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 13045 #define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */
lypinator 0:bb348c97df44 13046 #define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U)
lypinator 0:bb348c97df44 13047 #define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1U << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 13048 #define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */
lypinator 0:bb348c97df44 13049 #define USB_OTG_GINTSTS_ESUSP_Pos (10U)
lypinator 0:bb348c97df44 13050 #define USB_OTG_GINTSTS_ESUSP_Msk (0x1U << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 13051 #define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */
lypinator 0:bb348c97df44 13052 #define USB_OTG_GINTSTS_USBSUSP_Pos (11U)
lypinator 0:bb348c97df44 13053 #define USB_OTG_GINTSTS_USBSUSP_Msk (0x1U << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 13054 #define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk /*!< USB suspend */
lypinator 0:bb348c97df44 13055 #define USB_OTG_GINTSTS_USBRST_Pos (12U)
lypinator 0:bb348c97df44 13056 #define USB_OTG_GINTSTS_USBRST_Msk (0x1U << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 13057 #define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk /*!< USB reset */
lypinator 0:bb348c97df44 13058 #define USB_OTG_GINTSTS_ENUMDNE_Pos (13U)
lypinator 0:bb348c97df44 13059 #define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1U << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 13060 #define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk /*!< Enumeration done */
lypinator 0:bb348c97df44 13061 #define USB_OTG_GINTSTS_ISOODRP_Pos (14U)
lypinator 0:bb348c97df44 13062 #define USB_OTG_GINTSTS_ISOODRP_Msk (0x1U << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 13063 #define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk /*!< Isochronous OUT packet dropped interrupt */
lypinator 0:bb348c97df44 13064 #define USB_OTG_GINTSTS_EOPF_Pos (15U)
lypinator 0:bb348c97df44 13065 #define USB_OTG_GINTSTS_EOPF_Msk (0x1U << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 13066 #define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk /*!< End of periodic frame interrupt */
lypinator 0:bb348c97df44 13067 #define USB_OTG_GINTSTS_IEPINT_Pos (18U)
lypinator 0:bb348c97df44 13068 #define USB_OTG_GINTSTS_IEPINT_Msk (0x1U << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 13069 #define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk /*!< IN endpoint interrupt */
lypinator 0:bb348c97df44 13070 #define USB_OTG_GINTSTS_OEPINT_Pos (19U)
lypinator 0:bb348c97df44 13071 #define USB_OTG_GINTSTS_OEPINT_Msk (0x1U << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 13072 #define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk /*!< OUT endpoint interrupt */
lypinator 0:bb348c97df44 13073 #define USB_OTG_GINTSTS_IISOIXFR_Pos (20U)
lypinator 0:bb348c97df44 13074 #define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1U << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 13075 #define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk /*!< Incomplete isochronous IN transfer */
lypinator 0:bb348c97df44 13076 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U)
lypinator 0:bb348c97df44 13077 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1U << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 13078 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer */
lypinator 0:bb348c97df44 13079 #define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U)
lypinator 0:bb348c97df44 13080 #define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1U << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 13081 #define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */
lypinator 0:bb348c97df44 13082 #define USB_OTG_GINTSTS_RSTDET_Pos (23U)
lypinator 0:bb348c97df44 13083 #define USB_OTG_GINTSTS_RSTDET_Msk (0x1U << USB_OTG_GINTSTS_RSTDET_Pos) /*!< 0x00800000 */
lypinator 0:bb348c97df44 13084 #define USB_OTG_GINTSTS_RSTDET USB_OTG_GINTSTS_RSTDET_Msk /*!< Reset detected interrupt */
lypinator 0:bb348c97df44 13085 #define USB_OTG_GINTSTS_HPRTINT_Pos (24U)
lypinator 0:bb348c97df44 13086 #define USB_OTG_GINTSTS_HPRTINT_Msk (0x1U << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 13087 #define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */
lypinator 0:bb348c97df44 13088 #define USB_OTG_GINTSTS_HCINT_Pos (25U)
lypinator 0:bb348c97df44 13089 #define USB_OTG_GINTSTS_HCINT_Msk (0x1U << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 13090 #define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk /*!< Host channels interrupt */
lypinator 0:bb348c97df44 13091 #define USB_OTG_GINTSTS_PTXFE_Pos (26U)
lypinator 0:bb348c97df44 13092 #define USB_OTG_GINTSTS_PTXFE_Msk (0x1U << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */
lypinator 0:bb348c97df44 13093 #define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk /*!< Periodic TxFIFO empty */
lypinator 0:bb348c97df44 13094 #define USB_OTG_GINTSTS_LPMINT_Pos (27U)
lypinator 0:bb348c97df44 13095 #define USB_OTG_GINTSTS_LPMINT_Msk (0x1U << USB_OTG_GINTSTS_LPMINT_Pos) /*!< 0x08000000 */
lypinator 0:bb348c97df44 13096 #define USB_OTG_GINTSTS_LPMINT USB_OTG_GINTSTS_LPMINT_Msk /*!< LPM interrupt */
lypinator 0:bb348c97df44 13097 #define USB_OTG_GINTSTS_CIDSCHG_Pos (28U)
lypinator 0:bb348c97df44 13098 #define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1U << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */
lypinator 0:bb348c97df44 13099 #define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk /*!< Connector ID status change */
lypinator 0:bb348c97df44 13100 #define USB_OTG_GINTSTS_DISCINT_Pos (29U)
lypinator 0:bb348c97df44 13101 #define USB_OTG_GINTSTS_DISCINT_Msk (0x1U << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */
lypinator 0:bb348c97df44 13102 #define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk /*!< Disconnect detected interrupt */
lypinator 0:bb348c97df44 13103 #define USB_OTG_GINTSTS_SRQINT_Pos (30U)
lypinator 0:bb348c97df44 13104 #define USB_OTG_GINTSTS_SRQINT_Msk (0x1U << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */
lypinator 0:bb348c97df44 13105 #define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */
lypinator 0:bb348c97df44 13106 #define USB_OTG_GINTSTS_WKUINT_Pos (31U)
lypinator 0:bb348c97df44 13107 #define USB_OTG_GINTSTS_WKUINT_Msk (0x1U << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */
lypinator 0:bb348c97df44 13108 #define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */
lypinator 0:bb348c97df44 13109
lypinator 0:bb348c97df44 13110 /******************** Bit definition for USB_OTG_GINTMSK register ********************/
lypinator 0:bb348c97df44 13111 #define USB_OTG_GINTMSK_MMISM_Pos (1U)
lypinator 0:bb348c97df44 13112 #define USB_OTG_GINTMSK_MMISM_Msk (0x1U << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 13113 #define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk /*!< Mode mismatch interrupt mask */
lypinator 0:bb348c97df44 13114 #define USB_OTG_GINTMSK_OTGINT_Pos (2U)
lypinator 0:bb348c97df44 13115 #define USB_OTG_GINTMSK_OTGINT_Msk (0x1U << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 13116 #define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk /*!< OTG interrupt mask */
lypinator 0:bb348c97df44 13117 #define USB_OTG_GINTMSK_SOFM_Pos (3U)
lypinator 0:bb348c97df44 13118 #define USB_OTG_GINTMSK_SOFM_Msk (0x1U << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 13119 #define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk /*!< Start of frame mask */
lypinator 0:bb348c97df44 13120 #define USB_OTG_GINTMSK_RXFLVLM_Pos (4U)
lypinator 0:bb348c97df44 13121 #define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1U << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 13122 #define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk /*!< Receive FIFO nonempty mask */
lypinator 0:bb348c97df44 13123 #define USB_OTG_GINTMSK_NPTXFEM_Pos (5U)
lypinator 0:bb348c97df44 13124 #define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1U << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 13125 #define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk /*!< Nonperiodic TxFIFO empty mask */
lypinator 0:bb348c97df44 13126 #define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U)
lypinator 0:bb348c97df44 13127 #define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 13128 #define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask */
lypinator 0:bb348c97df44 13129 #define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U)
lypinator 0:bb348c97df44 13130 #define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 13131 #define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask */
lypinator 0:bb348c97df44 13132 #define USB_OTG_GINTMSK_ESUSPM_Pos (10U)
lypinator 0:bb348c97df44 13133 #define USB_OTG_GINTMSK_ESUSPM_Msk (0x1U << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 13134 #define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk /*!< Early suspend mask */
lypinator 0:bb348c97df44 13135 #define USB_OTG_GINTMSK_USBSUSPM_Pos (11U)
lypinator 0:bb348c97df44 13136 #define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1U << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 13137 #define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk /*!< USB suspend mask */
lypinator 0:bb348c97df44 13138 #define USB_OTG_GINTMSK_USBRST_Pos (12U)
lypinator 0:bb348c97df44 13139 #define USB_OTG_GINTMSK_USBRST_Msk (0x1U << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 13140 #define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk /*!< USB reset mask */
lypinator 0:bb348c97df44 13141 #define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U)
lypinator 0:bb348c97df44 13142 #define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1U << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 13143 #define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk /*!< Enumeration done mask */
lypinator 0:bb348c97df44 13144 #define USB_OTG_GINTMSK_ISOODRPM_Pos (14U)
lypinator 0:bb348c97df44 13145 #define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1U << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 13146 #define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk /*!< Isochronous OUT packet dropped interrupt mask */
lypinator 0:bb348c97df44 13147 #define USB_OTG_GINTMSK_EOPFM_Pos (15U)
lypinator 0:bb348c97df44 13148 #define USB_OTG_GINTMSK_EOPFM_Msk (0x1U << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 13149 #define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk /*!< End of periodic frame interrupt mask */
lypinator 0:bb348c97df44 13150 #define USB_OTG_GINTMSK_EPMISM_Pos (17U)
lypinator 0:bb348c97df44 13151 #define USB_OTG_GINTMSK_EPMISM_Msk (0x1U << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 13152 #define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk /*!< Endpoint mismatch interrupt mask */
lypinator 0:bb348c97df44 13153 #define USB_OTG_GINTMSK_IEPINT_Pos (18U)
lypinator 0:bb348c97df44 13154 #define USB_OTG_GINTMSK_IEPINT_Msk (0x1U << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 13155 #define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk /*!< IN endpoints interrupt mask */
lypinator 0:bb348c97df44 13156 #define USB_OTG_GINTMSK_OEPINT_Pos (19U)
lypinator 0:bb348c97df44 13157 #define USB_OTG_GINTMSK_OEPINT_Msk (0x1U << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 13158 #define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk /*!< OUT endpoints interrupt mask */
lypinator 0:bb348c97df44 13159 #define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U)
lypinator 0:bb348c97df44 13160 #define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1U << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 13161 #define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */
lypinator 0:bb348c97df44 13162 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U)
lypinator 0:bb348c97df44 13163 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 13164 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */
lypinator 0:bb348c97df44 13165 #define USB_OTG_GINTMSK_FSUSPM_Pos (22U)
lypinator 0:bb348c97df44 13166 #define USB_OTG_GINTMSK_FSUSPM_Msk (0x1U << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 13167 #define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */
lypinator 0:bb348c97df44 13168 #define USB_OTG_GINTMSK_RSTDETM_Pos (23U)
lypinator 0:bb348c97df44 13169 #define USB_OTG_GINTMSK_RSTDETM_Msk (0x1U << USB_OTG_GINTMSK_RSTDETM_Pos) /*!< 0x00800000 */
lypinator 0:bb348c97df44 13170 #define USB_OTG_GINTMSK_RSTDETM USB_OTG_GINTMSK_RSTDETM_Msk /*!< Reset detected interrupt mask */
lypinator 0:bb348c97df44 13171 #define USB_OTG_GINTMSK_PRTIM_Pos (24U)
lypinator 0:bb348c97df44 13172 #define USB_OTG_GINTMSK_PRTIM_Msk (0x1U << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 13173 #define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */
lypinator 0:bb348c97df44 13174 #define USB_OTG_GINTMSK_HCIM_Pos (25U)
lypinator 0:bb348c97df44 13175 #define USB_OTG_GINTMSK_HCIM_Msk (0x1U << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 13176 #define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk /*!< Host channels interrupt mask */
lypinator 0:bb348c97df44 13177 #define USB_OTG_GINTMSK_PTXFEM_Pos (26U)
lypinator 0:bb348c97df44 13178 #define USB_OTG_GINTMSK_PTXFEM_Msk (0x1U << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */
lypinator 0:bb348c97df44 13179 #define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk /*!< Periodic TxFIFO empty mask */
lypinator 0:bb348c97df44 13180 #define USB_OTG_GINTMSK_LPMINTM_Pos (27U)
lypinator 0:bb348c97df44 13181 #define USB_OTG_GINTMSK_LPMINTM_Msk (0x1U << USB_OTG_GINTMSK_LPMINTM_Pos) /*!< 0x08000000 */
lypinator 0:bb348c97df44 13182 #define USB_OTG_GINTMSK_LPMINTM USB_OTG_GINTMSK_LPMINTM_Msk /*!< LPM interrupt Mask */
lypinator 0:bb348c97df44 13183 #define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U)
lypinator 0:bb348c97df44 13184 #define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1U << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */
lypinator 0:bb348c97df44 13185 #define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk /*!< Connector ID status change mask */
lypinator 0:bb348c97df44 13186 #define USB_OTG_GINTMSK_DISCINT_Pos (29U)
lypinator 0:bb348c97df44 13187 #define USB_OTG_GINTMSK_DISCINT_Msk (0x1U << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */
lypinator 0:bb348c97df44 13188 #define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk /*!< Disconnect detected interrupt mask */
lypinator 0:bb348c97df44 13189 #define USB_OTG_GINTMSK_SRQIM_Pos (30U)
lypinator 0:bb348c97df44 13190 #define USB_OTG_GINTMSK_SRQIM_Msk (0x1U << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */
lypinator 0:bb348c97df44 13191 #define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk /*!< Session request/new session detected interrupt mask */
lypinator 0:bb348c97df44 13192 #define USB_OTG_GINTMSK_WUIM_Pos (31U)
lypinator 0:bb348c97df44 13193 #define USB_OTG_GINTMSK_WUIM_Msk (0x1U << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */
lypinator 0:bb348c97df44 13194 #define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk /*!< Resume/remote wakeup detected interrupt mask */
lypinator 0:bb348c97df44 13195
lypinator 0:bb348c97df44 13196 /******************** Bit definition for USB_OTG_DAINT register ********************/
lypinator 0:bb348c97df44 13197 #define USB_OTG_DAINT_IEPINT_Pos (0U)
lypinator 0:bb348c97df44 13198 #define USB_OTG_DAINT_IEPINT_Msk (0xFFFFU << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */
lypinator 0:bb348c97df44 13199 #define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk /*!< IN endpoint interrupt bits */
lypinator 0:bb348c97df44 13200 #define USB_OTG_DAINT_OEPINT_Pos (16U)
lypinator 0:bb348c97df44 13201 #define USB_OTG_DAINT_OEPINT_Msk (0xFFFFU << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */
lypinator 0:bb348c97df44 13202 #define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk /*!< OUT endpoint interrupt bits */
lypinator 0:bb348c97df44 13203
lypinator 0:bb348c97df44 13204 /******************** Bit definition for USB_OTG_HAINTMSK register ********************/
lypinator 0:bb348c97df44 13205 #define USB_OTG_HAINTMSK_HAINTM_Pos (0U)
lypinator 0:bb348c97df44 13206 #define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFU << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */
lypinator 0:bb348c97df44 13207 #define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */
lypinator 0:bb348c97df44 13208
lypinator 0:bb348c97df44 13209 /******************** Bit definition for USB_OTG_GRXSTSP register ********************/
lypinator 0:bb348c97df44 13210 #define USB_OTG_GRXSTSP_EPNUM_Pos (0U)
lypinator 0:bb348c97df44 13211 #define USB_OTG_GRXSTSP_EPNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */
lypinator 0:bb348c97df44 13212 #define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */
lypinator 0:bb348c97df44 13213 #define USB_OTG_GRXSTSP_BCNT_Pos (4U)
lypinator 0:bb348c97df44 13214 #define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */
lypinator 0:bb348c97df44 13215 #define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */
lypinator 0:bb348c97df44 13216 #define USB_OTG_GRXSTSP_DPID_Pos (15U)
lypinator 0:bb348c97df44 13217 #define USB_OTG_GRXSTSP_DPID_Msk (0x3U << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */
lypinator 0:bb348c97df44 13218 #define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */
lypinator 0:bb348c97df44 13219 #define USB_OTG_GRXSTSP_PKTSTS_Pos (17U)
lypinator 0:bb348c97df44 13220 #define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */
lypinator 0:bb348c97df44 13221 #define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */
lypinator 0:bb348c97df44 13222
lypinator 0:bb348c97df44 13223 /******************** Bit definition for USB_OTG_DAINTMSK register ********************/
lypinator 0:bb348c97df44 13224 #define USB_OTG_DAINTMSK_IEPM_Pos (0U)
lypinator 0:bb348c97df44 13225 #define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */
lypinator 0:bb348c97df44 13226 #define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk /*!< IN EP interrupt mask bits */
lypinator 0:bb348c97df44 13227 #define USB_OTG_DAINTMSK_OEPM_Pos (16U)
lypinator 0:bb348c97df44 13228 #define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */
lypinator 0:bb348c97df44 13229 #define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk /*!< OUT EP interrupt mask bits */
lypinator 0:bb348c97df44 13230
lypinator 0:bb348c97df44 13231 /******************** Bit definition for USB_OTG_GRXFSIZ register ********************/
lypinator 0:bb348c97df44 13232 #define USB_OTG_GRXFSIZ_RXFD_Pos (0U)
lypinator 0:bb348c97df44 13233 #define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFU << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
lypinator 0:bb348c97df44 13234 #define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk /*!< RxFIFO depth */
lypinator 0:bb348c97df44 13235
lypinator 0:bb348c97df44 13236 /******************** Bit definition for USB_OTG_DVBUSDIS register ********************/
lypinator 0:bb348c97df44 13237 #define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U)
lypinator 0:bb348c97df44 13238 #define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFU << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */
lypinator 0:bb348c97df44 13239 #define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk /*!< Device VBUS discharge time */
lypinator 0:bb348c97df44 13240
lypinator 0:bb348c97df44 13241 /******************** Bit definition for OTG register ********************/
lypinator 0:bb348c97df44 13242 #define USB_OTG_NPTXFSA_Pos (0U)
lypinator 0:bb348c97df44 13243 #define USB_OTG_NPTXFSA_Msk (0xFFFFU << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */
lypinator 0:bb348c97df44 13244 #define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk /*!< Nonperiodic transmit RAM start address */
lypinator 0:bb348c97df44 13245 #define USB_OTG_NPTXFD_Pos (16U)
lypinator 0:bb348c97df44 13246 #define USB_OTG_NPTXFD_Msk (0xFFFFU << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */
lypinator 0:bb348c97df44 13247 #define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk /*!< Nonperiodic TxFIFO depth */
lypinator 0:bb348c97df44 13248 #define USB_OTG_TX0FSA_Pos (0U)
lypinator 0:bb348c97df44 13249 #define USB_OTG_TX0FSA_Msk (0xFFFFU << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */
lypinator 0:bb348c97df44 13250 #define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk /*!< Endpoint 0 transmit RAM start address */
lypinator 0:bb348c97df44 13251 #define USB_OTG_TX0FD_Pos (16U)
lypinator 0:bb348c97df44 13252 #define USB_OTG_TX0FD_Msk (0xFFFFU << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */
lypinator 0:bb348c97df44 13253 #define USB_OTG_TX0FD USB_OTG_TX0FD_Msk /*!< Endpoint 0 TxFIFO depth */
lypinator 0:bb348c97df44 13254
lypinator 0:bb348c97df44 13255 /******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
lypinator 0:bb348c97df44 13256 #define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U)
lypinator 0:bb348c97df44 13257 #define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFU << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */
lypinator 0:bb348c97df44 13258 #define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */
lypinator 0:bb348c97df44 13259
lypinator 0:bb348c97df44 13260 /******************** Bit definition for USB_OTG_GNPTXSTS register ********************/
lypinator 0:bb348c97df44 13261 #define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U)
lypinator 0:bb348c97df44 13262 #define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFU << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */
lypinator 0:bb348c97df44 13263 #define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */
lypinator 0:bb348c97df44 13264
lypinator 0:bb348c97df44 13265 #define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U)
lypinator 0:bb348c97df44 13266 #define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFU << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */
lypinator 0:bb348c97df44 13267 #define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */
lypinator 0:bb348c97df44 13268 #define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 13269 #define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 13270 #define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 13271 #define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 13272 #define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 13273 #define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 13274 #define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 13275 #define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */
lypinator 0:bb348c97df44 13276
lypinator 0:bb348c97df44 13277 #define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U)
lypinator 0:bb348c97df44 13278 #define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FU << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */
lypinator 0:bb348c97df44 13279 #define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */
lypinator 0:bb348c97df44 13280 #define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 13281 #define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 13282 #define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */
lypinator 0:bb348c97df44 13283 #define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */
lypinator 0:bb348c97df44 13284 #define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */
lypinator 0:bb348c97df44 13285 #define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */
lypinator 0:bb348c97df44 13286 #define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */
lypinator 0:bb348c97df44 13287
lypinator 0:bb348c97df44 13288 /******************** Bit definition for USB_OTG_DTHRCTL register ********************/
lypinator 0:bb348c97df44 13289 #define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U)
lypinator 0:bb348c97df44 13290 #define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1U << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 13291 #define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */
lypinator 0:bb348c97df44 13292 #define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U)
lypinator 0:bb348c97df44 13293 #define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1U << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 13294 #define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk /*!< ISO IN endpoint threshold enable */
lypinator 0:bb348c97df44 13295
lypinator 0:bb348c97df44 13296 #define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U)
lypinator 0:bb348c97df44 13297 #define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFU << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */
lypinator 0:bb348c97df44 13298 #define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk /*!< Transmit threshold length */
lypinator 0:bb348c97df44 13299 #define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 13300 #define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 13301 #define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 13302 #define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 13303 #define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 13304 #define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 13305 #define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 13306 #define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 13307 #define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 13308 #define USB_OTG_DTHRCTL_RXTHREN_Pos (16U)
lypinator 0:bb348c97df44 13309 #define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1U << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 13310 #define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk /*!< Receive threshold enable */
lypinator 0:bb348c97df44 13311
lypinator 0:bb348c97df44 13312 #define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U)
lypinator 0:bb348c97df44 13313 #define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFU << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */
lypinator 0:bb348c97df44 13314 #define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk /*!< Receive threshold length */
lypinator 0:bb348c97df44 13315 #define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 13316 #define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 13317 #define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 13318 #define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 13319 #define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 13320 #define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 13321 #define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */
lypinator 0:bb348c97df44 13322 #define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 13323 #define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 13324 #define USB_OTG_DTHRCTL_ARPEN_Pos (27U)
lypinator 0:bb348c97df44 13325 #define USB_OTG_DTHRCTL_ARPEN_Msk (0x1U << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */
lypinator 0:bb348c97df44 13326 #define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk /*!< Arbiter parking enable */
lypinator 0:bb348c97df44 13327
lypinator 0:bb348c97df44 13328 /******************** Bit definition for USB_OTG_DIEPEMPMSK register ********************/
lypinator 0:bb348c97df44 13329 #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U)
lypinator 0:bb348c97df44 13330 #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFU << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */
lypinator 0:bb348c97df44 13331 #define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */
lypinator 0:bb348c97df44 13332
lypinator 0:bb348c97df44 13333 /******************** Bit definition for USB_OTG_DEACHINT register ********************/
lypinator 0:bb348c97df44 13334 #define USB_OTG_DEACHINT_IEP1INT_Pos (1U)
lypinator 0:bb348c97df44 13335 #define USB_OTG_DEACHINT_IEP1INT_Msk (0x1U << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 13336 #define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk /*!< IN endpoint 1interrupt bit */
lypinator 0:bb348c97df44 13337 #define USB_OTG_DEACHINT_OEP1INT_Pos (17U)
lypinator 0:bb348c97df44 13338 #define USB_OTG_DEACHINT_OEP1INT_Msk (0x1U << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 13339 #define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk /*!< OUT endpoint 1 interrupt bit */
lypinator 0:bb348c97df44 13340
lypinator 0:bb348c97df44 13341 /******************** Bit definition for USB_OTG_GCCFG register ********************/
lypinator 0:bb348c97df44 13342 #define USB_OTG_GCCFG_DCDET_Pos (0U)
lypinator 0:bb348c97df44 13343 #define USB_OTG_GCCFG_DCDET_Msk (0x1U << USB_OTG_GCCFG_DCDET_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 13344 #define USB_OTG_GCCFG_DCDET USB_OTG_GCCFG_DCDET_Msk /*!< Data contact detection (DCD) status */
lypinator 0:bb348c97df44 13345 #define USB_OTG_GCCFG_PDET_Pos (1U)
lypinator 0:bb348c97df44 13346 #define USB_OTG_GCCFG_PDET_Msk (0x1U << USB_OTG_GCCFG_PDET_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 13347 #define USB_OTG_GCCFG_PDET USB_OTG_GCCFG_PDET_Msk /*!< Primary detection (PD) status */
lypinator 0:bb348c97df44 13348 #define USB_OTG_GCCFG_SDET_Pos (2U)
lypinator 0:bb348c97df44 13349 #define USB_OTG_GCCFG_SDET_Msk (0x1U << USB_OTG_GCCFG_SDET_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 13350 #define USB_OTG_GCCFG_SDET USB_OTG_GCCFG_SDET_Msk /*!< Secondary detection (SD) status */
lypinator 0:bb348c97df44 13351 #define USB_OTG_GCCFG_PS2DET_Pos (3U)
lypinator 0:bb348c97df44 13352 #define USB_OTG_GCCFG_PS2DET_Msk (0x1U << USB_OTG_GCCFG_PS2DET_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 13353 #define USB_OTG_GCCFG_PS2DET USB_OTG_GCCFG_PS2DET_Msk /*!< DM pull-up detection status */
lypinator 0:bb348c97df44 13354 #define USB_OTG_GCCFG_PWRDWN_Pos (16U)
lypinator 0:bb348c97df44 13355 #define USB_OTG_GCCFG_PWRDWN_Msk (0x1U << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 13356 #define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk /*!< Power down */
lypinator 0:bb348c97df44 13357 #define USB_OTG_GCCFG_BCDEN_Pos (17U)
lypinator 0:bb348c97df44 13358 #define USB_OTG_GCCFG_BCDEN_Msk (0x1U << USB_OTG_GCCFG_BCDEN_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 13359 #define USB_OTG_GCCFG_BCDEN USB_OTG_GCCFG_BCDEN_Msk /*!< Battery charging detector (BCD) enable */
lypinator 0:bb348c97df44 13360 #define USB_OTG_GCCFG_DCDEN_Pos (18U)
lypinator 0:bb348c97df44 13361 #define USB_OTG_GCCFG_DCDEN_Msk (0x1U << USB_OTG_GCCFG_DCDEN_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 13362 #define USB_OTG_GCCFG_DCDEN USB_OTG_GCCFG_DCDEN_Msk /*!< Data contact detection (DCD) mode enable*/
lypinator 0:bb348c97df44 13363 #define USB_OTG_GCCFG_PDEN_Pos (19U)
lypinator 0:bb348c97df44 13364 #define USB_OTG_GCCFG_PDEN_Msk (0x1U << USB_OTG_GCCFG_PDEN_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 13365 #define USB_OTG_GCCFG_PDEN USB_OTG_GCCFG_PDEN_Msk /*!< Primary detection (PD) mode enable*/
lypinator 0:bb348c97df44 13366 #define USB_OTG_GCCFG_SDEN_Pos (20U)
lypinator 0:bb348c97df44 13367 #define USB_OTG_GCCFG_SDEN_Msk (0x1U << USB_OTG_GCCFG_SDEN_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 13368 #define USB_OTG_GCCFG_SDEN USB_OTG_GCCFG_SDEN_Msk /*!< Secondary detection (SD) mode enable */
lypinator 0:bb348c97df44 13369 #define USB_OTG_GCCFG_VBDEN_Pos (21U)
lypinator 0:bb348c97df44 13370 #define USB_OTG_GCCFG_VBDEN_Msk (0x1U << USB_OTG_GCCFG_VBDEN_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 13371 #define USB_OTG_GCCFG_VBDEN USB_OTG_GCCFG_VBDEN_Msk /*!< USB VBUS Detection Enable */
lypinator 0:bb348c97df44 13372
lypinator 0:bb348c97df44 13373 /******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
lypinator 0:bb348c97df44 13374 #define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U)
lypinator 0:bb348c97df44 13375 #define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1U << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 13376 #define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit */
lypinator 0:bb348c97df44 13377 #define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U)
lypinator 0:bb348c97df44 13378 #define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1U << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 13379 #define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */
lypinator 0:bb348c97df44 13380
lypinator 0:bb348c97df44 13381 /******************** Bit definition for USB_OTG_CID register ********************/
lypinator 0:bb348c97df44 13382 #define USB_OTG_CID_PRODUCT_ID_Pos (0U)
lypinator 0:bb348c97df44 13383 #define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFU << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */
lypinator 0:bb348c97df44 13384 #define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk /*!< Product ID field */
lypinator 0:bb348c97df44 13385
lypinator 0:bb348c97df44 13386 /******************** Bit definition for USB_OTG_GLPMCFG register ********************/
lypinator 0:bb348c97df44 13387 #define USB_OTG_GLPMCFG_LPMEN_Pos (0U)
lypinator 0:bb348c97df44 13388 #define USB_OTG_GLPMCFG_LPMEN_Msk (0x1U << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 13389 #define USB_OTG_GLPMCFG_LPMEN USB_OTG_GLPMCFG_LPMEN_Msk /*!< LPM support enable */
lypinator 0:bb348c97df44 13390 #define USB_OTG_GLPMCFG_LPMACK_Pos (1U)
lypinator 0:bb348c97df44 13391 #define USB_OTG_GLPMCFG_LPMACK_Msk (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 13392 #define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /*!< LPM Token acknowledge enable */
lypinator 0:bb348c97df44 13393 #define USB_OTG_GLPMCFG_BESL_Pos (2U)
lypinator 0:bb348c97df44 13394 #define USB_OTG_GLPMCFG_BESL_Msk (0xFU << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */
lypinator 0:bb348c97df44 13395 #define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk /*!< BESL value received with last ACKed LPM Token */
lypinator 0:bb348c97df44 13396 #define USB_OTG_GLPMCFG_REMWAKE_Pos (6U)
lypinator 0:bb348c97df44 13397 #define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1U << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 13398 #define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk /*!< bRemoteWake value received with last ACKed LPM Token */
lypinator 0:bb348c97df44 13399 #define USB_OTG_GLPMCFG_L1SSEN_Pos (7U)
lypinator 0:bb348c97df44 13400 #define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 13401 #define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk /*!< L1 shallow sleep enable */
lypinator 0:bb348c97df44 13402 #define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U)
lypinator 0:bb348c97df44 13403 #define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFU << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */
lypinator 0:bb348c97df44 13404 #define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk /*!< BESL threshold */
lypinator 0:bb348c97df44 13405 #define USB_OTG_GLPMCFG_L1DSEN_Pos (12U)
lypinator 0:bb348c97df44 13406 #define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 13407 #define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk /*!< L1 deep sleep enable */
lypinator 0:bb348c97df44 13408 #define USB_OTG_GLPMCFG_LPMRSP_Pos (13U)
lypinator 0:bb348c97df44 13409 #define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3U << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */
lypinator 0:bb348c97df44 13410 #define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk /*!< LPM response */
lypinator 0:bb348c97df44 13411 #define USB_OTG_GLPMCFG_SLPSTS_Pos (15U)
lypinator 0:bb348c97df44 13412 #define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1U << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 13413 #define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk /*!< Port sleep status */
lypinator 0:bb348c97df44 13414 #define USB_OTG_GLPMCFG_L1RSMOK_Pos (16U)
lypinator 0:bb348c97df44 13415 #define USB_OTG_GLPMCFG_L1RSMOK_Msk (0x1U << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 13416 #define USB_OTG_GLPMCFG_L1RSMOK USB_OTG_GLPMCFG_L1RSMOK_Msk /*!< Sleep State Resume OK */
lypinator 0:bb348c97df44 13417 #define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U)
lypinator 0:bb348c97df44 13418 #define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFU << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */
lypinator 0:bb348c97df44 13419 #define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk /*!< LPM Channel Index */
lypinator 0:bb348c97df44 13420 #define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U)
lypinator 0:bb348c97df44 13421 #define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */
lypinator 0:bb348c97df44 13422 #define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk /*!< LPM retry count */
lypinator 0:bb348c97df44 13423 #define USB_OTG_GLPMCFG_SNDLPM_Pos (24U)
lypinator 0:bb348c97df44 13424 #define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1U << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 13425 #define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk /*!< Send LPM transaction */
lypinator 0:bb348c97df44 13426 #define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U)
lypinator 0:bb348c97df44 13427 #define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */
lypinator 0:bb348c97df44 13428 #define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /*!< LPM retry count status */
lypinator 0:bb348c97df44 13429 #define USB_OTG_GLPMCFG_ENBESL_Pos (28U)
lypinator 0:bb348c97df44 13430 #define USB_OTG_GLPMCFG_ENBESL_Msk (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */
lypinator 0:bb348c97df44 13431 #define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /*!< Enable best effort service latency */
lypinator 0:bb348c97df44 13432
lypinator 0:bb348c97df44 13433 /******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/
lypinator 0:bb348c97df44 13434 #define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U)
lypinator 0:bb348c97df44 13435 #define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 13436 #define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
lypinator 0:bb348c97df44 13437 #define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U)
lypinator 0:bb348c97df44 13438 #define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 13439 #define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
lypinator 0:bb348c97df44 13440 #define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U)
lypinator 0:bb348c97df44 13441 #define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 13442 #define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
lypinator 0:bb348c97df44 13443 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U)
lypinator 0:bb348c97df44 13444 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1U << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 13445 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
lypinator 0:bb348c97df44 13446 #define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U)
lypinator 0:bb348c97df44 13447 #define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 13448 #define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
lypinator 0:bb348c97df44 13449 #define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U)
lypinator 0:bb348c97df44 13450 #define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 13451 #define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
lypinator 0:bb348c97df44 13452 #define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U)
lypinator 0:bb348c97df44 13453 #define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 13454 #define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */
lypinator 0:bb348c97df44 13455 #define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U)
lypinator 0:bb348c97df44 13456 #define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 13457 #define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
lypinator 0:bb348c97df44 13458 #define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U)
lypinator 0:bb348c97df44 13459 #define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 13460 #define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
lypinator 0:bb348c97df44 13461
lypinator 0:bb348c97df44 13462 /******************** Bit definition for USB_OTG_HPRT register ********************/
lypinator 0:bb348c97df44 13463 #define USB_OTG_HPRT_PCSTS_Pos (0U)
lypinator 0:bb348c97df44 13464 #define USB_OTG_HPRT_PCSTS_Msk (0x1U << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 13465 #define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk /*!< Port connect status */
lypinator 0:bb348c97df44 13466 #define USB_OTG_HPRT_PCDET_Pos (1U)
lypinator 0:bb348c97df44 13467 #define USB_OTG_HPRT_PCDET_Msk (0x1U << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 13468 #define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk /*!< Port connect detected */
lypinator 0:bb348c97df44 13469 #define USB_OTG_HPRT_PENA_Pos (2U)
lypinator 0:bb348c97df44 13470 #define USB_OTG_HPRT_PENA_Msk (0x1U << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 13471 #define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk /*!< Port enable */
lypinator 0:bb348c97df44 13472 #define USB_OTG_HPRT_PENCHNG_Pos (3U)
lypinator 0:bb348c97df44 13473 #define USB_OTG_HPRT_PENCHNG_Msk (0x1U << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 13474 #define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk /*!< Port enable/disable change */
lypinator 0:bb348c97df44 13475 #define USB_OTG_HPRT_POCA_Pos (4U)
lypinator 0:bb348c97df44 13476 #define USB_OTG_HPRT_POCA_Msk (0x1U << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 13477 #define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk /*!< Port overcurrent active */
lypinator 0:bb348c97df44 13478 #define USB_OTG_HPRT_POCCHNG_Pos (5U)
lypinator 0:bb348c97df44 13479 #define USB_OTG_HPRT_POCCHNG_Msk (0x1U << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 13480 #define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk /*!< Port overcurrent change */
lypinator 0:bb348c97df44 13481 #define USB_OTG_HPRT_PRES_Pos (6U)
lypinator 0:bb348c97df44 13482 #define USB_OTG_HPRT_PRES_Msk (0x1U << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 13483 #define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk /*!< Port resume */
lypinator 0:bb348c97df44 13484 #define USB_OTG_HPRT_PSUSP_Pos (7U)
lypinator 0:bb348c97df44 13485 #define USB_OTG_HPRT_PSUSP_Msk (0x1U << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 13486 #define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk /*!< Port suspend */
lypinator 0:bb348c97df44 13487 #define USB_OTG_HPRT_PRST_Pos (8U)
lypinator 0:bb348c97df44 13488 #define USB_OTG_HPRT_PRST_Msk (0x1U << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 13489 #define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */
lypinator 0:bb348c97df44 13490
lypinator 0:bb348c97df44 13491 #define USB_OTG_HPRT_PLSTS_Pos (10U)
lypinator 0:bb348c97df44 13492 #define USB_OTG_HPRT_PLSTS_Msk (0x3U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */
lypinator 0:bb348c97df44 13493 #define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */
lypinator 0:bb348c97df44 13494 #define USB_OTG_HPRT_PLSTS_0 (0x1U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 13495 #define USB_OTG_HPRT_PLSTS_1 (0x2U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 13496 #define USB_OTG_HPRT_PPWR_Pos (12U)
lypinator 0:bb348c97df44 13497 #define USB_OTG_HPRT_PPWR_Msk (0x1U << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 13498 #define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */
lypinator 0:bb348c97df44 13499
lypinator 0:bb348c97df44 13500 #define USB_OTG_HPRT_PTCTL_Pos (13U)
lypinator 0:bb348c97df44 13501 #define USB_OTG_HPRT_PTCTL_Msk (0xFU << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */
lypinator 0:bb348c97df44 13502 #define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */
lypinator 0:bb348c97df44 13503 #define USB_OTG_HPRT_PTCTL_0 (0x1U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 13504 #define USB_OTG_HPRT_PTCTL_1 (0x2U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 13505 #define USB_OTG_HPRT_PTCTL_2 (0x4U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 13506 #define USB_OTG_HPRT_PTCTL_3 (0x8U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 13507
lypinator 0:bb348c97df44 13508 #define USB_OTG_HPRT_PSPD_Pos (17U)
lypinator 0:bb348c97df44 13509 #define USB_OTG_HPRT_PSPD_Msk (0x3U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */
lypinator 0:bb348c97df44 13510 #define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */
lypinator 0:bb348c97df44 13511 #define USB_OTG_HPRT_PSPD_0 (0x1U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 13512 #define USB_OTG_HPRT_PSPD_1 (0x2U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 13513
lypinator 0:bb348c97df44 13514 /******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/
lypinator 0:bb348c97df44 13515 #define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U)
lypinator 0:bb348c97df44 13516 #define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 13517 #define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
lypinator 0:bb348c97df44 13518 #define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U)
lypinator 0:bb348c97df44 13519 #define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 13520 #define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
lypinator 0:bb348c97df44 13521 #define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U)
lypinator 0:bb348c97df44 13522 #define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 13523 #define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk /*!< Timeout condition mask */
lypinator 0:bb348c97df44 13524 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U)
lypinator 0:bb348c97df44 13525 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1U << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 13526 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
lypinator 0:bb348c97df44 13527 #define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U)
lypinator 0:bb348c97df44 13528 #define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 13529 #define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
lypinator 0:bb348c97df44 13530 #define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U)
lypinator 0:bb348c97df44 13531 #define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 13532 #define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
lypinator 0:bb348c97df44 13533 #define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U)
lypinator 0:bb348c97df44 13534 #define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 13535 #define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */
lypinator 0:bb348c97df44 13536 #define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U)
lypinator 0:bb348c97df44 13537 #define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 13538 #define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
lypinator 0:bb348c97df44 13539 #define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U)
lypinator 0:bb348c97df44 13540 #define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 13541 #define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */
lypinator 0:bb348c97df44 13542 #define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U)
lypinator 0:bb348c97df44 13543 #define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 13544 #define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
lypinator 0:bb348c97df44 13545 #define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U)
lypinator 0:bb348c97df44 13546 #define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 13547 #define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */
lypinator 0:bb348c97df44 13548
lypinator 0:bb348c97df44 13549 /******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/
lypinator 0:bb348c97df44 13550 #define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U)
lypinator 0:bb348c97df44 13551 #define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */
lypinator 0:bb348c97df44 13552 #define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */
lypinator 0:bb348c97df44 13553 #define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U)
lypinator 0:bb348c97df44 13554 #define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */
lypinator 0:bb348c97df44 13555 #define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */
lypinator 0:bb348c97df44 13556
lypinator 0:bb348c97df44 13557 /******************** Bit definition for USB_OTG_DIEPCTL register ********************/
lypinator 0:bb348c97df44 13558 #define USB_OTG_DIEPCTL_MPSIZ_Pos (0U)
lypinator 0:bb348c97df44 13559 #define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFU << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
lypinator 0:bb348c97df44 13560 #define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk /*!< Maximum packet size */
lypinator 0:bb348c97df44 13561 #define USB_OTG_DIEPCTL_USBAEP_Pos (15U)
lypinator 0:bb348c97df44 13562 #define USB_OTG_DIEPCTL_USBAEP_Msk (0x1U << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 13563 #define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk /*!< USB active endpoint */
lypinator 0:bb348c97df44 13564 #define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U)
lypinator 0:bb348c97df44 13565 #define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1U << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 13566 #define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */
lypinator 0:bb348c97df44 13567 #define USB_OTG_DIEPCTL_NAKSTS_Pos (17U)
lypinator 0:bb348c97df44 13568 #define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 13569 #define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk /*!< NAK status */
lypinator 0:bb348c97df44 13570
lypinator 0:bb348c97df44 13571 #define USB_OTG_DIEPCTL_EPTYP_Pos (18U)
lypinator 0:bb348c97df44 13572 #define USB_OTG_DIEPCTL_EPTYP_Msk (0x3U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
lypinator 0:bb348c97df44 13573 #define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk /*!< Endpoint type */
lypinator 0:bb348c97df44 13574 #define USB_OTG_DIEPCTL_EPTYP_0 (0x1U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 13575 #define USB_OTG_DIEPCTL_EPTYP_1 (0x2U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 13576 #define USB_OTG_DIEPCTL_STALL_Pos (21U)
lypinator 0:bb348c97df44 13577 #define USB_OTG_DIEPCTL_STALL_Msk (0x1U << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 13578 #define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk /*!< STALL handshake */
lypinator 0:bb348c97df44 13579
lypinator 0:bb348c97df44 13580 #define USB_OTG_DIEPCTL_TXFNUM_Pos (22U)
lypinator 0:bb348c97df44 13581 #define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFU << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */
lypinator 0:bb348c97df44 13582 #define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk /*!< TxFIFO number */
lypinator 0:bb348c97df44 13583 #define USB_OTG_DIEPCTL_TXFNUM_0 (0x1U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 13584 #define USB_OTG_DIEPCTL_TXFNUM_1 (0x2U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */
lypinator 0:bb348c97df44 13585 #define USB_OTG_DIEPCTL_TXFNUM_2 (0x4U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 13586 #define USB_OTG_DIEPCTL_TXFNUM_3 (0x8U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 13587 #define USB_OTG_DIEPCTL_CNAK_Pos (26U)
lypinator 0:bb348c97df44 13588 #define USB_OTG_DIEPCTL_CNAK_Msk (0x1U << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */
lypinator 0:bb348c97df44 13589 #define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk /*!< Clear NAK */
lypinator 0:bb348c97df44 13590 #define USB_OTG_DIEPCTL_SNAK_Pos (27U)
lypinator 0:bb348c97df44 13591 #define USB_OTG_DIEPCTL_SNAK_Msk (0x1U << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */
lypinator 0:bb348c97df44 13592 #define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */
lypinator 0:bb348c97df44 13593 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U)
lypinator 0:bb348c97df44 13594 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
lypinator 0:bb348c97df44 13595 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
lypinator 0:bb348c97df44 13596 #define USB_OTG_DIEPCTL_SODDFRM_Pos (29U)
lypinator 0:bb348c97df44 13597 #define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
lypinator 0:bb348c97df44 13598 #define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */
lypinator 0:bb348c97df44 13599 #define USB_OTG_DIEPCTL_EPDIS_Pos (30U)
lypinator 0:bb348c97df44 13600 #define USB_OTG_DIEPCTL_EPDIS_Msk (0x1U << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */
lypinator 0:bb348c97df44 13601 #define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */
lypinator 0:bb348c97df44 13602 #define USB_OTG_DIEPCTL_EPENA_Pos (31U)
lypinator 0:bb348c97df44 13603 #define USB_OTG_DIEPCTL_EPENA_Msk (0x1U << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */
lypinator 0:bb348c97df44 13604 #define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk /*!< Endpoint enable */
lypinator 0:bb348c97df44 13605
lypinator 0:bb348c97df44 13606 /******************** Bit definition for USB_OTG_HCCHAR register ********************/
lypinator 0:bb348c97df44 13607 #define USB_OTG_HCCHAR_MPSIZ_Pos (0U)
lypinator 0:bb348c97df44 13608 #define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFU << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */
lypinator 0:bb348c97df44 13609 #define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */
lypinator 0:bb348c97df44 13610
lypinator 0:bb348c97df44 13611 #define USB_OTG_HCCHAR_EPNUM_Pos (11U)
lypinator 0:bb348c97df44 13612 #define USB_OTG_HCCHAR_EPNUM_Msk (0xFU << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */
lypinator 0:bb348c97df44 13613 #define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */
lypinator 0:bb348c97df44 13614 #define USB_OTG_HCCHAR_EPNUM_0 (0x1U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 13615 #define USB_OTG_HCCHAR_EPNUM_1 (0x2U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 13616 #define USB_OTG_HCCHAR_EPNUM_2 (0x4U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 13617 #define USB_OTG_HCCHAR_EPNUM_3 (0x8U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 13618 #define USB_OTG_HCCHAR_EPDIR_Pos (15U)
lypinator 0:bb348c97df44 13619 #define USB_OTG_HCCHAR_EPDIR_Msk (0x1U << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 13620 #define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk /*!< Endpoint direction */
lypinator 0:bb348c97df44 13621 #define USB_OTG_HCCHAR_LSDEV_Pos (17U)
lypinator 0:bb348c97df44 13622 #define USB_OTG_HCCHAR_LSDEV_Msk (0x1U << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 13623 #define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */
lypinator 0:bb348c97df44 13624
lypinator 0:bb348c97df44 13625 #define USB_OTG_HCCHAR_EPTYP_Pos (18U)
lypinator 0:bb348c97df44 13626 #define USB_OTG_HCCHAR_EPTYP_Msk (0x3U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */
lypinator 0:bb348c97df44 13627 #define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */
lypinator 0:bb348c97df44 13628 #define USB_OTG_HCCHAR_EPTYP_0 (0x1U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 13629 #define USB_OTG_HCCHAR_EPTYP_1 (0x2U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 13630
lypinator 0:bb348c97df44 13631 #define USB_OTG_HCCHAR_MC_Pos (20U)
lypinator 0:bb348c97df44 13632 #define USB_OTG_HCCHAR_MC_Msk (0x3U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */
lypinator 0:bb348c97df44 13633 #define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */
lypinator 0:bb348c97df44 13634 #define USB_OTG_HCCHAR_MC_0 (0x1U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 13635 #define USB_OTG_HCCHAR_MC_1 (0x2U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 13636
lypinator 0:bb348c97df44 13637 #define USB_OTG_HCCHAR_DAD_Pos (22U)
lypinator 0:bb348c97df44 13638 #define USB_OTG_HCCHAR_DAD_Msk (0x7FU << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */
lypinator 0:bb348c97df44 13639 #define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */
lypinator 0:bb348c97df44 13640 #define USB_OTG_HCCHAR_DAD_0 (0x01U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 13641 #define USB_OTG_HCCHAR_DAD_1 (0x02U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */
lypinator 0:bb348c97df44 13642 #define USB_OTG_HCCHAR_DAD_2 (0x04U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 13643 #define USB_OTG_HCCHAR_DAD_3 (0x08U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 13644 #define USB_OTG_HCCHAR_DAD_4 (0x10U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */
lypinator 0:bb348c97df44 13645 #define USB_OTG_HCCHAR_DAD_5 (0x20U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */
lypinator 0:bb348c97df44 13646 #define USB_OTG_HCCHAR_DAD_6 (0x40U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */
lypinator 0:bb348c97df44 13647 #define USB_OTG_HCCHAR_ODDFRM_Pos (29U)
lypinator 0:bb348c97df44 13648 #define USB_OTG_HCCHAR_ODDFRM_Msk (0x1U << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */
lypinator 0:bb348c97df44 13649 #define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk /*!< Odd frame */
lypinator 0:bb348c97df44 13650 #define USB_OTG_HCCHAR_CHDIS_Pos (30U)
lypinator 0:bb348c97df44 13651 #define USB_OTG_HCCHAR_CHDIS_Msk (0x1U << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */
lypinator 0:bb348c97df44 13652 #define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk /*!< Channel disable */
lypinator 0:bb348c97df44 13653 #define USB_OTG_HCCHAR_CHENA_Pos (31U)
lypinator 0:bb348c97df44 13654 #define USB_OTG_HCCHAR_CHENA_Msk (0x1U << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */
lypinator 0:bb348c97df44 13655 #define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk /*!< Channel enable */
lypinator 0:bb348c97df44 13656
lypinator 0:bb348c97df44 13657 /******************** Bit definition for USB_OTG_HCSPLT register ********************/
lypinator 0:bb348c97df44 13658
lypinator 0:bb348c97df44 13659 #define USB_OTG_HCSPLT_PRTADDR_Pos (0U)
lypinator 0:bb348c97df44 13660 #define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FU << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */
lypinator 0:bb348c97df44 13661 #define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk /*!< Port address */
lypinator 0:bb348c97df44 13662 #define USB_OTG_HCSPLT_PRTADDR_0 (0x01U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 13663 #define USB_OTG_HCSPLT_PRTADDR_1 (0x02U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 13664 #define USB_OTG_HCSPLT_PRTADDR_2 (0x04U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 13665 #define USB_OTG_HCSPLT_PRTADDR_3 (0x08U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 13666 #define USB_OTG_HCSPLT_PRTADDR_4 (0x10U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 13667 #define USB_OTG_HCSPLT_PRTADDR_5 (0x20U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 13668 #define USB_OTG_HCSPLT_PRTADDR_6 (0x40U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 13669
lypinator 0:bb348c97df44 13670 #define USB_OTG_HCSPLT_HUBADDR_Pos (7U)
lypinator 0:bb348c97df44 13671 #define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FU << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */
lypinator 0:bb348c97df44 13672 #define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk /*!< Hub address */
lypinator 0:bb348c97df44 13673 #define USB_OTG_HCSPLT_HUBADDR_0 (0x01U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 13674 #define USB_OTG_HCSPLT_HUBADDR_1 (0x02U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 13675 #define USB_OTG_HCSPLT_HUBADDR_2 (0x04U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 13676 #define USB_OTG_HCSPLT_HUBADDR_3 (0x08U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 13677 #define USB_OTG_HCSPLT_HUBADDR_4 (0x10U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 13678 #define USB_OTG_HCSPLT_HUBADDR_5 (0x20U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 13679 #define USB_OTG_HCSPLT_HUBADDR_6 (0x40U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 13680
lypinator 0:bb348c97df44 13681 #define USB_OTG_HCSPLT_XACTPOS_Pos (14U)
lypinator 0:bb348c97df44 13682 #define USB_OTG_HCSPLT_XACTPOS_Msk (0x3U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */
lypinator 0:bb348c97df44 13683 #define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk /*!< XACTPOS */
lypinator 0:bb348c97df44 13684 #define USB_OTG_HCSPLT_XACTPOS_0 (0x1U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 13685 #define USB_OTG_HCSPLT_XACTPOS_1 (0x2U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 13686 #define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U)
lypinator 0:bb348c97df44 13687 #define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1U << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 13688 #define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk /*!< Do complete split */
lypinator 0:bb348c97df44 13689 #define USB_OTG_HCSPLT_SPLITEN_Pos (31U)
lypinator 0:bb348c97df44 13690 #define USB_OTG_HCSPLT_SPLITEN_Msk (0x1U << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */
lypinator 0:bb348c97df44 13691 #define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk /*!< Split enable */
lypinator 0:bb348c97df44 13692
lypinator 0:bb348c97df44 13693 /******************** Bit definition for USB_OTG_HCINT register ********************/
lypinator 0:bb348c97df44 13694 #define USB_OTG_HCINT_XFRC_Pos (0U)
lypinator 0:bb348c97df44 13695 #define USB_OTG_HCINT_XFRC_Msk (0x1U << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 13696 #define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk /*!< Transfer completed */
lypinator 0:bb348c97df44 13697 #define USB_OTG_HCINT_CHH_Pos (1U)
lypinator 0:bb348c97df44 13698 #define USB_OTG_HCINT_CHH_Msk (0x1U << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 13699 #define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk /*!< Channel halted */
lypinator 0:bb348c97df44 13700 #define USB_OTG_HCINT_AHBERR_Pos (2U)
lypinator 0:bb348c97df44 13701 #define USB_OTG_HCINT_AHBERR_Msk (0x1U << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 13702 #define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk /*!< AHB error */
lypinator 0:bb348c97df44 13703 #define USB_OTG_HCINT_STALL_Pos (3U)
lypinator 0:bb348c97df44 13704 #define USB_OTG_HCINT_STALL_Msk (0x1U << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 13705 #define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk /*!< STALL response received interrupt */
lypinator 0:bb348c97df44 13706 #define USB_OTG_HCINT_NAK_Pos (4U)
lypinator 0:bb348c97df44 13707 #define USB_OTG_HCINT_NAK_Msk (0x1U << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 13708 #define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk /*!< NAK response received interrupt */
lypinator 0:bb348c97df44 13709 #define USB_OTG_HCINT_ACK_Pos (5U)
lypinator 0:bb348c97df44 13710 #define USB_OTG_HCINT_ACK_Msk (0x1U << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 13711 #define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk /*!< ACK response received/transmitted interrupt */
lypinator 0:bb348c97df44 13712 #define USB_OTG_HCINT_NYET_Pos (6U)
lypinator 0:bb348c97df44 13713 #define USB_OTG_HCINT_NYET_Msk (0x1U << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 13714 #define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk /*!< Response received interrupt */
lypinator 0:bb348c97df44 13715 #define USB_OTG_HCINT_TXERR_Pos (7U)
lypinator 0:bb348c97df44 13716 #define USB_OTG_HCINT_TXERR_Msk (0x1U << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 13717 #define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk /*!< Transaction error */
lypinator 0:bb348c97df44 13718 #define USB_OTG_HCINT_BBERR_Pos (8U)
lypinator 0:bb348c97df44 13719 #define USB_OTG_HCINT_BBERR_Msk (0x1U << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 13720 #define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk /*!< Babble error */
lypinator 0:bb348c97df44 13721 #define USB_OTG_HCINT_FRMOR_Pos (9U)
lypinator 0:bb348c97df44 13722 #define USB_OTG_HCINT_FRMOR_Msk (0x1U << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 13723 #define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk /*!< Frame overrun */
lypinator 0:bb348c97df44 13724 #define USB_OTG_HCINT_DTERR_Pos (10U)
lypinator 0:bb348c97df44 13725 #define USB_OTG_HCINT_DTERR_Msk (0x1U << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 13726 #define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk /*!< Data toggle error */
lypinator 0:bb348c97df44 13727
lypinator 0:bb348c97df44 13728 /******************** Bit definition for USB_OTG_DIEPINT register ********************/
lypinator 0:bb348c97df44 13729 #define USB_OTG_DIEPINT_XFRC_Pos (0U)
lypinator 0:bb348c97df44 13730 #define USB_OTG_DIEPINT_XFRC_Msk (0x1U << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 13731 #define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk /*!< Transfer completed interrupt */
lypinator 0:bb348c97df44 13732 #define USB_OTG_DIEPINT_EPDISD_Pos (1U)
lypinator 0:bb348c97df44 13733 #define USB_OTG_DIEPINT_EPDISD_Msk (0x1U << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 13734 #define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
lypinator 0:bb348c97df44 13735 #define USB_OTG_DIEPINT_TOC_Pos (3U)
lypinator 0:bb348c97df44 13736 #define USB_OTG_DIEPINT_TOC_Msk (0x1U << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 13737 #define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk /*!< Timeout condition */
lypinator 0:bb348c97df44 13738 #define USB_OTG_DIEPINT_ITTXFE_Pos (4U)
lypinator 0:bb348c97df44 13739 #define USB_OTG_DIEPINT_ITTXFE_Msk (0x1U << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 13740 #define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */
lypinator 0:bb348c97df44 13741 #define USB_OTG_DIEPINT_INEPNE_Pos (6U)
lypinator 0:bb348c97df44 13742 #define USB_OTG_DIEPINT_INEPNE_Msk (0x1U << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 13743 #define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */
lypinator 0:bb348c97df44 13744 #define USB_OTG_DIEPINT_TXFE_Pos (7U)
lypinator 0:bb348c97df44 13745 #define USB_OTG_DIEPINT_TXFE_Msk (0x1U << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 13746 #define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk /*!< Transmit FIFO empty */
lypinator 0:bb348c97df44 13747 #define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U)
lypinator 0:bb348c97df44 13748 #define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1U << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 13749 #define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */
lypinator 0:bb348c97df44 13750 #define USB_OTG_DIEPINT_BNA_Pos (9U)
lypinator 0:bb348c97df44 13751 #define USB_OTG_DIEPINT_BNA_Msk (0x1U << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 13752 #define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk /*!< Buffer not available interrupt */
lypinator 0:bb348c97df44 13753 #define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U)
lypinator 0:bb348c97df44 13754 #define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1U << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 13755 #define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */
lypinator 0:bb348c97df44 13756 #define USB_OTG_DIEPINT_BERR_Pos (12U)
lypinator 0:bb348c97df44 13757 #define USB_OTG_DIEPINT_BERR_Msk (0x1U << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 13758 #define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk /*!< Babble error interrupt */
lypinator 0:bb348c97df44 13759 #define USB_OTG_DIEPINT_NAK_Pos (13U)
lypinator 0:bb348c97df44 13760 #define USB_OTG_DIEPINT_NAK_Msk (0x1U << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 13761 #define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk /*!< NAK interrupt */
lypinator 0:bb348c97df44 13762
lypinator 0:bb348c97df44 13763 /******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
lypinator 0:bb348c97df44 13764 #define USB_OTG_HCINTMSK_XFRCM_Pos (0U)
lypinator 0:bb348c97df44 13765 #define USB_OTG_HCINTMSK_XFRCM_Msk (0x1U << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 13766 #define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk /*!< Transfer completed mask */
lypinator 0:bb348c97df44 13767 #define USB_OTG_HCINTMSK_CHHM_Pos (1U)
lypinator 0:bb348c97df44 13768 #define USB_OTG_HCINTMSK_CHHM_Msk (0x1U << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 13769 #define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */
lypinator 0:bb348c97df44 13770 #define USB_OTG_HCINTMSK_AHBERR_Pos (2U)
lypinator 0:bb348c97df44 13771 #define USB_OTG_HCINTMSK_AHBERR_Msk (0x1U << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 13772 #define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */
lypinator 0:bb348c97df44 13773 #define USB_OTG_HCINTMSK_STALLM_Pos (3U)
lypinator 0:bb348c97df44 13774 #define USB_OTG_HCINTMSK_STALLM_Msk (0x1U << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 13775 #define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */
lypinator 0:bb348c97df44 13776 #define USB_OTG_HCINTMSK_NAKM_Pos (4U)
lypinator 0:bb348c97df44 13777 #define USB_OTG_HCINTMSK_NAKM_Msk (0x1U << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 13778 #define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk /*!< NAK response received interrupt mask */
lypinator 0:bb348c97df44 13779 #define USB_OTG_HCINTMSK_ACKM_Pos (5U)
lypinator 0:bb348c97df44 13780 #define USB_OTG_HCINTMSK_ACKM_Msk (0x1U << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 13781 #define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk /*!< ACK response received/transmitted interrupt mask */
lypinator 0:bb348c97df44 13782 #define USB_OTG_HCINTMSK_NYET_Pos (6U)
lypinator 0:bb348c97df44 13783 #define USB_OTG_HCINTMSK_NYET_Msk (0x1U << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 13784 #define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk /*!< response received interrupt mask */
lypinator 0:bb348c97df44 13785 #define USB_OTG_HCINTMSK_TXERRM_Pos (7U)
lypinator 0:bb348c97df44 13786 #define USB_OTG_HCINTMSK_TXERRM_Msk (0x1U << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 13787 #define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk /*!< Transaction error mask */
lypinator 0:bb348c97df44 13788 #define USB_OTG_HCINTMSK_BBERRM_Pos (8U)
lypinator 0:bb348c97df44 13789 #define USB_OTG_HCINTMSK_BBERRM_Msk (0x1U << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 13790 #define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk /*!< Babble error mask */
lypinator 0:bb348c97df44 13791 #define USB_OTG_HCINTMSK_FRMORM_Pos (9U)
lypinator 0:bb348c97df44 13792 #define USB_OTG_HCINTMSK_FRMORM_Msk (0x1U << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 13793 #define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk /*!< Frame overrun mask */
lypinator 0:bb348c97df44 13794 #define USB_OTG_HCINTMSK_DTERRM_Pos (10U)
lypinator 0:bb348c97df44 13795 #define USB_OTG_HCINTMSK_DTERRM_Msk (0x1U << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 13796 #define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk /*!< Data toggle error mask */
lypinator 0:bb348c97df44 13797
lypinator 0:bb348c97df44 13798 /******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
lypinator 0:bb348c97df44 13799
lypinator 0:bb348c97df44 13800 #define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U)
lypinator 0:bb348c97df44 13801 #define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
lypinator 0:bb348c97df44 13802 #define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
lypinator 0:bb348c97df44 13803 #define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U)
lypinator 0:bb348c97df44 13804 #define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
lypinator 0:bb348c97df44 13805 #define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */
lypinator 0:bb348c97df44 13806 #define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U)
lypinator 0:bb348c97df44 13807 #define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */
lypinator 0:bb348c97df44 13808 #define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */
lypinator 0:bb348c97df44 13809 /******************** Bit definition for USB_OTG_HCTSIZ register ********************/
lypinator 0:bb348c97df44 13810 #define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U)
lypinator 0:bb348c97df44 13811 #define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
lypinator 0:bb348c97df44 13812 #define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk /*!< Transfer size */
lypinator 0:bb348c97df44 13813 #define USB_OTG_HCTSIZ_PKTCNT_Pos (19U)
lypinator 0:bb348c97df44 13814 #define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
lypinator 0:bb348c97df44 13815 #define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */
lypinator 0:bb348c97df44 13816 #define USB_OTG_HCTSIZ_DOPING_Pos (31U)
lypinator 0:bb348c97df44 13817 #define USB_OTG_HCTSIZ_DOPING_Msk (0x1U << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */
lypinator 0:bb348c97df44 13818 #define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */
lypinator 0:bb348c97df44 13819 #define USB_OTG_HCTSIZ_DPID_Pos (29U)
lypinator 0:bb348c97df44 13820 #define USB_OTG_HCTSIZ_DPID_Msk (0x3U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */
lypinator 0:bb348c97df44 13821 #define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */
lypinator 0:bb348c97df44 13822 #define USB_OTG_HCTSIZ_DPID_0 (0x1U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */
lypinator 0:bb348c97df44 13823 #define USB_OTG_HCTSIZ_DPID_1 (0x2U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */
lypinator 0:bb348c97df44 13824
lypinator 0:bb348c97df44 13825 /******************** Bit definition for USB_OTG_DIEPDMA register ********************/
lypinator 0:bb348c97df44 13826 #define USB_OTG_DIEPDMA_DMAADDR_Pos (0U)
lypinator 0:bb348c97df44 13827 #define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFU << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
lypinator 0:bb348c97df44 13828 #define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk /*!< DMA address */
lypinator 0:bb348c97df44 13829
lypinator 0:bb348c97df44 13830 /******************** Bit definition for USB_OTG_HCDMA register ********************/
lypinator 0:bb348c97df44 13831 #define USB_OTG_HCDMA_DMAADDR_Pos (0U)
lypinator 0:bb348c97df44 13832 #define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFU << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
lypinator 0:bb348c97df44 13833 #define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk /*!< DMA address */
lypinator 0:bb348c97df44 13834
lypinator 0:bb348c97df44 13835 /******************** Bit definition for USB_OTG_DTXFSTS register ********************/
lypinator 0:bb348c97df44 13836 #define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U)
lypinator 0:bb348c97df44 13837 #define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFU << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */
lypinator 0:bb348c97df44 13838 #define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */
lypinator 0:bb348c97df44 13839
lypinator 0:bb348c97df44 13840 /******************** Bit definition for USB_OTG_DIEPTXF register ********************/
lypinator 0:bb348c97df44 13841 #define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U)
lypinator 0:bb348c97df44 13842 #define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFU << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */
lypinator 0:bb348c97df44 13843 #define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk /*!< IN endpoint FIFOx transmit RAM start address */
lypinator 0:bb348c97df44 13844 #define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U)
lypinator 0:bb348c97df44 13845 #define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFU << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */
lypinator 0:bb348c97df44 13846 #define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk /*!< IN endpoint TxFIFO depth */
lypinator 0:bb348c97df44 13847
lypinator 0:bb348c97df44 13848 /******************** Bit definition for USB_OTG_DOEPCTL register ********************/
lypinator 0:bb348c97df44 13849
lypinator 0:bb348c97df44 13850 #define USB_OTG_DOEPCTL_MPSIZ_Pos (0U)
lypinator 0:bb348c97df44 13851 #define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFU << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
lypinator 0:bb348c97df44 13852 #define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk /*!< Maximum packet size */ /*!<Bit 1 */
lypinator 0:bb348c97df44 13853 #define USB_OTG_DOEPCTL_USBAEP_Pos (15U)
lypinator 0:bb348c97df44 13854 #define USB_OTG_DOEPCTL_USBAEP_Msk (0x1U << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 13855 #define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk /*!< USB active endpoint */
lypinator 0:bb348c97df44 13856 #define USB_OTG_DOEPCTL_NAKSTS_Pos (17U)
lypinator 0:bb348c97df44 13857 #define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 13858 #define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk /*!< NAK status */
lypinator 0:bb348c97df44 13859 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U)
lypinator 0:bb348c97df44 13860 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
lypinator 0:bb348c97df44 13861 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
lypinator 0:bb348c97df44 13862 #define USB_OTG_DOEPCTL_SODDFRM_Pos (29U)
lypinator 0:bb348c97df44 13863 #define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
lypinator 0:bb348c97df44 13864 #define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk /*!< Set odd frame */
lypinator 0:bb348c97df44 13865 #define USB_OTG_DOEPCTL_EPTYP_Pos (18U)
lypinator 0:bb348c97df44 13866 #define USB_OTG_DOEPCTL_EPTYP_Msk (0x3U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
lypinator 0:bb348c97df44 13867 #define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk /*!< Endpoint type */
lypinator 0:bb348c97df44 13868 #define USB_OTG_DOEPCTL_EPTYP_0 (0x1U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 13869 #define USB_OTG_DOEPCTL_EPTYP_1 (0x2U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 13870 #define USB_OTG_DOEPCTL_SNPM_Pos (20U)
lypinator 0:bb348c97df44 13871 #define USB_OTG_DOEPCTL_SNPM_Msk (0x1U << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 13872 #define USB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_Msk /*!< Snoop mode */
lypinator 0:bb348c97df44 13873 #define USB_OTG_DOEPCTL_STALL_Pos (21U)
lypinator 0:bb348c97df44 13874 #define USB_OTG_DOEPCTL_STALL_Msk (0x1U << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 13875 #define USB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_Msk /*!< STALL handshake */
lypinator 0:bb348c97df44 13876 #define USB_OTG_DOEPCTL_CNAK_Pos (26U)
lypinator 0:bb348c97df44 13877 #define USB_OTG_DOEPCTL_CNAK_Msk (0x1U << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */
lypinator 0:bb348c97df44 13878 #define USB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_Msk /*!< Clear NAK */
lypinator 0:bb348c97df44 13879 #define USB_OTG_DOEPCTL_SNAK_Pos (27U)
lypinator 0:bb348c97df44 13880 #define USB_OTG_DOEPCTL_SNAK_Msk (0x1U << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */
lypinator 0:bb348c97df44 13881 #define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk /*!< Set NAK */
lypinator 0:bb348c97df44 13882 #define USB_OTG_DOEPCTL_EPDIS_Pos (30U)
lypinator 0:bb348c97df44 13883 #define USB_OTG_DOEPCTL_EPDIS_Msk (0x1U << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */
lypinator 0:bb348c97df44 13884 #define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk /*!< Endpoint disable */
lypinator 0:bb348c97df44 13885 #define USB_OTG_DOEPCTL_EPENA_Pos (31U)
lypinator 0:bb348c97df44 13886 #define USB_OTG_DOEPCTL_EPENA_Msk (0x1U << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */
lypinator 0:bb348c97df44 13887 #define USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_Msk /*!< Endpoint enable */
lypinator 0:bb348c97df44 13888
lypinator 0:bb348c97df44 13889 /******************** Bit definition for USB_OTG_DOEPINT register ********************/
lypinator 0:bb348c97df44 13890 #define USB_OTG_DOEPINT_XFRC_Pos (0U)
lypinator 0:bb348c97df44 13891 #define USB_OTG_DOEPINT_XFRC_Msk (0x1U << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 13892 #define USB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_Msk /*!< Transfer completed interrupt */
lypinator 0:bb348c97df44 13893 #define USB_OTG_DOEPINT_EPDISD_Pos (1U)
lypinator 0:bb348c97df44 13894 #define USB_OTG_DOEPINT_EPDISD_Msk (0x1U << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 13895 #define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
lypinator 0:bb348c97df44 13896 #define USB_OTG_DOEPINT_STUP_Pos (3U)
lypinator 0:bb348c97df44 13897 #define USB_OTG_DOEPINT_STUP_Msk (0x1U << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 13898 #define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk /*!< SETUP phase done */
lypinator 0:bb348c97df44 13899 #define USB_OTG_DOEPINT_OTEPDIS_Pos (4U)
lypinator 0:bb348c97df44 13900 #define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1U << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 13901 #define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk /*!< OUT token received when endpoint disabled */
lypinator 0:bb348c97df44 13902 #define USB_OTG_DOEPINT_OTEPSPR_Pos (5U)
lypinator 0:bb348c97df44 13903 #define USB_OTG_DOEPINT_OTEPSPR_Msk (0x1U << USB_OTG_DOEPINT_OTEPSPR_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 13904 #define USB_OTG_DOEPINT_OTEPSPR USB_OTG_DOEPINT_OTEPSPR_Msk /*!< Status Phase Received For Control Write */
lypinator 0:bb348c97df44 13905 #define USB_OTG_DOEPINT_B2BSTUP_Pos (6U)
lypinator 0:bb348c97df44 13906 #define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1U << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 13907 #define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */
lypinator 0:bb348c97df44 13908 #define USB_OTG_DOEPINT_NYET_Pos (14U)
lypinator 0:bb348c97df44 13909 #define USB_OTG_DOEPINT_NYET_Msk (0x1U << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 13910 #define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk /*!< NYET interrupt */
lypinator 0:bb348c97df44 13911
lypinator 0:bb348c97df44 13912 /******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/
lypinator 0:bb348c97df44 13913
lypinator 0:bb348c97df44 13914 #define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U)
lypinator 0:bb348c97df44 13915 #define USB_OTG_DOEPTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
lypinator 0:bb348c97df44 13916 #define USB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
lypinator 0:bb348c97df44 13917 #define USB_OTG_DOEPTSIZ_PKTCNT_Pos (19U)
lypinator 0:bb348c97df44 13918 #define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
lypinator 0:bb348c97df44 13919 #define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk /*!< Packet count */
lypinator 0:bb348c97df44 13920
lypinator 0:bb348c97df44 13921 #define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U)
lypinator 0:bb348c97df44 13922 #define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */
lypinator 0:bb348c97df44 13923 #define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk /*!< SETUP packet count */
lypinator 0:bb348c97df44 13924 #define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */
lypinator 0:bb348c97df44 13925 #define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */
lypinator 0:bb348c97df44 13926
lypinator 0:bb348c97df44 13927 /******************** Bit definition for PCGCCTL register ********************/
lypinator 0:bb348c97df44 13928 #define USB_OTG_PCGCCTL_STOPCLK_Pos (0U)
lypinator 0:bb348c97df44 13929 #define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1U << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 13930 #define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk /*!< SETUP packet count */
lypinator 0:bb348c97df44 13931 #define USB_OTG_PCGCCTL_GATECLK_Pos (1U)
lypinator 0:bb348c97df44 13932 #define USB_OTG_PCGCCTL_GATECLK_Msk (0x1U << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 13933 #define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk /*!<Bit 0 */
lypinator 0:bb348c97df44 13934 #define USB_OTG_PCGCCTL_PHYSUSP_Pos (4U)
lypinator 0:bb348c97df44 13935 #define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1U << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 13936 #define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk /*!<Bit 1 */
lypinator 0:bb348c97df44 13937
lypinator 0:bb348c97df44 13938 /* Legacy define */
lypinator 0:bb348c97df44 13939 /******************** Bit definition for OTG register ********************/
lypinator 0:bb348c97df44 13940 #define USB_OTG_CHNUM_Pos (0U)
lypinator 0:bb348c97df44 13941 #define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */
lypinator 0:bb348c97df44 13942 #define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */
lypinator 0:bb348c97df44 13943 #define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 13944 #define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 13945 #define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 13946 #define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 13947 #define USB_OTG_BCNT_Pos (4U)
lypinator 0:bb348c97df44 13948 #define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
lypinator 0:bb348c97df44 13949 #define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */
lypinator 0:bb348c97df44 13950
lypinator 0:bb348c97df44 13951 #define USB_OTG_DPID_Pos (15U)
lypinator 0:bb348c97df44 13952 #define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */
lypinator 0:bb348c97df44 13953 #define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */
lypinator 0:bb348c97df44 13954 #define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 13955 #define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 13956
lypinator 0:bb348c97df44 13957 #define USB_OTG_PKTSTS_Pos (17U)
lypinator 0:bb348c97df44 13958 #define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
lypinator 0:bb348c97df44 13959 #define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */
lypinator 0:bb348c97df44 13960 #define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 13961 #define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 13962 #define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 13963 #define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 13964
lypinator 0:bb348c97df44 13965 #define USB_OTG_EPNUM_Pos (0U)
lypinator 0:bb348c97df44 13966 #define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */
lypinator 0:bb348c97df44 13967 #define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */
lypinator 0:bb348c97df44 13968 #define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 13969 #define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 13970 #define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 13971 #define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 13972
lypinator 0:bb348c97df44 13973 #define USB_OTG_FRMNUM_Pos (21U)
lypinator 0:bb348c97df44 13974 #define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
lypinator 0:bb348c97df44 13975 #define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */
lypinator 0:bb348c97df44 13976 #define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 13977 #define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 13978 #define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
lypinator 0:bb348c97df44 13979 #define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 13980 /**
lypinator 0:bb348c97df44 13981 * @}
lypinator 0:bb348c97df44 13982 */
lypinator 0:bb348c97df44 13983
lypinator 0:bb348c97df44 13984 /**
lypinator 0:bb348c97df44 13985 * @}
lypinator 0:bb348c97df44 13986 */
lypinator 0:bb348c97df44 13987
lypinator 0:bb348c97df44 13988 /** @addtogroup Exported_macros
lypinator 0:bb348c97df44 13989 * @{
lypinator 0:bb348c97df44 13990 */
lypinator 0:bb348c97df44 13991
lypinator 0:bb348c97df44 13992 /******************************* ADC Instances ********************************/
lypinator 0:bb348c97df44 13993 #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
lypinator 0:bb348c97df44 13994
lypinator 0:bb348c97df44 13995 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
lypinator 0:bb348c97df44 13996
lypinator 0:bb348c97df44 13997 /******************************* CAN Instances ********************************/
lypinator 0:bb348c97df44 13998 #define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
lypinator 0:bb348c97df44 13999 ((INSTANCE) == CAN2))
lypinator 0:bb348c97df44 14000
lypinator 0:bb348c97df44 14001 /****************************** DFSDM Instances *******************************/
lypinator 0:bb348c97df44 14002 #define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \
lypinator 0:bb348c97df44 14003 ((INSTANCE) == DFSDM1_Filter1))
lypinator 0:bb348c97df44 14004
lypinator 0:bb348c97df44 14005 #define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \
lypinator 0:bb348c97df44 14006 ((INSTANCE) == DFSDM1_Channel1) || \
lypinator 0:bb348c97df44 14007 ((INSTANCE) == DFSDM1_Channel2) || \
lypinator 0:bb348c97df44 14008 ((INSTANCE) == DFSDM1_Channel3))
lypinator 0:bb348c97df44 14009 /******************************* CRC Instances ********************************/
lypinator 0:bb348c97df44 14010 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
lypinator 0:bb348c97df44 14011
lypinator 0:bb348c97df44 14012
lypinator 0:bb348c97df44 14013 /******************************** DMA Instances *******************************/
lypinator 0:bb348c97df44 14014 #define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
lypinator 0:bb348c97df44 14015 ((INSTANCE) == DMA1_Stream1) || \
lypinator 0:bb348c97df44 14016 ((INSTANCE) == DMA1_Stream2) || \
lypinator 0:bb348c97df44 14017 ((INSTANCE) == DMA1_Stream3) || \
lypinator 0:bb348c97df44 14018 ((INSTANCE) == DMA1_Stream4) || \
lypinator 0:bb348c97df44 14019 ((INSTANCE) == DMA1_Stream5) || \
lypinator 0:bb348c97df44 14020 ((INSTANCE) == DMA1_Stream6) || \
lypinator 0:bb348c97df44 14021 ((INSTANCE) == DMA1_Stream7) || \
lypinator 0:bb348c97df44 14022 ((INSTANCE) == DMA2_Stream0) || \
lypinator 0:bb348c97df44 14023 ((INSTANCE) == DMA2_Stream1) || \
lypinator 0:bb348c97df44 14024 ((INSTANCE) == DMA2_Stream2) || \
lypinator 0:bb348c97df44 14025 ((INSTANCE) == DMA2_Stream3) || \
lypinator 0:bb348c97df44 14026 ((INSTANCE) == DMA2_Stream4) || \
lypinator 0:bb348c97df44 14027 ((INSTANCE) == DMA2_Stream5) || \
lypinator 0:bb348c97df44 14028 ((INSTANCE) == DMA2_Stream6) || \
lypinator 0:bb348c97df44 14029 ((INSTANCE) == DMA2_Stream7))
lypinator 0:bb348c97df44 14030
lypinator 0:bb348c97df44 14031 /******************************* GPIO Instances *******************************/
lypinator 0:bb348c97df44 14032 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
lypinator 0:bb348c97df44 14033 ((INSTANCE) == GPIOB) || \
lypinator 0:bb348c97df44 14034 ((INSTANCE) == GPIOC) || \
lypinator 0:bb348c97df44 14035 ((INSTANCE) == GPIOD) || \
lypinator 0:bb348c97df44 14036 ((INSTANCE) == GPIOE) || \
lypinator 0:bb348c97df44 14037 ((INSTANCE) == GPIOF) || \
lypinator 0:bb348c97df44 14038 ((INSTANCE) == GPIOG) || \
lypinator 0:bb348c97df44 14039 ((INSTANCE) == GPIOH))
lypinator 0:bb348c97df44 14040
lypinator 0:bb348c97df44 14041 /******************************** I2C Instances *******************************/
lypinator 0:bb348c97df44 14042 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
lypinator 0:bb348c97df44 14043 ((INSTANCE) == I2C2) || \
lypinator 0:bb348c97df44 14044 ((INSTANCE) == I2C3))
lypinator 0:bb348c97df44 14045
lypinator 0:bb348c97df44 14046 /******************************* SMBUS Instances ******************************/
lypinator 0:bb348c97df44 14047 #define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE
lypinator 0:bb348c97df44 14048
lypinator 0:bb348c97df44 14049 /******************************** I2S Instances *******************************/
lypinator 0:bb348c97df44 14050 #define IS_I2S_APB1_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
lypinator 0:bb348c97df44 14051 ((INSTANCE) == SPI3))
lypinator 0:bb348c97df44 14052
lypinator 0:bb348c97df44 14053 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
lypinator 0:bb348c97df44 14054 ((INSTANCE) == SPI2) || \
lypinator 0:bb348c97df44 14055 ((INSTANCE) == SPI3) || \
lypinator 0:bb348c97df44 14056 ((INSTANCE) == SPI4) || \
lypinator 0:bb348c97df44 14057 ((INSTANCE) == SPI5))
lypinator 0:bb348c97df44 14058
lypinator 0:bb348c97df44 14059 /*************************** I2S Extended Instances ***************************/
lypinator 0:bb348c97df44 14060 #define IS_I2S_EXT_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2S2ext)|| \
lypinator 0:bb348c97df44 14061 ((INSTANCE) == I2S3ext))
lypinator 0:bb348c97df44 14062 /* Legacy Defines */
lypinator 0:bb348c97df44 14063 #define IS_I2S_ALL_INSTANCE_EXT IS_I2S_EXT_ALL_INSTANCE
lypinator 0:bb348c97df44 14064
lypinator 0:bb348c97df44 14065 /******************************* RNG Instances ********************************/
lypinator 0:bb348c97df44 14066 #define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
lypinator 0:bb348c97df44 14067
lypinator 0:bb348c97df44 14068 /****************************** RTC Instances *********************************/
lypinator 0:bb348c97df44 14069 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
lypinator 0:bb348c97df44 14070
lypinator 0:bb348c97df44 14071
lypinator 0:bb348c97df44 14072 /******************************** SPI Instances *******************************/
lypinator 0:bb348c97df44 14073
lypinator 0:bb348c97df44 14074 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
lypinator 0:bb348c97df44 14075 ((INSTANCE) == SPI2) || \
lypinator 0:bb348c97df44 14076 ((INSTANCE) == SPI3) || \
lypinator 0:bb348c97df44 14077 ((INSTANCE) == SPI4) || \
lypinator 0:bb348c97df44 14078 ((INSTANCE) == SPI5))
lypinator 0:bb348c97df44 14079
lypinator 0:bb348c97df44 14080
lypinator 0:bb348c97df44 14081 /****************** TIM Instances : All supported instances *******************/
lypinator 0:bb348c97df44 14082 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
lypinator 0:bb348c97df44 14083 ((INSTANCE) == TIM2) || \
lypinator 0:bb348c97df44 14084 ((INSTANCE) == TIM3) || \
lypinator 0:bb348c97df44 14085 ((INSTANCE) == TIM4) || \
lypinator 0:bb348c97df44 14086 ((INSTANCE) == TIM5) || \
lypinator 0:bb348c97df44 14087 ((INSTANCE) == TIM6) || \
lypinator 0:bb348c97df44 14088 ((INSTANCE) == TIM7) || \
lypinator 0:bb348c97df44 14089 ((INSTANCE) == TIM8) || \
lypinator 0:bb348c97df44 14090 ((INSTANCE) == TIM9) || \
lypinator 0:bb348c97df44 14091 ((INSTANCE) == TIM10)|| \
lypinator 0:bb348c97df44 14092 ((INSTANCE) == TIM11)|| \
lypinator 0:bb348c97df44 14093 ((INSTANCE) == TIM12)|| \
lypinator 0:bb348c97df44 14094 ((INSTANCE) == TIM13)|| \
lypinator 0:bb348c97df44 14095 ((INSTANCE) == TIM14))
lypinator 0:bb348c97df44 14096
lypinator 0:bb348c97df44 14097 /************* TIM Instances : at least 1 capture/compare channel *************/
lypinator 0:bb348c97df44 14098 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
lypinator 0:bb348c97df44 14099 ((INSTANCE) == TIM2) || \
lypinator 0:bb348c97df44 14100 ((INSTANCE) == TIM3) || \
lypinator 0:bb348c97df44 14101 ((INSTANCE) == TIM4) || \
lypinator 0:bb348c97df44 14102 ((INSTANCE) == TIM5) || \
lypinator 0:bb348c97df44 14103 ((INSTANCE) == TIM8) || \
lypinator 0:bb348c97df44 14104 ((INSTANCE) == TIM9) || \
lypinator 0:bb348c97df44 14105 ((INSTANCE) == TIM10) || \
lypinator 0:bb348c97df44 14106 ((INSTANCE) == TIM11) || \
lypinator 0:bb348c97df44 14107 ((INSTANCE) == TIM12) || \
lypinator 0:bb348c97df44 14108 ((INSTANCE) == TIM13) || \
lypinator 0:bb348c97df44 14109 ((INSTANCE) == TIM14))
lypinator 0:bb348c97df44 14110
lypinator 0:bb348c97df44 14111 /************ TIM Instances : at least 2 capture/compare channels *************/
lypinator 0:bb348c97df44 14112 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
lypinator 0:bb348c97df44 14113 ((INSTANCE) == TIM2) || \
lypinator 0:bb348c97df44 14114 ((INSTANCE) == TIM3) || \
lypinator 0:bb348c97df44 14115 ((INSTANCE) == TIM4) || \
lypinator 0:bb348c97df44 14116 ((INSTANCE) == TIM5) || \
lypinator 0:bb348c97df44 14117 ((INSTANCE) == TIM8) || \
lypinator 0:bb348c97df44 14118 ((INSTANCE) == TIM9) || \
lypinator 0:bb348c97df44 14119 ((INSTANCE) == TIM12))
lypinator 0:bb348c97df44 14120
lypinator 0:bb348c97df44 14121 /************ TIM Instances : at least 3 capture/compare channels *************/
lypinator 0:bb348c97df44 14122 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
lypinator 0:bb348c97df44 14123 ((INSTANCE) == TIM2) || \
lypinator 0:bb348c97df44 14124 ((INSTANCE) == TIM3) || \
lypinator 0:bb348c97df44 14125 ((INSTANCE) == TIM4) || \
lypinator 0:bb348c97df44 14126 ((INSTANCE) == TIM5) || \
lypinator 0:bb348c97df44 14127 ((INSTANCE) == TIM8))
lypinator 0:bb348c97df44 14128
lypinator 0:bb348c97df44 14129 /************ TIM Instances : at least 4 capture/compare channels *************/
lypinator 0:bb348c97df44 14130 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
lypinator 0:bb348c97df44 14131 ((INSTANCE) == TIM2) || \
lypinator 0:bb348c97df44 14132 ((INSTANCE) == TIM3) || \
lypinator 0:bb348c97df44 14133 ((INSTANCE) == TIM4) || \
lypinator 0:bb348c97df44 14134 ((INSTANCE) == TIM5) || \
lypinator 0:bb348c97df44 14135 ((INSTANCE) == TIM8))
lypinator 0:bb348c97df44 14136
lypinator 0:bb348c97df44 14137 /******************** TIM Instances : Advanced-control timers *****************/
lypinator 0:bb348c97df44 14138 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
lypinator 0:bb348c97df44 14139 ((INSTANCE) == TIM8))
lypinator 0:bb348c97df44 14140
lypinator 0:bb348c97df44 14141 /******************* TIM Instances : Timer input XOR function *****************/
lypinator 0:bb348c97df44 14142 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
lypinator 0:bb348c97df44 14143 ((INSTANCE) == TIM2) || \
lypinator 0:bb348c97df44 14144 ((INSTANCE) == TIM3) || \
lypinator 0:bb348c97df44 14145 ((INSTANCE) == TIM4) || \
lypinator 0:bb348c97df44 14146 ((INSTANCE) == TIM5) || \
lypinator 0:bb348c97df44 14147 ((INSTANCE) == TIM8))
lypinator 0:bb348c97df44 14148
lypinator 0:bb348c97df44 14149 /****************** TIM Instances : DMA requests generation (UDE) *************/
lypinator 0:bb348c97df44 14150 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
lypinator 0:bb348c97df44 14151 ((INSTANCE) == TIM2) || \
lypinator 0:bb348c97df44 14152 ((INSTANCE) == TIM3) || \
lypinator 0:bb348c97df44 14153 ((INSTANCE) == TIM4) || \
lypinator 0:bb348c97df44 14154 ((INSTANCE) == TIM5) || \
lypinator 0:bb348c97df44 14155 ((INSTANCE) == TIM6) || \
lypinator 0:bb348c97df44 14156 ((INSTANCE) == TIM7) || \
lypinator 0:bb348c97df44 14157 ((INSTANCE) == TIM8))
lypinator 0:bb348c97df44 14158
lypinator 0:bb348c97df44 14159 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
lypinator 0:bb348c97df44 14160 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
lypinator 0:bb348c97df44 14161 ((INSTANCE) == TIM2) || \
lypinator 0:bb348c97df44 14162 ((INSTANCE) == TIM3) || \
lypinator 0:bb348c97df44 14163 ((INSTANCE) == TIM4) || \
lypinator 0:bb348c97df44 14164 ((INSTANCE) == TIM5) || \
lypinator 0:bb348c97df44 14165 ((INSTANCE) == TIM8))
lypinator 0:bb348c97df44 14166
lypinator 0:bb348c97df44 14167 /************ TIM Instances : DMA requests generation (COMDE) *****************/
lypinator 0:bb348c97df44 14168 #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
lypinator 0:bb348c97df44 14169 ((INSTANCE) == TIM2) || \
lypinator 0:bb348c97df44 14170 ((INSTANCE) == TIM3) || \
lypinator 0:bb348c97df44 14171 ((INSTANCE) == TIM4) || \
lypinator 0:bb348c97df44 14172 ((INSTANCE) == TIM5) || \
lypinator 0:bb348c97df44 14173 ((INSTANCE) == TIM8))
lypinator 0:bb348c97df44 14174
lypinator 0:bb348c97df44 14175 /******************** TIM Instances : DMA burst feature ***********************/
lypinator 0:bb348c97df44 14176 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
lypinator 0:bb348c97df44 14177 ((INSTANCE) == TIM2) || \
lypinator 0:bb348c97df44 14178 ((INSTANCE) == TIM3) || \
lypinator 0:bb348c97df44 14179 ((INSTANCE) == TIM4) || \
lypinator 0:bb348c97df44 14180 ((INSTANCE) == TIM5) || \
lypinator 0:bb348c97df44 14181 ((INSTANCE) == TIM8))
lypinator 0:bb348c97df44 14182
lypinator 0:bb348c97df44 14183 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
lypinator 0:bb348c97df44 14184 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
lypinator 0:bb348c97df44 14185 ((INSTANCE) == TIM2) || \
lypinator 0:bb348c97df44 14186 ((INSTANCE) == TIM3) || \
lypinator 0:bb348c97df44 14187 ((INSTANCE) == TIM4) || \
lypinator 0:bb348c97df44 14188 ((INSTANCE) == TIM5) || \
lypinator 0:bb348c97df44 14189 ((INSTANCE) == TIM6) || \
lypinator 0:bb348c97df44 14190 ((INSTANCE) == TIM8))
lypinator 0:bb348c97df44 14191
lypinator 0:bb348c97df44 14192 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
lypinator 0:bb348c97df44 14193 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
lypinator 0:bb348c97df44 14194 ((INSTANCE) == TIM2) || \
lypinator 0:bb348c97df44 14195 ((INSTANCE) == TIM3) || \
lypinator 0:bb348c97df44 14196 ((INSTANCE) == TIM4) || \
lypinator 0:bb348c97df44 14197 ((INSTANCE) == TIM5) || \
lypinator 0:bb348c97df44 14198 ((INSTANCE) == TIM8) || \
lypinator 0:bb348c97df44 14199 ((INSTANCE) == TIM9) || \
lypinator 0:bb348c97df44 14200 ((INSTANCE) == TIM12))
lypinator 0:bb348c97df44 14201
lypinator 0:bb348c97df44 14202 /********************** TIM Instances : 32 bit Counter ************************/
lypinator 0:bb348c97df44 14203 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
lypinator 0:bb348c97df44 14204 ((INSTANCE) == TIM5))
lypinator 0:bb348c97df44 14205
lypinator 0:bb348c97df44 14206 /***************** TIM Instances : external trigger input availabe ************/
lypinator 0:bb348c97df44 14207 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
lypinator 0:bb348c97df44 14208 ((INSTANCE) == TIM2) || \
lypinator 0:bb348c97df44 14209 ((INSTANCE) == TIM3) || \
lypinator 0:bb348c97df44 14210 ((INSTANCE) == TIM4) || \
lypinator 0:bb348c97df44 14211 ((INSTANCE) == TIM5) || \
lypinator 0:bb348c97df44 14212 ((INSTANCE) == TIM8))
lypinator 0:bb348c97df44 14213
lypinator 0:bb348c97df44 14214 /****************** TIM Instances : remapping capability **********************/
lypinator 0:bb348c97df44 14215 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
lypinator 0:bb348c97df44 14216 ((INSTANCE) == TIM5) || \
lypinator 0:bb348c97df44 14217 ((INSTANCE) == TIM11))
lypinator 0:bb348c97df44 14218
lypinator 0:bb348c97df44 14219 /******************* TIM Instances : output(s) available **********************/
lypinator 0:bb348c97df44 14220 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
lypinator 0:bb348c97df44 14221 ((((INSTANCE) == TIM1) && \
lypinator 0:bb348c97df44 14222 (((CHANNEL) == TIM_CHANNEL_1) || \
lypinator 0:bb348c97df44 14223 ((CHANNEL) == TIM_CHANNEL_2) || \
lypinator 0:bb348c97df44 14224 ((CHANNEL) == TIM_CHANNEL_3) || \
lypinator 0:bb348c97df44 14225 ((CHANNEL) == TIM_CHANNEL_4))) \
lypinator 0:bb348c97df44 14226 || \
lypinator 0:bb348c97df44 14227 (((INSTANCE) == TIM2) && \
lypinator 0:bb348c97df44 14228 (((CHANNEL) == TIM_CHANNEL_1) || \
lypinator 0:bb348c97df44 14229 ((CHANNEL) == TIM_CHANNEL_2) || \
lypinator 0:bb348c97df44 14230 ((CHANNEL) == TIM_CHANNEL_3) || \
lypinator 0:bb348c97df44 14231 ((CHANNEL) == TIM_CHANNEL_4))) \
lypinator 0:bb348c97df44 14232 || \
lypinator 0:bb348c97df44 14233 (((INSTANCE) == TIM3) && \
lypinator 0:bb348c97df44 14234 (((CHANNEL) == TIM_CHANNEL_1) || \
lypinator 0:bb348c97df44 14235 ((CHANNEL) == TIM_CHANNEL_2) || \
lypinator 0:bb348c97df44 14236 ((CHANNEL) == TIM_CHANNEL_3) || \
lypinator 0:bb348c97df44 14237 ((CHANNEL) == TIM_CHANNEL_4))) \
lypinator 0:bb348c97df44 14238 || \
lypinator 0:bb348c97df44 14239 (((INSTANCE) == TIM4) && \
lypinator 0:bb348c97df44 14240 (((CHANNEL) == TIM_CHANNEL_1) || \
lypinator 0:bb348c97df44 14241 ((CHANNEL) == TIM_CHANNEL_2) || \
lypinator 0:bb348c97df44 14242 ((CHANNEL) == TIM_CHANNEL_3) || \
lypinator 0:bb348c97df44 14243 ((CHANNEL) == TIM_CHANNEL_4))) \
lypinator 0:bb348c97df44 14244 || \
lypinator 0:bb348c97df44 14245 (((INSTANCE) == TIM5) && \
lypinator 0:bb348c97df44 14246 (((CHANNEL) == TIM_CHANNEL_1) || \
lypinator 0:bb348c97df44 14247 ((CHANNEL) == TIM_CHANNEL_2) || \
lypinator 0:bb348c97df44 14248 ((CHANNEL) == TIM_CHANNEL_3) || \
lypinator 0:bb348c97df44 14249 ((CHANNEL) == TIM_CHANNEL_4))) \
lypinator 0:bb348c97df44 14250 || \
lypinator 0:bb348c97df44 14251 (((INSTANCE) == TIM8) && \
lypinator 0:bb348c97df44 14252 (((CHANNEL) == TIM_CHANNEL_1) || \
lypinator 0:bb348c97df44 14253 ((CHANNEL) == TIM_CHANNEL_2) || \
lypinator 0:bb348c97df44 14254 ((CHANNEL) == TIM_CHANNEL_3) || \
lypinator 0:bb348c97df44 14255 ((CHANNEL) == TIM_CHANNEL_4))) \
lypinator 0:bb348c97df44 14256 || \
lypinator 0:bb348c97df44 14257 (((INSTANCE) == TIM9) && \
lypinator 0:bb348c97df44 14258 (((CHANNEL) == TIM_CHANNEL_1) || \
lypinator 0:bb348c97df44 14259 ((CHANNEL) == TIM_CHANNEL_2))) \
lypinator 0:bb348c97df44 14260 || \
lypinator 0:bb348c97df44 14261 (((INSTANCE) == TIM10) && \
lypinator 0:bb348c97df44 14262 (((CHANNEL) == TIM_CHANNEL_1))) \
lypinator 0:bb348c97df44 14263 || \
lypinator 0:bb348c97df44 14264 (((INSTANCE) == TIM11) && \
lypinator 0:bb348c97df44 14265 (((CHANNEL) == TIM_CHANNEL_1))) \
lypinator 0:bb348c97df44 14266 || \
lypinator 0:bb348c97df44 14267 (((INSTANCE) == TIM12) && \
lypinator 0:bb348c97df44 14268 (((CHANNEL) == TIM_CHANNEL_1) || \
lypinator 0:bb348c97df44 14269 ((CHANNEL) == TIM_CHANNEL_2))) \
lypinator 0:bb348c97df44 14270 || \
lypinator 0:bb348c97df44 14271 (((INSTANCE) == TIM13) && \
lypinator 0:bb348c97df44 14272 (((CHANNEL) == TIM_CHANNEL_1))) \
lypinator 0:bb348c97df44 14273 || \
lypinator 0:bb348c97df44 14274 (((INSTANCE) == TIM14) && \
lypinator 0:bb348c97df44 14275 (((CHANNEL) == TIM_CHANNEL_1))))
lypinator 0:bb348c97df44 14276
lypinator 0:bb348c97df44 14277 /************ TIM Instances : complementary output(s) available ***************/
lypinator 0:bb348c97df44 14278 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
lypinator 0:bb348c97df44 14279 ((((INSTANCE) == TIM1) && \
lypinator 0:bb348c97df44 14280 (((CHANNEL) == TIM_CHANNEL_1) || \
lypinator 0:bb348c97df44 14281 ((CHANNEL) == TIM_CHANNEL_2) || \
lypinator 0:bb348c97df44 14282 ((CHANNEL) == TIM_CHANNEL_3))) \
lypinator 0:bb348c97df44 14283 || \
lypinator 0:bb348c97df44 14284 (((INSTANCE) == TIM8) && \
lypinator 0:bb348c97df44 14285 (((CHANNEL) == TIM_CHANNEL_1) || \
lypinator 0:bb348c97df44 14286 ((CHANNEL) == TIM_CHANNEL_2) || \
lypinator 0:bb348c97df44 14287 ((CHANNEL) == TIM_CHANNEL_3))))
lypinator 0:bb348c97df44 14288
lypinator 0:bb348c97df44 14289 /****************** TIM Instances : supporting counting mode selection ********/
lypinator 0:bb348c97df44 14290 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
lypinator 0:bb348c97df44 14291 ((INSTANCE) == TIM2) || \
lypinator 0:bb348c97df44 14292 ((INSTANCE) == TIM3) || \
lypinator 0:bb348c97df44 14293 ((INSTANCE) == TIM4) || \
lypinator 0:bb348c97df44 14294 ((INSTANCE) == TIM5) || \
lypinator 0:bb348c97df44 14295 ((INSTANCE) == TIM8))
lypinator 0:bb348c97df44 14296
lypinator 0:bb348c97df44 14297 /****************** TIM Instances : supporting clock division *****************/
lypinator 0:bb348c97df44 14298 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
lypinator 0:bb348c97df44 14299 ((INSTANCE) == TIM2) || \
lypinator 0:bb348c97df44 14300 ((INSTANCE) == TIM3) || \
lypinator 0:bb348c97df44 14301 ((INSTANCE) == TIM4) || \
lypinator 0:bb348c97df44 14302 ((INSTANCE) == TIM5) || \
lypinator 0:bb348c97df44 14303 ((INSTANCE) == TIM8) || \
lypinator 0:bb348c97df44 14304 ((INSTANCE) == TIM9) || \
lypinator 0:bb348c97df44 14305 ((INSTANCE) == TIM10)|| \
lypinator 0:bb348c97df44 14306 ((INSTANCE) == TIM11)|| \
lypinator 0:bb348c97df44 14307 ((INSTANCE) == TIM12)|| \
lypinator 0:bb348c97df44 14308 ((INSTANCE) == TIM13)|| \
lypinator 0:bb348c97df44 14309 ((INSTANCE) == TIM14))
lypinator 0:bb348c97df44 14310
lypinator 0:bb348c97df44 14311 /****************** TIM Instances : supporting commutation event generation ***/
lypinator 0:bb348c97df44 14312 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)|| \
lypinator 0:bb348c97df44 14313 ((INSTANCE) == TIM8))
lypinator 0:bb348c97df44 14314
lypinator 0:bb348c97df44 14315
lypinator 0:bb348c97df44 14316 /****************** TIM Instances : supporting OCxREF clear *******************/
lypinator 0:bb348c97df44 14317 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
lypinator 0:bb348c97df44 14318 ((INSTANCE) == TIM2) || \
lypinator 0:bb348c97df44 14319 ((INSTANCE) == TIM3) || \
lypinator 0:bb348c97df44 14320 ((INSTANCE) == TIM4) || \
lypinator 0:bb348c97df44 14321 ((INSTANCE) == TIM5) || \
lypinator 0:bb348c97df44 14322 ((INSTANCE) == TIM8))
lypinator 0:bb348c97df44 14323
lypinator 0:bb348c97df44 14324 /****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
lypinator 0:bb348c97df44 14325 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
lypinator 0:bb348c97df44 14326 ((INSTANCE) == TIM2) || \
lypinator 0:bb348c97df44 14327 ((INSTANCE) == TIM3) || \
lypinator 0:bb348c97df44 14328 ((INSTANCE) == TIM4) || \
lypinator 0:bb348c97df44 14329 ((INSTANCE) == TIM5) || \
lypinator 0:bb348c97df44 14330 ((INSTANCE) == TIM8) || \
lypinator 0:bb348c97df44 14331 ((INSTANCE) == TIM9) || \
lypinator 0:bb348c97df44 14332 ((INSTANCE) == TIM12))
lypinator 0:bb348c97df44 14333
lypinator 0:bb348c97df44 14334 /****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
lypinator 0:bb348c97df44 14335 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
lypinator 0:bb348c97df44 14336 ((INSTANCE) == TIM2) || \
lypinator 0:bb348c97df44 14337 ((INSTANCE) == TIM3) || \
lypinator 0:bb348c97df44 14338 ((INSTANCE) == TIM4) || \
lypinator 0:bb348c97df44 14339 ((INSTANCE) == TIM5) || \
lypinator 0:bb348c97df44 14340 ((INSTANCE) == TIM8))
lypinator 0:bb348c97df44 14341
lypinator 0:bb348c97df44 14342 /****************** TIM Instances : supporting repetition counter *************/
lypinator 0:bb348c97df44 14343 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
lypinator 0:bb348c97df44 14344 ((INSTANCE) == TIM8))
lypinator 0:bb348c97df44 14345
lypinator 0:bb348c97df44 14346 /****************** TIM Instances : supporting encoder interface **************/
lypinator 0:bb348c97df44 14347 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
lypinator 0:bb348c97df44 14348 ((INSTANCE) == TIM2) || \
lypinator 0:bb348c97df44 14349 ((INSTANCE) == TIM3) || \
lypinator 0:bb348c97df44 14350 ((INSTANCE) == TIM4) || \
lypinator 0:bb348c97df44 14351 ((INSTANCE) == TIM5) || \
lypinator 0:bb348c97df44 14352 ((INSTANCE) == TIM8) || \
lypinator 0:bb348c97df44 14353 ((INSTANCE) == TIM9) || \
lypinator 0:bb348c97df44 14354 ((INSTANCE) == TIM12))
lypinator 0:bb348c97df44 14355 /****************** TIM Instances : supporting Hall sensor interface **********/
lypinator 0:bb348c97df44 14356 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
lypinator 0:bb348c97df44 14357 ((INSTANCE) == TIM2) || \
lypinator 0:bb348c97df44 14358 ((INSTANCE) == TIM3) || \
lypinator 0:bb348c97df44 14359 ((INSTANCE) == TIM4) || \
lypinator 0:bb348c97df44 14360 ((INSTANCE) == TIM5) || \
lypinator 0:bb348c97df44 14361 ((INSTANCE) == TIM8))
lypinator 0:bb348c97df44 14362 /****************** TIM Instances : supporting the break function *************/
lypinator 0:bb348c97df44 14363 #define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
lypinator 0:bb348c97df44 14364 ((INSTANCE) == TIM8))
lypinator 0:bb348c97df44 14365
lypinator 0:bb348c97df44 14366 /******************** USART Instances : Synchronous mode **********************/
lypinator 0:bb348c97df44 14367 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
lypinator 0:bb348c97df44 14368 ((INSTANCE) == USART2) || \
lypinator 0:bb348c97df44 14369 ((INSTANCE) == USART3) || \
lypinator 0:bb348c97df44 14370 ((INSTANCE) == USART6))
lypinator 0:bb348c97df44 14371
lypinator 0:bb348c97df44 14372 /******************** UART Instances : Half-Duplex mode **********************/
lypinator 0:bb348c97df44 14373 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
lypinator 0:bb348c97df44 14374 ((INSTANCE) == USART2) || \
lypinator 0:bb348c97df44 14375 ((INSTANCE) == USART3) || \
lypinator 0:bb348c97df44 14376 ((INSTANCE) == USART6))
lypinator 0:bb348c97df44 14377
lypinator 0:bb348c97df44 14378 /* Legacy defines */
lypinator 0:bb348c97df44 14379 #define IS_UART_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
lypinator 0:bb348c97df44 14380
lypinator 0:bb348c97df44 14381 /****************** UART Instances : Hardware Flow control ********************/
lypinator 0:bb348c97df44 14382 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
lypinator 0:bb348c97df44 14383 ((INSTANCE) == USART2) || \
lypinator 0:bb348c97df44 14384 ((INSTANCE) == USART3) || \
lypinator 0:bb348c97df44 14385 ((INSTANCE) == USART6))
lypinator 0:bb348c97df44 14386 /******************** UART Instances : LIN mode **********************/
lypinator 0:bb348c97df44 14387 #define IS_UART_LIN_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
lypinator 0:bb348c97df44 14388
lypinator 0:bb348c97df44 14389 /********************* UART Instances : Smart card mode ***********************/
lypinator 0:bb348c97df44 14390 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
lypinator 0:bb348c97df44 14391 ((INSTANCE) == USART2) || \
lypinator 0:bb348c97df44 14392 ((INSTANCE) == USART3) || \
lypinator 0:bb348c97df44 14393 ((INSTANCE) == USART6))
lypinator 0:bb348c97df44 14394
lypinator 0:bb348c97df44 14395 /*********************** UART Instances : IRDA mode ***************************/
lypinator 0:bb348c97df44 14396 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
lypinator 0:bb348c97df44 14397 ((INSTANCE) == USART2) || \
lypinator 0:bb348c97df44 14398 ((INSTANCE) == USART3) || \
lypinator 0:bb348c97df44 14399 ((INSTANCE) == USART6))
lypinator 0:bb348c97df44 14400
lypinator 0:bb348c97df44 14401 /*********************** PCD Instances ****************************************/
lypinator 0:bb348c97df44 14402 #define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))
lypinator 0:bb348c97df44 14403
lypinator 0:bb348c97df44 14404 /*********************** HCD Instances ****************************************/
lypinator 0:bb348c97df44 14405 #define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))
lypinator 0:bb348c97df44 14406
lypinator 0:bb348c97df44 14407 /****************************** SDIO Instances ********************************/
lypinator 0:bb348c97df44 14408 #define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
lypinator 0:bb348c97df44 14409
lypinator 0:bb348c97df44 14410 /****************************** IWDG Instances ********************************/
lypinator 0:bb348c97df44 14411 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
lypinator 0:bb348c97df44 14412
lypinator 0:bb348c97df44 14413 /****************************** WWDG Instances ********************************/
lypinator 0:bb348c97df44 14414 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
lypinator 0:bb348c97df44 14415
lypinator 0:bb348c97df44 14416
lypinator 0:bb348c97df44 14417 /***************************** FMPI2C Instances *******************************/
lypinator 0:bb348c97df44 14418 #define IS_FMPI2C_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FMPI2C1)
lypinator 0:bb348c97df44 14419
lypinator 0:bb348c97df44 14420 /****************************** QSPI Instances ********************************/
lypinator 0:bb348c97df44 14421 #define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)
lypinator 0:bb348c97df44 14422 /****************************** USB Instances ********************************/
lypinator 0:bb348c97df44 14423 #define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_FS)
lypinator 0:bb348c97df44 14424 /****************************** USB Exported Constants ************************/
lypinator 0:bb348c97df44 14425 #define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 12U
lypinator 0:bb348c97df44 14426 #define USB_OTG_FS_MAX_IN_ENDPOINTS 6U /* Including EP0 */
lypinator 0:bb348c97df44 14427 #define USB_OTG_FS_MAX_OUT_ENDPOINTS 6U /* Including EP0 */
lypinator 0:bb348c97df44 14428 #define USB_OTG_FS_TOTAL_FIFO_SIZE 1280U /* in Bytes */
lypinator 0:bb348c97df44 14429
lypinator 0:bb348c97df44 14430 /*
lypinator 0:bb348c97df44 14431 * @brief Specific devices reset values definitions
lypinator 0:bb348c97df44 14432 */
lypinator 0:bb348c97df44 14433 #define RCC_PLLCFGR_RST_VALUE 0x24003010U
lypinator 0:bb348c97df44 14434 #define RCC_PLLI2SCFGR_RST_VALUE 0x24003010U
lypinator 0:bb348c97df44 14435
lypinator 0:bb348c97df44 14436 #define RCC_MAX_FREQUENCY 100000000U /*!< Max frequency of family in Hz*/
lypinator 0:bb348c97df44 14437 #define RCC_MAX_FREQUENCY_SCALE1 RCC_MAX_FREQUENCY /*!< Maximum frequency for system clock at power scale1, in Hz */
lypinator 0:bb348c97df44 14438 #define RCC_MAX_FREQUENCY_SCALE2 84000000U /*!< Maximum frequency for system clock at power scale2, in Hz */
lypinator 0:bb348c97df44 14439 #define RCC_MAX_FREQUENCY_SCALE3 64000000U /*!< Maximum frequency for system clock at power scale3, in Hz */
lypinator 0:bb348c97df44 14440 #define RCC_PLLVCO_OUTPUT_MIN 100000000U /*!< Frequency min for PLLVCO output, in Hz */
lypinator 0:bb348c97df44 14441 #define RCC_PLLVCO_INPUT_MIN 950000U /*!< Frequency min for PLLVCO input, in Hz */
lypinator 0:bb348c97df44 14442 #define RCC_PLLVCO_INPUT_MAX 2100000U /*!< Frequency max for PLLVCO input, in Hz */
lypinator 0:bb348c97df44 14443 #define RCC_PLLVCO_OUTPUT_MAX 432000000U /*!< Frequency max for PLLVCO output, in Hz */
lypinator 0:bb348c97df44 14444
lypinator 0:bb348c97df44 14445 #define RCC_PLLN_MIN_VALUE 50U
lypinator 0:bb348c97df44 14446 #define RCC_PLLN_MAX_VALUE 432U
lypinator 0:bb348c97df44 14447
lypinator 0:bb348c97df44 14448 #define FLASH_SCALE1_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */
lypinator 0:bb348c97df44 14449 #define FLASH_SCALE1_LATENCY2_FREQ 64000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */
lypinator 0:bb348c97df44 14450 #define FLASH_SCALE1_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 1 */
lypinator 0:bb348c97df44 14451
lypinator 0:bb348c97df44 14452 #define FLASH_SCALE2_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */
lypinator 0:bb348c97df44 14453 #define FLASH_SCALE2_LATENCY2_FREQ 64000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */
lypinator 0:bb348c97df44 14454
lypinator 0:bb348c97df44 14455 #define FLASH_SCALE3_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 3 */
lypinator 0:bb348c97df44 14456 #define FLASH_SCALE3_LATENCY2_FREQ 64000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 3 */
lypinator 0:bb348c97df44 14457
lypinator 0:bb348c97df44 14458 /******************************************************************************/
lypinator 0:bb348c97df44 14459 /* For a painless codes migration between the STM32F4xx device product */
lypinator 0:bb348c97df44 14460 /* lines, the aliases defined below are put in place to overcome the */
lypinator 0:bb348c97df44 14461 /* differences in the interrupt handlers and IRQn definitions. */
lypinator 0:bb348c97df44 14462 /* No need to update developed interrupt code when moving across */
lypinator 0:bb348c97df44 14463 /* product lines within the same STM32F4 Family */
lypinator 0:bb348c97df44 14464 /******************************************************************************/
lypinator 0:bb348c97df44 14465 /* Aliases for __IRQn */
lypinator 0:bb348c97df44 14466 #define FMC_IRQn FSMC_IRQn
lypinator 0:bb348c97df44 14467
lypinator 0:bb348c97df44 14468 /* Aliases for __IRQHandler */
lypinator 0:bb348c97df44 14469 #define FMC_IRQHandler FSMC_IRQHandler
lypinator 0:bb348c97df44 14470
lypinator 0:bb348c97df44 14471 /**
lypinator 0:bb348c97df44 14472 * @}
lypinator 0:bb348c97df44 14473 */
lypinator 0:bb348c97df44 14474
lypinator 0:bb348c97df44 14475 /**
lypinator 0:bb348c97df44 14476 * @}
lypinator 0:bb348c97df44 14477 */
lypinator 0:bb348c97df44 14478
lypinator 0:bb348c97df44 14479 /**
lypinator 0:bb348c97df44 14480 * @}
lypinator 0:bb348c97df44 14481 */
lypinator 0:bb348c97df44 14482
lypinator 0:bb348c97df44 14483 #ifdef __cplusplus
lypinator 0:bb348c97df44 14484 }
lypinator 0:bb348c97df44 14485 #endif /* __cplusplus */
lypinator 0:bb348c97df44 14486
lypinator 0:bb348c97df44 14487 #endif /* __STM32F412Zx_H */
lypinator 0:bb348c97df44 14488
lypinator 0:bb348c97df44 14489
lypinator 0:bb348c97df44 14490
lypinator 0:bb348c97df44 14491 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/