Thomas Lyp / DevLibMemoryController

Initial commit

Dependencies:   FastPWM

mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_NUCLEO_F411RE/system_clock.c@0:bb348c97df44, 2020-09-16 (annotated)

Committer:
lypinator
Date:
Wed Sep 16 01:11:49 2020 +0000
Revision:
0:bb348c97df44
Added PWM

Who changed what in which revision?

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lypinator 0:bb348c97df44 1 /* mbed Microcontroller Library
lypinator 0:bb348c97df44 2 * Copyright (c) 2006-2017 ARM Limited
lypinator 0:bb348c97df44 3 *
lypinator 0:bb348c97df44 4 * Licensed under the Apache License, Version 2.0 (the "License");
lypinator 0:bb348c97df44 5 * you may not use this file except in compliance with the License.
lypinator 0:bb348c97df44 6 * You may obtain a copy of the License at
lypinator 0:bb348c97df44 7 *
lypinator 0:bb348c97df44 8 * http://www.apache.org/licenses/LICENSE-2.0
lypinator 0:bb348c97df44 9 *
lypinator 0:bb348c97df44 10 * Unless required by applicable law or agreed to in writing, software
lypinator 0:bb348c97df44 11 * distributed under the License is distributed on an "AS IS" BASIS,
lypinator 0:bb348c97df44 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
lypinator 0:bb348c97df44 13 * See the License for the specific language governing permissions and
lypinator 0:bb348c97df44 14 * limitations under the License.
lypinator 0:bb348c97df44 15 */
lypinator 0:bb348c97df44 16
lypinator 0:bb348c97df44 17 /**
lypinator 0:bb348c97df44 18 * This file configures the system clock as follows:
lypinator 0:bb348c97df44 19 *-----------------------------------------------------------------------------
lypinator 0:bb348c97df44 20 * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock) | CLOCK_SOURCE_USB=1
lypinator 0:bb348c97df44 21 * | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal) |
lypinator 0:bb348c97df44 22 * | 3- USE_PLL_HSI (internal 16 MHz) |
lypinator 0:bb348c97df44 23 *-----------------------------------------------------------------------------
lypinator 0:bb348c97df44 24 * SYSCLK(MHz) | 100 | 96
lypinator 0:bb348c97df44 25 * AHBCLK (MHz) | 100 | 96
lypinator 0:bb348c97df44 26 * APB1CLK (MHz) | 50 | 48
lypinator 0:bb348c97df44 27 * APB2CLK (MHz) | 100 | 96
lypinator 0:bb348c97df44 28 * USB capable | NO | YES
lypinator 0:bb348c97df44 29 *-----------------------------------------------------------------------------
lypinator 0:bb348c97df44 30 **/
lypinator 0:bb348c97df44 31
lypinator 0:bb348c97df44 32 #include "stm32f4xx.h"
lypinator 0:bb348c97df44 33 #include "mbed_error.h"
lypinator 0:bb348c97df44 34
lypinator 0:bb348c97df44 35 // clock source is selected with CLOCK_SOURCE in json config
lypinator 0:bb348c97df44 36 #define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO)
lypinator 0:bb348c97df44 37 #define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default)
lypinator 0:bb348c97df44 38 #define USE_PLL_HSI 0x2 // Use HSI internal clock
lypinator 0:bb348c97df44 39
lypinator 0:bb348c97df44 40 #if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
lypinator 0:bb348c97df44 41 uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
lypinator 0:bb348c97df44 42 #endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
lypinator 0:bb348c97df44 43
lypinator 0:bb348c97df44 44 #if ((CLOCK_SOURCE) & USE_PLL_HSI)
lypinator 0:bb348c97df44 45 uint8_t SetSysClock_PLL_HSI(void);
lypinator 0:bb348c97df44 46 #endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
lypinator 0:bb348c97df44 47
lypinator 0:bb348c97df44 48
lypinator 0:bb348c97df44 49 /**
lypinator 0:bb348c97df44 50 * @brief Setup the microcontroller system
lypinator 0:bb348c97df44 51 * Initialize the FPU setting, vector table location and External memory
lypinator 0:bb348c97df44 52 * configuration.
lypinator 0:bb348c97df44 53 * @param None
lypinator 0:bb348c97df44 54 * @retval None
lypinator 0:bb348c97df44 55 */
lypinator 0:bb348c97df44 56 void SystemInit(void)
lypinator 0:bb348c97df44 57 {
lypinator 0:bb348c97df44 58 /* FPU settings ------------------------------------------------------------*/
lypinator 0:bb348c97df44 59 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
lypinator 0:bb348c97df44 60 SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */
lypinator 0:bb348c97df44 61 #endif
lypinator 0:bb348c97df44 62 /* Reset the RCC clock configuration to the default reset state ------------*/
lypinator 0:bb348c97df44 63 /* Set HSION bit */
lypinator 0:bb348c97df44 64 RCC->CR |= (uint32_t)0x00000001;
lypinator 0:bb348c97df44 65
lypinator 0:bb348c97df44 66 /* Reset CFGR register */
lypinator 0:bb348c97df44 67 RCC->CFGR = 0x00000000;
lypinator 0:bb348c97df44 68
lypinator 0:bb348c97df44 69 /* Reset HSEON, CSSON and PLLON bits */
lypinator 0:bb348c97df44 70 RCC->CR &= (uint32_t)0xFEF6FFFF;
lypinator 0:bb348c97df44 71
lypinator 0:bb348c97df44 72 /* Reset PLLCFGR register */
lypinator 0:bb348c97df44 73 RCC->PLLCFGR = 0x24003010;
lypinator 0:bb348c97df44 74
lypinator 0:bb348c97df44 75 /* Reset HSEBYP bit */
lypinator 0:bb348c97df44 76 RCC->CR &= (uint32_t)0xFFFBFFFF;
lypinator 0:bb348c97df44 77
lypinator 0:bb348c97df44 78 /* Disable all interrupts */
lypinator 0:bb348c97df44 79 RCC->CIR = 0x00000000;
lypinator 0:bb348c97df44 80
lypinator 0:bb348c97df44 81 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
lypinator 0:bb348c97df44 82 SystemInit_ExtMemCtl();
lypinator 0:bb348c97df44 83 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
lypinator 0:bb348c97df44 84 }
lypinator 0:bb348c97df44 85
lypinator 0:bb348c97df44 86
lypinator 0:bb348c97df44 87 /**
lypinator 0:bb348c97df44 88 * @brief Configures the System clock source, PLL Multiplier and Divider factors,
lypinator 0:bb348c97df44 89 * AHB/APBx prescalers and Flash settings
lypinator 0:bb348c97df44 90 * @note This function should be called only once the RCC clock configuration
lypinator 0:bb348c97df44 91 * is reset to the default reset state (done in SystemInit() function).
lypinator 0:bb348c97df44 92 * @param None
lypinator 0:bb348c97df44 93 * @retval None
lypinator 0:bb348c97df44 94 */
lypinator 0:bb348c97df44 95
lypinator 0:bb348c97df44 96 void SetSysClock(void)
lypinator 0:bb348c97df44 97 {
lypinator 0:bb348c97df44 98 #if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
lypinator 0:bb348c97df44 99 /* 1- Try to start with HSE and external clock */
lypinator 0:bb348c97df44 100 if (SetSysClock_PLL_HSE(1) == 0)
lypinator 0:bb348c97df44 101 #endif
lypinator 0:bb348c97df44 102 {
lypinator 0:bb348c97df44 103 #if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
lypinator 0:bb348c97df44 104 /* 2- If fail try to start with HSE and external xtal */
lypinator 0:bb348c97df44 105 if (SetSysClock_PLL_HSE(0) == 0)
lypinator 0:bb348c97df44 106 #endif
lypinator 0:bb348c97df44 107 {
lypinator 0:bb348c97df44 108 #if ((CLOCK_SOURCE) & USE_PLL_HSI)
lypinator 0:bb348c97df44 109 /* 3- If fail start with HSI clock */
lypinator 0:bb348c97df44 110 if (SetSysClock_PLL_HSI() == 0)
lypinator 0:bb348c97df44 111 #endif
lypinator 0:bb348c97df44 112 {
lypinator 0:bb348c97df44 113 {
lypinator 0:bb348c97df44 114 error("SetSysClock failed\n");
lypinator 0:bb348c97df44 115 }
lypinator 0:bb348c97df44 116 }
lypinator 0:bb348c97df44 117 }
lypinator 0:bb348c97df44 118 }
lypinator 0:bb348c97df44 119
lypinator 0:bb348c97df44 120 /* Output clock on MCO2 pin(PC9) for debugging purpose */
lypinator 0:bb348c97df44 121 //HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_4);
lypinator 0:bb348c97df44 122 }
lypinator 0:bb348c97df44 123
lypinator 0:bb348c97df44 124 #if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
lypinator 0:bb348c97df44 125 /******************************************************************************/
lypinator 0:bb348c97df44 126 /* PLL (clocked by HSE) used as System clock source */
lypinator 0:bb348c97df44 127 /******************************************************************************/
lypinator 0:bb348c97df44 128 uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
lypinator 0:bb348c97df44 129 {
lypinator 0:bb348c97df44 130 RCC_OscInitTypeDef RCC_OscInitStruct;
lypinator 0:bb348c97df44 131 RCC_ClkInitTypeDef RCC_ClkInitStruct;
lypinator 0:bb348c97df44 132
lypinator 0:bb348c97df44 133 /* The voltage scaling allows optimizing the power consumption when the device is
lypinator 0:bb348c97df44 134 clocked below the maximum system frequency, to update the voltage scaling value
lypinator 0:bb348c97df44 135 regarding system frequency refer to product datasheet. */
lypinator 0:bb348c97df44 136 __HAL_RCC_PWR_CLK_ENABLE();
lypinator 0:bb348c97df44 137 __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
lypinator 0:bb348c97df44 138
lypinator 0:bb348c97df44 139 // Enable HSE oscillator and activate PLL with HSE as source
lypinator 0:bb348c97df44 140 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
lypinator 0:bb348c97df44 141 if (bypass == 0) {
lypinator 0:bb348c97df44 142 RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
lypinator 0:bb348c97df44 143 } else {
lypinator 0:bb348c97df44 144 RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN
lypinator 0:bb348c97df44 145 }
lypinator 0:bb348c97df44 146
lypinator 0:bb348c97df44 147 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
lypinator 0:bb348c97df44 148 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
lypinator 0:bb348c97df44 149 RCC_OscInitStruct.PLL.PLLM = 4; // VCO input clock = 2 MHz (8 MHz / 4)
lypinator 0:bb348c97df44 150 #if (CLOCK_SOURCE_USB)
lypinator 0:bb348c97df44 151 RCC_OscInitStruct.PLL.PLLN = 192; // VCO output clock = 384 MHz (2 MHz * 192)
lypinator 0:bb348c97df44 152 #else /* CLOCK_SOURCE_USB */
lypinator 0:bb348c97df44 153 RCC_OscInitStruct.PLL.PLLN = 200; // VCO output clock = 400 MHz (2 MHz * 200)
lypinator 0:bb348c97df44 154 #endif /* CLOCK_SOURCE_USB */
lypinator 0:bb348c97df44 155 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; // PLLCLK = 100 MHz or 96 MHz (depending on CLOCK_SOURCE_USB)
lypinator 0:bb348c97df44 156 RCC_OscInitStruct.PLL.PLLQ = 8; // USB clock = 48 MHz (CLOCK_SOURCE_USB=1)
lypinator 0:bb348c97df44 157 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
lypinator 0:bb348c97df44 158 return 0; // FAIL
lypinator 0:bb348c97df44 159 }
lypinator 0:bb348c97df44 160
lypinator 0:bb348c97df44 161 // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
lypinator 0:bb348c97df44 162 RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
lypinator 0:bb348c97df44 163 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 100/96 MHz
lypinator 0:bb348c97df44 164 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 100/96 MHz
lypinator 0:bb348c97df44 165 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 50/48 MHz
lypinator 0:bb348c97df44 166 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 100/96 MHz
lypinator 0:bb348c97df44 167 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) {
lypinator 0:bb348c97df44 168 return 0; // FAIL
lypinator 0:bb348c97df44 169 }
lypinator 0:bb348c97df44 170
lypinator 0:bb348c97df44 171 /* Output clock on MCO1 pin(PA8) for debugging purpose */
lypinator 0:bb348c97df44 172 //if (bypass == 0)
lypinator 0:bb348c97df44 173 // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz with xtal
lypinator 0:bb348c97df44 174 //else
lypinator 0:bb348c97df44 175 // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz with external clock
lypinator 0:bb348c97df44 176
lypinator 0:bb348c97df44 177 return 1; // OK
lypinator 0:bb348c97df44 178 }
lypinator 0:bb348c97df44 179 #endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
lypinator 0:bb348c97df44 180
lypinator 0:bb348c97df44 181 #if ((CLOCK_SOURCE) & USE_PLL_HSI)
lypinator 0:bb348c97df44 182 /******************************************************************************/
lypinator 0:bb348c97df44 183 /* PLL (clocked by HSI) used as System clock source */
lypinator 0:bb348c97df44 184 /******************************************************************************/
lypinator 0:bb348c97df44 185 uint8_t SetSysClock_PLL_HSI(void)
lypinator 0:bb348c97df44 186 {
lypinator 0:bb348c97df44 187 RCC_OscInitTypeDef RCC_OscInitStruct;
lypinator 0:bb348c97df44 188 RCC_ClkInitTypeDef RCC_ClkInitStruct;
lypinator 0:bb348c97df44 189
lypinator 0:bb348c97df44 190 /* The voltage scaling allows optimizing the power consumption when the device is
lypinator 0:bb348c97df44 191 clocked below the maximum system frequency, to update the voltage scaling value
lypinator 0:bb348c97df44 192 regarding system frequency refer to product datasheet. */
lypinator 0:bb348c97df44 193 __HAL_RCC_PWR_CLK_ENABLE();
lypinator 0:bb348c97df44 194 __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
lypinator 0:bb348c97df44 195
lypinator 0:bb348c97df44 196 // Enable HSI oscillator and activate PLL with HSI as source
lypinator 0:bb348c97df44 197 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
lypinator 0:bb348c97df44 198 RCC_OscInitStruct.HSIState = RCC_HSI_ON;
lypinator 0:bb348c97df44 199 RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
lypinator 0:bb348c97df44 200 RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
lypinator 0:bb348c97df44 201 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
lypinator 0:bb348c97df44 202 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
lypinator 0:bb348c97df44 203 RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 2 MHz (16 MHz / 8)
lypinator 0:bb348c97df44 204 #if (CLOCK_SOURCE_USB)
lypinator 0:bb348c97df44 205 RCC_OscInitStruct.PLL.PLLN = 192; // VCO output clock = 384 MHz (2 MHz * 192)
lypinator 0:bb348c97df44 206 #else /* CLOCK_SOURCE_USB */
lypinator 0:bb348c97df44 207 RCC_OscInitStruct.PLL.PLLN = 200; // VCO output clock = 400 MHz (2 MHz * 200)
lypinator 0:bb348c97df44 208 #endif /* CLOCK_SOURCE_USB */
lypinator 0:bb348c97df44 209 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; // PLLCLK = 100 MHz or 96 MHz (depending on CLOCK_SOURCE_USB)
lypinator 0:bb348c97df44 210 RCC_OscInitStruct.PLL.PLLQ = 8; // USB clock = 48 MHz (CLOCK_SOURCE_USB=1)
lypinator 0:bb348c97df44 211 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
lypinator 0:bb348c97df44 212 return 0; // FAIL
lypinator 0:bb348c97df44 213 }
lypinator 0:bb348c97df44 214
lypinator 0:bb348c97df44 215 /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
lypinator 0:bb348c97df44 216 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
lypinator 0:bb348c97df44 217 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
lypinator 0:bb348c97df44 218 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
lypinator 0:bb348c97df44 219 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
lypinator 0:bb348c97df44 220 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
lypinator 0:bb348c97df44 221 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) {
lypinator 0:bb348c97df44 222 return 0; // FAIL
lypinator 0:bb348c97df44 223 }
lypinator 0:bb348c97df44 224
lypinator 0:bb348c97df44 225 /* Output clock on MCO1 pin(PA8) for debugging purpose */
lypinator 0:bb348c97df44 226 //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
lypinator 0:bb348c97df44 227
lypinator 0:bb348c97df44 228 return 1; // OK
lypinator 0:bb348c97df44 229 }
lypinator 0:bb348c97df44 230 #endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */