Thomas Lyp / DevLibMemoryController

Initial commit

Dependencies:   FastPWM

mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_ELMO_F411RE/system_clock.c@0:bb348c97df44, 2020-09-16 (annotated)

Committer:
lypinator
Date:
Wed Sep 16 01:11:49 2020 +0000
Revision:
0:bb348c97df44
Added PWM

Who changed what in which revision?

UserRevisionLine numberNew contents of line
lypinator 0:bb348c97df44 1 /* mbed Microcontroller Library
lypinator 0:bb348c97df44 2 * Copyright (c) 2006-2017 ARM Limited
lypinator 0:bb348c97df44 3 *
lypinator 0:bb348c97df44 4 * Licensed under the Apache License, Version 2.0 (the "License");
lypinator 0:bb348c97df44 5 * you may not use this file except in compliance with the License.
lypinator 0:bb348c97df44 6 * You may obtain a copy of the License at
lypinator 0:bb348c97df44 7 *
lypinator 0:bb348c97df44 8 * http://www.apache.org/licenses/LICENSE-2.0
lypinator 0:bb348c97df44 9 *
lypinator 0:bb348c97df44 10 * Unless required by applicable law or agreed to in writing, software
lypinator 0:bb348c97df44 11 * distributed under the License is distributed on an "AS IS" BASIS,
lypinator 0:bb348c97df44 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
lypinator 0:bb348c97df44 13 * See the License for the specific language governing permissions and
lypinator 0:bb348c97df44 14 * limitations under the License.
lypinator 0:bb348c97df44 15 */
lypinator 0:bb348c97df44 16
lypinator 0:bb348c97df44 17 /**
lypinator 0:bb348c97df44 18 * This file configures the system clock as follows:
lypinator 0:bb348c97df44 19 *-----------------------------------------------------------------------------
lypinator 0:bb348c97df44 20 * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI
lypinator 0:bb348c97df44 21 * | (external 8 MHz clock) | (internal 16 MHz)
lypinator 0:bb348c97df44 22 * | 2- PLL_HSE_XTAL |
lypinator 0:bb348c97df44 23 * | (external 8 MHz xtal) |
lypinator 0:bb348c97df44 24 *-----------------------------------------------------------------------------
lypinator 0:bb348c97df44 25 * SYSCLK(MHz) | 96 | 96
lypinator 0:bb348c97df44 26 *-----------------------------------------------------------------------------
lypinator 0:bb348c97df44 27 * AHBCLK (MHz) | 96 | 96
lypinator 0:bb348c97df44 28 *-----------------------------------------------------------------------------
lypinator 0:bb348c97df44 29 * APB1CLK (MHz) | 48 | 48
lypinator 0:bb348c97df44 30 *-----------------------------------------------------------------------------
lypinator 0:bb348c97df44 31 * APB2CLK (MHz) | 96 | 96
lypinator 0:bb348c97df44 32 *-----------------------------------------------------------------------------
lypinator 0:bb348c97df44 33 * USB capable (48 MHz precise clock) | YES | YES
lypinator 0:bb348c97df44 34 *-----------------------------------------------------------------------------
lypinator 0:bb348c97df44 35 **/
lypinator 0:bb348c97df44 36
lypinator 0:bb348c97df44 37 #include "stm32f4xx.h"
lypinator 0:bb348c97df44 38
lypinator 0:bb348c97df44 39
lypinator 0:bb348c97df44 40 /*!< Uncomment the following line if you need to relocate your vector Table in
lypinator 0:bb348c97df44 41 Internal SRAM. */
lypinator 0:bb348c97df44 42 /* #define VECT_TAB_SRAM */
lypinator 0:bb348c97df44 43 #define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
lypinator 0:bb348c97df44 44 This value must be a multiple of 0x200. */
lypinator 0:bb348c97df44 45
lypinator 0:bb348c97df44 46
lypinator 0:bb348c97df44 47 /* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
lypinator 0:bb348c97df44 48 #define USE_PLL_HSE_EXTC (0) /* Use external clock */
lypinator 0:bb348c97df44 49 #define USE_PLL_HSE_XTAL (1) /* Use external xtal */
lypinator 0:bb348c97df44 50
lypinator 0:bb348c97df44 51
lypinator 0:bb348c97df44 52 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
lypinator 0:bb348c97df44 53 uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
lypinator 0:bb348c97df44 54 #endif
lypinator 0:bb348c97df44 55
lypinator 0:bb348c97df44 56 uint8_t SetSysClock_PLL_HSI(void);
lypinator 0:bb348c97df44 57
lypinator 0:bb348c97df44 58
lypinator 0:bb348c97df44 59 /**
lypinator 0:bb348c97df44 60 * @brief Setup the microcontroller system
lypinator 0:bb348c97df44 61 * Initialize the FPU setting, vector table location and External memory
lypinator 0:bb348c97df44 62 * configuration.
lypinator 0:bb348c97df44 63 * @param None
lypinator 0:bb348c97df44 64 * @retval None
lypinator 0:bb348c97df44 65 */
lypinator 0:bb348c97df44 66 void SystemInit(void)
lypinator 0:bb348c97df44 67 {
lypinator 0:bb348c97df44 68 /* FPU settings ------------------------------------------------------------*/
lypinator 0:bb348c97df44 69 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
lypinator 0:bb348c97df44 70 SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */
lypinator 0:bb348c97df44 71 #endif
lypinator 0:bb348c97df44 72 /* Reset the RCC clock configuration to the default reset state ------------*/
lypinator 0:bb348c97df44 73 /* Set HSION bit */
lypinator 0:bb348c97df44 74 RCC->CR |= (uint32_t)0x00000001;
lypinator 0:bb348c97df44 75
lypinator 0:bb348c97df44 76 /* Reset CFGR register */
lypinator 0:bb348c97df44 77 RCC->CFGR = 0x00000000;
lypinator 0:bb348c97df44 78
lypinator 0:bb348c97df44 79 /* Reset HSEON, CSSON and PLLON bits */
lypinator 0:bb348c97df44 80 RCC->CR &= (uint32_t)0xFEF6FFFF;
lypinator 0:bb348c97df44 81
lypinator 0:bb348c97df44 82 /* Reset PLLCFGR register */
lypinator 0:bb348c97df44 83 RCC->PLLCFGR = 0x24003010;
lypinator 0:bb348c97df44 84
lypinator 0:bb348c97df44 85 /* Reset HSEBYP bit */
lypinator 0:bb348c97df44 86 RCC->CR &= (uint32_t)0xFFFBFFFF;
lypinator 0:bb348c97df44 87
lypinator 0:bb348c97df44 88 /* Disable all interrupts */
lypinator 0:bb348c97df44 89 RCC->CIR = 0x00000000;
lypinator 0:bb348c97df44 90
lypinator 0:bb348c97df44 91 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
lypinator 0:bb348c97df44 92 SystemInit_ExtMemCtl();
lypinator 0:bb348c97df44 93 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
lypinator 0:bb348c97df44 94
lypinator 0:bb348c97df44 95 /* Configure the Vector Table location add offset address ------------------*/
lypinator 0:bb348c97df44 96 #ifdef VECT_TAB_SRAM
lypinator 0:bb348c97df44 97 SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
lypinator 0:bb348c97df44 98 #else
lypinator 0:bb348c97df44 99 SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
lypinator 0:bb348c97df44 100 #endif
lypinator 0:bb348c97df44 101
lypinator 0:bb348c97df44 102 }
lypinator 0:bb348c97df44 103
lypinator 0:bb348c97df44 104
lypinator 0:bb348c97df44 105 /**
lypinator 0:bb348c97df44 106 * @brief Configures the System clock source, PLL Multiplier and Divider factors,
lypinator 0:bb348c97df44 107 * AHB/APBx prescalers and Flash settings
lypinator 0:bb348c97df44 108 * @note This function should be called only once the RCC clock configuration
lypinator 0:bb348c97df44 109 * is reset to the default reset state (done in SystemInit() function).
lypinator 0:bb348c97df44 110 * @param None
lypinator 0:bb348c97df44 111 * @retval None
lypinator 0:bb348c97df44 112 */
lypinator 0:bb348c97df44 113 void SetSysClock(void)
lypinator 0:bb348c97df44 114 {
lypinator 0:bb348c97df44 115 /* 1- Try to start with HSE and external clock */
lypinator 0:bb348c97df44 116 #if USE_PLL_HSE_EXTC != 0
lypinator 0:bb348c97df44 117 if (SetSysClock_PLL_HSE(1) == 0)
lypinator 0:bb348c97df44 118 #endif
lypinator 0:bb348c97df44 119 {
lypinator 0:bb348c97df44 120 /* 2- If fail try to start with HSE and external xtal */
lypinator 0:bb348c97df44 121 #if USE_PLL_HSE_XTAL != 0
lypinator 0:bb348c97df44 122 if (SetSysClock_PLL_HSE(0) == 0)
lypinator 0:bb348c97df44 123 #endif
lypinator 0:bb348c97df44 124 {
lypinator 0:bb348c97df44 125 /* 3- If fail start with HSI clock */
lypinator 0:bb348c97df44 126 if (SetSysClock_PLL_HSI() == 0) {
lypinator 0:bb348c97df44 127 while (1) {
lypinator 0:bb348c97df44 128 // [TODO] Put something here to tell the user that a problem occured...
lypinator 0:bb348c97df44 129 }
lypinator 0:bb348c97df44 130 }
lypinator 0:bb348c97df44 131 }
lypinator 0:bb348c97df44 132 }
lypinator 0:bb348c97df44 133
lypinator 0:bb348c97df44 134 /* Output clock on MCO2 pin(PC9) for debugging purpose */
lypinator 0:bb348c97df44 135 //HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_4); // 100 MHz / 4 = 25 MHz
lypinator 0:bb348c97df44 136 }
lypinator 0:bb348c97df44 137
lypinator 0:bb348c97df44 138 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
lypinator 0:bb348c97df44 139 /******************************************************************************/
lypinator 0:bb348c97df44 140 /* PLL (clocked by HSE) used as System clock source */
lypinator 0:bb348c97df44 141 /******************************************************************************/
lypinator 0:bb348c97df44 142 uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
lypinator 0:bb348c97df44 143 {
lypinator 0:bb348c97df44 144 RCC_ClkInitTypeDef RCC_ClkInitStruct;
lypinator 0:bb348c97df44 145 RCC_OscInitTypeDef RCC_OscInitStruct;
lypinator 0:bb348c97df44 146
lypinator 0:bb348c97df44 147 /* The voltage scaling allows optimizing the power consumption when the device is
lypinator 0:bb348c97df44 148 clocked below the maximum system frequency, to update the voltage scaling value
lypinator 0:bb348c97df44 149 regarding system frequency refer to product datasheet. */
lypinator 0:bb348c97df44 150 __HAL_RCC_PWR_CLK_ENABLE();
lypinator 0:bb348c97df44 151 __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
lypinator 0:bb348c97df44 152
lypinator 0:bb348c97df44 153 /* Enable HSE oscillator and activate PLL with HSE as source */
lypinator 0:bb348c97df44 154 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
lypinator 0:bb348c97df44 155 if (bypass == 0) {
lypinator 0:bb348c97df44 156 RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
lypinator 0:bb348c97df44 157 } else {
lypinator 0:bb348c97df44 158 RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
lypinator 0:bb348c97df44 159 }
lypinator 0:bb348c97df44 160 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
lypinator 0:bb348c97df44 161 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
lypinator 0:bb348c97df44 162 //RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 1 MHz (8 MHz / 8)
lypinator 0:bb348c97df44 163 //RCC_OscInitStruct.PLL.PLLN = 384; // VCO output clock = 384 MHz (1 MHz * 384)
lypinator 0:bb348c97df44 164 //RCC_OscInitStruct.PLL.PLLM = 4; // VCO input clock = 2 MHz (8 MHz / 4)
lypinator 0:bb348c97df44 165 //RCC_OscInitStruct.PLL.PLLN = 192; // VCO output clock = 384 MHz (2 MHz * 192)
lypinator 0:bb348c97df44 166
lypinator 0:bb348c97df44 167 RCC_OscInitStruct.PLL.PLLM = 25; // VCO input clock = 2 MHz (8 MHz / 4)
lypinator 0:bb348c97df44 168 RCC_OscInitStruct.PLL.PLLN = 384; // VCO output clock = 384 MHz (2 MHz * 192)
lypinator 0:bb348c97df44 169
lypinator 0:bb348c97df44 170
lypinator 0:bb348c97df44 171 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; // PLLCLK = 96 MHz (384 MHz / 4)
lypinator 0:bb348c97df44 172 RCC_OscInitStruct.PLL.PLLQ = 8; // USB clock = 48 MHz (384 MHz / 8) --> Good for USB
lypinator 0:bb348c97df44 173 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
lypinator 0:bb348c97df44 174 return 0; // FAIL
lypinator 0:bb348c97df44 175 }
lypinator 0:bb348c97df44 176
lypinator 0:bb348c97df44 177 /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
lypinator 0:bb348c97df44 178 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
lypinator 0:bb348c97df44 179 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 96 MHz
lypinator 0:bb348c97df44 180 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 96 MHz
lypinator 0:bb348c97df44 181 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 48 MHz
lypinator 0:bb348c97df44 182 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 96 MHz
lypinator 0:bb348c97df44 183 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) {
lypinator 0:bb348c97df44 184 return 0; // FAIL
lypinator 0:bb348c97df44 185 }
lypinator 0:bb348c97df44 186
lypinator 0:bb348c97df44 187 /* Output clock on MCO1 pin(PA8) for debugging purpose */
lypinator 0:bb348c97df44 188
lypinator 0:bb348c97df44 189 //if (bypass == 0)
lypinator 0:bb348c97df44 190 // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz with xtal
lypinator 0:bb348c97df44 191 //else
lypinator 0:bb348c97df44 192 // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz with external clock
lypinator 0:bb348c97df44 193
lypinator 0:bb348c97df44 194 return 1; // OK
lypinator 0:bb348c97df44 195 }
lypinator 0:bb348c97df44 196 #endif
lypinator 0:bb348c97df44 197
lypinator 0:bb348c97df44 198 /******************************************************************************/
lypinator 0:bb348c97df44 199 /* PLL (clocked by HSI) used as System clock source */
lypinator 0:bb348c97df44 200 /******************************************************************************/
lypinator 0:bb348c97df44 201 uint8_t SetSysClock_PLL_HSI(void)
lypinator 0:bb348c97df44 202 {
lypinator 0:bb348c97df44 203 RCC_ClkInitTypeDef RCC_ClkInitStruct;
lypinator 0:bb348c97df44 204 RCC_OscInitTypeDef RCC_OscInitStruct;
lypinator 0:bb348c97df44 205
lypinator 0:bb348c97df44 206 /* The voltage scaling allows optimizing the power consumption when the device is
lypinator 0:bb348c97df44 207 clocked below the maximum system frequency, to update the voltage scaling value
lypinator 0:bb348c97df44 208 regarding system frequency refer to product datasheet. */
lypinator 0:bb348c97df44 209 __HAL_RCC_PWR_CLK_ENABLE();
lypinator 0:bb348c97df44 210 __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
lypinator 0:bb348c97df44 211
lypinator 0:bb348c97df44 212 /* Enable HSI oscillator and activate PLL with HSI as source */
lypinator 0:bb348c97df44 213 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
lypinator 0:bb348c97df44 214 RCC_OscInitStruct.HSIState = RCC_HSI_ON;
lypinator 0:bb348c97df44 215 RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
lypinator 0:bb348c97df44 216 RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
lypinator 0:bb348c97df44 217 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
lypinator 0:bb348c97df44 218 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
lypinator 0:bb348c97df44 219 //RCC_OscInitStruct.PLL.PLLM = 16; // VCO input clock = 1 MHz (16 MHz / 16)
lypinator 0:bb348c97df44 220 //RCC_OscInitStruct.PLL.PLLN = 384; // VCO output clock = 384 MHz (1 MHz * 384)
lypinator 0:bb348c97df44 221 RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 2 MHz (16 MHz / 8)
lypinator 0:bb348c97df44 222 RCC_OscInitStruct.PLL.PLLN = 192; // VCO output clock = 384 MHz (2 MHz * 192)
lypinator 0:bb348c97df44 223 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; // PLLCLK = 96 MHz (384 MHz / 4)
lypinator 0:bb348c97df44 224 RCC_OscInitStruct.PLL.PLLQ = 8; // USB clock = 48 MHz (384 MHz / 8) --> Good for USB
lypinator 0:bb348c97df44 225 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
lypinator 0:bb348c97df44 226 return 0; // FAIL
lypinator 0:bb348c97df44 227 }
lypinator 0:bb348c97df44 228
lypinator 0:bb348c97df44 229 /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
lypinator 0:bb348c97df44 230 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
lypinator 0:bb348c97df44 231 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 96 MHz
lypinator 0:bb348c97df44 232 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 96 MHz
lypinator 0:bb348c97df44 233 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 48 MHz
lypinator 0:bb348c97df44 234 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 96 MHz
lypinator 0:bb348c97df44 235 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) {
lypinator 0:bb348c97df44 236 return 0; // FAIL
lypinator 0:bb348c97df44 237 }
lypinator 0:bb348c97df44 238
lypinator 0:bb348c97df44 239 /* Output clock on MCO1 pin(PA8) for debugging purpose */
lypinator 0:bb348c97df44 240 //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
lypinator 0:bb348c97df44 241
lypinator 0:bb348c97df44 242 return 1; // OK
lypinator 0:bb348c97df44 243 }