Thomas Lyp / DevLibMemoryController

Initial commit

Dependencies:   FastPWM

mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xC/TARGET_DISCO_F401VC/system_clock.c@0:bb348c97df44, 2020-09-16 (annotated)

Committer:
lypinator
Date:
Wed Sep 16 01:11:49 2020 +0000
Revision:
0:bb348c97df44
Added PWM

Who changed what in which revision?

UserRevisionLine numberNew contents of line
lypinator 0:bb348c97df44 1 /* mbed Microcontroller Library
lypinator 0:bb348c97df44 2 * Copyright (c) 2006-2017 ARM Limited
lypinator 0:bb348c97df44 3 *
lypinator 0:bb348c97df44 4 * Licensed under the Apache License, Version 2.0 (the "License");
lypinator 0:bb348c97df44 5 * you may not use this file except in compliance with the License.
lypinator 0:bb348c97df44 6 * You may obtain a copy of the License at
lypinator 0:bb348c97df44 7 *
lypinator 0:bb348c97df44 8 * http://www.apache.org/licenses/LICENSE-2.0
lypinator 0:bb348c97df44 9 *
lypinator 0:bb348c97df44 10 * Unless required by applicable law or agreed to in writing, software
lypinator 0:bb348c97df44 11 * distributed under the License is distributed on an "AS IS" BASIS,
lypinator 0:bb348c97df44 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
lypinator 0:bb348c97df44 13 * See the License for the specific language governing permissions and
lypinator 0:bb348c97df44 14 * limitations under the License.
lypinator 0:bb348c97df44 15 */
lypinator 0:bb348c97df44 16
lypinator 0:bb348c97df44 17 /**
lypinator 0:bb348c97df44 18 * This file configures the system clock as follows:
lypinator 0:bb348c97df44 19 *-----------------------------------------------------------------------------
lypinator 0:bb348c97df44 20 * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI
lypinator 0:bb348c97df44 21 * | (external 8 MHz clock) | (internal 16 MHz)
lypinator 0:bb348c97df44 22 * | 2- PLL_HSE_XTAL |
lypinator 0:bb348c97df44 23 * | (external 8 MHz xtal) |
lypinator 0:bb348c97df44 24 *-----------------------------------------------------------------------------
lypinator 0:bb348c97df44 25 * SYSCLK(MHz) | 84 | 84
lypinator 0:bb348c97df44 26 *-----------------------------------------------------------------------------
lypinator 0:bb348c97df44 27 * AHBCLK (MHz) | 84 | 84
lypinator 0:bb348c97df44 28 *-----------------------------------------------------------------------------
lypinator 0:bb348c97df44 29 * APB1CLK (MHz) | 42 | 42
lypinator 0:bb348c97df44 30 *-----------------------------------------------------------------------------
lypinator 0:bb348c97df44 31 * APB2CLK (MHz) | 84 | 84
lypinator 0:bb348c97df44 32 *-----------------------------------------------------------------------------
lypinator 0:bb348c97df44 33 * USB capable (48 MHz precise clock) | YES | NO
lypinator 0:bb348c97df44 34 *-----------------------------------------------------------------------------
lypinator 0:bb348c97df44 35 **/
lypinator 0:bb348c97df44 36
lypinator 0:bb348c97df44 37 #include "stm32f4xx.h"
lypinator 0:bb348c97df44 38
lypinator 0:bb348c97df44 39 /*!< Uncomment the following line if you need to relocate your vector Table in
lypinator 0:bb348c97df44 40 Internal SRAM. */
lypinator 0:bb348c97df44 41 /* #define VECT_TAB_SRAM */
lypinator 0:bb348c97df44 42 #define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
lypinator 0:bb348c97df44 43 This value must be a multiple of 0x200. */
lypinator 0:bb348c97df44 44
lypinator 0:bb348c97df44 45 /* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
lypinator 0:bb348c97df44 46 #define USE_PLL_HSE_EXTC (1) /* Use external clock */
lypinator 0:bb348c97df44 47 #define USE_PLL_HSE_XTAL (1) /* Use external xtal */
lypinator 0:bb348c97df44 48
lypinator 0:bb348c97df44 49 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
lypinator 0:bb348c97df44 50 uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
lypinator 0:bb348c97df44 51 #endif
lypinator 0:bb348c97df44 52
lypinator 0:bb348c97df44 53 uint8_t SetSysClock_PLL_HSI(void);
lypinator 0:bb348c97df44 54
lypinator 0:bb348c97df44 55 /**
lypinator 0:bb348c97df44 56 * @brief Setup the microcontroller system
lypinator 0:bb348c97df44 57 * Initialize the FPU setting, vector table location and External memory
lypinator 0:bb348c97df44 58 * configuration.
lypinator 0:bb348c97df44 59 * @param None
lypinator 0:bb348c97df44 60 * @retval None
lypinator 0:bb348c97df44 61 */
lypinator 0:bb348c97df44 62 void SystemInit(void)
lypinator 0:bb348c97df44 63 {
lypinator 0:bb348c97df44 64 /* FPU settings ------------------------------------------------------------*/
lypinator 0:bb348c97df44 65 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
lypinator 0:bb348c97df44 66 SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */
lypinator 0:bb348c97df44 67 #endif
lypinator 0:bb348c97df44 68 /* Reset the RCC clock configuration to the default reset state ------------*/
lypinator 0:bb348c97df44 69 /* Set HSION bit */
lypinator 0:bb348c97df44 70 RCC->CR |= (uint32_t)0x00000001;
lypinator 0:bb348c97df44 71
lypinator 0:bb348c97df44 72 /* Reset CFGR register */
lypinator 0:bb348c97df44 73 RCC->CFGR = 0x00000000;
lypinator 0:bb348c97df44 74
lypinator 0:bb348c97df44 75 /* Reset HSEON, CSSON and PLLON bits */
lypinator 0:bb348c97df44 76 RCC->CR &= (uint32_t)0xFEF6FFFF;
lypinator 0:bb348c97df44 77
lypinator 0:bb348c97df44 78 /* Reset PLLCFGR register */
lypinator 0:bb348c97df44 79 RCC->PLLCFGR = 0x24003010;
lypinator 0:bb348c97df44 80
lypinator 0:bb348c97df44 81 /* Reset HSEBYP bit */
lypinator 0:bb348c97df44 82 RCC->CR &= (uint32_t)0xFFFBFFFF;
lypinator 0:bb348c97df44 83
lypinator 0:bb348c97df44 84 /* Disable all interrupts */
lypinator 0:bb348c97df44 85 RCC->CIR = 0x00000000;
lypinator 0:bb348c97df44 86
lypinator 0:bb348c97df44 87 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
lypinator 0:bb348c97df44 88 SystemInit_ExtMemCtl();
lypinator 0:bb348c97df44 89 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
lypinator 0:bb348c97df44 90
lypinator 0:bb348c97df44 91 /* Configure the Vector Table location add offset address ------------------*/
lypinator 0:bb348c97df44 92 #ifdef VECT_TAB_SRAM
lypinator 0:bb348c97df44 93 SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
lypinator 0:bb348c97df44 94 #else
lypinator 0:bb348c97df44 95 SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
lypinator 0:bb348c97df44 96 #endif
lypinator 0:bb348c97df44 97
lypinator 0:bb348c97df44 98 }
lypinator 0:bb348c97df44 99
lypinator 0:bb348c97df44 100
lypinator 0:bb348c97df44 101 /**
lypinator 0:bb348c97df44 102 * @brief Configures the System clock source, PLL Multiplier and Divider factors,
lypinator 0:bb348c97df44 103 * AHB/APBx prescalers and Flash settings
lypinator 0:bb348c97df44 104 * @note This function should be called only once the RCC clock configuration
lypinator 0:bb348c97df44 105 * is reset to the default reset state (done in SystemInit() function).
lypinator 0:bb348c97df44 106 * @param None
lypinator 0:bb348c97df44 107 * @retval None
lypinator 0:bb348c97df44 108 */
lypinator 0:bb348c97df44 109 void SetSysClock(void)
lypinator 0:bb348c97df44 110 {
lypinator 0:bb348c97df44 111 /* 1- Try to start with HSE and external clock */
lypinator 0:bb348c97df44 112 #if USE_PLL_HSE_EXTC != 0
lypinator 0:bb348c97df44 113 if (SetSysClock_PLL_HSE(1) == 0)
lypinator 0:bb348c97df44 114 #endif
lypinator 0:bb348c97df44 115 {
lypinator 0:bb348c97df44 116 /* 2- If fail try to start with HSE and external xtal */
lypinator 0:bb348c97df44 117 #if USE_PLL_HSE_XTAL != 0
lypinator 0:bb348c97df44 118 if (SetSysClock_PLL_HSE(0) == 0)
lypinator 0:bb348c97df44 119 #endif
lypinator 0:bb348c97df44 120 {
lypinator 0:bb348c97df44 121 /* 3- If fail start with HSI clock */
lypinator 0:bb348c97df44 122 if (SetSysClock_PLL_HSI() == 0) {
lypinator 0:bb348c97df44 123 while (1) {
lypinator 0:bb348c97df44 124 // [TODO] Put something here to tell the user that a problem occured...
lypinator 0:bb348c97df44 125 }
lypinator 0:bb348c97df44 126 }
lypinator 0:bb348c97df44 127 }
lypinator 0:bb348c97df44 128 }
lypinator 0:bb348c97df44 129
lypinator 0:bb348c97df44 130 /* Output clock on MCO2 pin(PC9) for debugging purpose */
lypinator 0:bb348c97df44 131 //HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_1); // 84 MHz
lypinator 0:bb348c97df44 132 }
lypinator 0:bb348c97df44 133
lypinator 0:bb348c97df44 134 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
lypinator 0:bb348c97df44 135 /******************************************************************************/
lypinator 0:bb348c97df44 136 /* PLL (clocked by HSE) used as System clock source */
lypinator 0:bb348c97df44 137 /******************************************************************************/
lypinator 0:bb348c97df44 138 uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
lypinator 0:bb348c97df44 139 {
lypinator 0:bb348c97df44 140 RCC_ClkInitTypeDef RCC_ClkInitStruct;
lypinator 0:bb348c97df44 141 RCC_OscInitTypeDef RCC_OscInitStruct;
lypinator 0:bb348c97df44 142
lypinator 0:bb348c97df44 143 /* The voltage scaling allows optimizing the power consumption when the device is
lypinator 0:bb348c97df44 144 clocked below the maximum system frequency, to update the voltage scaling value
lypinator 0:bb348c97df44 145 regarding system frequency refer to product datasheet. */
lypinator 0:bb348c97df44 146 __HAL_RCC_PWR_CLK_ENABLE();
lypinator 0:bb348c97df44 147 __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
lypinator 0:bb348c97df44 148
lypinator 0:bb348c97df44 149 /* Enable HSE oscillator and activate PLL with HSE as source */
lypinator 0:bb348c97df44 150 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
lypinator 0:bb348c97df44 151 if (bypass == 0) {
lypinator 0:bb348c97df44 152 RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
lypinator 0:bb348c97df44 153 } else {
lypinator 0:bb348c97df44 154 RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
lypinator 0:bb348c97df44 155 }
lypinator 0:bb348c97df44 156 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
lypinator 0:bb348c97df44 157 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
lypinator 0:bb348c97df44 158 RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 1 MHz (8 MHz / 8)
lypinator 0:bb348c97df44 159 RCC_OscInitStruct.PLL.PLLN = 336; // VCO output clock = 336 MHz (1 MHz * 336)
lypinator 0:bb348c97df44 160 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; // PLLCLK = 84 MHz (336 MHz / 4)
lypinator 0:bb348c97df44 161 RCC_OscInitStruct.PLL.PLLQ = 7; // USB clock = 48 MHz (336 MHz / 7) --> OK for USB
lypinator 0:bb348c97df44 162 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
lypinator 0:bb348c97df44 163 return 0; // FAIL
lypinator 0:bb348c97df44 164 }
lypinator 0:bb348c97df44 165
lypinator 0:bb348c97df44 166 /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
lypinator 0:bb348c97df44 167 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
lypinator 0:bb348c97df44 168 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 84 MHz
lypinator 0:bb348c97df44 169 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 84 MHz
lypinator 0:bb348c97df44 170 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 42 MHz
lypinator 0:bb348c97df44 171 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 84 MHz
lypinator 0:bb348c97df44 172 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) {
lypinator 0:bb348c97df44 173 return 0; // FAIL
lypinator 0:bb348c97df44 174 }
lypinator 0:bb348c97df44 175
lypinator 0:bb348c97df44 176 /* Output clock on MCO1 pin(PA8) for debugging purpose */
lypinator 0:bb348c97df44 177 /*
lypinator 0:bb348c97df44 178 if (bypass == 0)
lypinator 0:bb348c97df44 179 HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
lypinator 0:bb348c97df44 180 else
lypinator 0:bb348c97df44 181 HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
lypinator 0:bb348c97df44 182 */
lypinator 0:bb348c97df44 183
lypinator 0:bb348c97df44 184 return 1; // OK
lypinator 0:bb348c97df44 185 }
lypinator 0:bb348c97df44 186 #endif
lypinator 0:bb348c97df44 187
lypinator 0:bb348c97df44 188 /******************************************************************************/
lypinator 0:bb348c97df44 189 /* PLL (clocked by HSI) used as System clock source */
lypinator 0:bb348c97df44 190 /******************************************************************************/
lypinator 0:bb348c97df44 191 uint8_t SetSysClock_PLL_HSI(void)
lypinator 0:bb348c97df44 192 {
lypinator 0:bb348c97df44 193 RCC_ClkInitTypeDef RCC_ClkInitStruct;
lypinator 0:bb348c97df44 194 RCC_OscInitTypeDef RCC_OscInitStruct;
lypinator 0:bb348c97df44 195
lypinator 0:bb348c97df44 196 /* The voltage scaling allows optimizing the power consumption when the device is
lypinator 0:bb348c97df44 197 clocked below the maximum system frequency, to update the voltage scaling value
lypinator 0:bb348c97df44 198 regarding system frequency refer to product datasheet. */
lypinator 0:bb348c97df44 199 __HAL_RCC_PWR_CLK_ENABLE();
lypinator 0:bb348c97df44 200 __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
lypinator 0:bb348c97df44 201
lypinator 0:bb348c97df44 202 /* Enable HSI oscillator and activate PLL with HSI as source */
lypinator 0:bb348c97df44 203 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
lypinator 0:bb348c97df44 204 RCC_OscInitStruct.HSIState = RCC_HSI_ON;
lypinator 0:bb348c97df44 205 RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
lypinator 0:bb348c97df44 206 RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
lypinator 0:bb348c97df44 207 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
lypinator 0:bb348c97df44 208 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
lypinator 0:bb348c97df44 209 RCC_OscInitStruct.PLL.PLLM = 16; // VCO input clock = 1 MHz (16 MHz / 16)
lypinator 0:bb348c97df44 210 RCC_OscInitStruct.PLL.PLLN = 336; // VCO output clock = 336 MHz (1 MHz * 336)
lypinator 0:bb348c97df44 211 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; // PLLCLK = 84 MHz (336 MHz / 4)
lypinator 0:bb348c97df44 212 RCC_OscInitStruct.PLL.PLLQ = 7; // USB clock = 48 MHz (336 MHz / 7) --> freq is ok but not precise enough
lypinator 0:bb348c97df44 213 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
lypinator 0:bb348c97df44 214 return 0; // FAIL
lypinator 0:bb348c97df44 215 }
lypinator 0:bb348c97df44 216
lypinator 0:bb348c97df44 217 /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
lypinator 0:bb348c97df44 218 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
lypinator 0:bb348c97df44 219 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 84 MHz
lypinator 0:bb348c97df44 220 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 84 MHz
lypinator 0:bb348c97df44 221 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 42 MHz
lypinator 0:bb348c97df44 222 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 84 MHz
lypinator 0:bb348c97df44 223 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) {
lypinator 0:bb348c97df44 224 return 0; // FAIL
lypinator 0:bb348c97df44 225 }
lypinator 0:bb348c97df44 226
lypinator 0:bb348c97df44 227 /* Output clock on MCO1 pin(PA8) for debugging purpose */
lypinator 0:bb348c97df44 228 //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
lypinator 0:bb348c97df44 229
lypinator 0:bb348c97df44 230 return 1; // OK
lypinator 0:bb348c97df44 231 }