Thomas Lyp / DevLibMemoryController

Initial commit

Dependencies:   FastPWM

mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/device/system_clock.c@0:bb348c97df44, 2020-09-16 (annotated)

Committer:
lypinator
Date:
Wed Sep 16 01:11:49 2020 +0000
Revision:
0:bb348c97df44
Added PWM

Who changed what in which revision?

UserRevisionLine numberNew contents of line
lypinator 0:bb348c97df44 1 /* mbed Microcontroller Library
lypinator 0:bb348c97df44 2 * Copyright (c) 2006-2017 ARM Limited
lypinator 0:bb348c97df44 3 *
lypinator 0:bb348c97df44 4 * Licensed under the Apache License, Version 2.0 (the "License");
lypinator 0:bb348c97df44 5 * you may not use this file except in compliance with the License.
lypinator 0:bb348c97df44 6 * You may obtain a copy of the License at
lypinator 0:bb348c97df44 7 *
lypinator 0:bb348c97df44 8 * http://www.apache.org/licenses/LICENSE-2.0
lypinator 0:bb348c97df44 9 *
lypinator 0:bb348c97df44 10 * Unless required by applicable law or agreed to in writing, software
lypinator 0:bb348c97df44 11 * distributed under the License is distributed on an "AS IS" BASIS,
lypinator 0:bb348c97df44 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
lypinator 0:bb348c97df44 13 * See the License for the specific language governing permissions and
lypinator 0:bb348c97df44 14 * limitations under the License.
lypinator 0:bb348c97df44 15 */
lypinator 0:bb348c97df44 16
lypinator 0:bb348c97df44 17 /**
lypinator 0:bb348c97df44 18 * This file configures the system clock as follows:
lypinator 0:bb348c97df44 19 *-----------------------------------------------------------------------------
lypinator 0:bb348c97df44 20 * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI
lypinator 0:bb348c97df44 21 * | (external 8 MHz clock) | (internal 16 MHz)
lypinator 0:bb348c97df44 22 * | 2- PLL_HSE_XTAL |
lypinator 0:bb348c97df44 23 * | (external 8 MHz xtal) |
lypinator 0:bb348c97df44 24 *-----------------------------------------------------------------------------
lypinator 0:bb348c97df44 25 * SYSCLK(MHz) | 96 | 96
lypinator 0:bb348c97df44 26 *-----------------------------------------------------------------------------
lypinator 0:bb348c97df44 27 * AHBCLK (MHz) | 96 | 96
lypinator 0:bb348c97df44 28 *-----------------------------------------------------------------------------
lypinator 0:bb348c97df44 29 * APB1CLK (MHz) | 48 | 48
lypinator 0:bb348c97df44 30 *-----------------------------------------------------------------------------
lypinator 0:bb348c97df44 31 * APB2CLK (MHz) | 96 | 96
lypinator 0:bb348c97df44 32 *-----------------------------------------------------------------------------
lypinator 0:bb348c97df44 33 * USB capable (48 MHz precise clock) | YES | NO
lypinator 0:bb348c97df44 34 *-----------------------------------------------------------------------------
lypinator 0:bb348c97df44 35 **/
lypinator 0:bb348c97df44 36
lypinator 0:bb348c97df44 37 #include "stm32f4xx.h"
lypinator 0:bb348c97df44 38 #include "mbed_debug.h"
lypinator 0:bb348c97df44 39
lypinator 0:bb348c97df44 40 /*!< Uncomment the following line if you need to relocate your vector Table in
lypinator 0:bb348c97df44 41 Internal SRAM. */
lypinator 0:bb348c97df44 42 /* #define VECT_TAB_SRAM */
lypinator 0:bb348c97df44 43 #ifndef VECT_TAB_OFFSET
lypinator 0:bb348c97df44 44 #define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
lypinator 0:bb348c97df44 45 This value must be a multiple of 0x200. */
lypinator 0:bb348c97df44 46 #endif
lypinator 0:bb348c97df44 47
lypinator 0:bb348c97df44 48
lypinator 0:bb348c97df44 49 /* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
lypinator 0:bb348c97df44 50 #if !defined (USE_PLL_HSE_EXTC)
lypinator 0:bb348c97df44 51 #define USE_PLL_HSE_EXTC (1) /* Use external clock */
lypinator 0:bb348c97df44 52 #endif
lypinator 0:bb348c97df44 53 #if !defined (USE_PLL_HSE_XTAL)
lypinator 0:bb348c97df44 54 #define USE_PLL_HSE_XTAL (1) /* Use external xtal */
lypinator 0:bb348c97df44 55 #endif
lypinator 0:bb348c97df44 56
lypinator 0:bb348c97df44 57 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
lypinator 0:bb348c97df44 58 uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
lypinator 0:bb348c97df44 59 #endif
lypinator 0:bb348c97df44 60
lypinator 0:bb348c97df44 61 uint8_t SetSysClock_PLL_HSI(void);
lypinator 0:bb348c97df44 62
lypinator 0:bb348c97df44 63
lypinator 0:bb348c97df44 64 /**
lypinator 0:bb348c97df44 65 * @brief Setup the microcontroller system
lypinator 0:bb348c97df44 66 * Initialize the FPU setting, vector table location and External memory
lypinator 0:bb348c97df44 67 * configuration.
lypinator 0:bb348c97df44 68 * @param None
lypinator 0:bb348c97df44 69 * @retval None
lypinator 0:bb348c97df44 70 */
lypinator 0:bb348c97df44 71 void SystemInit(void)
lypinator 0:bb348c97df44 72 {
lypinator 0:bb348c97df44 73 /* FPU settings ------------------------------------------------------------*/
lypinator 0:bb348c97df44 74 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
lypinator 0:bb348c97df44 75 SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
lypinator 0:bb348c97df44 76 #endif
lypinator 0:bb348c97df44 77 /* Reset the RCC clock configuration to the default reset state ------------*/
lypinator 0:bb348c97df44 78 /* Set HSION bit */
lypinator 0:bb348c97df44 79 RCC->CR |= (uint32_t)0x00000001;
lypinator 0:bb348c97df44 80
lypinator 0:bb348c97df44 81 /* Reset CFGR register */
lypinator 0:bb348c97df44 82 RCC->CFGR = 0x00000000;
lypinator 0:bb348c97df44 83
lypinator 0:bb348c97df44 84 /* Reset HSEON, CSSON and PLLON bits */
lypinator 0:bb348c97df44 85 RCC->CR &= (uint32_t)0xFEF6FFFF;
lypinator 0:bb348c97df44 86
lypinator 0:bb348c97df44 87 /* Reset PLLCFGR register */
lypinator 0:bb348c97df44 88 RCC->PLLCFGR = 0x24003010;
lypinator 0:bb348c97df44 89
lypinator 0:bb348c97df44 90 /* Reset HSEBYP bit */
lypinator 0:bb348c97df44 91 RCC->CR &= (uint32_t)0xFFFBFFFF;
lypinator 0:bb348c97df44 92
lypinator 0:bb348c97df44 93 /* Disable all interrupts */
lypinator 0:bb348c97df44 94 RCC->CIR = 0x00000000;
lypinator 0:bb348c97df44 95
lypinator 0:bb348c97df44 96 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
lypinator 0:bb348c97df44 97 SystemInit_ExtMemCtl();
lypinator 0:bb348c97df44 98 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
lypinator 0:bb348c97df44 99
lypinator 0:bb348c97df44 100 /* Configure the Vector Table location add offset address ------------------*/
lypinator 0:bb348c97df44 101 #ifdef VECT_TAB_SRAM
lypinator 0:bb348c97df44 102 SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
lypinator 0:bb348c97df44 103 #else
lypinator 0:bb348c97df44 104 SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
lypinator 0:bb348c97df44 105 #endif
lypinator 0:bb348c97df44 106
lypinator 0:bb348c97df44 107 }
lypinator 0:bb348c97df44 108
lypinator 0:bb348c97df44 109
lypinator 0:bb348c97df44 110 /**
lypinator 0:bb348c97df44 111 * @brief Configures the System clock source, PLL Multiplier and Divider factors,
lypinator 0:bb348c97df44 112 * AHB/APBx prescalers and Flash settings
lypinator 0:bb348c97df44 113 * @note This function should be called only once the RCC clock configuration
lypinator 0:bb348c97df44 114 * is reset to the default reset state (done in SystemInit() function).
lypinator 0:bb348c97df44 115 * @param None
lypinator 0:bb348c97df44 116 * @retval None
lypinator 0:bb348c97df44 117 */
lypinator 0:bb348c97df44 118 void SetSysClock(void)
lypinator 0:bb348c97df44 119 {
lypinator 0:bb348c97df44 120 /* 1- Try to start with HSE and external clock */
lypinator 0:bb348c97df44 121 #if USE_PLL_HSE_EXTC != 0
lypinator 0:bb348c97df44 122 if (SetSysClock_PLL_HSE(1) == 0)
lypinator 0:bb348c97df44 123 #endif
lypinator 0:bb348c97df44 124 {
lypinator 0:bb348c97df44 125 /* 2- If fail try to start with HSE and external xtal */
lypinator 0:bb348c97df44 126 #if USE_PLL_HSE_XTAL != 0
lypinator 0:bb348c97df44 127 if (SetSysClock_PLL_HSE(0) == 0)
lypinator 0:bb348c97df44 128 #endif
lypinator 0:bb348c97df44 129 {
lypinator 0:bb348c97df44 130 /* 3- If fail start with HSI clock */
lypinator 0:bb348c97df44 131 if (SetSysClock_PLL_HSI() == 0) {
lypinator 0:bb348c97df44 132 while(1) {
lypinator 0:bb348c97df44 133 // [TODO] Put something here to tell the user that a problem occured...
lypinator 0:bb348c97df44 134 }
lypinator 0:bb348c97df44 135 }
lypinator 0:bb348c97df44 136 }
lypinator 0:bb348c97df44 137 }
lypinator 0:bb348c97df44 138
lypinator 0:bb348c97df44 139 /* Output clock on MCO2 pin(PC9) for debugging purpose */
lypinator 0:bb348c97df44 140 //HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_4); // 100 MHz / 4 = 25 MHz
lypinator 0:bb348c97df44 141 }
lypinator 0:bb348c97df44 142
lypinator 0:bb348c97df44 143 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
lypinator 0:bb348c97df44 144 /******************************************************************************/
lypinator 0:bb348c97df44 145 /* PLL (clocked by HSE) used as System clock source */
lypinator 0:bb348c97df44 146 /******************************************************************************/
lypinator 0:bb348c97df44 147 uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
lypinator 0:bb348c97df44 148 {
lypinator 0:bb348c97df44 149 RCC_ClkInitTypeDef RCC_ClkInitStruct;
lypinator 0:bb348c97df44 150 RCC_OscInitTypeDef RCC_OscInitStruct;
lypinator 0:bb348c97df44 151
lypinator 0:bb348c97df44 152 /* The voltage scaling allows optimizing the power consumption when the device is
lypinator 0:bb348c97df44 153 clocked below the maximum system frequency, to update the voltage scaling value
lypinator 0:bb348c97df44 154 regarding system frequency refer to product datasheet. */
lypinator 0:bb348c97df44 155 __HAL_RCC_PWR_CLK_ENABLE();
lypinator 0:bb348c97df44 156 __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
lypinator 0:bb348c97df44 157
lypinator 0:bb348c97df44 158 /* Enable HSE oscillator and activate PLL with HSE as source */
lypinator 0:bb348c97df44 159 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
lypinator 0:bb348c97df44 160 if (bypass == 0) {
lypinator 0:bb348c97df44 161 RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
lypinator 0:bb348c97df44 162 } else {
lypinator 0:bb348c97df44 163 RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
lypinator 0:bb348c97df44 164 }
lypinator 0:bb348c97df44 165 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
lypinator 0:bb348c97df44 166 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
lypinator 0:bb348c97df44 167 RCC_OscInitStruct.PLL.PLLM = HSE_VALUE/1000000; // VCO input clock = 1 MHz
lypinator 0:bb348c97df44 168 RCC_OscInitStruct.PLL.PLLN = 192; // VCO output clock = 192 MHz (1 MHz * 192)
lypinator 0:bb348c97df44 169 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // PLLCLK = 96 MHz (192 MHz / 2)
lypinator 0:bb348c97df44 170 RCC_OscInitStruct.PLL.PLLQ = 4; // USB clock = 48 MHz (192 MHz / 4)
lypinator 0:bb348c97df44 171 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
lypinator 0:bb348c97df44 172 return 0; // FAIL
lypinator 0:bb348c97df44 173 }
lypinator 0:bb348c97df44 174
lypinator 0:bb348c97df44 175 /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
lypinator 0:bb348c97df44 176 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
lypinator 0:bb348c97df44 177 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 96 MHz
lypinator 0:bb348c97df44 178 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 96 MHz
lypinator 0:bb348c97df44 179 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 48 MHz
lypinator 0:bb348c97df44 180 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 96 MHz
lypinator 0:bb348c97df44 181 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) {
lypinator 0:bb348c97df44 182 return 0; // FAIL
lypinator 0:bb348c97df44 183 }
lypinator 0:bb348c97df44 184
lypinator 0:bb348c97df44 185 /* Output clock on MCO1 pin(PA8) for debugging purpose */
lypinator 0:bb348c97df44 186
lypinator 0:bb348c97df44 187 //if (bypass == 0)
lypinator 0:bb348c97df44 188 // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz with xtal
lypinator 0:bb348c97df44 189 //else
lypinator 0:bb348c97df44 190 // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz with external clock
lypinator 0:bb348c97df44 191
lypinator 0:bb348c97df44 192 return 1; // OK
lypinator 0:bb348c97df44 193 }
lypinator 0:bb348c97df44 194 #endif
lypinator 0:bb348c97df44 195
lypinator 0:bb348c97df44 196 /******************************************************************************/
lypinator 0:bb348c97df44 197 /* PLL (clocked by HSI) used as System clock source */
lypinator 0:bb348c97df44 198 /******************************************************************************/
lypinator 0:bb348c97df44 199 uint8_t SetSysClock_PLL_HSI(void)
lypinator 0:bb348c97df44 200 {
lypinator 0:bb348c97df44 201 RCC_ClkInitTypeDef RCC_ClkInitStruct;
lypinator 0:bb348c97df44 202 RCC_OscInitTypeDef RCC_OscInitStruct;
lypinator 0:bb348c97df44 203
lypinator 0:bb348c97df44 204 /* The voltage scaling allows optimizing the power consumption when the device is
lypinator 0:bb348c97df44 205 clocked below the maximum system frequency, to update the voltage scaling value
lypinator 0:bb348c97df44 206 regarding system frequency refer to product datasheet. */
lypinator 0:bb348c97df44 207 __HAL_RCC_PWR_CLK_ENABLE();
lypinator 0:bb348c97df44 208 __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
lypinator 0:bb348c97df44 209
lypinator 0:bb348c97df44 210 /* Enable HSI oscillator and activate PLL with HSI as source */
lypinator 0:bb348c97df44 211 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
lypinator 0:bb348c97df44 212 RCC_OscInitStruct.HSIState = RCC_HSI_ON;
lypinator 0:bb348c97df44 213 RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
lypinator 0:bb348c97df44 214 RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
lypinator 0:bb348c97df44 215 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
lypinator 0:bb348c97df44 216 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
lypinator 0:bb348c97df44 217 RCC_OscInitStruct.PLL.PLLM = 16; // VCO input clock = 1 MHz (16 MHz / 16)
lypinator 0:bb348c97df44 218 RCC_OscInitStruct.PLL.PLLN = 192; // VCO output clock = 192 MHz (1 MHz * 192)
lypinator 0:bb348c97df44 219 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // PLLCLK = 96 MHz (192 MHz / 2)
lypinator 0:bb348c97df44 220 RCC_OscInitStruct.PLL.PLLQ = 4; // USB clock = 48 MHz (192 MHz / 4) --> Not stable for USB
lypinator 0:bb348c97df44 221 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
lypinator 0:bb348c97df44 222 return 0; // FAIL
lypinator 0:bb348c97df44 223 }
lypinator 0:bb348c97df44 224
lypinator 0:bb348c97df44 225 /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
lypinator 0:bb348c97df44 226 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
lypinator 0:bb348c97df44 227 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 96 MHz
lypinator 0:bb348c97df44 228 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 96 MHz
lypinator 0:bb348c97df44 229 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 48 MHz
lypinator 0:bb348c97df44 230 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 96 MHz
lypinator 0:bb348c97df44 231 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) {
lypinator 0:bb348c97df44 232 return 0; // FAIL
lypinator 0:bb348c97df44 233 }
lypinator 0:bb348c97df44 234
lypinator 0:bb348c97df44 235 /* Output clock on MCO1 pin(PA8) for debugging purpose */
lypinator 0:bb348c97df44 236 //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
lypinator 0:bb348c97df44 237
lypinator 0:bb348c97df44 238 return 1; // OK
lypinator 0:bb348c97df44 239 }
lypinator 0:bb348c97df44 240