Thomas Lyp / DevLibMemoryController

Initial commit

Dependencies:   FastPWM

mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/device/system_clock.c@0:bb348c97df44, 2020-09-16 (annotated)

Committer:
lypinator
Date:
Wed Sep 16 01:11:49 2020 +0000
Revision:
0:bb348c97df44
Added PWM

Who changed what in which revision?

UserRevisionLine numberNew contents of line
lypinator 0:bb348c97df44 1 /* mbed Microcontroller Library
lypinator 0:bb348c97df44 2 * Copyright (c) 2006-2017 ARM Limited
lypinator 0:bb348c97df44 3 *
lypinator 0:bb348c97df44 4 * Licensed under the Apache License, Version 2.0 (the "License");
lypinator 0:bb348c97df44 5 * you may not use this file except in compliance with the License.
lypinator 0:bb348c97df44 6 * You may obtain a copy of the License at
lypinator 0:bb348c97df44 7 *
lypinator 0:bb348c97df44 8 * http://www.apache.org/licenses/LICENSE-2.0
lypinator 0:bb348c97df44 9 *
lypinator 0:bb348c97df44 10 * Unless required by applicable law or agreed to in writing, software
lypinator 0:bb348c97df44 11 * distributed under the License is distributed on an "AS IS" BASIS,
lypinator 0:bb348c97df44 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
lypinator 0:bb348c97df44 13 * See the License for the specific language governing permissions and
lypinator 0:bb348c97df44 14 * limitations under the License.
lypinator 0:bb348c97df44 15 */
lypinator 0:bb348c97df44 16
lypinator 0:bb348c97df44 17 #include "stm32f4xx.h"
lypinator 0:bb348c97df44 18
lypinator 0:bb348c97df44 19
lypinator 0:bb348c97df44 20 /**
lypinator 0:bb348c97df44 21 /*!< Uncomment the following line if you need to relocate your vector Table in
lypinator 0:bb348c97df44 22 Internal SRAM. */
lypinator 0:bb348c97df44 23 /* #define VECT_TAB_SRAM */
lypinator 0:bb348c97df44 24 #define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
lypinator 0:bb348c97df44 25 This value must be a multiple of 0x200. */
lypinator 0:bb348c97df44 26
lypinator 0:bb348c97df44 27 /**
lypinator 0:bb348c97df44 28 * @brief Setup the microcontroller system
lypinator 0:bb348c97df44 29 * Initialize the FPU setting, vector table location and External memory
lypinator 0:bb348c97df44 30 * configuration.
lypinator 0:bb348c97df44 31 * @param None
lypinator 0:bb348c97df44 32 * @retval None
lypinator 0:bb348c97df44 33 */
lypinator 0:bb348c97df44 34 void SystemInit(void)
lypinator 0:bb348c97df44 35 {
lypinator 0:bb348c97df44 36 /* FPU settings ------------------------------------------------------------*/
lypinator 0:bb348c97df44 37 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
lypinator 0:bb348c97df44 38 SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
lypinator 0:bb348c97df44 39 #endif
lypinator 0:bb348c97df44 40 /* Reset the RCC clock configuration to the default reset state ------------*/
lypinator 0:bb348c97df44 41 /* Set HSION bit */
lypinator 0:bb348c97df44 42 RCC->CR |= (uint32_t)0x00000001;
lypinator 0:bb348c97df44 43
lypinator 0:bb348c97df44 44 /* Reset CFGR register */
lypinator 0:bb348c97df44 45 RCC->CFGR = 0x00000000;
lypinator 0:bb348c97df44 46
lypinator 0:bb348c97df44 47 /* Reset HSEON, CSSON and PLLON bits */
lypinator 0:bb348c97df44 48 RCC->CR &= (uint32_t)0xFEF6FFFF;
lypinator 0:bb348c97df44 49
lypinator 0:bb348c97df44 50 /* Reset PLLCFGR register */
lypinator 0:bb348c97df44 51 RCC->PLLCFGR = 0x24003010;
lypinator 0:bb348c97df44 52
lypinator 0:bb348c97df44 53 /* Reset HSEBYP bit */
lypinator 0:bb348c97df44 54 RCC->CR &= (uint32_t)0xFFFBFFFF;
lypinator 0:bb348c97df44 55
lypinator 0:bb348c97df44 56 /* Disable all interrupts */
lypinator 0:bb348c97df44 57 RCC->CIR = 0x00000000;
lypinator 0:bb348c97df44 58
lypinator 0:bb348c97df44 59 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
lypinator 0:bb348c97df44 60 SystemInit_ExtMemCtl();
lypinator 0:bb348c97df44 61 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
lypinator 0:bb348c97df44 62
lypinator 0:bb348c97df44 63 /* Configure the Vector Table location add offset address ------------------*/
lypinator 0:bb348c97df44 64 #ifdef VECT_TAB_SRAM
lypinator 0:bb348c97df44 65 SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
lypinator 0:bb348c97df44 66 #else
lypinator 0:bb348c97df44 67 SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
lypinator 0:bb348c97df44 68 #endif
lypinator 0:bb348c97df44 69
lypinator 0:bb348c97df44 70 }
lypinator 0:bb348c97df44 71
lypinator 0:bb348c97df44 72 /**
lypinator 0:bb348c97df44 73 * @brief Configures the System clock source, PLL Multiplier and Divider factors,
lypinator 0:bb348c97df44 74 * AHB/APBx prescalers and Flash settings
lypinator 0:bb348c97df44 75 * @note This function should be called only once the RCC clock configuration
lypinator 0:bb348c97df44 76 * is reset to the default reset state (done in SystemInit() function).
lypinator 0:bb348c97df44 77 * @param None
lypinator 0:bb348c97df44 78 * @retval None
lypinator 0:bb348c97df44 79 */
lypinator 0:bb348c97df44 80 void SetSysClock(void)
lypinator 0:bb348c97df44 81 {
lypinator 0:bb348c97df44 82 RCC_ClkInitTypeDef RCC_ClkInitStruct;
lypinator 0:bb348c97df44 83 RCC_OscInitTypeDef RCC_OscInitStruct;
lypinator 0:bb348c97df44 84
lypinator 0:bb348c97df44 85 __HAL_RCC_PWR_CLK_ENABLE();
lypinator 0:bb348c97df44 86
lypinator 0:bb348c97df44 87 __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
lypinator 0:bb348c97df44 88
lypinator 0:bb348c97df44 89 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
lypinator 0:bb348c97df44 90 RCC_OscInitStruct.HSEState = RCC_HSE_ON;
lypinator 0:bb348c97df44 91 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
lypinator 0:bb348c97df44 92 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
lypinator 0:bb348c97df44 93 RCC_OscInitStruct.PLL.PLLM = 26;
lypinator 0:bb348c97df44 94 RCC_OscInitStruct.PLL.PLLN = 192;
lypinator 0:bb348c97df44 95 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4;
lypinator 0:bb348c97df44 96 RCC_OscInitStruct.PLL.PLLQ = 4;
lypinator 0:bb348c97df44 97 HAL_RCC_OscConfig(&RCC_OscInitStruct);
lypinator 0:bb348c97df44 98
lypinator 0:bb348c97df44 99 RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
lypinator 0:bb348c97df44 100 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
lypinator 0:bb348c97df44 101 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
lypinator 0:bb348c97df44 102 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
lypinator 0:bb348c97df44 103 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
lypinator 0:bb348c97df44 104 HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1);
lypinator 0:bb348c97df44 105 }