Thomas Lyp / DevLibMemoryController

Initial commit

Dependencies:   FastPWM

mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/device/TOOLCHAIN_GCC_ARM/startup_STM32F40x.S@0:bb348c97df44, 2020-09-16 (annotated)

Committer:
lypinator
Date:
Wed Sep 16 01:11:49 2020 +0000
Revision:
0:bb348c97df44
Added PWM

Who changed what in which revision?

UserRevisionLine numberNew contents of line
lypinator 0:bb348c97df44 1 /* File: startup_STM32F40x.S
lypinator 0:bb348c97df44 2 * Purpose: startup file for Cortex-M4 devices. Should use with
lypinator 0:bb348c97df44 3 * GCC for ARM Embedded Processors
lypinator 0:bb348c97df44 4 * Version: V1.4
lypinator 0:bb348c97df44 5 * Date: 09 July 2012
lypinator 0:bb348c97df44 6 *
lypinator 0:bb348c97df44 7 * Copyright (c) 2011, 2012, ARM Limited
lypinator 0:bb348c97df44 8 * All rights reserved.
lypinator 0:bb348c97df44 9 *
lypinator 0:bb348c97df44 10 * Redistribution and use in source and binary forms, with or without
lypinator 0:bb348c97df44 11 * modification, are permitted provided that the following conditions are met:
lypinator 0:bb348c97df44 12 * Redistributions of source code must retain the above copyright
lypinator 0:bb348c97df44 13 notice, this list of conditions and the following disclaimer.
lypinator 0:bb348c97df44 14 * Redistributions in binary form must reproduce the above copyright
lypinator 0:bb348c97df44 15 notice, this list of conditions and the following disclaimer in the
lypinator 0:bb348c97df44 16 documentation and/or other materials provided with the distribution.
lypinator 0:bb348c97df44 17 * Neither the name of the ARM Limited nor the
lypinator 0:bb348c97df44 18 names of its contributors may be used to endorse or promote products
lypinator 0:bb348c97df44 19 derived from this software without specific prior written permission.
lypinator 0:bb348c97df44 20 *
lypinator 0:bb348c97df44 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
lypinator 0:bb348c97df44 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
lypinator 0:bb348c97df44 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
lypinator 0:bb348c97df44 24 * DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY
lypinator 0:bb348c97df44 25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
lypinator 0:bb348c97df44 26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
lypinator 0:bb348c97df44 27 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
lypinator 0:bb348c97df44 28 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
lypinator 0:bb348c97df44 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
lypinator 0:bb348c97df44 30 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
lypinator 0:bb348c97df44 31 */
lypinator 0:bb348c97df44 32 .syntax unified
lypinator 0:bb348c97df44 33 .arch armv7-m
lypinator 0:bb348c97df44 34
lypinator 0:bb348c97df44 35 .section .stack
lypinator 0:bb348c97df44 36 .align 3
lypinator 0:bb348c97df44 37 #ifdef __STACK_SIZE
lypinator 0:bb348c97df44 38 .equ Stack_Size, __STACK_SIZE
lypinator 0:bb348c97df44 39 #else
lypinator 0:bb348c97df44 40 .equ Stack_Size, 0xc00
lypinator 0:bb348c97df44 41 #endif
lypinator 0:bb348c97df44 42 .globl __StackTop
lypinator 0:bb348c97df44 43 .globl __StackLimit
lypinator 0:bb348c97df44 44 __StackLimit:
lypinator 0:bb348c97df44 45 .space Stack_Size
lypinator 0:bb348c97df44 46 .size __StackLimit, . - __StackLimit
lypinator 0:bb348c97df44 47 __StackTop:
lypinator 0:bb348c97df44 48 .size __StackTop, . - __StackTop
lypinator 0:bb348c97df44 49
lypinator 0:bb348c97df44 50 .section .heap
lypinator 0:bb348c97df44 51 .align 3
lypinator 0:bb348c97df44 52 #ifdef __HEAP_SIZE
lypinator 0:bb348c97df44 53 .equ Heap_Size, __HEAP_SIZE
lypinator 0:bb348c97df44 54 #else
lypinator 0:bb348c97df44 55 .equ Heap_Size, 0
lypinator 0:bb348c97df44 56 #endif
lypinator 0:bb348c97df44 57 .globl __HeapBase
lypinator 0:bb348c97df44 58 .globl __HeapLimit
lypinator 0:bb348c97df44 59 __HeapBase:
lypinator 0:bb348c97df44 60 .if Heap_Size
lypinator 0:bb348c97df44 61 .space Heap_Size
lypinator 0:bb348c97df44 62 .endif
lypinator 0:bb348c97df44 63 .size __HeapBase, . - __HeapBase
lypinator 0:bb348c97df44 64 __HeapLimit:
lypinator 0:bb348c97df44 65 .size __HeapLimit, . - __HeapLimit
lypinator 0:bb348c97df44 66
lypinator 0:bb348c97df44 67 .section .isr_vector
lypinator 0:bb348c97df44 68 .align 2
lypinator 0:bb348c97df44 69 .globl __isr_vector
lypinator 0:bb348c97df44 70 __isr_vector:
lypinator 0:bb348c97df44 71 .long __StackTop /* Top of Stack */
lypinator 0:bb348c97df44 72 .long Reset_Handler /* Reset Handler */
lypinator 0:bb348c97df44 73 .long NMI_Handler /* NMI Handler */
lypinator 0:bb348c97df44 74 .long HardFault_Handler /* Hard Fault Handler */
lypinator 0:bb348c97df44 75 .long MemManage_Handler /* MPU Fault Handler */
lypinator 0:bb348c97df44 76 .long BusFault_Handler /* Bus Fault Handler */
lypinator 0:bb348c97df44 77 .long UsageFault_Handler /* Usage Fault Handler */
lypinator 0:bb348c97df44 78 .long 0 /* Reserved */
lypinator 0:bb348c97df44 79 .long 0 /* Reserved */
lypinator 0:bb348c97df44 80 .long 0 /* Reserved */
lypinator 0:bb348c97df44 81 .long 0 /* Reserved */
lypinator 0:bb348c97df44 82 .long SVC_Handler /* SVCall Handler */
lypinator 0:bb348c97df44 83 .long DebugMon_Handler /* Debug Monitor Handler */
lypinator 0:bb348c97df44 84 .long 0 /* Reserved */
lypinator 0:bb348c97df44 85 .long PendSV_Handler /* PendSV Handler */
lypinator 0:bb348c97df44 86 .long SysTick_Handler /* SysTick Handler */
lypinator 0:bb348c97df44 87
lypinator 0:bb348c97df44 88 /* External interrupts */
lypinator 0:bb348c97df44 89 .long WWDG_IRQHandler /* Window WatchDog */
lypinator 0:bb348c97df44 90 .long PVD_IRQHandler /* PVD through EXTI Line detection */
lypinator 0:bb348c97df44 91 .long TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
lypinator 0:bb348c97df44 92 .long RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
lypinator 0:bb348c97df44 93 .long FLASH_IRQHandler /* FLASH */
lypinator 0:bb348c97df44 94 .long RCC_IRQHandler /* RCC */
lypinator 0:bb348c97df44 95 .long EXTI0_IRQHandler /* EXTI Line0 */
lypinator 0:bb348c97df44 96 .long EXTI1_IRQHandler /* EXTI Line1 */
lypinator 0:bb348c97df44 97 .long EXTI2_IRQHandler /* EXTI Line2 */
lypinator 0:bb348c97df44 98 .long EXTI3_IRQHandler /* EXTI Line3 */
lypinator 0:bb348c97df44 99 .long EXTI4_IRQHandler /* EXTI Line4 */
lypinator 0:bb348c97df44 100 .long DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
lypinator 0:bb348c97df44 101 .long DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
lypinator 0:bb348c97df44 102 .long DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
lypinator 0:bb348c97df44 103 .long DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
lypinator 0:bb348c97df44 104 .long DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
lypinator 0:bb348c97df44 105 .long DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
lypinator 0:bb348c97df44 106 .long DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
lypinator 0:bb348c97df44 107 .long ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
lypinator 0:bb348c97df44 108 .long CAN1_TX_IRQHandler /* CAN1 TX */
lypinator 0:bb348c97df44 109 .long CAN1_RX0_IRQHandler /* CAN1 RX0 */
lypinator 0:bb348c97df44 110 .long CAN1_RX1_IRQHandler /* CAN1 RX1 */
lypinator 0:bb348c97df44 111 .long CAN1_SCE_IRQHandler /* CAN1 SCE */
lypinator 0:bb348c97df44 112 .long EXTI9_5_IRQHandler /* External Line[9:5]s */
lypinator 0:bb348c97df44 113 .long TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */
lypinator 0:bb348c97df44 114 .long TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */
lypinator 0:bb348c97df44 115 .long TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */
lypinator 0:bb348c97df44 116 .long TIM1_CC_IRQHandler /* TIM1 Capture Compare */
lypinator 0:bb348c97df44 117 .long TIM2_IRQHandler /* TIM2 */
lypinator 0:bb348c97df44 118 .long TIM3_IRQHandler /* TIM3 */
lypinator 0:bb348c97df44 119 .long TIM4_IRQHandler /* TIM4 */
lypinator 0:bb348c97df44 120 .long I2C1_EV_IRQHandler /* I2C1 Event */
lypinator 0:bb348c97df44 121 .long I2C1_ER_IRQHandler /* I2C1 Error */
lypinator 0:bb348c97df44 122 .long I2C2_EV_IRQHandler /* I2C2 Event */
lypinator 0:bb348c97df44 123 .long I2C2_ER_IRQHandler /* I2C2 Error */
lypinator 0:bb348c97df44 124 .long SPI1_IRQHandler /* SPI1 */
lypinator 0:bb348c97df44 125 .long SPI2_IRQHandler /* SPI2 */
lypinator 0:bb348c97df44 126 .long USART1_IRQHandler /* USART1 */
lypinator 0:bb348c97df44 127 .long USART2_IRQHandler /* USART2 */
lypinator 0:bb348c97df44 128 .long USART3_IRQHandler /* USART3 */
lypinator 0:bb348c97df44 129 .long EXTI15_10_IRQHandler /* External Line[15:10]s */
lypinator 0:bb348c97df44 130 .long RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
lypinator 0:bb348c97df44 131 .long OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */
lypinator 0:bb348c97df44 132 .long TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
lypinator 0:bb348c97df44 133 .long TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
lypinator 0:bb348c97df44 134 .long TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
lypinator 0:bb348c97df44 135 .long TIM8_CC_IRQHandler /* TIM8 Capture Compare */
lypinator 0:bb348c97df44 136 .long DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
lypinator 0:bb348c97df44 137 .long FSMC_IRQHandler /* FSMC */
lypinator 0:bb348c97df44 138 .long SDIO_IRQHandler /* SDIO */
lypinator 0:bb348c97df44 139 .long TIM5_IRQHandler /* TIM5 */
lypinator 0:bb348c97df44 140 .long SPI3_IRQHandler /* SPI3 */
lypinator 0:bb348c97df44 141 .long UART4_IRQHandler /* UART4 */
lypinator 0:bb348c97df44 142 .long UART5_IRQHandler /* UART5 */
lypinator 0:bb348c97df44 143 .long TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
lypinator 0:bb348c97df44 144 .long TIM7_IRQHandler /* TIM7 */
lypinator 0:bb348c97df44 145 .long DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
lypinator 0:bb348c97df44 146 .long DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
lypinator 0:bb348c97df44 147 .long DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
lypinator 0:bb348c97df44 148 .long DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
lypinator 0:bb348c97df44 149 .long DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
lypinator 0:bb348c97df44 150 .long 0 /* Reserved */
lypinator 0:bb348c97df44 151 .long 0 /* Reserved */
lypinator 0:bb348c97df44 152 .long CAN2_TX_IRQHandler /* CAN2 TX */
lypinator 0:bb348c97df44 153 .long CAN2_RX0_IRQHandler /* CAN2 RX0 */
lypinator 0:bb348c97df44 154 .long CAN2_RX1_IRQHandler /* CAN2 RX1 */
lypinator 0:bb348c97df44 155 .long CAN2_SCE_IRQHandler /* CAN2 SCE */
lypinator 0:bb348c97df44 156 .long OTG_FS_IRQHandler /* USB OTG FS */
lypinator 0:bb348c97df44 157 .long DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
lypinator 0:bb348c97df44 158 .long DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
lypinator 0:bb348c97df44 159 .long DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
lypinator 0:bb348c97df44 160 .long USART6_IRQHandler /* USART6 */
lypinator 0:bb348c97df44 161 .long I2C3_EV_IRQHandler /* I2C3 event */
lypinator 0:bb348c97df44 162 .long I2C3_ER_IRQHandler /* I2C3 error */
lypinator 0:bb348c97df44 163 .long OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
lypinator 0:bb348c97df44 164 .long OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
lypinator 0:bb348c97df44 165 .long OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
lypinator 0:bb348c97df44 166 .long OTG_HS_IRQHandler /* USB OTG HS */
lypinator 0:bb348c97df44 167 .long 0 /* Reserved */
lypinator 0:bb348c97df44 168 .long 0 /* Reserved */
lypinator 0:bb348c97df44 169 .long HASH_RNG_IRQHandler /* Hash and Rng */
lypinator 0:bb348c97df44 170 .long FPU_IRQHandler /* FPU */
lypinator 0:bb348c97df44 171
lypinator 0:bb348c97df44 172 .size __isr_vector, . - __isr_vector
lypinator 0:bb348c97df44 173
lypinator 0:bb348c97df44 174 .text
lypinator 0:bb348c97df44 175 .thumb
lypinator 0:bb348c97df44 176 .thumb_func
lypinator 0:bb348c97df44 177 .align 2
lypinator 0:bb348c97df44 178 .globl Reset_Handler
lypinator 0:bb348c97df44 179 .type Reset_Handler, %function
lypinator 0:bb348c97df44 180 Reset_Handler:
lypinator 0:bb348c97df44 181 /* Loop to copy data from read only memory to RAM. The ranges
lypinator 0:bb348c97df44 182 * of copy from/to are specified by following symbols evaluated in
lypinator 0:bb348c97df44 183 * linker script.
lypinator 0:bb348c97df44 184 * __etext: End of code section, i.e., begin of data sections to copy from.
lypinator 0:bb348c97df44 185 * __data_start__/__data_end__: RAM address range that data should be
lypinator 0:bb348c97df44 186 * copied to. Both must be aligned to 4 bytes boundary. */
lypinator 0:bb348c97df44 187
lypinator 0:bb348c97df44 188 ldr r1, =__etext
lypinator 0:bb348c97df44 189 ldr r2, =__data_start__
lypinator 0:bb348c97df44 190 ldr r3, =__data_end__
lypinator 0:bb348c97df44 191
lypinator 0:bb348c97df44 192 .LC0:
lypinator 0:bb348c97df44 193 cmp r2, r3
lypinator 0:bb348c97df44 194 ittt lt
lypinator 0:bb348c97df44 195 ldrlt r0, [r1], #4
lypinator 0:bb348c97df44 196 strlt r0, [r2], #4
lypinator 0:bb348c97df44 197 blt .LC0
lypinator 0:bb348c97df44 198
lypinator 0:bb348c97df44 199 ldr r0, =SystemInit
lypinator 0:bb348c97df44 200 blx r0
lypinator 0:bb348c97df44 201 ldr r0, =_start
lypinator 0:bb348c97df44 202 bx r0
lypinator 0:bb348c97df44 203 .pool
lypinator 0:bb348c97df44 204 .size Reset_Handler, . - Reset_Handler
lypinator 0:bb348c97df44 205
lypinator 0:bb348c97df44 206 .text
lypinator 0:bb348c97df44 207 /* Macro to define default handlers. Default handler
lypinator 0:bb348c97df44 208 * will be weak symbol and just dead loops. They can be
lypinator 0:bb348c97df44 209 * overwritten by other handlers */
lypinator 0:bb348c97df44 210 .macro def_default_handler handler_name
lypinator 0:bb348c97df44 211 .align 1
lypinator 0:bb348c97df44 212 .thumb_func
lypinator 0:bb348c97df44 213 .weak \handler_name
lypinator 0:bb348c97df44 214 .type \handler_name, %function
lypinator 0:bb348c97df44 215 \handler_name :
lypinator 0:bb348c97df44 216 b .
lypinator 0:bb348c97df44 217 .size \handler_name, . - \handler_name
lypinator 0:bb348c97df44 218 .endm
lypinator 0:bb348c97df44 219
lypinator 0:bb348c97df44 220 def_default_handler NMI_Handler
lypinator 0:bb348c97df44 221 def_default_handler HardFault_Handler
lypinator 0:bb348c97df44 222 def_default_handler MemManage_Handler
lypinator 0:bb348c97df44 223 def_default_handler BusFault_Handler
lypinator 0:bb348c97df44 224 def_default_handler UsageFault_Handler
lypinator 0:bb348c97df44 225 def_default_handler SVC_Handler
lypinator 0:bb348c97df44 226 def_default_handler DebugMon_Handler
lypinator 0:bb348c97df44 227 def_default_handler PendSV_Handler
lypinator 0:bb348c97df44 228 def_default_handler SysTick_Handler
lypinator 0:bb348c97df44 229 def_default_handler Default_Handler
lypinator 0:bb348c97df44 230
lypinator 0:bb348c97df44 231 .macro def_irq_default_handler handler_name
lypinator 0:bb348c97df44 232 .weak \handler_name
lypinator 0:bb348c97df44 233 .set \handler_name, Default_Handler
lypinator 0:bb348c97df44 234 .endm
lypinator 0:bb348c97df44 235
lypinator 0:bb348c97df44 236 def_irq_default_handler WWDG_IRQHandler
lypinator 0:bb348c97df44 237 def_irq_default_handler PVD_IRQHandler
lypinator 0:bb348c97df44 238 def_irq_default_handler TAMP_STAMP_IRQHandler
lypinator 0:bb348c97df44 239 def_irq_default_handler RTC_WKUP_IRQHandler
lypinator 0:bb348c97df44 240 def_irq_default_handler FLASH_IRQHandler
lypinator 0:bb348c97df44 241 def_irq_default_handler RCC_IRQHandler
lypinator 0:bb348c97df44 242 def_irq_default_handler EXTI0_IRQHandler
lypinator 0:bb348c97df44 243 def_irq_default_handler EXTI1_IRQHandler
lypinator 0:bb348c97df44 244 def_irq_default_handler EXTI2_IRQHandler
lypinator 0:bb348c97df44 245 def_irq_default_handler EXTI3_IRQHandler
lypinator 0:bb348c97df44 246 def_irq_default_handler EXTI4_IRQHandler
lypinator 0:bb348c97df44 247 def_irq_default_handler DMA1_Stream0_IRQHandler
lypinator 0:bb348c97df44 248 def_irq_default_handler DMA1_Stream1_IRQHandler
lypinator 0:bb348c97df44 249 def_irq_default_handler DMA1_Stream2_IRQHandler
lypinator 0:bb348c97df44 250 def_irq_default_handler DMA1_Stream3_IRQHandler
lypinator 0:bb348c97df44 251 def_irq_default_handler DMA1_Stream4_IRQHandler
lypinator 0:bb348c97df44 252 def_irq_default_handler DMA1_Stream5_IRQHandler
lypinator 0:bb348c97df44 253 def_irq_default_handler DMA1_Stream6_IRQHandler
lypinator 0:bb348c97df44 254 def_irq_default_handler ADC_IRQHandler
lypinator 0:bb348c97df44 255 def_irq_default_handler CAN1_TX_IRQHandler
lypinator 0:bb348c97df44 256 def_irq_default_handler CAN1_RX0_IRQHandler
lypinator 0:bb348c97df44 257 def_irq_default_handler CAN1_RX1_IRQHandler
lypinator 0:bb348c97df44 258 def_irq_default_handler CAN1_SCE_IRQHandler
lypinator 0:bb348c97df44 259 def_irq_default_handler EXTI9_5_IRQHandler
lypinator 0:bb348c97df44 260 def_irq_default_handler TIM1_BRK_TIM9_IRQHandler
lypinator 0:bb348c97df44 261 def_irq_default_handler TIM1_UP_TIM10_IRQHandler
lypinator 0:bb348c97df44 262 def_irq_default_handler TIM1_TRG_COM_TIM11_IRQHandler
lypinator 0:bb348c97df44 263 def_irq_default_handler TIM1_CC_IRQHandler
lypinator 0:bb348c97df44 264 def_irq_default_handler TIM2_IRQHandler
lypinator 0:bb348c97df44 265 def_irq_default_handler TIM3_IRQHandler
lypinator 0:bb348c97df44 266 def_irq_default_handler TIM4_IRQHandler
lypinator 0:bb348c97df44 267 def_irq_default_handler I2C1_EV_IRQHandler
lypinator 0:bb348c97df44 268 def_irq_default_handler I2C1_ER_IRQHandler
lypinator 0:bb348c97df44 269 def_irq_default_handler I2C2_EV_IRQHandler
lypinator 0:bb348c97df44 270 def_irq_default_handler I2C2_ER_IRQHandler
lypinator 0:bb348c97df44 271 def_irq_default_handler SPI1_IRQHandler
lypinator 0:bb348c97df44 272 def_irq_default_handler SPI2_IRQHandler
lypinator 0:bb348c97df44 273 def_irq_default_handler USART1_IRQHandler
lypinator 0:bb348c97df44 274 def_irq_default_handler USART2_IRQHandler
lypinator 0:bb348c97df44 275 def_irq_default_handler USART3_IRQHandler
lypinator 0:bb348c97df44 276 def_irq_default_handler EXTI15_10_IRQHandler
lypinator 0:bb348c97df44 277 def_irq_default_handler RTC_Alarm_IRQHandler
lypinator 0:bb348c97df44 278 def_irq_default_handler OTG_FS_WKUP_IRQHandler
lypinator 0:bb348c97df44 279 def_irq_default_handler TIM8_BRK_TIM12_IRQHandler
lypinator 0:bb348c97df44 280 def_irq_default_handler TIM8_UP_TIM13_IRQHandler
lypinator 0:bb348c97df44 281 def_irq_default_handler TIM8_TRG_COM_TIM14_IRQHandler
lypinator 0:bb348c97df44 282 def_irq_default_handler TIM8_CC_IRQHandler
lypinator 0:bb348c97df44 283 def_irq_default_handler DMA1_Stream7_IRQHandler
lypinator 0:bb348c97df44 284 def_irq_default_handler FSMC_IRQHandler
lypinator 0:bb348c97df44 285 def_irq_default_handler SDIO_IRQHandler
lypinator 0:bb348c97df44 286 def_irq_default_handler TIM5_IRQHandler
lypinator 0:bb348c97df44 287 def_irq_default_handler SPI3_IRQHandler
lypinator 0:bb348c97df44 288 def_irq_default_handler UART4_IRQHandler
lypinator 0:bb348c97df44 289 def_irq_default_handler UART5_IRQHandler
lypinator 0:bb348c97df44 290 def_irq_default_handler TIM6_DAC_IRQHandler
lypinator 0:bb348c97df44 291 def_irq_default_handler TIM7_IRQHandler
lypinator 0:bb348c97df44 292 def_irq_default_handler DMA2_Stream0_IRQHandler
lypinator 0:bb348c97df44 293 def_irq_default_handler DMA2_Stream1_IRQHandler
lypinator 0:bb348c97df44 294 def_irq_default_handler DMA2_Stream2_IRQHandler
lypinator 0:bb348c97df44 295 def_irq_default_handler DMA2_Stream3_IRQHandler
lypinator 0:bb348c97df44 296 def_irq_default_handler DMA2_Stream4_IRQHandler
lypinator 0:bb348c97df44 297 def_irq_default_handler CAN2_TX_IRQHandler
lypinator 0:bb348c97df44 298 def_irq_default_handler CAN2_RX0_IRQHandler
lypinator 0:bb348c97df44 299 def_irq_default_handler CAN2_RX1_IRQHandler
lypinator 0:bb348c97df44 300 def_irq_default_handler CAN2_SCE_IRQHandler
lypinator 0:bb348c97df44 301 def_irq_default_handler OTG_FS_IRQHandler
lypinator 0:bb348c97df44 302 def_irq_default_handler DMA2_Stream5_IRQHandler
lypinator 0:bb348c97df44 303 def_irq_default_handler DMA2_Stream6_IRQHandler
lypinator 0:bb348c97df44 304 def_irq_default_handler DMA2_Stream7_IRQHandler
lypinator 0:bb348c97df44 305 def_irq_default_handler USART6_IRQHandler
lypinator 0:bb348c97df44 306 def_irq_default_handler I2C3_EV_IRQHandler
lypinator 0:bb348c97df44 307 def_irq_default_handler I2C3_ER_IRQHandler
lypinator 0:bb348c97df44 308 def_irq_default_handler OTG_HS_EP1_OUT_IRQHandler
lypinator 0:bb348c97df44 309 def_irq_default_handler OTG_HS_EP1_IN_IRQHandler
lypinator 0:bb348c97df44 310 def_irq_default_handler OTG_HS_WKUP_IRQHandler
lypinator 0:bb348c97df44 311 def_irq_default_handler OTG_HS_IRQHandler
lypinator 0:bb348c97df44 312 def_irq_default_handler HASH_RNG_IRQHandler
lypinator 0:bb348c97df44 313 def_irq_default_handler FPU_IRQHandler
lypinator 0:bb348c97df44 314 def_irq_default_handler DEF_IRQHandler
lypinator 0:bb348c97df44 315
lypinator 0:bb348c97df44 316 .end