Thomas Lyp / DevLibMemoryController

Initial commit

Dependencies:   FastPWM

mbed-dev-master/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/stm32f411xe.h@0:bb348c97df44, 2020-09-16 (annotated)

Committer:
lypinator
Date:
Wed Sep 16 01:11:49 2020 +0000
Revision:
0:bb348c97df44
Added PWM

Who changed what in which revision?

UserRevisionLine numberNew contents of line
lypinator 0:bb348c97df44 1 /**
lypinator 0:bb348c97df44 2 ******************************************************************************
lypinator 0:bb348c97df44 3 * @file stm32f411xe.h
lypinator 0:bb348c97df44 4 * @author MCD Application Team
lypinator 0:bb348c97df44 5 * @version V2.6.1
lypinator 0:bb348c97df44 6 * @date 14-February-2017
lypinator 0:bb348c97df44 7 * @brief CMSIS STM32F411xE Device Peripheral Access Layer Header File.
lypinator 0:bb348c97df44 8 *
lypinator 0:bb348c97df44 9 * This file contains:
lypinator 0:bb348c97df44 10 * - Data structures and the address mapping for all peripherals
lypinator 0:bb348c97df44 11 * - peripherals registers declarations and bits definition
lypinator 0:bb348c97df44 12 * - Macros to access peripheral's registers hardware
lypinator 0:bb348c97df44 13 *
lypinator 0:bb348c97df44 14 ******************************************************************************
lypinator 0:bb348c97df44 15 * @attention
lypinator 0:bb348c97df44 16 *
lypinator 0:bb348c97df44 17 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
lypinator 0:bb348c97df44 18 *
lypinator 0:bb348c97df44 19 * Redistribution and use in source and binary forms, with or without modification,
lypinator 0:bb348c97df44 20 * are permitted provided that the following conditions are met:
lypinator 0:bb348c97df44 21 * 1. Redistributions of source code must retain the above copyright notice,
lypinator 0:bb348c97df44 22 * this list of conditions and the following disclaimer.
lypinator 0:bb348c97df44 23 * 2. Redistributions in binary form must reproduce the above copyright notice,
lypinator 0:bb348c97df44 24 * this list of conditions and the following disclaimer in the documentation
lypinator 0:bb348c97df44 25 * and/or other materials provided with the distribution.
lypinator 0:bb348c97df44 26 * 3. Neither the name of STMicroelectronics nor the names of its contributors
lypinator 0:bb348c97df44 27 * may be used to endorse or promote products derived from this software
lypinator 0:bb348c97df44 28 * without specific prior written permission.
lypinator 0:bb348c97df44 29 *
lypinator 0:bb348c97df44 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
lypinator 0:bb348c97df44 31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
lypinator 0:bb348c97df44 32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
lypinator 0:bb348c97df44 33 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
lypinator 0:bb348c97df44 34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
lypinator 0:bb348c97df44 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
lypinator 0:bb348c97df44 36 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
lypinator 0:bb348c97df44 37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
lypinator 0:bb348c97df44 38 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
lypinator 0:bb348c97df44 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
lypinator 0:bb348c97df44 40 *
lypinator 0:bb348c97df44 41 ******************************************************************************
lypinator 0:bb348c97df44 42 */
lypinator 0:bb348c97df44 43
lypinator 0:bb348c97df44 44 /** @addtogroup CMSIS_Device
lypinator 0:bb348c97df44 45 * @{
lypinator 0:bb348c97df44 46 */
lypinator 0:bb348c97df44 47
lypinator 0:bb348c97df44 48 /** @addtogroup stm32f411xe
lypinator 0:bb348c97df44 49 * @{
lypinator 0:bb348c97df44 50 */
lypinator 0:bb348c97df44 51
lypinator 0:bb348c97df44 52 #ifndef __STM32F411xE_H
lypinator 0:bb348c97df44 53 #define __STM32F411xE_H
lypinator 0:bb348c97df44 54
lypinator 0:bb348c97df44 55 #ifdef __cplusplus
lypinator 0:bb348c97df44 56 extern "C" {
lypinator 0:bb348c97df44 57 #endif /* __cplusplus */
lypinator 0:bb348c97df44 58
lypinator 0:bb348c97df44 59 /** @addtogroup Configuration_section_for_CMSIS
lypinator 0:bb348c97df44 60 * @{
lypinator 0:bb348c97df44 61 */
lypinator 0:bb348c97df44 62
lypinator 0:bb348c97df44 63 /**
lypinator 0:bb348c97df44 64 * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
lypinator 0:bb348c97df44 65 */
lypinator 0:bb348c97df44 66 #define __CM4_REV 0x0001U /*!< Core revision r0p1 */
lypinator 0:bb348c97df44 67 #define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */
lypinator 0:bb348c97df44 68 #define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */
lypinator 0:bb348c97df44 69 #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
lypinator 0:bb348c97df44 70 #ifndef __FPU_PRESENT
lypinator 0:bb348c97df44 71 #define __FPU_PRESENT 1U /*!< FPU present */
lypinator 0:bb348c97df44 72 #endif /* __FPU_PRESENT */
lypinator 0:bb348c97df44 73
lypinator 0:bb348c97df44 74 /**
lypinator 0:bb348c97df44 75 * @}
lypinator 0:bb348c97df44 76 */
lypinator 0:bb348c97df44 77
lypinator 0:bb348c97df44 78 /** @addtogroup Peripheral_interrupt_number_definition
lypinator 0:bb348c97df44 79 * @{
lypinator 0:bb348c97df44 80 */
lypinator 0:bb348c97df44 81
lypinator 0:bb348c97df44 82 /**
lypinator 0:bb348c97df44 83 * @brief STM32F4XX Interrupt Number Definition, according to the selected device
lypinator 0:bb348c97df44 84 * in @ref Library_configuration_section
lypinator 0:bb348c97df44 85 */
lypinator 0:bb348c97df44 86 typedef enum
lypinator 0:bb348c97df44 87 {
lypinator 0:bb348c97df44 88 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
lypinator 0:bb348c97df44 89 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
lypinator 0:bb348c97df44 90 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
lypinator 0:bb348c97df44 91 BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
lypinator 0:bb348c97df44 92 UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
lypinator 0:bb348c97df44 93 SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
lypinator 0:bb348c97df44 94 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
lypinator 0:bb348c97df44 95 PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
lypinator 0:bb348c97df44 96 SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
lypinator 0:bb348c97df44 97 /****** STM32 specific Interrupt Numbers **********************************************************************/
lypinator 0:bb348c97df44 98 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
lypinator 0:bb348c97df44 99 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
lypinator 0:bb348c97df44 100 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
lypinator 0:bb348c97df44 101 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
lypinator 0:bb348c97df44 102 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
lypinator 0:bb348c97df44 103 RCC_IRQn = 5, /*!< RCC global Interrupt */
lypinator 0:bb348c97df44 104 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
lypinator 0:bb348c97df44 105 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
lypinator 0:bb348c97df44 106 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
lypinator 0:bb348c97df44 107 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
lypinator 0:bb348c97df44 108 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
lypinator 0:bb348c97df44 109 DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
lypinator 0:bb348c97df44 110 DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
lypinator 0:bb348c97df44 111 DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
lypinator 0:bb348c97df44 112 DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
lypinator 0:bb348c97df44 113 DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
lypinator 0:bb348c97df44 114 DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
lypinator 0:bb348c97df44 115 DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
lypinator 0:bb348c97df44 116 ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
lypinator 0:bb348c97df44 117 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
lypinator 0:bb348c97df44 118 TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
lypinator 0:bb348c97df44 119 TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
lypinator 0:bb348c97df44 120 TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
lypinator 0:bb348c97df44 121 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
lypinator 0:bb348c97df44 122 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
lypinator 0:bb348c97df44 123 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
lypinator 0:bb348c97df44 124 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
lypinator 0:bb348c97df44 125 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
lypinator 0:bb348c97df44 126 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
lypinator 0:bb348c97df44 127 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
lypinator 0:bb348c97df44 128 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
lypinator 0:bb348c97df44 129 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
lypinator 0:bb348c97df44 130 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
lypinator 0:bb348c97df44 131 USART1_IRQn = 37, /*!< USART1 global Interrupt */
lypinator 0:bb348c97df44 132 USART2_IRQn = 38, /*!< USART2 global Interrupt */
lypinator 0:bb348c97df44 133 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
lypinator 0:bb348c97df44 134 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
lypinator 0:bb348c97df44 135 OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
lypinator 0:bb348c97df44 136 DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
lypinator 0:bb348c97df44 137 SDIO_IRQn = 49, /*!< SDIO global Interrupt */
lypinator 0:bb348c97df44 138 TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
lypinator 0:bb348c97df44 139 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
lypinator 0:bb348c97df44 140 DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
lypinator 0:bb348c97df44 141 DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
lypinator 0:bb348c97df44 142 DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
lypinator 0:bb348c97df44 143 DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
lypinator 0:bb348c97df44 144 DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
lypinator 0:bb348c97df44 145 OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
lypinator 0:bb348c97df44 146 DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
lypinator 0:bb348c97df44 147 DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
lypinator 0:bb348c97df44 148 DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
lypinator 0:bb348c97df44 149 USART6_IRQn = 71, /*!< USART6 global interrupt */
lypinator 0:bb348c97df44 150 I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
lypinator 0:bb348c97df44 151 I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
lypinator 0:bb348c97df44 152 FPU_IRQn = 81, /*!< FPU global interrupt */
lypinator 0:bb348c97df44 153 SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
lypinator 0:bb348c97df44 154 SPI5_IRQn = 85 /*!< SPI5 global Interrupt */
lypinator 0:bb348c97df44 155 } IRQn_Type;
lypinator 0:bb348c97df44 156
lypinator 0:bb348c97df44 157 /**
lypinator 0:bb348c97df44 158 * @}
lypinator 0:bb348c97df44 159 */
lypinator 0:bb348c97df44 160
lypinator 0:bb348c97df44 161 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
lypinator 0:bb348c97df44 162 #include "system_stm32f4xx.h"
lypinator 0:bb348c97df44 163 #include <stdint.h>
lypinator 0:bb348c97df44 164
lypinator 0:bb348c97df44 165 /** @addtogroup Peripheral_registers_structures
lypinator 0:bb348c97df44 166 * @{
lypinator 0:bb348c97df44 167 */
lypinator 0:bb348c97df44 168
lypinator 0:bb348c97df44 169 /**
lypinator 0:bb348c97df44 170 * @brief Analog to Digital Converter
lypinator 0:bb348c97df44 171 */
lypinator 0:bb348c97df44 172
lypinator 0:bb348c97df44 173 typedef struct
lypinator 0:bb348c97df44 174 {
lypinator 0:bb348c97df44 175 __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
lypinator 0:bb348c97df44 176 __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
lypinator 0:bb348c97df44 177 __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
lypinator 0:bb348c97df44 178 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
lypinator 0:bb348c97df44 179 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
lypinator 0:bb348c97df44 180 __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
lypinator 0:bb348c97df44 181 __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
lypinator 0:bb348c97df44 182 __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
lypinator 0:bb348c97df44 183 __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
lypinator 0:bb348c97df44 184 __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
lypinator 0:bb348c97df44 185 __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
lypinator 0:bb348c97df44 186 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
lypinator 0:bb348c97df44 187 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
lypinator 0:bb348c97df44 188 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
lypinator 0:bb348c97df44 189 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
lypinator 0:bb348c97df44 190 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
lypinator 0:bb348c97df44 191 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
lypinator 0:bb348c97df44 192 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
lypinator 0:bb348c97df44 193 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
lypinator 0:bb348c97df44 194 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
lypinator 0:bb348c97df44 195 } ADC_TypeDef;
lypinator 0:bb348c97df44 196
lypinator 0:bb348c97df44 197 typedef struct
lypinator 0:bb348c97df44 198 {
lypinator 0:bb348c97df44 199 __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
lypinator 0:bb348c97df44 200 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
lypinator 0:bb348c97df44 201 __IO uint32_t CDR; /*!< ADC common regular data register for dual
lypinator 0:bb348c97df44 202 AND triple modes, Address offset: ADC1 base address + 0x308 */
lypinator 0:bb348c97df44 203 } ADC_Common_TypeDef;
lypinator 0:bb348c97df44 204
lypinator 0:bb348c97df44 205 /**
lypinator 0:bb348c97df44 206 * @brief CRC calculation unit
lypinator 0:bb348c97df44 207 */
lypinator 0:bb348c97df44 208
lypinator 0:bb348c97df44 209 typedef struct
lypinator 0:bb348c97df44 210 {
lypinator 0:bb348c97df44 211 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
lypinator 0:bb348c97df44 212 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
lypinator 0:bb348c97df44 213 uint8_t RESERVED0; /*!< Reserved, 0x05 */
lypinator 0:bb348c97df44 214 uint16_t RESERVED1; /*!< Reserved, 0x06 */
lypinator 0:bb348c97df44 215 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
lypinator 0:bb348c97df44 216 } CRC_TypeDef;
lypinator 0:bb348c97df44 217
lypinator 0:bb348c97df44 218 /**
lypinator 0:bb348c97df44 219 * @brief Debug MCU
lypinator 0:bb348c97df44 220 */
lypinator 0:bb348c97df44 221
lypinator 0:bb348c97df44 222 typedef struct
lypinator 0:bb348c97df44 223 {
lypinator 0:bb348c97df44 224 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
lypinator 0:bb348c97df44 225 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
lypinator 0:bb348c97df44 226 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
lypinator 0:bb348c97df44 227 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
lypinator 0:bb348c97df44 228 }DBGMCU_TypeDef;
lypinator 0:bb348c97df44 229
lypinator 0:bb348c97df44 230
lypinator 0:bb348c97df44 231 /**
lypinator 0:bb348c97df44 232 * @brief DMA Controller
lypinator 0:bb348c97df44 233 */
lypinator 0:bb348c97df44 234
lypinator 0:bb348c97df44 235 typedef struct
lypinator 0:bb348c97df44 236 {
lypinator 0:bb348c97df44 237 __IO uint32_t CR; /*!< DMA stream x configuration register */
lypinator 0:bb348c97df44 238 __IO uint32_t NDTR; /*!< DMA stream x number of data register */
lypinator 0:bb348c97df44 239 __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
lypinator 0:bb348c97df44 240 __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
lypinator 0:bb348c97df44 241 __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
lypinator 0:bb348c97df44 242 __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
lypinator 0:bb348c97df44 243 } DMA_Stream_TypeDef;
lypinator 0:bb348c97df44 244
lypinator 0:bb348c97df44 245 typedef struct
lypinator 0:bb348c97df44 246 {
lypinator 0:bb348c97df44 247 __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
lypinator 0:bb348c97df44 248 __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
lypinator 0:bb348c97df44 249 __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
lypinator 0:bb348c97df44 250 __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
lypinator 0:bb348c97df44 251 } DMA_TypeDef;
lypinator 0:bb348c97df44 252
lypinator 0:bb348c97df44 253 /**
lypinator 0:bb348c97df44 254 * @brief External Interrupt/Event Controller
lypinator 0:bb348c97df44 255 */
lypinator 0:bb348c97df44 256
lypinator 0:bb348c97df44 257 typedef struct
lypinator 0:bb348c97df44 258 {
lypinator 0:bb348c97df44 259 __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
lypinator 0:bb348c97df44 260 __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
lypinator 0:bb348c97df44 261 __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
lypinator 0:bb348c97df44 262 __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
lypinator 0:bb348c97df44 263 __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
lypinator 0:bb348c97df44 264 __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
lypinator 0:bb348c97df44 265 } EXTI_TypeDef;
lypinator 0:bb348c97df44 266
lypinator 0:bb348c97df44 267 /**
lypinator 0:bb348c97df44 268 * @brief FLASH Registers
lypinator 0:bb348c97df44 269 */
lypinator 0:bb348c97df44 270
lypinator 0:bb348c97df44 271 typedef struct
lypinator 0:bb348c97df44 272 {
lypinator 0:bb348c97df44 273 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
lypinator 0:bb348c97df44 274 __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
lypinator 0:bb348c97df44 275 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
lypinator 0:bb348c97df44 276 __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
lypinator 0:bb348c97df44 277 __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
lypinator 0:bb348c97df44 278 __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
lypinator 0:bb348c97df44 279 __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
lypinator 0:bb348c97df44 280 } FLASH_TypeDef;
lypinator 0:bb348c97df44 281
lypinator 0:bb348c97df44 282 /**
lypinator 0:bb348c97df44 283 * @brief General Purpose I/O
lypinator 0:bb348c97df44 284 */
lypinator 0:bb348c97df44 285
lypinator 0:bb348c97df44 286 typedef struct
lypinator 0:bb348c97df44 287 {
lypinator 0:bb348c97df44 288 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
lypinator 0:bb348c97df44 289 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
lypinator 0:bb348c97df44 290 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
lypinator 0:bb348c97df44 291 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
lypinator 0:bb348c97df44 292 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
lypinator 0:bb348c97df44 293 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
lypinator 0:bb348c97df44 294 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
lypinator 0:bb348c97df44 295 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
lypinator 0:bb348c97df44 296 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
lypinator 0:bb348c97df44 297 } GPIO_TypeDef;
lypinator 0:bb348c97df44 298
lypinator 0:bb348c97df44 299 /**
lypinator 0:bb348c97df44 300 * @brief System configuration controller
lypinator 0:bb348c97df44 301 */
lypinator 0:bb348c97df44 302
lypinator 0:bb348c97df44 303 typedef struct
lypinator 0:bb348c97df44 304 {
lypinator 0:bb348c97df44 305 __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
lypinator 0:bb348c97df44 306 __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
lypinator 0:bb348c97df44 307 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
lypinator 0:bb348c97df44 308 uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
lypinator 0:bb348c97df44 309 __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
lypinator 0:bb348c97df44 310 } SYSCFG_TypeDef;
lypinator 0:bb348c97df44 311
lypinator 0:bb348c97df44 312 /**
lypinator 0:bb348c97df44 313 * @brief Inter-integrated Circuit Interface
lypinator 0:bb348c97df44 314 */
lypinator 0:bb348c97df44 315
lypinator 0:bb348c97df44 316 typedef struct
lypinator 0:bb348c97df44 317 {
lypinator 0:bb348c97df44 318 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
lypinator 0:bb348c97df44 319 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
lypinator 0:bb348c97df44 320 __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
lypinator 0:bb348c97df44 321 __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
lypinator 0:bb348c97df44 322 __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
lypinator 0:bb348c97df44 323 __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
lypinator 0:bb348c97df44 324 __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
lypinator 0:bb348c97df44 325 __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
lypinator 0:bb348c97df44 326 __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
lypinator 0:bb348c97df44 327 __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */
lypinator 0:bb348c97df44 328 } I2C_TypeDef;
lypinator 0:bb348c97df44 329
lypinator 0:bb348c97df44 330 /**
lypinator 0:bb348c97df44 331 * @brief Independent WATCHDOG
lypinator 0:bb348c97df44 332 */
lypinator 0:bb348c97df44 333
lypinator 0:bb348c97df44 334 typedef struct
lypinator 0:bb348c97df44 335 {
lypinator 0:bb348c97df44 336 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
lypinator 0:bb348c97df44 337 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
lypinator 0:bb348c97df44 338 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
lypinator 0:bb348c97df44 339 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
lypinator 0:bb348c97df44 340 } IWDG_TypeDef;
lypinator 0:bb348c97df44 341
lypinator 0:bb348c97df44 342
lypinator 0:bb348c97df44 343 /**
lypinator 0:bb348c97df44 344 * @brief Power Control
lypinator 0:bb348c97df44 345 */
lypinator 0:bb348c97df44 346
lypinator 0:bb348c97df44 347 typedef struct
lypinator 0:bb348c97df44 348 {
lypinator 0:bb348c97df44 349 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
lypinator 0:bb348c97df44 350 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
lypinator 0:bb348c97df44 351 } PWR_TypeDef;
lypinator 0:bb348c97df44 352
lypinator 0:bb348c97df44 353 /**
lypinator 0:bb348c97df44 354 * @brief Reset and Clock Control
lypinator 0:bb348c97df44 355 */
lypinator 0:bb348c97df44 356
lypinator 0:bb348c97df44 357 typedef struct
lypinator 0:bb348c97df44 358 {
lypinator 0:bb348c97df44 359 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
lypinator 0:bb348c97df44 360 __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
lypinator 0:bb348c97df44 361 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
lypinator 0:bb348c97df44 362 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
lypinator 0:bb348c97df44 363 __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
lypinator 0:bb348c97df44 364 __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
lypinator 0:bb348c97df44 365 __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
lypinator 0:bb348c97df44 366 uint32_t RESERVED0; /*!< Reserved, 0x1C */
lypinator 0:bb348c97df44 367 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
lypinator 0:bb348c97df44 368 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
lypinator 0:bb348c97df44 369 uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
lypinator 0:bb348c97df44 370 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
lypinator 0:bb348c97df44 371 __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
lypinator 0:bb348c97df44 372 __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
lypinator 0:bb348c97df44 373 uint32_t RESERVED2; /*!< Reserved, 0x3C */
lypinator 0:bb348c97df44 374 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
lypinator 0:bb348c97df44 375 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
lypinator 0:bb348c97df44 376 uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
lypinator 0:bb348c97df44 377 __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
lypinator 0:bb348c97df44 378 __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
lypinator 0:bb348c97df44 379 __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
lypinator 0:bb348c97df44 380 uint32_t RESERVED4; /*!< Reserved, 0x5C */
lypinator 0:bb348c97df44 381 __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
lypinator 0:bb348c97df44 382 __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
lypinator 0:bb348c97df44 383 uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
lypinator 0:bb348c97df44 384 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
lypinator 0:bb348c97df44 385 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
lypinator 0:bb348c97df44 386 uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
lypinator 0:bb348c97df44 387 __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
lypinator 0:bb348c97df44 388 __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
lypinator 0:bb348c97df44 389 uint32_t RESERVED7[1]; /*!< Reserved, 0x88 */
lypinator 0:bb348c97df44 390 __IO uint32_t DCKCFGR; /*!< RCC Dedicated Clocks configuration register, Address offset: 0x8C */
lypinator 0:bb348c97df44 391 } RCC_TypeDef;
lypinator 0:bb348c97df44 392
lypinator 0:bb348c97df44 393 /**
lypinator 0:bb348c97df44 394 * @brief Real-Time Clock
lypinator 0:bb348c97df44 395 */
lypinator 0:bb348c97df44 396
lypinator 0:bb348c97df44 397 typedef struct
lypinator 0:bb348c97df44 398 {
lypinator 0:bb348c97df44 399 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
lypinator 0:bb348c97df44 400 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
lypinator 0:bb348c97df44 401 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
lypinator 0:bb348c97df44 402 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
lypinator 0:bb348c97df44 403 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
lypinator 0:bb348c97df44 404 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
lypinator 0:bb348c97df44 405 __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
lypinator 0:bb348c97df44 406 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
lypinator 0:bb348c97df44 407 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
lypinator 0:bb348c97df44 408 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
lypinator 0:bb348c97df44 409 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
lypinator 0:bb348c97df44 410 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
lypinator 0:bb348c97df44 411 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
lypinator 0:bb348c97df44 412 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
lypinator 0:bb348c97df44 413 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
lypinator 0:bb348c97df44 414 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
lypinator 0:bb348c97df44 415 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
lypinator 0:bb348c97df44 416 __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
lypinator 0:bb348c97df44 417 __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
lypinator 0:bb348c97df44 418 uint32_t RESERVED7; /*!< Reserved, 0x4C */
lypinator 0:bb348c97df44 419 __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
lypinator 0:bb348c97df44 420 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
lypinator 0:bb348c97df44 421 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
lypinator 0:bb348c97df44 422 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
lypinator 0:bb348c97df44 423 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
lypinator 0:bb348c97df44 424 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
lypinator 0:bb348c97df44 425 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
lypinator 0:bb348c97df44 426 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
lypinator 0:bb348c97df44 427 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
lypinator 0:bb348c97df44 428 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
lypinator 0:bb348c97df44 429 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
lypinator 0:bb348c97df44 430 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
lypinator 0:bb348c97df44 431 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
lypinator 0:bb348c97df44 432 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
lypinator 0:bb348c97df44 433 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
lypinator 0:bb348c97df44 434 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
lypinator 0:bb348c97df44 435 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
lypinator 0:bb348c97df44 436 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
lypinator 0:bb348c97df44 437 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
lypinator 0:bb348c97df44 438 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
lypinator 0:bb348c97df44 439 } RTC_TypeDef;
lypinator 0:bb348c97df44 440
lypinator 0:bb348c97df44 441 /**
lypinator 0:bb348c97df44 442 * @brief SD host Interface
lypinator 0:bb348c97df44 443 */
lypinator 0:bb348c97df44 444
lypinator 0:bb348c97df44 445 typedef struct
lypinator 0:bb348c97df44 446 {
lypinator 0:bb348c97df44 447 __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
lypinator 0:bb348c97df44 448 __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
lypinator 0:bb348c97df44 449 __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
lypinator 0:bb348c97df44 450 __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
lypinator 0:bb348c97df44 451 __IO const uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
lypinator 0:bb348c97df44 452 __IO const uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
lypinator 0:bb348c97df44 453 __IO const uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
lypinator 0:bb348c97df44 454 __IO const uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
lypinator 0:bb348c97df44 455 __IO const uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
lypinator 0:bb348c97df44 456 __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
lypinator 0:bb348c97df44 457 __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
lypinator 0:bb348c97df44 458 __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
lypinator 0:bb348c97df44 459 __IO const uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
lypinator 0:bb348c97df44 460 __IO const uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
lypinator 0:bb348c97df44 461 __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
lypinator 0:bb348c97df44 462 __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
lypinator 0:bb348c97df44 463 uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
lypinator 0:bb348c97df44 464 __IO const uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
lypinator 0:bb348c97df44 465 uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
lypinator 0:bb348c97df44 466 __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
lypinator 0:bb348c97df44 467 } SDIO_TypeDef;
lypinator 0:bb348c97df44 468
lypinator 0:bb348c97df44 469 /**
lypinator 0:bb348c97df44 470 * @brief Serial Peripheral Interface
lypinator 0:bb348c97df44 471 */
lypinator 0:bb348c97df44 472
lypinator 0:bb348c97df44 473 typedef struct
lypinator 0:bb348c97df44 474 {
lypinator 0:bb348c97df44 475 __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
lypinator 0:bb348c97df44 476 __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
lypinator 0:bb348c97df44 477 __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
lypinator 0:bb348c97df44 478 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
lypinator 0:bb348c97df44 479 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
lypinator 0:bb348c97df44 480 __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
lypinator 0:bb348c97df44 481 __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
lypinator 0:bb348c97df44 482 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
lypinator 0:bb348c97df44 483 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
lypinator 0:bb348c97df44 484 } SPI_TypeDef;
lypinator 0:bb348c97df44 485
lypinator 0:bb348c97df44 486
lypinator 0:bb348c97df44 487 /**
lypinator 0:bb348c97df44 488 * @brief TIM
lypinator 0:bb348c97df44 489 */
lypinator 0:bb348c97df44 490
lypinator 0:bb348c97df44 491 typedef struct
lypinator 0:bb348c97df44 492 {
lypinator 0:bb348c97df44 493 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
lypinator 0:bb348c97df44 494 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
lypinator 0:bb348c97df44 495 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
lypinator 0:bb348c97df44 496 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
lypinator 0:bb348c97df44 497 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
lypinator 0:bb348c97df44 498 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
lypinator 0:bb348c97df44 499 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
lypinator 0:bb348c97df44 500 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
lypinator 0:bb348c97df44 501 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
lypinator 0:bb348c97df44 502 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
lypinator 0:bb348c97df44 503 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
lypinator 0:bb348c97df44 504 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
lypinator 0:bb348c97df44 505 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
lypinator 0:bb348c97df44 506 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
lypinator 0:bb348c97df44 507 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
lypinator 0:bb348c97df44 508 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
lypinator 0:bb348c97df44 509 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
lypinator 0:bb348c97df44 510 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
lypinator 0:bb348c97df44 511 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
lypinator 0:bb348c97df44 512 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
lypinator 0:bb348c97df44 513 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
lypinator 0:bb348c97df44 514 } TIM_TypeDef;
lypinator 0:bb348c97df44 515
lypinator 0:bb348c97df44 516 /**
lypinator 0:bb348c97df44 517 * @brief Universal Synchronous Asynchronous Receiver Transmitter
lypinator 0:bb348c97df44 518 */
lypinator 0:bb348c97df44 519
lypinator 0:bb348c97df44 520 typedef struct
lypinator 0:bb348c97df44 521 {
lypinator 0:bb348c97df44 522 __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
lypinator 0:bb348c97df44 523 __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
lypinator 0:bb348c97df44 524 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
lypinator 0:bb348c97df44 525 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
lypinator 0:bb348c97df44 526 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
lypinator 0:bb348c97df44 527 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
lypinator 0:bb348c97df44 528 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
lypinator 0:bb348c97df44 529 } USART_TypeDef;
lypinator 0:bb348c97df44 530
lypinator 0:bb348c97df44 531 /**
lypinator 0:bb348c97df44 532 * @brief Window WATCHDOG
lypinator 0:bb348c97df44 533 */
lypinator 0:bb348c97df44 534
lypinator 0:bb348c97df44 535 typedef struct
lypinator 0:bb348c97df44 536 {
lypinator 0:bb348c97df44 537 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
lypinator 0:bb348c97df44 538 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
lypinator 0:bb348c97df44 539 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
lypinator 0:bb348c97df44 540 } WWDG_TypeDef;
lypinator 0:bb348c97df44 541 /**
lypinator 0:bb348c97df44 542 * @brief USB_OTG_Core_Registers
lypinator 0:bb348c97df44 543 */
lypinator 0:bb348c97df44 544 typedef struct
lypinator 0:bb348c97df44 545 {
lypinator 0:bb348c97df44 546 __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */
lypinator 0:bb348c97df44 547 __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */
lypinator 0:bb348c97df44 548 __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */
lypinator 0:bb348c97df44 549 __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */
lypinator 0:bb348c97df44 550 __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */
lypinator 0:bb348c97df44 551 __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */
lypinator 0:bb348c97df44 552 __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */
lypinator 0:bb348c97df44 553 __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */
lypinator 0:bb348c97df44 554 __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */
lypinator 0:bb348c97df44 555 __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */
lypinator 0:bb348c97df44 556 __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */
lypinator 0:bb348c97df44 557 __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */
lypinator 0:bb348c97df44 558 uint32_t Reserved30[2]; /*!< Reserved 030h */
lypinator 0:bb348c97df44 559 __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */
lypinator 0:bb348c97df44 560 __IO uint32_t CID; /*!< User ID Register 03Ch */
lypinator 0:bb348c97df44 561 uint32_t Reserved40[48]; /*!< Reserved 0x40-0xFF */
lypinator 0:bb348c97df44 562 __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */
lypinator 0:bb348c97df44 563 __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
lypinator 0:bb348c97df44 564 } USB_OTG_GlobalTypeDef;
lypinator 0:bb348c97df44 565
lypinator 0:bb348c97df44 566 /**
lypinator 0:bb348c97df44 567 * @brief USB_OTG_device_Registers
lypinator 0:bb348c97df44 568 */
lypinator 0:bb348c97df44 569 typedef struct
lypinator 0:bb348c97df44 570 {
lypinator 0:bb348c97df44 571 __IO uint32_t DCFG; /*!< dev Configuration Register 800h */
lypinator 0:bb348c97df44 572 __IO uint32_t DCTL; /*!< dev Control Register 804h */
lypinator 0:bb348c97df44 573 __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */
lypinator 0:bb348c97df44 574 uint32_t Reserved0C; /*!< Reserved 80Ch */
lypinator 0:bb348c97df44 575 __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */
lypinator 0:bb348c97df44 576 __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */
lypinator 0:bb348c97df44 577 __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */
lypinator 0:bb348c97df44 578 __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */
lypinator 0:bb348c97df44 579 uint32_t Reserved20; /*!< Reserved 820h */
lypinator 0:bb348c97df44 580 uint32_t Reserved9; /*!< Reserved 824h */
lypinator 0:bb348c97df44 581 __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */
lypinator 0:bb348c97df44 582 __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */
lypinator 0:bb348c97df44 583 __IO uint32_t DTHRCTL; /*!< dev threshold 830h */
lypinator 0:bb348c97df44 584 __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */
lypinator 0:bb348c97df44 585 __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */
lypinator 0:bb348c97df44 586 __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */
lypinator 0:bb348c97df44 587 uint32_t Reserved40; /*!< dedicated EP mask 840h */
lypinator 0:bb348c97df44 588 __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */
lypinator 0:bb348c97df44 589 uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */
lypinator 0:bb348c97df44 590 __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */
lypinator 0:bb348c97df44 591 } USB_OTG_DeviceTypeDef;
lypinator 0:bb348c97df44 592
lypinator 0:bb348c97df44 593 /**
lypinator 0:bb348c97df44 594 * @brief USB_OTG_IN_Endpoint-Specific_Register
lypinator 0:bb348c97df44 595 */
lypinator 0:bb348c97df44 596 typedef struct
lypinator 0:bb348c97df44 597 {
lypinator 0:bb348c97df44 598 __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
lypinator 0:bb348c97df44 599 uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */
lypinator 0:bb348c97df44 600 __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
lypinator 0:bb348c97df44 601 uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */
lypinator 0:bb348c97df44 602 __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
lypinator 0:bb348c97df44 603 __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
lypinator 0:bb348c97df44 604 __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
lypinator 0:bb348c97df44 605 uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
lypinator 0:bb348c97df44 606 } USB_OTG_INEndpointTypeDef;
lypinator 0:bb348c97df44 607
lypinator 0:bb348c97df44 608 /**
lypinator 0:bb348c97df44 609 * @brief USB_OTG_OUT_Endpoint-Specific_Registers
lypinator 0:bb348c97df44 610 */
lypinator 0:bb348c97df44 611 typedef struct
lypinator 0:bb348c97df44 612 {
lypinator 0:bb348c97df44 613 __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */
lypinator 0:bb348c97df44 614 uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */
lypinator 0:bb348c97df44 615 __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */
lypinator 0:bb348c97df44 616 uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */
lypinator 0:bb348c97df44 617 __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */
lypinator 0:bb348c97df44 618 __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */
lypinator 0:bb348c97df44 619 uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
lypinator 0:bb348c97df44 620 } USB_OTG_OUTEndpointTypeDef;
lypinator 0:bb348c97df44 621
lypinator 0:bb348c97df44 622 /**
lypinator 0:bb348c97df44 623 * @brief USB_OTG_Host_Mode_Register_Structures
lypinator 0:bb348c97df44 624 */
lypinator 0:bb348c97df44 625 typedef struct
lypinator 0:bb348c97df44 626 {
lypinator 0:bb348c97df44 627 __IO uint32_t HCFG; /*!< Host Configuration Register 400h */
lypinator 0:bb348c97df44 628 __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */
lypinator 0:bb348c97df44 629 __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */
lypinator 0:bb348c97df44 630 uint32_t Reserved40C; /*!< Reserved 40Ch */
lypinator 0:bb348c97df44 631 __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */
lypinator 0:bb348c97df44 632 __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */
lypinator 0:bb348c97df44 633 __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */
lypinator 0:bb348c97df44 634 } USB_OTG_HostTypeDef;
lypinator 0:bb348c97df44 635
lypinator 0:bb348c97df44 636 /**
lypinator 0:bb348c97df44 637 * @brief USB_OTG_Host_Channel_Specific_Registers
lypinator 0:bb348c97df44 638 */
lypinator 0:bb348c97df44 639 typedef struct
lypinator 0:bb348c97df44 640 {
lypinator 0:bb348c97df44 641 __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */
lypinator 0:bb348c97df44 642 __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */
lypinator 0:bb348c97df44 643 __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */
lypinator 0:bb348c97df44 644 __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */
lypinator 0:bb348c97df44 645 __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */
lypinator 0:bb348c97df44 646 __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */
lypinator 0:bb348c97df44 647 uint32_t Reserved[2]; /*!< Reserved */
lypinator 0:bb348c97df44 648 } USB_OTG_HostChannelTypeDef;
lypinator 0:bb348c97df44 649
lypinator 0:bb348c97df44 650 /**
lypinator 0:bb348c97df44 651 * @}
lypinator 0:bb348c97df44 652 */
lypinator 0:bb348c97df44 653
lypinator 0:bb348c97df44 654 /** @addtogroup Peripheral_memory_map
lypinator 0:bb348c97df44 655 * @{
lypinator 0:bb348c97df44 656 */
lypinator 0:bb348c97df44 657 #define FLASH_BASE 0x08000000U /*!< FLASH(up to 1 MB) base address in the alias region */
lypinator 0:bb348c97df44 658 #define SRAM1_BASE 0x20000000U /*!< SRAM1(128 KB) base address in the alias region */
lypinator 0:bb348c97df44 659 #define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */
lypinator 0:bb348c97df44 660 #define BKPSRAM_BASE 0x40024000U /*!< Backup SRAM(4 KB) base address in the alias region */
lypinator 0:bb348c97df44 661 #define SRAM1_BB_BASE 0x22000000U /*!< SRAM1(128 KB) base address in the bit-band region */
lypinator 0:bb348c97df44 662 #define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */
lypinator 0:bb348c97df44 663 #define BKPSRAM_BB_BASE 0x42480000U /*!< Backup SRAM(4 KB) base address in the bit-band region */
lypinator 0:bb348c97df44 664 #define FLASH_END 0x0807FFFFU /*!< FLASH end address */
lypinator 0:bb348c97df44 665 #define FLASH_OTP_BASE 0x1FFF7800U /*!< Base address of : (up to 528 Bytes) embedded FLASH OTP Area */
lypinator 0:bb348c97df44 666 #define FLASH_OTP_END 0x1FFF7A0FU /*!< End address of : (up to 528 Bytes) embedded FLASH OTP Area */
lypinator 0:bb348c97df44 667
lypinator 0:bb348c97df44 668 /* Legacy defines */
lypinator 0:bb348c97df44 669 #define SRAM_BASE SRAM1_BASE
lypinator 0:bb348c97df44 670 #define SRAM_BB_BASE SRAM1_BB_BASE
lypinator 0:bb348c97df44 671
lypinator 0:bb348c97df44 672 /*!< Peripheral memory map */
lypinator 0:bb348c97df44 673 #define APB1PERIPH_BASE PERIPH_BASE
lypinator 0:bb348c97df44 674 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
lypinator 0:bb348c97df44 675 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
lypinator 0:bb348c97df44 676 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)
lypinator 0:bb348c97df44 677
lypinator 0:bb348c97df44 678 /*!< APB1 peripherals */
lypinator 0:bb348c97df44 679 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
lypinator 0:bb348c97df44 680 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)
lypinator 0:bb348c97df44 681 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800U)
lypinator 0:bb348c97df44 682 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
lypinator 0:bb348c97df44 683 #define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
lypinator 0:bb348c97df44 684 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
lypinator 0:bb348c97df44 685 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
lypinator 0:bb348c97df44 686 #define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400U)
lypinator 0:bb348c97df44 687 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
lypinator 0:bb348c97df44 688 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
lypinator 0:bb348c97df44 689 #define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000U)
lypinator 0:bb348c97df44 690 #define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
lypinator 0:bb348c97df44 691 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
lypinator 0:bb348c97df44 692 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
lypinator 0:bb348c97df44 693 #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
lypinator 0:bb348c97df44 694 #define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
lypinator 0:bb348c97df44 695
lypinator 0:bb348c97df44 696 /*!< APB2 peripherals */
lypinator 0:bb348c97df44 697 #define TIM1_BASE (APB2PERIPH_BASE + 0x0000U)
lypinator 0:bb348c97df44 698 #define USART1_BASE (APB2PERIPH_BASE + 0x1000U)
lypinator 0:bb348c97df44 699 #define USART6_BASE (APB2PERIPH_BASE + 0x1400U)
lypinator 0:bb348c97df44 700 #define ADC1_BASE (APB2PERIPH_BASE + 0x2000U)
lypinator 0:bb348c97df44 701 #define ADC1_COMMON_BASE (APB2PERIPH_BASE + 0x2300U)
lypinator 0:bb348c97df44 702 /* Legacy define */
lypinator 0:bb348c97df44 703 #define ADC_BASE ADC1_COMMON_BASE
lypinator 0:bb348c97df44 704 #define SDIO_BASE (APB2PERIPH_BASE + 0x2C00U)
lypinator 0:bb348c97df44 705 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
lypinator 0:bb348c97df44 706 #define SPI4_BASE (APB2PERIPH_BASE + 0x3400U)
lypinator 0:bb348c97df44 707 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)
lypinator 0:bb348c97df44 708 #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)
lypinator 0:bb348c97df44 709 #define TIM9_BASE (APB2PERIPH_BASE + 0x4000U)
lypinator 0:bb348c97df44 710 #define TIM10_BASE (APB2PERIPH_BASE + 0x4400U)
lypinator 0:bb348c97df44 711 #define TIM11_BASE (APB2PERIPH_BASE + 0x4800U)
lypinator 0:bb348c97df44 712 #define SPI5_BASE (APB2PERIPH_BASE + 0x5000U)
lypinator 0:bb348c97df44 713
lypinator 0:bb348c97df44 714 /*!< AHB1 peripherals */
lypinator 0:bb348c97df44 715 #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)
lypinator 0:bb348c97df44 716 #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)
lypinator 0:bb348c97df44 717 #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)
lypinator 0:bb348c97df44 718 #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U)
lypinator 0:bb348c97df44 719 #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U)
lypinator 0:bb348c97df44 720 #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)
lypinator 0:bb348c97df44 721 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
lypinator 0:bb348c97df44 722 #define RCC_BASE (AHB1PERIPH_BASE + 0x3800U)
lypinator 0:bb348c97df44 723 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)
lypinator 0:bb348c97df44 724 #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)
lypinator 0:bb348c97df44 725 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010U)
lypinator 0:bb348c97df44 726 #define DMA1_Stream1_BASE (DMA1_BASE + 0x028U)
lypinator 0:bb348c97df44 727 #define DMA1_Stream2_BASE (DMA1_BASE + 0x040U)
lypinator 0:bb348c97df44 728 #define DMA1_Stream3_BASE (DMA1_BASE + 0x058U)
lypinator 0:bb348c97df44 729 #define DMA1_Stream4_BASE (DMA1_BASE + 0x070U)
lypinator 0:bb348c97df44 730 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088U)
lypinator 0:bb348c97df44 731 #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)
lypinator 0:bb348c97df44 732 #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)
lypinator 0:bb348c97df44 733 #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)
lypinator 0:bb348c97df44 734 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010U)
lypinator 0:bb348c97df44 735 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028U)
lypinator 0:bb348c97df44 736 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040U)
lypinator 0:bb348c97df44 737 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058U)
lypinator 0:bb348c97df44 738 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070U)
lypinator 0:bb348c97df44 739 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088U)
lypinator 0:bb348c97df44 740 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)
lypinator 0:bb348c97df44 741 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)
lypinator 0:bb348c97df44 742
lypinator 0:bb348c97df44 743
lypinator 0:bb348c97df44 744 /*!< Debug MCU registers base address */
lypinator 0:bb348c97df44 745 #define DBGMCU_BASE 0xE0042000U
lypinator 0:bb348c97df44 746 /*!< USB registers base address */
lypinator 0:bb348c97df44 747 #define USB_OTG_FS_PERIPH_BASE 0x50000000U
lypinator 0:bb348c97df44 748
lypinator 0:bb348c97df44 749 #define USB_OTG_GLOBAL_BASE 0x000U
lypinator 0:bb348c97df44 750 #define USB_OTG_DEVICE_BASE 0x800U
lypinator 0:bb348c97df44 751 #define USB_OTG_IN_ENDPOINT_BASE 0x900U
lypinator 0:bb348c97df44 752 #define USB_OTG_OUT_ENDPOINT_BASE 0xB00U
lypinator 0:bb348c97df44 753 #define USB_OTG_EP_REG_SIZE 0x20U
lypinator 0:bb348c97df44 754 #define USB_OTG_HOST_BASE 0x400U
lypinator 0:bb348c97df44 755 #define USB_OTG_HOST_PORT_BASE 0x440U
lypinator 0:bb348c97df44 756 #define USB_OTG_HOST_CHANNEL_BASE 0x500U
lypinator 0:bb348c97df44 757 #define USB_OTG_HOST_CHANNEL_SIZE 0x20U
lypinator 0:bb348c97df44 758 #define USB_OTG_PCGCCTL_BASE 0xE00U
lypinator 0:bb348c97df44 759 #define USB_OTG_FIFO_BASE 0x1000U
lypinator 0:bb348c97df44 760 #define USB_OTG_FIFO_SIZE 0x1000U
lypinator 0:bb348c97df44 761
lypinator 0:bb348c97df44 762 #define UID_BASE 0x1FFF7A10U /*!< Unique device ID register base address */
lypinator 0:bb348c97df44 763 #define FLASHSIZE_BASE 0x1FFF7A22U /*!< FLASH Size register base address */
lypinator 0:bb348c97df44 764 #define PACKAGE_BASE 0x1FFF7BF0U /*!< Package size register base address */
lypinator 0:bb348c97df44 765 /**
lypinator 0:bb348c97df44 766 * @}
lypinator 0:bb348c97df44 767 */
lypinator 0:bb348c97df44 768
lypinator 0:bb348c97df44 769 /** @addtogroup Peripheral_declaration
lypinator 0:bb348c97df44 770 * @{
lypinator 0:bb348c97df44 771 */
lypinator 0:bb348c97df44 772 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
lypinator 0:bb348c97df44 773 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
lypinator 0:bb348c97df44 774 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
lypinator 0:bb348c97df44 775 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
lypinator 0:bb348c97df44 776 #define RTC ((RTC_TypeDef *) RTC_BASE)
lypinator 0:bb348c97df44 777 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
lypinator 0:bb348c97df44 778 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
lypinator 0:bb348c97df44 779 #define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
lypinator 0:bb348c97df44 780 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
lypinator 0:bb348c97df44 781 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
lypinator 0:bb348c97df44 782 #define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
lypinator 0:bb348c97df44 783 #define USART2 ((USART_TypeDef *) USART2_BASE)
lypinator 0:bb348c97df44 784 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
lypinator 0:bb348c97df44 785 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
lypinator 0:bb348c97df44 786 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
lypinator 0:bb348c97df44 787 #define PWR ((PWR_TypeDef *) PWR_BASE)
lypinator 0:bb348c97df44 788 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
lypinator 0:bb348c97df44 789 #define USART1 ((USART_TypeDef *) USART1_BASE)
lypinator 0:bb348c97df44 790 #define USART6 ((USART_TypeDef *) USART6_BASE)
lypinator 0:bb348c97df44 791 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
lypinator 0:bb348c97df44 792 #define ADC1_COMMON ((ADC_Common_TypeDef *) ADC1_COMMON_BASE)
lypinator 0:bb348c97df44 793 /* Legacy define */
lypinator 0:bb348c97df44 794 #define ADC ADC1_COMMON
lypinator 0:bb348c97df44 795 #define SDIO ((SDIO_TypeDef *) SDIO_BASE)
lypinator 0:bb348c97df44 796 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
lypinator 0:bb348c97df44 797 #define SPI4 ((SPI_TypeDef *) SPI4_BASE)
lypinator 0:bb348c97df44 798 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
lypinator 0:bb348c97df44 799 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
lypinator 0:bb348c97df44 800 #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
lypinator 0:bb348c97df44 801 #define TIM10 ((TIM_TypeDef *) TIM10_BASE)
lypinator 0:bb348c97df44 802 #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
lypinator 0:bb348c97df44 803 #define SPI5 ((SPI_TypeDef *) SPI5_BASE)
lypinator 0:bb348c97df44 804 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
lypinator 0:bb348c97df44 805 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
lypinator 0:bb348c97df44 806 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
lypinator 0:bb348c97df44 807 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
lypinator 0:bb348c97df44 808 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
lypinator 0:bb348c97df44 809 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
lypinator 0:bb348c97df44 810 #define CRC ((CRC_TypeDef *) CRC_BASE)
lypinator 0:bb348c97df44 811 #define RCC ((RCC_TypeDef *) RCC_BASE)
lypinator 0:bb348c97df44 812 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
lypinator 0:bb348c97df44 813 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
lypinator 0:bb348c97df44 814 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
lypinator 0:bb348c97df44 815 #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
lypinator 0:bb348c97df44 816 #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
lypinator 0:bb348c97df44 817 #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
lypinator 0:bb348c97df44 818 #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
lypinator 0:bb348c97df44 819 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
lypinator 0:bb348c97df44 820 #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
lypinator 0:bb348c97df44 821 #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
lypinator 0:bb348c97df44 822 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
lypinator 0:bb348c97df44 823 #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
lypinator 0:bb348c97df44 824 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
lypinator 0:bb348c97df44 825 #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
lypinator 0:bb348c97df44 826 #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
lypinator 0:bb348c97df44 827 #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
lypinator 0:bb348c97df44 828 #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
lypinator 0:bb348c97df44 829 #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
lypinator 0:bb348c97df44 830 #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
lypinator 0:bb348c97df44 831 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
lypinator 0:bb348c97df44 832 #define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
lypinator 0:bb348c97df44 833
lypinator 0:bb348c97df44 834 /**
lypinator 0:bb348c97df44 835 * @}
lypinator 0:bb348c97df44 836 */
lypinator 0:bb348c97df44 837
lypinator 0:bb348c97df44 838 /** @addtogroup Exported_constants
lypinator 0:bb348c97df44 839 * @{
lypinator 0:bb348c97df44 840 */
lypinator 0:bb348c97df44 841
lypinator 0:bb348c97df44 842 /** @addtogroup Peripheral_Registers_Bits_Definition
lypinator 0:bb348c97df44 843 * @{
lypinator 0:bb348c97df44 844 */
lypinator 0:bb348c97df44 845
lypinator 0:bb348c97df44 846 /******************************************************************************/
lypinator 0:bb348c97df44 847 /* Peripheral Registers_Bits_Definition */
lypinator 0:bb348c97df44 848 /******************************************************************************/
lypinator 0:bb348c97df44 849
lypinator 0:bb348c97df44 850 /******************************************************************************/
lypinator 0:bb348c97df44 851 /* */
lypinator 0:bb348c97df44 852 /* Analog to Digital Converter */
lypinator 0:bb348c97df44 853 /* */
lypinator 0:bb348c97df44 854 /******************************************************************************/
lypinator 0:bb348c97df44 855
lypinator 0:bb348c97df44 856 /******************** Bit definition for ADC_SR register ********************/
lypinator 0:bb348c97df44 857 #define ADC_SR_AWD_Pos (0U)
lypinator 0:bb348c97df44 858 #define ADC_SR_AWD_Msk (0x1U << ADC_SR_AWD_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 859 #define ADC_SR_AWD ADC_SR_AWD_Msk /*!<Analog watchdog flag */
lypinator 0:bb348c97df44 860 #define ADC_SR_EOC_Pos (1U)
lypinator 0:bb348c97df44 861 #define ADC_SR_EOC_Msk (0x1U << ADC_SR_EOC_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 862 #define ADC_SR_EOC ADC_SR_EOC_Msk /*!<End of conversion */
lypinator 0:bb348c97df44 863 #define ADC_SR_JEOC_Pos (2U)
lypinator 0:bb348c97df44 864 #define ADC_SR_JEOC_Msk (0x1U << ADC_SR_JEOC_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 865 #define ADC_SR_JEOC ADC_SR_JEOC_Msk /*!<Injected channel end of conversion */
lypinator 0:bb348c97df44 866 #define ADC_SR_JSTRT_Pos (3U)
lypinator 0:bb348c97df44 867 #define ADC_SR_JSTRT_Msk (0x1U << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 868 #define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!<Injected channel Start flag */
lypinator 0:bb348c97df44 869 #define ADC_SR_STRT_Pos (4U)
lypinator 0:bb348c97df44 870 #define ADC_SR_STRT_Msk (0x1U << ADC_SR_STRT_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 871 #define ADC_SR_STRT ADC_SR_STRT_Msk /*!<Regular channel Start flag */
lypinator 0:bb348c97df44 872 #define ADC_SR_OVR_Pos (5U)
lypinator 0:bb348c97df44 873 #define ADC_SR_OVR_Msk (0x1U << ADC_SR_OVR_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 874 #define ADC_SR_OVR ADC_SR_OVR_Msk /*!<Overrun flag */
lypinator 0:bb348c97df44 875
lypinator 0:bb348c97df44 876 /******************* Bit definition for ADC_CR1 register ********************/
lypinator 0:bb348c97df44 877 #define ADC_CR1_AWDCH_Pos (0U)
lypinator 0:bb348c97df44 878 #define ADC_CR1_AWDCH_Msk (0x1FU << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */
lypinator 0:bb348c97df44 879 #define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
lypinator 0:bb348c97df44 880 #define ADC_CR1_AWDCH_0 (0x01U << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 881 #define ADC_CR1_AWDCH_1 (0x02U << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 882 #define ADC_CR1_AWDCH_2 (0x04U << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 883 #define ADC_CR1_AWDCH_3 (0x08U << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 884 #define ADC_CR1_AWDCH_4 (0x10U << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 885 #define ADC_CR1_EOCIE_Pos (5U)
lypinator 0:bb348c97df44 886 #define ADC_CR1_EOCIE_Msk (0x1U << ADC_CR1_EOCIE_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 887 #define ADC_CR1_EOCIE ADC_CR1_EOCIE_Msk /*!<Interrupt enable for EOC */
lypinator 0:bb348c97df44 888 #define ADC_CR1_AWDIE_Pos (6U)
lypinator 0:bb348c97df44 889 #define ADC_CR1_AWDIE_Msk (0x1U << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 890 #define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!<AAnalog Watchdog interrupt enable */
lypinator 0:bb348c97df44 891 #define ADC_CR1_JEOCIE_Pos (7U)
lypinator 0:bb348c97df44 892 #define ADC_CR1_JEOCIE_Msk (0x1U << ADC_CR1_JEOCIE_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 893 #define ADC_CR1_JEOCIE ADC_CR1_JEOCIE_Msk /*!<Interrupt enable for injected channels */
lypinator 0:bb348c97df44 894 #define ADC_CR1_SCAN_Pos (8U)
lypinator 0:bb348c97df44 895 #define ADC_CR1_SCAN_Msk (0x1U << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 896 #define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!<Scan mode */
lypinator 0:bb348c97df44 897 #define ADC_CR1_AWDSGL_Pos (9U)
lypinator 0:bb348c97df44 898 #define ADC_CR1_AWDSGL_Msk (0x1U << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 899 #define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!<Enable the watchdog on a single channel in scan mode */
lypinator 0:bb348c97df44 900 #define ADC_CR1_JAUTO_Pos (10U)
lypinator 0:bb348c97df44 901 #define ADC_CR1_JAUTO_Msk (0x1U << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 902 #define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!<Automatic injected group conversion */
lypinator 0:bb348c97df44 903 #define ADC_CR1_DISCEN_Pos (11U)
lypinator 0:bb348c97df44 904 #define ADC_CR1_DISCEN_Msk (0x1U << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 905 #define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!<Discontinuous mode on regular channels */
lypinator 0:bb348c97df44 906 #define ADC_CR1_JDISCEN_Pos (12U)
lypinator 0:bb348c97df44 907 #define ADC_CR1_JDISCEN_Msk (0x1U << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 908 #define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!<Discontinuous mode on injected channels */
lypinator 0:bb348c97df44 909 #define ADC_CR1_DISCNUM_Pos (13U)
lypinator 0:bb348c97df44 910 #define ADC_CR1_DISCNUM_Msk (0x7U << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */
lypinator 0:bb348c97df44 911 #define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
lypinator 0:bb348c97df44 912 #define ADC_CR1_DISCNUM_0 (0x1U << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 913 #define ADC_CR1_DISCNUM_1 (0x2U << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 914 #define ADC_CR1_DISCNUM_2 (0x4U << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 915 #define ADC_CR1_JAWDEN_Pos (22U)
lypinator 0:bb348c97df44 916 #define ADC_CR1_JAWDEN_Msk (0x1U << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 917 #define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!<Analog watchdog enable on injected channels */
lypinator 0:bb348c97df44 918 #define ADC_CR1_AWDEN_Pos (23U)
lypinator 0:bb348c97df44 919 #define ADC_CR1_AWDEN_Msk (0x1U << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */
lypinator 0:bb348c97df44 920 #define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!<Analog watchdog enable on regular channels */
lypinator 0:bb348c97df44 921 #define ADC_CR1_RES_Pos (24U)
lypinator 0:bb348c97df44 922 #define ADC_CR1_RES_Msk (0x3U << ADC_CR1_RES_Pos) /*!< 0x03000000 */
lypinator 0:bb348c97df44 923 #define ADC_CR1_RES ADC_CR1_RES_Msk /*!<RES[2:0] bits (Resolution) */
lypinator 0:bb348c97df44 924 #define ADC_CR1_RES_0 (0x1U << ADC_CR1_RES_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 925 #define ADC_CR1_RES_1 (0x2U << ADC_CR1_RES_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 926 #define ADC_CR1_OVRIE_Pos (26U)
lypinator 0:bb348c97df44 927 #define ADC_CR1_OVRIE_Msk (0x1U << ADC_CR1_OVRIE_Pos) /*!< 0x04000000 */
lypinator 0:bb348c97df44 928 #define ADC_CR1_OVRIE ADC_CR1_OVRIE_Msk /*!<overrun interrupt enable */
lypinator 0:bb348c97df44 929
lypinator 0:bb348c97df44 930 /******************* Bit definition for ADC_CR2 register ********************/
lypinator 0:bb348c97df44 931 #define ADC_CR2_ADON_Pos (0U)
lypinator 0:bb348c97df44 932 #define ADC_CR2_ADON_Msk (0x1U << ADC_CR2_ADON_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 933 #define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!<A/D Converter ON / OFF */
lypinator 0:bb348c97df44 934 #define ADC_CR2_CONT_Pos (1U)
lypinator 0:bb348c97df44 935 #define ADC_CR2_CONT_Msk (0x1U << ADC_CR2_CONT_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 936 #define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!<Continuous Conversion */
lypinator 0:bb348c97df44 937 #define ADC_CR2_DMA_Pos (8U)
lypinator 0:bb348c97df44 938 #define ADC_CR2_DMA_Msk (0x1U << ADC_CR2_DMA_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 939 #define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!<Direct Memory access mode */
lypinator 0:bb348c97df44 940 #define ADC_CR2_DDS_Pos (9U)
lypinator 0:bb348c97df44 941 #define ADC_CR2_DDS_Msk (0x1U << ADC_CR2_DDS_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 942 #define ADC_CR2_DDS ADC_CR2_DDS_Msk /*!<DMA disable selection (Single ADC) */
lypinator 0:bb348c97df44 943 #define ADC_CR2_EOCS_Pos (10U)
lypinator 0:bb348c97df44 944 #define ADC_CR2_EOCS_Msk (0x1U << ADC_CR2_EOCS_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 945 #define ADC_CR2_EOCS ADC_CR2_EOCS_Msk /*!<End of conversion selection */
lypinator 0:bb348c97df44 946 #define ADC_CR2_ALIGN_Pos (11U)
lypinator 0:bb348c97df44 947 #define ADC_CR2_ALIGN_Msk (0x1U << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 948 #define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!<Data Alignment */
lypinator 0:bb348c97df44 949 #define ADC_CR2_JEXTSEL_Pos (16U)
lypinator 0:bb348c97df44 950 #define ADC_CR2_JEXTSEL_Msk (0xFU << ADC_CR2_JEXTSEL_Pos) /*!< 0x000F0000 */
lypinator 0:bb348c97df44 951 #define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!<JEXTSEL[3:0] bits (External event select for injected group) */
lypinator 0:bb348c97df44 952 #define ADC_CR2_JEXTSEL_0 (0x1U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 953 #define ADC_CR2_JEXTSEL_1 (0x2U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 954 #define ADC_CR2_JEXTSEL_2 (0x4U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 955 #define ADC_CR2_JEXTSEL_3 (0x8U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 956 #define ADC_CR2_JEXTEN_Pos (20U)
lypinator 0:bb348c97df44 957 #define ADC_CR2_JEXTEN_Msk (0x3U << ADC_CR2_JEXTEN_Pos) /*!< 0x00300000 */
lypinator 0:bb348c97df44 958 #define ADC_CR2_JEXTEN ADC_CR2_JEXTEN_Msk /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
lypinator 0:bb348c97df44 959 #define ADC_CR2_JEXTEN_0 (0x1U << ADC_CR2_JEXTEN_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 960 #define ADC_CR2_JEXTEN_1 (0x2U << ADC_CR2_JEXTEN_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 961 #define ADC_CR2_JSWSTART_Pos (22U)
lypinator 0:bb348c97df44 962 #define ADC_CR2_JSWSTART_Msk (0x1U << ADC_CR2_JSWSTART_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 963 #define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!<Start Conversion of injected channels */
lypinator 0:bb348c97df44 964 #define ADC_CR2_EXTSEL_Pos (24U)
lypinator 0:bb348c97df44 965 #define ADC_CR2_EXTSEL_Msk (0xFU << ADC_CR2_EXTSEL_Pos) /*!< 0x0F000000 */
lypinator 0:bb348c97df44 966 #define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
lypinator 0:bb348c97df44 967 #define ADC_CR2_EXTSEL_0 (0x1U << ADC_CR2_EXTSEL_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 968 #define ADC_CR2_EXTSEL_1 (0x2U << ADC_CR2_EXTSEL_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 969 #define ADC_CR2_EXTSEL_2 (0x4U << ADC_CR2_EXTSEL_Pos) /*!< 0x04000000 */
lypinator 0:bb348c97df44 970 #define ADC_CR2_EXTSEL_3 (0x8U << ADC_CR2_EXTSEL_Pos) /*!< 0x08000000 */
lypinator 0:bb348c97df44 971 #define ADC_CR2_EXTEN_Pos (28U)
lypinator 0:bb348c97df44 972 #define ADC_CR2_EXTEN_Msk (0x3U << ADC_CR2_EXTEN_Pos) /*!< 0x30000000 */
lypinator 0:bb348c97df44 973 #define ADC_CR2_EXTEN ADC_CR2_EXTEN_Msk /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
lypinator 0:bb348c97df44 974 #define ADC_CR2_EXTEN_0 (0x1U << ADC_CR2_EXTEN_Pos) /*!< 0x10000000 */
lypinator 0:bb348c97df44 975 #define ADC_CR2_EXTEN_1 (0x2U << ADC_CR2_EXTEN_Pos) /*!< 0x20000000 */
lypinator 0:bb348c97df44 976 #define ADC_CR2_SWSTART_Pos (30U)
lypinator 0:bb348c97df44 977 #define ADC_CR2_SWSTART_Msk (0x1U << ADC_CR2_SWSTART_Pos) /*!< 0x40000000 */
lypinator 0:bb348c97df44 978 #define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!<Start Conversion of regular channels */
lypinator 0:bb348c97df44 979
lypinator 0:bb348c97df44 980 /****************** Bit definition for ADC_SMPR1 register *******************/
lypinator 0:bb348c97df44 981 #define ADC_SMPR1_SMP10_Pos (0U)
lypinator 0:bb348c97df44 982 #define ADC_SMPR1_SMP10_Msk (0x7U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000007 */
lypinator 0:bb348c97df44 983 #define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
lypinator 0:bb348c97df44 984 #define ADC_SMPR1_SMP10_0 (0x1U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 985 #define ADC_SMPR1_SMP10_1 (0x2U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 986 #define ADC_SMPR1_SMP10_2 (0x4U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 987 #define ADC_SMPR1_SMP11_Pos (3U)
lypinator 0:bb348c97df44 988 #define ADC_SMPR1_SMP11_Msk (0x7U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000038 */
lypinator 0:bb348c97df44 989 #define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
lypinator 0:bb348c97df44 990 #define ADC_SMPR1_SMP11_0 (0x1U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 991 #define ADC_SMPR1_SMP11_1 (0x2U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 992 #define ADC_SMPR1_SMP11_2 (0x4U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 993 #define ADC_SMPR1_SMP12_Pos (6U)
lypinator 0:bb348c97df44 994 #define ADC_SMPR1_SMP12_Msk (0x7U << ADC_SMPR1_SMP12_Pos) /*!< 0x000001C0 */
lypinator 0:bb348c97df44 995 #define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
lypinator 0:bb348c97df44 996 #define ADC_SMPR1_SMP12_0 (0x1U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 997 #define ADC_SMPR1_SMP12_1 (0x2U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 998 #define ADC_SMPR1_SMP12_2 (0x4U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 999 #define ADC_SMPR1_SMP13_Pos (9U)
lypinator 0:bb348c97df44 1000 #define ADC_SMPR1_SMP13_Msk (0x7U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000E00 */
lypinator 0:bb348c97df44 1001 #define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
lypinator 0:bb348c97df44 1002 #define ADC_SMPR1_SMP13_0 (0x1U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 1003 #define ADC_SMPR1_SMP13_1 (0x2U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 1004 #define ADC_SMPR1_SMP13_2 (0x4U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 1005 #define ADC_SMPR1_SMP14_Pos (12U)
lypinator 0:bb348c97df44 1006 #define ADC_SMPR1_SMP14_Msk (0x7U << ADC_SMPR1_SMP14_Pos) /*!< 0x00007000 */
lypinator 0:bb348c97df44 1007 #define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
lypinator 0:bb348c97df44 1008 #define ADC_SMPR1_SMP14_0 (0x1U << ADC_SMPR1_SMP14_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 1009 #define ADC_SMPR1_SMP14_1 (0x2U << ADC_SMPR1_SMP14_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 1010 #define ADC_SMPR1_SMP14_2 (0x4U << ADC_SMPR1_SMP14_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 1011 #define ADC_SMPR1_SMP15_Pos (15U)
lypinator 0:bb348c97df44 1012 #define ADC_SMPR1_SMP15_Msk (0x7U << ADC_SMPR1_SMP15_Pos) /*!< 0x00038000 */
lypinator 0:bb348c97df44 1013 #define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
lypinator 0:bb348c97df44 1014 #define ADC_SMPR1_SMP15_0 (0x1U << ADC_SMPR1_SMP15_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 1015 #define ADC_SMPR1_SMP15_1 (0x2U << ADC_SMPR1_SMP15_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 1016 #define ADC_SMPR1_SMP15_2 (0x4U << ADC_SMPR1_SMP15_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 1017 #define ADC_SMPR1_SMP16_Pos (18U)
lypinator 0:bb348c97df44 1018 #define ADC_SMPR1_SMP16_Msk (0x7U << ADC_SMPR1_SMP16_Pos) /*!< 0x001C0000 */
lypinator 0:bb348c97df44 1019 #define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
lypinator 0:bb348c97df44 1020 #define ADC_SMPR1_SMP16_0 (0x1U << ADC_SMPR1_SMP16_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 1021 #define ADC_SMPR1_SMP16_1 (0x2U << ADC_SMPR1_SMP16_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 1022 #define ADC_SMPR1_SMP16_2 (0x4U << ADC_SMPR1_SMP16_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 1023 #define ADC_SMPR1_SMP17_Pos (21U)
lypinator 0:bb348c97df44 1024 #define ADC_SMPR1_SMP17_Msk (0x7U << ADC_SMPR1_SMP17_Pos) /*!< 0x00E00000 */
lypinator 0:bb348c97df44 1025 #define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
lypinator 0:bb348c97df44 1026 #define ADC_SMPR1_SMP17_0 (0x1U << ADC_SMPR1_SMP17_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 1027 #define ADC_SMPR1_SMP17_1 (0x2U << ADC_SMPR1_SMP17_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 1028 #define ADC_SMPR1_SMP17_2 (0x4U << ADC_SMPR1_SMP17_Pos) /*!< 0x00800000 */
lypinator 0:bb348c97df44 1029 #define ADC_SMPR1_SMP18_Pos (24U)
lypinator 0:bb348c97df44 1030 #define ADC_SMPR1_SMP18_Msk (0x7U << ADC_SMPR1_SMP18_Pos) /*!< 0x07000000 */
lypinator 0:bb348c97df44 1031 #define ADC_SMPR1_SMP18 ADC_SMPR1_SMP18_Msk /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
lypinator 0:bb348c97df44 1032 #define ADC_SMPR1_SMP18_0 (0x1U << ADC_SMPR1_SMP18_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 1033 #define ADC_SMPR1_SMP18_1 (0x2U << ADC_SMPR1_SMP18_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 1034 #define ADC_SMPR1_SMP18_2 (0x4U << ADC_SMPR1_SMP18_Pos) /*!< 0x04000000 */
lypinator 0:bb348c97df44 1035
lypinator 0:bb348c97df44 1036 /****************** Bit definition for ADC_SMPR2 register *******************/
lypinator 0:bb348c97df44 1037 #define ADC_SMPR2_SMP0_Pos (0U)
lypinator 0:bb348c97df44 1038 #define ADC_SMPR2_SMP0_Msk (0x7U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000007 */
lypinator 0:bb348c97df44 1039 #define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
lypinator 0:bb348c97df44 1040 #define ADC_SMPR2_SMP0_0 (0x1U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 1041 #define ADC_SMPR2_SMP0_1 (0x2U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 1042 #define ADC_SMPR2_SMP0_2 (0x4U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 1043 #define ADC_SMPR2_SMP1_Pos (3U)
lypinator 0:bb348c97df44 1044 #define ADC_SMPR2_SMP1_Msk (0x7U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000038 */
lypinator 0:bb348c97df44 1045 #define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
lypinator 0:bb348c97df44 1046 #define ADC_SMPR2_SMP1_0 (0x1U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 1047 #define ADC_SMPR2_SMP1_1 (0x2U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 1048 #define ADC_SMPR2_SMP1_2 (0x4U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 1049 #define ADC_SMPR2_SMP2_Pos (6U)
lypinator 0:bb348c97df44 1050 #define ADC_SMPR2_SMP2_Msk (0x7U << ADC_SMPR2_SMP2_Pos) /*!< 0x000001C0 */
lypinator 0:bb348c97df44 1051 #define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
lypinator 0:bb348c97df44 1052 #define ADC_SMPR2_SMP2_0 (0x1U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 1053 #define ADC_SMPR2_SMP2_1 (0x2U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 1054 #define ADC_SMPR2_SMP2_2 (0x4U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 1055 #define ADC_SMPR2_SMP3_Pos (9U)
lypinator 0:bb348c97df44 1056 #define ADC_SMPR2_SMP3_Msk (0x7U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000E00 */
lypinator 0:bb348c97df44 1057 #define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
lypinator 0:bb348c97df44 1058 #define ADC_SMPR2_SMP3_0 (0x1U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 1059 #define ADC_SMPR2_SMP3_1 (0x2U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 1060 #define ADC_SMPR2_SMP3_2 (0x4U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 1061 #define ADC_SMPR2_SMP4_Pos (12U)
lypinator 0:bb348c97df44 1062 #define ADC_SMPR2_SMP4_Msk (0x7U << ADC_SMPR2_SMP4_Pos) /*!< 0x00007000 */
lypinator 0:bb348c97df44 1063 #define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
lypinator 0:bb348c97df44 1064 #define ADC_SMPR2_SMP4_0 (0x1U << ADC_SMPR2_SMP4_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 1065 #define ADC_SMPR2_SMP4_1 (0x2U << ADC_SMPR2_SMP4_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 1066 #define ADC_SMPR2_SMP4_2 (0x4U << ADC_SMPR2_SMP4_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 1067 #define ADC_SMPR2_SMP5_Pos (15U)
lypinator 0:bb348c97df44 1068 #define ADC_SMPR2_SMP5_Msk (0x7U << ADC_SMPR2_SMP5_Pos) /*!< 0x00038000 */
lypinator 0:bb348c97df44 1069 #define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
lypinator 0:bb348c97df44 1070 #define ADC_SMPR2_SMP5_0 (0x1U << ADC_SMPR2_SMP5_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 1071 #define ADC_SMPR2_SMP5_1 (0x2U << ADC_SMPR2_SMP5_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 1072 #define ADC_SMPR2_SMP5_2 (0x4U << ADC_SMPR2_SMP5_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 1073 #define ADC_SMPR2_SMP6_Pos (18U)
lypinator 0:bb348c97df44 1074 #define ADC_SMPR2_SMP6_Msk (0x7U << ADC_SMPR2_SMP6_Pos) /*!< 0x001C0000 */
lypinator 0:bb348c97df44 1075 #define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
lypinator 0:bb348c97df44 1076 #define ADC_SMPR2_SMP6_0 (0x1U << ADC_SMPR2_SMP6_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 1077 #define ADC_SMPR2_SMP6_1 (0x2U << ADC_SMPR2_SMP6_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 1078 #define ADC_SMPR2_SMP6_2 (0x4U << ADC_SMPR2_SMP6_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 1079 #define ADC_SMPR2_SMP7_Pos (21U)
lypinator 0:bb348c97df44 1080 #define ADC_SMPR2_SMP7_Msk (0x7U << ADC_SMPR2_SMP7_Pos) /*!< 0x00E00000 */
lypinator 0:bb348c97df44 1081 #define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
lypinator 0:bb348c97df44 1082 #define ADC_SMPR2_SMP7_0 (0x1U << ADC_SMPR2_SMP7_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 1083 #define ADC_SMPR2_SMP7_1 (0x2U << ADC_SMPR2_SMP7_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 1084 #define ADC_SMPR2_SMP7_2 (0x4U << ADC_SMPR2_SMP7_Pos) /*!< 0x00800000 */
lypinator 0:bb348c97df44 1085 #define ADC_SMPR2_SMP8_Pos (24U)
lypinator 0:bb348c97df44 1086 #define ADC_SMPR2_SMP8_Msk (0x7U << ADC_SMPR2_SMP8_Pos) /*!< 0x07000000 */
lypinator 0:bb348c97df44 1087 #define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
lypinator 0:bb348c97df44 1088 #define ADC_SMPR2_SMP8_0 (0x1U << ADC_SMPR2_SMP8_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 1089 #define ADC_SMPR2_SMP8_1 (0x2U << ADC_SMPR2_SMP8_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 1090 #define ADC_SMPR2_SMP8_2 (0x4U << ADC_SMPR2_SMP8_Pos) /*!< 0x04000000 */
lypinator 0:bb348c97df44 1091 #define ADC_SMPR2_SMP9_Pos (27U)
lypinator 0:bb348c97df44 1092 #define ADC_SMPR2_SMP9_Msk (0x7U << ADC_SMPR2_SMP9_Pos) /*!< 0x38000000 */
lypinator 0:bb348c97df44 1093 #define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
lypinator 0:bb348c97df44 1094 #define ADC_SMPR2_SMP9_0 (0x1U << ADC_SMPR2_SMP9_Pos) /*!< 0x08000000 */
lypinator 0:bb348c97df44 1095 #define ADC_SMPR2_SMP9_1 (0x2U << ADC_SMPR2_SMP9_Pos) /*!< 0x10000000 */
lypinator 0:bb348c97df44 1096 #define ADC_SMPR2_SMP9_2 (0x4U << ADC_SMPR2_SMP9_Pos) /*!< 0x20000000 */
lypinator 0:bb348c97df44 1097
lypinator 0:bb348c97df44 1098 /****************** Bit definition for ADC_JOFR1 register *******************/
lypinator 0:bb348c97df44 1099 #define ADC_JOFR1_JOFFSET1_Pos (0U)
lypinator 0:bb348c97df44 1100 #define ADC_JOFR1_JOFFSET1_Msk (0xFFFU << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */
lypinator 0:bb348c97df44 1101 #define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!<Data offset for injected channel 1 */
lypinator 0:bb348c97df44 1102
lypinator 0:bb348c97df44 1103 /****************** Bit definition for ADC_JOFR2 register *******************/
lypinator 0:bb348c97df44 1104 #define ADC_JOFR2_JOFFSET2_Pos (0U)
lypinator 0:bb348c97df44 1105 #define ADC_JOFR2_JOFFSET2_Msk (0xFFFU << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */
lypinator 0:bb348c97df44 1106 #define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!<Data offset for injected channel 2 */
lypinator 0:bb348c97df44 1107
lypinator 0:bb348c97df44 1108 /****************** Bit definition for ADC_JOFR3 register *******************/
lypinator 0:bb348c97df44 1109 #define ADC_JOFR3_JOFFSET3_Pos (0U)
lypinator 0:bb348c97df44 1110 #define ADC_JOFR3_JOFFSET3_Msk (0xFFFU << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */
lypinator 0:bb348c97df44 1111 #define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!<Data offset for injected channel 3 */
lypinator 0:bb348c97df44 1112
lypinator 0:bb348c97df44 1113 /****************** Bit definition for ADC_JOFR4 register *******************/
lypinator 0:bb348c97df44 1114 #define ADC_JOFR4_JOFFSET4_Pos (0U)
lypinator 0:bb348c97df44 1115 #define ADC_JOFR4_JOFFSET4_Msk (0xFFFU << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */
lypinator 0:bb348c97df44 1116 #define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!<Data offset for injected channel 4 */
lypinator 0:bb348c97df44 1117
lypinator 0:bb348c97df44 1118 /******************* Bit definition for ADC_HTR register ********************/
lypinator 0:bb348c97df44 1119 #define ADC_HTR_HT_Pos (0U)
lypinator 0:bb348c97df44 1120 #define ADC_HTR_HT_Msk (0xFFFU << ADC_HTR_HT_Pos) /*!< 0x00000FFF */
lypinator 0:bb348c97df44 1121 #define ADC_HTR_HT ADC_HTR_HT_Msk /*!<Analog watchdog high threshold */
lypinator 0:bb348c97df44 1122
lypinator 0:bb348c97df44 1123 /******************* Bit definition for ADC_LTR register ********************/
lypinator 0:bb348c97df44 1124 #define ADC_LTR_LT_Pos (0U)
lypinator 0:bb348c97df44 1125 #define ADC_LTR_LT_Msk (0xFFFU << ADC_LTR_LT_Pos) /*!< 0x00000FFF */
lypinator 0:bb348c97df44 1126 #define ADC_LTR_LT ADC_LTR_LT_Msk /*!<Analog watchdog low threshold */
lypinator 0:bb348c97df44 1127
lypinator 0:bb348c97df44 1128 /******************* Bit definition for ADC_SQR1 register *******************/
lypinator 0:bb348c97df44 1129 #define ADC_SQR1_SQ13_Pos (0U)
lypinator 0:bb348c97df44 1130 #define ADC_SQR1_SQ13_Msk (0x1FU << ADC_SQR1_SQ13_Pos) /*!< 0x0000001F */
lypinator 0:bb348c97df44 1131 #define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
lypinator 0:bb348c97df44 1132 #define ADC_SQR1_SQ13_0 (0x01U << ADC_SQR1_SQ13_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 1133 #define ADC_SQR1_SQ13_1 (0x02U << ADC_SQR1_SQ13_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 1134 #define ADC_SQR1_SQ13_2 (0x04U << ADC_SQR1_SQ13_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 1135 #define ADC_SQR1_SQ13_3 (0x08U << ADC_SQR1_SQ13_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 1136 #define ADC_SQR1_SQ13_4 (0x10U << ADC_SQR1_SQ13_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 1137 #define ADC_SQR1_SQ14_Pos (5U)
lypinator 0:bb348c97df44 1138 #define ADC_SQR1_SQ14_Msk (0x1FU << ADC_SQR1_SQ14_Pos) /*!< 0x000003E0 */
lypinator 0:bb348c97df44 1139 #define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
lypinator 0:bb348c97df44 1140 #define ADC_SQR1_SQ14_0 (0x01U << ADC_SQR1_SQ14_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 1141 #define ADC_SQR1_SQ14_1 (0x02U << ADC_SQR1_SQ14_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 1142 #define ADC_SQR1_SQ14_2 (0x04U << ADC_SQR1_SQ14_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 1143 #define ADC_SQR1_SQ14_3 (0x08U << ADC_SQR1_SQ14_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 1144 #define ADC_SQR1_SQ14_4 (0x10U << ADC_SQR1_SQ14_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 1145 #define ADC_SQR1_SQ15_Pos (10U)
lypinator 0:bb348c97df44 1146 #define ADC_SQR1_SQ15_Msk (0x1FU << ADC_SQR1_SQ15_Pos) /*!< 0x00007C00 */
lypinator 0:bb348c97df44 1147 #define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
lypinator 0:bb348c97df44 1148 #define ADC_SQR1_SQ15_0 (0x01U << ADC_SQR1_SQ15_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 1149 #define ADC_SQR1_SQ15_1 (0x02U << ADC_SQR1_SQ15_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 1150 #define ADC_SQR1_SQ15_2 (0x04U << ADC_SQR1_SQ15_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 1151 #define ADC_SQR1_SQ15_3 (0x08U << ADC_SQR1_SQ15_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 1152 #define ADC_SQR1_SQ15_4 (0x10U << ADC_SQR1_SQ15_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 1153 #define ADC_SQR1_SQ16_Pos (15U)
lypinator 0:bb348c97df44 1154 #define ADC_SQR1_SQ16_Msk (0x1FU << ADC_SQR1_SQ16_Pos) /*!< 0x000F8000 */
lypinator 0:bb348c97df44 1155 #define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
lypinator 0:bb348c97df44 1156 #define ADC_SQR1_SQ16_0 (0x01U << ADC_SQR1_SQ16_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 1157 #define ADC_SQR1_SQ16_1 (0x02U << ADC_SQR1_SQ16_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 1158 #define ADC_SQR1_SQ16_2 (0x04U << ADC_SQR1_SQ16_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 1159 #define ADC_SQR1_SQ16_3 (0x08U << ADC_SQR1_SQ16_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 1160 #define ADC_SQR1_SQ16_4 (0x10U << ADC_SQR1_SQ16_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 1161 #define ADC_SQR1_L_Pos (20U)
lypinator 0:bb348c97df44 1162 #define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x00F00000 */
lypinator 0:bb348c97df44 1163 #define ADC_SQR1_L ADC_SQR1_L_Msk /*!<L[3:0] bits (Regular channel sequence length) */
lypinator 0:bb348c97df44 1164 #define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 1165 #define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 1166 #define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 1167 #define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00800000 */
lypinator 0:bb348c97df44 1168
lypinator 0:bb348c97df44 1169 /******************* Bit definition for ADC_SQR2 register *******************/
lypinator 0:bb348c97df44 1170 #define ADC_SQR2_SQ7_Pos (0U)
lypinator 0:bb348c97df44 1171 #define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0000001F */
lypinator 0:bb348c97df44 1172 #define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
lypinator 0:bb348c97df44 1173 #define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 1174 #define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 1175 #define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 1176 #define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 1177 #define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 1178 #define ADC_SQR2_SQ8_Pos (5U)
lypinator 0:bb348c97df44 1179 #define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x000003E0 */
lypinator 0:bb348c97df44 1180 #define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
lypinator 0:bb348c97df44 1181 #define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 1182 #define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 1183 #define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 1184 #define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 1185 #define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 1186 #define ADC_SQR2_SQ9_Pos (10U)
lypinator 0:bb348c97df44 1187 #define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x00007C00 */
lypinator 0:bb348c97df44 1188 #define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
lypinator 0:bb348c97df44 1189 #define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 1190 #define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 1191 #define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 1192 #define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 1193 #define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 1194 #define ADC_SQR2_SQ10_Pos (15U)
lypinator 0:bb348c97df44 1195 #define ADC_SQR2_SQ10_Msk (0x1FU << ADC_SQR2_SQ10_Pos) /*!< 0x000F8000 */
lypinator 0:bb348c97df44 1196 #define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
lypinator 0:bb348c97df44 1197 #define ADC_SQR2_SQ10_0 (0x01U << ADC_SQR2_SQ10_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 1198 #define ADC_SQR2_SQ10_1 (0x02U << ADC_SQR2_SQ10_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 1199 #define ADC_SQR2_SQ10_2 (0x04U << ADC_SQR2_SQ10_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 1200 #define ADC_SQR2_SQ10_3 (0x08U << ADC_SQR2_SQ10_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 1201 #define ADC_SQR2_SQ10_4 (0x10U << ADC_SQR2_SQ10_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 1202 #define ADC_SQR2_SQ11_Pos (20U)
lypinator 0:bb348c97df44 1203 #define ADC_SQR2_SQ11_Msk (0x1FU << ADC_SQR2_SQ11_Pos) /*!< 0x01F00000 */
lypinator 0:bb348c97df44 1204 #define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
lypinator 0:bb348c97df44 1205 #define ADC_SQR2_SQ11_0 (0x01U << ADC_SQR2_SQ11_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 1206 #define ADC_SQR2_SQ11_1 (0x02U << ADC_SQR2_SQ11_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 1207 #define ADC_SQR2_SQ11_2 (0x04U << ADC_SQR2_SQ11_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 1208 #define ADC_SQR2_SQ11_3 (0x08U << ADC_SQR2_SQ11_Pos) /*!< 0x00800000 */
lypinator 0:bb348c97df44 1209 #define ADC_SQR2_SQ11_4 (0x10U << ADC_SQR2_SQ11_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 1210 #define ADC_SQR2_SQ12_Pos (25U)
lypinator 0:bb348c97df44 1211 #define ADC_SQR2_SQ12_Msk (0x1FU << ADC_SQR2_SQ12_Pos) /*!< 0x3E000000 */
lypinator 0:bb348c97df44 1212 #define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
lypinator 0:bb348c97df44 1213 #define ADC_SQR2_SQ12_0 (0x01U << ADC_SQR2_SQ12_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 1214 #define ADC_SQR2_SQ12_1 (0x02U << ADC_SQR2_SQ12_Pos) /*!< 0x04000000 */
lypinator 0:bb348c97df44 1215 #define ADC_SQR2_SQ12_2 (0x04U << ADC_SQR2_SQ12_Pos) /*!< 0x08000000 */
lypinator 0:bb348c97df44 1216 #define ADC_SQR2_SQ12_3 (0x08U << ADC_SQR2_SQ12_Pos) /*!< 0x10000000 */
lypinator 0:bb348c97df44 1217 #define ADC_SQR2_SQ12_4 (0x10U << ADC_SQR2_SQ12_Pos) /*!< 0x20000000 */
lypinator 0:bb348c97df44 1218
lypinator 0:bb348c97df44 1219 /******************* Bit definition for ADC_SQR3 register *******************/
lypinator 0:bb348c97df44 1220 #define ADC_SQR3_SQ1_Pos (0U)
lypinator 0:bb348c97df44 1221 #define ADC_SQR3_SQ1_Msk (0x1FU << ADC_SQR3_SQ1_Pos) /*!< 0x0000001F */
lypinator 0:bb348c97df44 1222 #define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
lypinator 0:bb348c97df44 1223 #define ADC_SQR3_SQ1_0 (0x01U << ADC_SQR3_SQ1_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 1224 #define ADC_SQR3_SQ1_1 (0x02U << ADC_SQR3_SQ1_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 1225 #define ADC_SQR3_SQ1_2 (0x04U << ADC_SQR3_SQ1_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 1226 #define ADC_SQR3_SQ1_3 (0x08U << ADC_SQR3_SQ1_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 1227 #define ADC_SQR3_SQ1_4 (0x10U << ADC_SQR3_SQ1_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 1228 #define ADC_SQR3_SQ2_Pos (5U)
lypinator 0:bb348c97df44 1229 #define ADC_SQR3_SQ2_Msk (0x1FU << ADC_SQR3_SQ2_Pos) /*!< 0x000003E0 */
lypinator 0:bb348c97df44 1230 #define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
lypinator 0:bb348c97df44 1231 #define ADC_SQR3_SQ2_0 (0x01U << ADC_SQR3_SQ2_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 1232 #define ADC_SQR3_SQ2_1 (0x02U << ADC_SQR3_SQ2_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 1233 #define ADC_SQR3_SQ2_2 (0x04U << ADC_SQR3_SQ2_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 1234 #define ADC_SQR3_SQ2_3 (0x08U << ADC_SQR3_SQ2_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 1235 #define ADC_SQR3_SQ2_4 (0x10U << ADC_SQR3_SQ2_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 1236 #define ADC_SQR3_SQ3_Pos (10U)
lypinator 0:bb348c97df44 1237 #define ADC_SQR3_SQ3_Msk (0x1FU << ADC_SQR3_SQ3_Pos) /*!< 0x00007C00 */
lypinator 0:bb348c97df44 1238 #define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
lypinator 0:bb348c97df44 1239 #define ADC_SQR3_SQ3_0 (0x01U << ADC_SQR3_SQ3_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 1240 #define ADC_SQR3_SQ3_1 (0x02U << ADC_SQR3_SQ3_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 1241 #define ADC_SQR3_SQ3_2 (0x04U << ADC_SQR3_SQ3_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 1242 #define ADC_SQR3_SQ3_3 (0x08U << ADC_SQR3_SQ3_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 1243 #define ADC_SQR3_SQ3_4 (0x10U << ADC_SQR3_SQ3_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 1244 #define ADC_SQR3_SQ4_Pos (15U)
lypinator 0:bb348c97df44 1245 #define ADC_SQR3_SQ4_Msk (0x1FU << ADC_SQR3_SQ4_Pos) /*!< 0x000F8000 */
lypinator 0:bb348c97df44 1246 #define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
lypinator 0:bb348c97df44 1247 #define ADC_SQR3_SQ4_0 (0x01U << ADC_SQR3_SQ4_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 1248 #define ADC_SQR3_SQ4_1 (0x02U << ADC_SQR3_SQ4_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 1249 #define ADC_SQR3_SQ4_2 (0x04U << ADC_SQR3_SQ4_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 1250 #define ADC_SQR3_SQ4_3 (0x08U << ADC_SQR3_SQ4_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 1251 #define ADC_SQR3_SQ4_4 (0x10U << ADC_SQR3_SQ4_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 1252 #define ADC_SQR3_SQ5_Pos (20U)
lypinator 0:bb348c97df44 1253 #define ADC_SQR3_SQ5_Msk (0x1FU << ADC_SQR3_SQ5_Pos) /*!< 0x01F00000 */
lypinator 0:bb348c97df44 1254 #define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
lypinator 0:bb348c97df44 1255 #define ADC_SQR3_SQ5_0 (0x01U << ADC_SQR3_SQ5_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 1256 #define ADC_SQR3_SQ5_1 (0x02U << ADC_SQR3_SQ5_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 1257 #define ADC_SQR3_SQ5_2 (0x04U << ADC_SQR3_SQ5_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 1258 #define ADC_SQR3_SQ5_3 (0x08U << ADC_SQR3_SQ5_Pos) /*!< 0x00800000 */
lypinator 0:bb348c97df44 1259 #define ADC_SQR3_SQ5_4 (0x10U << ADC_SQR3_SQ5_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 1260 #define ADC_SQR3_SQ6_Pos (25U)
lypinator 0:bb348c97df44 1261 #define ADC_SQR3_SQ6_Msk (0x1FU << ADC_SQR3_SQ6_Pos) /*!< 0x3E000000 */
lypinator 0:bb348c97df44 1262 #define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
lypinator 0:bb348c97df44 1263 #define ADC_SQR3_SQ6_0 (0x01U << ADC_SQR3_SQ6_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 1264 #define ADC_SQR3_SQ6_1 (0x02U << ADC_SQR3_SQ6_Pos) /*!< 0x04000000 */
lypinator 0:bb348c97df44 1265 #define ADC_SQR3_SQ6_2 (0x04U << ADC_SQR3_SQ6_Pos) /*!< 0x08000000 */
lypinator 0:bb348c97df44 1266 #define ADC_SQR3_SQ6_3 (0x08U << ADC_SQR3_SQ6_Pos) /*!< 0x10000000 */
lypinator 0:bb348c97df44 1267 #define ADC_SQR3_SQ6_4 (0x10U << ADC_SQR3_SQ6_Pos) /*!< 0x20000000 */
lypinator 0:bb348c97df44 1268
lypinator 0:bb348c97df44 1269 /******************* Bit definition for ADC_JSQR register *******************/
lypinator 0:bb348c97df44 1270 #define ADC_JSQR_JSQ1_Pos (0U)
lypinator 0:bb348c97df44 1271 #define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */
lypinator 0:bb348c97df44 1272 #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
lypinator 0:bb348c97df44 1273 #define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 1274 #define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 1275 #define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 1276 #define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 1277 #define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 1278 #define ADC_JSQR_JSQ2_Pos (5U)
lypinator 0:bb348c97df44 1279 #define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */
lypinator 0:bb348c97df44 1280 #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
lypinator 0:bb348c97df44 1281 #define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 1282 #define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 1283 #define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 1284 #define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 1285 #define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 1286 #define ADC_JSQR_JSQ3_Pos (10U)
lypinator 0:bb348c97df44 1287 #define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */
lypinator 0:bb348c97df44 1288 #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
lypinator 0:bb348c97df44 1289 #define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 1290 #define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 1291 #define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 1292 #define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 1293 #define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 1294 #define ADC_JSQR_JSQ4_Pos (15U)
lypinator 0:bb348c97df44 1295 #define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */
lypinator 0:bb348c97df44 1296 #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
lypinator 0:bb348c97df44 1297 #define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 1298 #define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 1299 #define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 1300 #define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 1301 #define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 1302 #define ADC_JSQR_JL_Pos (20U)
lypinator 0:bb348c97df44 1303 #define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00300000 */
lypinator 0:bb348c97df44 1304 #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!<JL[1:0] bits (Injected Sequence length) */
lypinator 0:bb348c97df44 1305 #define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 1306 #define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 1307
lypinator 0:bb348c97df44 1308 /******************* Bit definition for ADC_JDR1 register *******************/
lypinator 0:bb348c97df44 1309 #define ADC_JDR1_JDATA_Pos (0U)
lypinator 0:bb348c97df44 1310 #define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */
lypinator 0:bb348c97df44 1311 #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!<Injected data */
lypinator 0:bb348c97df44 1312
lypinator 0:bb348c97df44 1313 /******************* Bit definition for ADC_JDR2 register *******************/
lypinator 0:bb348c97df44 1314 #define ADC_JDR2_JDATA_Pos (0U)
lypinator 0:bb348c97df44 1315 #define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */
lypinator 0:bb348c97df44 1316 #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!<Injected data */
lypinator 0:bb348c97df44 1317
lypinator 0:bb348c97df44 1318 /******************* Bit definition for ADC_JDR3 register *******************/
lypinator 0:bb348c97df44 1319 #define ADC_JDR3_JDATA_Pos (0U)
lypinator 0:bb348c97df44 1320 #define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */
lypinator 0:bb348c97df44 1321 #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!<Injected data */
lypinator 0:bb348c97df44 1322
lypinator 0:bb348c97df44 1323 /******************* Bit definition for ADC_JDR4 register *******************/
lypinator 0:bb348c97df44 1324 #define ADC_JDR4_JDATA_Pos (0U)
lypinator 0:bb348c97df44 1325 #define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */
lypinator 0:bb348c97df44 1326 #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!<Injected data */
lypinator 0:bb348c97df44 1327
lypinator 0:bb348c97df44 1328 /******************** Bit definition for ADC_DR register ********************/
lypinator 0:bb348c97df44 1329 #define ADC_DR_DATA_Pos (0U)
lypinator 0:bb348c97df44 1330 #define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
lypinator 0:bb348c97df44 1331 #define ADC_DR_DATA ADC_DR_DATA_Msk /*!<Regular data */
lypinator 0:bb348c97df44 1332 #define ADC_DR_ADC2DATA_Pos (16U)
lypinator 0:bb348c97df44 1333 #define ADC_DR_ADC2DATA_Msk (0xFFFFU << ADC_DR_ADC2DATA_Pos) /*!< 0xFFFF0000 */
lypinator 0:bb348c97df44 1334 #define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk /*!<ADC2 data */
lypinator 0:bb348c97df44 1335
lypinator 0:bb348c97df44 1336 /******************* Bit definition for ADC_CSR register ********************/
lypinator 0:bb348c97df44 1337 #define ADC_CSR_AWD1_Pos (0U)
lypinator 0:bb348c97df44 1338 #define ADC_CSR_AWD1_Msk (0x1U << ADC_CSR_AWD1_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 1339 #define ADC_CSR_AWD1 ADC_CSR_AWD1_Msk /*!<ADC1 Analog watchdog flag */
lypinator 0:bb348c97df44 1340 #define ADC_CSR_EOC1_Pos (1U)
lypinator 0:bb348c97df44 1341 #define ADC_CSR_EOC1_Msk (0x1U << ADC_CSR_EOC1_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 1342 #define ADC_CSR_EOC1 ADC_CSR_EOC1_Msk /*!<ADC1 End of conversion */
lypinator 0:bb348c97df44 1343 #define ADC_CSR_JEOC1_Pos (2U)
lypinator 0:bb348c97df44 1344 #define ADC_CSR_JEOC1_Msk (0x1U << ADC_CSR_JEOC1_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 1345 #define ADC_CSR_JEOC1 ADC_CSR_JEOC1_Msk /*!<ADC1 Injected channel end of conversion */
lypinator 0:bb348c97df44 1346 #define ADC_CSR_JSTRT1_Pos (3U)
lypinator 0:bb348c97df44 1347 #define ADC_CSR_JSTRT1_Msk (0x1U << ADC_CSR_JSTRT1_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 1348 #define ADC_CSR_JSTRT1 ADC_CSR_JSTRT1_Msk /*!<ADC1 Injected channel Start flag */
lypinator 0:bb348c97df44 1349 #define ADC_CSR_STRT1_Pos (4U)
lypinator 0:bb348c97df44 1350 #define ADC_CSR_STRT1_Msk (0x1U << ADC_CSR_STRT1_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 1351 #define ADC_CSR_STRT1 ADC_CSR_STRT1_Msk /*!<ADC1 Regular channel Start flag */
lypinator 0:bb348c97df44 1352 #define ADC_CSR_OVR1_Pos (5U)
lypinator 0:bb348c97df44 1353 #define ADC_CSR_OVR1_Msk (0x1U << ADC_CSR_OVR1_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 1354 #define ADC_CSR_OVR1 ADC_CSR_OVR1_Msk /*!<ADC1 DMA overrun flag */
lypinator 0:bb348c97df44 1355
lypinator 0:bb348c97df44 1356 /* Legacy defines */
lypinator 0:bb348c97df44 1357 #define ADC_CSR_DOVR1 ADC_CSR_OVR1
lypinator 0:bb348c97df44 1358
lypinator 0:bb348c97df44 1359 /******************* Bit definition for ADC_CCR register ********************/
lypinator 0:bb348c97df44 1360 #define ADC_CCR_MULTI_Pos (0U)
lypinator 0:bb348c97df44 1361 #define ADC_CCR_MULTI_Msk (0x1FU << ADC_CCR_MULTI_Pos) /*!< 0x0000001F */
lypinator 0:bb348c97df44 1362 #define ADC_CCR_MULTI ADC_CCR_MULTI_Msk /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
lypinator 0:bb348c97df44 1363 #define ADC_CCR_MULTI_0 (0x01U << ADC_CCR_MULTI_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 1364 #define ADC_CCR_MULTI_1 (0x02U << ADC_CCR_MULTI_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 1365 #define ADC_CCR_MULTI_2 (0x04U << ADC_CCR_MULTI_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 1366 #define ADC_CCR_MULTI_3 (0x08U << ADC_CCR_MULTI_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 1367 #define ADC_CCR_MULTI_4 (0x10U << ADC_CCR_MULTI_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 1368 #define ADC_CCR_DELAY_Pos (8U)
lypinator 0:bb348c97df44 1369 #define ADC_CCR_DELAY_Msk (0xFU << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */
lypinator 0:bb348c97df44 1370 #define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
lypinator 0:bb348c97df44 1371 #define ADC_CCR_DELAY_0 (0x1U << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 1372 #define ADC_CCR_DELAY_1 (0x2U << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 1373 #define ADC_CCR_DELAY_2 (0x4U << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 1374 #define ADC_CCR_DELAY_3 (0x8U << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 1375 #define ADC_CCR_DDS_Pos (13U)
lypinator 0:bb348c97df44 1376 #define ADC_CCR_DDS_Msk (0x1U << ADC_CCR_DDS_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 1377 #define ADC_CCR_DDS ADC_CCR_DDS_Msk /*!<DMA disable selection (Multi-ADC mode) */
lypinator 0:bb348c97df44 1378 #define ADC_CCR_DMA_Pos (14U)
lypinator 0:bb348c97df44 1379 #define ADC_CCR_DMA_Msk (0x3U << ADC_CCR_DMA_Pos) /*!< 0x0000C000 */
lypinator 0:bb348c97df44 1380 #define ADC_CCR_DMA ADC_CCR_DMA_Msk /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
lypinator 0:bb348c97df44 1381 #define ADC_CCR_DMA_0 (0x1U << ADC_CCR_DMA_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 1382 #define ADC_CCR_DMA_1 (0x2U << ADC_CCR_DMA_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 1383 #define ADC_CCR_ADCPRE_Pos (16U)
lypinator 0:bb348c97df44 1384 #define ADC_CCR_ADCPRE_Msk (0x3U << ADC_CCR_ADCPRE_Pos) /*!< 0x00030000 */
lypinator 0:bb348c97df44 1385 #define ADC_CCR_ADCPRE ADC_CCR_ADCPRE_Msk /*!<ADCPRE[1:0] bits (ADC prescaler) */
lypinator 0:bb348c97df44 1386 #define ADC_CCR_ADCPRE_0 (0x1U << ADC_CCR_ADCPRE_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 1387 #define ADC_CCR_ADCPRE_1 (0x2U << ADC_CCR_ADCPRE_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 1388 #define ADC_CCR_VBATE_Pos (22U)
lypinator 0:bb348c97df44 1389 #define ADC_CCR_VBATE_Msk (0x1U << ADC_CCR_VBATE_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 1390 #define ADC_CCR_VBATE ADC_CCR_VBATE_Msk /*!<VBAT Enable */
lypinator 0:bb348c97df44 1391 #define ADC_CCR_TSVREFE_Pos (23U)
lypinator 0:bb348c97df44 1392 #define ADC_CCR_TSVREFE_Msk (0x1U << ADC_CCR_TSVREFE_Pos) /*!< 0x00800000 */
lypinator 0:bb348c97df44 1393 #define ADC_CCR_TSVREFE ADC_CCR_TSVREFE_Msk /*!<Temperature Sensor and VREFINT Enable */
lypinator 0:bb348c97df44 1394
lypinator 0:bb348c97df44 1395 /******************* Bit definition for ADC_CDR register ********************/
lypinator 0:bb348c97df44 1396 #define ADC_CDR_DATA1_Pos (0U)
lypinator 0:bb348c97df44 1397 #define ADC_CDR_DATA1_Msk (0xFFFFU << ADC_CDR_DATA1_Pos) /*!< 0x0000FFFF */
lypinator 0:bb348c97df44 1398 #define ADC_CDR_DATA1 ADC_CDR_DATA1_Msk /*!<1st data of a pair of regular conversions */
lypinator 0:bb348c97df44 1399 #define ADC_CDR_DATA2_Pos (16U)
lypinator 0:bb348c97df44 1400 #define ADC_CDR_DATA2_Msk (0xFFFFU << ADC_CDR_DATA2_Pos) /*!< 0xFFFF0000 */
lypinator 0:bb348c97df44 1401 #define ADC_CDR_DATA2 ADC_CDR_DATA2_Msk /*!<2nd data of a pair of regular conversions */
lypinator 0:bb348c97df44 1402
lypinator 0:bb348c97df44 1403 /* Legacy defines */
lypinator 0:bb348c97df44 1404 #define ADC_CDR_RDATA_MST ADC_CDR_DATA1
lypinator 0:bb348c97df44 1405 #define ADC_CDR_RDATA_SLV ADC_CDR_DATA2
lypinator 0:bb348c97df44 1406
lypinator 0:bb348c97df44 1407 /******************************************************************************/
lypinator 0:bb348c97df44 1408 /* */
lypinator 0:bb348c97df44 1409 /* CRC calculation unit */
lypinator 0:bb348c97df44 1410 /* */
lypinator 0:bb348c97df44 1411 /******************************************************************************/
lypinator 0:bb348c97df44 1412 /******************* Bit definition for CRC_DR register *********************/
lypinator 0:bb348c97df44 1413 #define CRC_DR_DR_Pos (0U)
lypinator 0:bb348c97df44 1414 #define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
lypinator 0:bb348c97df44 1415 #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
lypinator 0:bb348c97df44 1416
lypinator 0:bb348c97df44 1417
lypinator 0:bb348c97df44 1418 /******************* Bit definition for CRC_IDR register ********************/
lypinator 0:bb348c97df44 1419 #define CRC_IDR_IDR_Pos (0U)
lypinator 0:bb348c97df44 1420 #define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
lypinator 0:bb348c97df44 1421 #define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */
lypinator 0:bb348c97df44 1422
lypinator 0:bb348c97df44 1423
lypinator 0:bb348c97df44 1424 /******************** Bit definition for CRC_CR register ********************/
lypinator 0:bb348c97df44 1425 #define CRC_CR_RESET_Pos (0U)
lypinator 0:bb348c97df44 1426 #define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 1427 #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET bit */
lypinator 0:bb348c97df44 1428
lypinator 0:bb348c97df44 1429
lypinator 0:bb348c97df44 1430 /******************************************************************************/
lypinator 0:bb348c97df44 1431 /* */
lypinator 0:bb348c97df44 1432 /* DMA Controller */
lypinator 0:bb348c97df44 1433 /* */
lypinator 0:bb348c97df44 1434 /******************************************************************************/
lypinator 0:bb348c97df44 1435 /******************** Bits definition for DMA_SxCR register *****************/
lypinator 0:bb348c97df44 1436 #define DMA_SxCR_CHSEL_Pos (25U)
lypinator 0:bb348c97df44 1437 #define DMA_SxCR_CHSEL_Msk (0x7U << DMA_SxCR_CHSEL_Pos) /*!< 0x0E000000 */
lypinator 0:bb348c97df44 1438 #define DMA_SxCR_CHSEL DMA_SxCR_CHSEL_Msk
lypinator 0:bb348c97df44 1439 #define DMA_SxCR_CHSEL_0 0x02000000U
lypinator 0:bb348c97df44 1440 #define DMA_SxCR_CHSEL_1 0x04000000U
lypinator 0:bb348c97df44 1441 #define DMA_SxCR_CHSEL_2 0x08000000U
lypinator 0:bb348c97df44 1442 #define DMA_SxCR_MBURST_Pos (23U)
lypinator 0:bb348c97df44 1443 #define DMA_SxCR_MBURST_Msk (0x3U << DMA_SxCR_MBURST_Pos) /*!< 0x01800000 */
lypinator 0:bb348c97df44 1444 #define DMA_SxCR_MBURST DMA_SxCR_MBURST_Msk
lypinator 0:bb348c97df44 1445 #define DMA_SxCR_MBURST_0 (0x1U << DMA_SxCR_MBURST_Pos) /*!< 0x00800000 */
lypinator 0:bb348c97df44 1446 #define DMA_SxCR_MBURST_1 (0x2U << DMA_SxCR_MBURST_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 1447 #define DMA_SxCR_PBURST_Pos (21U)
lypinator 0:bb348c97df44 1448 #define DMA_SxCR_PBURST_Msk (0x3U << DMA_SxCR_PBURST_Pos) /*!< 0x00600000 */
lypinator 0:bb348c97df44 1449 #define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk
lypinator 0:bb348c97df44 1450 #define DMA_SxCR_PBURST_0 (0x1U << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 1451 #define DMA_SxCR_PBURST_1 (0x2U << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 1452 #define DMA_SxCR_CT_Pos (19U)
lypinator 0:bb348c97df44 1453 #define DMA_SxCR_CT_Msk (0x1U << DMA_SxCR_CT_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 1454 #define DMA_SxCR_CT DMA_SxCR_CT_Msk
lypinator 0:bb348c97df44 1455 #define DMA_SxCR_DBM_Pos (18U)
lypinator 0:bb348c97df44 1456 #define DMA_SxCR_DBM_Msk (0x1U << DMA_SxCR_DBM_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 1457 #define DMA_SxCR_DBM DMA_SxCR_DBM_Msk
lypinator 0:bb348c97df44 1458 #define DMA_SxCR_PL_Pos (16U)
lypinator 0:bb348c97df44 1459 #define DMA_SxCR_PL_Msk (0x3U << DMA_SxCR_PL_Pos) /*!< 0x00030000 */
lypinator 0:bb348c97df44 1460 #define DMA_SxCR_PL DMA_SxCR_PL_Msk
lypinator 0:bb348c97df44 1461 #define DMA_SxCR_PL_0 (0x1U << DMA_SxCR_PL_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 1462 #define DMA_SxCR_PL_1 (0x2U << DMA_SxCR_PL_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 1463 #define DMA_SxCR_PINCOS_Pos (15U)
lypinator 0:bb348c97df44 1464 #define DMA_SxCR_PINCOS_Msk (0x1U << DMA_SxCR_PINCOS_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 1465 #define DMA_SxCR_PINCOS DMA_SxCR_PINCOS_Msk
lypinator 0:bb348c97df44 1466 #define DMA_SxCR_MSIZE_Pos (13U)
lypinator 0:bb348c97df44 1467 #define DMA_SxCR_MSIZE_Msk (0x3U << DMA_SxCR_MSIZE_Pos) /*!< 0x00006000 */
lypinator 0:bb348c97df44 1468 #define DMA_SxCR_MSIZE DMA_SxCR_MSIZE_Msk
lypinator 0:bb348c97df44 1469 #define DMA_SxCR_MSIZE_0 (0x1U << DMA_SxCR_MSIZE_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 1470 #define DMA_SxCR_MSIZE_1 (0x2U << DMA_SxCR_MSIZE_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 1471 #define DMA_SxCR_PSIZE_Pos (11U)
lypinator 0:bb348c97df44 1472 #define DMA_SxCR_PSIZE_Msk (0x3U << DMA_SxCR_PSIZE_Pos) /*!< 0x00001800 */
lypinator 0:bb348c97df44 1473 #define DMA_SxCR_PSIZE DMA_SxCR_PSIZE_Msk
lypinator 0:bb348c97df44 1474 #define DMA_SxCR_PSIZE_0 (0x1U << DMA_SxCR_PSIZE_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 1475 #define DMA_SxCR_PSIZE_1 (0x2U << DMA_SxCR_PSIZE_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 1476 #define DMA_SxCR_MINC_Pos (10U)
lypinator 0:bb348c97df44 1477 #define DMA_SxCR_MINC_Msk (0x1U << DMA_SxCR_MINC_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 1478 #define DMA_SxCR_MINC DMA_SxCR_MINC_Msk
lypinator 0:bb348c97df44 1479 #define DMA_SxCR_PINC_Pos (9U)
lypinator 0:bb348c97df44 1480 #define DMA_SxCR_PINC_Msk (0x1U << DMA_SxCR_PINC_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 1481 #define DMA_SxCR_PINC DMA_SxCR_PINC_Msk
lypinator 0:bb348c97df44 1482 #define DMA_SxCR_CIRC_Pos (8U)
lypinator 0:bb348c97df44 1483 #define DMA_SxCR_CIRC_Msk (0x1U << DMA_SxCR_CIRC_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 1484 #define DMA_SxCR_CIRC DMA_SxCR_CIRC_Msk
lypinator 0:bb348c97df44 1485 #define DMA_SxCR_DIR_Pos (6U)
lypinator 0:bb348c97df44 1486 #define DMA_SxCR_DIR_Msk (0x3U << DMA_SxCR_DIR_Pos) /*!< 0x000000C0 */
lypinator 0:bb348c97df44 1487 #define DMA_SxCR_DIR DMA_SxCR_DIR_Msk
lypinator 0:bb348c97df44 1488 #define DMA_SxCR_DIR_0 (0x1U << DMA_SxCR_DIR_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 1489 #define DMA_SxCR_DIR_1 (0x2U << DMA_SxCR_DIR_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 1490 #define DMA_SxCR_PFCTRL_Pos (5U)
lypinator 0:bb348c97df44 1491 #define DMA_SxCR_PFCTRL_Msk (0x1U << DMA_SxCR_PFCTRL_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 1492 #define DMA_SxCR_PFCTRL DMA_SxCR_PFCTRL_Msk
lypinator 0:bb348c97df44 1493 #define DMA_SxCR_TCIE_Pos (4U)
lypinator 0:bb348c97df44 1494 #define DMA_SxCR_TCIE_Msk (0x1U << DMA_SxCR_TCIE_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 1495 #define DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk
lypinator 0:bb348c97df44 1496 #define DMA_SxCR_HTIE_Pos (3U)
lypinator 0:bb348c97df44 1497 #define DMA_SxCR_HTIE_Msk (0x1U << DMA_SxCR_HTIE_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 1498 #define DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk
lypinator 0:bb348c97df44 1499 #define DMA_SxCR_TEIE_Pos (2U)
lypinator 0:bb348c97df44 1500 #define DMA_SxCR_TEIE_Msk (0x1U << DMA_SxCR_TEIE_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 1501 #define DMA_SxCR_TEIE DMA_SxCR_TEIE_Msk
lypinator 0:bb348c97df44 1502 #define DMA_SxCR_DMEIE_Pos (1U)
lypinator 0:bb348c97df44 1503 #define DMA_SxCR_DMEIE_Msk (0x1U << DMA_SxCR_DMEIE_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 1504 #define DMA_SxCR_DMEIE DMA_SxCR_DMEIE_Msk
lypinator 0:bb348c97df44 1505 #define DMA_SxCR_EN_Pos (0U)
lypinator 0:bb348c97df44 1506 #define DMA_SxCR_EN_Msk (0x1U << DMA_SxCR_EN_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 1507 #define DMA_SxCR_EN DMA_SxCR_EN_Msk
lypinator 0:bb348c97df44 1508
lypinator 0:bb348c97df44 1509 /* Legacy defines */
lypinator 0:bb348c97df44 1510 #define DMA_SxCR_ACK_Pos (20U)
lypinator 0:bb348c97df44 1511 #define DMA_SxCR_ACK_Msk (0x1U << DMA_SxCR_ACK_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 1512 #define DMA_SxCR_ACK DMA_SxCR_ACK_Msk
lypinator 0:bb348c97df44 1513
lypinator 0:bb348c97df44 1514 /******************** Bits definition for DMA_SxCNDTR register **************/
lypinator 0:bb348c97df44 1515 #define DMA_SxNDT_Pos (0U)
lypinator 0:bb348c97df44 1516 #define DMA_SxNDT_Msk (0xFFFFU << DMA_SxNDT_Pos) /*!< 0x0000FFFF */
lypinator 0:bb348c97df44 1517 #define DMA_SxNDT DMA_SxNDT_Msk
lypinator 0:bb348c97df44 1518 #define DMA_SxNDT_0 (0x0001U << DMA_SxNDT_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 1519 #define DMA_SxNDT_1 (0x0002U << DMA_SxNDT_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 1520 #define DMA_SxNDT_2 (0x0004U << DMA_SxNDT_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 1521 #define DMA_SxNDT_3 (0x0008U << DMA_SxNDT_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 1522 #define DMA_SxNDT_4 (0x0010U << DMA_SxNDT_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 1523 #define DMA_SxNDT_5 (0x0020U << DMA_SxNDT_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 1524 #define DMA_SxNDT_6 (0x0040U << DMA_SxNDT_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 1525 #define DMA_SxNDT_7 (0x0080U << DMA_SxNDT_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 1526 #define DMA_SxNDT_8 (0x0100U << DMA_SxNDT_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 1527 #define DMA_SxNDT_9 (0x0200U << DMA_SxNDT_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 1528 #define DMA_SxNDT_10 (0x0400U << DMA_SxNDT_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 1529 #define DMA_SxNDT_11 (0x0800U << DMA_SxNDT_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 1530 #define DMA_SxNDT_12 (0x1000U << DMA_SxNDT_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 1531 #define DMA_SxNDT_13 (0x2000U << DMA_SxNDT_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 1532 #define DMA_SxNDT_14 (0x4000U << DMA_SxNDT_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 1533 #define DMA_SxNDT_15 (0x8000U << DMA_SxNDT_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 1534
lypinator 0:bb348c97df44 1535 /******************** Bits definition for DMA_SxFCR register ****************/
lypinator 0:bb348c97df44 1536 #define DMA_SxFCR_FEIE_Pos (7U)
lypinator 0:bb348c97df44 1537 #define DMA_SxFCR_FEIE_Msk (0x1U << DMA_SxFCR_FEIE_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 1538 #define DMA_SxFCR_FEIE DMA_SxFCR_FEIE_Msk
lypinator 0:bb348c97df44 1539 #define DMA_SxFCR_FS_Pos (3U)
lypinator 0:bb348c97df44 1540 #define DMA_SxFCR_FS_Msk (0x7U << DMA_SxFCR_FS_Pos) /*!< 0x00000038 */
lypinator 0:bb348c97df44 1541 #define DMA_SxFCR_FS DMA_SxFCR_FS_Msk
lypinator 0:bb348c97df44 1542 #define DMA_SxFCR_FS_0 (0x1U << DMA_SxFCR_FS_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 1543 #define DMA_SxFCR_FS_1 (0x2U << DMA_SxFCR_FS_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 1544 #define DMA_SxFCR_FS_2 (0x4U << DMA_SxFCR_FS_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 1545 #define DMA_SxFCR_DMDIS_Pos (2U)
lypinator 0:bb348c97df44 1546 #define DMA_SxFCR_DMDIS_Msk (0x1U << DMA_SxFCR_DMDIS_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 1547 #define DMA_SxFCR_DMDIS DMA_SxFCR_DMDIS_Msk
lypinator 0:bb348c97df44 1548 #define DMA_SxFCR_FTH_Pos (0U)
lypinator 0:bb348c97df44 1549 #define DMA_SxFCR_FTH_Msk (0x3U << DMA_SxFCR_FTH_Pos) /*!< 0x00000003 */
lypinator 0:bb348c97df44 1550 #define DMA_SxFCR_FTH DMA_SxFCR_FTH_Msk
lypinator 0:bb348c97df44 1551 #define DMA_SxFCR_FTH_0 (0x1U << DMA_SxFCR_FTH_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 1552 #define DMA_SxFCR_FTH_1 (0x2U << DMA_SxFCR_FTH_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 1553
lypinator 0:bb348c97df44 1554 /******************** Bits definition for DMA_LISR register *****************/
lypinator 0:bb348c97df44 1555 #define DMA_LISR_TCIF3_Pos (27U)
lypinator 0:bb348c97df44 1556 #define DMA_LISR_TCIF3_Msk (0x1U << DMA_LISR_TCIF3_Pos) /*!< 0x08000000 */
lypinator 0:bb348c97df44 1557 #define DMA_LISR_TCIF3 DMA_LISR_TCIF3_Msk
lypinator 0:bb348c97df44 1558 #define DMA_LISR_HTIF3_Pos (26U)
lypinator 0:bb348c97df44 1559 #define DMA_LISR_HTIF3_Msk (0x1U << DMA_LISR_HTIF3_Pos) /*!< 0x04000000 */
lypinator 0:bb348c97df44 1560 #define DMA_LISR_HTIF3 DMA_LISR_HTIF3_Msk
lypinator 0:bb348c97df44 1561 #define DMA_LISR_TEIF3_Pos (25U)
lypinator 0:bb348c97df44 1562 #define DMA_LISR_TEIF3_Msk (0x1U << DMA_LISR_TEIF3_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 1563 #define DMA_LISR_TEIF3 DMA_LISR_TEIF3_Msk
lypinator 0:bb348c97df44 1564 #define DMA_LISR_DMEIF3_Pos (24U)
lypinator 0:bb348c97df44 1565 #define DMA_LISR_DMEIF3_Msk (0x1U << DMA_LISR_DMEIF3_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 1566 #define DMA_LISR_DMEIF3 DMA_LISR_DMEIF3_Msk
lypinator 0:bb348c97df44 1567 #define DMA_LISR_FEIF3_Pos (22U)
lypinator 0:bb348c97df44 1568 #define DMA_LISR_FEIF3_Msk (0x1U << DMA_LISR_FEIF3_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 1569 #define DMA_LISR_FEIF3 DMA_LISR_FEIF3_Msk
lypinator 0:bb348c97df44 1570 #define DMA_LISR_TCIF2_Pos (21U)
lypinator 0:bb348c97df44 1571 #define DMA_LISR_TCIF2_Msk (0x1U << DMA_LISR_TCIF2_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 1572 #define DMA_LISR_TCIF2 DMA_LISR_TCIF2_Msk
lypinator 0:bb348c97df44 1573 #define DMA_LISR_HTIF2_Pos (20U)
lypinator 0:bb348c97df44 1574 #define DMA_LISR_HTIF2_Msk (0x1U << DMA_LISR_HTIF2_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 1575 #define DMA_LISR_HTIF2 DMA_LISR_HTIF2_Msk
lypinator 0:bb348c97df44 1576 #define DMA_LISR_TEIF2_Pos (19U)
lypinator 0:bb348c97df44 1577 #define DMA_LISR_TEIF2_Msk (0x1U << DMA_LISR_TEIF2_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 1578 #define DMA_LISR_TEIF2 DMA_LISR_TEIF2_Msk
lypinator 0:bb348c97df44 1579 #define DMA_LISR_DMEIF2_Pos (18U)
lypinator 0:bb348c97df44 1580 #define DMA_LISR_DMEIF2_Msk (0x1U << DMA_LISR_DMEIF2_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 1581 #define DMA_LISR_DMEIF2 DMA_LISR_DMEIF2_Msk
lypinator 0:bb348c97df44 1582 #define DMA_LISR_FEIF2_Pos (16U)
lypinator 0:bb348c97df44 1583 #define DMA_LISR_FEIF2_Msk (0x1U << DMA_LISR_FEIF2_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 1584 #define DMA_LISR_FEIF2 DMA_LISR_FEIF2_Msk
lypinator 0:bb348c97df44 1585 #define DMA_LISR_TCIF1_Pos (11U)
lypinator 0:bb348c97df44 1586 #define DMA_LISR_TCIF1_Msk (0x1U << DMA_LISR_TCIF1_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 1587 #define DMA_LISR_TCIF1 DMA_LISR_TCIF1_Msk
lypinator 0:bb348c97df44 1588 #define DMA_LISR_HTIF1_Pos (10U)
lypinator 0:bb348c97df44 1589 #define DMA_LISR_HTIF1_Msk (0x1U << DMA_LISR_HTIF1_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 1590 #define DMA_LISR_HTIF1 DMA_LISR_HTIF1_Msk
lypinator 0:bb348c97df44 1591 #define DMA_LISR_TEIF1_Pos (9U)
lypinator 0:bb348c97df44 1592 #define DMA_LISR_TEIF1_Msk (0x1U << DMA_LISR_TEIF1_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 1593 #define DMA_LISR_TEIF1 DMA_LISR_TEIF1_Msk
lypinator 0:bb348c97df44 1594 #define DMA_LISR_DMEIF1_Pos (8U)
lypinator 0:bb348c97df44 1595 #define DMA_LISR_DMEIF1_Msk (0x1U << DMA_LISR_DMEIF1_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 1596 #define DMA_LISR_DMEIF1 DMA_LISR_DMEIF1_Msk
lypinator 0:bb348c97df44 1597 #define DMA_LISR_FEIF1_Pos (6U)
lypinator 0:bb348c97df44 1598 #define DMA_LISR_FEIF1_Msk (0x1U << DMA_LISR_FEIF1_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 1599 #define DMA_LISR_FEIF1 DMA_LISR_FEIF1_Msk
lypinator 0:bb348c97df44 1600 #define DMA_LISR_TCIF0_Pos (5U)
lypinator 0:bb348c97df44 1601 #define DMA_LISR_TCIF0_Msk (0x1U << DMA_LISR_TCIF0_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 1602 #define DMA_LISR_TCIF0 DMA_LISR_TCIF0_Msk
lypinator 0:bb348c97df44 1603 #define DMA_LISR_HTIF0_Pos (4U)
lypinator 0:bb348c97df44 1604 #define DMA_LISR_HTIF0_Msk (0x1U << DMA_LISR_HTIF0_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 1605 #define DMA_LISR_HTIF0 DMA_LISR_HTIF0_Msk
lypinator 0:bb348c97df44 1606 #define DMA_LISR_TEIF0_Pos (3U)
lypinator 0:bb348c97df44 1607 #define DMA_LISR_TEIF0_Msk (0x1U << DMA_LISR_TEIF0_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 1608 #define DMA_LISR_TEIF0 DMA_LISR_TEIF0_Msk
lypinator 0:bb348c97df44 1609 #define DMA_LISR_DMEIF0_Pos (2U)
lypinator 0:bb348c97df44 1610 #define DMA_LISR_DMEIF0_Msk (0x1U << DMA_LISR_DMEIF0_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 1611 #define DMA_LISR_DMEIF0 DMA_LISR_DMEIF0_Msk
lypinator 0:bb348c97df44 1612 #define DMA_LISR_FEIF0_Pos (0U)
lypinator 0:bb348c97df44 1613 #define DMA_LISR_FEIF0_Msk (0x1U << DMA_LISR_FEIF0_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 1614 #define DMA_LISR_FEIF0 DMA_LISR_FEIF0_Msk
lypinator 0:bb348c97df44 1615
lypinator 0:bb348c97df44 1616 /******************** Bits definition for DMA_HISR register *****************/
lypinator 0:bb348c97df44 1617 #define DMA_HISR_TCIF7_Pos (27U)
lypinator 0:bb348c97df44 1618 #define DMA_HISR_TCIF7_Msk (0x1U << DMA_HISR_TCIF7_Pos) /*!< 0x08000000 */
lypinator 0:bb348c97df44 1619 #define DMA_HISR_TCIF7 DMA_HISR_TCIF7_Msk
lypinator 0:bb348c97df44 1620 #define DMA_HISR_HTIF7_Pos (26U)
lypinator 0:bb348c97df44 1621 #define DMA_HISR_HTIF7_Msk (0x1U << DMA_HISR_HTIF7_Pos) /*!< 0x04000000 */
lypinator 0:bb348c97df44 1622 #define DMA_HISR_HTIF7 DMA_HISR_HTIF7_Msk
lypinator 0:bb348c97df44 1623 #define DMA_HISR_TEIF7_Pos (25U)
lypinator 0:bb348c97df44 1624 #define DMA_HISR_TEIF7_Msk (0x1U << DMA_HISR_TEIF7_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 1625 #define DMA_HISR_TEIF7 DMA_HISR_TEIF7_Msk
lypinator 0:bb348c97df44 1626 #define DMA_HISR_DMEIF7_Pos (24U)
lypinator 0:bb348c97df44 1627 #define DMA_HISR_DMEIF7_Msk (0x1U << DMA_HISR_DMEIF7_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 1628 #define DMA_HISR_DMEIF7 DMA_HISR_DMEIF7_Msk
lypinator 0:bb348c97df44 1629 #define DMA_HISR_FEIF7_Pos (22U)
lypinator 0:bb348c97df44 1630 #define DMA_HISR_FEIF7_Msk (0x1U << DMA_HISR_FEIF7_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 1631 #define DMA_HISR_FEIF7 DMA_HISR_FEIF7_Msk
lypinator 0:bb348c97df44 1632 #define DMA_HISR_TCIF6_Pos (21U)
lypinator 0:bb348c97df44 1633 #define DMA_HISR_TCIF6_Msk (0x1U << DMA_HISR_TCIF6_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 1634 #define DMA_HISR_TCIF6 DMA_HISR_TCIF6_Msk
lypinator 0:bb348c97df44 1635 #define DMA_HISR_HTIF6_Pos (20U)
lypinator 0:bb348c97df44 1636 #define DMA_HISR_HTIF6_Msk (0x1U << DMA_HISR_HTIF6_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 1637 #define DMA_HISR_HTIF6 DMA_HISR_HTIF6_Msk
lypinator 0:bb348c97df44 1638 #define DMA_HISR_TEIF6_Pos (19U)
lypinator 0:bb348c97df44 1639 #define DMA_HISR_TEIF6_Msk (0x1U << DMA_HISR_TEIF6_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 1640 #define DMA_HISR_TEIF6 DMA_HISR_TEIF6_Msk
lypinator 0:bb348c97df44 1641 #define DMA_HISR_DMEIF6_Pos (18U)
lypinator 0:bb348c97df44 1642 #define DMA_HISR_DMEIF6_Msk (0x1U << DMA_HISR_DMEIF6_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 1643 #define DMA_HISR_DMEIF6 DMA_HISR_DMEIF6_Msk
lypinator 0:bb348c97df44 1644 #define DMA_HISR_FEIF6_Pos (16U)
lypinator 0:bb348c97df44 1645 #define DMA_HISR_FEIF6_Msk (0x1U << DMA_HISR_FEIF6_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 1646 #define DMA_HISR_FEIF6 DMA_HISR_FEIF6_Msk
lypinator 0:bb348c97df44 1647 #define DMA_HISR_TCIF5_Pos (11U)
lypinator 0:bb348c97df44 1648 #define DMA_HISR_TCIF5_Msk (0x1U << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 1649 #define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk
lypinator 0:bb348c97df44 1650 #define DMA_HISR_HTIF5_Pos (10U)
lypinator 0:bb348c97df44 1651 #define DMA_HISR_HTIF5_Msk (0x1U << DMA_HISR_HTIF5_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 1652 #define DMA_HISR_HTIF5 DMA_HISR_HTIF5_Msk
lypinator 0:bb348c97df44 1653 #define DMA_HISR_TEIF5_Pos (9U)
lypinator 0:bb348c97df44 1654 #define DMA_HISR_TEIF5_Msk (0x1U << DMA_HISR_TEIF5_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 1655 #define DMA_HISR_TEIF5 DMA_HISR_TEIF5_Msk
lypinator 0:bb348c97df44 1656 #define DMA_HISR_DMEIF5_Pos (8U)
lypinator 0:bb348c97df44 1657 #define DMA_HISR_DMEIF5_Msk (0x1U << DMA_HISR_DMEIF5_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 1658 #define DMA_HISR_DMEIF5 DMA_HISR_DMEIF5_Msk
lypinator 0:bb348c97df44 1659 #define DMA_HISR_FEIF5_Pos (6U)
lypinator 0:bb348c97df44 1660 #define DMA_HISR_FEIF5_Msk (0x1U << DMA_HISR_FEIF5_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 1661 #define DMA_HISR_FEIF5 DMA_HISR_FEIF5_Msk
lypinator 0:bb348c97df44 1662 #define DMA_HISR_TCIF4_Pos (5U)
lypinator 0:bb348c97df44 1663 #define DMA_HISR_TCIF4_Msk (0x1U << DMA_HISR_TCIF4_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 1664 #define DMA_HISR_TCIF4 DMA_HISR_TCIF4_Msk
lypinator 0:bb348c97df44 1665 #define DMA_HISR_HTIF4_Pos (4U)
lypinator 0:bb348c97df44 1666 #define DMA_HISR_HTIF4_Msk (0x1U << DMA_HISR_HTIF4_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 1667 #define DMA_HISR_HTIF4 DMA_HISR_HTIF4_Msk
lypinator 0:bb348c97df44 1668 #define DMA_HISR_TEIF4_Pos (3U)
lypinator 0:bb348c97df44 1669 #define DMA_HISR_TEIF4_Msk (0x1U << DMA_HISR_TEIF4_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 1670 #define DMA_HISR_TEIF4 DMA_HISR_TEIF4_Msk
lypinator 0:bb348c97df44 1671 #define DMA_HISR_DMEIF4_Pos (2U)
lypinator 0:bb348c97df44 1672 #define DMA_HISR_DMEIF4_Msk (0x1U << DMA_HISR_DMEIF4_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 1673 #define DMA_HISR_DMEIF4 DMA_HISR_DMEIF4_Msk
lypinator 0:bb348c97df44 1674 #define DMA_HISR_FEIF4_Pos (0U)
lypinator 0:bb348c97df44 1675 #define DMA_HISR_FEIF4_Msk (0x1U << DMA_HISR_FEIF4_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 1676 #define DMA_HISR_FEIF4 DMA_HISR_FEIF4_Msk
lypinator 0:bb348c97df44 1677
lypinator 0:bb348c97df44 1678 /******************** Bits definition for DMA_LIFCR register ****************/
lypinator 0:bb348c97df44 1679 #define DMA_LIFCR_CTCIF3_Pos (27U)
lypinator 0:bb348c97df44 1680 #define DMA_LIFCR_CTCIF3_Msk (0x1U << DMA_LIFCR_CTCIF3_Pos) /*!< 0x08000000 */
lypinator 0:bb348c97df44 1681 #define DMA_LIFCR_CTCIF3 DMA_LIFCR_CTCIF3_Msk
lypinator 0:bb348c97df44 1682 #define DMA_LIFCR_CHTIF3_Pos (26U)
lypinator 0:bb348c97df44 1683 #define DMA_LIFCR_CHTIF3_Msk (0x1U << DMA_LIFCR_CHTIF3_Pos) /*!< 0x04000000 */
lypinator 0:bb348c97df44 1684 #define DMA_LIFCR_CHTIF3 DMA_LIFCR_CHTIF3_Msk
lypinator 0:bb348c97df44 1685 #define DMA_LIFCR_CTEIF3_Pos (25U)
lypinator 0:bb348c97df44 1686 #define DMA_LIFCR_CTEIF3_Msk (0x1U << DMA_LIFCR_CTEIF3_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 1687 #define DMA_LIFCR_CTEIF3 DMA_LIFCR_CTEIF3_Msk
lypinator 0:bb348c97df44 1688 #define DMA_LIFCR_CDMEIF3_Pos (24U)
lypinator 0:bb348c97df44 1689 #define DMA_LIFCR_CDMEIF3_Msk (0x1U << DMA_LIFCR_CDMEIF3_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 1690 #define DMA_LIFCR_CDMEIF3 DMA_LIFCR_CDMEIF3_Msk
lypinator 0:bb348c97df44 1691 #define DMA_LIFCR_CFEIF3_Pos (22U)
lypinator 0:bb348c97df44 1692 #define DMA_LIFCR_CFEIF3_Msk (0x1U << DMA_LIFCR_CFEIF3_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 1693 #define DMA_LIFCR_CFEIF3 DMA_LIFCR_CFEIF3_Msk
lypinator 0:bb348c97df44 1694 #define DMA_LIFCR_CTCIF2_Pos (21U)
lypinator 0:bb348c97df44 1695 #define DMA_LIFCR_CTCIF2_Msk (0x1U << DMA_LIFCR_CTCIF2_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 1696 #define DMA_LIFCR_CTCIF2 DMA_LIFCR_CTCIF2_Msk
lypinator 0:bb348c97df44 1697 #define DMA_LIFCR_CHTIF2_Pos (20U)
lypinator 0:bb348c97df44 1698 #define DMA_LIFCR_CHTIF2_Msk (0x1U << DMA_LIFCR_CHTIF2_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 1699 #define DMA_LIFCR_CHTIF2 DMA_LIFCR_CHTIF2_Msk
lypinator 0:bb348c97df44 1700 #define DMA_LIFCR_CTEIF2_Pos (19U)
lypinator 0:bb348c97df44 1701 #define DMA_LIFCR_CTEIF2_Msk (0x1U << DMA_LIFCR_CTEIF2_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 1702 #define DMA_LIFCR_CTEIF2 DMA_LIFCR_CTEIF2_Msk
lypinator 0:bb348c97df44 1703 #define DMA_LIFCR_CDMEIF2_Pos (18U)
lypinator 0:bb348c97df44 1704 #define DMA_LIFCR_CDMEIF2_Msk (0x1U << DMA_LIFCR_CDMEIF2_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 1705 #define DMA_LIFCR_CDMEIF2 DMA_LIFCR_CDMEIF2_Msk
lypinator 0:bb348c97df44 1706 #define DMA_LIFCR_CFEIF2_Pos (16U)
lypinator 0:bb348c97df44 1707 #define DMA_LIFCR_CFEIF2_Msk (0x1U << DMA_LIFCR_CFEIF2_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 1708 #define DMA_LIFCR_CFEIF2 DMA_LIFCR_CFEIF2_Msk
lypinator 0:bb348c97df44 1709 #define DMA_LIFCR_CTCIF1_Pos (11U)
lypinator 0:bb348c97df44 1710 #define DMA_LIFCR_CTCIF1_Msk (0x1U << DMA_LIFCR_CTCIF1_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 1711 #define DMA_LIFCR_CTCIF1 DMA_LIFCR_CTCIF1_Msk
lypinator 0:bb348c97df44 1712 #define DMA_LIFCR_CHTIF1_Pos (10U)
lypinator 0:bb348c97df44 1713 #define DMA_LIFCR_CHTIF1_Msk (0x1U << DMA_LIFCR_CHTIF1_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 1714 #define DMA_LIFCR_CHTIF1 DMA_LIFCR_CHTIF1_Msk
lypinator 0:bb348c97df44 1715 #define DMA_LIFCR_CTEIF1_Pos (9U)
lypinator 0:bb348c97df44 1716 #define DMA_LIFCR_CTEIF1_Msk (0x1U << DMA_LIFCR_CTEIF1_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 1717 #define DMA_LIFCR_CTEIF1 DMA_LIFCR_CTEIF1_Msk
lypinator 0:bb348c97df44 1718 #define DMA_LIFCR_CDMEIF1_Pos (8U)
lypinator 0:bb348c97df44 1719 #define DMA_LIFCR_CDMEIF1_Msk (0x1U << DMA_LIFCR_CDMEIF1_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 1720 #define DMA_LIFCR_CDMEIF1 DMA_LIFCR_CDMEIF1_Msk
lypinator 0:bb348c97df44 1721 #define DMA_LIFCR_CFEIF1_Pos (6U)
lypinator 0:bb348c97df44 1722 #define DMA_LIFCR_CFEIF1_Msk (0x1U << DMA_LIFCR_CFEIF1_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 1723 #define DMA_LIFCR_CFEIF1 DMA_LIFCR_CFEIF1_Msk
lypinator 0:bb348c97df44 1724 #define DMA_LIFCR_CTCIF0_Pos (5U)
lypinator 0:bb348c97df44 1725 #define DMA_LIFCR_CTCIF0_Msk (0x1U << DMA_LIFCR_CTCIF0_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 1726 #define DMA_LIFCR_CTCIF0 DMA_LIFCR_CTCIF0_Msk
lypinator 0:bb348c97df44 1727 #define DMA_LIFCR_CHTIF0_Pos (4U)
lypinator 0:bb348c97df44 1728 #define DMA_LIFCR_CHTIF0_Msk (0x1U << DMA_LIFCR_CHTIF0_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 1729 #define DMA_LIFCR_CHTIF0 DMA_LIFCR_CHTIF0_Msk
lypinator 0:bb348c97df44 1730 #define DMA_LIFCR_CTEIF0_Pos (3U)
lypinator 0:bb348c97df44 1731 #define DMA_LIFCR_CTEIF0_Msk (0x1U << DMA_LIFCR_CTEIF0_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 1732 #define DMA_LIFCR_CTEIF0 DMA_LIFCR_CTEIF0_Msk
lypinator 0:bb348c97df44 1733 #define DMA_LIFCR_CDMEIF0_Pos (2U)
lypinator 0:bb348c97df44 1734 #define DMA_LIFCR_CDMEIF0_Msk (0x1U << DMA_LIFCR_CDMEIF0_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 1735 #define DMA_LIFCR_CDMEIF0 DMA_LIFCR_CDMEIF0_Msk
lypinator 0:bb348c97df44 1736 #define DMA_LIFCR_CFEIF0_Pos (0U)
lypinator 0:bb348c97df44 1737 #define DMA_LIFCR_CFEIF0_Msk (0x1U << DMA_LIFCR_CFEIF0_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 1738 #define DMA_LIFCR_CFEIF0 DMA_LIFCR_CFEIF0_Msk
lypinator 0:bb348c97df44 1739
lypinator 0:bb348c97df44 1740 /******************** Bits definition for DMA_HIFCR register ****************/
lypinator 0:bb348c97df44 1741 #define DMA_HIFCR_CTCIF7_Pos (27U)
lypinator 0:bb348c97df44 1742 #define DMA_HIFCR_CTCIF7_Msk (0x1U << DMA_HIFCR_CTCIF7_Pos) /*!< 0x08000000 */
lypinator 0:bb348c97df44 1743 #define DMA_HIFCR_CTCIF7 DMA_HIFCR_CTCIF7_Msk
lypinator 0:bb348c97df44 1744 #define DMA_HIFCR_CHTIF7_Pos (26U)
lypinator 0:bb348c97df44 1745 #define DMA_HIFCR_CHTIF7_Msk (0x1U << DMA_HIFCR_CHTIF7_Pos) /*!< 0x04000000 */
lypinator 0:bb348c97df44 1746 #define DMA_HIFCR_CHTIF7 DMA_HIFCR_CHTIF7_Msk
lypinator 0:bb348c97df44 1747 #define DMA_HIFCR_CTEIF7_Pos (25U)
lypinator 0:bb348c97df44 1748 #define DMA_HIFCR_CTEIF7_Msk (0x1U << DMA_HIFCR_CTEIF7_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 1749 #define DMA_HIFCR_CTEIF7 DMA_HIFCR_CTEIF7_Msk
lypinator 0:bb348c97df44 1750 #define DMA_HIFCR_CDMEIF7_Pos (24U)
lypinator 0:bb348c97df44 1751 #define DMA_HIFCR_CDMEIF7_Msk (0x1U << DMA_HIFCR_CDMEIF7_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 1752 #define DMA_HIFCR_CDMEIF7 DMA_HIFCR_CDMEIF7_Msk
lypinator 0:bb348c97df44 1753 #define DMA_HIFCR_CFEIF7_Pos (22U)
lypinator 0:bb348c97df44 1754 #define DMA_HIFCR_CFEIF7_Msk (0x1U << DMA_HIFCR_CFEIF7_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 1755 #define DMA_HIFCR_CFEIF7 DMA_HIFCR_CFEIF7_Msk
lypinator 0:bb348c97df44 1756 #define DMA_HIFCR_CTCIF6_Pos (21U)
lypinator 0:bb348c97df44 1757 #define DMA_HIFCR_CTCIF6_Msk (0x1U << DMA_HIFCR_CTCIF6_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 1758 #define DMA_HIFCR_CTCIF6 DMA_HIFCR_CTCIF6_Msk
lypinator 0:bb348c97df44 1759 #define DMA_HIFCR_CHTIF6_Pos (20U)
lypinator 0:bb348c97df44 1760 #define DMA_HIFCR_CHTIF6_Msk (0x1U << DMA_HIFCR_CHTIF6_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 1761 #define DMA_HIFCR_CHTIF6 DMA_HIFCR_CHTIF6_Msk
lypinator 0:bb348c97df44 1762 #define DMA_HIFCR_CTEIF6_Pos (19U)
lypinator 0:bb348c97df44 1763 #define DMA_HIFCR_CTEIF6_Msk (0x1U << DMA_HIFCR_CTEIF6_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 1764 #define DMA_HIFCR_CTEIF6 DMA_HIFCR_CTEIF6_Msk
lypinator 0:bb348c97df44 1765 #define DMA_HIFCR_CDMEIF6_Pos (18U)
lypinator 0:bb348c97df44 1766 #define DMA_HIFCR_CDMEIF6_Msk (0x1U << DMA_HIFCR_CDMEIF6_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 1767 #define DMA_HIFCR_CDMEIF6 DMA_HIFCR_CDMEIF6_Msk
lypinator 0:bb348c97df44 1768 #define DMA_HIFCR_CFEIF6_Pos (16U)
lypinator 0:bb348c97df44 1769 #define DMA_HIFCR_CFEIF6_Msk (0x1U << DMA_HIFCR_CFEIF6_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 1770 #define DMA_HIFCR_CFEIF6 DMA_HIFCR_CFEIF6_Msk
lypinator 0:bb348c97df44 1771 #define DMA_HIFCR_CTCIF5_Pos (11U)
lypinator 0:bb348c97df44 1772 #define DMA_HIFCR_CTCIF5_Msk (0x1U << DMA_HIFCR_CTCIF5_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 1773 #define DMA_HIFCR_CTCIF5 DMA_HIFCR_CTCIF5_Msk
lypinator 0:bb348c97df44 1774 #define DMA_HIFCR_CHTIF5_Pos (10U)
lypinator 0:bb348c97df44 1775 #define DMA_HIFCR_CHTIF5_Msk (0x1U << DMA_HIFCR_CHTIF5_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 1776 #define DMA_HIFCR_CHTIF5 DMA_HIFCR_CHTIF5_Msk
lypinator 0:bb348c97df44 1777 #define DMA_HIFCR_CTEIF5_Pos (9U)
lypinator 0:bb348c97df44 1778 #define DMA_HIFCR_CTEIF5_Msk (0x1U << DMA_HIFCR_CTEIF5_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 1779 #define DMA_HIFCR_CTEIF5 DMA_HIFCR_CTEIF5_Msk
lypinator 0:bb348c97df44 1780 #define DMA_HIFCR_CDMEIF5_Pos (8U)
lypinator 0:bb348c97df44 1781 #define DMA_HIFCR_CDMEIF5_Msk (0x1U << DMA_HIFCR_CDMEIF5_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 1782 #define DMA_HIFCR_CDMEIF5 DMA_HIFCR_CDMEIF5_Msk
lypinator 0:bb348c97df44 1783 #define DMA_HIFCR_CFEIF5_Pos (6U)
lypinator 0:bb348c97df44 1784 #define DMA_HIFCR_CFEIF5_Msk (0x1U << DMA_HIFCR_CFEIF5_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 1785 #define DMA_HIFCR_CFEIF5 DMA_HIFCR_CFEIF5_Msk
lypinator 0:bb348c97df44 1786 #define DMA_HIFCR_CTCIF4_Pos (5U)
lypinator 0:bb348c97df44 1787 #define DMA_HIFCR_CTCIF4_Msk (0x1U << DMA_HIFCR_CTCIF4_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 1788 #define DMA_HIFCR_CTCIF4 DMA_HIFCR_CTCIF4_Msk
lypinator 0:bb348c97df44 1789 #define DMA_HIFCR_CHTIF4_Pos (4U)
lypinator 0:bb348c97df44 1790 #define DMA_HIFCR_CHTIF4_Msk (0x1U << DMA_HIFCR_CHTIF4_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 1791 #define DMA_HIFCR_CHTIF4 DMA_HIFCR_CHTIF4_Msk
lypinator 0:bb348c97df44 1792 #define DMA_HIFCR_CTEIF4_Pos (3U)
lypinator 0:bb348c97df44 1793 #define DMA_HIFCR_CTEIF4_Msk (0x1U << DMA_HIFCR_CTEIF4_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 1794 #define DMA_HIFCR_CTEIF4 DMA_HIFCR_CTEIF4_Msk
lypinator 0:bb348c97df44 1795 #define DMA_HIFCR_CDMEIF4_Pos (2U)
lypinator 0:bb348c97df44 1796 #define DMA_HIFCR_CDMEIF4_Msk (0x1U << DMA_HIFCR_CDMEIF4_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 1797 #define DMA_HIFCR_CDMEIF4 DMA_HIFCR_CDMEIF4_Msk
lypinator 0:bb348c97df44 1798 #define DMA_HIFCR_CFEIF4_Pos (0U)
lypinator 0:bb348c97df44 1799 #define DMA_HIFCR_CFEIF4_Msk (0x1U << DMA_HIFCR_CFEIF4_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 1800 #define DMA_HIFCR_CFEIF4 DMA_HIFCR_CFEIF4_Msk
lypinator 0:bb348c97df44 1801
lypinator 0:bb348c97df44 1802 /****************** Bit definition for DMA_SxPAR register ********************/
lypinator 0:bb348c97df44 1803 #define DMA_SxPAR_PA_Pos (0U)
lypinator 0:bb348c97df44 1804 #define DMA_SxPAR_PA_Msk (0xFFFFFFFFU << DMA_SxPAR_PA_Pos) /*!< 0xFFFFFFFF */
lypinator 0:bb348c97df44 1805 #define DMA_SxPAR_PA DMA_SxPAR_PA_Msk /*!< Peripheral Address */
lypinator 0:bb348c97df44 1806
lypinator 0:bb348c97df44 1807 /****************** Bit definition for DMA_SxM0AR register ********************/
lypinator 0:bb348c97df44 1808 #define DMA_SxM0AR_M0A_Pos (0U)
lypinator 0:bb348c97df44 1809 #define DMA_SxM0AR_M0A_Msk (0xFFFFFFFFU << DMA_SxM0AR_M0A_Pos) /*!< 0xFFFFFFFF */
lypinator 0:bb348c97df44 1810 #define DMA_SxM0AR_M0A DMA_SxM0AR_M0A_Msk /*!< Memory Address */
lypinator 0:bb348c97df44 1811
lypinator 0:bb348c97df44 1812 /****************** Bit definition for DMA_SxM1AR register ********************/
lypinator 0:bb348c97df44 1813 #define DMA_SxM1AR_M1A_Pos (0U)
lypinator 0:bb348c97df44 1814 #define DMA_SxM1AR_M1A_Msk (0xFFFFFFFFU << DMA_SxM1AR_M1A_Pos) /*!< 0xFFFFFFFF */
lypinator 0:bb348c97df44 1815 #define DMA_SxM1AR_M1A DMA_SxM1AR_M1A_Msk /*!< Memory Address */
lypinator 0:bb348c97df44 1816
lypinator 0:bb348c97df44 1817
lypinator 0:bb348c97df44 1818 /******************************************************************************/
lypinator 0:bb348c97df44 1819 /* */
lypinator 0:bb348c97df44 1820 /* External Interrupt/Event Controller */
lypinator 0:bb348c97df44 1821 /* */
lypinator 0:bb348c97df44 1822 /******************************************************************************/
lypinator 0:bb348c97df44 1823 /******************* Bit definition for EXTI_IMR register *******************/
lypinator 0:bb348c97df44 1824 #define EXTI_IMR_MR0_Pos (0U)
lypinator 0:bb348c97df44 1825 #define EXTI_IMR_MR0_Msk (0x1U << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 1826 #define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */
lypinator 0:bb348c97df44 1827 #define EXTI_IMR_MR1_Pos (1U)
lypinator 0:bb348c97df44 1828 #define EXTI_IMR_MR1_Msk (0x1U << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 1829 #define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */
lypinator 0:bb348c97df44 1830 #define EXTI_IMR_MR2_Pos (2U)
lypinator 0:bb348c97df44 1831 #define EXTI_IMR_MR2_Msk (0x1U << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 1832 #define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */
lypinator 0:bb348c97df44 1833 #define EXTI_IMR_MR3_Pos (3U)
lypinator 0:bb348c97df44 1834 #define EXTI_IMR_MR3_Msk (0x1U << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 1835 #define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */
lypinator 0:bb348c97df44 1836 #define EXTI_IMR_MR4_Pos (4U)
lypinator 0:bb348c97df44 1837 #define EXTI_IMR_MR4_Msk (0x1U << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 1838 #define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */
lypinator 0:bb348c97df44 1839 #define EXTI_IMR_MR5_Pos (5U)
lypinator 0:bb348c97df44 1840 #define EXTI_IMR_MR5_Msk (0x1U << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 1841 #define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */
lypinator 0:bb348c97df44 1842 #define EXTI_IMR_MR6_Pos (6U)
lypinator 0:bb348c97df44 1843 #define EXTI_IMR_MR6_Msk (0x1U << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 1844 #define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */
lypinator 0:bb348c97df44 1845 #define EXTI_IMR_MR7_Pos (7U)
lypinator 0:bb348c97df44 1846 #define EXTI_IMR_MR7_Msk (0x1U << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 1847 #define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */
lypinator 0:bb348c97df44 1848 #define EXTI_IMR_MR8_Pos (8U)
lypinator 0:bb348c97df44 1849 #define EXTI_IMR_MR8_Msk (0x1U << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 1850 #define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */
lypinator 0:bb348c97df44 1851 #define EXTI_IMR_MR9_Pos (9U)
lypinator 0:bb348c97df44 1852 #define EXTI_IMR_MR9_Msk (0x1U << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 1853 #define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */
lypinator 0:bb348c97df44 1854 #define EXTI_IMR_MR10_Pos (10U)
lypinator 0:bb348c97df44 1855 #define EXTI_IMR_MR10_Msk (0x1U << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 1856 #define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */
lypinator 0:bb348c97df44 1857 #define EXTI_IMR_MR11_Pos (11U)
lypinator 0:bb348c97df44 1858 #define EXTI_IMR_MR11_Msk (0x1U << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 1859 #define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */
lypinator 0:bb348c97df44 1860 #define EXTI_IMR_MR12_Pos (12U)
lypinator 0:bb348c97df44 1861 #define EXTI_IMR_MR12_Msk (0x1U << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 1862 #define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */
lypinator 0:bb348c97df44 1863 #define EXTI_IMR_MR13_Pos (13U)
lypinator 0:bb348c97df44 1864 #define EXTI_IMR_MR13_Msk (0x1U << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 1865 #define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */
lypinator 0:bb348c97df44 1866 #define EXTI_IMR_MR14_Pos (14U)
lypinator 0:bb348c97df44 1867 #define EXTI_IMR_MR14_Msk (0x1U << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 1868 #define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */
lypinator 0:bb348c97df44 1869 #define EXTI_IMR_MR15_Pos (15U)
lypinator 0:bb348c97df44 1870 #define EXTI_IMR_MR15_Msk (0x1U << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 1871 #define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */
lypinator 0:bb348c97df44 1872 #define EXTI_IMR_MR16_Pos (16U)
lypinator 0:bb348c97df44 1873 #define EXTI_IMR_MR16_Msk (0x1U << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 1874 #define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */
lypinator 0:bb348c97df44 1875 #define EXTI_IMR_MR17_Pos (17U)
lypinator 0:bb348c97df44 1876 #define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 1877 #define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */
lypinator 0:bb348c97df44 1878 #define EXTI_IMR_MR18_Pos (18U)
lypinator 0:bb348c97df44 1879 #define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 1880 #define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */
lypinator 0:bb348c97df44 1881 #define EXTI_IMR_MR19_Pos (19U)
lypinator 0:bb348c97df44 1882 #define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 1883 #define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */
lypinator 0:bb348c97df44 1884 #define EXTI_IMR_MR20_Pos (20U)
lypinator 0:bb348c97df44 1885 #define EXTI_IMR_MR20_Msk (0x1U << EXTI_IMR_MR20_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 1886 #define EXTI_IMR_MR20 EXTI_IMR_MR20_Msk /*!< Interrupt Mask on line 20 */
lypinator 0:bb348c97df44 1887 #define EXTI_IMR_MR21_Pos (21U)
lypinator 0:bb348c97df44 1888 #define EXTI_IMR_MR21_Msk (0x1U << EXTI_IMR_MR21_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 1889 #define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk /*!< Interrupt Mask on line 21 */
lypinator 0:bb348c97df44 1890 #define EXTI_IMR_MR22_Pos (22U)
lypinator 0:bb348c97df44 1891 #define EXTI_IMR_MR22_Msk (0x1U << EXTI_IMR_MR22_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 1892 #define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk /*!< Interrupt Mask on line 22 */
lypinator 0:bb348c97df44 1893
lypinator 0:bb348c97df44 1894 /* Reference Defines */
lypinator 0:bb348c97df44 1895 #define EXTI_IMR_IM0 EXTI_IMR_MR0
lypinator 0:bb348c97df44 1896 #define EXTI_IMR_IM1 EXTI_IMR_MR1
lypinator 0:bb348c97df44 1897 #define EXTI_IMR_IM2 EXTI_IMR_MR2
lypinator 0:bb348c97df44 1898 #define EXTI_IMR_IM3 EXTI_IMR_MR3
lypinator 0:bb348c97df44 1899 #define EXTI_IMR_IM4 EXTI_IMR_MR4
lypinator 0:bb348c97df44 1900 #define EXTI_IMR_IM5 EXTI_IMR_MR5
lypinator 0:bb348c97df44 1901 #define EXTI_IMR_IM6 EXTI_IMR_MR6
lypinator 0:bb348c97df44 1902 #define EXTI_IMR_IM7 EXTI_IMR_MR7
lypinator 0:bb348c97df44 1903 #define EXTI_IMR_IM8 EXTI_IMR_MR8
lypinator 0:bb348c97df44 1904 #define EXTI_IMR_IM9 EXTI_IMR_MR9
lypinator 0:bb348c97df44 1905 #define EXTI_IMR_IM10 EXTI_IMR_MR10
lypinator 0:bb348c97df44 1906 #define EXTI_IMR_IM11 EXTI_IMR_MR11
lypinator 0:bb348c97df44 1907 #define EXTI_IMR_IM12 EXTI_IMR_MR12
lypinator 0:bb348c97df44 1908 #define EXTI_IMR_IM13 EXTI_IMR_MR13
lypinator 0:bb348c97df44 1909 #define EXTI_IMR_IM14 EXTI_IMR_MR14
lypinator 0:bb348c97df44 1910 #define EXTI_IMR_IM15 EXTI_IMR_MR15
lypinator 0:bb348c97df44 1911 #define EXTI_IMR_IM16 EXTI_IMR_MR16
lypinator 0:bb348c97df44 1912 #define EXTI_IMR_IM17 EXTI_IMR_MR17
lypinator 0:bb348c97df44 1913 #define EXTI_IMR_IM18 EXTI_IMR_MR18
lypinator 0:bb348c97df44 1914 #define EXTI_IMR_IM19 EXTI_IMR_MR19
lypinator 0:bb348c97df44 1915 #define EXTI_IMR_IM20 EXTI_IMR_MR20
lypinator 0:bb348c97df44 1916 #define EXTI_IMR_IM21 EXTI_IMR_MR21
lypinator 0:bb348c97df44 1917 #define EXTI_IMR_IM22 EXTI_IMR_MR22
lypinator 0:bb348c97df44 1918 #define EXTI_IMR_IM_Pos (0U)
lypinator 0:bb348c97df44 1919 #define EXTI_IMR_IM_Msk (0x7FFFFFU << EXTI_IMR_IM_Pos) /*!< 0x007FFFFF */
lypinator 0:bb348c97df44 1920 #define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */
lypinator 0:bb348c97df44 1921
lypinator 0:bb348c97df44 1922 /******************* Bit definition for EXTI_EMR register *******************/
lypinator 0:bb348c97df44 1923 #define EXTI_EMR_MR0_Pos (0U)
lypinator 0:bb348c97df44 1924 #define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 1925 #define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */
lypinator 0:bb348c97df44 1926 #define EXTI_EMR_MR1_Pos (1U)
lypinator 0:bb348c97df44 1927 #define EXTI_EMR_MR1_Msk (0x1U << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 1928 #define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */
lypinator 0:bb348c97df44 1929 #define EXTI_EMR_MR2_Pos (2U)
lypinator 0:bb348c97df44 1930 #define EXTI_EMR_MR2_Msk (0x1U << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 1931 #define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */
lypinator 0:bb348c97df44 1932 #define EXTI_EMR_MR3_Pos (3U)
lypinator 0:bb348c97df44 1933 #define EXTI_EMR_MR3_Msk (0x1U << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 1934 #define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */
lypinator 0:bb348c97df44 1935 #define EXTI_EMR_MR4_Pos (4U)
lypinator 0:bb348c97df44 1936 #define EXTI_EMR_MR4_Msk (0x1U << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 1937 #define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */
lypinator 0:bb348c97df44 1938 #define EXTI_EMR_MR5_Pos (5U)
lypinator 0:bb348c97df44 1939 #define EXTI_EMR_MR5_Msk (0x1U << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 1940 #define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */
lypinator 0:bb348c97df44 1941 #define EXTI_EMR_MR6_Pos (6U)
lypinator 0:bb348c97df44 1942 #define EXTI_EMR_MR6_Msk (0x1U << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 1943 #define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */
lypinator 0:bb348c97df44 1944 #define EXTI_EMR_MR7_Pos (7U)
lypinator 0:bb348c97df44 1945 #define EXTI_EMR_MR7_Msk (0x1U << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 1946 #define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */
lypinator 0:bb348c97df44 1947 #define EXTI_EMR_MR8_Pos (8U)
lypinator 0:bb348c97df44 1948 #define EXTI_EMR_MR8_Msk (0x1U << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 1949 #define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */
lypinator 0:bb348c97df44 1950 #define EXTI_EMR_MR9_Pos (9U)
lypinator 0:bb348c97df44 1951 #define EXTI_EMR_MR9_Msk (0x1U << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 1952 #define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */
lypinator 0:bb348c97df44 1953 #define EXTI_EMR_MR10_Pos (10U)
lypinator 0:bb348c97df44 1954 #define EXTI_EMR_MR10_Msk (0x1U << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 1955 #define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */
lypinator 0:bb348c97df44 1956 #define EXTI_EMR_MR11_Pos (11U)
lypinator 0:bb348c97df44 1957 #define EXTI_EMR_MR11_Msk (0x1U << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 1958 #define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */
lypinator 0:bb348c97df44 1959 #define EXTI_EMR_MR12_Pos (12U)
lypinator 0:bb348c97df44 1960 #define EXTI_EMR_MR12_Msk (0x1U << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 1961 #define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */
lypinator 0:bb348c97df44 1962 #define EXTI_EMR_MR13_Pos (13U)
lypinator 0:bb348c97df44 1963 #define EXTI_EMR_MR13_Msk (0x1U << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 1964 #define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */
lypinator 0:bb348c97df44 1965 #define EXTI_EMR_MR14_Pos (14U)
lypinator 0:bb348c97df44 1966 #define EXTI_EMR_MR14_Msk (0x1U << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 1967 #define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */
lypinator 0:bb348c97df44 1968 #define EXTI_EMR_MR15_Pos (15U)
lypinator 0:bb348c97df44 1969 #define EXTI_EMR_MR15_Msk (0x1U << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 1970 #define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */
lypinator 0:bb348c97df44 1971 #define EXTI_EMR_MR16_Pos (16U)
lypinator 0:bb348c97df44 1972 #define EXTI_EMR_MR16_Msk (0x1U << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 1973 #define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */
lypinator 0:bb348c97df44 1974 #define EXTI_EMR_MR17_Pos (17U)
lypinator 0:bb348c97df44 1975 #define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 1976 #define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */
lypinator 0:bb348c97df44 1977 #define EXTI_EMR_MR18_Pos (18U)
lypinator 0:bb348c97df44 1978 #define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 1979 #define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */
lypinator 0:bb348c97df44 1980 #define EXTI_EMR_MR19_Pos (19U)
lypinator 0:bb348c97df44 1981 #define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 1982 #define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */
lypinator 0:bb348c97df44 1983 #define EXTI_EMR_MR20_Pos (20U)
lypinator 0:bb348c97df44 1984 #define EXTI_EMR_MR20_Msk (0x1U << EXTI_EMR_MR20_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 1985 #define EXTI_EMR_MR20 EXTI_EMR_MR20_Msk /*!< Event Mask on line 20 */
lypinator 0:bb348c97df44 1986 #define EXTI_EMR_MR21_Pos (21U)
lypinator 0:bb348c97df44 1987 #define EXTI_EMR_MR21_Msk (0x1U << EXTI_EMR_MR21_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 1988 #define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk /*!< Event Mask on line 21 */
lypinator 0:bb348c97df44 1989 #define EXTI_EMR_MR22_Pos (22U)
lypinator 0:bb348c97df44 1990 #define EXTI_EMR_MR22_Msk (0x1U << EXTI_EMR_MR22_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 1991 #define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk /*!< Event Mask on line 22 */
lypinator 0:bb348c97df44 1992
lypinator 0:bb348c97df44 1993 /* Reference Defines */
lypinator 0:bb348c97df44 1994 #define EXTI_EMR_EM0 EXTI_EMR_MR0
lypinator 0:bb348c97df44 1995 #define EXTI_EMR_EM1 EXTI_EMR_MR1
lypinator 0:bb348c97df44 1996 #define EXTI_EMR_EM2 EXTI_EMR_MR2
lypinator 0:bb348c97df44 1997 #define EXTI_EMR_EM3 EXTI_EMR_MR3
lypinator 0:bb348c97df44 1998 #define EXTI_EMR_EM4 EXTI_EMR_MR4
lypinator 0:bb348c97df44 1999 #define EXTI_EMR_EM5 EXTI_EMR_MR5
lypinator 0:bb348c97df44 2000 #define EXTI_EMR_EM6 EXTI_EMR_MR6
lypinator 0:bb348c97df44 2001 #define EXTI_EMR_EM7 EXTI_EMR_MR7
lypinator 0:bb348c97df44 2002 #define EXTI_EMR_EM8 EXTI_EMR_MR8
lypinator 0:bb348c97df44 2003 #define EXTI_EMR_EM9 EXTI_EMR_MR9
lypinator 0:bb348c97df44 2004 #define EXTI_EMR_EM10 EXTI_EMR_MR10
lypinator 0:bb348c97df44 2005 #define EXTI_EMR_EM11 EXTI_EMR_MR11
lypinator 0:bb348c97df44 2006 #define EXTI_EMR_EM12 EXTI_EMR_MR12
lypinator 0:bb348c97df44 2007 #define EXTI_EMR_EM13 EXTI_EMR_MR13
lypinator 0:bb348c97df44 2008 #define EXTI_EMR_EM14 EXTI_EMR_MR14
lypinator 0:bb348c97df44 2009 #define EXTI_EMR_EM15 EXTI_EMR_MR15
lypinator 0:bb348c97df44 2010 #define EXTI_EMR_EM16 EXTI_EMR_MR16
lypinator 0:bb348c97df44 2011 #define EXTI_EMR_EM17 EXTI_EMR_MR17
lypinator 0:bb348c97df44 2012 #define EXTI_EMR_EM18 EXTI_EMR_MR18
lypinator 0:bb348c97df44 2013 #define EXTI_EMR_EM19 EXTI_EMR_MR19
lypinator 0:bb348c97df44 2014 #define EXTI_EMR_EM20 EXTI_EMR_MR20
lypinator 0:bb348c97df44 2015 #define EXTI_EMR_EM21 EXTI_EMR_MR21
lypinator 0:bb348c97df44 2016 #define EXTI_EMR_EM22 EXTI_EMR_MR22
lypinator 0:bb348c97df44 2017
lypinator 0:bb348c97df44 2018 /****************** Bit definition for EXTI_RTSR register *******************/
lypinator 0:bb348c97df44 2019 #define EXTI_RTSR_TR0_Pos (0U)
lypinator 0:bb348c97df44 2020 #define EXTI_RTSR_TR0_Msk (0x1U << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 2021 #define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */
lypinator 0:bb348c97df44 2022 #define EXTI_RTSR_TR1_Pos (1U)
lypinator 0:bb348c97df44 2023 #define EXTI_RTSR_TR1_Msk (0x1U << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 2024 #define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */
lypinator 0:bb348c97df44 2025 #define EXTI_RTSR_TR2_Pos (2U)
lypinator 0:bb348c97df44 2026 #define EXTI_RTSR_TR2_Msk (0x1U << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 2027 #define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */
lypinator 0:bb348c97df44 2028 #define EXTI_RTSR_TR3_Pos (3U)
lypinator 0:bb348c97df44 2029 #define EXTI_RTSR_TR3_Msk (0x1U << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 2030 #define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */
lypinator 0:bb348c97df44 2031 #define EXTI_RTSR_TR4_Pos (4U)
lypinator 0:bb348c97df44 2032 #define EXTI_RTSR_TR4_Msk (0x1U << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 2033 #define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */
lypinator 0:bb348c97df44 2034 #define EXTI_RTSR_TR5_Pos (5U)
lypinator 0:bb348c97df44 2035 #define EXTI_RTSR_TR5_Msk (0x1U << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 2036 #define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */
lypinator 0:bb348c97df44 2037 #define EXTI_RTSR_TR6_Pos (6U)
lypinator 0:bb348c97df44 2038 #define EXTI_RTSR_TR6_Msk (0x1U << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 2039 #define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */
lypinator 0:bb348c97df44 2040 #define EXTI_RTSR_TR7_Pos (7U)
lypinator 0:bb348c97df44 2041 #define EXTI_RTSR_TR7_Msk (0x1U << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 2042 #define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */
lypinator 0:bb348c97df44 2043 #define EXTI_RTSR_TR8_Pos (8U)
lypinator 0:bb348c97df44 2044 #define EXTI_RTSR_TR8_Msk (0x1U << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 2045 #define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */
lypinator 0:bb348c97df44 2046 #define EXTI_RTSR_TR9_Pos (9U)
lypinator 0:bb348c97df44 2047 #define EXTI_RTSR_TR9_Msk (0x1U << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 2048 #define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */
lypinator 0:bb348c97df44 2049 #define EXTI_RTSR_TR10_Pos (10U)
lypinator 0:bb348c97df44 2050 #define EXTI_RTSR_TR10_Msk (0x1U << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 2051 #define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */
lypinator 0:bb348c97df44 2052 #define EXTI_RTSR_TR11_Pos (11U)
lypinator 0:bb348c97df44 2053 #define EXTI_RTSR_TR11_Msk (0x1U << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 2054 #define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */
lypinator 0:bb348c97df44 2055 #define EXTI_RTSR_TR12_Pos (12U)
lypinator 0:bb348c97df44 2056 #define EXTI_RTSR_TR12_Msk (0x1U << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 2057 #define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */
lypinator 0:bb348c97df44 2058 #define EXTI_RTSR_TR13_Pos (13U)
lypinator 0:bb348c97df44 2059 #define EXTI_RTSR_TR13_Msk (0x1U << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 2060 #define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */
lypinator 0:bb348c97df44 2061 #define EXTI_RTSR_TR14_Pos (14U)
lypinator 0:bb348c97df44 2062 #define EXTI_RTSR_TR14_Msk (0x1U << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 2063 #define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */
lypinator 0:bb348c97df44 2064 #define EXTI_RTSR_TR15_Pos (15U)
lypinator 0:bb348c97df44 2065 #define EXTI_RTSR_TR15_Msk (0x1U << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 2066 #define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */
lypinator 0:bb348c97df44 2067 #define EXTI_RTSR_TR16_Pos (16U)
lypinator 0:bb348c97df44 2068 #define EXTI_RTSR_TR16_Msk (0x1U << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 2069 #define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */
lypinator 0:bb348c97df44 2070 #define EXTI_RTSR_TR17_Pos (17U)
lypinator 0:bb348c97df44 2071 #define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 2072 #define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */
lypinator 0:bb348c97df44 2073 #define EXTI_RTSR_TR18_Pos (18U)
lypinator 0:bb348c97df44 2074 #define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 2075 #define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */
lypinator 0:bb348c97df44 2076 #define EXTI_RTSR_TR19_Pos (19U)
lypinator 0:bb348c97df44 2077 #define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 2078 #define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */
lypinator 0:bb348c97df44 2079 #define EXTI_RTSR_TR20_Pos (20U)
lypinator 0:bb348c97df44 2080 #define EXTI_RTSR_TR20_Msk (0x1U << EXTI_RTSR_TR20_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 2081 #define EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk /*!< Rising trigger event configuration bit of line 20 */
lypinator 0:bb348c97df44 2082 #define EXTI_RTSR_TR21_Pos (21U)
lypinator 0:bb348c97df44 2083 #define EXTI_RTSR_TR21_Msk (0x1U << EXTI_RTSR_TR21_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 2084 #define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk /*!< Rising trigger event configuration bit of line 21 */
lypinator 0:bb348c97df44 2085 #define EXTI_RTSR_TR22_Pos (22U)
lypinator 0:bb348c97df44 2086 #define EXTI_RTSR_TR22_Msk (0x1U << EXTI_RTSR_TR22_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 2087 #define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk /*!< Rising trigger event configuration bit of line 22 */
lypinator 0:bb348c97df44 2088
lypinator 0:bb348c97df44 2089 /****************** Bit definition for EXTI_FTSR register *******************/
lypinator 0:bb348c97df44 2090 #define EXTI_FTSR_TR0_Pos (0U)
lypinator 0:bb348c97df44 2091 #define EXTI_FTSR_TR0_Msk (0x1U << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 2092 #define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */
lypinator 0:bb348c97df44 2093 #define EXTI_FTSR_TR1_Pos (1U)
lypinator 0:bb348c97df44 2094 #define EXTI_FTSR_TR1_Msk (0x1U << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 2095 #define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */
lypinator 0:bb348c97df44 2096 #define EXTI_FTSR_TR2_Pos (2U)
lypinator 0:bb348c97df44 2097 #define EXTI_FTSR_TR2_Msk (0x1U << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 2098 #define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */
lypinator 0:bb348c97df44 2099 #define EXTI_FTSR_TR3_Pos (3U)
lypinator 0:bb348c97df44 2100 #define EXTI_FTSR_TR3_Msk (0x1U << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 2101 #define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */
lypinator 0:bb348c97df44 2102 #define EXTI_FTSR_TR4_Pos (4U)
lypinator 0:bb348c97df44 2103 #define EXTI_FTSR_TR4_Msk (0x1U << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 2104 #define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */
lypinator 0:bb348c97df44 2105 #define EXTI_FTSR_TR5_Pos (5U)
lypinator 0:bb348c97df44 2106 #define EXTI_FTSR_TR5_Msk (0x1U << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 2107 #define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */
lypinator 0:bb348c97df44 2108 #define EXTI_FTSR_TR6_Pos (6U)
lypinator 0:bb348c97df44 2109 #define EXTI_FTSR_TR6_Msk (0x1U << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 2110 #define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */
lypinator 0:bb348c97df44 2111 #define EXTI_FTSR_TR7_Pos (7U)
lypinator 0:bb348c97df44 2112 #define EXTI_FTSR_TR7_Msk (0x1U << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 2113 #define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */
lypinator 0:bb348c97df44 2114 #define EXTI_FTSR_TR8_Pos (8U)
lypinator 0:bb348c97df44 2115 #define EXTI_FTSR_TR8_Msk (0x1U << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 2116 #define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */
lypinator 0:bb348c97df44 2117 #define EXTI_FTSR_TR9_Pos (9U)
lypinator 0:bb348c97df44 2118 #define EXTI_FTSR_TR9_Msk (0x1U << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 2119 #define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */
lypinator 0:bb348c97df44 2120 #define EXTI_FTSR_TR10_Pos (10U)
lypinator 0:bb348c97df44 2121 #define EXTI_FTSR_TR10_Msk (0x1U << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 2122 #define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */
lypinator 0:bb348c97df44 2123 #define EXTI_FTSR_TR11_Pos (11U)
lypinator 0:bb348c97df44 2124 #define EXTI_FTSR_TR11_Msk (0x1U << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 2125 #define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */
lypinator 0:bb348c97df44 2126 #define EXTI_FTSR_TR12_Pos (12U)
lypinator 0:bb348c97df44 2127 #define EXTI_FTSR_TR12_Msk (0x1U << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 2128 #define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */
lypinator 0:bb348c97df44 2129 #define EXTI_FTSR_TR13_Pos (13U)
lypinator 0:bb348c97df44 2130 #define EXTI_FTSR_TR13_Msk (0x1U << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 2131 #define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */
lypinator 0:bb348c97df44 2132 #define EXTI_FTSR_TR14_Pos (14U)
lypinator 0:bb348c97df44 2133 #define EXTI_FTSR_TR14_Msk (0x1U << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 2134 #define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */
lypinator 0:bb348c97df44 2135 #define EXTI_FTSR_TR15_Pos (15U)
lypinator 0:bb348c97df44 2136 #define EXTI_FTSR_TR15_Msk (0x1U << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 2137 #define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */
lypinator 0:bb348c97df44 2138 #define EXTI_FTSR_TR16_Pos (16U)
lypinator 0:bb348c97df44 2139 #define EXTI_FTSR_TR16_Msk (0x1U << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 2140 #define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */
lypinator 0:bb348c97df44 2141 #define EXTI_FTSR_TR17_Pos (17U)
lypinator 0:bb348c97df44 2142 #define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 2143 #define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */
lypinator 0:bb348c97df44 2144 #define EXTI_FTSR_TR18_Pos (18U)
lypinator 0:bb348c97df44 2145 #define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 2146 #define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */
lypinator 0:bb348c97df44 2147 #define EXTI_FTSR_TR19_Pos (19U)
lypinator 0:bb348c97df44 2148 #define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 2149 #define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */
lypinator 0:bb348c97df44 2150 #define EXTI_FTSR_TR20_Pos (20U)
lypinator 0:bb348c97df44 2151 #define EXTI_FTSR_TR20_Msk (0x1U << EXTI_FTSR_TR20_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 2152 #define EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk /*!< Falling trigger event configuration bit of line 20 */
lypinator 0:bb348c97df44 2153 #define EXTI_FTSR_TR21_Pos (21U)
lypinator 0:bb348c97df44 2154 #define EXTI_FTSR_TR21_Msk (0x1U << EXTI_FTSR_TR21_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 2155 #define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk /*!< Falling trigger event configuration bit of line 21 */
lypinator 0:bb348c97df44 2156 #define EXTI_FTSR_TR22_Pos (22U)
lypinator 0:bb348c97df44 2157 #define EXTI_FTSR_TR22_Msk (0x1U << EXTI_FTSR_TR22_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 2158 #define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk /*!< Falling trigger event configuration bit of line 22 */
lypinator 0:bb348c97df44 2159
lypinator 0:bb348c97df44 2160 /****************** Bit definition for EXTI_SWIER register ******************/
lypinator 0:bb348c97df44 2161 #define EXTI_SWIER_SWIER0_Pos (0U)
lypinator 0:bb348c97df44 2162 #define EXTI_SWIER_SWIER0_Msk (0x1U << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 2163 #define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */
lypinator 0:bb348c97df44 2164 #define EXTI_SWIER_SWIER1_Pos (1U)
lypinator 0:bb348c97df44 2165 #define EXTI_SWIER_SWIER1_Msk (0x1U << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 2166 #define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */
lypinator 0:bb348c97df44 2167 #define EXTI_SWIER_SWIER2_Pos (2U)
lypinator 0:bb348c97df44 2168 #define EXTI_SWIER_SWIER2_Msk (0x1U << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 2169 #define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */
lypinator 0:bb348c97df44 2170 #define EXTI_SWIER_SWIER3_Pos (3U)
lypinator 0:bb348c97df44 2171 #define EXTI_SWIER_SWIER3_Msk (0x1U << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 2172 #define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */
lypinator 0:bb348c97df44 2173 #define EXTI_SWIER_SWIER4_Pos (4U)
lypinator 0:bb348c97df44 2174 #define EXTI_SWIER_SWIER4_Msk (0x1U << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 2175 #define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */
lypinator 0:bb348c97df44 2176 #define EXTI_SWIER_SWIER5_Pos (5U)
lypinator 0:bb348c97df44 2177 #define EXTI_SWIER_SWIER5_Msk (0x1U << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 2178 #define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */
lypinator 0:bb348c97df44 2179 #define EXTI_SWIER_SWIER6_Pos (6U)
lypinator 0:bb348c97df44 2180 #define EXTI_SWIER_SWIER6_Msk (0x1U << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 2181 #define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */
lypinator 0:bb348c97df44 2182 #define EXTI_SWIER_SWIER7_Pos (7U)
lypinator 0:bb348c97df44 2183 #define EXTI_SWIER_SWIER7_Msk (0x1U << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 2184 #define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */
lypinator 0:bb348c97df44 2185 #define EXTI_SWIER_SWIER8_Pos (8U)
lypinator 0:bb348c97df44 2186 #define EXTI_SWIER_SWIER8_Msk (0x1U << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 2187 #define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */
lypinator 0:bb348c97df44 2188 #define EXTI_SWIER_SWIER9_Pos (9U)
lypinator 0:bb348c97df44 2189 #define EXTI_SWIER_SWIER9_Msk (0x1U << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 2190 #define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */
lypinator 0:bb348c97df44 2191 #define EXTI_SWIER_SWIER10_Pos (10U)
lypinator 0:bb348c97df44 2192 #define EXTI_SWIER_SWIER10_Msk (0x1U << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 2193 #define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */
lypinator 0:bb348c97df44 2194 #define EXTI_SWIER_SWIER11_Pos (11U)
lypinator 0:bb348c97df44 2195 #define EXTI_SWIER_SWIER11_Msk (0x1U << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 2196 #define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */
lypinator 0:bb348c97df44 2197 #define EXTI_SWIER_SWIER12_Pos (12U)
lypinator 0:bb348c97df44 2198 #define EXTI_SWIER_SWIER12_Msk (0x1U << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 2199 #define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */
lypinator 0:bb348c97df44 2200 #define EXTI_SWIER_SWIER13_Pos (13U)
lypinator 0:bb348c97df44 2201 #define EXTI_SWIER_SWIER13_Msk (0x1U << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 2202 #define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */
lypinator 0:bb348c97df44 2203 #define EXTI_SWIER_SWIER14_Pos (14U)
lypinator 0:bb348c97df44 2204 #define EXTI_SWIER_SWIER14_Msk (0x1U << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 2205 #define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */
lypinator 0:bb348c97df44 2206 #define EXTI_SWIER_SWIER15_Pos (15U)
lypinator 0:bb348c97df44 2207 #define EXTI_SWIER_SWIER15_Msk (0x1U << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 2208 #define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */
lypinator 0:bb348c97df44 2209 #define EXTI_SWIER_SWIER16_Pos (16U)
lypinator 0:bb348c97df44 2210 #define EXTI_SWIER_SWIER16_Msk (0x1U << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 2211 #define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */
lypinator 0:bb348c97df44 2212 #define EXTI_SWIER_SWIER17_Pos (17U)
lypinator 0:bb348c97df44 2213 #define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 2214 #define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */
lypinator 0:bb348c97df44 2215 #define EXTI_SWIER_SWIER18_Pos (18U)
lypinator 0:bb348c97df44 2216 #define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 2217 #define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */
lypinator 0:bb348c97df44 2218 #define EXTI_SWIER_SWIER19_Pos (19U)
lypinator 0:bb348c97df44 2219 #define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 2220 #define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */
lypinator 0:bb348c97df44 2221 #define EXTI_SWIER_SWIER20_Pos (20U)
lypinator 0:bb348c97df44 2222 #define EXTI_SWIER_SWIER20_Msk (0x1U << EXTI_SWIER_SWIER20_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 2223 #define EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk /*!< Software Interrupt on line 20 */
lypinator 0:bb348c97df44 2224 #define EXTI_SWIER_SWIER21_Pos (21U)
lypinator 0:bb348c97df44 2225 #define EXTI_SWIER_SWIER21_Msk (0x1U << EXTI_SWIER_SWIER21_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 2226 #define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk /*!< Software Interrupt on line 21 */
lypinator 0:bb348c97df44 2227 #define EXTI_SWIER_SWIER22_Pos (22U)
lypinator 0:bb348c97df44 2228 #define EXTI_SWIER_SWIER22_Msk (0x1U << EXTI_SWIER_SWIER22_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 2229 #define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk /*!< Software Interrupt on line 22 */
lypinator 0:bb348c97df44 2230
lypinator 0:bb348c97df44 2231 /******************* Bit definition for EXTI_PR register ********************/
lypinator 0:bb348c97df44 2232 #define EXTI_PR_PR0_Pos (0U)
lypinator 0:bb348c97df44 2233 #define EXTI_PR_PR0_Msk (0x1U << EXTI_PR_PR0_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 2234 #define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */
lypinator 0:bb348c97df44 2235 #define EXTI_PR_PR1_Pos (1U)
lypinator 0:bb348c97df44 2236 #define EXTI_PR_PR1_Msk (0x1U << EXTI_PR_PR1_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 2237 #define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */
lypinator 0:bb348c97df44 2238 #define EXTI_PR_PR2_Pos (2U)
lypinator 0:bb348c97df44 2239 #define EXTI_PR_PR2_Msk (0x1U << EXTI_PR_PR2_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 2240 #define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */
lypinator 0:bb348c97df44 2241 #define EXTI_PR_PR3_Pos (3U)
lypinator 0:bb348c97df44 2242 #define EXTI_PR_PR3_Msk (0x1U << EXTI_PR_PR3_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 2243 #define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */
lypinator 0:bb348c97df44 2244 #define EXTI_PR_PR4_Pos (4U)
lypinator 0:bb348c97df44 2245 #define EXTI_PR_PR4_Msk (0x1U << EXTI_PR_PR4_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 2246 #define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */
lypinator 0:bb348c97df44 2247 #define EXTI_PR_PR5_Pos (5U)
lypinator 0:bb348c97df44 2248 #define EXTI_PR_PR5_Msk (0x1U << EXTI_PR_PR5_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 2249 #define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */
lypinator 0:bb348c97df44 2250 #define EXTI_PR_PR6_Pos (6U)
lypinator 0:bb348c97df44 2251 #define EXTI_PR_PR6_Msk (0x1U << EXTI_PR_PR6_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 2252 #define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */
lypinator 0:bb348c97df44 2253 #define EXTI_PR_PR7_Pos (7U)
lypinator 0:bb348c97df44 2254 #define EXTI_PR_PR7_Msk (0x1U << EXTI_PR_PR7_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 2255 #define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */
lypinator 0:bb348c97df44 2256 #define EXTI_PR_PR8_Pos (8U)
lypinator 0:bb348c97df44 2257 #define EXTI_PR_PR8_Msk (0x1U << EXTI_PR_PR8_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 2258 #define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */
lypinator 0:bb348c97df44 2259 #define EXTI_PR_PR9_Pos (9U)
lypinator 0:bb348c97df44 2260 #define EXTI_PR_PR9_Msk (0x1U << EXTI_PR_PR9_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 2261 #define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */
lypinator 0:bb348c97df44 2262 #define EXTI_PR_PR10_Pos (10U)
lypinator 0:bb348c97df44 2263 #define EXTI_PR_PR10_Msk (0x1U << EXTI_PR_PR10_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 2264 #define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */
lypinator 0:bb348c97df44 2265 #define EXTI_PR_PR11_Pos (11U)
lypinator 0:bb348c97df44 2266 #define EXTI_PR_PR11_Msk (0x1U << EXTI_PR_PR11_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 2267 #define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */
lypinator 0:bb348c97df44 2268 #define EXTI_PR_PR12_Pos (12U)
lypinator 0:bb348c97df44 2269 #define EXTI_PR_PR12_Msk (0x1U << EXTI_PR_PR12_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 2270 #define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */
lypinator 0:bb348c97df44 2271 #define EXTI_PR_PR13_Pos (13U)
lypinator 0:bb348c97df44 2272 #define EXTI_PR_PR13_Msk (0x1U << EXTI_PR_PR13_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 2273 #define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */
lypinator 0:bb348c97df44 2274 #define EXTI_PR_PR14_Pos (14U)
lypinator 0:bb348c97df44 2275 #define EXTI_PR_PR14_Msk (0x1U << EXTI_PR_PR14_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 2276 #define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */
lypinator 0:bb348c97df44 2277 #define EXTI_PR_PR15_Pos (15U)
lypinator 0:bb348c97df44 2278 #define EXTI_PR_PR15_Msk (0x1U << EXTI_PR_PR15_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 2279 #define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */
lypinator 0:bb348c97df44 2280 #define EXTI_PR_PR16_Pos (16U)
lypinator 0:bb348c97df44 2281 #define EXTI_PR_PR16_Msk (0x1U << EXTI_PR_PR16_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 2282 #define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */
lypinator 0:bb348c97df44 2283 #define EXTI_PR_PR17_Pos (17U)
lypinator 0:bb348c97df44 2284 #define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 2285 #define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */
lypinator 0:bb348c97df44 2286 #define EXTI_PR_PR18_Pos (18U)
lypinator 0:bb348c97df44 2287 #define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 2288 #define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */
lypinator 0:bb348c97df44 2289 #define EXTI_PR_PR19_Pos (19U)
lypinator 0:bb348c97df44 2290 #define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 2291 #define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */
lypinator 0:bb348c97df44 2292 #define EXTI_PR_PR20_Pos (20U)
lypinator 0:bb348c97df44 2293 #define EXTI_PR_PR20_Msk (0x1U << EXTI_PR_PR20_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 2294 #define EXTI_PR_PR20 EXTI_PR_PR20_Msk /*!< Pending bit for line 20 */
lypinator 0:bb348c97df44 2295 #define EXTI_PR_PR21_Pos (21U)
lypinator 0:bb348c97df44 2296 #define EXTI_PR_PR21_Msk (0x1U << EXTI_PR_PR21_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 2297 #define EXTI_PR_PR21 EXTI_PR_PR21_Msk /*!< Pending bit for line 21 */
lypinator 0:bb348c97df44 2298 #define EXTI_PR_PR22_Pos (22U)
lypinator 0:bb348c97df44 2299 #define EXTI_PR_PR22_Msk (0x1U << EXTI_PR_PR22_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 2300 #define EXTI_PR_PR22 EXTI_PR_PR22_Msk /*!< Pending bit for line 22 */
lypinator 0:bb348c97df44 2301
lypinator 0:bb348c97df44 2302 /******************************************************************************/
lypinator 0:bb348c97df44 2303 /* */
lypinator 0:bb348c97df44 2304 /* FLASH */
lypinator 0:bb348c97df44 2305 /* */
lypinator 0:bb348c97df44 2306 /******************************************************************************/
lypinator 0:bb348c97df44 2307 /******************* Bits definition for FLASH_ACR register *****************/
lypinator 0:bb348c97df44 2308 #define FLASH_ACR_LATENCY_Pos (0U)
lypinator 0:bb348c97df44 2309 #define FLASH_ACR_LATENCY_Msk (0xFU << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
lypinator 0:bb348c97df44 2310 #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
lypinator 0:bb348c97df44 2311 #define FLASH_ACR_LATENCY_0WS 0x00000000U
lypinator 0:bb348c97df44 2312 #define FLASH_ACR_LATENCY_1WS 0x00000001U
lypinator 0:bb348c97df44 2313 #define FLASH_ACR_LATENCY_2WS 0x00000002U
lypinator 0:bb348c97df44 2314 #define FLASH_ACR_LATENCY_3WS 0x00000003U
lypinator 0:bb348c97df44 2315 #define FLASH_ACR_LATENCY_4WS 0x00000004U
lypinator 0:bb348c97df44 2316 #define FLASH_ACR_LATENCY_5WS 0x00000005U
lypinator 0:bb348c97df44 2317 #define FLASH_ACR_LATENCY_6WS 0x00000006U
lypinator 0:bb348c97df44 2318 #define FLASH_ACR_LATENCY_7WS 0x00000007U
lypinator 0:bb348c97df44 2319
lypinator 0:bb348c97df44 2320 #define FLASH_ACR_PRFTEN_Pos (8U)
lypinator 0:bb348c97df44 2321 #define FLASH_ACR_PRFTEN_Msk (0x1U << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 2322 #define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk
lypinator 0:bb348c97df44 2323 #define FLASH_ACR_ICEN_Pos (9U)
lypinator 0:bb348c97df44 2324 #define FLASH_ACR_ICEN_Msk (0x1U << FLASH_ACR_ICEN_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 2325 #define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk
lypinator 0:bb348c97df44 2326 #define FLASH_ACR_DCEN_Pos (10U)
lypinator 0:bb348c97df44 2327 #define FLASH_ACR_DCEN_Msk (0x1U << FLASH_ACR_DCEN_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 2328 #define FLASH_ACR_DCEN FLASH_ACR_DCEN_Msk
lypinator 0:bb348c97df44 2329 #define FLASH_ACR_ICRST_Pos (11U)
lypinator 0:bb348c97df44 2330 #define FLASH_ACR_ICRST_Msk (0x1U << FLASH_ACR_ICRST_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 2331 #define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk
lypinator 0:bb348c97df44 2332 #define FLASH_ACR_DCRST_Pos (12U)
lypinator 0:bb348c97df44 2333 #define FLASH_ACR_DCRST_Msk (0x1U << FLASH_ACR_DCRST_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 2334 #define FLASH_ACR_DCRST FLASH_ACR_DCRST_Msk
lypinator 0:bb348c97df44 2335 #define FLASH_ACR_BYTE0_ADDRESS_Pos (10U)
lypinator 0:bb348c97df44 2336 #define FLASH_ACR_BYTE0_ADDRESS_Msk (0x10008FU << FLASH_ACR_BYTE0_ADDRESS_Pos) /*!< 0x40023C00 */
lypinator 0:bb348c97df44 2337 #define FLASH_ACR_BYTE0_ADDRESS FLASH_ACR_BYTE0_ADDRESS_Msk
lypinator 0:bb348c97df44 2338 #define FLASH_ACR_BYTE2_ADDRESS_Pos (0U)
lypinator 0:bb348c97df44 2339 #define FLASH_ACR_BYTE2_ADDRESS_Msk (0x40023C03U << FLASH_ACR_BYTE2_ADDRESS_Pos) /*!< 0x40023C03 */
lypinator 0:bb348c97df44 2340 #define FLASH_ACR_BYTE2_ADDRESS FLASH_ACR_BYTE2_ADDRESS_Msk
lypinator 0:bb348c97df44 2341
lypinator 0:bb348c97df44 2342 /******************* Bits definition for FLASH_SR register ******************/
lypinator 0:bb348c97df44 2343 #define FLASH_SR_EOP_Pos (0U)
lypinator 0:bb348c97df44 2344 #define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 2345 #define FLASH_SR_EOP FLASH_SR_EOP_Msk
lypinator 0:bb348c97df44 2346 #define FLASH_SR_SOP_Pos (1U)
lypinator 0:bb348c97df44 2347 #define FLASH_SR_SOP_Msk (0x1U << FLASH_SR_SOP_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 2348 #define FLASH_SR_SOP FLASH_SR_SOP_Msk
lypinator 0:bb348c97df44 2349 #define FLASH_SR_WRPERR_Pos (4U)
lypinator 0:bb348c97df44 2350 #define FLASH_SR_WRPERR_Msk (0x1U << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 2351 #define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
lypinator 0:bb348c97df44 2352 #define FLASH_SR_PGAERR_Pos (5U)
lypinator 0:bb348c97df44 2353 #define FLASH_SR_PGAERR_Msk (0x1U << FLASH_SR_PGAERR_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 2354 #define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk
lypinator 0:bb348c97df44 2355 #define FLASH_SR_PGPERR_Pos (6U)
lypinator 0:bb348c97df44 2356 #define FLASH_SR_PGPERR_Msk (0x1U << FLASH_SR_PGPERR_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 2357 #define FLASH_SR_PGPERR FLASH_SR_PGPERR_Msk
lypinator 0:bb348c97df44 2358 #define FLASH_SR_PGSERR_Pos (7U)
lypinator 0:bb348c97df44 2359 #define FLASH_SR_PGSERR_Msk (0x1U << FLASH_SR_PGSERR_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 2360 #define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk
lypinator 0:bb348c97df44 2361 #define FLASH_SR_RDERR_Pos (8U)
lypinator 0:bb348c97df44 2362 #define FLASH_SR_RDERR_Msk (0x1U << FLASH_SR_RDERR_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 2363 #define FLASH_SR_RDERR FLASH_SR_RDERR_Msk
lypinator 0:bb348c97df44 2364 #define FLASH_SR_BSY_Pos (16U)
lypinator 0:bb348c97df44 2365 #define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 2366 #define FLASH_SR_BSY FLASH_SR_BSY_Msk
lypinator 0:bb348c97df44 2367
lypinator 0:bb348c97df44 2368 /******************* Bits definition for FLASH_CR register ******************/
lypinator 0:bb348c97df44 2369 #define FLASH_CR_PG_Pos (0U)
lypinator 0:bb348c97df44 2370 #define FLASH_CR_PG_Msk (0x1U << FLASH_CR_PG_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 2371 #define FLASH_CR_PG FLASH_CR_PG_Msk
lypinator 0:bb348c97df44 2372 #define FLASH_CR_SER_Pos (1U)
lypinator 0:bb348c97df44 2373 #define FLASH_CR_SER_Msk (0x1U << FLASH_CR_SER_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 2374 #define FLASH_CR_SER FLASH_CR_SER_Msk
lypinator 0:bb348c97df44 2375 #define FLASH_CR_MER_Pos (2U)
lypinator 0:bb348c97df44 2376 #define FLASH_CR_MER_Msk (0x1U << FLASH_CR_MER_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 2377 #define FLASH_CR_MER FLASH_CR_MER_Msk
lypinator 0:bb348c97df44 2378 #define FLASH_CR_SNB_Pos (3U)
lypinator 0:bb348c97df44 2379 #define FLASH_CR_SNB_Msk (0x1FU << FLASH_CR_SNB_Pos) /*!< 0x000000F8 */
lypinator 0:bb348c97df44 2380 #define FLASH_CR_SNB FLASH_CR_SNB_Msk
lypinator 0:bb348c97df44 2381 #define FLASH_CR_SNB_0 (0x01U << FLASH_CR_SNB_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 2382 #define FLASH_CR_SNB_1 (0x02U << FLASH_CR_SNB_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 2383 #define FLASH_CR_SNB_2 (0x04U << FLASH_CR_SNB_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 2384 #define FLASH_CR_SNB_3 (0x08U << FLASH_CR_SNB_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 2385 #define FLASH_CR_SNB_4 (0x10U << FLASH_CR_SNB_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 2386 #define FLASH_CR_PSIZE_Pos (8U)
lypinator 0:bb348c97df44 2387 #define FLASH_CR_PSIZE_Msk (0x3U << FLASH_CR_PSIZE_Pos) /*!< 0x00000300 */
lypinator 0:bb348c97df44 2388 #define FLASH_CR_PSIZE FLASH_CR_PSIZE_Msk
lypinator 0:bb348c97df44 2389 #define FLASH_CR_PSIZE_0 (0x1U << FLASH_CR_PSIZE_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 2390 #define FLASH_CR_PSIZE_1 (0x2U << FLASH_CR_PSIZE_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 2391 #define FLASH_CR_STRT_Pos (16U)
lypinator 0:bb348c97df44 2392 #define FLASH_CR_STRT_Msk (0x1U << FLASH_CR_STRT_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 2393 #define FLASH_CR_STRT FLASH_CR_STRT_Msk
lypinator 0:bb348c97df44 2394 #define FLASH_CR_EOPIE_Pos (24U)
lypinator 0:bb348c97df44 2395 #define FLASH_CR_EOPIE_Msk (0x1U << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 2396 #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
lypinator 0:bb348c97df44 2397 #define FLASH_CR_LOCK_Pos (31U)
lypinator 0:bb348c97df44 2398 #define FLASH_CR_LOCK_Msk (0x1U << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */
lypinator 0:bb348c97df44 2399 #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
lypinator 0:bb348c97df44 2400
lypinator 0:bb348c97df44 2401 /******************* Bits definition for FLASH_OPTCR register ***************/
lypinator 0:bb348c97df44 2402 #define FLASH_OPTCR_OPTLOCK_Pos (0U)
lypinator 0:bb348c97df44 2403 #define FLASH_OPTCR_OPTLOCK_Msk (0x1U << FLASH_OPTCR_OPTLOCK_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 2404 #define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk
lypinator 0:bb348c97df44 2405 #define FLASH_OPTCR_OPTSTRT_Pos (1U)
lypinator 0:bb348c97df44 2406 #define FLASH_OPTCR_OPTSTRT_Msk (0x1U << FLASH_OPTCR_OPTSTRT_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 2407 #define FLASH_OPTCR_OPTSTRT FLASH_OPTCR_OPTSTRT_Msk
lypinator 0:bb348c97df44 2408
lypinator 0:bb348c97df44 2409 #define FLASH_OPTCR_BOR_LEV_0 0x00000004U
lypinator 0:bb348c97df44 2410 #define FLASH_OPTCR_BOR_LEV_1 0x00000008U
lypinator 0:bb348c97df44 2411 #define FLASH_OPTCR_BOR_LEV_Pos (2U)
lypinator 0:bb348c97df44 2412 #define FLASH_OPTCR_BOR_LEV_Msk (0x3U << FLASH_OPTCR_BOR_LEV_Pos) /*!< 0x0000000C */
lypinator 0:bb348c97df44 2413 #define FLASH_OPTCR_BOR_LEV FLASH_OPTCR_BOR_LEV_Msk
lypinator 0:bb348c97df44 2414 #define FLASH_OPTCR_WDG_SW_Pos (5U)
lypinator 0:bb348c97df44 2415 #define FLASH_OPTCR_WDG_SW_Msk (0x1U << FLASH_OPTCR_WDG_SW_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 2416 #define FLASH_OPTCR_WDG_SW FLASH_OPTCR_WDG_SW_Msk
lypinator 0:bb348c97df44 2417 #define FLASH_OPTCR_nRST_STOP_Pos (6U)
lypinator 0:bb348c97df44 2418 #define FLASH_OPTCR_nRST_STOP_Msk (0x1U << FLASH_OPTCR_nRST_STOP_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 2419 #define FLASH_OPTCR_nRST_STOP FLASH_OPTCR_nRST_STOP_Msk
lypinator 0:bb348c97df44 2420 #define FLASH_OPTCR_nRST_STDBY_Pos (7U)
lypinator 0:bb348c97df44 2421 #define FLASH_OPTCR_nRST_STDBY_Msk (0x1U << FLASH_OPTCR_nRST_STDBY_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 2422 #define FLASH_OPTCR_nRST_STDBY FLASH_OPTCR_nRST_STDBY_Msk
lypinator 0:bb348c97df44 2423 #define FLASH_OPTCR_RDP_Pos (8U)
lypinator 0:bb348c97df44 2424 #define FLASH_OPTCR_RDP_Msk (0xFFU << FLASH_OPTCR_RDP_Pos) /*!< 0x0000FF00 */
lypinator 0:bb348c97df44 2425 #define FLASH_OPTCR_RDP FLASH_OPTCR_RDP_Msk
lypinator 0:bb348c97df44 2426 #define FLASH_OPTCR_RDP_0 (0x01U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 2427 #define FLASH_OPTCR_RDP_1 (0x02U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 2428 #define FLASH_OPTCR_RDP_2 (0x04U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 2429 #define FLASH_OPTCR_RDP_3 (0x08U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 2430 #define FLASH_OPTCR_RDP_4 (0x10U << FLASH_OPTCR_RDP_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 2431 #define FLASH_OPTCR_RDP_5 (0x20U << FLASH_OPTCR_RDP_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 2432 #define FLASH_OPTCR_RDP_6 (0x40U << FLASH_OPTCR_RDP_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 2433 #define FLASH_OPTCR_RDP_7 (0x80U << FLASH_OPTCR_RDP_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 2434 #define FLASH_OPTCR_nWRP_Pos (16U)
lypinator 0:bb348c97df44 2435 #define FLASH_OPTCR_nWRP_Msk (0xFFFU << FLASH_OPTCR_nWRP_Pos) /*!< 0x0FFF0000 */
lypinator 0:bb348c97df44 2436 #define FLASH_OPTCR_nWRP FLASH_OPTCR_nWRP_Msk
lypinator 0:bb348c97df44 2437 #define FLASH_OPTCR_nWRP_0 0x00010000U
lypinator 0:bb348c97df44 2438 #define FLASH_OPTCR_nWRP_1 0x00020000U
lypinator 0:bb348c97df44 2439 #define FLASH_OPTCR_nWRP_2 0x00040000U
lypinator 0:bb348c97df44 2440 #define FLASH_OPTCR_nWRP_3 0x00080000U
lypinator 0:bb348c97df44 2441 #define FLASH_OPTCR_nWRP_4 0x00100000U
lypinator 0:bb348c97df44 2442 #define FLASH_OPTCR_nWRP_5 0x00200000U
lypinator 0:bb348c97df44 2443 #define FLASH_OPTCR_nWRP_6 0x00400000U
lypinator 0:bb348c97df44 2444 #define FLASH_OPTCR_nWRP_7 0x00800000U
lypinator 0:bb348c97df44 2445 #define FLASH_OPTCR_nWRP_8 0x01000000U
lypinator 0:bb348c97df44 2446 #define FLASH_OPTCR_nWRP_9 0x02000000U
lypinator 0:bb348c97df44 2447 #define FLASH_OPTCR_nWRP_10 0x04000000U
lypinator 0:bb348c97df44 2448 #define FLASH_OPTCR_nWRP_11 0x08000000U
lypinator 0:bb348c97df44 2449
lypinator 0:bb348c97df44 2450 /****************** Bits definition for FLASH_OPTCR1 register ***************/
lypinator 0:bb348c97df44 2451 #define FLASH_OPTCR1_nWRP_Pos (16U)
lypinator 0:bb348c97df44 2452 #define FLASH_OPTCR1_nWRP_Msk (0xFFFU << FLASH_OPTCR1_nWRP_Pos) /*!< 0x0FFF0000 */
lypinator 0:bb348c97df44 2453 #define FLASH_OPTCR1_nWRP FLASH_OPTCR1_nWRP_Msk
lypinator 0:bb348c97df44 2454 #define FLASH_OPTCR1_nWRP_0 (0x001U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 2455 #define FLASH_OPTCR1_nWRP_1 (0x002U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 2456 #define FLASH_OPTCR1_nWRP_2 (0x004U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 2457 #define FLASH_OPTCR1_nWRP_3 (0x008U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 2458 #define FLASH_OPTCR1_nWRP_4 (0x010U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 2459 #define FLASH_OPTCR1_nWRP_5 (0x020U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 2460 #define FLASH_OPTCR1_nWRP_6 (0x040U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 2461 #define FLASH_OPTCR1_nWRP_7 (0x080U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00800000 */
lypinator 0:bb348c97df44 2462 #define FLASH_OPTCR1_nWRP_8 (0x100U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 2463 #define FLASH_OPTCR1_nWRP_9 (0x200U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 2464 #define FLASH_OPTCR1_nWRP_10 (0x400U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x04000000 */
lypinator 0:bb348c97df44 2465 #define FLASH_OPTCR1_nWRP_11 (0x800U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x08000000 */
lypinator 0:bb348c97df44 2466
lypinator 0:bb348c97df44 2467 /******************************************************************************/
lypinator 0:bb348c97df44 2468 /* */
lypinator 0:bb348c97df44 2469 /* General Purpose I/O */
lypinator 0:bb348c97df44 2470 /* */
lypinator 0:bb348c97df44 2471 /******************************************************************************/
lypinator 0:bb348c97df44 2472 /****************** Bits definition for GPIO_MODER register *****************/
lypinator 0:bb348c97df44 2473 #define GPIO_MODER_MODE0_Pos (0U)
lypinator 0:bb348c97df44 2474 #define GPIO_MODER_MODE0_Msk (0x3U << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */
lypinator 0:bb348c97df44 2475 #define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
lypinator 0:bb348c97df44 2476 #define GPIO_MODER_MODE0_0 (0x1U << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 2477 #define GPIO_MODER_MODE0_1 (0x2U << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 2478 #define GPIO_MODER_MODE1_Pos (2U)
lypinator 0:bb348c97df44 2479 #define GPIO_MODER_MODE1_Msk (0x3U << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */
lypinator 0:bb348c97df44 2480 #define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
lypinator 0:bb348c97df44 2481 #define GPIO_MODER_MODE1_0 (0x1U << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 2482 #define GPIO_MODER_MODE1_1 (0x2U << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 2483 #define GPIO_MODER_MODE2_Pos (4U)
lypinator 0:bb348c97df44 2484 #define GPIO_MODER_MODE2_Msk (0x3U << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */
lypinator 0:bb348c97df44 2485 #define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
lypinator 0:bb348c97df44 2486 #define GPIO_MODER_MODE2_0 (0x1U << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 2487 #define GPIO_MODER_MODE2_1 (0x2U << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 2488 #define GPIO_MODER_MODE3_Pos (6U)
lypinator 0:bb348c97df44 2489 #define GPIO_MODER_MODE3_Msk (0x3U << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */
lypinator 0:bb348c97df44 2490 #define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
lypinator 0:bb348c97df44 2491 #define GPIO_MODER_MODE3_0 (0x1U << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 2492 #define GPIO_MODER_MODE3_1 (0x2U << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 2493 #define GPIO_MODER_MODE4_Pos (8U)
lypinator 0:bb348c97df44 2494 #define GPIO_MODER_MODE4_Msk (0x3U << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */
lypinator 0:bb348c97df44 2495 #define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
lypinator 0:bb348c97df44 2496 #define GPIO_MODER_MODE4_0 (0x1U << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 2497 #define GPIO_MODER_MODE4_1 (0x2U << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 2498 #define GPIO_MODER_MODE5_Pos (10U)
lypinator 0:bb348c97df44 2499 #define GPIO_MODER_MODE5_Msk (0x3U << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */
lypinator 0:bb348c97df44 2500 #define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
lypinator 0:bb348c97df44 2501 #define GPIO_MODER_MODE5_0 (0x1U << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 2502 #define GPIO_MODER_MODE5_1 (0x2U << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 2503 #define GPIO_MODER_MODE6_Pos (12U)
lypinator 0:bb348c97df44 2504 #define GPIO_MODER_MODE6_Msk (0x3U << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */
lypinator 0:bb348c97df44 2505 #define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
lypinator 0:bb348c97df44 2506 #define GPIO_MODER_MODE6_0 (0x1U << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 2507 #define GPIO_MODER_MODE6_1 (0x2U << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 2508 #define GPIO_MODER_MODE7_Pos (14U)
lypinator 0:bb348c97df44 2509 #define GPIO_MODER_MODE7_Msk (0x3U << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */
lypinator 0:bb348c97df44 2510 #define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
lypinator 0:bb348c97df44 2511 #define GPIO_MODER_MODE7_0 (0x1U << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 2512 #define GPIO_MODER_MODE7_1 (0x2U << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 2513 #define GPIO_MODER_MODE8_Pos (16U)
lypinator 0:bb348c97df44 2514 #define GPIO_MODER_MODE8_Msk (0x3U << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */
lypinator 0:bb348c97df44 2515 #define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
lypinator 0:bb348c97df44 2516 #define GPIO_MODER_MODE8_0 (0x1U << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 2517 #define GPIO_MODER_MODE8_1 (0x2U << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 2518 #define GPIO_MODER_MODE9_Pos (18U)
lypinator 0:bb348c97df44 2519 #define GPIO_MODER_MODE9_Msk (0x3U << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */
lypinator 0:bb348c97df44 2520 #define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
lypinator 0:bb348c97df44 2521 #define GPIO_MODER_MODE9_0 (0x1U << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 2522 #define GPIO_MODER_MODE9_1 (0x2U << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 2523 #define GPIO_MODER_MODE10_Pos (20U)
lypinator 0:bb348c97df44 2524 #define GPIO_MODER_MODE10_Msk (0x3U << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */
lypinator 0:bb348c97df44 2525 #define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
lypinator 0:bb348c97df44 2526 #define GPIO_MODER_MODE10_0 (0x1U << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 2527 #define GPIO_MODER_MODE10_1 (0x2U << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 2528 #define GPIO_MODER_MODE11_Pos (22U)
lypinator 0:bb348c97df44 2529 #define GPIO_MODER_MODE11_Msk (0x3U << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */
lypinator 0:bb348c97df44 2530 #define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
lypinator 0:bb348c97df44 2531 #define GPIO_MODER_MODE11_0 (0x1U << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 2532 #define GPIO_MODER_MODE11_1 (0x2U << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */
lypinator 0:bb348c97df44 2533 #define GPIO_MODER_MODE12_Pos (24U)
lypinator 0:bb348c97df44 2534 #define GPIO_MODER_MODE12_Msk (0x3U << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */
lypinator 0:bb348c97df44 2535 #define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
lypinator 0:bb348c97df44 2536 #define GPIO_MODER_MODE12_0 (0x1U << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 2537 #define GPIO_MODER_MODE12_1 (0x2U << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 2538 #define GPIO_MODER_MODE13_Pos (26U)
lypinator 0:bb348c97df44 2539 #define GPIO_MODER_MODE13_Msk (0x3U << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */
lypinator 0:bb348c97df44 2540 #define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
lypinator 0:bb348c97df44 2541 #define GPIO_MODER_MODE13_0 (0x1U << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */
lypinator 0:bb348c97df44 2542 #define GPIO_MODER_MODE13_1 (0x2U << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */
lypinator 0:bb348c97df44 2543 #define GPIO_MODER_MODE14_Pos (28U)
lypinator 0:bb348c97df44 2544 #define GPIO_MODER_MODE14_Msk (0x3U << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */
lypinator 0:bb348c97df44 2545 #define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
lypinator 0:bb348c97df44 2546 #define GPIO_MODER_MODE14_0 (0x1U << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */
lypinator 0:bb348c97df44 2547 #define GPIO_MODER_MODE14_1 (0x2U << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */
lypinator 0:bb348c97df44 2548 #define GPIO_MODER_MODE15_Pos (30U)
lypinator 0:bb348c97df44 2549 #define GPIO_MODER_MODE15_Msk (0x3U << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */
lypinator 0:bb348c97df44 2550 #define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
lypinator 0:bb348c97df44 2551 #define GPIO_MODER_MODE15_0 (0x1U << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */
lypinator 0:bb348c97df44 2552 #define GPIO_MODER_MODE15_1 (0x2U << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */
lypinator 0:bb348c97df44 2553
lypinator 0:bb348c97df44 2554 /* Legacy defines */
lypinator 0:bb348c97df44 2555 #define GPIO_MODER_MODER0_Pos (0U)
lypinator 0:bb348c97df44 2556 #define GPIO_MODER_MODER0_Msk (0x3U << GPIO_MODER_MODER0_Pos) /*!< 0x00000003 */
lypinator 0:bb348c97df44 2557 #define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk
lypinator 0:bb348c97df44 2558 #define GPIO_MODER_MODER0_0 (0x1U << GPIO_MODER_MODER0_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 2559 #define GPIO_MODER_MODER0_1 (0x2U << GPIO_MODER_MODER0_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 2560 #define GPIO_MODER_MODER1_Pos (2U)
lypinator 0:bb348c97df44 2561 #define GPIO_MODER_MODER1_Msk (0x3U << GPIO_MODER_MODER1_Pos) /*!< 0x0000000C */
lypinator 0:bb348c97df44 2562 #define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk
lypinator 0:bb348c97df44 2563 #define GPIO_MODER_MODER1_0 (0x1U << GPIO_MODER_MODER1_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 2564 #define GPIO_MODER_MODER1_1 (0x2U << GPIO_MODER_MODER1_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 2565 #define GPIO_MODER_MODER2_Pos (4U)
lypinator 0:bb348c97df44 2566 #define GPIO_MODER_MODER2_Msk (0x3U << GPIO_MODER_MODER2_Pos) /*!< 0x00000030 */
lypinator 0:bb348c97df44 2567 #define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk
lypinator 0:bb348c97df44 2568 #define GPIO_MODER_MODER2_0 (0x1U << GPIO_MODER_MODER2_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 2569 #define GPIO_MODER_MODER2_1 (0x2U << GPIO_MODER_MODER2_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 2570 #define GPIO_MODER_MODER3_Pos (6U)
lypinator 0:bb348c97df44 2571 #define GPIO_MODER_MODER3_Msk (0x3U << GPIO_MODER_MODER3_Pos) /*!< 0x000000C0 */
lypinator 0:bb348c97df44 2572 #define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk
lypinator 0:bb348c97df44 2573 #define GPIO_MODER_MODER3_0 (0x1U << GPIO_MODER_MODER3_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 2574 #define GPIO_MODER_MODER3_1 (0x2U << GPIO_MODER_MODER3_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 2575 #define GPIO_MODER_MODER4_Pos (8U)
lypinator 0:bb348c97df44 2576 #define GPIO_MODER_MODER4_Msk (0x3U << GPIO_MODER_MODER4_Pos) /*!< 0x00000300 */
lypinator 0:bb348c97df44 2577 #define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk
lypinator 0:bb348c97df44 2578 #define GPIO_MODER_MODER4_0 (0x1U << GPIO_MODER_MODER4_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 2579 #define GPIO_MODER_MODER4_1 (0x2U << GPIO_MODER_MODER4_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 2580 #define GPIO_MODER_MODER5_Pos (10U)
lypinator 0:bb348c97df44 2581 #define GPIO_MODER_MODER5_Msk (0x3U << GPIO_MODER_MODER5_Pos) /*!< 0x00000C00 */
lypinator 0:bb348c97df44 2582 #define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk
lypinator 0:bb348c97df44 2583 #define GPIO_MODER_MODER5_0 (0x1U << GPIO_MODER_MODER5_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 2584 #define GPIO_MODER_MODER5_1 (0x2U << GPIO_MODER_MODER5_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 2585 #define GPIO_MODER_MODER6_Pos (12U)
lypinator 0:bb348c97df44 2586 #define GPIO_MODER_MODER6_Msk (0x3U << GPIO_MODER_MODER6_Pos) /*!< 0x00003000 */
lypinator 0:bb348c97df44 2587 #define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk
lypinator 0:bb348c97df44 2588 #define GPIO_MODER_MODER6_0 (0x1U << GPIO_MODER_MODER6_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 2589 #define GPIO_MODER_MODER6_1 (0x2U << GPIO_MODER_MODER6_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 2590 #define GPIO_MODER_MODER7_Pos (14U)
lypinator 0:bb348c97df44 2591 #define GPIO_MODER_MODER7_Msk (0x3U << GPIO_MODER_MODER7_Pos) /*!< 0x0000C000 */
lypinator 0:bb348c97df44 2592 #define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk
lypinator 0:bb348c97df44 2593 #define GPIO_MODER_MODER7_0 (0x1U << GPIO_MODER_MODER7_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 2594 #define GPIO_MODER_MODER7_1 (0x2U << GPIO_MODER_MODER7_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 2595 #define GPIO_MODER_MODER8_Pos (16U)
lypinator 0:bb348c97df44 2596 #define GPIO_MODER_MODER8_Msk (0x3U << GPIO_MODER_MODER8_Pos) /*!< 0x00030000 */
lypinator 0:bb348c97df44 2597 #define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk
lypinator 0:bb348c97df44 2598 #define GPIO_MODER_MODER8_0 (0x1U << GPIO_MODER_MODER8_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 2599 #define GPIO_MODER_MODER8_1 (0x2U << GPIO_MODER_MODER8_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 2600 #define GPIO_MODER_MODER9_Pos (18U)
lypinator 0:bb348c97df44 2601 #define GPIO_MODER_MODER9_Msk (0x3U << GPIO_MODER_MODER9_Pos) /*!< 0x000C0000 */
lypinator 0:bb348c97df44 2602 #define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk
lypinator 0:bb348c97df44 2603 #define GPIO_MODER_MODER9_0 (0x1U << GPIO_MODER_MODER9_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 2604 #define GPIO_MODER_MODER9_1 (0x2U << GPIO_MODER_MODER9_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 2605 #define GPIO_MODER_MODER10_Pos (20U)
lypinator 0:bb348c97df44 2606 #define GPIO_MODER_MODER10_Msk (0x3U << GPIO_MODER_MODER10_Pos) /*!< 0x00300000 */
lypinator 0:bb348c97df44 2607 #define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk
lypinator 0:bb348c97df44 2608 #define GPIO_MODER_MODER10_0 (0x1U << GPIO_MODER_MODER10_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 2609 #define GPIO_MODER_MODER10_1 (0x2U << GPIO_MODER_MODER10_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 2610 #define GPIO_MODER_MODER11_Pos (22U)
lypinator 0:bb348c97df44 2611 #define GPIO_MODER_MODER11_Msk (0x3U << GPIO_MODER_MODER11_Pos) /*!< 0x00C00000 */
lypinator 0:bb348c97df44 2612 #define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk
lypinator 0:bb348c97df44 2613 #define GPIO_MODER_MODER11_0 (0x1U << GPIO_MODER_MODER11_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 2614 #define GPIO_MODER_MODER11_1 (0x2U << GPIO_MODER_MODER11_Pos) /*!< 0x00800000 */
lypinator 0:bb348c97df44 2615 #define GPIO_MODER_MODER12_Pos (24U)
lypinator 0:bb348c97df44 2616 #define GPIO_MODER_MODER12_Msk (0x3U << GPIO_MODER_MODER12_Pos) /*!< 0x03000000 */
lypinator 0:bb348c97df44 2617 #define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk
lypinator 0:bb348c97df44 2618 #define GPIO_MODER_MODER12_0 (0x1U << GPIO_MODER_MODER12_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 2619 #define GPIO_MODER_MODER12_1 (0x2U << GPIO_MODER_MODER12_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 2620 #define GPIO_MODER_MODER13_Pos (26U)
lypinator 0:bb348c97df44 2621 #define GPIO_MODER_MODER13_Msk (0x3U << GPIO_MODER_MODER13_Pos) /*!< 0x0C000000 */
lypinator 0:bb348c97df44 2622 #define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk
lypinator 0:bb348c97df44 2623 #define GPIO_MODER_MODER13_0 (0x1U << GPIO_MODER_MODER13_Pos) /*!< 0x04000000 */
lypinator 0:bb348c97df44 2624 #define GPIO_MODER_MODER13_1 (0x2U << GPIO_MODER_MODER13_Pos) /*!< 0x08000000 */
lypinator 0:bb348c97df44 2625 #define GPIO_MODER_MODER14_Pos (28U)
lypinator 0:bb348c97df44 2626 #define GPIO_MODER_MODER14_Msk (0x3U << GPIO_MODER_MODER14_Pos) /*!< 0x30000000 */
lypinator 0:bb348c97df44 2627 #define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk
lypinator 0:bb348c97df44 2628 #define GPIO_MODER_MODER14_0 (0x1U << GPIO_MODER_MODER14_Pos) /*!< 0x10000000 */
lypinator 0:bb348c97df44 2629 #define GPIO_MODER_MODER14_1 (0x2U << GPIO_MODER_MODER14_Pos) /*!< 0x20000000 */
lypinator 0:bb348c97df44 2630 #define GPIO_MODER_MODER15_Pos (30U)
lypinator 0:bb348c97df44 2631 #define GPIO_MODER_MODER15_Msk (0x3U << GPIO_MODER_MODER15_Pos) /*!< 0xC0000000 */
lypinator 0:bb348c97df44 2632 #define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk
lypinator 0:bb348c97df44 2633 #define GPIO_MODER_MODER15_0 (0x1U << GPIO_MODER_MODER15_Pos) /*!< 0x40000000 */
lypinator 0:bb348c97df44 2634 #define GPIO_MODER_MODER15_1 (0x2U << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */
lypinator 0:bb348c97df44 2635
lypinator 0:bb348c97df44 2636 /****************** Bits definition for GPIO_OTYPER register ****************/
lypinator 0:bb348c97df44 2637 #define GPIO_OTYPER_OT0_Pos (0U)
lypinator 0:bb348c97df44 2638 #define GPIO_OTYPER_OT0_Msk (0x1U << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 2639 #define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
lypinator 0:bb348c97df44 2640 #define GPIO_OTYPER_OT1_Pos (1U)
lypinator 0:bb348c97df44 2641 #define GPIO_OTYPER_OT1_Msk (0x1U << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 2642 #define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
lypinator 0:bb348c97df44 2643 #define GPIO_OTYPER_OT2_Pos (2U)
lypinator 0:bb348c97df44 2644 #define GPIO_OTYPER_OT2_Msk (0x1U << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 2645 #define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
lypinator 0:bb348c97df44 2646 #define GPIO_OTYPER_OT3_Pos (3U)
lypinator 0:bb348c97df44 2647 #define GPIO_OTYPER_OT3_Msk (0x1U << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 2648 #define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
lypinator 0:bb348c97df44 2649 #define GPIO_OTYPER_OT4_Pos (4U)
lypinator 0:bb348c97df44 2650 #define GPIO_OTYPER_OT4_Msk (0x1U << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 2651 #define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
lypinator 0:bb348c97df44 2652 #define GPIO_OTYPER_OT5_Pos (5U)
lypinator 0:bb348c97df44 2653 #define GPIO_OTYPER_OT5_Msk (0x1U << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 2654 #define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
lypinator 0:bb348c97df44 2655 #define GPIO_OTYPER_OT6_Pos (6U)
lypinator 0:bb348c97df44 2656 #define GPIO_OTYPER_OT6_Msk (0x1U << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 2657 #define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
lypinator 0:bb348c97df44 2658 #define GPIO_OTYPER_OT7_Pos (7U)
lypinator 0:bb348c97df44 2659 #define GPIO_OTYPER_OT7_Msk (0x1U << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 2660 #define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
lypinator 0:bb348c97df44 2661 #define GPIO_OTYPER_OT8_Pos (8U)
lypinator 0:bb348c97df44 2662 #define GPIO_OTYPER_OT8_Msk (0x1U << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 2663 #define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
lypinator 0:bb348c97df44 2664 #define GPIO_OTYPER_OT9_Pos (9U)
lypinator 0:bb348c97df44 2665 #define GPIO_OTYPER_OT9_Msk (0x1U << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 2666 #define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
lypinator 0:bb348c97df44 2667 #define GPIO_OTYPER_OT10_Pos (10U)
lypinator 0:bb348c97df44 2668 #define GPIO_OTYPER_OT10_Msk (0x1U << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 2669 #define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
lypinator 0:bb348c97df44 2670 #define GPIO_OTYPER_OT11_Pos (11U)
lypinator 0:bb348c97df44 2671 #define GPIO_OTYPER_OT11_Msk (0x1U << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 2672 #define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
lypinator 0:bb348c97df44 2673 #define GPIO_OTYPER_OT12_Pos (12U)
lypinator 0:bb348c97df44 2674 #define GPIO_OTYPER_OT12_Msk (0x1U << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 2675 #define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
lypinator 0:bb348c97df44 2676 #define GPIO_OTYPER_OT13_Pos (13U)
lypinator 0:bb348c97df44 2677 #define GPIO_OTYPER_OT13_Msk (0x1U << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 2678 #define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
lypinator 0:bb348c97df44 2679 #define GPIO_OTYPER_OT14_Pos (14U)
lypinator 0:bb348c97df44 2680 #define GPIO_OTYPER_OT14_Msk (0x1U << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 2681 #define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
lypinator 0:bb348c97df44 2682 #define GPIO_OTYPER_OT15_Pos (15U)
lypinator 0:bb348c97df44 2683 #define GPIO_OTYPER_OT15_Msk (0x1U << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 2684 #define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
lypinator 0:bb348c97df44 2685
lypinator 0:bb348c97df44 2686 /* Legacy defines */
lypinator 0:bb348c97df44 2687 #define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0
lypinator 0:bb348c97df44 2688 #define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1
lypinator 0:bb348c97df44 2689 #define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2
lypinator 0:bb348c97df44 2690 #define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3
lypinator 0:bb348c97df44 2691 #define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4
lypinator 0:bb348c97df44 2692 #define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5
lypinator 0:bb348c97df44 2693 #define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6
lypinator 0:bb348c97df44 2694 #define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7
lypinator 0:bb348c97df44 2695 #define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8
lypinator 0:bb348c97df44 2696 #define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9
lypinator 0:bb348c97df44 2697 #define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10
lypinator 0:bb348c97df44 2698 #define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11
lypinator 0:bb348c97df44 2699 #define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12
lypinator 0:bb348c97df44 2700 #define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13
lypinator 0:bb348c97df44 2701 #define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14
lypinator 0:bb348c97df44 2702 #define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15
lypinator 0:bb348c97df44 2703
lypinator 0:bb348c97df44 2704 /****************** Bits definition for GPIO_OSPEEDR register ***************/
lypinator 0:bb348c97df44 2705 #define GPIO_OSPEEDR_OSPEED0_Pos (0U)
lypinator 0:bb348c97df44 2706 #define GPIO_OSPEEDR_OSPEED0_Msk (0x3U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */
lypinator 0:bb348c97df44 2707 #define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk
lypinator 0:bb348c97df44 2708 #define GPIO_OSPEEDR_OSPEED0_0 (0x1U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 2709 #define GPIO_OSPEEDR_OSPEED0_1 (0x2U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 2710 #define GPIO_OSPEEDR_OSPEED1_Pos (2U)
lypinator 0:bb348c97df44 2711 #define GPIO_OSPEEDR_OSPEED1_Msk (0x3U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */
lypinator 0:bb348c97df44 2712 #define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk
lypinator 0:bb348c97df44 2713 #define GPIO_OSPEEDR_OSPEED1_0 (0x1U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 2714 #define GPIO_OSPEEDR_OSPEED1_1 (0x2U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 2715 #define GPIO_OSPEEDR_OSPEED2_Pos (4U)
lypinator 0:bb348c97df44 2716 #define GPIO_OSPEEDR_OSPEED2_Msk (0x3U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */
lypinator 0:bb348c97df44 2717 #define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk
lypinator 0:bb348c97df44 2718 #define GPIO_OSPEEDR_OSPEED2_0 (0x1U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 2719 #define GPIO_OSPEEDR_OSPEED2_1 (0x2U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 2720 #define GPIO_OSPEEDR_OSPEED3_Pos (6U)
lypinator 0:bb348c97df44 2721 #define GPIO_OSPEEDR_OSPEED3_Msk (0x3U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */
lypinator 0:bb348c97df44 2722 #define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk
lypinator 0:bb348c97df44 2723 #define GPIO_OSPEEDR_OSPEED3_0 (0x1U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 2724 #define GPIO_OSPEEDR_OSPEED3_1 (0x2U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 2725 #define GPIO_OSPEEDR_OSPEED4_Pos (8U)
lypinator 0:bb348c97df44 2726 #define GPIO_OSPEEDR_OSPEED4_Msk (0x3U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */
lypinator 0:bb348c97df44 2727 #define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk
lypinator 0:bb348c97df44 2728 #define GPIO_OSPEEDR_OSPEED4_0 (0x1U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 2729 #define GPIO_OSPEEDR_OSPEED4_1 (0x2U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 2730 #define GPIO_OSPEEDR_OSPEED5_Pos (10U)
lypinator 0:bb348c97df44 2731 #define GPIO_OSPEEDR_OSPEED5_Msk (0x3U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */
lypinator 0:bb348c97df44 2732 #define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk
lypinator 0:bb348c97df44 2733 #define GPIO_OSPEEDR_OSPEED5_0 (0x1U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 2734 #define GPIO_OSPEEDR_OSPEED5_1 (0x2U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 2735 #define GPIO_OSPEEDR_OSPEED6_Pos (12U)
lypinator 0:bb348c97df44 2736 #define GPIO_OSPEEDR_OSPEED6_Msk (0x3U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */
lypinator 0:bb348c97df44 2737 #define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk
lypinator 0:bb348c97df44 2738 #define GPIO_OSPEEDR_OSPEED6_0 (0x1U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 2739 #define GPIO_OSPEEDR_OSPEED6_1 (0x2U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 2740 #define GPIO_OSPEEDR_OSPEED7_Pos (14U)
lypinator 0:bb348c97df44 2741 #define GPIO_OSPEEDR_OSPEED7_Msk (0x3U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */
lypinator 0:bb348c97df44 2742 #define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk
lypinator 0:bb348c97df44 2743 #define GPIO_OSPEEDR_OSPEED7_0 (0x1U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 2744 #define GPIO_OSPEEDR_OSPEED7_1 (0x2U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 2745 #define GPIO_OSPEEDR_OSPEED8_Pos (16U)
lypinator 0:bb348c97df44 2746 #define GPIO_OSPEEDR_OSPEED8_Msk (0x3U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */
lypinator 0:bb348c97df44 2747 #define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk
lypinator 0:bb348c97df44 2748 #define GPIO_OSPEEDR_OSPEED8_0 (0x1U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 2749 #define GPIO_OSPEEDR_OSPEED8_1 (0x2U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 2750 #define GPIO_OSPEEDR_OSPEED9_Pos (18U)
lypinator 0:bb348c97df44 2751 #define GPIO_OSPEEDR_OSPEED9_Msk (0x3U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */
lypinator 0:bb348c97df44 2752 #define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk
lypinator 0:bb348c97df44 2753 #define GPIO_OSPEEDR_OSPEED9_0 (0x1U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 2754 #define GPIO_OSPEEDR_OSPEED9_1 (0x2U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 2755 #define GPIO_OSPEEDR_OSPEED10_Pos (20U)
lypinator 0:bb348c97df44 2756 #define GPIO_OSPEEDR_OSPEED10_Msk (0x3U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */
lypinator 0:bb348c97df44 2757 #define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk
lypinator 0:bb348c97df44 2758 #define GPIO_OSPEEDR_OSPEED10_0 (0x1U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 2759 #define GPIO_OSPEEDR_OSPEED10_1 (0x2U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 2760 #define GPIO_OSPEEDR_OSPEED11_Pos (22U)
lypinator 0:bb348c97df44 2761 #define GPIO_OSPEEDR_OSPEED11_Msk (0x3U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */
lypinator 0:bb348c97df44 2762 #define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk
lypinator 0:bb348c97df44 2763 #define GPIO_OSPEEDR_OSPEED11_0 (0x1U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 2764 #define GPIO_OSPEEDR_OSPEED11_1 (0x2U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */
lypinator 0:bb348c97df44 2765 #define GPIO_OSPEEDR_OSPEED12_Pos (24U)
lypinator 0:bb348c97df44 2766 #define GPIO_OSPEEDR_OSPEED12_Msk (0x3U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */
lypinator 0:bb348c97df44 2767 #define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk
lypinator 0:bb348c97df44 2768 #define GPIO_OSPEEDR_OSPEED12_0 (0x1U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 2769 #define GPIO_OSPEEDR_OSPEED12_1 (0x2U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 2770 #define GPIO_OSPEEDR_OSPEED13_Pos (26U)
lypinator 0:bb348c97df44 2771 #define GPIO_OSPEEDR_OSPEED13_Msk (0x3U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */
lypinator 0:bb348c97df44 2772 #define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk
lypinator 0:bb348c97df44 2773 #define GPIO_OSPEEDR_OSPEED13_0 (0x1U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */
lypinator 0:bb348c97df44 2774 #define GPIO_OSPEEDR_OSPEED13_1 (0x2U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */
lypinator 0:bb348c97df44 2775 #define GPIO_OSPEEDR_OSPEED14_Pos (28U)
lypinator 0:bb348c97df44 2776 #define GPIO_OSPEEDR_OSPEED14_Msk (0x3U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */
lypinator 0:bb348c97df44 2777 #define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk
lypinator 0:bb348c97df44 2778 #define GPIO_OSPEEDR_OSPEED14_0 (0x1U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */
lypinator 0:bb348c97df44 2779 #define GPIO_OSPEEDR_OSPEED14_1 (0x2U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */
lypinator 0:bb348c97df44 2780 #define GPIO_OSPEEDR_OSPEED15_Pos (30U)
lypinator 0:bb348c97df44 2781 #define GPIO_OSPEEDR_OSPEED15_Msk (0x3U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */
lypinator 0:bb348c97df44 2782 #define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk
lypinator 0:bb348c97df44 2783 #define GPIO_OSPEEDR_OSPEED15_0 (0x1U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */
lypinator 0:bb348c97df44 2784 #define GPIO_OSPEEDR_OSPEED15_1 (0x2U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */
lypinator 0:bb348c97df44 2785
lypinator 0:bb348c97df44 2786 /* Legacy defines */
lypinator 0:bb348c97df44 2787 #define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEED0
lypinator 0:bb348c97df44 2788 #define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEED0_0
lypinator 0:bb348c97df44 2789 #define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEED0_1
lypinator 0:bb348c97df44 2790 #define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEED1
lypinator 0:bb348c97df44 2791 #define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEED1_0
lypinator 0:bb348c97df44 2792 #define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEED1_1
lypinator 0:bb348c97df44 2793 #define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEED2
lypinator 0:bb348c97df44 2794 #define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEED2_0
lypinator 0:bb348c97df44 2795 #define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEED2_1
lypinator 0:bb348c97df44 2796 #define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEED3
lypinator 0:bb348c97df44 2797 #define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEED3_0
lypinator 0:bb348c97df44 2798 #define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEED3_1
lypinator 0:bb348c97df44 2799 #define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEED4
lypinator 0:bb348c97df44 2800 #define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEED4_0
lypinator 0:bb348c97df44 2801 #define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEED4_1
lypinator 0:bb348c97df44 2802 #define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEED5
lypinator 0:bb348c97df44 2803 #define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEED5_0
lypinator 0:bb348c97df44 2804 #define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEED5_1
lypinator 0:bb348c97df44 2805 #define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEED6
lypinator 0:bb348c97df44 2806 #define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEED6_0
lypinator 0:bb348c97df44 2807 #define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEED6_1
lypinator 0:bb348c97df44 2808 #define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEED7
lypinator 0:bb348c97df44 2809 #define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEED7_0
lypinator 0:bb348c97df44 2810 #define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEED7_1
lypinator 0:bb348c97df44 2811 #define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEED8
lypinator 0:bb348c97df44 2812 #define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEED8_0
lypinator 0:bb348c97df44 2813 #define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEED8_1
lypinator 0:bb348c97df44 2814 #define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEED9
lypinator 0:bb348c97df44 2815 #define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEED9_0
lypinator 0:bb348c97df44 2816 #define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEED9_1
lypinator 0:bb348c97df44 2817 #define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEED10
lypinator 0:bb348c97df44 2818 #define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEED10_0
lypinator 0:bb348c97df44 2819 #define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEED10_1
lypinator 0:bb348c97df44 2820 #define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEED11
lypinator 0:bb348c97df44 2821 #define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEED11_0
lypinator 0:bb348c97df44 2822 #define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEED11_1
lypinator 0:bb348c97df44 2823 #define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEED12
lypinator 0:bb348c97df44 2824 #define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEED12_0
lypinator 0:bb348c97df44 2825 #define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEED12_1
lypinator 0:bb348c97df44 2826 #define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEED13
lypinator 0:bb348c97df44 2827 #define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEED13_0
lypinator 0:bb348c97df44 2828 #define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEED13_1
lypinator 0:bb348c97df44 2829 #define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEED14
lypinator 0:bb348c97df44 2830 #define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEED14_0
lypinator 0:bb348c97df44 2831 #define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEED14_1
lypinator 0:bb348c97df44 2832 #define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEED15
lypinator 0:bb348c97df44 2833 #define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEED15_0
lypinator 0:bb348c97df44 2834 #define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEED15_1
lypinator 0:bb348c97df44 2835
lypinator 0:bb348c97df44 2836 /****************** Bits definition for GPIO_PUPDR register *****************/
lypinator 0:bb348c97df44 2837 #define GPIO_PUPDR_PUPD0_Pos (0U)
lypinator 0:bb348c97df44 2838 #define GPIO_PUPDR_PUPD0_Msk (0x3U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */
lypinator 0:bb348c97df44 2839 #define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
lypinator 0:bb348c97df44 2840 #define GPIO_PUPDR_PUPD0_0 (0x1U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 2841 #define GPIO_PUPDR_PUPD0_1 (0x2U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 2842 #define GPIO_PUPDR_PUPD1_Pos (2U)
lypinator 0:bb348c97df44 2843 #define GPIO_PUPDR_PUPD1_Msk (0x3U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */
lypinator 0:bb348c97df44 2844 #define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
lypinator 0:bb348c97df44 2845 #define GPIO_PUPDR_PUPD1_0 (0x1U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 2846 #define GPIO_PUPDR_PUPD1_1 (0x2U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 2847 #define GPIO_PUPDR_PUPD2_Pos (4U)
lypinator 0:bb348c97df44 2848 #define GPIO_PUPDR_PUPD2_Msk (0x3U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */
lypinator 0:bb348c97df44 2849 #define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
lypinator 0:bb348c97df44 2850 #define GPIO_PUPDR_PUPD2_0 (0x1U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 2851 #define GPIO_PUPDR_PUPD2_1 (0x2U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 2852 #define GPIO_PUPDR_PUPD3_Pos (6U)
lypinator 0:bb348c97df44 2853 #define GPIO_PUPDR_PUPD3_Msk (0x3U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */
lypinator 0:bb348c97df44 2854 #define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
lypinator 0:bb348c97df44 2855 #define GPIO_PUPDR_PUPD3_0 (0x1U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 2856 #define GPIO_PUPDR_PUPD3_1 (0x2U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 2857 #define GPIO_PUPDR_PUPD4_Pos (8U)
lypinator 0:bb348c97df44 2858 #define GPIO_PUPDR_PUPD4_Msk (0x3U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */
lypinator 0:bb348c97df44 2859 #define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
lypinator 0:bb348c97df44 2860 #define GPIO_PUPDR_PUPD4_0 (0x1U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 2861 #define GPIO_PUPDR_PUPD4_1 (0x2U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 2862 #define GPIO_PUPDR_PUPD5_Pos (10U)
lypinator 0:bb348c97df44 2863 #define GPIO_PUPDR_PUPD5_Msk (0x3U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */
lypinator 0:bb348c97df44 2864 #define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
lypinator 0:bb348c97df44 2865 #define GPIO_PUPDR_PUPD5_0 (0x1U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 2866 #define GPIO_PUPDR_PUPD5_1 (0x2U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 2867 #define GPIO_PUPDR_PUPD6_Pos (12U)
lypinator 0:bb348c97df44 2868 #define GPIO_PUPDR_PUPD6_Msk (0x3U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */
lypinator 0:bb348c97df44 2869 #define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
lypinator 0:bb348c97df44 2870 #define GPIO_PUPDR_PUPD6_0 (0x1U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 2871 #define GPIO_PUPDR_PUPD6_1 (0x2U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 2872 #define GPIO_PUPDR_PUPD7_Pos (14U)
lypinator 0:bb348c97df44 2873 #define GPIO_PUPDR_PUPD7_Msk (0x3U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */
lypinator 0:bb348c97df44 2874 #define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
lypinator 0:bb348c97df44 2875 #define GPIO_PUPDR_PUPD7_0 (0x1U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 2876 #define GPIO_PUPDR_PUPD7_1 (0x2U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 2877 #define GPIO_PUPDR_PUPD8_Pos (16U)
lypinator 0:bb348c97df44 2878 #define GPIO_PUPDR_PUPD8_Msk (0x3U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */
lypinator 0:bb348c97df44 2879 #define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
lypinator 0:bb348c97df44 2880 #define GPIO_PUPDR_PUPD8_0 (0x1U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 2881 #define GPIO_PUPDR_PUPD8_1 (0x2U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 2882 #define GPIO_PUPDR_PUPD9_Pos (18U)
lypinator 0:bb348c97df44 2883 #define GPIO_PUPDR_PUPD9_Msk (0x3U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */
lypinator 0:bb348c97df44 2884 #define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
lypinator 0:bb348c97df44 2885 #define GPIO_PUPDR_PUPD9_0 (0x1U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 2886 #define GPIO_PUPDR_PUPD9_1 (0x2U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 2887 #define GPIO_PUPDR_PUPD10_Pos (20U)
lypinator 0:bb348c97df44 2888 #define GPIO_PUPDR_PUPD10_Msk (0x3U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */
lypinator 0:bb348c97df44 2889 #define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
lypinator 0:bb348c97df44 2890 #define GPIO_PUPDR_PUPD10_0 (0x1U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 2891 #define GPIO_PUPDR_PUPD10_1 (0x2U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 2892 #define GPIO_PUPDR_PUPD11_Pos (22U)
lypinator 0:bb348c97df44 2893 #define GPIO_PUPDR_PUPD11_Msk (0x3U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */
lypinator 0:bb348c97df44 2894 #define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
lypinator 0:bb348c97df44 2895 #define GPIO_PUPDR_PUPD11_0 (0x1U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 2896 #define GPIO_PUPDR_PUPD11_1 (0x2U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */
lypinator 0:bb348c97df44 2897 #define GPIO_PUPDR_PUPD12_Pos (24U)
lypinator 0:bb348c97df44 2898 #define GPIO_PUPDR_PUPD12_Msk (0x3U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */
lypinator 0:bb348c97df44 2899 #define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
lypinator 0:bb348c97df44 2900 #define GPIO_PUPDR_PUPD12_0 (0x1U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 2901 #define GPIO_PUPDR_PUPD12_1 (0x2U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 2902 #define GPIO_PUPDR_PUPD13_Pos (26U)
lypinator 0:bb348c97df44 2903 #define GPIO_PUPDR_PUPD13_Msk (0x3U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */
lypinator 0:bb348c97df44 2904 #define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
lypinator 0:bb348c97df44 2905 #define GPIO_PUPDR_PUPD13_0 (0x1U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */
lypinator 0:bb348c97df44 2906 #define GPIO_PUPDR_PUPD13_1 (0x2U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */
lypinator 0:bb348c97df44 2907 #define GPIO_PUPDR_PUPD14_Pos (28U)
lypinator 0:bb348c97df44 2908 #define GPIO_PUPDR_PUPD14_Msk (0x3U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */
lypinator 0:bb348c97df44 2909 #define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
lypinator 0:bb348c97df44 2910 #define GPIO_PUPDR_PUPD14_0 (0x1U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */
lypinator 0:bb348c97df44 2911 #define GPIO_PUPDR_PUPD14_1 (0x2U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */
lypinator 0:bb348c97df44 2912 #define GPIO_PUPDR_PUPD15_Pos (30U)
lypinator 0:bb348c97df44 2913 #define GPIO_PUPDR_PUPD15_Msk (0x3U << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */
lypinator 0:bb348c97df44 2914 #define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
lypinator 0:bb348c97df44 2915 #define GPIO_PUPDR_PUPD15_0 (0x1U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */
lypinator 0:bb348c97df44 2916 #define GPIO_PUPDR_PUPD15_1 (0x2U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */
lypinator 0:bb348c97df44 2917
lypinator 0:bb348c97df44 2918 /* Legacy defines */
lypinator 0:bb348c97df44 2919 #define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPD0
lypinator 0:bb348c97df44 2920 #define GPIO_PUPDR_PUPDR0_0 GPIO_PUPDR_PUPD0_0
lypinator 0:bb348c97df44 2921 #define GPIO_PUPDR_PUPDR0_1 GPIO_PUPDR_PUPD0_1
lypinator 0:bb348c97df44 2922 #define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPD1
lypinator 0:bb348c97df44 2923 #define GPIO_PUPDR_PUPDR1_0 GPIO_PUPDR_PUPD1_0
lypinator 0:bb348c97df44 2924 #define GPIO_PUPDR_PUPDR1_1 GPIO_PUPDR_PUPD1_1
lypinator 0:bb348c97df44 2925 #define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPD2
lypinator 0:bb348c97df44 2926 #define GPIO_PUPDR_PUPDR2_0 GPIO_PUPDR_PUPD2_0
lypinator 0:bb348c97df44 2927 #define GPIO_PUPDR_PUPDR2_1 GPIO_PUPDR_PUPD2_1
lypinator 0:bb348c97df44 2928 #define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPD3
lypinator 0:bb348c97df44 2929 #define GPIO_PUPDR_PUPDR3_0 GPIO_PUPDR_PUPD3_0
lypinator 0:bb348c97df44 2930 #define GPIO_PUPDR_PUPDR3_1 GPIO_PUPDR_PUPD3_1
lypinator 0:bb348c97df44 2931 #define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPD4
lypinator 0:bb348c97df44 2932 #define GPIO_PUPDR_PUPDR4_0 GPIO_PUPDR_PUPD4_0
lypinator 0:bb348c97df44 2933 #define GPIO_PUPDR_PUPDR4_1 GPIO_PUPDR_PUPD4_1
lypinator 0:bb348c97df44 2934 #define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPD5
lypinator 0:bb348c97df44 2935 #define GPIO_PUPDR_PUPDR5_0 GPIO_PUPDR_PUPD5_0
lypinator 0:bb348c97df44 2936 #define GPIO_PUPDR_PUPDR5_1 GPIO_PUPDR_PUPD5_1
lypinator 0:bb348c97df44 2937 #define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPD6
lypinator 0:bb348c97df44 2938 #define GPIO_PUPDR_PUPDR6_0 GPIO_PUPDR_PUPD6_0
lypinator 0:bb348c97df44 2939 #define GPIO_PUPDR_PUPDR6_1 GPIO_PUPDR_PUPD6_1
lypinator 0:bb348c97df44 2940 #define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPD7
lypinator 0:bb348c97df44 2941 #define GPIO_PUPDR_PUPDR7_0 GPIO_PUPDR_PUPD7_0
lypinator 0:bb348c97df44 2942 #define GPIO_PUPDR_PUPDR7_1 GPIO_PUPDR_PUPD7_1
lypinator 0:bb348c97df44 2943 #define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPD8
lypinator 0:bb348c97df44 2944 #define GPIO_PUPDR_PUPDR8_0 GPIO_PUPDR_PUPD8_0
lypinator 0:bb348c97df44 2945 #define GPIO_PUPDR_PUPDR8_1 GPIO_PUPDR_PUPD8_1
lypinator 0:bb348c97df44 2946 #define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPD9
lypinator 0:bb348c97df44 2947 #define GPIO_PUPDR_PUPDR9_0 GPIO_PUPDR_PUPD9_0
lypinator 0:bb348c97df44 2948 #define GPIO_PUPDR_PUPDR9_1 GPIO_PUPDR_PUPD9_1
lypinator 0:bb348c97df44 2949 #define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPD10
lypinator 0:bb348c97df44 2950 #define GPIO_PUPDR_PUPDR10_0 GPIO_PUPDR_PUPD10_0
lypinator 0:bb348c97df44 2951 #define GPIO_PUPDR_PUPDR10_1 GPIO_PUPDR_PUPD10_1
lypinator 0:bb348c97df44 2952 #define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPD11
lypinator 0:bb348c97df44 2953 #define GPIO_PUPDR_PUPDR11_0 GPIO_PUPDR_PUPD11_0
lypinator 0:bb348c97df44 2954 #define GPIO_PUPDR_PUPDR11_1 GPIO_PUPDR_PUPD11_1
lypinator 0:bb348c97df44 2955 #define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPD12
lypinator 0:bb348c97df44 2956 #define GPIO_PUPDR_PUPDR12_0 GPIO_PUPDR_PUPD12_0
lypinator 0:bb348c97df44 2957 #define GPIO_PUPDR_PUPDR12_1 GPIO_PUPDR_PUPD12_1
lypinator 0:bb348c97df44 2958 #define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPD13
lypinator 0:bb348c97df44 2959 #define GPIO_PUPDR_PUPDR13_0 GPIO_PUPDR_PUPD13_0
lypinator 0:bb348c97df44 2960 #define GPIO_PUPDR_PUPDR13_1 GPIO_PUPDR_PUPD13_1
lypinator 0:bb348c97df44 2961 #define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPD14
lypinator 0:bb348c97df44 2962 #define GPIO_PUPDR_PUPDR14_0 GPIO_PUPDR_PUPD14_0
lypinator 0:bb348c97df44 2963 #define GPIO_PUPDR_PUPDR14_1 GPIO_PUPDR_PUPD14_1
lypinator 0:bb348c97df44 2964 #define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPD15
lypinator 0:bb348c97df44 2965 #define GPIO_PUPDR_PUPDR15_0 GPIO_PUPDR_PUPD15_0
lypinator 0:bb348c97df44 2966 #define GPIO_PUPDR_PUPDR15_1 GPIO_PUPDR_PUPD15_1
lypinator 0:bb348c97df44 2967
lypinator 0:bb348c97df44 2968 /****************** Bits definition for GPIO_IDR register *******************/
lypinator 0:bb348c97df44 2969 #define GPIO_IDR_ID0_Pos (0U)
lypinator 0:bb348c97df44 2970 #define GPIO_IDR_ID0_Msk (0x1U << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 2971 #define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
lypinator 0:bb348c97df44 2972 #define GPIO_IDR_ID1_Pos (1U)
lypinator 0:bb348c97df44 2973 #define GPIO_IDR_ID1_Msk (0x1U << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 2974 #define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
lypinator 0:bb348c97df44 2975 #define GPIO_IDR_ID2_Pos (2U)
lypinator 0:bb348c97df44 2976 #define GPIO_IDR_ID2_Msk (0x1U << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 2977 #define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
lypinator 0:bb348c97df44 2978 #define GPIO_IDR_ID3_Pos (3U)
lypinator 0:bb348c97df44 2979 #define GPIO_IDR_ID3_Msk (0x1U << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 2980 #define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
lypinator 0:bb348c97df44 2981 #define GPIO_IDR_ID4_Pos (4U)
lypinator 0:bb348c97df44 2982 #define GPIO_IDR_ID4_Msk (0x1U << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 2983 #define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
lypinator 0:bb348c97df44 2984 #define GPIO_IDR_ID5_Pos (5U)
lypinator 0:bb348c97df44 2985 #define GPIO_IDR_ID5_Msk (0x1U << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 2986 #define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
lypinator 0:bb348c97df44 2987 #define GPIO_IDR_ID6_Pos (6U)
lypinator 0:bb348c97df44 2988 #define GPIO_IDR_ID6_Msk (0x1U << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 2989 #define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
lypinator 0:bb348c97df44 2990 #define GPIO_IDR_ID7_Pos (7U)
lypinator 0:bb348c97df44 2991 #define GPIO_IDR_ID7_Msk (0x1U << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 2992 #define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
lypinator 0:bb348c97df44 2993 #define GPIO_IDR_ID8_Pos (8U)
lypinator 0:bb348c97df44 2994 #define GPIO_IDR_ID8_Msk (0x1U << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 2995 #define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
lypinator 0:bb348c97df44 2996 #define GPIO_IDR_ID9_Pos (9U)
lypinator 0:bb348c97df44 2997 #define GPIO_IDR_ID9_Msk (0x1U << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 2998 #define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
lypinator 0:bb348c97df44 2999 #define GPIO_IDR_ID10_Pos (10U)
lypinator 0:bb348c97df44 3000 #define GPIO_IDR_ID10_Msk (0x1U << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 3001 #define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
lypinator 0:bb348c97df44 3002 #define GPIO_IDR_ID11_Pos (11U)
lypinator 0:bb348c97df44 3003 #define GPIO_IDR_ID11_Msk (0x1U << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 3004 #define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
lypinator 0:bb348c97df44 3005 #define GPIO_IDR_ID12_Pos (12U)
lypinator 0:bb348c97df44 3006 #define GPIO_IDR_ID12_Msk (0x1U << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 3007 #define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
lypinator 0:bb348c97df44 3008 #define GPIO_IDR_ID13_Pos (13U)
lypinator 0:bb348c97df44 3009 #define GPIO_IDR_ID13_Msk (0x1U << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 3010 #define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
lypinator 0:bb348c97df44 3011 #define GPIO_IDR_ID14_Pos (14U)
lypinator 0:bb348c97df44 3012 #define GPIO_IDR_ID14_Msk (0x1U << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 3013 #define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
lypinator 0:bb348c97df44 3014 #define GPIO_IDR_ID15_Pos (15U)
lypinator 0:bb348c97df44 3015 #define GPIO_IDR_ID15_Msk (0x1U << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 3016 #define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
lypinator 0:bb348c97df44 3017
lypinator 0:bb348c97df44 3018 /* Legacy defines */
lypinator 0:bb348c97df44 3019 #define GPIO_IDR_IDR_0 GPIO_IDR_ID0
lypinator 0:bb348c97df44 3020 #define GPIO_IDR_IDR_1 GPIO_IDR_ID1
lypinator 0:bb348c97df44 3021 #define GPIO_IDR_IDR_2 GPIO_IDR_ID2
lypinator 0:bb348c97df44 3022 #define GPIO_IDR_IDR_3 GPIO_IDR_ID3
lypinator 0:bb348c97df44 3023 #define GPIO_IDR_IDR_4 GPIO_IDR_ID4
lypinator 0:bb348c97df44 3024 #define GPIO_IDR_IDR_5 GPIO_IDR_ID5
lypinator 0:bb348c97df44 3025 #define GPIO_IDR_IDR_6 GPIO_IDR_ID6
lypinator 0:bb348c97df44 3026 #define GPIO_IDR_IDR_7 GPIO_IDR_ID7
lypinator 0:bb348c97df44 3027 #define GPIO_IDR_IDR_8 GPIO_IDR_ID8
lypinator 0:bb348c97df44 3028 #define GPIO_IDR_IDR_9 GPIO_IDR_ID9
lypinator 0:bb348c97df44 3029 #define GPIO_IDR_IDR_10 GPIO_IDR_ID10
lypinator 0:bb348c97df44 3030 #define GPIO_IDR_IDR_11 GPIO_IDR_ID11
lypinator 0:bb348c97df44 3031 #define GPIO_IDR_IDR_12 GPIO_IDR_ID12
lypinator 0:bb348c97df44 3032 #define GPIO_IDR_IDR_13 GPIO_IDR_ID13
lypinator 0:bb348c97df44 3033 #define GPIO_IDR_IDR_14 GPIO_IDR_ID14
lypinator 0:bb348c97df44 3034 #define GPIO_IDR_IDR_15 GPIO_IDR_ID15
lypinator 0:bb348c97df44 3035
lypinator 0:bb348c97df44 3036 /****************** Bits definition for GPIO_ODR register *******************/
lypinator 0:bb348c97df44 3037 #define GPIO_ODR_OD0_Pos (0U)
lypinator 0:bb348c97df44 3038 #define GPIO_ODR_OD0_Msk (0x1U << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 3039 #define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
lypinator 0:bb348c97df44 3040 #define GPIO_ODR_OD1_Pos (1U)
lypinator 0:bb348c97df44 3041 #define GPIO_ODR_OD1_Msk (0x1U << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 3042 #define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
lypinator 0:bb348c97df44 3043 #define GPIO_ODR_OD2_Pos (2U)
lypinator 0:bb348c97df44 3044 #define GPIO_ODR_OD2_Msk (0x1U << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 3045 #define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
lypinator 0:bb348c97df44 3046 #define GPIO_ODR_OD3_Pos (3U)
lypinator 0:bb348c97df44 3047 #define GPIO_ODR_OD3_Msk (0x1U << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 3048 #define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
lypinator 0:bb348c97df44 3049 #define GPIO_ODR_OD4_Pos (4U)
lypinator 0:bb348c97df44 3050 #define GPIO_ODR_OD4_Msk (0x1U << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 3051 #define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
lypinator 0:bb348c97df44 3052 #define GPIO_ODR_OD5_Pos (5U)
lypinator 0:bb348c97df44 3053 #define GPIO_ODR_OD5_Msk (0x1U << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 3054 #define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
lypinator 0:bb348c97df44 3055 #define GPIO_ODR_OD6_Pos (6U)
lypinator 0:bb348c97df44 3056 #define GPIO_ODR_OD6_Msk (0x1U << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 3057 #define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
lypinator 0:bb348c97df44 3058 #define GPIO_ODR_OD7_Pos (7U)
lypinator 0:bb348c97df44 3059 #define GPIO_ODR_OD7_Msk (0x1U << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 3060 #define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
lypinator 0:bb348c97df44 3061 #define GPIO_ODR_OD8_Pos (8U)
lypinator 0:bb348c97df44 3062 #define GPIO_ODR_OD8_Msk (0x1U << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 3063 #define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
lypinator 0:bb348c97df44 3064 #define GPIO_ODR_OD9_Pos (9U)
lypinator 0:bb348c97df44 3065 #define GPIO_ODR_OD9_Msk (0x1U << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 3066 #define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
lypinator 0:bb348c97df44 3067 #define GPIO_ODR_OD10_Pos (10U)
lypinator 0:bb348c97df44 3068 #define GPIO_ODR_OD10_Msk (0x1U << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 3069 #define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
lypinator 0:bb348c97df44 3070 #define GPIO_ODR_OD11_Pos (11U)
lypinator 0:bb348c97df44 3071 #define GPIO_ODR_OD11_Msk (0x1U << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 3072 #define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
lypinator 0:bb348c97df44 3073 #define GPIO_ODR_OD12_Pos (12U)
lypinator 0:bb348c97df44 3074 #define GPIO_ODR_OD12_Msk (0x1U << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 3075 #define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
lypinator 0:bb348c97df44 3076 #define GPIO_ODR_OD13_Pos (13U)
lypinator 0:bb348c97df44 3077 #define GPIO_ODR_OD13_Msk (0x1U << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 3078 #define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
lypinator 0:bb348c97df44 3079 #define GPIO_ODR_OD14_Pos (14U)
lypinator 0:bb348c97df44 3080 #define GPIO_ODR_OD14_Msk (0x1U << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 3081 #define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
lypinator 0:bb348c97df44 3082 #define GPIO_ODR_OD15_Pos (15U)
lypinator 0:bb348c97df44 3083 #define GPIO_ODR_OD15_Msk (0x1U << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 3084 #define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
lypinator 0:bb348c97df44 3085 /* Legacy defines */
lypinator 0:bb348c97df44 3086 #define GPIO_ODR_ODR_0 GPIO_ODR_OD0
lypinator 0:bb348c97df44 3087 #define GPIO_ODR_ODR_1 GPIO_ODR_OD1
lypinator 0:bb348c97df44 3088 #define GPIO_ODR_ODR_2 GPIO_ODR_OD2
lypinator 0:bb348c97df44 3089 #define GPIO_ODR_ODR_3 GPIO_ODR_OD3
lypinator 0:bb348c97df44 3090 #define GPIO_ODR_ODR_4 GPIO_ODR_OD4
lypinator 0:bb348c97df44 3091 #define GPIO_ODR_ODR_5 GPIO_ODR_OD5
lypinator 0:bb348c97df44 3092 #define GPIO_ODR_ODR_6 GPIO_ODR_OD6
lypinator 0:bb348c97df44 3093 #define GPIO_ODR_ODR_7 GPIO_ODR_OD7
lypinator 0:bb348c97df44 3094 #define GPIO_ODR_ODR_8 GPIO_ODR_OD8
lypinator 0:bb348c97df44 3095 #define GPIO_ODR_ODR_9 GPIO_ODR_OD9
lypinator 0:bb348c97df44 3096 #define GPIO_ODR_ODR_10 GPIO_ODR_OD10
lypinator 0:bb348c97df44 3097 #define GPIO_ODR_ODR_11 GPIO_ODR_OD11
lypinator 0:bb348c97df44 3098 #define GPIO_ODR_ODR_12 GPIO_ODR_OD12
lypinator 0:bb348c97df44 3099 #define GPIO_ODR_ODR_13 GPIO_ODR_OD13
lypinator 0:bb348c97df44 3100 #define GPIO_ODR_ODR_14 GPIO_ODR_OD14
lypinator 0:bb348c97df44 3101 #define GPIO_ODR_ODR_15 GPIO_ODR_OD15
lypinator 0:bb348c97df44 3102
lypinator 0:bb348c97df44 3103 /****************** Bits definition for GPIO_BSRR register ******************/
lypinator 0:bb348c97df44 3104 #define GPIO_BSRR_BS0_Pos (0U)
lypinator 0:bb348c97df44 3105 #define GPIO_BSRR_BS0_Msk (0x1U << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 3106 #define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
lypinator 0:bb348c97df44 3107 #define GPIO_BSRR_BS1_Pos (1U)
lypinator 0:bb348c97df44 3108 #define GPIO_BSRR_BS1_Msk (0x1U << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 3109 #define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
lypinator 0:bb348c97df44 3110 #define GPIO_BSRR_BS2_Pos (2U)
lypinator 0:bb348c97df44 3111 #define GPIO_BSRR_BS2_Msk (0x1U << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 3112 #define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
lypinator 0:bb348c97df44 3113 #define GPIO_BSRR_BS3_Pos (3U)
lypinator 0:bb348c97df44 3114 #define GPIO_BSRR_BS3_Msk (0x1U << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 3115 #define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
lypinator 0:bb348c97df44 3116 #define GPIO_BSRR_BS4_Pos (4U)
lypinator 0:bb348c97df44 3117 #define GPIO_BSRR_BS4_Msk (0x1U << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 3118 #define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
lypinator 0:bb348c97df44 3119 #define GPIO_BSRR_BS5_Pos (5U)
lypinator 0:bb348c97df44 3120 #define GPIO_BSRR_BS5_Msk (0x1U << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 3121 #define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
lypinator 0:bb348c97df44 3122 #define GPIO_BSRR_BS6_Pos (6U)
lypinator 0:bb348c97df44 3123 #define GPIO_BSRR_BS6_Msk (0x1U << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 3124 #define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
lypinator 0:bb348c97df44 3125 #define GPIO_BSRR_BS7_Pos (7U)
lypinator 0:bb348c97df44 3126 #define GPIO_BSRR_BS7_Msk (0x1U << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 3127 #define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
lypinator 0:bb348c97df44 3128 #define GPIO_BSRR_BS8_Pos (8U)
lypinator 0:bb348c97df44 3129 #define GPIO_BSRR_BS8_Msk (0x1U << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 3130 #define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
lypinator 0:bb348c97df44 3131 #define GPIO_BSRR_BS9_Pos (9U)
lypinator 0:bb348c97df44 3132 #define GPIO_BSRR_BS9_Msk (0x1U << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 3133 #define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
lypinator 0:bb348c97df44 3134 #define GPIO_BSRR_BS10_Pos (10U)
lypinator 0:bb348c97df44 3135 #define GPIO_BSRR_BS10_Msk (0x1U << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 3136 #define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
lypinator 0:bb348c97df44 3137 #define GPIO_BSRR_BS11_Pos (11U)
lypinator 0:bb348c97df44 3138 #define GPIO_BSRR_BS11_Msk (0x1U << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 3139 #define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
lypinator 0:bb348c97df44 3140 #define GPIO_BSRR_BS12_Pos (12U)
lypinator 0:bb348c97df44 3141 #define GPIO_BSRR_BS12_Msk (0x1U << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 3142 #define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
lypinator 0:bb348c97df44 3143 #define GPIO_BSRR_BS13_Pos (13U)
lypinator 0:bb348c97df44 3144 #define GPIO_BSRR_BS13_Msk (0x1U << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 3145 #define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
lypinator 0:bb348c97df44 3146 #define GPIO_BSRR_BS14_Pos (14U)
lypinator 0:bb348c97df44 3147 #define GPIO_BSRR_BS14_Msk (0x1U << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 3148 #define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
lypinator 0:bb348c97df44 3149 #define GPIO_BSRR_BS15_Pos (15U)
lypinator 0:bb348c97df44 3150 #define GPIO_BSRR_BS15_Msk (0x1U << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 3151 #define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
lypinator 0:bb348c97df44 3152 #define GPIO_BSRR_BR0_Pos (16U)
lypinator 0:bb348c97df44 3153 #define GPIO_BSRR_BR0_Msk (0x1U << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 3154 #define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
lypinator 0:bb348c97df44 3155 #define GPIO_BSRR_BR1_Pos (17U)
lypinator 0:bb348c97df44 3156 #define GPIO_BSRR_BR1_Msk (0x1U << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 3157 #define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
lypinator 0:bb348c97df44 3158 #define GPIO_BSRR_BR2_Pos (18U)
lypinator 0:bb348c97df44 3159 #define GPIO_BSRR_BR2_Msk (0x1U << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 3160 #define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
lypinator 0:bb348c97df44 3161 #define GPIO_BSRR_BR3_Pos (19U)
lypinator 0:bb348c97df44 3162 #define GPIO_BSRR_BR3_Msk (0x1U << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 3163 #define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
lypinator 0:bb348c97df44 3164 #define GPIO_BSRR_BR4_Pos (20U)
lypinator 0:bb348c97df44 3165 #define GPIO_BSRR_BR4_Msk (0x1U << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 3166 #define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
lypinator 0:bb348c97df44 3167 #define GPIO_BSRR_BR5_Pos (21U)
lypinator 0:bb348c97df44 3168 #define GPIO_BSRR_BR5_Msk (0x1U << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 3169 #define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
lypinator 0:bb348c97df44 3170 #define GPIO_BSRR_BR6_Pos (22U)
lypinator 0:bb348c97df44 3171 #define GPIO_BSRR_BR6_Msk (0x1U << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 3172 #define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
lypinator 0:bb348c97df44 3173 #define GPIO_BSRR_BR7_Pos (23U)
lypinator 0:bb348c97df44 3174 #define GPIO_BSRR_BR7_Msk (0x1U << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
lypinator 0:bb348c97df44 3175 #define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
lypinator 0:bb348c97df44 3176 #define GPIO_BSRR_BR8_Pos (24U)
lypinator 0:bb348c97df44 3177 #define GPIO_BSRR_BR8_Msk (0x1U << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 3178 #define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
lypinator 0:bb348c97df44 3179 #define GPIO_BSRR_BR9_Pos (25U)
lypinator 0:bb348c97df44 3180 #define GPIO_BSRR_BR9_Msk (0x1U << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 3181 #define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
lypinator 0:bb348c97df44 3182 #define GPIO_BSRR_BR10_Pos (26U)
lypinator 0:bb348c97df44 3183 #define GPIO_BSRR_BR10_Msk (0x1U << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
lypinator 0:bb348c97df44 3184 #define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
lypinator 0:bb348c97df44 3185 #define GPIO_BSRR_BR11_Pos (27U)
lypinator 0:bb348c97df44 3186 #define GPIO_BSRR_BR11_Msk (0x1U << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
lypinator 0:bb348c97df44 3187 #define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
lypinator 0:bb348c97df44 3188 #define GPIO_BSRR_BR12_Pos (28U)
lypinator 0:bb348c97df44 3189 #define GPIO_BSRR_BR12_Msk (0x1U << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
lypinator 0:bb348c97df44 3190 #define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
lypinator 0:bb348c97df44 3191 #define GPIO_BSRR_BR13_Pos (29U)
lypinator 0:bb348c97df44 3192 #define GPIO_BSRR_BR13_Msk (0x1U << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
lypinator 0:bb348c97df44 3193 #define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
lypinator 0:bb348c97df44 3194 #define GPIO_BSRR_BR14_Pos (30U)
lypinator 0:bb348c97df44 3195 #define GPIO_BSRR_BR14_Msk (0x1U << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
lypinator 0:bb348c97df44 3196 #define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
lypinator 0:bb348c97df44 3197 #define GPIO_BSRR_BR15_Pos (31U)
lypinator 0:bb348c97df44 3198 #define GPIO_BSRR_BR15_Msk (0x1U << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
lypinator 0:bb348c97df44 3199 #define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
lypinator 0:bb348c97df44 3200
lypinator 0:bb348c97df44 3201 /* Legacy defines */
lypinator 0:bb348c97df44 3202 #define GPIO_BSRR_BS_0 GPIO_BSRR_BS0
lypinator 0:bb348c97df44 3203 #define GPIO_BSRR_BS_1 GPIO_BSRR_BS1
lypinator 0:bb348c97df44 3204 #define GPIO_BSRR_BS_2 GPIO_BSRR_BS2
lypinator 0:bb348c97df44 3205 #define GPIO_BSRR_BS_3 GPIO_BSRR_BS3
lypinator 0:bb348c97df44 3206 #define GPIO_BSRR_BS_4 GPIO_BSRR_BS4
lypinator 0:bb348c97df44 3207 #define GPIO_BSRR_BS_5 GPIO_BSRR_BS5
lypinator 0:bb348c97df44 3208 #define GPIO_BSRR_BS_6 GPIO_BSRR_BS6
lypinator 0:bb348c97df44 3209 #define GPIO_BSRR_BS_7 GPIO_BSRR_BS7
lypinator 0:bb348c97df44 3210 #define GPIO_BSRR_BS_8 GPIO_BSRR_BS8
lypinator 0:bb348c97df44 3211 #define GPIO_BSRR_BS_9 GPIO_BSRR_BS9
lypinator 0:bb348c97df44 3212 #define GPIO_BSRR_BS_10 GPIO_BSRR_BS10
lypinator 0:bb348c97df44 3213 #define GPIO_BSRR_BS_11 GPIO_BSRR_BS11
lypinator 0:bb348c97df44 3214 #define GPIO_BSRR_BS_12 GPIO_BSRR_BS12
lypinator 0:bb348c97df44 3215 #define GPIO_BSRR_BS_13 GPIO_BSRR_BS13
lypinator 0:bb348c97df44 3216 #define GPIO_BSRR_BS_14 GPIO_BSRR_BS14
lypinator 0:bb348c97df44 3217 #define GPIO_BSRR_BS_15 GPIO_BSRR_BS15
lypinator 0:bb348c97df44 3218 #define GPIO_BSRR_BR_0 GPIO_BSRR_BR0
lypinator 0:bb348c97df44 3219 #define GPIO_BSRR_BR_1 GPIO_BSRR_BR1
lypinator 0:bb348c97df44 3220 #define GPIO_BSRR_BR_2 GPIO_BSRR_BR2
lypinator 0:bb348c97df44 3221 #define GPIO_BSRR_BR_3 GPIO_BSRR_BR3
lypinator 0:bb348c97df44 3222 #define GPIO_BSRR_BR_4 GPIO_BSRR_BR4
lypinator 0:bb348c97df44 3223 #define GPIO_BSRR_BR_5 GPIO_BSRR_BR5
lypinator 0:bb348c97df44 3224 #define GPIO_BSRR_BR_6 GPIO_BSRR_BR6
lypinator 0:bb348c97df44 3225 #define GPIO_BSRR_BR_7 GPIO_BSRR_BR7
lypinator 0:bb348c97df44 3226 #define GPIO_BSRR_BR_8 GPIO_BSRR_BR8
lypinator 0:bb348c97df44 3227 #define GPIO_BSRR_BR_9 GPIO_BSRR_BR9
lypinator 0:bb348c97df44 3228 #define GPIO_BSRR_BR_10 GPIO_BSRR_BR10
lypinator 0:bb348c97df44 3229 #define GPIO_BSRR_BR_11 GPIO_BSRR_BR11
lypinator 0:bb348c97df44 3230 #define GPIO_BSRR_BR_12 GPIO_BSRR_BR12
lypinator 0:bb348c97df44 3231 #define GPIO_BSRR_BR_13 GPIO_BSRR_BR13
lypinator 0:bb348c97df44 3232 #define GPIO_BSRR_BR_14 GPIO_BSRR_BR14
lypinator 0:bb348c97df44 3233 #define GPIO_BSRR_BR_15 GPIO_BSRR_BR15
lypinator 0:bb348c97df44 3234 /****************** Bit definition for GPIO_LCKR register *********************/
lypinator 0:bb348c97df44 3235 #define GPIO_LCKR_LCK0_Pos (0U)
lypinator 0:bb348c97df44 3236 #define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 3237 #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
lypinator 0:bb348c97df44 3238 #define GPIO_LCKR_LCK1_Pos (1U)
lypinator 0:bb348c97df44 3239 #define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 3240 #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
lypinator 0:bb348c97df44 3241 #define GPIO_LCKR_LCK2_Pos (2U)
lypinator 0:bb348c97df44 3242 #define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 3243 #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
lypinator 0:bb348c97df44 3244 #define GPIO_LCKR_LCK3_Pos (3U)
lypinator 0:bb348c97df44 3245 #define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 3246 #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
lypinator 0:bb348c97df44 3247 #define GPIO_LCKR_LCK4_Pos (4U)
lypinator 0:bb348c97df44 3248 #define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 3249 #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
lypinator 0:bb348c97df44 3250 #define GPIO_LCKR_LCK5_Pos (5U)
lypinator 0:bb348c97df44 3251 #define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 3252 #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
lypinator 0:bb348c97df44 3253 #define GPIO_LCKR_LCK6_Pos (6U)
lypinator 0:bb348c97df44 3254 #define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 3255 #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
lypinator 0:bb348c97df44 3256 #define GPIO_LCKR_LCK7_Pos (7U)
lypinator 0:bb348c97df44 3257 #define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 3258 #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
lypinator 0:bb348c97df44 3259 #define GPIO_LCKR_LCK8_Pos (8U)
lypinator 0:bb348c97df44 3260 #define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 3261 #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
lypinator 0:bb348c97df44 3262 #define GPIO_LCKR_LCK9_Pos (9U)
lypinator 0:bb348c97df44 3263 #define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 3264 #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
lypinator 0:bb348c97df44 3265 #define GPIO_LCKR_LCK10_Pos (10U)
lypinator 0:bb348c97df44 3266 #define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 3267 #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
lypinator 0:bb348c97df44 3268 #define GPIO_LCKR_LCK11_Pos (11U)
lypinator 0:bb348c97df44 3269 #define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 3270 #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
lypinator 0:bb348c97df44 3271 #define GPIO_LCKR_LCK12_Pos (12U)
lypinator 0:bb348c97df44 3272 #define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 3273 #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
lypinator 0:bb348c97df44 3274 #define GPIO_LCKR_LCK13_Pos (13U)
lypinator 0:bb348c97df44 3275 #define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 3276 #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
lypinator 0:bb348c97df44 3277 #define GPIO_LCKR_LCK14_Pos (14U)
lypinator 0:bb348c97df44 3278 #define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 3279 #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
lypinator 0:bb348c97df44 3280 #define GPIO_LCKR_LCK15_Pos (15U)
lypinator 0:bb348c97df44 3281 #define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 3282 #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
lypinator 0:bb348c97df44 3283 #define GPIO_LCKR_LCKK_Pos (16U)
lypinator 0:bb348c97df44 3284 #define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 3285 #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
lypinator 0:bb348c97df44 3286 /****************** Bit definition for GPIO_AFRL register *********************/
lypinator 0:bb348c97df44 3287 #define GPIO_AFRL_AFSEL0_Pos (0U)
lypinator 0:bb348c97df44 3288 #define GPIO_AFRL_AFSEL0_Msk (0xFU << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
lypinator 0:bb348c97df44 3289 #define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
lypinator 0:bb348c97df44 3290 #define GPIO_AFRL_AFSEL0_0 (0x1U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 3291 #define GPIO_AFRL_AFSEL0_1 (0x2U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 3292 #define GPIO_AFRL_AFSEL0_2 (0x4U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 3293 #define GPIO_AFRL_AFSEL0_3 (0x8U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 3294 #define GPIO_AFRL_AFSEL1_Pos (4U)
lypinator 0:bb348c97df44 3295 #define GPIO_AFRL_AFSEL1_Msk (0xFU << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
lypinator 0:bb348c97df44 3296 #define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
lypinator 0:bb348c97df44 3297 #define GPIO_AFRL_AFSEL1_0 (0x1U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 3298 #define GPIO_AFRL_AFSEL1_1 (0x2U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 3299 #define GPIO_AFRL_AFSEL1_2 (0x4U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 3300 #define GPIO_AFRL_AFSEL1_3 (0x8U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 3301 #define GPIO_AFRL_AFSEL2_Pos (8U)
lypinator 0:bb348c97df44 3302 #define GPIO_AFRL_AFSEL2_Msk (0xFU << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
lypinator 0:bb348c97df44 3303 #define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
lypinator 0:bb348c97df44 3304 #define GPIO_AFRL_AFSEL2_0 (0x1U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 3305 #define GPIO_AFRL_AFSEL2_1 (0x2U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 3306 #define GPIO_AFRL_AFSEL2_2 (0x4U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 3307 #define GPIO_AFRL_AFSEL2_3 (0x8U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 3308 #define GPIO_AFRL_AFSEL3_Pos (12U)
lypinator 0:bb348c97df44 3309 #define GPIO_AFRL_AFSEL3_Msk (0xFU << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
lypinator 0:bb348c97df44 3310 #define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
lypinator 0:bb348c97df44 3311 #define GPIO_AFRL_AFSEL3_0 (0x1U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 3312 #define GPIO_AFRL_AFSEL3_1 (0x2U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 3313 #define GPIO_AFRL_AFSEL3_2 (0x4U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 3314 #define GPIO_AFRL_AFSEL3_3 (0x8U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 3315 #define GPIO_AFRL_AFSEL4_Pos (16U)
lypinator 0:bb348c97df44 3316 #define GPIO_AFRL_AFSEL4_Msk (0xFU << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
lypinator 0:bb348c97df44 3317 #define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
lypinator 0:bb348c97df44 3318 #define GPIO_AFRL_AFSEL4_0 (0x1U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 3319 #define GPIO_AFRL_AFSEL4_1 (0x2U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 3320 #define GPIO_AFRL_AFSEL4_2 (0x4U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 3321 #define GPIO_AFRL_AFSEL4_3 (0x8U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 3322 #define GPIO_AFRL_AFSEL5_Pos (20U)
lypinator 0:bb348c97df44 3323 #define GPIO_AFRL_AFSEL5_Msk (0xFU << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
lypinator 0:bb348c97df44 3324 #define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
lypinator 0:bb348c97df44 3325 #define GPIO_AFRL_AFSEL5_0 (0x1U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 3326 #define GPIO_AFRL_AFSEL5_1 (0x2U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 3327 #define GPIO_AFRL_AFSEL5_2 (0x4U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 3328 #define GPIO_AFRL_AFSEL5_3 (0x8U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */
lypinator 0:bb348c97df44 3329 #define GPIO_AFRL_AFSEL6_Pos (24U)
lypinator 0:bb348c97df44 3330 #define GPIO_AFRL_AFSEL6_Msk (0xFU << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
lypinator 0:bb348c97df44 3331 #define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
lypinator 0:bb348c97df44 3332 #define GPIO_AFRL_AFSEL6_0 (0x1U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 3333 #define GPIO_AFRL_AFSEL6_1 (0x2U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 3334 #define GPIO_AFRL_AFSEL6_2 (0x4U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */
lypinator 0:bb348c97df44 3335 #define GPIO_AFRL_AFSEL6_3 (0x8U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */
lypinator 0:bb348c97df44 3336 #define GPIO_AFRL_AFSEL7_Pos (28U)
lypinator 0:bb348c97df44 3337 #define GPIO_AFRL_AFSEL7_Msk (0xFU << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
lypinator 0:bb348c97df44 3338 #define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
lypinator 0:bb348c97df44 3339 #define GPIO_AFRL_AFSEL7_0 (0x1U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */
lypinator 0:bb348c97df44 3340 #define GPIO_AFRL_AFSEL7_1 (0x2U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */
lypinator 0:bb348c97df44 3341 #define GPIO_AFRL_AFSEL7_2 (0x4U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */
lypinator 0:bb348c97df44 3342 #define GPIO_AFRL_AFSEL7_3 (0x8U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */
lypinator 0:bb348c97df44 3343
lypinator 0:bb348c97df44 3344 /* Legacy defines */
lypinator 0:bb348c97df44 3345 #define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
lypinator 0:bb348c97df44 3346 #define GPIO_AFRL_AFRL0_0 GPIO_AFRL_AFSEL0_0
lypinator 0:bb348c97df44 3347 #define GPIO_AFRL_AFRL0_1 GPIO_AFRL_AFSEL0_1
lypinator 0:bb348c97df44 3348 #define GPIO_AFRL_AFRL0_2 GPIO_AFRL_AFSEL0_2
lypinator 0:bb348c97df44 3349 #define GPIO_AFRL_AFRL0_3 GPIO_AFRL_AFSEL0_3
lypinator 0:bb348c97df44 3350 #define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
lypinator 0:bb348c97df44 3351 #define GPIO_AFRL_AFRL1_0 GPIO_AFRL_AFSEL1_0
lypinator 0:bb348c97df44 3352 #define GPIO_AFRL_AFRL1_1 GPIO_AFRL_AFSEL1_1
lypinator 0:bb348c97df44 3353 #define GPIO_AFRL_AFRL1_2 GPIO_AFRL_AFSEL1_2
lypinator 0:bb348c97df44 3354 #define GPIO_AFRL_AFRL1_3 GPIO_AFRL_AFSEL1_3
lypinator 0:bb348c97df44 3355 #define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
lypinator 0:bb348c97df44 3356 #define GPIO_AFRL_AFRL2_0 GPIO_AFRL_AFSEL2_0
lypinator 0:bb348c97df44 3357 #define GPIO_AFRL_AFRL2_1 GPIO_AFRL_AFSEL2_1
lypinator 0:bb348c97df44 3358 #define GPIO_AFRL_AFRL2_2 GPIO_AFRL_AFSEL2_2
lypinator 0:bb348c97df44 3359 #define GPIO_AFRL_AFRL2_3 GPIO_AFRL_AFSEL2_3
lypinator 0:bb348c97df44 3360 #define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
lypinator 0:bb348c97df44 3361 #define GPIO_AFRL_AFRL3_0 GPIO_AFRL_AFSEL3_0
lypinator 0:bb348c97df44 3362 #define GPIO_AFRL_AFRL3_1 GPIO_AFRL_AFSEL3_1
lypinator 0:bb348c97df44 3363 #define GPIO_AFRL_AFRL3_2 GPIO_AFRL_AFSEL3_2
lypinator 0:bb348c97df44 3364 #define GPIO_AFRL_AFRL3_3 GPIO_AFRL_AFSEL3_3
lypinator 0:bb348c97df44 3365 #define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
lypinator 0:bb348c97df44 3366 #define GPIO_AFRL_AFRL4_0 GPIO_AFRL_AFSEL4_0
lypinator 0:bb348c97df44 3367 #define GPIO_AFRL_AFRL4_1 GPIO_AFRL_AFSEL4_1
lypinator 0:bb348c97df44 3368 #define GPIO_AFRL_AFRL4_2 GPIO_AFRL_AFSEL4_2
lypinator 0:bb348c97df44 3369 #define GPIO_AFRL_AFRL4_3 GPIO_AFRL_AFSEL4_3
lypinator 0:bb348c97df44 3370 #define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
lypinator 0:bb348c97df44 3371 #define GPIO_AFRL_AFRL5_0 GPIO_AFRL_AFSEL5_0
lypinator 0:bb348c97df44 3372 #define GPIO_AFRL_AFRL5_1 GPIO_AFRL_AFSEL5_1
lypinator 0:bb348c97df44 3373 #define GPIO_AFRL_AFRL5_2 GPIO_AFRL_AFSEL5_2
lypinator 0:bb348c97df44 3374 #define GPIO_AFRL_AFRL5_3 GPIO_AFRL_AFSEL5_3
lypinator 0:bb348c97df44 3375 #define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
lypinator 0:bb348c97df44 3376 #define GPIO_AFRL_AFRL6_0 GPIO_AFRL_AFSEL6_0
lypinator 0:bb348c97df44 3377 #define GPIO_AFRL_AFRL6_1 GPIO_AFRL_AFSEL6_1
lypinator 0:bb348c97df44 3378 #define GPIO_AFRL_AFRL6_2 GPIO_AFRL_AFSEL6_2
lypinator 0:bb348c97df44 3379 #define GPIO_AFRL_AFRL6_3 GPIO_AFRL_AFSEL6_3
lypinator 0:bb348c97df44 3380 #define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
lypinator 0:bb348c97df44 3381 #define GPIO_AFRL_AFRL7_0 GPIO_AFRL_AFSEL7_0
lypinator 0:bb348c97df44 3382 #define GPIO_AFRL_AFRL7_1 GPIO_AFRL_AFSEL7_1
lypinator 0:bb348c97df44 3383 #define GPIO_AFRL_AFRL7_2 GPIO_AFRL_AFSEL7_2
lypinator 0:bb348c97df44 3384 #define GPIO_AFRL_AFRL7_3 GPIO_AFRL_AFSEL7_3
lypinator 0:bb348c97df44 3385
lypinator 0:bb348c97df44 3386 /****************** Bit definition for GPIO_AFRH register *********************/
lypinator 0:bb348c97df44 3387 #define GPIO_AFRH_AFSEL8_Pos (0U)
lypinator 0:bb348c97df44 3388 #define GPIO_AFRH_AFSEL8_Msk (0xFU << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
lypinator 0:bb348c97df44 3389 #define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
lypinator 0:bb348c97df44 3390 #define GPIO_AFRH_AFSEL8_0 (0x1U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 3391 #define GPIO_AFRH_AFSEL8_1 (0x2U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 3392 #define GPIO_AFRH_AFSEL8_2 (0x4U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 3393 #define GPIO_AFRH_AFSEL8_3 (0x8U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 3394 #define GPIO_AFRH_AFSEL9_Pos (4U)
lypinator 0:bb348c97df44 3395 #define GPIO_AFRH_AFSEL9_Msk (0xFU << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
lypinator 0:bb348c97df44 3396 #define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
lypinator 0:bb348c97df44 3397 #define GPIO_AFRH_AFSEL9_0 (0x1U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 3398 #define GPIO_AFRH_AFSEL9_1 (0x2U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 3399 #define GPIO_AFRH_AFSEL9_2 (0x4U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 3400 #define GPIO_AFRH_AFSEL9_3 (0x8U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 3401 #define GPIO_AFRH_AFSEL10_Pos (8U)
lypinator 0:bb348c97df44 3402 #define GPIO_AFRH_AFSEL10_Msk (0xFU << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
lypinator 0:bb348c97df44 3403 #define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
lypinator 0:bb348c97df44 3404 #define GPIO_AFRH_AFSEL10_0 (0x1U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 3405 #define GPIO_AFRH_AFSEL10_1 (0x2U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 3406 #define GPIO_AFRH_AFSEL10_2 (0x4U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 3407 #define GPIO_AFRH_AFSEL10_3 (0x8U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 3408 #define GPIO_AFRH_AFSEL11_Pos (12U)
lypinator 0:bb348c97df44 3409 #define GPIO_AFRH_AFSEL11_Msk (0xFU << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
lypinator 0:bb348c97df44 3410 #define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
lypinator 0:bb348c97df44 3411 #define GPIO_AFRH_AFSEL11_0 (0x1U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 3412 #define GPIO_AFRH_AFSEL11_1 (0x2U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 3413 #define GPIO_AFRH_AFSEL11_2 (0x4U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 3414 #define GPIO_AFRH_AFSEL11_3 (0x8U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 3415 #define GPIO_AFRH_AFSEL12_Pos (16U)
lypinator 0:bb348c97df44 3416 #define GPIO_AFRH_AFSEL12_Msk (0xFU << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
lypinator 0:bb348c97df44 3417 #define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
lypinator 0:bb348c97df44 3418 #define GPIO_AFRH_AFSEL12_0 (0x1U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 3419 #define GPIO_AFRH_AFSEL12_1 (0x2U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 3420 #define GPIO_AFRH_AFSEL12_2 (0x4U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 3421 #define GPIO_AFRH_AFSEL12_3 (0x8U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 3422 #define GPIO_AFRH_AFSEL13_Pos (20U)
lypinator 0:bb348c97df44 3423 #define GPIO_AFRH_AFSEL13_Msk (0xFU << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
lypinator 0:bb348c97df44 3424 #define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
lypinator 0:bb348c97df44 3425 #define GPIO_AFRH_AFSEL13_0 (0x1U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 3426 #define GPIO_AFRH_AFSEL13_1 (0x2U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 3427 #define GPIO_AFRH_AFSEL13_2 (0x4U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 3428 #define GPIO_AFRH_AFSEL13_3 (0x8U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */
lypinator 0:bb348c97df44 3429 #define GPIO_AFRH_AFSEL14_Pos (24U)
lypinator 0:bb348c97df44 3430 #define GPIO_AFRH_AFSEL14_Msk (0xFU << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
lypinator 0:bb348c97df44 3431 #define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
lypinator 0:bb348c97df44 3432 #define GPIO_AFRH_AFSEL14_0 (0x1U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 3433 #define GPIO_AFRH_AFSEL14_1 (0x2U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 3434 #define GPIO_AFRH_AFSEL14_2 (0x4U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */
lypinator 0:bb348c97df44 3435 #define GPIO_AFRH_AFSEL14_3 (0x8U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */
lypinator 0:bb348c97df44 3436 #define GPIO_AFRH_AFSEL15_Pos (28U)
lypinator 0:bb348c97df44 3437 #define GPIO_AFRH_AFSEL15_Msk (0xFU << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
lypinator 0:bb348c97df44 3438 #define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
lypinator 0:bb348c97df44 3439 #define GPIO_AFRH_AFSEL15_0 (0x1U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */
lypinator 0:bb348c97df44 3440 #define GPIO_AFRH_AFSEL15_1 (0x2U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */
lypinator 0:bb348c97df44 3441 #define GPIO_AFRH_AFSEL15_2 (0x4U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */
lypinator 0:bb348c97df44 3442 #define GPIO_AFRH_AFSEL15_3 (0x8U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */
lypinator 0:bb348c97df44 3443
lypinator 0:bb348c97df44 3444 /* Legacy defines */
lypinator 0:bb348c97df44 3445 #define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
lypinator 0:bb348c97df44 3446 #define GPIO_AFRH_AFRH0_0 GPIO_AFRH_AFSEL8_0
lypinator 0:bb348c97df44 3447 #define GPIO_AFRH_AFRH0_1 GPIO_AFRH_AFSEL8_1
lypinator 0:bb348c97df44 3448 #define GPIO_AFRH_AFRH0_2 GPIO_AFRH_AFSEL8_2
lypinator 0:bb348c97df44 3449 #define GPIO_AFRH_AFRH0_3 GPIO_AFRH_AFSEL8_3
lypinator 0:bb348c97df44 3450 #define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
lypinator 0:bb348c97df44 3451 #define GPIO_AFRH_AFRH1_0 GPIO_AFRH_AFSEL9_0
lypinator 0:bb348c97df44 3452 #define GPIO_AFRH_AFRH1_1 GPIO_AFRH_AFSEL9_1
lypinator 0:bb348c97df44 3453 #define GPIO_AFRH_AFRH1_2 GPIO_AFRH_AFSEL9_2
lypinator 0:bb348c97df44 3454 #define GPIO_AFRH_AFRH1_3 GPIO_AFRH_AFSEL9_3
lypinator 0:bb348c97df44 3455 #define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
lypinator 0:bb348c97df44 3456 #define GPIO_AFRH_AFRH2_0 GPIO_AFRH_AFSEL10_0
lypinator 0:bb348c97df44 3457 #define GPIO_AFRH_AFRH2_1 GPIO_AFRH_AFSEL10_1
lypinator 0:bb348c97df44 3458 #define GPIO_AFRH_AFRH2_2 GPIO_AFRH_AFSEL10_2
lypinator 0:bb348c97df44 3459 #define GPIO_AFRH_AFRH2_3 GPIO_AFRH_AFSEL10_3
lypinator 0:bb348c97df44 3460 #define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
lypinator 0:bb348c97df44 3461 #define GPIO_AFRH_AFRH3_0 GPIO_AFRH_AFSEL11_0
lypinator 0:bb348c97df44 3462 #define GPIO_AFRH_AFRH3_1 GPIO_AFRH_AFSEL11_1
lypinator 0:bb348c97df44 3463 #define GPIO_AFRH_AFRH3_2 GPIO_AFRH_AFSEL11_2
lypinator 0:bb348c97df44 3464 #define GPIO_AFRH_AFRH3_3 GPIO_AFRH_AFSEL11_3
lypinator 0:bb348c97df44 3465 #define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
lypinator 0:bb348c97df44 3466 #define GPIO_AFRH_AFRH4_0 GPIO_AFRH_AFSEL12_0
lypinator 0:bb348c97df44 3467 #define GPIO_AFRH_AFRH4_1 GPIO_AFRH_AFSEL12_1
lypinator 0:bb348c97df44 3468 #define GPIO_AFRH_AFRH4_2 GPIO_AFRH_AFSEL12_2
lypinator 0:bb348c97df44 3469 #define GPIO_AFRH_AFRH4_3 GPIO_AFRH_AFSEL12_3
lypinator 0:bb348c97df44 3470 #define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
lypinator 0:bb348c97df44 3471 #define GPIO_AFRH_AFRH5_0 GPIO_AFRH_AFSEL13_0
lypinator 0:bb348c97df44 3472 #define GPIO_AFRH_AFRH5_1 GPIO_AFRH_AFSEL13_1
lypinator 0:bb348c97df44 3473 #define GPIO_AFRH_AFRH5_2 GPIO_AFRH_AFSEL13_2
lypinator 0:bb348c97df44 3474 #define GPIO_AFRH_AFRH5_3 GPIO_AFRH_AFSEL13_3
lypinator 0:bb348c97df44 3475 #define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
lypinator 0:bb348c97df44 3476 #define GPIO_AFRH_AFRH6_0 GPIO_AFRH_AFSEL14_0
lypinator 0:bb348c97df44 3477 #define GPIO_AFRH_AFRH6_1 GPIO_AFRH_AFSEL14_1
lypinator 0:bb348c97df44 3478 #define GPIO_AFRH_AFRH6_2 GPIO_AFRH_AFSEL14_2
lypinator 0:bb348c97df44 3479 #define GPIO_AFRH_AFRH6_3 GPIO_AFRH_AFSEL14_3
lypinator 0:bb348c97df44 3480 #define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
lypinator 0:bb348c97df44 3481 #define GPIO_AFRH_AFRH7_0 GPIO_AFRH_AFSEL15_0
lypinator 0:bb348c97df44 3482 #define GPIO_AFRH_AFRH7_1 GPIO_AFRH_AFSEL15_1
lypinator 0:bb348c97df44 3483 #define GPIO_AFRH_AFRH7_2 GPIO_AFRH_AFSEL15_2
lypinator 0:bb348c97df44 3484 #define GPIO_AFRH_AFRH7_3 GPIO_AFRH_AFSEL15_3
lypinator 0:bb348c97df44 3485
lypinator 0:bb348c97df44 3486 /****************** Bits definition for GPIO_BRR register ******************/
lypinator 0:bb348c97df44 3487 #define GPIO_BRR_BR0_Pos (0U)
lypinator 0:bb348c97df44 3488 #define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 3489 #define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk
lypinator 0:bb348c97df44 3490 #define GPIO_BRR_BR1_Pos (1U)
lypinator 0:bb348c97df44 3491 #define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 3492 #define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk
lypinator 0:bb348c97df44 3493 #define GPIO_BRR_BR2_Pos (2U)
lypinator 0:bb348c97df44 3494 #define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 3495 #define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk
lypinator 0:bb348c97df44 3496 #define GPIO_BRR_BR3_Pos (3U)
lypinator 0:bb348c97df44 3497 #define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 3498 #define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk
lypinator 0:bb348c97df44 3499 #define GPIO_BRR_BR4_Pos (4U)
lypinator 0:bb348c97df44 3500 #define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 3501 #define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk
lypinator 0:bb348c97df44 3502 #define GPIO_BRR_BR5_Pos (5U)
lypinator 0:bb348c97df44 3503 #define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 3504 #define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk
lypinator 0:bb348c97df44 3505 #define GPIO_BRR_BR6_Pos (6U)
lypinator 0:bb348c97df44 3506 #define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 3507 #define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk
lypinator 0:bb348c97df44 3508 #define GPIO_BRR_BR7_Pos (7U)
lypinator 0:bb348c97df44 3509 #define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 3510 #define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk
lypinator 0:bb348c97df44 3511 #define GPIO_BRR_BR8_Pos (8U)
lypinator 0:bb348c97df44 3512 #define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 3513 #define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk
lypinator 0:bb348c97df44 3514 #define GPIO_BRR_BR9_Pos (9U)
lypinator 0:bb348c97df44 3515 #define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 3516 #define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk
lypinator 0:bb348c97df44 3517 #define GPIO_BRR_BR10_Pos (10U)
lypinator 0:bb348c97df44 3518 #define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 3519 #define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk
lypinator 0:bb348c97df44 3520 #define GPIO_BRR_BR11_Pos (11U)
lypinator 0:bb348c97df44 3521 #define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 3522 #define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk
lypinator 0:bb348c97df44 3523 #define GPIO_BRR_BR12_Pos (12U)
lypinator 0:bb348c97df44 3524 #define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 3525 #define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk
lypinator 0:bb348c97df44 3526 #define GPIO_BRR_BR13_Pos (13U)
lypinator 0:bb348c97df44 3527 #define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 3528 #define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk
lypinator 0:bb348c97df44 3529 #define GPIO_BRR_BR14_Pos (14U)
lypinator 0:bb348c97df44 3530 #define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 3531 #define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk
lypinator 0:bb348c97df44 3532 #define GPIO_BRR_BR15_Pos (15U)
lypinator 0:bb348c97df44 3533 #define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 3534 #define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk
lypinator 0:bb348c97df44 3535
lypinator 0:bb348c97df44 3536
lypinator 0:bb348c97df44 3537 /******************************************************************************/
lypinator 0:bb348c97df44 3538 /* */
lypinator 0:bb348c97df44 3539 /* Inter-integrated Circuit Interface */
lypinator 0:bb348c97df44 3540 /* */
lypinator 0:bb348c97df44 3541 /******************************************************************************/
lypinator 0:bb348c97df44 3542 /******************* Bit definition for I2C_CR1 register ********************/
lypinator 0:bb348c97df44 3543 #define I2C_CR1_PE_Pos (0U)
lypinator 0:bb348c97df44 3544 #define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 3545 #define I2C_CR1_PE I2C_CR1_PE_Msk /*!<Peripheral Enable */
lypinator 0:bb348c97df44 3546 #define I2C_CR1_SMBUS_Pos (1U)
lypinator 0:bb348c97df44 3547 #define I2C_CR1_SMBUS_Msk (0x1U << I2C_CR1_SMBUS_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 3548 #define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk /*!<SMBus Mode */
lypinator 0:bb348c97df44 3549 #define I2C_CR1_SMBTYPE_Pos (3U)
lypinator 0:bb348c97df44 3550 #define I2C_CR1_SMBTYPE_Msk (0x1U << I2C_CR1_SMBTYPE_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 3551 #define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk /*!<SMBus Type */
lypinator 0:bb348c97df44 3552 #define I2C_CR1_ENARP_Pos (4U)
lypinator 0:bb348c97df44 3553 #define I2C_CR1_ENARP_Msk (0x1U << I2C_CR1_ENARP_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 3554 #define I2C_CR1_ENARP I2C_CR1_ENARP_Msk /*!<ARP Enable */
lypinator 0:bb348c97df44 3555 #define I2C_CR1_ENPEC_Pos (5U)
lypinator 0:bb348c97df44 3556 #define I2C_CR1_ENPEC_Msk (0x1U << I2C_CR1_ENPEC_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 3557 #define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk /*!<PEC Enable */
lypinator 0:bb348c97df44 3558 #define I2C_CR1_ENGC_Pos (6U)
lypinator 0:bb348c97df44 3559 #define I2C_CR1_ENGC_Msk (0x1U << I2C_CR1_ENGC_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 3560 #define I2C_CR1_ENGC I2C_CR1_ENGC_Msk /*!<General Call Enable */
lypinator 0:bb348c97df44 3561 #define I2C_CR1_NOSTRETCH_Pos (7U)
lypinator 0:bb348c97df44 3562 #define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 3563 #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!<Clock Stretching Disable (Slave mode) */
lypinator 0:bb348c97df44 3564 #define I2C_CR1_START_Pos (8U)
lypinator 0:bb348c97df44 3565 #define I2C_CR1_START_Msk (0x1U << I2C_CR1_START_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 3566 #define I2C_CR1_START I2C_CR1_START_Msk /*!<Start Generation */
lypinator 0:bb348c97df44 3567 #define I2C_CR1_STOP_Pos (9U)
lypinator 0:bb348c97df44 3568 #define I2C_CR1_STOP_Msk (0x1U << I2C_CR1_STOP_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 3569 #define I2C_CR1_STOP I2C_CR1_STOP_Msk /*!<Stop Generation */
lypinator 0:bb348c97df44 3570 #define I2C_CR1_ACK_Pos (10U)
lypinator 0:bb348c97df44 3571 #define I2C_CR1_ACK_Msk (0x1U << I2C_CR1_ACK_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 3572 #define I2C_CR1_ACK I2C_CR1_ACK_Msk /*!<Acknowledge Enable */
lypinator 0:bb348c97df44 3573 #define I2C_CR1_POS_Pos (11U)
lypinator 0:bb348c97df44 3574 #define I2C_CR1_POS_Msk (0x1U << I2C_CR1_POS_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 3575 #define I2C_CR1_POS I2C_CR1_POS_Msk /*!<Acknowledge/PEC Position (for data reception) */
lypinator 0:bb348c97df44 3576 #define I2C_CR1_PEC_Pos (12U)
lypinator 0:bb348c97df44 3577 #define I2C_CR1_PEC_Msk (0x1U << I2C_CR1_PEC_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 3578 #define I2C_CR1_PEC I2C_CR1_PEC_Msk /*!<Packet Error Checking */
lypinator 0:bb348c97df44 3579 #define I2C_CR1_ALERT_Pos (13U)
lypinator 0:bb348c97df44 3580 #define I2C_CR1_ALERT_Msk (0x1U << I2C_CR1_ALERT_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 3581 #define I2C_CR1_ALERT I2C_CR1_ALERT_Msk /*!<SMBus Alert */
lypinator 0:bb348c97df44 3582 #define I2C_CR1_SWRST_Pos (15U)
lypinator 0:bb348c97df44 3583 #define I2C_CR1_SWRST_Msk (0x1U << I2C_CR1_SWRST_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 3584 #define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!<Software Reset */
lypinator 0:bb348c97df44 3585
lypinator 0:bb348c97df44 3586 /******************* Bit definition for I2C_CR2 register ********************/
lypinator 0:bb348c97df44 3587 #define I2C_CR2_FREQ_Pos (0U)
lypinator 0:bb348c97df44 3588 #define I2C_CR2_FREQ_Msk (0x3FU << I2C_CR2_FREQ_Pos) /*!< 0x0000003F */
lypinator 0:bb348c97df44 3589 #define I2C_CR2_FREQ I2C_CR2_FREQ_Msk /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
lypinator 0:bb348c97df44 3590 #define I2C_CR2_FREQ_0 (0x01U << I2C_CR2_FREQ_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 3591 #define I2C_CR2_FREQ_1 (0x02U << I2C_CR2_FREQ_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 3592 #define I2C_CR2_FREQ_2 (0x04U << I2C_CR2_FREQ_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 3593 #define I2C_CR2_FREQ_3 (0x08U << I2C_CR2_FREQ_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 3594 #define I2C_CR2_FREQ_4 (0x10U << I2C_CR2_FREQ_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 3595 #define I2C_CR2_FREQ_5 (0x20U << I2C_CR2_FREQ_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 3596
lypinator 0:bb348c97df44 3597 #define I2C_CR2_ITERREN_Pos (8U)
lypinator 0:bb348c97df44 3598 #define I2C_CR2_ITERREN_Msk (0x1U << I2C_CR2_ITERREN_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 3599 #define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk /*!<Error Interrupt Enable */
lypinator 0:bb348c97df44 3600 #define I2C_CR2_ITEVTEN_Pos (9U)
lypinator 0:bb348c97df44 3601 #define I2C_CR2_ITEVTEN_Msk (0x1U << I2C_CR2_ITEVTEN_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 3602 #define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk /*!<Event Interrupt Enable */
lypinator 0:bb348c97df44 3603 #define I2C_CR2_ITBUFEN_Pos (10U)
lypinator 0:bb348c97df44 3604 #define I2C_CR2_ITBUFEN_Msk (0x1U << I2C_CR2_ITBUFEN_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 3605 #define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk /*!<Buffer Interrupt Enable */
lypinator 0:bb348c97df44 3606 #define I2C_CR2_DMAEN_Pos (11U)
lypinator 0:bb348c97df44 3607 #define I2C_CR2_DMAEN_Msk (0x1U << I2C_CR2_DMAEN_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 3608 #define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk /*!<DMA Requests Enable */
lypinator 0:bb348c97df44 3609 #define I2C_CR2_LAST_Pos (12U)
lypinator 0:bb348c97df44 3610 #define I2C_CR2_LAST_Msk (0x1U << I2C_CR2_LAST_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 3611 #define I2C_CR2_LAST I2C_CR2_LAST_Msk /*!<DMA Last Transfer */
lypinator 0:bb348c97df44 3612
lypinator 0:bb348c97df44 3613 /******************* Bit definition for I2C_OAR1 register *******************/
lypinator 0:bb348c97df44 3614 #define I2C_OAR1_ADD1_7 0x000000FEU /*!<Interface Address */
lypinator 0:bb348c97df44 3615 #define I2C_OAR1_ADD8_9 0x00000300U /*!<Interface Address */
lypinator 0:bb348c97df44 3616
lypinator 0:bb348c97df44 3617 #define I2C_OAR1_ADD0_Pos (0U)
lypinator 0:bb348c97df44 3618 #define I2C_OAR1_ADD0_Msk (0x1U << I2C_OAR1_ADD0_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 3619 #define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk /*!<Bit 0 */
lypinator 0:bb348c97df44 3620 #define I2C_OAR1_ADD1_Pos (1U)
lypinator 0:bb348c97df44 3621 #define I2C_OAR1_ADD1_Msk (0x1U << I2C_OAR1_ADD1_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 3622 #define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk /*!<Bit 1 */
lypinator 0:bb348c97df44 3623 #define I2C_OAR1_ADD2_Pos (2U)
lypinator 0:bb348c97df44 3624 #define I2C_OAR1_ADD2_Msk (0x1U << I2C_OAR1_ADD2_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 3625 #define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk /*!<Bit 2 */
lypinator 0:bb348c97df44 3626 #define I2C_OAR1_ADD3_Pos (3U)
lypinator 0:bb348c97df44 3627 #define I2C_OAR1_ADD3_Msk (0x1U << I2C_OAR1_ADD3_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 3628 #define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk /*!<Bit 3 */
lypinator 0:bb348c97df44 3629 #define I2C_OAR1_ADD4_Pos (4U)
lypinator 0:bb348c97df44 3630 #define I2C_OAR1_ADD4_Msk (0x1U << I2C_OAR1_ADD4_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 3631 #define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk /*!<Bit 4 */
lypinator 0:bb348c97df44 3632 #define I2C_OAR1_ADD5_Pos (5U)
lypinator 0:bb348c97df44 3633 #define I2C_OAR1_ADD5_Msk (0x1U << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 3634 #define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk /*!<Bit 5 */
lypinator 0:bb348c97df44 3635 #define I2C_OAR1_ADD6_Pos (6U)
lypinator 0:bb348c97df44 3636 #define I2C_OAR1_ADD6_Msk (0x1U << I2C_OAR1_ADD6_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 3637 #define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk /*!<Bit 6 */
lypinator 0:bb348c97df44 3638 #define I2C_OAR1_ADD7_Pos (7U)
lypinator 0:bb348c97df44 3639 #define I2C_OAR1_ADD7_Msk (0x1U << I2C_OAR1_ADD7_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 3640 #define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk /*!<Bit 7 */
lypinator 0:bb348c97df44 3641 #define I2C_OAR1_ADD8_Pos (8U)
lypinator 0:bb348c97df44 3642 #define I2C_OAR1_ADD8_Msk (0x1U << I2C_OAR1_ADD8_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 3643 #define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk /*!<Bit 8 */
lypinator 0:bb348c97df44 3644 #define I2C_OAR1_ADD9_Pos (9U)
lypinator 0:bb348c97df44 3645 #define I2C_OAR1_ADD9_Msk (0x1U << I2C_OAR1_ADD9_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 3646 #define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk /*!<Bit 9 */
lypinator 0:bb348c97df44 3647
lypinator 0:bb348c97df44 3648 #define I2C_OAR1_ADDMODE_Pos (15U)
lypinator 0:bb348c97df44 3649 #define I2C_OAR1_ADDMODE_Msk (0x1U << I2C_OAR1_ADDMODE_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 3650 #define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk /*!<Addressing Mode (Slave mode) */
lypinator 0:bb348c97df44 3651
lypinator 0:bb348c97df44 3652 /******************* Bit definition for I2C_OAR2 register *******************/
lypinator 0:bb348c97df44 3653 #define I2C_OAR2_ENDUAL_Pos (0U)
lypinator 0:bb348c97df44 3654 #define I2C_OAR2_ENDUAL_Msk (0x1U << I2C_OAR2_ENDUAL_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 3655 #define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk /*!<Dual addressing mode enable */
lypinator 0:bb348c97df44 3656 #define I2C_OAR2_ADD2_Pos (1U)
lypinator 0:bb348c97df44 3657 #define I2C_OAR2_ADD2_Msk (0x7FU << I2C_OAR2_ADD2_Pos) /*!< 0x000000FE */
lypinator 0:bb348c97df44 3658 #define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk /*!<Interface address */
lypinator 0:bb348c97df44 3659
lypinator 0:bb348c97df44 3660 /******************** Bit definition for I2C_DR register ********************/
lypinator 0:bb348c97df44 3661 #define I2C_DR_DR_Pos (0U)
lypinator 0:bb348c97df44 3662 #define I2C_DR_DR_Msk (0xFFU << I2C_DR_DR_Pos) /*!< 0x000000FF */
lypinator 0:bb348c97df44 3663 #define I2C_DR_DR I2C_DR_DR_Msk /*!<8-bit Data Register */
lypinator 0:bb348c97df44 3664
lypinator 0:bb348c97df44 3665 /******************* Bit definition for I2C_SR1 register ********************/
lypinator 0:bb348c97df44 3666 #define I2C_SR1_SB_Pos (0U)
lypinator 0:bb348c97df44 3667 #define I2C_SR1_SB_Msk (0x1U << I2C_SR1_SB_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 3668 #define I2C_SR1_SB I2C_SR1_SB_Msk /*!<Start Bit (Master mode) */
lypinator 0:bb348c97df44 3669 #define I2C_SR1_ADDR_Pos (1U)
lypinator 0:bb348c97df44 3670 #define I2C_SR1_ADDR_Msk (0x1U << I2C_SR1_ADDR_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 3671 #define I2C_SR1_ADDR I2C_SR1_ADDR_Msk /*!<Address sent (master mode)/matched (slave mode) */
lypinator 0:bb348c97df44 3672 #define I2C_SR1_BTF_Pos (2U)
lypinator 0:bb348c97df44 3673 #define I2C_SR1_BTF_Msk (0x1U << I2C_SR1_BTF_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 3674 #define I2C_SR1_BTF I2C_SR1_BTF_Msk /*!<Byte Transfer Finished */
lypinator 0:bb348c97df44 3675 #define I2C_SR1_ADD10_Pos (3U)
lypinator 0:bb348c97df44 3676 #define I2C_SR1_ADD10_Msk (0x1U << I2C_SR1_ADD10_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 3677 #define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk /*!<10-bit header sent (Master mode) */
lypinator 0:bb348c97df44 3678 #define I2C_SR1_STOPF_Pos (4U)
lypinator 0:bb348c97df44 3679 #define I2C_SR1_STOPF_Msk (0x1U << I2C_SR1_STOPF_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 3680 #define I2C_SR1_STOPF I2C_SR1_STOPF_Msk /*!<Stop detection (Slave mode) */
lypinator 0:bb348c97df44 3681 #define I2C_SR1_RXNE_Pos (6U)
lypinator 0:bb348c97df44 3682 #define I2C_SR1_RXNE_Msk (0x1U << I2C_SR1_RXNE_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 3683 #define I2C_SR1_RXNE I2C_SR1_RXNE_Msk /*!<Data Register not Empty (receivers) */
lypinator 0:bb348c97df44 3684 #define I2C_SR1_TXE_Pos (7U)
lypinator 0:bb348c97df44 3685 #define I2C_SR1_TXE_Msk (0x1U << I2C_SR1_TXE_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 3686 #define I2C_SR1_TXE I2C_SR1_TXE_Msk /*!<Data Register Empty (transmitters) */
lypinator 0:bb348c97df44 3687 #define I2C_SR1_BERR_Pos (8U)
lypinator 0:bb348c97df44 3688 #define I2C_SR1_BERR_Msk (0x1U << I2C_SR1_BERR_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 3689 #define I2C_SR1_BERR I2C_SR1_BERR_Msk /*!<Bus Error */
lypinator 0:bb348c97df44 3690 #define I2C_SR1_ARLO_Pos (9U)
lypinator 0:bb348c97df44 3691 #define I2C_SR1_ARLO_Msk (0x1U << I2C_SR1_ARLO_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 3692 #define I2C_SR1_ARLO I2C_SR1_ARLO_Msk /*!<Arbitration Lost (master mode) */
lypinator 0:bb348c97df44 3693 #define I2C_SR1_AF_Pos (10U)
lypinator 0:bb348c97df44 3694 #define I2C_SR1_AF_Msk (0x1U << I2C_SR1_AF_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 3695 #define I2C_SR1_AF I2C_SR1_AF_Msk /*!<Acknowledge Failure */
lypinator 0:bb348c97df44 3696 #define I2C_SR1_OVR_Pos (11U)
lypinator 0:bb348c97df44 3697 #define I2C_SR1_OVR_Msk (0x1U << I2C_SR1_OVR_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 3698 #define I2C_SR1_OVR I2C_SR1_OVR_Msk /*!<Overrun/Underrun */
lypinator 0:bb348c97df44 3699 #define I2C_SR1_PECERR_Pos (12U)
lypinator 0:bb348c97df44 3700 #define I2C_SR1_PECERR_Msk (0x1U << I2C_SR1_PECERR_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 3701 #define I2C_SR1_PECERR I2C_SR1_PECERR_Msk /*!<PEC Error in reception */
lypinator 0:bb348c97df44 3702 #define I2C_SR1_TIMEOUT_Pos (14U)
lypinator 0:bb348c97df44 3703 #define I2C_SR1_TIMEOUT_Msk (0x1U << I2C_SR1_TIMEOUT_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 3704 #define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk /*!<Timeout or Tlow Error */
lypinator 0:bb348c97df44 3705 #define I2C_SR1_SMBALERT_Pos (15U)
lypinator 0:bb348c97df44 3706 #define I2C_SR1_SMBALERT_Msk (0x1U << I2C_SR1_SMBALERT_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 3707 #define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk /*!<SMBus Alert */
lypinator 0:bb348c97df44 3708
lypinator 0:bb348c97df44 3709 /******************* Bit definition for I2C_SR2 register ********************/
lypinator 0:bb348c97df44 3710 #define I2C_SR2_MSL_Pos (0U)
lypinator 0:bb348c97df44 3711 #define I2C_SR2_MSL_Msk (0x1U << I2C_SR2_MSL_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 3712 #define I2C_SR2_MSL I2C_SR2_MSL_Msk /*!<Master/Slave */
lypinator 0:bb348c97df44 3713 #define I2C_SR2_BUSY_Pos (1U)
lypinator 0:bb348c97df44 3714 #define I2C_SR2_BUSY_Msk (0x1U << I2C_SR2_BUSY_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 3715 #define I2C_SR2_BUSY I2C_SR2_BUSY_Msk /*!<Bus Busy */
lypinator 0:bb348c97df44 3716 #define I2C_SR2_TRA_Pos (2U)
lypinator 0:bb348c97df44 3717 #define I2C_SR2_TRA_Msk (0x1U << I2C_SR2_TRA_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 3718 #define I2C_SR2_TRA I2C_SR2_TRA_Msk /*!<Transmitter/Receiver */
lypinator 0:bb348c97df44 3719 #define I2C_SR2_GENCALL_Pos (4U)
lypinator 0:bb348c97df44 3720 #define I2C_SR2_GENCALL_Msk (0x1U << I2C_SR2_GENCALL_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 3721 #define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk /*!<General Call Address (Slave mode) */
lypinator 0:bb348c97df44 3722 #define I2C_SR2_SMBDEFAULT_Pos (5U)
lypinator 0:bb348c97df44 3723 #define I2C_SR2_SMBDEFAULT_Msk (0x1U << I2C_SR2_SMBDEFAULT_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 3724 #define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk /*!<SMBus Device Default Address (Slave mode) */
lypinator 0:bb348c97df44 3725 #define I2C_SR2_SMBHOST_Pos (6U)
lypinator 0:bb348c97df44 3726 #define I2C_SR2_SMBHOST_Msk (0x1U << I2C_SR2_SMBHOST_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 3727 #define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk /*!<SMBus Host Header (Slave mode) */
lypinator 0:bb348c97df44 3728 #define I2C_SR2_DUALF_Pos (7U)
lypinator 0:bb348c97df44 3729 #define I2C_SR2_DUALF_Msk (0x1U << I2C_SR2_DUALF_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 3730 #define I2C_SR2_DUALF I2C_SR2_DUALF_Msk /*!<Dual Flag (Slave mode) */
lypinator 0:bb348c97df44 3731 #define I2C_SR2_PEC_Pos (8U)
lypinator 0:bb348c97df44 3732 #define I2C_SR2_PEC_Msk (0xFFU << I2C_SR2_PEC_Pos) /*!< 0x0000FF00 */
lypinator 0:bb348c97df44 3733 #define I2C_SR2_PEC I2C_SR2_PEC_Msk /*!<Packet Error Checking Register */
lypinator 0:bb348c97df44 3734
lypinator 0:bb348c97df44 3735 /******************* Bit definition for I2C_CCR register ********************/
lypinator 0:bb348c97df44 3736 #define I2C_CCR_CCR_Pos (0U)
lypinator 0:bb348c97df44 3737 #define I2C_CCR_CCR_Msk (0xFFFU << I2C_CCR_CCR_Pos) /*!< 0x00000FFF */
lypinator 0:bb348c97df44 3738 #define I2C_CCR_CCR I2C_CCR_CCR_Msk /*!<Clock Control Register in Fast/Standard mode (Master mode) */
lypinator 0:bb348c97df44 3739 #define I2C_CCR_DUTY_Pos (14U)
lypinator 0:bb348c97df44 3740 #define I2C_CCR_DUTY_Msk (0x1U << I2C_CCR_DUTY_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 3741 #define I2C_CCR_DUTY I2C_CCR_DUTY_Msk /*!<Fast Mode Duty Cycle */
lypinator 0:bb348c97df44 3742 #define I2C_CCR_FS_Pos (15U)
lypinator 0:bb348c97df44 3743 #define I2C_CCR_FS_Msk (0x1U << I2C_CCR_FS_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 3744 #define I2C_CCR_FS I2C_CCR_FS_Msk /*!<I2C Master Mode Selection */
lypinator 0:bb348c97df44 3745
lypinator 0:bb348c97df44 3746 /****************** Bit definition for I2C_TRISE register *******************/
lypinator 0:bb348c97df44 3747 #define I2C_TRISE_TRISE_Pos (0U)
lypinator 0:bb348c97df44 3748 #define I2C_TRISE_TRISE_Msk (0x3FU << I2C_TRISE_TRISE_Pos) /*!< 0x0000003F */
lypinator 0:bb348c97df44 3749 #define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
lypinator 0:bb348c97df44 3750
lypinator 0:bb348c97df44 3751 /****************** Bit definition for I2C_FLTR register *******************/
lypinator 0:bb348c97df44 3752 #define I2C_FLTR_DNF_Pos (0U)
lypinator 0:bb348c97df44 3753 #define I2C_FLTR_DNF_Msk (0xFU << I2C_FLTR_DNF_Pos) /*!< 0x0000000F */
lypinator 0:bb348c97df44 3754 #define I2C_FLTR_DNF I2C_FLTR_DNF_Msk /*!<Digital Noise Filter */
lypinator 0:bb348c97df44 3755 #define I2C_FLTR_ANOFF_Pos (4U)
lypinator 0:bb348c97df44 3756 #define I2C_FLTR_ANOFF_Msk (0x1U << I2C_FLTR_ANOFF_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 3757 #define I2C_FLTR_ANOFF I2C_FLTR_ANOFF_Msk /*!<Analog Noise Filter OFF */
lypinator 0:bb348c97df44 3758
lypinator 0:bb348c97df44 3759 /******************************************************************************/
lypinator 0:bb348c97df44 3760 /* */
lypinator 0:bb348c97df44 3761 /* Independent WATCHDOG */
lypinator 0:bb348c97df44 3762 /* */
lypinator 0:bb348c97df44 3763 /******************************************************************************/
lypinator 0:bb348c97df44 3764 /******************* Bit definition for IWDG_KR register ********************/
lypinator 0:bb348c97df44 3765 #define IWDG_KR_KEY_Pos (0U)
lypinator 0:bb348c97df44 3766 #define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
lypinator 0:bb348c97df44 3767 #define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!<Key value (write only, read 0000h) */
lypinator 0:bb348c97df44 3768
lypinator 0:bb348c97df44 3769 /******************* Bit definition for IWDG_PR register ********************/
lypinator 0:bb348c97df44 3770 #define IWDG_PR_PR_Pos (0U)
lypinator 0:bb348c97df44 3771 #define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */
lypinator 0:bb348c97df44 3772 #define IWDG_PR_PR IWDG_PR_PR_Msk /*!<PR[2:0] (Prescaler divider) */
lypinator 0:bb348c97df44 3773 #define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x01 */
lypinator 0:bb348c97df44 3774 #define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x02 */
lypinator 0:bb348c97df44 3775 #define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x04 */
lypinator 0:bb348c97df44 3776
lypinator 0:bb348c97df44 3777 /******************* Bit definition for IWDG_RLR register *******************/
lypinator 0:bb348c97df44 3778 #define IWDG_RLR_RL_Pos (0U)
lypinator 0:bb348c97df44 3779 #define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
lypinator 0:bb348c97df44 3780 #define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!<Watchdog counter reload value */
lypinator 0:bb348c97df44 3781
lypinator 0:bb348c97df44 3782 /******************* Bit definition for IWDG_SR register ********************/
lypinator 0:bb348c97df44 3783 #define IWDG_SR_PVU_Pos (0U)
lypinator 0:bb348c97df44 3784 #define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 3785 #define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!<Watchdog prescaler value update */
lypinator 0:bb348c97df44 3786 #define IWDG_SR_RVU_Pos (1U)
lypinator 0:bb348c97df44 3787 #define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 3788 #define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!<Watchdog counter reload value update */
lypinator 0:bb348c97df44 3789
lypinator 0:bb348c97df44 3790
lypinator 0:bb348c97df44 3791
lypinator 0:bb348c97df44 3792 /******************************************************************************/
lypinator 0:bb348c97df44 3793 /* */
lypinator 0:bb348c97df44 3794 /* Power Control */
lypinator 0:bb348c97df44 3795 /* */
lypinator 0:bb348c97df44 3796 /******************************************************************************/
lypinator 0:bb348c97df44 3797 /******************** Bit definition for PWR_CR register ********************/
lypinator 0:bb348c97df44 3798 #define PWR_CR_LPDS_Pos (0U)
lypinator 0:bb348c97df44 3799 #define PWR_CR_LPDS_Msk (0x1U << PWR_CR_LPDS_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 3800 #define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-Power Deepsleep */
lypinator 0:bb348c97df44 3801 #define PWR_CR_PDDS_Pos (1U)
lypinator 0:bb348c97df44 3802 #define PWR_CR_PDDS_Msk (0x1U << PWR_CR_PDDS_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 3803 #define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */
lypinator 0:bb348c97df44 3804 #define PWR_CR_CWUF_Pos (2U)
lypinator 0:bb348c97df44 3805 #define PWR_CR_CWUF_Msk (0x1U << PWR_CR_CWUF_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 3806 #define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */
lypinator 0:bb348c97df44 3807 #define PWR_CR_CSBF_Pos (3U)
lypinator 0:bb348c97df44 3808 #define PWR_CR_CSBF_Msk (0x1U << PWR_CR_CSBF_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 3809 #define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */
lypinator 0:bb348c97df44 3810 #define PWR_CR_PVDE_Pos (4U)
lypinator 0:bb348c97df44 3811 #define PWR_CR_PVDE_Msk (0x1U << PWR_CR_PVDE_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 3812 #define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */
lypinator 0:bb348c97df44 3813
lypinator 0:bb348c97df44 3814 #define PWR_CR_PLS_Pos (5U)
lypinator 0:bb348c97df44 3815 #define PWR_CR_PLS_Msk (0x7U << PWR_CR_PLS_Pos) /*!< 0x000000E0 */
lypinator 0:bb348c97df44 3816 #define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */
lypinator 0:bb348c97df44 3817 #define PWR_CR_PLS_0 (0x1U << PWR_CR_PLS_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 3818 #define PWR_CR_PLS_1 (0x2U << PWR_CR_PLS_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 3819 #define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 3820
lypinator 0:bb348c97df44 3821 /*!< PVD level configuration */
lypinator 0:bb348c97df44 3822 #define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 0 */
lypinator 0:bb348c97df44 3823 #define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 1 */
lypinator 0:bb348c97df44 3824 #define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2 */
lypinator 0:bb348c97df44 3825 #define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 3 */
lypinator 0:bb348c97df44 3826 #define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 4 */
lypinator 0:bb348c97df44 3827 #define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 5 */
lypinator 0:bb348c97df44 3828 #define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 6 */
lypinator 0:bb348c97df44 3829 #define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 7 */
lypinator 0:bb348c97df44 3830 #define PWR_CR_DBP_Pos (8U)
lypinator 0:bb348c97df44 3831 #define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 3832 #define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */
lypinator 0:bb348c97df44 3833 #define PWR_CR_FPDS_Pos (9U)
lypinator 0:bb348c97df44 3834 #define PWR_CR_FPDS_Msk (0x1U << PWR_CR_FPDS_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 3835 #define PWR_CR_FPDS PWR_CR_FPDS_Msk /*!< Flash power down in Stop mode */
lypinator 0:bb348c97df44 3836 #define PWR_CR_LPLVDS_Pos (10U)
lypinator 0:bb348c97df44 3837 #define PWR_CR_LPLVDS_Msk (0x1U << PWR_CR_LPLVDS_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 3838 #define PWR_CR_LPLVDS PWR_CR_LPLVDS_Msk /*!< Low Power Regulator Low Voltage in Deep Sleep mode */
lypinator 0:bb348c97df44 3839 #define PWR_CR_MRLVDS_Pos (11U)
lypinator 0:bb348c97df44 3840 #define PWR_CR_MRLVDS_Msk (0x1U << PWR_CR_MRLVDS_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 3841 #define PWR_CR_MRLVDS PWR_CR_MRLVDS_Msk /*!< Main Regulator Low Voltage in Deep Sleep mode */
lypinator 0:bb348c97df44 3842 #define PWR_CR_ADCDC1_Pos (13U)
lypinator 0:bb348c97df44 3843 #define PWR_CR_ADCDC1_Msk (0x1U << PWR_CR_ADCDC1_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 3844 #define PWR_CR_ADCDC1 PWR_CR_ADCDC1_Msk /*!< Refer to AN4073 on how to use this bit */
lypinator 0:bb348c97df44 3845 #define PWR_CR_VOS_Pos (14U)
lypinator 0:bb348c97df44 3846 #define PWR_CR_VOS_Msk (0x3U << PWR_CR_VOS_Pos) /*!< 0x0000C000 */
lypinator 0:bb348c97df44 3847 #define PWR_CR_VOS PWR_CR_VOS_Msk /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
lypinator 0:bb348c97df44 3848 #define PWR_CR_VOS_0 0x00004000U /*!< Bit 0 */
lypinator 0:bb348c97df44 3849 #define PWR_CR_VOS_1 0x00008000U /*!< Bit 1 */
lypinator 0:bb348c97df44 3850 #define PWR_CR_FMSSR_Pos (20U)
lypinator 0:bb348c97df44 3851 #define PWR_CR_FMSSR_Msk (0x1U << PWR_CR_FMSSR_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 3852 #define PWR_CR_FMSSR PWR_CR_FMSSR_Msk /*!< Flash Memory Sleep System Run */
lypinator 0:bb348c97df44 3853 #define PWR_CR_FISSR_Pos (21U)
lypinator 0:bb348c97df44 3854 #define PWR_CR_FISSR_Msk (0x1U << PWR_CR_FISSR_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 3855 #define PWR_CR_FISSR PWR_CR_FISSR_Msk /*!< Flash Interface Stop while System Run */
lypinator 0:bb348c97df44 3856
lypinator 0:bb348c97df44 3857 /* Legacy define */
lypinator 0:bb348c97df44 3858 #define PWR_CR_PMODE PWR_CR_VOS
lypinator 0:bb348c97df44 3859
lypinator 0:bb348c97df44 3860 /******************* Bit definition for PWR_CSR register ********************/
lypinator 0:bb348c97df44 3861 #define PWR_CSR_WUF_Pos (0U)
lypinator 0:bb348c97df44 3862 #define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 3863 #define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */
lypinator 0:bb348c97df44 3864 #define PWR_CSR_SBF_Pos (1U)
lypinator 0:bb348c97df44 3865 #define PWR_CSR_SBF_Msk (0x1U << PWR_CSR_SBF_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 3866 #define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */
lypinator 0:bb348c97df44 3867 #define PWR_CSR_PVDO_Pos (2U)
lypinator 0:bb348c97df44 3868 #define PWR_CSR_PVDO_Msk (0x1U << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 3869 #define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */
lypinator 0:bb348c97df44 3870 #define PWR_CSR_BRR_Pos (3U)
lypinator 0:bb348c97df44 3871 #define PWR_CSR_BRR_Msk (0x1U << PWR_CSR_BRR_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 3872 #define PWR_CSR_BRR PWR_CSR_BRR_Msk /*!< Backup regulator ready */
lypinator 0:bb348c97df44 3873 #define PWR_CSR_EWUP_Pos (8U)
lypinator 0:bb348c97df44 3874 #define PWR_CSR_EWUP_Msk (0x1U << PWR_CSR_EWUP_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 3875 #define PWR_CSR_EWUP PWR_CSR_EWUP_Msk /*!< Enable WKUP pin */
lypinator 0:bb348c97df44 3876 #define PWR_CSR_BRE_Pos (9U)
lypinator 0:bb348c97df44 3877 #define PWR_CSR_BRE_Msk (0x1U << PWR_CSR_BRE_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 3878 #define PWR_CSR_BRE PWR_CSR_BRE_Msk /*!< Backup regulator enable */
lypinator 0:bb348c97df44 3879 #define PWR_CSR_VOSRDY_Pos (14U)
lypinator 0:bb348c97df44 3880 #define PWR_CSR_VOSRDY_Msk (0x1U << PWR_CSR_VOSRDY_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 3881 #define PWR_CSR_VOSRDY PWR_CSR_VOSRDY_Msk /*!< Regulator voltage scaling output selection ready */
lypinator 0:bb348c97df44 3882
lypinator 0:bb348c97df44 3883 /* Legacy define */
lypinator 0:bb348c97df44 3884 #define PWR_CSR_REGRDY PWR_CSR_VOSRDY
lypinator 0:bb348c97df44 3885
lypinator 0:bb348c97df44 3886 /******************************************************************************/
lypinator 0:bb348c97df44 3887 /* */
lypinator 0:bb348c97df44 3888 /* Reset and Clock Control */
lypinator 0:bb348c97df44 3889 /* */
lypinator 0:bb348c97df44 3890 /******************************************************************************/
lypinator 0:bb348c97df44 3891 /******************** Bit definition for RCC_CR register ********************/
lypinator 0:bb348c97df44 3892 #define RCC_CR_HSION_Pos (0U)
lypinator 0:bb348c97df44 3893 #define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 3894 #define RCC_CR_HSION RCC_CR_HSION_Msk
lypinator 0:bb348c97df44 3895 #define RCC_CR_HSIRDY_Pos (1U)
lypinator 0:bb348c97df44 3896 #define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 3897 #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk
lypinator 0:bb348c97df44 3898
lypinator 0:bb348c97df44 3899 #define RCC_CR_HSITRIM_Pos (3U)
lypinator 0:bb348c97df44 3900 #define RCC_CR_HSITRIM_Msk (0x1FU << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */
lypinator 0:bb348c97df44 3901 #define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk
lypinator 0:bb348c97df44 3902 #define RCC_CR_HSITRIM_0 (0x01U << RCC_CR_HSITRIM_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 3903 #define RCC_CR_HSITRIM_1 (0x02U << RCC_CR_HSITRIM_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 3904 #define RCC_CR_HSITRIM_2 (0x04U << RCC_CR_HSITRIM_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 3905 #define RCC_CR_HSITRIM_3 (0x08U << RCC_CR_HSITRIM_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 3906 #define RCC_CR_HSITRIM_4 (0x10U << RCC_CR_HSITRIM_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 3907
lypinator 0:bb348c97df44 3908 #define RCC_CR_HSICAL_Pos (8U)
lypinator 0:bb348c97df44 3909 #define RCC_CR_HSICAL_Msk (0xFFU << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */
lypinator 0:bb348c97df44 3910 #define RCC_CR_HSICAL RCC_CR_HSICAL_Msk
lypinator 0:bb348c97df44 3911 #define RCC_CR_HSICAL_0 (0x01U << RCC_CR_HSICAL_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 3912 #define RCC_CR_HSICAL_1 (0x02U << RCC_CR_HSICAL_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 3913 #define RCC_CR_HSICAL_2 (0x04U << RCC_CR_HSICAL_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 3914 #define RCC_CR_HSICAL_3 (0x08U << RCC_CR_HSICAL_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 3915 #define RCC_CR_HSICAL_4 (0x10U << RCC_CR_HSICAL_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 3916 #define RCC_CR_HSICAL_5 (0x20U << RCC_CR_HSICAL_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 3917 #define RCC_CR_HSICAL_6 (0x40U << RCC_CR_HSICAL_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 3918 #define RCC_CR_HSICAL_7 (0x80U << RCC_CR_HSICAL_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 3919
lypinator 0:bb348c97df44 3920 #define RCC_CR_HSEON_Pos (16U)
lypinator 0:bb348c97df44 3921 #define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 3922 #define RCC_CR_HSEON RCC_CR_HSEON_Msk
lypinator 0:bb348c97df44 3923 #define RCC_CR_HSERDY_Pos (17U)
lypinator 0:bb348c97df44 3924 #define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 3925 #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk
lypinator 0:bb348c97df44 3926 #define RCC_CR_HSEBYP_Pos (18U)
lypinator 0:bb348c97df44 3927 #define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 3928 #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk
lypinator 0:bb348c97df44 3929 #define RCC_CR_CSSON_Pos (19U)
lypinator 0:bb348c97df44 3930 #define RCC_CR_CSSON_Msk (0x1U << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 3931 #define RCC_CR_CSSON RCC_CR_CSSON_Msk
lypinator 0:bb348c97df44 3932 #define RCC_CR_PLLON_Pos (24U)
lypinator 0:bb348c97df44 3933 #define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 3934 #define RCC_CR_PLLON RCC_CR_PLLON_Msk
lypinator 0:bb348c97df44 3935 #define RCC_CR_PLLRDY_Pos (25U)
lypinator 0:bb348c97df44 3936 #define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 3937 #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk
lypinator 0:bb348c97df44 3938 /*
lypinator 0:bb348c97df44 3939 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
lypinator 0:bb348c97df44 3940 */
lypinator 0:bb348c97df44 3941 #define RCC_PLLI2S_SUPPORT /*!< Support PLLI2S oscillator */
lypinator 0:bb348c97df44 3942
lypinator 0:bb348c97df44 3943 #define RCC_CR_PLLI2SON_Pos (26U)
lypinator 0:bb348c97df44 3944 #define RCC_CR_PLLI2SON_Msk (0x1U << RCC_CR_PLLI2SON_Pos) /*!< 0x04000000 */
lypinator 0:bb348c97df44 3945 #define RCC_CR_PLLI2SON RCC_CR_PLLI2SON_Msk
lypinator 0:bb348c97df44 3946 #define RCC_CR_PLLI2SRDY_Pos (27U)
lypinator 0:bb348c97df44 3947 #define RCC_CR_PLLI2SRDY_Msk (0x1U << RCC_CR_PLLI2SRDY_Pos) /*!< 0x08000000 */
lypinator 0:bb348c97df44 3948 #define RCC_CR_PLLI2SRDY RCC_CR_PLLI2SRDY_Msk
lypinator 0:bb348c97df44 3949
lypinator 0:bb348c97df44 3950 /******************** Bit definition for RCC_PLLCFGR register ***************/
lypinator 0:bb348c97df44 3951 #define RCC_PLLCFGR_PLLM_Pos (0U)
lypinator 0:bb348c97df44 3952 #define RCC_PLLCFGR_PLLM_Msk (0x3FU << RCC_PLLCFGR_PLLM_Pos) /*!< 0x0000003F */
lypinator 0:bb348c97df44 3953 #define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk
lypinator 0:bb348c97df44 3954 #define RCC_PLLCFGR_PLLM_0 (0x01U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 3955 #define RCC_PLLCFGR_PLLM_1 (0x02U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 3956 #define RCC_PLLCFGR_PLLM_2 (0x04U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 3957 #define RCC_PLLCFGR_PLLM_3 (0x08U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 3958 #define RCC_PLLCFGR_PLLM_4 (0x10U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 3959 #define RCC_PLLCFGR_PLLM_5 (0x20U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 3960
lypinator 0:bb348c97df44 3961 #define RCC_PLLCFGR_PLLN_Pos (6U)
lypinator 0:bb348c97df44 3962 #define RCC_PLLCFGR_PLLN_Msk (0x1FFU << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00007FC0 */
lypinator 0:bb348c97df44 3963 #define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk
lypinator 0:bb348c97df44 3964 #define RCC_PLLCFGR_PLLN_0 (0x001U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 3965 #define RCC_PLLCFGR_PLLN_1 (0x002U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 3966 #define RCC_PLLCFGR_PLLN_2 (0x004U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 3967 #define RCC_PLLCFGR_PLLN_3 (0x008U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 3968 #define RCC_PLLCFGR_PLLN_4 (0x010U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 3969 #define RCC_PLLCFGR_PLLN_5 (0x020U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 3970 #define RCC_PLLCFGR_PLLN_6 (0x040U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 3971 #define RCC_PLLCFGR_PLLN_7 (0x080U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 3972 #define RCC_PLLCFGR_PLLN_8 (0x100U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 3973
lypinator 0:bb348c97df44 3974 #define RCC_PLLCFGR_PLLP_Pos (16U)
lypinator 0:bb348c97df44 3975 #define RCC_PLLCFGR_PLLP_Msk (0x3U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00030000 */
lypinator 0:bb348c97df44 3976 #define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk
lypinator 0:bb348c97df44 3977 #define RCC_PLLCFGR_PLLP_0 (0x1U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 3978 #define RCC_PLLCFGR_PLLP_1 (0x2U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 3979
lypinator 0:bb348c97df44 3980 #define RCC_PLLCFGR_PLLSRC_Pos (22U)
lypinator 0:bb348c97df44 3981 #define RCC_PLLCFGR_PLLSRC_Msk (0x1U << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 3982 #define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk
lypinator 0:bb348c97df44 3983 #define RCC_PLLCFGR_PLLSRC_HSE_Pos (22U)
lypinator 0:bb348c97df44 3984 #define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x1U << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 3985 #define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk
lypinator 0:bb348c97df44 3986 #define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
lypinator 0:bb348c97df44 3987
lypinator 0:bb348c97df44 3988 #define RCC_PLLCFGR_PLLQ_Pos (24U)
lypinator 0:bb348c97df44 3989 #define RCC_PLLCFGR_PLLQ_Msk (0xFU << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x0F000000 */
lypinator 0:bb348c97df44 3990 #define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk
lypinator 0:bb348c97df44 3991 #define RCC_PLLCFGR_PLLQ_0 (0x1U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 3992 #define RCC_PLLCFGR_PLLQ_1 (0x2U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 3993 #define RCC_PLLCFGR_PLLQ_2 (0x4U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x04000000 */
lypinator 0:bb348c97df44 3994 #define RCC_PLLCFGR_PLLQ_3 (0x8U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x08000000 */
lypinator 0:bb348c97df44 3995
lypinator 0:bb348c97df44 3996
lypinator 0:bb348c97df44 3997 /******************** Bit definition for RCC_CFGR register ******************/
lypinator 0:bb348c97df44 3998 /*!< SW configuration */
lypinator 0:bb348c97df44 3999 #define RCC_CFGR_SW_Pos (0U)
lypinator 0:bb348c97df44 4000 #define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
lypinator 0:bb348c97df44 4001 #define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
lypinator 0:bb348c97df44 4002 #define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 4003 #define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 4004
lypinator 0:bb348c97df44 4005 #define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */
lypinator 0:bb348c97df44 4006 #define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */
lypinator 0:bb348c97df44 4007 #define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */
lypinator 0:bb348c97df44 4008
lypinator 0:bb348c97df44 4009 /*!< SWS configuration */
lypinator 0:bb348c97df44 4010 #define RCC_CFGR_SWS_Pos (2U)
lypinator 0:bb348c97df44 4011 #define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
lypinator 0:bb348c97df44 4012 #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
lypinator 0:bb348c97df44 4013 #define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 4014 #define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 4015
lypinator 0:bb348c97df44 4016 #define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */
lypinator 0:bb348c97df44 4017 #define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */
lypinator 0:bb348c97df44 4018 #define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */
lypinator 0:bb348c97df44 4019
lypinator 0:bb348c97df44 4020 /*!< HPRE configuration */
lypinator 0:bb348c97df44 4021 #define RCC_CFGR_HPRE_Pos (4U)
lypinator 0:bb348c97df44 4022 #define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
lypinator 0:bb348c97df44 4023 #define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
lypinator 0:bb348c97df44 4024 #define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 4025 #define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 4026 #define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 4027 #define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 4028
lypinator 0:bb348c97df44 4029 #define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */
lypinator 0:bb348c97df44 4030 #define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */
lypinator 0:bb348c97df44 4031 #define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */
lypinator 0:bb348c97df44 4032 #define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */
lypinator 0:bb348c97df44 4033 #define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */
lypinator 0:bb348c97df44 4034 #define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */
lypinator 0:bb348c97df44 4035 #define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */
lypinator 0:bb348c97df44 4036 #define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */
lypinator 0:bb348c97df44 4037 #define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */
lypinator 0:bb348c97df44 4038
lypinator 0:bb348c97df44 4039 /*!< PPRE1 configuration */
lypinator 0:bb348c97df44 4040 #define RCC_CFGR_PPRE1_Pos (10U)
lypinator 0:bb348c97df44 4041 #define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /*!< 0x00001C00 */
lypinator 0:bb348c97df44 4042 #define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */
lypinator 0:bb348c97df44 4043 #define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 4044 #define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 4045 #define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 4046
lypinator 0:bb348c97df44 4047 #define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */
lypinator 0:bb348c97df44 4048 #define RCC_CFGR_PPRE1_DIV2 0x00001000U /*!< HCLK divided by 2 */
lypinator 0:bb348c97df44 4049 #define RCC_CFGR_PPRE1_DIV4 0x00001400U /*!< HCLK divided by 4 */
lypinator 0:bb348c97df44 4050 #define RCC_CFGR_PPRE1_DIV8 0x00001800U /*!< HCLK divided by 8 */
lypinator 0:bb348c97df44 4051 #define RCC_CFGR_PPRE1_DIV16 0x00001C00U /*!< HCLK divided by 16 */
lypinator 0:bb348c97df44 4052
lypinator 0:bb348c97df44 4053 /*!< PPRE2 configuration */
lypinator 0:bb348c97df44 4054 #define RCC_CFGR_PPRE2_Pos (13U)
lypinator 0:bb348c97df44 4055 #define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /*!< 0x0000E000 */
lypinator 0:bb348c97df44 4056 #define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
lypinator 0:bb348c97df44 4057 #define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 4058 #define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 4059 #define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 4060
lypinator 0:bb348c97df44 4061 #define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */
lypinator 0:bb348c97df44 4062 #define RCC_CFGR_PPRE2_DIV2 0x00008000U /*!< HCLK divided by 2 */
lypinator 0:bb348c97df44 4063 #define RCC_CFGR_PPRE2_DIV4 0x0000A000U /*!< HCLK divided by 4 */
lypinator 0:bb348c97df44 4064 #define RCC_CFGR_PPRE2_DIV8 0x0000C000U /*!< HCLK divided by 8 */
lypinator 0:bb348c97df44 4065 #define RCC_CFGR_PPRE2_DIV16 0x0000E000U /*!< HCLK divided by 16 */
lypinator 0:bb348c97df44 4066
lypinator 0:bb348c97df44 4067 /*!< RTCPRE configuration */
lypinator 0:bb348c97df44 4068 #define RCC_CFGR_RTCPRE_Pos (16U)
lypinator 0:bb348c97df44 4069 #define RCC_CFGR_RTCPRE_Msk (0x1FU << RCC_CFGR_RTCPRE_Pos) /*!< 0x001F0000 */
lypinator 0:bb348c97df44 4070 #define RCC_CFGR_RTCPRE RCC_CFGR_RTCPRE_Msk
lypinator 0:bb348c97df44 4071 #define RCC_CFGR_RTCPRE_0 (0x01U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 4072 #define RCC_CFGR_RTCPRE_1 (0x02U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 4073 #define RCC_CFGR_RTCPRE_2 (0x04U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 4074 #define RCC_CFGR_RTCPRE_3 (0x08U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 4075 #define RCC_CFGR_RTCPRE_4 (0x10U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 4076
lypinator 0:bb348c97df44 4077 /*!< MCO1 configuration */
lypinator 0:bb348c97df44 4078 #define RCC_CFGR_MCO1_Pos (21U)
lypinator 0:bb348c97df44 4079 #define RCC_CFGR_MCO1_Msk (0x3U << RCC_CFGR_MCO1_Pos) /*!< 0x00600000 */
lypinator 0:bb348c97df44 4080 #define RCC_CFGR_MCO1 RCC_CFGR_MCO1_Msk
lypinator 0:bb348c97df44 4081 #define RCC_CFGR_MCO1_0 (0x1U << RCC_CFGR_MCO1_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 4082 #define RCC_CFGR_MCO1_1 (0x2U << RCC_CFGR_MCO1_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 4083
lypinator 0:bb348c97df44 4084 #define RCC_CFGR_I2SSRC_Pos (23U)
lypinator 0:bb348c97df44 4085 #define RCC_CFGR_I2SSRC_Msk (0x1U << RCC_CFGR_I2SSRC_Pos) /*!< 0x00800000 */
lypinator 0:bb348c97df44 4086 #define RCC_CFGR_I2SSRC RCC_CFGR_I2SSRC_Msk
lypinator 0:bb348c97df44 4087
lypinator 0:bb348c97df44 4088 #define RCC_CFGR_MCO1PRE_Pos (24U)
lypinator 0:bb348c97df44 4089 #define RCC_CFGR_MCO1PRE_Msk (0x7U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x07000000 */
lypinator 0:bb348c97df44 4090 #define RCC_CFGR_MCO1PRE RCC_CFGR_MCO1PRE_Msk
lypinator 0:bb348c97df44 4091 #define RCC_CFGR_MCO1PRE_0 (0x1U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 4092 #define RCC_CFGR_MCO1PRE_1 (0x2U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 4093 #define RCC_CFGR_MCO1PRE_2 (0x4U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x04000000 */
lypinator 0:bb348c97df44 4094
lypinator 0:bb348c97df44 4095 #define RCC_CFGR_MCO2PRE_Pos (27U)
lypinator 0:bb348c97df44 4096 #define RCC_CFGR_MCO2PRE_Msk (0x7U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x38000000 */
lypinator 0:bb348c97df44 4097 #define RCC_CFGR_MCO2PRE RCC_CFGR_MCO2PRE_Msk
lypinator 0:bb348c97df44 4098 #define RCC_CFGR_MCO2PRE_0 (0x1U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x08000000 */
lypinator 0:bb348c97df44 4099 #define RCC_CFGR_MCO2PRE_1 (0x2U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x10000000 */
lypinator 0:bb348c97df44 4100 #define RCC_CFGR_MCO2PRE_2 (0x4U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x20000000 */
lypinator 0:bb348c97df44 4101
lypinator 0:bb348c97df44 4102 #define RCC_CFGR_MCO2_Pos (30U)
lypinator 0:bb348c97df44 4103 #define RCC_CFGR_MCO2_Msk (0x3U << RCC_CFGR_MCO2_Pos) /*!< 0xC0000000 */
lypinator 0:bb348c97df44 4104 #define RCC_CFGR_MCO2 RCC_CFGR_MCO2_Msk
lypinator 0:bb348c97df44 4105 #define RCC_CFGR_MCO2_0 (0x1U << RCC_CFGR_MCO2_Pos) /*!< 0x40000000 */
lypinator 0:bb348c97df44 4106 #define RCC_CFGR_MCO2_1 (0x2U << RCC_CFGR_MCO2_Pos) /*!< 0x80000000 */
lypinator 0:bb348c97df44 4107
lypinator 0:bb348c97df44 4108 /******************** Bit definition for RCC_CIR register *******************/
lypinator 0:bb348c97df44 4109 #define RCC_CIR_LSIRDYF_Pos (0U)
lypinator 0:bb348c97df44 4110 #define RCC_CIR_LSIRDYF_Msk (0x1U << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 4111 #define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk
lypinator 0:bb348c97df44 4112 #define RCC_CIR_LSERDYF_Pos (1U)
lypinator 0:bb348c97df44 4113 #define RCC_CIR_LSERDYF_Msk (0x1U << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 4114 #define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk
lypinator 0:bb348c97df44 4115 #define RCC_CIR_HSIRDYF_Pos (2U)
lypinator 0:bb348c97df44 4116 #define RCC_CIR_HSIRDYF_Msk (0x1U << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 4117 #define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk
lypinator 0:bb348c97df44 4118 #define RCC_CIR_HSERDYF_Pos (3U)
lypinator 0:bb348c97df44 4119 #define RCC_CIR_HSERDYF_Msk (0x1U << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 4120 #define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk
lypinator 0:bb348c97df44 4121 #define RCC_CIR_PLLRDYF_Pos (4U)
lypinator 0:bb348c97df44 4122 #define RCC_CIR_PLLRDYF_Msk (0x1U << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 4123 #define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk
lypinator 0:bb348c97df44 4124 #define RCC_CIR_PLLI2SRDYF_Pos (5U)
lypinator 0:bb348c97df44 4125 #define RCC_CIR_PLLI2SRDYF_Msk (0x1U << RCC_CIR_PLLI2SRDYF_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 4126 #define RCC_CIR_PLLI2SRDYF RCC_CIR_PLLI2SRDYF_Msk
lypinator 0:bb348c97df44 4127
lypinator 0:bb348c97df44 4128 #define RCC_CIR_CSSF_Pos (7U)
lypinator 0:bb348c97df44 4129 #define RCC_CIR_CSSF_Msk (0x1U << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 4130 #define RCC_CIR_CSSF RCC_CIR_CSSF_Msk
lypinator 0:bb348c97df44 4131 #define RCC_CIR_LSIRDYIE_Pos (8U)
lypinator 0:bb348c97df44 4132 #define RCC_CIR_LSIRDYIE_Msk (0x1U << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 4133 #define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk
lypinator 0:bb348c97df44 4134 #define RCC_CIR_LSERDYIE_Pos (9U)
lypinator 0:bb348c97df44 4135 #define RCC_CIR_LSERDYIE_Msk (0x1U << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 4136 #define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk
lypinator 0:bb348c97df44 4137 #define RCC_CIR_HSIRDYIE_Pos (10U)
lypinator 0:bb348c97df44 4138 #define RCC_CIR_HSIRDYIE_Msk (0x1U << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 4139 #define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk
lypinator 0:bb348c97df44 4140 #define RCC_CIR_HSERDYIE_Pos (11U)
lypinator 0:bb348c97df44 4141 #define RCC_CIR_HSERDYIE_Msk (0x1U << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 4142 #define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk
lypinator 0:bb348c97df44 4143 #define RCC_CIR_PLLRDYIE_Pos (12U)
lypinator 0:bb348c97df44 4144 #define RCC_CIR_PLLRDYIE_Msk (0x1U << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 4145 #define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk
lypinator 0:bb348c97df44 4146 #define RCC_CIR_PLLI2SRDYIE_Pos (13U)
lypinator 0:bb348c97df44 4147 #define RCC_CIR_PLLI2SRDYIE_Msk (0x1U << RCC_CIR_PLLI2SRDYIE_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 4148 #define RCC_CIR_PLLI2SRDYIE RCC_CIR_PLLI2SRDYIE_Msk
lypinator 0:bb348c97df44 4149
lypinator 0:bb348c97df44 4150 #define RCC_CIR_LSIRDYC_Pos (16U)
lypinator 0:bb348c97df44 4151 #define RCC_CIR_LSIRDYC_Msk (0x1U << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 4152 #define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk
lypinator 0:bb348c97df44 4153 #define RCC_CIR_LSERDYC_Pos (17U)
lypinator 0:bb348c97df44 4154 #define RCC_CIR_LSERDYC_Msk (0x1U << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 4155 #define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk
lypinator 0:bb348c97df44 4156 #define RCC_CIR_HSIRDYC_Pos (18U)
lypinator 0:bb348c97df44 4157 #define RCC_CIR_HSIRDYC_Msk (0x1U << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 4158 #define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk
lypinator 0:bb348c97df44 4159 #define RCC_CIR_HSERDYC_Pos (19U)
lypinator 0:bb348c97df44 4160 #define RCC_CIR_HSERDYC_Msk (0x1U << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 4161 #define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk
lypinator 0:bb348c97df44 4162 #define RCC_CIR_PLLRDYC_Pos (20U)
lypinator 0:bb348c97df44 4163 #define RCC_CIR_PLLRDYC_Msk (0x1U << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 4164 #define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk
lypinator 0:bb348c97df44 4165 #define RCC_CIR_PLLI2SRDYC_Pos (21U)
lypinator 0:bb348c97df44 4166 #define RCC_CIR_PLLI2SRDYC_Msk (0x1U << RCC_CIR_PLLI2SRDYC_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 4167 #define RCC_CIR_PLLI2SRDYC RCC_CIR_PLLI2SRDYC_Msk
lypinator 0:bb348c97df44 4168
lypinator 0:bb348c97df44 4169 #define RCC_CIR_CSSC_Pos (23U)
lypinator 0:bb348c97df44 4170 #define RCC_CIR_CSSC_Msk (0x1U << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */
lypinator 0:bb348c97df44 4171 #define RCC_CIR_CSSC RCC_CIR_CSSC_Msk
lypinator 0:bb348c97df44 4172
lypinator 0:bb348c97df44 4173 /******************** Bit definition for RCC_AHB1RSTR register **************/
lypinator 0:bb348c97df44 4174 #define RCC_AHB1RSTR_GPIOARST_Pos (0U)
lypinator 0:bb348c97df44 4175 #define RCC_AHB1RSTR_GPIOARST_Msk (0x1U << RCC_AHB1RSTR_GPIOARST_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 4176 #define RCC_AHB1RSTR_GPIOARST RCC_AHB1RSTR_GPIOARST_Msk
lypinator 0:bb348c97df44 4177 #define RCC_AHB1RSTR_GPIOBRST_Pos (1U)
lypinator 0:bb348c97df44 4178 #define RCC_AHB1RSTR_GPIOBRST_Msk (0x1U << RCC_AHB1RSTR_GPIOBRST_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 4179 #define RCC_AHB1RSTR_GPIOBRST RCC_AHB1RSTR_GPIOBRST_Msk
lypinator 0:bb348c97df44 4180 #define RCC_AHB1RSTR_GPIOCRST_Pos (2U)
lypinator 0:bb348c97df44 4181 #define RCC_AHB1RSTR_GPIOCRST_Msk (0x1U << RCC_AHB1RSTR_GPIOCRST_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 4182 #define RCC_AHB1RSTR_GPIOCRST RCC_AHB1RSTR_GPIOCRST_Msk
lypinator 0:bb348c97df44 4183 #define RCC_AHB1RSTR_GPIODRST_Pos (3U)
lypinator 0:bb348c97df44 4184 #define RCC_AHB1RSTR_GPIODRST_Msk (0x1U << RCC_AHB1RSTR_GPIODRST_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 4185 #define RCC_AHB1RSTR_GPIODRST RCC_AHB1RSTR_GPIODRST_Msk
lypinator 0:bb348c97df44 4186 #define RCC_AHB1RSTR_GPIOERST_Pos (4U)
lypinator 0:bb348c97df44 4187 #define RCC_AHB1RSTR_GPIOERST_Msk (0x1U << RCC_AHB1RSTR_GPIOERST_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 4188 #define RCC_AHB1RSTR_GPIOERST RCC_AHB1RSTR_GPIOERST_Msk
lypinator 0:bb348c97df44 4189 #define RCC_AHB1RSTR_GPIOHRST_Pos (7U)
lypinator 0:bb348c97df44 4190 #define RCC_AHB1RSTR_GPIOHRST_Msk (0x1U << RCC_AHB1RSTR_GPIOHRST_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 4191 #define RCC_AHB1RSTR_GPIOHRST RCC_AHB1RSTR_GPIOHRST_Msk
lypinator 0:bb348c97df44 4192 #define RCC_AHB1RSTR_CRCRST_Pos (12U)
lypinator 0:bb348c97df44 4193 #define RCC_AHB1RSTR_CRCRST_Msk (0x1U << RCC_AHB1RSTR_CRCRST_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 4194 #define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk
lypinator 0:bb348c97df44 4195 #define RCC_AHB1RSTR_DMA1RST_Pos (21U)
lypinator 0:bb348c97df44 4196 #define RCC_AHB1RSTR_DMA1RST_Msk (0x1U << RCC_AHB1RSTR_DMA1RST_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 4197 #define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk
lypinator 0:bb348c97df44 4198 #define RCC_AHB1RSTR_DMA2RST_Pos (22U)
lypinator 0:bb348c97df44 4199 #define RCC_AHB1RSTR_DMA2RST_Msk (0x1U << RCC_AHB1RSTR_DMA2RST_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 4200 #define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk
lypinator 0:bb348c97df44 4201
lypinator 0:bb348c97df44 4202 /******************** Bit definition for RCC_AHB2RSTR register **************/
lypinator 0:bb348c97df44 4203 #define RCC_AHB2RSTR_OTGFSRST_Pos (7U)
lypinator 0:bb348c97df44 4204 #define RCC_AHB2RSTR_OTGFSRST_Msk (0x1U << RCC_AHB2RSTR_OTGFSRST_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 4205 #define RCC_AHB2RSTR_OTGFSRST RCC_AHB2RSTR_OTGFSRST_Msk
lypinator 0:bb348c97df44 4206 /******************** Bit definition for RCC_AHB3RSTR register **************/
lypinator 0:bb348c97df44 4207
lypinator 0:bb348c97df44 4208
lypinator 0:bb348c97df44 4209 /******************** Bit definition for RCC_APB1RSTR register **************/
lypinator 0:bb348c97df44 4210 #define RCC_APB1RSTR_TIM2RST_Pos (0U)
lypinator 0:bb348c97df44 4211 #define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 4212 #define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk
lypinator 0:bb348c97df44 4213 #define RCC_APB1RSTR_TIM3RST_Pos (1U)
lypinator 0:bb348c97df44 4214 #define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 4215 #define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk
lypinator 0:bb348c97df44 4216 #define RCC_APB1RSTR_TIM4RST_Pos (2U)
lypinator 0:bb348c97df44 4217 #define RCC_APB1RSTR_TIM4RST_Msk (0x1U << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 4218 #define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk
lypinator 0:bb348c97df44 4219 #define RCC_APB1RSTR_TIM5RST_Pos (3U)
lypinator 0:bb348c97df44 4220 #define RCC_APB1RSTR_TIM5RST_Msk (0x1U << RCC_APB1RSTR_TIM5RST_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 4221 #define RCC_APB1RSTR_TIM5RST RCC_APB1RSTR_TIM5RST_Msk
lypinator 0:bb348c97df44 4222 #define RCC_APB1RSTR_WWDGRST_Pos (11U)
lypinator 0:bb348c97df44 4223 #define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 4224 #define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk
lypinator 0:bb348c97df44 4225 #define RCC_APB1RSTR_SPI2RST_Pos (14U)
lypinator 0:bb348c97df44 4226 #define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 4227 #define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk
lypinator 0:bb348c97df44 4228 #define RCC_APB1RSTR_SPI3RST_Pos (15U)
lypinator 0:bb348c97df44 4229 #define RCC_APB1RSTR_SPI3RST_Msk (0x1U << RCC_APB1RSTR_SPI3RST_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 4230 #define RCC_APB1RSTR_SPI3RST RCC_APB1RSTR_SPI3RST_Msk
lypinator 0:bb348c97df44 4231 #define RCC_APB1RSTR_USART2RST_Pos (17U)
lypinator 0:bb348c97df44 4232 #define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 4233 #define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk
lypinator 0:bb348c97df44 4234 #define RCC_APB1RSTR_I2C1RST_Pos (21U)
lypinator 0:bb348c97df44 4235 #define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 4236 #define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk
lypinator 0:bb348c97df44 4237 #define RCC_APB1RSTR_I2C2RST_Pos (22U)
lypinator 0:bb348c97df44 4238 #define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 4239 #define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk
lypinator 0:bb348c97df44 4240 #define RCC_APB1RSTR_I2C3RST_Pos (23U)
lypinator 0:bb348c97df44 4241 #define RCC_APB1RSTR_I2C3RST_Msk (0x1U << RCC_APB1RSTR_I2C3RST_Pos) /*!< 0x00800000 */
lypinator 0:bb348c97df44 4242 #define RCC_APB1RSTR_I2C3RST RCC_APB1RSTR_I2C3RST_Msk
lypinator 0:bb348c97df44 4243 #define RCC_APB1RSTR_PWRRST_Pos (28U)
lypinator 0:bb348c97df44 4244 #define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
lypinator 0:bb348c97df44 4245 #define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk
lypinator 0:bb348c97df44 4246
lypinator 0:bb348c97df44 4247 /******************** Bit definition for RCC_APB2RSTR register **************/
lypinator 0:bb348c97df44 4248 #define RCC_APB2RSTR_TIM1RST_Pos (0U)
lypinator 0:bb348c97df44 4249 #define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 4250 #define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
lypinator 0:bb348c97df44 4251 #define RCC_APB2RSTR_USART1RST_Pos (4U)
lypinator 0:bb348c97df44 4252 #define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 4253 #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
lypinator 0:bb348c97df44 4254 #define RCC_APB2RSTR_USART6RST_Pos (5U)
lypinator 0:bb348c97df44 4255 #define RCC_APB2RSTR_USART6RST_Msk (0x1U << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 4256 #define RCC_APB2RSTR_USART6RST RCC_APB2RSTR_USART6RST_Msk
lypinator 0:bb348c97df44 4257 #define RCC_APB2RSTR_ADCRST_Pos (8U)
lypinator 0:bb348c97df44 4258 #define RCC_APB2RSTR_ADCRST_Msk (0x1U << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 4259 #define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk
lypinator 0:bb348c97df44 4260 #define RCC_APB2RSTR_SDIORST_Pos (11U)
lypinator 0:bb348c97df44 4261 #define RCC_APB2RSTR_SDIORST_Msk (0x1U << RCC_APB2RSTR_SDIORST_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 4262 #define RCC_APB2RSTR_SDIORST RCC_APB2RSTR_SDIORST_Msk
lypinator 0:bb348c97df44 4263 #define RCC_APB2RSTR_SPI1RST_Pos (12U)
lypinator 0:bb348c97df44 4264 #define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 4265 #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
lypinator 0:bb348c97df44 4266 #define RCC_APB2RSTR_SPI4RST_Pos (13U)
lypinator 0:bb348c97df44 4267 #define RCC_APB2RSTR_SPI4RST_Msk (0x1U << RCC_APB2RSTR_SPI4RST_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 4268 #define RCC_APB2RSTR_SPI4RST RCC_APB2RSTR_SPI4RST_Msk
lypinator 0:bb348c97df44 4269 #define RCC_APB2RSTR_SYSCFGRST_Pos (14U)
lypinator 0:bb348c97df44 4270 #define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 4271 #define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk
lypinator 0:bb348c97df44 4272 #define RCC_APB2RSTR_TIM9RST_Pos (16U)
lypinator 0:bb348c97df44 4273 #define RCC_APB2RSTR_TIM9RST_Msk (0x1U << RCC_APB2RSTR_TIM9RST_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 4274 #define RCC_APB2RSTR_TIM9RST RCC_APB2RSTR_TIM9RST_Msk
lypinator 0:bb348c97df44 4275 #define RCC_APB2RSTR_TIM10RST_Pos (17U)
lypinator 0:bb348c97df44 4276 #define RCC_APB2RSTR_TIM10RST_Msk (0x1U << RCC_APB2RSTR_TIM10RST_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 4277 #define RCC_APB2RSTR_TIM10RST RCC_APB2RSTR_TIM10RST_Msk
lypinator 0:bb348c97df44 4278 #define RCC_APB2RSTR_TIM11RST_Pos (18U)
lypinator 0:bb348c97df44 4279 #define RCC_APB2RSTR_TIM11RST_Msk (0x1U << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 4280 #define RCC_APB2RSTR_TIM11RST RCC_APB2RSTR_TIM11RST_Msk
lypinator 0:bb348c97df44 4281 #define RCC_APB2RSTR_SPI5RST_Pos (20U)
lypinator 0:bb348c97df44 4282 #define RCC_APB2RSTR_SPI5RST_Msk (0x1U << RCC_APB2RSTR_SPI5RST_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 4283 #define RCC_APB2RSTR_SPI5RST RCC_APB2RSTR_SPI5RST_Msk
lypinator 0:bb348c97df44 4284
lypinator 0:bb348c97df44 4285 /* Old SPI1RST bit definition, maintained for legacy purpose */
lypinator 0:bb348c97df44 4286 #define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
lypinator 0:bb348c97df44 4287
lypinator 0:bb348c97df44 4288 /******************** Bit definition for RCC_AHB1ENR register ***************/
lypinator 0:bb348c97df44 4289 #define RCC_AHB1ENR_GPIOAEN_Pos (0U)
lypinator 0:bb348c97df44 4290 #define RCC_AHB1ENR_GPIOAEN_Msk (0x1U << RCC_AHB1ENR_GPIOAEN_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 4291 #define RCC_AHB1ENR_GPIOAEN RCC_AHB1ENR_GPIOAEN_Msk
lypinator 0:bb348c97df44 4292 #define RCC_AHB1ENR_GPIOBEN_Pos (1U)
lypinator 0:bb348c97df44 4293 #define RCC_AHB1ENR_GPIOBEN_Msk (0x1U << RCC_AHB1ENR_GPIOBEN_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 4294 #define RCC_AHB1ENR_GPIOBEN RCC_AHB1ENR_GPIOBEN_Msk
lypinator 0:bb348c97df44 4295 #define RCC_AHB1ENR_GPIOCEN_Pos (2U)
lypinator 0:bb348c97df44 4296 #define RCC_AHB1ENR_GPIOCEN_Msk (0x1U << RCC_AHB1ENR_GPIOCEN_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 4297 #define RCC_AHB1ENR_GPIOCEN RCC_AHB1ENR_GPIOCEN_Msk
lypinator 0:bb348c97df44 4298 #define RCC_AHB1ENR_GPIODEN_Pos (3U)
lypinator 0:bb348c97df44 4299 #define RCC_AHB1ENR_GPIODEN_Msk (0x1U << RCC_AHB1ENR_GPIODEN_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 4300 #define RCC_AHB1ENR_GPIODEN RCC_AHB1ENR_GPIODEN_Msk
lypinator 0:bb348c97df44 4301 #define RCC_AHB1ENR_GPIOEEN_Pos (4U)
lypinator 0:bb348c97df44 4302 #define RCC_AHB1ENR_GPIOEEN_Msk (0x1U << RCC_AHB1ENR_GPIOEEN_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 4303 #define RCC_AHB1ENR_GPIOEEN RCC_AHB1ENR_GPIOEEN_Msk
lypinator 0:bb348c97df44 4304 #define RCC_AHB1ENR_GPIOHEN_Pos (7U)
lypinator 0:bb348c97df44 4305 #define RCC_AHB1ENR_GPIOHEN_Msk (0x1U << RCC_AHB1ENR_GPIOHEN_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 4306 #define RCC_AHB1ENR_GPIOHEN RCC_AHB1ENR_GPIOHEN_Msk
lypinator 0:bb348c97df44 4307 #define RCC_AHB1ENR_CRCEN_Pos (12U)
lypinator 0:bb348c97df44 4308 #define RCC_AHB1ENR_CRCEN_Msk (0x1U << RCC_AHB1ENR_CRCEN_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 4309 #define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk
lypinator 0:bb348c97df44 4310 #define RCC_AHB1ENR_DMA1EN_Pos (21U)
lypinator 0:bb348c97df44 4311 #define RCC_AHB1ENR_DMA1EN_Msk (0x1U << RCC_AHB1ENR_DMA1EN_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 4312 #define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk
lypinator 0:bb348c97df44 4313 #define RCC_AHB1ENR_DMA2EN_Pos (22U)
lypinator 0:bb348c97df44 4314 #define RCC_AHB1ENR_DMA2EN_Msk (0x1U << RCC_AHB1ENR_DMA2EN_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 4315 #define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk
lypinator 0:bb348c97df44 4316 /******************** Bit definition for RCC_AHB2ENR register ***************/
lypinator 0:bb348c97df44 4317 /*
lypinator 0:bb348c97df44 4318 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
lypinator 0:bb348c97df44 4319 */
lypinator 0:bb348c97df44 4320 #define RCC_AHB2_SUPPORT /*!< AHB2 Bus is supported */
lypinator 0:bb348c97df44 4321
lypinator 0:bb348c97df44 4322 #define RCC_AHB2ENR_OTGFSEN_Pos (7U)
lypinator 0:bb348c97df44 4323 #define RCC_AHB2ENR_OTGFSEN_Msk (0x1U << RCC_AHB2ENR_OTGFSEN_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 4324 #define RCC_AHB2ENR_OTGFSEN RCC_AHB2ENR_OTGFSEN_Msk
lypinator 0:bb348c97df44 4325
lypinator 0:bb348c97df44 4326 /******************** Bit definition for RCC_APB1ENR register ***************/
lypinator 0:bb348c97df44 4327 #define RCC_APB1ENR_TIM2EN_Pos (0U)
lypinator 0:bb348c97df44 4328 #define RCC_APB1ENR_TIM2EN_Msk (0x1U << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 4329 #define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk
lypinator 0:bb348c97df44 4330 #define RCC_APB1ENR_TIM3EN_Pos (1U)
lypinator 0:bb348c97df44 4331 #define RCC_APB1ENR_TIM3EN_Msk (0x1U << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 4332 #define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk
lypinator 0:bb348c97df44 4333 #define RCC_APB1ENR_TIM4EN_Pos (2U)
lypinator 0:bb348c97df44 4334 #define RCC_APB1ENR_TIM4EN_Msk (0x1U << RCC_APB1ENR_TIM4EN_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 4335 #define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk
lypinator 0:bb348c97df44 4336 #define RCC_APB1ENR_TIM5EN_Pos (3U)
lypinator 0:bb348c97df44 4337 #define RCC_APB1ENR_TIM5EN_Msk (0x1U << RCC_APB1ENR_TIM5EN_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 4338 #define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk
lypinator 0:bb348c97df44 4339 #define RCC_APB1ENR_WWDGEN_Pos (11U)
lypinator 0:bb348c97df44 4340 #define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 4341 #define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk
lypinator 0:bb348c97df44 4342 #define RCC_APB1ENR_SPI2EN_Pos (14U)
lypinator 0:bb348c97df44 4343 #define RCC_APB1ENR_SPI2EN_Msk (0x1U << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 4344 #define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk
lypinator 0:bb348c97df44 4345 #define RCC_APB1ENR_SPI3EN_Pos (15U)
lypinator 0:bb348c97df44 4346 #define RCC_APB1ENR_SPI3EN_Msk (0x1U << RCC_APB1ENR_SPI3EN_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 4347 #define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk
lypinator 0:bb348c97df44 4348 #define RCC_APB1ENR_USART2EN_Pos (17U)
lypinator 0:bb348c97df44 4349 #define RCC_APB1ENR_USART2EN_Msk (0x1U << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 4350 #define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk
lypinator 0:bb348c97df44 4351 #define RCC_APB1ENR_I2C1EN_Pos (21U)
lypinator 0:bb348c97df44 4352 #define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 4353 #define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk
lypinator 0:bb348c97df44 4354 #define RCC_APB1ENR_I2C2EN_Pos (22U)
lypinator 0:bb348c97df44 4355 #define RCC_APB1ENR_I2C2EN_Msk (0x1U << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 4356 #define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk
lypinator 0:bb348c97df44 4357 #define RCC_APB1ENR_I2C3EN_Pos (23U)
lypinator 0:bb348c97df44 4358 #define RCC_APB1ENR_I2C3EN_Msk (0x1U << RCC_APB1ENR_I2C3EN_Pos) /*!< 0x00800000 */
lypinator 0:bb348c97df44 4359 #define RCC_APB1ENR_I2C3EN RCC_APB1ENR_I2C3EN_Msk
lypinator 0:bb348c97df44 4360 #define RCC_APB1ENR_PWREN_Pos (28U)
lypinator 0:bb348c97df44 4361 #define RCC_APB1ENR_PWREN_Msk (0x1U << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
lypinator 0:bb348c97df44 4362 #define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk
lypinator 0:bb348c97df44 4363
lypinator 0:bb348c97df44 4364 /******************** Bit definition for RCC_APB2ENR register ***************/
lypinator 0:bb348c97df44 4365 #define RCC_APB2ENR_TIM1EN_Pos (0U)
lypinator 0:bb348c97df44 4366 #define RCC_APB2ENR_TIM1EN_Msk (0x1U << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 4367 #define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
lypinator 0:bb348c97df44 4368 #define RCC_APB2ENR_USART1EN_Pos (4U)
lypinator 0:bb348c97df44 4369 #define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 4370 #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
lypinator 0:bb348c97df44 4371 #define RCC_APB2ENR_USART6EN_Pos (5U)
lypinator 0:bb348c97df44 4372 #define RCC_APB2ENR_USART6EN_Msk (0x1U << RCC_APB2ENR_USART6EN_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 4373 #define RCC_APB2ENR_USART6EN RCC_APB2ENR_USART6EN_Msk
lypinator 0:bb348c97df44 4374 #define RCC_APB2ENR_ADC1EN_Pos (8U)
lypinator 0:bb348c97df44 4375 #define RCC_APB2ENR_ADC1EN_Msk (0x1U << RCC_APB2ENR_ADC1EN_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 4376 #define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk
lypinator 0:bb348c97df44 4377 #define RCC_APB2ENR_SDIOEN_Pos (11U)
lypinator 0:bb348c97df44 4378 #define RCC_APB2ENR_SDIOEN_Msk (0x1U << RCC_APB2ENR_SDIOEN_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 4379 #define RCC_APB2ENR_SDIOEN RCC_APB2ENR_SDIOEN_Msk
lypinator 0:bb348c97df44 4380 #define RCC_APB2ENR_SPI1EN_Pos (12U)
lypinator 0:bb348c97df44 4381 #define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 4382 #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
lypinator 0:bb348c97df44 4383 #define RCC_APB2ENR_SPI4EN_Pos (13U)
lypinator 0:bb348c97df44 4384 #define RCC_APB2ENR_SPI4EN_Msk (0x1U << RCC_APB2ENR_SPI4EN_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 4385 #define RCC_APB2ENR_SPI4EN RCC_APB2ENR_SPI4EN_Msk
lypinator 0:bb348c97df44 4386 #define RCC_APB2ENR_SYSCFGEN_Pos (14U)
lypinator 0:bb348c97df44 4387 #define RCC_APB2ENR_SYSCFGEN_Msk (0x1U << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 4388 #define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk
lypinator 0:bb348c97df44 4389 #define RCC_APB2ENR_TIM9EN_Pos (16U)
lypinator 0:bb348c97df44 4390 #define RCC_APB2ENR_TIM9EN_Msk (0x1U << RCC_APB2ENR_TIM9EN_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 4391 #define RCC_APB2ENR_TIM9EN RCC_APB2ENR_TIM9EN_Msk
lypinator 0:bb348c97df44 4392 #define RCC_APB2ENR_TIM10EN_Pos (17U)
lypinator 0:bb348c97df44 4393 #define RCC_APB2ENR_TIM10EN_Msk (0x1U << RCC_APB2ENR_TIM10EN_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 4394 #define RCC_APB2ENR_TIM10EN RCC_APB2ENR_TIM10EN_Msk
lypinator 0:bb348c97df44 4395 #define RCC_APB2ENR_TIM11EN_Pos (18U)
lypinator 0:bb348c97df44 4396 #define RCC_APB2ENR_TIM11EN_Msk (0x1U << RCC_APB2ENR_TIM11EN_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 4397 #define RCC_APB2ENR_TIM11EN RCC_APB2ENR_TIM11EN_Msk
lypinator 0:bb348c97df44 4398 #define RCC_APB2ENR_SPI5EN_Pos (20U)
lypinator 0:bb348c97df44 4399 #define RCC_APB2ENR_SPI5EN_Msk (0x1U << RCC_APB2ENR_SPI5EN_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 4400 #define RCC_APB2ENR_SPI5EN RCC_APB2ENR_SPI5EN_Msk
lypinator 0:bb348c97df44 4401
lypinator 0:bb348c97df44 4402 /******************** Bit definition for RCC_AHB1LPENR register *************/
lypinator 0:bb348c97df44 4403 #define RCC_AHB1LPENR_GPIOALPEN_Pos (0U)
lypinator 0:bb348c97df44 4404 #define RCC_AHB1LPENR_GPIOALPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 4405 #define RCC_AHB1LPENR_GPIOALPEN RCC_AHB1LPENR_GPIOALPEN_Msk
lypinator 0:bb348c97df44 4406 #define RCC_AHB1LPENR_GPIOBLPEN_Pos (1U)
lypinator 0:bb348c97df44 4407 #define RCC_AHB1LPENR_GPIOBLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 4408 #define RCC_AHB1LPENR_GPIOBLPEN RCC_AHB1LPENR_GPIOBLPEN_Msk
lypinator 0:bb348c97df44 4409 #define RCC_AHB1LPENR_GPIOCLPEN_Pos (2U)
lypinator 0:bb348c97df44 4410 #define RCC_AHB1LPENR_GPIOCLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 4411 #define RCC_AHB1LPENR_GPIOCLPEN RCC_AHB1LPENR_GPIOCLPEN_Msk
lypinator 0:bb348c97df44 4412 #define RCC_AHB1LPENR_GPIODLPEN_Pos (3U)
lypinator 0:bb348c97df44 4413 #define RCC_AHB1LPENR_GPIODLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 4414 #define RCC_AHB1LPENR_GPIODLPEN RCC_AHB1LPENR_GPIODLPEN_Msk
lypinator 0:bb348c97df44 4415 #define RCC_AHB1LPENR_GPIOELPEN_Pos (4U)
lypinator 0:bb348c97df44 4416 #define RCC_AHB1LPENR_GPIOELPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 4417 #define RCC_AHB1LPENR_GPIOELPEN RCC_AHB1LPENR_GPIOELPEN_Msk
lypinator 0:bb348c97df44 4418 #define RCC_AHB1LPENR_GPIOHLPEN_Pos (7U)
lypinator 0:bb348c97df44 4419 #define RCC_AHB1LPENR_GPIOHLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 4420 #define RCC_AHB1LPENR_GPIOHLPEN RCC_AHB1LPENR_GPIOHLPEN_Msk
lypinator 0:bb348c97df44 4421 #define RCC_AHB1LPENR_CRCLPEN_Pos (12U)
lypinator 0:bb348c97df44 4422 #define RCC_AHB1LPENR_CRCLPEN_Msk (0x1U << RCC_AHB1LPENR_CRCLPEN_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 4423 #define RCC_AHB1LPENR_CRCLPEN RCC_AHB1LPENR_CRCLPEN_Msk
lypinator 0:bb348c97df44 4424 #define RCC_AHB1LPENR_FLITFLPEN_Pos (15U)
lypinator 0:bb348c97df44 4425 #define RCC_AHB1LPENR_FLITFLPEN_Msk (0x1U << RCC_AHB1LPENR_FLITFLPEN_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 4426 #define RCC_AHB1LPENR_FLITFLPEN RCC_AHB1LPENR_FLITFLPEN_Msk
lypinator 0:bb348c97df44 4427 #define RCC_AHB1LPENR_SRAM1LPEN_Pos (16U)
lypinator 0:bb348c97df44 4428 #define RCC_AHB1LPENR_SRAM1LPEN_Msk (0x1U << RCC_AHB1LPENR_SRAM1LPEN_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 4429 #define RCC_AHB1LPENR_SRAM1LPEN RCC_AHB1LPENR_SRAM1LPEN_Msk
lypinator 0:bb348c97df44 4430 #define RCC_AHB1LPENR_DMA1LPEN_Pos (21U)
lypinator 0:bb348c97df44 4431 #define RCC_AHB1LPENR_DMA1LPEN_Msk (0x1U << RCC_AHB1LPENR_DMA1LPEN_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 4432 #define RCC_AHB1LPENR_DMA1LPEN RCC_AHB1LPENR_DMA1LPEN_Msk
lypinator 0:bb348c97df44 4433 #define RCC_AHB1LPENR_DMA2LPEN_Pos (22U)
lypinator 0:bb348c97df44 4434 #define RCC_AHB1LPENR_DMA2LPEN_Msk (0x1U << RCC_AHB1LPENR_DMA2LPEN_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 4435 #define RCC_AHB1LPENR_DMA2LPEN RCC_AHB1LPENR_DMA2LPEN_Msk
lypinator 0:bb348c97df44 4436
lypinator 0:bb348c97df44 4437
lypinator 0:bb348c97df44 4438 /******************** Bit definition for RCC_AHB2LPENR register *************/
lypinator 0:bb348c97df44 4439 #define RCC_AHB2LPENR_OTGFSLPEN_Pos (7U)
lypinator 0:bb348c97df44 4440 #define RCC_AHB2LPENR_OTGFSLPEN_Msk (0x1U << RCC_AHB2LPENR_OTGFSLPEN_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 4441 #define RCC_AHB2LPENR_OTGFSLPEN RCC_AHB2LPENR_OTGFSLPEN_Msk
lypinator 0:bb348c97df44 4442
lypinator 0:bb348c97df44 4443 /******************** Bit definition for RCC_AHB3LPENR register *************/
lypinator 0:bb348c97df44 4444
lypinator 0:bb348c97df44 4445 /******************** Bit definition for RCC_APB1LPENR register *************/
lypinator 0:bb348c97df44 4446 #define RCC_APB1LPENR_TIM2LPEN_Pos (0U)
lypinator 0:bb348c97df44 4447 #define RCC_APB1LPENR_TIM2LPEN_Msk (0x1U << RCC_APB1LPENR_TIM2LPEN_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 4448 #define RCC_APB1LPENR_TIM2LPEN RCC_APB1LPENR_TIM2LPEN_Msk
lypinator 0:bb348c97df44 4449 #define RCC_APB1LPENR_TIM3LPEN_Pos (1U)
lypinator 0:bb348c97df44 4450 #define RCC_APB1LPENR_TIM3LPEN_Msk (0x1U << RCC_APB1LPENR_TIM3LPEN_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 4451 #define RCC_APB1LPENR_TIM3LPEN RCC_APB1LPENR_TIM3LPEN_Msk
lypinator 0:bb348c97df44 4452 #define RCC_APB1LPENR_TIM4LPEN_Pos (2U)
lypinator 0:bb348c97df44 4453 #define RCC_APB1LPENR_TIM4LPEN_Msk (0x1U << RCC_APB1LPENR_TIM4LPEN_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 4454 #define RCC_APB1LPENR_TIM4LPEN RCC_APB1LPENR_TIM4LPEN_Msk
lypinator 0:bb348c97df44 4455 #define RCC_APB1LPENR_TIM5LPEN_Pos (3U)
lypinator 0:bb348c97df44 4456 #define RCC_APB1LPENR_TIM5LPEN_Msk (0x1U << RCC_APB1LPENR_TIM5LPEN_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 4457 #define RCC_APB1LPENR_TIM5LPEN RCC_APB1LPENR_TIM5LPEN_Msk
lypinator 0:bb348c97df44 4458 #define RCC_APB1LPENR_WWDGLPEN_Pos (11U)
lypinator 0:bb348c97df44 4459 #define RCC_APB1LPENR_WWDGLPEN_Msk (0x1U << RCC_APB1LPENR_WWDGLPEN_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 4460 #define RCC_APB1LPENR_WWDGLPEN RCC_APB1LPENR_WWDGLPEN_Msk
lypinator 0:bb348c97df44 4461 #define RCC_APB1LPENR_SPI2LPEN_Pos (14U)
lypinator 0:bb348c97df44 4462 #define RCC_APB1LPENR_SPI2LPEN_Msk (0x1U << RCC_APB1LPENR_SPI2LPEN_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 4463 #define RCC_APB1LPENR_SPI2LPEN RCC_APB1LPENR_SPI2LPEN_Msk
lypinator 0:bb348c97df44 4464 #define RCC_APB1LPENR_SPI3LPEN_Pos (15U)
lypinator 0:bb348c97df44 4465 #define RCC_APB1LPENR_SPI3LPEN_Msk (0x1U << RCC_APB1LPENR_SPI3LPEN_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 4466 #define RCC_APB1LPENR_SPI3LPEN RCC_APB1LPENR_SPI3LPEN_Msk
lypinator 0:bb348c97df44 4467 #define RCC_APB1LPENR_USART2LPEN_Pos (17U)
lypinator 0:bb348c97df44 4468 #define RCC_APB1LPENR_USART2LPEN_Msk (0x1U << RCC_APB1LPENR_USART2LPEN_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 4469 #define RCC_APB1LPENR_USART2LPEN RCC_APB1LPENR_USART2LPEN_Msk
lypinator 0:bb348c97df44 4470 #define RCC_APB1LPENR_I2C1LPEN_Pos (21U)
lypinator 0:bb348c97df44 4471 #define RCC_APB1LPENR_I2C1LPEN_Msk (0x1U << RCC_APB1LPENR_I2C1LPEN_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 4472 #define RCC_APB1LPENR_I2C1LPEN RCC_APB1LPENR_I2C1LPEN_Msk
lypinator 0:bb348c97df44 4473 #define RCC_APB1LPENR_I2C2LPEN_Pos (22U)
lypinator 0:bb348c97df44 4474 #define RCC_APB1LPENR_I2C2LPEN_Msk (0x1U << RCC_APB1LPENR_I2C2LPEN_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 4475 #define RCC_APB1LPENR_I2C2LPEN RCC_APB1LPENR_I2C2LPEN_Msk
lypinator 0:bb348c97df44 4476 #define RCC_APB1LPENR_I2C3LPEN_Pos (23U)
lypinator 0:bb348c97df44 4477 #define RCC_APB1LPENR_I2C3LPEN_Msk (0x1U << RCC_APB1LPENR_I2C3LPEN_Pos) /*!< 0x00800000 */
lypinator 0:bb348c97df44 4478 #define RCC_APB1LPENR_I2C3LPEN RCC_APB1LPENR_I2C3LPEN_Msk
lypinator 0:bb348c97df44 4479 #define RCC_APB1LPENR_PWRLPEN_Pos (28U)
lypinator 0:bb348c97df44 4480 #define RCC_APB1LPENR_PWRLPEN_Msk (0x1U << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */
lypinator 0:bb348c97df44 4481 #define RCC_APB1LPENR_PWRLPEN RCC_APB1LPENR_PWRLPEN_Msk
lypinator 0:bb348c97df44 4482
lypinator 0:bb348c97df44 4483 /******************** Bit definition for RCC_APB2LPENR register *************/
lypinator 0:bb348c97df44 4484 #define RCC_APB2LPENR_TIM1LPEN_Pos (0U)
lypinator 0:bb348c97df44 4485 #define RCC_APB2LPENR_TIM1LPEN_Msk (0x1U << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 4486 #define RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk
lypinator 0:bb348c97df44 4487 #define RCC_APB2LPENR_USART1LPEN_Pos (4U)
lypinator 0:bb348c97df44 4488 #define RCC_APB2LPENR_USART1LPEN_Msk (0x1U << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 4489 #define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk
lypinator 0:bb348c97df44 4490 #define RCC_APB2LPENR_USART6LPEN_Pos (5U)
lypinator 0:bb348c97df44 4491 #define RCC_APB2LPENR_USART6LPEN_Msk (0x1U << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 4492 #define RCC_APB2LPENR_USART6LPEN RCC_APB2LPENR_USART6LPEN_Msk
lypinator 0:bb348c97df44 4493 #define RCC_APB2LPENR_ADC1LPEN_Pos (8U)
lypinator 0:bb348c97df44 4494 #define RCC_APB2LPENR_ADC1LPEN_Msk (0x1U << RCC_APB2LPENR_ADC1LPEN_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 4495 #define RCC_APB2LPENR_ADC1LPEN RCC_APB2LPENR_ADC1LPEN_Msk
lypinator 0:bb348c97df44 4496 #define RCC_APB2LPENR_SDIOLPEN_Pos (11U)
lypinator 0:bb348c97df44 4497 #define RCC_APB2LPENR_SDIOLPEN_Msk (0x1U << RCC_APB2LPENR_SDIOLPEN_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 4498 #define RCC_APB2LPENR_SDIOLPEN RCC_APB2LPENR_SDIOLPEN_Msk
lypinator 0:bb348c97df44 4499 #define RCC_APB2LPENR_SPI1LPEN_Pos (12U)
lypinator 0:bb348c97df44 4500 #define RCC_APB2LPENR_SPI1LPEN_Msk (0x1U << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 4501 #define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk
lypinator 0:bb348c97df44 4502 #define RCC_APB2LPENR_SPI4LPEN_Pos (13U)
lypinator 0:bb348c97df44 4503 #define RCC_APB2LPENR_SPI4LPEN_Msk (0x1U << RCC_APB2LPENR_SPI4LPEN_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 4504 #define RCC_APB2LPENR_SPI4LPEN RCC_APB2LPENR_SPI4LPEN_Msk
lypinator 0:bb348c97df44 4505 #define RCC_APB2LPENR_SYSCFGLPEN_Pos (14U)
lypinator 0:bb348c97df44 4506 #define RCC_APB2LPENR_SYSCFGLPEN_Msk (0x1U << RCC_APB2LPENR_SYSCFGLPEN_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 4507 #define RCC_APB2LPENR_SYSCFGLPEN RCC_APB2LPENR_SYSCFGLPEN_Msk
lypinator 0:bb348c97df44 4508 #define RCC_APB2LPENR_TIM9LPEN_Pos (16U)
lypinator 0:bb348c97df44 4509 #define RCC_APB2LPENR_TIM9LPEN_Msk (0x1U << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 4510 #define RCC_APB2LPENR_TIM9LPEN RCC_APB2LPENR_TIM9LPEN_Msk
lypinator 0:bb348c97df44 4511 #define RCC_APB2LPENR_TIM10LPEN_Pos (17U)
lypinator 0:bb348c97df44 4512 #define RCC_APB2LPENR_TIM10LPEN_Msk (0x1U << RCC_APB2LPENR_TIM10LPEN_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 4513 #define RCC_APB2LPENR_TIM10LPEN RCC_APB2LPENR_TIM10LPEN_Msk
lypinator 0:bb348c97df44 4514 #define RCC_APB2LPENR_TIM11LPEN_Pos (18U)
lypinator 0:bb348c97df44 4515 #define RCC_APB2LPENR_TIM11LPEN_Msk (0x1U << RCC_APB2LPENR_TIM11LPEN_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 4516 #define RCC_APB2LPENR_TIM11LPEN RCC_APB2LPENR_TIM11LPEN_Msk
lypinator 0:bb348c97df44 4517 #define RCC_APB2LPENR_SPI5LPEN_Pos (20U)
lypinator 0:bb348c97df44 4518 #define RCC_APB2LPENR_SPI5LPEN_Msk (0x1U << RCC_APB2LPENR_SPI5LPEN_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 4519 #define RCC_APB2LPENR_SPI5LPEN RCC_APB2LPENR_SPI5LPEN_Msk
lypinator 0:bb348c97df44 4520
lypinator 0:bb348c97df44 4521 /******************** Bit definition for RCC_BDCR register ******************/
lypinator 0:bb348c97df44 4522 #define RCC_BDCR_LSEON_Pos (0U)
lypinator 0:bb348c97df44 4523 #define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 4524 #define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
lypinator 0:bb348c97df44 4525 #define RCC_BDCR_LSERDY_Pos (1U)
lypinator 0:bb348c97df44 4526 #define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 4527 #define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
lypinator 0:bb348c97df44 4528 #define RCC_BDCR_LSEBYP_Pos (2U)
lypinator 0:bb348c97df44 4529 #define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 4530 #define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
lypinator 0:bb348c97df44 4531 #define RCC_BDCR_LSEMOD_Pos (3U)
lypinator 0:bb348c97df44 4532 #define RCC_BDCR_LSEMOD_Msk (0x1U << RCC_BDCR_LSEMOD_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 4533 #define RCC_BDCR_LSEMOD RCC_BDCR_LSEMOD_Msk
lypinator 0:bb348c97df44 4534
lypinator 0:bb348c97df44 4535 #define RCC_BDCR_RTCSEL_Pos (8U)
lypinator 0:bb348c97df44 4536 #define RCC_BDCR_RTCSEL_Msk (0x3U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
lypinator 0:bb348c97df44 4537 #define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
lypinator 0:bb348c97df44 4538 #define RCC_BDCR_RTCSEL_0 (0x1U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 4539 #define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 4540
lypinator 0:bb348c97df44 4541 #define RCC_BDCR_RTCEN_Pos (15U)
lypinator 0:bb348c97df44 4542 #define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 4543 #define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
lypinator 0:bb348c97df44 4544 #define RCC_BDCR_BDRST_Pos (16U)
lypinator 0:bb348c97df44 4545 #define RCC_BDCR_BDRST_Msk (0x1U << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 4546 #define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
lypinator 0:bb348c97df44 4547
lypinator 0:bb348c97df44 4548 /******************** Bit definition for RCC_CSR register *******************/
lypinator 0:bb348c97df44 4549 #define RCC_CSR_LSION_Pos (0U)
lypinator 0:bb348c97df44 4550 #define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 4551 #define RCC_CSR_LSION RCC_CSR_LSION_Msk
lypinator 0:bb348c97df44 4552 #define RCC_CSR_LSIRDY_Pos (1U)
lypinator 0:bb348c97df44 4553 #define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 4554 #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
lypinator 0:bb348c97df44 4555 #define RCC_CSR_RMVF_Pos (24U)
lypinator 0:bb348c97df44 4556 #define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 4557 #define RCC_CSR_RMVF RCC_CSR_RMVF_Msk
lypinator 0:bb348c97df44 4558 #define RCC_CSR_BORRSTF_Pos (25U)
lypinator 0:bb348c97df44 4559 #define RCC_CSR_BORRSTF_Msk (0x1U << RCC_CSR_BORRSTF_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 4560 #define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk
lypinator 0:bb348c97df44 4561 #define RCC_CSR_PINRSTF_Pos (26U)
lypinator 0:bb348c97df44 4562 #define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
lypinator 0:bb348c97df44 4563 #define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk
lypinator 0:bb348c97df44 4564 #define RCC_CSR_PORRSTF_Pos (27U)
lypinator 0:bb348c97df44 4565 #define RCC_CSR_PORRSTF_Msk (0x1U << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
lypinator 0:bb348c97df44 4566 #define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk
lypinator 0:bb348c97df44 4567 #define RCC_CSR_SFTRSTF_Pos (28U)
lypinator 0:bb348c97df44 4568 #define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
lypinator 0:bb348c97df44 4569 #define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk
lypinator 0:bb348c97df44 4570 #define RCC_CSR_IWDGRSTF_Pos (29U)
lypinator 0:bb348c97df44 4571 #define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
lypinator 0:bb348c97df44 4572 #define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk
lypinator 0:bb348c97df44 4573 #define RCC_CSR_WWDGRSTF_Pos (30U)
lypinator 0:bb348c97df44 4574 #define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
lypinator 0:bb348c97df44 4575 #define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk
lypinator 0:bb348c97df44 4576 #define RCC_CSR_LPWRRSTF_Pos (31U)
lypinator 0:bb348c97df44 4577 #define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
lypinator 0:bb348c97df44 4578 #define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk
lypinator 0:bb348c97df44 4579 /* Legacy defines */
lypinator 0:bb348c97df44 4580 #define RCC_CSR_PADRSTF RCC_CSR_PINRSTF
lypinator 0:bb348c97df44 4581 #define RCC_CSR_WDGRSTF RCC_CSR_IWDGRSTF
lypinator 0:bb348c97df44 4582
lypinator 0:bb348c97df44 4583 /******************** Bit definition for RCC_SSCGR register *****************/
lypinator 0:bb348c97df44 4584 #define RCC_SSCGR_MODPER_Pos (0U)
lypinator 0:bb348c97df44 4585 #define RCC_SSCGR_MODPER_Msk (0x1FFFU << RCC_SSCGR_MODPER_Pos) /*!< 0x00001FFF */
lypinator 0:bb348c97df44 4586 #define RCC_SSCGR_MODPER RCC_SSCGR_MODPER_Msk
lypinator 0:bb348c97df44 4587 #define RCC_SSCGR_INCSTEP_Pos (13U)
lypinator 0:bb348c97df44 4588 #define RCC_SSCGR_INCSTEP_Msk (0x7FFFU << RCC_SSCGR_INCSTEP_Pos) /*!< 0x0FFFE000 */
lypinator 0:bb348c97df44 4589 #define RCC_SSCGR_INCSTEP RCC_SSCGR_INCSTEP_Msk
lypinator 0:bb348c97df44 4590 #define RCC_SSCGR_SPREADSEL_Pos (30U)
lypinator 0:bb348c97df44 4591 #define RCC_SSCGR_SPREADSEL_Msk (0x1U << RCC_SSCGR_SPREADSEL_Pos) /*!< 0x40000000 */
lypinator 0:bb348c97df44 4592 #define RCC_SSCGR_SPREADSEL RCC_SSCGR_SPREADSEL_Msk
lypinator 0:bb348c97df44 4593 #define RCC_SSCGR_SSCGEN_Pos (31U)
lypinator 0:bb348c97df44 4594 #define RCC_SSCGR_SSCGEN_Msk (0x1U << RCC_SSCGR_SSCGEN_Pos) /*!< 0x80000000 */
lypinator 0:bb348c97df44 4595 #define RCC_SSCGR_SSCGEN RCC_SSCGR_SSCGEN_Msk
lypinator 0:bb348c97df44 4596
lypinator 0:bb348c97df44 4597 /******************** Bit definition for RCC_PLLI2SCFGR register ************/
lypinator 0:bb348c97df44 4598 #define RCC_PLLI2SCFGR_PLLI2SM_Pos (0U)
lypinator 0:bb348c97df44 4599 #define RCC_PLLI2SCFGR_PLLI2SM_Msk (0x3FU << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x0000003F */
lypinator 0:bb348c97df44 4600 #define RCC_PLLI2SCFGR_PLLI2SM RCC_PLLI2SCFGR_PLLI2SM_Msk
lypinator 0:bb348c97df44 4601 #define RCC_PLLI2SCFGR_PLLI2SM_0 (0x01U << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 4602 #define RCC_PLLI2SCFGR_PLLI2SM_1 (0x02U << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 4603 #define RCC_PLLI2SCFGR_PLLI2SM_2 (0x04U << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 4604 #define RCC_PLLI2SCFGR_PLLI2SM_3 (0x08U << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 4605 #define RCC_PLLI2SCFGR_PLLI2SM_4 (0x10U << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 4606 #define RCC_PLLI2SCFGR_PLLI2SM_5 (0x20U << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 4607
lypinator 0:bb348c97df44 4608 #define RCC_PLLI2SCFGR_PLLI2SN_Pos (6U)
lypinator 0:bb348c97df44 4609 #define RCC_PLLI2SCFGR_PLLI2SN_Msk (0x1FFU << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00007FC0 */
lypinator 0:bb348c97df44 4610 #define RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN_Msk
lypinator 0:bb348c97df44 4611 #define RCC_PLLI2SCFGR_PLLI2SN_0 (0x001U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 4612 #define RCC_PLLI2SCFGR_PLLI2SN_1 (0x002U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 4613 #define RCC_PLLI2SCFGR_PLLI2SN_2 (0x004U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 4614 #define RCC_PLLI2SCFGR_PLLI2SN_3 (0x008U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 4615 #define RCC_PLLI2SCFGR_PLLI2SN_4 (0x010U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 4616 #define RCC_PLLI2SCFGR_PLLI2SN_5 (0x020U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 4617 #define RCC_PLLI2SCFGR_PLLI2SN_6 (0x040U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 4618 #define RCC_PLLI2SCFGR_PLLI2SN_7 (0x080U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 4619 #define RCC_PLLI2SCFGR_PLLI2SN_8 (0x100U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 4620
lypinator 0:bb348c97df44 4621 #define RCC_PLLI2SCFGR_PLLI2SR_Pos (28U)
lypinator 0:bb348c97df44 4622 #define RCC_PLLI2SCFGR_PLLI2SR_Msk (0x7U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x70000000 */
lypinator 0:bb348c97df44 4623 #define RCC_PLLI2SCFGR_PLLI2SR RCC_PLLI2SCFGR_PLLI2SR_Msk
lypinator 0:bb348c97df44 4624 #define RCC_PLLI2SCFGR_PLLI2SR_0 (0x1U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x10000000 */
lypinator 0:bb348c97df44 4625 #define RCC_PLLI2SCFGR_PLLI2SR_1 (0x2U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x20000000 */
lypinator 0:bb348c97df44 4626 #define RCC_PLLI2SCFGR_PLLI2SR_2 (0x4U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x40000000 */
lypinator 0:bb348c97df44 4627
lypinator 0:bb348c97df44 4628 /******************** Bit definition for RCC_DCKCFGR register ***************/
lypinator 0:bb348c97df44 4629
lypinator 0:bb348c97df44 4630 #define RCC_DCKCFGR_TIMPRE_Pos (24U)
lypinator 0:bb348c97df44 4631 #define RCC_DCKCFGR_TIMPRE_Msk (0x1U << RCC_DCKCFGR_TIMPRE_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 4632 #define RCC_DCKCFGR_TIMPRE RCC_DCKCFGR_TIMPRE_Msk
lypinator 0:bb348c97df44 4633
lypinator 0:bb348c97df44 4634
lypinator 0:bb348c97df44 4635 /******************************************************************************/
lypinator 0:bb348c97df44 4636 /* */
lypinator 0:bb348c97df44 4637 /* Real-Time Clock (RTC) */
lypinator 0:bb348c97df44 4638 /* */
lypinator 0:bb348c97df44 4639 /******************************************************************************/
lypinator 0:bb348c97df44 4640 /******************** Bits definition for RTC_TR register *******************/
lypinator 0:bb348c97df44 4641 #define RTC_TR_PM_Pos (22U)
lypinator 0:bb348c97df44 4642 #define RTC_TR_PM_Msk (0x1U << RTC_TR_PM_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 4643 #define RTC_TR_PM RTC_TR_PM_Msk
lypinator 0:bb348c97df44 4644 #define RTC_TR_HT_Pos (20U)
lypinator 0:bb348c97df44 4645 #define RTC_TR_HT_Msk (0x3U << RTC_TR_HT_Pos) /*!< 0x00300000 */
lypinator 0:bb348c97df44 4646 #define RTC_TR_HT RTC_TR_HT_Msk
lypinator 0:bb348c97df44 4647 #define RTC_TR_HT_0 (0x1U << RTC_TR_HT_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 4648 #define RTC_TR_HT_1 (0x2U << RTC_TR_HT_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 4649 #define RTC_TR_HU_Pos (16U)
lypinator 0:bb348c97df44 4650 #define RTC_TR_HU_Msk (0xFU << RTC_TR_HU_Pos) /*!< 0x000F0000 */
lypinator 0:bb348c97df44 4651 #define RTC_TR_HU RTC_TR_HU_Msk
lypinator 0:bb348c97df44 4652 #define RTC_TR_HU_0 (0x1U << RTC_TR_HU_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 4653 #define RTC_TR_HU_1 (0x2U << RTC_TR_HU_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 4654 #define RTC_TR_HU_2 (0x4U << RTC_TR_HU_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 4655 #define RTC_TR_HU_3 (0x8U << RTC_TR_HU_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 4656 #define RTC_TR_MNT_Pos (12U)
lypinator 0:bb348c97df44 4657 #define RTC_TR_MNT_Msk (0x7U << RTC_TR_MNT_Pos) /*!< 0x00007000 */
lypinator 0:bb348c97df44 4658 #define RTC_TR_MNT RTC_TR_MNT_Msk
lypinator 0:bb348c97df44 4659 #define RTC_TR_MNT_0 (0x1U << RTC_TR_MNT_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 4660 #define RTC_TR_MNT_1 (0x2U << RTC_TR_MNT_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 4661 #define RTC_TR_MNT_2 (0x4U << RTC_TR_MNT_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 4662 #define RTC_TR_MNU_Pos (8U)
lypinator 0:bb348c97df44 4663 #define RTC_TR_MNU_Msk (0xFU << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
lypinator 0:bb348c97df44 4664 #define RTC_TR_MNU RTC_TR_MNU_Msk
lypinator 0:bb348c97df44 4665 #define RTC_TR_MNU_0 (0x1U << RTC_TR_MNU_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 4666 #define RTC_TR_MNU_1 (0x2U << RTC_TR_MNU_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 4667 #define RTC_TR_MNU_2 (0x4U << RTC_TR_MNU_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 4668 #define RTC_TR_MNU_3 (0x8U << RTC_TR_MNU_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 4669 #define RTC_TR_ST_Pos (4U)
lypinator 0:bb348c97df44 4670 #define RTC_TR_ST_Msk (0x7U << RTC_TR_ST_Pos) /*!< 0x00000070 */
lypinator 0:bb348c97df44 4671 #define RTC_TR_ST RTC_TR_ST_Msk
lypinator 0:bb348c97df44 4672 #define RTC_TR_ST_0 (0x1U << RTC_TR_ST_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 4673 #define RTC_TR_ST_1 (0x2U << RTC_TR_ST_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 4674 #define RTC_TR_ST_2 (0x4U << RTC_TR_ST_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 4675 #define RTC_TR_SU_Pos (0U)
lypinator 0:bb348c97df44 4676 #define RTC_TR_SU_Msk (0xFU << RTC_TR_SU_Pos) /*!< 0x0000000F */
lypinator 0:bb348c97df44 4677 #define RTC_TR_SU RTC_TR_SU_Msk
lypinator 0:bb348c97df44 4678 #define RTC_TR_SU_0 (0x1U << RTC_TR_SU_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 4679 #define RTC_TR_SU_1 (0x2U << RTC_TR_SU_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 4680 #define RTC_TR_SU_2 (0x4U << RTC_TR_SU_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 4681 #define RTC_TR_SU_3 (0x8U << RTC_TR_SU_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 4682
lypinator 0:bb348c97df44 4683 /******************** Bits definition for RTC_DR register *******************/
lypinator 0:bb348c97df44 4684 #define RTC_DR_YT_Pos (20U)
lypinator 0:bb348c97df44 4685 #define RTC_DR_YT_Msk (0xFU << RTC_DR_YT_Pos) /*!< 0x00F00000 */
lypinator 0:bb348c97df44 4686 #define RTC_DR_YT RTC_DR_YT_Msk
lypinator 0:bb348c97df44 4687 #define RTC_DR_YT_0 (0x1U << RTC_DR_YT_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 4688 #define RTC_DR_YT_1 (0x2U << RTC_DR_YT_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 4689 #define RTC_DR_YT_2 (0x4U << RTC_DR_YT_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 4690 #define RTC_DR_YT_3 (0x8U << RTC_DR_YT_Pos) /*!< 0x00800000 */
lypinator 0:bb348c97df44 4691 #define RTC_DR_YU_Pos (16U)
lypinator 0:bb348c97df44 4692 #define RTC_DR_YU_Msk (0xFU << RTC_DR_YU_Pos) /*!< 0x000F0000 */
lypinator 0:bb348c97df44 4693 #define RTC_DR_YU RTC_DR_YU_Msk
lypinator 0:bb348c97df44 4694 #define RTC_DR_YU_0 (0x1U << RTC_DR_YU_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 4695 #define RTC_DR_YU_1 (0x2U << RTC_DR_YU_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 4696 #define RTC_DR_YU_2 (0x4U << RTC_DR_YU_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 4697 #define RTC_DR_YU_3 (0x8U << RTC_DR_YU_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 4698 #define RTC_DR_WDU_Pos (13U)
lypinator 0:bb348c97df44 4699 #define RTC_DR_WDU_Msk (0x7U << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
lypinator 0:bb348c97df44 4700 #define RTC_DR_WDU RTC_DR_WDU_Msk
lypinator 0:bb348c97df44 4701 #define RTC_DR_WDU_0 (0x1U << RTC_DR_WDU_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 4702 #define RTC_DR_WDU_1 (0x2U << RTC_DR_WDU_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 4703 #define RTC_DR_WDU_2 (0x4U << RTC_DR_WDU_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 4704 #define RTC_DR_MT_Pos (12U)
lypinator 0:bb348c97df44 4705 #define RTC_DR_MT_Msk (0x1U << RTC_DR_MT_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 4706 #define RTC_DR_MT RTC_DR_MT_Msk
lypinator 0:bb348c97df44 4707 #define RTC_DR_MU_Pos (8U)
lypinator 0:bb348c97df44 4708 #define RTC_DR_MU_Msk (0xFU << RTC_DR_MU_Pos) /*!< 0x00000F00 */
lypinator 0:bb348c97df44 4709 #define RTC_DR_MU RTC_DR_MU_Msk
lypinator 0:bb348c97df44 4710 #define RTC_DR_MU_0 (0x1U << RTC_DR_MU_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 4711 #define RTC_DR_MU_1 (0x2U << RTC_DR_MU_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 4712 #define RTC_DR_MU_2 (0x4U << RTC_DR_MU_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 4713 #define RTC_DR_MU_3 (0x8U << RTC_DR_MU_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 4714 #define RTC_DR_DT_Pos (4U)
lypinator 0:bb348c97df44 4715 #define RTC_DR_DT_Msk (0x3U << RTC_DR_DT_Pos) /*!< 0x00000030 */
lypinator 0:bb348c97df44 4716 #define RTC_DR_DT RTC_DR_DT_Msk
lypinator 0:bb348c97df44 4717 #define RTC_DR_DT_0 (0x1U << RTC_DR_DT_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 4718 #define RTC_DR_DT_1 (0x2U << RTC_DR_DT_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 4719 #define RTC_DR_DU_Pos (0U)
lypinator 0:bb348c97df44 4720 #define RTC_DR_DU_Msk (0xFU << RTC_DR_DU_Pos) /*!< 0x0000000F */
lypinator 0:bb348c97df44 4721 #define RTC_DR_DU RTC_DR_DU_Msk
lypinator 0:bb348c97df44 4722 #define RTC_DR_DU_0 (0x1U << RTC_DR_DU_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 4723 #define RTC_DR_DU_1 (0x2U << RTC_DR_DU_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 4724 #define RTC_DR_DU_2 (0x4U << RTC_DR_DU_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 4725 #define RTC_DR_DU_3 (0x8U << RTC_DR_DU_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 4726
lypinator 0:bb348c97df44 4727 /******************** Bits definition for RTC_CR register *******************/
lypinator 0:bb348c97df44 4728 #define RTC_CR_COE_Pos (23U)
lypinator 0:bb348c97df44 4729 #define RTC_CR_COE_Msk (0x1U << RTC_CR_COE_Pos) /*!< 0x00800000 */
lypinator 0:bb348c97df44 4730 #define RTC_CR_COE RTC_CR_COE_Msk
lypinator 0:bb348c97df44 4731 #define RTC_CR_OSEL_Pos (21U)
lypinator 0:bb348c97df44 4732 #define RTC_CR_OSEL_Msk (0x3U << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
lypinator 0:bb348c97df44 4733 #define RTC_CR_OSEL RTC_CR_OSEL_Msk
lypinator 0:bb348c97df44 4734 #define RTC_CR_OSEL_0 (0x1U << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 4735 #define RTC_CR_OSEL_1 (0x2U << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 4736 #define RTC_CR_POL_Pos (20U)
lypinator 0:bb348c97df44 4737 #define RTC_CR_POL_Msk (0x1U << RTC_CR_POL_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 4738 #define RTC_CR_POL RTC_CR_POL_Msk
lypinator 0:bb348c97df44 4739 #define RTC_CR_COSEL_Pos (19U)
lypinator 0:bb348c97df44 4740 #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 4741 #define RTC_CR_COSEL RTC_CR_COSEL_Msk
lypinator 0:bb348c97df44 4742 #define RTC_CR_BKP_Pos (18U)
lypinator 0:bb348c97df44 4743 #define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 4744 #define RTC_CR_BKP RTC_CR_BKP_Msk
lypinator 0:bb348c97df44 4745 #define RTC_CR_SUB1H_Pos (17U)
lypinator 0:bb348c97df44 4746 #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 4747 #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
lypinator 0:bb348c97df44 4748 #define RTC_CR_ADD1H_Pos (16U)
lypinator 0:bb348c97df44 4749 #define RTC_CR_ADD1H_Msk (0x1U << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 4750 #define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
lypinator 0:bb348c97df44 4751 #define RTC_CR_TSIE_Pos (15U)
lypinator 0:bb348c97df44 4752 #define RTC_CR_TSIE_Msk (0x1U << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 4753 #define RTC_CR_TSIE RTC_CR_TSIE_Msk
lypinator 0:bb348c97df44 4754 #define RTC_CR_WUTIE_Pos (14U)
lypinator 0:bb348c97df44 4755 #define RTC_CR_WUTIE_Msk (0x1U << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 4756 #define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
lypinator 0:bb348c97df44 4757 #define RTC_CR_ALRBIE_Pos (13U)
lypinator 0:bb348c97df44 4758 #define RTC_CR_ALRBIE_Msk (0x1U << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 4759 #define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
lypinator 0:bb348c97df44 4760 #define RTC_CR_ALRAIE_Pos (12U)
lypinator 0:bb348c97df44 4761 #define RTC_CR_ALRAIE_Msk (0x1U << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 4762 #define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
lypinator 0:bb348c97df44 4763 #define RTC_CR_TSE_Pos (11U)
lypinator 0:bb348c97df44 4764 #define RTC_CR_TSE_Msk (0x1U << RTC_CR_TSE_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 4765 #define RTC_CR_TSE RTC_CR_TSE_Msk
lypinator 0:bb348c97df44 4766 #define RTC_CR_WUTE_Pos (10U)
lypinator 0:bb348c97df44 4767 #define RTC_CR_WUTE_Msk (0x1U << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 4768 #define RTC_CR_WUTE RTC_CR_WUTE_Msk
lypinator 0:bb348c97df44 4769 #define RTC_CR_ALRBE_Pos (9U)
lypinator 0:bb348c97df44 4770 #define RTC_CR_ALRBE_Msk (0x1U << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 4771 #define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
lypinator 0:bb348c97df44 4772 #define RTC_CR_ALRAE_Pos (8U)
lypinator 0:bb348c97df44 4773 #define RTC_CR_ALRAE_Msk (0x1U << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 4774 #define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
lypinator 0:bb348c97df44 4775 #define RTC_CR_DCE_Pos (7U)
lypinator 0:bb348c97df44 4776 #define RTC_CR_DCE_Msk (0x1U << RTC_CR_DCE_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 4777 #define RTC_CR_DCE RTC_CR_DCE_Msk
lypinator 0:bb348c97df44 4778 #define RTC_CR_FMT_Pos (6U)
lypinator 0:bb348c97df44 4779 #define RTC_CR_FMT_Msk (0x1U << RTC_CR_FMT_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 4780 #define RTC_CR_FMT RTC_CR_FMT_Msk
lypinator 0:bb348c97df44 4781 #define RTC_CR_BYPSHAD_Pos (5U)
lypinator 0:bb348c97df44 4782 #define RTC_CR_BYPSHAD_Msk (0x1U << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 4783 #define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
lypinator 0:bb348c97df44 4784 #define RTC_CR_REFCKON_Pos (4U)
lypinator 0:bb348c97df44 4785 #define RTC_CR_REFCKON_Msk (0x1U << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 4786 #define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
lypinator 0:bb348c97df44 4787 #define RTC_CR_TSEDGE_Pos (3U)
lypinator 0:bb348c97df44 4788 #define RTC_CR_TSEDGE_Msk (0x1U << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 4789 #define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
lypinator 0:bb348c97df44 4790 #define RTC_CR_WUCKSEL_Pos (0U)
lypinator 0:bb348c97df44 4791 #define RTC_CR_WUCKSEL_Msk (0x7U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
lypinator 0:bb348c97df44 4792 #define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
lypinator 0:bb348c97df44 4793 #define RTC_CR_WUCKSEL_0 (0x1U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 4794 #define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 4795 #define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 4796
lypinator 0:bb348c97df44 4797 /* Legacy defines */
lypinator 0:bb348c97df44 4798 #define RTC_CR_BCK RTC_CR_BKP
lypinator 0:bb348c97df44 4799
lypinator 0:bb348c97df44 4800 /******************** Bits definition for RTC_ISR register ******************/
lypinator 0:bb348c97df44 4801 #define RTC_ISR_RECALPF_Pos (16U)
lypinator 0:bb348c97df44 4802 #define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 4803 #define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk
lypinator 0:bb348c97df44 4804 #define RTC_ISR_TAMP1F_Pos (13U)
lypinator 0:bb348c97df44 4805 #define RTC_ISR_TAMP1F_Msk (0x1U << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 4806 #define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk
lypinator 0:bb348c97df44 4807 #define RTC_ISR_TAMP2F_Pos (14U)
lypinator 0:bb348c97df44 4808 #define RTC_ISR_TAMP2F_Msk (0x1U << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 4809 #define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk
lypinator 0:bb348c97df44 4810 #define RTC_ISR_TSOVF_Pos (12U)
lypinator 0:bb348c97df44 4811 #define RTC_ISR_TSOVF_Msk (0x1U << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 4812 #define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
lypinator 0:bb348c97df44 4813 #define RTC_ISR_TSF_Pos (11U)
lypinator 0:bb348c97df44 4814 #define RTC_ISR_TSF_Msk (0x1U << RTC_ISR_TSF_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 4815 #define RTC_ISR_TSF RTC_ISR_TSF_Msk
lypinator 0:bb348c97df44 4816 #define RTC_ISR_WUTF_Pos (10U)
lypinator 0:bb348c97df44 4817 #define RTC_ISR_WUTF_Msk (0x1U << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 4818 #define RTC_ISR_WUTF RTC_ISR_WUTF_Msk
lypinator 0:bb348c97df44 4819 #define RTC_ISR_ALRBF_Pos (9U)
lypinator 0:bb348c97df44 4820 #define RTC_ISR_ALRBF_Msk (0x1U << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 4821 #define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk
lypinator 0:bb348c97df44 4822 #define RTC_ISR_ALRAF_Pos (8U)
lypinator 0:bb348c97df44 4823 #define RTC_ISR_ALRAF_Msk (0x1U << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 4824 #define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
lypinator 0:bb348c97df44 4825 #define RTC_ISR_INIT_Pos (7U)
lypinator 0:bb348c97df44 4826 #define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 4827 #define RTC_ISR_INIT RTC_ISR_INIT_Msk
lypinator 0:bb348c97df44 4828 #define RTC_ISR_INITF_Pos (6U)
lypinator 0:bb348c97df44 4829 #define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 4830 #define RTC_ISR_INITF RTC_ISR_INITF_Msk
lypinator 0:bb348c97df44 4831 #define RTC_ISR_RSF_Pos (5U)
lypinator 0:bb348c97df44 4832 #define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 4833 #define RTC_ISR_RSF RTC_ISR_RSF_Msk
lypinator 0:bb348c97df44 4834 #define RTC_ISR_INITS_Pos (4U)
lypinator 0:bb348c97df44 4835 #define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 4836 #define RTC_ISR_INITS RTC_ISR_INITS_Msk
lypinator 0:bb348c97df44 4837 #define RTC_ISR_SHPF_Pos (3U)
lypinator 0:bb348c97df44 4838 #define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 4839 #define RTC_ISR_SHPF RTC_ISR_SHPF_Msk
lypinator 0:bb348c97df44 4840 #define RTC_ISR_WUTWF_Pos (2U)
lypinator 0:bb348c97df44 4841 #define RTC_ISR_WUTWF_Msk (0x1U << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 4842 #define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk
lypinator 0:bb348c97df44 4843 #define RTC_ISR_ALRBWF_Pos (1U)
lypinator 0:bb348c97df44 4844 #define RTC_ISR_ALRBWF_Msk (0x1U << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 4845 #define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk
lypinator 0:bb348c97df44 4846 #define RTC_ISR_ALRAWF_Pos (0U)
lypinator 0:bb348c97df44 4847 #define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 4848 #define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
lypinator 0:bb348c97df44 4849
lypinator 0:bb348c97df44 4850 /******************** Bits definition for RTC_PRER register *****************/
lypinator 0:bb348c97df44 4851 #define RTC_PRER_PREDIV_A_Pos (16U)
lypinator 0:bb348c97df44 4852 #define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
lypinator 0:bb348c97df44 4853 #define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
lypinator 0:bb348c97df44 4854 #define RTC_PRER_PREDIV_S_Pos (0U)
lypinator 0:bb348c97df44 4855 #define RTC_PRER_PREDIV_S_Msk (0x7FFFU << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
lypinator 0:bb348c97df44 4856 #define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
lypinator 0:bb348c97df44 4857
lypinator 0:bb348c97df44 4858 /******************** Bits definition for RTC_WUTR register *****************/
lypinator 0:bb348c97df44 4859 #define RTC_WUTR_WUT_Pos (0U)
lypinator 0:bb348c97df44 4860 #define RTC_WUTR_WUT_Msk (0xFFFFU << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
lypinator 0:bb348c97df44 4861 #define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
lypinator 0:bb348c97df44 4862
lypinator 0:bb348c97df44 4863 /******************** Bits definition for RTC_CALIBR register ***************/
lypinator 0:bb348c97df44 4864 #define RTC_CALIBR_DCS_Pos (7U)
lypinator 0:bb348c97df44 4865 #define RTC_CALIBR_DCS_Msk (0x1U << RTC_CALIBR_DCS_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 4866 #define RTC_CALIBR_DCS RTC_CALIBR_DCS_Msk
lypinator 0:bb348c97df44 4867 #define RTC_CALIBR_DC_Pos (0U)
lypinator 0:bb348c97df44 4868 #define RTC_CALIBR_DC_Msk (0x1FU << RTC_CALIBR_DC_Pos) /*!< 0x0000001F */
lypinator 0:bb348c97df44 4869 #define RTC_CALIBR_DC RTC_CALIBR_DC_Msk
lypinator 0:bb348c97df44 4870
lypinator 0:bb348c97df44 4871 /******************** Bits definition for RTC_ALRMAR register ***************/
lypinator 0:bb348c97df44 4872 #define RTC_ALRMAR_MSK4_Pos (31U)
lypinator 0:bb348c97df44 4873 #define RTC_ALRMAR_MSK4_Msk (0x1U << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
lypinator 0:bb348c97df44 4874 #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
lypinator 0:bb348c97df44 4875 #define RTC_ALRMAR_WDSEL_Pos (30U)
lypinator 0:bb348c97df44 4876 #define RTC_ALRMAR_WDSEL_Msk (0x1U << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
lypinator 0:bb348c97df44 4877 #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
lypinator 0:bb348c97df44 4878 #define RTC_ALRMAR_DT_Pos (28U)
lypinator 0:bb348c97df44 4879 #define RTC_ALRMAR_DT_Msk (0x3U << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
lypinator 0:bb348c97df44 4880 #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
lypinator 0:bb348c97df44 4881 #define RTC_ALRMAR_DT_0 (0x1U << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
lypinator 0:bb348c97df44 4882 #define RTC_ALRMAR_DT_1 (0x2U << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
lypinator 0:bb348c97df44 4883 #define RTC_ALRMAR_DU_Pos (24U)
lypinator 0:bb348c97df44 4884 #define RTC_ALRMAR_DU_Msk (0xFU << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
lypinator 0:bb348c97df44 4885 #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
lypinator 0:bb348c97df44 4886 #define RTC_ALRMAR_DU_0 (0x1U << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 4887 #define RTC_ALRMAR_DU_1 (0x2U << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 4888 #define RTC_ALRMAR_DU_2 (0x4U << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
lypinator 0:bb348c97df44 4889 #define RTC_ALRMAR_DU_3 (0x8U << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
lypinator 0:bb348c97df44 4890 #define RTC_ALRMAR_MSK3_Pos (23U)
lypinator 0:bb348c97df44 4891 #define RTC_ALRMAR_MSK3_Msk (0x1U << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
lypinator 0:bb348c97df44 4892 #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
lypinator 0:bb348c97df44 4893 #define RTC_ALRMAR_PM_Pos (22U)
lypinator 0:bb348c97df44 4894 #define RTC_ALRMAR_PM_Msk (0x1U << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 4895 #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
lypinator 0:bb348c97df44 4896 #define RTC_ALRMAR_HT_Pos (20U)
lypinator 0:bb348c97df44 4897 #define RTC_ALRMAR_HT_Msk (0x3U << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
lypinator 0:bb348c97df44 4898 #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
lypinator 0:bb348c97df44 4899 #define RTC_ALRMAR_HT_0 (0x1U << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 4900 #define RTC_ALRMAR_HT_1 (0x2U << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 4901 #define RTC_ALRMAR_HU_Pos (16U)
lypinator 0:bb348c97df44 4902 #define RTC_ALRMAR_HU_Msk (0xFU << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
lypinator 0:bb348c97df44 4903 #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
lypinator 0:bb348c97df44 4904 #define RTC_ALRMAR_HU_0 (0x1U << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 4905 #define RTC_ALRMAR_HU_1 (0x2U << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 4906 #define RTC_ALRMAR_HU_2 (0x4U << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 4907 #define RTC_ALRMAR_HU_3 (0x8U << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 4908 #define RTC_ALRMAR_MSK2_Pos (15U)
lypinator 0:bb348c97df44 4909 #define RTC_ALRMAR_MSK2_Msk (0x1U << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 4910 #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
lypinator 0:bb348c97df44 4911 #define RTC_ALRMAR_MNT_Pos (12U)
lypinator 0:bb348c97df44 4912 #define RTC_ALRMAR_MNT_Msk (0x7U << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
lypinator 0:bb348c97df44 4913 #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
lypinator 0:bb348c97df44 4914 #define RTC_ALRMAR_MNT_0 (0x1U << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 4915 #define RTC_ALRMAR_MNT_1 (0x2U << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 4916 #define RTC_ALRMAR_MNT_2 (0x4U << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 4917 #define RTC_ALRMAR_MNU_Pos (8U)
lypinator 0:bb348c97df44 4918 #define RTC_ALRMAR_MNU_Msk (0xFU << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
lypinator 0:bb348c97df44 4919 #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
lypinator 0:bb348c97df44 4920 #define RTC_ALRMAR_MNU_0 (0x1U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 4921 #define RTC_ALRMAR_MNU_1 (0x2U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 4922 #define RTC_ALRMAR_MNU_2 (0x4U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 4923 #define RTC_ALRMAR_MNU_3 (0x8U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 4924 #define RTC_ALRMAR_MSK1_Pos (7U)
lypinator 0:bb348c97df44 4925 #define RTC_ALRMAR_MSK1_Msk (0x1U << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 4926 #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
lypinator 0:bb348c97df44 4927 #define RTC_ALRMAR_ST_Pos (4U)
lypinator 0:bb348c97df44 4928 #define RTC_ALRMAR_ST_Msk (0x7U << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
lypinator 0:bb348c97df44 4929 #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
lypinator 0:bb348c97df44 4930 #define RTC_ALRMAR_ST_0 (0x1U << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 4931 #define RTC_ALRMAR_ST_1 (0x2U << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 4932 #define RTC_ALRMAR_ST_2 (0x4U << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 4933 #define RTC_ALRMAR_SU_Pos (0U)
lypinator 0:bb348c97df44 4934 #define RTC_ALRMAR_SU_Msk (0xFU << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
lypinator 0:bb348c97df44 4935 #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
lypinator 0:bb348c97df44 4936 #define RTC_ALRMAR_SU_0 (0x1U << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 4937 #define RTC_ALRMAR_SU_1 (0x2U << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 4938 #define RTC_ALRMAR_SU_2 (0x4U << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 4939 #define RTC_ALRMAR_SU_3 (0x8U << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 4940
lypinator 0:bb348c97df44 4941 /******************** Bits definition for RTC_ALRMBR register ***************/
lypinator 0:bb348c97df44 4942 #define RTC_ALRMBR_MSK4_Pos (31U)
lypinator 0:bb348c97df44 4943 #define RTC_ALRMBR_MSK4_Msk (0x1U << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
lypinator 0:bb348c97df44 4944 #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
lypinator 0:bb348c97df44 4945 #define RTC_ALRMBR_WDSEL_Pos (30U)
lypinator 0:bb348c97df44 4946 #define RTC_ALRMBR_WDSEL_Msk (0x1U << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
lypinator 0:bb348c97df44 4947 #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
lypinator 0:bb348c97df44 4948 #define RTC_ALRMBR_DT_Pos (28U)
lypinator 0:bb348c97df44 4949 #define RTC_ALRMBR_DT_Msk (0x3U << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
lypinator 0:bb348c97df44 4950 #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
lypinator 0:bb348c97df44 4951 #define RTC_ALRMBR_DT_0 (0x1U << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
lypinator 0:bb348c97df44 4952 #define RTC_ALRMBR_DT_1 (0x2U << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
lypinator 0:bb348c97df44 4953 #define RTC_ALRMBR_DU_Pos (24U)
lypinator 0:bb348c97df44 4954 #define RTC_ALRMBR_DU_Msk (0xFU << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
lypinator 0:bb348c97df44 4955 #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
lypinator 0:bb348c97df44 4956 #define RTC_ALRMBR_DU_0 (0x1U << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 4957 #define RTC_ALRMBR_DU_1 (0x2U << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 4958 #define RTC_ALRMBR_DU_2 (0x4U << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
lypinator 0:bb348c97df44 4959 #define RTC_ALRMBR_DU_3 (0x8U << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
lypinator 0:bb348c97df44 4960 #define RTC_ALRMBR_MSK3_Pos (23U)
lypinator 0:bb348c97df44 4961 #define RTC_ALRMBR_MSK3_Msk (0x1U << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
lypinator 0:bb348c97df44 4962 #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
lypinator 0:bb348c97df44 4963 #define RTC_ALRMBR_PM_Pos (22U)
lypinator 0:bb348c97df44 4964 #define RTC_ALRMBR_PM_Msk (0x1U << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 4965 #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
lypinator 0:bb348c97df44 4966 #define RTC_ALRMBR_HT_Pos (20U)
lypinator 0:bb348c97df44 4967 #define RTC_ALRMBR_HT_Msk (0x3U << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
lypinator 0:bb348c97df44 4968 #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
lypinator 0:bb348c97df44 4969 #define RTC_ALRMBR_HT_0 (0x1U << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 4970 #define RTC_ALRMBR_HT_1 (0x2U << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 4971 #define RTC_ALRMBR_HU_Pos (16U)
lypinator 0:bb348c97df44 4972 #define RTC_ALRMBR_HU_Msk (0xFU << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
lypinator 0:bb348c97df44 4973 #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
lypinator 0:bb348c97df44 4974 #define RTC_ALRMBR_HU_0 (0x1U << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 4975 #define RTC_ALRMBR_HU_1 (0x2U << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 4976 #define RTC_ALRMBR_HU_2 (0x4U << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 4977 #define RTC_ALRMBR_HU_3 (0x8U << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 4978 #define RTC_ALRMBR_MSK2_Pos (15U)
lypinator 0:bb348c97df44 4979 #define RTC_ALRMBR_MSK2_Msk (0x1U << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 4980 #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
lypinator 0:bb348c97df44 4981 #define RTC_ALRMBR_MNT_Pos (12U)
lypinator 0:bb348c97df44 4982 #define RTC_ALRMBR_MNT_Msk (0x7U << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
lypinator 0:bb348c97df44 4983 #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
lypinator 0:bb348c97df44 4984 #define RTC_ALRMBR_MNT_0 (0x1U << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 4985 #define RTC_ALRMBR_MNT_1 (0x2U << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 4986 #define RTC_ALRMBR_MNT_2 (0x4U << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 4987 #define RTC_ALRMBR_MNU_Pos (8U)
lypinator 0:bb348c97df44 4988 #define RTC_ALRMBR_MNU_Msk (0xFU << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
lypinator 0:bb348c97df44 4989 #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
lypinator 0:bb348c97df44 4990 #define RTC_ALRMBR_MNU_0 (0x1U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 4991 #define RTC_ALRMBR_MNU_1 (0x2U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 4992 #define RTC_ALRMBR_MNU_2 (0x4U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 4993 #define RTC_ALRMBR_MNU_3 (0x8U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 4994 #define RTC_ALRMBR_MSK1_Pos (7U)
lypinator 0:bb348c97df44 4995 #define RTC_ALRMBR_MSK1_Msk (0x1U << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 4996 #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
lypinator 0:bb348c97df44 4997 #define RTC_ALRMBR_ST_Pos (4U)
lypinator 0:bb348c97df44 4998 #define RTC_ALRMBR_ST_Msk (0x7U << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
lypinator 0:bb348c97df44 4999 #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
lypinator 0:bb348c97df44 5000 #define RTC_ALRMBR_ST_0 (0x1U << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 5001 #define RTC_ALRMBR_ST_1 (0x2U << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 5002 #define RTC_ALRMBR_ST_2 (0x4U << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 5003 #define RTC_ALRMBR_SU_Pos (0U)
lypinator 0:bb348c97df44 5004 #define RTC_ALRMBR_SU_Msk (0xFU << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
lypinator 0:bb348c97df44 5005 #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
lypinator 0:bb348c97df44 5006 #define RTC_ALRMBR_SU_0 (0x1U << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 5007 #define RTC_ALRMBR_SU_1 (0x2U << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 5008 #define RTC_ALRMBR_SU_2 (0x4U << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 5009 #define RTC_ALRMBR_SU_3 (0x8U << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 5010
lypinator 0:bb348c97df44 5011 /******************** Bits definition for RTC_WPR register ******************/
lypinator 0:bb348c97df44 5012 #define RTC_WPR_KEY_Pos (0U)
lypinator 0:bb348c97df44 5013 #define RTC_WPR_KEY_Msk (0xFFU << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
lypinator 0:bb348c97df44 5014 #define RTC_WPR_KEY RTC_WPR_KEY_Msk
lypinator 0:bb348c97df44 5015
lypinator 0:bb348c97df44 5016 /******************** Bits definition for RTC_SSR register ******************/
lypinator 0:bb348c97df44 5017 #define RTC_SSR_SS_Pos (0U)
lypinator 0:bb348c97df44 5018 #define RTC_SSR_SS_Msk (0xFFFFU << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
lypinator 0:bb348c97df44 5019 #define RTC_SSR_SS RTC_SSR_SS_Msk
lypinator 0:bb348c97df44 5020
lypinator 0:bb348c97df44 5021 /******************** Bits definition for RTC_SHIFTR register ***************/
lypinator 0:bb348c97df44 5022 #define RTC_SHIFTR_SUBFS_Pos (0U)
lypinator 0:bb348c97df44 5023 #define RTC_SHIFTR_SUBFS_Msk (0x7FFFU << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
lypinator 0:bb348c97df44 5024 #define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
lypinator 0:bb348c97df44 5025 #define RTC_SHIFTR_ADD1S_Pos (31U)
lypinator 0:bb348c97df44 5026 #define RTC_SHIFTR_ADD1S_Msk (0x1U << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
lypinator 0:bb348c97df44 5027 #define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
lypinator 0:bb348c97df44 5028
lypinator 0:bb348c97df44 5029 /******************** Bits definition for RTC_TSTR register *****************/
lypinator 0:bb348c97df44 5030 #define RTC_TSTR_PM_Pos (22U)
lypinator 0:bb348c97df44 5031 #define RTC_TSTR_PM_Msk (0x1U << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 5032 #define RTC_TSTR_PM RTC_TSTR_PM_Msk
lypinator 0:bb348c97df44 5033 #define RTC_TSTR_HT_Pos (20U)
lypinator 0:bb348c97df44 5034 #define RTC_TSTR_HT_Msk (0x3U << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
lypinator 0:bb348c97df44 5035 #define RTC_TSTR_HT RTC_TSTR_HT_Msk
lypinator 0:bb348c97df44 5036 #define RTC_TSTR_HT_0 (0x1U << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 5037 #define RTC_TSTR_HT_1 (0x2U << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 5038 #define RTC_TSTR_HU_Pos (16U)
lypinator 0:bb348c97df44 5039 #define RTC_TSTR_HU_Msk (0xFU << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
lypinator 0:bb348c97df44 5040 #define RTC_TSTR_HU RTC_TSTR_HU_Msk
lypinator 0:bb348c97df44 5041 #define RTC_TSTR_HU_0 (0x1U << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 5042 #define RTC_TSTR_HU_1 (0x2U << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 5043 #define RTC_TSTR_HU_2 (0x4U << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 5044 #define RTC_TSTR_HU_3 (0x8U << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 5045 #define RTC_TSTR_MNT_Pos (12U)
lypinator 0:bb348c97df44 5046 #define RTC_TSTR_MNT_Msk (0x7U << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
lypinator 0:bb348c97df44 5047 #define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
lypinator 0:bb348c97df44 5048 #define RTC_TSTR_MNT_0 (0x1U << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 5049 #define RTC_TSTR_MNT_1 (0x2U << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 5050 #define RTC_TSTR_MNT_2 (0x4U << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 5051 #define RTC_TSTR_MNU_Pos (8U)
lypinator 0:bb348c97df44 5052 #define RTC_TSTR_MNU_Msk (0xFU << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
lypinator 0:bb348c97df44 5053 #define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
lypinator 0:bb348c97df44 5054 #define RTC_TSTR_MNU_0 (0x1U << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 5055 #define RTC_TSTR_MNU_1 (0x2U << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 5056 #define RTC_TSTR_MNU_2 (0x4U << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 5057 #define RTC_TSTR_MNU_3 (0x8U << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 5058 #define RTC_TSTR_ST_Pos (4U)
lypinator 0:bb348c97df44 5059 #define RTC_TSTR_ST_Msk (0x7U << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
lypinator 0:bb348c97df44 5060 #define RTC_TSTR_ST RTC_TSTR_ST_Msk
lypinator 0:bb348c97df44 5061 #define RTC_TSTR_ST_0 (0x1U << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 5062 #define RTC_TSTR_ST_1 (0x2U << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 5063 #define RTC_TSTR_ST_2 (0x4U << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 5064 #define RTC_TSTR_SU_Pos (0U)
lypinator 0:bb348c97df44 5065 #define RTC_TSTR_SU_Msk (0xFU << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
lypinator 0:bb348c97df44 5066 #define RTC_TSTR_SU RTC_TSTR_SU_Msk
lypinator 0:bb348c97df44 5067 #define RTC_TSTR_SU_0 (0x1U << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 5068 #define RTC_TSTR_SU_1 (0x2U << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 5069 #define RTC_TSTR_SU_2 (0x4U << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 5070 #define RTC_TSTR_SU_3 (0x8U << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 5071
lypinator 0:bb348c97df44 5072 /******************** Bits definition for RTC_TSDR register *****************/
lypinator 0:bb348c97df44 5073 #define RTC_TSDR_WDU_Pos (13U)
lypinator 0:bb348c97df44 5074 #define RTC_TSDR_WDU_Msk (0x7U << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
lypinator 0:bb348c97df44 5075 #define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
lypinator 0:bb348c97df44 5076 #define RTC_TSDR_WDU_0 (0x1U << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 5077 #define RTC_TSDR_WDU_1 (0x2U << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 5078 #define RTC_TSDR_WDU_2 (0x4U << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 5079 #define RTC_TSDR_MT_Pos (12U)
lypinator 0:bb348c97df44 5080 #define RTC_TSDR_MT_Msk (0x1U << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 5081 #define RTC_TSDR_MT RTC_TSDR_MT_Msk
lypinator 0:bb348c97df44 5082 #define RTC_TSDR_MU_Pos (8U)
lypinator 0:bb348c97df44 5083 #define RTC_TSDR_MU_Msk (0xFU << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
lypinator 0:bb348c97df44 5084 #define RTC_TSDR_MU RTC_TSDR_MU_Msk
lypinator 0:bb348c97df44 5085 #define RTC_TSDR_MU_0 (0x1U << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 5086 #define RTC_TSDR_MU_1 (0x2U << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 5087 #define RTC_TSDR_MU_2 (0x4U << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 5088 #define RTC_TSDR_MU_3 (0x8U << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 5089 #define RTC_TSDR_DT_Pos (4U)
lypinator 0:bb348c97df44 5090 #define RTC_TSDR_DT_Msk (0x3U << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
lypinator 0:bb348c97df44 5091 #define RTC_TSDR_DT RTC_TSDR_DT_Msk
lypinator 0:bb348c97df44 5092 #define RTC_TSDR_DT_0 (0x1U << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 5093 #define RTC_TSDR_DT_1 (0x2U << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 5094 #define RTC_TSDR_DU_Pos (0U)
lypinator 0:bb348c97df44 5095 #define RTC_TSDR_DU_Msk (0xFU << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
lypinator 0:bb348c97df44 5096 #define RTC_TSDR_DU RTC_TSDR_DU_Msk
lypinator 0:bb348c97df44 5097 #define RTC_TSDR_DU_0 (0x1U << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 5098 #define RTC_TSDR_DU_1 (0x2U << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 5099 #define RTC_TSDR_DU_2 (0x4U << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 5100 #define RTC_TSDR_DU_3 (0x8U << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 5101
lypinator 0:bb348c97df44 5102 /******************** Bits definition for RTC_TSSSR register ****************/
lypinator 0:bb348c97df44 5103 #define RTC_TSSSR_SS_Pos (0U)
lypinator 0:bb348c97df44 5104 #define RTC_TSSSR_SS_Msk (0xFFFFU << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
lypinator 0:bb348c97df44 5105 #define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
lypinator 0:bb348c97df44 5106
lypinator 0:bb348c97df44 5107 /******************** Bits definition for RTC_CAL register *****************/
lypinator 0:bb348c97df44 5108 #define RTC_CALR_CALP_Pos (15U)
lypinator 0:bb348c97df44 5109 #define RTC_CALR_CALP_Msk (0x1U << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 5110 #define RTC_CALR_CALP RTC_CALR_CALP_Msk
lypinator 0:bb348c97df44 5111 #define RTC_CALR_CALW8_Pos (14U)
lypinator 0:bb348c97df44 5112 #define RTC_CALR_CALW8_Msk (0x1U << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 5113 #define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
lypinator 0:bb348c97df44 5114 #define RTC_CALR_CALW16_Pos (13U)
lypinator 0:bb348c97df44 5115 #define RTC_CALR_CALW16_Msk (0x1U << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 5116 #define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
lypinator 0:bb348c97df44 5117 #define RTC_CALR_CALM_Pos (0U)
lypinator 0:bb348c97df44 5118 #define RTC_CALR_CALM_Msk (0x1FFU << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
lypinator 0:bb348c97df44 5119 #define RTC_CALR_CALM RTC_CALR_CALM_Msk
lypinator 0:bb348c97df44 5120 #define RTC_CALR_CALM_0 (0x001U << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 5121 #define RTC_CALR_CALM_1 (0x002U << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 5122 #define RTC_CALR_CALM_2 (0x004U << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 5123 #define RTC_CALR_CALM_3 (0x008U << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 5124 #define RTC_CALR_CALM_4 (0x010U << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 5125 #define RTC_CALR_CALM_5 (0x020U << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 5126 #define RTC_CALR_CALM_6 (0x040U << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 5127 #define RTC_CALR_CALM_7 (0x080U << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 5128 #define RTC_CALR_CALM_8 (0x100U << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 5129
lypinator 0:bb348c97df44 5130 /******************** Bits definition for RTC_TAFCR register ****************/
lypinator 0:bb348c97df44 5131 #define RTC_TAFCR_ALARMOUTTYPE_Pos (18U)
lypinator 0:bb348c97df44 5132 #define RTC_TAFCR_ALARMOUTTYPE_Msk (0x1U << RTC_TAFCR_ALARMOUTTYPE_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 5133 #define RTC_TAFCR_ALARMOUTTYPE RTC_TAFCR_ALARMOUTTYPE_Msk
lypinator 0:bb348c97df44 5134 #define RTC_TAFCR_TSINSEL_Pos (17U)
lypinator 0:bb348c97df44 5135 #define RTC_TAFCR_TSINSEL_Msk (0x1U << RTC_TAFCR_TSINSEL_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 5136 #define RTC_TAFCR_TSINSEL RTC_TAFCR_TSINSEL_Msk
lypinator 0:bb348c97df44 5137 #define RTC_TAFCR_TAMP1INSEL_Pos (16U)
lypinator 0:bb348c97df44 5138 #define RTC_TAFCR_TAMP1INSEL_Msk (0x1U << RTC_TAFCR_TAMP1INSEL_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 5139 #define RTC_TAFCR_TAMP1INSEL RTC_TAFCR_TAMP1INSEL_Msk
lypinator 0:bb348c97df44 5140 #define RTC_TAFCR_TAMPPUDIS_Pos (15U)
lypinator 0:bb348c97df44 5141 #define RTC_TAFCR_TAMPPUDIS_Msk (0x1U << RTC_TAFCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 5142 #define RTC_TAFCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS_Msk
lypinator 0:bb348c97df44 5143 #define RTC_TAFCR_TAMPPRCH_Pos (13U)
lypinator 0:bb348c97df44 5144 #define RTC_TAFCR_TAMPPRCH_Msk (0x3U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00006000 */
lypinator 0:bb348c97df44 5145 #define RTC_TAFCR_TAMPPRCH RTC_TAFCR_TAMPPRCH_Msk
lypinator 0:bb348c97df44 5146 #define RTC_TAFCR_TAMPPRCH_0 (0x1U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 5147 #define RTC_TAFCR_TAMPPRCH_1 (0x2U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 5148 #define RTC_TAFCR_TAMPFLT_Pos (11U)
lypinator 0:bb348c97df44 5149 #define RTC_TAFCR_TAMPFLT_Msk (0x3U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001800 */
lypinator 0:bb348c97df44 5150 #define RTC_TAFCR_TAMPFLT RTC_TAFCR_TAMPFLT_Msk
lypinator 0:bb348c97df44 5151 #define RTC_TAFCR_TAMPFLT_0 (0x1U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 5152 #define RTC_TAFCR_TAMPFLT_1 (0x2U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 5153 #define RTC_TAFCR_TAMPFREQ_Pos (8U)
lypinator 0:bb348c97df44 5154 #define RTC_TAFCR_TAMPFREQ_Msk (0x7U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000700 */
lypinator 0:bb348c97df44 5155 #define RTC_TAFCR_TAMPFREQ RTC_TAFCR_TAMPFREQ_Msk
lypinator 0:bb348c97df44 5156 #define RTC_TAFCR_TAMPFREQ_0 (0x1U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 5157 #define RTC_TAFCR_TAMPFREQ_1 (0x2U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 5158 #define RTC_TAFCR_TAMPFREQ_2 (0x4U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 5159 #define RTC_TAFCR_TAMPTS_Pos (7U)
lypinator 0:bb348c97df44 5160 #define RTC_TAFCR_TAMPTS_Msk (0x1U << RTC_TAFCR_TAMPTS_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 5161 #define RTC_TAFCR_TAMPTS RTC_TAFCR_TAMPTS_Msk
lypinator 0:bb348c97df44 5162 #define RTC_TAFCR_TAMP2TRG_Pos (4U)
lypinator 0:bb348c97df44 5163 #define RTC_TAFCR_TAMP2TRG_Msk (0x1U << RTC_TAFCR_TAMP2TRG_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 5164 #define RTC_TAFCR_TAMP2TRG RTC_TAFCR_TAMP2TRG_Msk
lypinator 0:bb348c97df44 5165 #define RTC_TAFCR_TAMP2E_Pos (3U)
lypinator 0:bb348c97df44 5166 #define RTC_TAFCR_TAMP2E_Msk (0x1U << RTC_TAFCR_TAMP2E_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 5167 #define RTC_TAFCR_TAMP2E RTC_TAFCR_TAMP2E_Msk
lypinator 0:bb348c97df44 5168 #define RTC_TAFCR_TAMPIE_Pos (2U)
lypinator 0:bb348c97df44 5169 #define RTC_TAFCR_TAMPIE_Msk (0x1U << RTC_TAFCR_TAMPIE_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 5170 #define RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk
lypinator 0:bb348c97df44 5171 #define RTC_TAFCR_TAMP1TRG_Pos (1U)
lypinator 0:bb348c97df44 5172 #define RTC_TAFCR_TAMP1TRG_Msk (0x1U << RTC_TAFCR_TAMP1TRG_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 5173 #define RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk
lypinator 0:bb348c97df44 5174 #define RTC_TAFCR_TAMP1E_Pos (0U)
lypinator 0:bb348c97df44 5175 #define RTC_TAFCR_TAMP1E_Msk (0x1U << RTC_TAFCR_TAMP1E_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 5176 #define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk
lypinator 0:bb348c97df44 5177
lypinator 0:bb348c97df44 5178 /* Legacy defines */
lypinator 0:bb348c97df44 5179 #define RTC_TAFCR_TAMPINSEL RTC_TAFCR_TAMP1INSEL
lypinator 0:bb348c97df44 5180
lypinator 0:bb348c97df44 5181 /******************** Bits definition for RTC_ALRMASSR register *************/
lypinator 0:bb348c97df44 5182 #define RTC_ALRMASSR_MASKSS_Pos (24U)
lypinator 0:bb348c97df44 5183 #define RTC_ALRMASSR_MASKSS_Msk (0xFU << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
lypinator 0:bb348c97df44 5184 #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
lypinator 0:bb348c97df44 5185 #define RTC_ALRMASSR_MASKSS_0 (0x1U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 5186 #define RTC_ALRMASSR_MASKSS_1 (0x2U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 5187 #define RTC_ALRMASSR_MASKSS_2 (0x4U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
lypinator 0:bb348c97df44 5188 #define RTC_ALRMASSR_MASKSS_3 (0x8U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
lypinator 0:bb348c97df44 5189 #define RTC_ALRMASSR_SS_Pos (0U)
lypinator 0:bb348c97df44 5190 #define RTC_ALRMASSR_SS_Msk (0x7FFFU << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
lypinator 0:bb348c97df44 5191 #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
lypinator 0:bb348c97df44 5192
lypinator 0:bb348c97df44 5193 /******************** Bits definition for RTC_ALRMBSSR register *************/
lypinator 0:bb348c97df44 5194 #define RTC_ALRMBSSR_MASKSS_Pos (24U)
lypinator 0:bb348c97df44 5195 #define RTC_ALRMBSSR_MASKSS_Msk (0xFU << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
lypinator 0:bb348c97df44 5196 #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
lypinator 0:bb348c97df44 5197 #define RTC_ALRMBSSR_MASKSS_0 (0x1U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 5198 #define RTC_ALRMBSSR_MASKSS_1 (0x2U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 5199 #define RTC_ALRMBSSR_MASKSS_2 (0x4U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
lypinator 0:bb348c97df44 5200 #define RTC_ALRMBSSR_MASKSS_3 (0x8U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
lypinator 0:bb348c97df44 5201 #define RTC_ALRMBSSR_SS_Pos (0U)
lypinator 0:bb348c97df44 5202 #define RTC_ALRMBSSR_SS_Msk (0x7FFFU << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
lypinator 0:bb348c97df44 5203 #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
lypinator 0:bb348c97df44 5204
lypinator 0:bb348c97df44 5205 /******************** Bits definition for RTC_BKP0R register ****************/
lypinator 0:bb348c97df44 5206 #define RTC_BKP0R_Pos (0U)
lypinator 0:bb348c97df44 5207 #define RTC_BKP0R_Msk (0xFFFFFFFFU << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */
lypinator 0:bb348c97df44 5208 #define RTC_BKP0R RTC_BKP0R_Msk
lypinator 0:bb348c97df44 5209
lypinator 0:bb348c97df44 5210 /******************** Bits definition for RTC_BKP1R register ****************/
lypinator 0:bb348c97df44 5211 #define RTC_BKP1R_Pos (0U)
lypinator 0:bb348c97df44 5212 #define RTC_BKP1R_Msk (0xFFFFFFFFU << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */
lypinator 0:bb348c97df44 5213 #define RTC_BKP1R RTC_BKP1R_Msk
lypinator 0:bb348c97df44 5214
lypinator 0:bb348c97df44 5215 /******************** Bits definition for RTC_BKP2R register ****************/
lypinator 0:bb348c97df44 5216 #define RTC_BKP2R_Pos (0U)
lypinator 0:bb348c97df44 5217 #define RTC_BKP2R_Msk (0xFFFFFFFFU << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */
lypinator 0:bb348c97df44 5218 #define RTC_BKP2R RTC_BKP2R_Msk
lypinator 0:bb348c97df44 5219
lypinator 0:bb348c97df44 5220 /******************** Bits definition for RTC_BKP3R register ****************/
lypinator 0:bb348c97df44 5221 #define RTC_BKP3R_Pos (0U)
lypinator 0:bb348c97df44 5222 #define RTC_BKP3R_Msk (0xFFFFFFFFU << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */
lypinator 0:bb348c97df44 5223 #define RTC_BKP3R RTC_BKP3R_Msk
lypinator 0:bb348c97df44 5224
lypinator 0:bb348c97df44 5225 /******************** Bits definition for RTC_BKP4R register ****************/
lypinator 0:bb348c97df44 5226 #define RTC_BKP4R_Pos (0U)
lypinator 0:bb348c97df44 5227 #define RTC_BKP4R_Msk (0xFFFFFFFFU << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */
lypinator 0:bb348c97df44 5228 #define RTC_BKP4R RTC_BKP4R_Msk
lypinator 0:bb348c97df44 5229
lypinator 0:bb348c97df44 5230 /******************** Bits definition for RTC_BKP5R register ****************/
lypinator 0:bb348c97df44 5231 #define RTC_BKP5R_Pos (0U)
lypinator 0:bb348c97df44 5232 #define RTC_BKP5R_Msk (0xFFFFFFFFU << RTC_BKP5R_Pos) /*!< 0xFFFFFFFF */
lypinator 0:bb348c97df44 5233 #define RTC_BKP5R RTC_BKP5R_Msk
lypinator 0:bb348c97df44 5234
lypinator 0:bb348c97df44 5235 /******************** Bits definition for RTC_BKP6R register ****************/
lypinator 0:bb348c97df44 5236 #define RTC_BKP6R_Pos (0U)
lypinator 0:bb348c97df44 5237 #define RTC_BKP6R_Msk (0xFFFFFFFFU << RTC_BKP6R_Pos) /*!< 0xFFFFFFFF */
lypinator 0:bb348c97df44 5238 #define RTC_BKP6R RTC_BKP6R_Msk
lypinator 0:bb348c97df44 5239
lypinator 0:bb348c97df44 5240 /******************** Bits definition for RTC_BKP7R register ****************/
lypinator 0:bb348c97df44 5241 #define RTC_BKP7R_Pos (0U)
lypinator 0:bb348c97df44 5242 #define RTC_BKP7R_Msk (0xFFFFFFFFU << RTC_BKP7R_Pos) /*!< 0xFFFFFFFF */
lypinator 0:bb348c97df44 5243 #define RTC_BKP7R RTC_BKP7R_Msk
lypinator 0:bb348c97df44 5244
lypinator 0:bb348c97df44 5245 /******************** Bits definition for RTC_BKP8R register ****************/
lypinator 0:bb348c97df44 5246 #define RTC_BKP8R_Pos (0U)
lypinator 0:bb348c97df44 5247 #define RTC_BKP8R_Msk (0xFFFFFFFFU << RTC_BKP8R_Pos) /*!< 0xFFFFFFFF */
lypinator 0:bb348c97df44 5248 #define RTC_BKP8R RTC_BKP8R_Msk
lypinator 0:bb348c97df44 5249
lypinator 0:bb348c97df44 5250 /******************** Bits definition for RTC_BKP9R register ****************/
lypinator 0:bb348c97df44 5251 #define RTC_BKP9R_Pos (0U)
lypinator 0:bb348c97df44 5252 #define RTC_BKP9R_Msk (0xFFFFFFFFU << RTC_BKP9R_Pos) /*!< 0xFFFFFFFF */
lypinator 0:bb348c97df44 5253 #define RTC_BKP9R RTC_BKP9R_Msk
lypinator 0:bb348c97df44 5254
lypinator 0:bb348c97df44 5255 /******************** Bits definition for RTC_BKP10R register ***************/
lypinator 0:bb348c97df44 5256 #define RTC_BKP10R_Pos (0U)
lypinator 0:bb348c97df44 5257 #define RTC_BKP10R_Msk (0xFFFFFFFFU << RTC_BKP10R_Pos) /*!< 0xFFFFFFFF */
lypinator 0:bb348c97df44 5258 #define RTC_BKP10R RTC_BKP10R_Msk
lypinator 0:bb348c97df44 5259
lypinator 0:bb348c97df44 5260 /******************** Bits definition for RTC_BKP11R register ***************/
lypinator 0:bb348c97df44 5261 #define RTC_BKP11R_Pos (0U)
lypinator 0:bb348c97df44 5262 #define RTC_BKP11R_Msk (0xFFFFFFFFU << RTC_BKP11R_Pos) /*!< 0xFFFFFFFF */
lypinator 0:bb348c97df44 5263 #define RTC_BKP11R RTC_BKP11R_Msk
lypinator 0:bb348c97df44 5264
lypinator 0:bb348c97df44 5265 /******************** Bits definition for RTC_BKP12R register ***************/
lypinator 0:bb348c97df44 5266 #define RTC_BKP12R_Pos (0U)
lypinator 0:bb348c97df44 5267 #define RTC_BKP12R_Msk (0xFFFFFFFFU << RTC_BKP12R_Pos) /*!< 0xFFFFFFFF */
lypinator 0:bb348c97df44 5268 #define RTC_BKP12R RTC_BKP12R_Msk
lypinator 0:bb348c97df44 5269
lypinator 0:bb348c97df44 5270 /******************** Bits definition for RTC_BKP13R register ***************/
lypinator 0:bb348c97df44 5271 #define RTC_BKP13R_Pos (0U)
lypinator 0:bb348c97df44 5272 #define RTC_BKP13R_Msk (0xFFFFFFFFU << RTC_BKP13R_Pos) /*!< 0xFFFFFFFF */
lypinator 0:bb348c97df44 5273 #define RTC_BKP13R RTC_BKP13R_Msk
lypinator 0:bb348c97df44 5274
lypinator 0:bb348c97df44 5275 /******************** Bits definition for RTC_BKP14R register ***************/
lypinator 0:bb348c97df44 5276 #define RTC_BKP14R_Pos (0U)
lypinator 0:bb348c97df44 5277 #define RTC_BKP14R_Msk (0xFFFFFFFFU << RTC_BKP14R_Pos) /*!< 0xFFFFFFFF */
lypinator 0:bb348c97df44 5278 #define RTC_BKP14R RTC_BKP14R_Msk
lypinator 0:bb348c97df44 5279
lypinator 0:bb348c97df44 5280 /******************** Bits definition for RTC_BKP15R register ***************/
lypinator 0:bb348c97df44 5281 #define RTC_BKP15R_Pos (0U)
lypinator 0:bb348c97df44 5282 #define RTC_BKP15R_Msk (0xFFFFFFFFU << RTC_BKP15R_Pos) /*!< 0xFFFFFFFF */
lypinator 0:bb348c97df44 5283 #define RTC_BKP15R RTC_BKP15R_Msk
lypinator 0:bb348c97df44 5284
lypinator 0:bb348c97df44 5285 /******************** Bits definition for RTC_BKP16R register ***************/
lypinator 0:bb348c97df44 5286 #define RTC_BKP16R_Pos (0U)
lypinator 0:bb348c97df44 5287 #define RTC_BKP16R_Msk (0xFFFFFFFFU << RTC_BKP16R_Pos) /*!< 0xFFFFFFFF */
lypinator 0:bb348c97df44 5288 #define RTC_BKP16R RTC_BKP16R_Msk
lypinator 0:bb348c97df44 5289
lypinator 0:bb348c97df44 5290 /******************** Bits definition for RTC_BKP17R register ***************/
lypinator 0:bb348c97df44 5291 #define RTC_BKP17R_Pos (0U)
lypinator 0:bb348c97df44 5292 #define RTC_BKP17R_Msk (0xFFFFFFFFU << RTC_BKP17R_Pos) /*!< 0xFFFFFFFF */
lypinator 0:bb348c97df44 5293 #define RTC_BKP17R RTC_BKP17R_Msk
lypinator 0:bb348c97df44 5294
lypinator 0:bb348c97df44 5295 /******************** Bits definition for RTC_BKP18R register ***************/
lypinator 0:bb348c97df44 5296 #define RTC_BKP18R_Pos (0U)
lypinator 0:bb348c97df44 5297 #define RTC_BKP18R_Msk (0xFFFFFFFFU << RTC_BKP18R_Pos) /*!< 0xFFFFFFFF */
lypinator 0:bb348c97df44 5298 #define RTC_BKP18R RTC_BKP18R_Msk
lypinator 0:bb348c97df44 5299
lypinator 0:bb348c97df44 5300 /******************** Bits definition for RTC_BKP19R register ***************/
lypinator 0:bb348c97df44 5301 #define RTC_BKP19R_Pos (0U)
lypinator 0:bb348c97df44 5302 #define RTC_BKP19R_Msk (0xFFFFFFFFU << RTC_BKP19R_Pos) /*!< 0xFFFFFFFF */
lypinator 0:bb348c97df44 5303 #define RTC_BKP19R RTC_BKP19R_Msk
lypinator 0:bb348c97df44 5304
lypinator 0:bb348c97df44 5305 /******************** Number of backup registers ******************************/
lypinator 0:bb348c97df44 5306 #define RTC_BKP_NUMBER 0x000000014U
lypinator 0:bb348c97df44 5307
lypinator 0:bb348c97df44 5308
lypinator 0:bb348c97df44 5309 /******************************************************************************/
lypinator 0:bb348c97df44 5310 /* */
lypinator 0:bb348c97df44 5311 /* SD host Interface */
lypinator 0:bb348c97df44 5312 /* */
lypinator 0:bb348c97df44 5313 /******************************************************************************/
lypinator 0:bb348c97df44 5314 /****************** Bit definition for SDIO_POWER register ******************/
lypinator 0:bb348c97df44 5315 #define SDIO_POWER_PWRCTRL_Pos (0U)
lypinator 0:bb348c97df44 5316 #define SDIO_POWER_PWRCTRL_Msk (0x3U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x00000003 */
lypinator 0:bb348c97df44 5317 #define SDIO_POWER_PWRCTRL SDIO_POWER_PWRCTRL_Msk /*!<PWRCTRL[1:0] bits (Power supply control bits) */
lypinator 0:bb348c97df44 5318 #define SDIO_POWER_PWRCTRL_0 (0x1U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x01 */
lypinator 0:bb348c97df44 5319 #define SDIO_POWER_PWRCTRL_1 (0x2U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x02 */
lypinator 0:bb348c97df44 5320
lypinator 0:bb348c97df44 5321 /****************** Bit definition for SDIO_CLKCR register ******************/
lypinator 0:bb348c97df44 5322 #define SDIO_CLKCR_CLKDIV_Pos (0U)
lypinator 0:bb348c97df44 5323 #define SDIO_CLKCR_CLKDIV_Msk (0xFFU << SDIO_CLKCR_CLKDIV_Pos) /*!< 0x000000FF */
lypinator 0:bb348c97df44 5324 #define SDIO_CLKCR_CLKDIV SDIO_CLKCR_CLKDIV_Msk /*!<Clock divide factor */
lypinator 0:bb348c97df44 5325 #define SDIO_CLKCR_CLKEN_Pos (8U)
lypinator 0:bb348c97df44 5326 #define SDIO_CLKCR_CLKEN_Msk (0x1U << SDIO_CLKCR_CLKEN_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 5327 #define SDIO_CLKCR_CLKEN SDIO_CLKCR_CLKEN_Msk /*!<Clock enable bit */
lypinator 0:bb348c97df44 5328 #define SDIO_CLKCR_PWRSAV_Pos (9U)
lypinator 0:bb348c97df44 5329 #define SDIO_CLKCR_PWRSAV_Msk (0x1U << SDIO_CLKCR_PWRSAV_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 5330 #define SDIO_CLKCR_PWRSAV SDIO_CLKCR_PWRSAV_Msk /*!<Power saving configuration bit */
lypinator 0:bb348c97df44 5331 #define SDIO_CLKCR_BYPASS_Pos (10U)
lypinator 0:bb348c97df44 5332 #define SDIO_CLKCR_BYPASS_Msk (0x1U << SDIO_CLKCR_BYPASS_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 5333 #define SDIO_CLKCR_BYPASS SDIO_CLKCR_BYPASS_Msk /*!<Clock divider bypass enable bit */
lypinator 0:bb348c97df44 5334
lypinator 0:bb348c97df44 5335 #define SDIO_CLKCR_WIDBUS_Pos (11U)
lypinator 0:bb348c97df44 5336 #define SDIO_CLKCR_WIDBUS_Msk (0x3U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x00001800 */
lypinator 0:bb348c97df44 5337 #define SDIO_CLKCR_WIDBUS SDIO_CLKCR_WIDBUS_Msk /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
lypinator 0:bb348c97df44 5338 #define SDIO_CLKCR_WIDBUS_0 (0x1U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x0800 */
lypinator 0:bb348c97df44 5339 #define SDIO_CLKCR_WIDBUS_1 (0x2U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x1000 */
lypinator 0:bb348c97df44 5340
lypinator 0:bb348c97df44 5341 #define SDIO_CLKCR_NEGEDGE_Pos (13U)
lypinator 0:bb348c97df44 5342 #define SDIO_CLKCR_NEGEDGE_Msk (0x1U << SDIO_CLKCR_NEGEDGE_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 5343 #define SDIO_CLKCR_NEGEDGE SDIO_CLKCR_NEGEDGE_Msk /*!<SDIO_CK dephasing selection bit */
lypinator 0:bb348c97df44 5344 #define SDIO_CLKCR_HWFC_EN_Pos (14U)
lypinator 0:bb348c97df44 5345 #define SDIO_CLKCR_HWFC_EN_Msk (0x1U << SDIO_CLKCR_HWFC_EN_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 5346 #define SDIO_CLKCR_HWFC_EN SDIO_CLKCR_HWFC_EN_Msk /*!<HW Flow Control enable */
lypinator 0:bb348c97df44 5347
lypinator 0:bb348c97df44 5348 /******************* Bit definition for SDIO_ARG register *******************/
lypinator 0:bb348c97df44 5349 #define SDIO_ARG_CMDARG_Pos (0U)
lypinator 0:bb348c97df44 5350 #define SDIO_ARG_CMDARG_Msk (0xFFFFFFFFU << SDIO_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */
lypinator 0:bb348c97df44 5351 #define SDIO_ARG_CMDARG SDIO_ARG_CMDARG_Msk /*!<Command argument */
lypinator 0:bb348c97df44 5352
lypinator 0:bb348c97df44 5353 /******************* Bit definition for SDIO_CMD register *******************/
lypinator 0:bb348c97df44 5354 #define SDIO_CMD_CMDINDEX_Pos (0U)
lypinator 0:bb348c97df44 5355 #define SDIO_CMD_CMDINDEX_Msk (0x3FU << SDIO_CMD_CMDINDEX_Pos) /*!< 0x0000003F */
lypinator 0:bb348c97df44 5356 #define SDIO_CMD_CMDINDEX SDIO_CMD_CMDINDEX_Msk /*!<Command Index */
lypinator 0:bb348c97df44 5357
lypinator 0:bb348c97df44 5358 #define SDIO_CMD_WAITRESP_Pos (6U)
lypinator 0:bb348c97df44 5359 #define SDIO_CMD_WAITRESP_Msk (0x3U << SDIO_CMD_WAITRESP_Pos) /*!< 0x000000C0 */
lypinator 0:bb348c97df44 5360 #define SDIO_CMD_WAITRESP SDIO_CMD_WAITRESP_Msk /*!<WAITRESP[1:0] bits (Wait for response bits) */
lypinator 0:bb348c97df44 5361 #define SDIO_CMD_WAITRESP_0 (0x1U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0040 */
lypinator 0:bb348c97df44 5362 #define SDIO_CMD_WAITRESP_1 (0x2U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0080 */
lypinator 0:bb348c97df44 5363
lypinator 0:bb348c97df44 5364 #define SDIO_CMD_WAITINT_Pos (8U)
lypinator 0:bb348c97df44 5365 #define SDIO_CMD_WAITINT_Msk (0x1U << SDIO_CMD_WAITINT_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 5366 #define SDIO_CMD_WAITINT SDIO_CMD_WAITINT_Msk /*!<CPSM Waits for Interrupt Request */
lypinator 0:bb348c97df44 5367 #define SDIO_CMD_WAITPEND_Pos (9U)
lypinator 0:bb348c97df44 5368 #define SDIO_CMD_WAITPEND_Msk (0x1U << SDIO_CMD_WAITPEND_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 5369 #define SDIO_CMD_WAITPEND SDIO_CMD_WAITPEND_Msk /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
lypinator 0:bb348c97df44 5370 #define SDIO_CMD_CPSMEN_Pos (10U)
lypinator 0:bb348c97df44 5371 #define SDIO_CMD_CPSMEN_Msk (0x1U << SDIO_CMD_CPSMEN_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 5372 #define SDIO_CMD_CPSMEN SDIO_CMD_CPSMEN_Msk /*!<Command path state machine (CPSM) Enable bit */
lypinator 0:bb348c97df44 5373 #define SDIO_CMD_SDIOSUSPEND_Pos (11U)
lypinator 0:bb348c97df44 5374 #define SDIO_CMD_SDIOSUSPEND_Msk (0x1U << SDIO_CMD_SDIOSUSPEND_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 5375 #define SDIO_CMD_SDIOSUSPEND SDIO_CMD_SDIOSUSPEND_Msk /*!<SD I/O suspend command */
lypinator 0:bb348c97df44 5376 #define SDIO_CMD_ENCMDCOMPL_Pos (12U)
lypinator 0:bb348c97df44 5377 #define SDIO_CMD_ENCMDCOMPL_Msk (0x1U << SDIO_CMD_ENCMDCOMPL_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 5378 #define SDIO_CMD_ENCMDCOMPL SDIO_CMD_ENCMDCOMPL_Msk /*!<Enable CMD completion */
lypinator 0:bb348c97df44 5379 #define SDIO_CMD_NIEN_Pos (13U)
lypinator 0:bb348c97df44 5380 #define SDIO_CMD_NIEN_Msk (0x1U << SDIO_CMD_NIEN_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 5381 #define SDIO_CMD_NIEN SDIO_CMD_NIEN_Msk /*!<Not Interrupt Enable */
lypinator 0:bb348c97df44 5382 #define SDIO_CMD_CEATACMD_Pos (14U)
lypinator 0:bb348c97df44 5383 #define SDIO_CMD_CEATACMD_Msk (0x1U << SDIO_CMD_CEATACMD_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 5384 #define SDIO_CMD_CEATACMD SDIO_CMD_CEATACMD_Msk /*!<CE-ATA command */
lypinator 0:bb348c97df44 5385
lypinator 0:bb348c97df44 5386 /***************** Bit definition for SDIO_RESPCMD register *****************/
lypinator 0:bb348c97df44 5387 #define SDIO_RESPCMD_RESPCMD_Pos (0U)
lypinator 0:bb348c97df44 5388 #define SDIO_RESPCMD_RESPCMD_Msk (0x3FU << SDIO_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */
lypinator 0:bb348c97df44 5389 #define SDIO_RESPCMD_RESPCMD SDIO_RESPCMD_RESPCMD_Msk /*!<Response command index */
lypinator 0:bb348c97df44 5390
lypinator 0:bb348c97df44 5391 /****************** Bit definition for SDIO_RESP0 register ******************/
lypinator 0:bb348c97df44 5392 #define SDIO_RESP0_CARDSTATUS0_Pos (0U)
lypinator 0:bb348c97df44 5393 #define SDIO_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFU << SDIO_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */
lypinator 0:bb348c97df44 5394 #define SDIO_RESP0_CARDSTATUS0 SDIO_RESP0_CARDSTATUS0_Msk /*!<Card Status */
lypinator 0:bb348c97df44 5395
lypinator 0:bb348c97df44 5396 /****************** Bit definition for SDIO_RESP1 register ******************/
lypinator 0:bb348c97df44 5397 #define SDIO_RESP1_CARDSTATUS1_Pos (0U)
lypinator 0:bb348c97df44 5398 #define SDIO_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFU << SDIO_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
lypinator 0:bb348c97df44 5399 #define SDIO_RESP1_CARDSTATUS1 SDIO_RESP1_CARDSTATUS1_Msk /*!<Card Status */
lypinator 0:bb348c97df44 5400
lypinator 0:bb348c97df44 5401 /****************** Bit definition for SDIO_RESP2 register ******************/
lypinator 0:bb348c97df44 5402 #define SDIO_RESP2_CARDSTATUS2_Pos (0U)
lypinator 0:bb348c97df44 5403 #define SDIO_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFU << SDIO_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
lypinator 0:bb348c97df44 5404 #define SDIO_RESP2_CARDSTATUS2 SDIO_RESP2_CARDSTATUS2_Msk /*!<Card Status */
lypinator 0:bb348c97df44 5405
lypinator 0:bb348c97df44 5406 /****************** Bit definition for SDIO_RESP3 register ******************/
lypinator 0:bb348c97df44 5407 #define SDIO_RESP3_CARDSTATUS3_Pos (0U)
lypinator 0:bb348c97df44 5408 #define SDIO_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFU << SDIO_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
lypinator 0:bb348c97df44 5409 #define SDIO_RESP3_CARDSTATUS3 SDIO_RESP3_CARDSTATUS3_Msk /*!<Card Status */
lypinator 0:bb348c97df44 5410
lypinator 0:bb348c97df44 5411 /****************** Bit definition for SDIO_RESP4 register ******************/
lypinator 0:bb348c97df44 5412 #define SDIO_RESP4_CARDSTATUS4_Pos (0U)
lypinator 0:bb348c97df44 5413 #define SDIO_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFU << SDIO_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
lypinator 0:bb348c97df44 5414 #define SDIO_RESP4_CARDSTATUS4 SDIO_RESP4_CARDSTATUS4_Msk /*!<Card Status */
lypinator 0:bb348c97df44 5415
lypinator 0:bb348c97df44 5416 /****************** Bit definition for SDIO_DTIMER register *****************/
lypinator 0:bb348c97df44 5417 #define SDIO_DTIMER_DATATIME_Pos (0U)
lypinator 0:bb348c97df44 5418 #define SDIO_DTIMER_DATATIME_Msk (0xFFFFFFFFU << SDIO_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
lypinator 0:bb348c97df44 5419 #define SDIO_DTIMER_DATATIME SDIO_DTIMER_DATATIME_Msk /*!<Data timeout period. */
lypinator 0:bb348c97df44 5420
lypinator 0:bb348c97df44 5421 /****************** Bit definition for SDIO_DLEN register *******************/
lypinator 0:bb348c97df44 5422 #define SDIO_DLEN_DATALENGTH_Pos (0U)
lypinator 0:bb348c97df44 5423 #define SDIO_DLEN_DATALENGTH_Msk (0x1FFFFFFU << SDIO_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
lypinator 0:bb348c97df44 5424 #define SDIO_DLEN_DATALENGTH SDIO_DLEN_DATALENGTH_Msk /*!<Data length value */
lypinator 0:bb348c97df44 5425
lypinator 0:bb348c97df44 5426 /****************** Bit definition for SDIO_DCTRL register ******************/
lypinator 0:bb348c97df44 5427 #define SDIO_DCTRL_DTEN_Pos (0U)
lypinator 0:bb348c97df44 5428 #define SDIO_DCTRL_DTEN_Msk (0x1U << SDIO_DCTRL_DTEN_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 5429 #define SDIO_DCTRL_DTEN SDIO_DCTRL_DTEN_Msk /*!<Data transfer enabled bit */
lypinator 0:bb348c97df44 5430 #define SDIO_DCTRL_DTDIR_Pos (1U)
lypinator 0:bb348c97df44 5431 #define SDIO_DCTRL_DTDIR_Msk (0x1U << SDIO_DCTRL_DTDIR_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 5432 #define SDIO_DCTRL_DTDIR SDIO_DCTRL_DTDIR_Msk /*!<Data transfer direction selection */
lypinator 0:bb348c97df44 5433 #define SDIO_DCTRL_DTMODE_Pos (2U)
lypinator 0:bb348c97df44 5434 #define SDIO_DCTRL_DTMODE_Msk (0x1U << SDIO_DCTRL_DTMODE_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 5435 #define SDIO_DCTRL_DTMODE SDIO_DCTRL_DTMODE_Msk /*!<Data transfer mode selection */
lypinator 0:bb348c97df44 5436 #define SDIO_DCTRL_DMAEN_Pos (3U)
lypinator 0:bb348c97df44 5437 #define SDIO_DCTRL_DMAEN_Msk (0x1U << SDIO_DCTRL_DMAEN_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 5438 #define SDIO_DCTRL_DMAEN SDIO_DCTRL_DMAEN_Msk /*!<DMA enabled bit */
lypinator 0:bb348c97df44 5439
lypinator 0:bb348c97df44 5440 #define SDIO_DCTRL_DBLOCKSIZE_Pos (4U)
lypinator 0:bb348c97df44 5441 #define SDIO_DCTRL_DBLOCKSIZE_Msk (0xFU << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */
lypinator 0:bb348c97df44 5442 #define SDIO_DCTRL_DBLOCKSIZE SDIO_DCTRL_DBLOCKSIZE_Msk /*!<DBLOCKSIZE[3:0] bits (Data block size) */
lypinator 0:bb348c97df44 5443 #define SDIO_DCTRL_DBLOCKSIZE_0 (0x1U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0010 */
lypinator 0:bb348c97df44 5444 #define SDIO_DCTRL_DBLOCKSIZE_1 (0x2U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0020 */
lypinator 0:bb348c97df44 5445 #define SDIO_DCTRL_DBLOCKSIZE_2 (0x4U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0040 */
lypinator 0:bb348c97df44 5446 #define SDIO_DCTRL_DBLOCKSIZE_3 (0x8U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0080 */
lypinator 0:bb348c97df44 5447
lypinator 0:bb348c97df44 5448 #define SDIO_DCTRL_RWSTART_Pos (8U)
lypinator 0:bb348c97df44 5449 #define SDIO_DCTRL_RWSTART_Msk (0x1U << SDIO_DCTRL_RWSTART_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 5450 #define SDIO_DCTRL_RWSTART SDIO_DCTRL_RWSTART_Msk /*!<Read wait start */
lypinator 0:bb348c97df44 5451 #define SDIO_DCTRL_RWSTOP_Pos (9U)
lypinator 0:bb348c97df44 5452 #define SDIO_DCTRL_RWSTOP_Msk (0x1U << SDIO_DCTRL_RWSTOP_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 5453 #define SDIO_DCTRL_RWSTOP SDIO_DCTRL_RWSTOP_Msk /*!<Read wait stop */
lypinator 0:bb348c97df44 5454 #define SDIO_DCTRL_RWMOD_Pos (10U)
lypinator 0:bb348c97df44 5455 #define SDIO_DCTRL_RWMOD_Msk (0x1U << SDIO_DCTRL_RWMOD_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 5456 #define SDIO_DCTRL_RWMOD SDIO_DCTRL_RWMOD_Msk /*!<Read wait mode */
lypinator 0:bb348c97df44 5457 #define SDIO_DCTRL_SDIOEN_Pos (11U)
lypinator 0:bb348c97df44 5458 #define SDIO_DCTRL_SDIOEN_Msk (0x1U << SDIO_DCTRL_SDIOEN_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 5459 #define SDIO_DCTRL_SDIOEN SDIO_DCTRL_SDIOEN_Msk /*!<SD I/O enable functions */
lypinator 0:bb348c97df44 5460
lypinator 0:bb348c97df44 5461 /****************** Bit definition for SDIO_DCOUNT register *****************/
lypinator 0:bb348c97df44 5462 #define SDIO_DCOUNT_DATACOUNT_Pos (0U)
lypinator 0:bb348c97df44 5463 #define SDIO_DCOUNT_DATACOUNT_Msk (0x1FFFFFFU << SDIO_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
lypinator 0:bb348c97df44 5464 #define SDIO_DCOUNT_DATACOUNT SDIO_DCOUNT_DATACOUNT_Msk /*!<Data count value */
lypinator 0:bb348c97df44 5465
lypinator 0:bb348c97df44 5466 /****************** Bit definition for SDIO_STA register ********************/
lypinator 0:bb348c97df44 5467 #define SDIO_STA_CCRCFAIL_Pos (0U)
lypinator 0:bb348c97df44 5468 #define SDIO_STA_CCRCFAIL_Msk (0x1U << SDIO_STA_CCRCFAIL_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 5469 #define SDIO_STA_CCRCFAIL SDIO_STA_CCRCFAIL_Msk /*!<Command response received (CRC check failed) */
lypinator 0:bb348c97df44 5470 #define SDIO_STA_DCRCFAIL_Pos (1U)
lypinator 0:bb348c97df44 5471 #define SDIO_STA_DCRCFAIL_Msk (0x1U << SDIO_STA_DCRCFAIL_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 5472 #define SDIO_STA_DCRCFAIL SDIO_STA_DCRCFAIL_Msk /*!<Data block sent/received (CRC check failed) */
lypinator 0:bb348c97df44 5473 #define SDIO_STA_CTIMEOUT_Pos (2U)
lypinator 0:bb348c97df44 5474 #define SDIO_STA_CTIMEOUT_Msk (0x1U << SDIO_STA_CTIMEOUT_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 5475 #define SDIO_STA_CTIMEOUT SDIO_STA_CTIMEOUT_Msk /*!<Command response timeout */
lypinator 0:bb348c97df44 5476 #define SDIO_STA_DTIMEOUT_Pos (3U)
lypinator 0:bb348c97df44 5477 #define SDIO_STA_DTIMEOUT_Msk (0x1U << SDIO_STA_DTIMEOUT_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 5478 #define SDIO_STA_DTIMEOUT SDIO_STA_DTIMEOUT_Msk /*!<Data timeout */
lypinator 0:bb348c97df44 5479 #define SDIO_STA_TXUNDERR_Pos (4U)
lypinator 0:bb348c97df44 5480 #define SDIO_STA_TXUNDERR_Msk (0x1U << SDIO_STA_TXUNDERR_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 5481 #define SDIO_STA_TXUNDERR SDIO_STA_TXUNDERR_Msk /*!<Transmit FIFO underrun error */
lypinator 0:bb348c97df44 5482 #define SDIO_STA_RXOVERR_Pos (5U)
lypinator 0:bb348c97df44 5483 #define SDIO_STA_RXOVERR_Msk (0x1U << SDIO_STA_RXOVERR_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 5484 #define SDIO_STA_RXOVERR SDIO_STA_RXOVERR_Msk /*!<Received FIFO overrun error */
lypinator 0:bb348c97df44 5485 #define SDIO_STA_CMDREND_Pos (6U)
lypinator 0:bb348c97df44 5486 #define SDIO_STA_CMDREND_Msk (0x1U << SDIO_STA_CMDREND_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 5487 #define SDIO_STA_CMDREND SDIO_STA_CMDREND_Msk /*!<Command response received (CRC check passed) */
lypinator 0:bb348c97df44 5488 #define SDIO_STA_CMDSENT_Pos (7U)
lypinator 0:bb348c97df44 5489 #define SDIO_STA_CMDSENT_Msk (0x1U << SDIO_STA_CMDSENT_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 5490 #define SDIO_STA_CMDSENT SDIO_STA_CMDSENT_Msk /*!<Command sent (no response required) */
lypinator 0:bb348c97df44 5491 #define SDIO_STA_DATAEND_Pos (8U)
lypinator 0:bb348c97df44 5492 #define SDIO_STA_DATAEND_Msk (0x1U << SDIO_STA_DATAEND_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 5493 #define SDIO_STA_DATAEND SDIO_STA_DATAEND_Msk /*!<Data end (data counter, SDIDCOUNT, is zero) */
lypinator 0:bb348c97df44 5494 #define SDIO_STA_STBITERR_Pos (9U)
lypinator 0:bb348c97df44 5495 #define SDIO_STA_STBITERR_Msk (0x1U << SDIO_STA_STBITERR_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 5496 #define SDIO_STA_STBITERR SDIO_STA_STBITERR_Msk /*!<Start bit not detected on all data signals in wide bus mode */
lypinator 0:bb348c97df44 5497 #define SDIO_STA_DBCKEND_Pos (10U)
lypinator 0:bb348c97df44 5498 #define SDIO_STA_DBCKEND_Msk (0x1U << SDIO_STA_DBCKEND_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 5499 #define SDIO_STA_DBCKEND SDIO_STA_DBCKEND_Msk /*!<Data block sent/received (CRC check passed) */
lypinator 0:bb348c97df44 5500 #define SDIO_STA_CMDACT_Pos (11U)
lypinator 0:bb348c97df44 5501 #define SDIO_STA_CMDACT_Msk (0x1U << SDIO_STA_CMDACT_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 5502 #define SDIO_STA_CMDACT SDIO_STA_CMDACT_Msk /*!<Command transfer in progress */
lypinator 0:bb348c97df44 5503 #define SDIO_STA_TXACT_Pos (12U)
lypinator 0:bb348c97df44 5504 #define SDIO_STA_TXACT_Msk (0x1U << SDIO_STA_TXACT_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 5505 #define SDIO_STA_TXACT SDIO_STA_TXACT_Msk /*!<Data transmit in progress */
lypinator 0:bb348c97df44 5506 #define SDIO_STA_RXACT_Pos (13U)
lypinator 0:bb348c97df44 5507 #define SDIO_STA_RXACT_Msk (0x1U << SDIO_STA_RXACT_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 5508 #define SDIO_STA_RXACT SDIO_STA_RXACT_Msk /*!<Data receive in progress */
lypinator 0:bb348c97df44 5509 #define SDIO_STA_TXFIFOHE_Pos (14U)
lypinator 0:bb348c97df44 5510 #define SDIO_STA_TXFIFOHE_Msk (0x1U << SDIO_STA_TXFIFOHE_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 5511 #define SDIO_STA_TXFIFOHE SDIO_STA_TXFIFOHE_Msk /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
lypinator 0:bb348c97df44 5512 #define SDIO_STA_RXFIFOHF_Pos (15U)
lypinator 0:bb348c97df44 5513 #define SDIO_STA_RXFIFOHF_Msk (0x1U << SDIO_STA_RXFIFOHF_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 5514 #define SDIO_STA_RXFIFOHF SDIO_STA_RXFIFOHF_Msk /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
lypinator 0:bb348c97df44 5515 #define SDIO_STA_TXFIFOF_Pos (16U)
lypinator 0:bb348c97df44 5516 #define SDIO_STA_TXFIFOF_Msk (0x1U << SDIO_STA_TXFIFOF_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 5517 #define SDIO_STA_TXFIFOF SDIO_STA_TXFIFOF_Msk /*!<Transmit FIFO full */
lypinator 0:bb348c97df44 5518 #define SDIO_STA_RXFIFOF_Pos (17U)
lypinator 0:bb348c97df44 5519 #define SDIO_STA_RXFIFOF_Msk (0x1U << SDIO_STA_RXFIFOF_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 5520 #define SDIO_STA_RXFIFOF SDIO_STA_RXFIFOF_Msk /*!<Receive FIFO full */
lypinator 0:bb348c97df44 5521 #define SDIO_STA_TXFIFOE_Pos (18U)
lypinator 0:bb348c97df44 5522 #define SDIO_STA_TXFIFOE_Msk (0x1U << SDIO_STA_TXFIFOE_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 5523 #define SDIO_STA_TXFIFOE SDIO_STA_TXFIFOE_Msk /*!<Transmit FIFO empty */
lypinator 0:bb348c97df44 5524 #define SDIO_STA_RXFIFOE_Pos (19U)
lypinator 0:bb348c97df44 5525 #define SDIO_STA_RXFIFOE_Msk (0x1U << SDIO_STA_RXFIFOE_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 5526 #define SDIO_STA_RXFIFOE SDIO_STA_RXFIFOE_Msk /*!<Receive FIFO empty */
lypinator 0:bb348c97df44 5527 #define SDIO_STA_TXDAVL_Pos (20U)
lypinator 0:bb348c97df44 5528 #define SDIO_STA_TXDAVL_Msk (0x1U << SDIO_STA_TXDAVL_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 5529 #define SDIO_STA_TXDAVL SDIO_STA_TXDAVL_Msk /*!<Data available in transmit FIFO */
lypinator 0:bb348c97df44 5530 #define SDIO_STA_RXDAVL_Pos (21U)
lypinator 0:bb348c97df44 5531 #define SDIO_STA_RXDAVL_Msk (0x1U << SDIO_STA_RXDAVL_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 5532 #define SDIO_STA_RXDAVL SDIO_STA_RXDAVL_Msk /*!<Data available in receive FIFO */
lypinator 0:bb348c97df44 5533 #define SDIO_STA_SDIOIT_Pos (22U)
lypinator 0:bb348c97df44 5534 #define SDIO_STA_SDIOIT_Msk (0x1U << SDIO_STA_SDIOIT_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 5535 #define SDIO_STA_SDIOIT SDIO_STA_SDIOIT_Msk /*!<SDIO interrupt received */
lypinator 0:bb348c97df44 5536 #define SDIO_STA_CEATAEND_Pos (23U)
lypinator 0:bb348c97df44 5537 #define SDIO_STA_CEATAEND_Msk (0x1U << SDIO_STA_CEATAEND_Pos) /*!< 0x00800000 */
lypinator 0:bb348c97df44 5538 #define SDIO_STA_CEATAEND SDIO_STA_CEATAEND_Msk /*!<CE-ATA command completion signal received for CMD61 */
lypinator 0:bb348c97df44 5539
lypinator 0:bb348c97df44 5540 /******************* Bit definition for SDIO_ICR register *******************/
lypinator 0:bb348c97df44 5541 #define SDIO_ICR_CCRCFAILC_Pos (0U)
lypinator 0:bb348c97df44 5542 #define SDIO_ICR_CCRCFAILC_Msk (0x1U << SDIO_ICR_CCRCFAILC_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 5543 #define SDIO_ICR_CCRCFAILC SDIO_ICR_CCRCFAILC_Msk /*!<CCRCFAIL flag clear bit */
lypinator 0:bb348c97df44 5544 #define SDIO_ICR_DCRCFAILC_Pos (1U)
lypinator 0:bb348c97df44 5545 #define SDIO_ICR_DCRCFAILC_Msk (0x1U << SDIO_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 5546 #define SDIO_ICR_DCRCFAILC SDIO_ICR_DCRCFAILC_Msk /*!<DCRCFAIL flag clear bit */
lypinator 0:bb348c97df44 5547 #define SDIO_ICR_CTIMEOUTC_Pos (2U)
lypinator 0:bb348c97df44 5548 #define SDIO_ICR_CTIMEOUTC_Msk (0x1U << SDIO_ICR_CTIMEOUTC_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 5549 #define SDIO_ICR_CTIMEOUTC SDIO_ICR_CTIMEOUTC_Msk /*!<CTIMEOUT flag clear bit */
lypinator 0:bb348c97df44 5550 #define SDIO_ICR_DTIMEOUTC_Pos (3U)
lypinator 0:bb348c97df44 5551 #define SDIO_ICR_DTIMEOUTC_Msk (0x1U << SDIO_ICR_DTIMEOUTC_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 5552 #define SDIO_ICR_DTIMEOUTC SDIO_ICR_DTIMEOUTC_Msk /*!<DTIMEOUT flag clear bit */
lypinator 0:bb348c97df44 5553 #define SDIO_ICR_TXUNDERRC_Pos (4U)
lypinator 0:bb348c97df44 5554 #define SDIO_ICR_TXUNDERRC_Msk (0x1U << SDIO_ICR_TXUNDERRC_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 5555 #define SDIO_ICR_TXUNDERRC SDIO_ICR_TXUNDERRC_Msk /*!<TXUNDERR flag clear bit */
lypinator 0:bb348c97df44 5556 #define SDIO_ICR_RXOVERRC_Pos (5U)
lypinator 0:bb348c97df44 5557 #define SDIO_ICR_RXOVERRC_Msk (0x1U << SDIO_ICR_RXOVERRC_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 5558 #define SDIO_ICR_RXOVERRC SDIO_ICR_RXOVERRC_Msk /*!<RXOVERR flag clear bit */
lypinator 0:bb348c97df44 5559 #define SDIO_ICR_CMDRENDC_Pos (6U)
lypinator 0:bb348c97df44 5560 #define SDIO_ICR_CMDRENDC_Msk (0x1U << SDIO_ICR_CMDRENDC_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 5561 #define SDIO_ICR_CMDRENDC SDIO_ICR_CMDRENDC_Msk /*!<CMDREND flag clear bit */
lypinator 0:bb348c97df44 5562 #define SDIO_ICR_CMDSENTC_Pos (7U)
lypinator 0:bb348c97df44 5563 #define SDIO_ICR_CMDSENTC_Msk (0x1U << SDIO_ICR_CMDSENTC_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 5564 #define SDIO_ICR_CMDSENTC SDIO_ICR_CMDSENTC_Msk /*!<CMDSENT flag clear bit */
lypinator 0:bb348c97df44 5565 #define SDIO_ICR_DATAENDC_Pos (8U)
lypinator 0:bb348c97df44 5566 #define SDIO_ICR_DATAENDC_Msk (0x1U << SDIO_ICR_DATAENDC_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 5567 #define SDIO_ICR_DATAENDC SDIO_ICR_DATAENDC_Msk /*!<DATAEND flag clear bit */
lypinator 0:bb348c97df44 5568 #define SDIO_ICR_STBITERRC_Pos (9U)
lypinator 0:bb348c97df44 5569 #define SDIO_ICR_STBITERRC_Msk (0x1U << SDIO_ICR_STBITERRC_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 5570 #define SDIO_ICR_STBITERRC SDIO_ICR_STBITERRC_Msk /*!<STBITERR flag clear bit */
lypinator 0:bb348c97df44 5571 #define SDIO_ICR_DBCKENDC_Pos (10U)
lypinator 0:bb348c97df44 5572 #define SDIO_ICR_DBCKENDC_Msk (0x1U << SDIO_ICR_DBCKENDC_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 5573 #define SDIO_ICR_DBCKENDC SDIO_ICR_DBCKENDC_Msk /*!<DBCKEND flag clear bit */
lypinator 0:bb348c97df44 5574 #define SDIO_ICR_SDIOITC_Pos (22U)
lypinator 0:bb348c97df44 5575 #define SDIO_ICR_SDIOITC_Msk (0x1U << SDIO_ICR_SDIOITC_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 5576 #define SDIO_ICR_SDIOITC SDIO_ICR_SDIOITC_Msk /*!<SDIOIT flag clear bit */
lypinator 0:bb348c97df44 5577 #define SDIO_ICR_CEATAENDC_Pos (23U)
lypinator 0:bb348c97df44 5578 #define SDIO_ICR_CEATAENDC_Msk (0x1U << SDIO_ICR_CEATAENDC_Pos) /*!< 0x00800000 */
lypinator 0:bb348c97df44 5579 #define SDIO_ICR_CEATAENDC SDIO_ICR_CEATAENDC_Msk /*!<CEATAEND flag clear bit */
lypinator 0:bb348c97df44 5580
lypinator 0:bb348c97df44 5581 /****************** Bit definition for SDIO_MASK register *******************/
lypinator 0:bb348c97df44 5582 #define SDIO_MASK_CCRCFAILIE_Pos (0U)
lypinator 0:bb348c97df44 5583 #define SDIO_MASK_CCRCFAILIE_Msk (0x1U << SDIO_MASK_CCRCFAILIE_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 5584 #define SDIO_MASK_CCRCFAILIE SDIO_MASK_CCRCFAILIE_Msk /*!<Command CRC Fail Interrupt Enable */
lypinator 0:bb348c97df44 5585 #define SDIO_MASK_DCRCFAILIE_Pos (1U)
lypinator 0:bb348c97df44 5586 #define SDIO_MASK_DCRCFAILIE_Msk (0x1U << SDIO_MASK_DCRCFAILIE_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 5587 #define SDIO_MASK_DCRCFAILIE SDIO_MASK_DCRCFAILIE_Msk /*!<Data CRC Fail Interrupt Enable */
lypinator 0:bb348c97df44 5588 #define SDIO_MASK_CTIMEOUTIE_Pos (2U)
lypinator 0:bb348c97df44 5589 #define SDIO_MASK_CTIMEOUTIE_Msk (0x1U << SDIO_MASK_CTIMEOUTIE_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 5590 #define SDIO_MASK_CTIMEOUTIE SDIO_MASK_CTIMEOUTIE_Msk /*!<Command TimeOut Interrupt Enable */
lypinator 0:bb348c97df44 5591 #define SDIO_MASK_DTIMEOUTIE_Pos (3U)
lypinator 0:bb348c97df44 5592 #define SDIO_MASK_DTIMEOUTIE_Msk (0x1U << SDIO_MASK_DTIMEOUTIE_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 5593 #define SDIO_MASK_DTIMEOUTIE SDIO_MASK_DTIMEOUTIE_Msk /*!<Data TimeOut Interrupt Enable */
lypinator 0:bb348c97df44 5594 #define SDIO_MASK_TXUNDERRIE_Pos (4U)
lypinator 0:bb348c97df44 5595 #define SDIO_MASK_TXUNDERRIE_Msk (0x1U << SDIO_MASK_TXUNDERRIE_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 5596 #define SDIO_MASK_TXUNDERRIE SDIO_MASK_TXUNDERRIE_Msk /*!<Tx FIFO UnderRun Error Interrupt Enable */
lypinator 0:bb348c97df44 5597 #define SDIO_MASK_RXOVERRIE_Pos (5U)
lypinator 0:bb348c97df44 5598 #define SDIO_MASK_RXOVERRIE_Msk (0x1U << SDIO_MASK_RXOVERRIE_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 5599 #define SDIO_MASK_RXOVERRIE SDIO_MASK_RXOVERRIE_Msk /*!<Rx FIFO OverRun Error Interrupt Enable */
lypinator 0:bb348c97df44 5600 #define SDIO_MASK_CMDRENDIE_Pos (6U)
lypinator 0:bb348c97df44 5601 #define SDIO_MASK_CMDRENDIE_Msk (0x1U << SDIO_MASK_CMDRENDIE_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 5602 #define SDIO_MASK_CMDRENDIE SDIO_MASK_CMDRENDIE_Msk /*!<Command Response Received Interrupt Enable */
lypinator 0:bb348c97df44 5603 #define SDIO_MASK_CMDSENTIE_Pos (7U)
lypinator 0:bb348c97df44 5604 #define SDIO_MASK_CMDSENTIE_Msk (0x1U << SDIO_MASK_CMDSENTIE_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 5605 #define SDIO_MASK_CMDSENTIE SDIO_MASK_CMDSENTIE_Msk /*!<Command Sent Interrupt Enable */
lypinator 0:bb348c97df44 5606 #define SDIO_MASK_DATAENDIE_Pos (8U)
lypinator 0:bb348c97df44 5607 #define SDIO_MASK_DATAENDIE_Msk (0x1U << SDIO_MASK_DATAENDIE_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 5608 #define SDIO_MASK_DATAENDIE SDIO_MASK_DATAENDIE_Msk /*!<Data End Interrupt Enable */
lypinator 0:bb348c97df44 5609 #define SDIO_MASK_STBITERRIE_Pos (9U)
lypinator 0:bb348c97df44 5610 #define SDIO_MASK_STBITERRIE_Msk (0x1U << SDIO_MASK_STBITERRIE_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 5611 #define SDIO_MASK_STBITERRIE SDIO_MASK_STBITERRIE_Msk /*!<Start Bit Error Interrupt Enable */
lypinator 0:bb348c97df44 5612 #define SDIO_MASK_DBCKENDIE_Pos (10U)
lypinator 0:bb348c97df44 5613 #define SDIO_MASK_DBCKENDIE_Msk (0x1U << SDIO_MASK_DBCKENDIE_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 5614 #define SDIO_MASK_DBCKENDIE SDIO_MASK_DBCKENDIE_Msk /*!<Data Block End Interrupt Enable */
lypinator 0:bb348c97df44 5615 #define SDIO_MASK_CMDACTIE_Pos (11U)
lypinator 0:bb348c97df44 5616 #define SDIO_MASK_CMDACTIE_Msk (0x1U << SDIO_MASK_CMDACTIE_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 5617 #define SDIO_MASK_CMDACTIE SDIO_MASK_CMDACTIE_Msk /*!<CCommand Acting Interrupt Enable */
lypinator 0:bb348c97df44 5618 #define SDIO_MASK_TXACTIE_Pos (12U)
lypinator 0:bb348c97df44 5619 #define SDIO_MASK_TXACTIE_Msk (0x1U << SDIO_MASK_TXACTIE_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 5620 #define SDIO_MASK_TXACTIE SDIO_MASK_TXACTIE_Msk /*!<Data Transmit Acting Interrupt Enable */
lypinator 0:bb348c97df44 5621 #define SDIO_MASK_RXACTIE_Pos (13U)
lypinator 0:bb348c97df44 5622 #define SDIO_MASK_RXACTIE_Msk (0x1U << SDIO_MASK_RXACTIE_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 5623 #define SDIO_MASK_RXACTIE SDIO_MASK_RXACTIE_Msk /*!<Data receive acting interrupt enabled */
lypinator 0:bb348c97df44 5624 #define SDIO_MASK_TXFIFOHEIE_Pos (14U)
lypinator 0:bb348c97df44 5625 #define SDIO_MASK_TXFIFOHEIE_Msk (0x1U << SDIO_MASK_TXFIFOHEIE_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 5626 #define SDIO_MASK_TXFIFOHEIE SDIO_MASK_TXFIFOHEIE_Msk /*!<Tx FIFO Half Empty interrupt Enable */
lypinator 0:bb348c97df44 5627 #define SDIO_MASK_RXFIFOHFIE_Pos (15U)
lypinator 0:bb348c97df44 5628 #define SDIO_MASK_RXFIFOHFIE_Msk (0x1U << SDIO_MASK_RXFIFOHFIE_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 5629 #define SDIO_MASK_RXFIFOHFIE SDIO_MASK_RXFIFOHFIE_Msk /*!<Rx FIFO Half Full interrupt Enable */
lypinator 0:bb348c97df44 5630 #define SDIO_MASK_TXFIFOFIE_Pos (16U)
lypinator 0:bb348c97df44 5631 #define SDIO_MASK_TXFIFOFIE_Msk (0x1U << SDIO_MASK_TXFIFOFIE_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 5632 #define SDIO_MASK_TXFIFOFIE SDIO_MASK_TXFIFOFIE_Msk /*!<Tx FIFO Full interrupt Enable */
lypinator 0:bb348c97df44 5633 #define SDIO_MASK_RXFIFOFIE_Pos (17U)
lypinator 0:bb348c97df44 5634 #define SDIO_MASK_RXFIFOFIE_Msk (0x1U << SDIO_MASK_RXFIFOFIE_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 5635 #define SDIO_MASK_RXFIFOFIE SDIO_MASK_RXFIFOFIE_Msk /*!<Rx FIFO Full interrupt Enable */
lypinator 0:bb348c97df44 5636 #define SDIO_MASK_TXFIFOEIE_Pos (18U)
lypinator 0:bb348c97df44 5637 #define SDIO_MASK_TXFIFOEIE_Msk (0x1U << SDIO_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 5638 #define SDIO_MASK_TXFIFOEIE SDIO_MASK_TXFIFOEIE_Msk /*!<Tx FIFO Empty interrupt Enable */
lypinator 0:bb348c97df44 5639 #define SDIO_MASK_RXFIFOEIE_Pos (19U)
lypinator 0:bb348c97df44 5640 #define SDIO_MASK_RXFIFOEIE_Msk (0x1U << SDIO_MASK_RXFIFOEIE_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 5641 #define SDIO_MASK_RXFIFOEIE SDIO_MASK_RXFIFOEIE_Msk /*!<Rx FIFO Empty interrupt Enable */
lypinator 0:bb348c97df44 5642 #define SDIO_MASK_TXDAVLIE_Pos (20U)
lypinator 0:bb348c97df44 5643 #define SDIO_MASK_TXDAVLIE_Msk (0x1U << SDIO_MASK_TXDAVLIE_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 5644 #define SDIO_MASK_TXDAVLIE SDIO_MASK_TXDAVLIE_Msk /*!<Data available in Tx FIFO interrupt Enable */
lypinator 0:bb348c97df44 5645 #define SDIO_MASK_RXDAVLIE_Pos (21U)
lypinator 0:bb348c97df44 5646 #define SDIO_MASK_RXDAVLIE_Msk (0x1U << SDIO_MASK_RXDAVLIE_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 5647 #define SDIO_MASK_RXDAVLIE SDIO_MASK_RXDAVLIE_Msk /*!<Data available in Rx FIFO interrupt Enable */
lypinator 0:bb348c97df44 5648 #define SDIO_MASK_SDIOITIE_Pos (22U)
lypinator 0:bb348c97df44 5649 #define SDIO_MASK_SDIOITIE_Msk (0x1U << SDIO_MASK_SDIOITIE_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 5650 #define SDIO_MASK_SDIOITIE SDIO_MASK_SDIOITIE_Msk /*!<SDIO Mode Interrupt Received interrupt Enable */
lypinator 0:bb348c97df44 5651 #define SDIO_MASK_CEATAENDIE_Pos (23U)
lypinator 0:bb348c97df44 5652 #define SDIO_MASK_CEATAENDIE_Msk (0x1U << SDIO_MASK_CEATAENDIE_Pos) /*!< 0x00800000 */
lypinator 0:bb348c97df44 5653 #define SDIO_MASK_CEATAENDIE SDIO_MASK_CEATAENDIE_Msk /*!<CE-ATA command completion signal received Interrupt Enable */
lypinator 0:bb348c97df44 5654
lypinator 0:bb348c97df44 5655 /***************** Bit definition for SDIO_FIFOCNT register *****************/
lypinator 0:bb348c97df44 5656 #define SDIO_FIFOCNT_FIFOCOUNT_Pos (0U)
lypinator 0:bb348c97df44 5657 #define SDIO_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFU << SDIO_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */
lypinator 0:bb348c97df44 5658 #define SDIO_FIFOCNT_FIFOCOUNT SDIO_FIFOCNT_FIFOCOUNT_Msk /*!<Remaining number of words to be written to or read from the FIFO */
lypinator 0:bb348c97df44 5659
lypinator 0:bb348c97df44 5660 /****************** Bit definition for SDIO_FIFO register *******************/
lypinator 0:bb348c97df44 5661 #define SDIO_FIFO_FIFODATA_Pos (0U)
lypinator 0:bb348c97df44 5662 #define SDIO_FIFO_FIFODATA_Msk (0xFFFFFFFFU << SDIO_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
lypinator 0:bb348c97df44 5663 #define SDIO_FIFO_FIFODATA SDIO_FIFO_FIFODATA_Msk /*!<Receive and transmit FIFO data */
lypinator 0:bb348c97df44 5664
lypinator 0:bb348c97df44 5665 /******************************************************************************/
lypinator 0:bb348c97df44 5666 /* */
lypinator 0:bb348c97df44 5667 /* Serial Peripheral Interface */
lypinator 0:bb348c97df44 5668 /* */
lypinator 0:bb348c97df44 5669 /******************************************************************************/
lypinator 0:bb348c97df44 5670 #define SPI_I2S_FULLDUPLEX_SUPPORT /*!< I2S Full-Duplex support */
lypinator 0:bb348c97df44 5671
lypinator 0:bb348c97df44 5672 /******************* Bit definition for SPI_CR1 register ********************/
lypinator 0:bb348c97df44 5673 #define SPI_CR1_CPHA_Pos (0U)
lypinator 0:bb348c97df44 5674 #define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 5675 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!<Clock Phase */
lypinator 0:bb348c97df44 5676 #define SPI_CR1_CPOL_Pos (1U)
lypinator 0:bb348c97df44 5677 #define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 5678 #define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!<Clock Polarity */
lypinator 0:bb348c97df44 5679 #define SPI_CR1_MSTR_Pos (2U)
lypinator 0:bb348c97df44 5680 #define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 5681 #define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!<Master Selection */
lypinator 0:bb348c97df44 5682
lypinator 0:bb348c97df44 5683 #define SPI_CR1_BR_Pos (3U)
lypinator 0:bb348c97df44 5684 #define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /*!< 0x00000038 */
lypinator 0:bb348c97df44 5685 #define SPI_CR1_BR SPI_CR1_BR_Msk /*!<BR[2:0] bits (Baud Rate Control) */
lypinator 0:bb348c97df44 5686 #define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 5687 #define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 5688 #define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 5689
lypinator 0:bb348c97df44 5690 #define SPI_CR1_SPE_Pos (6U)
lypinator 0:bb348c97df44 5691 #define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 5692 #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!<SPI Enable */
lypinator 0:bb348c97df44 5693 #define SPI_CR1_LSBFIRST_Pos (7U)
lypinator 0:bb348c97df44 5694 #define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 5695 #define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!<Frame Format */
lypinator 0:bb348c97df44 5696 #define SPI_CR1_SSI_Pos (8U)
lypinator 0:bb348c97df44 5697 #define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 5698 #define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!<Internal slave select */
lypinator 0:bb348c97df44 5699 #define SPI_CR1_SSM_Pos (9U)
lypinator 0:bb348c97df44 5700 #define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 5701 #define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!<Software slave management */
lypinator 0:bb348c97df44 5702 #define SPI_CR1_RXONLY_Pos (10U)
lypinator 0:bb348c97df44 5703 #define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 5704 #define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!<Receive only */
lypinator 0:bb348c97df44 5705 #define SPI_CR1_DFF_Pos (11U)
lypinator 0:bb348c97df44 5706 #define SPI_CR1_DFF_Msk (0x1U << SPI_CR1_DFF_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 5707 #define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!<Data Frame Format */
lypinator 0:bb348c97df44 5708 #define SPI_CR1_CRCNEXT_Pos (12U)
lypinator 0:bb348c97df44 5709 #define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 5710 #define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!<Transmit CRC next */
lypinator 0:bb348c97df44 5711 #define SPI_CR1_CRCEN_Pos (13U)
lypinator 0:bb348c97df44 5712 #define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 5713 #define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!<Hardware CRC calculation enable */
lypinator 0:bb348c97df44 5714 #define SPI_CR1_BIDIOE_Pos (14U)
lypinator 0:bb348c97df44 5715 #define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 5716 #define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!<Output enable in bidirectional mode */
lypinator 0:bb348c97df44 5717 #define SPI_CR1_BIDIMODE_Pos (15U)
lypinator 0:bb348c97df44 5718 #define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 5719 #define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!<Bidirectional data mode enable */
lypinator 0:bb348c97df44 5720
lypinator 0:bb348c97df44 5721 /******************* Bit definition for SPI_CR2 register ********************/
lypinator 0:bb348c97df44 5722 #define SPI_CR2_RXDMAEN_Pos (0U)
lypinator 0:bb348c97df44 5723 #define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 5724 #define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!<Rx Buffer DMA Enable */
lypinator 0:bb348c97df44 5725 #define SPI_CR2_TXDMAEN_Pos (1U)
lypinator 0:bb348c97df44 5726 #define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 5727 #define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!<Tx Buffer DMA Enable */
lypinator 0:bb348c97df44 5728 #define SPI_CR2_SSOE_Pos (2U)
lypinator 0:bb348c97df44 5729 #define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 5730 #define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!<SS Output Enable */
lypinator 0:bb348c97df44 5731 #define SPI_CR2_FRF_Pos (4U)
lypinator 0:bb348c97df44 5732 #define SPI_CR2_FRF_Msk (0x1U << SPI_CR2_FRF_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 5733 #define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!<Frame Format */
lypinator 0:bb348c97df44 5734 #define SPI_CR2_ERRIE_Pos (5U)
lypinator 0:bb348c97df44 5735 #define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 5736 #define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!<Error Interrupt Enable */
lypinator 0:bb348c97df44 5737 #define SPI_CR2_RXNEIE_Pos (6U)
lypinator 0:bb348c97df44 5738 #define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 5739 #define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!<RX buffer Not Empty Interrupt Enable */
lypinator 0:bb348c97df44 5740 #define SPI_CR2_TXEIE_Pos (7U)
lypinator 0:bb348c97df44 5741 #define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 5742 #define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!<Tx buffer Empty Interrupt Enable */
lypinator 0:bb348c97df44 5743
lypinator 0:bb348c97df44 5744 /******************** Bit definition for SPI_SR register ********************/
lypinator 0:bb348c97df44 5745 #define SPI_SR_RXNE_Pos (0U)
lypinator 0:bb348c97df44 5746 #define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 5747 #define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!<Receive buffer Not Empty */
lypinator 0:bb348c97df44 5748 #define SPI_SR_TXE_Pos (1U)
lypinator 0:bb348c97df44 5749 #define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 5750 #define SPI_SR_TXE SPI_SR_TXE_Msk /*!<Transmit buffer Empty */
lypinator 0:bb348c97df44 5751 #define SPI_SR_CHSIDE_Pos (2U)
lypinator 0:bb348c97df44 5752 #define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 5753 #define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!<Channel side */
lypinator 0:bb348c97df44 5754 #define SPI_SR_UDR_Pos (3U)
lypinator 0:bb348c97df44 5755 #define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 5756 #define SPI_SR_UDR SPI_SR_UDR_Msk /*!<Underrun flag */
lypinator 0:bb348c97df44 5757 #define SPI_SR_CRCERR_Pos (4U)
lypinator 0:bb348c97df44 5758 #define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 5759 #define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!<CRC Error flag */
lypinator 0:bb348c97df44 5760 #define SPI_SR_MODF_Pos (5U)
lypinator 0:bb348c97df44 5761 #define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 5762 #define SPI_SR_MODF SPI_SR_MODF_Msk /*!<Mode fault */
lypinator 0:bb348c97df44 5763 #define SPI_SR_OVR_Pos (6U)
lypinator 0:bb348c97df44 5764 #define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 5765 #define SPI_SR_OVR SPI_SR_OVR_Msk /*!<Overrun flag */
lypinator 0:bb348c97df44 5766 #define SPI_SR_BSY_Pos (7U)
lypinator 0:bb348c97df44 5767 #define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 5768 #define SPI_SR_BSY SPI_SR_BSY_Msk /*!<Busy flag */
lypinator 0:bb348c97df44 5769 #define SPI_SR_FRE_Pos (8U)
lypinator 0:bb348c97df44 5770 #define SPI_SR_FRE_Msk (0x1U << SPI_SR_FRE_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 5771 #define SPI_SR_FRE SPI_SR_FRE_Msk /*!<Frame format error flag */
lypinator 0:bb348c97df44 5772
lypinator 0:bb348c97df44 5773 /******************** Bit definition for SPI_DR register ********************/
lypinator 0:bb348c97df44 5774 #define SPI_DR_DR_Pos (0U)
lypinator 0:bb348c97df44 5775 #define SPI_DR_DR_Msk (0xFFFFU << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
lypinator 0:bb348c97df44 5776 #define SPI_DR_DR SPI_DR_DR_Msk /*!<Data Register */
lypinator 0:bb348c97df44 5777
lypinator 0:bb348c97df44 5778 /******************* Bit definition for SPI_CRCPR register ******************/
lypinator 0:bb348c97df44 5779 #define SPI_CRCPR_CRCPOLY_Pos (0U)
lypinator 0:bb348c97df44 5780 #define SPI_CRCPR_CRCPOLY_Msk (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
lypinator 0:bb348c97df44 5781 #define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!<CRC polynomial register */
lypinator 0:bb348c97df44 5782
lypinator 0:bb348c97df44 5783 /****************** Bit definition for SPI_RXCRCR register ******************/
lypinator 0:bb348c97df44 5784 #define SPI_RXCRCR_RXCRC_Pos (0U)
lypinator 0:bb348c97df44 5785 #define SPI_RXCRCR_RXCRC_Msk (0xFFFFU << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
lypinator 0:bb348c97df44 5786 #define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!<Rx CRC Register */
lypinator 0:bb348c97df44 5787
lypinator 0:bb348c97df44 5788 /****************** Bit definition for SPI_TXCRCR register ******************/
lypinator 0:bb348c97df44 5789 #define SPI_TXCRCR_TXCRC_Pos (0U)
lypinator 0:bb348c97df44 5790 #define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
lypinator 0:bb348c97df44 5791 #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!<Tx CRC Register */
lypinator 0:bb348c97df44 5792
lypinator 0:bb348c97df44 5793 /****************** Bit definition for SPI_I2SCFGR register *****************/
lypinator 0:bb348c97df44 5794 #define SPI_I2SCFGR_CHLEN_Pos (0U)
lypinator 0:bb348c97df44 5795 #define SPI_I2SCFGR_CHLEN_Msk (0x1U << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 5796 #define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */
lypinator 0:bb348c97df44 5797
lypinator 0:bb348c97df44 5798 #define SPI_I2SCFGR_DATLEN_Pos (1U)
lypinator 0:bb348c97df44 5799 #define SPI_I2SCFGR_DATLEN_Msk (0x3U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */
lypinator 0:bb348c97df44 5800 #define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] bits (Data length to be transferred) */
lypinator 0:bb348c97df44 5801 #define SPI_I2SCFGR_DATLEN_0 (0x1U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 5802 #define SPI_I2SCFGR_DATLEN_1 (0x2U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 5803
lypinator 0:bb348c97df44 5804 #define SPI_I2SCFGR_CKPOL_Pos (3U)
lypinator 0:bb348c97df44 5805 #define SPI_I2SCFGR_CKPOL_Msk (0x1U << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 5806 #define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<steady state clock polarity */
lypinator 0:bb348c97df44 5807
lypinator 0:bb348c97df44 5808 #define SPI_I2SCFGR_I2SSTD_Pos (4U)
lypinator 0:bb348c97df44 5809 #define SPI_I2SCFGR_I2SSTD_Msk (0x3U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */
lypinator 0:bb348c97df44 5810 #define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] bits (I2S standard selection) */
lypinator 0:bb348c97df44 5811 #define SPI_I2SCFGR_I2SSTD_0 (0x1U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 5812 #define SPI_I2SCFGR_I2SSTD_1 (0x2U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 5813
lypinator 0:bb348c97df44 5814 #define SPI_I2SCFGR_PCMSYNC_Pos (7U)
lypinator 0:bb348c97df44 5815 #define SPI_I2SCFGR_PCMSYNC_Msk (0x1U << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 5816 #define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */
lypinator 0:bb348c97df44 5817
lypinator 0:bb348c97df44 5818 #define SPI_I2SCFGR_I2SCFG_Pos (8U)
lypinator 0:bb348c97df44 5819 #define SPI_I2SCFGR_I2SCFG_Msk (0x3U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */
lypinator 0:bb348c97df44 5820 #define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[1:0] bits (I2S configuration mode) */
lypinator 0:bb348c97df44 5821 #define SPI_I2SCFGR_I2SCFG_0 (0x1U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 5822 #define SPI_I2SCFGR_I2SCFG_1 (0x2U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 5823
lypinator 0:bb348c97df44 5824 #define SPI_I2SCFGR_I2SE_Pos (10U)
lypinator 0:bb348c97df44 5825 #define SPI_I2SCFGR_I2SE_Msk (0x1U << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 5826 #define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!<I2S Enable */
lypinator 0:bb348c97df44 5827 #define SPI_I2SCFGR_I2SMOD_Pos (11U)
lypinator 0:bb348c97df44 5828 #define SPI_I2SCFGR_I2SMOD_Msk (0x1U << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 5829 #define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */
lypinator 0:bb348c97df44 5830
lypinator 0:bb348c97df44 5831 /****************** Bit definition for SPI_I2SPR register *******************/
lypinator 0:bb348c97df44 5832 #define SPI_I2SPR_I2SDIV_Pos (0U)
lypinator 0:bb348c97df44 5833 #define SPI_I2SPR_I2SDIV_Msk (0xFFU << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */
lypinator 0:bb348c97df44 5834 #define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!<I2S Linear prescaler */
lypinator 0:bb348c97df44 5835 #define SPI_I2SPR_ODD_Pos (8U)
lypinator 0:bb348c97df44 5836 #define SPI_I2SPR_ODD_Msk (0x1U << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 5837 #define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!<Odd factor for the prescaler */
lypinator 0:bb348c97df44 5838 #define SPI_I2SPR_MCKOE_Pos (9U)
lypinator 0:bb348c97df44 5839 #define SPI_I2SPR_MCKOE_Msk (0x1U << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 5840 #define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!<Master Clock Output Enable */
lypinator 0:bb348c97df44 5841
lypinator 0:bb348c97df44 5842 /******************************************************************************/
lypinator 0:bb348c97df44 5843 /* */
lypinator 0:bb348c97df44 5844 /* SYSCFG */
lypinator 0:bb348c97df44 5845 /* */
lypinator 0:bb348c97df44 5846 /******************************************************************************/
lypinator 0:bb348c97df44 5847 /****************** Bit definition for SYSCFG_MEMRMP register ***************/
lypinator 0:bb348c97df44 5848 #define SYSCFG_MEMRMP_MEM_MODE_Pos (0U)
lypinator 0:bb348c97df44 5849 #define SYSCFG_MEMRMP_MEM_MODE_Msk (0x3U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000003 */
lypinator 0:bb348c97df44 5850 #define SYSCFG_MEMRMP_MEM_MODE SYSCFG_MEMRMP_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */
lypinator 0:bb348c97df44 5851 #define SYSCFG_MEMRMP_MEM_MODE_0 (0x1U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 5852 #define SYSCFG_MEMRMP_MEM_MODE_1 (0x2U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 5853 /****************** Bit definition for SYSCFG_PMC register ******************/
lypinator 0:bb348c97df44 5854 #define SYSCFG_PMC_ADC1DC2_Pos (16U)
lypinator 0:bb348c97df44 5855 #define SYSCFG_PMC_ADC1DC2_Msk (0x1U << SYSCFG_PMC_ADC1DC2_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 5856 #define SYSCFG_PMC_ADC1DC2 SYSCFG_PMC_ADC1DC2_Msk /*!< Refer to AN4073 on how to use this bit */
lypinator 0:bb348c97df44 5857
lypinator 0:bb348c97df44 5858 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
lypinator 0:bb348c97df44 5859 #define SYSCFG_EXTICR1_EXTI0_Pos (0U)
lypinator 0:bb348c97df44 5860 #define SYSCFG_EXTICR1_EXTI0_Msk (0xFU << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
lypinator 0:bb348c97df44 5861 #define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!<EXTI 0 configuration */
lypinator 0:bb348c97df44 5862 #define SYSCFG_EXTICR1_EXTI1_Pos (4U)
lypinator 0:bb348c97df44 5863 #define SYSCFG_EXTICR1_EXTI1_Msk (0xFU << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
lypinator 0:bb348c97df44 5864 #define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!<EXTI 1 configuration */
lypinator 0:bb348c97df44 5865 #define SYSCFG_EXTICR1_EXTI2_Pos (8U)
lypinator 0:bb348c97df44 5866 #define SYSCFG_EXTICR1_EXTI2_Msk (0xFU << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
lypinator 0:bb348c97df44 5867 #define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!<EXTI 2 configuration */
lypinator 0:bb348c97df44 5868 #define SYSCFG_EXTICR1_EXTI3_Pos (12U)
lypinator 0:bb348c97df44 5869 #define SYSCFG_EXTICR1_EXTI3_Msk (0xFU << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
lypinator 0:bb348c97df44 5870 #define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!<EXTI 3 configuration */
lypinator 0:bb348c97df44 5871 /**
lypinator 0:bb348c97df44 5872 * @brief EXTI0 configuration
lypinator 0:bb348c97df44 5873 */
lypinator 0:bb348c97df44 5874 #define SYSCFG_EXTICR1_EXTI0_PA 0x0000U /*!<PA[0] pin */
lypinator 0:bb348c97df44 5875 #define SYSCFG_EXTICR1_EXTI0_PB 0x0001U /*!<PB[0] pin */
lypinator 0:bb348c97df44 5876 #define SYSCFG_EXTICR1_EXTI0_PC 0x0002U /*!<PC[0] pin */
lypinator 0:bb348c97df44 5877 #define SYSCFG_EXTICR1_EXTI0_PD 0x0003U /*!<PD[0] pin */
lypinator 0:bb348c97df44 5878 #define SYSCFG_EXTICR1_EXTI0_PE 0x0004U /*!<PE[0] pin */
lypinator 0:bb348c97df44 5879 #define SYSCFG_EXTICR1_EXTI0_PH 0x0007U /*!<PH[0] pin */
lypinator 0:bb348c97df44 5880
lypinator 0:bb348c97df44 5881 /**
lypinator 0:bb348c97df44 5882 * @brief EXTI1 configuration
lypinator 0:bb348c97df44 5883 */
lypinator 0:bb348c97df44 5884 #define SYSCFG_EXTICR1_EXTI1_PA 0x0000U /*!<PA[1] pin */
lypinator 0:bb348c97df44 5885 #define SYSCFG_EXTICR1_EXTI1_PB 0x0010U /*!<PB[1] pin */
lypinator 0:bb348c97df44 5886 #define SYSCFG_EXTICR1_EXTI1_PC 0x0020U /*!<PC[1] pin */
lypinator 0:bb348c97df44 5887 #define SYSCFG_EXTICR1_EXTI1_PD 0x0030U /*!<PD[1] pin */
lypinator 0:bb348c97df44 5888 #define SYSCFG_EXTICR1_EXTI1_PE 0x0040U /*!<PE[1] pin */
lypinator 0:bb348c97df44 5889 #define SYSCFG_EXTICR1_EXTI1_PH 0x0070U /*!<PH[1] pin */
lypinator 0:bb348c97df44 5890
lypinator 0:bb348c97df44 5891 /**
lypinator 0:bb348c97df44 5892 * @brief EXTI2 configuration
lypinator 0:bb348c97df44 5893 */
lypinator 0:bb348c97df44 5894 #define SYSCFG_EXTICR1_EXTI2_PA 0x0000U /*!<PA[2] pin */
lypinator 0:bb348c97df44 5895 #define SYSCFG_EXTICR1_EXTI2_PB 0x0100U /*!<PB[2] pin */
lypinator 0:bb348c97df44 5896 #define SYSCFG_EXTICR1_EXTI2_PC 0x0200U /*!<PC[2] pin */
lypinator 0:bb348c97df44 5897 #define SYSCFG_EXTICR1_EXTI2_PD 0x0300U /*!<PD[2] pin */
lypinator 0:bb348c97df44 5898 #define SYSCFG_EXTICR1_EXTI2_PE 0x0400U /*!<PE[2] pin */
lypinator 0:bb348c97df44 5899 #define SYSCFG_EXTICR1_EXTI2_PH 0x0700U /*!<PH[2] pin */
lypinator 0:bb348c97df44 5900
lypinator 0:bb348c97df44 5901 /**
lypinator 0:bb348c97df44 5902 * @brief EXTI3 configuration
lypinator 0:bb348c97df44 5903 */
lypinator 0:bb348c97df44 5904 #define SYSCFG_EXTICR1_EXTI3_PA 0x0000U /*!<PA[3] pin */
lypinator 0:bb348c97df44 5905 #define SYSCFG_EXTICR1_EXTI3_PB 0x1000U /*!<PB[3] pin */
lypinator 0:bb348c97df44 5906 #define SYSCFG_EXTICR1_EXTI3_PC 0x2000U /*!<PC[3] pin */
lypinator 0:bb348c97df44 5907 #define SYSCFG_EXTICR1_EXTI3_PD 0x3000U /*!<PD[3] pin */
lypinator 0:bb348c97df44 5908 #define SYSCFG_EXTICR1_EXTI3_PE 0x4000U /*!<PE[3] pin */
lypinator 0:bb348c97df44 5909 #define SYSCFG_EXTICR1_EXTI3_PH 0x7000U /*!<PH[3] pin */
lypinator 0:bb348c97df44 5910
lypinator 0:bb348c97df44 5911 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
lypinator 0:bb348c97df44 5912 #define SYSCFG_EXTICR2_EXTI4_Pos (0U)
lypinator 0:bb348c97df44 5913 #define SYSCFG_EXTICR2_EXTI4_Msk (0xFU << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
lypinator 0:bb348c97df44 5914 #define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!<EXTI 4 configuration */
lypinator 0:bb348c97df44 5915 #define SYSCFG_EXTICR2_EXTI5_Pos (4U)
lypinator 0:bb348c97df44 5916 #define SYSCFG_EXTICR2_EXTI5_Msk (0xFU << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
lypinator 0:bb348c97df44 5917 #define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!<EXTI 5 configuration */
lypinator 0:bb348c97df44 5918 #define SYSCFG_EXTICR2_EXTI6_Pos (8U)
lypinator 0:bb348c97df44 5919 #define SYSCFG_EXTICR2_EXTI6_Msk (0xFU << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
lypinator 0:bb348c97df44 5920 #define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!<EXTI 6 configuration */
lypinator 0:bb348c97df44 5921 #define SYSCFG_EXTICR2_EXTI7_Pos (12U)
lypinator 0:bb348c97df44 5922 #define SYSCFG_EXTICR2_EXTI7_Msk (0xFU << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
lypinator 0:bb348c97df44 5923 #define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!<EXTI 7 configuration */
lypinator 0:bb348c97df44 5924
lypinator 0:bb348c97df44 5925 /**
lypinator 0:bb348c97df44 5926 * @brief EXTI4 configuration
lypinator 0:bb348c97df44 5927 */
lypinator 0:bb348c97df44 5928 #define SYSCFG_EXTICR2_EXTI4_PA 0x0000U /*!<PA[4] pin */
lypinator 0:bb348c97df44 5929 #define SYSCFG_EXTICR2_EXTI4_PB 0x0001U /*!<PB[4] pin */
lypinator 0:bb348c97df44 5930 #define SYSCFG_EXTICR2_EXTI4_PC 0x0002U /*!<PC[4] pin */
lypinator 0:bb348c97df44 5931 #define SYSCFG_EXTICR2_EXTI4_PD 0x0003U /*!<PD[4] pin */
lypinator 0:bb348c97df44 5932 #define SYSCFG_EXTICR2_EXTI4_PE 0x0004U /*!<PE[4] pin */
lypinator 0:bb348c97df44 5933 #define SYSCFG_EXTICR2_EXTI4_PH 0x0007U /*!<PH[4] pin */
lypinator 0:bb348c97df44 5934
lypinator 0:bb348c97df44 5935 /**
lypinator 0:bb348c97df44 5936 * @brief EXTI5 configuration
lypinator 0:bb348c97df44 5937 */
lypinator 0:bb348c97df44 5938 #define SYSCFG_EXTICR2_EXTI5_PA 0x0000U /*!<PA[5] pin */
lypinator 0:bb348c97df44 5939 #define SYSCFG_EXTICR2_EXTI5_PB 0x0010U /*!<PB[5] pin */
lypinator 0:bb348c97df44 5940 #define SYSCFG_EXTICR2_EXTI5_PC 0x0020U /*!<PC[5] pin */
lypinator 0:bb348c97df44 5941 #define SYSCFG_EXTICR2_EXTI5_PD 0x0030U /*!<PD[5] pin */
lypinator 0:bb348c97df44 5942 #define SYSCFG_EXTICR2_EXTI5_PE 0x0040U /*!<PE[5] pin */
lypinator 0:bb348c97df44 5943 #define SYSCFG_EXTICR2_EXTI5_PH 0x0070U /*!<PH[5] pin */
lypinator 0:bb348c97df44 5944
lypinator 0:bb348c97df44 5945 /**
lypinator 0:bb348c97df44 5946 * @brief EXTI6 configuration
lypinator 0:bb348c97df44 5947 */
lypinator 0:bb348c97df44 5948 #define SYSCFG_EXTICR2_EXTI6_PA 0x0000U /*!<PA[6] pin */
lypinator 0:bb348c97df44 5949 #define SYSCFG_EXTICR2_EXTI6_PB 0x0100U /*!<PB[6] pin */
lypinator 0:bb348c97df44 5950 #define SYSCFG_EXTICR2_EXTI6_PC 0x0200U /*!<PC[6] pin */
lypinator 0:bb348c97df44 5951 #define SYSCFG_EXTICR2_EXTI6_PD 0x0300U /*!<PD[6] pin */
lypinator 0:bb348c97df44 5952 #define SYSCFG_EXTICR2_EXTI6_PE 0x0400U /*!<PE[6] pin */
lypinator 0:bb348c97df44 5953 #define SYSCFG_EXTICR2_EXTI6_PH 0x0700U /*!<PH[6] pin */
lypinator 0:bb348c97df44 5954
lypinator 0:bb348c97df44 5955 /**
lypinator 0:bb348c97df44 5956 * @brief EXTI7 configuration
lypinator 0:bb348c97df44 5957 */
lypinator 0:bb348c97df44 5958 #define SYSCFG_EXTICR2_EXTI7_PA 0x0000U /*!<PA[7] pin */
lypinator 0:bb348c97df44 5959 #define SYSCFG_EXTICR2_EXTI7_PB 0x1000U /*!<PB[7] pin */
lypinator 0:bb348c97df44 5960 #define SYSCFG_EXTICR2_EXTI7_PC 0x2000U /*!<PC[7] pin */
lypinator 0:bb348c97df44 5961 #define SYSCFG_EXTICR2_EXTI7_PD 0x3000U /*!<PD[7] pin */
lypinator 0:bb348c97df44 5962 #define SYSCFG_EXTICR2_EXTI7_PE 0x4000U /*!<PE[7] pin */
lypinator 0:bb348c97df44 5963 #define SYSCFG_EXTICR2_EXTI7_PH 0x7000U /*!<PH[7] pin */
lypinator 0:bb348c97df44 5964
lypinator 0:bb348c97df44 5965 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
lypinator 0:bb348c97df44 5966 #define SYSCFG_EXTICR3_EXTI8_Pos (0U)
lypinator 0:bb348c97df44 5967 #define SYSCFG_EXTICR3_EXTI8_Msk (0xFU << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
lypinator 0:bb348c97df44 5968 #define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!<EXTI 8 configuration */
lypinator 0:bb348c97df44 5969 #define SYSCFG_EXTICR3_EXTI9_Pos (4U)
lypinator 0:bb348c97df44 5970 #define SYSCFG_EXTICR3_EXTI9_Msk (0xFU << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
lypinator 0:bb348c97df44 5971 #define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!<EXTI 9 configuration */
lypinator 0:bb348c97df44 5972 #define SYSCFG_EXTICR3_EXTI10_Pos (8U)
lypinator 0:bb348c97df44 5973 #define SYSCFG_EXTICR3_EXTI10_Msk (0xFU << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
lypinator 0:bb348c97df44 5974 #define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!<EXTI 10 configuration */
lypinator 0:bb348c97df44 5975 #define SYSCFG_EXTICR3_EXTI11_Pos (12U)
lypinator 0:bb348c97df44 5976 #define SYSCFG_EXTICR3_EXTI11_Msk (0xFU << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
lypinator 0:bb348c97df44 5977 #define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!<EXTI 11 configuration */
lypinator 0:bb348c97df44 5978
lypinator 0:bb348c97df44 5979 /**
lypinator 0:bb348c97df44 5980 * @brief EXTI8 configuration
lypinator 0:bb348c97df44 5981 */
lypinator 0:bb348c97df44 5982 #define SYSCFG_EXTICR3_EXTI8_PA 0x0000U /*!<PA[8] pin */
lypinator 0:bb348c97df44 5983 #define SYSCFG_EXTICR3_EXTI8_PB 0x0001U /*!<PB[8] pin */
lypinator 0:bb348c97df44 5984 #define SYSCFG_EXTICR3_EXTI8_PC 0x0002U /*!<PC[8] pin */
lypinator 0:bb348c97df44 5985 #define SYSCFG_EXTICR3_EXTI8_PD 0x0003U /*!<PD[8] pin */
lypinator 0:bb348c97df44 5986 #define SYSCFG_EXTICR3_EXTI8_PE 0x0004U /*!<PE[8] pin */
lypinator 0:bb348c97df44 5987 #define SYSCFG_EXTICR3_EXTI8_PH 0x0007U /*!<PH[8] pin */
lypinator 0:bb348c97df44 5988
lypinator 0:bb348c97df44 5989 /**
lypinator 0:bb348c97df44 5990 * @brief EXTI9 configuration
lypinator 0:bb348c97df44 5991 */
lypinator 0:bb348c97df44 5992 #define SYSCFG_EXTICR3_EXTI9_PA 0x0000U /*!<PA[9] pin */
lypinator 0:bb348c97df44 5993 #define SYSCFG_EXTICR3_EXTI9_PB 0x0010U /*!<PB[9] pin */
lypinator 0:bb348c97df44 5994 #define SYSCFG_EXTICR3_EXTI9_PC 0x0020U /*!<PC[9] pin */
lypinator 0:bb348c97df44 5995 #define SYSCFG_EXTICR3_EXTI9_PD 0x0030U /*!<PD[9] pin */
lypinator 0:bb348c97df44 5996 #define SYSCFG_EXTICR3_EXTI9_PE 0x0040U /*!<PE[9] pin */
lypinator 0:bb348c97df44 5997 #define SYSCFG_EXTICR3_EXTI9_PH 0x0070U /*!<PH[9] pin */
lypinator 0:bb348c97df44 5998
lypinator 0:bb348c97df44 5999 /**
lypinator 0:bb348c97df44 6000 * @brief EXTI10 configuration
lypinator 0:bb348c97df44 6001 */
lypinator 0:bb348c97df44 6002 #define SYSCFG_EXTICR3_EXTI10_PA 0x0000U /*!<PA[10] pin */
lypinator 0:bb348c97df44 6003 #define SYSCFG_EXTICR3_EXTI10_PB 0x0100U /*!<PB[10] pin */
lypinator 0:bb348c97df44 6004 #define SYSCFG_EXTICR3_EXTI10_PC 0x0200U /*!<PC[10] pin */
lypinator 0:bb348c97df44 6005 #define SYSCFG_EXTICR3_EXTI10_PD 0x0300U /*!<PD[10] pin */
lypinator 0:bb348c97df44 6006 #define SYSCFG_EXTICR3_EXTI10_PE 0x0400U /*!<PE[10] pin */
lypinator 0:bb348c97df44 6007 #define SYSCFG_EXTICR3_EXTI10_PH 0x0700U /*!<PH[10] pin */
lypinator 0:bb348c97df44 6008
lypinator 0:bb348c97df44 6009 /**
lypinator 0:bb348c97df44 6010 * @brief EXTI11 configuration
lypinator 0:bb348c97df44 6011 */
lypinator 0:bb348c97df44 6012 #define SYSCFG_EXTICR3_EXTI11_PA 0x0000U /*!<PA[11] pin */
lypinator 0:bb348c97df44 6013 #define SYSCFG_EXTICR3_EXTI11_PB 0x1000U /*!<PB[11] pin */
lypinator 0:bb348c97df44 6014 #define SYSCFG_EXTICR3_EXTI11_PC 0x2000U /*!<PC[11] pin */
lypinator 0:bb348c97df44 6015 #define SYSCFG_EXTICR3_EXTI11_PD 0x3000U /*!<PD[11] pin */
lypinator 0:bb348c97df44 6016 #define SYSCFG_EXTICR3_EXTI11_PE 0x4000U /*!<PE[11] pin */
lypinator 0:bb348c97df44 6017 #define SYSCFG_EXTICR3_EXTI11_PH 0x7000U /*!<PH[11] pin */
lypinator 0:bb348c97df44 6018
lypinator 0:bb348c97df44 6019 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
lypinator 0:bb348c97df44 6020 #define SYSCFG_EXTICR4_EXTI12_Pos (0U)
lypinator 0:bb348c97df44 6021 #define SYSCFG_EXTICR4_EXTI12_Msk (0xFU << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
lypinator 0:bb348c97df44 6022 #define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!<EXTI 12 configuration */
lypinator 0:bb348c97df44 6023 #define SYSCFG_EXTICR4_EXTI13_Pos (4U)
lypinator 0:bb348c97df44 6024 #define SYSCFG_EXTICR4_EXTI13_Msk (0xFU << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
lypinator 0:bb348c97df44 6025 #define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!<EXTI 13 configuration */
lypinator 0:bb348c97df44 6026 #define SYSCFG_EXTICR4_EXTI14_Pos (8U)
lypinator 0:bb348c97df44 6027 #define SYSCFG_EXTICR4_EXTI14_Msk (0xFU << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
lypinator 0:bb348c97df44 6028 #define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!<EXTI 14 configuration */
lypinator 0:bb348c97df44 6029 #define SYSCFG_EXTICR4_EXTI15_Pos (12U)
lypinator 0:bb348c97df44 6030 #define SYSCFG_EXTICR4_EXTI15_Msk (0xFU << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
lypinator 0:bb348c97df44 6031 #define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!<EXTI 15 configuration */
lypinator 0:bb348c97df44 6032
lypinator 0:bb348c97df44 6033 /**
lypinator 0:bb348c97df44 6034 * @brief EXTI12 configuration
lypinator 0:bb348c97df44 6035 */
lypinator 0:bb348c97df44 6036 #define SYSCFG_EXTICR4_EXTI12_PA 0x0000U /*!<PA[12] pin */
lypinator 0:bb348c97df44 6037 #define SYSCFG_EXTICR4_EXTI12_PB 0x0001U /*!<PB[12] pin */
lypinator 0:bb348c97df44 6038 #define SYSCFG_EXTICR4_EXTI12_PC 0x0002U /*!<PC[12] pin */
lypinator 0:bb348c97df44 6039 #define SYSCFG_EXTICR4_EXTI12_PD 0x0003U /*!<PD[12] pin */
lypinator 0:bb348c97df44 6040 #define SYSCFG_EXTICR4_EXTI12_PE 0x0004U /*!<PE[12] pin */
lypinator 0:bb348c97df44 6041 #define SYSCFG_EXTICR4_EXTI12_PH 0x0007U /*!<PH[12] pin */
lypinator 0:bb348c97df44 6042
lypinator 0:bb348c97df44 6043 /**
lypinator 0:bb348c97df44 6044 * @brief EXTI13 configuration
lypinator 0:bb348c97df44 6045 */
lypinator 0:bb348c97df44 6046 #define SYSCFG_EXTICR4_EXTI13_PA 0x0000U /*!<PA[13] pin */
lypinator 0:bb348c97df44 6047 #define SYSCFG_EXTICR4_EXTI13_PB 0x0010U /*!<PB[13] pin */
lypinator 0:bb348c97df44 6048 #define SYSCFG_EXTICR4_EXTI13_PC 0x0020U /*!<PC[13] pin */
lypinator 0:bb348c97df44 6049 #define SYSCFG_EXTICR4_EXTI13_PD 0x0030U /*!<PD[13] pin */
lypinator 0:bb348c97df44 6050 #define SYSCFG_EXTICR4_EXTI13_PE 0x0040U /*!<PE[13] pin */
lypinator 0:bb348c97df44 6051 #define SYSCFG_EXTICR4_EXTI13_PH 0x0070U /*!<PH[13] pin */
lypinator 0:bb348c97df44 6052
lypinator 0:bb348c97df44 6053 /**
lypinator 0:bb348c97df44 6054 * @brief EXTI14 configuration
lypinator 0:bb348c97df44 6055 */
lypinator 0:bb348c97df44 6056 #define SYSCFG_EXTICR4_EXTI14_PA 0x0000U /*!<PA[14] pin */
lypinator 0:bb348c97df44 6057 #define SYSCFG_EXTICR4_EXTI14_PB 0x0100U /*!<PB[14] pin */
lypinator 0:bb348c97df44 6058 #define SYSCFG_EXTICR4_EXTI14_PC 0x0200U /*!<PC[14] pin */
lypinator 0:bb348c97df44 6059 #define SYSCFG_EXTICR4_EXTI14_PD 0x0300U /*!<PD[14] pin */
lypinator 0:bb348c97df44 6060 #define SYSCFG_EXTICR4_EXTI14_PE 0x0400U /*!<PE[14] pin */
lypinator 0:bb348c97df44 6061 #define SYSCFG_EXTICR4_EXTI14_PH 0x0700U /*!<PH[14] pin */
lypinator 0:bb348c97df44 6062
lypinator 0:bb348c97df44 6063 /**
lypinator 0:bb348c97df44 6064 * @brief EXTI15 configuration
lypinator 0:bb348c97df44 6065 */
lypinator 0:bb348c97df44 6066 #define SYSCFG_EXTICR4_EXTI15_PA 0x0000U /*!<PA[15] pin */
lypinator 0:bb348c97df44 6067 #define SYSCFG_EXTICR4_EXTI15_PB 0x1000U /*!<PB[15] pin */
lypinator 0:bb348c97df44 6068 #define SYSCFG_EXTICR4_EXTI15_PC 0x2000U /*!<PC[15] pin */
lypinator 0:bb348c97df44 6069 #define SYSCFG_EXTICR4_EXTI15_PD 0x3000U /*!<PD[15] pin */
lypinator 0:bb348c97df44 6070 #define SYSCFG_EXTICR4_EXTI15_PE 0x4000U /*!<PE[15] pin */
lypinator 0:bb348c97df44 6071 #define SYSCFG_EXTICR4_EXTI15_PH 0x7000U /*!<PH[15] pin */
lypinator 0:bb348c97df44 6072
lypinator 0:bb348c97df44 6073 /****************** Bit definition for SYSCFG_CMPCR register ****************/
lypinator 0:bb348c97df44 6074 #define SYSCFG_CMPCR_CMP_PD_Pos (0U)
lypinator 0:bb348c97df44 6075 #define SYSCFG_CMPCR_CMP_PD_Msk (0x1U << SYSCFG_CMPCR_CMP_PD_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 6076 #define SYSCFG_CMPCR_CMP_PD SYSCFG_CMPCR_CMP_PD_Msk /*!<Compensation cell ready flag */
lypinator 0:bb348c97df44 6077 #define SYSCFG_CMPCR_READY_Pos (8U)
lypinator 0:bb348c97df44 6078 #define SYSCFG_CMPCR_READY_Msk (0x1U << SYSCFG_CMPCR_READY_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 6079 #define SYSCFG_CMPCR_READY SYSCFG_CMPCR_READY_Msk /*!<Compensation cell power-down */
lypinator 0:bb348c97df44 6080
lypinator 0:bb348c97df44 6081 /******************************************************************************/
lypinator 0:bb348c97df44 6082 /* */
lypinator 0:bb348c97df44 6083 /* TIM */
lypinator 0:bb348c97df44 6084 /* */
lypinator 0:bb348c97df44 6085 /******************************************************************************/
lypinator 0:bb348c97df44 6086 /******************* Bit definition for TIM_CR1 register ********************/
lypinator 0:bb348c97df44 6087 #define TIM_CR1_CEN_Pos (0U)
lypinator 0:bb348c97df44 6088 #define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 6089 #define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
lypinator 0:bb348c97df44 6090 #define TIM_CR1_UDIS_Pos (1U)
lypinator 0:bb348c97df44 6091 #define TIM_CR1_UDIS_Msk (0x1U << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 6092 #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
lypinator 0:bb348c97df44 6093 #define TIM_CR1_URS_Pos (2U)
lypinator 0:bb348c97df44 6094 #define TIM_CR1_URS_Msk (0x1U << TIM_CR1_URS_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 6095 #define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
lypinator 0:bb348c97df44 6096 #define TIM_CR1_OPM_Pos (3U)
lypinator 0:bb348c97df44 6097 #define TIM_CR1_OPM_Msk (0x1U << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 6098 #define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
lypinator 0:bb348c97df44 6099 #define TIM_CR1_DIR_Pos (4U)
lypinator 0:bb348c97df44 6100 #define TIM_CR1_DIR_Msk (0x1U << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 6101 #define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
lypinator 0:bb348c97df44 6102
lypinator 0:bb348c97df44 6103 #define TIM_CR1_CMS_Pos (5U)
lypinator 0:bb348c97df44 6104 #define TIM_CR1_CMS_Msk (0x3U << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
lypinator 0:bb348c97df44 6105 #define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
lypinator 0:bb348c97df44 6106 #define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) /*!< 0x0020 */
lypinator 0:bb348c97df44 6107 #define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) /*!< 0x0040 */
lypinator 0:bb348c97df44 6108
lypinator 0:bb348c97df44 6109 #define TIM_CR1_ARPE_Pos (7U)
lypinator 0:bb348c97df44 6110 #define TIM_CR1_ARPE_Msk (0x1U << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 6111 #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
lypinator 0:bb348c97df44 6112
lypinator 0:bb348c97df44 6113 #define TIM_CR1_CKD_Pos (8U)
lypinator 0:bb348c97df44 6114 #define TIM_CR1_CKD_Msk (0x3U << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
lypinator 0:bb348c97df44 6115 #define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
lypinator 0:bb348c97df44 6116 #define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) /*!< 0x0100 */
lypinator 0:bb348c97df44 6117 #define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) /*!< 0x0200 */
lypinator 0:bb348c97df44 6118
lypinator 0:bb348c97df44 6119 /******************* Bit definition for TIM_CR2 register ********************/
lypinator 0:bb348c97df44 6120 #define TIM_CR2_CCPC_Pos (0U)
lypinator 0:bb348c97df44 6121 #define TIM_CR2_CCPC_Msk (0x1U << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 6122 #define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
lypinator 0:bb348c97df44 6123 #define TIM_CR2_CCUS_Pos (2U)
lypinator 0:bb348c97df44 6124 #define TIM_CR2_CCUS_Msk (0x1U << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 6125 #define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
lypinator 0:bb348c97df44 6126 #define TIM_CR2_CCDS_Pos (3U)
lypinator 0:bb348c97df44 6127 #define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 6128 #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
lypinator 0:bb348c97df44 6129
lypinator 0:bb348c97df44 6130 #define TIM_CR2_MMS_Pos (4U)
lypinator 0:bb348c97df44 6131 #define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
lypinator 0:bb348c97df44 6132 #define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
lypinator 0:bb348c97df44 6133 #define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /*!< 0x0010 */
lypinator 0:bb348c97df44 6134 #define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x0020 */
lypinator 0:bb348c97df44 6135 #define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /*!< 0x0040 */
lypinator 0:bb348c97df44 6136
lypinator 0:bb348c97df44 6137 #define TIM_CR2_TI1S_Pos (7U)
lypinator 0:bb348c97df44 6138 #define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 6139 #define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
lypinator 0:bb348c97df44 6140 #define TIM_CR2_OIS1_Pos (8U)
lypinator 0:bb348c97df44 6141 #define TIM_CR2_OIS1_Msk (0x1U << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 6142 #define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
lypinator 0:bb348c97df44 6143 #define TIM_CR2_OIS1N_Pos (9U)
lypinator 0:bb348c97df44 6144 #define TIM_CR2_OIS1N_Msk (0x1U << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 6145 #define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
lypinator 0:bb348c97df44 6146 #define TIM_CR2_OIS2_Pos (10U)
lypinator 0:bb348c97df44 6147 #define TIM_CR2_OIS2_Msk (0x1U << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 6148 #define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
lypinator 0:bb348c97df44 6149 #define TIM_CR2_OIS2N_Pos (11U)
lypinator 0:bb348c97df44 6150 #define TIM_CR2_OIS2N_Msk (0x1U << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 6151 #define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
lypinator 0:bb348c97df44 6152 #define TIM_CR2_OIS3_Pos (12U)
lypinator 0:bb348c97df44 6153 #define TIM_CR2_OIS3_Msk (0x1U << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 6154 #define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
lypinator 0:bb348c97df44 6155 #define TIM_CR2_OIS3N_Pos (13U)
lypinator 0:bb348c97df44 6156 #define TIM_CR2_OIS3N_Msk (0x1U << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 6157 #define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
lypinator 0:bb348c97df44 6158 #define TIM_CR2_OIS4_Pos (14U)
lypinator 0:bb348c97df44 6159 #define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 6160 #define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
lypinator 0:bb348c97df44 6161
lypinator 0:bb348c97df44 6162 /******************* Bit definition for TIM_SMCR register *******************/
lypinator 0:bb348c97df44 6163 #define TIM_SMCR_SMS_Pos (0U)
lypinator 0:bb348c97df44 6164 #define TIM_SMCR_SMS_Msk (0x7U << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */
lypinator 0:bb348c97df44 6165 #define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
lypinator 0:bb348c97df44 6166 #define TIM_SMCR_SMS_0 (0x1U << TIM_SMCR_SMS_Pos) /*!< 0x0001 */
lypinator 0:bb348c97df44 6167 #define TIM_SMCR_SMS_1 (0x2U << TIM_SMCR_SMS_Pos) /*!< 0x0002 */
lypinator 0:bb348c97df44 6168 #define TIM_SMCR_SMS_2 (0x4U << TIM_SMCR_SMS_Pos) /*!< 0x0004 */
lypinator 0:bb348c97df44 6169
lypinator 0:bb348c97df44 6170 #define TIM_SMCR_TS_Pos (4U)
lypinator 0:bb348c97df44 6171 #define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
lypinator 0:bb348c97df44 6172 #define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
lypinator 0:bb348c97df44 6173 #define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) /*!< 0x0010 */
lypinator 0:bb348c97df44 6174 #define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) /*!< 0x0020 */
lypinator 0:bb348c97df44 6175 #define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) /*!< 0x0040 */
lypinator 0:bb348c97df44 6176
lypinator 0:bb348c97df44 6177 #define TIM_SMCR_MSM_Pos (7U)
lypinator 0:bb348c97df44 6178 #define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 6179 #define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
lypinator 0:bb348c97df44 6180
lypinator 0:bb348c97df44 6181 #define TIM_SMCR_ETF_Pos (8U)
lypinator 0:bb348c97df44 6182 #define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
lypinator 0:bb348c97df44 6183 #define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
lypinator 0:bb348c97df44 6184 #define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /*!< 0x0100 */
lypinator 0:bb348c97df44 6185 #define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /*!< 0x0200 */
lypinator 0:bb348c97df44 6186 #define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /*!< 0x0400 */
lypinator 0:bb348c97df44 6187 #define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /*!< 0x0800 */
lypinator 0:bb348c97df44 6188
lypinator 0:bb348c97df44 6189 #define TIM_SMCR_ETPS_Pos (12U)
lypinator 0:bb348c97df44 6190 #define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
lypinator 0:bb348c97df44 6191 #define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
lypinator 0:bb348c97df44 6192 #define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /*!< 0x1000 */
lypinator 0:bb348c97df44 6193 #define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /*!< 0x2000 */
lypinator 0:bb348c97df44 6194
lypinator 0:bb348c97df44 6195 #define TIM_SMCR_ECE_Pos (14U)
lypinator 0:bb348c97df44 6196 #define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 6197 #define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
lypinator 0:bb348c97df44 6198 #define TIM_SMCR_ETP_Pos (15U)
lypinator 0:bb348c97df44 6199 #define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 6200 #define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
lypinator 0:bb348c97df44 6201
lypinator 0:bb348c97df44 6202 /******************* Bit definition for TIM_DIER register *******************/
lypinator 0:bb348c97df44 6203 #define TIM_DIER_UIE_Pos (0U)
lypinator 0:bb348c97df44 6204 #define TIM_DIER_UIE_Msk (0x1U << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 6205 #define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
lypinator 0:bb348c97df44 6206 #define TIM_DIER_CC1IE_Pos (1U)
lypinator 0:bb348c97df44 6207 #define TIM_DIER_CC1IE_Msk (0x1U << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 6208 #define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
lypinator 0:bb348c97df44 6209 #define TIM_DIER_CC2IE_Pos (2U)
lypinator 0:bb348c97df44 6210 #define TIM_DIER_CC2IE_Msk (0x1U << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 6211 #define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
lypinator 0:bb348c97df44 6212 #define TIM_DIER_CC3IE_Pos (3U)
lypinator 0:bb348c97df44 6213 #define TIM_DIER_CC3IE_Msk (0x1U << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 6214 #define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
lypinator 0:bb348c97df44 6215 #define TIM_DIER_CC4IE_Pos (4U)
lypinator 0:bb348c97df44 6216 #define TIM_DIER_CC4IE_Msk (0x1U << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 6217 #define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
lypinator 0:bb348c97df44 6218 #define TIM_DIER_COMIE_Pos (5U)
lypinator 0:bb348c97df44 6219 #define TIM_DIER_COMIE_Msk (0x1U << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 6220 #define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
lypinator 0:bb348c97df44 6221 #define TIM_DIER_TIE_Pos (6U)
lypinator 0:bb348c97df44 6222 #define TIM_DIER_TIE_Msk (0x1U << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 6223 #define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
lypinator 0:bb348c97df44 6224 #define TIM_DIER_BIE_Pos (7U)
lypinator 0:bb348c97df44 6225 #define TIM_DIER_BIE_Msk (0x1U << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 6226 #define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
lypinator 0:bb348c97df44 6227 #define TIM_DIER_UDE_Pos (8U)
lypinator 0:bb348c97df44 6228 #define TIM_DIER_UDE_Msk (0x1U << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 6229 #define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
lypinator 0:bb348c97df44 6230 #define TIM_DIER_CC1DE_Pos (9U)
lypinator 0:bb348c97df44 6231 #define TIM_DIER_CC1DE_Msk (0x1U << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 6232 #define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
lypinator 0:bb348c97df44 6233 #define TIM_DIER_CC2DE_Pos (10U)
lypinator 0:bb348c97df44 6234 #define TIM_DIER_CC2DE_Msk (0x1U << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 6235 #define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
lypinator 0:bb348c97df44 6236 #define TIM_DIER_CC3DE_Pos (11U)
lypinator 0:bb348c97df44 6237 #define TIM_DIER_CC3DE_Msk (0x1U << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 6238 #define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
lypinator 0:bb348c97df44 6239 #define TIM_DIER_CC4DE_Pos (12U)
lypinator 0:bb348c97df44 6240 #define TIM_DIER_CC4DE_Msk (0x1U << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 6241 #define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
lypinator 0:bb348c97df44 6242 #define TIM_DIER_COMDE_Pos (13U)
lypinator 0:bb348c97df44 6243 #define TIM_DIER_COMDE_Msk (0x1U << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 6244 #define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
lypinator 0:bb348c97df44 6245 #define TIM_DIER_TDE_Pos (14U)
lypinator 0:bb348c97df44 6246 #define TIM_DIER_TDE_Msk (0x1U << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 6247 #define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
lypinator 0:bb348c97df44 6248
lypinator 0:bb348c97df44 6249 /******************** Bit definition for TIM_SR register ********************/
lypinator 0:bb348c97df44 6250 #define TIM_SR_UIF_Pos (0U)
lypinator 0:bb348c97df44 6251 #define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 6252 #define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
lypinator 0:bb348c97df44 6253 #define TIM_SR_CC1IF_Pos (1U)
lypinator 0:bb348c97df44 6254 #define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 6255 #define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
lypinator 0:bb348c97df44 6256 #define TIM_SR_CC2IF_Pos (2U)
lypinator 0:bb348c97df44 6257 #define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 6258 #define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
lypinator 0:bb348c97df44 6259 #define TIM_SR_CC3IF_Pos (3U)
lypinator 0:bb348c97df44 6260 #define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 6261 #define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
lypinator 0:bb348c97df44 6262 #define TIM_SR_CC4IF_Pos (4U)
lypinator 0:bb348c97df44 6263 #define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 6264 #define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
lypinator 0:bb348c97df44 6265 #define TIM_SR_COMIF_Pos (5U)
lypinator 0:bb348c97df44 6266 #define TIM_SR_COMIF_Msk (0x1U << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 6267 #define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
lypinator 0:bb348c97df44 6268 #define TIM_SR_TIF_Pos (6U)
lypinator 0:bb348c97df44 6269 #define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 6270 #define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
lypinator 0:bb348c97df44 6271 #define TIM_SR_BIF_Pos (7U)
lypinator 0:bb348c97df44 6272 #define TIM_SR_BIF_Msk (0x1U << TIM_SR_BIF_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 6273 #define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
lypinator 0:bb348c97df44 6274 #define TIM_SR_CC1OF_Pos (9U)
lypinator 0:bb348c97df44 6275 #define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 6276 #define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
lypinator 0:bb348c97df44 6277 #define TIM_SR_CC2OF_Pos (10U)
lypinator 0:bb348c97df44 6278 #define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 6279 #define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
lypinator 0:bb348c97df44 6280 #define TIM_SR_CC3OF_Pos (11U)
lypinator 0:bb348c97df44 6281 #define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 6282 #define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
lypinator 0:bb348c97df44 6283 #define TIM_SR_CC4OF_Pos (12U)
lypinator 0:bb348c97df44 6284 #define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 6285 #define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
lypinator 0:bb348c97df44 6286
lypinator 0:bb348c97df44 6287 /******************* Bit definition for TIM_EGR register ********************/
lypinator 0:bb348c97df44 6288 #define TIM_EGR_UG_Pos (0U)
lypinator 0:bb348c97df44 6289 #define TIM_EGR_UG_Msk (0x1U << TIM_EGR_UG_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 6290 #define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
lypinator 0:bb348c97df44 6291 #define TIM_EGR_CC1G_Pos (1U)
lypinator 0:bb348c97df44 6292 #define TIM_EGR_CC1G_Msk (0x1U << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 6293 #define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
lypinator 0:bb348c97df44 6294 #define TIM_EGR_CC2G_Pos (2U)
lypinator 0:bb348c97df44 6295 #define TIM_EGR_CC2G_Msk (0x1U << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 6296 #define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
lypinator 0:bb348c97df44 6297 #define TIM_EGR_CC3G_Pos (3U)
lypinator 0:bb348c97df44 6298 #define TIM_EGR_CC3G_Msk (0x1U << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 6299 #define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
lypinator 0:bb348c97df44 6300 #define TIM_EGR_CC4G_Pos (4U)
lypinator 0:bb348c97df44 6301 #define TIM_EGR_CC4G_Msk (0x1U << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 6302 #define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
lypinator 0:bb348c97df44 6303 #define TIM_EGR_COMG_Pos (5U)
lypinator 0:bb348c97df44 6304 #define TIM_EGR_COMG_Msk (0x1U << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 6305 #define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
lypinator 0:bb348c97df44 6306 #define TIM_EGR_TG_Pos (6U)
lypinator 0:bb348c97df44 6307 #define TIM_EGR_TG_Msk (0x1U << TIM_EGR_TG_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 6308 #define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
lypinator 0:bb348c97df44 6309 #define TIM_EGR_BG_Pos (7U)
lypinator 0:bb348c97df44 6310 #define TIM_EGR_BG_Msk (0x1U << TIM_EGR_BG_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 6311 #define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
lypinator 0:bb348c97df44 6312
lypinator 0:bb348c97df44 6313 /****************** Bit definition for TIM_CCMR1 register *******************/
lypinator 0:bb348c97df44 6314 #define TIM_CCMR1_CC1S_Pos (0U)
lypinator 0:bb348c97df44 6315 #define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
lypinator 0:bb348c97df44 6316 #define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
lypinator 0:bb348c97df44 6317 #define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /*!< 0x0001 */
lypinator 0:bb348c97df44 6318 #define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /*!< 0x0002 */
lypinator 0:bb348c97df44 6319
lypinator 0:bb348c97df44 6320 #define TIM_CCMR1_OC1FE_Pos (2U)
lypinator 0:bb348c97df44 6321 #define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 6322 #define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
lypinator 0:bb348c97df44 6323 #define TIM_CCMR1_OC1PE_Pos (3U)
lypinator 0:bb348c97df44 6324 #define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 6325 #define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
lypinator 0:bb348c97df44 6326
lypinator 0:bb348c97df44 6327 #define TIM_CCMR1_OC1M_Pos (4U)
lypinator 0:bb348c97df44 6328 #define TIM_CCMR1_OC1M_Msk (0x7U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */
lypinator 0:bb348c97df44 6329 #define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
lypinator 0:bb348c97df44 6330 #define TIM_CCMR1_OC1M_0 (0x1U << TIM_CCMR1_OC1M_Pos) /*!< 0x0010 */
lypinator 0:bb348c97df44 6331 #define TIM_CCMR1_OC1M_1 (0x2U << TIM_CCMR1_OC1M_Pos) /*!< 0x0020 */
lypinator 0:bb348c97df44 6332 #define TIM_CCMR1_OC1M_2 (0x4U << TIM_CCMR1_OC1M_Pos) /*!< 0x0040 */
lypinator 0:bb348c97df44 6333
lypinator 0:bb348c97df44 6334 #define TIM_CCMR1_OC1CE_Pos (7U)
lypinator 0:bb348c97df44 6335 #define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 6336 #define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
lypinator 0:bb348c97df44 6337
lypinator 0:bb348c97df44 6338 #define TIM_CCMR1_CC2S_Pos (8U)
lypinator 0:bb348c97df44 6339 #define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
lypinator 0:bb348c97df44 6340 #define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
lypinator 0:bb348c97df44 6341 #define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /*!< 0x0100 */
lypinator 0:bb348c97df44 6342 #define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /*!< 0x0200 */
lypinator 0:bb348c97df44 6343
lypinator 0:bb348c97df44 6344 #define TIM_CCMR1_OC2FE_Pos (10U)
lypinator 0:bb348c97df44 6345 #define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 6346 #define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
lypinator 0:bb348c97df44 6347 #define TIM_CCMR1_OC2PE_Pos (11U)
lypinator 0:bb348c97df44 6348 #define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 6349 #define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
lypinator 0:bb348c97df44 6350
lypinator 0:bb348c97df44 6351 #define TIM_CCMR1_OC2M_Pos (12U)
lypinator 0:bb348c97df44 6352 #define TIM_CCMR1_OC2M_Msk (0x7U << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */
lypinator 0:bb348c97df44 6353 #define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
lypinator 0:bb348c97df44 6354 #define TIM_CCMR1_OC2M_0 (0x1U << TIM_CCMR1_OC2M_Pos) /*!< 0x1000 */
lypinator 0:bb348c97df44 6355 #define TIM_CCMR1_OC2M_1 (0x2U << TIM_CCMR1_OC2M_Pos) /*!< 0x2000 */
lypinator 0:bb348c97df44 6356 #define TIM_CCMR1_OC2M_2 (0x4U << TIM_CCMR1_OC2M_Pos) /*!< 0x4000 */
lypinator 0:bb348c97df44 6357
lypinator 0:bb348c97df44 6358 #define TIM_CCMR1_OC2CE_Pos (15U)
lypinator 0:bb348c97df44 6359 #define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 6360 #define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
lypinator 0:bb348c97df44 6361
lypinator 0:bb348c97df44 6362 /*----------------------------------------------------------------------------*/
lypinator 0:bb348c97df44 6363
lypinator 0:bb348c97df44 6364 #define TIM_CCMR1_IC1PSC_Pos (2U)
lypinator 0:bb348c97df44 6365 #define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
lypinator 0:bb348c97df44 6366 #define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
lypinator 0:bb348c97df44 6367 #define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0004 */
lypinator 0:bb348c97df44 6368 #define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0008 */
lypinator 0:bb348c97df44 6369
lypinator 0:bb348c97df44 6370 #define TIM_CCMR1_IC1F_Pos (4U)
lypinator 0:bb348c97df44 6371 #define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
lypinator 0:bb348c97df44 6372 #define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
lypinator 0:bb348c97df44 6373 #define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /*!< 0x0010 */
lypinator 0:bb348c97df44 6374 #define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /*!< 0x0020 */
lypinator 0:bb348c97df44 6375 #define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /*!< 0x0040 */
lypinator 0:bb348c97df44 6376 #define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /*!< 0x0080 */
lypinator 0:bb348c97df44 6377
lypinator 0:bb348c97df44 6378 #define TIM_CCMR1_IC2PSC_Pos (10U)
lypinator 0:bb348c97df44 6379 #define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
lypinator 0:bb348c97df44 6380 #define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
lypinator 0:bb348c97df44 6381 #define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x0400 */
lypinator 0:bb348c97df44 6382 #define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x0800 */
lypinator 0:bb348c97df44 6383
lypinator 0:bb348c97df44 6384 #define TIM_CCMR1_IC2F_Pos (12U)
lypinator 0:bb348c97df44 6385 #define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
lypinator 0:bb348c97df44 6386 #define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
lypinator 0:bb348c97df44 6387 #define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /*!< 0x1000 */
lypinator 0:bb348c97df44 6388 #define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /*!< 0x2000 */
lypinator 0:bb348c97df44 6389 #define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /*!< 0x4000 */
lypinator 0:bb348c97df44 6390 #define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /*!< 0x8000 */
lypinator 0:bb348c97df44 6391
lypinator 0:bb348c97df44 6392 /****************** Bit definition for TIM_CCMR2 register *******************/
lypinator 0:bb348c97df44 6393 #define TIM_CCMR2_CC3S_Pos (0U)
lypinator 0:bb348c97df44 6394 #define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
lypinator 0:bb348c97df44 6395 #define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
lypinator 0:bb348c97df44 6396 #define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /*!< 0x0001 */
lypinator 0:bb348c97df44 6397 #define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /*!< 0x0002 */
lypinator 0:bb348c97df44 6398
lypinator 0:bb348c97df44 6399 #define TIM_CCMR2_OC3FE_Pos (2U)
lypinator 0:bb348c97df44 6400 #define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 6401 #define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
lypinator 0:bb348c97df44 6402 #define TIM_CCMR2_OC3PE_Pos (3U)
lypinator 0:bb348c97df44 6403 #define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 6404 #define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
lypinator 0:bb348c97df44 6405
lypinator 0:bb348c97df44 6406 #define TIM_CCMR2_OC3M_Pos (4U)
lypinator 0:bb348c97df44 6407 #define TIM_CCMR2_OC3M_Msk (0x7U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
lypinator 0:bb348c97df44 6408 #define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
lypinator 0:bb348c97df44 6409 #define TIM_CCMR2_OC3M_0 (0x1U << TIM_CCMR2_OC3M_Pos) /*!< 0x0010 */
lypinator 0:bb348c97df44 6410 #define TIM_CCMR2_OC3M_1 (0x2U << TIM_CCMR2_OC3M_Pos) /*!< 0x0020 */
lypinator 0:bb348c97df44 6411 #define TIM_CCMR2_OC3M_2 (0x4U << TIM_CCMR2_OC3M_Pos) /*!< 0x0040 */
lypinator 0:bb348c97df44 6412
lypinator 0:bb348c97df44 6413 #define TIM_CCMR2_OC3CE_Pos (7U)
lypinator 0:bb348c97df44 6414 #define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 6415 #define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
lypinator 0:bb348c97df44 6416
lypinator 0:bb348c97df44 6417 #define TIM_CCMR2_CC4S_Pos (8U)
lypinator 0:bb348c97df44 6418 #define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
lypinator 0:bb348c97df44 6419 #define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
lypinator 0:bb348c97df44 6420 #define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /*!< 0x0100 */
lypinator 0:bb348c97df44 6421 #define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /*!< 0x0200 */
lypinator 0:bb348c97df44 6422
lypinator 0:bb348c97df44 6423 #define TIM_CCMR2_OC4FE_Pos (10U)
lypinator 0:bb348c97df44 6424 #define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 6425 #define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
lypinator 0:bb348c97df44 6426 #define TIM_CCMR2_OC4PE_Pos (11U)
lypinator 0:bb348c97df44 6427 #define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 6428 #define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
lypinator 0:bb348c97df44 6429
lypinator 0:bb348c97df44 6430 #define TIM_CCMR2_OC4M_Pos (12U)
lypinator 0:bb348c97df44 6431 #define TIM_CCMR2_OC4M_Msk (0x7U << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
lypinator 0:bb348c97df44 6432 #define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
lypinator 0:bb348c97df44 6433 #define TIM_CCMR2_OC4M_0 (0x1U << TIM_CCMR2_OC4M_Pos) /*!< 0x1000 */
lypinator 0:bb348c97df44 6434 #define TIM_CCMR2_OC4M_1 (0x2U << TIM_CCMR2_OC4M_Pos) /*!< 0x2000 */
lypinator 0:bb348c97df44 6435 #define TIM_CCMR2_OC4M_2 (0x4U << TIM_CCMR2_OC4M_Pos) /*!< 0x4000 */
lypinator 0:bb348c97df44 6436
lypinator 0:bb348c97df44 6437 #define TIM_CCMR2_OC4CE_Pos (15U)
lypinator 0:bb348c97df44 6438 #define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 6439 #define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
lypinator 0:bb348c97df44 6440
lypinator 0:bb348c97df44 6441 /*----------------------------------------------------------------------------*/
lypinator 0:bb348c97df44 6442
lypinator 0:bb348c97df44 6443 #define TIM_CCMR2_IC3PSC_Pos (2U)
lypinator 0:bb348c97df44 6444 #define TIM_CCMR2_IC3PSC_Msk (0x3U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
lypinator 0:bb348c97df44 6445 #define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
lypinator 0:bb348c97df44 6446 #define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0004 */
lypinator 0:bb348c97df44 6447 #define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0008 */
lypinator 0:bb348c97df44 6448
lypinator 0:bb348c97df44 6449 #define TIM_CCMR2_IC3F_Pos (4U)
lypinator 0:bb348c97df44 6450 #define TIM_CCMR2_IC3F_Msk (0xFU << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
lypinator 0:bb348c97df44 6451 #define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
lypinator 0:bb348c97df44 6452 #define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) /*!< 0x0010 */
lypinator 0:bb348c97df44 6453 #define TIM_CCMR2_IC3F_1 (0x2U << TIM_CCMR2_IC3F_Pos) /*!< 0x0020 */
lypinator 0:bb348c97df44 6454 #define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) /*!< 0x0040 */
lypinator 0:bb348c97df44 6455 #define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) /*!< 0x0080 */
lypinator 0:bb348c97df44 6456
lypinator 0:bb348c97df44 6457 #define TIM_CCMR2_IC4PSC_Pos (10U)
lypinator 0:bb348c97df44 6458 #define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
lypinator 0:bb348c97df44 6459 #define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
lypinator 0:bb348c97df44 6460 #define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x0400 */
lypinator 0:bb348c97df44 6461 #define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x0800 */
lypinator 0:bb348c97df44 6462
lypinator 0:bb348c97df44 6463 #define TIM_CCMR2_IC4F_Pos (12U)
lypinator 0:bb348c97df44 6464 #define TIM_CCMR2_IC4F_Msk (0xFU << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
lypinator 0:bb348c97df44 6465 #define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
lypinator 0:bb348c97df44 6466 #define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) /*!< 0x1000 */
lypinator 0:bb348c97df44 6467 #define TIM_CCMR2_IC4F_1 (0x2U << TIM_CCMR2_IC4F_Pos) /*!< 0x2000 */
lypinator 0:bb348c97df44 6468 #define TIM_CCMR2_IC4F_2 (0x4U << TIM_CCMR2_IC4F_Pos) /*!< 0x4000 */
lypinator 0:bb348c97df44 6469 #define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) /*!< 0x8000 */
lypinator 0:bb348c97df44 6470
lypinator 0:bb348c97df44 6471 /******************* Bit definition for TIM_CCER register *******************/
lypinator 0:bb348c97df44 6472 #define TIM_CCER_CC1E_Pos (0U)
lypinator 0:bb348c97df44 6473 #define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 6474 #define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
lypinator 0:bb348c97df44 6475 #define TIM_CCER_CC1P_Pos (1U)
lypinator 0:bb348c97df44 6476 #define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 6477 #define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
lypinator 0:bb348c97df44 6478 #define TIM_CCER_CC1NE_Pos (2U)
lypinator 0:bb348c97df44 6479 #define TIM_CCER_CC1NE_Msk (0x1U << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 6480 #define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
lypinator 0:bb348c97df44 6481 #define TIM_CCER_CC1NP_Pos (3U)
lypinator 0:bb348c97df44 6482 #define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 6483 #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
lypinator 0:bb348c97df44 6484 #define TIM_CCER_CC2E_Pos (4U)
lypinator 0:bb348c97df44 6485 #define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 6486 #define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
lypinator 0:bb348c97df44 6487 #define TIM_CCER_CC2P_Pos (5U)
lypinator 0:bb348c97df44 6488 #define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 6489 #define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
lypinator 0:bb348c97df44 6490 #define TIM_CCER_CC2NE_Pos (6U)
lypinator 0:bb348c97df44 6491 #define TIM_CCER_CC2NE_Msk (0x1U << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 6492 #define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
lypinator 0:bb348c97df44 6493 #define TIM_CCER_CC2NP_Pos (7U)
lypinator 0:bb348c97df44 6494 #define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 6495 #define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
lypinator 0:bb348c97df44 6496 #define TIM_CCER_CC3E_Pos (8U)
lypinator 0:bb348c97df44 6497 #define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 6498 #define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
lypinator 0:bb348c97df44 6499 #define TIM_CCER_CC3P_Pos (9U)
lypinator 0:bb348c97df44 6500 #define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 6501 #define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
lypinator 0:bb348c97df44 6502 #define TIM_CCER_CC3NE_Pos (10U)
lypinator 0:bb348c97df44 6503 #define TIM_CCER_CC3NE_Msk (0x1U << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 6504 #define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
lypinator 0:bb348c97df44 6505 #define TIM_CCER_CC3NP_Pos (11U)
lypinator 0:bb348c97df44 6506 #define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 6507 #define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
lypinator 0:bb348c97df44 6508 #define TIM_CCER_CC4E_Pos (12U)
lypinator 0:bb348c97df44 6509 #define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 6510 #define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
lypinator 0:bb348c97df44 6511 #define TIM_CCER_CC4P_Pos (13U)
lypinator 0:bb348c97df44 6512 #define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 6513 #define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
lypinator 0:bb348c97df44 6514 #define TIM_CCER_CC4NP_Pos (15U)
lypinator 0:bb348c97df44 6515 #define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 6516 #define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
lypinator 0:bb348c97df44 6517
lypinator 0:bb348c97df44 6518 /******************* Bit definition for TIM_CNT register ********************/
lypinator 0:bb348c97df44 6519 #define TIM_CNT_CNT_Pos (0U)
lypinator 0:bb348c97df44 6520 #define TIM_CNT_CNT_Msk (0xFFFFFFFFU << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
lypinator 0:bb348c97df44 6521 #define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
lypinator 0:bb348c97df44 6522
lypinator 0:bb348c97df44 6523 /******************* Bit definition for TIM_PSC register ********************/
lypinator 0:bb348c97df44 6524 #define TIM_PSC_PSC_Pos (0U)
lypinator 0:bb348c97df44 6525 #define TIM_PSC_PSC_Msk (0xFFFFU << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
lypinator 0:bb348c97df44 6526 #define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
lypinator 0:bb348c97df44 6527
lypinator 0:bb348c97df44 6528 /******************* Bit definition for TIM_ARR register ********************/
lypinator 0:bb348c97df44 6529 #define TIM_ARR_ARR_Pos (0U)
lypinator 0:bb348c97df44 6530 #define TIM_ARR_ARR_Msk (0xFFFFFFFFU << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
lypinator 0:bb348c97df44 6531 #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
lypinator 0:bb348c97df44 6532
lypinator 0:bb348c97df44 6533 /******************* Bit definition for TIM_RCR register ********************/
lypinator 0:bb348c97df44 6534 #define TIM_RCR_REP_Pos (0U)
lypinator 0:bb348c97df44 6535 #define TIM_RCR_REP_Msk (0xFFU << TIM_RCR_REP_Pos) /*!< 0x000000FF */
lypinator 0:bb348c97df44 6536 #define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
lypinator 0:bb348c97df44 6537
lypinator 0:bb348c97df44 6538 /******************* Bit definition for TIM_CCR1 register *******************/
lypinator 0:bb348c97df44 6539 #define TIM_CCR1_CCR1_Pos (0U)
lypinator 0:bb348c97df44 6540 #define TIM_CCR1_CCR1_Msk (0xFFFFU << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
lypinator 0:bb348c97df44 6541 #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
lypinator 0:bb348c97df44 6542
lypinator 0:bb348c97df44 6543 /******************* Bit definition for TIM_CCR2 register *******************/
lypinator 0:bb348c97df44 6544 #define TIM_CCR2_CCR2_Pos (0U)
lypinator 0:bb348c97df44 6545 #define TIM_CCR2_CCR2_Msk (0xFFFFU << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
lypinator 0:bb348c97df44 6546 #define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
lypinator 0:bb348c97df44 6547
lypinator 0:bb348c97df44 6548 /******************* Bit definition for TIM_CCR3 register *******************/
lypinator 0:bb348c97df44 6549 #define TIM_CCR3_CCR3_Pos (0U)
lypinator 0:bb348c97df44 6550 #define TIM_CCR3_CCR3_Msk (0xFFFFU << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
lypinator 0:bb348c97df44 6551 #define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
lypinator 0:bb348c97df44 6552
lypinator 0:bb348c97df44 6553 /******************* Bit definition for TIM_CCR4 register *******************/
lypinator 0:bb348c97df44 6554 #define TIM_CCR4_CCR4_Pos (0U)
lypinator 0:bb348c97df44 6555 #define TIM_CCR4_CCR4_Msk (0xFFFFU << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
lypinator 0:bb348c97df44 6556 #define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
lypinator 0:bb348c97df44 6557
lypinator 0:bb348c97df44 6558 /******************* Bit definition for TIM_BDTR register *******************/
lypinator 0:bb348c97df44 6559 #define TIM_BDTR_DTG_Pos (0U)
lypinator 0:bb348c97df44 6560 #define TIM_BDTR_DTG_Msk (0xFFU << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
lypinator 0:bb348c97df44 6561 #define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
lypinator 0:bb348c97df44 6562 #define TIM_BDTR_DTG_0 (0x01U << TIM_BDTR_DTG_Pos) /*!< 0x0001 */
lypinator 0:bb348c97df44 6563 #define TIM_BDTR_DTG_1 (0x02U << TIM_BDTR_DTG_Pos) /*!< 0x0002 */
lypinator 0:bb348c97df44 6564 #define TIM_BDTR_DTG_2 (0x04U << TIM_BDTR_DTG_Pos) /*!< 0x0004 */
lypinator 0:bb348c97df44 6565 #define TIM_BDTR_DTG_3 (0x08U << TIM_BDTR_DTG_Pos) /*!< 0x0008 */
lypinator 0:bb348c97df44 6566 #define TIM_BDTR_DTG_4 (0x10U << TIM_BDTR_DTG_Pos) /*!< 0x0010 */
lypinator 0:bb348c97df44 6567 #define TIM_BDTR_DTG_5 (0x20U << TIM_BDTR_DTG_Pos) /*!< 0x0020 */
lypinator 0:bb348c97df44 6568 #define TIM_BDTR_DTG_6 (0x40U << TIM_BDTR_DTG_Pos) /*!< 0x0040 */
lypinator 0:bb348c97df44 6569 #define TIM_BDTR_DTG_7 (0x80U << TIM_BDTR_DTG_Pos) /*!< 0x0080 */
lypinator 0:bb348c97df44 6570
lypinator 0:bb348c97df44 6571 #define TIM_BDTR_LOCK_Pos (8U)
lypinator 0:bb348c97df44 6572 #define TIM_BDTR_LOCK_Msk (0x3U << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
lypinator 0:bb348c97df44 6573 #define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
lypinator 0:bb348c97df44 6574 #define TIM_BDTR_LOCK_0 (0x1U << TIM_BDTR_LOCK_Pos) /*!< 0x0100 */
lypinator 0:bb348c97df44 6575 #define TIM_BDTR_LOCK_1 (0x2U << TIM_BDTR_LOCK_Pos) /*!< 0x0200 */
lypinator 0:bb348c97df44 6576
lypinator 0:bb348c97df44 6577 #define TIM_BDTR_OSSI_Pos (10U)
lypinator 0:bb348c97df44 6578 #define TIM_BDTR_OSSI_Msk (0x1U << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 6579 #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
lypinator 0:bb348c97df44 6580 #define TIM_BDTR_OSSR_Pos (11U)
lypinator 0:bb348c97df44 6581 #define TIM_BDTR_OSSR_Msk (0x1U << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 6582 #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
lypinator 0:bb348c97df44 6583 #define TIM_BDTR_BKE_Pos (12U)
lypinator 0:bb348c97df44 6584 #define TIM_BDTR_BKE_Msk (0x1U << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 6585 #define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable */
lypinator 0:bb348c97df44 6586 #define TIM_BDTR_BKP_Pos (13U)
lypinator 0:bb348c97df44 6587 #define TIM_BDTR_BKP_Msk (0x1U << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 6588 #define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity */
lypinator 0:bb348c97df44 6589 #define TIM_BDTR_AOE_Pos (14U)
lypinator 0:bb348c97df44 6590 #define TIM_BDTR_AOE_Msk (0x1U << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 6591 #define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
lypinator 0:bb348c97df44 6592 #define TIM_BDTR_MOE_Pos (15U)
lypinator 0:bb348c97df44 6593 #define TIM_BDTR_MOE_Msk (0x1U << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 6594 #define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
lypinator 0:bb348c97df44 6595
lypinator 0:bb348c97df44 6596 /******************* Bit definition for TIM_DCR register ********************/
lypinator 0:bb348c97df44 6597 #define TIM_DCR_DBA_Pos (0U)
lypinator 0:bb348c97df44 6598 #define TIM_DCR_DBA_Msk (0x1FU << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
lypinator 0:bb348c97df44 6599 #define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
lypinator 0:bb348c97df44 6600 #define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) /*!< 0x0001 */
lypinator 0:bb348c97df44 6601 #define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) /*!< 0x0002 */
lypinator 0:bb348c97df44 6602 #define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) /*!< 0x0004 */
lypinator 0:bb348c97df44 6603 #define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) /*!< 0x0008 */
lypinator 0:bb348c97df44 6604 #define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) /*!< 0x0010 */
lypinator 0:bb348c97df44 6605
lypinator 0:bb348c97df44 6606 #define TIM_DCR_DBL_Pos (8U)
lypinator 0:bb348c97df44 6607 #define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
lypinator 0:bb348c97df44 6608 #define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
lypinator 0:bb348c97df44 6609 #define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x0100 */
lypinator 0:bb348c97df44 6610 #define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /*!< 0x0200 */
lypinator 0:bb348c97df44 6611 #define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /*!< 0x0400 */
lypinator 0:bb348c97df44 6612 #define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /*!< 0x0800 */
lypinator 0:bb348c97df44 6613 #define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x1000 */
lypinator 0:bb348c97df44 6614
lypinator 0:bb348c97df44 6615 /******************* Bit definition for TIM_DMAR register *******************/
lypinator 0:bb348c97df44 6616 #define TIM_DMAR_DMAB_Pos (0U)
lypinator 0:bb348c97df44 6617 #define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
lypinator 0:bb348c97df44 6618 #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
lypinator 0:bb348c97df44 6619
lypinator 0:bb348c97df44 6620 /******************* Bit definition for TIM_OR register *********************/
lypinator 0:bb348c97df44 6621 #define TIM_OR_TI1_RMP_Pos (0U)
lypinator 0:bb348c97df44 6622 #define TIM_OR_TI1_RMP_Msk (0x3U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000003 */
lypinator 0:bb348c97df44 6623 #define TIM_OR_TI1_RMP TIM_OR_TI1_RMP_Msk /*!< TI1_RMP[1:0] bits (TIM11 Input Capture 1 remap) */
lypinator 0:bb348c97df44 6624 #define TIM_OR_TI1_RMP_0 (0x1U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 6625 #define TIM_OR_TI1_RMP_1 (0x2U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 6626
lypinator 0:bb348c97df44 6627 #define TIM_OR_TI4_RMP_Pos (6U)
lypinator 0:bb348c97df44 6628 #define TIM_OR_TI4_RMP_Msk (0x3U << TIM_OR_TI4_RMP_Pos) /*!< 0x000000C0 */
lypinator 0:bb348c97df44 6629 #define TIM_OR_TI4_RMP TIM_OR_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
lypinator 0:bb348c97df44 6630 #define TIM_OR_TI4_RMP_0 (0x1U << TIM_OR_TI4_RMP_Pos) /*!< 0x0040 */
lypinator 0:bb348c97df44 6631 #define TIM_OR_TI4_RMP_1 (0x2U << TIM_OR_TI4_RMP_Pos) /*!< 0x0080 */
lypinator 0:bb348c97df44 6632 #define TIM_OR_ITR1_RMP_Pos (10U)
lypinator 0:bb348c97df44 6633 #define TIM_OR_ITR1_RMP_Msk (0x3U << TIM_OR_ITR1_RMP_Pos) /*!< 0x00000C00 */
lypinator 0:bb348c97df44 6634 #define TIM_OR_ITR1_RMP TIM_OR_ITR1_RMP_Msk /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
lypinator 0:bb348c97df44 6635 #define TIM_OR_ITR1_RMP_0 (0x1U << TIM_OR_ITR1_RMP_Pos) /*!< 0x0400 */
lypinator 0:bb348c97df44 6636 #define TIM_OR_ITR1_RMP_1 (0x2U << TIM_OR_ITR1_RMP_Pos) /*!< 0x0800 */
lypinator 0:bb348c97df44 6637
lypinator 0:bb348c97df44 6638
lypinator 0:bb348c97df44 6639 /******************************************************************************/
lypinator 0:bb348c97df44 6640 /* */
lypinator 0:bb348c97df44 6641 /* Universal Synchronous Asynchronous Receiver Transmitter */
lypinator 0:bb348c97df44 6642 /* */
lypinator 0:bb348c97df44 6643 /******************************************************************************/
lypinator 0:bb348c97df44 6644 /******************* Bit definition for USART_SR register *******************/
lypinator 0:bb348c97df44 6645 #define USART_SR_PE_Pos (0U)
lypinator 0:bb348c97df44 6646 #define USART_SR_PE_Msk (0x1U << USART_SR_PE_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 6647 #define USART_SR_PE USART_SR_PE_Msk /*!<Parity Error */
lypinator 0:bb348c97df44 6648 #define USART_SR_FE_Pos (1U)
lypinator 0:bb348c97df44 6649 #define USART_SR_FE_Msk (0x1U << USART_SR_FE_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 6650 #define USART_SR_FE USART_SR_FE_Msk /*!<Framing Error */
lypinator 0:bb348c97df44 6651 #define USART_SR_NE_Pos (2U)
lypinator 0:bb348c97df44 6652 #define USART_SR_NE_Msk (0x1U << USART_SR_NE_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 6653 #define USART_SR_NE USART_SR_NE_Msk /*!<Noise Error Flag */
lypinator 0:bb348c97df44 6654 #define USART_SR_ORE_Pos (3U)
lypinator 0:bb348c97df44 6655 #define USART_SR_ORE_Msk (0x1U << USART_SR_ORE_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 6656 #define USART_SR_ORE USART_SR_ORE_Msk /*!<OverRun Error */
lypinator 0:bb348c97df44 6657 #define USART_SR_IDLE_Pos (4U)
lypinator 0:bb348c97df44 6658 #define USART_SR_IDLE_Msk (0x1U << USART_SR_IDLE_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 6659 #define USART_SR_IDLE USART_SR_IDLE_Msk /*!<IDLE line detected */
lypinator 0:bb348c97df44 6660 #define USART_SR_RXNE_Pos (5U)
lypinator 0:bb348c97df44 6661 #define USART_SR_RXNE_Msk (0x1U << USART_SR_RXNE_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 6662 #define USART_SR_RXNE USART_SR_RXNE_Msk /*!<Read Data Register Not Empty */
lypinator 0:bb348c97df44 6663 #define USART_SR_TC_Pos (6U)
lypinator 0:bb348c97df44 6664 #define USART_SR_TC_Msk (0x1U << USART_SR_TC_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 6665 #define USART_SR_TC USART_SR_TC_Msk /*!<Transmission Complete */
lypinator 0:bb348c97df44 6666 #define USART_SR_TXE_Pos (7U)
lypinator 0:bb348c97df44 6667 #define USART_SR_TXE_Msk (0x1U << USART_SR_TXE_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 6668 #define USART_SR_TXE USART_SR_TXE_Msk /*!<Transmit Data Register Empty */
lypinator 0:bb348c97df44 6669 #define USART_SR_LBD_Pos (8U)
lypinator 0:bb348c97df44 6670 #define USART_SR_LBD_Msk (0x1U << USART_SR_LBD_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 6671 #define USART_SR_LBD USART_SR_LBD_Msk /*!<LIN Break Detection Flag */
lypinator 0:bb348c97df44 6672 #define USART_SR_CTS_Pos (9U)
lypinator 0:bb348c97df44 6673 #define USART_SR_CTS_Msk (0x1U << USART_SR_CTS_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 6674 #define USART_SR_CTS USART_SR_CTS_Msk /*!<CTS Flag */
lypinator 0:bb348c97df44 6675
lypinator 0:bb348c97df44 6676 /******************* Bit definition for USART_DR register *******************/
lypinator 0:bb348c97df44 6677 #define USART_DR_DR_Pos (0U)
lypinator 0:bb348c97df44 6678 #define USART_DR_DR_Msk (0x1FFU << USART_DR_DR_Pos) /*!< 0x000001FF */
lypinator 0:bb348c97df44 6679 #define USART_DR_DR USART_DR_DR_Msk /*!<Data value */
lypinator 0:bb348c97df44 6680
lypinator 0:bb348c97df44 6681 /****************** Bit definition for USART_BRR register *******************/
lypinator 0:bb348c97df44 6682 #define USART_BRR_DIV_Fraction_Pos (0U)
lypinator 0:bb348c97df44 6683 #define USART_BRR_DIV_Fraction_Msk (0xFU << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */
lypinator 0:bb348c97df44 6684 #define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /*!<Fraction of USARTDIV */
lypinator 0:bb348c97df44 6685 #define USART_BRR_DIV_Mantissa_Pos (4U)
lypinator 0:bb348c97df44 6686 #define USART_BRR_DIV_Mantissa_Msk (0xFFFU << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */
lypinator 0:bb348c97df44 6687 #define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /*!<Mantissa of USARTDIV */
lypinator 0:bb348c97df44 6688
lypinator 0:bb348c97df44 6689 /****************** Bit definition for USART_CR1 register *******************/
lypinator 0:bb348c97df44 6690 #define USART_CR1_SBK_Pos (0U)
lypinator 0:bb348c97df44 6691 #define USART_CR1_SBK_Msk (0x1U << USART_CR1_SBK_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 6692 #define USART_CR1_SBK USART_CR1_SBK_Msk /*!<Send Break */
lypinator 0:bb348c97df44 6693 #define USART_CR1_RWU_Pos (1U)
lypinator 0:bb348c97df44 6694 #define USART_CR1_RWU_Msk (0x1U << USART_CR1_RWU_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 6695 #define USART_CR1_RWU USART_CR1_RWU_Msk /*!<Receiver wakeup */
lypinator 0:bb348c97df44 6696 #define USART_CR1_RE_Pos (2U)
lypinator 0:bb348c97df44 6697 #define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 6698 #define USART_CR1_RE USART_CR1_RE_Msk /*!<Receiver Enable */
lypinator 0:bb348c97df44 6699 #define USART_CR1_TE_Pos (3U)
lypinator 0:bb348c97df44 6700 #define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 6701 #define USART_CR1_TE USART_CR1_TE_Msk /*!<Transmitter Enable */
lypinator 0:bb348c97df44 6702 #define USART_CR1_IDLEIE_Pos (4U)
lypinator 0:bb348c97df44 6703 #define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 6704 #define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!<IDLE Interrupt Enable */
lypinator 0:bb348c97df44 6705 #define USART_CR1_RXNEIE_Pos (5U)
lypinator 0:bb348c97df44 6706 #define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 6707 #define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!<RXNE Interrupt Enable */
lypinator 0:bb348c97df44 6708 #define USART_CR1_TCIE_Pos (6U)
lypinator 0:bb348c97df44 6709 #define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 6710 #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!<Transmission Complete Interrupt Enable */
lypinator 0:bb348c97df44 6711 #define USART_CR1_TXEIE_Pos (7U)
lypinator 0:bb348c97df44 6712 #define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 6713 #define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!<PE Interrupt Enable */
lypinator 0:bb348c97df44 6714 #define USART_CR1_PEIE_Pos (8U)
lypinator 0:bb348c97df44 6715 #define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 6716 #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!<PE Interrupt Enable */
lypinator 0:bb348c97df44 6717 #define USART_CR1_PS_Pos (9U)
lypinator 0:bb348c97df44 6718 #define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 6719 #define USART_CR1_PS USART_CR1_PS_Msk /*!<Parity Selection */
lypinator 0:bb348c97df44 6720 #define USART_CR1_PCE_Pos (10U)
lypinator 0:bb348c97df44 6721 #define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 6722 #define USART_CR1_PCE USART_CR1_PCE_Msk /*!<Parity Control Enable */
lypinator 0:bb348c97df44 6723 #define USART_CR1_WAKE_Pos (11U)
lypinator 0:bb348c97df44 6724 #define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 6725 #define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!<Wakeup method */
lypinator 0:bb348c97df44 6726 #define USART_CR1_M_Pos (12U)
lypinator 0:bb348c97df44 6727 #define USART_CR1_M_Msk (0x1U << USART_CR1_M_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 6728 #define USART_CR1_M USART_CR1_M_Msk /*!<Word length */
lypinator 0:bb348c97df44 6729 #define USART_CR1_UE_Pos (13U)
lypinator 0:bb348c97df44 6730 #define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 6731 #define USART_CR1_UE USART_CR1_UE_Msk /*!<USART Enable */
lypinator 0:bb348c97df44 6732 #define USART_CR1_OVER8_Pos (15U)
lypinator 0:bb348c97df44 6733 #define USART_CR1_OVER8_Msk (0x1U << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 6734 #define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!<USART Oversampling by 8 enable */
lypinator 0:bb348c97df44 6735
lypinator 0:bb348c97df44 6736 /****************** Bit definition for USART_CR2 register *******************/
lypinator 0:bb348c97df44 6737 #define USART_CR2_ADD_Pos (0U)
lypinator 0:bb348c97df44 6738 #define USART_CR2_ADD_Msk (0xFU << USART_CR2_ADD_Pos) /*!< 0x0000000F */
lypinator 0:bb348c97df44 6739 #define USART_CR2_ADD USART_CR2_ADD_Msk /*!<Address of the USART node */
lypinator 0:bb348c97df44 6740 #define USART_CR2_LBDL_Pos (5U)
lypinator 0:bb348c97df44 6741 #define USART_CR2_LBDL_Msk (0x1U << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 6742 #define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!<LIN Break Detection Length */
lypinator 0:bb348c97df44 6743 #define USART_CR2_LBDIE_Pos (6U)
lypinator 0:bb348c97df44 6744 #define USART_CR2_LBDIE_Msk (0x1U << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 6745 #define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!<LIN Break Detection Interrupt Enable */
lypinator 0:bb348c97df44 6746 #define USART_CR2_LBCL_Pos (8U)
lypinator 0:bb348c97df44 6747 #define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 6748 #define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!<Last Bit Clock pulse */
lypinator 0:bb348c97df44 6749 #define USART_CR2_CPHA_Pos (9U)
lypinator 0:bb348c97df44 6750 #define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 6751 #define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!<Clock Phase */
lypinator 0:bb348c97df44 6752 #define USART_CR2_CPOL_Pos (10U)
lypinator 0:bb348c97df44 6753 #define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 6754 #define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!<Clock Polarity */
lypinator 0:bb348c97df44 6755 #define USART_CR2_CLKEN_Pos (11U)
lypinator 0:bb348c97df44 6756 #define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 6757 #define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!<Clock Enable */
lypinator 0:bb348c97df44 6758
lypinator 0:bb348c97df44 6759 #define USART_CR2_STOP_Pos (12U)
lypinator 0:bb348c97df44 6760 #define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /*!< 0x00003000 */
lypinator 0:bb348c97df44 6761 #define USART_CR2_STOP USART_CR2_STOP_Msk /*!<STOP[1:0] bits (STOP bits) */
lypinator 0:bb348c97df44 6762 #define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /*!< 0x1000 */
lypinator 0:bb348c97df44 6763 #define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /*!< 0x2000 */
lypinator 0:bb348c97df44 6764
lypinator 0:bb348c97df44 6765 #define USART_CR2_LINEN_Pos (14U)
lypinator 0:bb348c97df44 6766 #define USART_CR2_LINEN_Msk (0x1U << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 6767 #define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!<LIN mode enable */
lypinator 0:bb348c97df44 6768
lypinator 0:bb348c97df44 6769 /****************** Bit definition for USART_CR3 register *******************/
lypinator 0:bb348c97df44 6770 #define USART_CR3_EIE_Pos (0U)
lypinator 0:bb348c97df44 6771 #define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 6772 #define USART_CR3_EIE USART_CR3_EIE_Msk /*!<Error Interrupt Enable */
lypinator 0:bb348c97df44 6773 #define USART_CR3_IREN_Pos (1U)
lypinator 0:bb348c97df44 6774 #define USART_CR3_IREN_Msk (0x1U << USART_CR3_IREN_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 6775 #define USART_CR3_IREN USART_CR3_IREN_Msk /*!<IrDA mode Enable */
lypinator 0:bb348c97df44 6776 #define USART_CR3_IRLP_Pos (2U)
lypinator 0:bb348c97df44 6777 #define USART_CR3_IRLP_Msk (0x1U << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 6778 #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!<IrDA Low-Power */
lypinator 0:bb348c97df44 6779 #define USART_CR3_HDSEL_Pos (3U)
lypinator 0:bb348c97df44 6780 #define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 6781 #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!<Half-Duplex Selection */
lypinator 0:bb348c97df44 6782 #define USART_CR3_NACK_Pos (4U)
lypinator 0:bb348c97df44 6783 #define USART_CR3_NACK_Msk (0x1U << USART_CR3_NACK_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 6784 #define USART_CR3_NACK USART_CR3_NACK_Msk /*!<Smartcard NACK enable */
lypinator 0:bb348c97df44 6785 #define USART_CR3_SCEN_Pos (5U)
lypinator 0:bb348c97df44 6786 #define USART_CR3_SCEN_Msk (0x1U << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 6787 #define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!<Smartcard mode enable */
lypinator 0:bb348c97df44 6788 #define USART_CR3_DMAR_Pos (6U)
lypinator 0:bb348c97df44 6789 #define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 6790 #define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!<DMA Enable Receiver */
lypinator 0:bb348c97df44 6791 #define USART_CR3_DMAT_Pos (7U)
lypinator 0:bb348c97df44 6792 #define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 6793 #define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!<DMA Enable Transmitter */
lypinator 0:bb348c97df44 6794 #define USART_CR3_RTSE_Pos (8U)
lypinator 0:bb348c97df44 6795 #define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 6796 #define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!<RTS Enable */
lypinator 0:bb348c97df44 6797 #define USART_CR3_CTSE_Pos (9U)
lypinator 0:bb348c97df44 6798 #define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 6799 #define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!<CTS Enable */
lypinator 0:bb348c97df44 6800 #define USART_CR3_CTSIE_Pos (10U)
lypinator 0:bb348c97df44 6801 #define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 6802 #define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!<CTS Interrupt Enable */
lypinator 0:bb348c97df44 6803 #define USART_CR3_ONEBIT_Pos (11U)
lypinator 0:bb348c97df44 6804 #define USART_CR3_ONEBIT_Msk (0x1U << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 6805 #define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!<USART One bit method enable */
lypinator 0:bb348c97df44 6806
lypinator 0:bb348c97df44 6807 /****************** Bit definition for USART_GTPR register ******************/
lypinator 0:bb348c97df44 6808 #define USART_GTPR_PSC_Pos (0U)
lypinator 0:bb348c97df44 6809 #define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
lypinator 0:bb348c97df44 6810 #define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!<PSC[7:0] bits (Prescaler value) */
lypinator 0:bb348c97df44 6811 #define USART_GTPR_PSC_0 (0x01U << USART_GTPR_PSC_Pos) /*!< 0x0001 */
lypinator 0:bb348c97df44 6812 #define USART_GTPR_PSC_1 (0x02U << USART_GTPR_PSC_Pos) /*!< 0x0002 */
lypinator 0:bb348c97df44 6813 #define USART_GTPR_PSC_2 (0x04U << USART_GTPR_PSC_Pos) /*!< 0x0004 */
lypinator 0:bb348c97df44 6814 #define USART_GTPR_PSC_3 (0x08U << USART_GTPR_PSC_Pos) /*!< 0x0008 */
lypinator 0:bb348c97df44 6815 #define USART_GTPR_PSC_4 (0x10U << USART_GTPR_PSC_Pos) /*!< 0x0010 */
lypinator 0:bb348c97df44 6816 #define USART_GTPR_PSC_5 (0x20U << USART_GTPR_PSC_Pos) /*!< 0x0020 */
lypinator 0:bb348c97df44 6817 #define USART_GTPR_PSC_6 (0x40U << USART_GTPR_PSC_Pos) /*!< 0x0040 */
lypinator 0:bb348c97df44 6818 #define USART_GTPR_PSC_7 (0x80U << USART_GTPR_PSC_Pos) /*!< 0x0080 */
lypinator 0:bb348c97df44 6819
lypinator 0:bb348c97df44 6820 #define USART_GTPR_GT_Pos (8U)
lypinator 0:bb348c97df44 6821 #define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
lypinator 0:bb348c97df44 6822 #define USART_GTPR_GT USART_GTPR_GT_Msk /*!<Guard time value */
lypinator 0:bb348c97df44 6823
lypinator 0:bb348c97df44 6824 /******************************************************************************/
lypinator 0:bb348c97df44 6825 /* */
lypinator 0:bb348c97df44 6826 /* Window WATCHDOG */
lypinator 0:bb348c97df44 6827 /* */
lypinator 0:bb348c97df44 6828 /******************************************************************************/
lypinator 0:bb348c97df44 6829 /******************* Bit definition for WWDG_CR register ********************/
lypinator 0:bb348c97df44 6830 #define WWDG_CR_T_Pos (0U)
lypinator 0:bb348c97df44 6831 #define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) /*!< 0x0000007F */
lypinator 0:bb348c97df44 6832 #define WWDG_CR_T WWDG_CR_T_Msk /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
lypinator 0:bb348c97df44 6833 #define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /*!< 0x01 */
lypinator 0:bb348c97df44 6834 #define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) /*!< 0x02 */
lypinator 0:bb348c97df44 6835 #define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) /*!< 0x04 */
lypinator 0:bb348c97df44 6836 #define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) /*!< 0x08 */
lypinator 0:bb348c97df44 6837 #define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) /*!< 0x10 */
lypinator 0:bb348c97df44 6838 #define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) /*!< 0x20 */
lypinator 0:bb348c97df44 6839 #define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) /*!< 0x40 */
lypinator 0:bb348c97df44 6840 /* Legacy defines */
lypinator 0:bb348c97df44 6841 #define WWDG_CR_T0 WWDG_CR_T_0
lypinator 0:bb348c97df44 6842 #define WWDG_CR_T1 WWDG_CR_T_1
lypinator 0:bb348c97df44 6843 #define WWDG_CR_T2 WWDG_CR_T_2
lypinator 0:bb348c97df44 6844 #define WWDG_CR_T3 WWDG_CR_T_3
lypinator 0:bb348c97df44 6845 #define WWDG_CR_T4 WWDG_CR_T_4
lypinator 0:bb348c97df44 6846 #define WWDG_CR_T5 WWDG_CR_T_5
lypinator 0:bb348c97df44 6847 #define WWDG_CR_T6 WWDG_CR_T_6
lypinator 0:bb348c97df44 6848
lypinator 0:bb348c97df44 6849 #define WWDG_CR_WDGA_Pos (7U)
lypinator 0:bb348c97df44 6850 #define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 6851 #define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!<Activation bit */
lypinator 0:bb348c97df44 6852
lypinator 0:bb348c97df44 6853 /******************* Bit definition for WWDG_CFR register *******************/
lypinator 0:bb348c97df44 6854 #define WWDG_CFR_W_Pos (0U)
lypinator 0:bb348c97df44 6855 #define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) /*!< 0x0000007F */
lypinator 0:bb348c97df44 6856 #define WWDG_CFR_W WWDG_CFR_W_Msk /*!<W[6:0] bits (7-bit window value) */
lypinator 0:bb348c97df44 6857 #define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /*!< 0x0001 */
lypinator 0:bb348c97df44 6858 #define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) /*!< 0x0002 */
lypinator 0:bb348c97df44 6859 #define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) /*!< 0x0004 */
lypinator 0:bb348c97df44 6860 #define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) /*!< 0x0008 */
lypinator 0:bb348c97df44 6861 #define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) /*!< 0x0010 */
lypinator 0:bb348c97df44 6862 #define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) /*!< 0x0020 */
lypinator 0:bb348c97df44 6863 #define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) /*!< 0x0040 */
lypinator 0:bb348c97df44 6864 /* Legacy defines */
lypinator 0:bb348c97df44 6865 #define WWDG_CFR_W0 WWDG_CFR_W_0
lypinator 0:bb348c97df44 6866 #define WWDG_CFR_W1 WWDG_CFR_W_1
lypinator 0:bb348c97df44 6867 #define WWDG_CFR_W2 WWDG_CFR_W_2
lypinator 0:bb348c97df44 6868 #define WWDG_CFR_W3 WWDG_CFR_W_3
lypinator 0:bb348c97df44 6869 #define WWDG_CFR_W4 WWDG_CFR_W_4
lypinator 0:bb348c97df44 6870 #define WWDG_CFR_W5 WWDG_CFR_W_5
lypinator 0:bb348c97df44 6871 #define WWDG_CFR_W6 WWDG_CFR_W_6
lypinator 0:bb348c97df44 6872
lypinator 0:bb348c97df44 6873 #define WWDG_CFR_WDGTB_Pos (7U)
lypinator 0:bb348c97df44 6874 #define WWDG_CFR_WDGTB_Msk (0x3U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
lypinator 0:bb348c97df44 6875 #define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!<WDGTB[1:0] bits (Timer Base) */
lypinator 0:bb348c97df44 6876 #define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /*!< 0x0080 */
lypinator 0:bb348c97df44 6877 #define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) /*!< 0x0100 */
lypinator 0:bb348c97df44 6878 /* Legacy defines */
lypinator 0:bb348c97df44 6879 #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
lypinator 0:bb348c97df44 6880 #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
lypinator 0:bb348c97df44 6881
lypinator 0:bb348c97df44 6882 #define WWDG_CFR_EWI_Pos (9U)
lypinator 0:bb348c97df44 6883 #define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 6884 #define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!<Early Wakeup Interrupt */
lypinator 0:bb348c97df44 6885
lypinator 0:bb348c97df44 6886 /******************* Bit definition for WWDG_SR register ********************/
lypinator 0:bb348c97df44 6887 #define WWDG_SR_EWIF_Pos (0U)
lypinator 0:bb348c97df44 6888 #define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 6889 #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!<Early Wakeup Interrupt Flag */
lypinator 0:bb348c97df44 6890
lypinator 0:bb348c97df44 6891
lypinator 0:bb348c97df44 6892 /******************************************************************************/
lypinator 0:bb348c97df44 6893 /* */
lypinator 0:bb348c97df44 6894 /* DBG */
lypinator 0:bb348c97df44 6895 /* */
lypinator 0:bb348c97df44 6896 /******************************************************************************/
lypinator 0:bb348c97df44 6897 /******************** Bit definition for DBGMCU_IDCODE register *************/
lypinator 0:bb348c97df44 6898 #define DBGMCU_IDCODE_DEV_ID_Pos (0U)
lypinator 0:bb348c97df44 6899 #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
lypinator 0:bb348c97df44 6900 #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
lypinator 0:bb348c97df44 6901 #define DBGMCU_IDCODE_REV_ID_Pos (16U)
lypinator 0:bb348c97df44 6902 #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
lypinator 0:bb348c97df44 6903 #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
lypinator 0:bb348c97df44 6904
lypinator 0:bb348c97df44 6905 /******************** Bit definition for DBGMCU_CR register *****************/
lypinator 0:bb348c97df44 6906 #define DBGMCU_CR_DBG_SLEEP_Pos (0U)
lypinator 0:bb348c97df44 6907 #define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 6908 #define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk
lypinator 0:bb348c97df44 6909 #define DBGMCU_CR_DBG_STOP_Pos (1U)
lypinator 0:bb348c97df44 6910 #define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 6911 #define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk
lypinator 0:bb348c97df44 6912 #define DBGMCU_CR_DBG_STANDBY_Pos (2U)
lypinator 0:bb348c97df44 6913 #define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 6914 #define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk
lypinator 0:bb348c97df44 6915 #define DBGMCU_CR_TRACE_IOEN_Pos (5U)
lypinator 0:bb348c97df44 6916 #define DBGMCU_CR_TRACE_IOEN_Msk (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 6917 #define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk
lypinator 0:bb348c97df44 6918
lypinator 0:bb348c97df44 6919 #define DBGMCU_CR_TRACE_MODE_Pos (6U)
lypinator 0:bb348c97df44 6920 #define DBGMCU_CR_TRACE_MODE_Msk (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
lypinator 0:bb348c97df44 6921 #define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk
lypinator 0:bb348c97df44 6922 #define DBGMCU_CR_TRACE_MODE_0 (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 6923 #define DBGMCU_CR_TRACE_MODE_1 (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 6924
lypinator 0:bb348c97df44 6925 /******************** Bit definition for DBGMCU_APB1_FZ register ************/
lypinator 0:bb348c97df44 6926 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)
lypinator 0:bb348c97df44 6927 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 6928 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk
lypinator 0:bb348c97df44 6929 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U)
lypinator 0:bb348c97df44 6930 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 6931 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk
lypinator 0:bb348c97df44 6932 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos (2U)
lypinator 0:bb348c97df44 6933 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 6934 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk
lypinator 0:bb348c97df44 6935 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos (3U)
lypinator 0:bb348c97df44 6936 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 6937 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk
lypinator 0:bb348c97df44 6938 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
lypinator 0:bb348c97df44 6939 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 6940 #define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk
lypinator 0:bb348c97df44 6941 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
lypinator 0:bb348c97df44 6942 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 6943 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk
lypinator 0:bb348c97df44 6944 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
lypinator 0:bb348c97df44 6945 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 6946 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk
lypinator 0:bb348c97df44 6947 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)
lypinator 0:bb348c97df44 6948 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 6949 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk
lypinator 0:bb348c97df44 6950 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U)
lypinator 0:bb348c97df44 6951 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 6952 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk
lypinator 0:bb348c97df44 6953 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos (23U)
lypinator 0:bb348c97df44 6954 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos) /*!< 0x00800000 */
lypinator 0:bb348c97df44 6955 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk
lypinator 0:bb348c97df44 6956 /* Old IWDGSTOP bit definition, maintained for legacy purpose */
lypinator 0:bb348c97df44 6957 #define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
lypinator 0:bb348c97df44 6958
lypinator 0:bb348c97df44 6959 /******************** Bit definition for DBGMCU_APB2_FZ register ************/
lypinator 0:bb348c97df44 6960 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos (0U)
lypinator 0:bb348c97df44 6961 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 6962 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk
lypinator 0:bb348c97df44 6963 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos (16U)
lypinator 0:bb348c97df44 6964 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 6965 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk
lypinator 0:bb348c97df44 6966 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos (17U)
lypinator 0:bb348c97df44 6967 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 6968 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk
lypinator 0:bb348c97df44 6969 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos (18U)
lypinator 0:bb348c97df44 6970 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 6971 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk
lypinator 0:bb348c97df44 6972
lypinator 0:bb348c97df44 6973 /******************************************************************************/
lypinator 0:bb348c97df44 6974 /* */
lypinator 0:bb348c97df44 6975 /* USB_OTG */
lypinator 0:bb348c97df44 6976 /* */
lypinator 0:bb348c97df44 6977 /******************************************************************************/
lypinator 0:bb348c97df44 6978 /******************** Bit definition for USB_OTG_GOTGCTL register ***********/
lypinator 0:bb348c97df44 6979 #define USB_OTG_GOTGCTL_SRQSCS_Pos (0U)
lypinator 0:bb348c97df44 6980 #define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1U << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 6981 #define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk /*!< Session request success */
lypinator 0:bb348c97df44 6982 #define USB_OTG_GOTGCTL_SRQ_Pos (1U)
lypinator 0:bb348c97df44 6983 #define USB_OTG_GOTGCTL_SRQ_Msk (0x1U << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 6984 #define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk /*!< Session request */
lypinator 0:bb348c97df44 6985 #define USB_OTG_GOTGCTL_HNGSCS_Pos (8U)
lypinator 0:bb348c97df44 6986 #define USB_OTG_GOTGCTL_HNGSCS_Msk (0x1U << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 6987 #define USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_Msk /*!< Host set HNP enable */
lypinator 0:bb348c97df44 6988 #define USB_OTG_GOTGCTL_HNPRQ_Pos (9U)
lypinator 0:bb348c97df44 6989 #define USB_OTG_GOTGCTL_HNPRQ_Msk (0x1U << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 6990 #define USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_Msk /*!< HNP request */
lypinator 0:bb348c97df44 6991 #define USB_OTG_GOTGCTL_HSHNPEN_Pos (10U)
lypinator 0:bb348c97df44 6992 #define USB_OTG_GOTGCTL_HSHNPEN_Msk (0x1U << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 6993 #define USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_Msk /*!< Host set HNP enable */
lypinator 0:bb348c97df44 6994 #define USB_OTG_GOTGCTL_DHNPEN_Pos (11U)
lypinator 0:bb348c97df44 6995 #define USB_OTG_GOTGCTL_DHNPEN_Msk (0x1U << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 6996 #define USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_Msk /*!< Device HNP enabled */
lypinator 0:bb348c97df44 6997 #define USB_OTG_GOTGCTL_CIDSTS_Pos (16U)
lypinator 0:bb348c97df44 6998 #define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1U << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 6999 #define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk /*!< Connector ID status */
lypinator 0:bb348c97df44 7000 #define USB_OTG_GOTGCTL_DBCT_Pos (17U)
lypinator 0:bb348c97df44 7001 #define USB_OTG_GOTGCTL_DBCT_Msk (0x1U << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 7002 #define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk /*!< Long/short debounce time */
lypinator 0:bb348c97df44 7003 #define USB_OTG_GOTGCTL_ASVLD_Pos (18U)
lypinator 0:bb348c97df44 7004 #define USB_OTG_GOTGCTL_ASVLD_Msk (0x1U << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 7005 #define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid */
lypinator 0:bb348c97df44 7006 #define USB_OTG_GOTGCTL_BSVLD_Pos (19U)
lypinator 0:bb348c97df44 7007 #define USB_OTG_GOTGCTL_BSVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSVLD_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 7008 #define USB_OTG_GOTGCTL_BSVLD USB_OTG_GOTGCTL_BSVLD_Msk /*!< B-session valid */
lypinator 0:bb348c97df44 7009
lypinator 0:bb348c97df44 7010 /******************** Bit definition forUSB_OTG_HCFG register ********************/
lypinator 0:bb348c97df44 7011
lypinator 0:bb348c97df44 7012 #define USB_OTG_HCFG_FSLSPCS_Pos (0U)
lypinator 0:bb348c97df44 7013 #define USB_OTG_HCFG_FSLSPCS_Msk (0x3U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */
lypinator 0:bb348c97df44 7014 #define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk /*!< FS/LS PHY clock select */
lypinator 0:bb348c97df44 7015 #define USB_OTG_HCFG_FSLSPCS_0 (0x1U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 7016 #define USB_OTG_HCFG_FSLSPCS_1 (0x2U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 7017 #define USB_OTG_HCFG_FSLSS_Pos (2U)
lypinator 0:bb348c97df44 7018 #define USB_OTG_HCFG_FSLSS_Msk (0x1U << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 7019 #define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk /*!< FS- and LS-only support */
lypinator 0:bb348c97df44 7020
lypinator 0:bb348c97df44 7021 /******************** Bit definition for USB_OTG_DCFG register ********************/
lypinator 0:bb348c97df44 7022
lypinator 0:bb348c97df44 7023 #define USB_OTG_DCFG_DSPD_Pos (0U)
lypinator 0:bb348c97df44 7024 #define USB_OTG_DCFG_DSPD_Msk (0x3U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */
lypinator 0:bb348c97df44 7025 #define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk /*!< Device speed */
lypinator 0:bb348c97df44 7026 #define USB_OTG_DCFG_DSPD_0 (0x1U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 7027 #define USB_OTG_DCFG_DSPD_1 (0x2U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 7028 #define USB_OTG_DCFG_NZLSOHSK_Pos (2U)
lypinator 0:bb348c97df44 7029 #define USB_OTG_DCFG_NZLSOHSK_Msk (0x1U << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 7030 #define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk /*!< Nonzero-length status OUT handshake */
lypinator 0:bb348c97df44 7031
lypinator 0:bb348c97df44 7032 #define USB_OTG_DCFG_DAD_Pos (4U)
lypinator 0:bb348c97df44 7033 #define USB_OTG_DCFG_DAD_Msk (0x7FU << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
lypinator 0:bb348c97df44 7034 #define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
lypinator 0:bb348c97df44 7035 #define USB_OTG_DCFG_DAD_0 (0x01U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 7036 #define USB_OTG_DCFG_DAD_1 (0x02U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 7037 #define USB_OTG_DCFG_DAD_2 (0x04U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 7038 #define USB_OTG_DCFG_DAD_3 (0x08U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 7039 #define USB_OTG_DCFG_DAD_4 (0x10U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 7040 #define USB_OTG_DCFG_DAD_5 (0x20U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 7041 #define USB_OTG_DCFG_DAD_6 (0x40U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 7042
lypinator 0:bb348c97df44 7043 #define USB_OTG_DCFG_PFIVL_Pos (11U)
lypinator 0:bb348c97df44 7044 #define USB_OTG_DCFG_PFIVL_Msk (0x3U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
lypinator 0:bb348c97df44 7045 #define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
lypinator 0:bb348c97df44 7046 #define USB_OTG_DCFG_PFIVL_0 (0x1U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 7047 #define USB_OTG_DCFG_PFIVL_1 (0x2U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 7048
lypinator 0:bb348c97df44 7049 #define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
lypinator 0:bb348c97df44 7050 #define USB_OTG_DCFG_PERSCHIVL_Msk (0x3U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
lypinator 0:bb348c97df44 7051 #define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
lypinator 0:bb348c97df44 7052 #define USB_OTG_DCFG_PERSCHIVL_0 (0x1U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 7053 #define USB_OTG_DCFG_PERSCHIVL_1 (0x2U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 7054
lypinator 0:bb348c97df44 7055 /******************** Bit definition for USB_OTG_PCGCR register ********************/
lypinator 0:bb348c97df44 7056 #define USB_OTG_PCGCR_STPPCLK_Pos (0U)
lypinator 0:bb348c97df44 7057 #define USB_OTG_PCGCR_STPPCLK_Msk (0x1U << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 7058 #define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk /*!< Stop PHY clock */
lypinator 0:bb348c97df44 7059 #define USB_OTG_PCGCR_GATEHCLK_Pos (1U)
lypinator 0:bb348c97df44 7060 #define USB_OTG_PCGCR_GATEHCLK_Msk (0x1U << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 7061 #define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk /*!< Gate HCLK */
lypinator 0:bb348c97df44 7062 #define USB_OTG_PCGCR_PHYSUSP_Pos (4U)
lypinator 0:bb348c97df44 7063 #define USB_OTG_PCGCR_PHYSUSP_Msk (0x1U << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 7064 #define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk /*!< PHY suspended */
lypinator 0:bb348c97df44 7065
lypinator 0:bb348c97df44 7066 /******************** Bit definition for USB_OTG_GOTGINT register ********************/
lypinator 0:bb348c97df44 7067 #define USB_OTG_GOTGINT_SEDET_Pos (2U)
lypinator 0:bb348c97df44 7068 #define USB_OTG_GOTGINT_SEDET_Msk (0x1U << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 7069 #define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk /*!< Session end detected */
lypinator 0:bb348c97df44 7070 #define USB_OTG_GOTGINT_SRSSCHG_Pos (8U)
lypinator 0:bb348c97df44 7071 #define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1U << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 7072 #define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk /*!< Session request success status change */
lypinator 0:bb348c97df44 7073 #define USB_OTG_GOTGINT_HNSSCHG_Pos (9U)
lypinator 0:bb348c97df44 7074 #define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1U << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 7075 #define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk /*!< Host negotiation success status change */
lypinator 0:bb348c97df44 7076 #define USB_OTG_GOTGINT_HNGDET_Pos (17U)
lypinator 0:bb348c97df44 7077 #define USB_OTG_GOTGINT_HNGDET_Msk (0x1U << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 7078 #define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk /*!< Host negotiation detected */
lypinator 0:bb348c97df44 7079 #define USB_OTG_GOTGINT_ADTOCHG_Pos (18U)
lypinator 0:bb348c97df44 7080 #define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1U << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 7081 #define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk /*!< A-device timeout change */
lypinator 0:bb348c97df44 7082 #define USB_OTG_GOTGINT_DBCDNE_Pos (19U)
lypinator 0:bb348c97df44 7083 #define USB_OTG_GOTGINT_DBCDNE_Msk (0x1U << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 7084 #define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk /*!< Debounce done */
lypinator 0:bb348c97df44 7085
lypinator 0:bb348c97df44 7086 /******************** Bit definition for USB_OTG_DCTL register ********************/
lypinator 0:bb348c97df44 7087 #define USB_OTG_DCTL_RWUSIG_Pos (0U)
lypinator 0:bb348c97df44 7088 #define USB_OTG_DCTL_RWUSIG_Msk (0x1U << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 7089 #define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk /*!< Remote wakeup signaling */
lypinator 0:bb348c97df44 7090 #define USB_OTG_DCTL_SDIS_Pos (1U)
lypinator 0:bb348c97df44 7091 #define USB_OTG_DCTL_SDIS_Msk (0x1U << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 7092 #define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk /*!< Soft disconnect */
lypinator 0:bb348c97df44 7093 #define USB_OTG_DCTL_GINSTS_Pos (2U)
lypinator 0:bb348c97df44 7094 #define USB_OTG_DCTL_GINSTS_Msk (0x1U << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 7095 #define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk /*!< Global IN NAK status */
lypinator 0:bb348c97df44 7096 #define USB_OTG_DCTL_GONSTS_Pos (3U)
lypinator 0:bb348c97df44 7097 #define USB_OTG_DCTL_GONSTS_Msk (0x1U << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 7098 #define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk /*!< Global OUT NAK status */
lypinator 0:bb348c97df44 7099
lypinator 0:bb348c97df44 7100 #define USB_OTG_DCTL_TCTL_Pos (4U)
lypinator 0:bb348c97df44 7101 #define USB_OTG_DCTL_TCTL_Msk (0x7U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */
lypinator 0:bb348c97df44 7102 #define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk /*!< Test control */
lypinator 0:bb348c97df44 7103 #define USB_OTG_DCTL_TCTL_0 (0x1U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 7104 #define USB_OTG_DCTL_TCTL_1 (0x2U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 7105 #define USB_OTG_DCTL_TCTL_2 (0x4U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 7106 #define USB_OTG_DCTL_SGINAK_Pos (7U)
lypinator 0:bb348c97df44 7107 #define USB_OTG_DCTL_SGINAK_Msk (0x1U << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 7108 #define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk /*!< Set global IN NAK */
lypinator 0:bb348c97df44 7109 #define USB_OTG_DCTL_CGINAK_Pos (8U)
lypinator 0:bb348c97df44 7110 #define USB_OTG_DCTL_CGINAK_Msk (0x1U << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 7111 #define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk /*!< Clear global IN NAK */
lypinator 0:bb348c97df44 7112 #define USB_OTG_DCTL_SGONAK_Pos (9U)
lypinator 0:bb348c97df44 7113 #define USB_OTG_DCTL_SGONAK_Msk (0x1U << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 7114 #define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk /*!< Set global OUT NAK */
lypinator 0:bb348c97df44 7115 #define USB_OTG_DCTL_CGONAK_Pos (10U)
lypinator 0:bb348c97df44 7116 #define USB_OTG_DCTL_CGONAK_Msk (0x1U << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 7117 #define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk /*!< Clear global OUT NAK */
lypinator 0:bb348c97df44 7118 #define USB_OTG_DCTL_POPRGDNE_Pos (11U)
lypinator 0:bb348c97df44 7119 #define USB_OTG_DCTL_POPRGDNE_Msk (0x1U << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 7120 #define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */
lypinator 0:bb348c97df44 7121
lypinator 0:bb348c97df44 7122 /******************** Bit definition for USB_OTG_HFIR register ********************/
lypinator 0:bb348c97df44 7123 #define USB_OTG_HFIR_FRIVL_Pos (0U)
lypinator 0:bb348c97df44 7124 #define USB_OTG_HFIR_FRIVL_Msk (0xFFFFU << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */
lypinator 0:bb348c97df44 7125 #define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */
lypinator 0:bb348c97df44 7126
lypinator 0:bb348c97df44 7127 /******************** Bit definition for USB_OTG_HFNUM register ********************/
lypinator 0:bb348c97df44 7128 #define USB_OTG_HFNUM_FRNUM_Pos (0U)
lypinator 0:bb348c97df44 7129 #define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFU << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */
lypinator 0:bb348c97df44 7130 #define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk /*!< Frame number */
lypinator 0:bb348c97df44 7131 #define USB_OTG_HFNUM_FTREM_Pos (16U)
lypinator 0:bb348c97df44 7132 #define USB_OTG_HFNUM_FTREM_Msk (0xFFFFU << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */
lypinator 0:bb348c97df44 7133 #define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk /*!< Frame time remaining */
lypinator 0:bb348c97df44 7134
lypinator 0:bb348c97df44 7135 /******************** Bit definition for USB_OTG_DSTS register ********************/
lypinator 0:bb348c97df44 7136 #define USB_OTG_DSTS_SUSPSTS_Pos (0U)
lypinator 0:bb348c97df44 7137 #define USB_OTG_DSTS_SUSPSTS_Msk (0x1U << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 7138 #define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk /*!< Suspend status */
lypinator 0:bb348c97df44 7139
lypinator 0:bb348c97df44 7140 #define USB_OTG_DSTS_ENUMSPD_Pos (1U)
lypinator 0:bb348c97df44 7141 #define USB_OTG_DSTS_ENUMSPD_Msk (0x3U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */
lypinator 0:bb348c97df44 7142 #define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk /*!< Enumerated speed */
lypinator 0:bb348c97df44 7143 #define USB_OTG_DSTS_ENUMSPD_0 (0x1U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 7144 #define USB_OTG_DSTS_ENUMSPD_1 (0x2U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 7145 #define USB_OTG_DSTS_EERR_Pos (3U)
lypinator 0:bb348c97df44 7146 #define USB_OTG_DSTS_EERR_Msk (0x1U << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 7147 #define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk /*!< Erratic error */
lypinator 0:bb348c97df44 7148 #define USB_OTG_DSTS_FNSOF_Pos (8U)
lypinator 0:bb348c97df44 7149 #define USB_OTG_DSTS_FNSOF_Msk (0x3FFFU << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */
lypinator 0:bb348c97df44 7150 #define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */
lypinator 0:bb348c97df44 7151
lypinator 0:bb348c97df44 7152 /******************** Bit definition for USB_OTG_GAHBCFG register ********************/
lypinator 0:bb348c97df44 7153 #define USB_OTG_GAHBCFG_GINT_Pos (0U)
lypinator 0:bb348c97df44 7154 #define USB_OTG_GAHBCFG_GINT_Msk (0x1U << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 7155 #define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */
lypinator 0:bb348c97df44 7156 #define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U)
lypinator 0:bb348c97df44 7157 #define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFU << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */
lypinator 0:bb348c97df44 7158 #define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */
lypinator 0:bb348c97df44 7159 #define USB_OTG_GAHBCFG_HBSTLEN_0 (0x0U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */
lypinator 0:bb348c97df44 7160 #define USB_OTG_GAHBCFG_HBSTLEN_1 (0x1U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */
lypinator 0:bb348c97df44 7161 #define USB_OTG_GAHBCFG_HBSTLEN_2 (0x3U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */
lypinator 0:bb348c97df44 7162 #define USB_OTG_GAHBCFG_HBSTLEN_3 (0x5U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */
lypinator 0:bb348c97df44 7163 #define USB_OTG_GAHBCFG_HBSTLEN_4 (0x7U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */
lypinator 0:bb348c97df44 7164 #define USB_OTG_GAHBCFG_DMAEN_Pos (5U)
lypinator 0:bb348c97df44 7165 #define USB_OTG_GAHBCFG_DMAEN_Msk (0x1U << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 7166 #define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk /*!< DMA enable */
lypinator 0:bb348c97df44 7167 #define USB_OTG_GAHBCFG_TXFELVL_Pos (7U)
lypinator 0:bb348c97df44 7168 #define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 7169 #define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk /*!< TxFIFO empty level */
lypinator 0:bb348c97df44 7170 #define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U)
lypinator 0:bb348c97df44 7171 #define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 7172 #define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk /*!< Periodic TxFIFO empty level */
lypinator 0:bb348c97df44 7173
lypinator 0:bb348c97df44 7174 /******************** Bit definition for USB_OTG_GUSBCFG register ********************/
lypinator 0:bb348c97df44 7175
lypinator 0:bb348c97df44 7176 #define USB_OTG_GUSBCFG_TOCAL_Pos (0U)
lypinator 0:bb348c97df44 7177 #define USB_OTG_GUSBCFG_TOCAL_Msk (0x7U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */
lypinator 0:bb348c97df44 7178 #define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk /*!< FS timeout calibration */
lypinator 0:bb348c97df44 7179 #define USB_OTG_GUSBCFG_TOCAL_0 (0x1U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 7180 #define USB_OTG_GUSBCFG_TOCAL_1 (0x2U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 7181 #define USB_OTG_GUSBCFG_TOCAL_2 (0x4U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 7182 #define USB_OTG_GUSBCFG_PHYSEL_Pos (6U)
lypinator 0:bb348c97df44 7183 #define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1U << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 7184 #define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
lypinator 0:bb348c97df44 7185 #define USB_OTG_GUSBCFG_SRPCAP_Pos (8U)
lypinator 0:bb348c97df44 7186 #define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1U << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 7187 #define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk /*!< SRP-capable */
lypinator 0:bb348c97df44 7188 #define USB_OTG_GUSBCFG_HNPCAP_Pos (9U)
lypinator 0:bb348c97df44 7189 #define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1U << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 7190 #define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk /*!< HNP-capable */
lypinator 0:bb348c97df44 7191 #define USB_OTG_GUSBCFG_TRDT_Pos (10U)
lypinator 0:bb348c97df44 7192 #define USB_OTG_GUSBCFG_TRDT_Msk (0xFU << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */
lypinator 0:bb348c97df44 7193 #define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk /*!< USB turnaround time */
lypinator 0:bb348c97df44 7194 #define USB_OTG_GUSBCFG_TRDT_0 (0x1U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 7195 #define USB_OTG_GUSBCFG_TRDT_1 (0x2U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 7196 #define USB_OTG_GUSBCFG_TRDT_2 (0x4U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 7197 #define USB_OTG_GUSBCFG_TRDT_3 (0x8U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 7198 #define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U)
lypinator 0:bb348c97df44 7199 #define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 7200 #define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */
lypinator 0:bb348c97df44 7201 #define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U)
lypinator 0:bb348c97df44 7202 #define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1U << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 7203 #define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */
lypinator 0:bb348c97df44 7204 #define USB_OTG_GUSBCFG_ULPIAR_Pos (18U)
lypinator 0:bb348c97df44 7205 #define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1U << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 7206 #define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk /*!< ULPI Auto-resume */
lypinator 0:bb348c97df44 7207 #define USB_OTG_GUSBCFG_ULPICSM_Pos (19U)
lypinator 0:bb348c97df44 7208 #define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1U << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 7209 #define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk /*!< ULPI Clock SuspendM */
lypinator 0:bb348c97df44 7210 #define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U)
lypinator 0:bb348c97df44 7211 #define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 7212 #define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive */
lypinator 0:bb348c97df44 7213 #define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U)
lypinator 0:bb348c97df44 7214 #define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 7215 #define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator */
lypinator 0:bb348c97df44 7216 #define USB_OTG_GUSBCFG_TSDPS_Pos (22U)
lypinator 0:bb348c97df44 7217 #define USB_OTG_GUSBCFG_TSDPS_Msk (0x1U << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 7218 #define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk /*!< TermSel DLine pulsing selection */
lypinator 0:bb348c97df44 7219 #define USB_OTG_GUSBCFG_PCCI_Pos (23U)
lypinator 0:bb348c97df44 7220 #define USB_OTG_GUSBCFG_PCCI_Msk (0x1U << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */
lypinator 0:bb348c97df44 7221 #define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk /*!< Indicator complement */
lypinator 0:bb348c97df44 7222 #define USB_OTG_GUSBCFG_PTCI_Pos (24U)
lypinator 0:bb348c97df44 7223 #define USB_OTG_GUSBCFG_PTCI_Msk (0x1U << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 7224 #define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk /*!< Indicator pass through */
lypinator 0:bb348c97df44 7225 #define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U)
lypinator 0:bb348c97df44 7226 #define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 7227 #define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk /*!< ULPI interface protect disable */
lypinator 0:bb348c97df44 7228 #define USB_OTG_GUSBCFG_FHMOD_Pos (29U)
lypinator 0:bb348c97df44 7229 #define USB_OTG_GUSBCFG_FHMOD_Msk (0x1U << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */
lypinator 0:bb348c97df44 7230 #define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk /*!< Forced host mode */
lypinator 0:bb348c97df44 7231 #define USB_OTG_GUSBCFG_FDMOD_Pos (30U)
lypinator 0:bb348c97df44 7232 #define USB_OTG_GUSBCFG_FDMOD_Msk (0x1U << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */
lypinator 0:bb348c97df44 7233 #define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */
lypinator 0:bb348c97df44 7234 #define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
lypinator 0:bb348c97df44 7235 #define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1U << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
lypinator 0:bb348c97df44 7236 #define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */
lypinator 0:bb348c97df44 7237
lypinator 0:bb348c97df44 7238 /******************** Bit definition for USB_OTG_GRSTCTL register ********************/
lypinator 0:bb348c97df44 7239 #define USB_OTG_GRSTCTL_CSRST_Pos (0U)
lypinator 0:bb348c97df44 7240 #define USB_OTG_GRSTCTL_CSRST_Msk (0x1U << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 7241 #define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */
lypinator 0:bb348c97df44 7242 #define USB_OTG_GRSTCTL_HSRST_Pos (1U)
lypinator 0:bb348c97df44 7243 #define USB_OTG_GRSTCTL_HSRST_Msk (0x1U << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 7244 #define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */
lypinator 0:bb348c97df44 7245 #define USB_OTG_GRSTCTL_FCRST_Pos (2U)
lypinator 0:bb348c97df44 7246 #define USB_OTG_GRSTCTL_FCRST_Msk (0x1U << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 7247 #define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */
lypinator 0:bb348c97df44 7248 #define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U)
lypinator 0:bb348c97df44 7249 #define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1U << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 7250 #define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk /*!< RxFIFO flush */
lypinator 0:bb348c97df44 7251 #define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U)
lypinator 0:bb348c97df44 7252 #define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1U << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 7253 #define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk /*!< TxFIFO flush */
lypinator 0:bb348c97df44 7254
lypinator 0:bb348c97df44 7255
lypinator 0:bb348c97df44 7256 #define USB_OTG_GRSTCTL_TXFNUM_Pos (6U)
lypinator 0:bb348c97df44 7257 #define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FU << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */
lypinator 0:bb348c97df44 7258 #define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk /*!< TxFIFO number */
lypinator 0:bb348c97df44 7259 #define USB_OTG_GRSTCTL_TXFNUM_0 (0x01U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 7260 #define USB_OTG_GRSTCTL_TXFNUM_1 (0x02U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 7261 #define USB_OTG_GRSTCTL_TXFNUM_2 (0x04U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 7262 #define USB_OTG_GRSTCTL_TXFNUM_3 (0x08U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 7263 #define USB_OTG_GRSTCTL_TXFNUM_4 (0x10U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 7264 #define USB_OTG_GRSTCTL_DMAREQ_Pos (30U)
lypinator 0:bb348c97df44 7265 #define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1U << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */
lypinator 0:bb348c97df44 7266 #define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk /*!< DMA request signal */
lypinator 0:bb348c97df44 7267 #define USB_OTG_GRSTCTL_AHBIDL_Pos (31U)
lypinator 0:bb348c97df44 7268 #define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1U << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */
lypinator 0:bb348c97df44 7269 #define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk /*!< AHB master idle */
lypinator 0:bb348c97df44 7270
lypinator 0:bb348c97df44 7271 /******************** Bit definition for USB_OTG_DIEPMSK register ********************/
lypinator 0:bb348c97df44 7272 #define USB_OTG_DIEPMSK_XFRCM_Pos (0U)
lypinator 0:bb348c97df44 7273 #define USB_OTG_DIEPMSK_XFRCM_Msk (0x1U << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 7274 #define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
lypinator 0:bb348c97df44 7275 #define USB_OTG_DIEPMSK_EPDM_Pos (1U)
lypinator 0:bb348c97df44 7276 #define USB_OTG_DIEPMSK_EPDM_Msk (0x1U << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 7277 #define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
lypinator 0:bb348c97df44 7278 #define USB_OTG_DIEPMSK_TOM_Pos (3U)
lypinator 0:bb348c97df44 7279 #define USB_OTG_DIEPMSK_TOM_Msk (0x1U << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 7280 #define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
lypinator 0:bb348c97df44 7281 #define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U)
lypinator 0:bb348c97df44 7282 #define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1U << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 7283 #define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
lypinator 0:bb348c97df44 7284 #define USB_OTG_DIEPMSK_INEPNMM_Pos (5U)
lypinator 0:bb348c97df44 7285 #define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1U << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 7286 #define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
lypinator 0:bb348c97df44 7287 #define USB_OTG_DIEPMSK_INEPNEM_Pos (6U)
lypinator 0:bb348c97df44 7288 #define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1U << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 7289 #define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
lypinator 0:bb348c97df44 7290 #define USB_OTG_DIEPMSK_TXFURM_Pos (8U)
lypinator 0:bb348c97df44 7291 #define USB_OTG_DIEPMSK_TXFURM_Msk (0x1U << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 7292 #define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk /*!< FIFO underrun mask */
lypinator 0:bb348c97df44 7293 #define USB_OTG_DIEPMSK_BIM_Pos (9U)
lypinator 0:bb348c97df44 7294 #define USB_OTG_DIEPMSK_BIM_Msk (0x1U << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 7295 #define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */
lypinator 0:bb348c97df44 7296
lypinator 0:bb348c97df44 7297 /******************** Bit definition for USB_OTG_HPTXSTS register ********************/
lypinator 0:bb348c97df44 7298 #define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U)
lypinator 0:bb348c97df44 7299 #define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFU << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */
lypinator 0:bb348c97df44 7300 #define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk /*!< Periodic transmit data FIFO space available */
lypinator 0:bb348c97df44 7301 #define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U)
lypinator 0:bb348c97df44 7302 #define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFU << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */
lypinator 0:bb348c97df44 7303 #define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk /*!< Periodic transmit request queue space available */
lypinator 0:bb348c97df44 7304 #define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 7305 #define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 7306 #define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 7307 #define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 7308 #define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 7309 #define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 7310 #define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 7311 #define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */
lypinator 0:bb348c97df44 7312
lypinator 0:bb348c97df44 7313 #define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U)
lypinator 0:bb348c97df44 7314 #define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFU << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */
lypinator 0:bb348c97df44 7315 #define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk /*!< Top of the periodic transmit request queue */
lypinator 0:bb348c97df44 7316 #define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 7317 #define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 7318 #define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */
lypinator 0:bb348c97df44 7319 #define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */
lypinator 0:bb348c97df44 7320 #define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */
lypinator 0:bb348c97df44 7321 #define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */
lypinator 0:bb348c97df44 7322 #define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */
lypinator 0:bb348c97df44 7323 #define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */
lypinator 0:bb348c97df44 7324
lypinator 0:bb348c97df44 7325 /******************** Bit definition for USB_OTG_HAINT register ********************/
lypinator 0:bb348c97df44 7326 #define USB_OTG_HAINT_HAINT_Pos (0U)
lypinator 0:bb348c97df44 7327 #define USB_OTG_HAINT_HAINT_Msk (0xFFFFU << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */
lypinator 0:bb348c97df44 7328 #define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk /*!< Channel interrupts */
lypinator 0:bb348c97df44 7329
lypinator 0:bb348c97df44 7330 /******************** Bit definition for USB_OTG_DOEPMSK register ********************/
lypinator 0:bb348c97df44 7331 #define USB_OTG_DOEPMSK_XFRCM_Pos (0U)
lypinator 0:bb348c97df44 7332 #define USB_OTG_DOEPMSK_XFRCM_Msk (0x1U << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 7333 #define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
lypinator 0:bb348c97df44 7334 #define USB_OTG_DOEPMSK_EPDM_Pos (1U)
lypinator 0:bb348c97df44 7335 #define USB_OTG_DOEPMSK_EPDM_Msk (0x1U << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 7336 #define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
lypinator 0:bb348c97df44 7337 #define USB_OTG_DOEPMSK_STUPM_Pos (3U)
lypinator 0:bb348c97df44 7338 #define USB_OTG_DOEPMSK_STUPM_Msk (0x1U << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 7339 #define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */
lypinator 0:bb348c97df44 7340 #define USB_OTG_DOEPMSK_OTEPDM_Pos (4U)
lypinator 0:bb348c97df44 7341 #define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1U << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 7342 #define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */
lypinator 0:bb348c97df44 7343 #define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U)
lypinator 0:bb348c97df44 7344 #define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1U << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 7345 #define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */
lypinator 0:bb348c97df44 7346 #define USB_OTG_DOEPMSK_OPEM_Pos (8U)
lypinator 0:bb348c97df44 7347 #define USB_OTG_DOEPMSK_OPEM_Msk (0x1U << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 7348 #define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */
lypinator 0:bb348c97df44 7349 #define USB_OTG_DOEPMSK_BOIM_Pos (9U)
lypinator 0:bb348c97df44 7350 #define USB_OTG_DOEPMSK_BOIM_Msk (0x1U << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 7351 #define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */
lypinator 0:bb348c97df44 7352
lypinator 0:bb348c97df44 7353 /******************** Bit definition for USB_OTG_GINTSTS register ********************/
lypinator 0:bb348c97df44 7354 #define USB_OTG_GINTSTS_CMOD_Pos (0U)
lypinator 0:bb348c97df44 7355 #define USB_OTG_GINTSTS_CMOD_Msk (0x1U << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 7356 #define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk /*!< Current mode of operation */
lypinator 0:bb348c97df44 7357 #define USB_OTG_GINTSTS_MMIS_Pos (1U)
lypinator 0:bb348c97df44 7358 #define USB_OTG_GINTSTS_MMIS_Msk (0x1U << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 7359 #define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk /*!< Mode mismatch interrupt */
lypinator 0:bb348c97df44 7360 #define USB_OTG_GINTSTS_OTGINT_Pos (2U)
lypinator 0:bb348c97df44 7361 #define USB_OTG_GINTSTS_OTGINT_Msk (0x1U << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 7362 #define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk /*!< OTG interrupt */
lypinator 0:bb348c97df44 7363 #define USB_OTG_GINTSTS_SOF_Pos (3U)
lypinator 0:bb348c97df44 7364 #define USB_OTG_GINTSTS_SOF_Msk (0x1U << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 7365 #define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk /*!< Start of frame */
lypinator 0:bb348c97df44 7366 #define USB_OTG_GINTSTS_RXFLVL_Pos (4U)
lypinator 0:bb348c97df44 7367 #define USB_OTG_GINTSTS_RXFLVL_Msk (0x1U << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 7368 #define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk /*!< RxFIFO nonempty */
lypinator 0:bb348c97df44 7369 #define USB_OTG_GINTSTS_NPTXFE_Pos (5U)
lypinator 0:bb348c97df44 7370 #define USB_OTG_GINTSTS_NPTXFE_Msk (0x1U << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 7371 #define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk /*!< Nonperiodic TxFIFO empty */
lypinator 0:bb348c97df44 7372 #define USB_OTG_GINTSTS_GINAKEFF_Pos (6U)
lypinator 0:bb348c97df44 7373 #define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 7374 #define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */
lypinator 0:bb348c97df44 7375 #define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U)
lypinator 0:bb348c97df44 7376 #define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1U << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 7377 #define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */
lypinator 0:bb348c97df44 7378 #define USB_OTG_GINTSTS_ESUSP_Pos (10U)
lypinator 0:bb348c97df44 7379 #define USB_OTG_GINTSTS_ESUSP_Msk (0x1U << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 7380 #define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */
lypinator 0:bb348c97df44 7381 #define USB_OTG_GINTSTS_USBSUSP_Pos (11U)
lypinator 0:bb348c97df44 7382 #define USB_OTG_GINTSTS_USBSUSP_Msk (0x1U << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 7383 #define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk /*!< USB suspend */
lypinator 0:bb348c97df44 7384 #define USB_OTG_GINTSTS_USBRST_Pos (12U)
lypinator 0:bb348c97df44 7385 #define USB_OTG_GINTSTS_USBRST_Msk (0x1U << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 7386 #define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk /*!< USB reset */
lypinator 0:bb348c97df44 7387 #define USB_OTG_GINTSTS_ENUMDNE_Pos (13U)
lypinator 0:bb348c97df44 7388 #define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1U << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 7389 #define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk /*!< Enumeration done */
lypinator 0:bb348c97df44 7390 #define USB_OTG_GINTSTS_ISOODRP_Pos (14U)
lypinator 0:bb348c97df44 7391 #define USB_OTG_GINTSTS_ISOODRP_Msk (0x1U << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 7392 #define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk /*!< Isochronous OUT packet dropped interrupt */
lypinator 0:bb348c97df44 7393 #define USB_OTG_GINTSTS_EOPF_Pos (15U)
lypinator 0:bb348c97df44 7394 #define USB_OTG_GINTSTS_EOPF_Msk (0x1U << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 7395 #define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk /*!< End of periodic frame interrupt */
lypinator 0:bb348c97df44 7396 #define USB_OTG_GINTSTS_IEPINT_Pos (18U)
lypinator 0:bb348c97df44 7397 #define USB_OTG_GINTSTS_IEPINT_Msk (0x1U << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 7398 #define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk /*!< IN endpoint interrupt */
lypinator 0:bb348c97df44 7399 #define USB_OTG_GINTSTS_OEPINT_Pos (19U)
lypinator 0:bb348c97df44 7400 #define USB_OTG_GINTSTS_OEPINT_Msk (0x1U << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 7401 #define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk /*!< OUT endpoint interrupt */
lypinator 0:bb348c97df44 7402 #define USB_OTG_GINTSTS_IISOIXFR_Pos (20U)
lypinator 0:bb348c97df44 7403 #define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1U << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 7404 #define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk /*!< Incomplete isochronous IN transfer */
lypinator 0:bb348c97df44 7405 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U)
lypinator 0:bb348c97df44 7406 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1U << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 7407 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer */
lypinator 0:bb348c97df44 7408 #define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U)
lypinator 0:bb348c97df44 7409 #define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1U << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 7410 #define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */
lypinator 0:bb348c97df44 7411 #define USB_OTG_GINTSTS_HPRTINT_Pos (24U)
lypinator 0:bb348c97df44 7412 #define USB_OTG_GINTSTS_HPRTINT_Msk (0x1U << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 7413 #define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */
lypinator 0:bb348c97df44 7414 #define USB_OTG_GINTSTS_HCINT_Pos (25U)
lypinator 0:bb348c97df44 7415 #define USB_OTG_GINTSTS_HCINT_Msk (0x1U << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 7416 #define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk /*!< Host channels interrupt */
lypinator 0:bb348c97df44 7417 #define USB_OTG_GINTSTS_PTXFE_Pos (26U)
lypinator 0:bb348c97df44 7418 #define USB_OTG_GINTSTS_PTXFE_Msk (0x1U << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */
lypinator 0:bb348c97df44 7419 #define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk /*!< Periodic TxFIFO empty */
lypinator 0:bb348c97df44 7420 #define USB_OTG_GINTSTS_CIDSCHG_Pos (28U)
lypinator 0:bb348c97df44 7421 #define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1U << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */
lypinator 0:bb348c97df44 7422 #define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk /*!< Connector ID status change */
lypinator 0:bb348c97df44 7423 #define USB_OTG_GINTSTS_DISCINT_Pos (29U)
lypinator 0:bb348c97df44 7424 #define USB_OTG_GINTSTS_DISCINT_Msk (0x1U << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */
lypinator 0:bb348c97df44 7425 #define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk /*!< Disconnect detected interrupt */
lypinator 0:bb348c97df44 7426 #define USB_OTG_GINTSTS_SRQINT_Pos (30U)
lypinator 0:bb348c97df44 7427 #define USB_OTG_GINTSTS_SRQINT_Msk (0x1U << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */
lypinator 0:bb348c97df44 7428 #define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */
lypinator 0:bb348c97df44 7429 #define USB_OTG_GINTSTS_WKUINT_Pos (31U)
lypinator 0:bb348c97df44 7430 #define USB_OTG_GINTSTS_WKUINT_Msk (0x1U << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */
lypinator 0:bb348c97df44 7431 #define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */
lypinator 0:bb348c97df44 7432
lypinator 0:bb348c97df44 7433 /******************** Bit definition for USB_OTG_GINTMSK register ********************/
lypinator 0:bb348c97df44 7434 #define USB_OTG_GINTMSK_MMISM_Pos (1U)
lypinator 0:bb348c97df44 7435 #define USB_OTG_GINTMSK_MMISM_Msk (0x1U << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 7436 #define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk /*!< Mode mismatch interrupt mask */
lypinator 0:bb348c97df44 7437 #define USB_OTG_GINTMSK_OTGINT_Pos (2U)
lypinator 0:bb348c97df44 7438 #define USB_OTG_GINTMSK_OTGINT_Msk (0x1U << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 7439 #define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk /*!< OTG interrupt mask */
lypinator 0:bb348c97df44 7440 #define USB_OTG_GINTMSK_SOFM_Pos (3U)
lypinator 0:bb348c97df44 7441 #define USB_OTG_GINTMSK_SOFM_Msk (0x1U << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 7442 #define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk /*!< Start of frame mask */
lypinator 0:bb348c97df44 7443 #define USB_OTG_GINTMSK_RXFLVLM_Pos (4U)
lypinator 0:bb348c97df44 7444 #define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1U << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 7445 #define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk /*!< Receive FIFO nonempty mask */
lypinator 0:bb348c97df44 7446 #define USB_OTG_GINTMSK_NPTXFEM_Pos (5U)
lypinator 0:bb348c97df44 7447 #define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1U << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 7448 #define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk /*!< Nonperiodic TxFIFO empty mask */
lypinator 0:bb348c97df44 7449 #define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U)
lypinator 0:bb348c97df44 7450 #define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 7451 #define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask */
lypinator 0:bb348c97df44 7452 #define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U)
lypinator 0:bb348c97df44 7453 #define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 7454 #define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask */
lypinator 0:bb348c97df44 7455 #define USB_OTG_GINTMSK_ESUSPM_Pos (10U)
lypinator 0:bb348c97df44 7456 #define USB_OTG_GINTMSK_ESUSPM_Msk (0x1U << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 7457 #define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk /*!< Early suspend mask */
lypinator 0:bb348c97df44 7458 #define USB_OTG_GINTMSK_USBSUSPM_Pos (11U)
lypinator 0:bb348c97df44 7459 #define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1U << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 7460 #define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk /*!< USB suspend mask */
lypinator 0:bb348c97df44 7461 #define USB_OTG_GINTMSK_USBRST_Pos (12U)
lypinator 0:bb348c97df44 7462 #define USB_OTG_GINTMSK_USBRST_Msk (0x1U << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 7463 #define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk /*!< USB reset mask */
lypinator 0:bb348c97df44 7464 #define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U)
lypinator 0:bb348c97df44 7465 #define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1U << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 7466 #define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk /*!< Enumeration done mask */
lypinator 0:bb348c97df44 7467 #define USB_OTG_GINTMSK_ISOODRPM_Pos (14U)
lypinator 0:bb348c97df44 7468 #define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1U << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 7469 #define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk /*!< Isochronous OUT packet dropped interrupt mask */
lypinator 0:bb348c97df44 7470 #define USB_OTG_GINTMSK_EOPFM_Pos (15U)
lypinator 0:bb348c97df44 7471 #define USB_OTG_GINTMSK_EOPFM_Msk (0x1U << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 7472 #define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk /*!< End of periodic frame interrupt mask */
lypinator 0:bb348c97df44 7473 #define USB_OTG_GINTMSK_EPMISM_Pos (17U)
lypinator 0:bb348c97df44 7474 #define USB_OTG_GINTMSK_EPMISM_Msk (0x1U << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 7475 #define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk /*!< Endpoint mismatch interrupt mask */
lypinator 0:bb348c97df44 7476 #define USB_OTG_GINTMSK_IEPINT_Pos (18U)
lypinator 0:bb348c97df44 7477 #define USB_OTG_GINTMSK_IEPINT_Msk (0x1U << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 7478 #define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk /*!< IN endpoints interrupt mask */
lypinator 0:bb348c97df44 7479 #define USB_OTG_GINTMSK_OEPINT_Pos (19U)
lypinator 0:bb348c97df44 7480 #define USB_OTG_GINTMSK_OEPINT_Msk (0x1U << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 7481 #define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk /*!< OUT endpoints interrupt mask */
lypinator 0:bb348c97df44 7482 #define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U)
lypinator 0:bb348c97df44 7483 #define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1U << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 7484 #define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */
lypinator 0:bb348c97df44 7485 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U)
lypinator 0:bb348c97df44 7486 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 7487 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */
lypinator 0:bb348c97df44 7488 #define USB_OTG_GINTMSK_FSUSPM_Pos (22U)
lypinator 0:bb348c97df44 7489 #define USB_OTG_GINTMSK_FSUSPM_Msk (0x1U << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 7490 #define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */
lypinator 0:bb348c97df44 7491 #define USB_OTG_GINTMSK_PRTIM_Pos (24U)
lypinator 0:bb348c97df44 7492 #define USB_OTG_GINTMSK_PRTIM_Msk (0x1U << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 7493 #define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */
lypinator 0:bb348c97df44 7494 #define USB_OTG_GINTMSK_HCIM_Pos (25U)
lypinator 0:bb348c97df44 7495 #define USB_OTG_GINTMSK_HCIM_Msk (0x1U << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 7496 #define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk /*!< Host channels interrupt mask */
lypinator 0:bb348c97df44 7497 #define USB_OTG_GINTMSK_PTXFEM_Pos (26U)
lypinator 0:bb348c97df44 7498 #define USB_OTG_GINTMSK_PTXFEM_Msk (0x1U << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */
lypinator 0:bb348c97df44 7499 #define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk /*!< Periodic TxFIFO empty mask */
lypinator 0:bb348c97df44 7500 #define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U)
lypinator 0:bb348c97df44 7501 #define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1U << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */
lypinator 0:bb348c97df44 7502 #define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk /*!< Connector ID status change mask */
lypinator 0:bb348c97df44 7503 #define USB_OTG_GINTMSK_DISCINT_Pos (29U)
lypinator 0:bb348c97df44 7504 #define USB_OTG_GINTMSK_DISCINT_Msk (0x1U << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */
lypinator 0:bb348c97df44 7505 #define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk /*!< Disconnect detected interrupt mask */
lypinator 0:bb348c97df44 7506 #define USB_OTG_GINTMSK_SRQIM_Pos (30U)
lypinator 0:bb348c97df44 7507 #define USB_OTG_GINTMSK_SRQIM_Msk (0x1U << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */
lypinator 0:bb348c97df44 7508 #define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk /*!< Session request/new session detected interrupt mask */
lypinator 0:bb348c97df44 7509 #define USB_OTG_GINTMSK_WUIM_Pos (31U)
lypinator 0:bb348c97df44 7510 #define USB_OTG_GINTMSK_WUIM_Msk (0x1U << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */
lypinator 0:bb348c97df44 7511 #define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk /*!< Resume/remote wakeup detected interrupt mask */
lypinator 0:bb348c97df44 7512
lypinator 0:bb348c97df44 7513 /******************** Bit definition for USB_OTG_DAINT register ********************/
lypinator 0:bb348c97df44 7514 #define USB_OTG_DAINT_IEPINT_Pos (0U)
lypinator 0:bb348c97df44 7515 #define USB_OTG_DAINT_IEPINT_Msk (0xFFFFU << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */
lypinator 0:bb348c97df44 7516 #define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk /*!< IN endpoint interrupt bits */
lypinator 0:bb348c97df44 7517 #define USB_OTG_DAINT_OEPINT_Pos (16U)
lypinator 0:bb348c97df44 7518 #define USB_OTG_DAINT_OEPINT_Msk (0xFFFFU << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */
lypinator 0:bb348c97df44 7519 #define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk /*!< OUT endpoint interrupt bits */
lypinator 0:bb348c97df44 7520
lypinator 0:bb348c97df44 7521 /******************** Bit definition for USB_OTG_HAINTMSK register ********************/
lypinator 0:bb348c97df44 7522 #define USB_OTG_HAINTMSK_HAINTM_Pos (0U)
lypinator 0:bb348c97df44 7523 #define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFU << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */
lypinator 0:bb348c97df44 7524 #define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */
lypinator 0:bb348c97df44 7525
lypinator 0:bb348c97df44 7526 /******************** Bit definition for USB_OTG_GRXSTSP register ********************/
lypinator 0:bb348c97df44 7527 #define USB_OTG_GRXSTSP_EPNUM_Pos (0U)
lypinator 0:bb348c97df44 7528 #define USB_OTG_GRXSTSP_EPNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */
lypinator 0:bb348c97df44 7529 #define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */
lypinator 0:bb348c97df44 7530 #define USB_OTG_GRXSTSP_BCNT_Pos (4U)
lypinator 0:bb348c97df44 7531 #define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */
lypinator 0:bb348c97df44 7532 #define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */
lypinator 0:bb348c97df44 7533 #define USB_OTG_GRXSTSP_DPID_Pos (15U)
lypinator 0:bb348c97df44 7534 #define USB_OTG_GRXSTSP_DPID_Msk (0x3U << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */
lypinator 0:bb348c97df44 7535 #define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */
lypinator 0:bb348c97df44 7536 #define USB_OTG_GRXSTSP_PKTSTS_Pos (17U)
lypinator 0:bb348c97df44 7537 #define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */
lypinator 0:bb348c97df44 7538 #define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */
lypinator 0:bb348c97df44 7539
lypinator 0:bb348c97df44 7540 /******************** Bit definition for USB_OTG_DAINTMSK register ********************/
lypinator 0:bb348c97df44 7541 #define USB_OTG_DAINTMSK_IEPM_Pos (0U)
lypinator 0:bb348c97df44 7542 #define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */
lypinator 0:bb348c97df44 7543 #define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk /*!< IN EP interrupt mask bits */
lypinator 0:bb348c97df44 7544 #define USB_OTG_DAINTMSK_OEPM_Pos (16U)
lypinator 0:bb348c97df44 7545 #define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */
lypinator 0:bb348c97df44 7546 #define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk /*!< OUT EP interrupt mask bits */
lypinator 0:bb348c97df44 7547
lypinator 0:bb348c97df44 7548 /******************** Bit definition for OTG register ********************/
lypinator 0:bb348c97df44 7549
lypinator 0:bb348c97df44 7550 #define USB_OTG_CHNUM_Pos (0U)
lypinator 0:bb348c97df44 7551 #define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */
lypinator 0:bb348c97df44 7552 #define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */
lypinator 0:bb348c97df44 7553 #define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 7554 #define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 7555 #define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 7556 #define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 7557 #define USB_OTG_BCNT_Pos (4U)
lypinator 0:bb348c97df44 7558 #define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
lypinator 0:bb348c97df44 7559 #define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */
lypinator 0:bb348c97df44 7560
lypinator 0:bb348c97df44 7561 #define USB_OTG_DPID_Pos (15U)
lypinator 0:bb348c97df44 7562 #define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */
lypinator 0:bb348c97df44 7563 #define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */
lypinator 0:bb348c97df44 7564 #define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 7565 #define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 7566
lypinator 0:bb348c97df44 7567 #define USB_OTG_PKTSTS_Pos (17U)
lypinator 0:bb348c97df44 7568 #define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
lypinator 0:bb348c97df44 7569 #define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */
lypinator 0:bb348c97df44 7570 #define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 7571 #define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 7572 #define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 7573 #define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 7574
lypinator 0:bb348c97df44 7575 #define USB_OTG_EPNUM_Pos (0U)
lypinator 0:bb348c97df44 7576 #define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */
lypinator 0:bb348c97df44 7577 #define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */
lypinator 0:bb348c97df44 7578 #define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 7579 #define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 7580 #define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 7581 #define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 7582
lypinator 0:bb348c97df44 7583 #define USB_OTG_FRMNUM_Pos (21U)
lypinator 0:bb348c97df44 7584 #define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
lypinator 0:bb348c97df44 7585 #define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */
lypinator 0:bb348c97df44 7586 #define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 7587 #define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 7588 #define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
lypinator 0:bb348c97df44 7589 #define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 7590
lypinator 0:bb348c97df44 7591 /******************** Bit definition for OTG register ********************/
lypinator 0:bb348c97df44 7592
lypinator 0:bb348c97df44 7593 #define USB_OTG_CHNUM_Pos (0U)
lypinator 0:bb348c97df44 7594 #define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */
lypinator 0:bb348c97df44 7595 #define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */
lypinator 0:bb348c97df44 7596 #define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 7597 #define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 7598 #define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 7599 #define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 7600 #define USB_OTG_BCNT_Pos (4U)
lypinator 0:bb348c97df44 7601 #define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
lypinator 0:bb348c97df44 7602 #define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */
lypinator 0:bb348c97df44 7603
lypinator 0:bb348c97df44 7604 #define USB_OTG_DPID_Pos (15U)
lypinator 0:bb348c97df44 7605 #define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */
lypinator 0:bb348c97df44 7606 #define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */
lypinator 0:bb348c97df44 7607 #define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 7608 #define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 7609
lypinator 0:bb348c97df44 7610 #define USB_OTG_PKTSTS_Pos (17U)
lypinator 0:bb348c97df44 7611 #define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
lypinator 0:bb348c97df44 7612 #define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */
lypinator 0:bb348c97df44 7613 #define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 7614 #define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 7615 #define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 7616 #define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 7617
lypinator 0:bb348c97df44 7618 #define USB_OTG_EPNUM_Pos (0U)
lypinator 0:bb348c97df44 7619 #define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */
lypinator 0:bb348c97df44 7620 #define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */
lypinator 0:bb348c97df44 7621 #define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 7622 #define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 7623 #define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 7624 #define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 7625
lypinator 0:bb348c97df44 7626 #define USB_OTG_FRMNUM_Pos (21U)
lypinator 0:bb348c97df44 7627 #define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
lypinator 0:bb348c97df44 7628 #define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */
lypinator 0:bb348c97df44 7629 #define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 7630 #define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 7631 #define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
lypinator 0:bb348c97df44 7632 #define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 7633
lypinator 0:bb348c97df44 7634 /******************** Bit definition for USB_OTG_GRXFSIZ register ********************/
lypinator 0:bb348c97df44 7635 #define USB_OTG_GRXFSIZ_RXFD_Pos (0U)
lypinator 0:bb348c97df44 7636 #define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFU << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
lypinator 0:bb348c97df44 7637 #define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk /*!< RxFIFO depth */
lypinator 0:bb348c97df44 7638
lypinator 0:bb348c97df44 7639 /******************** Bit definition for USB_OTG_DVBUSDIS register ********************/
lypinator 0:bb348c97df44 7640 #define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U)
lypinator 0:bb348c97df44 7641 #define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFU << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */
lypinator 0:bb348c97df44 7642 #define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk /*!< Device VBUS discharge time */
lypinator 0:bb348c97df44 7643
lypinator 0:bb348c97df44 7644 /******************** Bit definition for OTG register ********************/
lypinator 0:bb348c97df44 7645 #define USB_OTG_NPTXFSA_Pos (0U)
lypinator 0:bb348c97df44 7646 #define USB_OTG_NPTXFSA_Msk (0xFFFFU << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */
lypinator 0:bb348c97df44 7647 #define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk /*!< Nonperiodic transmit RAM start address */
lypinator 0:bb348c97df44 7648 #define USB_OTG_NPTXFD_Pos (16U)
lypinator 0:bb348c97df44 7649 #define USB_OTG_NPTXFD_Msk (0xFFFFU << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */
lypinator 0:bb348c97df44 7650 #define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk /*!< Nonperiodic TxFIFO depth */
lypinator 0:bb348c97df44 7651 #define USB_OTG_TX0FSA_Pos (0U)
lypinator 0:bb348c97df44 7652 #define USB_OTG_TX0FSA_Msk (0xFFFFU << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */
lypinator 0:bb348c97df44 7653 #define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk /*!< Endpoint 0 transmit RAM start address */
lypinator 0:bb348c97df44 7654 #define USB_OTG_TX0FD_Pos (16U)
lypinator 0:bb348c97df44 7655 #define USB_OTG_TX0FD_Msk (0xFFFFU << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */
lypinator 0:bb348c97df44 7656 #define USB_OTG_TX0FD USB_OTG_TX0FD_Msk /*!< Endpoint 0 TxFIFO depth */
lypinator 0:bb348c97df44 7657
lypinator 0:bb348c97df44 7658 /******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
lypinator 0:bb348c97df44 7659 #define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U)
lypinator 0:bb348c97df44 7660 #define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFU << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */
lypinator 0:bb348c97df44 7661 #define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */
lypinator 0:bb348c97df44 7662
lypinator 0:bb348c97df44 7663 /******************** Bit definition for USB_OTG_GNPTXSTS register ********************/
lypinator 0:bb348c97df44 7664 #define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U)
lypinator 0:bb348c97df44 7665 #define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFU << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */
lypinator 0:bb348c97df44 7666 #define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */
lypinator 0:bb348c97df44 7667
lypinator 0:bb348c97df44 7668 #define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U)
lypinator 0:bb348c97df44 7669 #define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFU << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */
lypinator 0:bb348c97df44 7670 #define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */
lypinator 0:bb348c97df44 7671 #define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 7672 #define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 7673 #define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 7674 #define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 7675 #define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 7676 #define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 7677 #define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 7678 #define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */
lypinator 0:bb348c97df44 7679
lypinator 0:bb348c97df44 7680 #define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U)
lypinator 0:bb348c97df44 7681 #define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FU << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */
lypinator 0:bb348c97df44 7682 #define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */
lypinator 0:bb348c97df44 7683 #define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 7684 #define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 7685 #define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */
lypinator 0:bb348c97df44 7686 #define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */
lypinator 0:bb348c97df44 7687 #define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */
lypinator 0:bb348c97df44 7688 #define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */
lypinator 0:bb348c97df44 7689 #define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */
lypinator 0:bb348c97df44 7690
lypinator 0:bb348c97df44 7691 /******************** Bit definition for USB_OTG_DTHRCTL register ********************/
lypinator 0:bb348c97df44 7692 #define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U)
lypinator 0:bb348c97df44 7693 #define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1U << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 7694 #define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */
lypinator 0:bb348c97df44 7695 #define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U)
lypinator 0:bb348c97df44 7696 #define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1U << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 7697 #define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk /*!< ISO IN endpoint threshold enable */
lypinator 0:bb348c97df44 7698
lypinator 0:bb348c97df44 7699 #define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U)
lypinator 0:bb348c97df44 7700 #define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFU << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */
lypinator 0:bb348c97df44 7701 #define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk /*!< Transmit threshold length */
lypinator 0:bb348c97df44 7702 #define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 7703 #define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 7704 #define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 7705 #define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 7706 #define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 7707 #define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 7708 #define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 7709 #define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 7710 #define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 7711 #define USB_OTG_DTHRCTL_RXTHREN_Pos (16U)
lypinator 0:bb348c97df44 7712 #define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1U << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 7713 #define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk /*!< Receive threshold enable */
lypinator 0:bb348c97df44 7714
lypinator 0:bb348c97df44 7715 #define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U)
lypinator 0:bb348c97df44 7716 #define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFU << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */
lypinator 0:bb348c97df44 7717 #define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk /*!< Receive threshold length */
lypinator 0:bb348c97df44 7718 #define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 7719 #define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 7720 #define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 7721 #define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 7722 #define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 7723 #define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 7724 #define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */
lypinator 0:bb348c97df44 7725 #define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 7726 #define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 7727 #define USB_OTG_DTHRCTL_ARPEN_Pos (27U)
lypinator 0:bb348c97df44 7728 #define USB_OTG_DTHRCTL_ARPEN_Msk (0x1U << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */
lypinator 0:bb348c97df44 7729 #define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk /*!< Arbiter parking enable */
lypinator 0:bb348c97df44 7730
lypinator 0:bb348c97df44 7731 /******************** Bit definition for USB_OTG_DIEPEMPMSK register ********************/
lypinator 0:bb348c97df44 7732 #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U)
lypinator 0:bb348c97df44 7733 #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFU << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */
lypinator 0:bb348c97df44 7734 #define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */
lypinator 0:bb348c97df44 7735
lypinator 0:bb348c97df44 7736 /******************** Bit definition for USB_OTG_DEACHINT register ********************/
lypinator 0:bb348c97df44 7737 #define USB_OTG_DEACHINT_IEP1INT_Pos (1U)
lypinator 0:bb348c97df44 7738 #define USB_OTG_DEACHINT_IEP1INT_Msk (0x1U << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 7739 #define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk /*!< IN endpoint 1interrupt bit */
lypinator 0:bb348c97df44 7740 #define USB_OTG_DEACHINT_OEP1INT_Pos (17U)
lypinator 0:bb348c97df44 7741 #define USB_OTG_DEACHINT_OEP1INT_Msk (0x1U << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 7742 #define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk /*!< OUT endpoint 1 interrupt bit */
lypinator 0:bb348c97df44 7743
lypinator 0:bb348c97df44 7744 /******************** Bit definition for USB_OTG_GCCFG register ********************/
lypinator 0:bb348c97df44 7745 #define USB_OTG_GCCFG_PWRDWN_Pos (16U)
lypinator 0:bb348c97df44 7746 #define USB_OTG_GCCFG_PWRDWN_Msk (0x1U << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 7747 #define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk /*!< Power down */
lypinator 0:bb348c97df44 7748 #define USB_OTG_GCCFG_I2CPADEN_Pos (17U)
lypinator 0:bb348c97df44 7749 #define USB_OTG_GCCFG_I2CPADEN_Msk (0x1U << USB_OTG_GCCFG_I2CPADEN_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 7750 #define USB_OTG_GCCFG_I2CPADEN USB_OTG_GCCFG_I2CPADEN_Msk /*!< Enable I2C bus connection for the external I2C PHY interface*/
lypinator 0:bb348c97df44 7751 #define USB_OTG_GCCFG_VBUSASEN_Pos (18U)
lypinator 0:bb348c97df44 7752 #define USB_OTG_GCCFG_VBUSASEN_Msk (0x1U << USB_OTG_GCCFG_VBUSASEN_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 7753 #define USB_OTG_GCCFG_VBUSASEN USB_OTG_GCCFG_VBUSASEN_Msk /*!< Enable the VBUS sensing device */
lypinator 0:bb348c97df44 7754 #define USB_OTG_GCCFG_VBUSBSEN_Pos (19U)
lypinator 0:bb348c97df44 7755 #define USB_OTG_GCCFG_VBUSBSEN_Msk (0x1U << USB_OTG_GCCFG_VBUSBSEN_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 7756 #define USB_OTG_GCCFG_VBUSBSEN USB_OTG_GCCFG_VBUSBSEN_Msk /*!< Enable the VBUS sensing device */
lypinator 0:bb348c97df44 7757 #define USB_OTG_GCCFG_SOFOUTEN_Pos (20U)
lypinator 0:bb348c97df44 7758 #define USB_OTG_GCCFG_SOFOUTEN_Msk (0x1U << USB_OTG_GCCFG_SOFOUTEN_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 7759 #define USB_OTG_GCCFG_SOFOUTEN USB_OTG_GCCFG_SOFOUTEN_Msk /*!< SOF output enable */
lypinator 0:bb348c97df44 7760 #define USB_OTG_GCCFG_NOVBUSSENS_Pos (21U)
lypinator 0:bb348c97df44 7761 #define USB_OTG_GCCFG_NOVBUSSENS_Msk (0x1U << USB_OTG_GCCFG_NOVBUSSENS_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 7762 #define USB_OTG_GCCFG_NOVBUSSENS USB_OTG_GCCFG_NOVBUSSENS_Msk /*!< VBUS sensing disable option*/
lypinator 0:bb348c97df44 7763
lypinator 0:bb348c97df44 7764 /******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
lypinator 0:bb348c97df44 7765 #define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U)
lypinator 0:bb348c97df44 7766 #define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1U << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 7767 #define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit */
lypinator 0:bb348c97df44 7768 #define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U)
lypinator 0:bb348c97df44 7769 #define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1U << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 7770 #define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */
lypinator 0:bb348c97df44 7771
lypinator 0:bb348c97df44 7772 /******************** Bit definition for USB_OTG_CID register ********************/
lypinator 0:bb348c97df44 7773 #define USB_OTG_CID_PRODUCT_ID_Pos (0U)
lypinator 0:bb348c97df44 7774 #define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFU << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */
lypinator 0:bb348c97df44 7775 #define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk /*!< Product ID field */
lypinator 0:bb348c97df44 7776
lypinator 0:bb348c97df44 7777 /******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/
lypinator 0:bb348c97df44 7778 #define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U)
lypinator 0:bb348c97df44 7779 #define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 7780 #define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
lypinator 0:bb348c97df44 7781 #define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U)
lypinator 0:bb348c97df44 7782 #define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 7783 #define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
lypinator 0:bb348c97df44 7784 #define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U)
lypinator 0:bb348c97df44 7785 #define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 7786 #define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
lypinator 0:bb348c97df44 7787 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U)
lypinator 0:bb348c97df44 7788 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1U << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 7789 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
lypinator 0:bb348c97df44 7790 #define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U)
lypinator 0:bb348c97df44 7791 #define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 7792 #define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
lypinator 0:bb348c97df44 7793 #define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U)
lypinator 0:bb348c97df44 7794 #define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 7795 #define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
lypinator 0:bb348c97df44 7796 #define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U)
lypinator 0:bb348c97df44 7797 #define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 7798 #define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */
lypinator 0:bb348c97df44 7799 #define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U)
lypinator 0:bb348c97df44 7800 #define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 7801 #define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
lypinator 0:bb348c97df44 7802 #define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U)
lypinator 0:bb348c97df44 7803 #define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 7804 #define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
lypinator 0:bb348c97df44 7805
lypinator 0:bb348c97df44 7806 /******************** Bit definition for USB_OTG_HPRT register ********************/
lypinator 0:bb348c97df44 7807 #define USB_OTG_HPRT_PCSTS_Pos (0U)
lypinator 0:bb348c97df44 7808 #define USB_OTG_HPRT_PCSTS_Msk (0x1U << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 7809 #define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk /*!< Port connect status */
lypinator 0:bb348c97df44 7810 #define USB_OTG_HPRT_PCDET_Pos (1U)
lypinator 0:bb348c97df44 7811 #define USB_OTG_HPRT_PCDET_Msk (0x1U << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 7812 #define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk /*!< Port connect detected */
lypinator 0:bb348c97df44 7813 #define USB_OTG_HPRT_PENA_Pos (2U)
lypinator 0:bb348c97df44 7814 #define USB_OTG_HPRT_PENA_Msk (0x1U << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 7815 #define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk /*!< Port enable */
lypinator 0:bb348c97df44 7816 #define USB_OTG_HPRT_PENCHNG_Pos (3U)
lypinator 0:bb348c97df44 7817 #define USB_OTG_HPRT_PENCHNG_Msk (0x1U << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 7818 #define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk /*!< Port enable/disable change */
lypinator 0:bb348c97df44 7819 #define USB_OTG_HPRT_POCA_Pos (4U)
lypinator 0:bb348c97df44 7820 #define USB_OTG_HPRT_POCA_Msk (0x1U << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 7821 #define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk /*!< Port overcurrent active */
lypinator 0:bb348c97df44 7822 #define USB_OTG_HPRT_POCCHNG_Pos (5U)
lypinator 0:bb348c97df44 7823 #define USB_OTG_HPRT_POCCHNG_Msk (0x1U << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 7824 #define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk /*!< Port overcurrent change */
lypinator 0:bb348c97df44 7825 #define USB_OTG_HPRT_PRES_Pos (6U)
lypinator 0:bb348c97df44 7826 #define USB_OTG_HPRT_PRES_Msk (0x1U << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 7827 #define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk /*!< Port resume */
lypinator 0:bb348c97df44 7828 #define USB_OTG_HPRT_PSUSP_Pos (7U)
lypinator 0:bb348c97df44 7829 #define USB_OTG_HPRT_PSUSP_Msk (0x1U << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 7830 #define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk /*!< Port suspend */
lypinator 0:bb348c97df44 7831 #define USB_OTG_HPRT_PRST_Pos (8U)
lypinator 0:bb348c97df44 7832 #define USB_OTG_HPRT_PRST_Msk (0x1U << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 7833 #define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */
lypinator 0:bb348c97df44 7834
lypinator 0:bb348c97df44 7835 #define USB_OTG_HPRT_PLSTS_Pos (10U)
lypinator 0:bb348c97df44 7836 #define USB_OTG_HPRT_PLSTS_Msk (0x3U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */
lypinator 0:bb348c97df44 7837 #define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */
lypinator 0:bb348c97df44 7838 #define USB_OTG_HPRT_PLSTS_0 (0x1U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 7839 #define USB_OTG_HPRT_PLSTS_1 (0x2U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 7840 #define USB_OTG_HPRT_PPWR_Pos (12U)
lypinator 0:bb348c97df44 7841 #define USB_OTG_HPRT_PPWR_Msk (0x1U << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 7842 #define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */
lypinator 0:bb348c97df44 7843
lypinator 0:bb348c97df44 7844 #define USB_OTG_HPRT_PTCTL_Pos (13U)
lypinator 0:bb348c97df44 7845 #define USB_OTG_HPRT_PTCTL_Msk (0xFU << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */
lypinator 0:bb348c97df44 7846 #define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */
lypinator 0:bb348c97df44 7847 #define USB_OTG_HPRT_PTCTL_0 (0x1U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 7848 #define USB_OTG_HPRT_PTCTL_1 (0x2U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 7849 #define USB_OTG_HPRT_PTCTL_2 (0x4U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 7850 #define USB_OTG_HPRT_PTCTL_3 (0x8U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 7851
lypinator 0:bb348c97df44 7852 #define USB_OTG_HPRT_PSPD_Pos (17U)
lypinator 0:bb348c97df44 7853 #define USB_OTG_HPRT_PSPD_Msk (0x3U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */
lypinator 0:bb348c97df44 7854 #define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */
lypinator 0:bb348c97df44 7855 #define USB_OTG_HPRT_PSPD_0 (0x1U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 7856 #define USB_OTG_HPRT_PSPD_1 (0x2U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 7857
lypinator 0:bb348c97df44 7858 /******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/
lypinator 0:bb348c97df44 7859 #define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U)
lypinator 0:bb348c97df44 7860 #define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 7861 #define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
lypinator 0:bb348c97df44 7862 #define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U)
lypinator 0:bb348c97df44 7863 #define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 7864 #define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
lypinator 0:bb348c97df44 7865 #define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U)
lypinator 0:bb348c97df44 7866 #define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 7867 #define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk /*!< Timeout condition mask */
lypinator 0:bb348c97df44 7868 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U)
lypinator 0:bb348c97df44 7869 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1U << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 7870 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
lypinator 0:bb348c97df44 7871 #define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U)
lypinator 0:bb348c97df44 7872 #define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 7873 #define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
lypinator 0:bb348c97df44 7874 #define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U)
lypinator 0:bb348c97df44 7875 #define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 7876 #define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
lypinator 0:bb348c97df44 7877 #define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U)
lypinator 0:bb348c97df44 7878 #define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 7879 #define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */
lypinator 0:bb348c97df44 7880 #define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U)
lypinator 0:bb348c97df44 7881 #define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 7882 #define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
lypinator 0:bb348c97df44 7883 #define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U)
lypinator 0:bb348c97df44 7884 #define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 7885 #define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */
lypinator 0:bb348c97df44 7886 #define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U)
lypinator 0:bb348c97df44 7887 #define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 7888 #define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
lypinator 0:bb348c97df44 7889 #define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U)
lypinator 0:bb348c97df44 7890 #define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 7891 #define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */
lypinator 0:bb348c97df44 7892
lypinator 0:bb348c97df44 7893 /******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/
lypinator 0:bb348c97df44 7894 #define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U)
lypinator 0:bb348c97df44 7895 #define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */
lypinator 0:bb348c97df44 7896 #define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */
lypinator 0:bb348c97df44 7897 #define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U)
lypinator 0:bb348c97df44 7898 #define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */
lypinator 0:bb348c97df44 7899 #define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */
lypinator 0:bb348c97df44 7900
lypinator 0:bb348c97df44 7901 /******************** Bit definition for USB_OTG_DIEPCTL register ********************/
lypinator 0:bb348c97df44 7902 #define USB_OTG_DIEPCTL_MPSIZ_Pos (0U)
lypinator 0:bb348c97df44 7903 #define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFU << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
lypinator 0:bb348c97df44 7904 #define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk /*!< Maximum packet size */
lypinator 0:bb348c97df44 7905 #define USB_OTG_DIEPCTL_USBAEP_Pos (15U)
lypinator 0:bb348c97df44 7906 #define USB_OTG_DIEPCTL_USBAEP_Msk (0x1U << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 7907 #define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk /*!< USB active endpoint */
lypinator 0:bb348c97df44 7908 #define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U)
lypinator 0:bb348c97df44 7909 #define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1U << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 7910 #define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */
lypinator 0:bb348c97df44 7911 #define USB_OTG_DIEPCTL_NAKSTS_Pos (17U)
lypinator 0:bb348c97df44 7912 #define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 7913 #define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk /*!< NAK status */
lypinator 0:bb348c97df44 7914
lypinator 0:bb348c97df44 7915 #define USB_OTG_DIEPCTL_EPTYP_Pos (18U)
lypinator 0:bb348c97df44 7916 #define USB_OTG_DIEPCTL_EPTYP_Msk (0x3U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
lypinator 0:bb348c97df44 7917 #define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk /*!< Endpoint type */
lypinator 0:bb348c97df44 7918 #define USB_OTG_DIEPCTL_EPTYP_0 (0x1U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 7919 #define USB_OTG_DIEPCTL_EPTYP_1 (0x2U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 7920 #define USB_OTG_DIEPCTL_STALL_Pos (21U)
lypinator 0:bb348c97df44 7921 #define USB_OTG_DIEPCTL_STALL_Msk (0x1U << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 7922 #define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk /*!< STALL handshake */
lypinator 0:bb348c97df44 7923
lypinator 0:bb348c97df44 7924 #define USB_OTG_DIEPCTL_TXFNUM_Pos (22U)
lypinator 0:bb348c97df44 7925 #define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFU << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */
lypinator 0:bb348c97df44 7926 #define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk /*!< TxFIFO number */
lypinator 0:bb348c97df44 7927 #define USB_OTG_DIEPCTL_TXFNUM_0 (0x1U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 7928 #define USB_OTG_DIEPCTL_TXFNUM_1 (0x2U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */
lypinator 0:bb348c97df44 7929 #define USB_OTG_DIEPCTL_TXFNUM_2 (0x4U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 7930 #define USB_OTG_DIEPCTL_TXFNUM_3 (0x8U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 7931 #define USB_OTG_DIEPCTL_CNAK_Pos (26U)
lypinator 0:bb348c97df44 7932 #define USB_OTG_DIEPCTL_CNAK_Msk (0x1U << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */
lypinator 0:bb348c97df44 7933 #define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk /*!< Clear NAK */
lypinator 0:bb348c97df44 7934 #define USB_OTG_DIEPCTL_SNAK_Pos (27U)
lypinator 0:bb348c97df44 7935 #define USB_OTG_DIEPCTL_SNAK_Msk (0x1U << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */
lypinator 0:bb348c97df44 7936 #define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */
lypinator 0:bb348c97df44 7937 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U)
lypinator 0:bb348c97df44 7938 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
lypinator 0:bb348c97df44 7939 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
lypinator 0:bb348c97df44 7940 #define USB_OTG_DIEPCTL_SODDFRM_Pos (29U)
lypinator 0:bb348c97df44 7941 #define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
lypinator 0:bb348c97df44 7942 #define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */
lypinator 0:bb348c97df44 7943 #define USB_OTG_DIEPCTL_EPDIS_Pos (30U)
lypinator 0:bb348c97df44 7944 #define USB_OTG_DIEPCTL_EPDIS_Msk (0x1U << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */
lypinator 0:bb348c97df44 7945 #define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */
lypinator 0:bb348c97df44 7946 #define USB_OTG_DIEPCTL_EPENA_Pos (31U)
lypinator 0:bb348c97df44 7947 #define USB_OTG_DIEPCTL_EPENA_Msk (0x1U << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */
lypinator 0:bb348c97df44 7948 #define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk /*!< Endpoint enable */
lypinator 0:bb348c97df44 7949
lypinator 0:bb348c97df44 7950 /******************** Bit definition for USB_OTG_HCCHAR register ********************/
lypinator 0:bb348c97df44 7951 #define USB_OTG_HCCHAR_MPSIZ_Pos (0U)
lypinator 0:bb348c97df44 7952 #define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFU << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */
lypinator 0:bb348c97df44 7953 #define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */
lypinator 0:bb348c97df44 7954
lypinator 0:bb348c97df44 7955 #define USB_OTG_HCCHAR_EPNUM_Pos (11U)
lypinator 0:bb348c97df44 7956 #define USB_OTG_HCCHAR_EPNUM_Msk (0xFU << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */
lypinator 0:bb348c97df44 7957 #define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */
lypinator 0:bb348c97df44 7958 #define USB_OTG_HCCHAR_EPNUM_0 (0x1U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 7959 #define USB_OTG_HCCHAR_EPNUM_1 (0x2U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 7960 #define USB_OTG_HCCHAR_EPNUM_2 (0x4U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 7961 #define USB_OTG_HCCHAR_EPNUM_3 (0x8U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 7962 #define USB_OTG_HCCHAR_EPDIR_Pos (15U)
lypinator 0:bb348c97df44 7963 #define USB_OTG_HCCHAR_EPDIR_Msk (0x1U << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 7964 #define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk /*!< Endpoint direction */
lypinator 0:bb348c97df44 7965 #define USB_OTG_HCCHAR_LSDEV_Pos (17U)
lypinator 0:bb348c97df44 7966 #define USB_OTG_HCCHAR_LSDEV_Msk (0x1U << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 7967 #define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */
lypinator 0:bb348c97df44 7968
lypinator 0:bb348c97df44 7969 #define USB_OTG_HCCHAR_EPTYP_Pos (18U)
lypinator 0:bb348c97df44 7970 #define USB_OTG_HCCHAR_EPTYP_Msk (0x3U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */
lypinator 0:bb348c97df44 7971 #define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */
lypinator 0:bb348c97df44 7972 #define USB_OTG_HCCHAR_EPTYP_0 (0x1U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 7973 #define USB_OTG_HCCHAR_EPTYP_1 (0x2U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 7974
lypinator 0:bb348c97df44 7975 #define USB_OTG_HCCHAR_MC_Pos (20U)
lypinator 0:bb348c97df44 7976 #define USB_OTG_HCCHAR_MC_Msk (0x3U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */
lypinator 0:bb348c97df44 7977 #define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */
lypinator 0:bb348c97df44 7978 #define USB_OTG_HCCHAR_MC_0 (0x1U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 7979 #define USB_OTG_HCCHAR_MC_1 (0x2U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 7980
lypinator 0:bb348c97df44 7981 #define USB_OTG_HCCHAR_DAD_Pos (22U)
lypinator 0:bb348c97df44 7982 #define USB_OTG_HCCHAR_DAD_Msk (0x7FU << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */
lypinator 0:bb348c97df44 7983 #define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */
lypinator 0:bb348c97df44 7984 #define USB_OTG_HCCHAR_DAD_0 (0x01U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */
lypinator 0:bb348c97df44 7985 #define USB_OTG_HCCHAR_DAD_1 (0x02U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */
lypinator 0:bb348c97df44 7986 #define USB_OTG_HCCHAR_DAD_2 (0x04U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */
lypinator 0:bb348c97df44 7987 #define USB_OTG_HCCHAR_DAD_3 (0x08U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */
lypinator 0:bb348c97df44 7988 #define USB_OTG_HCCHAR_DAD_4 (0x10U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */
lypinator 0:bb348c97df44 7989 #define USB_OTG_HCCHAR_DAD_5 (0x20U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */
lypinator 0:bb348c97df44 7990 #define USB_OTG_HCCHAR_DAD_6 (0x40U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */
lypinator 0:bb348c97df44 7991 #define USB_OTG_HCCHAR_ODDFRM_Pos (29U)
lypinator 0:bb348c97df44 7992 #define USB_OTG_HCCHAR_ODDFRM_Msk (0x1U << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */
lypinator 0:bb348c97df44 7993 #define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk /*!< Odd frame */
lypinator 0:bb348c97df44 7994 #define USB_OTG_HCCHAR_CHDIS_Pos (30U)
lypinator 0:bb348c97df44 7995 #define USB_OTG_HCCHAR_CHDIS_Msk (0x1U << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */
lypinator 0:bb348c97df44 7996 #define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk /*!< Channel disable */
lypinator 0:bb348c97df44 7997 #define USB_OTG_HCCHAR_CHENA_Pos (31U)
lypinator 0:bb348c97df44 7998 #define USB_OTG_HCCHAR_CHENA_Msk (0x1U << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */
lypinator 0:bb348c97df44 7999 #define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk /*!< Channel enable */
lypinator 0:bb348c97df44 8000
lypinator 0:bb348c97df44 8001 /******************** Bit definition for USB_OTG_HCSPLT register ********************/
lypinator 0:bb348c97df44 8002
lypinator 0:bb348c97df44 8003 #define USB_OTG_HCSPLT_PRTADDR_Pos (0U)
lypinator 0:bb348c97df44 8004 #define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FU << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */
lypinator 0:bb348c97df44 8005 #define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk /*!< Port address */
lypinator 0:bb348c97df44 8006 #define USB_OTG_HCSPLT_PRTADDR_0 (0x01U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 8007 #define USB_OTG_HCSPLT_PRTADDR_1 (0x02U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 8008 #define USB_OTG_HCSPLT_PRTADDR_2 (0x04U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 8009 #define USB_OTG_HCSPLT_PRTADDR_3 (0x08U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 8010 #define USB_OTG_HCSPLT_PRTADDR_4 (0x10U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 8011 #define USB_OTG_HCSPLT_PRTADDR_5 (0x20U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 8012 #define USB_OTG_HCSPLT_PRTADDR_6 (0x40U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 8013
lypinator 0:bb348c97df44 8014 #define USB_OTG_HCSPLT_HUBADDR_Pos (7U)
lypinator 0:bb348c97df44 8015 #define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FU << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */
lypinator 0:bb348c97df44 8016 #define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk /*!< Hub address */
lypinator 0:bb348c97df44 8017 #define USB_OTG_HCSPLT_HUBADDR_0 (0x01U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 8018 #define USB_OTG_HCSPLT_HUBADDR_1 (0x02U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 8019 #define USB_OTG_HCSPLT_HUBADDR_2 (0x04U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 8020 #define USB_OTG_HCSPLT_HUBADDR_3 (0x08U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 8021 #define USB_OTG_HCSPLT_HUBADDR_4 (0x10U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 8022 #define USB_OTG_HCSPLT_HUBADDR_5 (0x20U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 8023 #define USB_OTG_HCSPLT_HUBADDR_6 (0x40U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 8024
lypinator 0:bb348c97df44 8025 #define USB_OTG_HCSPLT_XACTPOS_Pos (14U)
lypinator 0:bb348c97df44 8026 #define USB_OTG_HCSPLT_XACTPOS_Msk (0x3U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */
lypinator 0:bb348c97df44 8027 #define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk /*!< XACTPOS */
lypinator 0:bb348c97df44 8028 #define USB_OTG_HCSPLT_XACTPOS_0 (0x1U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 8029 #define USB_OTG_HCSPLT_XACTPOS_1 (0x2U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 8030 #define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U)
lypinator 0:bb348c97df44 8031 #define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1U << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */
lypinator 0:bb348c97df44 8032 #define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk /*!< Do complete split */
lypinator 0:bb348c97df44 8033 #define USB_OTG_HCSPLT_SPLITEN_Pos (31U)
lypinator 0:bb348c97df44 8034 #define USB_OTG_HCSPLT_SPLITEN_Msk (0x1U << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */
lypinator 0:bb348c97df44 8035 #define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk /*!< Split enable */
lypinator 0:bb348c97df44 8036
lypinator 0:bb348c97df44 8037 /******************** Bit definition for USB_OTG_HCINT register ********************/
lypinator 0:bb348c97df44 8038 #define USB_OTG_HCINT_XFRC_Pos (0U)
lypinator 0:bb348c97df44 8039 #define USB_OTG_HCINT_XFRC_Msk (0x1U << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 8040 #define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk /*!< Transfer completed */
lypinator 0:bb348c97df44 8041 #define USB_OTG_HCINT_CHH_Pos (1U)
lypinator 0:bb348c97df44 8042 #define USB_OTG_HCINT_CHH_Msk (0x1U << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 8043 #define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk /*!< Channel halted */
lypinator 0:bb348c97df44 8044 #define USB_OTG_HCINT_AHBERR_Pos (2U)
lypinator 0:bb348c97df44 8045 #define USB_OTG_HCINT_AHBERR_Msk (0x1U << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 8046 #define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk /*!< AHB error */
lypinator 0:bb348c97df44 8047 #define USB_OTG_HCINT_STALL_Pos (3U)
lypinator 0:bb348c97df44 8048 #define USB_OTG_HCINT_STALL_Msk (0x1U << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 8049 #define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk /*!< STALL response received interrupt */
lypinator 0:bb348c97df44 8050 #define USB_OTG_HCINT_NAK_Pos (4U)
lypinator 0:bb348c97df44 8051 #define USB_OTG_HCINT_NAK_Msk (0x1U << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 8052 #define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk /*!< NAK response received interrupt */
lypinator 0:bb348c97df44 8053 #define USB_OTG_HCINT_ACK_Pos (5U)
lypinator 0:bb348c97df44 8054 #define USB_OTG_HCINT_ACK_Msk (0x1U << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 8055 #define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk /*!< ACK response received/transmitted interrupt */
lypinator 0:bb348c97df44 8056 #define USB_OTG_HCINT_NYET_Pos (6U)
lypinator 0:bb348c97df44 8057 #define USB_OTG_HCINT_NYET_Msk (0x1U << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 8058 #define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk /*!< Response received interrupt */
lypinator 0:bb348c97df44 8059 #define USB_OTG_HCINT_TXERR_Pos (7U)
lypinator 0:bb348c97df44 8060 #define USB_OTG_HCINT_TXERR_Msk (0x1U << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 8061 #define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk /*!< Transaction error */
lypinator 0:bb348c97df44 8062 #define USB_OTG_HCINT_BBERR_Pos (8U)
lypinator 0:bb348c97df44 8063 #define USB_OTG_HCINT_BBERR_Msk (0x1U << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 8064 #define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk /*!< Babble error */
lypinator 0:bb348c97df44 8065 #define USB_OTG_HCINT_FRMOR_Pos (9U)
lypinator 0:bb348c97df44 8066 #define USB_OTG_HCINT_FRMOR_Msk (0x1U << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 8067 #define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk /*!< Frame overrun */
lypinator 0:bb348c97df44 8068 #define USB_OTG_HCINT_DTERR_Pos (10U)
lypinator 0:bb348c97df44 8069 #define USB_OTG_HCINT_DTERR_Msk (0x1U << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 8070 #define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk /*!< Data toggle error */
lypinator 0:bb348c97df44 8071
lypinator 0:bb348c97df44 8072 /******************** Bit definition for USB_OTG_DIEPINT register ********************/
lypinator 0:bb348c97df44 8073 #define USB_OTG_DIEPINT_XFRC_Pos (0U)
lypinator 0:bb348c97df44 8074 #define USB_OTG_DIEPINT_XFRC_Msk (0x1U << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 8075 #define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk /*!< Transfer completed interrupt */
lypinator 0:bb348c97df44 8076 #define USB_OTG_DIEPINT_EPDISD_Pos (1U)
lypinator 0:bb348c97df44 8077 #define USB_OTG_DIEPINT_EPDISD_Msk (0x1U << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 8078 #define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
lypinator 0:bb348c97df44 8079 #define USB_OTG_DIEPINT_TOC_Pos (3U)
lypinator 0:bb348c97df44 8080 #define USB_OTG_DIEPINT_TOC_Msk (0x1U << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 8081 #define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk /*!< Timeout condition */
lypinator 0:bb348c97df44 8082 #define USB_OTG_DIEPINT_ITTXFE_Pos (4U)
lypinator 0:bb348c97df44 8083 #define USB_OTG_DIEPINT_ITTXFE_Msk (0x1U << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 8084 #define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */
lypinator 0:bb348c97df44 8085 #define USB_OTG_DIEPINT_INEPNE_Pos (6U)
lypinator 0:bb348c97df44 8086 #define USB_OTG_DIEPINT_INEPNE_Msk (0x1U << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 8087 #define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */
lypinator 0:bb348c97df44 8088 #define USB_OTG_DIEPINT_TXFE_Pos (7U)
lypinator 0:bb348c97df44 8089 #define USB_OTG_DIEPINT_TXFE_Msk (0x1U << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 8090 #define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk /*!< Transmit FIFO empty */
lypinator 0:bb348c97df44 8091 #define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U)
lypinator 0:bb348c97df44 8092 #define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1U << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 8093 #define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */
lypinator 0:bb348c97df44 8094 #define USB_OTG_DIEPINT_BNA_Pos (9U)
lypinator 0:bb348c97df44 8095 #define USB_OTG_DIEPINT_BNA_Msk (0x1U << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 8096 #define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk /*!< Buffer not available interrupt */
lypinator 0:bb348c97df44 8097 #define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U)
lypinator 0:bb348c97df44 8098 #define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1U << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */
lypinator 0:bb348c97df44 8099 #define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */
lypinator 0:bb348c97df44 8100 #define USB_OTG_DIEPINT_BERR_Pos (12U)
lypinator 0:bb348c97df44 8101 #define USB_OTG_DIEPINT_BERR_Msk (0x1U << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */
lypinator 0:bb348c97df44 8102 #define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk /*!< Babble error interrupt */
lypinator 0:bb348c97df44 8103 #define USB_OTG_DIEPINT_NAK_Pos (13U)
lypinator 0:bb348c97df44 8104 #define USB_OTG_DIEPINT_NAK_Msk (0x1U << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */
lypinator 0:bb348c97df44 8105 #define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk /*!< NAK interrupt */
lypinator 0:bb348c97df44 8106
lypinator 0:bb348c97df44 8107 /******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
lypinator 0:bb348c97df44 8108 #define USB_OTG_HCINTMSK_XFRCM_Pos (0U)
lypinator 0:bb348c97df44 8109 #define USB_OTG_HCINTMSK_XFRCM_Msk (0x1U << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 8110 #define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk /*!< Transfer completed mask */
lypinator 0:bb348c97df44 8111 #define USB_OTG_HCINTMSK_CHHM_Pos (1U)
lypinator 0:bb348c97df44 8112 #define USB_OTG_HCINTMSK_CHHM_Msk (0x1U << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 8113 #define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */
lypinator 0:bb348c97df44 8114 #define USB_OTG_HCINTMSK_AHBERR_Pos (2U)
lypinator 0:bb348c97df44 8115 #define USB_OTG_HCINTMSK_AHBERR_Msk (0x1U << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */
lypinator 0:bb348c97df44 8116 #define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */
lypinator 0:bb348c97df44 8117 #define USB_OTG_HCINTMSK_STALLM_Pos (3U)
lypinator 0:bb348c97df44 8118 #define USB_OTG_HCINTMSK_STALLM_Msk (0x1U << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 8119 #define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */
lypinator 0:bb348c97df44 8120 #define USB_OTG_HCINTMSK_NAKM_Pos (4U)
lypinator 0:bb348c97df44 8121 #define USB_OTG_HCINTMSK_NAKM_Msk (0x1U << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 8122 #define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk /*!< NAK response received interrupt mask */
lypinator 0:bb348c97df44 8123 #define USB_OTG_HCINTMSK_ACKM_Pos (5U)
lypinator 0:bb348c97df44 8124 #define USB_OTG_HCINTMSK_ACKM_Msk (0x1U << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */
lypinator 0:bb348c97df44 8125 #define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk /*!< ACK response received/transmitted interrupt mask */
lypinator 0:bb348c97df44 8126 #define USB_OTG_HCINTMSK_NYET_Pos (6U)
lypinator 0:bb348c97df44 8127 #define USB_OTG_HCINTMSK_NYET_Msk (0x1U << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 8128 #define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk /*!< response received interrupt mask */
lypinator 0:bb348c97df44 8129 #define USB_OTG_HCINTMSK_TXERRM_Pos (7U)
lypinator 0:bb348c97df44 8130 #define USB_OTG_HCINTMSK_TXERRM_Msk (0x1U << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */
lypinator 0:bb348c97df44 8131 #define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk /*!< Transaction error mask */
lypinator 0:bb348c97df44 8132 #define USB_OTG_HCINTMSK_BBERRM_Pos (8U)
lypinator 0:bb348c97df44 8133 #define USB_OTG_HCINTMSK_BBERRM_Msk (0x1U << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */
lypinator 0:bb348c97df44 8134 #define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk /*!< Babble error mask */
lypinator 0:bb348c97df44 8135 #define USB_OTG_HCINTMSK_FRMORM_Pos (9U)
lypinator 0:bb348c97df44 8136 #define USB_OTG_HCINTMSK_FRMORM_Msk (0x1U << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */
lypinator 0:bb348c97df44 8137 #define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk /*!< Frame overrun mask */
lypinator 0:bb348c97df44 8138 #define USB_OTG_HCINTMSK_DTERRM_Pos (10U)
lypinator 0:bb348c97df44 8139 #define USB_OTG_HCINTMSK_DTERRM_Msk (0x1U << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */
lypinator 0:bb348c97df44 8140 #define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk /*!< Data toggle error mask */
lypinator 0:bb348c97df44 8141
lypinator 0:bb348c97df44 8142 /******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
lypinator 0:bb348c97df44 8143
lypinator 0:bb348c97df44 8144 #define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U)
lypinator 0:bb348c97df44 8145 #define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
lypinator 0:bb348c97df44 8146 #define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
lypinator 0:bb348c97df44 8147 #define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U)
lypinator 0:bb348c97df44 8148 #define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
lypinator 0:bb348c97df44 8149 #define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */
lypinator 0:bb348c97df44 8150 #define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U)
lypinator 0:bb348c97df44 8151 #define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */
lypinator 0:bb348c97df44 8152 #define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */
lypinator 0:bb348c97df44 8153 /******************** Bit definition for USB_OTG_HCTSIZ register ********************/
lypinator 0:bb348c97df44 8154 #define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U)
lypinator 0:bb348c97df44 8155 #define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
lypinator 0:bb348c97df44 8156 #define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk /*!< Transfer size */
lypinator 0:bb348c97df44 8157 #define USB_OTG_HCTSIZ_PKTCNT_Pos (19U)
lypinator 0:bb348c97df44 8158 #define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
lypinator 0:bb348c97df44 8159 #define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */
lypinator 0:bb348c97df44 8160 #define USB_OTG_HCTSIZ_DOPING_Pos (31U)
lypinator 0:bb348c97df44 8161 #define USB_OTG_HCTSIZ_DOPING_Msk (0x1U << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */
lypinator 0:bb348c97df44 8162 #define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */
lypinator 0:bb348c97df44 8163 #define USB_OTG_HCTSIZ_DPID_Pos (29U)
lypinator 0:bb348c97df44 8164 #define USB_OTG_HCTSIZ_DPID_Msk (0x3U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */
lypinator 0:bb348c97df44 8165 #define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */
lypinator 0:bb348c97df44 8166 #define USB_OTG_HCTSIZ_DPID_0 (0x1U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */
lypinator 0:bb348c97df44 8167 #define USB_OTG_HCTSIZ_DPID_1 (0x2U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */
lypinator 0:bb348c97df44 8168
lypinator 0:bb348c97df44 8169 /******************** Bit definition for USB_OTG_DIEPDMA register ********************/
lypinator 0:bb348c97df44 8170 #define USB_OTG_DIEPDMA_DMAADDR_Pos (0U)
lypinator 0:bb348c97df44 8171 #define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFU << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
lypinator 0:bb348c97df44 8172 #define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk /*!< DMA address */
lypinator 0:bb348c97df44 8173
lypinator 0:bb348c97df44 8174 /******************** Bit definition for USB_OTG_HCDMA register ********************/
lypinator 0:bb348c97df44 8175 #define USB_OTG_HCDMA_DMAADDR_Pos (0U)
lypinator 0:bb348c97df44 8176 #define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFU << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
lypinator 0:bb348c97df44 8177 #define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk /*!< DMA address */
lypinator 0:bb348c97df44 8178
lypinator 0:bb348c97df44 8179 /******************** Bit definition for USB_OTG_DTXFSTS register ********************/
lypinator 0:bb348c97df44 8180 #define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U)
lypinator 0:bb348c97df44 8181 #define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFU << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */
lypinator 0:bb348c97df44 8182 #define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */
lypinator 0:bb348c97df44 8183
lypinator 0:bb348c97df44 8184 /******************** Bit definition for USB_OTG_DIEPTXF register ********************/
lypinator 0:bb348c97df44 8185 #define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U)
lypinator 0:bb348c97df44 8186 #define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFU << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */
lypinator 0:bb348c97df44 8187 #define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk /*!< IN endpoint FIFOx transmit RAM start address */
lypinator 0:bb348c97df44 8188 #define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U)
lypinator 0:bb348c97df44 8189 #define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFU << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */
lypinator 0:bb348c97df44 8190 #define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk /*!< IN endpoint TxFIFO depth */
lypinator 0:bb348c97df44 8191
lypinator 0:bb348c97df44 8192 /******************** Bit definition for USB_OTG_DOEPCTL register ********************/
lypinator 0:bb348c97df44 8193
lypinator 0:bb348c97df44 8194 #define USB_OTG_DOEPCTL_MPSIZ_Pos (0U)
lypinator 0:bb348c97df44 8195 #define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFU << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
lypinator 0:bb348c97df44 8196 #define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk /*!< Maximum packet size */ /*!<Bit 1 */
lypinator 0:bb348c97df44 8197 #define USB_OTG_DOEPCTL_USBAEP_Pos (15U)
lypinator 0:bb348c97df44 8198 #define USB_OTG_DOEPCTL_USBAEP_Msk (0x1U << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */
lypinator 0:bb348c97df44 8199 #define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk /*!< USB active endpoint */
lypinator 0:bb348c97df44 8200 #define USB_OTG_DOEPCTL_NAKSTS_Pos (17U)
lypinator 0:bb348c97df44 8201 #define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
lypinator 0:bb348c97df44 8202 #define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk /*!< NAK status */
lypinator 0:bb348c97df44 8203 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U)
lypinator 0:bb348c97df44 8204 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
lypinator 0:bb348c97df44 8205 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
lypinator 0:bb348c97df44 8206 #define USB_OTG_DOEPCTL_SODDFRM_Pos (29U)
lypinator 0:bb348c97df44 8207 #define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
lypinator 0:bb348c97df44 8208 #define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk /*!< Set odd frame */
lypinator 0:bb348c97df44 8209 #define USB_OTG_DOEPCTL_EPTYP_Pos (18U)
lypinator 0:bb348c97df44 8210 #define USB_OTG_DOEPCTL_EPTYP_Msk (0x3U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
lypinator 0:bb348c97df44 8211 #define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk /*!< Endpoint type */
lypinator 0:bb348c97df44 8212 #define USB_OTG_DOEPCTL_EPTYP_0 (0x1U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */
lypinator 0:bb348c97df44 8213 #define USB_OTG_DOEPCTL_EPTYP_1 (0x2U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */
lypinator 0:bb348c97df44 8214 #define USB_OTG_DOEPCTL_SNPM_Pos (20U)
lypinator 0:bb348c97df44 8215 #define USB_OTG_DOEPCTL_SNPM_Msk (0x1U << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */
lypinator 0:bb348c97df44 8216 #define USB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_Msk /*!< Snoop mode */
lypinator 0:bb348c97df44 8217 #define USB_OTG_DOEPCTL_STALL_Pos (21U)
lypinator 0:bb348c97df44 8218 #define USB_OTG_DOEPCTL_STALL_Msk (0x1U << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */
lypinator 0:bb348c97df44 8219 #define USB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_Msk /*!< STALL handshake */
lypinator 0:bb348c97df44 8220 #define USB_OTG_DOEPCTL_CNAK_Pos (26U)
lypinator 0:bb348c97df44 8221 #define USB_OTG_DOEPCTL_CNAK_Msk (0x1U << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */
lypinator 0:bb348c97df44 8222 #define USB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_Msk /*!< Clear NAK */
lypinator 0:bb348c97df44 8223 #define USB_OTG_DOEPCTL_SNAK_Pos (27U)
lypinator 0:bb348c97df44 8224 #define USB_OTG_DOEPCTL_SNAK_Msk (0x1U << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */
lypinator 0:bb348c97df44 8225 #define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk /*!< Set NAK */
lypinator 0:bb348c97df44 8226 #define USB_OTG_DOEPCTL_EPDIS_Pos (30U)
lypinator 0:bb348c97df44 8227 #define USB_OTG_DOEPCTL_EPDIS_Msk (0x1U << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */
lypinator 0:bb348c97df44 8228 #define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk /*!< Endpoint disable */
lypinator 0:bb348c97df44 8229 #define USB_OTG_DOEPCTL_EPENA_Pos (31U)
lypinator 0:bb348c97df44 8230 #define USB_OTG_DOEPCTL_EPENA_Msk (0x1U << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */
lypinator 0:bb348c97df44 8231 #define USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_Msk /*!< Endpoint enable */
lypinator 0:bb348c97df44 8232
lypinator 0:bb348c97df44 8233 /******************** Bit definition for USB_OTG_DOEPINT register ********************/
lypinator 0:bb348c97df44 8234 #define USB_OTG_DOEPINT_XFRC_Pos (0U)
lypinator 0:bb348c97df44 8235 #define USB_OTG_DOEPINT_XFRC_Msk (0x1U << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 8236 #define USB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_Msk /*!< Transfer completed interrupt */
lypinator 0:bb348c97df44 8237 #define USB_OTG_DOEPINT_EPDISD_Pos (1U)
lypinator 0:bb348c97df44 8238 #define USB_OTG_DOEPINT_EPDISD_Msk (0x1U << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 8239 #define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
lypinator 0:bb348c97df44 8240 #define USB_OTG_DOEPINT_STUP_Pos (3U)
lypinator 0:bb348c97df44 8241 #define USB_OTG_DOEPINT_STUP_Msk (0x1U << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */
lypinator 0:bb348c97df44 8242 #define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk /*!< SETUP phase done */
lypinator 0:bb348c97df44 8243 #define USB_OTG_DOEPINT_OTEPDIS_Pos (4U)
lypinator 0:bb348c97df44 8244 #define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1U << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 8245 #define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk /*!< OUT token received when endpoint disabled */
lypinator 0:bb348c97df44 8246 #define USB_OTG_DOEPINT_B2BSTUP_Pos (6U)
lypinator 0:bb348c97df44 8247 #define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1U << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */
lypinator 0:bb348c97df44 8248 #define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */
lypinator 0:bb348c97df44 8249 #define USB_OTG_DOEPINT_NYET_Pos (14U)
lypinator 0:bb348c97df44 8250 #define USB_OTG_DOEPINT_NYET_Msk (0x1U << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */
lypinator 0:bb348c97df44 8251 #define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk /*!< NYET interrupt */
lypinator 0:bb348c97df44 8252
lypinator 0:bb348c97df44 8253 /******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/
lypinator 0:bb348c97df44 8254
lypinator 0:bb348c97df44 8255 #define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U)
lypinator 0:bb348c97df44 8256 #define USB_OTG_DOEPTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
lypinator 0:bb348c97df44 8257 #define USB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
lypinator 0:bb348c97df44 8258 #define USB_OTG_DOEPTSIZ_PKTCNT_Pos (19U)
lypinator 0:bb348c97df44 8259 #define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
lypinator 0:bb348c97df44 8260 #define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk /*!< Packet count */
lypinator 0:bb348c97df44 8261
lypinator 0:bb348c97df44 8262 #define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U)
lypinator 0:bb348c97df44 8263 #define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */
lypinator 0:bb348c97df44 8264 #define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk /*!< SETUP packet count */
lypinator 0:bb348c97df44 8265 #define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */
lypinator 0:bb348c97df44 8266 #define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */
lypinator 0:bb348c97df44 8267
lypinator 0:bb348c97df44 8268 /******************** Bit definition for PCGCCTL register ********************/
lypinator 0:bb348c97df44 8269 #define USB_OTG_PCGCCTL_STOPCLK_Pos (0U)
lypinator 0:bb348c97df44 8270 #define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1U << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */
lypinator 0:bb348c97df44 8271 #define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk /*!< SETUP packet count */
lypinator 0:bb348c97df44 8272 #define USB_OTG_PCGCCTL_GATECLK_Pos (1U)
lypinator 0:bb348c97df44 8273 #define USB_OTG_PCGCCTL_GATECLK_Msk (0x1U << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */
lypinator 0:bb348c97df44 8274 #define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk /*!<Bit 0 */
lypinator 0:bb348c97df44 8275 #define USB_OTG_PCGCCTL_PHYSUSP_Pos (4U)
lypinator 0:bb348c97df44 8276 #define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1U << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */
lypinator 0:bb348c97df44 8277 #define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk /*!<Bit 1 */
lypinator 0:bb348c97df44 8278
lypinator 0:bb348c97df44 8279 /**
lypinator 0:bb348c97df44 8280 * @}
lypinator 0:bb348c97df44 8281 */
lypinator 0:bb348c97df44 8282
lypinator 0:bb348c97df44 8283 /**
lypinator 0:bb348c97df44 8284 * @}
lypinator 0:bb348c97df44 8285 */
lypinator 0:bb348c97df44 8286
lypinator 0:bb348c97df44 8287 /** @addtogroup Exported_macros
lypinator 0:bb348c97df44 8288 * @{
lypinator 0:bb348c97df44 8289 */
lypinator 0:bb348c97df44 8290
lypinator 0:bb348c97df44 8291 /******************************* ADC Instances ********************************/
lypinator 0:bb348c97df44 8292 #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
lypinator 0:bb348c97df44 8293
lypinator 0:bb348c97df44 8294 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
lypinator 0:bb348c97df44 8295 /******************************* CRC Instances ********************************/
lypinator 0:bb348c97df44 8296 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
lypinator 0:bb348c97df44 8297
lypinator 0:bb348c97df44 8298
lypinator 0:bb348c97df44 8299 /******************************** DMA Instances *******************************/
lypinator 0:bb348c97df44 8300 #define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
lypinator 0:bb348c97df44 8301 ((INSTANCE) == DMA1_Stream1) || \
lypinator 0:bb348c97df44 8302 ((INSTANCE) == DMA1_Stream2) || \
lypinator 0:bb348c97df44 8303 ((INSTANCE) == DMA1_Stream3) || \
lypinator 0:bb348c97df44 8304 ((INSTANCE) == DMA1_Stream4) || \
lypinator 0:bb348c97df44 8305 ((INSTANCE) == DMA1_Stream5) || \
lypinator 0:bb348c97df44 8306 ((INSTANCE) == DMA1_Stream6) || \
lypinator 0:bb348c97df44 8307 ((INSTANCE) == DMA1_Stream7) || \
lypinator 0:bb348c97df44 8308 ((INSTANCE) == DMA2_Stream0) || \
lypinator 0:bb348c97df44 8309 ((INSTANCE) == DMA2_Stream1) || \
lypinator 0:bb348c97df44 8310 ((INSTANCE) == DMA2_Stream2) || \
lypinator 0:bb348c97df44 8311 ((INSTANCE) == DMA2_Stream3) || \
lypinator 0:bb348c97df44 8312 ((INSTANCE) == DMA2_Stream4) || \
lypinator 0:bb348c97df44 8313 ((INSTANCE) == DMA2_Stream5) || \
lypinator 0:bb348c97df44 8314 ((INSTANCE) == DMA2_Stream6) || \
lypinator 0:bb348c97df44 8315 ((INSTANCE) == DMA2_Stream7))
lypinator 0:bb348c97df44 8316
lypinator 0:bb348c97df44 8317 /******************************* GPIO Instances *******************************/
lypinator 0:bb348c97df44 8318 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
lypinator 0:bb348c97df44 8319 ((INSTANCE) == GPIOB) || \
lypinator 0:bb348c97df44 8320 ((INSTANCE) == GPIOC) || \
lypinator 0:bb348c97df44 8321 ((INSTANCE) == GPIOD) || \
lypinator 0:bb348c97df44 8322 ((INSTANCE) == GPIOE) || \
lypinator 0:bb348c97df44 8323 ((INSTANCE) == GPIOH))
lypinator 0:bb348c97df44 8324
lypinator 0:bb348c97df44 8325 /******************************** I2C Instances *******************************/
lypinator 0:bb348c97df44 8326 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
lypinator 0:bb348c97df44 8327 ((INSTANCE) == I2C2) || \
lypinator 0:bb348c97df44 8328 ((INSTANCE) == I2C3))
lypinator 0:bb348c97df44 8329
lypinator 0:bb348c97df44 8330 /******************************* SMBUS Instances ******************************/
lypinator 0:bb348c97df44 8331 #define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE
lypinator 0:bb348c97df44 8332
lypinator 0:bb348c97df44 8333 /******************************** I2S Instances *******************************/
lypinator 0:bb348c97df44 8334
lypinator 0:bb348c97df44 8335 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
lypinator 0:bb348c97df44 8336 ((INSTANCE) == SPI2) || \
lypinator 0:bb348c97df44 8337 ((INSTANCE) == SPI3) || \
lypinator 0:bb348c97df44 8338 ((INSTANCE) == SPI4) || \
lypinator 0:bb348c97df44 8339 ((INSTANCE) == SPI5))
lypinator 0:bb348c97df44 8340
lypinator 0:bb348c97df44 8341 /*************************** I2S Extended Instances ***************************/
lypinator 0:bb348c97df44 8342 #define IS_I2S_EXT_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2S2ext)|| \
lypinator 0:bb348c97df44 8343 ((INSTANCE) == I2S3ext))
lypinator 0:bb348c97df44 8344 /* Legacy Defines */
lypinator 0:bb348c97df44 8345 #define IS_I2S_ALL_INSTANCE_EXT IS_I2S_EXT_ALL_INSTANCE
lypinator 0:bb348c97df44 8346
lypinator 0:bb348c97df44 8347
lypinator 0:bb348c97df44 8348 /****************************** RTC Instances *********************************/
lypinator 0:bb348c97df44 8349 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
lypinator 0:bb348c97df44 8350
lypinator 0:bb348c97df44 8351
lypinator 0:bb348c97df44 8352 /******************************** SPI Instances *******************************/
lypinator 0:bb348c97df44 8353
lypinator 0:bb348c97df44 8354 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
lypinator 0:bb348c97df44 8355 ((INSTANCE) == SPI2) || \
lypinator 0:bb348c97df44 8356 ((INSTANCE) == SPI3) || \
lypinator 0:bb348c97df44 8357 ((INSTANCE) == SPI4) || \
lypinator 0:bb348c97df44 8358 ((INSTANCE) == SPI5))
lypinator 0:bb348c97df44 8359
lypinator 0:bb348c97df44 8360
lypinator 0:bb348c97df44 8361 /****************** TIM Instances : All supported instances *******************/
lypinator 0:bb348c97df44 8362 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
lypinator 0:bb348c97df44 8363 ((INSTANCE) == TIM2) || \
lypinator 0:bb348c97df44 8364 ((INSTANCE) == TIM3) || \
lypinator 0:bb348c97df44 8365 ((INSTANCE) == TIM4) || \
lypinator 0:bb348c97df44 8366 ((INSTANCE) == TIM5) || \
lypinator 0:bb348c97df44 8367 ((INSTANCE) == TIM9) || \
lypinator 0:bb348c97df44 8368 ((INSTANCE) == TIM10) || \
lypinator 0:bb348c97df44 8369 ((INSTANCE) == TIM11))
lypinator 0:bb348c97df44 8370
lypinator 0:bb348c97df44 8371 /************* TIM Instances : at least 1 capture/compare channel *************/
lypinator 0:bb348c97df44 8372 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
lypinator 0:bb348c97df44 8373 ((INSTANCE) == TIM2) || \
lypinator 0:bb348c97df44 8374 ((INSTANCE) == TIM3) || \
lypinator 0:bb348c97df44 8375 ((INSTANCE) == TIM4) || \
lypinator 0:bb348c97df44 8376 ((INSTANCE) == TIM5) || \
lypinator 0:bb348c97df44 8377 ((INSTANCE) == TIM9) || \
lypinator 0:bb348c97df44 8378 ((INSTANCE) == TIM10) || \
lypinator 0:bb348c97df44 8379 ((INSTANCE) == TIM11))
lypinator 0:bb348c97df44 8380
lypinator 0:bb348c97df44 8381 /************ TIM Instances : at least 2 capture/compare channels *************/
lypinator 0:bb348c97df44 8382 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
lypinator 0:bb348c97df44 8383 ((INSTANCE) == TIM2) || \
lypinator 0:bb348c97df44 8384 ((INSTANCE) == TIM3) || \
lypinator 0:bb348c97df44 8385 ((INSTANCE) == TIM4) || \
lypinator 0:bb348c97df44 8386 ((INSTANCE) == TIM5) || \
lypinator 0:bb348c97df44 8387 ((INSTANCE) == TIM9))
lypinator 0:bb348c97df44 8388
lypinator 0:bb348c97df44 8389 /************ TIM Instances : at least 3 capture/compare channels *************/
lypinator 0:bb348c97df44 8390 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
lypinator 0:bb348c97df44 8391 ((INSTANCE) == TIM2) || \
lypinator 0:bb348c97df44 8392 ((INSTANCE) == TIM3) || \
lypinator 0:bb348c97df44 8393 ((INSTANCE) == TIM4) || \
lypinator 0:bb348c97df44 8394 ((INSTANCE) == TIM5))
lypinator 0:bb348c97df44 8395
lypinator 0:bb348c97df44 8396 /************ TIM Instances : at least 4 capture/compare channels *************/
lypinator 0:bb348c97df44 8397 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
lypinator 0:bb348c97df44 8398 ((INSTANCE) == TIM2) || \
lypinator 0:bb348c97df44 8399 ((INSTANCE) == TIM3) || \
lypinator 0:bb348c97df44 8400 ((INSTANCE) == TIM4) || \
lypinator 0:bb348c97df44 8401 ((INSTANCE) == TIM5))
lypinator 0:bb348c97df44 8402
lypinator 0:bb348c97df44 8403 /******************** TIM Instances : Advanced-control timers *****************/
lypinator 0:bb348c97df44 8404 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
lypinator 0:bb348c97df44 8405
lypinator 0:bb348c97df44 8406 /******************* TIM Instances : Timer input XOR function *****************/
lypinator 0:bb348c97df44 8407 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
lypinator 0:bb348c97df44 8408 ((INSTANCE) == TIM2) || \
lypinator 0:bb348c97df44 8409 ((INSTANCE) == TIM3) || \
lypinator 0:bb348c97df44 8410 ((INSTANCE) == TIM4) || \
lypinator 0:bb348c97df44 8411 ((INSTANCE) == TIM5))
lypinator 0:bb348c97df44 8412
lypinator 0:bb348c97df44 8413 /****************** TIM Instances : DMA requests generation (UDE) *************/
lypinator 0:bb348c97df44 8414 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
lypinator 0:bb348c97df44 8415 ((INSTANCE) == TIM2) || \
lypinator 0:bb348c97df44 8416 ((INSTANCE) == TIM3) || \
lypinator 0:bb348c97df44 8417 ((INSTANCE) == TIM4) || \
lypinator 0:bb348c97df44 8418 ((INSTANCE) == TIM5))
lypinator 0:bb348c97df44 8419
lypinator 0:bb348c97df44 8420 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
lypinator 0:bb348c97df44 8421 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
lypinator 0:bb348c97df44 8422 ((INSTANCE) == TIM2) || \
lypinator 0:bb348c97df44 8423 ((INSTANCE) == TIM3) || \
lypinator 0:bb348c97df44 8424 ((INSTANCE) == TIM4) || \
lypinator 0:bb348c97df44 8425 ((INSTANCE) == TIM5))
lypinator 0:bb348c97df44 8426
lypinator 0:bb348c97df44 8427 /************ TIM Instances : DMA requests generation (COMDE) *****************/
lypinator 0:bb348c97df44 8428 #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
lypinator 0:bb348c97df44 8429 ((INSTANCE) == TIM2) || \
lypinator 0:bb348c97df44 8430 ((INSTANCE) == TIM3) || \
lypinator 0:bb348c97df44 8431 ((INSTANCE) == TIM4) || \
lypinator 0:bb348c97df44 8432 ((INSTANCE) == TIM5))
lypinator 0:bb348c97df44 8433
lypinator 0:bb348c97df44 8434 /******************** TIM Instances : DMA burst feature ***********************/
lypinator 0:bb348c97df44 8435 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
lypinator 0:bb348c97df44 8436 ((INSTANCE) == TIM2) || \
lypinator 0:bb348c97df44 8437 ((INSTANCE) == TIM3) || \
lypinator 0:bb348c97df44 8438 ((INSTANCE) == TIM4) || \
lypinator 0:bb348c97df44 8439 ((INSTANCE) == TIM5))
lypinator 0:bb348c97df44 8440
lypinator 0:bb348c97df44 8441 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
lypinator 0:bb348c97df44 8442 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
lypinator 0:bb348c97df44 8443 ((INSTANCE) == TIM2) || \
lypinator 0:bb348c97df44 8444 ((INSTANCE) == TIM3) || \
lypinator 0:bb348c97df44 8445 ((INSTANCE) == TIM4) || \
lypinator 0:bb348c97df44 8446 ((INSTANCE) == TIM5))
lypinator 0:bb348c97df44 8447
lypinator 0:bb348c97df44 8448 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
lypinator 0:bb348c97df44 8449 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
lypinator 0:bb348c97df44 8450 ((INSTANCE) == TIM2) || \
lypinator 0:bb348c97df44 8451 ((INSTANCE) == TIM3) || \
lypinator 0:bb348c97df44 8452 ((INSTANCE) == TIM4) || \
lypinator 0:bb348c97df44 8453 ((INSTANCE) == TIM5) || \
lypinator 0:bb348c97df44 8454 ((INSTANCE) == TIM9))
lypinator 0:bb348c97df44 8455
lypinator 0:bb348c97df44 8456 /********************** TIM Instances : 32 bit Counter ************************/
lypinator 0:bb348c97df44 8457 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
lypinator 0:bb348c97df44 8458 ((INSTANCE) == TIM5))
lypinator 0:bb348c97df44 8459
lypinator 0:bb348c97df44 8460 /***************** TIM Instances : external trigger input availabe ************/
lypinator 0:bb348c97df44 8461 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
lypinator 0:bb348c97df44 8462 ((INSTANCE) == TIM2) || \
lypinator 0:bb348c97df44 8463 ((INSTANCE) == TIM3) || \
lypinator 0:bb348c97df44 8464 ((INSTANCE) == TIM4) || \
lypinator 0:bb348c97df44 8465 ((INSTANCE) == TIM5))
lypinator 0:bb348c97df44 8466
lypinator 0:bb348c97df44 8467 /****************** TIM Instances : remapping capability **********************/
lypinator 0:bb348c97df44 8468 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
lypinator 0:bb348c97df44 8469 ((INSTANCE) == TIM5) || \
lypinator 0:bb348c97df44 8470 ((INSTANCE) == TIM11))
lypinator 0:bb348c97df44 8471
lypinator 0:bb348c97df44 8472 /******************* TIM Instances : output(s) available **********************/
lypinator 0:bb348c97df44 8473 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
lypinator 0:bb348c97df44 8474 ((((INSTANCE) == TIM1) && \
lypinator 0:bb348c97df44 8475 (((CHANNEL) == TIM_CHANNEL_1) || \
lypinator 0:bb348c97df44 8476 ((CHANNEL) == TIM_CHANNEL_2) || \
lypinator 0:bb348c97df44 8477 ((CHANNEL) == TIM_CHANNEL_3) || \
lypinator 0:bb348c97df44 8478 ((CHANNEL) == TIM_CHANNEL_4))) \
lypinator 0:bb348c97df44 8479 || \
lypinator 0:bb348c97df44 8480 (((INSTANCE) == TIM2) && \
lypinator 0:bb348c97df44 8481 (((CHANNEL) == TIM_CHANNEL_1) || \
lypinator 0:bb348c97df44 8482 ((CHANNEL) == TIM_CHANNEL_2) || \
lypinator 0:bb348c97df44 8483 ((CHANNEL) == TIM_CHANNEL_3) || \
lypinator 0:bb348c97df44 8484 ((CHANNEL) == TIM_CHANNEL_4))) \
lypinator 0:bb348c97df44 8485 || \
lypinator 0:bb348c97df44 8486 (((INSTANCE) == TIM3) && \
lypinator 0:bb348c97df44 8487 (((CHANNEL) == TIM_CHANNEL_1) || \
lypinator 0:bb348c97df44 8488 ((CHANNEL) == TIM_CHANNEL_2) || \
lypinator 0:bb348c97df44 8489 ((CHANNEL) == TIM_CHANNEL_3) || \
lypinator 0:bb348c97df44 8490 ((CHANNEL) == TIM_CHANNEL_4))) \
lypinator 0:bb348c97df44 8491 || \
lypinator 0:bb348c97df44 8492 (((INSTANCE) == TIM4) && \
lypinator 0:bb348c97df44 8493 (((CHANNEL) == TIM_CHANNEL_1) || \
lypinator 0:bb348c97df44 8494 ((CHANNEL) == TIM_CHANNEL_2) || \
lypinator 0:bb348c97df44 8495 ((CHANNEL) == TIM_CHANNEL_3) || \
lypinator 0:bb348c97df44 8496 ((CHANNEL) == TIM_CHANNEL_4))) \
lypinator 0:bb348c97df44 8497 || \
lypinator 0:bb348c97df44 8498 (((INSTANCE) == TIM5) && \
lypinator 0:bb348c97df44 8499 (((CHANNEL) == TIM_CHANNEL_1) || \
lypinator 0:bb348c97df44 8500 ((CHANNEL) == TIM_CHANNEL_2) || \
lypinator 0:bb348c97df44 8501 ((CHANNEL) == TIM_CHANNEL_3) || \
lypinator 0:bb348c97df44 8502 ((CHANNEL) == TIM_CHANNEL_4))) \
lypinator 0:bb348c97df44 8503 || \
lypinator 0:bb348c97df44 8504 (((INSTANCE) == TIM9) && \
lypinator 0:bb348c97df44 8505 (((CHANNEL) == TIM_CHANNEL_1) || \
lypinator 0:bb348c97df44 8506 ((CHANNEL) == TIM_CHANNEL_2))) \
lypinator 0:bb348c97df44 8507 || \
lypinator 0:bb348c97df44 8508 (((INSTANCE) == TIM10) && \
lypinator 0:bb348c97df44 8509 (((CHANNEL) == TIM_CHANNEL_1))) \
lypinator 0:bb348c97df44 8510 || \
lypinator 0:bb348c97df44 8511 (((INSTANCE) == TIM11) && \
lypinator 0:bb348c97df44 8512 (((CHANNEL) == TIM_CHANNEL_1))))
lypinator 0:bb348c97df44 8513
lypinator 0:bb348c97df44 8514 /************ TIM Instances : complementary output(s) available ***************/
lypinator 0:bb348c97df44 8515 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
lypinator 0:bb348c97df44 8516 ((((INSTANCE) == TIM1) && \
lypinator 0:bb348c97df44 8517 (((CHANNEL) == TIM_CHANNEL_1) || \
lypinator 0:bb348c97df44 8518 ((CHANNEL) == TIM_CHANNEL_2) || \
lypinator 0:bb348c97df44 8519 ((CHANNEL) == TIM_CHANNEL_3))))
lypinator 0:bb348c97df44 8520
lypinator 0:bb348c97df44 8521 /****************** TIM Instances : supporting counting mode selection ********/
lypinator 0:bb348c97df44 8522 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
lypinator 0:bb348c97df44 8523 ((INSTANCE) == TIM2) || \
lypinator 0:bb348c97df44 8524 ((INSTANCE) == TIM3) || \
lypinator 0:bb348c97df44 8525 ((INSTANCE) == TIM4) || \
lypinator 0:bb348c97df44 8526 ((INSTANCE) == TIM5))
lypinator 0:bb348c97df44 8527
lypinator 0:bb348c97df44 8528 /****************** TIM Instances : supporting clock division *****************/
lypinator 0:bb348c97df44 8529 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
lypinator 0:bb348c97df44 8530 ((INSTANCE) == TIM2) || \
lypinator 0:bb348c97df44 8531 ((INSTANCE) == TIM3) || \
lypinator 0:bb348c97df44 8532 ((INSTANCE) == TIM4) || \
lypinator 0:bb348c97df44 8533 ((INSTANCE) == TIM5) || \
lypinator 0:bb348c97df44 8534 ((INSTANCE) == TIM9) || \
lypinator 0:bb348c97df44 8535 ((INSTANCE) == TIM10) || \
lypinator 0:bb348c97df44 8536 ((INSTANCE) == TIM11))
lypinator 0:bb348c97df44 8537
lypinator 0:bb348c97df44 8538 /****************** TIM Instances : supporting commutation event generation ***/
lypinator 0:bb348c97df44 8539
lypinator 0:bb348c97df44 8540 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
lypinator 0:bb348c97df44 8541
lypinator 0:bb348c97df44 8542 /****************** TIM Instances : supporting OCxREF clear *******************/
lypinator 0:bb348c97df44 8543 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
lypinator 0:bb348c97df44 8544 ((INSTANCE) == TIM2) || \
lypinator 0:bb348c97df44 8545 ((INSTANCE) == TIM3) || \
lypinator 0:bb348c97df44 8546 ((INSTANCE) == TIM4) || \
lypinator 0:bb348c97df44 8547 ((INSTANCE) == TIM5))
lypinator 0:bb348c97df44 8548
lypinator 0:bb348c97df44 8549 /****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
lypinator 0:bb348c97df44 8550 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
lypinator 0:bb348c97df44 8551 ((INSTANCE) == TIM2) || \
lypinator 0:bb348c97df44 8552 ((INSTANCE) == TIM3) || \
lypinator 0:bb348c97df44 8553 ((INSTANCE) == TIM4) || \
lypinator 0:bb348c97df44 8554 ((INSTANCE) == TIM5) || \
lypinator 0:bb348c97df44 8555 ((INSTANCE) == TIM9))
lypinator 0:bb348c97df44 8556
lypinator 0:bb348c97df44 8557 /****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
lypinator 0:bb348c97df44 8558 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)|| \
lypinator 0:bb348c97df44 8559 ((INSTANCE) == TIM2) || \
lypinator 0:bb348c97df44 8560 ((INSTANCE) == TIM3) || \
lypinator 0:bb348c97df44 8561 ((INSTANCE) == TIM4) || \
lypinator 0:bb348c97df44 8562 ((INSTANCE) == TIM5))
lypinator 0:bb348c97df44 8563
lypinator 0:bb348c97df44 8564 /****************** TIM Instances : supporting repetition counter *************/
lypinator 0:bb348c97df44 8565 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1))
lypinator 0:bb348c97df44 8566
lypinator 0:bb348c97df44 8567 /****************** TIM Instances : supporting encoder interface **************/
lypinator 0:bb348c97df44 8568 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
lypinator 0:bb348c97df44 8569 ((INSTANCE) == TIM2) || \
lypinator 0:bb348c97df44 8570 ((INSTANCE) == TIM3) || \
lypinator 0:bb348c97df44 8571 ((INSTANCE) == TIM4) || \
lypinator 0:bb348c97df44 8572 ((INSTANCE) == TIM5) || \
lypinator 0:bb348c97df44 8573 ((INSTANCE) == TIM9))
lypinator 0:bb348c97df44 8574 /****************** TIM Instances : supporting Hall sensor interface **********/
lypinator 0:bb348c97df44 8575 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
lypinator 0:bb348c97df44 8576 ((INSTANCE) == TIM2) || \
lypinator 0:bb348c97df44 8577 ((INSTANCE) == TIM3) || \
lypinator 0:bb348c97df44 8578 ((INSTANCE) == TIM4) || \
lypinator 0:bb348c97df44 8579 ((INSTANCE) == TIM5))
lypinator 0:bb348c97df44 8580 /****************** TIM Instances : supporting the break function *************/
lypinator 0:bb348c97df44 8581 #define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1))
lypinator 0:bb348c97df44 8582
lypinator 0:bb348c97df44 8583 /******************** USART Instances : Synchronous mode **********************/
lypinator 0:bb348c97df44 8584 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
lypinator 0:bb348c97df44 8585 ((INSTANCE) == USART2) || \
lypinator 0:bb348c97df44 8586 ((INSTANCE) == USART6))
lypinator 0:bb348c97df44 8587
lypinator 0:bb348c97df44 8588 /******************** UART Instances : Half-Duplex mode **********************/
lypinator 0:bb348c97df44 8589 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
lypinator 0:bb348c97df44 8590 ((INSTANCE) == USART2) || \
lypinator 0:bb348c97df44 8591 ((INSTANCE) == USART6))
lypinator 0:bb348c97df44 8592
lypinator 0:bb348c97df44 8593 /* Legacy defines */
lypinator 0:bb348c97df44 8594 #define IS_UART_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
lypinator 0:bb348c97df44 8595
lypinator 0:bb348c97df44 8596 /****************** UART Instances : Hardware Flow control ********************/
lypinator 0:bb348c97df44 8597 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
lypinator 0:bb348c97df44 8598 ((INSTANCE) == USART2) || \
lypinator 0:bb348c97df44 8599 ((INSTANCE) == USART6))
lypinator 0:bb348c97df44 8600 /******************** UART Instances : LIN mode **********************/
lypinator 0:bb348c97df44 8601 #define IS_UART_LIN_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
lypinator 0:bb348c97df44 8602
lypinator 0:bb348c97df44 8603 /********************* UART Instances : Smart card mode ***********************/
lypinator 0:bb348c97df44 8604 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
lypinator 0:bb348c97df44 8605 ((INSTANCE) == USART2) || \
lypinator 0:bb348c97df44 8606 ((INSTANCE) == USART6))
lypinator 0:bb348c97df44 8607
lypinator 0:bb348c97df44 8608 /*********************** UART Instances : IRDA mode ***************************/
lypinator 0:bb348c97df44 8609 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
lypinator 0:bb348c97df44 8610 ((INSTANCE) == USART2) || \
lypinator 0:bb348c97df44 8611 ((INSTANCE) == USART6))
lypinator 0:bb348c97df44 8612
lypinator 0:bb348c97df44 8613 /*********************** PCD Instances ****************************************/
lypinator 0:bb348c97df44 8614 #define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))
lypinator 0:bb348c97df44 8615
lypinator 0:bb348c97df44 8616 /*********************** HCD Instances ****************************************/
lypinator 0:bb348c97df44 8617 #define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))
lypinator 0:bb348c97df44 8618
lypinator 0:bb348c97df44 8619 /****************************** SDIO Instances ********************************/
lypinator 0:bb348c97df44 8620 #define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
lypinator 0:bb348c97df44 8621
lypinator 0:bb348c97df44 8622 /****************************** IWDG Instances ********************************/
lypinator 0:bb348c97df44 8623 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
lypinator 0:bb348c97df44 8624
lypinator 0:bb348c97df44 8625 /****************************** WWDG Instances ********************************/
lypinator 0:bb348c97df44 8626 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
lypinator 0:bb348c97df44 8627
lypinator 0:bb348c97df44 8628 /****************************** USB Exported Constants ************************/
lypinator 0:bb348c97df44 8629 #define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 8U
lypinator 0:bb348c97df44 8630 #define USB_OTG_FS_MAX_IN_ENDPOINTS 4U /* Including EP0 */
lypinator 0:bb348c97df44 8631 #define USB_OTG_FS_MAX_OUT_ENDPOINTS 4U /* Including EP0 */
lypinator 0:bb348c97df44 8632 #define USB_OTG_FS_TOTAL_FIFO_SIZE 1280U /* in Bytes */
lypinator 0:bb348c97df44 8633
lypinator 0:bb348c97df44 8634 /*
lypinator 0:bb348c97df44 8635 * @brief Specific devices reset values definitions
lypinator 0:bb348c97df44 8636 */
lypinator 0:bb348c97df44 8637 #define RCC_PLLCFGR_RST_VALUE 0x24003010U
lypinator 0:bb348c97df44 8638 #define RCC_PLLI2SCFGR_RST_VALUE 0x20003010U
lypinator 0:bb348c97df44 8639
lypinator 0:bb348c97df44 8640 #define RCC_MAX_FREQUENCY 100000000U /*!< Max frequency of family in Hz*/
lypinator 0:bb348c97df44 8641 #define RCC_MAX_FREQUENCY_SCALE1 RCC_MAX_FREQUENCY /*!< Maximum frequency for system clock at power scale1, in Hz */
lypinator 0:bb348c97df44 8642 #define RCC_MAX_FREQUENCY_SCALE2 84000000U /*!< Maximum frequency for system clock at power scale2, in Hz */
lypinator 0:bb348c97df44 8643 #define RCC_MAX_FREQUENCY_SCALE3 64000000U /*!< Maximum frequency for system clock at power scale3, in Hz */
lypinator 0:bb348c97df44 8644 #define RCC_PLLVCO_OUTPUT_MIN 100000000U /*!< Frequency min for PLLVCO output, in Hz */
lypinator 0:bb348c97df44 8645 #define RCC_PLLVCO_INPUT_MIN 950000U /*!< Frequency min for PLLVCO input, in Hz */
lypinator 0:bb348c97df44 8646 #define RCC_PLLVCO_INPUT_MAX 2100000U /*!< Frequency max for PLLVCO input, in Hz */
lypinator 0:bb348c97df44 8647 #define RCC_PLLVCO_OUTPUT_MAX 432000000U /*!< Frequency max for PLLVCO output, in Hz */
lypinator 0:bb348c97df44 8648
lypinator 0:bb348c97df44 8649 #define RCC_PLLN_MIN_VALUE 50U
lypinator 0:bb348c97df44 8650 #define RCC_PLLN_MAX_VALUE 432U
lypinator 0:bb348c97df44 8651
lypinator 0:bb348c97df44 8652 #define FLASH_SCALE1_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */
lypinator 0:bb348c97df44 8653 #define FLASH_SCALE1_LATENCY2_FREQ 64000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */
lypinator 0:bb348c97df44 8654 #define FLASH_SCALE1_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 1 */
lypinator 0:bb348c97df44 8655
lypinator 0:bb348c97df44 8656 #define FLASH_SCALE2_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */
lypinator 0:bb348c97df44 8657 #define FLASH_SCALE2_LATENCY2_FREQ 64000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */
lypinator 0:bb348c97df44 8658
lypinator 0:bb348c97df44 8659 #define FLASH_SCALE3_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 3 */
lypinator 0:bb348c97df44 8660 #define FLASH_SCALE3_LATENCY2_FREQ 64000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 3 */
lypinator 0:bb348c97df44 8661
lypinator 0:bb348c97df44 8662
lypinator 0:bb348c97df44 8663 /**
lypinator 0:bb348c97df44 8664 * @}
lypinator 0:bb348c97df44 8665 */
lypinator 0:bb348c97df44 8666
lypinator 0:bb348c97df44 8667 /**
lypinator 0:bb348c97df44 8668 * @}
lypinator 0:bb348c97df44 8669 */
lypinator 0:bb348c97df44 8670
lypinator 0:bb348c97df44 8671 /**
lypinator 0:bb348c97df44 8672 * @}
lypinator 0:bb348c97df44 8673 */
lypinator 0:bb348c97df44 8674
lypinator 0:bb348c97df44 8675 #ifdef __cplusplus
lypinator 0:bb348c97df44 8676 }
lypinator 0:bb348c97df44 8677 #endif /* __cplusplus */
lypinator 0:bb348c97df44 8678
lypinator 0:bb348c97df44 8679 #endif /* __STM32F411xE_H */
lypinator 0:bb348c97df44 8680
lypinator 0:bb348c97df44 8681
lypinator 0:bb348c97df44 8682
lypinator 0:bb348c97df44 8683 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/