Thomas Lyp / DevLibMemoryController

Initial commit

Dependencies:   FastPWM

mbed-dev-master/cmsis/TARGET_CORTEX_M/mpu_armv8.h@0:bb348c97df44, 2020-09-16 (annotated)

Committer:
lypinator
Date:
Wed Sep 16 01:11:49 2020 +0000
Revision:
0:bb348c97df44
Added PWM

Who changed what in which revision?

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lypinator 0:bb348c97df44 1 /******************************************************************************
lypinator 0:bb348c97df44 2 * @file mpu_armv8.h
lypinator 0:bb348c97df44 3 * @brief CMSIS MPU API for Armv8-M MPU
lypinator 0:bb348c97df44 4 * @version V5.0.4
lypinator 0:bb348c97df44 5 * @date 10. January 2018
lypinator 0:bb348c97df44 6 ******************************************************************************/
lypinator 0:bb348c97df44 7 /*
lypinator 0:bb348c97df44 8 * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
lypinator 0:bb348c97df44 9 *
lypinator 0:bb348c97df44 10 * SPDX-License-Identifier: Apache-2.0
lypinator 0:bb348c97df44 11 *
lypinator 0:bb348c97df44 12 * Licensed under the Apache License, Version 2.0 (the License); you may
lypinator 0:bb348c97df44 13 * not use this file except in compliance with the License.
lypinator 0:bb348c97df44 14 * You may obtain a copy of the License at
lypinator 0:bb348c97df44 15 *
lypinator 0:bb348c97df44 16 * www.apache.org/licenses/LICENSE-2.0
lypinator 0:bb348c97df44 17 *
lypinator 0:bb348c97df44 18 * Unless required by applicable law or agreed to in writing, software
lypinator 0:bb348c97df44 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
lypinator 0:bb348c97df44 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
lypinator 0:bb348c97df44 21 * See the License for the specific language governing permissions and
lypinator 0:bb348c97df44 22 * limitations under the License.
lypinator 0:bb348c97df44 23 */
lypinator 0:bb348c97df44 24
lypinator 0:bb348c97df44 25 #if defined ( __ICCARM__ )
lypinator 0:bb348c97df44 26 #pragma system_include /* treat file as system include file for MISRA check */
lypinator 0:bb348c97df44 27 #elif defined (__clang__)
lypinator 0:bb348c97df44 28 #pragma clang system_header /* treat file as system include file */
lypinator 0:bb348c97df44 29 #endif
lypinator 0:bb348c97df44 30
lypinator 0:bb348c97df44 31 #ifndef ARM_MPU_ARMV8_H
lypinator 0:bb348c97df44 32 #define ARM_MPU_ARMV8_H
lypinator 0:bb348c97df44 33
lypinator 0:bb348c97df44 34 /** \brief Attribute for device memory (outer only) */
lypinator 0:bb348c97df44 35 #define ARM_MPU_ATTR_DEVICE ( 0U )
lypinator 0:bb348c97df44 36
lypinator 0:bb348c97df44 37 /** \brief Attribute for non-cacheable, normal memory */
lypinator 0:bb348c97df44 38 #define ARM_MPU_ATTR_NON_CACHEABLE ( 4U )
lypinator 0:bb348c97df44 39
lypinator 0:bb348c97df44 40 /** \brief Attribute for normal memory (outer and inner)
lypinator 0:bb348c97df44 41 * \param NT Non-Transient: Set to 1 for non-transient data.
lypinator 0:bb348c97df44 42 * \param WB Write-Back: Set to 1 to use write-back update policy.
lypinator 0:bb348c97df44 43 * \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
lypinator 0:bb348c97df44 44 * \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
lypinator 0:bb348c97df44 45 */
lypinator 0:bb348c97df44 46 #define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
lypinator 0:bb348c97df44 47 (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U))
lypinator 0:bb348c97df44 48
lypinator 0:bb348c97df44 49 /** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
lypinator 0:bb348c97df44 50 #define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
lypinator 0:bb348c97df44 51
lypinator 0:bb348c97df44 52 /** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
lypinator 0:bb348c97df44 53 #define ARM_MPU_ATTR_DEVICE_nGnRE (1U)
lypinator 0:bb348c97df44 54
lypinator 0:bb348c97df44 55 /** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
lypinator 0:bb348c97df44 56 #define ARM_MPU_ATTR_DEVICE_nGRE (2U)
lypinator 0:bb348c97df44 57
lypinator 0:bb348c97df44 58 /** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
lypinator 0:bb348c97df44 59 #define ARM_MPU_ATTR_DEVICE_GRE (3U)
lypinator 0:bb348c97df44 60
lypinator 0:bb348c97df44 61 /** \brief Memory Attribute
lypinator 0:bb348c97df44 62 * \param O Outer memory attributes
lypinator 0:bb348c97df44 63 * \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
lypinator 0:bb348c97df44 64 */
lypinator 0:bb348c97df44 65 #define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U)))
lypinator 0:bb348c97df44 66
lypinator 0:bb348c97df44 67 /** \brief Normal memory non-shareable */
lypinator 0:bb348c97df44 68 #define ARM_MPU_SH_NON (0U)
lypinator 0:bb348c97df44 69
lypinator 0:bb348c97df44 70 /** \brief Normal memory outer shareable */
lypinator 0:bb348c97df44 71 #define ARM_MPU_SH_OUTER (2U)
lypinator 0:bb348c97df44 72
lypinator 0:bb348c97df44 73 /** \brief Normal memory inner shareable */
lypinator 0:bb348c97df44 74 #define ARM_MPU_SH_INNER (3U)
lypinator 0:bb348c97df44 75
lypinator 0:bb348c97df44 76 /** \brief Memory access permissions
lypinator 0:bb348c97df44 77 * \param RO Read-Only: Set to 1 for read-only memory.
lypinator 0:bb348c97df44 78 * \param NP Non-Privileged: Set to 1 for non-privileged memory.
lypinator 0:bb348c97df44 79 */
lypinator 0:bb348c97df44 80 #define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U))
lypinator 0:bb348c97df44 81
lypinator 0:bb348c97df44 82 /** \brief Region Base Address Register value
lypinator 0:bb348c97df44 83 * \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
lypinator 0:bb348c97df44 84 * \param SH Defines the Shareability domain for this memory region.
lypinator 0:bb348c97df44 85 * \param RO Read-Only: Set to 1 for a read-only memory region.
lypinator 0:bb348c97df44 86 * \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
lypinator 0:bb348c97df44 87 * \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
lypinator 0:bb348c97df44 88 */
lypinator 0:bb348c97df44 89 #define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
lypinator 0:bb348c97df44 90 ((BASE & MPU_RBAR_BASE_Pos) | \
lypinator 0:bb348c97df44 91 ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
lypinator 0:bb348c97df44 92 ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
lypinator 0:bb348c97df44 93 ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
lypinator 0:bb348c97df44 94
lypinator 0:bb348c97df44 95 /** \brief Region Limit Address Register value
lypinator 0:bb348c97df44 96 * \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
lypinator 0:bb348c97df44 97 * \param IDX The attribute index to be associated with this memory region.
lypinator 0:bb348c97df44 98 */
lypinator 0:bb348c97df44 99 #define ARM_MPU_RLAR(LIMIT, IDX) \
lypinator 0:bb348c97df44 100 ((LIMIT & MPU_RLAR_LIMIT_Msk) | \
lypinator 0:bb348c97df44 101 ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
lypinator 0:bb348c97df44 102 (MPU_RLAR_EN_Msk))
lypinator 0:bb348c97df44 103
lypinator 0:bb348c97df44 104 /**
lypinator 0:bb348c97df44 105 * Struct for a single MPU Region
lypinator 0:bb348c97df44 106 */
lypinator 0:bb348c97df44 107 typedef struct {
lypinator 0:bb348c97df44 108 uint32_t RBAR; /*!< Region Base Address Register value */
lypinator 0:bb348c97df44 109 uint32_t RLAR; /*!< Region Limit Address Register value */
lypinator 0:bb348c97df44 110 } ARM_MPU_Region_t;
lypinator 0:bb348c97df44 111
lypinator 0:bb348c97df44 112 /** Enable the MPU.
lypinator 0:bb348c97df44 113 * \param MPU_Control Default access permissions for unconfigured regions.
lypinator 0:bb348c97df44 114 */
lypinator 0:bb348c97df44 115 __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
lypinator 0:bb348c97df44 116 {
lypinator 0:bb348c97df44 117 __DSB();
lypinator 0:bb348c97df44 118 __ISB();
lypinator 0:bb348c97df44 119 MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
lypinator 0:bb348c97df44 120 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
lypinator 0:bb348c97df44 121 SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
lypinator 0:bb348c97df44 122 #endif
lypinator 0:bb348c97df44 123 }
lypinator 0:bb348c97df44 124
lypinator 0:bb348c97df44 125 /** Disable the MPU.
lypinator 0:bb348c97df44 126 */
lypinator 0:bb348c97df44 127 __STATIC_INLINE void ARM_MPU_Disable(void)
lypinator 0:bb348c97df44 128 {
lypinator 0:bb348c97df44 129 __DSB();
lypinator 0:bb348c97df44 130 __ISB();
lypinator 0:bb348c97df44 131 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
lypinator 0:bb348c97df44 132 SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
lypinator 0:bb348c97df44 133 #endif
lypinator 0:bb348c97df44 134 MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
lypinator 0:bb348c97df44 135 }
lypinator 0:bb348c97df44 136
lypinator 0:bb348c97df44 137 #ifdef MPU_NS
lypinator 0:bb348c97df44 138 /** Enable the Non-secure MPU.
lypinator 0:bb348c97df44 139 * \param MPU_Control Default access permissions for unconfigured regions.
lypinator 0:bb348c97df44 140 */
lypinator 0:bb348c97df44 141 __STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
lypinator 0:bb348c97df44 142 {
lypinator 0:bb348c97df44 143 __DSB();
lypinator 0:bb348c97df44 144 __ISB();
lypinator 0:bb348c97df44 145 MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
lypinator 0:bb348c97df44 146 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
lypinator 0:bb348c97df44 147 SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
lypinator 0:bb348c97df44 148 #endif
lypinator 0:bb348c97df44 149 }
lypinator 0:bb348c97df44 150
lypinator 0:bb348c97df44 151 /** Disable the Non-secure MPU.
lypinator 0:bb348c97df44 152 */
lypinator 0:bb348c97df44 153 __STATIC_INLINE void ARM_MPU_Disable_NS(void)
lypinator 0:bb348c97df44 154 {
lypinator 0:bb348c97df44 155 __DSB();
lypinator 0:bb348c97df44 156 __ISB();
lypinator 0:bb348c97df44 157 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
lypinator 0:bb348c97df44 158 SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
lypinator 0:bb348c97df44 159 #endif
lypinator 0:bb348c97df44 160 MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk;
lypinator 0:bb348c97df44 161 }
lypinator 0:bb348c97df44 162 #endif
lypinator 0:bb348c97df44 163
lypinator 0:bb348c97df44 164 /** Set the memory attribute encoding to the given MPU.
lypinator 0:bb348c97df44 165 * \param mpu Pointer to the MPU to be configured.
lypinator 0:bb348c97df44 166 * \param idx The attribute index to be set [0-7]
lypinator 0:bb348c97df44 167 * \param attr The attribute value to be set.
lypinator 0:bb348c97df44 168 */
lypinator 0:bb348c97df44 169 __STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
lypinator 0:bb348c97df44 170 {
lypinator 0:bb348c97df44 171 const uint8_t reg = idx / 4U;
lypinator 0:bb348c97df44 172 const uint32_t pos = ((idx % 4U) * 8U);
lypinator 0:bb348c97df44 173 const uint32_t mask = 0xFFU << pos;
lypinator 0:bb348c97df44 174
lypinator 0:bb348c97df44 175 if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
lypinator 0:bb348c97df44 176 return; // invalid index
lypinator 0:bb348c97df44 177 }
lypinator 0:bb348c97df44 178
lypinator 0:bb348c97df44 179 mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
lypinator 0:bb348c97df44 180 }
lypinator 0:bb348c97df44 181
lypinator 0:bb348c97df44 182 /** Set the memory attribute encoding.
lypinator 0:bb348c97df44 183 * \param idx The attribute index to be set [0-7]
lypinator 0:bb348c97df44 184 * \param attr The attribute value to be set.
lypinator 0:bb348c97df44 185 */
lypinator 0:bb348c97df44 186 __STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
lypinator 0:bb348c97df44 187 {
lypinator 0:bb348c97df44 188 ARM_MPU_SetMemAttrEx(MPU, idx, attr);
lypinator 0:bb348c97df44 189 }
lypinator 0:bb348c97df44 190
lypinator 0:bb348c97df44 191 #ifdef MPU_NS
lypinator 0:bb348c97df44 192 /** Set the memory attribute encoding to the Non-secure MPU.
lypinator 0:bb348c97df44 193 * \param idx The attribute index to be set [0-7]
lypinator 0:bb348c97df44 194 * \param attr The attribute value to be set.
lypinator 0:bb348c97df44 195 */
lypinator 0:bb348c97df44 196 __STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
lypinator 0:bb348c97df44 197 {
lypinator 0:bb348c97df44 198 ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
lypinator 0:bb348c97df44 199 }
lypinator 0:bb348c97df44 200 #endif
lypinator 0:bb348c97df44 201
lypinator 0:bb348c97df44 202 /** Clear and disable the given MPU region of the given MPU.
lypinator 0:bb348c97df44 203 * \param mpu Pointer to MPU to be used.
lypinator 0:bb348c97df44 204 * \param rnr Region number to be cleared.
lypinator 0:bb348c97df44 205 */
lypinator 0:bb348c97df44 206 __STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
lypinator 0:bb348c97df44 207 {
lypinator 0:bb348c97df44 208 mpu->RNR = rnr;
lypinator 0:bb348c97df44 209 mpu->RLAR = 0U;
lypinator 0:bb348c97df44 210 }
lypinator 0:bb348c97df44 211
lypinator 0:bb348c97df44 212 /** Clear and disable the given MPU region.
lypinator 0:bb348c97df44 213 * \param rnr Region number to be cleared.
lypinator 0:bb348c97df44 214 */
lypinator 0:bb348c97df44 215 __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
lypinator 0:bb348c97df44 216 {
lypinator 0:bb348c97df44 217 ARM_MPU_ClrRegionEx(MPU, rnr);
lypinator 0:bb348c97df44 218 }
lypinator 0:bb348c97df44 219
lypinator 0:bb348c97df44 220 #ifdef MPU_NS
lypinator 0:bb348c97df44 221 /** Clear and disable the given Non-secure MPU region.
lypinator 0:bb348c97df44 222 * \param rnr Region number to be cleared.
lypinator 0:bb348c97df44 223 */
lypinator 0:bb348c97df44 224 __STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
lypinator 0:bb348c97df44 225 {
lypinator 0:bb348c97df44 226 ARM_MPU_ClrRegionEx(MPU_NS, rnr);
lypinator 0:bb348c97df44 227 }
lypinator 0:bb348c97df44 228 #endif
lypinator 0:bb348c97df44 229
lypinator 0:bb348c97df44 230 /** Configure the given MPU region of the given MPU.
lypinator 0:bb348c97df44 231 * \param mpu Pointer to MPU to be used.
lypinator 0:bb348c97df44 232 * \param rnr Region number to be configured.
lypinator 0:bb348c97df44 233 * \param rbar Value for RBAR register.
lypinator 0:bb348c97df44 234 * \param rlar Value for RLAR register.
lypinator 0:bb348c97df44 235 */
lypinator 0:bb348c97df44 236 __STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
lypinator 0:bb348c97df44 237 {
lypinator 0:bb348c97df44 238 mpu->RNR = rnr;
lypinator 0:bb348c97df44 239 mpu->RBAR = rbar;
lypinator 0:bb348c97df44 240 mpu->RLAR = rlar;
lypinator 0:bb348c97df44 241 }
lypinator 0:bb348c97df44 242
lypinator 0:bb348c97df44 243 /** Configure the given MPU region.
lypinator 0:bb348c97df44 244 * \param rnr Region number to be configured.
lypinator 0:bb348c97df44 245 * \param rbar Value for RBAR register.
lypinator 0:bb348c97df44 246 * \param rlar Value for RLAR register.
lypinator 0:bb348c97df44 247 */
lypinator 0:bb348c97df44 248 __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
lypinator 0:bb348c97df44 249 {
lypinator 0:bb348c97df44 250 ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
lypinator 0:bb348c97df44 251 }
lypinator 0:bb348c97df44 252
lypinator 0:bb348c97df44 253 #ifdef MPU_NS
lypinator 0:bb348c97df44 254 /** Configure the given Non-secure MPU region.
lypinator 0:bb348c97df44 255 * \param rnr Region number to be configured.
lypinator 0:bb348c97df44 256 * \param rbar Value for RBAR register.
lypinator 0:bb348c97df44 257 * \param rlar Value for RLAR register.
lypinator 0:bb348c97df44 258 */
lypinator 0:bb348c97df44 259 __STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
lypinator 0:bb348c97df44 260 {
lypinator 0:bb348c97df44 261 ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);
lypinator 0:bb348c97df44 262 }
lypinator 0:bb348c97df44 263 #endif
lypinator 0:bb348c97df44 264
lypinator 0:bb348c97df44 265 /** Memcopy with strictly ordered memory access, e.g. for register targets.
lypinator 0:bb348c97df44 266 * \param dst Destination data is copied to.
lypinator 0:bb348c97df44 267 * \param src Source data is copied from.
lypinator 0:bb348c97df44 268 * \param len Amount of data words to be copied.
lypinator 0:bb348c97df44 269 */
lypinator 0:bb348c97df44 270 __STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
lypinator 0:bb348c97df44 271 {
lypinator 0:bb348c97df44 272 uint32_t i;
lypinator 0:bb348c97df44 273 for (i = 0U; i < len; ++i)
lypinator 0:bb348c97df44 274 {
lypinator 0:bb348c97df44 275 dst[i] = src[i];
lypinator 0:bb348c97df44 276 }
lypinator 0:bb348c97df44 277 }
lypinator 0:bb348c97df44 278
lypinator 0:bb348c97df44 279 /** Load the given number of MPU regions from a table to the given MPU.
lypinator 0:bb348c97df44 280 * \param mpu Pointer to the MPU registers to be used.
lypinator 0:bb348c97df44 281 * \param rnr First region number to be configured.
lypinator 0:bb348c97df44 282 * \param table Pointer to the MPU configuration table.
lypinator 0:bb348c97df44 283 * \param cnt Amount of regions to be configured.
lypinator 0:bb348c97df44 284 */
lypinator 0:bb348c97df44 285 __STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
lypinator 0:bb348c97df44 286 {
lypinator 0:bb348c97df44 287 const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
lypinator 0:bb348c97df44 288 if (cnt == 1U) {
lypinator 0:bb348c97df44 289 mpu->RNR = rnr;
lypinator 0:bb348c97df44 290 orderedCpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
lypinator 0:bb348c97df44 291 } else {
lypinator 0:bb348c97df44 292 uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U);
lypinator 0:bb348c97df44 293 uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
lypinator 0:bb348c97df44 294
lypinator 0:bb348c97df44 295 mpu->RNR = rnrBase;
lypinator 0:bb348c97df44 296 while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
lypinator 0:bb348c97df44 297 uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
lypinator 0:bb348c97df44 298 orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
lypinator 0:bb348c97df44 299 table += c;
lypinator 0:bb348c97df44 300 cnt -= c;
lypinator 0:bb348c97df44 301 rnrOffset = 0U;
lypinator 0:bb348c97df44 302 rnrBase += MPU_TYPE_RALIASES;
lypinator 0:bb348c97df44 303 mpu->RNR = rnrBase;
lypinator 0:bb348c97df44 304 }
lypinator 0:bb348c97df44 305
lypinator 0:bb348c97df44 306 orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
lypinator 0:bb348c97df44 307 }
lypinator 0:bb348c97df44 308 }
lypinator 0:bb348c97df44 309
lypinator 0:bb348c97df44 310 /** Load the given number of MPU regions from a table.
lypinator 0:bb348c97df44 311 * \param rnr First region number to be configured.
lypinator 0:bb348c97df44 312 * \param table Pointer to the MPU configuration table.
lypinator 0:bb348c97df44 313 * \param cnt Amount of regions to be configured.
lypinator 0:bb348c97df44 314 */
lypinator 0:bb348c97df44 315 __STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
lypinator 0:bb348c97df44 316 {
lypinator 0:bb348c97df44 317 ARM_MPU_LoadEx(MPU, rnr, table, cnt);
lypinator 0:bb348c97df44 318 }
lypinator 0:bb348c97df44 319
lypinator 0:bb348c97df44 320 #ifdef MPU_NS
lypinator 0:bb348c97df44 321 /** Load the given number of MPU regions from a table to the Non-secure MPU.
lypinator 0:bb348c97df44 322 * \param rnr First region number to be configured.
lypinator 0:bb348c97df44 323 * \param table Pointer to the MPU configuration table.
lypinator 0:bb348c97df44 324 * \param cnt Amount of regions to be configured.
lypinator 0:bb348c97df44 325 */
lypinator 0:bb348c97df44 326 __STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
lypinator 0:bb348c97df44 327 {
lypinator 0:bb348c97df44 328 ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
lypinator 0:bb348c97df44 329 }
lypinator 0:bb348c97df44 330 #endif
lypinator 0:bb348c97df44 331
lypinator 0:bb348c97df44 332 #endif
lypinator 0:bb348c97df44 333