Thomas Lyp / DevLibMemoryController

Initial commit

Dependencies:   FastPWM

mbed-dev-master/cmsis/TARGET_CORTEX_M/mpu_armv7.h@0:bb348c97df44, 2020-09-16 (annotated)

Committer:
lypinator
Date:
Wed Sep 16 01:11:49 2020 +0000
Revision:
0:bb348c97df44
Added PWM

Who changed what in which revision?

UserRevisionLine numberNew contents of line
lypinator 0:bb348c97df44 1 /******************************************************************************
lypinator 0:bb348c97df44 2 * @file mpu_armv7.h
lypinator 0:bb348c97df44 3 * @brief CMSIS MPU API for Armv7-M MPU
lypinator 0:bb348c97df44 4 * @version V5.0.4
lypinator 0:bb348c97df44 5 * @date 10. January 2018
lypinator 0:bb348c97df44 6 ******************************************************************************/
lypinator 0:bb348c97df44 7 /*
lypinator 0:bb348c97df44 8 * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
lypinator 0:bb348c97df44 9 *
lypinator 0:bb348c97df44 10 * SPDX-License-Identifier: Apache-2.0
lypinator 0:bb348c97df44 11 *
lypinator 0:bb348c97df44 12 * Licensed under the Apache License, Version 2.0 (the License); you may
lypinator 0:bb348c97df44 13 * not use this file except in compliance with the License.
lypinator 0:bb348c97df44 14 * You may obtain a copy of the License at
lypinator 0:bb348c97df44 15 *
lypinator 0:bb348c97df44 16 * www.apache.org/licenses/LICENSE-2.0
lypinator 0:bb348c97df44 17 *
lypinator 0:bb348c97df44 18 * Unless required by applicable law or agreed to in writing, software
lypinator 0:bb348c97df44 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
lypinator 0:bb348c97df44 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
lypinator 0:bb348c97df44 21 * See the License for the specific language governing permissions and
lypinator 0:bb348c97df44 22 * limitations under the License.
lypinator 0:bb348c97df44 23 */
lypinator 0:bb348c97df44 24
lypinator 0:bb348c97df44 25 #if defined ( __ICCARM__ )
lypinator 0:bb348c97df44 26 #pragma system_include /* treat file as system include file for MISRA check */
lypinator 0:bb348c97df44 27 #elif defined (__clang__)
lypinator 0:bb348c97df44 28 #pragma clang system_header /* treat file as system include file */
lypinator 0:bb348c97df44 29 #endif
lypinator 0:bb348c97df44 30
lypinator 0:bb348c97df44 31 #ifndef ARM_MPU_ARMV7_H
lypinator 0:bb348c97df44 32 #define ARM_MPU_ARMV7_H
lypinator 0:bb348c97df44 33
lypinator 0:bb348c97df44 34 #define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U)
lypinator 0:bb348c97df44 35 #define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U)
lypinator 0:bb348c97df44 36 #define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U)
lypinator 0:bb348c97df44 37 #define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U)
lypinator 0:bb348c97df44 38 #define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U)
lypinator 0:bb348c97df44 39 #define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U)
lypinator 0:bb348c97df44 40 #define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU)
lypinator 0:bb348c97df44 41 #define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU)
lypinator 0:bb348c97df44 42 #define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU)
lypinator 0:bb348c97df44 43 #define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU)
lypinator 0:bb348c97df44 44 #define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU)
lypinator 0:bb348c97df44 45 #define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU)
lypinator 0:bb348c97df44 46 #define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U)
lypinator 0:bb348c97df44 47 #define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U)
lypinator 0:bb348c97df44 48 #define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U)
lypinator 0:bb348c97df44 49 #define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U)
lypinator 0:bb348c97df44 50 #define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U)
lypinator 0:bb348c97df44 51 #define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U)
lypinator 0:bb348c97df44 52 #define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U)
lypinator 0:bb348c97df44 53 #define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U)
lypinator 0:bb348c97df44 54 #define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U)
lypinator 0:bb348c97df44 55 #define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U)
lypinator 0:bb348c97df44 56 #define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU)
lypinator 0:bb348c97df44 57 #define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU)
lypinator 0:bb348c97df44 58 #define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU)
lypinator 0:bb348c97df44 59 #define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU)
lypinator 0:bb348c97df44 60 #define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU)
lypinator 0:bb348c97df44 61 #define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU)
lypinator 0:bb348c97df44 62
lypinator 0:bb348c97df44 63 #define ARM_MPU_AP_NONE 0U
lypinator 0:bb348c97df44 64 #define ARM_MPU_AP_PRIV 1U
lypinator 0:bb348c97df44 65 #define ARM_MPU_AP_URO 2U
lypinator 0:bb348c97df44 66 #define ARM_MPU_AP_FULL 3U
lypinator 0:bb348c97df44 67 #define ARM_MPU_AP_PRO 5U
lypinator 0:bb348c97df44 68 #define ARM_MPU_AP_RO 6U
lypinator 0:bb348c97df44 69
lypinator 0:bb348c97df44 70 /** MPU Region Base Address Register Value
lypinator 0:bb348c97df44 71 *
lypinator 0:bb348c97df44 72 * \param Region The region to be configured, number 0 to 15.
lypinator 0:bb348c97df44 73 * \param BaseAddress The base address for the region.
lypinator 0:bb348c97df44 74 */
lypinator 0:bb348c97df44 75 #define ARM_MPU_RBAR(Region, BaseAddress) \
lypinator 0:bb348c97df44 76 (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
lypinator 0:bb348c97df44 77 ((Region) & MPU_RBAR_REGION_Msk) | \
lypinator 0:bb348c97df44 78 (MPU_RBAR_VALID_Msk))
lypinator 0:bb348c97df44 79
lypinator 0:bb348c97df44 80 /**
lypinator 0:bb348c97df44 81 * MPU Region Attribute and Size Register Value
lypinator 0:bb348c97df44 82 *
lypinator 0:bb348c97df44 83 * \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
lypinator 0:bb348c97df44 84 * \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
lypinator 0:bb348c97df44 85 * \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
lypinator 0:bb348c97df44 86 * \param IsShareable Region is shareable between multiple bus masters.
lypinator 0:bb348c97df44 87 * \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
lypinator 0:bb348c97df44 88 * \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
lypinator 0:bb348c97df44 89 * \param SubRegionDisable Sub-region disable field.
lypinator 0:bb348c97df44 90 * \param Size Region size of the region to be configured, for example 4K, 8K.
lypinator 0:bb348c97df44 91 */
lypinator 0:bb348c97df44 92 #define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
lypinator 0:bb348c97df44 93 ((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
lypinator 0:bb348c97df44 94 (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
lypinator 0:bb348c97df44 95 (((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
lypinator 0:bb348c97df44 96 (((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
lypinator 0:bb348c97df44 97 (((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
lypinator 0:bb348c97df44 98 (((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk) | \
lypinator 0:bb348c97df44 99 (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \
lypinator 0:bb348c97df44 100 (((Size ) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \
lypinator 0:bb348c97df44 101 (MPU_RASR_ENABLE_Msk))
lypinator 0:bb348c97df44 102
lypinator 0:bb348c97df44 103
lypinator 0:bb348c97df44 104 /**
lypinator 0:bb348c97df44 105 * Struct for a single MPU Region
lypinator 0:bb348c97df44 106 */
lypinator 0:bb348c97df44 107 typedef struct {
lypinator 0:bb348c97df44 108 uint32_t RBAR; //!< The region base address register value (RBAR)
lypinator 0:bb348c97df44 109 uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
lypinator 0:bb348c97df44 110 } ARM_MPU_Region_t;
lypinator 0:bb348c97df44 111
lypinator 0:bb348c97df44 112 /** Enable the MPU.
lypinator 0:bb348c97df44 113 * \param MPU_Control Default access permissions for unconfigured regions.
lypinator 0:bb348c97df44 114 */
lypinator 0:bb348c97df44 115 __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
lypinator 0:bb348c97df44 116 {
lypinator 0:bb348c97df44 117 __DSB();
lypinator 0:bb348c97df44 118 __ISB();
lypinator 0:bb348c97df44 119 MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
lypinator 0:bb348c97df44 120 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
lypinator 0:bb348c97df44 121 SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
lypinator 0:bb348c97df44 122 #endif
lypinator 0:bb348c97df44 123 }
lypinator 0:bb348c97df44 124
lypinator 0:bb348c97df44 125 /** Disable the MPU.
lypinator 0:bb348c97df44 126 */
lypinator 0:bb348c97df44 127 __STATIC_INLINE void ARM_MPU_Disable(void)
lypinator 0:bb348c97df44 128 {
lypinator 0:bb348c97df44 129 __DSB();
lypinator 0:bb348c97df44 130 __ISB();
lypinator 0:bb348c97df44 131 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
lypinator 0:bb348c97df44 132 SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
lypinator 0:bb348c97df44 133 #endif
lypinator 0:bb348c97df44 134 MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
lypinator 0:bb348c97df44 135 }
lypinator 0:bb348c97df44 136
lypinator 0:bb348c97df44 137 /** Clear and disable the given MPU region.
lypinator 0:bb348c97df44 138 * \param rnr Region number to be cleared.
lypinator 0:bb348c97df44 139 */
lypinator 0:bb348c97df44 140 __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
lypinator 0:bb348c97df44 141 {
lypinator 0:bb348c97df44 142 MPU->RNR = rnr;
lypinator 0:bb348c97df44 143 MPU->RASR = 0U;
lypinator 0:bb348c97df44 144 }
lypinator 0:bb348c97df44 145
lypinator 0:bb348c97df44 146 /** Configure an MPU region.
lypinator 0:bb348c97df44 147 * \param rbar Value for RBAR register.
lypinator 0:bb348c97df44 148 * \param rsar Value for RSAR register.
lypinator 0:bb348c97df44 149 */
lypinator 0:bb348c97df44 150 __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
lypinator 0:bb348c97df44 151 {
lypinator 0:bb348c97df44 152 MPU->RBAR = rbar;
lypinator 0:bb348c97df44 153 MPU->RASR = rasr;
lypinator 0:bb348c97df44 154 }
lypinator 0:bb348c97df44 155
lypinator 0:bb348c97df44 156 /** Configure the given MPU region.
lypinator 0:bb348c97df44 157 * \param rnr Region number to be configured.
lypinator 0:bb348c97df44 158 * \param rbar Value for RBAR register.
lypinator 0:bb348c97df44 159 * \param rsar Value for RSAR register.
lypinator 0:bb348c97df44 160 */
lypinator 0:bb348c97df44 161 __STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
lypinator 0:bb348c97df44 162 {
lypinator 0:bb348c97df44 163 MPU->RNR = rnr;
lypinator 0:bb348c97df44 164 MPU->RBAR = rbar;
lypinator 0:bb348c97df44 165 MPU->RASR = rasr;
lypinator 0:bb348c97df44 166 }
lypinator 0:bb348c97df44 167
lypinator 0:bb348c97df44 168 /** Memcopy with strictly ordered memory access, e.g. for register targets.
lypinator 0:bb348c97df44 169 * \param dst Destination data is copied to.
lypinator 0:bb348c97df44 170 * \param src Source data is copied from.
lypinator 0:bb348c97df44 171 * \param len Amount of data words to be copied.
lypinator 0:bb348c97df44 172 */
lypinator 0:bb348c97df44 173 __STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
lypinator 0:bb348c97df44 174 {
lypinator 0:bb348c97df44 175 uint32_t i;
lypinator 0:bb348c97df44 176 for (i = 0U; i < len; ++i)
lypinator 0:bb348c97df44 177 {
lypinator 0:bb348c97df44 178 dst[i] = src[i];
lypinator 0:bb348c97df44 179 }
lypinator 0:bb348c97df44 180 }
lypinator 0:bb348c97df44 181
lypinator 0:bb348c97df44 182 /** Load the given number of MPU regions from a table.
lypinator 0:bb348c97df44 183 * \param table Pointer to the MPU configuration table.
lypinator 0:bb348c97df44 184 * \param cnt Amount of regions to be configured.
lypinator 0:bb348c97df44 185 */
lypinator 0:bb348c97df44 186 __STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
lypinator 0:bb348c97df44 187 {
lypinator 0:bb348c97df44 188 const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
lypinator 0:bb348c97df44 189 while (cnt > MPU_TYPE_RALIASES) {
lypinator 0:bb348c97df44 190 orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
lypinator 0:bb348c97df44 191 table += MPU_TYPE_RALIASES;
lypinator 0:bb348c97df44 192 cnt -= MPU_TYPE_RALIASES;
lypinator 0:bb348c97df44 193 }
lypinator 0:bb348c97df44 194 orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
lypinator 0:bb348c97df44 195 }
lypinator 0:bb348c97df44 196
lypinator 0:bb348c97df44 197 #endif