Thomas Lyp / DevLibMemoryController

Initial commit

Dependencies:   FastPWM

mbed-dev-master/cmsis/TARGET_CORTEX_M/core_sc000.h@0:bb348c97df44, 2020-09-16 (annotated)

Committer:
lypinator
Date:
Wed Sep 16 01:11:49 2020 +0000
Revision:
0:bb348c97df44
Added PWM

Who changed what in which revision?

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lypinator 0:bb348c97df44 1 /**************************************************************************//**
lypinator 0:bb348c97df44 2 * @file core_sc000.h
lypinator 0:bb348c97df44 3 * @brief CMSIS SC000 Core Peripheral Access Layer Header File
lypinator 0:bb348c97df44 4 * @version V5.0.3
lypinator 0:bb348c97df44 5 * @date 10. January 2018
lypinator 0:bb348c97df44 6 ******************************************************************************/
lypinator 0:bb348c97df44 7 /*
lypinator 0:bb348c97df44 8 * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
lypinator 0:bb348c97df44 9 *
lypinator 0:bb348c97df44 10 * SPDX-License-Identifier: Apache-2.0
lypinator 0:bb348c97df44 11 *
lypinator 0:bb348c97df44 12 * Licensed under the Apache License, Version 2.0 (the License); you may
lypinator 0:bb348c97df44 13 * not use this file except in compliance with the License.
lypinator 0:bb348c97df44 14 * You may obtain a copy of the License at
lypinator 0:bb348c97df44 15 *
lypinator 0:bb348c97df44 16 * www.apache.org/licenses/LICENSE-2.0
lypinator 0:bb348c97df44 17 *
lypinator 0:bb348c97df44 18 * Unless required by applicable law or agreed to in writing, software
lypinator 0:bb348c97df44 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
lypinator 0:bb348c97df44 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
lypinator 0:bb348c97df44 21 * See the License for the specific language governing permissions and
lypinator 0:bb348c97df44 22 * limitations under the License.
lypinator 0:bb348c97df44 23 */
lypinator 0:bb348c97df44 24
lypinator 0:bb348c97df44 25 #if defined ( __ICCARM__ )
lypinator 0:bb348c97df44 26 #pragma system_include /* treat file as system include file for MISRA check */
lypinator 0:bb348c97df44 27 #elif defined (__clang__)
lypinator 0:bb348c97df44 28 #pragma clang system_header /* treat file as system include file */
lypinator 0:bb348c97df44 29 #endif
lypinator 0:bb348c97df44 30
lypinator 0:bb348c97df44 31 #ifndef __CORE_SC000_H_GENERIC
lypinator 0:bb348c97df44 32 #define __CORE_SC000_H_GENERIC
lypinator 0:bb348c97df44 33
lypinator 0:bb348c97df44 34 #include <stdint.h>
lypinator 0:bb348c97df44 35
lypinator 0:bb348c97df44 36 #ifdef __cplusplus
lypinator 0:bb348c97df44 37 extern "C" {
lypinator 0:bb348c97df44 38 #endif
lypinator 0:bb348c97df44 39
lypinator 0:bb348c97df44 40 /**
lypinator 0:bb348c97df44 41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
lypinator 0:bb348c97df44 42 CMSIS violates the following MISRA-C:2004 rules:
lypinator 0:bb348c97df44 43
lypinator 0:bb348c97df44 44 \li Required Rule 8.5, object/function definition in header file.<br>
lypinator 0:bb348c97df44 45 Function definitions in header files are used to allow 'inlining'.
lypinator 0:bb348c97df44 46
lypinator 0:bb348c97df44 47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
lypinator 0:bb348c97df44 48 Unions are used for effective representation of core registers.
lypinator 0:bb348c97df44 49
lypinator 0:bb348c97df44 50 \li Advisory Rule 19.7, Function-like macro defined.<br>
lypinator 0:bb348c97df44 51 Function-like macros are used to allow more efficient code.
lypinator 0:bb348c97df44 52 */
lypinator 0:bb348c97df44 53
lypinator 0:bb348c97df44 54
lypinator 0:bb348c97df44 55 /*******************************************************************************
lypinator 0:bb348c97df44 56 * CMSIS definitions
lypinator 0:bb348c97df44 57 ******************************************************************************/
lypinator 0:bb348c97df44 58 /**
lypinator 0:bb348c97df44 59 \ingroup SC000
lypinator 0:bb348c97df44 60 @{
lypinator 0:bb348c97df44 61 */
lypinator 0:bb348c97df44 62
lypinator 0:bb348c97df44 63 #include "cmsis_version.h"
lypinator 0:bb348c97df44 64
lypinator 0:bb348c97df44 65 /* CMSIS SC000 definitions */
lypinator 0:bb348c97df44 66 #define __SC000_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
lypinator 0:bb348c97df44 67 #define __SC000_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
lypinator 0:bb348c97df44 68 #define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \
lypinator 0:bb348c97df44 69 __SC000_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
lypinator 0:bb348c97df44 70
lypinator 0:bb348c97df44 71 #define __CORTEX_SC (000U) /*!< Cortex secure core */
lypinator 0:bb348c97df44 72
lypinator 0:bb348c97df44 73 /** __FPU_USED indicates whether an FPU is used or not.
lypinator 0:bb348c97df44 74 This core does not support an FPU at all
lypinator 0:bb348c97df44 75 */
lypinator 0:bb348c97df44 76 #define __FPU_USED 0U
lypinator 0:bb348c97df44 77
lypinator 0:bb348c97df44 78 #if defined ( __CC_ARM )
lypinator 0:bb348c97df44 79 #if defined __TARGET_FPU_VFP
lypinator 0:bb348c97df44 80 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
lypinator 0:bb348c97df44 81 #endif
lypinator 0:bb348c97df44 82
lypinator 0:bb348c97df44 83 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
lypinator 0:bb348c97df44 84 #if defined __ARM_PCS_VFP
lypinator 0:bb348c97df44 85 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
lypinator 0:bb348c97df44 86 #endif
lypinator 0:bb348c97df44 87
lypinator 0:bb348c97df44 88 #elif defined ( __GNUC__ )
lypinator 0:bb348c97df44 89 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
lypinator 0:bb348c97df44 90 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
lypinator 0:bb348c97df44 91 #endif
lypinator 0:bb348c97df44 92
lypinator 0:bb348c97df44 93 #elif defined ( __ICCARM__ )
lypinator 0:bb348c97df44 94 #if defined __ARMVFP__
lypinator 0:bb348c97df44 95 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
lypinator 0:bb348c97df44 96 #endif
lypinator 0:bb348c97df44 97
lypinator 0:bb348c97df44 98 #elif defined ( __TI_ARM__ )
lypinator 0:bb348c97df44 99 #if defined __TI_VFP_SUPPORT__
lypinator 0:bb348c97df44 100 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
lypinator 0:bb348c97df44 101 #endif
lypinator 0:bb348c97df44 102
lypinator 0:bb348c97df44 103 #elif defined ( __TASKING__ )
lypinator 0:bb348c97df44 104 #if defined __FPU_VFP__
lypinator 0:bb348c97df44 105 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
lypinator 0:bb348c97df44 106 #endif
lypinator 0:bb348c97df44 107
lypinator 0:bb348c97df44 108 #elif defined ( __CSMC__ )
lypinator 0:bb348c97df44 109 #if ( __CSMC__ & 0x400U)
lypinator 0:bb348c97df44 110 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
lypinator 0:bb348c97df44 111 #endif
lypinator 0:bb348c97df44 112
lypinator 0:bb348c97df44 113 #endif
lypinator 0:bb348c97df44 114
lypinator 0:bb348c97df44 115 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
lypinator 0:bb348c97df44 116
lypinator 0:bb348c97df44 117
lypinator 0:bb348c97df44 118 #ifdef __cplusplus
lypinator 0:bb348c97df44 119 }
lypinator 0:bb348c97df44 120 #endif
lypinator 0:bb348c97df44 121
lypinator 0:bb348c97df44 122 #endif /* __CORE_SC000_H_GENERIC */
lypinator 0:bb348c97df44 123
lypinator 0:bb348c97df44 124 #ifndef __CMSIS_GENERIC
lypinator 0:bb348c97df44 125
lypinator 0:bb348c97df44 126 #ifndef __CORE_SC000_H_DEPENDANT
lypinator 0:bb348c97df44 127 #define __CORE_SC000_H_DEPENDANT
lypinator 0:bb348c97df44 128
lypinator 0:bb348c97df44 129 #ifdef __cplusplus
lypinator 0:bb348c97df44 130 extern "C" {
lypinator 0:bb348c97df44 131 #endif
lypinator 0:bb348c97df44 132
lypinator 0:bb348c97df44 133 /* check device defines and use defaults */
lypinator 0:bb348c97df44 134 #if defined __CHECK_DEVICE_DEFINES
lypinator 0:bb348c97df44 135 #ifndef __SC000_REV
lypinator 0:bb348c97df44 136 #define __SC000_REV 0x0000U
lypinator 0:bb348c97df44 137 #warning "__SC000_REV not defined in device header file; using default!"
lypinator 0:bb348c97df44 138 #endif
lypinator 0:bb348c97df44 139
lypinator 0:bb348c97df44 140 #ifndef __MPU_PRESENT
lypinator 0:bb348c97df44 141 #define __MPU_PRESENT 0U
lypinator 0:bb348c97df44 142 #warning "__MPU_PRESENT not defined in device header file; using default!"
lypinator 0:bb348c97df44 143 #endif
lypinator 0:bb348c97df44 144
lypinator 0:bb348c97df44 145 #ifndef __NVIC_PRIO_BITS
lypinator 0:bb348c97df44 146 #define __NVIC_PRIO_BITS 2U
lypinator 0:bb348c97df44 147 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
lypinator 0:bb348c97df44 148 #endif
lypinator 0:bb348c97df44 149
lypinator 0:bb348c97df44 150 #ifndef __Vendor_SysTickConfig
lypinator 0:bb348c97df44 151 #define __Vendor_SysTickConfig 0U
lypinator 0:bb348c97df44 152 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
lypinator 0:bb348c97df44 153 #endif
lypinator 0:bb348c97df44 154 #endif
lypinator 0:bb348c97df44 155
lypinator 0:bb348c97df44 156 /* IO definitions (access restrictions to peripheral registers) */
lypinator 0:bb348c97df44 157 /**
lypinator 0:bb348c97df44 158 \defgroup CMSIS_glob_defs CMSIS Global Defines
lypinator 0:bb348c97df44 159
lypinator 0:bb348c97df44 160 <strong>IO Type Qualifiers</strong> are used
lypinator 0:bb348c97df44 161 \li to specify the access to peripheral variables.
lypinator 0:bb348c97df44 162 \li for automatic generation of peripheral register debug information.
lypinator 0:bb348c97df44 163 */
lypinator 0:bb348c97df44 164 #ifdef __cplusplus
lypinator 0:bb348c97df44 165 #define __I volatile /*!< Defines 'read only' permissions */
lypinator 0:bb348c97df44 166 #else
lypinator 0:bb348c97df44 167 #define __I volatile const /*!< Defines 'read only' permissions */
lypinator 0:bb348c97df44 168 #endif
lypinator 0:bb348c97df44 169 #define __O volatile /*!< Defines 'write only' permissions */
lypinator 0:bb348c97df44 170 #define __IO volatile /*!< Defines 'read / write' permissions */
lypinator 0:bb348c97df44 171
lypinator 0:bb348c97df44 172 /* following defines should be used for structure members */
lypinator 0:bb348c97df44 173 #define __IM volatile const /*! Defines 'read only' structure member permissions */
lypinator 0:bb348c97df44 174 #define __OM volatile /*! Defines 'write only' structure member permissions */
lypinator 0:bb348c97df44 175 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
lypinator 0:bb348c97df44 176
lypinator 0:bb348c97df44 177 /*@} end of group SC000 */
lypinator 0:bb348c97df44 178
lypinator 0:bb348c97df44 179
lypinator 0:bb348c97df44 180
lypinator 0:bb348c97df44 181 /*******************************************************************************
lypinator 0:bb348c97df44 182 * Register Abstraction
lypinator 0:bb348c97df44 183 Core Register contain:
lypinator 0:bb348c97df44 184 - Core Register
lypinator 0:bb348c97df44 185 - Core NVIC Register
lypinator 0:bb348c97df44 186 - Core SCB Register
lypinator 0:bb348c97df44 187 - Core SysTick Register
lypinator 0:bb348c97df44 188 - Core MPU Register
lypinator 0:bb348c97df44 189 ******************************************************************************/
lypinator 0:bb348c97df44 190 /**
lypinator 0:bb348c97df44 191 \defgroup CMSIS_core_register Defines and Type Definitions
lypinator 0:bb348c97df44 192 \brief Type definitions and defines for Cortex-M processor based devices.
lypinator 0:bb348c97df44 193 */
lypinator 0:bb348c97df44 194
lypinator 0:bb348c97df44 195 /**
lypinator 0:bb348c97df44 196 \ingroup CMSIS_core_register
lypinator 0:bb348c97df44 197 \defgroup CMSIS_CORE Status and Control Registers
lypinator 0:bb348c97df44 198 \brief Core Register type definitions.
lypinator 0:bb348c97df44 199 @{
lypinator 0:bb348c97df44 200 */
lypinator 0:bb348c97df44 201
lypinator 0:bb348c97df44 202 /**
lypinator 0:bb348c97df44 203 \brief Union type to access the Application Program Status Register (APSR).
lypinator 0:bb348c97df44 204 */
lypinator 0:bb348c97df44 205 typedef union
lypinator 0:bb348c97df44 206 {
lypinator 0:bb348c97df44 207 struct
lypinator 0:bb348c97df44 208 {
lypinator 0:bb348c97df44 209 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
lypinator 0:bb348c97df44 210 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
lypinator 0:bb348c97df44 211 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
lypinator 0:bb348c97df44 212 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
lypinator 0:bb348c97df44 213 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
lypinator 0:bb348c97df44 214 } b; /*!< Structure used for bit access */
lypinator 0:bb348c97df44 215 uint32_t w; /*!< Type used for word access */
lypinator 0:bb348c97df44 216 } APSR_Type;
lypinator 0:bb348c97df44 217
lypinator 0:bb348c97df44 218 /* APSR Register Definitions */
lypinator 0:bb348c97df44 219 #define APSR_N_Pos 31U /*!< APSR: N Position */
lypinator 0:bb348c97df44 220 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
lypinator 0:bb348c97df44 221
lypinator 0:bb348c97df44 222 #define APSR_Z_Pos 30U /*!< APSR: Z Position */
lypinator 0:bb348c97df44 223 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
lypinator 0:bb348c97df44 224
lypinator 0:bb348c97df44 225 #define APSR_C_Pos 29U /*!< APSR: C Position */
lypinator 0:bb348c97df44 226 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
lypinator 0:bb348c97df44 227
lypinator 0:bb348c97df44 228 #define APSR_V_Pos 28U /*!< APSR: V Position */
lypinator 0:bb348c97df44 229 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
lypinator 0:bb348c97df44 230
lypinator 0:bb348c97df44 231
lypinator 0:bb348c97df44 232 /**
lypinator 0:bb348c97df44 233 \brief Union type to access the Interrupt Program Status Register (IPSR).
lypinator 0:bb348c97df44 234 */
lypinator 0:bb348c97df44 235 typedef union
lypinator 0:bb348c97df44 236 {
lypinator 0:bb348c97df44 237 struct
lypinator 0:bb348c97df44 238 {
lypinator 0:bb348c97df44 239 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
lypinator 0:bb348c97df44 240 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
lypinator 0:bb348c97df44 241 } b; /*!< Structure used for bit access */
lypinator 0:bb348c97df44 242 uint32_t w; /*!< Type used for word access */
lypinator 0:bb348c97df44 243 } IPSR_Type;
lypinator 0:bb348c97df44 244
lypinator 0:bb348c97df44 245 /* IPSR Register Definitions */
lypinator 0:bb348c97df44 246 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
lypinator 0:bb348c97df44 247 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
lypinator 0:bb348c97df44 248
lypinator 0:bb348c97df44 249
lypinator 0:bb348c97df44 250 /**
lypinator 0:bb348c97df44 251 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
lypinator 0:bb348c97df44 252 */
lypinator 0:bb348c97df44 253 typedef union
lypinator 0:bb348c97df44 254 {
lypinator 0:bb348c97df44 255 struct
lypinator 0:bb348c97df44 256 {
lypinator 0:bb348c97df44 257 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
lypinator 0:bb348c97df44 258 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
lypinator 0:bb348c97df44 259 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
lypinator 0:bb348c97df44 260 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
lypinator 0:bb348c97df44 261 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
lypinator 0:bb348c97df44 262 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
lypinator 0:bb348c97df44 263 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
lypinator 0:bb348c97df44 264 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
lypinator 0:bb348c97df44 265 } b; /*!< Structure used for bit access */
lypinator 0:bb348c97df44 266 uint32_t w; /*!< Type used for word access */
lypinator 0:bb348c97df44 267 } xPSR_Type;
lypinator 0:bb348c97df44 268
lypinator 0:bb348c97df44 269 /* xPSR Register Definitions */
lypinator 0:bb348c97df44 270 #define xPSR_N_Pos 31U /*!< xPSR: N Position */
lypinator 0:bb348c97df44 271 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
lypinator 0:bb348c97df44 272
lypinator 0:bb348c97df44 273 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
lypinator 0:bb348c97df44 274 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
lypinator 0:bb348c97df44 275
lypinator 0:bb348c97df44 276 #define xPSR_C_Pos 29U /*!< xPSR: C Position */
lypinator 0:bb348c97df44 277 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
lypinator 0:bb348c97df44 278
lypinator 0:bb348c97df44 279 #define xPSR_V_Pos 28U /*!< xPSR: V Position */
lypinator 0:bb348c97df44 280 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
lypinator 0:bb348c97df44 281
lypinator 0:bb348c97df44 282 #define xPSR_T_Pos 24U /*!< xPSR: T Position */
lypinator 0:bb348c97df44 283 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
lypinator 0:bb348c97df44 284
lypinator 0:bb348c97df44 285 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
lypinator 0:bb348c97df44 286 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
lypinator 0:bb348c97df44 287
lypinator 0:bb348c97df44 288
lypinator 0:bb348c97df44 289 /**
lypinator 0:bb348c97df44 290 \brief Union type to access the Control Registers (CONTROL).
lypinator 0:bb348c97df44 291 */
lypinator 0:bb348c97df44 292 typedef union
lypinator 0:bb348c97df44 293 {
lypinator 0:bb348c97df44 294 struct
lypinator 0:bb348c97df44 295 {
lypinator 0:bb348c97df44 296 uint32_t _reserved0:1; /*!< bit: 0 Reserved */
lypinator 0:bb348c97df44 297 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
lypinator 0:bb348c97df44 298 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
lypinator 0:bb348c97df44 299 } b; /*!< Structure used for bit access */
lypinator 0:bb348c97df44 300 uint32_t w; /*!< Type used for word access */
lypinator 0:bb348c97df44 301 } CONTROL_Type;
lypinator 0:bb348c97df44 302
lypinator 0:bb348c97df44 303 /* CONTROL Register Definitions */
lypinator 0:bb348c97df44 304 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
lypinator 0:bb348c97df44 305 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
lypinator 0:bb348c97df44 306
lypinator 0:bb348c97df44 307 /*@} end of group CMSIS_CORE */
lypinator 0:bb348c97df44 308
lypinator 0:bb348c97df44 309
lypinator 0:bb348c97df44 310 /**
lypinator 0:bb348c97df44 311 \ingroup CMSIS_core_register
lypinator 0:bb348c97df44 312 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
lypinator 0:bb348c97df44 313 \brief Type definitions for the NVIC Registers
lypinator 0:bb348c97df44 314 @{
lypinator 0:bb348c97df44 315 */
lypinator 0:bb348c97df44 316
lypinator 0:bb348c97df44 317 /**
lypinator 0:bb348c97df44 318 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
lypinator 0:bb348c97df44 319 */
lypinator 0:bb348c97df44 320 typedef struct
lypinator 0:bb348c97df44 321 {
lypinator 0:bb348c97df44 322 __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
lypinator 0:bb348c97df44 323 uint32_t RESERVED0[31U];
lypinator 0:bb348c97df44 324 __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
lypinator 0:bb348c97df44 325 uint32_t RSERVED1[31U];
lypinator 0:bb348c97df44 326 __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
lypinator 0:bb348c97df44 327 uint32_t RESERVED2[31U];
lypinator 0:bb348c97df44 328 __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
lypinator 0:bb348c97df44 329 uint32_t RESERVED3[31U];
lypinator 0:bb348c97df44 330 uint32_t RESERVED4[64U];
lypinator 0:bb348c97df44 331 __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
lypinator 0:bb348c97df44 332 } NVIC_Type;
lypinator 0:bb348c97df44 333
lypinator 0:bb348c97df44 334 /*@} end of group CMSIS_NVIC */
lypinator 0:bb348c97df44 335
lypinator 0:bb348c97df44 336
lypinator 0:bb348c97df44 337 /**
lypinator 0:bb348c97df44 338 \ingroup CMSIS_core_register
lypinator 0:bb348c97df44 339 \defgroup CMSIS_SCB System Control Block (SCB)
lypinator 0:bb348c97df44 340 \brief Type definitions for the System Control Block Registers
lypinator 0:bb348c97df44 341 @{
lypinator 0:bb348c97df44 342 */
lypinator 0:bb348c97df44 343
lypinator 0:bb348c97df44 344 /**
lypinator 0:bb348c97df44 345 \brief Structure type to access the System Control Block (SCB).
lypinator 0:bb348c97df44 346 */
lypinator 0:bb348c97df44 347 typedef struct
lypinator 0:bb348c97df44 348 {
lypinator 0:bb348c97df44 349 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
lypinator 0:bb348c97df44 350 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
lypinator 0:bb348c97df44 351 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
lypinator 0:bb348c97df44 352 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
lypinator 0:bb348c97df44 353 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
lypinator 0:bb348c97df44 354 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
lypinator 0:bb348c97df44 355 uint32_t RESERVED0[1U];
lypinator 0:bb348c97df44 356 __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
lypinator 0:bb348c97df44 357 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
lypinator 0:bb348c97df44 358 uint32_t RESERVED1[154U];
lypinator 0:bb348c97df44 359 __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */
lypinator 0:bb348c97df44 360 } SCB_Type;
lypinator 0:bb348c97df44 361
lypinator 0:bb348c97df44 362 /* SCB CPUID Register Definitions */
lypinator 0:bb348c97df44 363 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
lypinator 0:bb348c97df44 364 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
lypinator 0:bb348c97df44 365
lypinator 0:bb348c97df44 366 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
lypinator 0:bb348c97df44 367 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
lypinator 0:bb348c97df44 368
lypinator 0:bb348c97df44 369 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
lypinator 0:bb348c97df44 370 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
lypinator 0:bb348c97df44 371
lypinator 0:bb348c97df44 372 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
lypinator 0:bb348c97df44 373 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
lypinator 0:bb348c97df44 374
lypinator 0:bb348c97df44 375 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
lypinator 0:bb348c97df44 376 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
lypinator 0:bb348c97df44 377
lypinator 0:bb348c97df44 378 /* SCB Interrupt Control State Register Definitions */
lypinator 0:bb348c97df44 379 #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
lypinator 0:bb348c97df44 380 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
lypinator 0:bb348c97df44 381
lypinator 0:bb348c97df44 382 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
lypinator 0:bb348c97df44 383 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
lypinator 0:bb348c97df44 384
lypinator 0:bb348c97df44 385 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
lypinator 0:bb348c97df44 386 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
lypinator 0:bb348c97df44 387
lypinator 0:bb348c97df44 388 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
lypinator 0:bb348c97df44 389 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
lypinator 0:bb348c97df44 390
lypinator 0:bb348c97df44 391 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
lypinator 0:bb348c97df44 392 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
lypinator 0:bb348c97df44 393
lypinator 0:bb348c97df44 394 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
lypinator 0:bb348c97df44 395 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
lypinator 0:bb348c97df44 396
lypinator 0:bb348c97df44 397 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
lypinator 0:bb348c97df44 398 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
lypinator 0:bb348c97df44 399
lypinator 0:bb348c97df44 400 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
lypinator 0:bb348c97df44 401 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
lypinator 0:bb348c97df44 402
lypinator 0:bb348c97df44 403 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
lypinator 0:bb348c97df44 404 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
lypinator 0:bb348c97df44 405
lypinator 0:bb348c97df44 406 /* SCB Interrupt Control State Register Definitions */
lypinator 0:bb348c97df44 407 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
lypinator 0:bb348c97df44 408 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
lypinator 0:bb348c97df44 409
lypinator 0:bb348c97df44 410 /* SCB Application Interrupt and Reset Control Register Definitions */
lypinator 0:bb348c97df44 411 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
lypinator 0:bb348c97df44 412 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
lypinator 0:bb348c97df44 413
lypinator 0:bb348c97df44 414 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
lypinator 0:bb348c97df44 415 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
lypinator 0:bb348c97df44 416
lypinator 0:bb348c97df44 417 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
lypinator 0:bb348c97df44 418 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
lypinator 0:bb348c97df44 419
lypinator 0:bb348c97df44 420 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
lypinator 0:bb348c97df44 421 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
lypinator 0:bb348c97df44 422
lypinator 0:bb348c97df44 423 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
lypinator 0:bb348c97df44 424 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
lypinator 0:bb348c97df44 425
lypinator 0:bb348c97df44 426 /* SCB System Control Register Definitions */
lypinator 0:bb348c97df44 427 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
lypinator 0:bb348c97df44 428 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
lypinator 0:bb348c97df44 429
lypinator 0:bb348c97df44 430 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
lypinator 0:bb348c97df44 431 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
lypinator 0:bb348c97df44 432
lypinator 0:bb348c97df44 433 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
lypinator 0:bb348c97df44 434 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
lypinator 0:bb348c97df44 435
lypinator 0:bb348c97df44 436 /* SCB Configuration Control Register Definitions */
lypinator 0:bb348c97df44 437 #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
lypinator 0:bb348c97df44 438 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
lypinator 0:bb348c97df44 439
lypinator 0:bb348c97df44 440 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
lypinator 0:bb348c97df44 441 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
lypinator 0:bb348c97df44 442
lypinator 0:bb348c97df44 443 /* SCB System Handler Control and State Register Definitions */
lypinator 0:bb348c97df44 444 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
lypinator 0:bb348c97df44 445 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
lypinator 0:bb348c97df44 446
lypinator 0:bb348c97df44 447 /*@} end of group CMSIS_SCB */
lypinator 0:bb348c97df44 448
lypinator 0:bb348c97df44 449
lypinator 0:bb348c97df44 450 /**
lypinator 0:bb348c97df44 451 \ingroup CMSIS_core_register
lypinator 0:bb348c97df44 452 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
lypinator 0:bb348c97df44 453 \brief Type definitions for the System Control and ID Register not in the SCB
lypinator 0:bb348c97df44 454 @{
lypinator 0:bb348c97df44 455 */
lypinator 0:bb348c97df44 456
lypinator 0:bb348c97df44 457 /**
lypinator 0:bb348c97df44 458 \brief Structure type to access the System Control and ID Register not in the SCB.
lypinator 0:bb348c97df44 459 */
lypinator 0:bb348c97df44 460 typedef struct
lypinator 0:bb348c97df44 461 {
lypinator 0:bb348c97df44 462 uint32_t RESERVED0[2U];
lypinator 0:bb348c97df44 463 __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
lypinator 0:bb348c97df44 464 } SCnSCB_Type;
lypinator 0:bb348c97df44 465
lypinator 0:bb348c97df44 466 /* Auxiliary Control Register Definitions */
lypinator 0:bb348c97df44 467 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
lypinator 0:bb348c97df44 468 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
lypinator 0:bb348c97df44 469
lypinator 0:bb348c97df44 470 /*@} end of group CMSIS_SCnotSCB */
lypinator 0:bb348c97df44 471
lypinator 0:bb348c97df44 472
lypinator 0:bb348c97df44 473 /**
lypinator 0:bb348c97df44 474 \ingroup CMSIS_core_register
lypinator 0:bb348c97df44 475 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
lypinator 0:bb348c97df44 476 \brief Type definitions for the System Timer Registers.
lypinator 0:bb348c97df44 477 @{
lypinator 0:bb348c97df44 478 */
lypinator 0:bb348c97df44 479
lypinator 0:bb348c97df44 480 /**
lypinator 0:bb348c97df44 481 \brief Structure type to access the System Timer (SysTick).
lypinator 0:bb348c97df44 482 */
lypinator 0:bb348c97df44 483 typedef struct
lypinator 0:bb348c97df44 484 {
lypinator 0:bb348c97df44 485 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
lypinator 0:bb348c97df44 486 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
lypinator 0:bb348c97df44 487 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
lypinator 0:bb348c97df44 488 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
lypinator 0:bb348c97df44 489 } SysTick_Type;
lypinator 0:bb348c97df44 490
lypinator 0:bb348c97df44 491 /* SysTick Control / Status Register Definitions */
lypinator 0:bb348c97df44 492 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
lypinator 0:bb348c97df44 493 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
lypinator 0:bb348c97df44 494
lypinator 0:bb348c97df44 495 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
lypinator 0:bb348c97df44 496 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
lypinator 0:bb348c97df44 497
lypinator 0:bb348c97df44 498 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
lypinator 0:bb348c97df44 499 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
lypinator 0:bb348c97df44 500
lypinator 0:bb348c97df44 501 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
lypinator 0:bb348c97df44 502 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
lypinator 0:bb348c97df44 503
lypinator 0:bb348c97df44 504 /* SysTick Reload Register Definitions */
lypinator 0:bb348c97df44 505 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
lypinator 0:bb348c97df44 506 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
lypinator 0:bb348c97df44 507
lypinator 0:bb348c97df44 508 /* SysTick Current Register Definitions */
lypinator 0:bb348c97df44 509 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
lypinator 0:bb348c97df44 510 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
lypinator 0:bb348c97df44 511
lypinator 0:bb348c97df44 512 /* SysTick Calibration Register Definitions */
lypinator 0:bb348c97df44 513 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
lypinator 0:bb348c97df44 514 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
lypinator 0:bb348c97df44 515
lypinator 0:bb348c97df44 516 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
lypinator 0:bb348c97df44 517 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
lypinator 0:bb348c97df44 518
lypinator 0:bb348c97df44 519 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
lypinator 0:bb348c97df44 520 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
lypinator 0:bb348c97df44 521
lypinator 0:bb348c97df44 522 /*@} end of group CMSIS_SysTick */
lypinator 0:bb348c97df44 523
lypinator 0:bb348c97df44 524 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
lypinator 0:bb348c97df44 525 /**
lypinator 0:bb348c97df44 526 \ingroup CMSIS_core_register
lypinator 0:bb348c97df44 527 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
lypinator 0:bb348c97df44 528 \brief Type definitions for the Memory Protection Unit (MPU)
lypinator 0:bb348c97df44 529 @{
lypinator 0:bb348c97df44 530 */
lypinator 0:bb348c97df44 531
lypinator 0:bb348c97df44 532 /**
lypinator 0:bb348c97df44 533 \brief Structure type to access the Memory Protection Unit (MPU).
lypinator 0:bb348c97df44 534 */
lypinator 0:bb348c97df44 535 typedef struct
lypinator 0:bb348c97df44 536 {
lypinator 0:bb348c97df44 537 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
lypinator 0:bb348c97df44 538 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
lypinator 0:bb348c97df44 539 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
lypinator 0:bb348c97df44 540 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
lypinator 0:bb348c97df44 541 __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
lypinator 0:bb348c97df44 542 } MPU_Type;
lypinator 0:bb348c97df44 543
lypinator 0:bb348c97df44 544 /* MPU Type Register Definitions */
lypinator 0:bb348c97df44 545 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
lypinator 0:bb348c97df44 546 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
lypinator 0:bb348c97df44 547
lypinator 0:bb348c97df44 548 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
lypinator 0:bb348c97df44 549 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
lypinator 0:bb348c97df44 550
lypinator 0:bb348c97df44 551 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
lypinator 0:bb348c97df44 552 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
lypinator 0:bb348c97df44 553
lypinator 0:bb348c97df44 554 /* MPU Control Register Definitions */
lypinator 0:bb348c97df44 555 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
lypinator 0:bb348c97df44 556 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
lypinator 0:bb348c97df44 557
lypinator 0:bb348c97df44 558 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
lypinator 0:bb348c97df44 559 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
lypinator 0:bb348c97df44 560
lypinator 0:bb348c97df44 561 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
lypinator 0:bb348c97df44 562 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
lypinator 0:bb348c97df44 563
lypinator 0:bb348c97df44 564 /* MPU Region Number Register Definitions */
lypinator 0:bb348c97df44 565 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
lypinator 0:bb348c97df44 566 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
lypinator 0:bb348c97df44 567
lypinator 0:bb348c97df44 568 /* MPU Region Base Address Register Definitions */
lypinator 0:bb348c97df44 569 #define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */
lypinator 0:bb348c97df44 570 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
lypinator 0:bb348c97df44 571
lypinator 0:bb348c97df44 572 #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
lypinator 0:bb348c97df44 573 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
lypinator 0:bb348c97df44 574
lypinator 0:bb348c97df44 575 #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
lypinator 0:bb348c97df44 576 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
lypinator 0:bb348c97df44 577
lypinator 0:bb348c97df44 578 /* MPU Region Attribute and Size Register Definitions */
lypinator 0:bb348c97df44 579 #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
lypinator 0:bb348c97df44 580 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
lypinator 0:bb348c97df44 581
lypinator 0:bb348c97df44 582 #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
lypinator 0:bb348c97df44 583 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
lypinator 0:bb348c97df44 584
lypinator 0:bb348c97df44 585 #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
lypinator 0:bb348c97df44 586 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
lypinator 0:bb348c97df44 587
lypinator 0:bb348c97df44 588 #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
lypinator 0:bb348c97df44 589 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
lypinator 0:bb348c97df44 590
lypinator 0:bb348c97df44 591 #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
lypinator 0:bb348c97df44 592 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
lypinator 0:bb348c97df44 593
lypinator 0:bb348c97df44 594 #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
lypinator 0:bb348c97df44 595 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
lypinator 0:bb348c97df44 596
lypinator 0:bb348c97df44 597 #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
lypinator 0:bb348c97df44 598 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
lypinator 0:bb348c97df44 599
lypinator 0:bb348c97df44 600 #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
lypinator 0:bb348c97df44 601 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
lypinator 0:bb348c97df44 602
lypinator 0:bb348c97df44 603 #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
lypinator 0:bb348c97df44 604 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
lypinator 0:bb348c97df44 605
lypinator 0:bb348c97df44 606 #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
lypinator 0:bb348c97df44 607 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
lypinator 0:bb348c97df44 608
lypinator 0:bb348c97df44 609 /*@} end of group CMSIS_MPU */
lypinator 0:bb348c97df44 610 #endif
lypinator 0:bb348c97df44 611
lypinator 0:bb348c97df44 612
lypinator 0:bb348c97df44 613 /**
lypinator 0:bb348c97df44 614 \ingroup CMSIS_core_register
lypinator 0:bb348c97df44 615 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
lypinator 0:bb348c97df44 616 \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
lypinator 0:bb348c97df44 617 Therefore they are not covered by the SC000 header file.
lypinator 0:bb348c97df44 618 @{
lypinator 0:bb348c97df44 619 */
lypinator 0:bb348c97df44 620 /*@} end of group CMSIS_CoreDebug */
lypinator 0:bb348c97df44 621
lypinator 0:bb348c97df44 622
lypinator 0:bb348c97df44 623 /**
lypinator 0:bb348c97df44 624 \ingroup CMSIS_core_register
lypinator 0:bb348c97df44 625 \defgroup CMSIS_core_bitfield Core register bit field macros
lypinator 0:bb348c97df44 626 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
lypinator 0:bb348c97df44 627 @{
lypinator 0:bb348c97df44 628 */
lypinator 0:bb348c97df44 629
lypinator 0:bb348c97df44 630 /**
lypinator 0:bb348c97df44 631 \brief Mask and shift a bit field value for use in a register bit range.
lypinator 0:bb348c97df44 632 \param[in] field Name of the register bit field.
lypinator 0:bb348c97df44 633 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
lypinator 0:bb348c97df44 634 \return Masked and shifted value.
lypinator 0:bb348c97df44 635 */
lypinator 0:bb348c97df44 636 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
lypinator 0:bb348c97df44 637
lypinator 0:bb348c97df44 638 /**
lypinator 0:bb348c97df44 639 \brief Mask and shift a register value to extract a bit filed value.
lypinator 0:bb348c97df44 640 \param[in] field Name of the register bit field.
lypinator 0:bb348c97df44 641 \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
lypinator 0:bb348c97df44 642 \return Masked and shifted bit field value.
lypinator 0:bb348c97df44 643 */
lypinator 0:bb348c97df44 644 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
lypinator 0:bb348c97df44 645
lypinator 0:bb348c97df44 646 /*@} end of group CMSIS_core_bitfield */
lypinator 0:bb348c97df44 647
lypinator 0:bb348c97df44 648
lypinator 0:bb348c97df44 649 /**
lypinator 0:bb348c97df44 650 \ingroup CMSIS_core_register
lypinator 0:bb348c97df44 651 \defgroup CMSIS_core_base Core Definitions
lypinator 0:bb348c97df44 652 \brief Definitions for base addresses, unions, and structures.
lypinator 0:bb348c97df44 653 @{
lypinator 0:bb348c97df44 654 */
lypinator 0:bb348c97df44 655
lypinator 0:bb348c97df44 656 /* Memory mapping of Core Hardware */
lypinator 0:bb348c97df44 657 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
lypinator 0:bb348c97df44 658 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
lypinator 0:bb348c97df44 659 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
lypinator 0:bb348c97df44 660 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
lypinator 0:bb348c97df44 661
lypinator 0:bb348c97df44 662 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
lypinator 0:bb348c97df44 663 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
lypinator 0:bb348c97df44 664 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
lypinator 0:bb348c97df44 665 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
lypinator 0:bb348c97df44 666
lypinator 0:bb348c97df44 667 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
lypinator 0:bb348c97df44 668 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
lypinator 0:bb348c97df44 669 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
lypinator 0:bb348c97df44 670 #endif
lypinator 0:bb348c97df44 671
lypinator 0:bb348c97df44 672 /*@} */
lypinator 0:bb348c97df44 673
lypinator 0:bb348c97df44 674
lypinator 0:bb348c97df44 675
lypinator 0:bb348c97df44 676 /*******************************************************************************
lypinator 0:bb348c97df44 677 * Hardware Abstraction Layer
lypinator 0:bb348c97df44 678 Core Function Interface contains:
lypinator 0:bb348c97df44 679 - Core NVIC Functions
lypinator 0:bb348c97df44 680 - Core SysTick Functions
lypinator 0:bb348c97df44 681 - Core Register Access Functions
lypinator 0:bb348c97df44 682 ******************************************************************************/
lypinator 0:bb348c97df44 683 /**
lypinator 0:bb348c97df44 684 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
lypinator 0:bb348c97df44 685 */
lypinator 0:bb348c97df44 686
lypinator 0:bb348c97df44 687
lypinator 0:bb348c97df44 688
lypinator 0:bb348c97df44 689 /* ########################## NVIC functions #################################### */
lypinator 0:bb348c97df44 690 /**
lypinator 0:bb348c97df44 691 \ingroup CMSIS_Core_FunctionInterface
lypinator 0:bb348c97df44 692 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
lypinator 0:bb348c97df44 693 \brief Functions that manage interrupts and exceptions via the NVIC.
lypinator 0:bb348c97df44 694 @{
lypinator 0:bb348c97df44 695 */
lypinator 0:bb348c97df44 696
lypinator 0:bb348c97df44 697 #ifdef CMSIS_NVIC_VIRTUAL
lypinator 0:bb348c97df44 698 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
lypinator 0:bb348c97df44 699 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
lypinator 0:bb348c97df44 700 #endif
lypinator 0:bb348c97df44 701 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
lypinator 0:bb348c97df44 702 #else
lypinator 0:bb348c97df44 703 /*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */
lypinator 0:bb348c97df44 704 /*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */
lypinator 0:bb348c97df44 705 #define NVIC_EnableIRQ __NVIC_EnableIRQ
lypinator 0:bb348c97df44 706 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
lypinator 0:bb348c97df44 707 #define NVIC_DisableIRQ __NVIC_DisableIRQ
lypinator 0:bb348c97df44 708 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
lypinator 0:bb348c97df44 709 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
lypinator 0:bb348c97df44 710 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
lypinator 0:bb348c97df44 711 /*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */
lypinator 0:bb348c97df44 712 #define NVIC_SetPriority __NVIC_SetPriority
lypinator 0:bb348c97df44 713 #define NVIC_GetPriority __NVIC_GetPriority
lypinator 0:bb348c97df44 714 #define NVIC_SystemReset __NVIC_SystemReset
lypinator 0:bb348c97df44 715 #endif /* CMSIS_NVIC_VIRTUAL */
lypinator 0:bb348c97df44 716
lypinator 0:bb348c97df44 717 #ifdef CMSIS_VECTAB_VIRTUAL
lypinator 0:bb348c97df44 718 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
lypinator 0:bb348c97df44 719 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
lypinator 0:bb348c97df44 720 #endif
lypinator 0:bb348c97df44 721 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
lypinator 0:bb348c97df44 722 #else
lypinator 0:bb348c97df44 723 #define NVIC_SetVector __NVIC_SetVector
lypinator 0:bb348c97df44 724 #define NVIC_GetVector __NVIC_GetVector
lypinator 0:bb348c97df44 725 #endif /* (CMSIS_VECTAB_VIRTUAL) */
lypinator 0:bb348c97df44 726
lypinator 0:bb348c97df44 727 #define NVIC_USER_IRQ_OFFSET 16
lypinator 0:bb348c97df44 728
lypinator 0:bb348c97df44 729
lypinator 0:bb348c97df44 730 /* Interrupt Priorities are WORD accessible only under Armv6-M */
lypinator 0:bb348c97df44 731 /* The following MACROS handle generation of the register offset and byte masks */
lypinator 0:bb348c97df44 732 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
lypinator 0:bb348c97df44 733 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
lypinator 0:bb348c97df44 734 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
lypinator 0:bb348c97df44 735
lypinator 0:bb348c97df44 736
lypinator 0:bb348c97df44 737 /**
lypinator 0:bb348c97df44 738 \brief Enable Interrupt
lypinator 0:bb348c97df44 739 \details Enables a device specific interrupt in the NVIC interrupt controller.
lypinator 0:bb348c97df44 740 \param [in] IRQn Device specific interrupt number.
lypinator 0:bb348c97df44 741 \note IRQn must not be negative.
lypinator 0:bb348c97df44 742 */
lypinator 0:bb348c97df44 743 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
lypinator 0:bb348c97df44 744 {
lypinator 0:bb348c97df44 745 if ((int32_t)(IRQn) >= 0)
lypinator 0:bb348c97df44 746 {
lypinator 0:bb348c97df44 747 NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
lypinator 0:bb348c97df44 748 }
lypinator 0:bb348c97df44 749 }
lypinator 0:bb348c97df44 750
lypinator 0:bb348c97df44 751
lypinator 0:bb348c97df44 752 /**
lypinator 0:bb348c97df44 753 \brief Get Interrupt Enable status
lypinator 0:bb348c97df44 754 \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
lypinator 0:bb348c97df44 755 \param [in] IRQn Device specific interrupt number.
lypinator 0:bb348c97df44 756 \return 0 Interrupt is not enabled.
lypinator 0:bb348c97df44 757 \return 1 Interrupt is enabled.
lypinator 0:bb348c97df44 758 \note IRQn must not be negative.
lypinator 0:bb348c97df44 759 */
lypinator 0:bb348c97df44 760 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
lypinator 0:bb348c97df44 761 {
lypinator 0:bb348c97df44 762 if ((int32_t)(IRQn) >= 0)
lypinator 0:bb348c97df44 763 {
lypinator 0:bb348c97df44 764 return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
lypinator 0:bb348c97df44 765 }
lypinator 0:bb348c97df44 766 else
lypinator 0:bb348c97df44 767 {
lypinator 0:bb348c97df44 768 return(0U);
lypinator 0:bb348c97df44 769 }
lypinator 0:bb348c97df44 770 }
lypinator 0:bb348c97df44 771
lypinator 0:bb348c97df44 772
lypinator 0:bb348c97df44 773 /**
lypinator 0:bb348c97df44 774 \brief Disable Interrupt
lypinator 0:bb348c97df44 775 \details Disables a device specific interrupt in the NVIC interrupt controller.
lypinator 0:bb348c97df44 776 \param [in] IRQn Device specific interrupt number.
lypinator 0:bb348c97df44 777 \note IRQn must not be negative.
lypinator 0:bb348c97df44 778 */
lypinator 0:bb348c97df44 779 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
lypinator 0:bb348c97df44 780 {
lypinator 0:bb348c97df44 781 if ((int32_t)(IRQn) >= 0)
lypinator 0:bb348c97df44 782 {
lypinator 0:bb348c97df44 783 NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
lypinator 0:bb348c97df44 784 __DSB();
lypinator 0:bb348c97df44 785 __ISB();
lypinator 0:bb348c97df44 786 }
lypinator 0:bb348c97df44 787 }
lypinator 0:bb348c97df44 788
lypinator 0:bb348c97df44 789
lypinator 0:bb348c97df44 790 /**
lypinator 0:bb348c97df44 791 \brief Get Pending Interrupt
lypinator 0:bb348c97df44 792 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
lypinator 0:bb348c97df44 793 \param [in] IRQn Device specific interrupt number.
lypinator 0:bb348c97df44 794 \return 0 Interrupt status is not pending.
lypinator 0:bb348c97df44 795 \return 1 Interrupt status is pending.
lypinator 0:bb348c97df44 796 \note IRQn must not be negative.
lypinator 0:bb348c97df44 797 */
lypinator 0:bb348c97df44 798 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
lypinator 0:bb348c97df44 799 {
lypinator 0:bb348c97df44 800 if ((int32_t)(IRQn) >= 0)
lypinator 0:bb348c97df44 801 {
lypinator 0:bb348c97df44 802 return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
lypinator 0:bb348c97df44 803 }
lypinator 0:bb348c97df44 804 else
lypinator 0:bb348c97df44 805 {
lypinator 0:bb348c97df44 806 return(0U);
lypinator 0:bb348c97df44 807 }
lypinator 0:bb348c97df44 808 }
lypinator 0:bb348c97df44 809
lypinator 0:bb348c97df44 810
lypinator 0:bb348c97df44 811 /**
lypinator 0:bb348c97df44 812 \brief Set Pending Interrupt
lypinator 0:bb348c97df44 813 \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
lypinator 0:bb348c97df44 814 \param [in] IRQn Device specific interrupt number.
lypinator 0:bb348c97df44 815 \note IRQn must not be negative.
lypinator 0:bb348c97df44 816 */
lypinator 0:bb348c97df44 817 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
lypinator 0:bb348c97df44 818 {
lypinator 0:bb348c97df44 819 if ((int32_t)(IRQn) >= 0)
lypinator 0:bb348c97df44 820 {
lypinator 0:bb348c97df44 821 NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
lypinator 0:bb348c97df44 822 }
lypinator 0:bb348c97df44 823 }
lypinator 0:bb348c97df44 824
lypinator 0:bb348c97df44 825
lypinator 0:bb348c97df44 826 /**
lypinator 0:bb348c97df44 827 \brief Clear Pending Interrupt
lypinator 0:bb348c97df44 828 \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
lypinator 0:bb348c97df44 829 \param [in] IRQn Device specific interrupt number.
lypinator 0:bb348c97df44 830 \note IRQn must not be negative.
lypinator 0:bb348c97df44 831 */
lypinator 0:bb348c97df44 832 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
lypinator 0:bb348c97df44 833 {
lypinator 0:bb348c97df44 834 if ((int32_t)(IRQn) >= 0)
lypinator 0:bb348c97df44 835 {
lypinator 0:bb348c97df44 836 NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
lypinator 0:bb348c97df44 837 }
lypinator 0:bb348c97df44 838 }
lypinator 0:bb348c97df44 839
lypinator 0:bb348c97df44 840
lypinator 0:bb348c97df44 841 /**
lypinator 0:bb348c97df44 842 \brief Set Interrupt Priority
lypinator 0:bb348c97df44 843 \details Sets the priority of a device specific interrupt or a processor exception.
lypinator 0:bb348c97df44 844 The interrupt number can be positive to specify a device specific interrupt,
lypinator 0:bb348c97df44 845 or negative to specify a processor exception.
lypinator 0:bb348c97df44 846 \param [in] IRQn Interrupt number.
lypinator 0:bb348c97df44 847 \param [in] priority Priority to set.
lypinator 0:bb348c97df44 848 \note The priority cannot be set for every processor exception.
lypinator 0:bb348c97df44 849 */
lypinator 0:bb348c97df44 850 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
lypinator 0:bb348c97df44 851 {
lypinator 0:bb348c97df44 852 if ((int32_t)(IRQn) >= 0)
lypinator 0:bb348c97df44 853 {
lypinator 0:bb348c97df44 854 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
lypinator 0:bb348c97df44 855 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
lypinator 0:bb348c97df44 856 }
lypinator 0:bb348c97df44 857 else
lypinator 0:bb348c97df44 858 {
lypinator 0:bb348c97df44 859 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
lypinator 0:bb348c97df44 860 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
lypinator 0:bb348c97df44 861 }
lypinator 0:bb348c97df44 862 }
lypinator 0:bb348c97df44 863
lypinator 0:bb348c97df44 864
lypinator 0:bb348c97df44 865 /**
lypinator 0:bb348c97df44 866 \brief Get Interrupt Priority
lypinator 0:bb348c97df44 867 \details Reads the priority of a device specific interrupt or a processor exception.
lypinator 0:bb348c97df44 868 The interrupt number can be positive to specify a device specific interrupt,
lypinator 0:bb348c97df44 869 or negative to specify a processor exception.
lypinator 0:bb348c97df44 870 \param [in] IRQn Interrupt number.
lypinator 0:bb348c97df44 871 \return Interrupt Priority.
lypinator 0:bb348c97df44 872 Value is aligned automatically to the implemented priority bits of the microcontroller.
lypinator 0:bb348c97df44 873 */
lypinator 0:bb348c97df44 874 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
lypinator 0:bb348c97df44 875 {
lypinator 0:bb348c97df44 876
lypinator 0:bb348c97df44 877 if ((int32_t)(IRQn) >= 0)
lypinator 0:bb348c97df44 878 {
lypinator 0:bb348c97df44 879 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
lypinator 0:bb348c97df44 880 }
lypinator 0:bb348c97df44 881 else
lypinator 0:bb348c97df44 882 {
lypinator 0:bb348c97df44 883 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
lypinator 0:bb348c97df44 884 }
lypinator 0:bb348c97df44 885 }
lypinator 0:bb348c97df44 886
lypinator 0:bb348c97df44 887
lypinator 0:bb348c97df44 888 /**
lypinator 0:bb348c97df44 889 \brief Set Interrupt Vector
lypinator 0:bb348c97df44 890 \details Sets an interrupt vector in SRAM based interrupt vector table.
lypinator 0:bb348c97df44 891 The interrupt number can be positive to specify a device specific interrupt,
lypinator 0:bb348c97df44 892 or negative to specify a processor exception.
lypinator 0:bb348c97df44 893 VTOR must been relocated to SRAM before.
lypinator 0:bb348c97df44 894 \param [in] IRQn Interrupt number
lypinator 0:bb348c97df44 895 \param [in] vector Address of interrupt handler function
lypinator 0:bb348c97df44 896 */
lypinator 0:bb348c97df44 897 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
lypinator 0:bb348c97df44 898 {
lypinator 0:bb348c97df44 899 uint32_t *vectors = (uint32_t *)SCB->VTOR;
lypinator 0:bb348c97df44 900 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
lypinator 0:bb348c97df44 901 }
lypinator 0:bb348c97df44 902
lypinator 0:bb348c97df44 903
lypinator 0:bb348c97df44 904 /**
lypinator 0:bb348c97df44 905 \brief Get Interrupt Vector
lypinator 0:bb348c97df44 906 \details Reads an interrupt vector from interrupt vector table.
lypinator 0:bb348c97df44 907 The interrupt number can be positive to specify a device specific interrupt,
lypinator 0:bb348c97df44 908 or negative to specify a processor exception.
lypinator 0:bb348c97df44 909 \param [in] IRQn Interrupt number.
lypinator 0:bb348c97df44 910 \return Address of interrupt handler function
lypinator 0:bb348c97df44 911 */
lypinator 0:bb348c97df44 912 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
lypinator 0:bb348c97df44 913 {
lypinator 0:bb348c97df44 914 uint32_t *vectors = (uint32_t *)SCB->VTOR;
lypinator 0:bb348c97df44 915 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
lypinator 0:bb348c97df44 916 }
lypinator 0:bb348c97df44 917
lypinator 0:bb348c97df44 918
lypinator 0:bb348c97df44 919 /**
lypinator 0:bb348c97df44 920 \brief System Reset
lypinator 0:bb348c97df44 921 \details Initiates a system reset request to reset the MCU.
lypinator 0:bb348c97df44 922 */
lypinator 0:bb348c97df44 923 __STATIC_INLINE void __NVIC_SystemReset(void)
lypinator 0:bb348c97df44 924 {
lypinator 0:bb348c97df44 925 __DSB(); /* Ensure all outstanding memory accesses included
lypinator 0:bb348c97df44 926 buffered write are completed before reset */
lypinator 0:bb348c97df44 927 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
lypinator 0:bb348c97df44 928 SCB_AIRCR_SYSRESETREQ_Msk);
lypinator 0:bb348c97df44 929 __DSB(); /* Ensure completion of memory access */
lypinator 0:bb348c97df44 930
lypinator 0:bb348c97df44 931 for(;;) /* wait until reset */
lypinator 0:bb348c97df44 932 {
lypinator 0:bb348c97df44 933 __NOP();
lypinator 0:bb348c97df44 934 }
lypinator 0:bb348c97df44 935 }
lypinator 0:bb348c97df44 936
lypinator 0:bb348c97df44 937 /*@} end of CMSIS_Core_NVICFunctions */
lypinator 0:bb348c97df44 938
lypinator 0:bb348c97df44 939
lypinator 0:bb348c97df44 940 /* ########################## FPU functions #################################### */
lypinator 0:bb348c97df44 941 /**
lypinator 0:bb348c97df44 942 \ingroup CMSIS_Core_FunctionInterface
lypinator 0:bb348c97df44 943 \defgroup CMSIS_Core_FpuFunctions FPU Functions
lypinator 0:bb348c97df44 944 \brief Function that provides FPU type.
lypinator 0:bb348c97df44 945 @{
lypinator 0:bb348c97df44 946 */
lypinator 0:bb348c97df44 947
lypinator 0:bb348c97df44 948 /**
lypinator 0:bb348c97df44 949 \brief get FPU type
lypinator 0:bb348c97df44 950 \details returns the FPU type
lypinator 0:bb348c97df44 951 \returns
lypinator 0:bb348c97df44 952 - \b 0: No FPU
lypinator 0:bb348c97df44 953 - \b 1: Single precision FPU
lypinator 0:bb348c97df44 954 - \b 2: Double + Single precision FPU
lypinator 0:bb348c97df44 955 */
lypinator 0:bb348c97df44 956 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
lypinator 0:bb348c97df44 957 {
lypinator 0:bb348c97df44 958 return 0U; /* No FPU */
lypinator 0:bb348c97df44 959 }
lypinator 0:bb348c97df44 960
lypinator 0:bb348c97df44 961
lypinator 0:bb348c97df44 962 /*@} end of CMSIS_Core_FpuFunctions */
lypinator 0:bb348c97df44 963
lypinator 0:bb348c97df44 964
lypinator 0:bb348c97df44 965
lypinator 0:bb348c97df44 966 /* ################################## SysTick function ############################################ */
lypinator 0:bb348c97df44 967 /**
lypinator 0:bb348c97df44 968 \ingroup CMSIS_Core_FunctionInterface
lypinator 0:bb348c97df44 969 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
lypinator 0:bb348c97df44 970 \brief Functions that configure the System.
lypinator 0:bb348c97df44 971 @{
lypinator 0:bb348c97df44 972 */
lypinator 0:bb348c97df44 973
lypinator 0:bb348c97df44 974 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
lypinator 0:bb348c97df44 975
lypinator 0:bb348c97df44 976 /**
lypinator 0:bb348c97df44 977 \brief System Tick Configuration
lypinator 0:bb348c97df44 978 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
lypinator 0:bb348c97df44 979 Counter is in free running mode to generate periodic interrupts.
lypinator 0:bb348c97df44 980 \param [in] ticks Number of ticks between two interrupts.
lypinator 0:bb348c97df44 981 \return 0 Function succeeded.
lypinator 0:bb348c97df44 982 \return 1 Function failed.
lypinator 0:bb348c97df44 983 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
lypinator 0:bb348c97df44 984 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
lypinator 0:bb348c97df44 985 must contain a vendor-specific implementation of this function.
lypinator 0:bb348c97df44 986 */
lypinator 0:bb348c97df44 987 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
lypinator 0:bb348c97df44 988 {
lypinator 0:bb348c97df44 989 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
lypinator 0:bb348c97df44 990 {
lypinator 0:bb348c97df44 991 return (1UL); /* Reload value impossible */
lypinator 0:bb348c97df44 992 }
lypinator 0:bb348c97df44 993
lypinator 0:bb348c97df44 994 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
lypinator 0:bb348c97df44 995 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
lypinator 0:bb348c97df44 996 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
lypinator 0:bb348c97df44 997 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
lypinator 0:bb348c97df44 998 SysTick_CTRL_TICKINT_Msk |
lypinator 0:bb348c97df44 999 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
lypinator 0:bb348c97df44 1000 return (0UL); /* Function successful */
lypinator 0:bb348c97df44 1001 }
lypinator 0:bb348c97df44 1002
lypinator 0:bb348c97df44 1003 #endif
lypinator 0:bb348c97df44 1004
lypinator 0:bb348c97df44 1005 /*@} end of CMSIS_Core_SysTickFunctions */
lypinator 0:bb348c97df44 1006
lypinator 0:bb348c97df44 1007
lypinator 0:bb348c97df44 1008
lypinator 0:bb348c97df44 1009
lypinator 0:bb348c97df44 1010 #ifdef __cplusplus
lypinator 0:bb348c97df44 1011 }
lypinator 0:bb348c97df44 1012 #endif
lypinator 0:bb348c97df44 1013
lypinator 0:bb348c97df44 1014 #endif /* __CORE_SC000_H_DEPENDANT */
lypinator 0:bb348c97df44 1015
lypinator 0:bb348c97df44 1016 #endif /* __CMSIS_GENERIC */